mirror of
https://github.com/revyos/th1520-vendor-uboot.git
synced 2026-06-21 09:02:25 +02:00
Revert "fix(c9xx): don't flush dcache when invalidating"
This reverts commit adec30ace4.
This commit is contained in:
committed by
Han Gao/Revy/Rabenda
parent
74eca2553e
commit
4529d8d50f
@@ -247,9 +247,10 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
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}
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} while (!(stat & SDHCI_INT_DATA_END));
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#ifdef CONFIG_TARGET_LIGHT_C910
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extern void invalid_dcache_range(unsigned long start, unsigned long end);
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/*After read ,invalid dcache range again to avoid cache filled during read tranfer*/
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if(data->flags == MMC_DATA_READ){
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invalidate_dcache_range(host->start_addr,host->start_addr+ROUND(data->blocks*data->blocksize, ARCH_DMA_MINALIGN));
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invalid_dcache_range(host->start_addr,host->start_addr+ROUND(data->blocks*data->blocksize, ARCH_DMA_MINALIGN));
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}
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#endif
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return 0;
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@@ -906,7 +906,8 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
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dep->resource_index = 0;
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dwc->setup_packet_pending = false;
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#ifdef CONFIG_TARGET_LIGHT_C910
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invalidate_dcache_range((unsigned long)dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
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extern void invalid_dcache_range(unsigned long start, unsigned long end);
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invalid_dcache_range((unsigned long)dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
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#endif
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switch (dwc->ep0state) {
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