Revert "fix(c9xx): don't flush dcache when invalidating"

This reverts commit adec30ace4.
This commit is contained in:
Han Gao
2024-01-31 13:37:42 +08:00
committed by Han Gao/Revy/Rabenda
parent 74eca2553e
commit 4529d8d50f
5 changed files with 17 additions and 3 deletions

View File

@@ -247,9 +247,10 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
}
} while (!(stat & SDHCI_INT_DATA_END));
#ifdef CONFIG_TARGET_LIGHT_C910
extern void invalid_dcache_range(unsigned long start, unsigned long end);
/*After read ,invalid dcache range again to avoid cache filled during read tranfer*/
if(data->flags == MMC_DATA_READ){
invalidate_dcache_range(host->start_addr,host->start_addr+ROUND(data->blocks*data->blocksize, ARCH_DMA_MINALIGN));
invalid_dcache_range(host->start_addr,host->start_addr+ROUND(data->blocks*data->blocksize, ARCH_DMA_MINALIGN));
}
#endif
return 0;

View File

@@ -906,7 +906,8 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
dep->resource_index = 0;
dwc->setup_packet_pending = false;
#ifdef CONFIG_TARGET_LIGHT_C910
invalidate_dcache_range((unsigned long)dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
extern void invalid_dcache_range(unsigned long start, unsigned long end);
invalid_dcache_range((unsigned long)dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
#endif
switch (dwc->ep0state) {