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22 lines
459 B
C
22 lines
459 B
C
/*
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* Copyright (C) 2017-2020 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_CACHE_H
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#define __ASM_CACHE_H
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#include <asm/system.h>
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/*
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* We use that value for aligning DMA buffers unless the board config has specified
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* an alternate cache line size.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 64
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#endif
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#endif /* __ASM_CACHE_H */
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