mirror of
https://github.com/revyos/th1520-vendor-uboot.git
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96 lines
3.1 KiB
C
96 lines
3.1 KiB
C
/*
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* Copyright (C) 2017-2020 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_UART_H__
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#define __ASM_ARCH_UART_H__
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#include <linux/types.h>
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#include "datatype.h"
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#include "uart/uart.h"
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/* UART registers addr definition */
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#define UART_RBR 0x00 /* Receive Buffer Register (32 bits, R) */
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#define UART_THR 0x00 /* Transmit Holding Register (32 bits, W) */
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#define UART_DLL 0x00 /* Divisor Latch(Low) (32 bits, R/W) */
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#define UART_IER 0x01 /* Interrupt Enable Register (32 bits, R/W) */
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#define UART_DLH 0x01 /* Divisor Latch(High) (32 bits, R/W) */
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#define UART_IIR 0x02 /* Interrupt Identity Register (32 bits, R) */
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#define UART_FCR 0x02 /* fifo Countrol Register (32 bits, W) */
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#define UART_LCR 0x03 /* Line Control Register (32 bits, R/W) */
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#define UART_MCR 0x04 /* Modem Control Register (32 bits, W) */
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#define UART_LSR 0x05 /* Line Status Register (32 bits, R) */
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#define UART_MSR 0x06 /* Modem Status Register (32 bits, R/W) */
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#define UART_USR 0x1f /* UART Status Register (32 bits, R/W) */
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#define UART_BUSY_TIMEOUT 1000000
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#define UART_RECEIVE_TIMEOUT 1000
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#define UART_TRANSMIT_TIMEOUT 1000
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/* UART register bit definitions */
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#define USR_UART_BUSY 0x01
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#define LSR_DATA_READY 0x01
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#define LSR_THR_EMPTY 0x20
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#define IER_RDA_INT_ENABLE 0x01
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#define IER_THRE_INT_ENABLE 0x02
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#define IIR_NO_ISQ_PEND 0x01
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#define LCR_SET_DLAB 0x80 /* enable r/w DLR to set the baud rate */
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#define LCR_PARITY_ENABLE 0x08 /* parity enabled */
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#define LCR_PARITY_EVEN 0x10 /* Even parity enabled */
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#define LCR_PARITY_ODD 0xef /* Odd parity enabled */
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#define LCR_WORD_SIZE_5 0xfc /* the data length is 5 bits */
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#define LCR_WORD_SIZE_6 0x01 /* the data length is 6 bits */
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#define LCR_WORD_SIZE_7 0x02 /* the data length is 7 bits */
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#define LCR_WORD_SIZE_8 0x03 /* the data length is 8 bits */
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#define LCR_STOP_BIT1 0xfb /* 1 stop bit */
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#define LCR_STOP_BIT2 0x04 /* 1.5 stop bit */
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#define LSR_PFE 0x80
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#define LSR_TEMT 0x40
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#define LSR_THRE 0x40
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#define LSR_BI 0x10
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#define LSR_FE 0x08
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#define LSR_PE 0x04
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#define LSR_OE 0x02
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#define LSR_DR 0x01
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#define LSR_TRANS_EMPTY 0x20
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/*config the uart */
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typedef struct UART_Info_t {
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volatile u32* addr;
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} CKStruct_UartInfo, *PCKStruct_UartInfo;
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/* Struct of Uart REG*/
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typedef struct UART_REG {
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union {
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volatile u32 uart_RBR;
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volatile u32 uart_THR;
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volatile u32 uart_DLL;
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};
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union {
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volatile u32 uart_IER;
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volatile u32 uart_DLH;
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};
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union {
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volatile u32 uart_IIR;
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volatile u32 uart_FCR;
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};
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volatile u32 uart_LCR;
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volatile u32 uart_MCR;
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volatile u32 uart_LSR;
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volatile u32 uart_MSR;
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volatile u32 uart_RSV[24];
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volatile u32 uart_USR;
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} UART_REG;
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#endif /* __ASM_ARCH_UART_H__ */
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