mirror of
https://github.com/revyos/th1520-vendor-uboot.git
synced 2026-09-10 03:16:10 +02:00
288 lines
8.4 KiB
C
288 lines
8.4 KiB
C
/*
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* Copyright (C) 2018-2020 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/clock.h>
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#include <miiphy.h>
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void gmac_clk_config(u32 interface)
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{
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// release phy by gpio0_0
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*(volatile unsigned int*)(0xbff71000) = 0x1;
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udelay(10000);
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#ifdef CONFIG_IS_ASIC
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if (interface == PHY_INTERFACE_MODE_MII) {
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*(volatile unsigned int *)(0xbe83025c) = 0x0; //MII MODE
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*(volatile unsigned int *)(0xbe83031c) = 0x1; //CLK_OUT pad disable
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*(volatile unsigned int *)(0xbff770c0) = 0x18a;
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} else if (interface == PHY_INTERFACE_MODE_RMII) {
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*(volatile unsigned int *)(0xbe83025c) = 0x4; //RMII MODE
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//RMII, External 100Mbps Mode
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*(volatile unsigned int *)(0xbe83031c) = 0x0; //CLK_OUT pad enable
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//50MHz
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*(volatile unsigned int *)(0xbff770cc) = 0x14;
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*(volatile unsigned int *)(0xbff770cc) = 0x80000014;
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//25MHz
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*(volatile unsigned int *)(0xbff770d4) = 0x2;
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*(volatile unsigned int *)(0xbff770d4) = 0x80000002;
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//enable rmii clocks
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*(volatile unsigned int *)(0xbff770c0) = 0xd68;
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} else if (interface == PHY_INTERFACE_MODE_RGMII) {
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//RGMII mode
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*(volatile unsigned int*)(0xbe8302cc) = 0x20202020;
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*(volatile unsigned int*)(0xbe8302cf) = 0x07072020;
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*(volatile unsigned int*)(0xbe8302d4) = 0x07070707;
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//PHY Mode Sel
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*(volatile unsigned int*)(0xbe83025c) = 0x1; //0:MII/GMII, 1:RGMII, 4:RMII
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//Enable TX_CLK PAD
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*(volatile unsigned int*)(0xbe83031c) = 0x0; //oen
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//enable pll_div, 1000/4=250MHz
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*(volatile unsigned int*)(0xbff770cc) = 0x4;
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*(volatile unsigned int*)(0xbff770cc) = 0x4;
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*(volatile unsigned int*)(0xbff770cc) = 0x80000004;
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*(volatile unsigned int*)(0xbff770cc) = 0x80000004;
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#if 0
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*(volatile unsigned int*)(0xbff770d0) = 0x2;
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*(volatile unsigned int*)(0xbff770d0) = 0x2;
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*(volatile unsigned int*)(0xbff770d0) = 0x80000002;
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*(volatile unsigned int*)(0xbff770d0) = 0x80000002;
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#else
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*(volatile unsigned int*)(0xbff770d0) = 0xa;
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*(volatile unsigned int*)(0xbff770d0) = 0xa;
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*(volatile unsigned int*)(0xbff770d0) = 0x8000000a;
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*(volatile unsigned int*)(0xbff770d0) = 0x8000000a;
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#endif
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*(volatile unsigned int*)(0xbff770d8) = 0x28;
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*(volatile unsigned int*)(0xbff770d8) = 0x28;
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*(volatile unsigned int*)(0xbff770d8) = 0x80000028;
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*(volatile unsigned int*)(0xbff770d8) = 0x80000028;
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*(volatile unsigned int*)(0xbff770c4) = 0x1f;//rx
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*(volatile unsigned int*)(0xbff770c8) = 0x1f;//tx
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*(volatile unsigned int*)(0xbff770c0) = 0x13dc;
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}
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#endif
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}
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static void usb_clk_config(void)
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{
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// # Setup USB_CLK_CFG(0xFFF770F0)
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// set $USB_CLK_CFG=*0xFFF770F0
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unsigned int usb_clk_cfg = *(volatile unsigned int *)0xbff770f0;
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// # Set ahb_clk_usb_en=1 to enable USB AHB clock
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// set $USB_CLK_CFG |= (1<<17)
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usb_clk_cfg |= (1 << 17);
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// # Set cfg_apb_clk_usb_phy_en=1 to enable APB clock
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// set $USB_CLK_CFG |= (1<<16)
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usb_clk_cfg|= (1 << 16);
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// # Set usb_phy_ref_clk_div_en=1 to enable PHY ref clock
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// set $USB_CLK_CFG |= (1<<7)
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usb_clk_cfg |= (1 << 7);
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// # Set usb_suspend_clk_div_en=1 to enable suspend clock
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// set $USB_CLK_CFG |= (1<<15)
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usb_clk_cfg |= (1 << 15);
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// set *0xFFF770F0=$USB_CLK_CFG
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*(volatile unsigned int *)0xbff770f0 = usb_clk_cfg;
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// # delay 10us at least
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// shell sleep 0.1
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udelay(10);
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// # echo USB_CLK_CFG(0xFFF770F0, should be 0x39899) is:\n
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// # x/wx 0xFFF770F0
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// # Setup PHY internal ref clock (USB_CLK_CFG)
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// set *0xFE83009C=0x1
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*(volatile unsigned int *)0xbe83009c = 0x1;
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// # delay 10us at least
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// shell sleep 0.1
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udelay(10);
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// # echo USB_CLK_CFG(0xFE83009C) is:\n
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// # x/wx 0xFE83009C
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// # Release PHY (USB_PHY_USW_RST_CFG)
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// set *0xFFF78048=0x1
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*(volatile unsigned int *)0xbff78048 = 0x1;
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// # delay 10us at least
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// shell sleep 0.1
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udelay(10);
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// # echo USB_CLK_CFG(0xFFF78048) is:\n
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// # x/wx 0xFFF78048
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}
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// #################################
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// # Define DelayTick function
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// #################################
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// define DelayTicks
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// set $total = $arg0
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// set $i = 0
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// set $temp = 0
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// while ($i < $total)
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// # Read SRAM which always can be read
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// set $temp = *(0xFE400000 + $i * 4)
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// set $i = $i + 1
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// end
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// end
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// static void delay_tick(int ticks)
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// {
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// unsigned int temp = 0;
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// while (ticks--) {
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// temp = *(volatile unsigned int *)0xbe400000;
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// }
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// }
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static void gpu_config(void)
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{
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*(volatile unsigned int *)0xbff77070 &= ~((1 << 21) | (1 << 20));
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udelay(100);
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*(volatile unsigned int *)0xbff7709c = 0x00011212;
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udelay(100);
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*(volatile unsigned int *)0xbff77070 |= (1 << 21) | (1 << 20);
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*(volatile unsigned int *)0xbff780a4=0;
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*(volatile unsigned int *)0xbff78094=0;
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*(volatile unsigned int *)0xbff780c0=0;
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udelay(100);
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*(volatile unsigned int *)0xbff78094=1;
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*(volatile unsigned int *)0xbff780c0=1;
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*(volatile unsigned int *)0xbff780a4=1;
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udelay(1000);
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//# x/wx 0x3fff27028 should get 0x20151217
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printf("GPU ChipDate is:0x%08x\n", *(volatile unsigned int *)0xbff27028);
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printf("GPU Frequency is:%dKHz\n", *(volatile unsigned int *)0xbff7713c);
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}
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static void npu_config(void)
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{
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*(volatile unsigned int *)0xbff78044 = 0xff;
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udelay(100);
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printf("NPU ChipDate is:0x%08x\n", *(volatile unsigned int *)0xbff20028);
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}
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static void dpu_config(void)
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{
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//set dpu_pixclk_div_en
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*(volatile unsigned int *)0xbff77098 |= 0x10811212;
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//enable dpu_aclk and dpu_cclk
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*(volatile unsigned int *)0xbff77070 |= (1 << 23 | 1 << 22);
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//set dpu_pixclk_div_en, dpu_pixclk_div_en, ahb_clk_dpu_en, dpu_aclk_div_en, dpu_cclk_div_en
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*(volatile unsigned int *)0xbff77098 |= 0x11811212;
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//dpu rst
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*(volatile unsigned int *)0xbff78090 |= (1 << 0);
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//dpu crst
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*(volatile unsigned int *)0xbff780a0 |= (1 << 0);
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//dpu arst
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*(volatile unsigned int *)0xbff7809c |= (1 << 0);
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//set DPU_DISPLAY_BUF as GPIO
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*(volatile unsigned int *)0xbe830700 |= (1 << 2);
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//Enable LCD 5V output, it also control by "lcd-power" in dts
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*(volatile unsigned int *)0xbff72000 |= (1 << 2);
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*(volatile unsigned int *)0xbff72004 |= (1 << 2);
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printf("DPU ChipDate is:0x%08x\n", *(volatile unsigned int *)0xbff28028);
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}
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static void vpu_clk_config(void)
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{
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// # enable video clock
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// set *0xFFF77074 |= 0xf
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*(volatile unsigned int *)0xbff77074 |= 0xf;
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// # release video reset
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// set *0xFFF78064 |= (1 << 0)
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*(volatile unsigned int *)0xbff78064 |= (1 << 0);
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}
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// static void pcie_clk_config(void)
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// {
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// // # enable PCIe clock (apb, axi, aux)
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// // set *0xFFF770E0 |= (1 << 9) | (1 << 8) | (1 << 7)
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// *(volatile unsigned int *)0xbff770e0 |= (1 << 9) | (1 << 8) | (1 << 7);
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// }
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static void dmac_clk_config(void)
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{
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// # enable DMAC clock
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// set *0xFFF77094 |= (1 << 11)
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*(volatile unsigned int *)0xbff77094 |= (1 << 11);
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// # enable SCE-dmac clock
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// set *0xFFF77104 |= 0x7
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*(volatile unsigned int *)0xbff77070 |= (1 << 13);
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// # de-assert DMAC reset
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// set *0xFFF78050 |= (1 << 0)
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*(volatile unsigned int *)0xbff78050 |= (1 << 0);
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// # de-assert SCE reset
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// set *0xFFF78054 |= 0x11010
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*(volatile unsigned int *)0xbff780c4 |= 0x11010;
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}
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static void sd_clk_config(void)
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{
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// #################################
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// # Enable SD
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// #################################
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// # set SD1_CWPR/GPIO1-15 to GPIO
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// set *0xFE83033C |= (1 << 22)
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*(volatile unsigned int *)0xbe83033c |= (1 << 22);
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// # set SD1_CWPR/GPIO1-15 to output
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// set *0xFFF72004 |= (1 << 15)
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*(volatile unsigned int *)0xbff72004 |= (1 << 15);
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// # set SD1_CWPR/GPIO1-15 to Low(enable power)
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// set *0xFFF72000 &= ~(1 << 15)
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*(volatile unsigned int *)0xbff72000 &= ~(1 << 15);
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// # enable SD clock
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// set *0xFFF77078 = 0x0c800c80
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*(volatile unsigned int *)0xbff77078 = 0x0c800c80;
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// # de-assert SD reset
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// set *0xFFF78058 |= (1 << 16)
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*(volatile unsigned int *)0xbff78058 |= (1 << 16);
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}
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static void spi_config(void)
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{
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// #################################
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// # Set padmux for SPI CS
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// #################################
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// # SPI0: config CS0/CS1 as GPIO
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// set *0xFE830334 |= (1 << 2) | (1 << 4)
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*(volatile unsigned int *)0xbe830334 |= (1 << 2) | (1 << 4);
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// # SPI1: config CS0/CS1 as GPIO
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// set *0xFE830334 |= (1 << 12) | (1 << 14)
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*(volatile unsigned int *)0xbe830334 |= (1 << 12) | (1 << 14);
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// # SFC: config SFC_CSN as GPIO
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// set *0xFE830330 |= (1 << 22)
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*(volatile unsigned int *)0xbe830330 |= (1 << 22);
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}
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void clock_init(void)
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{
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gmac_clk_config(PHY_INTERFACE_MODE_RGMII);
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usb_clk_config();
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gpu_config();
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npu_config();
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dpu_config();
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vpu_clk_config();
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// pcie_clk_config();
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dmac_clk_config();
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sd_clk_config();
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spi_config();
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}
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