mirror of
https://github.com/revyos/th1520-vendor-uboot.git
synced 2026-06-21 09:02:25 +02:00
adec30ace4
The data cache invalidation function for c9xx CPUs uses `dcache.cipa`
instruction. According to T-Head extension specification[1] section
3.1.5, this instruction also performs a cache clean along with the
invalidation.
On top of being incorrect, this leads to a serious issue on the
designware ethernet driver, where stalled cache may get flushed each
time we handle a new received packet[2]. As a result, received packet
are randomly corrupted with old cached data. This can easily be
reproduced by sending an ARP request to the device during a TFTP
transfer. The last TFTP block is treated as the ARP reply we just sent,
which makes U-Boot hang on the block.
Always use `dcache.ipa` instruction to invalidate dcache. Replace
existing usages of `dcache.ipa` with our implementation.
Note that this fix is slightly intrusive as it changes the cache
invalidation behavior in all drivers. However, I have not noticed any
side-effect during my tests.
[1] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
[2] 918a8c89e0/drivers/net/designware.c (L475)
642 lines
18 KiB
C
642 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright(C) 2021 Alibaba Communications Inc.
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* Author: David Li <liyong.li@alibaba-inc.com>
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*/
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/*
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* PRBS test pattern
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*
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*/
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#include <common.h>
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#include <console.h>
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#include <bootretry.h>
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#include <cli.h>
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#include <command.h>
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#include <console.h>
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#include <hash.h>
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#include <mapmem.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <asm/asm.h>
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#include <asm/csr.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "queue.h"
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//#define DEBUG
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#ifdef DEBUG
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#define CHECK_RESULT
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#endif
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#ifdef CHECK_RESULT
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static bool checked = true;
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#else
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static bool checked = false;
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#endif
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#define FIXED_RANGE 0x100000 // write fixed range for prbs_31 only
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#define BYTE_PER_CACHELINE 64
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#define BIT_PER_BYTE 8
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#define TIMER_FREQ (3*1000*1000)
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#define TIMER_TICK_MS (TIMER_FREQ/1000)
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u64 t_begin;
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u64 t_end;
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extern void flush_dcache_range(unsigned long start, unsigned long end);
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extern void invalidate_dcache_range(unsigned long start, unsigned long end);
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extern unsigned long get_ddr_density(void);
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extern int riscv_get_time(u64 *time);
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struct PRBS_ELE {
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char *name;
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char *init_value;
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unsigned int init_cnt;
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char *expression;
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unsigned int exp_cnt;
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};
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char prbs7_init_value[] = {1,1,1,1,1,0,1};
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char prbs7_exp[] = {7,3};
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struct PRBS_ELE prbs7 = {
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"prbs_7",
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prbs7_init_value,
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7,
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prbs7_exp,
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2
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};
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char prbs15_init_value[] = {1,1,1,1,1,0,1,0,1,1,0,1,1,1,0};
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char prbs15_exp[] = {15,1};
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struct PRBS_ELE prbs15 = {
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"prbs_15",
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prbs15_init_value,
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15,
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prbs15_exp,
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2
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};
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char prbs23_init_value[] = {1,1,1,1,1,0,1,0,1,1,0,1,1,1,0,0,1,0,1,1,1,0,1};
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char prbs23_exp[] = {23,5};
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struct PRBS_ELE prbs23 = {
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"prbs_23",
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prbs23_init_value,
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23,
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prbs23_exp,
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2
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};
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char prbs31_init_value[] = {1,1,1,1,1,0,1,0,1,1,0,1,1,1,0,0,1,0,1,1,1,0,1,0,0,0,1,0,0,1,1};
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char prbs31_exp[] = {31,3};
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struct PRBS_ELE prbs31 = {
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"prbs_31",
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prbs31_init_value,
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31,
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prbs31_exp,
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2
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};
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unsigned int _generate_prbs_pos(unsigned int pos, unsigned int bit_value) {
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unsigned int pat = 0;
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int i;
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for(i=0; i<sizeof(pat)*BIT_PER_BYTE; i++)
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{
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pat |= bit_value << i;
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}
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return pat;
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}
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unsigned int _generate_prbs_neg(unsigned int pos, unsigned int bit_value) {
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unsigned int pat = 0;
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pat = bit_value;
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// reverse bit
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if((bit_value & (1 << pos)) == 0) {
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pat |= (unsigned int)0x1 << pos;
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}
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else {
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pat &= ~(bit_value & (1 << pos));
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}
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return pat;
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}
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unsigned int _generate_prbs_neg_all(unsigned int pos, unsigned int bit_value) {
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unsigned int pat = 0;
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int i;
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for(i=0; i<sizeof(pat)*BIT_PER_BYTE; i++)
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{
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pat |= bit_value << i;
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}
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pat = ~pat;
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return pat;
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}
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#define BYTE_PER_INTERLEAVE 512
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#ifdef CONFIG_DDR_CHBIT_256B
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//#define DDR_PHY0_ONLY
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#define DDR_PHY1_ONLY
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#define MULTIPLY 2
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#else
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#define MULTIPLY 1
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#endif
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int prbs_test(struct PRBS_ELE *prbs, unsigned int *buf, int pos, bool random_dq, bool need_check) {
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unsigned int i,j,k;
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unsigned int pattern;
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unsigned int bit_value;
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char *init_value = prbs->init_value;
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char *exp = prbs->expression;
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unsigned int init_cnt = prbs->init_cnt;
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unsigned int bit_len = (1 << init_cnt) -1;
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unsigned int exp_cnt = prbs->exp_cnt;
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unsigned int *p1;
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unsigned int tmp;
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unsigned int dq_cnt = 32;
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bool fixed_range = false;
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ulong ddr_density = get_ddr_density();
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printf("prbs name: %s\n", prbs->name);
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printf("prbs bit_len: %d\n", bit_len);
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printf("prbs init_cnt: %d\n", init_cnt);
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printf("prbs exp_cnt: %d\n", exp_cnt);
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if (strcmp(prbs->name, "prbs_31") == 0)
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fixed_range = true; // not enough space for prbs_31 incr range mode
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//Queue* queue = NULL;
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Queue* (queue[dq_cnt]);
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for (i = 0; i < dq_cnt; i++) {
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queue[i] = Queue_Init(OnQueueIncreasedEvent);
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if (queue[i] == NULL) {
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printf("ERROR: fail to Queue_Init queue[%d]\n", i);
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return -1;
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}
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}
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// fill queue with init_value
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for (i = 0; i < init_cnt; i++) {
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printf("prbs init_value[%d]: %d\n", init_cnt-i-1, init_value[init_cnt-i-1]);
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for (j = 0; j < dq_cnt; j++) {
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if ((j == pos) || (!random_dq)) {
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if (Queue_AddToHead(queue[j], init_value[init_cnt-i-1]) == -1)
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printf("fail to Queue_AddToHead queue[%d], vect[%d]\n", j, i);
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}
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else {
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//ulong tmp = rand_ul() % 2;
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u64 tmp;
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riscv_get_time(&tmp);
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tmp = tmp % 2;
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if (Queue_AddToHead(queue[j], (tmp==0)?0:1) == -1)
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printf("fail to Queue_AddToHead queue[%d], vect[%d]\n", j, i);
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}
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}
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}
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for (i = 0; i < dq_cnt; i++) {
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printf("prbs queue_value[%d]: [", i);
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for (j = 0; j < init_cnt; j++) {
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char data = Queue_QueryAt(queue[i], j);
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printf(" %d,", data);
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}
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printf("]\n");
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}
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//prbs31 sequence write
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p1 = buf;
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u64 bit_cnt = 0;
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for (i = 0; i < bit_len; i++) {
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bit_cnt++;
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if (fixed_range && ((bit_cnt % FIXED_RANGE) == 0))
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p1 = buf; // reset ptr to beginning
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else if ((bit_cnt % (ddr_density/4/2)) == 0)
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p1 = buf; // reset ptr to beginning
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bit_value = 0;
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for (j = 0; j < dq_cnt; j++) {
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unsigned int sum = 0;
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for (k = 0; k < exp_cnt; k++) {
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char data = Queue_QueryAt(queue[j], exp[k]-1);
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sum += data;
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}
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sum = sum % 2;
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Queue_AddToHead(queue[j], sum);
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bit_value |= Queue_GetFromTail(queue[j]) << j;
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}
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pattern = bit_value;
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//pattern = _generate_prbs_pos(pos, bit_value);
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#ifdef DEBUG
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printf("bit[%d]: val<0x%x>, addr<0x%lx>, write pos pattern: 0x%x\n", bit_len-i-1, bit_value, (ulong)p1, pattern);
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#endif
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*p1++ = pattern;
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// flush cache after write
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if(((ulong)p1 - (ulong)buf) % BYTE_PER_CACHELINE == 0)
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{
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flush_dcache_range((ulong)p1-BYTE_PER_CACHELINE, (ulong)p1-1);
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#ifdef DEBUG
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printf("flush cache start<0x%lx>, end<0x%lx>\n", (ulong)p1-BYTE_PER_CACHELINE, (ulong)p1-1);
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#endif
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}
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#if defined(DDR_PHY0_ONLY) || defined(DDR_PHY1_ONLY)
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if(((ulong)p1 - (ulong)buf) % (BYTE_PER_INTERLEAVE/2) == 0)
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{
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// jump to next PHY1's interleave space
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p1+=BYTE_PER_INTERLEAVE/2/sizeof(pattern);
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}
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#endif
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}
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for (i = 0; i < bit_len; i++) {
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bit_cnt++;
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if (fixed_range && ((bit_cnt % FIXED_RANGE) == 0))
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p1 = buf; // reset ptr to beginning
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else if ((bit_cnt % (ddr_density/4/2)) == 0)
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p1 = buf; // reset ptr to beginning
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bit_value = 0;
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for (j = 0; j < dq_cnt; j++) {
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unsigned int sum = 0;
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for (k = 0; k < exp_cnt; k++) {
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char data = Queue_QueryAt(queue[j], exp[k]-1);
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sum += data;
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}
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sum = sum % 2;
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Queue_AddToHead(queue[j], sum);
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bit_value |= Queue_GetFromTail(queue[j]) << j;
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}
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pattern = _generate_prbs_neg(pos, bit_value);
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#ifdef DEBUG
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printf("bit[%d]: val<0x%x>, addr<0x%lx>, write neg pattern: 0x%x\n", bit_len-i-1, bit_value, (ulong)p1, pattern);
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#endif
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*p1++ = pattern;
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// flush cache after write
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if(((ulong)p1 - (ulong)buf) % BYTE_PER_CACHELINE == 0)
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{
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flush_dcache_range((ulong)p1-BYTE_PER_CACHELINE, (ulong)p1-1);
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#ifdef DEBUG
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printf("flush cache start<0x%lx>, end<0x%lx>\n", (ulong)p1-BYTE_PER_CACHELINE, (ulong)p1-1);
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#endif
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}
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#if defined(DDR_PHY0_ONLY) || defined(DDR_PHY1_ONLY)
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if(((ulong)p1 - (ulong)buf) % (BYTE_PER_INTERLEAVE/2) == 0)
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{
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// jump to next PHY1's interleave space
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p1+=BYTE_PER_INTERLEAVE/2/sizeof(pattern);
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}
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#endif
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}
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if((ulong)p1 % BYTE_PER_CACHELINE != 0)
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{
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flush_dcache_range((ulong)p1&(~(BYTE_PER_CACHELINE-1)), (ulong)p1-1);
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#ifdef DEBUG
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printf("flush cache start<0x%lx>, end<0x%lx>\n", (ulong)p1&(~(BYTE_PER_CACHELINE-1)), (ulong)p1-1);
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#endif
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}
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if (!need_check)
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goto ret;
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// compare result
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// invalid cache before read
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mdelay(100);
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invalidate_dcache_range((ulong)buf, (ulong)buf+(bit_len*4*2*2));
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p1 = buf;
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bit_cnt = 0;
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for (i = 0; i < bit_len; i++) {
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bit_cnt++;
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if (fixed_range && ((bit_cnt % FIXED_RANGE) == 0))
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p1 = buf; // reset ptr to beginning
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else if ((bit_cnt % (ddr_density/4/2)) == 0)
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p1 = buf; // reset ptr to beginning
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bit_value = 0;
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for (j = 0; j < dq_cnt; j++) {
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unsigned int sum = 0;
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for (k = 0; k < exp_cnt; k++) {
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char data = Queue_QueryAt(queue[j], exp[k]-1);
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sum += data;
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}
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sum = sum % 2;
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Queue_AddToHead(queue[j], sum);
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bit_value |= Queue_GetFromTail(queue[j]) << j;
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}
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pattern = bit_value;
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//pattern = _generate_prbs_pos(pos, bit_value);
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tmp = *p1;
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if (tmp != pattern) {
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printf("prbs test failure at addr<0x%lx>, expect<0x%x>, actual<0x%x>\n", (ulong)p1, pattern, tmp);
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}
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p1++;
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#if defined(DDR_PHY0_ONLY) || defined(DDR_PHY1_ONLY)
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if(((ulong)p1 - (ulong)buf) % (BYTE_PER_INTERLEAVE/2) == 0)
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{
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// jump to next PHY1's interleave space
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p1+=BYTE_PER_INTERLEAVE/2/sizeof(pattern);
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}
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#endif
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}
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for (i = 0; i < bit_len; i++) {
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bit_cnt++;
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if (fixed_range && ((bit_cnt % FIXED_RANGE) == 0))
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p1 = buf; // reset ptr to beginning
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else if ((bit_cnt % (ddr_density/4/2)) == 0)
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p1 = buf; // reset ptr to beginning
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bit_value = 0;
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for (j = 0; j < dq_cnt; j++) {
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unsigned int sum = 0;
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for (k = 0; k < exp_cnt; k++) {
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char data = Queue_QueryAt(queue[j], exp[k]-1);
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sum += data;
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}
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sum = sum % 2;
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Queue_AddToHead(queue[j], sum);
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bit_value |= Queue_GetFromTail(queue[j]) << j;
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}
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pattern = _generate_prbs_neg(pos, bit_value);
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tmp = *p1;
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if (tmp != pattern) {
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printf("prbs test failure at addr<0x%lx>, expect<0x%x>, actual<0x%x>\n", (ulong)p1, pattern, tmp);
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}
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p1++;
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#if defined(DDR_PHY0_ONLY) || defined(DDR_PHY1_ONLY)
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if(((ulong)p1 - (ulong)buf) % (BYTE_PER_INTERLEAVE/2) == 0)
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{
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// jump to next PHY1's interleave space
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p1+=BYTE_PER_INTERLEAVE/2/sizeof(pattern);
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}
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#endif
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}
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ret:
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for (i = 0; i < dq_cnt; i++)
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Queue_Free(queue[i], true);
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return 0;
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}
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static int do_prbs7_sequence_test(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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int ret = 0;
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unsigned int *buf, *p1;
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ulong addr = 0;
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ulong pos = 0;
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ulong iter = 1;
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ulong random_dq = 1;
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ulong i;
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ulong range = (1 << 7) *4 *2 *MULTIPLY; // occupys 4byte per bit, positive & negative, PHY0 & PHY1 space
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if (argc != 4 && argc != 5) {
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printf("should be 4 input parameters!!!");
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return CMD_RET_USAGE;
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}
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if (strict_strtoul(argv[1], 16, &addr) < 0)
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return CMD_RET_USAGE;
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if (strict_strtoul(argv[2], 16, &pos) < 0)
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return CMD_RET_USAGE;
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if (strict_strtoul(argv[3], 16, &iter) < 0)
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return CMD_RET_USAGE;
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if ((argc > 4) && strict_strtoul(argv[4], 16, &random_dq) < 0)
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return CMD_RET_USAGE;
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if ((addr < CONFIG_SYS_MEMTEST_START) || (addr > CONFIG_SYS_MEMTEST_END)) {
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printf("Refusing to do invalid region test 0x%lx\n", addr);
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//return -1;
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}
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if (pos >= 32) {
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printf("Refusing to do invalid bit position %ld\n", pos);
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return -1;
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}
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addr = addr & (~(BYTE_PER_INTERLEAVE - 1)); //addr align with ddr interleave(cacheline)
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#if defined(CONFIG_DDR_CHBIT_256B) && defined(DDR_PHY1_ONLY)
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addr += BYTE_PER_INTERLEAVE/2; // only access PHY1
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#endif
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printf("PRBS7 test: addr=0x%lx, pos=%d, iter=%d\n",
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addr, (int)pos, (int)iter);
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buf = map_sysmem(addr, range);
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p1 = buf;
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//clear buf and assure all buf allocated into cache entry
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for(i = 0; i < range; i+=4) {
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*p1++ = 0;
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}
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mdelay(100);
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for(i=0; i<iter; i++)
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{
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printf("prbs7 test itration<%ld>\n", i);
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riscv_get_time(&t_begin);
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prbs_test(&prbs7, buf, (int)pos, (random_dq!=0), checked);
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riscv_get_time(&t_end);
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printf("it spends %lld ms to do prbs7 sequence\n", (t_end - t_begin)/TIMER_TICK_MS);
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}
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return ret;
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}
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static int do_prbs15_sequence_test(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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int ret = 0;
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unsigned int *buf, *p1;
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ulong addr = 0;
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ulong pos = 0;
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ulong iter = 1;
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ulong random_dq = 1;
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ulong i;
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ulong range = (1 << 15) *4 *2 *MULTIPLY; // occupys 4byte per bit, positive & negative, PHY0 & PHY1 space
|
|
|
|
if (argc != 4 && argc != 5) {
|
|
printf("should be 4 input parameters!!!");
|
|
return CMD_RET_USAGE;
|
|
}
|
|
if (strict_strtoul(argv[1], 16, &addr) < 0)
|
|
return CMD_RET_USAGE;
|
|
if (strict_strtoul(argv[2], 16, &pos) < 0)
|
|
return CMD_RET_USAGE;
|
|
if (strict_strtoul(argv[3], 16, &iter) < 0)
|
|
return CMD_RET_USAGE;
|
|
if ((argc > 4) && strict_strtoul(argv[4], 16, &random_dq) < 0)
|
|
return CMD_RET_USAGE;
|
|
if ((addr < CONFIG_SYS_MEMTEST_START) || (addr > CONFIG_SYS_MEMTEST_END)) {
|
|
printf("Refusing to do invalid region test 0x%lx\n", addr);
|
|
//return -1;
|
|
}
|
|
if (pos >= 32) {
|
|
printf("Refusing to do invalid bit position %ld\n", pos);
|
|
return -1;
|
|
}
|
|
addr = addr & (~(BYTE_PER_INTERLEAVE - 1)); //addr align with ddr interleave(cacheline)
|
|
#if defined(CONFIG_DDR_CHBIT_256B) && defined(DDR_PHY1_ONLY)
|
|
addr += BYTE_PER_INTERLEAVE/2; // only access PHY1
|
|
#endif
|
|
printf("PRBS15 test: addr=0x%lx, pos=%d, iter=%d\n",
|
|
addr, (int)pos, (int)iter);
|
|
|
|
buf = map_sysmem(addr, range);
|
|
p1 = buf;
|
|
|
|
//clear buf and assure all buf allocated into cache entry
|
|
for(i = 0; i < range; i+=4) {
|
|
*p1++ = 0;
|
|
}
|
|
mdelay(100);
|
|
for(i=0; i<iter; i++)
|
|
{
|
|
printf("prbs15 test itration<%ld>\n", i);
|
|
riscv_get_time(&t_begin);
|
|
prbs_test(&prbs15, buf, (int)pos, (random_dq!=0), checked);
|
|
riscv_get_time(&t_end);
|
|
printf("it spends %lld ms to do prbs15 sequence\n", (t_end - t_begin)/TIMER_TICK_MS);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
static int do_prbs23_sequence_test(cmd_tbl_t *cmdtp, int flag, int argc,
|
|
char * const argv[])
|
|
{
|
|
int ret = 0;
|
|
unsigned int *buf, *p1;
|
|
ulong addr = 0;
|
|
ulong pos = 0;
|
|
ulong iter = 1;
|
|
ulong random_dq = 1;
|
|
ulong i;
|
|
ulong range = (1 << 23) *4 *2 *MULTIPLY; // occupys 4byte per bit, positive & negative, PHY0 & PHY1 space
|
|
|
|
if (argc != 4 && argc != 5) {
|
|
printf("should be 4 input parameters!!!");
|
|
return CMD_RET_USAGE;
|
|
}
|
|
if (strict_strtoul(argv[1], 16, &addr) < 0)
|
|
return CMD_RET_USAGE;
|
|
if (strict_strtoul(argv[2], 16, &pos) < 0)
|
|
return CMD_RET_USAGE;
|
|
if (strict_strtoul(argv[3], 16, &iter) < 0)
|
|
return CMD_RET_USAGE;
|
|
if ((argc > 4) && strict_strtoul(argv[4], 16, &random_dq) < 0)
|
|
return CMD_RET_USAGE;
|
|
if ((addr < CONFIG_SYS_MEMTEST_START) || (addr > CONFIG_SYS_MEMTEST_END)) {
|
|
printf("Refusing to do invalid region test 0x%lx\n", addr);
|
|
//return -1;
|
|
}
|
|
if (pos >= 32) {
|
|
printf("Refusing to do invalid bit position %ld\n", pos);
|
|
return -1;
|
|
}
|
|
addr = addr & (~(BYTE_PER_INTERLEAVE - 1)); //addr align with ddr interleave(cacheline)
|
|
#if defined(CONFIG_DDR_CHBIT_256B) && defined(DDR_PHY1_ONLY)
|
|
addr += BYTE_PER_INTERLEAVE/2; // only access PHY1
|
|
#endif
|
|
printf("PRBS23 test: addr=0x%lx, pos=%d, iter=%d\n",
|
|
addr, (int)pos, (int)iter);
|
|
|
|
buf = map_sysmem(addr, range);
|
|
p1 = buf;
|
|
|
|
//clear buf and assure all buf allocated into cache entry
|
|
for(i = 0; i < range; i+=4) {
|
|
*p1++ = 0;
|
|
}
|
|
mdelay(100);
|
|
for(i=0; i<iter; i++)
|
|
{
|
|
printf("prbs23 test itration<%ld>\n", i);
|
|
riscv_get_time(&t_begin);
|
|
prbs_test(&prbs23, buf, (int)pos, (random_dq!=0), checked);
|
|
riscv_get_time(&t_end);
|
|
printf("it spends %lld ms to do prbs23 sequence\n", (t_end - t_begin)/TIMER_TICK_MS);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
static int do_prbs31_sequence_test(cmd_tbl_t *cmdtp, int flag, int argc,
|
|
char * const argv[])
|
|
{
|
|
int ret = 0;
|
|
unsigned int *buf, *p1;
|
|
ulong addr = 0;
|
|
ulong pos = 0;
|
|
ulong iter = 1;
|
|
ulong random_dq = 1;
|
|
ulong i;
|
|
ulong ddr_density = get_ddr_density();
|
|
ulong range = (ulong)(1 << 31) *4; // occupys 4byte per bit, positive & negative, PHY0 & PHY1 space
|
|
// too large to store prbs31 patterns in DDR space, mmap 4GB and wrap write is allowed
|
|
if (range > ddr_density)
|
|
range = ddr_density;
|
|
|
|
range = FIXED_RANGE; // FIXED_RANGE for prbs_31
|
|
|
|
if (argc != 4 && argc != 5) {
|
|
printf("should be 4 input parameters!!!");
|
|
return CMD_RET_USAGE;
|
|
}
|
|
if (strict_strtoul(argv[1], 16, &addr) < 0)
|
|
return CMD_RET_USAGE;
|
|
if (strict_strtoul(argv[2], 16, &pos) < 0)
|
|
return CMD_RET_USAGE;
|
|
if (strict_strtoul(argv[3], 16, &iter) < 0)
|
|
return CMD_RET_USAGE;
|
|
|
|
if ((argc > 4) && strict_strtoul(argv[4], 16, &random_dq) < 0)
|
|
return CMD_RET_USAGE;
|
|
if ((addr < CONFIG_SYS_MEMTEST_START) || (addr > CONFIG_SYS_MEMTEST_END)) {
|
|
printf("Refusing to do invalid region test 0x%lx\n", addr);
|
|
//return -1;
|
|
}
|
|
if (pos >= 32) {
|
|
printf("Refusing to do invalid bit position %ld\n", pos);
|
|
return -1;
|
|
}
|
|
addr = addr & (~(BYTE_PER_INTERLEAVE - 1)); //addr align with ddr interleave(cacheline)
|
|
#if defined(CONFIG_DDR_CHBIT_256B) && defined(DDR_PHY1_ONLY)
|
|
addr += BYTE_PER_INTERLEAVE/2; // only access PHY1
|
|
#endif
|
|
printf("PRBS31 test: addr=0x%lx, pos=%d, iter=%d\n",
|
|
addr, (int)pos, (int)iter);
|
|
|
|
buf = map_sysmem(addr, range);
|
|
p1 = buf;
|
|
|
|
//clear buf and assure all buf allocated into cache entry
|
|
for(i = 0; i < range; i+=4) {
|
|
*p1++ = 0;
|
|
}
|
|
mdelay(100);
|
|
for(i=0; i<iter; i++)
|
|
{
|
|
printf("prbs31 test itration<%ld>\n", i);
|
|
riscv_get_time(&t_begin);
|
|
prbs_test(&prbs31, buf, (int)pos, (random_dq!=0), false); // too large to check result
|
|
riscv_get_time(&t_end);
|
|
printf("it spends %lld ms to do prbs31 sequence\n", (t_end - t_begin)/TIMER_TICK_MS);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
U_BOOT_CMD(
|
|
prbs_7, 5, 1, do_prbs7_sequence_test,
|
|
"PRBS_7 sequence test",
|
|
"[addr bit [iterations [is_random_dq]]]"
|
|
);
|
|
U_BOOT_CMD(
|
|
prbs_15, 5, 1, do_prbs15_sequence_test,
|
|
"PRBS_15 sequence test",
|
|
"[addr bit [iterations [is_random_dq]]]"
|
|
);
|
|
U_BOOT_CMD(
|
|
prbs_23, 5, 1, do_prbs23_sequence_test,
|
|
"PRBS_23 sequence test",
|
|
"[addr bit [iterations [is_random_dq]]]"
|
|
);
|
|
U_BOOT_CMD(
|
|
prbs_31, 5, 1, do_prbs31_sequence_test,
|
|
"PRBS_31 sequence test",
|
|
"[addr bit [iterations [is_random_dq]]]"
|
|
);
|
|
|