mirror of
https://github.com/revyos/th1520-vendor-uboot.git
synced 2026-09-17 21:02:04 +02:00
117 lines
3.5 KiB
ArmAsm
117 lines
3.5 KiB
ArmAsm
/*
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* Copyright (C) 2017-2020 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "config.h"
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.global hw_vsr_default_exception
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.global hw_vsr_autovec
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.global hw_vsr_fastautovec
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.global hw_vsr_reset
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.global hw_vsr_tlbmiss
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.extern csky_default_exception_handler
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.extern ck_irq_service
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.text
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.balign 4
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hw_vsr_default_exception:
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subi sp, 124 /* Preserve the entire state. */
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stm r0-r13, (sp)
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addi sp, 56
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stm r15-r31, (sp)
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subi sp, 56
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subi sp, 8
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mfcr r2, epsr
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stw r2, (sp,4) /* save epsr registwr */
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mfcr r2, epc
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stw r2, (sp,0) /* save epc register */
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mfcr r0, psr /* Get psr register */
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lsri r0, 16 /* Get vector in 7 bits */
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sextb r0 /* Fill upper bytes with zero */
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mov r1, sp /* pass stack point to r3*/
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jsri csky_default_exception_handler
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/* exception VSR.*/
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ldw r2, (sp,0)
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mtcr r2, epc /* restore the epc */
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ldw r2, (sp,4)
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mtcr r2, epsr /* restore the epsr */
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addi sp, 8
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ldm r0-r13,(sp) /* restore all the regs */
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addi sp,56
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ldm r15-r31,(sp)
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addi sp,68
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rte
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/*********************************************************************/
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/* Normal interrupt vector handler. */
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/*********************************************************************/
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.text
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.balign 4
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hw_vsr_autovec:
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subi sp, 124 /* Preserve the entire state. */
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stm r0-r13, (sp)
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addi sp, 56
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stm r15-r31, (sp)
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subi sp, 56
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subi sp, 8
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mfcr r2, epsr
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stw r2, (sp,4) /* save epsr registwr */
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mfcr r2, epc
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stw r2, (sp,0) /* save epc register */
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/* read the interrupt vector number from interrupt status register */
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lrw r4, INTC_BASEADDRESS
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ldw r0, (r4, 0x0)
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movi r10,0x7f
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and r0, r10
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subi r0, 0x20
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jsri ck_irq_service
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ldw r2, (sp,0)
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mtcr r2, epc /* restore the epc */
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ldw r2, (sp,4)
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mtcr r2, epsr /* restore the epsr */
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addi sp, 8
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ldm r0-r13,(sp) /* restore all the regs */
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addi sp,56
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ldm r15-r31,(sp)
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addi sp,68
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rte
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/****************************************************************************/
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/* Fast interrupt vector handler. */
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/****************************************************************************/
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.text
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.balign 4
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hw_vsr_fastautovec:
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/*read the interrupt vector number from interrupt status register */
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lrw r4, INTC_BASEADDRESS
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ldw r0, (r4, 0x0)
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movi r10,0x7f
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and r0, r10
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jsri ck_irq_service
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rfi /* Restore the psr and pc */
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/****************************************************************************/
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/* reset interrupt vector handler. */
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/****************************************************************************/
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.text
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.balign 4
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hw_vsr_reset:
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jsri _start
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rte /* Restore the psr and pc */
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