commit 23b86710327ba2a0a4dbd2386a353b3e41b877b8 Author: thead_admin Date: Tue Sep 13 10:34:22 2022 +0800 Linux_SDK_V0.9.5 diff --git a/Makefile b/Makefile new file mode 100755 index 0000000..7d5246d --- /dev/null +++ b/Makefile @@ -0,0 +1,164 @@ +## + # Copyright (C) 2020 Alibaba Group Holding Limited +## +test = $(shell if [ -f "../.param" ]; then echo "exist"; else echo "noexist"; fi) +ifeq ("$(test)", "exist") + include ../.param +endif + +CONFIG_COMPILE_PLATFORM=RISCV + +CONFIG_ISP_BUILD_TYPE=DEBUG +#CONFIG_ISP_BUILD_TYPE=RELEASE +CONFIG_ISP_VERSION=ISP8000L_V2008 + +CONFIG_ISP_RY_BUILD_TYPE=DEBUG +#CONFIG_ISP_RY_BUILD_TYPE=RELEASE +CONFIG_ISP_RY_VERSION=ISP8000_V2009 + + +CONFIG_MAKE_ISP_DRIVER_CMD:= \ + make -C vvcam/native VERSION_CFG=$(CONFIG_ISP_VERSION) \ + KERNEL=$(LINUX_DIR) CROSS=$(CROSS_COMPILE) ARCH=$(ARCH) BOARD_NAME=$(BOARD_NAME) + +CONFIG_DW200_CMAKE_CMD:= \ + cmake -DCMODEL=$(CONFIG_DW200_CMODEL) \ + -DV4L2=$(CONFIG_DW200_V4L2) \ + -DARM64_LOCAL_CROSS=OFF .. + +CONFIG_DEC400_CMAKE_CMD:= \ + cmake -Wno-dev .. + + +CONFIG_MAKE_ISP_RY_DRIVER_CMD:= \ + make -C vvcam_ry/native VERSION_CFG=$(CONFIG_ISP_RY_VERSION) \ + KERNEL=$(LINUX_DIR) CROSS=$(CROSS_COMPILE) ARCH=$(ARCH) BOARD_NAME=$(BOARD_NAME) + +DIR_ISP_TARGET_BASE=bsp/isp +DIR_ISP_TARGET_KO =bsp/isp/ko + +DIR_ISP_RY_TARGET_BASE=bsp/isp_ry +DIR_ISP_RY_TARGET_KO =bsp/isp_ry/ko + +DIR_DW200_TARGET_BASE=bsp/dw200 + + +DIR_DEC400_TARGET_BASE=bsp/dec400 + +MODULE_NAME=ISP +BUILD_LOG_START="\033[47;30m>>> $(MODULE_NAME) $@ begin\033[0m" +BUILD_LOG_END ="\033[47;30m<<< $(MODULE_NAME) $@ end\033[0m" + +# +# Do a parallel build with multiple jobs, based on the number of CPUs online +# in this system: 'make -j8' on a 8-CPU system, etc. +# +# (To override it, run 'make JOBS=1' and similar.) +# +ifeq ($(JOBS),) + JOBS := $(shell grep -c ^processor /proc/cpuinfo 2>/dev/null) + ifeq ($(JOBS),) + JOBS := 1 + endif +endif + +all: info isp_driver isp_ry_driver\ + install_local_output install_rootfs +.PHONY: info isp_driver isp_ry_driver\ + install_local_output install_rootfs \ + clean_isp_driver clean_isp_ry_driver \ + clean_output clean + +info: + @echo $(BUILD_LOG_START) + @echo " ====== Build Info from repo project ======" + @echo " BUILDROOT_DIR="$(BUILDROOT_DIR) + @echo " CROSS_COMPILE="$(CROSS_COMPILE) + @echo " LINUX_DIR="$(LINUX_DIR) + @echo " ARCH="$(ARCH) + @echo " BOARD_NAME="$(BOARD_NAME) + @echo " KERNEL_ID="$(KERNELVERSION) + @echo " KERNEL_DIR="$(LINUX_DIR) + @echo " INSTALL_DIR_ROOTFS="$(INSTALL_DIR_ROOTFS) + @echo " DIR_MODULE_TOP="$(DIR_MODULE_TOP) + @echo " ====== Build configuration by settings ======" + @echo " COMPILE_PLATFORM="$(CONFIG_COMPILE_PLATFORM) + @echo " JOBS="$(JOBS) + @echo " ISP_BUILD_TYPE="$(CONFIG_ISP_BUILD_TYPE) + @echo " ISP_VERSION="$(CONFIG_ISP_VERSION) + @echo " CMAKE_ISP_DRIVER_CMD=" $(CONFIG_MAKE_ISP_DRIVER_CMD) + @echo " DW200_CMODEL="$(CONFIG_DW200_CMODEL) + @echo " DW200_V4L2="$(CONFIG_DW200_V4L2) + @echo " DW200_BUILD_DIR="$(CONFIG_DW200_BUILD_DIR) + @echo " DW200_CMAKE_CMD="$(CONFIG_DW200_CMAKE_CMD) + @echo " DEC400_BUILD_DIR="$(CONFIG_DEC400_BUILD_DIR) + @echo " DEC400_CMAKE_CMD="$(CONFIG_DEC400_CMAKE_CMD) + @echo " ISP_RY_BUILD_TYPE="$(CONFIG_ISP_RY_BUILD_TYPE) + @echo " ISP_RY_VERSION="$(CONFIG_ISP_RY_VERSION) + + @echo $(BUILD_LOG_END) + +isp_driver: + @echo $(BUILD_LOG_START) + $(CONFIG_MAKE_ISP_DRIVER_CMD) + @echo $(BUILD_LOG_END) + +clean_isp_driver: + @echo $(BUILD_LOG_START) + make -C vvcam/native VERSION_CFG=$(CONFIG_ISP_VERSION) clean + #make -C vvcam/v4l2 VERSION_CFG=$(CONFIG_ISP_VERSION) clean + rm -f vvcam/dw200/.*.o.cmd + rm -f vvcam/isp/.*.o.cmd + rm -f vvcam/native/bin/*.ko + @echo $(BUILD_LOG_END) + +isp_ry_driver: + @echo $(BUILD_LOG_START) + $(CONFIG_MAKE_ISP_RY_DRIVER_CMD) + @echo $(BUILD_LOG_END) + +clean_isp_ry_driver: + @echo $(BUILD_LOG_START) + make -C vvcam_ry/native VERSION_CFG=$(CONFIG_ISP_RY_VERSION) clean + make -C vvcam_ry/v4l2 VERSION_CFG=$(CONFIG_ISP_RY_VERSION) clean + rm -f vvcam_ry/dw200/.*.o.cmd + rm -f vvcam_ry/isp/.*.o.cmd + rm -f vvcam_ry/native/bin/*.ko + @echo $(BUILD_LOG_END) + + + + + +install_local_output: isp_driver isp_ry_driver + @echo $(BUILD_LOG_START) + # isp driver files + mkdir -p ./output/rootfs/$(DIR_ISP_TARGET_KO) + chmod +x ./vvcam/native/bin/*.sh + cp -f ./vvcam/native/bin/* ./output/rootfs/$(DIR_ISP_TARGET_KO) + + # isp ry driver files + mkdir -p ./output/rootfs/$(DIR_ISP_RY_TARGET_KO) + chmod +x ./vvcam_ry/native/bin/*.sh + cp -f ./vvcam_ry/native/bin/vvcam_isp_ry.ko ./output/rootfs/$(DIR_ISP_TARGET_KO) + +install_rootfs: install_local_output + @echo $(BUILD_LOG_START) +# cp -rf output/rootfs/* $(INSTALL_DIR_ROOTFS) + @echo $(BUILD_LOG_END) + +clean_output: + @echo $(BUILD_LOG_START) + rm -rf ./output + rm -rf $(INSTALL_DIR_ROOTFS)/$(DIR_ISP_TARGET_BASE) + rm -rf $(INSTALL_DIR_ROOTFS)/$(DIR_ISP_RY_TARGET_BASE) + rm -rf $(INSTALL_DIR_ROOTFS)/$(DIR_DW200_TARGET_BASE) + rm -rf $(INSTALL_DIR_ROOTFS)/$(DIR_DEC400_TARGET_BASE) + @echo $(BUILD_LOG_END) + +clean_proprietories_include: + @echo $(BUILD_LOG_START) + @echo $(BUILD_LOG_END) + +clean: clean_output clean_isp_driver \ + clean_isp_ry_driver clean_proprietories_include diff --git a/README.md b/README.md new file mode 100644 index 0000000..e69de29 diff --git a/vvcam/.gitignore b/vvcam/.gitignore new file mode 100755 index 0000000..3e321f2 --- /dev/null +++ b/vvcam/.gitignore @@ -0,0 +1,15 @@ +*.cmd +*.mod +*.o +*.swp +.vscode/* +.tmp_versions/* +Module.symvers +*.ko +modules.order +*mod.c +*cmd.c +*.o.d +*.a +*.tmp +.cache.mk diff --git a/vvcam/LICENSE b/vvcam/LICENSE new file mode 100755 index 0000000..efa96c4 --- /dev/null +++ b/vvcam/LICENSE @@ -0,0 +1,114 @@ +/**************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + *****************************************************************************/ + +GNU GENERAL PUBLIC LICENSE +Version 2, June 1991 + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. + +Preamble + +The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. + +To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. + +For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. + +We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. + +Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. + +Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. + +The precise terms and conditions for copying, distribution and modification follow. + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + +0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. + +1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. + +You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. + +2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. + + c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. + +3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. + +If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. + +4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. + +5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. + +6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. + +7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. + +This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. + +8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. + +9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. + +10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. + +NO WARRANTY + +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +END OF TERMS AND CONDITIONS + diff --git a/vvcam/README.md b/vvcam/README.md new file mode 100755 index 0000000..4c41acc --- /dev/null +++ b/vvcam/README.md @@ -0,0 +1,4 @@ +# vvcam + +ISP8000 vvcam project. +ISP8000NANO TAG:origin/nxp_4.2.2_rc5 diff --git a/vvcam/common/viv_video_kevent.h b/vvcam/common/viv_video_kevent.h new file mode 100755 index 0000000..d900f1c --- /dev/null +++ b/vvcam/common/viv_video_kevent.h @@ -0,0 +1,191 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VIV_VIDEO_KEVENT_H_ +#define _VIV_VIDEO_KEVENT_H_ +#include + +#ifndef __KERNEL__ +#include +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; +#endif + +enum { + VIV_VIDEO_EVENT_MIN = 0, + VIV_VIDEO_EVENT_NEW_STREAM, + VIV_VIDEO_EVENT_DEL_STREAM, + VIV_VIDEO_EVENT_START_STREAM, + VIV_VIDEO_EVENT_STOP_STREAM, + VIV_VIDEO_EVENT_SET_FMT, + VIV_VIDEO_EVENT_SET_CROP, + VIV_VIDEO_EVENT_SET_COMPOSE, + VIV_VIDEO_EVENT_QUERYCAPS, + VIV_VIDEO_EVENT_PASS_JSON, + VIV_VIDEO_EVENT_EXTCTRL, + VIV_VIDEO_EVENT_EXTCTRL2, + VIV_VIDEO_EVENT_SET_CAPSMODE, + VIV_VIDEO_EVENT_GET_CAPS_SUPPORTS, + VIV_VIDEO_EVENT_CREATE_PIPELINE, + VIV_VIDEO_EVENT_QBUF, + VIV_VIDEO_EVENT_MAX, +}; + +enum { + VIV_DWE_EVENT_MIN = VIV_VIDEO_EVENT_MAX + 1, + VIV_DWE_EVENT_FRAMEDONE, + VIV_DWE_EVENT_MAX, +}; + +/* max support to 64 bytes! */ +struct viv_video_event { + u32 stream_id; + void *file; + u64 addr; + int buf_index; + u64 response; + u32 sync; +}; + +struct v4l2_user_buffer { + u64 addr; + int streamid; + void *file; +}; + +struct viv_rect { + __s16 left; + __s16 top; + __u16 width; + __u16 height; +}; + +#define VIV_EVENT_BUF_SIZE (4*1024) + +#define VIV_JSON_BUFFER_SIZE (64*1024) +struct viv_control_event { + /* physical address of json request, fixed size 64K */ + u64 request; + /* physical address of json response fixed size 64K */ + u64 response; + u32 id; +}; + + +struct ext_buf_info { + u64 addr; + u64 size; +}; + +struct vvcam_constant_modeinfo { + unsigned index; + unsigned w; + unsigned h; + unsigned fps; + unsigned brpat; /*bayer pattern*/ + unsigned bitw; /*bit width*/ +}; + +#define CALIBXML_FILE_NAME_SIZE 64 +struct viv_caps_mode_s { + int mode; + char CalibXmlName[CALIBXML_FILE_NAME_SIZE]; +}; + +enum viv_caps_hdr_mode_e +{ + VIV_CAPS_MODE_LINEAR , + VIV_CAPS_MODE_HDR_STITCH, + VIV_CAPS_MODE_HDR_NATIVE, +}; + +struct viv_caps_mode_info_s{ + unsigned int index; + unsigned int width; + unsigned int height; + unsigned int hdr_mode; + unsigned int fps; +}; + +#define VIV_CAPS_MODE_MAX_COUNT 20 +struct viv_caps_supports{ + unsigned int count; + struct viv_caps_mode_info_s mode[VIV_CAPS_MODE_MAX_COUNT]; +}; + +#define VIV_VIDEO_ISPIRQ_TYPE (V4L2_EVENT_PRIVATE_START + 0x0) +#define VIV_VIDEO_MIIRQ_TYPE (V4L2_EVENT_PRIVATE_START + 0x1) +#define VIV_VIDEO_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x2000) +#define VIV_DWE_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x3000) + +#define VIV_VIDEO_EVENT_TIMOUT_MS 5000 + +#define VIV_VIDIOC_EVENT_COMPLETE _IOW('V', BASE_VIDIOC_PRIVATE + 100, struct viv_video_event) +#define VIV_VIDIOC_BUFFER_ALLOC _IOWR('V', BASE_VIDIOC_PRIVATE + 101, struct ext_buf_info) +#define VIV_VIDIOC_BUFFER_FREE _IOWR('V', BASE_VIDIOC_PRIVATE + 102, struct ext_buf_info) +#define VIV_VIDIOC_CONTROL_EVENT _IOWR('V', BASE_VIDIOC_PRIVATE + 103, struct viv_control_event) +#define VIV_VIDIOC_S_STREAMID _IOW('V', BASE_VIDIOC_PRIVATE + 104, int) +#define VIV_VIDIOC_BUFDONE _IOW('V', BASE_VIDIOC_PRIVATE + 105, struct v4l2_user_buffer) +#define VIV_VIDIOC_QUERY_EXTMEM _IOWR('V', BASE_VIDIOC_PRIVATE + 106, struct ext_buf_info) +#define VIV_VIDIOC_S_ENDPOINT _IOW('V', BASE_VIDIOC_PRIVATE + 107, int) +#define VIV_VIDIOC_S_MODEINFO _IOW('V', BASE_VIDIOC_PRIVATE + 108, struct vvcam_constant_modeinfo) +#define VIV_VIDIOC_S_CAPS_MODE _IOW('V', BASE_VIDIOC_PRIVATE + 109, struct viv_caps_mode_s) +#define VIV_VIDIOC_G_CAPS_MODE _IOWR('V', BASE_VIDIOC_PRIVATE + 110, struct viv_caps_mode_s) +#define VIV_VIDIOC_EVENT_RESULT _IOWR('V', BASE_VIDIOC_PRIVATE + 111,int) +#define VIV_VIDIOC_GET_CAPS_SUPPORTS _IOWR('V', BASE_VIDIOC_PRIVATE + 112,struct viv_caps_supports) +#define VIV_VIDIOC_SET_CAPS_SUPPORTS _IOWR('V', BASE_VIDIOC_PRIVATE + 113,struct viv_caps_supports) +#define VIV_VIDIOC_S_DWECFG _IOW('V', BASE_VIDIOC_PRIVATE + 114, int) +#define VIV_VIDIOC_G_DWECFG _IOR('V', BASE_VIDIOC_PRIVATE + 115, int) + +#endif diff --git a/vvcam/common/vvcsioc.h b/vvcam/common/vvcsioc.h new file mode 100755 index 0000000..9dfe9fa --- /dev/null +++ b/vvcam/common/vvcsioc.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVCAM_CSIOC_H_ +#define _VVCAM_CSIOC_H_ +#ifdef __KERNEL__ +#include +#else +#include +#endif + +enum { + VVCSIOC_RESET = 0x100, + VVCSIOC_POWERON, + VVCSIOC_POWEROFF, + VVCSIOC_STREAMON, + VVCSIOC_STREAMOFF, + VVCSIOC_S_FMT, + VVCSIOC_S_HDR, +}; + +struct csi_sam_format { + int64_t format; + __u32 width; + __u32 height; +}; + +#endif /* _VVCAM_CSIOC_H_ */ diff --git a/vvcam/common/vvctrl.h b/vvcam/common/vvctrl.h new file mode 100755 index 0000000..7a6ca0e --- /dev/null +++ b/vvcam/common/vvctrl.h @@ -0,0 +1,148 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVCTRL_H_ +#define _VVCTRL_H_ + +#include + +#define VIV_CUSTOM_CID_BASE (V4L2_CID_USER_BASE | 0xf000) +#define V4L2_CID_VIV_STRING (VIV_CUSTOM_CID_BASE + 0x01) +#define V4L2_CID_VIV_SENSOR_MODE (VIV_CUSTOM_CID_BASE + 0x02) +#define V4L2_CID_VIV_SENSOR_RES_W (VIV_CUSTOM_CID_BASE + 0x03) +#define V4L2_CID_VIV_SENSOR_RES_H (VIV_CUSTOM_CID_BASE + 0x04) +#define V4L2_CID_VIV_SENSOR_TPG_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x05) +#define V4L2_CID_VIV_DEWARP_MODE (VIV_CUSTOM_CID_BASE + 0x06) +#define V4L2_CID_VIV_DEWARP_BYPASS_STATUS (VIV_CUSTOM_CID_BASE + 0x07) +#define V4L2_CID_VIV_AEC_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x08) +#define V4L2_CID_VIV_AWB_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x09) +#define V4L2_CID_VIV_AWB_DAMPING_STATUS (VIV_CUSTOM_CID_BASE + 0x0A) +#define V4L2_CID_VIV_LSC_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x0B) +#define V4L2_CID_VIV_CPROC_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x0C) +#define V4L2_CID_VIV_GAMMA_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x0D) +#define V4L2_CID_VIV_GAMMA_MODE (VIV_CUSTOM_CID_BASE + 0x0E) +#define V4L2_CID_VIV_DEMOSAIC_MODE (VIV_CUSTOM_CID_BASE + 0x0F) +#define V4L2_CID_VIV_FILTER_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x10) +#define V4L2_CID_VIV_CAC_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x11) +#define V4L2_CID_VIV_DPCC_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x12) +#define V4L2_CID_VIV_CNR_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x13) +#define V4L2_CID_VIV_DPF_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x14) +#define V4L2_CID_VIV_WDR3_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x15) +#define V4L2_CID_VIV_AVS_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x16) +#define V4L2_CID_VIV_2DNR_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x17) +#define V4L2_CID_VIV_3DNR_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x18) +#define V4L2_CID_VIV_HDR_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x19) +#define V4L2_CID_VIV_HDR_MODE (VIV_CUSTOM_CID_BASE + 0x1A) +#define V4L2_CID_VIV_STITCHING_MODE (VIV_CUSTOM_CID_BASE + 0x1B) +#define V4L2_CID_VIV_IS_OUT_RES_W (VIV_CUSTOM_CID_BASE + 0x1C) +#define V4L2_CID_VIV_IS_OUT_RES_H (VIV_CUSTOM_CID_BASE + 0x1D) +#define V4L2_CID_VIV_MP_OUT_RES_W (VIV_CUSTOM_CID_BASE + 0x1E) +#define V4L2_CID_VIV_MP_OUT_RES_H (VIV_CUSTOM_CID_BASE + 0x1F) +#define V4L2_CID_VIV_MP_OUT_FORMAT (VIV_CUSTOM_CID_BASE + 0x20) +#define V4L2_CID_VIV_PIPELINE_SMP_MODE (VIV_CUSTOM_CID_BASE + 0x21) +#define V4L2_CID_VIV_PIPELINE_DWE_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x22) + +enum v4l2_ctrl_direction { + V4L2_CTRL_GET, + V4L2_CTRL_SET, +}; + +struct v4l2_ctrl_data { + struct v4l2_ext_controls ctrls; + enum v4l2_ctrl_direction dir; + int ret; +}; + +#define nextof(ptr, new_type) ((new_type)((ptr) + 1)) + +#ifdef __KERNEL__ +int viv_gen_g_ctrl(struct v4l2_ctrl *ctrl); +int viv_gen_s_ctrl(struct v4l2_ctrl *ctrl); + +static const struct v4l2_ctrl_ops viv_gen_ctrl_ops = { + .g_volatile_ctrl = viv_gen_g_ctrl, + .s_ctrl = viv_gen_s_ctrl, +}; + +static const struct v4l2_ctrl_config viv_ctrl_sensor_resw = { + .ops = &viv_gen_ctrl_ops, + .id = V4L2_CID_VIV_SENSOR_RES_W, + .name = "sensor.resw", + .type = V4L2_CTRL_TYPE_INTEGER, + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, + .min = 0, + .max = 3840, + .def = 1920, + .step = 1, +}; + +static const struct v4l2_ctrl_config viv_ctrl_sensor_resh = { + .ops = &viv_gen_ctrl_ops, + .id = V4L2_CID_VIV_SENSOR_RES_H, + .name = "sensor.resh", + .type = V4L2_CTRL_TYPE_INTEGER, + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, + .min = 0, + .max = 2160, + .def = 1080, + .step = 1, +}; + +#define create_controls(handler) \ +do { \ + v4l2_ctrl_new_custom(handler, &viv_ctrl_sensor_resw, NULL); \ + v4l2_ctrl_new_custom(handler, &viv_ctrl_sensor_resh, NULL); \ +} while (0) + +#endif + +#endif /* _VVCTRL_H_ */ diff --git a/vvcam/common/vvdefs.h b/vvcam/common/vvdefs.h new file mode 100755 index 0000000..cd45914 --- /dev/null +++ b/vvcam/common/vvdefs.h @@ -0,0 +1,146 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_VVDEFS_H_ +#define _ISP_VVDEFS_H_ + +#define viv_check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +#ifndef VIV_MEDIA_PIX_FMT +#define VIV_MEDIA_PIX_FMT +enum { + MEDIA_PIX_FMT_YUV422SP = 0, + MEDIA_PIX_FMT_YUV422I, + MEDIA_PIX_FMT_YUV420SP, + MEDIA_PIX_FMT_YUV444P, + MEDIA_PIX_FMT_YUV444I, + MEDIA_PIX_FMT_RGB888, + MEDIA_PIX_FMT_RGB888P, + MEDIA_PIX_FMT_BGR888P, + MEDIA_PIX_FMT_RAW8, + MEDIA_PIX_FMT_RAW10, + MEDIA_PIX_FMT_RAW12, +}; +#endif + +#ifndef __KERNEL__ +#include +#include +#include +#include +#include + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +#define pr_info(...) printf(__VA_ARGS__) +#define pr_err(...) printf(__VA_ARGS__) +#define pr_debug(...) printf(__VA_ARGS__) +#define __user +#define __iomem +#else /* __KERNEL__ */ + +/* if v4l2 */ +#include +#include +#include +#include +#include +#include +#include +#include + +enum STATE_CODE { + STATE_STOPPED = 0, + STATE_STREAM_STARTED = 1 << 1, + STATE_DRIVER_STARTED = 1 << 2, +}; +#endif + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef ALIGN_UP +#define ALIGN_UP(x, align) (((x) + ((align) - 1)) & ~((align)-1)) +#endif + +#define ISP_COMPAT_NAME "fsl,imx8mp-isp" +#define DWE_COMPAT_NAME "fsl,imx8mp-dwe" + +#define ISP_DEVICE_NAME "vvcam-isp" +#define DWE_DEVICE_NAME "vvcam-dwe" + +#define ISP_PAD_SOURCE (0) +#define ISP_PADS_NUM (1) + +#define DWE_PAD_SOURCE (0) +#define DWE_PAD_SINK (1) +#define DWE_PADS_NUM (2) + +#define RESV_STREAMID_ISP(id) \ + ((id) ? RESV_STREAMID_ISP1 : RESV_STREAMID_ISP0) +#define RESV_STREAMID_ISP0 (-2) +#define RESV_STREAMID_ISP1 (-3) +#define RESV_STREAMID_DWE (-4) + +#endif /* _ISP_VVDEFS_H_ */ diff --git a/vvcam/common/vvnative.c b/vvcam/common/vvnative.c new file mode 100755 index 0000000..2322820 --- /dev/null +++ b/vvcam/common/vvnative.c @@ -0,0 +1,642 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include /* Module support */ +#include /* Kernel version */ +#include /* Charactor device support */ +#include +#include +#include +#include + +#include +#include + + +#include "vvnative.h" +#include "vvnative_cfg.h" +#include "vvnative_combo.h" + +#ifdef SENSOR_USE_GPIO_I2C +#include "soc_i2c.h" +#endif + +#ifndef MODULE_LICENSE +# define MODULE_LICENSE(x) +#endif /* MODULE_LICENSE */ + +#ifndef MODULE_VERSION +# define MODULE_VERSION(x) +#endif /* MODULE_VERSION */ + +#define DRIVER_AUTHOR "VeriSilicon IPD" +#define DRIVER_DESC "Verisilicon ISP driver" +#define DRIVER_LICENSE "GPL" +#define DRIVER_VERSION "1.0" + + +#ifdef MODULE +MODULE_AUTHOR( DRIVER_AUTHOR ); +MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_LICENSE( DRIVER_LICENSE ); +MODULE_INFO( vermagic, VERMAGIC_STRING); +#endif /* MODULE */ + + +/* vvcam_isp_dev_major: device major number */ +unsigned int vvcam_isp_dev_major = 0; +module_param(vvcam_isp_dev_major, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcam_isp_dev_major, "vvcam ISP device major number"); + +/* vvcam_isp_dev_minor: device base(start) minor number */ +unsigned int vvcam_isp_dev_minor = 0; +module_param(vvcam_isp_dev_minor, uint, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(vvcam_isp_dev_minor, "vvcam ISP device base minor number"); + +/* vvcam_isp_dev_count: counts */ +unsigned int vvcam_isp_dev_count = VVCAM_ISP_DEVICES; +module_param(vvcam_isp_dev_count, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcam_isp_dev_count, "vvcam ISP device counts"); + + +struct vvcam_isp_dev *vvcam_isp_drv; +struct vvcam_common *vvcam_drv_common; + +static int vvcam_isp_dev_open(struct inode *inode, struct file *file); +static int vvcam_isp_dev_release(struct inode *inode, struct file *file); +static long vvcam_isp_dev_ioctl(struct file * pFile, unsigned int cmd, unsigned long arg); +static int vvcam_isp_dev_mmap(struct file *pFile, struct vm_area_struct *vma); +static int vvcam_isp_devio_remap(int dev_no); +static int vvcam_isp_devio_unmap(int dev_no); + +long (*vvnative_ioctl[])(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args)= +{ + vvcam_combo_isp_ioctl, /*devid0*/ + vvcam_combo_isp_ioctl, /*devid1*/ + vvcam_combo_csi_ioctl, /*devid2*/ + vvcam_combo_csi_ioctl, /*devid3*/ + vvcam_combo_sensor_ioctl, /*devid4*/ + vvcam_combo_sensor_ioctl, /*devid5*/ + vvcam_combo_dwe_ioctl, /*devid6*/ + vvcam_combo_vse_ioctl, /*devid7*/ + vvcam_combo_soc_ioctl, /*devid8*/ +}; + +int (*vvnative_init[])(struct vvcam_isp_dev *vvcam_isp_drv)= +{ + vvcam_combo_isp_init, /*devid0*/ + vvcam_combo_isp_init, /*devid1*/ + vvcam_combo_csi_init, /*devid2*/ + vvcam_combo_csi_init, /*devid3*/ + vvcam_combo_sensor_init, /*devid4*/ + vvcam_combo_sensor_init, /*devid5*/ + vvcam_combo_dwe_init, /*devid6*/ + vvcam_combo_vse_init, /*devid7*/ + vvcam_combo_soc_init, /*devid8*/ +}; + +int (*vvnative_deinit[])(struct vvcam_isp_dev *vvcam_isp_drv)= +{ + vvcam_combo_isp_deinit, /*devid0*/ + vvcam_combo_isp_deinit, /*devid1*/ + vvcam_combo_csi_deinit, /*devid2*/ + vvcam_combo_csi_deinit, /*devid3*/ + vvcam_combo_sensor_deinit, /*devid4*/ + vvcam_combo_sensor_deinit, /*devid5*/ + vvcam_combo_dwe_deinit, /*devid6*/ + vvcam_combo_vse_deinit, /*devid7*/ + vvcam_combo_soc_deinit, /*devid8*/ +}; + +/*TODO:expand dual camera devs*/ +struct file_operations vvcam_isp_fops = { + .owner = THIS_MODULE, + .open = vvcam_isp_dev_open, + .release = vvcam_isp_dev_release, + .unlocked_ioctl = vvcam_isp_dev_ioctl, + .mmap = vvcam_isp_dev_mmap, +}; + +/*On-the-fly debug opitions*/ +char * on_the_fly_str="VIV ISP local debug buffer"; +static void vivdev_dump_buf(unsigned char *out_buf, unsigned char* dump_data, int len, unsigned char * phy_address) +{ + int m; + int n; + char *buf; + buf = out_buf; + int llength = 0x10; + unsigned int udata; + sprintf (buf, "Phy Addr: 0x%lx, Va Addr:0x%lx, len:%d\n", (unsigned long)phy_address, dump_data, len); + buf += strlen(buf); + + for (m=0; m0;n--) + { + if ((*(dump_data+m+1-n)>31) && (*(dump_data+m+1-n)<127)) + { + sprintf (buf, "%c", *(dump_data+m+1-n)); + buf += strlen(buf); + } + else + { + sprintf (buf, "."); + buf += strlen(buf); + } + } + sprintf (buf, "\n"); + buf += strlen(buf); + } + } + sprintf (buf, "\n"); + buf += strlen(buf); +} + +static ssize_t get_vivdev(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const char * name; + char dev_name_perfix[8]; + int dev_index; + int ret; + if(NULL == vvcam_drv_common) + { + pr_info("-->%s Error, null pointer of vvcam_drv_common\n", __func__); + return 0; + } + + mutex_lock(&vvcam_drv_common->vvmutex); + + name = dev_name(dev); + pr_info("-->%s dev_name name:%s\n", __func__, name); + ret = sscanf(name, "%6s%d", dev_name_perfix, &dev_index); + pr_info("-->%s sscanf ret:%d, name:%s, id:%d\n", __func__, ret, dev_name_perfix, dev_index); + + ret = sprintf(buf, "%s\n", vvcam_drv_common->viv_buf); + mutex_unlock(&vvcam_drv_common->vvmutex); + + return ret; +} + +static ssize_t set_vivdev(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + const char * name; + char dev_name_perfix[8]; + int dev_index; + + unsigned int data; + unsigned int addr; + unsigned int read_cnt; + unsigned char mode; + int ret; + + if(NULL == vvcam_drv_common) + { + pr_info("-->%s Error, null pointer of vvcam_drv_common\n", __func__); + return 0; + } + + mutex_lock(&vvcam_drv_common->vvmutex); + + name = dev_name(dev); + pr_info("-->%s dev_name name:%s\n", __func__, name); + ret = sscanf(name, "%6s%d", dev_name_perfix, &dev_index); + pr_info("-->%s sscanf ret:%d, name:%s, id:%d\n", __func__, ret, dev_name_perfix, dev_index); + + ret = sscanf(buf, "%c, 0x%x, 0x%x, 0x%d", &mode, &addr, &data, &read_cnt); + if(ret < 3) + { + sprintf(vvcam_drv_common->viv_buf, "Error input string %s The parameters number:%d, expect format: 'r/w, 0xAddress, 0xData, 0xReadCnt'", + buf, ret); + pr_info("Error input string %s The parameters number:%d, expect format: 'r/w, 0xAddress, 0xData, 0xReadNumber'",buf, ret); + mutex_unlock(&vvcam_drv_common->vvmutex); + return len; + } + + sprintf(vvcam_drv_common->viv_buf, "init: %s, scanf ret:%d, mode:%c, addr:0x%x, data:0x%x, readcnt:0x%x", buf, ret, mode, addr, data, read_cnt); + pr_info("-->%s init: %s, scanf ret:%d, mode:%c, addr:0x%x, data:0x%x, readcnt:0x%x", __func__, buf, ret, mode, addr, data, read_cnt); + + vivdev_dump_buf((unsigned char*)vvcam_drv_common->viv_buf, on_the_fly_str, strlen(on_the_fly_str), 0xaaaa); + + mutex_unlock(&vvcam_drv_common->vvmutex); + + return len; +} + +static DEVICE_ATTR(vivdevio, S_IWUSR|S_IRUSR|S_IRGRP|S_IWGRP|S_IROTH, get_vivdev, set_vivdev); + +static int vvcam_isp_dev_open(struct inode *inode, struct file *file) +{ + + int minor = iminor(inode); + pr_info("-->%s: ISPdev%d opened\n", __func__, minor); + + mutex_lock(&(vvcam_isp_drv + minor)->vvmutex); + + if((vvcam_isp_drv + minor)->open_cnt >= VVISP_OPEN_LIMITATION) + { + pr_info("-->%s: ISPdev%d cannot open device\n", __func__, minor); + mutex_unlock(&(vvcam_isp_drv + minor)->vvmutex); + return -EBUSY; + } + + if((vvcam_isp_drv + minor)->initialized == 0) + { + pr_info("-->%s: ISPdev%d device not initialized\n", __func__, minor); + mutex_unlock(&(vvcam_isp_drv + minor)->vvmutex); + return -EBUSY; + } + + (vvcam_isp_drv + minor)->open_cnt++; + pr_info("-->%s: ISPdev%d update open_cnt to %d\n", __func__, minor, (vvcam_isp_drv + minor)->open_cnt); + try_module_get(THIS_MODULE); + mutex_unlock(&(vvcam_isp_drv + minor)->vvmutex); + + return 0; +} + + +/* Called when a process closes the device file */ +static int vvcam_isp_dev_release(struct inode *inode, struct file *file) +{ + int minor = iminor(inode); + pr_info("-->%s: ISPdev%d releaseing...\n", __func__, minor); + + mutex_lock(&(vvcam_isp_drv + minor)->vvmutex); + + if((vvcam_isp_drv + minor)->open_cnt <= 0) + { + pr_info("-->%s: ISPdev%d internal error\n", __func__, minor); + mutex_unlock(&(vvcam_isp_drv + minor)->vvmutex); + return -EBUSY; + } + + (vvcam_isp_drv + minor)->open_cnt--; + module_put(THIS_MODULE); + + mutex_unlock(&(vvcam_isp_drv + minor)->vvmutex); + + return 0; +} + +static long vvcam_isp_dev_ioctl(struct file * pFile, unsigned int cmd, unsigned long arg) +{ + long ret; + struct inode *inode =pFile->f_mapping->host; + int minor = iminor(inode); + pr_info("-->%s: ISPdev%d Ioctl runs, cmd:%d, args:%ld...\n", __func__, minor, cmd, arg); + + ret = (*(vvnative_ioctl+minor))(vvcam_isp_drv + minor, cmd, arg); + + return ret; +}; + +static int vvcam_isp_dev_mmap(struct file *pFile, struct vm_area_struct *vma) +{ + struct inode *inode =pFile->f_mapping->host; + int minor = iminor(inode); + ulong img_buf_base = vvnative_get_img_buf_base(); + ulong img_buf_size = vvnative_get_img_buf_size(); + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + unsigned long pfn_start = (img_buf_base >> PAGE_SHIFT) + vma->vm_pgoff; + unsigned long size = vma->vm_end - vma->vm_start; + int ret = 0; + + if(size > img_buf_size) + { + size = img_buf_size; + } + pr_info("-->%s: ISPdev%d mmap runs...\n", __func__, minor); + pr_info("-->%s: mmap parameters: phy start:0x%lx, ph size:0x%lx, vm start: 0x%lx, size: 0x%lx, offset, page start: 0x%lx\n", + __func__, img_buf_base, img_buf_size, vma->vm_start, size, offset, pfn_start); + + /* Map reserved image buffer memory. */ + if (remap_pfn_range(vma, vma->vm_start, + (img_buf_base >> PAGE_SHIFT), + size, vma->vm_page_prot)) + { + pr_err("-->%s: remap_pfn_range error!\n", __func__); + pr_info("-->%s: mmap parameters: phy start:0x%lx, ph size:0x%lx, vm start: 0x%lx, size: 0x%lx, offset\n", + __func__, img_buf_base, img_buf_size, vma->vm_start, size, offset); + return -EIO; + } + + return ret; +}; + +static int vvcam_isp_devio_remap(int dev_no) +{ + void __iomem *addr; + ulong reg_base = vvnative_get_reg_base_by_idx(dev_no); + ulong reg_size = vvnative_get_reg_size_by_idx(dev_no); + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: NULL pointer!\n", __func__); + return -1; + } + + (vvcam_isp_drv + dev_no)->phy_address = reg_base; + (vvcam_isp_drv + dev_no)->size = reg_size; + pr_info("ioremap of dev: %d, phy address:0x%lx, size:0x%lx\n", dev_no, reg_base, reg_size); + if((0 == reg_base) ||(0 == reg_size)) + { + (vvcam_isp_drv + dev_no)->base_address = NULL; + pr_info("ioremap of dev: %d, phy address is 0\n", dev_no); + }else{ + addr = ioremap(reg_base, reg_size); + pr_info("ioremap of dev: %d, address:0x%lx\n", dev_no, (unsigned long)addr); + (vvcam_isp_drv + dev_no)->base_address = addr; + } + + return 0; +} + +static int vvcam_isp_devio_unmap(int dev_no) +{ + if((NULL == vvcam_isp_drv)) + { + pr_err("-->%s: NULL pointer!\n", __func__); + return -1; + } + if(NULL != (vvcam_isp_drv + dev_no)->base_address) + { + iounmap((vvcam_isp_drv + dev_no)->base_address); + } + return 0; +} + +/*! +******************************************************************************* +** First function called by the OS. This function registers the device and +** vendor id that this driver handles. +*/ +int __init vvcam_isp_dev_initialize( void ) +{ + int result = 0; + struct device *dev; + dev_t devt; + int retval; + int dev_idx = 0; + struct class *vvisp_class; + + pr_info("-->%s enter\n", __func__); + pr_info("-->%s : %d, registerMemBase = 0x%lx, dev number:%d\n", __func__, __LINE__, VVISP0_BASE, VVCAM_ISP_DEVICES); + + /********************************************************************** + * register/alloc the device major number and range, if + * major = 0, alloc from kernel to get an available device major number + * major != 0, use the specific value as major number, this value may be invalid + **********************************************************************/ + vvcam_isp_drv = kzalloc(sizeof(struct vvcam_isp_dev) * VVCAM_ISP_DEVICES, GFP_KERNEL); + if (!vvcam_isp_drv) + { + return -ENOMEM; + } + + vvcam_drv_common = kzalloc(sizeof(struct vvcam_common), GFP_KERNEL); + if (!vvcam_drv_common) + { + return -ENOMEM; + } + + if (0 == vvcam_isp_dev_major) + { + result = alloc_chrdev_region(&devt, 0, VVCAM_ISP_DEVICES, DRIVER_NAME); + if (result) + { + goto fail_check; + } + vvcam_isp_dev_major = MAJOR(devt); + vvcam_isp_dev_minor = MINOR(devt); + } + else + { + devt = MKDEV(vvcam_isp_dev_major, vvcam_isp_dev_minor); + result = register_chrdev_region(devt, VVCAM_ISP_DEVICES, DRIVER_NAME); + if (result) + { + result = -EBUSY; + goto fail_check; + } + } + + pr_info("--> vvcam ISP init, major id: %d, minor id: %d\n", MAJOR(devt), MINOR(devt)); + + vvisp_class = class_create(THIS_MODULE, DRIVER_NAME); + if (IS_ERR(vvisp_class)) + { + pr_info("-->%s : %d, class_create error!\n", __func__, __LINE__); + goto fail_check; + } + + dev_idx = 0; + for(dev_idx = 0; dev_idx < VVCAM_ISP_DEVICES; dev_idx++) + { + if(strcmp(vvnative_get_dev_name_by_idx(dev_idx), VVNATIVE_NA) == 0) + { + pr_info("--> subisp%d is absent, id number:%s, skip..\n", dev_idx, vvnative_get_dev_name_by_idx(dev_idx) ); + (vvcam_isp_drv + dev_idx)->initialized = 0; + continue; + } + + (vvcam_isp_drv + dev_idx)->devt = MKDEV(vvcam_isp_dev_major, vvcam_isp_dev_minor + dev_idx); + + pr_info("--> subisp%d reg, major id: %d, minor id: %d, dev_name:%s\n", dev_idx, + MAJOR((vvcam_isp_drv + dev_idx)->devt), MINOR((vvcam_isp_drv + dev_idx)->devt), + vvnative_get_dev_name_by_idx(dev_idx)); + + cdev_init(&(vvcam_isp_drv + dev_idx)->cdev, &vvcam_isp_fops); + (vvcam_isp_drv + dev_idx)->cdev.owner = THIS_MODULE; + + retval = cdev_add(&(vvcam_isp_drv + dev_idx)->cdev, (vvcam_isp_drv + dev_idx)->devt, 1); + if (retval) + { + pr_info("-->%s : %d, cdev_add error!\n", __func__, __LINE__); + goto fail_check; + } + + (vvcam_isp_drv + dev_idx)->class = vvisp_class; + + dev = device_create((vvcam_isp_drv + dev_idx)->class, NULL, (vvcam_isp_drv + dev_idx)->devt, + (vvcam_isp_drv + dev_idx), "%s%d", vvnative_get_dev_name_by_idx(dev_idx), vvnative_get_dev_idx(dev_idx)); + if (IS_ERR(dev)) + { + pr_info("-->%s : %d, device_create error!\n", __func__, __LINE__); + class_destroy(vvcam_isp_drv->class); + goto fail_check; + } + pr_info("-->dev create for subisp %s %d done\n", DRIVER_NAME, dev_idx); + (vvcam_isp_drv + dev_idx)->dev = dev; + + + if(sysfs_create_file(&(dev->kobj), &dev_attr_vivdevio.attr)) { + pr_info("-->%s : %d, sysfs_create_file error!\n", __func__, __LINE__); + goto fail_check; + } + + /* init */ + mutex_init(&(vvcam_isp_drv + dev_idx)->vvmutex); + (vvcam_isp_drv + dev_idx)->open_cnt = 0; + (vvcam_isp_drv + dev_idx)->initialized = 1; + (vvcam_isp_drv + dev_idx)->dev_idx = vvnative_get_dev_idx(dev_idx); + + result = vvcam_isp_devio_remap(dev_idx); + if(result) + { + pr_err("-->%s: vvcam_isp_devio_remap error!\n", __func__); + goto fail_check; + } + + /* submodule initialization */ + result = (*(vvnative_init+dev_idx))(vvcam_isp_drv + dev_idx); + if(result) + { + pr_err("-->%s: vvnative_init error with subdev:%d!\n", __func__, dev_idx); + goto fail_check; + } + } + + /* on-the-fly debug init */ + mutex_init(&vvcam_drv_common->vvmutex); + sprintf(vvcam_drv_common->viv_buf, "vivisp_buf"); + return result; + +fail_check: + /* Unregister char driver */ + pr_info("-->vvcam_isp_dev_initialize error\n"); + unregister_chrdev_region(devt, VVCAM_ISP_DEVICES); + return result; +} + +/*! +******************************************************************************* +** Unload the driver module +*/ +void __exit vvcam_isp_dev_cleanup( void ) +{ + int result = 0; + int dev_idx = 0; + + pr_info("-->%s enter\n", __func__); + if(NULL == vvcam_isp_drv) + { + pr_info("-->%s Internal error, NULL pointer\n", __func__); + return; + } + for(dev_idx = 0; dev_idx < VVCAM_ISP_DEVICES; dev_idx++) + { + if(0 == (vvcam_isp_drv + dev_idx)->initialized) + { + continue; + } + + /* submodule un-initialization */ + result = (*(vvnative_deinit+dev_idx))(vvcam_isp_drv + dev_idx); + if(result) + { + pr_err("-->%s: vvnative_deinit error with subdev:%d!\n", __func__, dev_idx); + } + + result = vvcam_isp_devio_unmap(dev_idx); + if(result) + { + pr_err("-->%s: vvcam_isp_devio_unmap error!\n", __func__); + } + + device_destroy((vvcam_isp_drv + dev_idx)->class, (vvcam_isp_drv + dev_idx)->devt); + + cdev_del(&(vvcam_isp_drv + dev_idx)->cdev); + /* remove the char device structure (has been added) */ + + unregister_chrdev_region((vvcam_isp_drv + dev_idx)->devt, VVCAM_ISP_DEVICES); + (vvcam_isp_drv + dev_idx)->dev = NULL; + (vvcam_isp_drv + dev_idx)->open_cnt = 0; + } + + class_destroy(vvcam_isp_drv->class); + vvcam_isp_drv->class = NULL; + + kfree(vvcam_isp_drv); + vvcam_isp_drv = NULL; + kfree(vvcam_drv_common); + vvcam_drv_common = NULL; + + return; +} + +module_init(vvcam_isp_dev_initialize); +module_exit(vvcam_isp_dev_cleanup); + +MODULE_LICENSE ("GPL"); \ No newline at end of file diff --git a/vvcam/common/vvnative.h b/vvcam/common/vvnative.h new file mode 100755 index 0000000..c6fb967 --- /dev/null +++ b/vvcam/common/vvnative.h @@ -0,0 +1,95 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVNATIVE_H_ +#define _VVNATIVE_H_ + +/* #include for kernel space */ +/* #include for user space */ + +#define VVISP_OPEN_LIMITATION 1 +#define VVISP_DBG_BUFFER 4096 + + +#define IOC_MAGIC 'v' +#define IOCINIT _IO(IOC_MAGIC, 0) + +struct vvcam_isp_dev { + struct device *dev; + struct cdev cdev; + dev_t devt; + int dev_idx; + + struct class *class; + int status; + + long phy_address; + long size; + void __iomem *base_address; + int base_range; + + struct mutex vvmutex; + int open_cnt; + int initialized; + void *private_ctx; +}; + +struct vvcam_common{ + struct mutex vvmutex; + char viv_buf[VVISP_DBG_BUFFER]; +}; + + + + + +#endif // _VVNATIVE_H_ \ No newline at end of file diff --git a/vvcam/common/vvnative_cfg.c b/vvcam/common/vvnative_cfg.c new file mode 100755 index 0000000..e470c25 --- /dev/null +++ b/vvcam/common/vvnative_cfg.c @@ -0,0 +1,264 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include /* Module support */ +#include "vvnative_cfg.h" + +char vvcam_driver_name [][8]= +{ + #ifdef WITH_VVISP /* devid 0 */ + VVNATIVE_ISP, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVISP_DUAL /* devid 1 */ + VVNATIVE_ISP, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVCSI /* devid 2 */ + VVNATIVE_CSI, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVCSI_DUAL /* devid 3 */ + VVNATIVE_CSI, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVCAM /* devid 4 */ + VVNATIVE_SENSOR, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVCAM_DUAL /* devid 5 */ + VVNATIVE_SENSOR, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVDWE /* devid 6 */ + VVNATIVE_DWE, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVVSE /* devid 7 */ + VVNATIVE_VSE, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVCTL /* devid 8 */ + VVNATIVE_SOC, + #else + VVNATIVE_NA, + #endif +}; + +char * vvnative_get_dev_name_by_idx(int devidx) +{ + if((devidx > VVCAM_ISP_DEVICES)||(devidx < 0)) + { + return VVNATIVE_NA; + } + return vvcam_driver_name[devidx]; +} + + +/* Parameters that can be set with 'insmod' */ +/* ISP */ +static ulong vvisp0_reg_base = VVISP0_BASE; +module_param(vvisp0_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH ); +MODULE_PARM_DESC(vvisp0_reg_base, "VVISP0 Reg Base address of AHB register"); + +static ulong vvisp1_reg_base = VVISP1_BASE; +module_param(vvisp1_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH ); +MODULE_PARM_DESC(vvisp1_reg_base, "VVISP1 Reg Base address of AHB register"); + +static ulong vvisp_reg_size = VVISP_SIZE; +module_param(vvisp_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvisp_reg_size, "VVISP0/1 Reg address range of AHB register"); + +/* CSI */ +static ulong vvcsi0_reg_base = VVCSI0_BASE; +module_param(vvcsi0_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcsi0_reg_base, "VVCSI0 Reg Base address of AHB register"); + +static ulong vvcsi1_reg_base = VVCSI1_BASE; +module_param(vvcsi1_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcsi1_reg_base, "VVCSI1 Reg Base address of AHB register"); + +static ulong vvcsi_reg_size = VVCSI_SIZE; +module_param(vvcsi_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcsi_reg_size, "VVCSI0/1 Reg address range of AHB register"); + +/* Sensor */ +static ulong vvcam0_reg_base = VVCAM0_BASE; +module_param(vvcam0_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcam0_reg_base, "VVCAM0 Reg Base address of AHB register"); + +static ulong vvcam1_reg_base = VVCAM1_BASE; +module_param(vvcam1_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcam1_reg_base, "VVCAM1 Reg Base address of AHB register"); + +static ulong vvcam_reg_size = VVCAM_SIZE; +module_param(vvcam_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcam_reg_size, "VVCAM0/1 Reg address range of AHB register"); + +/* Dwe */ +static ulong vvdwe_reg_base = VVDWE_BASE; +module_param(vvdwe_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvdwe_reg_base, "VVDWE Reg Base address of AHB register"); + +static ulong vvdwe_reg_size = VVDWE_SIZE; +module_param(vvdwe_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvdwe_reg_size, "VVDWE Reg address range of AHB register"); + +/* Vse */ +static ulong vvvse_reg_base = VVVSE_BASE; +module_param(vvvse_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvvse_reg_base, "VVVSE Reg Base address of AHB register"); + +static ulong vvvse_reg_size = VVVSE_SIZE; +module_param(vvvse_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvvse_reg_size, "VVVSE Reg address range of AHB register"); + +/* Crtl */ +static ulong vvctl_reg_base = VVCTRL_BASE; +module_param(vvctl_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvctl_reg_base, "VVCTRL Reg Base address of AHB register"); + +static ulong vvctl_reg_size = VVCTRL_SIZE; +module_param(vvctl_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvctl_reg_size, "VVCTRL Reg address range of AHB register"); + + +static ulong vvImgBufBase = 0x10000000; +module_param(vvImgBufBase, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvImgBufBase, "Base addrss of memory reserved for ISP"); + +static ulong vvImgBufSize = 0x10000000; +module_param(vvImgBufSize, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvImgBufSize, "Size of memory reserved for ISP"); + + +ulong* reg_base_size_array[] = +{ + &vvisp0_reg_base, /* devid 0 */ + &vvisp_reg_size, + &vvisp1_reg_base, /* devid 1 */ + &vvisp_reg_size, + &vvcsi0_reg_base, /* devid 2 */ + &vvcsi_reg_size, + &vvcsi1_reg_base, /* devid 3 */ + &vvcsi_reg_size, + &vvcam0_reg_base, /* devid 4 */ + &vvcam_reg_size, + &vvcam1_reg_base, /* devid 5 */ + &vvcam_reg_size, + &vvdwe_reg_base, /* devid 6 */ + &vvdwe_reg_size, + &vvvse_reg_base, /* devid 7 */ + &vvvse_reg_size, + &vvctl_reg_base, /* devid 8 */ + &vvctl_reg_size, +}; + +ulong vvnative_get_reg_base_by_idx(int devidx) +{ + if((devidx > VVCAM_ISP_DEVICES)||(devidx < 0)) + { + return 0; + } + return *reg_base_size_array[devidx*2]; +} + +ulong vvnative_get_reg_size_by_idx(int devidx) +{ + if((devidx > VVCAM_ISP_DEVICES)||(devidx < 0)) + { + return 0; + } + return *reg_base_size_array[devidx*2 + 1]; +} + +int reg_dev_idx_array[] = +{ + 0, /* devid 0 isp0*/ + 1, /* devid 1 isp1 */ + 0, /* devid 2 csi0*/ + 1, /* devid 3 csi1*/ + 0, /* devid 4 cam0*/ + 1, /* devid 5 cam1*/ + 0, /* devid 6 dwe0*/ + 0, /* devid 7 vse0*/ + 0, /* devid 8 ctrl0*/ +}; + + +int vvnative_get_dev_idx(int devidx) +{ + if((devidx > VVCAM_ISP_DEVICES)||(devidx < 0)) + { + return -1; + } + return reg_dev_idx_array[devidx]; +} + + +ulong vvnative_get_img_buf_base(void) +{ + return vvImgBufBase; +} + +ulong vvnative_get_img_buf_size(void) +{ + return vvImgBufSize; +} diff --git a/vvcam/common/vvnative_cfg.h b/vvcam/common/vvnative_cfg.h new file mode 100755 index 0000000..b70a2e9 --- /dev/null +++ b/vvcam/common/vvnative_cfg.h @@ -0,0 +1,78 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVNATIVE_CFG_H_ +#define _VVNATIVE_CFG_H_ + + +//#define DRIVER_NAME "" +#define DRIVER_NAME "vivisp" + +#define VVNATIVE_ISP "vivisp" +//#define VVNATIVE_CSI "vivcsi" +#define VVNATIVE_CSI "bm_csi" +#define VVNATIVE_SENSOR "vivcam" +#define VVNATIVE_DWE "vivdwe" +#define VVNATIVE_VSE "vivvse" +#define VVNATIVE_SOC "vivsoc" +#define VVNATIVE_NA "nondev" + +#define VVCAM_ISP_DEVICES (9) + +char * vvnative_get_dev_name_by_idx(int devidx); +ulong vvnative_get_reg_base_by_idx(int devidx); +ulong vvnative_get_reg_size_by_idx(int devidx); +ulong vvnative_get_img_buf_base(void); +ulong vvnative_get_img_buf_size(void); +int vvnative_get_dev_idx(int devidx); + +#endif // _VVNATIVE_CFG_H_ \ No newline at end of file diff --git a/vvcam/common/vvnative_combo.c b/vvcam/common/vvnative_combo.c new file mode 100755 index 0000000..3dd316a --- /dev/null +++ b/vvcam/common/vvnative_combo.c @@ -0,0 +1,509 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include /* Charactor device support */ +#include + +#include "isp_ioctl.h" +#include "sensor_ioctl.h" +#include "csi_ioctl.h" +#include "soc_ioctl.h" +#include "dwe_ioctl.h" +#include "vse_ioctl.h" + + + +#include "vvnative.h" +#include "vvnative_combo.h" + +/* IOCTL combos */ +long vvcam_combo_isp_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct isp_ic_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: NULL pointer input!\n", __func__); + return -1; + } + + mutex_lock(&vvcam_isp_drv->vvmutex); + pr_info("-->%s: Ioctl runs, cmd:%d, args:%px...\n", __func__, cmd, args); + + dev = (struct isp_ic_dev *)vvcam_isp_drv->private_ctx; + ret = isp_priv_ioctl(dev, cmd, args); + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + + +long vvcam_combo_csi_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct vvcam_csi_dev *dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: NULL pointer input!\n", __func__); + return -1; + } + + mutex_lock(&vvcam_isp_drv->vvmutex); + + dev = (struct vvcam_csi_dev *)vvcam_isp_drv->private_ctx; + ret = csi_priv_ioctl(dev, cmd, args); + + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + +#if 0 +static struct i2c_board_info sensor_i2c_info = +{ + I2C_BOARD_INFO("sensor_ov2775", 0x00), +}; + +static void *vvcamGetSensorI2cClient(struct vvcam_isp_dev *vvcam_isp_drv) +{ + struct i2c_adapter *i2c_adap; + static struct i2c_client *i2c_client = NULL; + if (i2c_client == NULL) + { + i2c_adap = i2c_get_adapter(0); + i2c_client = i2c_new_device(i2c_adap, &sensor_i2c_info); + i2c_put_adapter(i2c_adap); + } + + return i2c_client; +} +#endif + +long vvcam_combo_sensor_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct vvcam_sensor_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: NULL pointer input!\n", __func__); + return -1; + } + + mutex_lock(&vvcam_isp_drv->vvmutex); + pr_info("-->%s: Ioctl runs, cmd:%d, args:%px...\n", __func__, cmd, args); + + dev = (struct vvcam_sensor_dev *)vvcam_isp_drv->private_ctx; + ret = sensor_priv_ioctl(dev, cmd, (void __user *)args); + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + +long vvcam_combo_dwe_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct dwe_ic_dev *dev; + + mutex_lock(&vvcam_isp_drv->vvmutex); + pr_info("-->%s: Ioctl runs, cmd:%d, args:%px...\n", __func__, cmd, args); + + dev = (struct dwe_ic_dev *)vvcam_isp_drv->private_ctx; + ret = dwe_priv_ioctl(dev, cmd, args); + + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + +long vvcam_combo_vse_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct vse_ic_dev *dev; + + mutex_lock(&vvcam_isp_drv->vvmutex); + pr_info("-->%s: Ioctl runs, cmd:%d, args:%px...\n", __func__, cmd, args); + + dev = (struct vse_ic_dev *)vvcam_isp_drv->private_ctx; + ret = vse_priv_ioctl(dev, cmd, args); + + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + +long vvcam_combo_soc_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct vvcam_soc_dev *dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: NULL pointer input!\n", __func__); + return -1; + } + + mutex_lock(&vvcam_isp_drv->vvmutex); + + dev = (struct vvcam_soc_dev *)vvcam_isp_drv->private_ctx; + ret = soc_priv_ioctl(dev, cmd, (void __user)args); + + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + +/* Submodule init combos */ +int vvcam_combo_isp_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct isp_ic_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct isp_ic_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct isp_ic_dev *)vvcam_isp_drv->private_ctx; + dev->base = vvcam_isp_drv->base_address; + + dev->reset = NULL; + + return ret; +} + +int vvcam_combo_csi_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_csi_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct vvcam_csi_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct vvcam_csi_dev *)vvcam_isp_drv->private_ctx; + + dev->base = vvcam_isp_drv->base_address; + dev->device_idx = vvcam_isp_drv->dev_idx; + ret = vvnative_csi_init(dev); + if (ret != 0) + { + pr_err("-->%s: vvnative_csi_init error!\n", __func__); + return -1; + } + + return ret; +} + +int vvcam_combo_sensor_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_sensor_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct vvcam_sensor_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct vvcam_sensor_dev *)vvcam_isp_drv->private_ctx; + dev->phy_addr = vvcam_isp_drv->phy_address; + dev->reg_size = vvcam_isp_drv->size; + dev->base = vvcam_isp_drv->base_address; + dev->device_idx = vvcam_isp_drv->dev_idx; + + ret = vvnative_sensor_init(dev); + if (ret != 0) + { + pr_err("-->%s: vvnative_sensor_init error!\n", __func__); + return -1; + } + + return ret; +} + +int vvcam_combo_dwe_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct dwe_ic_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct dwe_ic_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct dwe_ic_dev *)vvcam_isp_drv->private_ctx; + dev->base = vvcam_isp_drv->base_address; + + ret = vvnative_dwe_init(dev); + if (ret != 0) + { + pr_err("-->%s: vvnative_dwe_init error!\n", __func__); + return -1; + } + + return ret; +} + +int vvcam_combo_vse_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vse_ic_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct vse_ic_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct vse_ic_dev *)vvcam_isp_drv->private_ctx; + dev->base = vvcam_isp_drv->base_address; + + ret = vvnative_vse_init(dev); + if (ret != 0) + { + pr_err("-->%s: vvnative_vse_init error!\n", __func__); + return -1; + } + + return ret; +} + +int vvcam_combo_soc_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_soc_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct vvcam_soc_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct vvcam_soc_dev *)vvcam_isp_drv->private_ctx; + dev->base = vvcam_isp_drv->base_address; + vvnative_soc_init(dev); + + return ret; +} + + + +/* Submodule deinit combos */ +int vvcam_combo_isp_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} + +int vvcam_combo_csi_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_csi_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + dev = (struct vvcam_csi_dev *)vvcam_isp_drv->private_ctx; + vvnative_csi_deinit(dev); + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} + +int vvcam_combo_sensor_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_sensor_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + dev = (struct vvcam_sensor_dev *)vvcam_isp_drv->private_ctx; + vvnative_sensor_deinit(dev); + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} + +int vvcam_combo_dwe_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct dwe_ic_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + dev = (struct dwe_ic_dev *)vvcam_isp_drv->private_ctx; + vvnative_dwe_deinit(dev); + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} + +int vvcam_combo_vse_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vse_ic_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + dev = (struct vse_ic_dev *)vvcam_isp_drv->private_ctx; + vvnative_vse_deinit(dev); + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} + +int vvcam_combo_soc_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_soc_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + dev = (struct vvcam_soc_dev *)vvcam_isp_drv->private_ctx; + vvnative_soc_deinit(dev); + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} diff --git a/vvcam/common/vvnative_combo.h b/vvcam/common/vvnative_combo.h new file mode 100755 index 0000000..46c6ef6 --- /dev/null +++ b/vvcam/common/vvnative_combo.h @@ -0,0 +1,78 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVNATIVE_COMBO_H_ +#define _VVNATIVE_COMBO_H_ + +long vvcam_combo_isp_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); +long vvcam_combo_csi_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); +long vvcam_combo_sensor_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); +long vvcam_combo_dwe_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); +long vvcam_combo_vse_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); +long vvcam_combo_soc_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); + +int vvcam_combo_isp_init(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_csi_init(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_sensor_init(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_dwe_init(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_vse_init(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_soc_init(struct vvcam_isp_dev *vvcam_isp_drv); + +int vvcam_combo_isp_deinit(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_csi_deinit(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_sensor_deinit(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_dwe_deinit(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_vse_deinit(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_soc_deinit(struct vvcam_isp_dev *vvcam_isp_drv); + +#endif + diff --git a/vvcam/common/vvsensor.h b/vvcam/common/vvsensor.h new file mode 100755 index 0000000..2bc6e17 --- /dev/null +++ b/vvcam/common/vvsensor.h @@ -0,0 +1,265 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVSENSOR_PUBLIC_HEADER_H_ +#define _VVSENSOR_PUBLIC_HEADER_H_ + +#ifndef __KERNEL__ +#include +#else +#include +#endif + +#define VVCAM_SUPPORT_MAX_MODE_COUNT 20 +#define VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS 8 + +enum { + VVSENSORIOC_RESET = 0x100, + VVSENSORIOC_S_CLK, + VVSENSORIOC_G_CLK, + VVSENSORIOC_S_POWER, + VVSENSORIOC_G_POWER, + VVSENSORIOC_SENSOR_SCCB_CFG, + VVSENSORIOC_FOCUS_SCCB_CFG, + VVSENSORIOC_READ_REG, + VVSENSORIOC_WRITE_REG, + VVSENSORIOC_READ_ARRAY, + VVSENSORIOC_WRITE_ARRAY, + VVSENSORIOC_AF_READ_REG, + VVSENSORIOC_AF_WRITE_REG, + VVSENSORIOC_G_MIPI, + VVSENSORIOC_G_NAME, + VVSENSORIOC_G_RESERVE_ID, + VVSENSORIOC_G_CHIP_ID, + VVSENSORIOC_S_INIT, + VVSENSORIOC_S_STREAM, + VVSENSORIOC_S_LONG_EXP, + VVSENSORIOC_S_EXP, + VVSENSORIOC_S_VSEXP, + VVSENSORIOC_S_LONG_GAIN, + VVSENSORIOC_S_GAIN, + VVSENSORIOC_S_VSGAIN, + VVSENSORIOC_S_FRAMESIZE, + VVSENSORIOC_ENUM_FRAMESIZES, + VVSENSORIOC_S_HDR_MODE, + VVSENSORIOC_G_HDR_MODE, + VVSENSORIOC_S_FPS, + VVSENSORIOC_G_FPS, + VVSENSORIOC_S_HDR_RADIO, + VVSENSORIOC_G_AE_INFO, + VVSENSORIOC_QUERY, + VVSENSORIOC_G_SENSOR_MODE, + VVSENSORIOC_S_WB, + VVSENSORIOC_S_BLC, + VVSENSORIOC_G_EXPAND_CURVE, + VVSENSORIOC_S_SENSOR_MODE, + VVSENSORIOC_MAX, +}; + +/* W/R registers */ +struct vvcam_sccb_data { + uint32_t addr; + uint32_t data; +}; + +/* init settings */ +struct vvsensor_reg_value_t { + uint16_t addr; + uint8_t val; + uint8_t mask; + uint32_t delay; +}; + +/* priv ioctl */ +struct vvsensor_gain_context { + uint32_t again; + uint32_t dgain; +}; + +/* vsi native usage */ +struct vvcam_sccb_cfg_s { + uint8_t slave_addr; + uint8_t addr_byte; + uint8_t data_byte; +}; + +struct vvcam_sccb_array { + uint32_t count; + struct vvcam_sccb_data *sccb_data; +}; + +typedef struct vvcam_ae_info_s { + uint32_t DefaultFrameLengthLines; + uint32_t CurFrameLengthLines; + uint32_t one_line_exp_time_ns; + uint32_t max_integration_time; + uint32_t min_integration_time; + uint32_t integration_accuracy; + uint32_t max_gain; + uint32_t min_gain; + uint32_t gain_accuracy; + uint32_t cur_fps; + uint32_t hdr_radio; +} vvcam_ae_info_t; + +struct sensor_mipi_info { + uint32_t mipi_lane; + uint32_t sensor_data_bit; +}; + +enum sensor_hdr_mode_e +{ + SENSOR_MODE_LINEAR , + SENSOR_MODE_HDR_STITCH, + SENSOR_MODE_HDR_NATIVE, +}; + +enum SENSOR_BAYER_PATTERN_E +{ + BAYER_RGGB = 0, + BAYER_GRBG = 1, + BAYER_GBRG = 2, + BAYER_BGGR = 3, + BAYER_BUTT +}; + +enum sensor_stitching_mode_e +{ + SENSOR_STITCHING_DUAL_DCG = 0, /**< dual DCG mode 3x12-bit */ + SENSOR_STITCHING_3DOL = 1, /**< dol3 frame 3x12-bit */ + SENSOR_STITCHING_LINEBYLINE = 2, /**< 3x12-bit line by line without waiting */ + SENSOR_STITCHING_16BIT_COMPRESS = 3, /**< 16-bit compressed data + 12-bit RAW */ + SENSOR_STITCHING_DUAL_DCG_NOWAIT = 4, /**< 2x12-bit dual DCG without waiting */ + SENSOR_STITCHING_2DOL = 5, /**< dol2 frame or 1 CG+VS sx12-bit RAW */ + SENSOR_STITCHING_L_AND_S = 6, /**< L+S 2x12-bit RAW */ + SENSOR_STITCHING_MAX + +}; + +typedef struct sensor_expand_curve_s +{ + uint32_t x_bit; + uint32_t y_bit; + uint8_t expand_px[64]; + uint32_t expand_x_data[65]; + uint32_t expand_y_data[65]; +}sensor_expand_curve_t; + +typedef struct sensor_data_compress_s +{ + uint32_t enable; + uint32_t x_bit; + uint32_t y_bit; +}sensor_data_compress_t; + + +typedef struct vvcam_mode_info { + uint32_t index; + uint32_t width; + uint32_t height; + uint32_t fps; + uint32_t hdr_mode; + uint32_t stitching_mode; + uint32_t bit_width; + sensor_data_compress_t data_compress; + uint32_t bayer_pattern; + vvcam_ae_info_t ae_info; + void *preg_data; + uint32_t reg_data_count; + uint32_t mipi_phy_freq; + uint32_t mipi_line_num; +} vvcam_mode_info_t; + +typedef struct sensor_blc_s +{ + uint32_t red; + uint32_t gr; + uint32_t gb; + uint32_t blue; +}sensor_blc_t; + +typedef struct sensor_white_balance_s +{ + uint32_t r_gain; + uint32_t gr_gain; + uint32_t gb_gain; + uint32_t b_gain; +}sensor_white_balance_t; + +typedef struct vvcam_mode_info_array { + uint32_t count; + struct vvcam_mode_info modes[VVCAM_SUPPORT_MAX_MODE_COUNT]; +} vvcam_mode_info_array_t; + + +#ifdef SENSOR_CROP +/************************************** +*Reserved for sensor crop +***************************************/ +typedef struct sensor_crop_regions_s +{ + uint32_t offs_x; + uint32_t offs_y; + uint32_t width; + uint32_t height; +}sensor_crop_regions_t; + +typedef struct sensor_crop_limits_s +{ + uint32_t mode_index; + sensor_crop_regions_t max_regions; + sensor_crop_regions_t min_regions; +}sensor_crop_limits_t; +#endif + +#endif + diff --git a/vvcam/csi/csi_ioctl.c b/vvcam/csi/csi_ioctl.c new file mode 100755 index 0000000..21d0365 --- /dev/null +++ b/vvcam/csi/csi_ioctl.c @@ -0,0 +1,204 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef __KERNEL__ +#include +#include +#include +#include + +#define pr_info printf +#define pr_err printf +#define copy_from_user(a, b, c) csi_copy_data(a, b, c) +#define copy_to_user(a, b, c) csi_copy_data(a, b, c) +#define __user +#define __iomem + +void csi_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); +} + +#else // __KERNEL__ +#include /* Module support */ +#include + +#endif + +#include "csi_ioctl.h" +#include "vivcsi_hub.h" + + +long csi_priv_ioctl(struct vvcam_csi_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + if (!dev) { + return ret; + } + + switch (cmd) { + case VVCSI_IOC_S_RESET: + ret = vivcsi_hub_reset(dev); + break; + + case VVCSI_IOC_S_POWER: + copy_from_user(&dev->power_status, args, sizeof(dev->power_status)); + ret = vivcsi_hub_set_power(dev); + break; + + case VVCSI_IOC_G_POWER: + ret = vivcsi_hub_get_power(dev); + copy_to_user(args, &dev->power_status, sizeof(dev->power_status)); + break; + + case VVCSI_IOC_S_CLOCK: + copy_from_user(&dev->clock, args, sizeof(dev->clock)); + ret = vivcsi_hub_set_clock(dev); + break; + + case VVCSI_IOC_G_CLOCK: + ret = vivcsi_hub_get_clock(dev); + copy_to_user(args, &dev->clock, sizeof(dev->clock)); + ret = 0; + break; + + case VVCSI_IOC_S_STREAM: + copy_from_user(&dev->streaming_enable, args, sizeof(dev->streaming_enable)); + ret = vivcsi_hub_set_stream_control(dev); + break; + + case VVCSI_IOC_G_STREAM: + ret = vivcsi_hub_get_stream_control(dev); + copy_to_user(args, &dev->streaming_enable, sizeof(dev->streaming_enable)); + break; + + case VVCSI_IOC_S_FMT: + copy_from_user(&dev->csi_format, args, sizeof(dev->csi_format)); + ret = vivcsi_hub_set_fmt(dev); + break; + + case VVCSI_IOC_G_FMT: + ret = vivcsi_hub_get_fmt(dev); + copy_to_user(args, &dev->csi_format, sizeof(dev->csi_format)); + break; + + case VVCSI_IOC_S_VC_SELECT: + copy_from_user(&dev->csi_vc_select, args, sizeof(dev->csi_vc_select)); + ret = vivcsi_hub_set_vc_select(dev); + break; + + case VVCSI_IOC_G_VC_SELECT: + ret = vivcsi_hub_get_vc_select(dev); + copy_to_user(args, &dev->csi_vc_select, sizeof(dev->csi_vc_select)); + break; + case VVCSI_IOC_S_LANE_CFG: + copy_from_user(&dev->csi_lane_cfg, args, sizeof(dev->csi_lane_cfg)); + ret = vivcsi_hub_set_csi_lane_cfg(dev); + break; + default: + pr_err("unsupported command %d", cmd); + break; + } + + return ret; +} + +extern struct vvcam_csi_hardware_function_s nwl_mipi_function; + +int vvnative_csi_init(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if (dev == NULL) + { + pr_err("[%s] dev is NULL\n", __func__); + return -1; + } + + vvcsi_register_hardware(dev,&nwl_mipi_function); + if (dev->csi_hard_func.init) + { + ret = dev->csi_hard_func.init(dev); + if (ret < 0) + { + pr_err("[%s] init failed\n", __func__); + return -1; + } + } + return 0; +} + +int vvnative_csi_deinit(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if (dev == NULL) + { + pr_err("[%s] dev is NULL\n", __func__); + return -1; + } + + if (dev->csi_hard_func.exit) + { + ret = dev->csi_hard_func.exit(dev); + if (ret < 0) + { + pr_err("[%s] exit failed\n", __func__); + return -1; + } + } + + return 0; +} + + diff --git a/vvcam/csi/csi_ioctl.h b/vvcam/csi/csi_ioctl.h new file mode 100755 index 0000000..1bc84bd --- /dev/null +++ b/vvcam/csi/csi_ioctl.h @@ -0,0 +1,154 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _CSI_IOC_H_ +#define _CSI_IOC_H_ + +#ifndef __KERNEL__ +#include +#endif +#include + +enum { + VVCSI_IOC_S_RESET = _IO('r', 0), + VVCSI_IOC_S_POWER, + VVCSI_IOC_G_POWER, + VVCSI_IOC_S_CLOCK, + VVCSI_IOC_G_CLOCK, + VVCSI_IOC_S_STREAM, + VVCSI_IOC_G_STREAM, + VVCSI_IOC_S_FMT, + VVCSI_IOC_G_FMT, + VVCSI_IOC_S_VC_SELECT, + VVCSI_IOC_G_VC_SELECT, + VVCSI_IOC_S_LANE_CFG, + VVCSI_IOC_S_BIT_SHIFT, + VVCSI_IOC_MAX, +}; + +struct csi_vc_select_context { + uint32_t csi_vc_select_mode; + uint32_t vc_channel; +}; + +struct csi_format_context { + uint32_t format; + uint32_t width; + uint32_t height; +}; + +struct vvcam_csi_hardware_function_s +{ + int (*init)(void* dev); + int (*exit)(void* dev); + int (*reset)(void* dev); + int (*set_power)(void* dev); + int (*get_power)(void* dev); + int (*set_clock)(void* dev); + int (*get_clock)(void* dev); + int (*set_stream_control)(void* dev); + int (*get_stream_control)(void* dev); + int (*set_fmt)(void* dev); + int (*get_fmt)(void* dev); + int (*set_vc_select)(void* dev); + int (*get_vc_select)(void* dev); + int (*set_lane_cfg)(void* dev); +}; + +struct vvcam_csi_lane_cfg +{ + uint32_t mipi_lane_num; +}; + +struct vvcam_csi_access_s +{ + int (*write)(void * ctx, uint32_t address, uint32_t data); + int (*read)(void * ctx, uint32_t address, uint32_t *data); +}; + + +#ifdef __KERNEL__ + +struct vvcam_csi_dev { + void __iomem *base; + char name[16]; + + int present; + int device_idx; + + uint32_t power_status; + uint32_t clock; + + uint32_t streaming_enable; + struct csi_vc_select_context csi_vc_select; + struct csi_format_context csi_format; + struct vvcam_csi_hardware_function_s csi_hard_func; + struct vvcam_csi_access_s csi_access; + struct vvcam_csi_lane_cfg csi_lane_cfg; + void * csi_private; +}; + +// internal functions + +long csi_priv_ioctl(struct vvcam_csi_dev *dev, unsigned int cmd, void *args); +int vvnative_csi_init(struct vvcam_csi_dev *dev); +int vvnative_csi_deinit(struct vvcam_csi_dev *dev); + + + +#else +//User space connections + + +#endif + +#endif // _CSI_IOC_H_ diff --git a/vvcam/csi/nwl/nwl_core.c b/vvcam/csi/nwl/nwl_core.c new file mode 100755 index 0000000..feecbb0 --- /dev/null +++ b/vvcam/csi/nwl/nwl_core.c @@ -0,0 +1,322 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#ifdef ISP8000L_V2008 +#include //Fix thead compile error. +#endif + +#include "nwl_regs.h" +#include "../csi_ioctl.h" + + +int nwl_register_write(void * dev,unsigned int addr, unsigned int data) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + writel(data, base_addr + addr); + + return 0; +} + +int nwl_register_read(void * dev,unsigned int addr, unsigned int *data) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + *data = readl(base_addr + addr); + + return 0; +} + + +static int nwl_init(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + nwl_csi_dev->csi_access.write = nwl_register_write; + nwl_csi_dev->csi_access.read = nwl_register_read; + + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_NUM_LANES, 0x4); + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_LANES_CLK, 0x1); + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_LANES_DATA, 0xF); + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_IGNORE_VC, 0x1); + + if (nwl_csi_dev->device_idx == 0) + { + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI0_CTRL, 0x4); + }else + { + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI1_CTRL, 0x4); + } + + return 0; +} + +static int nwl_exit(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_reset(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_power(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_get_power(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_clock(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_get_clock(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_stream_control(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + u32 clock_status; + u32 data_status; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + if (nwl_csi_dev->streaming_enable) + { + clock_status = 0x01; + data_status = 0xFF; + } + else + { + clock_status = 0x00; + data_status = 0x00; + } + + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_LANES_CLK, clock_status); + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_LANES_DATA, data_status); + return 0; +} + +static int nwl_get_stream_control(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_fmt(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_get_fmt(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_vc_select(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_get_vc_select(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_lane_cfg(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_NUM_LANES, nwl_csi_dev->csi_lane_cfg.mipi_lane_num); + + return 0; +} + +struct vvcam_csi_hardware_function_s nwl_mipi_function = +{ + .init = nwl_init, + .exit = nwl_exit, + .reset = nwl_reset, + .set_power = nwl_set_power, + .get_power = nwl_get_power, + .set_clock = nwl_set_clock, + .get_clock = nwl_get_clock, + .set_stream_control = nwl_set_stream_control, + .get_stream_control = nwl_get_stream_control, + .set_fmt = nwl_set_fmt, + .get_fmt = nwl_get_fmt, + .set_vc_select = nwl_set_vc_select, + .get_vc_select = nwl_get_vc_select, + .set_lane_cfg = nwl_set_lane_cfg, +}; + + diff --git a/vvcam/csi/nwl/nwl_ioctl.c b/vvcam/csi/nwl/nwl_ioctl.c new file mode 100755 index 0000000..00db1e4 --- /dev/null +++ b/vvcam/csi/nwl/nwl_ioctl.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include "nwl_driver.h" +#endif +#include "nwl_ioctl.h" +#include "nwl_regs.h" + +#ifndef __KERNEL__ +#include +#include "common_dev.h" + +#define NWL_EXTREG_OFFSET 0x308244 +#define NWL_REG_OFFSET 0x300000 + +static HalHandle_t hal_handle; +void nwl_ic_set_hal(HalHandle_t hal) +{ + hal_handle = hal; +} + +void nwl_write_reg(u32 offset, u32 val) +{ + offset += NWL_REG_OFFSET; + HalWriteReg(hal_handle, offset, val); +} + +u32 nwl_read_reg(u32 offset) +{ + offset += NWL_REG_OFFSET; + return HalReadReg(hal_handle, offset); +} + +u32 nwl_write_extreg(u32 offset, u32 val) +{ + offset += NWL_EXTREG_OFFSET; + return HalReadReg(hal_handle, offset); +} + +int nwl_set_stream(void *dev, int enable) +{ + u32 clock_status; + u32 data_status; + + nwl_write_reg(MRV_MIPICSI1_NUM_LANES, 0x4); + + if (enable == true) { + clock_status = 0x1; + data_status = 0xFF; + } else { + clock_status = 0x0; + data_status = 0x0; + } + nwl_write_reg(MRV_MIPICSI1_LANES_CLK, clock_status); + nwl_write_reg(MRV_MIPICSI1_LANES_DATA, data_status); + + return 0; +} + +int nwl_init(void) +{ + nwl_write_reg(MRV_MIPICSI1_NUM_LANES, 0x4); + nwl_write_reg(MRV_MIPICSI1_LANES_CLK, 0x1); + nwl_write_reg(MRV_MIPICSI1_LANES_DATA, 0xF); + nwl_write_reg(MRV_MIPICSI1_IGNORE_VC, 0x1); + nwl_write_extreg(MRV_MIPICSI1_OUT_SHIFT, 0x4); + + return 0; +} +#endif + +int nwl_ioc_init(void) +{ + nwl_init(); + + return 0; +} + +int nwl_ioc_s_stream(void *dev, void *__user args) +{ + int enable; + + copy_from_user(&enable, args, sizeof(enable)); + nwl_set_stream(dev, enable); + return 0; +} + +long nwl_priv_ioctl(void *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + switch (cmd) { + case CSIIOC_INIT: + ret = nwl_ioc_init(); + break; + case CSIIOC_S_STREAM:{ + ret = nwl_ioc_s_stream(dev, args); + } + break; + default: + pr_err("Unsupported csi command %d.\n", cmd); + break; + } + + return ret; +} diff --git a/vvcam/csi/nwl/nwl_ioctl.h b/vvcam/csi/nwl/nwl_ioctl.h new file mode 100755 index 0000000..a561015 --- /dev/null +++ b/vvcam/csi/nwl/nwl_ioctl.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _NWL_IOC_H_ +#define _NWL_IOC_H_ + +enum { + CSIIOC_INIT = 0, + CSIIOC_S_STREAM, +}; + +long nwl_priv_ioctl(void *dev, unsigned int cmd, void *args); + +#endif /* _NWL_IOC_H_ */ diff --git a/vvcam/csi/nwl/nwl_regs.h b/vvcam/csi/nwl/nwl_regs.h new file mode 100755 index 0000000..6ba7749 --- /dev/null +++ b/vvcam/csi/nwl/nwl_regs.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _NWL_REGS_H_ +#define _NWL_REGS_H_ + +/* + * MRV_MIPICSI1_NUM_LANES + * Config num lanes register [3:0] rw + * 0000b - controller off + * 0001b - 1 Lane + * 0010b - 2 Lanes + * 0011b - 3 Lanes + * 0100b - 4 Lanes + */ +#define MRV_MIPICSI_NUM_LANES 0x0 + +/* + * MRV_MIPICSI1_LANES_CLK + * Configure lanes clock [0] + * 0b - disable + * 1b - enable + */ +#define MRV_MIPICSI_LANES_CLK 0x4 + +/* + * MRV_MIPICSI1_LANES_DATA + * enable/disable lanes data [7:0] + * setting bits to a '1' value enable data lane + */ +#define MRV_MIPICSI_LANES_DATA 0x8 + +/* + * MRV_MIPICSI1_IGNORE_VC + * enable/disable lanes clock [0] + * setting bits to a '1' value enable data value + */ +#define MRV_MIPICSI_IGNORE_VC 0x80 + +/* + * MRV_MIPICSI1_OUT_SHIFT + * Configure csi_vid_out register + */ + +#define MRV_MIPICSI0_CTRL 0x108240 //0x308240 +#define MRV_MIPICSI1_CTRL 0x8244 //0x308244 + +#endif /* _NWL_REGS_H_ */ diff --git a/vvcam/csi/vivcsi_hub.c b/vvcam/csi/vivcsi_hub.c new file mode 100755 index 0000000..467fb41 --- /dev/null +++ b/vvcam/csi/vivcsi_hub.c @@ -0,0 +1,335 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include "csi_ioctl.h" +#include "vivcsi_hub.h" + +unsigned int vvcsi_register_hardware(struct vvcam_csi_dev *dev, struct vvcam_csi_hardware_function_s *func) +{ + int ret = 0; + if (func == NULL) + { + return -1; + } + + memcpy(&dev->csi_hard_func,func,sizeof(struct vvcam_csi_hardware_function_s)); + return 0; +} + +int vivcsi_hub_init(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.init == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.init(dev); + + return ret; +} + + +int vivcsi_hub_reset(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.reset == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.reset(dev); + + return ret; +} + + +int vivcsi_hub_set_power(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_power == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_power(dev); + + return ret; +} + +int vivcsi_hub_get_power(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.get_power == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.get_power(dev); + + return ret; +} + +int vivcsi_hub_set_clock(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_clock == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_clock(dev); + + return ret; +} + +int vivcsi_hub_get_clock(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.get_clock == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.get_clock(dev); + + return ret; +} + + +int vivcsi_hub_set_stream_control(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_stream_control == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_stream_control(dev); + + return ret; +} + +int vivcsi_hub_get_stream_control(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.get_stream_control == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.get_stream_control(dev); + + return ret; +} + +int vivcsi_hub_set_fmt(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_fmt == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_fmt(dev); + + return ret; +} + +int vivcsi_hub_get_fmt(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.get_fmt == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.get_fmt(dev); + + return ret; +} + +int vivcsi_hub_set_vc_select(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_vc_select == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_vc_select(dev); + + return ret; +} + + +int vivcsi_hub_get_vc_select(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.get_vc_select == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.get_vc_select(dev); + + return ret; +} + +int vivcsi_hub_set_csi_lane_cfg(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_lane_cfg == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_lane_cfg(dev); + + return ret; + +} + diff --git a/vvcam/csi/vivcsi_hub.h b/vvcam/csi/vivcsi_hub.h new file mode 100755 index 0000000..6f9368e --- /dev/null +++ b/vvcam/csi/vivcsi_hub.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VIVCSI_HUB_H_ +#define _VIVCSI_HUB_H_ + +unsigned int vvcsi_register_hardware(struct vvcam_csi_dev *dev, struct vvcam_csi_hardware_function_s *func); + +int vivcsi_hub_init(struct vvcam_csi_dev *dev); +int vivcsi_hub_reset(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_power(struct vvcam_csi_dev *dev); +int vivcsi_hub_get_power(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_clock(struct vvcam_csi_dev *dev); +int vivcsi_hub_get_clock(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_stream_control(struct vvcam_csi_dev *dev); +int vivcsi_hub_get_stream_control(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_fmt(struct vvcam_csi_dev *dev); +int vivcsi_hub_get_fmt(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_vc_select(struct vvcam_csi_dev *dev); +int vivcsi_hub_get_vc_select(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_csi_lane_cfg(struct vvcam_csi_dev *dev); + +#endif /* _VIVCSI_HUB_H_ */ diff --git a/vvcam/dw200/dw200_ioctl.c b/vvcam/dw200/dw200_ioctl.c new file mode 100644 index 0000000..763c52c --- /dev/null +++ b/vvcam/dw200/dw200_ioctl.c @@ -0,0 +1,1127 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +//#include "dw200_driver.h" +#else +#include +#include +#include +#endif + +#include "dw200_ioctl.h" +#include "dwe_regs.h" +#include "vse_regs.h" +#undef ALIGN_UP +#define ALIGN_UP(x, align) (((x) + ((align) - 1)) & ~((align)-1)) + +#ifdef __KERNEL__ +#define dw_info(...) +#else +#define dw_info(...) +#endif + +#ifndef __KERNEL__ +#ifdef HAL_CMODEL +#define DEWARP_REGISTER_OFFSET 0xc00 +#else +#define DEWARP_REGISTER_OFFSET 0x380000 +#endif + +#define DEWARP_REGISTER_CTL 0x308250 + +pReadBar g_dw200_read_func; +pWriteBar g_dw200_write_func; + +void dwe_set_func(pReadBar read_func, pWriteBar write_func) +{ + g_dw200_read_func = read_func; + g_dw200_write_func = write_func; +} + + +void dwe_write_reg(struct dw200_subdev *dev, u32 offset, u32 val) +{ + g_dw200_write_func(DEWARP_REGISTER_OFFSET + offset, val); +} + +u32 dwe_read_reg(struct dw200_subdev *dev, u32 offset) +{ + u32 data; + g_dw200_read_func(DEWARP_REGISTER_OFFSET + offset, &data); + return data; +} + +long dw200_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); + return 0; +} + +void vse_set_func(pVseReadBar read_func, pVseWriteBar write_func) +{ + g_dw200_read_func = read_func; + g_dw200_write_func = write_func; +} + +void vse_write_reg(struct dw200_subdev *dev, u32 offset, u32 val) +{ + g_dw200_write_func(offset, val); +} + +u32 vse_read_reg(struct dw200_subdev *dev, u32 offset) +{ + u32 data; + g_dw200_read_func(offset, &data); + return data; +} +#else + +void dwe_write_reg(struct dw200_subdev *dev, u32 offset, u32 val) +{ + //dw_info("dwe write addr 0x%08x val 0x%08x\n",offset,val); + __raw_writel(val, dev->dwe_base + offset); +} + +u32 dwe_read_reg(struct dw200_subdev *dev, u32 offset) +{ + u32 val; + val=__raw_readl(dev->dwe_base + offset); + dw_info("dwe read addr 0x%08x val 0x%08x\n",offset,val); + return val; +} + +void vse_write_reg(struct dw200_subdev *dev, u32 offset, u32 val) +{ + //dw_info("vse write addr 0x%08x val 0x%08x\n",offset,val); + __raw_writel(val, dev->vse_base + offset); +} + +u32 vse_read_reg(struct dw200_subdev *dev, u32 offset) +{ + u32 val; + return __raw_readl(dev->vse_base + offset); + dw_info("vse read addr 0x%08x val 0x%08x\n",offset,val); + return val; +} + +#endif + +int dwe_reset(struct dw200_subdev *dev) +{ + dw_info("enter %s\n", __func__); +#ifdef DWE_REG_RESET + __raw_writel(0, dev->dwe_reset); + __raw_writel(1, dev->dwe_reset); +#endif + dwe_write_reg(dev, DEWARP_CTRL, 0x0c); + return 0; +} + +int dwe_s_params(struct dw200_subdev *dev) +{ + struct dwe_hw_info *info = &dev->dwe_info; + u32 reg = 0; + u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16); + u32 vUp = (info->split_v1 & ~0x0F) | 0x0C; + u32 vDown = (info->split_v2 & ~0x0F) | 0x0C; + u32 hLine = (info->split_h & ~0x0F) | 0x0C; + u32 dst_img_width_bn; + + if(info->out_yuvbit) + dst_img_width_bn = info->dst_w * 2; + else{ + if(info->out_format == MEDIA_PIX_FMT_YUV422I) + dst_img_width_bn = info->dst_w * 2; + else + dst_img_width_bn = info->dst_w; + } + + dw_info("enter %s\n", __func__); + + dwe_write_reg(dev, MAP_LUT_SIZE, + ((info->map_w & 0x7ff) | ((info->map_h & 0x7ff) << 16))); + dwe_write_reg(dev, SRC_IMG_SIZE, + ((info->src_w & 0x1fff) | + ((info->src_h & 0x1fff) << 16))); + dwe_write_reg(dev, SRC_IMG_STRIDE, info->src_stride); + + dwe_write_reg(dev, DST_IMG_SIZE, + ((info->dst_w & 0x1FFF) | + ((info->dst_h & 0x1FFF) << 16))); + + dwe_write_reg(dev, DST_IMG_WIDTH_BN, + ((dst_img_width_bn & 0x7FFF) | + ((dst_img_width_bn & 0x7FFF) << 16))); + dwe_write_reg(dev, DST_IMG_STRIDE, info->dst_stride); + dwe_write_reg(dev, DST_IMG_Y_SIZE1, reg_y_rbuff_size >> 4); + dwe_write_reg(dev, DST_IMG_UV_SIZE1, info->dst_size_uv >> 4); + dwe_write_reg(dev, VERTICAL_SPLIT_LINE, + (vUp & 0x1fff) | ((vDown & 0x1fff) << 16)); + dwe_write_reg(dev, HORIZON_SPLIT_LINE, (hLine & 0x1fff)); + + reg = 0x4c808009; + reg |= ((info->split_line & 0x1) << 11); + reg |= ((info->in_format & 0x3) << 4); + reg |= ((info->out_format & 0x3) << 6); + reg |= ((info->in_yuvbit & 0x1) << 12); + reg |= ((info->out_yuvbit & 0x1) << 13); + reg |= + ((info->src_auto_shadow & 0x1) << 8) | + ((info->dst_auto_shadow & 0x1) << 10); + reg |= ((info->hand_shake & 0x1) << 9); + dwe_write_reg(dev, DEWARP_CTRL, reg); + + dwe_write_reg(dev, BOUNDRY_PIXEL, + (((info->boundary_y & 0xff) << 16) | + ((info->boundary_u & 0xff) + << 8) | (info->boundary_v & 0xff))); + dwe_write_reg(dev, SCALE_FACTOR, info->scale_factor); + dwe_write_reg(dev, ROI_START, + ((info->roi_x & 0x1fff) | + ((info->roi_y & 0x1fff) << 16))); + return 0; +} + +int dwe_enable_bus(struct dw200_subdev *dev, bool enable) +{ + u32 reg = dwe_read_reg(dev, BUS_CTRL); + + dw_info("enter %s\n", __func__); + + if (enable) { + reg |= DEWRAP_BUS_CTRL_ENABLE_MASK; + reg |= DEWRAP_BUS_CTRL_WR_ID_ENABLE_MASK; + reg |= DEWRAP_BUS_CTRL_RD_ID_ENABLE_MASK; + reg &= ~(0xff << DEWRAP_BUS_CTRL_RD_ID_SHIFT); + reg &= ~(0xff << DEWRAP_BUS_CTRL_WR_ID_SHIFT); + reg |= (0x0 << DEWRAP_BUS_CTRL_RD_ID_SHIFT); //set read id as 1 + reg |= (0x0 << DEWRAP_BUS_CTRL_WR_ID_SHIFT); //set write id as 2 + dwe_write_reg(dev, BUS_CTRL, reg); + } else { + reg &= ~DEWRAP_BUS_CTRL_ENABLE_MASK; + reg &= ~DEWRAP_BUS_CTRL_WR_ID_ENABLE_MASK; + reg &= ~DEWRAP_BUS_CTRL_RD_ID_ENABLE_MASK; + reg &= ~(0xff << DEWRAP_BUS_CTRL_RD_ID_SHIFT); + reg &= ~(0xff << DEWRAP_BUS_CTRL_WR_ID_SHIFT); + dwe_write_reg(dev, BUS_CTRL, reg); + } + + return 0; +} + +int dwe_disable_irq(struct dw200_subdev *dev) +{ + dw_info("enter %s\n", __func__); + dwe_write_reg(dev, INTERRUPT_STATUS, INT_RESET_MASK|INT_CLR_MASK); + return 0; +} + +int dwe_clear_irq(struct dw200_subdev *dev, u32 mis) +{ + u32 interrupt_status; + + dw_info("enter %s\n", __func__); + interrupt_status = dwe_read_reg(dev, INTERRUPT_STATUS); + + dwe_write_reg(dev, INTERRUPT_STATUS, mis|interrupt_status);// INT_CLR_MASK); + // dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl | 2); + // dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl); + return 0; +} +int dwe_clear_irq_1(struct dw200_subdev *dev) +{ + u32 reg_dewarp_ctrl; + + dw_info("enter %s\n", __func__); + reg_dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL); + dwe_write_reg(dev, INTERRUPT_STATUS, INT_CLR_MASK); + dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl | 2); + dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl); + return 0; +} +int dwe_read_irq(struct dw200_subdev *dev, u32 * ret) +{ + u32 irq = 0; + + irq = dwe_read_reg(dev, INTERRUPT_STATUS); + *ret = irq; + + return 0; +} + +int dwe_dequeue_irq(struct dw200_subdev *dev, u32 * ret) +{ + vivdw200_mis_t data; + + if (dev == NULL || ret == NULL) { + dw_info("wrong input parameter.\n"); + return -1; + } + if(0 ==vivdw200_read_circle_queue(&data, &dev->dwe_circle_list)){ + *ret = data.val; + } else { + //pr_err("failed to dequeue dwe mis.\n"); + *ret = 0; + } + return 0; +} + +int dwe_start_dma_read(struct dw200_subdev *dev, dw_src_addr_t src_addr) +{ + struct dwe_hw_info *info = &dev->dwe_info; +#ifdef DWE_REG_RESET + u32 regStart = 1 << 4; + u32 reg; +#endif + + if (src_addr.uv_addr == 0) { + u32 reg_y_rbuff_size = ALIGN_UP(info->src_stride * info->src_h, 16); + src_addr.uv_addr = (u32) src_addr.y_addr + reg_y_rbuff_size; + } + + dw_info("enter %s\n", __func__); + + dwe_write_reg(dev, SRC_IMG_Y_BASE, (src_addr.y_addr) >> 4); + dwe_write_reg(dev, SRC_IMG_UV_BASE, (src_addr.uv_addr) >> 4); + +#ifdef DWE_REG_RESET + reg = __raw_readl(dev->dwe_reset); + __raw_writel(reg | regStart, dev->dwe_reset); + __raw_writel(reg & ~regStart, dev->dwe_reset); +#endif + return 0; +} + +int dwe_start(struct dw200_subdev *dev) +{ + dw_info("enter %s\n", __func__); + u32 reg_dewarp_ctrl; + reg_dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL); + dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl | 2); + return 0; +} + +int dwe_set_buffer(struct dw200_subdev *dev, u64 addr) +{ + struct dwe_hw_info *info = &dev->dwe_info; + u32 reg_dst_y_base = (u32) addr; + u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16); + u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size; + + dw_info("enter %s\n", __func__); + dwe_write_reg(dev, DST_IMG_Y_BASE, (reg_dst_y_base) >> 4); + dwe_write_reg(dev, DST_IMG_UV_BASE, (reg_dst_uv_base) >> 4); + + return 0; +} + +int dwe_set_lut(struct dw200_subdev *dev, u64 addr) +{ + dwe_write_reg(dev, MAP_LUT_ADDR, ((u32) addr) >> 4); + return 0; +} + +int dwe_ioc_qcap(struct dw200_subdev *dev, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "viv_dw200"); + return 0; +} + +extern void __iomem *visys_sw_rst; +void visys_reset(void) +{ + u32 val = __raw_readl(visys_sw_rst); + __raw_writel( val & ~BIT(31), visys_sw_rst); + __raw_writel(val, visys_sw_rst); +} + +int vse_reset(struct dw200_subdev *dev) +{ + dw_info("enter %s\n", __func__); + +#ifdef VSE_REG_RESET + __raw_writel(0, dev->vse_reset); + __raw_writel(1, dev->vse_reset); +#endif + vse_write_reg(dev, VSE_REG_CTRL, 0x100); + return 0; +} + +void vse_triger_dma_read(struct dw200_subdev *dev) +{ + u32 reg = vse_read_reg(dev, VSE_REG_CTRL); + REG_SET_BIT(reg, VSE_CONTROL_DMA_FRAME_START_BIT, 1); + vse_write_reg(dev, VSE_REG_CTRL, reg); + vse_write_reg(dev, VSE_REG_DMA_CTRL, 5); +} + +#define swap(a, b) \ +{ \ + (a) ^= (b); \ + (b) ^= (a); \ + (a) ^= (b); \ +} + +void setMIBaseAddress(struct dw200_subdev *dev, u32 width, u32 height, + u32 format,u32 yuvbit, u64 addr, int channel) +{ + u32 stride = ALIGN_UP(width*(yuvbit+1), 16); + u32 crSize = 0; + u32 yBaseAddr = addr; + u32 regAddress = VSE_MI_BASE(channel); + u32 crBaseAddr = 0; + u32 ysize = stride * height; + u32 cbSize = ysize; + u32 cbBaseAddr = yBaseAddr + ysize; + + if (ysize == 0) + return; + + switch (format) { + case MEDIA_PIX_FMT_YUV420SP: + cbSize /= 2; + crSize = 0; + break; + case MEDIA_PIX_FMT_YUV422SP: + break; + case MEDIA_PIX_FMT_YUV422I: + ysize = ysize * 2; + break; + case MEDIA_PIX_FMT_YUV444P: + case MEDIA_PIX_FMT_RGB888P: + crSize = ysize; + crBaseAddr = cbBaseAddr + cbSize; + break; + case MEDIA_PIX_FMT_RGB888: /* only supoort RGB interleave format. RGB RGB RGB .. */ + case MEDIA_PIX_FMT_YUV444I: + ysize *= 3; + cbSize = 0; + cbBaseAddr = 0; + break; + case MEDIA_PIX_FMT_BGR888P: + crSize = ysize; + crBaseAddr = cbBaseAddr + cbSize; + swap(yBaseAddr, crBaseAddr); + break; + } + + vse_write_reg(dev, regAddress + VSE_REG_MI_Y_BASE_ADDR_INIT, yBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_Y_SIZE_INIT, ysize); + vse_write_reg(dev, regAddress + VSE_REG_MI_CB_BASE_ADDR_INIT, + cbBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_CB_SIZE_INIT, cbSize); + vse_write_reg(dev, regAddress + VSE_REG_MI_CR_BASE_ADDR_INIT, + crBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_CR_SIZE_INIT, crSize); +} + +int vse_start_dma_read(struct dw200_subdev *dev, u64 addr) +{ + u32 writeFormat = 0; + u32 writeString = 0; + u32 reg = 0; + u32 address = VSE_REG_DMA_FORMAT; + u32 width = dev->vse_info.src_w; + u32 height = dev->vse_info.src_h; + u32 format = dev->vse_info.in_format; + u32 yuvbit = dev->vse_info.in_yuvbit; + u32 ysize, cbSize; + u32 yBaseAddr, cbBaseAddr, crBaseAddr; + u32 stride; + u32 img_width_bn; + if(yuvbit) + img_width_bn = width * 2; + else{ + if(format == MEDIA_PIX_FMT_YUV422I){ + img_width_bn = width * 2; + stride = stride * 2; + }else + img_width_bn = width; + + } + switch (format) { + case MEDIA_PIX_FMT_YUV422SP: + writeFormat = 1; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV422I: + writeFormat = 1; + writeString = 1; + break; + case MEDIA_PIX_FMT_YUV420SP: + writeFormat = 0; + writeString = 0; + break; + } + + reg = vse_read_reg(dev, address); + + dw_info("img_width_bn 0x%08x\n", img_width_bn ); + REG_SET_MASK(reg, VSE_RD_IMG_HSIZE_BN, (img_width_bn & 0x3FFF)); + REG_SET_MASK(reg, VSE_MI_FORMAT_WORD_ALIGNED, yuvbit); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_FMT_ALIGNED, yuvbit); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_STR, writeString); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_FMT, writeFormat); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_10BIT, yuvbit); + dw_info("VSE_REG_DMA_FORMAT reg 0x%08x\n", reg); + vse_write_reg(dev, address, reg); + stride = ALIGN_UP(width*(yuvbit+1), 16); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_WIDTH, width); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_HEIGHT, height); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_STRIDE, stride); + ysize = stride * height; + cbSize = ysize; + yBaseAddr = addr; + cbBaseAddr = yBaseAddr + ysize; + crBaseAddr = 0; + + if (format == MEDIA_PIX_FMT_YUV420SP) { + cbSize /= 2; + } else if (format == MEDIA_PIX_FMT_YUV422I) { + cbSize /= 2; + crBaseAddr = cbBaseAddr + cbSize; + } + vse_write_reg(dev, VSE_REG_Y_PIC_START_ADDR, yBaseAddr); + vse_write_reg(dev, VSE_REG_CB_PIC_START_ADDR, cbBaseAddr); + vse_write_reg(dev, VSE_REG_CR_PIC_START_ADDR, crBaseAddr); + vse_triger_dma_read(dev); + return 0; +} + +void setFormatConvPack(struct dw200_subdev *dev, u32 enable, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_ENABLE_PACK, enable); + vse_write_reg(dev, address, reg); +} + +void setFormatConvFull(struct dw200_subdev *dev, u32 y_full, u32 cbcr_full, + u32 noco422, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_Y_FULL, y_full); + REG_SET_MASK(reg, VSE_FORMAT_CONV_CBCR_FULL, cbcr_full); + REG_SET_MASK(reg, VSE_FORMAT_CONV_CONFIG_422NOCO, 0); + vse_write_reg(dev, address, reg); +} + +static u32 format_conv_map[] = { 2, 2, 1, 3, 3, 6, 6, 6 }; + +void setFormatConvFormat(struct dw200_subdev *dev, u32 inputFormat, + u32 outputFormat,u32 yuvbit, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + } else if (inputFormat == MEDIA_PIX_FMT_YUV422SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + inputFormat = MEDIA_PIX_FMT_YUV420SP; + } else if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat != MEDIA_PIX_FMT_YUV420SP) { + inputFormat = MEDIA_PIX_FMT_YUV422SP; + } + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_OUTPUT_FORMAT, + format_conv_map[outputFormat]); + REG_SET_MASK(reg, VSE_FORMAT_CONV_INPUT_FORMAT, + format_conv_map[inputFormat]); + REG_SET_MASK(reg, VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE, + yuvbit); + vse_write_reg(dev, address, reg); +} + +void setInputSize(struct dw200_subdev *dev, u32 width, u32 height) +{ + u32 reg = ((height & 0x1FFF) << 16) | (width & 0x1FFF); + + vse_write_reg(dev, VSE_REG_IN_SIZE, reg); +} + +void setCropSize(struct dw200_subdev *dev, u32 left, u32 right, u32 top, + u32 bottom, int channel) +{ + u32 hreg = ((right & 0x1FFF) << 16) | (left & 0x1FFF); + u32 vreg = ((bottom & 0x1FFF) << 16) | (top & 0x1FFF); + + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_CROP_XDIR, hreg); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_CROP_YDIR, vreg); +} + +void updateResizeControl(struct dw200_subdev *dev, u32 reg, int channel) +{ + u32 address = VSE_RSZBASE(channel); + + vse_write_reg(dev, address, reg); +} + +void resizeControlAutoUpdate(struct dw200_subdev *dev, u32 autoUpdate, + int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_AUTO_UPDATE_BIT, autoUpdate); + vse_write_reg(dev, address, reg); +} + +void resizeControlConfigUpdate(struct dw200_subdev *dev, u32 configUpdate, + int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT, configUpdate); + vse_write_reg(dev, address, reg); +} + +void resizeControlEnableCrop(struct dw200_subdev *dev, u32 enable, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_CROP_ENABLE_BIT, enable); + vse_write_reg(dev, address, reg); +} + +void updateVseControl(struct dw200_subdev *dev, u32 inputChannel, + u32 inputFormat, u32 enbalePath0, u32 enbalePath1, + u32 enbalePath2, u32 autoUpdate, u32 configUpdate) +{ + u32 reg = 0; + + REG_SET_BIT(reg, VSE_CONTROL_AUTO_UPDATE_BIT, autoUpdate); + REG_SET_BIT(reg, VSE_CONTROL_CONFIG_UPDATE_BIT, configUpdate); + REG_SET_BIT(reg, VSE_CONTROL_PATH0_ENABLE_BIT, enbalePath0); + REG_SET_BIT(reg, VSE_CONTROL_PATH1_ENABLE_BIT, enbalePath1); + REG_SET_BIT(reg, VSE_CONTROL_PATH2_ENABLE_BIT, enbalePath2); + + REG_SET_MASK(reg, VSE_CONTROL_INPUT_SELECT, inputChannel); + REG_SET_MASK(reg, VSE_CONTROL_INPUT_FORMAT, inputFormat); + vse_write_reg(dev, VSE_REG_CTRL, reg); + int i; + for(i=0 ;i <3; i++){ + reg = vse_read_reg(dev,VSE_RSZBASE(i)); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT, 1); + vse_write_reg(dev, VSE_RSZBASE(i), reg); + } + + /* BUS ID and BUS CONFIG, hardcode here, user need adjust it on their hardware. */ + vse_write_reg(dev, 0xa24, 0x01000100); + vse_write_reg(dev, 0xa20, 0x001000fa); + vse_write_reg(dev, 0xa28, 0x924c5214); + vse_write_reg(dev, 0xa30, 0x100000fa); + vse_write_reg(dev, 0xa34, 0x01000100); + vse_write_reg(dev, 0xa38, 0x924c5214); +} + +void enableMIControl(struct dw200_subdev *dev, u32 enable, int channel) +{ + u32 reg = vse_read_reg(dev, VSE_REG_MI_CTRL); + + REG_SET_BIT(reg, channel, enable); + REG_SET_BIT(reg, VSE_MI_CONTROL_RDMA_ENABLE_BIT, 1); + vse_write_reg(dev, VSE_REG_MI_CTRL, reg); +} + +void setMIBufferInfo(struct dw200_subdev *dev, u32 width, u32 height, + u32 format, u32 is10Bit, u32 aligned, int channel) +{ + u32 writeFormat = 0; + u32 writeString = 0; + u32 reg = 0; + u32 address; + + u32 stride = ALIGN_UP(width*(is10Bit+1), 16); + u32 size = stride * height; + + switch (format) { + case MEDIA_PIX_FMT_YUV422SP: + writeFormat = 1; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV422I: + size = size * 2; + writeFormat = 1; + writeString = 1; + break; + case MEDIA_PIX_FMT_YUV420SP: + writeFormat = 0; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV444P: + writeFormat = 2; + writeString = 2; + break; + case MEDIA_PIX_FMT_YUV444I: + writeFormat = 2; + writeString = 1; + break; + case MEDIA_PIX_FMT_RGB888: + writeFormat = 2; + writeString = 1; + break; + case MEDIA_PIX_FMT_RGB888P: + case MEDIA_PIX_FMT_BGR888P: + writeFormat = 2; + writeString = 2; + break; + } + + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_LENGTH, stride); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_WIDTH, + width); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_HEIGHT, + height); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_SIZE, size); + + address = VSE_MI_BASE(channel) + VSE_REG_MI_FMT; + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_MI_FORMAT_WORD_ALIGNED, is10Bit); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_FMT_ALIGNED, is10Bit); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_STR, writeString); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_FMT, writeFormat); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_10BIT, is10Bit); + vse_write_reg(dev, address, reg); +} + +void setMIControlConfig(struct dw200_subdev *dev, u32 enableOffset, + u32 enableUpdateBaseAddress, u32 configUpdate, u32 skip, + u32 autoUpdate, u32 enablePingpong, int channel) +{ + u32 reg = 0; + + REG_SET_BIT(reg, VSE_MI_PATH_INIT_OFFSET_EN_BIT, enableOffset); + REG_SET_BIT(reg, VSE_MI_PATH_INIT_BASE_EN_BIT, enableUpdateBaseAddress); + REG_SET_BIT(reg, VSE_MI_PATH_CONFIG_UPDATE_BIT, configUpdate); + REG_SET_BIT(reg, VSE_MI_PATH_ENABLE_SKIP_BIT, skip); + REG_SET_BIT(reg, VSE_MI_PATH_AUTO_UPDATE_BIT, autoUpdate); + REG_SET_BIT(reg, VSE_MI_PATH_ENABLE_PINGPONG_BIT, enablePingpong); + vse_write_reg(dev, VSE_MI_BASE(channel), reg); +} + +u32 vse_get_scale_factor(int src, int dst) +{ + if (dst >= src) { + return ((65536 * (src - 1)) / (dst - 1)); + } else if (dst < src) { + return ((65536 * (dst - 1)) / (src - 1)) + 1; + } + return 0; +} + +void setScaleFactor(struct dw200_subdev *dev, u32 src_w, u32 src_h, u32 dst_w, + u32 dst_h, u32 inputFormat, u32 outputFormat, int channel) +{ + bool hyup, vyup, hcup, vcup; + u32 scale_factor = vse_get_scale_factor(src_w, dst_w); + u32 address = VSE_RSZBASE(channel); + u32 reg = vse_read_reg(dev, address); + + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HY, + scale_factor); + scale_factor = vse_get_scale_factor(src_h, dst_h); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_VY, + scale_factor); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VY_ENABLE_BIT, + ((src_h != dst_h) & 0x01)); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HY_ENABLE_BIT, + ((src_w != dst_w) & 0x01)); + hyup = src_w < dst_w; + vyup = src_h < dst_h; + + /* Format conv module doesn't support convert other formats to YUV420SP. + doesn't support convert 420SP to other formats too. + so scale down/up cbcr here. + */ + src_w /= 2; + dst_w /= 2; + if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + src_h /= 2; + dst_h /= 2; + } else if (inputFormat == MEDIA_PIX_FMT_YUV422SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + /* scale 422 to 420 */ + dst_h /= 2; + } else if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat != MEDIA_PIX_FMT_YUV420SP) { + /* scale 420 to 422 + cbcr width*2, use input buffer as 422SP */ + src_h /= 2; + } + + hcup = src_w < dst_w; + vcup = src_h < dst_h; + scale_factor = vse_get_scale_factor(src_w, dst_w); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HCB, + scale_factor); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HCR, + scale_factor); + scale_factor = vse_get_scale_factor(src_h, dst_h); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_VC, + scale_factor); + + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VCUP_BIT, vcup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VYUP_BIT, vyup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HCUP_BIT, hcup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HYUP_BIT, hyup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VC_ENABLE_BIT, + (src_h != dst_h)); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HC_ENABLE_BIT, + (src_w != dst_w)); + vse_write_reg(dev, address, reg); +} + +int vse_read_irq(struct dw200_subdev *dev, u32 * ret) +{ + // dw_info("enter %s\n", __func__); + *ret = vse_read_reg(dev, VSE_REG_MI_MSI); + return 0; +} + +int vse_dequeue_irq(struct dw200_subdev *dev, u32 * ret) +{ + vivdw200_mis_t data; + + if (dev == NULL || ret == NULL) { + dw_info("wrong input parameter.\n"); + return -1; + } + if(0 == vivdw200_read_circle_queue(&data, &dev->vse_circle_list)) { + *ret = data.val; + } else { + //pr_err("failed to dequeue vse mis.\n"); + *ret = 0; + } + return 0; +} + +int vse_clear_irq(struct dw200_subdev *dev, u32 mis) +{ + dw_info("enter %s\n", __func__); + vse_write_reg(dev, VSE_REG_MI_ICR, mis); + return 0; +} + +int vse_mask_irq(struct dw200_subdev *dev, u32 mask) +{ + dw_info("enter %s 0x%08x\n", __func__, mask); + vse_write_reg(dev, VSE_REG_MI_IMSC, mask); + return 0; +} + +int vse_ioc_qcap(struct dw200_subdev *dev, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "viv_vse"); + return 0; +} + +int vse_update_buffers(struct dw200_subdev *dev, u64 * addr) +{ + struct vse_params *param = &dev->vse_info; + struct vse_mi_settings *mi = param->mi_settings; + int i = 0; + + dw_info("enter %s\n", __func__); + for (; i < 3; i++) { + if (addr[i] != 0) { + setMIBaseAddress(dev, mi[i].width, mi[i].height, + mi[i].out_format,mi[i].yuvbit, addr[i], i); + } + } + return 0; +} + +int vse_update_mi_info(struct dw200_subdev *dev) +{ + struct vse_params *param = &dev->vse_info; + struct vse_mi_settings *mi = param->mi_settings; + int i = 0; + + dw_info("enter %s\n", __func__); + + for (; i < 3; i++) { + if (!mi[i].enable) + continue; + setMIBufferInfo(dev, mi[i].width, mi[i].height, + mi[i].out_format, mi[i].yuvbit, true, i); + enableMIControl(dev, mi[i].enable, i); + setMIControlConfig(dev, true, true, true, false, true, false, + i); + } + return 0; +} + +int vse_s_params(struct dw200_subdev *dev) +{ + struct vse_params *param = &dev->vse_info; + int i = 0; + int input_select = 0; + int crop_w, crop_h, scale_w, scale_h; + struct vse_crop_size *cropSize; + struct vse_size *outputSize; + + dw_info("enter %s\n", __func__); + setInputSize(dev, param->src_w, param->src_h); + + for (; i < 3; i++) { + if (!param->resize_enable[i]) + continue; + cropSize = ¶m->crop_size[i]; + outputSize = ¶m->out_size[i]; + crop_w = cropSize->right - cropSize->left + 1; + crop_h = cropSize->bottom - cropSize->top + 1; + scale_w = param->src_w; + scale_h = param->src_h; + if (crop_w > 1 && crop_h > 1) { + resizeControlEnableCrop(dev, 1, i); + setCropSize(dev, cropSize->left, cropSize->right, + cropSize->top, cropSize->bottom, i); + scale_w = crop_w; + scale_h = crop_h; + } else { + resizeControlEnableCrop(dev, 0, i); + } + + /* ONLY SUPPORT Semiplanar NOW, all enable pack */ + setFormatConvPack(dev, true, i); + setFormatConvFull(dev, true, true, false, i); + setFormatConvFormat(dev, param->in_format, + param->format_conv[i].out_format,param->mi_settings[i].yuvbit, i); + + setScaleFactor(dev, scale_w, scale_h, outputSize->width, + outputSize->height, param->in_format, + param->format_conv[i].out_format, i); + resizeControlAutoUpdate(dev, 1, i); + resizeControlConfigUpdate(dev, 1, i); + } + +#ifndef HAL_CMODEL + input_select = param->input_select; +#endif + updateVseControl(dev, input_select, param->in_format, + param->resize_enable[0], + param->resize_enable[1], + param->resize_enable[2], true, true); + return 0; +} + +void dw200_mutex_lock(struct dw200_subdev *dev) +{ + mutex_lock(dev->vvmutex); +} + +void dw200_mutex_unlock(struct dw200_subdev *dev) +{ + mutex_unlock(dev->vvmutex); +} + +long dw200_priv_ioctl(struct dw200_subdev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + u64 addr; + + switch (cmd) { + case DWEIOC_RESET: + dw_info("DWEIOC_RESET\n"); + ret = dwe_reset(dev); + break; + case DWEIOC_S_PARAMS: + dw_info("DWEIOC_S_PARAMS\n"); + viv_check_retval(copy_from_user + (&dev->dwe_info, args, sizeof(dev->dwe_info))); + ret = dwe_s_params(dev); + break; + case DWEIOC_ENABLE_BUS: + dw_info("DWEIOC_ENABLE_BUS\n"); + ret = dwe_enable_bus(dev, 1); + break; + case DWEIOC_DISABLE_BUS: + dw_info("DWEIOC_DISABLE_BUS\n"); + ret = dwe_enable_bus(dev, 0); + break; + case DWEIOC_DISABLE_IRQ: + dw_info("DWEIOC_DISABLE_IRQ\n"); + ret = dwe_disable_irq(dev); + break; + case DWEIOC_CLEAR_IRQ: + dw_info("DWEIOC_CLEAR_IRQ\n"); + ret = dwe_clear_irq_1(dev); + break; + case DWEIOC_READ_IRQ:{ + dw_info("DWEIOC_READ_IRQ\n"); + u32 irq = 0; +#ifdef HAL_CMODEL + dwe_read_irq((struct dw200_subdev *)dev, &irq); +#else + ret = dwe_dequeue_irq(dev, &irq); +#endif + + viv_check_retval(copy_to_user(args, &irq, sizeof(irq))); + break; + } + case DWEIOC_START_DMA_READ: + dw_info("DWEIOC_START_DMA_READ\n"); + ;dw_src_addr_t src_addr; + viv_check_retval(copy_from_user(&src_addr, args, sizeof(src_addr))); + ret = dwe_start_dma_read(dev, src_addr); + break; + case DWEIOC_SET_BUFFER: + dw_info("DWEIOC_SET_BUFFER\n"); + viv_check_retval(copy_from_user(&addr, args, sizeof(addr))); + ret = dwe_set_buffer(dev, addr); + break; + case DWEIOC_SET_LUT: + dw_info("DWEIOC_SET_LUT\n"); + viv_check_retval(copy_from_user(&addr, args, sizeof(addr))); + ret = dwe_set_lut(dev, addr); + break; + case DWEIOC_START: + dw_info("DWEIOC_START\n"); + ret = dwe_start(dev); + break; +#ifdef __KERNEL__ + case VIDIOC_QUERYCAP: + ret = dwe_ioc_qcap(dev, args); + break; +#endif + case VSEIOC_RESET: + dw_info("VSEIOC_RESET\n"); + ret = vse_reset(dev); + break; + case VSEIOC_S_PARAMS: + dw_info("VSEIOC_S_PARAMS\n"); + viv_check_retval(copy_from_user + (&dev->vse_info, args, sizeof(dev->vse_info))); + ret = vse_s_params(dev); + break; + case VSEIOC_CLEAR_IRQ: + dw_info("VSEIOC_CLEAR_IRQ\n"); + //ret = vse_clear_irq(dev); + vse_write_reg(dev, VSE_REG_MI_MSI, 0); + break; + case VSEIOC_READ_IRQ:{ + dw_info("VSEIOC_READ_IRQ\n"); + u32 irq = 0; +#ifdef HAL_CMODEL + vse_read_irq((struct dw200_subdev *)dev, &irq); +#else + ret = vse_dequeue_irq(dev, &irq); +#endif + viv_check_retval(copy_to_user(args, &irq, sizeof(irq))); + break; + } + case VSEIOC_START_DMA_READ:{ + dw_info("VSEIOC_START_DMA_READ\n"); + u64 addr; + viv_check_retval(copy_from_user + (&addr, args, sizeof(addr))); + ret = vse_start_dma_read(dev, addr); + break; + } + case VSEIOC_U_MI_INFO: + dw_info("VSEIOC_U_MI_INFO\n"); + ret = vse_update_mi_info(dev); + break; + case VSEIOC_U_BUFFER:{ + dw_info("VSEIOC_U_BUFFER\n"); + u64 addrs[3]; + viv_check_retval(copy_from_user + (addrs, args, sizeof(addrs))); + vse_update_buffers(dev, addrs); + break; + } + case VSEIOC_MASK_IRQ:{ + dw_info("VSEIOC_MASK_IRQ\n"); + u32 mask; + viv_check_retval(copy_from_user + (&mask, args, sizeof(mask))); + vse_mask_irq(dev, mask); + break; + } + case DW200IOC_LOCK: + dw_info("DW200IOC_LOCK\n"); + dw200_mutex_lock(dev); + break; + case DW200IOC_UNLOCK: + dw_info("DW200IOC_UNLOCK\n"); + dw200_mutex_unlock(dev); + break; + case DW200IOC_VISYS_RESET: + dw_info("DW200IOC_VISYS_RESET\n"); + visys_reset(); + break; + default: + //pr_err("unsupported dwe command %d", cmd); + break; + } + + return ret; +} diff --git a/vvcam/dw200/dw200_ioctl.h b/vvcam/dw200/dw200_ioctl.h new file mode 100644 index 0000000..14d458f --- /dev/null +++ b/vvcam/dw200/dw200_ioctl.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_IOC_H_ +#define _DWE_IOC_H_ +#include "dw200_subdev.h" +#include "dwe_regs.h" +#include "vse_regs.h" + +enum { + DWEIOC_RESET = 0x100, + DWEIOC_S_PARAMS, + DWEIOC_ENABLE_BUS, + DWEIOC_DISABLE_BUS, + DWEIOC_DISABLE_IRQ, + DWEIOC_CLEAR_IRQ, + DWEIOC_READ_IRQ, + DWEIOC_START_DMA_READ, + DWEIOC_SET_BUFFER, + DWEIOC_SET_LUT, + DWEIOC_START, + // vse + VSEIOC_RESET, + VSEIOC_S_PARAMS, + VSEIOC_U_BUFFER, + VSEIOC_U_MI_INFO, + VSEIOC_MASK_IRQ, + VSEIOC_READ_IRQ, + VSEIOC_CLEAR_IRQ, + VSEIOC_START_DMA_READ, + DW200IOC_LOCK, // 113 + DW200IOC_UNLOCK, + DW200IOC_UPDATECURR, + DW200IOC_VISYS_RESET, + DW200IOC_GET_RESERVE_ADDR, + DW200IOC_RUNTIME_RESUME, + DW200IOC_RUNTIME_SUSPEND, +}; + +typedef struct dw_src_addr { + u64 y_addr; + u64 uv_addr; +} dw_src_addr_t; + +long dw200_priv_ioctl(struct dw200_subdev *dev, unsigned int cmd, void *args); + +int dwe_reset(struct dw200_subdev *dev); +int dwe_s_params(struct dw200_subdev *dev); +int dwe_enable_bus(struct dw200_subdev *dev, bool enable); +int dwe_disable_irq(struct dw200_subdev *dev); +int dwe_clear_irq(struct dw200_subdev *dev, u32 mis); +int dwe_clear_irq_1(struct dw200_subdev *dev); + +int dwe_read_irq(struct dw200_subdev *dev, u32 *ret); +int dwe_start_dma_read(struct dw200_subdev *dev, dw_src_addr_t src_addr); +int dwe_set_buffer(struct dw200_subdev *dev, u64 addr); +int dwe_set_lut(struct dw200_subdev *dev, u64 addr); + +int vse_reset(struct dw200_subdev *dev); +int vse_s_params(struct dw200_subdev *dev); +int vse_update_mi_info(struct dw200_subdev *dev); +int vse_mask_irq(struct dw200_subdev *dev, u32 mask); +int vse_clear_irq(struct dw200_subdev *dev, u32 mis); +int vse_read_irq(struct dw200_subdev *dev, u32 *ret); +/* dma input pa */ +int vse_start_dma_read(struct dw200_subdev *dev, u64 addr); +/* mi output pa */ +int vse_update_buffers(struct dw200_subdev *dev, u64 *addr); + +#endif // _DWE_IOC_H_ diff --git a/vvcam/dw200/dw200_subdev.h b/vvcam/dw200/dw200_subdev.h new file mode 100644 index 0000000..ab2df69 --- /dev/null +++ b/vvcam/dw200/dw200_subdev.h @@ -0,0 +1,168 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DW200_DEV_H +#define _DW200_DEV_H + + +#include +#include "vivdw200_irq_queue.h" + +#ifndef __KERNEL__ +#include +#include +#define copy_from_user(a, b, c) dw200_copy_data(a, b, c) +#define copy_to_user(a, b, c) dw200_copy_data(a, b, c) + + +typedef void(*pReadBar) (uint32_t bar, uint32_t *data); +typedef void(*pWriteBar) (uint32_t bar, uint32_t data); + +extern void dwe_set_func(pReadBar read_func, pWriteBar write_func); +//extern void dw200_set_func(cmDW200* pDW200,pDw200ReadBar read_func, pDw200WriteBar write_func); + + +typedef bool(*pVseReadBar) (uint32_t bar, uint32_t * data); +typedef bool(*pVseWriteBar) (uint32_t bar, uint32_t data); + +extern void vse_set_func(pVseReadBar read_func, pVseWriteBar write_func); +extern long dw200_copy_data(void *dst, void *src, int size); +#endif + + +typedef enum dw200_input_id { + DW200_INPUT_DWE = 0, + DW200_INPUT_VSE, + DW200_INPUT_MAX +} dw200_input_id; + +typedef enum dw200_output_id { + DW200_OUTPUT_DWE = 0, + DW200_OUTPUT_VSE0, + DW200_OUTPUT_VSE1, + DW200_OUTPUT_VSE2, + DW200_OUTPUT_MAX +} dw200_output_id; + +struct dwe_hw_info { + u32 split_line; + u32 scale_factor; + u32 in_format; + u32 out_format; + u32 in_yuvbit; + u32 out_yuvbit; + u32 hand_shake; + u32 roi_x, roi_y; + u32 boundary_y, boundary_u, boundary_v; + u32 map_w, map_h; + u32 src_auto_shadow, dst_auto_shadow; + u32 src_w, src_stride, src_h; + u32 dst_w, dst_stride, dst_h, dst_size_uv; + u32 split_h, split_v1, split_v2; +}; + +struct vse_crop_size { + u32 left; + u32 right; + u32 top; + u32 bottom; +}; + +struct vse_size { + u32 width; + u32 height; +}; + +struct vse_format_conv_settings { + u32 in_format; + u32 out_format; +}; + +struct vse_mi_settings { + bool enable; + u32 out_format; + u32 width; + u32 height; + u32 yuvbit; +}; + +struct vse_params { + u32 src_w; + u32 src_h; + u32 in_format; + u32 in_yuvbit; + u32 input_select; + struct vse_crop_size crop_size[3]; + struct vse_size out_size[3]; + struct vse_format_conv_settings format_conv[3]; + bool resize_enable[3]; + struct vse_mi_settings mi_settings[3]; +}; + +struct dw200_subdev { + struct dwe_hw_info dwe_info; + struct vse_params vse_info; + void __iomem *dwe_base; + void __iomem *dwe_reset; + void __iomem *vse_base; + void __iomem *vse_reset; + vivdw200_mis_list_t dwe_circle_list; + vivdw200_mis_list_t vse_circle_list; + struct mutex *vvmutex; +}; + +void dwe_write_reg(struct dw200_subdev *dev, u32 offset, u32 val); +u32 dwe_read_reg(struct dw200_subdev *dev, u32 offset); +void vse_write_reg(struct dw200_subdev *dev, u32 offset, u32 val); +u32 vse_read_reg(struct dw200_subdev *dev, u32 offset); + +#endif // _DW200_DEV_H diff --git a/vvcam/dw200/dwe_regs.h b/vvcam/dw200/dwe_regs.h new file mode 100644 index 0000000..232808f --- /dev/null +++ b/vvcam/dw200/dwe_regs.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_REGS_H_ +#define _DWE_REGS_H_ + +//#define REGISTER_NUM 100 +#define DEWARP_REGISTER_BASE_ADDR 0x00000C00 +#define DEWARP_CTRL 0x00000004 +#define SWAP_CONTROL 0x00000058 +#define VERTICAL_SPLIT_LINE 0x0000005C +#define HORIZON_SPLIT_LINE 0x00000060 +#define SCALE_FACTOR 0x00000064 +#define ROI_START 0x00000068 +#define BOUNDRY_PIXEL 0x0000006C +#define INTERRUPT_STATUS 0x00000070 + +#define INT_FRAME_DONE (1 << 0) +#define INT_ERR_STATUS_MASK 0x000000FE +#define INT_ERR_STATUS_SHIFT 1 +#define INT_MSK_STATUS_MASK 0x0000FF00 +#define INT_MSK_STATUS_SHIFT 8 +#define INT_FRAME_BUSY 0x00010000 + +#ifdef HAL_CMODEL +#define INT_CLR_MASK 0x00007F00 +#else +#define INT_CLR_MASK 0x00000100 +#endif + +#define INT_RESET_MASK 0x01000000 +#define BUS_CTRL 0x00000074 +#define DEWRAP_BUS_CTRL_ENABLE_MASK (1 << 31) +#define DEWRAP_BUS_CTRL_RD_ID_ENABLE_MASK (1 << 30) +#define DEWRAP_BUS_CTRL_WR_ID_ENABLE_MASK (1 << 29) +#define DEWRAP_BUS_CTRL_RD_ID_SHIFT (8) +#define DEWRAP_BUS_CTRL_WR_ID_SHIFT (16) + + + +#define BUS_CTRL1 0x00000078 +#define BUS_TIME_OUT_CYCLE 0x0000007C +#define MAP_LUT_ADDR 0x00000008 +#define MAP_LUT_SIZE 0x0000000C +#define SRC_IMG_Y_BASE 0x00000010 +#define SRC_IMG_UV_BASE 0x00000014 +#define SRC_IMG_SIZE 0x00000018 +#define SRC_IMG_STRIDE 0x0000001C +#define MAP_LUT_ADDR2 0x00000020 +#define MAP_LUT_SIZE2 0x00000024 +#define SRC_IMG_Y_BASE2 0x00000028 +#define SRC_IMG_UV_BASE2 0x0000002C +#define SRC_IMG_SIZE2 0x00000030 +#define SRC_IMG_STRIDE2 0x00000034 +#define DST_IMG_Y_BASE 0x00000038 +#define DST_IMG_UV_BASE 0x0000003C +#define DST_IMG_SIZE 0x00000040 +#define DST_IMG_STRIDE 0x00000044 +#define DST_IMG_Y_BASE2 0x00000048 +#define DST_IMG_UV_BASE2 0x0000004C +#define DST_IMG_SIZE2 0x00000050 +#define DST_IMG_STRIDE2 0x00000054 +#define DST_IMG_Y_SIZE1 0x00000080 +#define DST_IMG_UV_SIZE1 0x00000084 +#define DST_IMG_Y_SIZE2 0x00000088 +#define DST_IMG_UV_SIZE2 0x0000008C +#define DST_IMG_WIDTH_BN 0x0000009C + + +#endif /* _DWE_REGS_H_ */ diff --git a/vvcam/dw200/vivdw200_irq_queue.c b/vvcam/dw200/vivdw200_irq_queue.c new file mode 100644 index 0000000..0575077 --- /dev/null +++ b/vvcam/dw200/vivdw200_irq_queue.c @@ -0,0 +1,191 @@ + +#ifdef __KERNEL__ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#else +#include +#include +#include +#endif +#include "vivdw200_irq_queue.h" + +#ifdef __KERNEL__ +#define dw_info(...) +#else +#define dw_info(...) +#endif + + //enqueue +int vivdw200_enqueue(vivdw200_mis_t *data,vivdw200_mis_t* head) + { +#ifdef __KERNEL__ + vivdw200_mis_t* new_node = (vivdw200_mis_t*)kmalloc(sizeof(vivdw200_mis_t), GFP_KERNEL); //create new node + + + if (data == NULL || head == NULL) { + //dw_info("%s: input wrong parameter\n", __func__); + return -1; + } + new_node->val = data->val; + + dw_info("%s: new_node %px", __func__, new_node); + INIT_LIST_HEAD(&new_node->list); + list_add_tail(&new_node->list, &head->list); //append to tail + #endif + return 0; + + } + + //dequeue && release memory +int vivdw200_dequeue(vivdw200_mis_t* data, vivdw200_mis_t* head) + { + +#ifdef __KERNEL__ + vivdw200_mis_t* entry; + if (data == NULL || head == NULL) { + //dw_info("%s: input wrong parameter\n", __func__); + return -1; + } + if (list_empty(&head->list)) { + //dw_info("%s: There is no node\n", __func__); + return -1; + } + + entry = list_first_entry(&head->list, vivdw200_mis_t, list); + dw_info("%s: entry %px", __func__, entry); + data->val = entry->val; + + list_del_init(&entry->list); + + kfree(entry); +#endif + return 0; + } + +bool vivdw200_is_queue_empty( vivdw200_mis_t* head) + { +#ifdef __KERNEL__ + return list_empty(&head->list); +#else + return 0; +#endif + } + +int vivdw200_create_circle_queue(vivdw200_mis_list_t* pCList, int number) +{ +#ifdef __KERNEL__ + int i; + vivdw200_mis_t* pMisNode; + if (pCList == NULL || number <= 0) { + dw_info("%s: create circle queue failed\n", __func__); + return -1; + } + + if (pCList->pHead == NULL) { + + pCList->pHead = (vivdw200_mis_t*)kmalloc(sizeof(vivdw200_mis_t), GFP_KERNEL); + INIT_LIST_HEAD(&pCList->pHead->list); + pCList->pRead = pCList->pHead; + pCList->pWrite = pCList->pHead; + } + dw_info("%s:pHead %px\n", __func__, pCList->pHead); + for (i = 0; i < number - 1; i++) { + pMisNode = (vivdw200_mis_t*)kmalloc(sizeof(vivdw200_mis_t), GFP_KERNEL); + INIT_LIST_HEAD(&pMisNode->list); + list_add_tail(&pMisNode->list, &pCList->pHead->list); + dw_info("%s:pMisNode %px\n", __func__, pMisNode); + } + +#endif + return 0; +} + +int vivdw200_destroy_circle_queue(vivdw200_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + vivdw200_mis_t* pMisNode; + if (pCList == NULL || (pCList->pHead == NULL) ) { + dw_info("%s: destroy circle queue failed. pClist %px\n", __func__, pCList); + return -1; + } + + while(!list_empty(&pCList->pHead->list)) { + pMisNode = list_first_entry(&pCList->pHead->list, vivdw200_mis_t, list); + dw_info("%s:pMisNode %px\n", __func__, pMisNode); + list_del(&pMisNode->list); + kfree(pMisNode); + pMisNode = NULL; + } + dw_info("%s:pHead %px\n", __func__, pCList->pHead); + kfree(pCList->pHead); + pCList->pHead = NULL; + pCList->pRead = NULL; + pCList->pWrite = NULL; +#endif + return 0; +} + +int vivdw200_read_circle_queue(vivdw200_mis_t* data, vivdw200_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + //vivdw200_mis_t* pReadEntry; + if (pCList == NULL) { + dw_info("%s: can not read circle queue\n", __func__); + return -1; + } + + if (pCList->pRead == pCList->pWrite) { + dw_info("%s: There is no irq mis data\n", __func__); + return -1; + } + data->val = pCList->pRead->val; + + dw_info("%s: entry %px, msi %08x\n", __func__, pCList->pRead, data->val); + /*Get the next entry that link with read entry list*/ + /*Update read pointer to next entry*/ + pCList->pRead = list_first_entry(&pCList->pRead->list, vivdw200_mis_t, list); + + //pCList->pRead = pReadEntry; + +#endif + return 0; +} + +int vivdw200_write_circle_queue(vivdw200_mis_t* data, vivdw200_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + vivdw200_mis_t* pWriteEntry; + if (pCList == NULL) { + dw_info("%s: can not read circle queue\n", __func__); + return -1; + } + + pCList->pWrite->val = data->val; + dw_info("%s: entry %px, msi %08x\n", __func__, pCList->pWrite, data->val); + /*get the next write entry pointer that link with the write entry list*/ + pWriteEntry = list_first_entry(&pCList->pWrite->list, vivdw200_mis_t, list); + + /*Update write pointer to point next entry*/ + pCList->pWrite = pWriteEntry; + +#endif + return 0; +} \ No newline at end of file diff --git a/vvcam/dw200/vivdw200_irq_queue.h b/vvcam/dw200/vivdw200_irq_queue.h new file mode 100644 index 0000000..38567e1 --- /dev/null +++ b/vvcam/dw200/vivdw200_irq_queue.h @@ -0,0 +1,83 @@ + /**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + #ifndef _VIVDW200_QUEUE_H_ + #define _VIVDW200_QUEUE_H_ +#ifdef __KERNEL__ +#include +#endif + +typedef struct vivdw200_mis_s { + unsigned int val; +#ifdef __KERNEL__ + struct list_head list; +#endif +}vivdw200_mis_t; +typedef struct vivdw200_mis_list_s { + + vivdw200_mis_t* pHead; + vivdw200_mis_t* pRead; + vivdw200_mis_t* pWrite; +}vivdw200_mis_list_t; + +int vivdw200_enqueue(vivdw200_mis_t *data,vivdw200_mis_t* head); +int vivdw200_dequeue(vivdw200_mis_t* data, vivdw200_mis_t* head); +bool vivdw200_is_queue_empty( vivdw200_mis_t* head); + +#define QUEUE_NODE_COUNT 15 +int vivdw200_create_circle_queue(vivdw200_mis_list_t* pCList, int number); +int vivdw200_destroy_circle_queue(vivdw200_mis_list_t* pCList); + +int vivdw200_read_circle_queue(vivdw200_mis_t* data, vivdw200_mis_list_t* pCList); +int vivdw200_write_circle_queue(vivdw200_mis_t* data, vivdw200_mis_list_t* pCList); + +#endif \ No newline at end of file diff --git a/vvcam/dw200/vse_regs.h b/vvcam/dw200/vse_regs.h new file mode 100644 index 0000000..45710c1 --- /dev/null +++ b/vvcam/dw200/vse_regs.h @@ -0,0 +1,322 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VSE_REGS_H_ +#define _VSE_REGS_H_ + +/* product identification */ +#define VSE_REG_ID 0x00000000 +#define VSE_REG_CTRL 0x00000004 + +#define VSE_CONTROL_ENABLE_RAM_CLK 17 +#define VSE_CONTROL_AUTO_UPDATE_BIT 16 +#define VSE_CONTROL_CONFIG_UPDATE_BIT 15 +#define VSE_CONTROL_DMA_FRAME_START_BIT 14 +#define VSE_CONTROL_INPUT_SELECT_SHIFT 11 +#define VSE_CONTROL_INPUT_SELECT (7 << 11) +#define VSE_CONTROL_INPUT_FORMAT_SHIFT 9 +#define VSE_CONTROL_INPUT_FORMAT (3 << 9) +#define VSE_CONTROL_SOFT_RESET_BIT 8 +#define VSE_CONTROL_PATH2_ENABLE_BIT 2 +#define VSE_CONTROL_PATH1_ENABLE_BIT 1 +#define VSE_CONTROL_PATH0_ENABLE_BIT 0 + +/* input size 28:16 height, 12:0 width */ +#define VSE_REG_IN_SIZE 0x00000008 +#define VSE_REG_CTRL_SHD 0x0000000C +#define VSE_REG_RSZ0_CTL 0x00000400 +#define VSE_REG_RSZ1_CTL 0x00000500 +#define VSE_REG_RSZ2_CTL 0x00000600 +#define VSE_RSZBASE(c) ((c) == 0 ? VSE_REG_RSZ0_CTL : ((c) == 1 ? VSE_REG_RSZ1_CTL : VSE_REG_RSZ2_CTL)) +#define VSE_RSZ_SCALE_HY 0x00000004 +#define VSE_RSZ_SCALE_HCB 0x00000008 +#define VSE_RSZ_SCALE_HCR 0x0000000C +#define VSE_RSZ_SCALE_VY 0x00000010 +#define VSE_RSZ_SCALE_VC 0x00000014 +#define VSE_RSZ_PHASE_HY 0x00000018 +#define VSE_RSZ_PHASE_HC 0x0000001C +#define VSE_RSZ_PHASE_VY 0x00000020 +#define VSE_RSZ_PHASE_VC 0x00000024 +#define VSE_RSZ_SCALE_LUT_ADDR 0x00000028 +#define VSE_RSZ_SCALE_LUT 0x0000002C +#define VSE_RSZ_CTRL_SHD 0x00000030 +#define VSE_RSZ_SCALE_HY_SHD 0x00000034 +#define VSE_RSZ_SCALE_HCB_SHD 0x00000038 +#define VSE_RSZ_SCALE_HCR_SHD 0x0000003C +#define VSE_RSZ_SCALE_VY_SHD 0x00000040 +#define VSE_RSZ_SCALE_VC_SHD 0x00000044 +#define VSE_RSZ_PHASE_HY_SHD 0x00000048 +#define VSE_RSZ_PHASE_HC_SHD 0x0000004C +#define VSE_RSZ_PHASE_VY_SHD 0x00000050 +#define VSE_RSZ_PHASE_VC_SHD 0x00000054 +#define VSE_RSZ_CROP_XDIR 0x00000058 +#define VSE_RSZ_CROP_YDIR 0x0000005C +#define VSE_RSZ_CROP_XDIR_SHD 0x00000060 +#define VSE_RSZ_CROP_YDIR_SHD 0x00000064 +#define VSE_RSZ_FRAME_RATE 0x00000068 +#define VSE_REG_FORMAT_CONV_CTRL 0x0000006C +#define VSE_REG_HBLANK_VALUE 0x000001A0 + +#define VSE_REG_VBLANK_VALUE 0x000001A4 +#define VSE_REG_VSYNC_WIDTH 0x000001A8 +#define VSE_REG_HSYNC_PREAMBLE 0x000001AC +#define VSE_REG_MI_CTRL 0x00000800 +#define VSE_REG_MI_CTRL_SHD 0x00000804 +#define VSE_REG_MI_PATH_0 0x00000810 +#define VSE_REG_MI_PATH_1 0x000008b0 +#define VSE_REG_MI_PATH_2 0x00000950 +#define VSE_MI_BASE(c) ((c) == 0 ? VSE_REG_MI_PATH_0 : ((c) == 1 ? VSE_REG_MI_PATH_1 : VSE_REG_MI_PATH_2)) +#define VSE_REG_MI_FMT 0x00000004 + +#define VSE_REG_MI_Y_BASE_ADDR_INIT 0x00000014 +#define VSE_REG_MI_Y_SIZE_INIT 0x00000018 +#define VSE_REG_MI_Y_OFFSET_COUNT_INIT 0x0000001C +#define VSE_REG_MI_Y_LENGTH 0x00000020 +#define VSE_REG_MI_Y_PIC_WIDTH 0x00000024 +#define VSE_REG_MI_Y_PIC_HEIGHT 0x00000028 +#define VSE_REG_MI_Y_PIC_SIZE 0x0000002C + +#define VSE_REG_MI_CB_BASE_ADDR_INIT 0x00000030 +#define VSE_REG_MI_CB_SIZE_INIT 0x00000034 +#define VSE_REG_MI_CB_OFFSET_COUNT_INIT 0x00000038 +#define VSE_REG_MI_CR_BASE_ADDR_INIT 0x0000003C +#define VSE_REG_MI_CR_SIZE_INIT 0x00000040 +#define VSE_REG_MI_CR_OFFSET_COUNT_INIT 0x00000044 +#define VSE_REG_MI_Y_BASE_ADDR_INIT2 0x00000048 +#define VSE_REG_MI_CB_BASE_ADDR_INIT2 0x0000004C +#define VSE_REG_MI_CR_BASE_ADDR_INIT2 0x00000050 +#define VSE_REG_MI_Y_OFFS_CNT_START 0x00000054 +#define VSE_REG_MI_CB_OFFS_CNT_START 0x00000058 +#define VSE_REG_MI_CR_OFFS_CNT_START 0x0000005C +#define VSE_REG_MI_Y_BASE_ADDR_SHD 0x00000060 +#define VSE_REG_MI_Y_SIZE_SHD 0x00000064 +#define VSE_REG_MI_Y_OFFS_COUNT_SHD 0x00000068 +#define VSE_REG_MI_CB_BASE_ADDR_SHD 0x0000006C +#define VSE_REG_MI_CB_SIZE_SHD 0x00000070 +#define VSE_REG_MI_CB_OFFS_COUNT_SHD 0x00000074 +#define VSE_REG_MI_CR_BASE_ADDR_SHD 0x00000078 +#define VSE_REG_MI_CR_SIZE_SHD 0x0000007C +#define VSE_REG_MI_CR_OFFS_COUNT_SHD 0x00000080 +#define VSE_REG_MI_STATUS_CLR 0x00000084 +#define VSE_REG_MI_CTRL_STATUS 0x00000088 +#define VSE_REG_MI_Y_IRQ_OFFS_INIT 0x0000008C +#define VSE_REG_MI_Y_IRQ_OFFS_SHD 0x00000090 +#define VSE_REG_DMA_CTRL 0x000009E8 +#define VSE_REG_DMA_FORMAT 0x000009EC +#define VSE_REG_DMA_Y_PIC_WIDTH 0x000009F0 +#define VSE_REG_DMA_Y_PIC_HEIGHT 0x000009F4 +#define VSE_REG_DMA_Y_PIC_STRIDE 0x000009F8 +#define VSE_REG_Y_PIC_START_ADDR 0x000009FC +#define VSE_REG_CB_PIC_START_ADDR 0x00000A00 +#define VSE_REG_CR_PIC_START_ADDR 0x00000A04 +#define VSE_REG_Y_START_ADDR_SHD 0x00000A08 +#define VSE_REG_CB_START_ADDR_SHD 0x00000A0C +#define VSE_REG_CR_START_ADDR_SHD 0x00000A10 +#define VSE_REG_DMA_STATUS 0x00000A14 +#define VSE_REG_MI0_BUS_CONFIG 0x00000A20 +#define VSE_REG_MI0_BUS_ID 0x00000A24 +#define VSE_REG_MI0_BUS_TIME_OUT 0x00000A28 +#define VSE_REG_MI0_AXI_STATUS 0x00000A2C + +#define VSE_REG_MI1_BUS_CONFIG 0x00000A30 +#define VSE_REG_MI1_BUS_ID 0x00000A34 +#define VSE_REG_MI1_BUS_TIME_OUT 0x00000A38 +#define VSE_REG_MI1_AXI_STATUS 0x00000A3C + +#define VSE_REG_MI_IMSC 0x00000A40 +#define VSE_REG_MI_IMSC1 0x00000A44 +#define VSE_REG_MI_ISR 0x00000A48 +#define VSE_REG_MI_ISR1 0x00000A4C +#define VSE_REG_MI_MSI 0x00000A50 +#define VSE_REG_MI_MSI1 0x00000A54 +#define VSE_REG_MI_ICR 0x00000A58 +#define VSE_REG_MI_ICR1 0x00000A5C +#define VSE_REG_MI_RIS 0x00000A60 +#define VSE_REG_MI_RIS1 0x00000A64 + +#define VSE_FORMAT_CONV_ENABLE_PACK_SHIFT 10 +#define VSE_FORMAT_CONV_ENABLE_PACK (1 << 10) +#define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD_SHIFT 9 +#define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD (1 << 9) +#define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE_SHIFT 8 +#define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE (1 << 8) +#define VSE_FORMAT_CONV_CONFIG_422NOCO_SHIFT 7 +#define VSE_FORMAT_CONV_CONFIG_422NOCO (1 << 7) +#define VSE_FORMAT_CONV_CBCR_FULL_SHIFT 6 +#define VSE_FORMAT_CONV_CBCR_FULL (1 << 6) +#define VSE_FORMAT_CONV_Y_FULL_SHIFT 5 +#define VSE_FORMAT_CONV_Y_FULL (1 << 5) +#define VSE_FORMAT_CONV_OUTPUT_FORMAT_SHIFT 2 +#define VSE_FORMAT_CONV_OUTPUT_FORMAT (7 << 2) +#define VSE_FORMAT_CONV_INPUT_FORMAT_SHIFT 0 +#define VSE_FORMAT_CONV_INPUT_FORMAT (3) + +/* slice of VSE_REG_RSZ0_CTL */ +#define VSE_RESIZE_CONTROL_AUTO_UPDATE_BIT 10 +#define VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT 9 +#define VSE_RESIZE_CONTROL_CROP_ENABLE_BIT 8 +#define VSE_RESIZE_CONTROL_SCALE_VCUP_BIT 7 +#define VSE_RESIZE_CONTROL_SCALE_VYUP_BIT 6 +#define VSE_RESIZE_CONTROL_SCALE_HCUP_BIT 5 +#define VSE_RESIZE_CONTROL_SCALE_HYUP_BIT 4 +#define VSE_RESIZE_CONTROL_SCALE_VC_ENABLE_BIT 3 +#define VSE_RESIZE_CONTROL_SCALE_VY_ENABLE_BIT 2 +#define VSE_RESIZE_CONTROL_SCALE_HC_ENABLE_BIT 1 +#define VSE_RESIZE_CONTROL_SCALE_HY_ENABLE_BIT 0 + +/* slice of VSE_REG_MI_FMT */ +#define VSE_RD_IMG_HSIZE_BN_SHIFT 16 +#define VSE_RD_IMG_HSIZE_BN (0x3fff<<16) +#define VSE_MI_FORMAT_WA_MSB_EN_SHIFT 10 +#define VSE_MI_FORMAT_WA_MSB_EN (1<<10) +#define VSE_MI_FORMAT_WORD_ALIGNED_SHIFT 9 +#define VSE_MI_FORMAT_WORD_ALIGNED (1<<9) +#define VSE_MI_FORMAT_WR_YUV_NVY_SHIFT 7 +#define VSE_MI_FORMAT_WR_YUV_NVY (3 << 7) +#define VSE_MI_FORMAT_WR_YUV_N21_SHIFT 6 +#define VSE_MI_FORMAT_WR_YUV_N21 (1 << 6) +#define VSE_MI_FORMAT_WR_FMT_ALIGNED_SHIFT 5 +#define VSE_MI_FORMAT_WR_FMT_ALIGNED (1 << 5) +#define VSE_MI_FORMAT_WR_YUV_STR_SHIFT 3 +#define VSE_MI_FORMAT_WR_YUV_STR (3 << 3) +#define VSE_MI_FORMAT_WR_YUV_FMT_SHIFT 1 +#define VSE_MI_FORMAT_WR_YUV_FMT (3 << 1) +#define VSE_MI_FORMAT_WR_YUV_10BIT_SHIFT 0 +#define VSE_MI_FORMAT_WR_YUV_10BIT (1) + +/* slice of VSE_REG_MI_CTRL */ +#define VSE_MI_CONTROL_RDMA_START_BIT 4 +#define VSE_MI_CONTROL_RDMA_ENABLE_BIT 3 +#define VSE_MI_CONTROL_MI2_PATH_ENABLE_BIT 2 +#define VSE_MI_CONTROL_MI1_PATH_ENABLE_BIT 1 +#define VSE_MI_CONTROL_MI0_PATH_ENABLE_BIT 0 + +/* slice of VSE_REG_MI_PATH */ +#define VSE_MI_PATH_INIT_OFFSET_EN_BIT 5 +#define VSE_MI_PATH_INIT_BASE_EN_BIT 4 +#define VSE_MI_PATH_CONFIG_UPDATE_BIT 3 +#define VSE_MI_PATH_ENABLE_SKIP_BIT 2 +#define VSE_MI_PATH_AUTO_UPDATE_BIT 1 +#define VSE_MI_PATH_ENABLE_PINGPONG_BIT 0 +#define VSE_MI_ISR_STATUS_VSE_AND_DEWARP_ALL_DONE_BIT 14 +#define VSE_MI_ISR_STATUS_FINAL_FRAME_END_BIT 13 +#define VSE_MI_ISR_STATUS_DMA_YCBCR_READY_BIT 12 +#define VSE_MI_ISR_STATUS_WRAP_MI2_CR_BIT 11 +#define VSE_MI_ISR_STATUS_WRAP_MI2_CB_BIT 10 +#define VSE_MI_ISR_STATUS_WRAP_MI2_Y_BIT 9 +#define VSE_MI_ISR_STATUS_WRAP_MI1_CR_BIT 8 +#define VSE_MI_ISR_STATUS_WRAP_MI1_CB_BIT 7 +#define VSE_MI_ISR_STATUS_WRAP_MI1_Y_BIT 6 +#define VSE_MI_ISR_STATUS_WRAP_MI0_CR_BIT 5 +#define VSE_MI_ISR_STATUS_WRAP_MI0_CB_BIT 4 +#define VSE_MI_ISR_STATUS_WRAP_MI0_Y_BIT 3 +#define VSE_MI_ISR_STATUS_MI2_FRAME_END_BIT 2 +#define VSE_MI_ISR_STATUS_MI1_FRAME_END_BIT 1 +#define VSE_MI_ISR_STATUS_MI0_FRAME_END_BIT 0 +#define VSE_MI_MIS_VSE_AND_DEWARP_ALL_DONE_BIT 14 +#define VSE_MI_MIS_FINAL_FRAME_END_BIT 13 +#define VSE_MI_MIS_DMA_YCBCR_READY_BIT 12 +#define VSE_MI_MIS_WRAP_MI2_CR_BIT 11 +#define VSE_MI_MIS_WRAP_MI2_CB_BIT 10 +#define VSE_MI_MIS_WRAP_MI2_Y_BIT 9 +#define VSE_MI_MIS_WRAP_MI1_CR_BIT 8 +#define VSE_MI_MIS_WRAP_MI1_CB_BIT 7 +#define VSE_MI_MIS_WRAP_MI1_Y_BIT 6 +#define VSE_MI_MIS_WRAP_MI0_CR_BIT 5 +#define VSE_MI_MIS_WRAP_MI0_CB_BIT 4 +#define VSE_MI_MIS_WRAP_MI0_Y_BIT 3 +#define VSE_MI_MIS_MI2_FRAME_END_BIT 2 +#define VSE_MI_MIS_MI1_FRAME_END_BIT 1 +#define VSE_MI_MIS_MI0_FRAME_END_BIT 0 + + +#define VSE_MI_ISR_ERROR_MI2_BUS_ERROR_BIT 5 +#define VSE_MI_ISR_ERROR_MI2_BUS_TIMEOUT_BIT 4 +#define VSE_MI_ISR_ERROR_MI1_BUS_ERROR_BIT 3 +#define VSE_MI_ISR_ERROR_MI1_BUS_TIMEOUT_BIT 2 +#define VSE_MI_ISR_ERROR_MI0_BUS_ERROR_BIT 1 +#define VSE_MI_ISR_ERROR_MI0_BUS_TIMEOUT_BIT 0 + +#define VSE_MI_BUS_CONFIG_WR_SWAP_V_SHIFT 16 +#define VSE_MI_BUS_CONFIG_WR_SWAP_V (0XF << 16) +#define VSE_MI_BUS_CONFIG_WR_SWAP_U_SHIFT 12 +#define VSE_MI_BUS_CONFIG_WR_SWAP_U (0XF << 12) +#define VSE_MI_BUS_CONFIG_WR_SWAP_Y_SHIFT 8 +#define VSE_MI_BUS_CONFIG_WR_SWAP_Y (0XF << 8) +#define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP_SHIFT 6 +#define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP (0X3 << 6) +#define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP_SHIFT 4 +#define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP (0X3 << 4) +#define VSE_MI_BUS_CONFIG_RD_BURST_LEN_SHIFT 2 +#define VSE_MI_BUS_CONFIG_RD_BURST_LEN (0X3 << 2) +#define VSE_MI_BUS_CONFIG_WR_BURST_LEN_SHIFT 0 +#define VSE_MI_BUS_CONFIG_WR_BURST_LEN (0X3 << 0) + +#ifndef REG_GET_MASK +#define REG_GET_MASK(reg, mask)\ + (((reg) & (mask)) >> (mask##_SHIFT)) + +#define REG_SET_MASK(reg, mask, value)\ + {\ + ((reg) = (((reg) & ~(mask)) | (((value) << (mask##_SHIFT)) & (mask))));\ + } + +#define REG_GET_BIT(reg, shift)\ + (((reg) & 1) >> shift) + +#define REG_SET_BIT(reg, shift, value)\ + {\ + ((reg) = (((reg) & ~(1 << (shift))) | (((value) & 1) << (shift))));\ + } +#endif + +#endif /* _VSE_REGS_H_ */ diff --git a/vvcam/dwe/dwe_dev.h b/vvcam/dwe/dwe_dev.h new file mode 100755 index 0000000..9a6d6e6 --- /dev/null +++ b/vvcam/dwe/dwe_dev.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_DEV_H +#define _DWE_DEV_H + +#include "vvdefs.h" + +#ifndef __KERNEL__ +#define copy_from_user(a, b, c) dwe_copy_data(a, b, c) +#define copy_to_user(a, b, c) dwe_copy_data(a, b, c) + +typedef bool(*pReadBar) (uint32_t bar, uint32_t *data); +typedef bool(*pWriteBar) (uint32_t bar, uint32_t data); + +extern void dwe_set_func(pReadBar read_func, pWriteBar write_func); +extern long dwe_copy_data(void *dst, void *src, int size); +#endif + +#define MAX_DWE_NUM (2) +#define MAX_CFG_NUM (2) + +struct dwe_hw_info { + u32 split_line; + u32 scale_factor; + u32 in_format; + u32 out_format; + u32 hand_shake; + u32 roi_x, roi_y; + u32 boundary_y, boundary_u, boundary_v; + u32 map_w, map_h; + u32 src_auto_shadow, dst_auto_shadow; + u32 src_w, src_stride, src_h; + u32 dst_w, dst_stride, dst_h, dst_size_uv; + u32 split_h, split_v1, split_v2; +}; + +enum BUF_ERR_TYPE { + BUF_ERR_UNDERFLOW = 1, + BUF_ERR_OVERFLOW0 = 1 << 1, + BUF_ERR_OVERFLOW1 = 1 << 2, + BUF_ERR_NO_DIST_MAP0 = 1 << 3, + BUF_ERR_NO_DIST_MAP1 = 1 << 4, + BUF_ERR_WRONGSTATE = 1 << 5, +}; + +struct dwe_ic_dev { + struct dwe_hw_info info[MAX_DWE_NUM][MAX_CFG_NUM]; + int which[MAX_DWE_NUM]; + void __iomem *base; + void __iomem *reset; +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + struct vvbuf_ctx *sink_bctx; + struct vvbuf_ctx *src_bctx[MAX_DWE_NUM]; + dma_addr_t dist_map[MAX_DWE_NUM][MAX_CFG_NUM]; + int *state[MAX_DWE_NUM]; + int index; + struct vb2_dc_buf *src; + struct vb2_dc_buf *dst; + spinlock_t irqlock; + u32 error; + int (*get_index)(struct dwe_ic_dev *dev, struct vb2_dc_buf *buf); +#endif + +}; + +void dwe_write_reg(struct dwe_ic_dev *dev, u32 offset, u32 val); +u32 dwe_read_reg(struct dwe_ic_dev *dev, u32 offset); + +#endif /* _DWE_DEV_H */ diff --git a/vvcam/dwe/dwe_ioctl.c b/vvcam/dwe/dwe_ioctl.c new file mode 100755 index 0000000..43a3b4a --- /dev/null +++ b/vvcam/dwe/dwe_ioctl.c @@ -0,0 +1,381 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include "dwe_ioctl.h" +#include "dwe_regs.h" +#ifndef __KERNEL__ +#include +#include +#include +#ifdef USE_V4L2 +#include +#endif +#endif + +#ifndef __KERNEL__ +#ifdef HAL_CMODEL +#define DEWARP_REGISTER_OFFSET 0 +#else +#define DEWARP_REGISTER_OFFSET 0x380000 +#endif + +#define DEWARP_REGISTER_CTL 0x308250 + +pReadBar g_read_func; +pWriteBar g_write_func; + +void dwe_set_func(pReadBar read_func, pWriteBar write_func) +{ + g_read_func = read_func; + g_write_func = write_func; +} + +void dwe_write_reg(struct dwe_ic_dev *dev, u32 offset, u32 val) +{ + g_write_func(DEWARP_REGISTER_OFFSET + offset, val); +} + +u32 dwe_read_reg(struct dwe_ic_dev *dev, u32 offset) +{ + u32 data; + + g_read_func(DEWARP_REGISTER_OFFSET + offset, &data); + return data; +} + +void dwe_write_extreg(u32 offset, u32 val) +{ + g_write_func(DEWARP_REGISTER_CTL + offset, val); +} + +u32 dwe_read_extreg(u32 offset) +{ + u32 data; + + g_read_func(DEWARP_REGISTER_CTL + offset, &data); + return data; +} + +long dwe_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); + return 0; +} +#else +void dwe_write_reg(struct dwe_ic_dev *dev, u32 offset, u32 val) +{ + __raw_writel(val, dev->base + offset); +} + +u32 dwe_read_reg(struct dwe_ic_dev *dev, u32 offset) +{ + return __raw_readl(dev->base + offset); +} +#endif + +int dwe_reset(struct dwe_ic_dev *dev) +{ + pr_debug("enter %s\n", __func__); +#ifdef DWE_REG_RESET + __raw_writel(0, dev->reset); + __raw_writel(1, dev->reset); +#endif + dwe_write_reg(dev, DEWARP_CTRL, 0x0c); + return 0; +} + +int dwe_s_params(struct dwe_ic_dev *dev, struct dwe_hw_info *info) +{ + u32 reg = 0; + u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16); + u32 vUp = (info->split_v1 & ~0x0F) | 0x0C; + u32 vDown = (info->split_v2 & ~0x0F) | 0x0C; + u32 hLine = (info->split_h & ~0x0F) | 0x0C; + + pr_debug("enter %s\n", __func__); + + dwe_write_reg(dev, MAP_LUT_SIZE, + ((info->map_w & 0x7ff) | ((info->map_h & 0x7ff) << 16))); + dwe_write_reg(dev, SRC_IMG_SIZE, + ((info->src_w & 0x1fff) | + ((info->src_h & 0x1fff) << 16))); + dwe_write_reg(dev, SRC_IMG_STRIDE, info->src_stride); + + dwe_write_reg(dev, DST_IMG_SIZE, + ((info->dst_w & 0x1FFF) | + ((info->dst_h & 0x1FFF) << 16))); + dwe_write_reg(dev, DST_IMG_STRIDE, info->dst_stride); + dwe_write_reg(dev, DST_IMG_Y_SIZE1, reg_y_rbuff_size >> 4); + dwe_write_reg(dev, DST_IMG_UV_SIZE1, info->dst_size_uv >> 4); + dwe_write_reg(dev, VERTICAL_SPLIT_LINE, + (vUp & 0x1fff) | ((vDown & 0x1fff) << 16)); + dwe_write_reg(dev, HORIZON_SPLIT_LINE, (hLine & 0x1fff)); + + reg = 0x4C800001; + reg |= ((info->split_line & 0x1) << 11); + reg |= ((info->in_format & 0x3) << 4); + reg |= ((info->out_format & 0x3) << 6); + reg |= + ((info->src_auto_shadow & 0x1) << 8) | + ((info->dst_auto_shadow & 0x1) << 10); + reg |= ((info->hand_shake & 0x1) << 9); + dwe_write_reg(dev, DEWARP_CTRL, reg); + + dwe_write_reg(dev, BOUNDRY_PIXEL, + (((info->boundary_y & 0xff) << 16) | + ((info->boundary_u & 0xff) + << 8) | (info->boundary_v & 0xff))); + dwe_write_reg(dev, SCALE_FACTOR, info->scale_factor); + dwe_write_reg(dev, ROI_START, + ((info->roi_x & 0x1fff) | + ((info->roi_y & 0x1fff) << 16))); + return 0; +} + +int dwe_enable_bus(struct dwe_ic_dev *dev, bool enable) +{ + u32 reg = dwe_read_reg(dev, BUS_CTRL); + + /* pr_debug("enter %s\n", __func__); */ + + if (enable) { + dwe_write_reg(dev, BUS_CTRL, reg | DEWRAP_BUS_CTRL_ENABLE_MASK); + } else { + dwe_write_reg(dev, BUS_CTRL, + reg & ~DEWRAP_BUS_CTRL_ENABLE_MASK); + } + + return 0; +} + +int dwe_disable_irq(struct dwe_ic_dev *dev) +{ + /* pr_debug("enter %s\n", __func__); */ + dwe_write_reg(dev, INTERRUPT_STATUS, INT_CLR_MASK); + return 0; +} + +int dwe_clear_irq(struct dwe_ic_dev *dev) +{ + u32 reg_dewarp_ctrl; + + /* pr_debug("enter %s\n", __func__); */ + reg_dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL); + dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl | 2); + dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl); + dwe_write_reg(dev, INTERRUPT_STATUS, INT_CLR_MASK | INT_MSK_STATUS_MASK); + + return 0; +} + +int dwe_read_irq(struct dwe_ic_dev *dev, u32 *ret) +{ + u32 irq = 0; + + irq = dwe_read_reg(dev, INTERRUPT_STATUS); + *ret = irq; + + return 0; +} + +int dwe_start(struct dwe_ic_dev *dev) +{ +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + dev->src = NULL; + dev->dst = NULL; + dev->error = BUF_ERR_UNDERFLOW; +#endif + return 0; +} + +int dwe_stop(struct dwe_ic_dev *dev) +{ + dwe_enable_bus(dev, 0); + dwe_disable_irq(dev); + return 0; +} + +int dwe_start_dma_read(struct dwe_ic_dev *dev, + struct dwe_hw_info *info, u64 addr) +{ +#ifdef DWE_REG_RESET + u32 regStart = 1 << 4; + u32 reg; +#endif + u32 reg_dst_y_base = (u32)addr; + u32 reg_y_rbuff_size = ALIGN_UP(info->src_stride * info->src_h, 16); + u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size; + + /* pr_debug("enter %s\n", __func__); */ + + dwe_write_reg(dev, SRC_IMG_Y_BASE, (reg_dst_y_base) >> 4); + dwe_write_reg(dev, SRC_IMG_UV_BASE, (reg_dst_uv_base) >> 4); + +#ifdef DWE_REG_RESET + reg = __raw_readl(dev->reset); + __raw_writel(reg | regStart, dev->reset); + __raw_writel(reg & ~regStart, dev->reset); +#endif + + return 0; +} + +int dwe_set_buffer(struct dwe_ic_dev *dev, struct dwe_hw_info *info, u64 addr) +{ + u32 reg_dst_y_base = (u32) addr; + u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16); + u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size; + + /* pr_debug("enter %s\n", __func__); */ + dwe_write_reg(dev, DST_IMG_Y_BASE, (reg_dst_y_base) >> 4); + dwe_write_reg(dev, DST_IMG_UV_BASE, (reg_dst_uv_base) >> 4); + + return 0; +} + +int dwe_set_lut(struct dwe_ic_dev *dev, u64 addr) +{ + dwe_write_reg(dev, MAP_LUT_ADDR, ((u32) addr) >> 4); + return 0; +} + +int dwe_ioc_qcap(struct dwe_ic_dev *dev, void __user *args) +{ +#ifdef __KERNEL__ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "viv_dewarp100"); +#endif + return 0; +} + +long dwe_priv_ioctl(struct dwe_ic_dev *dev, unsigned int cmd, void __user *args) +{ + int ret = -1; + + switch (cmd) { + case DWEIOC_RESET: + ret = dwe_reset(dev); + break; + case DWEIOC_S_PARAMS: + viv_check_retval(copy_from_user + (&dev->info[0][0], args, sizeof(dev->info[0][0]))); + ret = dwe_s_params(dev, &dev->info[0][0]); + break; +#ifndef ENABLE_IRQ + case DWEIOC_ENABLE_BUS: + ret = dwe_enable_bus(dev, 1); + break; + case DWEIOC_DISABLE_BUS: + ret = dwe_enable_bus(dev, 0); + break; + case DWEIOC_DISABLE_IRQ: + ret = dwe_disable_irq(dev); + break; + case DWEIOC_CLEAR_IRQ: + ret = dwe_clear_irq(dev); + break; +#endif + case DWEIOC_READ_IRQ: { + u32 irq = 0; +#ifndef ENABLE_IRQ + ret = dwe_read_irq(dev, &irq); +#endif + viv_check_retval(copy_to_user(args, &irq, sizeof(irq))); + break; + } + case DWEIOC_START: + ret = dwe_start(dev); + break; + case DWEIOC_STOP: + ret = dwe_stop(dev); + break; + case DWEIOC_START_DMA_READ: { +#ifndef ENABLE_IRQ + u64 addr; + + viv_check_retval(copy_from_user(&addr, args, sizeof(addr))); + ret = dwe_start_dma_read(dev, &dev->info[0][0], addr); +#endif + break; + } + case DWEIOC_SET_BUFFER: { +#ifndef ENABLE_IRQ + u64 addr; + + viv_check_retval(copy_from_user(&addr, args, sizeof(addr))); + ret = dwe_set_buffer(dev, &dev->info[0][0], addr); +#endif + break; + } + case DWEIOC_SET_LUT: { + struct lut_info info; + + viv_check_retval(copy_from_user(&info, args, sizeof(info))); +#ifndef ENABLE_IRQ + ret = dwe_set_lut(dev, info.addr); +#endif + break; + } +#ifdef __KERNEL__ + case VIDIOC_QUERYCAP: + ret = dwe_ioc_qcap(dev, args); + break; +#endif + default: + pr_err("unsupported dwe command %d", cmd); + break; + } + + return ret; +} diff --git a/vvcam/dwe/dwe_ioctl.h b/vvcam/dwe/dwe_ioctl.h new file mode 100755 index 0000000..77d3707 --- /dev/null +++ b/vvcam/dwe/dwe_ioctl.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_IOC_H_ +#define _DWE_IOC_H_ +#include "dwe_dev.h" + +enum { + DWEIOC_RESET = 0x100, + DWEIOC_S_PARAMS, + DWEIOC_ENABLE_BUS, + DWEIOC_DISABLE_BUS, + DWEIOC_DISABLE_IRQ, + DWEIOC_CLEAR_IRQ, + DWEIOC_READ_IRQ, + DWEIOC_START, + DWEIOC_STOP, + DWEIOC_START_DMA_READ, + DWEIOC_SET_BUFFER, + DWEIOC_SET_LUT, +}; + +struct lut_info { + u32 port; + u64 addr; +}; + +long dwe_priv_ioctl(struct dwe_ic_dev *dev, unsigned int cmd, void *args); + +int dwe_reset(struct dwe_ic_dev *dev); +int dwe_s_params(struct dwe_ic_dev *dev, struct dwe_hw_info *info); +int dwe_enable_bus(struct dwe_ic_dev *dev, bool enable); +int dwe_disable_irq(struct dwe_ic_dev *dev); +int dwe_clear_irq(struct dwe_ic_dev *dev); +int dwe_read_irq(struct dwe_ic_dev *dev, u32 *ret); +int dwe_start_dma_read(struct dwe_ic_dev *dev, + struct dwe_hw_info *info, u64 addr); +int dwe_set_buffer(struct dwe_ic_dev *dev, struct dwe_hw_info *info, u64 addr); +int dwe_set_lut(struct dwe_ic_dev *dev, u64 addr); +#ifdef __KERNEL__ +int dwe_on_buf_update(struct dwe_ic_dev *dev); +irqreturn_t dwe_hw_isr(int irq, void *data); +void dwe_clear_interrupts(struct dwe_ic_dev *dev); +#endif +#endif /* _DWE_IOC_H_ */ diff --git a/vvcam/dwe/dwe_isr.c b/vvcam/dwe/dwe_isr.c new file mode 100755 index 0000000..44f6965 --- /dev/null +++ b/vvcam/dwe/dwe_isr.c @@ -0,0 +1,183 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +# include "dwe_driver.h" +# include "video/vvbuf.h" +#endif +#include "dwe_ioctl.h" +#include "dwe_regs.h" + +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + +static int update_dma_buffer(struct dwe_ic_dev *dev) +{ + int no_dist_map_err, overflow_err; + int which; + u32 dewarp_ctrl; + + dwe_enable_bus(dev, 0); + if (dev->dst) + return -EBUSY; + if (dev->src) { + vvbuf_ready(dev->sink_bctx, dev->src->pad, dev->src); + dev->src = NULL; + } + dev->src = vvbuf_try_dqbuf(dev->sink_bctx); + if (!dev->src) { + dev->error |= BUF_ERR_UNDERFLOW; + return -ENOMEM; + } + dev->error &= ~BUF_ERR_UNDERFLOW; + if (!dev->get_index) { + dev->error |= BUF_ERR_WRONGSTATE; + dev->src = NULL; + return -ENXIO; + } + dev->index = dev->get_index(dev, dev->src); + if (dev->index < 0 || dev->index >= MAX_DWE_NUM) { + dev->error |= BUF_ERR_WRONGSTATE; + dev->src = NULL; + return -ENXIO; + } + dev->error &= ~BUF_ERR_WRONGSTATE; + if (!(*dev->state[dev->index] & STATE_DRIVER_STARTED)) { + vvbuf_try_dqbuf_done(dev->sink_bctx, dev->src); + vvbuf_ready(dev->sink_bctx, dev->src->pad, dev->src); + dev->error |= BUF_ERR_UNDERFLOW; + dev->src = NULL; + return 0; + } + no_dist_map_err = BUF_ERR_NO_DIST_MAP0 << dev->index; + if (!dev->dist_map[dev->index]) { + dev->error |= no_dist_map_err; + dev->src = NULL; + return -ENOMEM; + } + dev->error &= ~no_dist_map_err; + overflow_err = BUF_ERR_OVERFLOW0 << dev->index; + dev->dst = vvbuf_try_dqbuf(dev->src_bctx[dev->index]); + if (!dev->dst) { + if (!(*dev->state[dev->index] & STATE_STREAM_STARTED)) { + vvbuf_try_dqbuf_done(dev->sink_bctx, dev->src); + vvbuf_ready(dev->sink_bctx, dev->src->pad, dev->src); + } + dev->error |= overflow_err; + dev->src = NULL; + return -ENOMEM; + } + dev->error &= ~overflow_err; + vvbuf_try_dqbuf_done(dev->sink_bctx, dev->src); + vvbuf_try_dqbuf_done(dev->src_bctx[dev->index], dev->dst); + which = dev->which[dev->index]; + dwe_s_params(dev, &dev->info[dev->index][which]); + dwe_set_buffer(dev, &dev->info[dev->index][which], dev->dst->dma); + dwe_set_lut(dev, dev->dist_map[dev->index][which]); + dwe_start_dma_read(dev, &dev->info[dev->index][which], dev->src->dma); + dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL); + dwe_write_reg(dev, DEWARP_CTRL, dewarp_ctrl | 2); + dwe_write_reg(dev, DEWARP_CTRL, dewarp_ctrl); + dwe_write_reg(dev, INTERRUPT_STATUS, INT_MSK_STATUS_MASK); + dwe_enable_bus(dev, 1); + return 0; +} + +int dwe_on_buf_update(struct dwe_ic_dev *dev) +{ + int rc = 0; + unsigned long flags; + + if (dev) { + spin_lock_irqsave(&dev->irqlock, flags); + if (dev->error) + rc = update_dma_buffer(dev); + spin_unlock_irqrestore(&dev->irqlock, flags); + } + return rc; +} + +void dwe_clear_interrupts(struct dwe_ic_dev *dev) +{ + u32 status; + u32 clr; + status = dwe_read_reg(dev, INTERRUPT_STATUS); + clr = (status & 0xFF) << 24; + dwe_write_reg(dev, INTERRUPT_STATUS, clr); +} + +irqreturn_t dwe_hw_isr(int irq, void *data) +{ + struct dwe_ic_dev *dev = (struct dwe_ic_dev *)data; + u32 status; + u32 clr; + unsigned long flags; + + if (!dev) + return IRQ_HANDLED; + + status = dwe_read_reg(dev, INTERRUPT_STATUS); + if (status & INT_FRAME_DONE) { + clr = (status & 0xFF) << 24; + dwe_write_reg(dev, INTERRUPT_STATUS, clr); + spin_lock_irqsave(&dev->irqlock, flags); + if (dev->dst) { + vvbuf_ready(dev->src_bctx[dev->index], + dev->dst->pad, dev->dst); + dev->dst = NULL; + } + update_dma_buffer(dev); + spin_unlock_irqrestore(&dev->irqlock, flags); + } + return IRQ_HANDLED; +} + +#endif diff --git a/vvcam/dwe/dwe_regs.h b/vvcam/dwe/dwe_regs.h new file mode 100755 index 0000000..61d355f --- /dev/null +++ b/vvcam/dwe/dwe_regs.h @@ -0,0 +1,104 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_REGS_H_ +#define _DWE_REGS_H_ + +#define REGISTER_NUM 100 +#define DEWARP_REGISTER_BASE_ADDR 0x00000000 +#define DEWARP_CTRL 0x00000004 +#define SWAP_CONTROL 0x00000058 +#define VERTICAL_SPLIT_LINE 0x0000005C +#define HORIZON_SPLIT_LINE 0x00000060 +#define SCALE_FACTOR 0x00000064 +#define ROI_START 0x00000068 +#define BOUNDRY_PIXEL 0x0000006C +#define INTERRUPT_STATUS 0x00000070 + +#define INT_FRAME_DONE (1 << 0) +#define INT_ERR_STATUS_MASK 0x000000FE +#define INT_ERR_STATUS_SHIFT 1 +#define INT_MSK_STATUS_MASK 0x0000FF00 +#define INT_MSK_STATUS_SHIFT 8 +#define INT_FRAME_BUSY 0x00010000 +#define INT_CLR_MASK 0xFF000000 +#define BUS_CTRL 0x00000074 +#define DEWRAP_BUS_CTRL_ENABLE_MASK (1 << 31) + +#define BUS_CTRL1 0x00000078 +#define BUS_TIME_OUT_CYCLE 0x0000007C +#define MAP_LUT_ADDR 0x00000008 +#define MAP_LUT_SIZE 0x0000000C +#define SRC_IMG_Y_BASE 0x00000010 +#define SRC_IMG_UV_BASE 0x00000014 +#define SRC_IMG_SIZE 0x00000018 +#define SRC_IMG_STRIDE 0x0000001C +#define MAP_LUT_ADDR2 0x00000020 +#define MAP_LUT_SIZE2 0x00000024 +#define SRC_IMG_Y_BASE2 0x00000028 +#define SRC_IMG_UV_BASE2 0x0000002C +#define SRC_IMG_SIZE2 0x00000030 +#define SRC_IMG_STRIDE2 0x00000034 +#define DST_IMG_Y_BASE 0x00000038 +#define DST_IMG_UV_BASE 0x0000003C +#define DST_IMG_SIZE 0x00000040 +#define DST_IMG_STRIDE 0x00000044 +#define DST_IMG_Y_BASE2 0x00000048 +#define DST_IMG_UV_BASE2 0x0000004C +#define DST_IMG_SIZE2 0x00000050 +#define DST_IMG_STRIDE2 0x00000054 +#define DST_IMG_Y_SIZE1 0x00000080 +#define DST_IMG_UV_SIZE1 0x00000084 +#define DST_IMG_Y_SIZE2 0x00000088 +#define DST_IMG_UV_SIZE2 0x0000008C + +#endif /* _DWE_REGS_H_ */ diff --git a/vvcam/isp/cam_device_buf_defs_common.h b/vvcam/isp/cam_device_buf_defs_common.h new file mode 100755 index 0000000..f5b7a88 --- /dev/null +++ b/vvcam/isp/cam_device_buf_defs_common.h @@ -0,0 +1,110 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _CAMERA_DEVICE_BUF_DEFS_COMMON_H_ +#define _CAMERA_DEVICE_BUF_DEFS_COMMON_H_ + +enum { + CAMERA_PIX_FMT_YUV422SP = 0, + CAMERA_PIX_FMT_YUV422I, + CAMERA_PIX_FMT_YUV420SP, + CAMERA_PIX_FMT_YUV444, + CAMERA_PIX_FMT_RGB888, + CAMERA_PIX_FMT_RGB888P, +}; + + +typedef enum _ISPCORE_BUFIO_ID_ { + ISPCORE_BUFIO_MP = 0, + ISPCORE_BUFIO_SP1 = 1, + ISPCORE_BUFIO_SP2 = 2, + ISPCORE_BUFIO_RDI = 3, //RAW dump interface + ISPCORE_BUFIO_META = 4, //meta sw delivery port + ISPCORE_BUFIO_WRITEMAX = 5, + ISPCORE_BUFIO_READ = 6, + ISPCORE_BUFIO_MAX = 7, +} ISPCORE_BUFIO_ID; + +typedef struct __BufIdentity__ { + uint64_t address_usr; //address in V4l2 application space + uint64_t address_daemon; //address in native stack space + uint64_t address_kernel; //address in kernel space + uint32_t address_reg; //address set to ispcore register + uint32_t buffer_idx; //buffer index + uint32_t buff_size; //biffer size + uint32_t filled; + void *ctx; //memory handle + int width; + int height; + int format; +} BufIdentity; + +typedef struct ispcore_meta_kernel_s { + unsigned int data_kernel; +} ispcore_meta_kernel_t; + +typedef struct ispcore_meta_kernel_dma_s { + unsigned int data_kernel_dma; +} ispcore_meta_kernel_dma_t; + +typedef struct ispcore_meta_user_s { + unsigned int data_user; +} ispcore_meta_user_t; + +typedef struct ispcore_meta_s { + ispcore_meta_kernel_t kernel_meta; + ispcore_meta_kernel_dma_t kernel_meta_dma; + ispcore_meta_user_t user_meta; +} ispcore_meta_t; + +#endif // _CAMERA_DEVICE_BUF_DEFS_COMMON_H_ diff --git a/vvcam/isp/ic_dev.h b/vvcam/isp/ic_dev.h new file mode 100755 index 0000000..0cab935 --- /dev/null +++ b/vvcam/isp/ic_dev.h @@ -0,0 +1,1105 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_DEV_H_ +#define _ISP_DEV_H_ + +#ifndef __KERNEL__ +#include +#include +#include +#include + +#define copy_from_user(a, b, c) isp_copy_data(a, b, c) +#define copy_to_user(a, b, c) isp_copy_data(a, b, c) + +#if defined(HAL_CMODEL) || defined(HAL_ALTERA) || defined ( HAL_LIGHT_FPGA ) +#include + +void isp_ic_set_hal(HalHandle_t hal); +#endif +#endif + +#include "isp_irq_queue.h" +#include "isp_version.h" +#include "vvdefs.h" + +#define REG_ADDR(x) ((uint32_t)(uintptr_t)&all_regs->x) + +#ifdef ISP_MIV1 +#define ISP_BUF_GAP (1024) +#elif defined ISP_MIV2 +#define ISP_BUF_GAP (0) +#endif + +#ifdef ISP_MI_BP +# define MI_PATH_NUM (3) +#else +# define MI_PATH_NUM (2) +#endif + +struct isp_reg_t { + u32 offset; + u32 val; +}; + +struct ic_window { + u16 x; + u16 y; + u16 width; + u16 height; +}; + +struct isp_context { + u32 mode; + u32 sample_edge; + bool hSyncLowPolarity, vSyncLowPolarity; + u32 bayer_pattern; + u32 sub_sampling; + u32 seq_ccir; + u32 field_selection; + u32 input_selection; + u32 latency_fifo; + struct ic_window acqWindow; /**< acquisition window */ + struct ic_window ofWindow; /**< output formatter window */ + struct ic_window isWindow; /**< image stabilization output window */ + u32 bypass_mode; + u8 demosaic_threshold; + u32 stitching_mode; +}; + +typedef struct isp_wdr_context +{ + bool enabled; + bool changed; //the wdr ctrl && reb shift does not have shandow + //register,need to change after frame end irq. + u16 LumOffset; + u16 RgbOffset; + u16 Ym[33]; + u8 dY[33]; + +} isp_wdr_context_t; + +struct isp_digital_gain_cxt { + /* data */ + bool enable; + u16 gain_r; + u16 gain_b; + u16 gain_gr; + u16 gain_gb; +}; + +struct isp_mi_data_path_context { + bool enable; + u32 out_mode; /**< output format */ + u32 in_mode; /**< input format */ + u32 data_layout; /**< layout of data */ + u32 data_alignMode; /**< align mode of data */ + u32 in_width; + u32 in_height; + u32 out_width; + u32 out_height; + bool hscale; + bool vscale; + int pixelformat; + bool yuv_bit; +}; + +struct isp_dummy_hblank_cxt { + u8 bp, fp, w, in_hsize; +}; +enum MIV2_PATH_ID { + ISP_MI_PATH_MP = 0, + ISP_MI_PATH_SP, + ISP_MI_PATH_SP2_BP, +#ifdef ISP_MI_MCM_WR + ISP_MI_MCM_WR0, + ISP_MI_MCM_WR1, +#endif + ISP_MI_PATH_PP, + +#ifdef ISP_MI_HDR + ISP_MI_HDR_L, + ISP_MI_HDR_S, + ISP_MI_HDR_VS, +#endif + ISP_MI_PATH_ID_MAX +}; + +enum DMA_ID { + ISP_MI_DMA_ID_MCM_PP = 0, + ISP_MI_DMA_ID_HDR_L, + ISP_MI_DMA_ID_HDR_S, + ISP_MI_DMA_ID_HDR_VS, + ISP_MI_DMA_ID_MAX +}; +typedef enum start_dma_path_e{ + ISP_MI_DMA_PATH_MCM_PP = 0, + ISP_MI_DMA_PATH_HDR, + ISP_MI_DMA_PATH_MAX, +}start_dma_path_t; + +struct isp_mi_context { + struct isp_mi_data_path_context path[ISP_MI_PATH_ID_MAX]; + u32 burst_len; +}; + +struct isp_bls_context { + bool enabled; + u32 mode; + u16 a, b, c, d; +}; + +struct isp_tpg_userdefine_mode { + u16 total, fp, sync, bp, act; +}; + +struct isp_tpg_context { + bool enabled; + u32 image_type; + u32 frame_num; + u32 bayer_pattern; + u32 color_depth; + u32 resolution; + u16 pixleGap; + u16 lineGap; + u16 gapStandard; + u32 randomSeed; + struct isp_tpg_userdefine_mode user_mode_h, user_mode_v; +}; + +typedef enum mcm_fmt_e{ + MCM_FMT_RAW8 = 0, + MCM_FMT_RAW10, + MCM_FMT_RAW12, + MCM_FMT_RAW14, + MCM_FMT_RAW16, + MCM_FMT_RAW20, + MCM_FMT_MAX, +}mcm_fmt_t; + +typedef enum mcm_wr_index_e{ + MCM_INDEX_WR0 = 0, //write channel 0 + MCM_INDEX_WR1, //write channel 1 + MCM_INDEX_G2_WR0, //MCM_G2 writec channel 0 + MCM_INDEX_G2_WR1, //MCM_G2 writec channel 1 + MCM_INDEX_WR_MAX, +}mcm_wr_fmt_t; + +struct isp_mcm_context { + bool sensor_mem_bypass; //0: use sensor latency memory in MCM + mcm_fmt_t wr_fmt[MCM_INDEX_WR_MAX]; + u8 bypass_switch; //Bypass switch 0000: sensor0 bypass 0001:sensor1 bypass .. 1111:sensor15 bypass if any + u16 height[MCM_INDEX_WR_MAX]; + u16 width[MCM_INDEX_WR_MAX]; + mcm_fmt_t rd_fmt; + u32 hsync_rpeample_ext; + + bool bypass_enable; + u32 vsync_blank; + u32 vsync_duration; + u32 hsync_blank; + u32 hsync_preample; +}; + +struct isp_mux_context { + u32 mp_mux; /**< main path muxer (vi_mp_mux) */ + u32 sp_mux; /**< self path muxer (vi_dma_spmux) */ + u32 chan_mode; /**< 1-mp, 2-sp, 4-sp2 */ + u32 ie_mux; /**< image effects muxer (vi_dma_iemux) */ + u32 dma_read_switch; /**< dma read switch (vi_dma_switch) */ + u32 if_select; /**< interface selector (if_select) */ +}; + +struct isp_awb_context { + bool enable; + u8 mode; + u16 gain_r, gain_gr, gain_gb, gain_b; + struct ic_window window; + u16 refcb_max_b; + u16 refcr_max_r; + u16 max_y; + u16 max_c_sum; + u16 min_y_max_g; + u16 min_c; +}; + +struct isp_awb_mean { + u32 r, g, b; + u32 no_white_count; +}; + +struct isp_cnr_context { + bool enable; + u32 line_width; + u32 threshold_1; + u32 threshold_2; +}; + +struct isp_cc_context { + u32 lCoeff[9]; + bool update_curve; + bool conv_range_y_full, conv_range_c_full; +}; + +struct isp_xtalk_context { + u32 lCoeff[9]; + u32 r, g, b; +}; + +struct isp_gamma_out_context { + bool enableWB, enableGamma; + bool changed; + u32 mode; + u32 curve[17]; +}; + +#define CAEMRIC_GRAD_TBL_SIZE 8 +#define CAMERIC_DATA_TBL_SIZE 289 +#define CAMERIC_MAX_LSC_SECTORS 16 +#define CA_CURVE_DATA_TABLE_LEN 65 + +struct isp_lsc_context { + /**< correction values of R color part */ + u16 r[CAMERIC_DATA_TBL_SIZE]; + /**< correction values of G (red lines) color part */ + u16 gr[CAMERIC_DATA_TBL_SIZE]; + /**< correction values of G (blue lines) color part */ + u16 gb[CAMERIC_DATA_TBL_SIZE]; + /**< correction values of B color part */ + u16 b[CAMERIC_DATA_TBL_SIZE]; + /**< multiplication factors of x direction */ + u16 x_grad[CAEMRIC_GRAD_TBL_SIZE]; + /**< multiplication factors of y direction */ + u16 y_grad[CAEMRIC_GRAD_TBL_SIZE]; + /**< sector sizes of x direction */ + u16 x_size[CAEMRIC_GRAD_TBL_SIZE]; + /**< sector sizes of y direction */ + u16 y_size[CAEMRIC_GRAD_TBL_SIZE]; +}; + +struct isp_dmoi_context { + bool enable; + uint8_t demoire_area_thr; + uint8_t demoire_sat_shrink; + uint16_t demoire_r2; + uint16_t demoire_r1; + uint8_t demoire_t2_shift; + uint8_t demoire_t1; + uint16_t demoire_edge_r2; + uint16_t demoire_edge_r1; + uint8_t demoire_edge_t2_shift; + uint16_t demoire_edge_t1; +}; + +struct isp_shap_context { + bool enable; + uint16_t sharpen_factor_black; + uint16_t sharpen_factor_white; + uint16_t sharpen_clip_black; + uint16_t sharpen_clip_white; + uint16_t sharpen_t4_shift; + uint16_t sharpen_t3; + uint8_t sharpen_t2_shift; + uint16_t sharpen_t1; + uint16_t sharpen_r3; + uint16_t sharpen_r2; + uint16_t sharpen_r1; +}; + +struct isp_shap_line_context { + bool enable; + uint8_t sharpen_line_shift2; + uint8_t sharpen_line_shift1; + uint16_t sharpen_line_t1; + uint16_t sharpen_line_strength; + uint16_t sharpen_line_r2; + uint16_t sharpen_line_r1; +}; + +struct isp_gfilter_context { + uint8_t sharpen_size; + uint8_t hf_filt_00; + uint8_t hf_filt_01; + uint8_t hf_filt_02; + uint8_t hf_filt_10; + uint8_t hf_filt_11; + uint8_t hf_filt_12; + uint8_t hf_filt_20; + uint8_t hf_filt_21; + uint8_t hf_filt_22; +}; + +struct isp_skin_context { + bool enable; + uint16_t cb_thr_max_2047; + uint16_t cb_thr_min_2047; + uint16_t cr_thr_max_2047; + uint16_t cr_thr_min_2047; + uint16_t y_thr_max_2047; + uint16_t y_thr_min_2047; +}; + +struct isp_depurple_context { + bool enable; + bool red_sat, blue_sat; + uint8_t depurple_sat_shrink; + uint8_t depurple_thr; +}; + +struct isp_intp_thr_cxt { + u16 intp_dir_thr_min; + u16 intp_dir_thr_max; +}; + +struct isp_dmsc_context { + bool enable; + uint8_t demosaic_thr; + uint8_t denoise_stren; + struct isp_intp_thr_cxt intp; + struct isp_dmoi_context demoire; + struct isp_shap_context sharpen; + struct isp_gfilter_context gFilter; + struct isp_shap_line_context sharpenLine; + struct isp_skin_context skin; + struct isp_depurple_context depurple; +}; + +struct isp_ge_context { + bool enable; + u16 threshold; + u16 h_dummy; +}; + +struct isp_ca_context { + bool enable; + u8 mode; + u16 lut_x[CA_CURVE_DATA_TABLE_LEN]; + u16 lut_luma[CA_CURVE_DATA_TABLE_LEN]; + u16 lut_chroma[CA_CURVE_DATA_TABLE_LEN]; + u16 lut_shift[CA_CURVE_DATA_TABLE_LEN]; +}; + +struct isp_buffer_context { + u32 type; + u32 path; + u32 addr_y, addr_cb, addr_cr; + u32 size_y, size_cb, size_cr; +}; + +struct isp_bp_buffer_context { + u32 addr_r; + u32 addr_gr; + u32 addr_gb; + u32 addr_b; +}; + +struct isp_dma_context { + u32 type; + u32 base; + u32 width; + u32 height; + u32 burst_y; + u32 burst_c; + u8 align; + u8 id; +#ifdef ISP_MI_HDR + u8 rd_wr_str; +#endif +}; + +struct isp_dpf_context { + bool enable; + u32 filter_type; + u32 gain_usage; + u32 strength_r; + u32 strength_g; + u32 strength_b; + u8 weight_g[6]; + u8 weight_rb[6]; + u16 denoise_talbe[17]; + u32 x_scale; + u32 nf_gain_r; + u32 nf_gain_gr; + u32 nf_gain_gb; + u32 nf_gain_b; + bool filter_r_off; + bool filter_gr_off; + bool filter_gb_off; + bool filter_b_off; +}; + +struct isp_is_context { + bool enable; + bool update; + struct ic_window window; + u32 recenter; + u32 max_dx, max_dy; + u32 displace_x, displace_y; +}; + +struct isp_ee_context { + bool enable; + u8 src_strength; + u8 strength; + u8 input_sel; + u32 y_gain, uv_gain, edge_gain; +}; + +struct isp_exp_context { + bool enable; + u32 mode; + struct ic_window window; +}; + +struct isp_hist_context { + bool enable; + u32 mode; + u32 step_size; + struct ic_window window; + u8 weight[25]; +}; + +struct isp_hist64_context { + bool enable; + u8 channel; + u32 mode; + u8 vStepSize; + u32 hStepInc; + u8 r_coeff, g_coeff, b_coeff; + u8 sample_shift; + u16 sample_offset; + u16 forced_upd_start_line; + bool forced_upd; + struct ic_window window; + u8 weight[25]; +}; + +struct isp_dpcc_params { + u32 line_thresh; + u32 line_mad_fac; + u32 pg_fac; + u32 rnd_thresh; + u32 rg_fac; +}; + +struct isp_dpcc_context { + bool enable; + u32 mode; + u32 outmode; + u32 set_use; + u32 methods_set[3]; + struct isp_dpcc_params params[3]; + u32 ro_limits; + u32 rnd_offs; +}; + +struct isp_flt_context { + bool enable; + bool changed; + u32 denoise; + u32 sharpen; +}; + +struct isp_cac_context { + bool enable; + u32 hmode, vmode; + u32 ab, ar, bb, br, cb, cr; + u32 xns, xnf, yns, ynf; + u32 hstart, vstart; +}; + +/* degamma */ +struct isp_deg_context { + bool enable; + u8 segment[16]; + u16 r[17]; + u16 g[17]; + u16 b[17]; +}; + +struct isp_ie_context { + bool enable; + u32 mode; + u32 color_sel; + u32 color_thresh; + u32 sharpen_factor; + u32 sharpen_thresh; + int32_t m[9]; + u32 tint_cr; + u32 tint_cb; + bool full_range; +}; + +struct isp_afm_result { + u32 sum_a, sum_b, sum_c; + u32 lum_a, lum_b, lum_c; +}; + +struct isp_afm_context { + bool enable; + u32 thresh; + struct ic_window window[3]; + u32 pixCnt[3]; + bool enableWinId[3]; + u32 lum_shift; + u32 afm_shift; + u32 max_pix_cnt; +}; + +struct isp_vsm_result { + u32 x, y; +}; + +struct isp_vsm_context { + bool enable; + struct ic_window window; + u32 h_seg, v_seg; +}; + +#ifndef WDR3_BIN +#define WDR3_BIN 14 +#endif +struct isp_wdr3_context { + bool enable; + bool changed; + bool inited; + u32 strength; + u32 max_gain; + u32 global_strength; + u32 histogram[WDR3_BIN]; + u32 shift[WDR3_BIN]; + u32 invert_linear[WDR3_BIN]; + u32 invert_curve[WDR3_BIN]; + u32 gamma_pre[WDR3_BIN]; + u32 gamma_up[WDR3_BIN]; + u32 gamma_down[WDR3_BIN]; + u32 entropy[WDR3_BIN]; + u32 distance_weight[WDR3_BIN]; + u32 difference_weight[WDR3_BIN]; +}; + +#ifdef ISP_WDR_V4 +#ifndef WDR4_BIN +#define WDR4_BIN 20 +#endif + +struct isp_wdr4_context { + bool enable; + bool changed; + bool inited; + u8 ratioLSVS, ratioLS; + u8 drc_bayer_ratio, drc_bayer_ratioLSVS; + u32 strength; + u32 high_strength; + u32 low_strength; + u32 low_gain; + u32 global_strength; + int contrast; + u32 flat_strength; + u32 flat_threshold; + u32 histogram[WDR4_BIN]; + u32 shift[WDR4_BIN]; + u32 shift0[WDR4_BIN]; + u32 invert_linear[WDR4_BIN]; + u32 invert_curve[WDR4_BIN]; + u32 gamma_pre[WDR4_BIN]; + u32 gamma_up[WDR4_BIN]; + u32 gamma_down[WDR4_BIN]; + u32 entropy[WDR4_BIN]; + u32 distance_weight[WDR4_BIN]; + u32 difference_weight[WDR4_BIN]; + u32 smooth_invert[WDR4_BIN]; +}; + +#endif +#ifndef ISP_AEV2_V2 +#define AEV2_DMA_SIZE 4096 +#else +#define AEV2_DMA_SIZE (4096 *2) +#endif +struct isp_exp2_context { + bool enable; + struct ic_window window; + /* weight; */ + u8 r, gr, gb, b; + u8 input_select; //00: degamma output, 01: awb_gain output 10: WDR3 output + /* write 4096/8192 EXPV2 mean value to dma by MI MP-JDP path. */ + /* physical address, alloacte by user */ + u64 pa; +}; + +#define ISP_2DNR_SIGMA_BIN 60 +struct isp_2dnr_context { + bool enable; + u32 pre_gamma; + u32 strength; + u16 sigma[ISP_2DNR_SIGMA_BIN]; +#if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4) || defined(ISP_2DNR_V5) + u32 sigma_sqr; + u32 weight; +#endif +#if defined(ISP_2DNR_V4) || defined(ISP_2DNR_V5) + u16 str_off; + u16 str_max; + u8 str_slope; +#endif +}; + +struct isp_3dnr_compress_context { + u8 weight_up_y[2]; + u8 weight_down[4]; + u8 weight_up[8]; +}; +struct isp_3dnr_context { + bool enable; + bool update_bin; + bool enable_h, enable_v; + bool enable_temperal; + bool enable_dilate; + bool init; + u32 spacial_curve[17]; + u32 temperal_curve[17]; + u32 strength; + u16 motion_factor; + u16 delta_factor; + /* write full denoise3d reference raw image to dma by MI SP2. */ + /* physical address, alloacte by user */ + u64 pa; + u32 size; + struct isp_3dnr_compress_context compress; +}; + +struct isp_3dnr_update { + u32 thr_edge_h_inv; + u32 thr_edge_v_inv; + u32 thr_motion_inv; + u32 thr_range_s_inv; + u32 range_t_h; + u32 range_t_v; + u32 range_d; + u32 thr_range_t_inv; + u32 thr_delta_h_inv; + u32 thr_delta_v_inv; + u32 thr_delta_t_inv; +}; + +#ifdef ISP_3DNR_V3 +#define DENOISE3D_GAMMA_BIN 33 + +struct isp_tdnr_stats { + u32 bg_sum; + u32 motion_sum; + u32 bg_pixel_cnt; + u32 motion_pixel_cnt; + u32 frame_avg; +}; + +struct isp_tdnr_curve { + u16 preGamma_y[DENOISE3D_GAMMA_BIN]; + u16 invGamma_y[DENOISE3D_GAMMA_BIN]; +}; + +struct isp_tdnr_buffer { + /* write full denoise3d reference raw image to dma by MI SP2. */ + /* physical address, alloacte by user */ + u64 pa_refer; + u32 size_refer; + u64 pa_motion; + u32 size_motion; +}; + +struct isp_tdnr_context { + bool enable; + bool enable_inv_gamma; + bool enable_pre_gamma; + bool enable_motion_erosion; + bool enable_motion_converage; + bool enable_motion_dilation; + bool enable_tnr; + bool enable_2dnr; + u8 strength; + u16 noise_level; + u16 noise_mean; + u16 noise_threshold; + u16 motion_mean; + u8 range_h; + u8 range_v; + u8 dilate_range_h; + u8 dilate_range_v; + u32 motion_inv_factor; + u16 update_factor; + u16 motion_update_factor; + u16 pre_motion_weight; + u16 motion_slope; + u16 motion_converage_shift; + u16 motion_converage_max; + u16 tnr_val_shift_bit; + u16 tnr_diff_shift_bit; + u16 sad_weight; + u16 luma_pixel_val_shift; + u16 luma_pixel_slope; + u16 luma_pixel_slope_shift; + u16 luma_pixel_slope_min; + u16 dmy_hblank; + u32 fn; + struct isp_tdnr_curve curve; + struct isp_tdnr_buffer buf; + + u8 frames; //skip the first frame before clear reset. + //keep the 3dnr enable in register to avoid scrolling screen when repeat enable +}; + +#endif + +struct isp_hdr_context { + bool enable; + /* hdr bls */ + u16 width; + u16 height; + u8 l_bit_dep, s_bit_dep, vs_bit_dep, ls_bit_dep; + u8 weight0, weight1, weight2; + u16 start_linear, norm_factor_mul_linear; + u16 start_nonlinear, norm_factor_mul_nonlinear; + u16 dummy_hblank, out_hblank; + u16 out_vblank; + u16 long_exp, short_exp, very_short_exp; + u16 bls[4]; + u16 digal_gain[4]; + u32 reg; + /* hdr awb */ + u32 r, gr, gb, b; + /* hdr exp */ + u32 compress_lut[15]; + /* long short, very short */ + u32 ls0, ls1, vs0, vs1; + u32 ext_bit; + u32 valid_thresh; + u32 offset_val; + u32 sat_thresh; + u32 combine_weight; +}; + +struct isp_simp_context { + bool enable; + u32 x, y; + u32 r, g, b; + u32 transparency_mode; + u32 ref_image; +}; + +struct isp_compand_curve_context { + bool enable; + bool update_curve; + uint8_t in_bit; + uint8_t out_bit; + uint32_t px[64]; + uint32_t x_data[63]; + uint32_t y_data[64]; +}; + +struct isp_compand_bls_context { + uint8_t bit_width; + bool enable; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; +}; + +/* COMPAND */ +struct isp_comp_context { + bool enable; + struct isp_compand_curve_context expand; + struct isp_compand_bls_context bls; + struct isp_compand_curve_context compress; +}; + +struct isp_cproc_context { + bool enable; + bool changed; + u32 contrast; + u32 brightness; + u32 saturation; + u32 hue; + bool y_out_full; + bool c_out_full; + bool y_in_full; +}; + +struct elawb_ellipse_info { + u32 x, y; /* ellipse center */ + u32 a1, a2, a3, a4; /* ellipse axis */ + u32 r_max_sqr; +}; + +struct isp_elawb_context { + bool enable; + u32 id; /* ellipse id, 1-8, 0 means update all. */ + struct elawb_ellipse_info info[8]; + struct ic_window window; + u32 r, gr, gb, b; /* gain */ +}; + +struct isp_gcmono_data { + u8 basePara[1024]; + u32 px[64]; + u32 dataX[63]; + u32 dataY[64]; +}; + +struct isp_gcmono_context { + u32 enable; + u32 mode; +}; + +struct isp_rgbgamma_data { + u32 rgbgc_r_px[64]; + u32 rgbgc_r_datax[63]; + u32 rgbgc_r_datay[64]; + u32 rgbgc_g_px[64]; + u32 rgbgc_g_datax[63]; + u32 rgbgc_g_datay[64]; + u32 rgbgc_b_px[64]; + u32 rgbgc_b_datax[63]; + u32 rgbgc_b_datay[64]; +}; + +struct isp_rgbgamma_context { + bool enable; +}; + +struct isp_irq_data { + uint32_t addr; + uint32_t val; + uint32_t nop[14]; +}; + +struct isp_rgbir_bls_context { + u16 a; + u16 b; + u16 c; + u16 d; +}; + +struct isp_rgbir_rgb_gain_context { + u16 r; + u16 g; + u16 b; +}; + +struct isp_rgbir_dpcc_context { + u16 median_thr[4]; + u16 avg_thr[4]; +}; + +struct isp_rgbir_cc_context { + u16 mtx[3][4]; +}; + +struct isp_rgbir_des_context { + u32 ir_px1, ir_py[16]; + u32 ir_pd[16], l_pd[16]; + u32 l_px1, l_py[16]; +}; + +struct isp_rgbir_sharpen_context { + u8 sharpen_lvl, middle; + u16 thresh_bl0, thresh_bl1; + u16 thresh_sh0, thresh_sh1; + u8 lum_weight_min, lum_weight_kink, lum_weight_gain; +}; + +struct isp_rgbir_ir_dnr_context { + u16 ir_sigmaS; + u8 winweight[6]; + u16 width, height; +}; +struct isp_rgbir_context{ + bool prefilt_enable, green_filt_mode, green_filt_enable; + u8 rgbirPattern, out_rgb_pattern, green_filt_stage1_select; + u8 demosaic_threshold; + bool part1_enable, part2_enable; + bool enable_ir_raw_out; + + struct isp_rgbir_bls_context bls; + struct isp_rgbir_rgb_gain_context rgb_gain; + struct isp_rgbir_dpcc_context dpcc; + struct isp_rgbir_cc_context cc; + struct isp_rgbir_des_context des; + struct isp_rgbir_sharpen_context sharpen; + struct isp_rgbir_ir_dnr_context ir_dnr; +}; + +struct isp_crop_context { + bool enabled; + struct ic_window window; +}; + +#if 1 //def ISP_MI_PP_READ +typedef struct pp_dma_line_entry_s { + u32 width; + u32 height; + u32 stride; + u32 buf_size;/**/ + u32 data_format; + u16 entry_line_num; + u32 buf_line_num; + u64 buf_addr; +} pp_dma_line_entry_t; + +#endif + +typedef struct pp_wr_line_entry_s { + u16 entry_line_num; + u16 buf_line_num; + u32 buf_addr; + u32 buf_size; +} pp_wr_line_entry_t; + +struct isp_ic_dev { + void __iomem *base; + void __iomem *reset; + int id; +#ifdef ISP8000NANO_V1802 + struct regmap *mix_gpr; +#endif +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + struct vvbuf_ctx *bctx; + struct vb2_dc_buf *mi_buf[MI_PATH_NUM]; + struct vb2_dc_buf *mi_buf_shd[MI_PATH_NUM]; + int (*alloc)(struct isp_ic_dev *dev, struct isp_buffer_context *buf); + int (*free)(struct isp_ic_dev *dev, struct vb2_dc_buf *buf); + int *state; +#endif + void (*post_event)(struct isp_ic_dev *dev, void *data, size_t size); + + struct isp_context ctx; + struct isp_digital_gain_cxt dgain; + struct isp_bls_context bls; + struct isp_tpg_context tpg; + struct isp_mcm_context mcm; + struct isp_mux_context mux; + struct isp_awb_context awb; + struct isp_lsc_context lsc; + struct isp_gamma_out_context gamma_out; + struct isp_xtalk_context xtalk; + struct isp_cc_context cc; + struct isp_cnr_context cnr; + struct isp_is_context is; + struct isp_is_context rawis; + struct isp_mi_context mi; + struct isp_dpf_context dpf; + struct isp_ee_context ee; + struct isp_exp_context exp; + struct isp_hist_context hist; +#ifdef ISP_HIST64 + struct isp_hist64_context hist64; +#endif + struct isp_dpcc_context dpcc; + struct isp_flt_context flt; + struct isp_cac_context cac; + struct isp_deg_context deg; + struct isp_ie_context ie; + struct isp_vsm_context vsm; + struct isp_afm_context afm; + struct isp_wdr3_context wdr3; + struct isp_exp2_context exp2; + struct isp_hdr_context hdr; + struct isp_exp_context hdrexp; + struct isp_hist_context hdrhist; + struct isp_2dnr_context dnr2; + struct isp_3dnr_context dnr3; + + struct isp_comp_context comp; + struct isp_simp_context simp; + struct isp_cproc_context cproc; + struct isp_elawb_context elawb; + struct isp_gcmono_context gcmono; + struct isp_rgbgamma_context rgbgamma; + struct isp_dmsc_context demosaic; + struct isp_ge_context ge; + struct isp_ca_context ca; + struct isp_dummy_hblank_cxt hblank; + isp_wdr_context_t wdr; + bool streaming; + bool update_lsc_tbl; + bool update_gamma_en; +#ifdef ISP_WDR_V4 + struct isp_wdr4_context wdr4; +#endif +#ifdef ISP_3DNR_V3 + struct isp_tdnr_context tdnr; +#endif + struct isp_rgbir_context rgbir; + u32 isp_mis; +#ifdef ISP_MI_PP_READ + pp_dma_line_entry_t pp_dma_line_entry; +#endif + struct isp_crop_context crop[ISP_MI_PATH_SP2_BP + 1]; + pp_wr_line_entry_t pp_write; + isp_mis_list_t circle_list; //The irq circle list + long long unsigned int frame_mark_info_addr; + long long unsigned int ut_phy_addr; //for units test + void *ut_addr; + struct device *device; +}; + +struct isp_extmem_info { + u64 addr; + u64 size; +}; + +void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val); +u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset); + +#endif /* _ISP_DEV_H_ */ diff --git a/vvcam/isp/insmod.sh b/vvcam/isp/insmod.sh new file mode 100755 index 0000000..e7f868a --- /dev/null +++ b/vvcam/isp/insmod.sh @@ -0,0 +1,6 @@ +#!/bin/bash +modprobe vivid +rmmod vivid +rmmod viv_isp_driver.ko +insmod viv_isp_driver.ko + diff --git a/vvcam/isp/isp_3dnr.c b/vvcam/isp/isp_3dnr.c new file mode 100755 index 0000000..903700c --- /dev/null +++ b/vvcam/isp/isp_3dnr.c @@ -0,0 +1,455 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "isp_ioctl.h" +#include "mrv_all_bits.h" + +#include "isp_types.h" +#ifdef ISP_3DNR +extern MrvAllRegister_t *all_regs; + + +static void dnr3_hw_init(struct isp_ic_dev *dev) +{ + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 regVal = 0; + int i, pos; + /* spacial */ + u32 update_spacial = 900; + u32 strength_curve_spacial = 64; + u32 thr_edge_v_inv = 1024; + u32 thr_edge_h_inv = 1024; + u32 thr_range_s_inv = 1024; + /* temperal */ + u32 update_temperal = 1020; + u32 strength_curve_temperal = 64; + u32 range_t_h = 2; + u32 range_t_v = 2; + u32 thr_range_t_inv = 41943; + u32 thr_motion_inv = 1024; + u32 range_d = 1; + u32 thr_delta_h_inv = 1023; + u32 thr_delta_v_inv = 1023; + u32 thr_delta_t_inv = 1023; + u32 strength = dnr3->strength; + strength = MIN(MAX(strength, 0), 128); + + if (dnr3->init) { //for 3dnr init + u32 isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl)); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_HORIZONTAL_EN, + dnr3->enable_h); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_VERTICAL_EN, + dnr3->enable_v); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_TEMPERAL_EN, + dnr3->enable_temperal); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_DILATE_EN, + dnr3->enable_dilate); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl); + } + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_SPACIAL, + strength_curve_spacial); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, thr_edge_h_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_TEMPERAL, + strength_curve_temperal); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, thr_edge_v_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, thr_range_s_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, range_t_h); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, range_t_v); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, thr_range_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, range_d); + REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, thr_motion_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, thr_delta_h_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, thr_delta_v_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, thr_delta_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal); + /* spacial */ + + for (i = 0; i < 6; i++) { + regVal = 0; + pos = i * 3; + if (i < 5) { + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE0, + dnr3->spacial_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1, + dnr3->spacial_curve[pos + 1]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2, + dnr3->spacial_curve[pos + 2]); + } else { + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1, + dnr3->spacial_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2, + dnr3->spacial_curve[pos + 1]); + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_s[i]), regVal); + regVal = 0; + if (i < 5) { + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE0, + dnr3->temperal_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1, + dnr3->temperal_curve[pos + 1]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2, + dnr3->temperal_curve[pos + 2]); + } else { + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1, + dnr3->temperal_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2, + dnr3->temperal_curve[pos + 1]); + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_t[i]), regVal); + } + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_UPDATE_SPACIAL, update_spacial); + REG_SET_SLICE(regVal, DENOISE3D_UPDATE_TEMPERAL, update_temperal); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_dummy_hblank), 0x80); +} + +int isp_u_3dnr_strength(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR + //pr_err("Not supported 3dnr\n"); + return -1; +#else + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 isp_ctrl; + u32 isp_denoise3d_strength; + + isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + return 0; +#endif +} + +int isp_s_3dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR + //pr_err("Not supported 3dnr\n"); + return -1; +#else + u32 isp_denoise3d_ctrl; + + struct isp_3dnr_context *dnr3 = &dev->dnr3; + + u32 isp_denoise3d_strength, isp_denoise3d_motion, isp_denoise3d_delta_inv; + + pr_info("enter %s\n", __func__); + if (dnr3->update_bin) { + dnr3_hw_init(dev); + } + + isp_denoise3d_motion = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), + isp_denoise3d_motion); + isp_denoise3d_delta_inv = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), + isp_denoise3d_delta_inv); + + isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); +#ifndef NR200 + if (!dnr3->enable) { + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, 0); + } else { + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength); + isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl)); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl); + + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength); +#else + isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl)); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl); + + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); +#endif + return 0; +#endif +} + +int isp_s_3dnr_motion(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR + pr_err("Not supported 3dnr\n"); + return -1; +#else + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 isp_denoise3d_motion; + u32 isp_ctrl; + + isp_denoise3d_motion = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), + isp_denoise3d_motion); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); +#endif + return 0; +} + +int isp_s_3dnr_delta(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR + pr_err("Not supported 3dnr\n"); + return -1; +#else + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 isp_denoise3d_delta_inv; + u32 isp_ctrl; + + isp_denoise3d_delta_inv = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), + isp_denoise3d_delta_inv); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); +#endif + + return 0; +} + +int isp_u_3dnr(struct isp_ic_dev *dev, struct isp_3dnr_update *dnr3_update) +{ +#ifndef ISP_3DNR + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + u32 regVal = 0; + + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH, dev->dnr3.strength); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_h)); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, + dnr3_update->thr_edge_h_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_v)); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, + dnr3_update->thr_edge_v_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_s)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, + dnr3_update->thr_range_s_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_t)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, dnr3_update->range_t_h); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, dnr3_update->range_t_v); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, + dnr3_update->thr_range_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, dnr3_update->range_d); + REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, + dnr3_update->thr_motion_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, + dnr3_update->thr_delta_h_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, + dnr3_update->thr_delta_v_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, + dnr3_update->thr_delta_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal); + +#ifdef NR200 + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); +#endif + return 0; +#endif +} + +int isp_g_3dnr(struct isp_ic_dev *dev, u32 * avg) +{ + if (!dev || !avg) { + return -EINVAL; + } + *avg = isp_read_reg(dev, REG_ADDR(isp_denoise3d_average)); + return 0; +} + +int isp_r_3dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR + return -1; +#else + u32 in_width, in_height; + u32 size, lval; + u32 miv2_sp2_bus_id; + u32 miv2_sp2_fmt; + + u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc)); + u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl)); + + //SP2_RAW_PATH_ENABLE is shadow bit, need set SP2_MI_CFG_UPD to update to shadow. + //So here config before set SP2_MI_CFG_UPD + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW_PATH_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + + +#ifndef NR200 + in_width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size)); + in_height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size)); +#else + in_width = isp_read_reg(dev, REG_ADDR(isp_out_h_size)); + in_height = isp_read_reg(dev, REG_ADDR(isp_out_v_size)); +#endif + lval = (in_width * 12 + 127)/ 128; + + lval <<= 4; + + size = in_height * lval; //raw12 unaligned + //write reference frame config + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_base_ad_init), dev->dnr3.pa); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_size_init), size); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_offs_cnt_init), 0); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_height), in_height); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_size), size); + + miv2_sp2_bus_id = isp_read_reg(dev, REG_ADDR(miv2_sp2_bus_id)); + + REG_SET_SLICE(miv2_sp2_bus_id, SP2_WR_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_BURST_LEN, 2); //sp2 rd burst lenghth 16 + REG_SET_SLICE(miv2_sp2_bus_id, SP2_BUS_SW_EN, 1); + + isp_write_reg(dev, REG_ADDR(miv2_sp2_bus_id), miv2_sp2_bus_id); + + miv2_sp2_fmt = isp_read_reg(dev, REG_ADDR(miv2_sp2_fmt)); + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_ALIGNED, 0); //unaligned + + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_ALIGNED, 0); //unaligned + + isp_write_reg(dev, REG_ADDR(miv2_sp2_fmt), miv2_sp2_fmt); + + //read reference frame config + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), dev->dnr3.pa); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_lval), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_size), size); + + + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1); + + /* we successfully programmed a buffer to marvin, so we need + * to enable updateing of base and offset registers */ + miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK); + isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl); + + miv2_imsc |= SP2_DMA_RAW_READY_MASK; + isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc); + + return 0; +#endif +} +#endif diff --git a/vvcam/isp/isp_3dnr2.c b/vvcam/isp/isp_3dnr2.c new file mode 100755 index 0000000..9721f44 --- /dev/null +++ b/vvcam/isp/isp_3dnr2.c @@ -0,0 +1,433 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +#ifdef ISP_3DNR_V2 + +extern MrvAllRegister_t *all_regs; + +static void dnr3_hw_init(struct isp_ic_dev *dev) +{ + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 regVal = 0; + int i, pos; + /* spacial */ + u32 update_spacial = 900; + u32 strength_curve_spacial = 64; + u32 thr_edge_v_inv = 1024; + u32 thr_edge_h_inv = 1024; + u32 thr_range_s_inv = 1024; + /* temperal */ + u32 update_temperal = 1020; + u32 strength_curve_temperal = 64; + u32 range_t_h = 1; + u32 range_t_v = 1; + u32 thr_range_t_inv = 1024; + u32 thr_motion_inv = 1024; + u32 range_d = 1; + u32 thr_delta_h_inv = 1023; + u32 thr_delta_v_inv = 1023; + u32 thr_delta_t_inv = 1023; + u32 strength = dnr3->strength; + strength = MIN(MAX(strength, 0), 128); + + if (dnr3->init) { //for 3dnr init + u32 isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl)); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_READ_REF_EN, 1); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_WRITE_REF_EN, 1); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_HORIZONTAL_EN, + dnr3->enable_h); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_VERTICAL_EN, + dnr3->enable_v); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_TEMPERAL_EN, + dnr3->enable_temperal); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_DILATE_EN, + dnr3->enable_dilate); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl); + + } + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_SPACIAL, + strength_curve_spacial); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, thr_edge_h_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_TEMPERAL, + strength_curve_temperal); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, thr_edge_v_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, thr_range_s_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, range_t_h); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, range_t_v); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, thr_range_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, range_d); + REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, thr_motion_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, thr_delta_h_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, thr_delta_v_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, thr_delta_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal); + /* spacial */ + + for (i = 0; i < 6; i++) { + regVal = 0; + pos = i * 3; + if (i < 5) { + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE0, + dnr3->spacial_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1, + dnr3->spacial_curve[pos + 1]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2, + dnr3->spacial_curve[pos + 2]); + } else { + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1, + dnr3->spacial_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2, + dnr3->spacial_curve[pos + 1]); + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_s[i]), regVal); + regVal = 0; + if (i < 5) { + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE0, + dnr3->temperal_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1, + dnr3->temperal_curve[pos + 1]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2, + dnr3->temperal_curve[pos + 2]); + } else { + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1, + dnr3->temperal_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2, + dnr3->temperal_curve[pos + 1]); + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_t[i]), regVal); + } + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_UPDATE_SPACIAL, update_spacial); + REG_SET_SLICE(regVal, DENOISE3D_UPDATE_TEMPERAL, update_temperal); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal); +} + +int isp_s_3dnr_cmp(struct isp_ic_dev *dev) { + + struct isp_3dnr_compress_context *compress = &dev->dnr3.compress; + + u32 isp_denoise3d_weight1 = 0; // isp_read_reg(dev, REG_ADDR(isp_denoise3d_weight1)); + u32 isp_denoise3d_weight2 = 0; // isp_read_reg(dev, REG_ADDR(isp_denoise3d_weight2)); + int i = 0; + for (i = 0; i < 4; i++) { + isp_denoise3d_weight1 |= (compress->weight_down[i] & DENOISE3D_WEIGHT_MASK) << (3 - i) * 4; + } + REG_SET_SLICE(isp_denoise3d_weight1, DENOISE3D_WEIGHT_UP_Y0, compress->weight_up_y[0]); + REG_SET_SLICE(isp_denoise3d_weight1, DENOISE3D_WEIGHT_UP_Y1, compress->weight_up_y[1]); + + for (i = 0; i < 8; i++) { + isp_denoise3d_weight2 |= (compress->weight_up[i] & DENOISE3D_WEIGHT_MASK) << (7 - i) * 4; + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_weight1), isp_denoise3d_weight1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_weight2), isp_denoise3d_weight2); + return 0; +} + +int isp_s_3dnr(struct isp_ic_dev *dev) +{ + + struct isp_3dnr_context *dnr3 = &dev->dnr3; + + u32 isp_denoise3d_strength, isp_denoise3d_motion, isp_denoise3d_delta_inv; + u32 isp_denoise3d_ctrl; + + pr_info("enter %s\n", __func__); + if (dnr3->update_bin) { + dnr3_hw_init(dev); + } + + isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); + if (!dnr3->enable) { + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, 0); + } else { + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength); + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), + isp_denoise3d_strength); + + isp_denoise3d_motion = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), + isp_denoise3d_motion); + isp_denoise3d_delta_inv = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), + isp_denoise3d_delta_inv); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_dummy_hblank), 0x80); + + + isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl)); + + if (dnr3->enable) { + isp_s_3dnr_cmp(dev); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, 1); + } + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl); + + + return 0; +} + + +int isp_s_3dnr_motion(struct isp_ic_dev *dev) +{ + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 isp_denoise3d_motion; + u32 isp_ctrl; + + isp_denoise3d_motion = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), + isp_denoise3d_motion); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + return 0; +} + +int isp_s_3dnr_delta(struct isp_ic_dev *dev) +{ + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 isp_denoise3d_delta_inv; + u32 isp_ctrl; + + isp_denoise3d_delta_inv = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), + isp_denoise3d_delta_inv); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + return 0; +} + +int isp_u_3dnr(struct isp_ic_dev *dev, struct isp_3dnr_update *dnr3_update) +{ + + u32 regVal = 0; + + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH, dev->dnr3.strength); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_h)); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, + dnr3_update->thr_edge_h_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_v)); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, + dnr3_update->thr_edge_v_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_s)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, + dnr3_update->thr_range_s_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_t)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, dnr3_update->range_t_h); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, dnr3_update->range_t_v); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, + dnr3_update->thr_range_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, dnr3_update->range_d); + REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, + dnr3_update->thr_motion_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, + dnr3_update->thr_delta_h_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, + dnr3_update->thr_delta_v_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, + dnr3_update->thr_delta_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal); + + return 0; +} + +int isp_g_3dnr(struct isp_ic_dev *dev, u32 * avg) +{ + if (!dev || !avg) { + return -EINVAL; + } + *avg = isp_read_reg(dev, REG_ADDR(isp_denoise3d_average)); + return 0; +} + +int isp_u_3dnr_strength(struct isp_ic_dev *dev) +{ + uint32_t isp_denoise3d_strength; + + isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dev->dnr3.strength); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength); + return 0; +} + + +int isp_r_3dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR_V2_V1 + return -1; +#else + u32 in_width, in_height; + u32 size, lval; + u32 miv2_sp2_bus_id; + u32 miv2_sp2_fmt; + + u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc)); + u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl)); + + //SP2_RAW_PATH_ENABLE is shadow bit, need set SP2_MI_CFG_UPD to update to shadow. + //So here config before set SP2_MI_CFG_UPD + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW_PATH_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + + in_width = isp_read_reg(dev, REG_ADDR(isp_out_h_size)); + in_height = isp_read_reg(dev, REG_ADDR(isp_out_v_size)); + + lval = (in_width * 12 + 127)/ 128; + + lval <<= 4; + + size = in_height * lval; //raw12 unaligned + //write reference frame config + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_base_ad_init), dev->dnr3.pa); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_size_init), size); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_offs_cnt_init), 0); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_height), in_height); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_size), size); + + miv2_sp2_bus_id = isp_read_reg(dev, REG_ADDR(miv2_sp2_bus_id)); + + REG_SET_SLICE(miv2_sp2_bus_id, SP2_WR_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_BURST_LEN, 2); //sp2 rd burst lenghth 16 + REG_SET_SLICE(miv2_sp2_bus_id, SP2_BUS_SW_EN, 1); + + isp_write_reg(dev, REG_ADDR(miv2_sp2_bus_id), miv2_sp2_bus_id); + + miv2_sp2_fmt = isp_read_reg(dev, REG_ADDR(miv2_sp2_fmt)); + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_ALIGNED, 0); //unaligned + + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_ALIGNED, 0); //unaligned + + isp_write_reg(dev, REG_ADDR(miv2_sp2_fmt), miv2_sp2_fmt); + + //read reference frame config + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), dev->dnr3.pa); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_lval), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_size), size); + + + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1); + + /* we successfully programmed a buffer to marvin, so we need + * to enable updateing of base and offset registers */ + miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK); + isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl); + + miv2_imsc |= SP2_DMA_RAW_READY_MASK; + isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc); + + return 0; +#endif +} +#endif diff --git a/vvcam/isp/isp_compand.c b/vvcam/isp/isp_compand.c new file mode 100755 index 0000000..f08fae2 --- /dev/null +++ b/vvcam/isp/isp_compand.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; + +int isp_s_comp(struct isp_ic_dev *dev) +{ +#ifndef ISP_COMPAND + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_comp_context *comp = &dev->comp; + int ri, valr; + uint32_t x_data; + uint32_t y_data; + u32 isp_compand_ctrl = isp_read_reg(dev, REG_ADDR(isp_compand_ctrl)); + + /*pr_debug("enter %s\n", __func__);*/ + if (comp->bls.enable) { + isp_write_reg(dev, REG_ADDR(isp_compand_bls_a_fixed), comp->bls.a << (20 - comp->bls.bit_width)); + isp_write_reg(dev, REG_ADDR(isp_compand_bls_b_fixed), comp->bls.b << (20 - comp->bls.bit_width)); + isp_write_reg(dev, REG_ADDR(isp_compand_bls_c_fixed), comp->bls.c << (20 - comp->bls.bit_width)); + isp_write_reg(dev, REG_ADDR(isp_compand_bls_d_fixed), comp->bls.d << (20 - comp->bls.bit_width)); + } + + if (!comp->enable) { + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_BLS_ENABLE, 0); + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_COMPRESS_ENABLE, 0); + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_EXPAND_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_compand_ctrl), isp_compand_ctrl); + return 0; + } + + if (comp->expand.enable && comp->expand.update_curve) { + for (ri = 0; ri < 10; ri++) { + valr = (comp->expand.px[ri * 6 + 0] + (20-comp->expand.in_bit)) | + ((comp->expand.px[ri * 6 + 1] + (20-comp->expand.in_bit)) << 5) | + ((comp->expand.px[ri * 6 + 2] + (20-comp->expand.in_bit)) << 10) | + ((comp->expand.px[ri * 6 + 3] + (20-comp->expand.in_bit)) << 15) | + ((comp->expand.px[ri * 6 + 4] + (20-comp->expand.in_bit)) << 20) | + ((comp->expand.px[ri * 6 + 5] + (20-comp->expand.in_bit)) << 25); + isp_write_reg(dev, REG_ADDR(isp_compand_expand_px_0) + ri * 4, valr); + } + valr = ( comp->expand.px[60] + (20-comp->expand.in_bit)) | + ((comp->expand.px[61] + (20-comp->expand.in_bit)) << 5) | + ((comp->expand.px[62] + (20-comp->expand.in_bit)) << 10) | + ((comp->expand.px[63] + (20-comp->expand.in_bit)) << 15); + isp_write_reg(dev, REG_ADDR(isp_compand_expand_px_10), valr); + + isp_write_reg(dev, REG_ADDR(isp_compand_expand_x_addr), 0x0); + for (ri = 0; ri < 63; ri++) { + x_data = (comp->expand.x_data[ri] << (20 - comp->expand.in_bit)); + isp_write_reg(dev, REG_ADDR(isp_compand_expand_x_write_data), x_data); + } + + isp_write_reg(dev, REG_ADDR(isp_compand_expand_y_addr), 0x0); + for (ri = 0; ri < 64; ri++) { + y_data = (comp->expand.y_data[ri] << (20 - comp->expand.out_bit)); + isp_write_reg(dev, REG_ADDR(isp_compand_expand_y_write_data), y_data); + } + + } + + if (comp->compress.enable && comp->compress.update_curve) { + for (ri = 0; ri < 10; ri++) { + valr = comp->compress.px[ri * 6 + 0] | + (comp->compress.px[ri * 6 + 1] << 5) | + (comp->compress.px[ri * 6 + 2] << 10) | + (comp->compress.px[ri * 6 + 3] << 15) | + (comp->compress.px[ri * 6 + 4] << 20) | + (comp->compress.px[ri * 6 + 5] << 25); + isp_write_reg(dev, REG_ADDR(isp_compand_compress_px_0) + ri * 4, valr); + } + valr = comp->compress.px[60] | (comp->compress.px[61] << 5) | (comp->compress.px[62] << 10) | (comp->compress.px[63] << 15); + isp_write_reg(dev, REG_ADDR(isp_compand_compress_px_10), valr); + + isp_write_reg(dev, REG_ADDR(isp_compand_compress_x_addr), 0x0); + for (ri = 0; ri < 63; ri++) { + x_data = (comp->compress.x_data[ri] << (20 - comp->compress.in_bit)); + isp_write_reg(dev, REG_ADDR(isp_compand_compress_x_write_data), x_data); + } + + isp_write_reg(dev, REG_ADDR(isp_compand_compress_y_addr), 0x0); + for (ri = 0; ri < 64; ri++) { + y_data = (comp->compress.y_data[ri] << (20 - comp->compress.out_bit)); + isp_write_reg(dev, REG_ADDR(isp_compand_compress_y_write_data), y_data); + } + } + + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_BLS_ENABLE, comp->bls.enable); + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_COMPRESS_ENABLE, comp->compress.enable); + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_EXPAND_ENABLE, comp->expand.enable); + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_EXPAND_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_compand_ctrl), isp_compand_ctrl); + + return 0; +#endif +} diff --git a/vvcam/isp/isp_dmsc2.c b/vvcam/isp/isp_dmsc2.c new file mode 100755 index 0000000..c9efb62 --- /dev/null +++ b/vvcam/isp/isp_dmsc2.c @@ -0,0 +1,432 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; +#ifdef ISP_DEMOSAIC2 +int isp_enable_dmsc(struct isp_ic_dev *dev) +{ + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + u32 isp_dmsc_size_ctrl = + isp_read_reg(dev, REG_ADDR(isp_dmsc_size_ctrl)); + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_BYPASS, 0U); + REG_SET_SLICE(isp_dmsc_size_ctrl, ISP_DMSC_IMAGE_H_SIZE, + isp_read_reg(dev, REG_ADDR(isp_acq_h_size))); + REG_SET_SLICE(isp_dmsc_size_ctrl, ISP_DMSC_IMAGE_H_BLANK, 0x039c); + isp_write_reg(dev, REG_ADDR(isp_dmsc_size_ctrl), isp_dmsc_size_ctrl); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl_shd), isp_dmsc_ctrl); + return 0; +} + +int isp_disable_dmsc(struct isp_ic_dev *dev) +{ + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + isp_dmsc_ctrl = 0; //clear fpga default bit 3 and 13 to keep the same value with cmodel. + + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_BYPASS, 1U); + + /*clear the reg default val to keep weith cmodel */ + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_fact), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_clip), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt2), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb), 0); + //isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_a), 0); + //isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_c), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; +} + +int isp_set_dmsc_intp(struct isp_ic_dev *dev) +{ + u32 isp_dmsc_intp_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_intp_thr)); + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_dmsc_intp_thr, ISP_DMSC_INTERPLATION_DIR_THR_MAX, + dev->demosaic.intp.intp_dir_thr_max); + REG_SET_SLICE(isp_dmsc_intp_thr, ISP_DMSC_INTERPLATION_DIR_THR_MIN, + dev->demosaic.intp.intp_dir_thr_min); + isp_write_reg(dev, REG_ADDR(isp_dmsc_intp_thr), isp_dmsc_intp_thr); + return 0; +} + +int isp_set_dmsc_dmoi(struct isp_ic_dev *dev) +{ + + struct isp_dmoi_context *pDemoire = &dev->demosaic.demoire; + u32 isp_dmsc_dmoi_ctrl = + isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl)); + u32 isp_dmsc_dmoi_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr)); + u32 isp_dmsc_dmoi_patn_thr = + isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_patn_thr)); + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + + pr_info("enter %s\n", __func__); + + if (!pDemoire->enable) { + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEMOIRE_ENABLE, 0U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_dmoi_ctrl, ISP_DMSC_DEMOIRE_AREA_THR, + pDemoire->demoire_area_thr); + REG_SET_SLICE(isp_dmsc_dmoi_ctrl, ISP_DMSC_DEMOIRE_SAT_SHRINK, + pDemoire->demoire_sat_shrink); + REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_R2, + pDemoire->demoire_r2); + REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_R1, + pDemoire->demoire_r1); + REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_T2_SHIFT, + pDemoire->demoire_t2_shift); + REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_T1, + pDemoire->demoire_t1); + REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_R2, + pDemoire->demoire_edge_r2); + REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_R1, + pDemoire->demoire_edge_r1); + REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT, + pDemoire->demoire_edge_t2_shift); + REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_T1, + pDemoire->demoire_edge_t1); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl), isp_dmsc_dmoi_ctrl); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr), isp_dmsc_dmoi_thr); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_patn_thr), + isp_dmsc_dmoi_patn_thr); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEMOIRE_ENABLE, 1U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; +} + +int isp_set_dmsc_sharpen(struct isp_ic_dev *dev) +{ + struct isp_shap_context *pSharpen = &dev->demosaic.sharpen; + u32 isp_dmsc_shap_fact = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_fact)); + u32 isp_dmsc_shap_clip = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_clip)); + u32 isp_dmsc_shap_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_thr)); + u32 isp_dmsc_shap_ratio = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_ratio)); + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + + pr_info("enter %s\n", __func__); + + if (!pSharpen->enable) { + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_ENBALE, 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl_shd), isp_dmsc_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_shap_fact, ISP_DMSC_SHARPEN_FACTOR_BLACK, + pSharpen->sharpen_factor_black); + REG_SET_SLICE(isp_dmsc_shap_fact, ISP_DMSC_SHARPEN_FACTOR_WHITE, + pSharpen->sharpen_factor_white); + REG_SET_SLICE(isp_dmsc_shap_clip, ISP_DMSC_SHARPEN_CLIP_BLACK, + pSharpen->sharpen_clip_black); + REG_SET_SLICE(isp_dmsc_shap_clip, ISP_DMSC_SHARPEN_CLIP_WHITE, + pSharpen->sharpen_clip_white); + REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T4_SHIFT, + pSharpen->sharpen_t4_shift); + REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T3, + pSharpen->sharpen_t3); + REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T2_SHIFT, + pSharpen->sharpen_t2_shift); + REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T1, + pSharpen->sharpen_t1); + REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R3, + pSharpen->sharpen_r3); + REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R2, + pSharpen->sharpen_r2); + REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R1, + pSharpen->sharpen_r1); + + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_fact), isp_dmsc_shap_fact); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_clip), isp_dmsc_shap_clip); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_thr), isp_dmsc_shap_thr); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_ratio), isp_dmsc_shap_ratio); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_ENBALE, 1); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + return 0; +} + +int isp_set_dmsc_gfilter(struct isp_ic_dev *dev) +{ + struct isp_gfilter_context *pgfilter = &dev->demosaic.gFilter; + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + u32 isp_dmsc_shap_filt1 = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_filt1)); + u32 isp_dmsc_shap_filt2 = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_filt2)); + pr_info("enter %s\n", __func__); + + REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_00, + pgfilter->hf_filt_00); + REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_01, + pgfilter->hf_filt_01); + REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_02, + pgfilter->hf_filt_02); + REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_10, + pgfilter->hf_filt_10); + REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_11, + pgfilter->hf_filt_11); + REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_12, + pgfilter->hf_filt_12); + REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_20, + pgfilter->hf_filt_20); + REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_21, + pgfilter->hf_filt_21); + REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_22, + pgfilter->hf_filt_22); + + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt1), isp_dmsc_shap_filt1); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt2), isp_dmsc_shap_filt2); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_SIZE, pgfilter->sharpen_size); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + return 0; +} + +int isp_set_dmsc_sharpen_line(struct isp_ic_dev *dev) +{ + struct isp_shap_line_context *sharpenLine = &dev->demosaic.sharpenLine; + + u32 isp_dmsc_shap_line_ctrl = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_line_ctrl)); + u32 isp_dmsc_shap_line_ratio = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_line_ratio)); + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + + pr_info("enter %s\n", __func__); + + if (!sharpenLine->enable) { + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_LINE_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_SHIFT2, + sharpenLine->sharpen_line_shift2); + REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_SHIFT1, + sharpenLine->sharpen_line_shift1); + REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_T1, + sharpenLine->sharpen_line_t1); + REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_STRENGTH, + sharpenLine->sharpen_line_strength); + REG_SET_SLICE(isp_dmsc_shap_line_ratio, ISP_DMSC_SHARPEN_LINE_R2, + sharpenLine->sharpen_line_r2); + REG_SET_SLICE(isp_dmsc_shap_line_ratio, ISP_DMSC_SHARPEN_LINE_R1, + sharpenLine->sharpen_line_r1); + + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_line_ctrl), + isp_dmsc_shap_line_ctrl); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_line_ratio), + isp_dmsc_shap_line_ratio); + + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_LINE_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + return 0; +} + +int isp_set_dmsc_cac(struct isp_ic_dev *dev) +{ + struct isp_cac_context *cac = &dev->cac; + u32 val = 0; + u32 isp_dmsc_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl)); + + pr_info("enter %s\n", __func__); + + if (!cac->enable) { + REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_CAC_EN, 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl), + isp_dmsc_cac_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode); + REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_count_start), + cac->hstart | (cac->vstart << 16)); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_a), cac->ar | (cac->ab << 16)); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_b), cac->br | (cac->bb << 16)); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_c), cac->cr | (cac->cb << 16)); + + REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns); + REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_x_norm), val); + val = 0; + REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns); + REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_y_norm), val); + REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_CAC_EN, 1); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl), isp_dmsc_cac_ctrl); + + return 0; +} + +int isp_set_dmsc_depurple(struct isp_ic_dev *dev) +{ + struct isp_depurple_context *depurple = &dev->demosaic.depurple; + u32 isp_dmsc_dpul_ctrl = + isp_read_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl)); + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + + pr_info("enter %s\n", __func__); + if (!depurple->enable) { + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEPURPLE_ENABLE, 0U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_RED_SAT, depurple->red_sat); + REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_BLUE_SAT, depurple->blue_sat); + REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_SAT_SHRINK, + depurple->depurple_sat_shrink); + REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_THR, + depurple->depurple_thr); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl), isp_dmsc_dpul_ctrl); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEPURPLE_ENABLE, 1U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + return 0; +} + +int isp_set_dmsc_skin(struct isp_ic_dev *dev) +{ + struct isp_skin_context *skin = &dev->demosaic.skin; + u32 isp_dmsc_skin_thr_cb = + isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb)); + u32 isp_dmsc_skin_thr_cr = + isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr)); + u32 isp_dmsc_skin_thr_y = + isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y)); + + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + + pr_info("enter %s\n", __func__); + if (!skin->enable) { + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SKIN_ENABLE, 0U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_skin_thr_cb, ISP_DMSC_SKIN_CB_THR_MAX_2047, + skin->cb_thr_max_2047); + REG_SET_SLICE(isp_dmsc_skin_thr_cb, ISP_DMSC_SKIN_CB_THR_MIN_2047, + skin->cb_thr_min_2047); + REG_SET_SLICE(isp_dmsc_skin_thr_cr, ISP_DMSC_SKIN_CR_THR_MAX_2047, + skin->cr_thr_max_2047); + REG_SET_SLICE(isp_dmsc_skin_thr_cr, ISP_DMSC_SKIN_CR_THR_MIN_2047, + skin->cr_thr_min_2047); + REG_SET_SLICE(isp_dmsc_skin_thr_y, ISP_DMSC_SKIN_Y_THR_MAX, + skin->y_thr_max_2047); + REG_SET_SLICE(isp_dmsc_skin_thr_y, ISP_DMSC_SKIN_Y_THR_MIN, + skin->y_thr_min_2047); + + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb), + isp_dmsc_skin_thr_cb); + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr), + isp_dmsc_skin_thr_cr); + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y), isp_dmsc_skin_thr_y); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SKIN_ENABLE, 1U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + return 0; +} + +int isp_s_dmsc(struct isp_ic_dev *dev) +{ + u32 isp_dmsc_ctrl; + /*Clear the cmodel register default value to match the fpga default value */ + isp_disable_dmsc(dev); + + isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + pr_info("enter %s\n", __func__); + if (!dev->demosaic.enable) { + isp_disable_dmsc(dev); + return 0; + } + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_THR, + dev->demosaic.demosaic_thr); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DENOISE_STRENGTH, + dev->demosaic.denoise_stren); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + isp_set_dmsc_intp(dev); + isp_set_dmsc_dmoi(dev); + isp_set_dmsc_skin(dev); + isp_enable_dmsc(dev); + isp_set_dmsc_depurple(dev); + isp_set_dmsc_sharpen_line(dev); + isp_set_dmsc_sharpen(dev); + isp_set_dmsc_gfilter(dev); + + return 0; +} + +#endif diff --git a/vvcam/isp/isp_dpf.c b/vvcam/isp/isp_dpf.c new file mode 100755 index 0000000..ac6a109 --- /dev/null +++ b/vvcam/isp/isp_dpf.c @@ -0,0 +1,193 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#else +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; + +int isp_s_dpf(struct isp_ic_dev *dev) +{ + struct isp_dpf_context *dpf = &dev->dpf; + u32 value; + int i = 0; + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + u32 isp_dpf_mode = isp_read_reg(dev, REG_ADDR(isp_dpf_mode)); + + //pr_info("enter %s\n", __func__); + + if (!dpf->enable) { + isp_write_reg(dev, REG_ADDR(isp_dpf_mode), + isp_dpf_mode & ~MRV_DPF_DPF_ENABLE_MASK); + return 0; + } + + isp_dpf_mode &= + (MRV_DPF_DPF_ENABLE_MASK | MRV_DPF_NLL_SEGMENTATION_MASK); + + switch (dpf->gain_usage) { + case IC_DPF_GAIN_USAGE_DISABLED: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 0); + break; + case IC_DPF_GAIN_USAGE_NF_GAINS: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 1); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1); + break; + case IC_DPF_GAIN_USAGE_LSC_GAINS: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 0); + break; + case IC_DPF_GAIN_USAGE_NF_LSC_GAINS: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 1); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1); + break; + case IC_DPF_GAIN_USAGE_AWB_GAINS: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1); + break; + case IC_DPF_GAIN_USAGE_AWB_LSC_GAINS: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1); + break; + default: + /*pr_err("%s: unsupported gain usage\n", __func__);*/ + break; + } + + switch (dpf->filter_type) { + case IC_DPF_RB_FILTERSIZE_13x9: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_RB_FILTER_SIZE, 0U); + break; + case IC_DPF_RB_FILTERSIZE_9x9: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_RB_FILTER_SIZE, 1U); + break; + default: + /*pr_err + ("%s: unsupported filter kernel size for red/blue pixel\n", + __func__);*/ + break; + } + + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_R_FILTER_OFF, dpf->filter_r_off); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_GR_FILTER_OFF, dpf->filter_gr_off); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_GB_FILTER_OFF, dpf->filter_gb_off); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_B_FILTER_OFF, dpf->filter_b_off); + value = 0; + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G1, dpf->weight_g[0]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G2, dpf->weight_g[1]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G3, dpf->weight_g[2]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G4, dpf->weight_g[3]); + isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_g_1_4), value); + value = 0; + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G5, dpf->weight_g[4]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G6, dpf->weight_g[5]); + isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_g_5_6), value); + value = 0; + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB1, dpf->weight_rb[0]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB2, dpf->weight_rb[1]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB3, dpf->weight_rb[2]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB4, dpf->weight_rb[3]); + isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_rb_1_4), value); + value = 0; + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB5, dpf->weight_rb[4]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB6, dpf->weight_rb[5]); + isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_rb_5_6), value); + isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_r), dpf->nf_gain_r); + isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_gr), dpf->nf_gain_gr); + isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_gb), dpf->nf_gain_gb); + isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_b), dpf->nf_gain_b); + isp_write_reg(dev, REG_ADDR(isp_dpf_strength_r), + (MRV_DPF_INV_WEIGHT_R_MASK & dpf->strength_r)); + isp_write_reg(dev, REG_ADDR(isp_dpf_strength_g), + (MRV_DPF_INV_WEIGHT_G_MASK & dpf->strength_g)); + isp_write_reg(dev, REG_ADDR(isp_dpf_strength_b), + (MRV_DPF_INV_WEIGHT_B_MASK & dpf->strength_b)); + + for (i = 0; i < 17; i++) { + if (dpf->denoise_talbe[i] <= MRV_DPF_NLL_COEFF_N_MASK) { + isp_write_reg(dev, + REG_ADDR(nlf_lookup_table_block_arr[i]), + dpf->denoise_talbe[i]); + } + } + + switch (dpf->x_scale) { + case IC_NLL_SCALE_LINEAR: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_NLL_SEGMENTATION, 0); + break; + case IC_NLL_SCALE_LOGARITHMIC: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_NLL_SEGMENTATION, 1); + break; + default: + break; + } + + isp_write_reg(dev, REG_ADDR(isp_dpf_mode), isp_dpf_mode); + isp_write_reg(dev, REG_ADDR(isp_dpf_mode), + isp_dpf_mode | MRV_DPF_DPF_ENABLE_MASK); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + return 0; +} diff --git a/vvcam/isp/isp_gcmono.c b/vvcam/isp/isp_gcmono.c new file mode 100755 index 0000000..3ab59cf --- /dev/null +++ b/vvcam/isp/isp_gcmono.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#else +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; + +int isp_enable_gcmono(struct isp_ic_dev *dev) +{ +#ifndef ISP_GCMONO + pr_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_gcmono_ctrl = isp_read_reg(dev, REG_ADDR(isp_gcmono_ctrl)); + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_gcmono_ctrl, ISP_GCMONO_CFG_DONE, 1); + REG_SET_SLICE(isp_gcmono_ctrl, ISP_GCMONO_SWITCH, + ISP_GCMONO_SWITCH_ENABLE); + isp_write_reg(dev, REG_ADDR(isp_gcmono_ctrl), isp_gcmono_ctrl); + REG_SET_SLICE(isp_ctrl, ISP_GCMONO_MODE, dev->gcmono.mode); + REG_SET_SLICE(isp_ctrl, ISP_GCMONO_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + dev->gcmono.enable = true; + return 0; +#endif +} + +int isp_disable_gcmono(struct isp_ic_dev *dev) +{ +#ifndef ISP_GCMONO + pr_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_gcmono_ctrl = isp_read_reg(dev, REG_ADDR(isp_gcmono_ctrl)); + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_gcmono_ctrl, ISP_GCMONO_SWITCH, + ISP_GCMONO_SWITCH_DISABLE); + isp_write_reg(dev, REG_ADDR(isp_gcmono_ctrl), isp_gcmono_ctrl); + REG_SET_SLICE(isp_ctrl, ISP_GCMONO_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + dev->gcmono.enable = false; + return 0; +#endif +} + +#ifdef ISP_GCMONO +static int isp_s_gcmonopx(struct isp_ic_dev *dev, struct isp_gcmono_data *data) +{ + u32 isp_gc_px_reg = REG_ADDR(isp_gcmono_px_0); + u32 *p_table = NULL; + int i; + u32 gc_px_data = 0; + + pr_info("enter %s\n", __func__); + p_table = (u32 *)&data->px; + for (i = 0; i < 64; i++) { + gc_px_data |= (*(p_table + i) << (i % 6 * 5)); + if (i % 6 == 5 || i == 63) { + isp_write_reg(dev, isp_gc_px_reg, gc_px_data); + isp_gc_px_reg += 4; + gc_px_data = 0; + } + } + return 0; +} +#endif + +#ifdef ISP_GCMONO +static int isp_s_gcmonoWriteData(struct isp_ic_dev *dev, u32 *tblX, u32 *tblY) +{ + u32 isp_gc_y_data, isp_gc_x_data; + // u32 *p_table = NULL; + int i; + // u32 gc_px_data = 0; + + pr_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(isp_gcmono_y_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_gcmono_x_addr), 0); + for (i = 0; i < 64; i++) { + isp_gc_y_data = *(tblY + i); + isp_write_reg(dev, REG_ADDR(isp_gcmono_y_write_data), + isp_gc_y_data); + } + for (i = 0; i < 63; i++) { + isp_gc_x_data = *(tblX + i); + isp_write_reg(dev, REG_ADDR(isp_gcmono_x_write_data), + isp_gc_x_data); + } + return 0; +} +#endif + +int isp_s_gcmono(struct isp_ic_dev *dev, struct isp_gcmono_data *data) +{ +#ifndef ISP_GCMONO + pr_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_gcmono_ctrl = isp_read_reg(dev, REG_ADDR(isp_gcmono_ctrl)); + u32 isp_gc_para_base = 0; + u8 *p_table = NULL; + int i; + + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_gcmono_ctrl, ISP_GCMONO_SWITCH, + ISP_GCMONO_SWITCH_DISABLE); + REG_SET_SLICE(isp_gcmono_ctrl, ISP_GCMONO_CFG_DONE, + ISP_GCMONO_CFG_DONE_SET_CURVE); + isp_write_reg(dev, REG_ADDR(isp_gcmono_ctrl), isp_gcmono_ctrl); + p_table = (u8 *)&data->basePara; + for (i = 0; i < 1024; i++) { + isp_gc_para_base |= (*(p_table + i) << (i % 4 * 8)); + if (i % 4 == 3) { + isp_write_reg(dev, REG_ADDR(isp_gcmono_para_base), + isp_gc_para_base); + isp_gc_para_base = 0; + } + } + isp_s_gcmonopx(dev, data); + isp_s_gcmonoWriteData(dev, data->dataX, data->dataY); + if (dev->gcmono.enable) { + isp_enable_gcmono(dev); + } + return 0; +#endif +} diff --git a/vvcam/isp/isp_hdr.c b/vvcam/isp/isp_hdr.c new file mode 100755 index 0000000..fd6a733 --- /dev/null +++ b/vvcam/isp/isp_hdr.c @@ -0,0 +1,259 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; + +int isp_s_hdr(struct isp_ic_dev *dev) +{ + struct isp_hdr_context *hdr = &dev->hdr; + u32 isp_stitching_ctrl = + isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl)); + u32 val; + int i; + + pr_info("enter %s\n", __func__); + + val = 0; +#if 0 + REG_SET_SLICE(val, STITCHING_FRAME_WIDTH, hdr->width); + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_FRAME_HEIGHT, hdr->height); + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_L_BIT_DEPTH, hdr->l_bit_dep); + REG_SET_SLICE(val, STITCHING_S_BIT_DEPTH, hdr->s_bit_dep); + REG_SET_SLICE(val, STITCHING_VS_BIT_DEPTH, hdr->vs_bit_dep); + REG_SET_SLICE(val, STITCHING_LS_BIT_DEPTH, hdr->ls_bit_dep); + isp_write_reg(dev, REG_ADDR(isp_stitching_exposure_bit), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_COLOR_WEIGHT_0, hdr->weight0); + REG_SET_SLICE(val, STITCHING_COLOR_WEIGHT_1, hdr->weight1); + REG_SET_SLICE(val, STITCHING_COLOR_WEIGHT_2, hdr->weight2); + isp_write_reg(dev, REG_ADDR(isp_stitching_color_weight), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_TRANS_RANGE_START_LINEAR, + hdr->start_linear); + REG_SET_SLICE(val, STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR, + hdr->norm_factor_mul_linear); + isp_write_reg(dev, REG_ADDR(isp_stitching_trans_range_linear), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_TRANS_RANGE_START_NONLINEAR, + hdr->start_nonlinear); + REG_SET_SLICE(val, STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR, + hdr->norm_factor_mul_nonlinear); + isp_write_reg(dev, REG_ADDR(isp_stitching_trans_range_nonlinear), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_DUMMY_HBLANK, hdr->dummy_hblank); + REG_SET_SLICE(val, STITCHING_OUT_HBLANK, hdr->out_hblank); + isp_write_reg(dev, REG_ADDR(isp_stitching_out_hblank), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_OUT_VBLANK, hdr->out_vblank); + isp_write_reg(dev, REG_ADDR(isp_stitching_out_vblank), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_LONG_EXPOSURE_TIME, hdr->long_exp); + isp_write_reg(dev, REG_ADDR(isp_stitching_long_exposure), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_SHORT_EXPOSURE_TIME, hdr->short_exp); + isp_write_reg(dev, REG_ADDR(isp_stitching_short_exposure), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_VERY_SHORT_EXPOSURE_TIME, + hdr->very_short_exp); + isp_write_reg(dev, REG_ADDR(isp_stitching_very_short_exposure), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_LONG_EXPOSURE_TIME, hdr->long_exp); + isp_write_reg(dev, REG_ADDR(isp_stitching_long_exposure), val); +#endif + val = 0; + REG_SET_SLICE(val, STITCHING_RATIO_LONG_SHORT_1, hdr->ls1); + REG_SET_SLICE(val, STITCHING_RATIO_LONG_SHORT_0, hdr->ls0); + isp_write_reg(dev, REG_ADDR(isp_stitching_ratio_ls), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_RATIO_VERYSHORT_SHORT_1, hdr->vs1); + REG_SET_SLICE(val, STITCHING_RATIO_VERYSHORT_SHORT_0, hdr->vs0); + isp_write_reg(dev, REG_ADDR(isp_stitching_ratio_vs), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_SHORT_EXTEND_BIT, hdr->ext_bit); + REG_SET_SLICE(val, STITCHING_VERYSHORT_VALID_THRESH, hdr->valid_thresh); + REG_SET_SLICE(val, STITCHING_VERYSHORT_OFFSET_VAL, hdr->offset_val); + isp_write_reg(dev, REG_ADDR(isp_stitching_sat_level), val); + + for (i = 0; i < 5; i++) { + val = 0; + REG_SET_SLICE(val, STITCHING_COMPRESS_LUT_2, + hdr->compress_lut[i * 3 + 2]); + REG_SET_SLICE(val, STITCHING_COMPRESS_LUT_1, + hdr->compress_lut[i * 3 + 1]); + REG_SET_SLICE(val, STITCHING_COMPRESS_LUT_0, + hdr->compress_lut[i * 3]); + isp_write_reg(dev, + REG_ADDR(isp_stitching_compress_lut_0) + i * 4, + val); + } + val = 0; + REG_SET_SLICE(val, STITCHING_LONG_SAT_THRESH, hdr->sat_thresh); + REG_SET_SLICE(val, STITCHING_LONG_SAT_COMBINE_WEIGHT, + hdr->combine_weight); + isp_write_reg(dev, REG_ADDR(isp_stitching_long_sat_params), val); + + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINE_ENABLE_BIT, 1); + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_CFG_UPD, 1); + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINATION_MODE, 1); + isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), 0x4c0221); + + return 0; +} + +int isp_s_hdr_wb(struct isp_ic_dev *dev) +{ + struct isp_hdr_context *hdr = &dev->hdr; + u32 val = 0; + u32 isp_stitching_ctrl = + isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl)); + + pr_info("enter %s\n", __func__); + REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_GR, hdr->gr); + REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_GB, hdr->gb); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp0_awb_gain_g), val); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp1_awb_gain_g), val); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp2_awb_gain_g), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_R, hdr->r); + REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_B, hdr->b); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp0_awb_gain_rb), val); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp1_awb_gain_rb), val); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp2_awb_gain_rb), val); + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), 0x4c0221); + + return 0; +} + +int isp_s_hdr_bls(struct isp_ic_dev *dev) +{ + struct isp_hdr_context *hdr = &dev->hdr; + u32 isp_stitching_ctrl = + isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl)); + u32 val = 0; + int i; + + pr_info("enter %s\n", __func__); + + for (i = 0; i < 12; i++) { + val = 0; + REG_SET_SLICE(val, STITCHING_BLS_EXP_0_A, hdr->bls[i % 4]); + isp_write_reg(dev, REG_ADDR(isp_stitching_bls_exp_0_a) + i * 4, + val); + } + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), 0x4c0221); + + return 0; +} + +int isp_enable_hdr(struct isp_ic_dev *dev) +{ + u32 addr, isp_stitching_ctrl; + u32 dpcl; + int val = 0; + + pr_info("enter %s\n", __func__); + addr = REG_ADDR(isp_stitching_ctrl); + isp_stitching_ctrl = isp_read_reg(dev, addr); + REG_SET_SLICE(val, STITCHING_FRAME_WIDTH, dev->ctx.acqWindow.width); + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), val); + val = 0; + REG_SET_SLICE(val, STITCHING_FRAME_HEIGHT, dev->ctx.acqWindow.height); + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), val); + + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINE_ENABLE_BIT, 0); + isp_write_reg(dev, addr, isp_stitching_ctrl); + dpcl = isp_read_reg(dev, REG_ADDR(vi_dpcl)); + REG_SET_SLICE(dpcl, MRV_IF_SELECT, MRV_IF_SELECT_HDR); + isp_write_reg(dev, REG_ADDR(vi_dpcl), dpcl); + dev->mux.if_select = MRV_IF_SELECT_HDR; + return 0; +} + +int isp_disable_hdr(struct isp_ic_dev *dev) +{ + u32 addr, isp_stitching_ctrl = 0; + + pr_info("enter %s\n", __func__); + addr = REG_ADDR(isp_stitching_ctrl); + isp_stitching_ctrl = isp_read_reg(dev, addr); + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINE_ENABLE_BIT, 1); + isp_write_reg(dev, addr, isp_stitching_ctrl); + return 0; +} diff --git a/vvcam/isp/isp_ioctl.c b/vvcam/isp/isp_ioctl.c new file mode 100755 index 0000000..ee2f42b --- /dev/null +++ b/vvcam/isp/isp_ioctl.c @@ -0,0 +1,3688 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +/* process public and sample isp command. for complex modules, need new files.*/ +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" +#include "isp_wdr.h" +#include +#include + +#ifdef __KERNEL__ +#include +#include +#endif + +#ifdef CONFIG_VSI_ISP_DEBUG +#define isp_info(fmt, ...) pr_info(fmt, ##__VA_ARGS__) +#define isp_debug(fmt, ...) pr_debug(fmt, ##__VA_ARGS__) +#define isp_err(fmt, ...) pr_err(fmt, ##__VA_ARGS__) +#else +#define isp_info(fmt, ...) +#define isp_debug(fmt, ...) +#define isp_err(fmt, ...) pr_err(fmt, ##__VA_ARGS__) +#endif + +volatile MrvAllRegister_t *all_regs = NULL; + +#ifndef __KERNEL__ +#define ISP_REG_SIZE 0x10000 +static HalHandle_t hal_handle; + +void isp_ic_set_hal(HalHandle_t hal) +{ + hal_handle = hal; +} + +void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val) +{ + //pr_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val); + if (offset >= ISP_REG_SIZE) + return; + HalWriteReg(hal_handle, offset, val); +} + +u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset) +{ + if (offset >= ISP_REG_SIZE) + return 0; + return HalReadReg(hal_handle, offset); +} + +long isp_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); + return 0; +} +#else +void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val) +{ +// isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val); + if (offset >= ISP_REG_SIZE) + return; + __raw_writel(val, dev->base + offset); + /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/ +} + +u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset) +{ + u32 val = 0; + + if (offset >= ISP_REG_SIZE) + return 0; + val = __raw_readl(dev->base + offset); + /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/ + return val; +} +#endif + +int isp_reset(struct isp_ic_dev *dev) +{ + isp_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(vi_ircl), 0xFFFFFFBF); +#ifdef __KERNEL__ + mdelay(2); +#endif + isp_write_reg(dev, REG_ADDR(vi_ircl), 0x0); + /*clear mis array*/ + isp_write_reg(dev, REG_ADDR(isp_ctrl), 0x0); //clear isp_ctrl disable_isp_clk + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_enable_tpg(struct isp_ic_dev *dev) +{ + u32 addr, isp_tpg_ctrl; + + isp_info("enter %s\n", __func__); + addr = REG_ADDR(isp_tpg_ctrl); + isp_tpg_ctrl = isp_read_reg(dev, addr); + //REG_SET_SLICE(isp_tpg_ctrl, TPG_FRAME_NUM, 1);//set tpg frame num + REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 1); + isp_write_reg(dev, addr, isp_tpg_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_disable_tpg(struct isp_ic_dev *dev) +{ + u32 addr, isp_tpg_ctrl; + + isp_info("enter %s\n", __func__); + addr = REG_ADDR(isp_tpg_ctrl); + isp_tpg_ctrl = isp_read_reg(dev, addr); + REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 0); + isp_write_reg(dev, addr, isp_tpg_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_enable_bls(struct isp_ic_dev *dev) +{ +#ifndef ISP_BLS + //isp_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE, + MRV_BLS_BLS_ENABLE_PROCESS); + isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl); + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_disable_bls(struct isp_ic_dev *dev) +{ +#ifndef ISP_BLS + //isp_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE, + MRV_BLS_BLS_ENABLE_BYPASS); + isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl); + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_enable(struct isp_ic_dev *dev) +{ + u32 isp_ctrl, isp_imsc; + + isp_info("enter %s\n", __func__); + isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK); + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + /*Set lsc tbl after isp enable*/ + if (dev->update_lsc_tbl) { + isp_s_lsc_tbl(dev); + dev->update_lsc_tbl = false; + } + + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_disable(struct isp_ic_dev *dev) +{ + u32 isp_ctrl; +/* #ifndef ENABLE_IRQ + u32 isp_imsc; + #endif*/ + + isp_info("enter %s\n", __func__); + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); +/* #ifndef ENABLE_IRQ + isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK); + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + #endif*/ + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_write_reg(dev, REG_ADDR(isp_isr), MRV_ISP_ISR_ISP_OFF_MASK); + isp_info("exit %s\n", __func__); + return 0; +} + +bool is_isp_enable(struct isp_ic_dev *dev) +{ +// isp_info("enter %s\n", __func__); + return isp_read_reg(dev, REG_ADDR(isp_ctrl)) & 0x01; +} + +int isp_enable_lsc(struct isp_ic_dev *dev) +{ + + u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl)); + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 1U); + isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl); + + { + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_disable_lsc(struct isp_ic_dev *dev) +{ + u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 0U); + isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl); + + { + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } + isp_info("exit %s\n", __func__); + return 0; +} + +#if defined(__KERNEL__) && defined(ISP8000NANO_V1802) +static int isp_gpr_input_control(struct isp_ic_dev *dev) +{ + struct isp_context isp_ctx = *(&dev->ctx); + unsigned int fmt_offset = 3; + unsigned int isp_dewarp_control_val; + + if (dev->mix_gpr == NULL) + return -ENOMEM; + + if (dev->id == 0) + fmt_offset = 3; + else + fmt_offset = 13; + + regmap_read(dev->mix_gpr, 0x138, &isp_dewarp_control_val); + if (isp_dewarp_control_val == 0) + isp_dewarp_control_val = 0x8d8360; + + switch (isp_ctx.input_selection) { + case MRV_ISP_INPUT_SELECTION_12EXT: + isp_dewarp_control_val &= ~(0x3f << fmt_offset); + isp_dewarp_control_val |= (0x2c << fmt_offset); + break; + case MRV_ISP_INPUT_SELECTION_10ZERO: + case MRV_ISP_INPUT_SELECTION_10MSB: + isp_dewarp_control_val &= ~(0x3f << fmt_offset); + isp_dewarp_control_val |= (0x2b << fmt_offset); + break; + case MRV_ISP_INPUT_SELECTION_8ZERO: + case MRV_ISP_INPUT_SELECTION_8MSB: + isp_dewarp_control_val &= ~(0x3f << fmt_offset); + isp_dewarp_control_val |= (0x2a << fmt_offset); + break; + default: + return 0; + } + regmap_write(dev->mix_gpr, 0x138, isp_dewarp_control_val); + return 0; +} +#endif + +int isp_s_input(struct isp_ic_dev *dev) +{ + struct isp_context isp_ctx = *(&dev->ctx); + u32 isp_ctrl, isp_acq_prop, isp_demosaic; +#ifdef ISP_HDR_STITCH + u32 isp_stitching_ctrl; +#endif //ISP_HDR_STITCH + isp_info("enter %s\n", __func__); + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_MODE, isp_ctx.mode); + isp_acq_prop = isp_read_reg(dev, REG_ADDR(isp_acq_prop)); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_SAMPLE_EDGE, isp_ctx.sample_edge); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_HSYNC_POL, + isp_ctx.hSyncLowPolarity); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_VSYNC_POL, + isp_ctx.vSyncLowPolarity); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_BAYER_PAT, isp_ctx.bayer_pattern); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_CONV_422, isp_ctx.sub_sampling); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_CCIR_SEQ, isp_ctx.seq_ccir); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_FIELD_SELECTION, + isp_ctx.field_selection); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_INPUT_SELECTION, + isp_ctx.input_selection); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_LATENCY_FIFO_SELECTION, + isp_ctx.latency_fifo); + + isp_write_reg(dev, REG_ADDR(isp_acq_prop), isp_acq_prop); + isp_write_reg(dev, REG_ADDR(isp_acq_h_offs), isp_ctx.acqWindow.x); + isp_write_reg(dev, REG_ADDR(isp_acq_v_offs), isp_ctx.acqWindow.y); + isp_write_reg(dev, REG_ADDR(isp_acq_h_size), isp_ctx.acqWindow.width); + isp_write_reg(dev, REG_ADDR(isp_acq_v_size), isp_ctx.acqWindow.height); +#ifdef ISP_MI_HDR + isp_write_reg(dev, REG_ADDR(isp_hdr_interval), 0x113); + isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_blank), 0x200); + isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_blank), 0x30); + isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_size), isp_ctx.acqWindow.width); + isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_size), isp_ctx.acqWindow.height); +#endif + + isp_write_reg(dev, REG_ADDR(isp_out_h_offs), + (isp_ctx.ofWindow.x & MRV_ISP_ISP_OUT_H_OFFS_MASK)); + isp_write_reg(dev, REG_ADDR(isp_out_v_offs), + (isp_ctx.ofWindow.y & MRV_ISP_ISP_OUT_V_OFFS_MASK)); + isp_write_reg(dev, REG_ADDR(isp_out_h_size), + (isp_ctx.ofWindow.width & MRV_ISP_ISP_OUT_H_SIZE_MASK)); + isp_write_reg(dev, REG_ADDR(isp_out_v_size), + (isp_ctx.ofWindow.height & MRV_ISP_ISP_OUT_V_SIZE_MASK)); + + isp_write_reg(dev, REG_ADDR(isp_is_h_offs), + (isp_ctx.isWindow.x & MRV_IS_IS_H_OFFS_MASK)); + isp_write_reg(dev, REG_ADDR(isp_is_v_offs), + (isp_ctx.isWindow.y & MRV_IS_IS_V_OFFS_MASK)); + isp_write_reg(dev, REG_ADDR(isp_is_h_size), + (isp_ctx.isWindow.width & MRV_IS_IS_H_SIZE_MASK)); + isp_write_reg(dev, REG_ADDR(isp_is_v_size), + (isp_ctx.isWindow.height & MRV_IS_IS_V_SIZE_MASK)); + + isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic)); + REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS, + isp_ctx.bypass_mode); + REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH, + isp_ctx.demosaic_threshold); + isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic); + +#ifdef ISP_HDR_STITCH + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), isp_ctx.acqWindow.width); + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), isp_ctx.acqWindow.height); + isp_write_reg(dev, REG_ADDR(isp_stitching_hdr_mode), isp_ctx.stitching_mode); + isp_stitching_ctrl = isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl)); + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_BAYER_PATTERN, isp_ctx.bayer_pattern); + isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), isp_stitching_ctrl); +#endif + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); +#if defined(__KERNEL__) && defined(ISP8000NANO_V1802) + isp_gpr_input_control(dev); +#endif + + return 0; +} + +int isp_s_digital_gain(struct isp_ic_dev *dev) +{ + struct isp_digital_gain_cxt dgain = *(&dev->dgain); + u32 isp_dgain_rb = isp_read_reg(dev, REG_ADDR(isp_dgain_rb)); + u32 isp_dgain_g = isp_read_reg(dev, REG_ADDR(isp_dgain_g)); + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + if (!dgain.enable) { + isp_err("%s, Disable isp digital gain", __func__); + REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 0U); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + return 0; + } + + //isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_R, dgain.gain_r); + REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_B, dgain.gain_b); + + REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GR, dgain.gain_gr); + REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GB, dgain.gain_gb); + REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 1U); + + isp_write_reg(dev, REG_ADDR(isp_dgain_rb), isp_dgain_rb); + isp_write_reg(dev, REG_ADDR(isp_dgain_g), isp_dgain_g); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + //isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_demosaic(struct isp_ic_dev *dev) +{ + struct isp_context isp_ctx = *(&dev->ctx); + u32 isp_demosaic; + isp_info("enter %s\n", __func__); + isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic)); + REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS, + isp_ctx.bypass_mode); + REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH, + isp_ctx.demosaic_threshold); + isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic); + isp_info("exit %s\n", __func__); + return 0;; +} + +int isp_s_tpg(struct isp_ic_dev *dev) +{ + struct isp_tpg_context tpg = *(&dev->tpg); + u32 addr, regVal; + + isp_info("enter %s\n", __func__); + addr = REG_ADDR(isp_tpg_ctrl); + regVal = isp_read_reg(dev, addr); + REG_SET_SLICE(regVal, TPG_IMG_NUM, tpg.image_type); + REG_SET_SLICE(regVal, TPG_CFA_PAT, tpg.bayer_pattern); + REG_SET_SLICE(regVal, TPG_COLOR_DEPTH, tpg.color_depth); + REG_SET_SLICE(regVal, TPG_RESOLUTION, tpg.resolution); + REG_SET_SLICE(regVal, TPG_FRAME_NUM, tpg.frame_num); + isp_write_reg(dev, addr, regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_PIX_GAP_IN, tpg.pixleGap); + REG_SET_SLICE(regVal, TPG_LINE_GAP_IN, tpg.lineGap); + isp_write_reg(dev, REG_ADDR(isp_tpg_gap_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_PIX_GAP_STD_IN, tpg.gapStandard); + isp_write_reg(dev, REG_ADDR(isp_tpg_gap_std_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_RANDOM_SEED, tpg.randomSeed); + isp_write_reg(dev, REG_ADDR(isp_tpg_random_seed), regVal); + REG_SET_SLICE(regVal, TPG_HTOTAL_IN, tpg.user_mode_h.total); + REG_SET_SLICE(regVal, TPG_VTOTAL_IN, tpg.user_mode_v.total); + isp_write_reg(dev, REG_ADDR(isp_tpg_total_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_HACT_IN, tpg.user_mode_h.act); + REG_SET_SLICE(regVal, TPG_VACT_IN, tpg.user_mode_v.act); + isp_write_reg(dev, REG_ADDR(isp_tpg_act_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_FP_H_IN, tpg.user_mode_h.fp); + REG_SET_SLICE(regVal, TPG_FP_V_IN, tpg.user_mode_v.fp); + isp_write_reg(dev, REG_ADDR(isp_tpg_fp_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_BP_H_IN, tpg.user_mode_h.bp); + REG_SET_SLICE(regVal, TPG_BP_V_IN, tpg.user_mode_v.bp); + isp_write_reg(dev, REG_ADDR(isp_tpg_bp_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_HS_W_IN, tpg.user_mode_h.sync); + REG_SET_SLICE(regVal, TPG_VS_W_IN, tpg.user_mode_v.sync); + isp_write_reg(dev, REG_ADDR(isp_tpg_w_in), regVal); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_mcm_wr(struct isp_ic_dev *dev) +{ + struct isp_mcm_context *mcm = &dev->mcm; + u32 mcm_ctrl; + u32 mcm_hsync_preample_ext; + u32 mcm_size, mcm_rd_fmt; + int i; + isp_info("enter %s\n", __func__); + + mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl)); + mcm_rd_fmt = isp_read_reg(dev, REG_ADDR(mcm_rd_cfg)); + mcm_hsync_preample_ext = isp_read_reg(dev, REG_ADDR(mcm_hsync_preample_ext)); + + REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_SWITCH, mcm->bypass_switch); + REG_SET_SLICE(mcm_ctrl, MCM_WR0_FMT, mcm->wr_fmt[MCM_INDEX_WR0]); + REG_SET_SLICE(mcm_ctrl, MCM_WR1_FMT, mcm->wr_fmt[MCM_INDEX_WR1]); + REG_SET_SLICE(mcm_ctrl, MCM_G2_WR0_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR0]); + REG_SET_SLICE(mcm_ctrl, MCM_G2_WR1_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR1]); + REG_SET_SLICE(mcm_ctrl, MCM_SENSOR_MEM_BYPASS, mcm->sensor_mem_bypass); + + REG_SET_SLICE(mcm_rd_fmt, MCM_RD_FMT, mcm->rd_fmt); + REG_SET_SLICE(mcm_hsync_preample_ext, MCM_HSYNC_PREAMPLE_EXT, mcm->hsync_rpeample_ext); + + for (i = MCM_INDEX_WR0 ; i < MCM_INDEX_WR_MAX; i++){ + REG_SET_SLICE(mcm_size, MCM_HEIGHT0, mcm->height[i]); + REG_SET_SLICE(mcm_size, MCM_WIDTH0, mcm->width[i]); + isp_write_reg(dev, REG_ADDR(mcm_size0) + i *4, mcm_size); + } + isp_write_reg(dev, REG_ADDR(mcm_hsync_preample_ext), mcm_hsync_preample_ext); + isp_write_reg(dev, REG_ADDR(mcm_rd_cfg), mcm_rd_fmt); + isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} +int isp_bypass_mcm(struct isp_ic_dev *dev) +{ + struct isp_mcm_context *mcm = &dev->mcm; + u32 mcm_ctrl; + u32 mcm_retiming0; + u32 mcm_retiming1; + u32 mcm_wr_retiming0; + u32 mcm_wr_retiming1; + + isp_info("enter %s\n", __func__); + mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl)); + mcm_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_retiming0)); + mcm_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_retiming1)); + + mcm_wr_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming0)); + mcm_wr_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming1)); + + if (mcm->bypass_enable) { + REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 1); + } else { + REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 0); + } + + REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration); + REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank); + REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample); + REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank); + + REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration); + REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank); + REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample); + REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank); + + isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl); + isp_write_reg(dev, REG_ADDR(mcm_retiming0), mcm_retiming0); // 0x01042801);// + isp_write_reg(dev, REG_ADDR(mcm_retiming1), mcm_retiming1); //0x00008478); // + isp_write_reg(dev, REG_ADDR(mcm_wr_retiming0), mcm_wr_retiming0); //0x01042801); // + isp_write_reg(dev, REG_ADDR(mcm_wr_retiming1), mcm_wr_retiming1); //0x000084ec);// + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_mux(struct isp_ic_dev *dev) +{ + struct isp_mux_context mux = *(&dev->mux); + u32 vi_dpcl; + + isp_info("enter %s\n", __func__); + vi_dpcl = isp_read_reg(dev, REG_ADDR(vi_dpcl)); + REG_SET_SLICE(vi_dpcl, MRV_VI_MP_MUX, mux.mp_mux); + REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SPMUX, mux.sp_mux); + REG_SET_SLICE(vi_dpcl, MRV_VI_CHAN_MODE, mux.chan_mode); + REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_IEMUX, mux.ie_mux); + REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SWITCH, mux.dma_read_switch); + REG_SET_SLICE(vi_dpcl, MRV_IF_SELECT, mux.if_select); + isp_write_reg(dev, REG_ADDR(vi_dpcl), vi_dpcl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_bls(struct isp_ic_dev *dev) +{ +#ifndef ISP_BLS + //isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_bls_context bls = *(&dev->bls); + u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_MODE, bls.mode); + isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl); + isp_write_reg(dev, REG_ADDR(isp_bls_a_fixed), bls.a); + isp_write_reg(dev, REG_ADDR(isp_bls_b_fixed), bls.b); + isp_write_reg(dev, REG_ADDR(isp_bls_c_fixed), bls.c); + isp_write_reg(dev, REG_ADDR(isp_bls_d_fixed), bls.d); + return 0; +#endif +} + +int isp_enable_awb(struct isp_ic_dev *dev) +{ + u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_MEAS); + isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_disable_awb(struct isp_ic_dev *dev) +{ + u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_NOMEAS); + isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_awb(struct isp_ic_dev *dev) +{ + struct isp_awb_context awb = *(&dev->awb); + u32 gain_data = 0; + u32 isp_awb_thresh = 0; + u32 isp_awb_ref = 0; + u32 isp_awb_prop = 0; + + /* isp_info("enter %s\n", __func__); */ + isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop)); + + if (awb.mode == MRV_ISP_AWB_MEAS_MODE_YCBCR) { + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE, + MRV_ISP_AWB_MEAS_MODE_YCBCR); + if (awb.max_y == 0) { + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN, + MRV_ISP_AWB_MAX_EN_DISABLE); + } else { + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN, + MRV_ISP_AWB_MAX_EN_ENABLE); + } + } else if (awb.mode == MRV_ISP_AWB_MEAS_MODE_RGB) { + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN, + MRV_ISP_AWB_MAX_EN_DISABLE); + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE, + MRV_ISP_AWB_MEAS_MODE_RGB); + } + isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop); + + REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_Y, awb.max_y); + REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_Y__MAX_G, + awb.min_y_max_g); + REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_CSUM, awb.max_c_sum); + REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_C, awb.min_c); + isp_write_reg(dev, REG_ADDR(isp_awb_thresh), isp_awb_thresh); + + REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CR__MAX_R, awb.refcr_max_r); + REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CB__MAX_B, awb.refcb_max_b); + isp_write_reg(dev, REG_ADDR(isp_awb_ref), isp_awb_ref); + isp_write_reg(dev, REG_ADDR(isp_awb_frames), 0); + isp_write_reg(dev, REG_ADDR(isp_awb_h_offs), + (MRV_ISP_AWB_H_OFFS_MASK & awb.window.x)); + isp_write_reg(dev, REG_ADDR(isp_awb_v_offs), + (MRV_ISP_AWB_V_OFFS_MASK & awb.window.y)); + isp_write_reg(dev, REG_ADDR(isp_awb_h_size), + (MRV_ISP_AWB_H_SIZE_MASK & awb.window.width)); + isp_write_reg(dev, REG_ADDR(isp_awb_v_size), + (MRV_ISP_AWB_V_SIZE_MASK & awb.window.height)); + + gain_data = 0UL; +#ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r << 2); + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b << 2) ; +#else //This is Gain value component 2 bit int part and 8 bit fractional part + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r); + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b); +#endif + isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), gain_data); + + gain_data = 0UL; +#ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr << 2); + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb << 2); +#else //This is Gain value component 2 bit int part and 8 bit fractional part + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr); + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb); +#endif + + isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), gain_data); + return 0; +} + +int isp_s_is(struct isp_ic_dev *dev) +{ + struct isp_is_context is = *(&dev->is); + u32 isp_is_ctrl; + u32 isp_is_displace; + u32 isp_ctrl; + + isp_info("enter %s\n", __func__); + + isp_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_is_ctrl)); + + if (!is.enable) { + REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 0); + isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl); + return 0; + } + + REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 1); + isp_write_reg(dev, REG_ADDR(isp_is_h_offs), is.window.x); + isp_write_reg(dev, REG_ADDR(isp_is_v_offs), is.window.y); + isp_write_reg(dev, REG_ADDR(isp_is_h_size), is.window.width); + isp_write_reg(dev, REG_ADDR(isp_is_v_size), is.window.height); + isp_write_reg(dev, REG_ADDR(isp_is_recenter), + is.recenter & MRV_IS_IS_RECENTER_MASK); + isp_write_reg(dev, REG_ADDR(isp_is_max_dx), is.max_dx); + isp_write_reg(dev, REG_ADDR(isp_is_max_dy), is.max_dy); + isp_is_displace = isp_read_reg(dev, REG_ADDR(isp_is_displace)); + REG_SET_SLICE(isp_is_displace, MRV_IS_DX, is.displace_x); + REG_SET_SLICE(isp_is_displace, MRV_IS_DY, is.displace_y); + isp_write_reg(dev, REG_ADDR(isp_is_displace), isp_is_displace); + isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl); + if (is.update) { + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + is.update = false; + } + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_raw_is(struct isp_ic_dev *dev) +{ +#ifndef ISP_RAWIS + //isp_err("unsupported funciton: %s\n", __func__); + return -EINVAL; +#else + struct isp_is_context rawis = *(&dev->rawis); + u32 isp_raw_is_ctrl; + u32 isp_raw_is_displace; + // u32 isp_ctrl; + + isp_info("enter %s\n", __func__); + + isp_raw_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_raw_is_ctrl)); + + if (!rawis.enable) { + isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), + rawis.window.width); + isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), + rawis.window.height); + + REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 0); + isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl); + return 0; + } + + REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 1); + isp_write_reg(dev, REG_ADDR(isp_raw_is_h_offs), rawis.window.x); + isp_write_reg(dev, REG_ADDR(isp_raw_is_v_offs), rawis.window.y); + isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), rawis.window.width); + isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), rawis.window.height); + isp_write_reg(dev, REG_ADDR(isp_raw_is_recenter), + rawis.recenter & MRV_IS_IS_RECENTER_MASK); + isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dx), rawis.max_dx); + isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dy), rawis.max_dy); + isp_raw_is_displace = isp_read_reg(dev, REG_ADDR(isp_raw_is_displace)); + REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DX, rawis.displace_x); + REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DY, rawis.displace_y); + isp_write_reg(dev, REG_ADDR(isp_raw_is_displace), isp_raw_is_displace); + isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl); + /*dont update the configuration at the sub module function*/ +#if 0 + if (rawis.update) { + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + rawis.update = false; + } +#endif + return 0; +#endif +} + +int isp_s_cnr(struct isp_ic_dev *dev) +{ + struct isp_cnr_context *cnr = &dev->cnr; + u32 isp_ctrl; + + isp_info("enter %s\n", __func__); + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + if (!cnr->enable) { + REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + return 0; + } + + REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 1); + isp_write_reg(dev, REG_ADDR(isp_cnr_linesize), cnr->line_width); + isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c1), cnr->threshold_1); + isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c2), cnr->threshold_2); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +void isp_test_bt(struct isp_ic_dev *dev) +{ + + isp_write_reg(dev, 0x00000010, 0x00019f7b); + isp_write_reg(dev, 0x00000014, 0x00020000); + isp_write_reg(dev, 0x00001200, 0x00000000); + isp_write_reg(dev, 0x00001204, 0x01e00280); + isp_write_reg(dev, 0x00001208, 0x01e00280); + isp_write_reg(dev, 0x00001308, 0x6ce60608); + isp_write_reg(dev, 0x00001314, 0x000008c4); + isp_write_reg(dev, 0x00001318, 0x00000001); + isp_write_reg(dev, 0x0000131c, 0x03a2013b); + isp_write_reg(dev, 0x00001320, 0x00000000); + isp_write_reg(dev, 0x00001324, 0xc0000000); + isp_write_reg(dev, 0x00001328, 0x0004B000); + isp_write_reg(dev, 0x0000132c, 0x00000000); + isp_write_reg(dev, 0x00001330, 0x00000280); + isp_write_reg(dev, 0x00001334, 0x00000280); + isp_write_reg(dev, 0x00001338, 0x000001e0); + isp_write_reg(dev, 0x0000133c, 0x0004B000); + isp_write_reg(dev, 0x00001340, 0xc0040000); + isp_write_reg(dev, 0x00001344, 0x0004B000); + isp_write_reg(dev, 0x000016c0, 0x07ffffff); + isp_write_reg(dev, 0x000005bc, 0x00000003); + isp_write_reg(dev, 0x000016c4, 0x052c4e39); + isp_write_reg(dev, 0x00000404, 0x00d00018); + isp_write_reg(dev, 0x00000410, 0x00000280); + isp_write_reg(dev, 0x00000414, 0x000001e0); + + isp_write_reg(dev, 0x00000538, 0x01000100); + isp_write_reg(dev, 0x0000053c, 0x02270220); + isp_write_reg(dev, 0x0000059c, 0x00000280); + isp_write_reg(dev, 0x000005a0, 0x000001e0); + + isp_write_reg(dev, 0x00002310, 0x00000280); + isp_write_reg(dev, 0x00002314, 0x000001e0); + isp_write_reg(dev, 0x0000295c, 0x00000070); + isp_write_reg(dev, 0x00003e00, 0x040128be); + isp_write_reg(dev, 0x00003e04, 0x00000000); + isp_write_reg(dev, 0x00003e08, 0x00001f08); + isp_write_reg(dev, 0x00003e0c, 0x200003ff); + isp_write_reg(dev, 0x00003e10, 0x0c968628); + isp_write_reg(dev, 0x00003e14, 0x00008008); + isp_write_reg(dev, 0x00003e18, 0x007d07d0); + isp_write_reg(dev, 0x00003e1c, 0x301a3012); + isp_write_reg(dev, 0x00003e20, 0x04010000); + isp_write_reg(dev, 0x00003e24, 0x22018000); + isp_write_reg(dev, 0x00003e28, 0x00020000); + isp_write_reg(dev, 0x00003e2c, 0x0210210a); + isp_write_reg(dev, 0x00003e30, 0x00102102); + isp_write_reg(dev, 0x00003e34, 0x0000388c); + isp_write_reg(dev, 0x00003e38, 0x00000000); + isp_write_reg(dev, 0x00003e3c, 0x00000000); + isp_write_reg(dev, 0x00003e40, 0x00000000); + isp_write_reg(dev, 0x00003e44, 0x00000001); + isp_write_reg(dev, 0x00003e48, 0x10001000); + isp_write_reg(dev, 0x00003e4c, 0x00000000); + isp_write_reg(dev, 0x00003e50, 0x00000000); + isp_write_reg(dev, 0x00003e54, 0x00000000); + isp_write_reg(dev, 0x00003e58, 0x00080010); + isp_write_reg(dev, 0x00003e5c, 0x00080010); + isp_write_reg(dev, 0x00003e60, 0x01300280); + isp_write_reg(dev, 0x00000018, 0x00001000); + isp_write_reg(dev, 0x00001200, 0x00000001); //why + + isp_write_reg(dev, 0x00000418, 0x00000001); + isp_write_reg(dev, 0x00000400, 0x80100686); + isp_write_reg(dev, 0x00000400, 0x80100097); + isp_write_reg(dev, 0x00001300, 0x00000001); + isp_write_reg(dev, 0x00001310, 0x00000038); + isp_write_reg(dev, 0x000014e4, 0x00000238); + isp_write_reg(dev, 0x00001600, 0x0000005c); + isp_write_reg(dev, 0x00000704, 0x00c00222); + isp_write_reg(dev, 0x00000708, 0x00a001e0); + isp_write_reg(dev, 0x0000070c, 0x000a4023); + isp_write_reg(dev, 0x00000710, 0x000a401e); + isp_write_reg(dev, 0x00000714, 0x000b8001); + isp_write_reg(dev, 0x00000718, 0x003540a0); + isp_write_reg(dev, 0x0000071c, 0x00000050); + isp_write_reg(dev, 0x00000720, 0x3aca095b); + isp_write_reg(dev, 0x00000700, 0x00000c42); + isp_info("end %s\n", __func__); +} +int isp_start_stream(struct isp_ic_dev *dev, u32 numFrames) +{ + + u32 isp_imsc, isp_ctrl; + + isp_info("enter %s\n", __func__); +#ifdef ISP_PDAF + isp_write_reg(dev, 0x5d00, 0x1); +#endif + + isp_write_reg(dev, REG_ADDR(isp_sh_ctrl), 0x10); + isp_write_reg(dev, REG_ADDR(isp_acq_nr_frames), + (MRV_ISP_ACQ_NR_FRAMES_MASK & numFrames)); + isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + isp_imsc |= + (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK | + MRV_ISP_IMSC_FRAME_IN_MASK | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK | MRV_ISP_IMSC_FLASH_ON_MASK); + /* isp_imsc |= (MRV_ISP_IMSC_FRAME_MASK | MRV_ISP_IMSC_DATA_LOSS_MASK | MRV_ISP_IMSC_FRAME_IN_MASK); */ + isp_write_reg(dev, REG_ADDR(isp_icr), 0xFFFFFFFF); + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + isp_write_reg(dev, 0x00001320, 1); + isp_write_reg(dev, 0x00001610, 1); +#if 0/*add by shenwuyi for live sensor*/ + isp_write_reg(dev, 0x00000c68, 10);/*fream_rete_ctrl*/ + isp_write_reg(dev, 0x00002200, 0x00000000); //disable lsc + isp_write_reg(dev, 0x000005bc, 0x00000001); //irq_enable + isp_write_reg(dev, 0x00000538, 0x01000100); //awb_gain_gr + isp_write_reg(dev, 0x0000053c, 0x02270220); //awb_gain_gc +#endif + /*isp_test_bt(dev);*/ + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + /*Set lsc tbl after isp enable*/ + if (dev->update_lsc_tbl) { + isp_s_lsc_tbl(dev); + dev->update_lsc_tbl = false; + } + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_stop_stream(struct isp_ic_dev *dev) +{ + isp_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(isp_imsc), 0); + isp_disable(dev); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_cc(struct isp_ic_dev *dev) +{ + struct isp_cc_context *cc = &dev->cc; + u32 isp_ctrl, addr; + int i; + + isp_info("enter %s\n", __func__); + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_Y_RANGE, cc->conv_range_y_full); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_C_RANGE, cc->conv_range_c_full); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + if (cc->update_curve) { + addr = REG_ADDR(isp_cc_coeff_0); + for (i = 0; i < 9; i++) { + isp_write_reg(dev, addr + i * 4, + MRV_ISP_CC_COEFF_0_MASK & cc->lCoeff[i]); + } + } + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_xtalk(struct isp_ic_dev *dev) +{ + struct isp_xtalk_context xtalk = *(&dev->xtalk); + int i; + + /* isp_info("enter %s\n", __func__); */ + + for (i = 0; i < 9; i++) { +#ifdef ISP_CTM_0507 // Coefficient for cross talk matrix.Use bit 11,Values are 12-bit signed fixed-point numbers with 5 bit integer and 7 bit fractional part, ranging from -16 (0x800) to +15.992 (0x7FF). + isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]), + MRV_ISP_CT_COEFF_MASK & (xtalk.lCoeff[i] << 1)); +#else // Coefficient for cross talk matrix.Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF). + isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]), + MRV_ISP_CT_COEFF_MASK & xtalk.lCoeff[i]); +#endif + } + + isp_write_reg(dev, REG_ADDR(isp_ct_offset_r), + (MRV_ISP_CT_OFFSET_R_MASK & xtalk.r)); + isp_write_reg(dev, REG_ADDR(isp_ct_offset_g), + (MRV_ISP_CT_OFFSET_G_MASK & xtalk.g)); + isp_write_reg(dev, REG_ADDR(isp_ct_offset_b), + (MRV_ISP_CT_OFFSET_B_MASK & xtalk.b)); + return 0; +} + +int isp_enable_wb(struct isp_ic_dev *dev, bool bEnable) +{ + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_AWB_ENABLE, bEnable); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_enable_gamma_out(struct isp_ic_dev *dev, bool bEnable) +{ + u32 isp_ctrl; + struct isp_gamma_out_context *gamma = &dev->gamma_out; + isp_info("enter %s\n", __func__); + gamma->enableGamma = bEnable; + if(gamma->changed || !is_isp_enable(dev)) + { + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, bEnable); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + gamma->changed = false; + } else { + gamma->changed = true; + } + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_gamma_out(struct isp_ic_dev *dev) +{ + u32 isp_gamma_out_mode; + int i; + u32 isp_ctrl; + struct isp_gamma_out_context *gamma = &dev->gamma_out; + if(gamma->changed || !is_isp_enable(dev)) { + isp_gamma_out_mode = isp_read_reg(dev, REG_ADDR(isp_gamma_out_mode)); + REG_SET_SLICE(isp_gamma_out_mode, MRV_ISP_EQU_SEGM, gamma->mode); + isp_write_reg(dev, REG_ADDR(isp_gamma_out_mode), isp_gamma_out_mode); + + for (i = 0; i < 17; i++) { + isp_write_reg(dev, REG_ADDR(gamma_out_y_block_arr[i]), + MRV_ISP_ISP_GAMMA_OUT_Y_MASK & gamma->curve[i]); + } + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, gamma->enableGamma); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + gamma->changed = false; + } else { + gamma->changed = true; + } + + return 0; +} + +int isp_s_lsc_tbl(struct isp_ic_dev *dev) +{ + int i, n; + u32 isp_ctrl; + u32 sram_addr; + u32 isp_lsc_status; + struct isp_lsc_context *lsc = (&dev->lsc); + + //isp_debug("enter %s\n", __func__); + + /*need to set tbl after isp_ctrl enable In ISP8000NANO_V1802*/ + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + /* Enable isp to enable ram clock for write correct table to ram. */ + if (!(isp_ctrl & 0x01)) { + dev->update_lsc_tbl = true; + return 0; + } + + isp_lsc_status = isp_read_reg(dev, REG_ADDR(isp_lsc_status)); + sram_addr = (isp_lsc_status & 0x2U) ? 0U : 153U; + isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_addr), sram_addr); + isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_addr), sram_addr); + isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_addr), sram_addr); + isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_addr), sram_addr); +#ifdef ISP_LSC_V2 + for (n = 0; n < ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1)); n += CAMERIC_MAX_LSC_SECTORS + 1) { + for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) { + isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + i] & 0xFFF) | ((lsc->r[n + i + 1] & 0xFFF) << 12) | ((lsc->r[n + i] >> 12) << 24) | ((lsc->r[n + i + 1] >> 12) << 28)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + i] & 0xFFF) | ((lsc->gr[n + i + 1] & 0xFFF) << 12) | ((lsc->gr[n + i] >> 12) << 24) | ((lsc->gr[n + i + 1] >> 12) << 28)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + i] & 0xFFF) | ((lsc->gb[n + i + 1] & 0xFFF) << 12) | ((lsc->gb[n + i] >> 12) << 24) | ((lsc->gb[n + i + 1] >> 12) << 28)); + isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + i] & 0xFFF) | ((lsc->b[n + i + 1] & 0xFFF) << 12) | ((lsc->b[n + i] >> 12) << 24) | ((lsc->b[n + i + 1] >> 12) << 28)); + } + isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->r[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24)); + isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->b[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24)); + } +#else + for (n = 0; + n < + ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1)); + n += CAMERIC_MAX_LSC_SECTORS + 1) { + /* 17 sectors with 2 values in one DWORD = 9 DWORDs (8 steps + 1 outside loop) */ + for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) { + isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), + lsc->r[n + + i] | (lsc->r[n + i + 1] << 12)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), + lsc->gr[n + + i] | (lsc->gr[n + i + 1] << 12)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), + lsc->gb[n + + i] | (lsc->gb[n + i + 1] << 12)); + isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), + lsc->b[n + + i] | (lsc->b[n + i + 1] << 12)); + } + isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), + lsc->r[n + CAMERIC_MAX_LSC_SECTORS]); + isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), + lsc->gr[n + CAMERIC_MAX_LSC_SECTORS]); + isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), + lsc->gb[n + CAMERIC_MAX_LSC_SECTORS]); + isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), + lsc->b[n + CAMERIC_MAX_LSC_SECTORS]); + } +#endif + isp_write_reg(dev, REG_ADDR(isp_lsc_table_sel), + (isp_lsc_status & 0x2U) ? 0U : 1U); + //isp_info("exit %s\n", __func__); + return 0; +} + + +int isp_s_lsc_sec(struct isp_ic_dev *dev) +{ + int i; + struct isp_lsc_context *lsc = (&dev->lsc); + /* isp_info("enter %s\n", __func__); */ + for (i = 0; i < CAEMRIC_GRAD_TBL_SIZE; i += 2) { + isp_write_reg(dev, REG_ADDR(isp_lsc_xsize_01) + i * 2, + (lsc->x_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) | + ((lsc->x_size[i + 1] + << MRV_LSC_X_SECT_SIZE_1_SHIFT) + & MRV_LSC_X_SECT_SIZE_1_MASK)); + isp_write_reg(dev, REG_ADDR(isp_lsc_ysize_01) + i * 2, + (lsc->y_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) | + ((lsc->y_size[i + 1] + << MRV_LSC_Y_SECT_SIZE_1_SHIFT) + & MRV_LSC_Y_SECT_SIZE_1_MASK)); + isp_write_reg(dev, REG_ADDR(isp_lsc_xgrad_01) + i * 2, + (lsc->x_grad[i] & MRV_LSC_XGRAD_0_MASK) | + ((lsc->x_grad[i + 1] + << MRV_LSC_XGRAD_1_SHIFT) + & MRV_LSC_XGRAD_1_MASK)); + isp_write_reg(dev, REG_ADDR(isp_lsc_ygrad_01) + i * 2, + (lsc->y_grad[i] & MRV_LSC_YGRAD_0_MASK) | + ((lsc->y_grad[i + 1] + << MRV_LSC_YGRAD_1_SHIFT) + & MRV_LSC_YGRAD_1_MASK)); + } + return 0; +} + +int isp_ioc_read_mis(struct isp_ic_dev *dev, void __user *args) +{ + isp_mis_list_t* pCList = &dev->circle_list; + isp_mis_t mis_data; + u32 ary[2]; + int ret = -1; + ret = isp_irq_read_circle_queue(&mis_data, pCList); + if (ret < 0) { + /*isp_info("%s can not dequeue mis data\n", __func__);*/ + return ret; + } + + /*isp_info("%s irq src %d val 0x%08x\n", __func__, mis_data.irq_src, mis_data.val);*/ + ary[0] = mis_data.irq_src; + ary[1] = mis_data.val; + viv_check_retval(copy_to_user(args, ary, sizeof( ary))); + return 0; +} + +static int isp_ioc_read_reg(struct isp_ic_dev *dev, void __user * args) +{ + struct isp_reg_t reg; + + viv_check_retval(copy_from_user(®, args, sizeof(reg))); + reg.val = isp_read_reg(dev, reg.offset); + viv_check_retval(copy_to_user(args, ®, sizeof(reg))); + return 0; +} + +static int isp_ioc_write_reg(struct isp_ic_dev *dev, void __user *args) +{ + struct isp_reg_t reg; + + viv_check_retval((copy_from_user(®, args, sizeof(reg)))); + isp_write_reg(dev, reg.offset, reg.val); + return 0; +} + +int isp_ioc_disable_isp_off(struct isp_ic_dev *dev, void __user *args) +{ + u32 isp_imsc; + + isp_info("enter %s\n", __func__); + isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + isp_imsc &= ~MRV_ISP_IMSC_ISP_OFF_MASK; + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_g_awbmean(struct isp_ic_dev *dev, struct isp_awb_mean *mean) +{ + u32 reg = isp_read_reg(dev, REG_ADDR(isp_awb_mean)); + + /* isp_info("enter %s\n", __func__); */ + mean->g = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_Y__G); + mean->b = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CB__B); + mean->r = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CR__R); + mean->no_white_count = isp_read_reg(dev, REG_ADDR(isp_awb_white_cnt)); + + return 0; +} + +int isp_s_ee(struct isp_ic_dev *dev) +{ +#ifndef ISP_EE + //isp_err("unsupported function: %s\n", __func__); + return -EINVAL; +#else + struct isp_ee_context *ee = &dev->ee; + u32 isp_ee_ctrl = isp_read_reg(dev, REG_ADDR(isp_ee_ctrl)); + u32 gain = 0; + + //isp_info("enter %s\n", __func__); + + if (!ee->enable) { + isp_write_reg(dev, REG_ADDR(isp_ee_ctrl), + isp_ee_ctrl & ~EE_CTRL_ENABLE_MASK); + return 0; + } + + REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_INPUT_SEL, ee->input_sel); + REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_SOURCE_STRENGTH, ee->src_strength); + REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_STRENGTH, ee->strength); + REG_SET_SLICE(gain, EE_UV_GAIN, ee->uv_gain); + REG_SET_SLICE(gain, EE_EDGE_GAIN, ee->edge_gain); + isp_write_reg(dev, REG_ADDR(isp_ee_y_gain), ee->y_gain); + isp_write_reg(dev, REG_ADDR(isp_ee_uv_gain), gain); + isp_write_reg(dev, REG_ADDR(isp_ee_ctrl), + isp_ee_ctrl | EE_CTRL_ENABLE_MASK); + //isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_s_exp(struct isp_ic_dev *dev) +{ + struct isp_exp_context *exp = &dev->exp; + u32 isp_exp_ctrl = isp_read_reg(dev, REG_ADDR(isp_exp_ctrl)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + + isp_info("enter %s\n", __func__); + + if (!exp->enable) { + REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 0); + isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc & ~MRV_ISP_IMSC_EXP_END_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_exp_h_offset), + (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x)); + isp_write_reg(dev, REG_ADDR(isp_exp_v_offset), + (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y)); + isp_write_reg(dev, REG_ADDR(isp_exp_h_size), + (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width)); + isp_write_reg(dev, REG_ADDR(isp_exp_v_size), + (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height)); +#ifdef ISP_AE_SHADOW + isp_write_reg(dev, REG_ADDR(isp_exp_h_offset_shd), + (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x)); + isp_write_reg(dev, REG_ADDR(isp_exp_v_offset_shd), + (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y)); + isp_write_reg(dev, REG_ADDR(isp_exp_h_size_shd), + (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width)); + isp_write_reg(dev, REG_ADDR(isp_exp_v_size_shd), + (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height)); +#endif + REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_MEAS_MODE, exp->mode); + REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 1); + isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_EXP_END_MASK); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_hdrexp(struct isp_ic_dev *dev) +{ + struct isp_exp_context *hdrexp = &dev->hdrexp; + u32 isp_hdr_exp_conf = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_conf)); + u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc)); + + pr_info("enter %s\n", __func__); + if (!dev->hdrexp.enable) { + pr_info("%s, hdr disabled\n",__func__); + REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 0); + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf); + isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc & ~0x38); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_offset), + (MRV_ISP_HDR_EXP_H_OFFSET_MASK & hdrexp->window.x)); + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_offset), + (MRV_ISP_HDR_EXP_V_OFFSET_MASK & hdrexp->window.y)); + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_size), + (MRV_ISP_HDR_EXP_H_SIZE_MASK & hdrexp->window.width)); + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_size), + (MRV_ISP_HDR_EXP_V_SIZE_MASK & hdrexp->window.height)); + + REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_MEAS_MODE, hdrexp->mode); + REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_SRC_SEL, 1); //hardware only support 1 + REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 1); + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf); + isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x38); + return 0; +} + +int isp_g_expmean(struct isp_ic_dev *dev, u8 *mean) +{ + int i = 0; + + /* isp_info("enter %s\n", __func__); */ + if (!dev || !mean) + return -EINVAL; + for (; i < 25; i++) { + mean[i] = isp_read_reg(dev, REG_ADDR(isp_exp_mean_00) + i * 4); + } + + return 0; +} + +int isp_g_hdrexpmean(struct isp_ic_dev *dev, u8 * mean) +{ + int i = 0; + + pr_info("enter %s\n", __func__); + if (!dev || !mean) + return -EINVAL; + for (; i < 75; i++) { + mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_statistics[i])); + } + + return 0; +} + +#ifdef ISP_HIST256 +#define HIST_BIN_TOTAL 256 +#else +#define HIST_BIN_TOTAL 16 +#endif + +int isp_s_hist(struct isp_ic_dev *dev) +{ + struct isp_hist_context *hist = &dev->hist; + +#ifdef ISP_HIST256 + u32 isp_hist256_prop = isp_read_reg(dev, REG_ADDR(isp_hist256_prop)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + int i; + + if (!hist->enable) { + REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE, + MRV_HIST_MODE_NONE); + isp_write_reg(dev, REG_ADDR(isp_hist256_prop), + isp_hist256_prop); + //isp_write_reg(dev, REG_ADDR(isp_imsc), + // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_hist256_h_offs), + (MRV_HIST_H_OFFSET_MASK & hist->window.x)); + isp_write_reg(dev, REG_ADDR(isp_hist256_v_offs), + (MRV_HIST_V_OFFSET_MASK & hist->window.y)); + isp_write_reg(dev, REG_ADDR(isp_hist256_h_size), + (MRV_HIST_H_SIZE_MASK & hist->window.width)); + isp_write_reg(dev, REG_ADDR(isp_hist256_v_size), + (MRV_HIST_V_SIZE_MASK & hist->window.height)); + + for (i = 0; i < 24; i += 4) { + isp_write_reg(dev, REG_ADDR(isp_hist256_weight_00to30) + i, + hist->weight[i + + 0] | (hist->weight[i + + 1] << 8) | + (hist->weight[i + 2] << 16) | (hist->weight[i + + 3] << + 24)); + } + + isp_write_reg(dev, REG_ADDR(isp_hist256_weight_44), hist->weight[24]); + REG_SET_SLICE(isp_hist256_prop, MRV_HIST_STEPSIZE, hist->step_size); + REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE, hist->mode); + isp_write_reg(dev, REG_ADDR(isp_hist256_prop), isp_hist256_prop); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); +#else + u32 isp_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hist_prop)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + int i; + + isp_info("enter %s\n", __func__); + if (!hist->enable) { + REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE); + isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop); + //isp_write_reg(dev, REG_ADDR(isp_imsc), + // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_hist_h_offs), + (MRV_HIST_H_OFFSET_MASK & hist->window.x)); + isp_write_reg(dev, REG_ADDR(isp_hist_v_offs), + (MRV_HIST_V_OFFSET_MASK & hist->window.y)); + isp_write_reg(dev, REG_ADDR(isp_hist_h_size), + (MRV_HIST_H_SIZE_MASK & hist->window.width)); + isp_write_reg(dev, REG_ADDR(isp_hist_v_size), + (MRV_HIST_V_SIZE_MASK & hist->window.height)); + + for (i = 0; i < 24; i += 4) { + isp_write_reg(dev, REG_ADDR(isp_hist_weight_00to30) + i, + hist->weight[i + 0] | + (hist->weight[i + 1] << 8) | + (hist->weight[i + 2] << 16) | + (hist->weight[i + 3] << 24)); + } + + isp_write_reg(dev, REG_ADDR(isp_hist_weight_44), hist->weight[24]); + REG_SET_SLICE(isp_hist_prop, MRV_HIST_STEPSIZE, hist->step_size); + REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, hist->mode); + isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); + isp_info("exit %s\n", __func__); +#endif + return 0; +} + +int isp_s_hdrhist(struct isp_ic_dev *dev) +{ + struct isp_hist_context *hdrhist = &dev->hdrhist; + u32 isp_hdr_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_prop)); + u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc)); + + pr_info("enter %s\n", __func__); + if (!dev->hdrhist.enable) { + pr_info("%s, hdr disable\n", __func__); + REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE); + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop); + isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), + isp_stitching_imsc & ~0x1c0); + return 0; + } + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_offs), + (MRV_HIST_H_OFFSET_MASK & hdrhist->window.x)); + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_offs), + (MRV_HIST_V_OFFSET_MASK & hdrhist->window.y)); + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_size), + (MRV_HIST_H_SIZE_MASK & hdrhist->window.width)); + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_size), + (MRV_HIST_V_SIZE_MASK & hdrhist->window.height)); + + REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_STEPSIZE, hdrhist->step_size); + REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, hdrhist->mode); + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop); + isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x1c0); + return 0; +} + +int isp_g_histmean(struct isp_ic_dev *dev, u32 *mean) +{ + int i = 0; + + /* isp_info("enter %s\n", __func__); */ + if (!dev || !mean) + return -EINVAL; +#ifdef ISP_HIST256 + for (; i < HIST_BIN_TOTAL; i++) { + mean[i] = isp_read_reg(dev, REG_ADDR(isp_hist256_bin_n)); + } +#else + for (; i < HIST_BIN_TOTAL; i++) { + mean[i] = isp_read_reg(dev, + REG_ADDR(histogram_measurement_result_arr[i])); + + } +#endif + return 0; +} + +int isp_g_hdrhistmean(struct isp_ic_dev *dev, u32 * mean) +{ + int i = 0; + + pr_info("enter %s\n", __func__); + if (!dev || !mean) + return -EINVAL; + + // size is fixed 48 now, contain 3 channels + for (; i < 48; i++) { + mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_statistics[i])); + } + return 0; +} + +int isp_s_hist64(struct isp_ic_dev *dev) +{ +#ifndef ISP_HIST64 + //pr_err("Not supported hist64 module\n"); + return -1; +#else + struct isp_hist64_context *hist64 = &dev->hist64; + + u32 isp64_hist_prop = isp_read_reg(dev, REG_ADDR(isp64_hist_prop)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + u32 isp64_hist_subsampling = isp_read_reg(dev, REG_ADDR(isp64_hist_subsampling)); + u32 isp64_hist_sample_range = isp_read_reg(dev, REG_ADDR(isp64_hist_sample_range)); + + u32 isp64_hist_coeff_r = 0, isp64_hist_coeff_g = 0, isp64_hist_coeff_b = 0; + int i; + + if (!hist64->enable) { + REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE, + MRV_HIST_MODE_NONE); + isp_write_reg(dev, REG_ADDR(isp64_hist_prop), + isp64_hist_prop); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); + //isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl), + /// hist64->enable & ~MRV_HIST_UPDATE_ENABLE_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp64_hist_h_offs), + (MRV_HIST_H_OFFSET_MASK & hist64->window.x)); + isp_write_reg(dev, REG_ADDR(isp64_hist_v_offs), + (MRV_HIST_V_OFFSET_MASK & hist64->window.y)); + isp_write_reg(dev, REG_ADDR(isp64_hist_h_size), + (MRV_HIST_H_SIZE_MASK & hist64->window.width)); + isp_write_reg(dev, REG_ADDR(isp64_hist_v_size), + (MRV_HIST_V_SIZE_MASK & hist64->window.height)); + + for (i = 0; i < 24; i += 4) { + isp_write_reg(dev, REG_ADDR(isp64_hist_weight_00to30) + i, + hist64->weight[i + + 0] | (hist64->weight[i + + 1] << 8) | + (hist64->weight[i + 2] << 16) | (hist64->weight[i + + 3] << + 24)); + } + + isp_write_reg(dev, REG_ADDR(isp64_hist_weight_44), hist64->weight[24]); + REG_SET_SLICE(isp64_hist_prop, MRV_HIST_CHANNEL_SELECT, hist64->channel); + REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE, hist64->mode); + + REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_V_STEPSIZE, hist64->vStepSize); + REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_H_STEP_INC, hist64->hStepInc); + + REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_OFFSET, hist64->sample_offset); + REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_SHIFT, hist64->sample_shift); + + REG_SET_SLICE(isp64_hist_coeff_r, MRV_HIST_COEFF_R, hist64->r_coeff); + REG_SET_SLICE(isp64_hist_coeff_g, MRV_HIST_COEFF_G, hist64->g_coeff); + REG_SET_SLICE(isp64_hist_coeff_b, MRV_HIST_COEFF_B, hist64->b_coeff); + isp_write_reg(dev, REG_ADDR(isp64_hist_subsampling), isp64_hist_subsampling); + isp_write_reg(dev, REG_ADDR(isp64_hist_sample_range), isp64_hist_sample_range); + isp_write_reg(dev, REG_ADDR(isp64_hist_prop), isp64_hist_prop); + + isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_r), isp64_hist_coeff_r); + isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_g), isp64_hist_coeff_g); + isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_b), isp64_hist_coeff_b); + + isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl), + hist64->enable); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); + + return 0; +#endif +} + +#define HIST64_BIN_TOTAL 32 +int isp_g_hist64mean(struct isp_ic_dev *dev, u32 *mean) +{ +#ifndef ISP_HIST64 + //pr_err("Not supported hist64 module\n"); + return -1; +#else + int i = 0; + + isp_info("enter %s\n", __func__); + if (!dev || !mean) + return -EINVAL; + + for (; i < HIST64_BIN_TOTAL; i++) { + mean[i] = isp_read_reg(dev, + REG_ADDR(isp64_histogram_measurement_result_arr[i])); + + } + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_g_hist64_vstart_status(struct isp_ic_dev *dev, u32 *status) +{ +#ifndef ISP_HIST64 + //pr_err("Not supported hist64 module\n"); + return -1; +#else + + /* isp_info("enter %s\n", __func__); */ + if (!dev || !status) + return -EINVAL; + + *status = isp_read_reg(dev, REG_ADDR(isp64_hist_vstart_status)); + + return 0; +#endif +} + +int isp_update_hist64(struct isp_ic_dev *dev) +{ +#ifndef ISP_HIST64 + //pr_err("Not supported hist64\n"); + return -1; +#else + struct isp_hist64_context* hist64 =&dev->hist64; + + isp_write_reg(dev, REG_ADDR(isp64_hist_forced_upd_start_line),hist64->forced_upd_start_line); + isp_write_reg(dev, REG_ADDR(isp64_hist_forced_update), hist64->forced_upd); + + return 0; +#endif +} + +int isp_s_ge(struct isp_ic_dev *dev) +{ +#ifndef ISP_GREENEQUILIBRATE + //isp_err("unsupported function %s\n", __func__); + return -1; +#else + struct isp_ge_context *ge = &dev->ge; + u32 green_equilibrate_ctrl = + isp_read_reg(dev, REG_ADDR(green_equilibrate_ctrl)); + u32 green_equilibrate_hcnt_dummy = 0; + + isp_info("enter %s\n", __func__); + + if (!ge->enable) { + REG_SET_SLICE(green_equilibrate_ctrl, + ISP_GREEN_EQUILIBTATE_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl), + green_equilibrate_ctrl); + return 0; + } + + REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_TH, + ge->threshold); + REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_ENABLE, 1); + REG_SET_SLICE(green_equilibrate_hcnt_dummy, + ISP_GREEN_EQUILIBTATE_HCNT_DUMMY, ge->h_dummy); + isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl), + green_equilibrate_ctrl); + isp_write_reg(dev, REG_ADDR(green_equilibrate_hcnt_dummy), + green_equilibrate_hcnt_dummy); + isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl_shd), + green_equilibrate_ctrl); + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_s_ca(struct isp_ic_dev *dev) +{ +#ifndef ISP_CA + //isp_err("unsupported function %s\n", __func__); + return -1; +#else + struct isp_ca_context *ca = &dev->ca; + u32 isp_curve_ctrl = isp_read_reg(dev, REG_ADDR(isp_curve_ctrl)); + // u32 isp_curve_lut_x_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_x_addr)); + // u32 isp_curve_lut_luma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_luma_addr)); + // u32 isp_curve_lut_chroma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr)); + // u32 isp_curve_lut_shift_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_shift_addr)); + + int i = 0; + /*isp_info("enter %s\n", __func__);*/ + if (!ca->enable) { + REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_addr), 0); + + for (i = 0; i < CA_CURVE_DATA_TABLE_LEN; i++) { + isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_write_data), + dev->ca.lut_x[i]); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_write_data), + dev->ca.lut_luma[i]); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_write_data), + dev->ca.lut_chroma[i]); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_write_data), + dev->ca.lut_shift[i]); + } + REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_MODE, dev->ca.mode); + REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl); + /*isp_info("exit %s\n", __func__);*/ + return 0; +#endif +} + +int isp_s_dpcc(struct isp_ic_dev *dev) +{ + struct isp_dpcc_context *dpcc = &dev->dpcc; + const u32 reg_gap = 20; + int i; + u32 isp_dpcc_mode = isp_read_reg(dev, REG_ADDR(isp_dpcc_mode)); + + isp_info("enter %s\n", __func__); + + if (!dpcc->enable) { + REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 0); + } else { + REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 1); + } + + isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), dpcc->mode); + isp_write_reg(dev, REG_ADDR(isp_dpcc_output_mode), dpcc->outmode); + isp_write_reg(dev, REG_ADDR(isp_dpcc_set_use), dpcc->set_use); + + for (i = 0; i < 3; i++) { + isp_write_reg(dev, REG_ADDR(isp_dpcc_methods_set_1) + i * 4, + 0x1FFF & dpcc->methods_set[i]); + isp_write_reg(dev, + REG_ADDR(isp_dpcc_line_thresh_1) + i * reg_gap, + 0xFFFF & dpcc->params[i].line_thresh); + isp_write_reg(dev, + REG_ADDR(isp_dpcc_line_mad_fac_1) + i * reg_gap, + 0x3F3F & dpcc->params[i].line_mad_fac); + isp_write_reg(dev, REG_ADDR(isp_dpcc_pg_fac_1) + i * reg_gap, + 0x3F3F & dpcc->params[i].pg_fac); + isp_write_reg(dev, + REG_ADDR(isp_dpcc_rnd_thresh_1) + i * reg_gap, + 0xFFFF & dpcc->params[i].rnd_thresh); + isp_write_reg(dev, REG_ADDR(isp_dpcc_rg_fac_1) + i * reg_gap, + 0x3F3F & dpcc->params[i].rg_fac); + } + + isp_write_reg(dev, REG_ADDR(isp_dpcc_ro_limits), dpcc->ro_limits); + isp_write_reg(dev, REG_ADDR(isp_dpcc_rnd_offs), dpcc->rnd_offs); + isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), isp_dpcc_mode); + isp_info("exit %s\n", __func__); + return 0; +} + + +int isp_s_flt(struct isp_ic_dev *dev) +{ + struct flt_denoise_type { + u32 thresh_sh0; + u32 thresh_sh1; + u32 thresh_bl0; + u32 thresh_bl1; + u32 stage_select; + u32 vmode; + u32 hmode; + }; + + struct flt_sharpen_type { + u32 fac_sh0; + u32 fac_sh1; + u32 fac_mid; + u32 fac_bl0; + u32 fac_bl1; + }; + + static struct flt_denoise_type denoise_tbl[] = { + {0, 0, 0, 0, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC8, + MRV_FILT_FILT_CHR_H_MODE_BYPASS}, + {18, 33, 8, 2, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {26, 44, 13, 5, 4, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {36, 51, 23, 10, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {41, 67, 26, 15, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {75, 10, 50, 20, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {90, 120, 60, 26, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {120, 150, 80, 51, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {170, 200, 140, 100, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {250, 300, 180, 150, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {1023, 1023, 1023, 1023, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {1023, 1023, 1023, 1023, 0, MRV_FILT_FILT_CHR_V_MODE_BYPASS, + MRV_FILT_FILT_CHR_H_MODE_BYPASS}, + }; + + static struct flt_sharpen_type sharpen_tbl[] = { + {0x4, 0x4, 0x4, 0x2, 0x0}, + {0x7, 0x8, 0x6, 0x2, 0x0}, + {0xA, 0xC, 0x8, 0x4, 0x0}, + {0xC, 0x10, 0xA, 0x6, 0x2}, + {0x16, 0x16, 0xC, 0x8, 0x4}, + {0x14, 0x1B, 0x10, 0xA, 0x4}, + {0x1A, 0x20, 0x13, 0xC, 0x6}, + {0x1E, 0x26, 0x17, 0x10, 0x8}, + {0x24, 0x2C, 0x1D, 0x15, 0x0D}, + {0x2A, 0x30, 0x22, 0x1A, 0x14}, + {0x30, 0x3F, 0x28, 0x24, 0x20}, + }; + + // isp_info("enter %s\n", __func__); + + if(dev->flt.changed || !is_isp_enable(dev)) + { + struct isp_flt_context *flt = &dev->flt; + u32 isp_flt_mode = isp_read_reg(dev, REG_ADDR(isp_filt_mode)); + + if (!flt->enable) { + REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode); + return 0; + } + + if (flt->denoise >= 0) { + isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh0), + denoise_tbl[flt->denoise].thresh_sh0); + isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh1), + denoise_tbl[flt->denoise].thresh_sh1); + isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl0), + denoise_tbl[flt->denoise].thresh_bl0); + isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl1), + denoise_tbl[flt->denoise].thresh_bl1); + REG_SET_SLICE(isp_flt_mode, MRV_FILT_STAGE1_SELECT, + denoise_tbl[flt->denoise].stage_select); + REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_V_MODE, + denoise_tbl[flt->denoise].vmode); + REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_H_MODE, + denoise_tbl[flt->denoise].hmode); + } + + if (flt->sharpen >= 0) { + isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh0), + sharpen_tbl[flt->sharpen].fac_sh0); + isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh1), + sharpen_tbl[flt->sharpen].fac_sh1); + isp_write_reg(dev, REG_ADDR(isp_filt_fac_mid), + sharpen_tbl[flt->sharpen].fac_mid); + isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl0), + sharpen_tbl[flt->sharpen].fac_bl0); + isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl1), + sharpen_tbl[flt->sharpen].fac_bl1); + } + + REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_MODE, + MRV_FILT_FILT_MODE_DYNAMIC); + isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode); + REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode); + isp_write_reg(dev, REG_ADDR(isp_filt_lum_weight), 0x00032040); + + dev->flt.changed = false; + } else { + dev->flt.changed = true; + } + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_cac(struct isp_ic_dev *dev) +{ + struct isp_cac_context *cac = &dev->cac; + u32 val = 0; + u32 isp_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_cac_ctrl)); + + isp_info("enter %s\n", __func__); + + if (!cac->enable) { + REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 0); + isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl); + return 0; + } + + REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode); + REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode); + isp_write_reg(dev, REG_ADDR(isp_cac_count_start), + cac->hstart | (cac->vstart << 16)); + isp_write_reg(dev, REG_ADDR(isp_cac_a), cac->ar | (cac->ab << 16)); + isp_write_reg(dev, REG_ADDR(isp_cac_b), cac->br | (cac->bb << 16)); + isp_write_reg(dev, REG_ADDR(isp_cac_c), cac->cr | (cac->cb << 16)); + + REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns); + REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf); + isp_write_reg(dev, REG_ADDR(isp_cac_x_norm), val); + val = 0; + REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns); + REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf); + isp_write_reg(dev, REG_ADDR(isp_cac_y_norm), val); + REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 1); + isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_deg(struct isp_ic_dev *dev) +{ + struct isp_deg_context *deg = &dev->deg; + int i; + u32 isp_gamma_dx_lo = 0; + u32 isp_gamma_dx_hi = 0; + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + isp_info("enter %s\n", __func__); + + if (!deg->enable) { + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + return 0; + } + + for (i = 0; i < 8; i++) { + isp_gamma_dx_lo |= deg->segment[i] << (i * 4); + isp_gamma_dx_hi |= deg->segment[i + 8] << (i * 4); + } + + isp_write_reg(dev, REG_ADDR(isp_gamma_dx_lo), isp_gamma_dx_lo); + isp_write_reg(dev, REG_ADDR(isp_gamma_dx_hi), isp_gamma_dx_hi); + + for (i = 0; i < 17; i++) { + isp_write_reg(dev, REG_ADDR(degamma_r_y_block_arr[i]), + deg->r[i]); + isp_write_reg(dev, REG_ADDR(degamma_g_y_block_arr[i]), + deg->g[i]); + isp_write_reg(dev, REG_ADDR(degamma_b_y_block_arr[i]), + deg->b[i]); + } + + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +static u32 get_eff_coeff(int decimal) +{ + u32 value = 0; + + if (decimal <= -6) + value = 15; + else if (decimal <= -3) + value = 14; + else if (decimal == -2) + value = 13; + else if (decimal == -1) + value = 12; + else if (decimal == 0) + value = 0; + else if (decimal == 1) + value = 8; + else if (decimal == 2) + value = 9; + else if (decimal < 6) + value = 10; + else + value = 11; + + return value; +} + +int isp_s_ie(struct isp_ic_dev *dev) +{ + struct isp_ie_context *ie = &dev->ie; + u32 img_eff_ctrl = isp_read_reg(dev, REG_ADDR(img_eff_ctrl)); + u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl)); + u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl)); + u32 img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint)); + u32 img_eff_color_sel = isp_read_reg(dev, REG_ADDR(img_eff_color_sel)); + u32 mat[9]; + u32 sharpen = 0; + int i; + + isp_info("enter %s\n", __func__); + + REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 1); + isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + + if (!ie->enable) { + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD, + MRV_IMGEFF_CFG_UPD_UPDATE); + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE, + MRV_IMGEFF_BYPASS_MODE_BYPASS); + REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); + isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl); + return 0; + } + + REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 0); + isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + + REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_EFFECT_MODE, ie->mode); + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_FULL_RANGE, ie->full_range); + + for (i = 0; i < 9; i++) + mat[i] = get_eff_coeff(ie->m[i]); + + if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SEPIA) { + img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint)); + REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CR, ie->tint_cr); + REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CB, ie->tint_cb); + isp_write_reg(dev, REG_ADDR(img_eff_tint), img_eff_tint); + } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_COLOR_SEL) { + REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_SELECTION, + ie->color_sel); + REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_THRESHOLD, + ie->color_thresh); + isp_write_reg(dev, REG_ADDR(img_eff_color_sel), + img_eff_color_sel); + } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_EMBOSS) { + isp_write_reg(dev, REG_ADDR(img_eff_mat_1), + mat[0] | (mat[1] << 4) | (mat[2] << 8) | (mat[3] + << 12)); + isp_write_reg(dev, REG_ADDR(img_eff_mat_2), + mat[4] | (mat[5] << 4) | (mat[6] << 8) | (mat[7] + << 12)); + isp_write_reg(dev, REG_ADDR(img_eff_mat_3), mat[8]); + } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SKETCH || + ie->mode == MRV_IMGEFF_EFFECT_MODE_SHARPEN) { + isp_write_reg(dev, REG_ADDR(img_eff_mat_3), + (mat[0] << 4) | (mat[1] << 8) | (mat[2] << 12)); + isp_write_reg(dev, REG_ADDR(img_eff_mat_4), + mat[3] | (mat[4] << 4) | (mat[5] << 8) | (mat[6] + << 12)); + isp_write_reg(dev, REG_ADDR(img_eff_mat_5), + mat[7] | (mat[8] << 4)); + REG_SET_SLICE(sharpen, MRV_IMGEFF_SHARP_FACTOR, + ie->sharpen_factor); + REG_SET_SLICE(sharpen, MRV_IMGEFF_CORING_THR, + ie->sharpen_thresh); + isp_write_reg(dev, REG_ADDR(img_eff_sharpen), sharpen); + } + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD, + MRV_IMGEFF_CFG_UPD_UPDATE); + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE, + MRV_IMGEFF_BYPASS_MODE_PROCESS); + isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_vsm(struct isp_ic_dev *dev) +{ + struct isp_vsm_context *vsm = &dev->vsm; + u32 isp_vsm_mode = isp_read_reg(dev, REG_ADDR(isp_vsm_mode)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + + isp_info("enter %s\n", __func__); + + if (!vsm->enable) { + REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 0); + REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc & ~MRV_ISP_IMSC_VSM_END_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_vsm_h_offs), vsm->window.x); + isp_write_reg(dev, REG_ADDR(isp_vsm_v_offs), vsm->window.y); + isp_write_reg(dev, REG_ADDR(isp_vsm_h_size), + vsm->window.width & 0xFFFFE); + isp_write_reg(dev, REG_ADDR(isp_vsm_v_size), + vsm->window.height & 0xFFFFE); + isp_write_reg(dev, REG_ADDR(isp_vsm_h_segments), vsm->h_seg); + isp_write_reg(dev, REG_ADDR(isp_vsm_v_segments), vsm->v_seg); + REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 1); + REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_VSM_END_MASK); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_g_vsm(struct isp_ic_dev *dev, struct isp_vsm_result *vsm) +{ + isp_info("enter %s\n", __func__); + vsm->x = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_h)); + vsm->y = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_v)); + isp_info("exit %s\n", __func__); + return 0; +} + +#if 0 +u32 get_afm_shift(u32 count, u32 thresh) +{ + u32 grad = count; + u32 shift = 0; + + while (grad > (thresh)) { + ++shift; + grad >>= 1; + } + + return shift; +} +#endif + +int isp_s_afm(struct isp_ic_dev *dev) +{ + struct isp_afm_context *afm = &dev->afm; + u32 mask = + (MRV_ISP_IMSC_AFM_FIN_MASK | MRV_ISP_IMSC_AFM_LUM_OF_MASK | + MRV_ISP_IMSC_AFM_SUM_OF_MASK); + + u32 shift = 0; + int i; + + u32 isp_afm_ctrl = isp_read_reg(dev, REG_ADDR(isp_afm_ctrl)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + + isp_info("enter %s\n", __func__); + + if (!afm->enable) { + REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 0); + isp_imsc &= ~mask; + isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl); + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + return 0; + } + + for (i = 0; i < 3; i++) { + isp_write_reg(dev, REG_ADDR(isp_afm_lt_a) + i * 8, + (afm->window[i].x << 16) | afm->window[i].y); + isp_write_reg(dev, REG_ADDR(isp_afm_rb_a) + i * 8, + ((afm->window[i].x + afm->window[i].width - + 1) << 16) | ((afm->window[i].y + + afm->window[i].height - 1))); + } + + REG_SET_SLICE(shift, MRV_AFM_LUM_VAR_SHIFT, afm->lum_shift); + REG_SET_SLICE(shift, MRV_AFM_AFM_VAR_SHIFT, afm->afm_shift); + isp_write_reg(dev, REG_ADDR(isp_afm_var_shift), shift); + isp_write_reg(dev, REG_ADDR(isp_afm_thres), afm->thresh); + REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 1); + isp_imsc |= mask; + isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl); + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_g_afm(struct isp_ic_dev *dev, struct isp_afm_result *afm) +{ + isp_debug("enter %s\n", __func__); + afm->sum_a = isp_read_reg(dev, REG_ADDR(isp_afm_sum_a)); + afm->sum_b = isp_read_reg(dev, REG_ADDR(isp_afm_sum_b)); + afm->sum_c = isp_read_reg(dev, REG_ADDR(isp_afm_sum_c)); + afm->lum_a = isp_read_reg(dev, REG_ADDR(isp_afm_lum_a)); + afm->lum_b = isp_read_reg(dev, REG_ADDR(isp_afm_lum_b)); + afm->lum_c = isp_read_reg(dev, REG_ADDR(isp_afm_lum_c)); + isp_debug("exit %s\n", __func__); + return 0; +} + +int isp_s_exp2_inputsel(struct isp_ic_dev *dev) +{ +#ifndef ISP_AEV2 + pr_err("unsupported function: %s\n", __func__); + return -EINVAL; +#else + struct isp_exp2_context *exp2 = &dev->exp2; + u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl)); + REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select); + isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl); + return 0; +#endif +} + +int isp_s_exp2_sizeratio(struct isp_ic_dev *dev, u32 h_size) +{ +#ifndef ISP_AEV2 + pr_err("unsupported function: %s\n", __func__); + return -EINVAL; +#else + u32 size_inv; + size_inv = isp_read_reg(dev, REG_ADDR(isp_expv2_size_invert)); + REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, h_size); + isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv); + return 0; +#endif +} + +int isp_s_exp2(struct isp_ic_dev *dev) +{ +#ifndef ISP_AEV2 + //isp_err("unsupported function: %s\n", __func__); + return -EINVAL; +#else + u32 miv2_ctrl, miv2_mp_fmt, miv2_mp_bus_id, miv2_mp_ctrl, miv2_ctrl_shd; + struct isp_exp2_context *exp2 = &dev->exp2; + u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl)); + u32 grid_w, grid_h; + u32 size, offset, size_inv, weight; + + isp_info("enter %s\n", __func__); + grid_w = ((exp2->window.width - 1) >> 6) << 1; + grid_h = ((exp2->window.height - 1) >> 6) << 1; + + if (!exp2->enable) { + REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl); + return 0; + } + size = 0; + REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_H, grid_w); + REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_V, grid_h); + offset = 0; + REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_H, exp2->window.x); + REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_V, exp2->window.y); + size_inv = 0; + REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, (65536 + grid_w/2) / grid_w); + REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_V, (65536 + grid_h/2) / grid_h); + weight = 0; + REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_R, exp2->r) + REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR, exp2->gr) + REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB, exp2->gb) + REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_B, exp2->b) + isp_write_reg(dev, REG_ADDR(isp_expv2_offset), offset); + isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv); + isp_write_reg(dev, REG_ADDR(isp_expv2_size), size); +#ifdef ISP_AE_SHADOW + isp_write_reg(dev, REG_ADDR(isp_expv2_offset_shd), offset); + isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert_shd), size_inv); + isp_write_reg(dev, REG_ADDR(isp_expv2_size_shd), size); +#endif + isp_write_reg(dev, REG_ADDR(isp_expv2_pixel_weight), weight); + + miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_base_ad_init), dev->exp2.pa); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_size_init), AEV2_DMA_SIZE); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_offs_cnt_init), 0); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_llength), AEV2_DMA_SIZE); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_width), 1024); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_height), 1); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_size), AEV2_DMA_SIZE); + + REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 1); + REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select); + isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl); + + miv2_ctrl_shd = isp_read_reg(dev, REG_ADDR(miv2_ctrl_shd)); + if (!(miv2_ctrl_shd && MP_YCBCR_PATH_ENABLE_MASK) && !(miv2_ctrl_shd && MP_RAW_PATH_ENABLE_MASK)) { + miv2_mp_fmt = isp_read_reg(dev, REG_ADDR(miv2_mp_fmt)); +#ifdef ISP_AEV2_V2 + REG_SET_SLICE(miv2_mp_fmt, MP_WR_JDP_DP_BIT, 1); +#endif + REG_SET_SLICE(miv2_mp_fmt, MP_WR_JDP_FMT, 0); + isp_write_reg(dev, REG_ADDR(miv2_mp_fmt), miv2_mp_fmt); + + miv2_mp_bus_id = isp_read_reg(dev, REG_ADDR(miv2_mp_bus_id)); + REG_SET_SLICE(miv2_mp_bus_id, MP_BUS_SW_EN, 1); + REG_SET_SLICE(miv2_mp_bus_id, MP_WR_ID_EN, 1); + isp_write_reg(dev, REG_ADDR(miv2_mp_bus_id), miv2_mp_bus_id); + + miv2_mp_ctrl = isp_read_reg(dev, REG_ADDR(miv2_mp_ctrl)); + REG_SET_SLICE(miv2_mp_ctrl, MP_AUTO_UPDATE, 1); + REG_SET_SLICE(miv2_mp_ctrl, MP_INIT_BASE_EN, 1); + REG_SET_SLICE(miv2_mp_ctrl, MP_INIT_OFFSET_EN, 1); + isp_write_reg(dev, REG_ADDR(miv2_mp_ctrl), miv2_mp_ctrl); + } + isp_info("exit %s\n", __func__); + + return 0; +#endif +} + +int isp_s_2dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_2DNR + //isp_err("unsupported function: %s\n", __func__); + return -EINVAL; +#else + struct isp_2dnr_context *dnr2 = &dev->dnr2; + u32 isp_denoise2d_control = + isp_read_reg(dev, REG_ADDR(isp_denoise2d_control)); + u32 value, addr, strength; + u32 isp_ctrl; + int i; + + /*isp_info("enter %s\n", __func__);*/ + + if (!dnr2->enable) { +#ifndef ISP_2DNR_V4 + REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_control), + isp_denoise2d_control); +#else + value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 0); + if((value & DENOISE3D_V20_TNR_ENABLE_MASK) == 0) + REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), + value); + +#endif + return 0; + } + + strength = isp_read_reg(dev, REG_ADDR(isp_denoise2d_strength)); + REG_SET_SLICE(strength, ISP_2DNR_PRGAMMA_STRENGTH, dnr2->pre_gamma); + REG_SET_SLICE(strength, ISP_2DNR_STRENGTH, dnr2->strength); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength), strength); + + addr = REG_ADDR(isp_denoise2d_sigma_y[0]); + for (i = 0; i < 60; i += 5) { + value = 0; + REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i]); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 1]); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY2A, + dnr2->sigma[i + 2] >> 6); + isp_write_reg(dev, addr, value); + value = 0; + addr += 4; + REG_SET_SLICE(value, ISP_2DNR_SIGMAY2B, + dnr2->sigma[i + 2] & 0x3f); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i + 3]); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 4]); + isp_write_reg(dev, addr, value); + addr += 4; + } + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 1); + +#if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4) + isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr), dnr2->sigma_sqr); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr_shd), + dnr2->sigma_sqr); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor), + dnr2->weight); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor_shd), + dnr2->weight); + /* refer to HW spec for HBLANK */ + //isp_write_reg(dev, REG_ADDR(isp_denoise2d_dummy_hblank), 0); + + isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength_shd), strength); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_control_shd), + isp_denoise2d_control); +#endif + +#ifndef ISP_2DNR_V4 + isp_write_reg(dev, REG_ADDR(isp_denoise2d_control), + isp_denoise2d_control); +#else + value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_blending)); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_OFFSET, dnr2->str_off); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_MAX, dnr2->str_max); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_SLOPE, dnr2->str_slope); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_blending), value); + value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 1); + REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), + value); +#endif + /*isp_info("exit %s\n", __func__);*/ + return 0; +#endif +} + +int isp_s_simp(struct isp_ic_dev *dev) +{ + struct isp_simp_context *simp = &dev->simp; + u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl)); + u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl)); + u32 super_imp_ctrl = isp_read_reg(dev, REG_ADDR(super_imp_ctrl)); + + isp_info("enter %s\n", __func__); + + REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 1); + isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + + if (!simp->enable) { + REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); + return 0; + } + + REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 0); + isp_write_reg(dev, REG_ADDR(super_imp_offset_x), simp->x); + isp_write_reg(dev, REG_ADDR(super_imp_offset_y), simp->y); + isp_write_reg(dev, REG_ADDR(super_imp_color_y), simp->r); + isp_write_reg(dev, REG_ADDR(super_imp_color_cb), simp->g); + isp_write_reg(dev, REG_ADDR(super_imp_color_cr), simp->b); + REG_SET_SLICE(super_imp_ctrl, MRV_SI_TRANSPARENCY_MODE, + simp->transparency_mode); + REG_SET_SLICE(super_imp_ctrl, MRV_SI_REF_IMAGE, simp->ref_image); + isp_write_reg(dev, REG_ADDR(super_imp_ctrl), super_imp_ctrl); + isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_cproc(struct isp_ic_dev *dev) +{ + struct isp_cproc_context *cproc = &dev->cproc; + u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl)); + u32 cproc_ctrl = isp_read_reg(dev, REG_ADDR(cproc_ctrl)); + + //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 1); + //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + + //if there is no shd register. should update cporc register in isp frame end irq. +#ifndef ISP_CPROC_SHD + if(dev->cproc.changed || !is_isp_enable(dev)) + { +#endif + /*isp_info("enter %s %d\n", __func__, cproc->enable);*/ + if (!cproc->enable) { + REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 0); + /* REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 0); */ + /* isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); */ + isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl); + return 0; + } + + //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 0); + //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + isp_write_reg(dev, REG_ADDR(cproc_contrast), cproc->contrast); + isp_write_reg(dev, REG_ADDR(cproc_brightness), cproc->brightness); + isp_write_reg(dev, REG_ADDR(cproc_saturation), cproc->saturation); + isp_write_reg(dev, REG_ADDR(cproc_hue), cproc->hue); + REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 1); + REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_C_OUT_RANGE, + cproc->c_out_full); + REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_OUT_RANGE, + cproc->y_out_full); + REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_IN_RANGE, cproc->y_in_full); + REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); + isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl); + +#ifndef ISP_CPROC_SHD + dev->cproc.changed = false; + } else { + dev->cproc.changed = true; + } +#endif + /*isp_info("exit %s\n", __func__);*/ + return 0; +} + +int isp_s_elawb(struct isp_ic_dev *dev) +{ + struct isp_elawb_context *elawb = &dev->elawb; + u32 awb_meas_mode = isp_read_reg(dev, REG_ADDR(awb_meas_mode)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + u32 id = elawb->id; + u32 data; + + if (!elawb->enable) { + REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 0); + REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 0); + isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(awb_meas_h_offs), elawb->window.x); + isp_write_reg(dev, REG_ADDR(awb_meas_v_offs), elawb->window.y); + isp_write_reg(dev, REG_ADDR(awb_meas_h_size), elawb->window.width); + isp_write_reg(dev, REG_ADDR(awb_meas_v_size), elawb->window.height); + + if (id > 0 && id < 9) { + isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].x), + elawb->info[id - 1].x); + isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].y), + elawb->info[id - 1].y); + isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a1), + elawb->info[id - 1].a1); + isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a2), + elawb->info[id - 1].a2); + isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a3), + elawb->info[id - 1].a3); + isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a4), + elawb->info[id - 1].a4); + isp_write_reg(dev, REG_ADDR(awb_meas_rmax[id - 1]), + elawb->info[id - 1].r_max_sqr); + } + + data = 0; + REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_R, elawb->r); + REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_B, elawb->b); + isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), data); + data = 0; + REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GR, elawb->gr); + REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GB, elawb->gb); + isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), data); + + REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 1); + REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 1); + isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK); + + return 0; +} + +int isp_ioc_qcap(struct isp_ic_dev *dev, void __user *args) +{ + + /* use public VIDIOC_QUERYCAP to query the type of v4l-subdevs. */ +#ifdef __KERNEL__ +#ifndef USE_FPGA + struct v4l2_capability *cap = (struct v4l2_capability *)args; + strcpy((char *)cap->driver, "viv_isp_subdev"); + cap->bus_info[0] = (__u8)dev->id;//isp channel id +#else + struct v4l2_capability cap; + strcpy((char *)cap.driver, "viv_isp_subdev"); + cap.bus_info[0] = (__u8)dev->id;//isp channel id + isp_info("enter %s viv_isp_subdev\n", __func__); + viv_check_retval(copy_to_user + ((struct v4l2_capability *)args, &cap, sizeof(cap))); +#endif +#endif + return 0; +} + +int isp_ioc_g_status(struct isp_ic_dev *dev, void __user *args) +{ + u32 val = 0; + /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */ + viv_check_retval(copy_to_user(args, &val, sizeof(val))); + return 0; +} + +static u32 getScaleFactor(u32 src, u32 dst) +{ + if (dst > src) { + return ((65536 * (src - 1)) / (dst - 1)); + } else if (dst < src) { + return ((65536 * (dst - 1)) / (src - 1)) + 1; + } + return 65536; +} + +int isp_set_scaling(int id, struct isp_ic_dev *dev, bool stabilization, bool crop) +{ + u32 addr, ctrl; + u32 iw, ih, ow, oh; + u32 inputWidth, inputHeight, outputWidth, outputHeight; + u32 scale_hy, scale_hcb, scale_hcr, scale_vy, scale_vc; + struct isp_mi_data_path_context *path = &dev->mi.path[id]; + if (crop) { //enabled crop.Do not need to scaler. + isp_info("%s:The crop enabled ,So does not need to do scaler.\n", __func__); + return 0; + } + if (id == IC_MI_PATH_MAIN) { /* mp */ + addr = REG_ADDR(mrsz_ctrl); + } else if (id == IC_MI_PATH_SELF) { /* sp */ + addr = REG_ADDR(srsz_ctrl); + } else if (id == IC_MI_PATH_SELF2) { /* sp2 */ + addr = REG_ADDR(srsz2_ctrl); + } else { + return -EFAULT; + } + + inputWidth = path->in_width; + inputHeight = path->in_height; + outputWidth = path->out_width; + outputHeight = path->out_height; + + if (stabilization) { /* enabled image stabilization. */ + inputWidth = isp_read_reg(dev, REG_ADDR(isp_is_h_size)); + inputHeight = isp_read_reg(dev, REG_ADDR(isp_is_v_size)); + } + + ctrl = isp_read_reg(dev, addr); + iw = inputWidth / 2; + ih = inputHeight; + ow = outputWidth / 2; + oh = outputHeight; + + switch (path->in_mode) { + case IC_MI_DATAMODE_YUV422: + oh = outputHeight; + break; + case IC_MI_DATAMODE_YUV420: + oh = outputHeight / 2; /* scale cbcr */ + break; + case IC_MI_DATAMODE_YUV444: + oh = outputHeight; + break; + case IC_MI_DATAMODE_RGB888: + oh = outputHeight; + break; + default: + return -EFAULT; + } + + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_ENABLE, + inputWidth != outputWidth); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_ENABLE, + inputHeight != outputHeight); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_UP, inputWidth < outputWidth); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_UP, inputHeight < outputHeight); + scale_hy = getScaleFactor(inputWidth, outputWidth); + scale_vy = getScaleFactor(inputHeight, outputHeight); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_ENABLE, iw != ow); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_ENABLE, ih != oh); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_UP, iw < ow); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_UP, ih < oh); + scale_hcr = getScaleFactor(iw, ow); + scale_hcb = getScaleFactor(iw, ow); + scale_vc = getScaleFactor(ih, oh); + + /*Need to update immediately*/ + REG_SET_SLICE(ctrl, MRV_MRSZ_CFG_UPD, 1); + + if (id == IC_MI_PATH_MAIN) { + isp_write_reg(dev, REG_ADDR(mrsz_scale_vc), scale_vc); + isp_write_reg(dev, REG_ADDR(mrsz_scale_vy), scale_vy); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hcr), scale_hcr); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hcb), scale_hcb); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hy), scale_hy); + isp_write_reg(dev, REG_ADDR(mrsz_ctrl), ctrl); + } else if (id == IC_MI_PATH_SELF) { + isp_write_reg(dev, REG_ADDR(srsz_scale_vc), scale_vc); + isp_write_reg(dev, REG_ADDR(srsz_scale_vy), scale_vy); + isp_write_reg(dev, REG_ADDR(srsz_scale_hcr), scale_hcr); + isp_write_reg(dev, REG_ADDR(srsz_scale_hcb), scale_hcb); + isp_write_reg(dev, REG_ADDR(srsz_scale_hy), scale_hy); + isp_write_reg(dev, REG_ADDR(srsz_ctrl), ctrl); + } else if (id == IC_MI_PATH_SELF2) { + isp_write_reg(dev, REG_ADDR(srsz2_scale_vc), scale_vc); + isp_write_reg(dev, REG_ADDR(srsz2_scale_vy), scale_vy); + isp_write_reg(dev, REG_ADDR(srsz2_scale_hcr), scale_hcr); + isp_write_reg(dev, REG_ADDR(srsz2_scale_hcb), scale_hcb); + isp_write_reg(dev, REG_ADDR(srsz2_scale_hy), scale_hy); + isp_write_reg(dev, REG_ADDR(srsz2_ctrl), ctrl); + } + + return 0; +} + +typedef struct isp_crop_reg_s { + u32 crop_ctrl_addr; + u32 crop_x_dir_addr; + u32 crop_y_dir_addr; +} isp_crop_reg_t; + +int isp_set_crop(struct isp_ic_dev *dev) +{ + long ret = 0; + u32 crop_ctrl, crop_x_dir, crop_y_dir; + u8 i; + + isp_crop_reg_t crop_reg[ISP_MI_PATH_SP2_BP + 1] = { + { + REG_ADDR(mrsz_ctrl), + REG_ADDR(mrsz_phase_crop_x), + REG_ADDR(mrsz_phase_crop_y) + }, + { + REG_ADDR(srsz_ctrl), + REG_ADDR(srsz_phase_crop_x), + REG_ADDR(srsz_phase_crop_y) + }, + { + REG_ADDR(srsz2_ctrl), + REG_ADDR(srsz2_phase_crop_x), + REG_ADDR(srsz2_phase_crop_y) + } + }; + + struct isp_crop_context *crop = dev->crop; + for ( i = 0; i <= ISP_MI_PATH_SP2_BP; i++) { + crop_ctrl = isp_read_reg(dev, crop_reg[i].crop_ctrl_addr); + crop_x_dir = isp_read_reg(dev, crop_reg[i].crop_x_dir_addr); + crop_y_dir = isp_read_reg(dev, crop_reg[i].crop_y_dir_addr); + if (!crop[i].enabled) { +#ifndef ISP8000NANO_BASE + REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 0); +#endif + isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl); + continue; + } + REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_START, crop[i].window.x); + REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_START, crop[i].window.y); + REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_END, crop[i].window.width + crop[i].window.x - 1); //x_end = x + width -1 + REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_END, crop[i].window.height + crop[i].window.y - 1); //y_end = y + height -1 + +#ifndef ISP8000NANO_BASE + REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 1); + /*Need to update immediately*/ + REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CFG_UPD, 1); +#endif + + isp_write_reg(dev, crop_reg[i].crop_x_dir_addr, crop_x_dir); + isp_write_reg(dev, crop_reg[i].crop_y_dir_addr, crop_y_dir); + isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl); + + } + return ret; +} + +int isp_ioc_g_feature(struct isp_ic_dev *dev, void __user *args) +{ + u32 val = 0; + +#ifdef ISP_EE + val |= ISP_EE_SUPPORT; +#endif +#ifdef ISP_WDR3 + val |= ISP_WDR3_SUPPORT; +#endif +#ifdef ISP_2DNR + val |= ISP_2DNR_SUPPORT; +#endif +#ifdef ISP_3DNR + val |= ISP_3DNR_SUPPORT; +#endif +#ifdef ISP_WDR_V3 + val |= ISP_WDR3_SUPPORT; +#endif +#ifdef ISP_MIV2 + val |= ISP_MIV2_SUPPORT; +#endif +#ifdef ISP_AEV2 + val |= ISP_AEV2_SUPPORT; +#endif +#ifdef ISP_HDR_STITCH + val |= ISP_HDR_STITCH_SUPPORT; +#endif + viv_check_retval(copy_to_user(args, &val, sizeof(val))); + + return 0; +} + +int isp_ioc_g_feature_veresion(struct isp_ic_dev *dev, void __user *args) +{ + u32 val = 0; + + /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */ + viv_check_retval(copy_to_user(args, &val, sizeof(val))); + + return 0; +} + +static long isp_get_extmem(struct isp_ic_dev *dev, void __user *args) +{ + #define UT_USED_SIZE 0x01000000 + long ret = 0; + struct isp_extmem_info ext_mem; + + dev->ut_addr = dma_alloc_coherent(dev->device, UT_USED_SIZE, &dev->ut_phy_addr, GFP_KERNEL); + if (dev->ut_addr != NULL) { + ext_mem.addr = dev->ut_phy_addr; + ext_mem.size = UT_USED_SIZE; + } else { + return -1; + } + + ret = copy_to_user(args, &ext_mem, sizeof(struct isp_extmem_info)); + + return ret; +} + +long isp_priv_ioctl(struct isp_ic_dev *dev, unsigned int cmd, void __user *args) +{ + int ret = -1; + if (!dev) { + return ret; + } + /*pr_info("[%s:%d]cmd 0x%08x\n", __func__, __LINE__, cmd);*/ + switch (cmd) { + case ISPIOC_RESET: + if((ret = isp_mi_stop(dev)) != 0 ) + { + pr_err("[%s:%d]stop mi error before resetting!\n", __func__, __LINE__); + break; + } + if((ret = isp_stop_stream(dev)) != 0) + { + pr_err("[%s:%d]stop isp stream before resetting!\n", __func__, __LINE__); + break; + } + ret = isp_reset(dev); + break; + + case ISPIOC_WRITE_REG: + ret = isp_ioc_write_reg(dev, args); + break; + case ISPIOC_READ_REG: + ret = isp_ioc_read_reg(dev, args); + break; + case ISPIOC_GET_MIS: + ret = isp_ioc_read_mis(dev, args); + break; + case ISPIOC_ENABLE_TPG: + ret = isp_enable_tpg(dev); + break; + case ISPIOC_DISABLE_TPG: + ret = isp_disable_tpg(dev); + break; + case ISPIOC_ENABLE_BLS: + ret = isp_enable_bls(dev); + break; + case ISPIOC_DISABLE_BLS: + ret = isp_disable_bls(dev); + break; + case ISPIOC_START_DMA_READ: + ret = isp_ioc_start_dma_read(dev, args); + break; + case ISPIOC_CFG_DMA: + ret = isp_ioc_cfg_dma(dev, args); + break; + case ISPIOC_MI_STOP: + ret = isp_mi_stop(dev); + break; + case ISPIOC_DISABLE_ISP_OFF: + ret = isp_ioc_disable_isp_off(dev, args); + break; + case ISPIOC_ISP_STOP: + ret = isp_stop_stream(dev); + if(!ret) { + dev->streaming = false; + } + break; + case ISPIOC_ENABLE: + ret = isp_enable(dev); + break; + case ISPIOC_DISABLE: + ret = isp_disable(dev); + break; + case ISPIOC_ISP_STATUS:{ + bool enable = is_isp_enable(dev); + viv_check_retval(copy_to_user + (args, &enable, sizeof(bool))); + ret = 0; + break; + } + case ISPIOC_ENABLE_LSC: + ret = isp_enable_lsc(dev); + break; + case ISPIOC_DISABLE_LSC: + ret = isp_disable_lsc(dev); + break; + case ISPIOC_S_DIGITAL_GAIN: + viv_check_retval(copy_from_user + (&dev->dgain, args, sizeof(dev->dgain))); + ret = isp_s_digital_gain(dev); + break; +#ifdef ISP_DEMOSAIC2 + case ISPIOC_S_DMSC_INTP: + viv_check_retval(copy_from_user + (&dev->demosaic.intp, args, + sizeof(dev->demosaic.intp))); + ret = isp_set_dmsc_intp(dev); + break; + case ISPIOC_S_DMSC_DMOI: + viv_check_retval(copy_from_user + (&dev->demosaic.demoire, args, + sizeof(dev->demosaic.demoire))); + ret = isp_set_dmsc_dmoi(dev); + break; + case ISPIOC_S_DMSC_SKIN: + viv_check_retval(copy_from_user + (&dev->demosaic.skin, args, + sizeof(dev->demosaic.skin))); + ret = isp_set_dmsc_skin(dev); + break; + case ISPIOC_S_DMSC_SHAP: + viv_check_retval(copy_from_user + (&dev->demosaic.sharpen, args, + sizeof(dev->demosaic.sharpen))); + ret = isp_set_dmsc_sharpen(dev); + break; + case ISPIOC_S_DMSC_SHAP_LINE: + viv_check_retval(copy_from_user + (&dev->demosaic.sharpenLine, args, + sizeof(dev->demosaic.sharpenLine))); + ret = isp_set_dmsc_sharpen_line(dev); + break; + case ISPIOC_S_DMSC_CAC: + viv_check_retval(copy_from_user + (&dev->cac, args, sizeof(dev->cac))); + + ret = isp_set_dmsc_cac(dev); + break; + case ISPIOC_S_DMSC_DEPURPLE: + viv_check_retval(copy_from_user + (&dev->demosaic.depurple, args, + sizeof(dev->demosaic.depurple))); + ret = isp_set_dmsc_depurple(dev); + break; + case ISPIOC_S_DMSC_GFILTER: + viv_check_retval(copy_from_user + (&dev->demosaic.gFilter, args, + sizeof(dev->demosaic.gFilter))); + ret = isp_set_dmsc_gfilter(dev); + break; + case ISPIOC_S_DMSC: + viv_check_retval(copy_from_user + (&dev->demosaic, args, sizeof(dev->demosaic))); + ret = isp_s_dmsc(dev); + break; +#endif + case ISPIOC_ENABLE_AWB: + ret = isp_enable_awb(dev); + break; + case ISPIOC_DISABLE_AWB: + ret = isp_disable_awb(dev); + break; + case ISPIOC_ENABLE_WB: + ret = isp_enable_wb(dev, 1); + break; + case ISPIOC_DISABLE_WB: + ret = isp_enable_wb(dev, 0); + break; + case ISPIOC_ENABLE_GAMMA_OUT: + ret = isp_enable_gamma_out(dev, 1); + break; + case ISPIOC_DISABLE_GAMMA_OUT: + ret = isp_enable_gamma_out(dev, 0); + break; +#if defined(ISP_3DNR) || defined(ISP_3DNR_V2_V1) + case ISPIOC_R_3DNR: + viv_check_retval(copy_from_user + (&dev->dnr3, args, sizeof(dev->dnr3))); + ret = isp_r_3dnr(dev); + break; +#endif + case ISPIOC_S_IS: + viv_check_retval(copy_from_user + (&dev->is, args, sizeof(dev->is))); + ret = isp_s_is(dev); + break; + case ISPIOC_S_RAW_IS: + viv_check_retval(copy_from_user + (&dev->rawis, args, sizeof(dev->rawis))); + ret = isp_s_raw_is(dev); + break; + case ISPIOC_S_CC: + viv_check_retval(copy_from_user + (&dev->cc, args, sizeof(dev->cc))); + ret = isp_s_cc(dev); + break; + case ISPIOC_S_EE: + viv_check_retval(copy_from_user + (&dev->ee, args, sizeof(dev->ee))); + ret = isp_s_ee(dev); + break; + case ISPIOC_S_IE: + viv_check_retval(copy_from_user + (&dev->ie, args, sizeof(dev->ie))); + ret = isp_s_ie(dev); + break; + case ISPIOC_S_TPG: + viv_check_retval(copy_from_user + (&dev->tpg, args, sizeof(dev->tpg))); + ret = isp_s_tpg(dev); + break; + case ISPIOC_S_BLS: + viv_check_retval(copy_from_user + (&dev->bls, args, sizeof(dev->bls))); + ret = isp_s_bls(dev); + break; + case ISPIOC_BYPASS_MCM: + viv_check_retval(copy_from_user + (&dev->mcm, args, sizeof(dev->mcm))); + ret = isp_bypass_mcm(dev); + break; + case ISPIOC_S_MCM_WR: + viv_check_retval(copy_from_user + (&dev->mcm, args, sizeof(dev->mcm))); + ret = isp_s_mcm_wr(dev); + break; + case ISPIOC_S_MUX: + viv_check_retval(copy_from_user + (&dev->mux, args, sizeof(dev->mux))); + ret = isp_s_mux(dev); + break; + case ISPIOC_S_AWB: + viv_check_retval(copy_from_user + (&dev->awb, args, sizeof(dev->awb))); + ret = isp_s_awb(dev); + break; + case ISPIOC_S_LSC_TBL: + viv_check_retval(copy_from_user + (&dev->lsc, args, sizeof(dev->lsc))); + ret = isp_s_lsc_tbl(dev); + break; + case ISPIOC_S_LSC_SEC: + viv_check_retval(copy_from_user + (&dev->lsc, args, sizeof(dev->lsc))); + ret = isp_s_lsc_sec(dev); + break; + case ISPIOC_S_DPF: + viv_check_retval(copy_from_user + (&dev->dpf, args, sizeof(dev->dpf))); + ret = isp_s_dpf(dev); + break; + case ISPIOC_S_EXP: + viv_check_retval(copy_from_user + (&dev->exp, args, sizeof(dev->exp))); + ret = isp_s_exp(dev); + break; + case ISPIOC_S_HDREXP: + viv_check_retval(copy_from_user + (&dev->hdrexp, args, sizeof(dev->hdrexp))); + ret = isp_s_hdrexp(dev); + break; + case ISPIOC_S_CNR: + viv_check_retval(copy_from_user + (&dev->cnr, args, sizeof(dev->cnr))); + ret = isp_s_cnr(dev); + break; + case ISPIOC_S_FLT: + { + viv_check_retval(copy_from_user + (&dev->flt, args, sizeof(dev->flt))); + ret = isp_s_flt(dev); + + break; + } + case ISPIOC_S_CAC: + viv_check_retval(copy_from_user + (&dev->cac, args, sizeof(dev->cac))); + ret = isp_s_cac(dev); + break; + case ISPIOC_S_DEG: + viv_check_retval(copy_from_user + (&dev->deg, args, sizeof(dev->deg))); + ret = isp_s_deg(dev); + break; + case ISPIOC_S_VSM: + viv_check_retval(copy_from_user + (&dev->vsm, args, sizeof(dev->vsm))); + ret = isp_s_vsm(dev); + break; + case ISPIOC_S_AFM: + viv_check_retval(copy_from_user + (&dev->afm, args, sizeof(dev->afm))); + ret = isp_s_afm(dev); + break; + case ISPIOC_S_HDR: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + ret = isp_s_hdr(dev); + break; + case ISPIOC_ENABLE_HDR: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + ret = isp_enable_hdr(dev); + break; + case ISPIOC_DISABLE_HDR: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + ret = isp_disable_hdr(dev); + break; + case ISPIOC_S_HIST: + viv_check_retval(copy_from_user + (&dev->hist, args, sizeof(dev->hist))); + ret = isp_s_hist(dev); + break; + case ISPIOC_S_HDRHIST: + viv_check_retval(copy_from_user + (&dev->hdrhist, args, sizeof(dev->hdrhist))); + ret = isp_s_hdrhist(dev); + break; +#ifdef ISP_HIST64 + case ISPIOC_S_HIST64: + viv_check_retval(copy_from_user + (&dev->hist64, args, sizeof(dev->hist64))); + ret = isp_s_hist64(dev); + break; + case ISPIOC_U_HIST64: + viv_check_retval(copy_from_user + (&dev->hist64, args, sizeof(dev->hist64))); + ret = isp_update_hist64(dev); + break; +#endif + case ISPIOC_S_DPCC: + viv_check_retval(copy_from_user + (&dev->dpcc, args, sizeof(dev->dpcc))); + ret = isp_s_dpcc(dev); + break; + case ISPIOC_ENABLE_WDR3: + ret = isp_enable_wdr3(dev); + break; + case ISPIOC_DISABLE_WDR3: + ret = isp_disable_wdr3(dev); + break; + case ISPIOC_U_WDR3: + viv_check_retval(copy_from_user + (&dev->wdr3, args, sizeof(dev->wdr3))); + ret = isp_u_wdr3(dev); + break; + case ISPIOC_S_WDR3: + viv_check_retval(copy_from_user + (&dev->wdr3, args, sizeof(dev->wdr3))); + ret = isp_s_wdr3(dev); + break; +#ifdef ISP_WDR_V4 + case ISPIOC_ENABLE_WDR4: + ret = isp_enable_wdr4(dev); + break; + case ISPIOC_DISABLE_WDR4: + ret = isp_disable_wdr4(dev); + break; + case ISPIOC_U_WDR4: + viv_check_retval(copy_from_user + (&dev->wdr4, args, sizeof(dev->wdr4))); + ret = isp_u_wdr4(dev); + break; + case ISPIOC_S_WDR4: + viv_check_retval(copy_from_user + (&dev->wdr4, args, sizeof(dev->wdr4))); + ret = isp_s_wdr4(dev); + break; +#endif + case ISPIOC_S_EXP2: + viv_check_retval(copy_from_user + (&dev->exp2, args, sizeof(dev->exp2))); + ret = isp_s_exp2(dev); + break; + case ISPIOC_S_EXP2_INPUTSEL: + viv_check_retval(copy_from_user + (&dev->exp2.input_select, args, + sizeof(dev->exp2.input_select))); + ret = isp_s_exp2_inputsel(dev); + break; + case ISPIOC_S_EXP2_SIZERATIO: { + u32 ratio; + viv_check_retval(copy_from_user(&ratio, args, sizeof(ratio))); + ret = isp_s_exp2_sizeratio(dev, ratio); + break; + } + case ISPIOC_S_2DNR: + viv_check_retval(copy_from_user + (&dev->dnr2, args, sizeof(dev->dnr2))); + #ifdef ISP_2DNR_V5 + ret = isp_tdnr_s_2dnr(dev); + #else + ret = isp_s_2dnr(dev); + #endif + break; + case ISPIOC_S_SIMP: + viv_check_retval(copy_from_user + (&dev->simp, args, sizeof(dev->simp))); + ret = isp_s_simp(dev); + break; + case ISPIOC_S_COMP: + viv_check_retval(copy_from_user + (&dev->comp, args, sizeof(dev->comp))); + ret = isp_s_comp(dev); + break; + case ISPIOC_S_CPROC: + viv_check_retval(copy_from_user + (&dev->cproc, args, sizeof(dev->cproc))); + ret = isp_s_cproc(dev); + break; + case ISPIOC_S_XTALK: + viv_check_retval(copy_from_user + (&dev->xtalk, args, sizeof(dev->xtalk))); + ret = isp_s_xtalk(dev); + break; + case ISPIOC_S_ELAWB: + viv_check_retval(copy_from_user + (&dev->elawb, args, sizeof(dev->elawb))); + ret = isp_s_elawb(dev); + break; + case ISPIOC_S_INPUT: + viv_check_retval(copy_from_user + (&dev->ctx, args, sizeof(dev->ctx))); + ret = isp_s_input(dev); + break; + case ISPIOC_S_DEMOSAIC: + viv_check_retval(copy_from_user + (&dev->ctx, args, sizeof(dev->ctx))); + ret = isp_s_demosaic(dev); + break; + case ISPIOC_MI_START: + viv_check_retval(copy_from_user + (&dev->mi, args, sizeof(dev->mi))); + ret = isp_mi_start(dev); + break; + case ISPIOC_S_HDR_WB: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + ret = isp_s_hdr_wb(dev); + break; + case ISPIOC_S_HDR_BLS: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + ret = isp_s_hdr_bls(dev); + break; + case ISPIOC_S_HDR_DIGITAL_GAIN: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + // ret = isp_s_hdr_digal_gain(dev); + break; + case ISPIOC_S_GAMMA_OUT:{ + viv_check_retval(copy_from_user + (&dev->gamma_out, args, + sizeof(dev->gamma_out))); + ret = isp_s_gamma_out(dev); + break; + } + case ISPIOC_SET_BUFFER:{ + struct isp_buffer_context buf; + viv_check_retval(copy_from_user + (&buf, args, sizeof(buf))); +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + if (dev->alloc) + ret = dev->alloc(dev, &buf); +#else + ret = isp_set_buffer(dev, &buf); +#endif + break; + } + case ISPIOC_SET_BP_BUFFER:{ + struct isp_bp_buffer_context buf; + viv_check_retval(copy_from_user + (&buf, args, sizeof(buf))); + ret = isp_set_bp_buffer(dev, &buf); + break; + } + case ISPIOC_START_CAPTURE:{ + u32 num; + viv_check_retval(copy_from_user + (&num, args, sizeof(num))); + ret = isp_start_stream(dev, num); + if(!ret) { + dev->streaming = true; + } + break; + } +#if defined(ISP_3DNR_V2) || defined(ISP_3DNR_V2_V1) + case ISPIOC_S_3DNR_CMP: { + viv_check_retval( + copy_from_user(&dev->dnr3.compress, args, sizeof(dev->dnr3.compress))); + ret = isp_s_3dnr_cmp(dev); + break; + } +#endif +#if defined(ISP_3DNR) || defined(ISP_3DNR_V2) + case ISPIOC_U_3DNR:{ + struct isp_3dnr_update param; + viv_check_retval(copy_from_user + (¶m, args, sizeof(param))); + ret = isp_u_3dnr(dev, ¶m); + break; + } + case ISPIOC_S_3DNR: + viv_check_retval(copy_from_user + (&dev->dnr3, args, sizeof(dev->dnr3))); + ret = isp_s_3dnr(dev); + break; + case ISPIOC_U_3DNR_STRENGTH: { + viv_check_retval( + copy_from_user(&dev->dnr3, args, sizeof(dev->dnr3))); + ret = isp_u_3dnr_strength(dev); + break; + } + case ISPIOC_S_3DNR_MOT:{ + viv_check_retval(copy_from_user + (&dev->dnr3, args, sizeof(dev->dnr3))); + ret = isp_s_3dnr_motion(dev); + break; + } + case ISPIOC_S_3DNR_DLT:{ + viv_check_retval(copy_from_user + (&dev->dnr3, args, sizeof(dev->dnr3))); + + ret = isp_s_3dnr_delta(dev); + break; + } + case ISPIOC_G_3DNR:{ + u32 avg; + ret = isp_g_3dnr(dev, &avg); + viv_check_retval(copy_to_user(args, &avg, sizeof(avg))); + break; + } +#endif + case ISPIOC_G_AWBMEAN:{ + struct isp_awb_mean mean; + ret = isp_g_awbmean(dev, &mean); + viv_check_retval(copy_to_user + (args, &mean, sizeof(mean))); + break; + } + case ISPIOC_G_EXPMEAN:{ + u8 mean[25]; + ret = isp_g_expmean(dev, mean); + viv_check_retval(copy_to_user + (args, mean, sizeof(mean))); + break; + } + case ISPIOC_G_HDREXPMEAN:{ + u8 mean[75]; + ret = isp_g_hdrexpmean(dev, mean); + viv_check_retval(copy_to_user + (args, mean, sizeof(mean))); + break; + } + case ISPIOC_G_HISTMEAN:{ + u32 mean[HIST_BIN_TOTAL]; + ret = isp_g_histmean(dev, mean); + viv_check_retval(copy_to_user + (args, mean, sizeof(mean))); + break; + } + case ISPIOC_G_HDRHISTMEAN:{ + u32 mean[48]; + ret = isp_g_hdrhistmean(dev, mean); + viv_check_retval(copy_to_user + (args, mean, sizeof(mean))); + break; + } +#ifdef ISP_HIST64 + case ISPIOC_G_HIST64MEAN:{ + u32 mean[HIST64_BIN_TOTAL]; + ret = isp_g_hist64mean(dev, mean); + viv_check_retval(copy_to_user + (args, mean, sizeof(mean))); + break; + } + case ISPIOC_G_HIST64VSTART_STATUS:{ + u32 status = 0; + ret = isp_g_hist64_vstart_status(dev, &status); + viv_check_retval(copy_to_user + (args, &status, sizeof(status))); + break; + } +#endif + case ISPIOC_G_VSM:{ + struct isp_vsm_result vsm; + ret = isp_g_vsm(dev, &vsm); + viv_check_retval(copy_to_user(args, &vsm, sizeof(vsm))); + break; + } + case ISPIOC_G_AFM:{ + struct isp_afm_result afm; + ret = isp_g_afm(dev, &afm); + viv_check_retval(copy_to_user(args, &afm, sizeof(afm))); + break; + } + case ISPIOC_G_STATUS: + ret = isp_ioc_g_status(dev, args); + break; + case ISPIOC_G_FEATURE: + ret = isp_ioc_g_feature(dev, args); + break; + case ISPIOC_G_FEATURE_VERSION: + ret = isp_ioc_g_feature_veresion(dev, args); + break; + case ISPIOC_WDR_CONFIG: + viv_check_retval(copy_from_user + (&dev->wdr, args, sizeof(dev->wdr))); + ret = isp_s_wdr(dev); + break; + case ISPIOC_S_WDR_CURVE: + viv_check_retval(copy_from_user + (&dev->wdr, args, sizeof(dev->wdr))); + ret = isp_s_wdr_curve(dev); + break; + case ISPIOC_ENABLE_GCMONO: + viv_check_retval(copy_from_user + (&dev->gcmono.mode, args, sizeof(u32))); + ret = isp_enable_gcmono(dev); + break; + case ISPIOC_DISABLE_GCMONO: + ret = isp_disable_gcmono(dev); + break; + case ISPIOC_S_GCMONO:{ + struct isp_gcmono_data *data; +#ifdef __KERNEL__ + data = (struct isp_gcmono_data *) + kmalloc(sizeof(struct isp_gcmono_data), GFP_KERNEL); +#else + data = (struct isp_gcmono_data *) + malloc(sizeof(struct isp_gcmono_data)); +#endif + if (data == NULL) { + isp_err("%s, malloc mem for rgb gamma failed.", __func__); + ret = -1; + } else { + viv_check_retval(copy_from_user + (data, args, + sizeof(struct + isp_gcmono_data))); + ret = isp_s_gcmono(dev, data); +#ifdef __KERNEL__ + kfree(data); +#else + free(data); +#endif + + } + break; + } + case ISPIOC_ENABLE_RGBGAMMA: + ret = isp_enable_rgbgamma(dev); + break; + case ISPIOC_DISABLE_RGBGAMMA: + ret = isp_disable_rgbgamma(dev); + break; + case ISPIOC_S_RGBGAMMA:{ + struct isp_rgbgamma_data *data; +#ifdef __KERNEL__ + data = (struct isp_rgbgamma_data *) + kmalloc(sizeof(struct isp_rgbgamma_data), + GFP_KERNEL); +#else + data = (struct isp_rgbgamma_data *) + malloc(sizeof(struct isp_rgbgamma_data)); +#endif + if (data == NULL) { + isp_err("%s, malloc mem for rgb gamma failed.", __func__); + ret = -1; + } else { + viv_check_retval(copy_from_user + (data, args, + sizeof(struct + isp_rgbgamma_data))); + ret = isp_s_rgbgamma(dev, data); +#ifdef __KERNEL__ + kfree(data); +#else + free(data); +#endif + } + break; + } + case ISPIOC_S_GREENEQUILIBRATE: + viv_check_retval(copy_from_user + (&dev->ge, args, sizeof(dev->ge))); + ret = isp_s_ge(dev); + break; + case ISPIOC_S_COLOR_ADJUST: + viv_check_retval(copy_from_user + (&dev->ca, args, sizeof(dev->ca))); + ret = isp_s_ca(dev); + break; +#ifdef __KERNEL__ + case VIDIOC_QUERYCAP: + ret = isp_ioc_qcap(dev, args); + break; +#endif + case ISPIOC_G_QUERY_EXTMEM: + ret = isp_get_extmem(dev, args); + break; + case ISPIOC_ENABLE_RGBIR: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_enable_rgbir(dev); + break; + case ISPIOC_S_RGBIR: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_s_rgbir(dev); + break; + case ISPIOC_RGBIR_HW_INIT: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_hw_init(dev); + break; + case ISPIOC_RGBIR_S_IR_DNR: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_ir_dnr(dev); + break; + case ISPIOC_RGBIR_S_SHARPEN: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_sharpen(dev); + break; + case ISPIOC_RGBIR_S_DES: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_des(dev); + break; + case ISPIOC_RGBIR_S_CC_MATRIX: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_cc_matrix(dev); + break; + case ISPIOC_RGBIR_S_DPCC: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_dpcc(dev); + break; + case ISPIOC_RGBIR_S_GAIN: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_gain(dev); + break; + case ISPIOC_RGBIR_S_BLS: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_bls(dev); + break; + case ISPIOC_RGBIR_S_IR_RAW_OUT: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_out_ir_raw(dev); + break; + case ISPIOC_S_CROP: + viv_check_retval(copy_from_user + (&dev->crop, args, sizeof(struct isp_crop_context) * 3)); + ret = isp_set_crop(dev); + break; +#ifdef ISP_3DNR_V3 + case ISPIOC_S_TDNR: + viv_check_retval(copy_from_user + (&dev->tdnr, args, sizeof(dev->tdnr))); + ret = isp_s_tdnr(dev); + break; + case ISPIOC_TDNR_ENABLE: + ret = isp_tdnr_enable(dev); + break; + case ISPIOC_TDNR_DISABLE: + ret = isp_tdnr_disable(dev); + break; + case ISPIOC_TDNR_ENABLE_TDNR: + ret = isp_tdnr_enable_tdnr(dev); + break; + case ISPIOC_TDNR_DISABLE_TDNR: + ret = isp_tdnr_disable_tdnr(dev); + break; + case ISPIOC_TDNR_ENABLE_2DNR: + ret = isp_tdnr_enable_2dnr(dev); + break; + case ISPIOC_TDNR_DISABLE_2DNR: + ret = isp_tdnr_disable_2dnr(dev); + break; + case ISPIOC_S_TDNR_CURVE: + viv_check_retval(copy_from_user + (&dev->tdnr.curve, args, sizeof(dev->tdnr.curve))); + ret = isp_tdnr_cfg_gamma(dev); + break; + case ISPIOC_G_TDNR: { + struct isp_tdnr_stats stats; + ret = isp_tdnr_g_stats(dev, &stats); + viv_check_retval(copy_to_user(args, &stats, sizeof(stats))); + } + break; + case ISPIOC_S_TDNR_STRENGTH: + viv_check_retval(copy_from_user + (&dev->tdnr, args, sizeof(dev->tdnr))); + ret = isp_tdnr_set_strength(dev); + break; + case ISPIOC_U_TDNR_NOISE: + viv_check_retval(copy_from_user + (&dev->tdnr, args, sizeof(dev->tdnr))); + ret = isp_tdnr_u_noise(dev); + break; + case ISPIOC_U_TDNR_THR: + viv_check_retval(copy_from_user + (&dev->tdnr, args, sizeof(dev->tdnr))); + ret = isp_tdnr_u_thr(dev); + break; + case ISPIOC_R_TDNR_REFER: + ret = isp_r_tdnr_refer(dev); + break; + case ISPIOC_R_TDNR_MOTION: + ret = isp_r_tdnr_motion(dev); + break; + case ISPIOC_S_TDNR_BUF: + viv_check_retval(copy_from_user + (&dev->tdnr.buf, args, sizeof(dev->tdnr.buf))); + ret = isp_tdnr_s_buf(dev); + break; +#endif + + +#ifdef ISP_MI_PP_WRITE + case ISPIOC_GET_PPW_LINE_CNT: + { + u16 ppw_pic_cnt; + ret = isp_get_ppw_pic_cnt(dev, &ppw_pic_cnt); + viv_check_retval(copy_to_user + (args, &ppw_pic_cnt, sizeof(ppw_pic_cnt))); + + break; + } + case ISPIOC_SET_PPW_LINE_NUM: + { + viv_check_retval(copy_from_user + (&dev->pp_write, args, sizeof(dev->pp_write))); + ret = isp_set_ppw_line_num(dev); + break; + } +#endif + +#ifdef ISP_MI_PP_READ + case ISPIOC_CFG_DMA_LINE_ENTRY: + viv_check_retval(copy_from_user + (&dev->pp_dma_line_entry, args, sizeof(dev->pp_dma_line_entry))); + ret = isp_cfg_pp_dma_line_entry(dev); + break; +#endif + case ISPIOC_GET_FRAME_MASK_INFO_ADDR: { + unsigned long addr; + addr = dev->frame_mark_info_addr; + pr_info("ISPIOC_GET_FRAME_MASK_INFO_ADDR %lx\n", addr); + viv_check_retval(copy_to_user(args, &addr, sizeof(addr))); + ret = 0; + } + break; + + default: + isp_err("unsupported command %d", cmd); + break; + } + if (cmd != ISPIOC_WRITE_REG) //frame end isp update shd registers. + ISP_GEN_CFG_UPDATE(dev); + return ret; +} + diff --git a/vvcam/isp/isp_ioctl.h b/vvcam/isp/isp_ioctl.h new file mode 100755 index 0000000..a946f2b --- /dev/null +++ b/vvcam/isp/isp_ioctl.h @@ -0,0 +1,436 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_IOC_H_ +#define _ISP_IOC_H_ +#include "ic_dev.h" +#include +enum { + ISPIOC_RESET = 0x100, + ISPIOC_WRITE_REG = 0x101, + ISPIOC_READ_REG = 0x102, + ISPIOC_S_INPUT = 0x103, + ISPIOC_ENABLE = 0x104, + ISPIOC_DISABLE = 0x105, + ISPIOC_ISP_STATUS = 0x106, + ISPIOC_ISP_STOP = 0x107, + ISPIOC_START_CAPTURE = 0x108, + ISPIOC_DISABLE_ISP_OFF = 0x109, + ISPIOC_SET_BUFFER = 0x10A, + ISPIOC_SET_BP_BUFFER = 0x10B, + ISPIOC_START_DMA_READ = 0x10C, + ISPIOC_MI_START = 0x10D, + ISPIOC_MI_STOP = 0x10E, + ISPIOC_ENABLE_TPG = 0x10F, + ISPIOC_DISABLE_TPG = 0x110, + ISPIOC_S_TPG = 0x111, + ISPIOC_S_MCM_WR = 0x112, + ISPIOC_ENABLE_BLS = 0x113, + ISPIOC_DISABLE_BLS = 0x114, + ISPIOC_S_BLS = 0x115, + ISPIOC_S_MUX = 0x116, + ISPIOC_ENABLE_AWB = 0x117, + ISPIOC_DISABLE_AWB = 0x118, + ISPIOC_S_AWB = 0x119, + ISPIOC_G_AWBMEAN = 0x11A, + ISPIOC_S_IS = 0x11B, + ISPIOC_S_RAW_IS = 0x11C, + ISPIOC_S_CNR = 0x11D, + ISPIOC_S_CC = 0x11E, + ISPIOC_S_XTALK = 0x11F, + ISPIOC_S_GAMMA_OUT = 0x120, + ISPIOC_ENABLE_LSC = 0x121, + ISPIOC_DISABLE_LSC = 0x122, + ISPIOC_S_LSC_TBL = 0x123, + ISPIOC_S_LSC_SEC = 0x124, + ISPIOC_S_DPF = 0x125, + ISPIOC_S_EE = 0x126, + ISPIOC_S_EXP = 0x127, + ISPIOC_S_HDREXP = 0x128, + ISPIOC_G_EXPMEAN = 0x129, + ISPIOC_G_HDREXPMEAN = 0x12A, + ISPIOC_S_HIST = 0x12B, + ISPIOC_G_HISTMEAN = 0x12C, + ISPIOC_S_HDRHIST = 0x12D, + ISPIOC_G_HDRHISTMEAN = 0x12E, + ISPIOC_S_HIST64 = 0x12F, + ISPIOC_G_HIST64MEAN = 0x130, + ISPIOC_G_HIST64VSTART_STATUS= 0x131, + ISPIOC_U_HIST64 = 0x132, + ISPIOC_S_DPCC = 0x133, + ISPIOC_S_FLT = 0x134, + ISPIOC_S_CAC = 0x135, + ISPIOC_S_DEG = 0x136, + ISPIOC_S_AFM = 0x137, + ISPIOC_G_AFM = 0x138, + ISPIOC_S_VSM = 0x139, + ISPIOC_G_VSM = 0x13A, + ISPIOC_S_IE = 0x13B, + ISPIOC_ENABLE_WDR3 = 0x13C, + ISPIOC_DISABLE_WDR3 = 0x13D, + ISPIOC_U_WDR3 = 0x13E, + ISPIOC_S_WDR3 = 0x13F, + ISPIOC_S_EXP2 = 0x140, + ISPIOC_S_EXP2_INPUTSEL = 0x141, + ISPIOC_S_EXP2_SIZERATIO = 0x142, + ISPIOC_S_2DNR = 0x143, + ISPIOC_S_3DNR = 0x144, + ISPIOC_G_3DNR = 0x145, /* get last avg */ + ISPIOC_U_3DNR = 0x146, /* update */ + ISPIOC_R_3DNR = 0x147, /* read back 3dnr reference image. */ + ISPIOC_S_3DNR_CMP = 0x148, /*config 3dnr compress */ + ISPIOC_U_3DNR_STRENGTH = 0x149, + ISPIOC_S_3DNR_MOT = 0x14A, /*config 3dnr motion*/ + ISPIOC_S_3DNR_DLT = 0x14B,/*config 3dnr delta*/ + ISPIOC_S_HDR = 0x14C, + ISPIOC_S_COMP = 0x14D, + ISPIOC_S_CPROC = 0x14E, + ISPIOC_S_SIMP = 0x14F, + ISPIOC_S_ELAWB = 0x150, + ISPIOC_S_HDR_WB = 0x151, + ISPIOC_S_HDR_BLS = 0x152, + ISPIOC_S_HDR_DIGITAL_GAIN = 0x153, + ISPIOC_ENABLE_WB = 0x154, + ISPIOC_DISABLE_WB = 0x155, + ISPIOC_DISABLE_HDR = 0x156, + ISPIOC_ENABLE_HDR = 0x157, + ISPIOC_ENABLE_GAMMA_OUT = 0x158, + ISPIOC_DISABLE_GAMMA_OUT = 0x159, + ISPIOC_G_STATUS = 0x15A, + ISPIOC_G_FEATURE = 0x15B, + ISPIOC_G_FEATURE_VERSION = 0x15C, + ISPIOC_ENABLE_GCMONO = 0x15D, + ISPIOC_DISABLE_GCMONO = 0x15E, + ISPIOC_S_GCMONO = 0x15F, + ISPIOC_ENABLE_RGBGAMMA = 0x160, + ISPIOC_DISABLE_RGBGAMMA = 0x161, + ISPIOC_S_RGBGAMMA = 0x162, + ISPIOC_S_DEMOSAIC = 0x163, + ISPIOC_S_DMSC_INTP = 0x164, + ISPIOC_S_DMSC_DMOI = 0x165, + ISPIOC_S_DMSC_SKIN = 0x166, + ISPIOC_S_DMSC_CAC = 0x167, + ISPIOC_S_DMSC_SHAP = 0x168, + ISPIOC_S_DMSC_SHAP_LINE = 0x169, + ISPIOC_S_DMSC_DEPURPLE = 0x16A, + ISPIOC_S_DMSC_GFILTER = 0x16B, + ISPIOC_S_DMSC = 0x16C, + ISPIOC_S_GREENEQUILIBRATE = 0x16D, + ISPIOC_S_COLOR_ADJUST = 0x16E, + ISPIOC_S_DIGITAL_GAIN = 0x16F, + ISPIOC_G_QUERY_EXTMEM = 0x170, +#ifdef ISP_WDR_V4 + ISPIOC_ENABLE_WDR4 = 0x171, + ISPIOC_DISABLE_WDR4 = 0x172, + ISPIOC_U_WDR4 = 0x173, + ISPIOC_S_WDR4 = 0x174, +#endif + ISPIOC_WDR_CONFIG = 0x175, + ISPIOC_S_WDR_CURVE = 0x176, + ISPIOC_ENABLE_RGBIR = 0x177, + ISPIOC_S_RGBIR = 0x178, + ISPIOC_RGBIR_HW_INIT = 0x179, + ISPIOC_RGBIR_S_IR_DNR = 0x17A, + ISPIOC_RGBIR_S_SHARPEN = 0x17B, + ISPIOC_RGBIR_S_DES = 0x17C, + ISPIOC_RGBIR_S_CC_MATRIX = 0x17D, + ISPIOC_RGBIR_S_DPCC = 0x17E, + ISPIOC_RGBIR_S_GAIN = 0x17F, + ISPIOC_RGBIR_S_BLS = 0x180, + ISPIOC_RGBIR_S_IR_RAW_OUT = 0x181, + ISPIOC_S_TDNR = 0x182, + ISPIOC_TDNR_ENABLE = 0x183, + ISPIOC_TDNR_DISABLE = 0x184, + ISPIOC_TDNR_ENABLE_TDNR = 0x185, + ISPIOC_TDNR_DISABLE_TDNR = 0x186, + ISPIOC_TDNR_ENABLE_2DNR = 0x187, + ISPIOC_TDNR_DISABLE_2DNR = 0x188, + ISPIOC_S_TDNR_CURVE = 0x189, + ISPIOC_G_TDNR = 0x18A, + ISPIOC_S_TDNR_STRENGTH = 0x18B, + ISPIOC_U_TDNR_NOISE = 0x18C, + ISPIOC_U_TDNR_THR = 0x18D, + ISPIOC_S_TDNR_BUF = 0x18E, // refer and motion + ISPIOC_R_TDNR_REFER = 0x18F, + ISPIOC_R_TDNR_MOTION = 0x190, + ISPIOC_GET_MIS = 0x191, + ISPIOC_CFG_DMA = 0x192, + ISPIOC_BYPASS_MCM = 0x193, + ISPIOC_SET_PPW_LINE_NUM = 0x194, + ISPIOC_GET_PPW_LINE_CNT = 0x195, + ISPIOC_CFG_DMA_LINE_ENTRY = 0x196, + ISPIOC_S_CROP = 0x197, + ISPIOC_GET_FRAME_MASK_INFO_ADDR = 0x198, +}; + +#define ISP_GEN_CFG_UPDATE(dev) { \ + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); \ + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); \ + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); \ + } + +#define CONFIG_VSI_ISP_DEBUG 1 +#ifdef CONFIG_VSI_ISP_DEBUG +#define isp_info(fmt, ...) pr_info(fmt, ##__VA_ARGS__) +#define isp_debug(fmt, ...) pr_debug(fmt, ##__VA_ARGS__) +#define isp_err(fmt, ...) pr_err(fmt, ##__VA_ARGS__) +#else +#define isp_info(fmt, ...) +#define isp_debug(fmt, ...) +#define isp_err(fmt, ...) pr_err(fmt, ##__VA_ARGS__) +#endif + +#define ISP_REG_GAP 4 +#define MI_QOS 0x44440444 +#define MI_QOS2 0x44 +long isp_priv_ioctl(struct isp_ic_dev *dev, unsigned int cmd, void __user *args); +long isp_copy_data(void *dst, void *src, int size); + +/* internal functions, can called by v4l2 video device and ioctl */ +int isp_reset(struct isp_ic_dev *dev); +int isp_enable_tpg(struct isp_ic_dev *dev); +int isp_disable_tpg(struct isp_ic_dev *dev); +int isp_enable_bls(struct isp_ic_dev *dev); +int isp_disable_bls(struct isp_ic_dev *dev); +int isp_enable(struct isp_ic_dev *dev); +int isp_disable(struct isp_ic_dev *dev); +bool is_isp_enable(struct isp_ic_dev *dev); +int isp_enable_lsc(struct isp_ic_dev *dev); +int isp_disable_lsc(struct isp_ic_dev *dev); +int isp_s_input(struct isp_ic_dev *dev); +int isp_s_digital_gain(struct isp_ic_dev *dev); +int isp_s_demosaic(struct isp_ic_dev *dev); +int isp_s_tpg(struct isp_ic_dev *dev); +int isp_s_mcm_wr(struct isp_ic_dev *dev); +int isp_bypass_mcm(struct isp_ic_dev *dev); +int isp_s_mux(struct isp_ic_dev *dev); +int isp_s_bls(struct isp_ic_dev *dev); +int isp_enable_awb(struct isp_ic_dev *dev); +int isp_disable_awb(struct isp_ic_dev *dev); +int isp_s_awb(struct isp_ic_dev *dev); +int isp_g_awbmean(struct isp_ic_dev *dev, struct isp_awb_mean *mean); +int isp_s_is(struct isp_ic_dev *dev); +int isp_s_raw_is(struct isp_ic_dev *dev); +int isp_s_cnr(struct isp_ic_dev *dev); +int isp_start_stream(struct isp_ic_dev *dev, u32 framenum); +int isp_stop_stream(struct isp_ic_dev *dev); +int isp_s_cc(struct isp_ic_dev *dev); +int isp_s_xtalk(struct isp_ic_dev *dev); +int isp_enable_wb(struct isp_ic_dev *dev, bool bEnable); +int isp_enable_gamma_out(struct isp_ic_dev *dev, bool bEnable); +int isp_s_gamma_out(struct isp_ic_dev *dev); +int isp_s_lsc_sec(struct isp_ic_dev *dev); +int isp_s_lsc_tbl(struct isp_ic_dev *dev); +int isp_ioc_disable_isp_off(struct isp_ic_dev *dev, void __user *args); +int isp_s_dpf(struct isp_ic_dev *dev); +int isp_s_ee(struct isp_ic_dev *dev); +int isp_s_exp(struct isp_ic_dev *dev); +int isp_s_hdrexp(struct isp_ic_dev *dev); +int isp_g_expmean(struct isp_ic_dev *dev, u8 * mean); +int isp_g_hdrexpmean(struct isp_ic_dev *dev, u8 * mean); +int isp_s_hist(struct isp_ic_dev *dev); +int isp_g_histmean(struct isp_ic_dev *dev, u32 * mean); +int isp_s_hdrhist(struct isp_ic_dev *dev); +int isp_g_hdrhistmean(struct isp_ic_dev *dev, u32 * mean); +#ifdef ISP_HIST64 +int isp_s_hist64(struct isp_ic_dev *dev); +int isp_g_hist64mean(struct isp_ic_dev *dev, u32 *mean); +int isp_g_hist64_vstart(struct isp_ic_dev *dev, u32 start_line); +int isp_g_hist64_vstart_status(struct isp_ic_dev *dev, u32 *status); +int isp_update_hist64(struct isp_ic_dev *dev); +#endif +int isp_s_dpcc(struct isp_ic_dev *dev); +int isp_s_flt(struct isp_ic_dev *dev); +int isp_s_cac(struct isp_ic_dev *dev); +int isp_s_deg(struct isp_ic_dev *dev); +int isp_s_ie(struct isp_ic_dev *dev); +int isp_s_vsm(struct isp_ic_dev *dev); +int isp_g_vsm(struct isp_ic_dev *dev, struct isp_vsm_result *vsm); +int isp_s_afm(struct isp_ic_dev *dev); +int isp_g_afm(struct isp_ic_dev *dev, struct isp_afm_result *afm); +int isp_enable_wdr3(struct isp_ic_dev *dev); +int isp_disable_wdr3(struct isp_ic_dev *dev); +int isp_u_wdr3(struct isp_ic_dev *dev); +int isp_s_wdr3(struct isp_ic_dev *dev); +#ifdef ISP_WDR_V4 +int isp_enable_wdr4(struct isp_ic_dev *dev); +int isp_disable_wdr4(struct isp_ic_dev *dev); +int isp_u_wdr4(struct isp_ic_dev *dev); +int isp_s_wdr4(struct isp_ic_dev *dev); +#endif +int isp_s_exp2(struct isp_ic_dev *dev); +int isp_s_exp2_inputsel(struct isp_ic_dev *dev); +int isp_s_exp2_sizeratio(struct isp_ic_dev *dev, u32 ratio); +int isp_s_hdr(struct isp_ic_dev *dev); +int isp_s_hdr_wb(struct isp_ic_dev *dev); +int isp_s_hdr_bls(struct isp_ic_dev *dev); +//int isp_s_hdr_digal_gain(struct isp_ic_dev *dev); +int isp_enable_hdr(struct isp_ic_dev *dev); +int isp_disable_hdr(struct isp_ic_dev *dev); +#ifdef ISP_2DNR_V5 +int isp_tdnr_s_2dnr(struct isp_ic_dev *dev); +#else +int isp_s_2dnr(struct isp_ic_dev *dev); +#endif +#if defined(ISP_3DNR) || defined(ISP_3DNR_V2) +int isp_s_3dnr(struct isp_ic_dev *dev); +int isp_g_3dnr(struct isp_ic_dev *dev, u32 * avg); +int isp_u_3dnr(struct isp_ic_dev *dev, struct isp_3dnr_update *dnr3_update); +int isp_s_3dnr_motion(struct isp_ic_dev *dev); +int isp_s_3dnr_delta(struct isp_ic_dev *dev); +#endif + +#if defined(ISP_3DNR) || defined(ISP_3DNR_V2_V1) +int isp_r_3dnr(struct isp_ic_dev *dev); +#endif +#ifdef ISP_3DNR_V2 +int isp_s_3dnr_cmp(struct isp_ic_dev *dev); +#endif +int isp_u_3dnr_strength(struct isp_ic_dev *dev); +int isp_s_comp(struct isp_ic_dev *dev); +int isp_s_simp(struct isp_ic_dev *dev); +int isp_s_cproc(struct isp_ic_dev *dev); +int isp_s_elawb(struct isp_ic_dev *dev); +int isp_ioc_qcap(struct isp_ic_dev *dev, void __user *args); +int isp_ioc_g_status(struct isp_ic_dev *dev, void __user *args); + +int isp_enable_gcmono(struct isp_ic_dev *dev); +int isp_disable_gcmono(struct isp_ic_dev *dev); +int isp_s_gcmono(struct isp_ic_dev *dev, struct isp_gcmono_data *data); /* set curve */ +int isp_enable_rgbgamma(struct isp_ic_dev *dev); +int isp_disable_rgbgamma(struct isp_ic_dev *dev); +int isp_s_rgbgamma(struct isp_ic_dev *dev, struct isp_rgbgamma_data *data); + +u32 isp_read_mi_irq(struct isp_ic_dev *dev); +void isp_reset_mi_irq(struct isp_ic_dev *dev, u32 icr); + +int isp_ioc_cfg_dma(struct isp_ic_dev *dev, void __user *args); +int isp_ioc_start_dma_read(struct isp_ic_dev *dev, void __user *args); +int isp_mi_start(struct isp_ic_dev *dev); +int isp_mi_stop(struct isp_ic_dev *dev); +int isp_set_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf); +int isp_set_bp_buffer(struct isp_ic_dev *dev, + struct isp_bp_buffer_context *buf); + +int isp_enable_dmsc(struct isp_ic_dev *dev); +int isp_disable_dmsc(struct isp_ic_dev *dev); +int isp_set_dmsc_intp(struct isp_ic_dev *dev); +int isp_set_dmsc_skin(struct isp_ic_dev *dev); +int isp_set_dmsc_gfilter(struct isp_ic_dev *dev); +int isp_set_dmsc_depurple(struct isp_ic_dev *dev); +int isp_set_dmsc_cac(struct isp_ic_dev *dev); +int isp_set_dmsc_sharpen(struct isp_ic_dev *dev); +int isp_set_dmsc_sharpen_line(struct isp_ic_dev *dev); +int isp_set_dmsc_dmoi(struct isp_ic_dev *dev); +int isp_s_dmsc(struct isp_ic_dev *dev); +int isp_s_ge(struct isp_ic_dev *dev); +int isp_s_ca(struct isp_ic_dev *dev); +int isp_s_color_adjust(struct isp_ic_dev *dev); +int isp_config_dummy_hblank(struct isp_ic_dev *dev); + +int isp_s_rgbir(struct isp_ic_dev *dev); +int isp_enable_rgbir(struct isp_ic_dev *dev); +int isp_rgbir_hw_init(struct isp_ic_dev *dev); +int isp_rgbir_s_ir_dnr(struct isp_ic_dev *dev); +int isp_rgbir_s_sharpen(struct isp_ic_dev *dev); +int isp_rgbir_s_des(struct isp_ic_dev *dev); +int isp_rgbir_s_cc_matrix(struct isp_ic_dev *dev); +int isp_rgbir_s_dpcc(struct isp_ic_dev *dev); +int isp_rgbir_s_gain(struct isp_ic_dev *dev); +int isp_rgbir_s_bls(struct isp_ic_dev *dev); +int isp_rgbir_out_ir_raw(struct isp_ic_dev *dev); + +#ifdef ISP_3DNR_V3 +int isp_tdnr_cfg_gamma(struct isp_ic_dev *dev); +int isp_s_tdnr(struct isp_ic_dev *dev); +int isp_tdnr_set_strength(struct isp_ic_dev *dev); +int isp_tdnr_set_motion(struct isp_ic_dev *dev); +int isp_tdnr_enable(struct isp_ic_dev *dev); +int isp_tdnr_disable(struct isp_ic_dev *dev); +int isp_tdnr_enable_tdnr(struct isp_ic_dev *dev); +int isp_tdnr_disable_tdnr(struct isp_ic_dev *dev); +int isp_tdnr_enable_2dnr(struct isp_ic_dev *dev); +int isp_tdnr_disable_2dnr(struct isp_ic_dev *dev); +int isp_tdnr_g_stats(struct isp_ic_dev *dev, struct isp_tdnr_stats *avg); +int isp_tdnr_u_noise(struct isp_ic_dev *dev); +int isp_r_tdnr_refer(struct isp_ic_dev *dev); +int isp_r_tdnr_motion(struct isp_ic_dev *dev); +int isp_tdnr_u_thr(struct isp_ic_dev *dev); +int isp_tdnr_s_buf(struct isp_ic_dev *dev); +#endif + +#ifdef ISP_MI_PP_WRITE +int isp_set_ppw_line_num(struct isp_ic_dev *dev); +int isp_get_ppw_pic_cnt(struct isp_ic_dev *dev, u16* pic_cnt); +#endif + +#ifdef ISP_MI_PP_READ +int isp_cfg_pp_dma_line_entry(struct isp_ic_dev *dev); +#endif +#ifdef __KERNEL__ +int clean_dma_buffer(struct isp_ic_dev *dev); +irqreturn_t isp_hw_isr(int irq, void *data); +void isp_clear_interrupts(struct isp_ic_dev *dev); +#endif +/*get irq mis value from store array*/ +u32 isp_read_mis(struct isp_ic_dev *dev, u32 irq_src); +int isp_ioc_read_mis(struct isp_ic_dev *dev, void __user *args); + +/*set scaler*/ +int isp_set_scaling(int id, struct isp_ic_dev *dev, bool stabilization, bool crop); +int isp_set_crop(struct isp_ic_dev *dev); + + +int isp_ioc_g_feature(struct isp_ic_dev *dev, void __user *args); +int isp_ioc_g_feature_veresion(struct isp_ic_dev *dev, void __user *args); + +#endif /* _ISP_IOC_H_ */ diff --git a/vvcam/isp/isp_irq_queue.c b/vvcam/isp/isp_irq_queue.c new file mode 100755 index 0000000..3b8b82e --- /dev/null +++ b/vvcam/isp/isp_irq_queue.c @@ -0,0 +1,239 @@ +/**************************************************************************** + + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifdef __KERNEL__ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#else +#include +#include +#include +#endif +#include "isp_irq_queue.h" + + //enqueue +int isp_irq_enqueue(isp_mis_t *new,isp_mis_t* head) + { +#ifdef __KERNEL__ + isp_mis_t* new_node = (isp_mis_t*)kmalloc(sizeof(isp_mis_t), GFP_KERNEL); //create new node + + + if (new == NULL || head == NULL) { + //printk("%s: input wrong parameter\n", __func__); + return -1; + } + new_node->val = new->val; + new_node->irq_src = new->irq_src; + /*printk("%s: new_node %px irq_src %d", __func__, new_node, new->irq_src);*/ + INIT_LIST_HEAD(&new_node->list); + list_add_tail(&new_node->list, &head->list); //append to tail + #endif + return 0; + + } + + //dequeue && release memory +int isp_irq_dequeue(isp_mis_t* data, isp_mis_t* head) + { + +#ifdef __KERNEL__ + isp_mis_t* entry; + if (data == NULL || head == NULL) { + //printk("%s: input wrong parameter\n", __func__); + return -1; + } + if (list_empty(&head->list)) { + //printk("%s: There is no node\n", __func__); + return -1; + } + + entry = list_first_entry(&head->list, isp_mis_t, list); + /*printk("%s: entry %px irq_src %d", __func__, entry, entry->irq_src);*/ + data->val = entry->val; + data->irq_src = entry->irq_src; + list_del_init(&entry->list); + + kfree(entry); +#endif + return 0; + } + +bool isp_irq_is_queue_empty( isp_mis_t* head) + { +#ifdef __KERNEL__ + return list_empty(&head->list); +#endif + return 0; + } + +int isp_irq_create_circle_queue(isp_mis_list_t* pCList, int number) +{ +#ifdef __KERNEL__ + int i; + isp_mis_t* pMisNode; + if (pCList == NULL || number <= 0) { + printk("%s: create circle queue failed\n", __func__); + return -1; + } + + if (pCList->pHead == NULL) { + + pCList->pHead = (isp_mis_t*)kmalloc(sizeof(isp_mis_t), GFP_KERNEL); + INIT_LIST_HEAD(&pCList->pHead->list); + pCList->pRead = pCList->pHead; + pCList->pWrite = pCList->pHead; + } + printk("%s:pHead %px\n", __func__, pCList->pHead); + for (i = 0; i < number - 1; i++) { + pMisNode = (isp_mis_t*)kmalloc(sizeof(isp_mis_t), GFP_KERNEL); + INIT_LIST_HEAD(&pMisNode->list); + list_add_tail(&pMisNode->list, &pCList->pHead->list); + printk("%s:pMisNode %px\n", __func__, pMisNode); + } + +#endif + return 0; +} + +int isp_irq_destroy_circle_queue(isp_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + isp_mis_t* pMisNode; + if ((pCList == NULL) || (pCList->pHead == NULL) ) { + printk("%s: destroy circle queue failed. pClist %px\n", __func__, pCList); + return -1; + } + + while(!list_empty(&pCList->pHead->list)) { + pMisNode = list_first_entry(&pCList->pHead->list, isp_mis_t, list); + printk("%s:pMisNode %px\n", __func__, pMisNode); + list_del(&pMisNode->list); + kfree(pMisNode); + pMisNode = NULL; + } + printk("%s:pHead %px\n", __func__, pCList->pHead); + kfree(pCList->pHead); + pCList->pHead = NULL; + pCList->pRead = NULL; + pCList->pWrite = NULL; +#endif + return 0; +} + +int isp_irq_read_circle_queue(isp_mis_t* data, isp_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + //isp_mis_t* pReadEntry; + if (pCList == NULL) { + printk("%s: can not read circle queue\n", __func__); + return -1; + } + + if (pCList->pRead == pCList->pWrite) { + /*printk("%s: There is no irq mis data\n", __func__);*/ + return -1; + } + data->val = pCList->pRead->val; + data->irq_src = pCList->pRead->irq_src; + /*printk("%s: entry %px irq_src %d, msi %08x\n", __func__, pCList->pRead, data->irq_src, data->val);*/ + /*Get the next entry that link with read entry list*/ + /*Update read pointer to next entry*/ + pCList->pRead = list_first_entry(&pCList->pRead->list, isp_mis_t, list); + + //pCList->pRead = pReadEntry; + +#endif + return 0; +} + +int isp_irq_write_circle_queue(isp_mis_t* data, isp_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + isp_mis_t* pWriteEntry; + if (pCList == NULL) { + printk("%s: can not read circle queue\n", __func__); + return -1; + } + + pCList->pWrite->val = data->val; + pCList->pWrite->irq_src = data->irq_src; + /*printk("%s: entry %px irq_src %d, msi %08x\n", __func__, pCList->pWrite, data->irq_src, data->val);*/ + /*get the next write entry pointer that link with the write entry list*/ + pWriteEntry = list_first_entry(&pCList->pWrite->list, isp_mis_t, list); + + /*Update write pointer to point next entry*/ + pCList->pWrite = pWriteEntry; + +#endif + return 0; +} + diff --git a/vvcam/isp/isp_irq_queue.h b/vvcam/isp/isp_irq_queue.h new file mode 100755 index 0000000..cd2a50e --- /dev/null +++ b/vvcam/isp/isp_irq_queue.h @@ -0,0 +1,98 @@ + /**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_IRQ_QUEUE_H_ +#define _ISP_IRQ_QUEUE_H_ +#ifdef __KERNEL__ +#include +#endif +//#include "isp_ioctl.h" + typedef enum isp_src_e +{ + SRC_ISP_IRQ = 0X0000, + SRC_JPE_STATUS_IRQ, + SRC_JPE_ERROR_IRQ, + SRC_MI_IRQ, + SRC_MI1_IRQ, + SRC_MI2_IRQ, + SRC_MIPI_IRQ, + SRC_IRQ_MAX, +} isp_src_t; + +typedef struct isp_mis_s { + unsigned int irq_src; + unsigned int val; +#ifdef __KERNEL__ + struct list_head list; +#endif +}isp_mis_t; + +typedef struct isp_mis_list_s { + + isp_mis_t* pHead; + isp_mis_t* pRead; + isp_mis_t* pWrite; +}isp_mis_list_t; + + +int isp_irq_enqueue(isp_mis_t *new,isp_mis_t* head); +int isp_irq_dequeue(isp_mis_t* data, isp_mis_t* head); +bool isp_irq_is_queue_empty( isp_mis_t* head); + +#define QUEUE_NODE_COUNT 15 +int isp_irq_create_circle_queue(isp_mis_list_t* pCList, int number); +int isp_irq_destroy_circle_queue(isp_mis_list_t* pCList); + +int isp_irq_read_circle_queue(isp_mis_t* data, isp_mis_list_t* pCList); +int isp_irq_write_circle_queue(isp_mis_t* data, isp_mis_list_t* pCList); + +#endif \ No newline at end of file diff --git a/vvcam/isp/isp_isr.c b/vvcam/isp/isp_isr.c new file mode 100755 index 0000000..a5f6965 --- /dev/null +++ b/vvcam/isp/isp_isr.c @@ -0,0 +1,279 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef ENABLE_IRQ + +#include "isp_ioctl.h" +#include "isp_types.h" +#include "mrv_all_bits.h" +#include "video/vvbuf.h" + +extern MrvAllRegister_t *all_regs; + +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG +static int config_dma_buf(struct isp_mi_data_path_context *path, + dma_addr_t dma, struct isp_buffer_context *buf) +{ + u32 size = path->out_width * path->out_height; + + buf->addr_y = dma; + switch (path->out_mode) { + case IC_MI_DATAMODE_YUV444: + case IC_MI_DATAMODE_YUV422: + case IC_MI_DATAMODE_YUV420: + if (path->data_layout == IC_MI_DATASTORAGE_PLANAR) { + buf->size_y = size + ISP_BUF_GAP; + buf->addr_cb = buf->addr_y + size; + buf->size_cb = size + ISP_BUF_GAP; + buf->addr_cr = buf->addr_cb + size; + buf->size_cr = size + ISP_BUF_GAP; + } else if (path->data_layout == + IC_MI_DATASTORAGE_SEMIPLANAR) { + buf->size_y = size + ISP_BUF_GAP; + buf->addr_cb = buf->addr_y + size; + if (path->out_mode == IC_MI_DATAMODE_YUV420) + buf->size_cb = (size >> 1) + ISP_BUF_GAP; + else + buf->size_cb = size + ISP_BUF_GAP; + } else if (path->data_layout == + IC_MI_DATASTORAGE_INTERLEAVED) { + buf->size_y = (size << 1) + ISP_BUF_GAP; + } else + return -1; + break; + case IC_MI_DATAMODE_RAW8: + buf->size_y = size + ISP_BUF_GAP; + break; + case IC_MI_DATAMODE_RAW10: + case IC_MI_DATAMODE_RAW12: + buf->size_y = (size << 1) + ISP_BUF_GAP; + break; + default: + pr_err("unsupported out mode:%d\n", path->out_mode); + return -1; + } +#ifdef ISP_MP_34BIT + buf->addr_y >>= 2; + buf->addr_cb >>= 2; + buf->addr_cr >>= 2; +#endif + return 0; +} +#endif + +static int update_dma_buffer(struct isp_ic_dev *dev) +{ +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + struct isp_mi_context *mi = &dev->mi; + struct vb2_dc_buf *buf = NULL; + struct isp_buffer_context dmabuf; + int i,dequeued; + + for (i = 0; i < MI_PATH_NUM; ++i) { + if (!mi->path[i].enable) + continue; + if (dev->mi_buf[i]) { + vvbuf_ready(dev->bctx, dev->mi_buf[i]->pad, + dev->mi_buf[i]); + dev->mi_buf[i] = NULL; + } + if (dev->state && !(*dev->state & STATE_DRIVER_STARTED)) + continue; + dequeued = 1; + buf = vvbuf_try_dqbuf(dev->bctx); + if (!buf) { + buf = dev->mi_buf_shd[i]; + if (!buf) + return -ENOMEM; + dev->mi_buf_shd[i] = NULL; + dequeued = 0; + } else if (dev->mi_buf_shd[i]) { + dev->mi_buf[i] = dev->mi_buf_shd[i]; + dev->mi_buf_shd[i] = NULL; + } + + memset(&dmabuf, 0, sizeof(dmabuf)); + dmabuf.path = i; + if (config_dma_buf(&mi->path[i], buf->dma, &dmabuf)) + continue; + isp_set_buffer(dev, &dmabuf); + dev->mi_buf_shd[i] = buf; + if (dequeued) + vvbuf_try_dqbuf_done(dev->bctx, buf); + } +#endif + return 0; +} + +int clean_dma_buffer(struct isp_ic_dev *dev) +{ +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + int i; + + if (!dev->free) + return 0; + + dev->free(dev, NULL); + + for (i = 0; i < MI_PATH_NUM; ++i) { + if (dev->mi_buf[i]) { + dev->free(dev, dev->mi_buf[i]); + dev->mi_buf[i] = NULL; + } + if (dev->mi_buf_shd[i]) { + dev->free(dev, dev->mi_buf_shd[i]); + dev->mi_buf_shd[i] = NULL; + } + } +#endif + return 0; +} + +void isp_clear_interrupts(struct isp_ic_dev *dev) +{ + u32 isp_mis, mi_mis; + + isp_mis = isp_read_reg(dev, REG_ADDR(isp_mis)); + isp_write_reg(dev, REG_ADDR(isp_icr), isp_mis); + +#ifdef ISP_MIV1 + mi_mis = isp_read_reg(dev, REG_ADDR(mi_mis)); + isp_write_reg(dev, REG_ADDR(mi_icr), mi_mis); +#elif defined(ISP_MIV2) + mi_mis = isp_read_reg(dev, REG_ADDR(miv2_mis)); + isp_write_reg(dev, REG_ADDR(miv2_icr), mi_mis); +#else + mi_mis = 0; +#endif +} + +irqreturn_t isp_hw_isr(int irq, void *data) +{ + struct isp_ic_dev *dev = (struct isp_ic_dev *)data; + static const u32 frameendmask = MRV_MI_MP_FRAME_END_MASK | +#ifdef ISP_MI_BP + MRV_MI_BP_FRAME_END_MASK | +#endif + MRV_MI_SP_FRAME_END_MASK; + static const u32 errormask = MRV_MI_WRAP_MP_Y_MASK | + MRV_MI_WRAP_MP_CB_MASK | + MRV_MI_WRAP_MP_CR_MASK | +#ifdef ISP_MI_BP + MRV_MI_BP_WRAP_R_MASK | + MRV_MI_BP_WRAP_GR_MASK | + MRV_MI_BP_WRAP_GB_MASK | + MRV_MI_BP_WRAP_B_MASK | +#endif + MRV_MI_WRAP_SP_Y_MASK | + MRV_MI_WRAP_SP_CB_MASK | + MRV_MI_WRAP_SP_CR_MASK | + MRV_MI_FILL_MP_Y_MASK; + static const u32 fifofullmask = MRV_MI_MP_Y_FIFO_FULL_MASK | + MRV_MI_MP_CB_FIFO_FULL_MASK | + MRV_MI_MP_CR_FIFO_FULL_MASK | + MRV_MI_SP_Y_FIFO_FULL_MASK | + MRV_MI_SP_CB_FIFO_FULL_MASK | + MRV_MI_SP_CR_FIFO_FULL_MASK; + u32 isp_mis, mi_mis, mi_status; + struct isp_irq_data irq_data; + int rc = 0; + + if (!dev) + return IRQ_HANDLED; + + isp_mis = isp_read_reg(dev, REG_ADDR(isp_mis)); + isp_write_reg(dev, REG_ADDR(isp_icr), isp_mis); + +#ifdef ISP_MIV1 + mi_mis = isp_read_reg(dev, REG_ADDR(mi_mis)); + isp_write_reg(dev, REG_ADDR(mi_icr), mi_mis); +#elif defined(ISP_MIV2) + mi_mis = isp_read_reg(dev, REG_ADDR(miv2_mis)); + isp_write_reg(dev, REG_ADDR(miv2_icr), mi_mis); +#else + mi_mis = 0; +#endif + + mi_status = isp_read_reg(dev, REG_ADDR(mi_status)); + if (mi_status & fifofullmask) { + isp_write_reg(dev, REG_ADDR(mi_status), mi_status); + pr_debug("MI FIFO full: 0x%x\n", mi_status); + } + + if (mi_mis & errormask) + pr_debug("MI mis error: 0x%x\n", mi_mis); + + if (mi_mis & frameendmask) + rc = update_dma_buffer(dev); + + if (isp_mis) { + if(isp_mis & MRV_ISP_MIS_FRAME_MASK) { + if (dev->isp_update_flag & ISP_FLT_UPDATE) { + isp_s_flt(dev); + dev->isp_update_flag &= (~ISP_FLT_UPDATE); + } + + if (dev->gamma_out.changed) { + isp_s_gamma_out(dev); + } + + } + + memset(&irq_data, 0, sizeof(irq_data)); + irq_data.val = isp_mis; + if (dev->post_event) + dev->post_event(dev, &irq_data, sizeof(irq_data)); + } + return IRQ_HANDLED; +} + +#endif diff --git a/vvcam/isp/isp_miv1.c b/vvcam/isp/isp_miv1.c new file mode 100755 index 0000000..2a1d317 --- /dev/null +++ b/vvcam/isp/isp_miv1.c @@ -0,0 +1,626 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +#ifdef ISP_MIV1 + +extern MrvAllRegister_t *all_regs; + +static int getRawBit(u32 type, u32 *bit, u32 *len) +{ + *len = 16; + switch (type) { + case ISP_PICBUF_TYPE_RAW8: + *bit = 0; + *len = 8; + break; +#if 0 /* normal process, need pass type from engine. */ + case ISP_PICBUF_TYPE_RAW10: + *bit = 1; + break; + case ISP_PICBUF_TYPE_RAW12: + *bit = 2; + break; + case ISP_PICBUF_TYPE_RAW14: + *bit = 3; + break; + case ISP_PICBUF_TYPE_RAW16: + *bit = 4; + break; +#else /* WA */ + case ISP_PICBUF_TYPE_RAW10: + case ISP_PICBUF_TYPE_RAW12: + case ISP_PICBUF_TYPE_RAW14: + case ISP_PICBUF_TYPE_RAW16: + *bit = 4; + break; +#endif + default: + pr_err("unsupport raw formt: %d\n", type); + return -1; + } + return 0; +} +int isp_ioc_cfg_dma(struct isp_ic_dev *dev, void __user *args) +{ + return 0; +} +int isp_ioc_start_dma_read(struct isp_ic_dev *dev, void __user *args) +{ + struct isp_dma_context dma; + u32 mi_dma_ctrl = isp_read_reg(dev, REG_ADDR(mi_dma_ctrl)); + u32 llength = 0, mcm_rd_fmt_bit = 0; + u32 mi_imsc = 0, mcm_fmt = 0; + + pr_info("enter %s\n", __func__); + viv_check_retval(copy_from_user(&dma, args, sizeof(dma))); + + REG_SET_SLICE(mi_dma_ctrl, MRV_MI_DMA_BURST_LEN_LUM, dma.burst_y); + REG_SET_SLICE(mi_dma_ctrl, MRV_MI_DMA_BURST_LEN_CHROM, dma.burst_c); + + isp_write_reg(dev, REG_ADDR(mi_dma_y_pic_start_ad), + (MRV_MI_DMA_Y_PIC_START_AD_MASK & dma.base)); + getRawBit(dma.type, &mcm_rd_fmt_bit, &llength); + + llength = dma.width * llength / 8; + REG_SET_SLICE(mcm_fmt, MCM_RD_RAW_BIT, mcm_rd_fmt_bit); + isp_write_reg(dev, REG_ADDR(mi_dma_y_pic_width), + (MRV_MI_DMA_Y_PIC_WIDTH_MASK & dma.width)); + isp_write_reg(dev, REG_ADDR(mi_dma_y_llength), + (MRV_MI_DMA_Y_LLENGTH_MASK & llength)); + isp_write_reg(dev, REG_ADDR(mi_dma_y_pic_size), + (MRV_MI_DMA_Y_PIC_SIZE_MASK & (llength * dma.height))); + isp_write_reg(dev, REG_ADDR(mi_dma_cb_pic_start_ad), 0); + isp_write_reg(dev, REG_ADDR(mi_dma_cr_pic_start_ad), 0); + isp_write_reg(dev, REG_ADDR(mi_dma_ctrl), mi_dma_ctrl); + + isp_write_reg(dev, REG_ADDR(mi_dma_status), 0); + isp_write_reg(dev, REG_ADDR(mi_dma_y_raw_fmt), mcm_fmt); + isp_write_reg(dev, REG_ADDR(mi_dma_y_raw_lval), + (MRV_MI_DMA_Y_LLENGTH_MASK & llength)); + + mi_imsc = isp_read_reg(dev, REG_ADDR(mi_imsc)); + mi_imsc |= MRV_MI_DMA_READY_MASK; + + isp_write_reg(dev, REG_ADDR(mi_imsc), mi_imsc); + isp_write_reg(dev, REG_ADDR(mi_dma_start), MRV_MI_DMA_START_MASK); + return 0; +} + +u32 getScaleFactor(u32 src, u32 dst) +{ + if (dst > src) { + return ((65536 * (src - 1)) / (dst - 1)); + } else if (dst < src) { + return ((65536 * (dst - 1)) / (src - 1)) + 1; + } + return 65536; +} + +int set_scaling(int id, struct isp_ic_dev *dev, bool stabilization) +{ + u32 addr, ctrl; + u32 iw, ih, ow, oh; + u32 inputWidth, inputHeight, outputWidth, outputHeight; + u32 scale_hy, scale_hcb, scale_hcr, scale_vy, scale_vc; + struct isp_mi_data_path_context *path = &dev->mi.path[id]; + + if (id == IC_MI_PATH_MAIN) { /* mp */ + addr = REG_ADDR(mrsz_ctrl); + } else if (id == IC_MI_PATH_SELF) { /* sp */ + addr = REG_ADDR(srsz_ctrl); + } else { + return -EINVAL; + } + + inputWidth = path->in_width; + inputHeight = path->in_height; + outputWidth = path->out_width; + outputHeight = path->out_height; + + if (stabilization) { /* enabled image stabilization. */ + inputWidth = isp_read_reg(dev, REG_ADDR(isp_is_h_size)); + inputHeight = isp_read_reg(dev, REG_ADDR(isp_is_v_size)); + } + + ctrl = isp_read_reg(dev, addr); + iw = inputWidth / 2; + ih = inputHeight; + ow = outputWidth / 2; + oh = outputHeight; + + switch (path->in_mode) { + case IC_MI_DATAMODE_YUV422: + oh = outputHeight; + break; + case IC_MI_DATAMODE_YUV420: + oh = outputHeight / 2; /* scale cbcr */ + break; + default: + return -EFAULT; + } + + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_ENABLE, + inputWidth != outputWidth); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_ENABLE, + inputHeight != outputHeight); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_UP, inputWidth < outputWidth); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_UP, inputHeight < outputHeight); + scale_hy = getScaleFactor(inputWidth, outputWidth); + scale_vy = getScaleFactor(inputHeight, outputHeight); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_ENABLE, iw != ow); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_ENABLE, ih != oh); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_UP, iw < ow); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_UP, ih < oh); + scale_hcr = getScaleFactor(iw, ow); + scale_hcb = getScaleFactor(iw, ow); + scale_vc = getScaleFactor(ih, oh); + + REG_SET_SLICE(ctrl, MRV_MRSZ_AUTO_UPD, 1); + + if (id == IC_MI_PATH_MAIN) { + isp_write_reg(dev, REG_ADDR(mrsz_scale_vc), scale_vc); + isp_write_reg(dev, REG_ADDR(mrsz_scale_vy), scale_vy); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hcr), scale_hcr); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hcb), scale_hcb); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hy), scale_hy); + isp_write_reg(dev, REG_ADDR(mrsz_ctrl), + ctrl | MRV_MRSZ_CFG_UPD_MASK); + } else if (id == IC_MI_PATH_SELF) { + isp_write_reg(dev, REG_ADDR(srsz_scale_vc), scale_vc); + isp_write_reg(dev, REG_ADDR(srsz_scale_vy), scale_vy); + isp_write_reg(dev, REG_ADDR(srsz_scale_hcr), scale_hcr); + isp_write_reg(dev, REG_ADDR(srsz_scale_hcb), scale_hcb); + isp_write_reg(dev, REG_ADDR(srsz_scale_hy), scale_hy); + isp_write_reg(dev, REG_ADDR(srsz_ctrl), + ctrl | MRV_MRSZ_CFG_UPD_MASK); + } + + return 0; +} + +#ifdef ISP_MI_BP +int isp_bppath_start(struct isp_ic_dev *dev) +{ + struct isp_mi_context mi = *(&dev->mi); + u32 bp_ctrl = 0, lval = 0; + struct isp_mi_data_path_context *path = &mi.path[2]; + u32 mi_imsc = isp_read_reg(dev, REG_ADDR(mi_imsc)); + int i; + + pr_info("enter %s\n", __func__); + bp_ctrl = 0; + lval = path->out_width; + + if (mi.path[2].enable) { + bp_ctrl &= ~MRV_MI_BP_WRITE_RAWBIT_MASK; + + if (path->data_alignMode == ISP_MI_DATA_ALIGN_16BIT_MODE) { + if ((path->out_mode == IC_MI_DATAMODE_RAW10) || + (path->out_mode == IC_MI_DATAMODE_RAW12) || + (path->out_mode == IC_MI_DATAMODE_RAW14)) { + lval = (path->out_width + 3) / 4; + } + } else if (path->data_alignMode == + ISP_MI_DATA_ALIGN_128BIT_MODE) { + if ((path->out_mode == IC_MI_DATAMODE_RAW10) + || (path->out_mode == IC_MI_DATAMODE_RAW12) + || (path->out_mode == IC_MI_DATAMODE_RAW14)) { + lval = (path->out_width * 2 + 126) / 128; + } + } else { + if (path->out_mode == IC_MI_DATAMODE_RAW10) { + lval = (path->out_width * 10 + 63) / 64; + } else if (path->out_mode == IC_MI_DATAMODE_RAW12) { + lval = (path->out_width * 12 + 63) / 64; + } else if (path->out_mode == IC_MI_DATAMODE_RAW14) { + lval = (path->out_width * 14 + 63) / 64; + } else if (path->out_mode == IC_MI_DATAMODE_RAW16) { + lval = (path->out_width * 16 + 63) / 64; + } else { + lval = (path->out_width * 8 + 63) / 64; + } + } + lval <<= 3; + REG_SET_SLICE(bp_ctrl, BP_WR_RAW_ALIGNED, path->data_alignMode); + switch (mi.path[2].out_mode) { + case (IC_MI_DATAMODE_RAW8): + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_RAWBIT, + MRV_MI_BP_WRITE_RAWBIT_RAW_8); + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_FORMAT, + MRV_MI_BP_WRITE_INTERLEAVE_FORMAT); + break; + case (IC_MI_DATAMODE_RAW12): + REG_SET_SLICE(bp_ctrl, BP_WR_BYTE_SWAP, 1); + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_RAWBIT, + MRV_MI_BP_WRITE_RAWBIT_RAW_12); + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_FORMAT, + MRV_MI_BP_WRITE_INTERLEAVE_FORMAT); + break; + case (IC_MI_DATAMODE_RAW10): + REG_SET_SLICE(bp_ctrl, BP_WR_BYTE_SWAP, 1); + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_RAWBIT, + MRV_MI_BP_WRITE_RAWBIT_RAW_10); + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_FORMAT, + MRV_MI_BP_WRITE_INTERLEAVE_FORMAT); + break; + default: + break; + } + isp_write_reg(dev, REG_ADDR(mi_bp_wr_size_init), + lval * mi.path[2].out_height); + isp_write_reg(dev, REG_ADDR(mi_bp_pic_width), + mi.path[2].out_width); + isp_write_reg(dev, REG_ADDR(mi_bp_wr_llength), lval); + isp_write_reg(dev, REG_ADDR(mi_bp_pic_height), + mi.path[2].out_height); + isp_write_reg(dev, REG_ADDR(mi_bp_pic_size), + lval * mi.path[2].out_height); + /* enable frame end irq for bp path */ + mi_imsc |= + MRV_MI_BP_FRAME_END_MASK | MRV_MI_BP_WRAP_R_MASK | + MRV_MI_BP_WRAP_GR_MASK | MRV_MI_BP_WRAP_GB_MASK | + MRV_MI_BP_WRAP_B_MASK; + } + if (!dev->rawis.enable) { + isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), + mi.path[2].out_width); + isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), + mi.path[2].out_height); + isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), 0); + } + bp_ctrl |= MRV_MI_BP_PATH_ENABLE_MASK; + isp_write_reg(dev, REG_ADDR(mi_bp_ctrl), bp_ctrl); + + isp_write_reg(dev, REG_ADDR(mi_imsc), mi_imsc); + return 0; +} +#endif +int isp_mi_start(struct isp_ic_dev *dev) +{ + struct isp_mi_context mi = *(&dev->mi); + u32 mi_init, mi_ctrl, mi_imsc; + u32 out_stride; + int i; + u8 retry = 3; + + pr_info("enter %s\n", __func__); + + isp_write_reg(dev, REG_ADDR(mrsz_ctrl), 0); + isp_write_reg(dev, REG_ADDR(mrsz_ctrl_shd), 0); + + for (i = 0; i < 2; i++) { + if (mi.path[i].hscale || mi.path[i].vscale) { + set_scaling(i, dev, dev->is.enable); + } + } + + mi_init = 0; + mi_ctrl = 0; + mi_imsc = 0; + if (mi.path[0].enable) { + /* remove update enable bits for offset and base registers */ + mi_init &= ~MRV_MI_MP_OUTPUT_FORMAT_MASK; + mi_ctrl &= ~MRV_MI_MP_WRITE_FORMAT_MASK; + + /* config mi_init output format for yuv format */ + if (mi.path[0].out_mode <= IC_MI_DATAMODE_YUV400) + REG_SET_SLICE(mi_init, MRV_MI_MP_OUTPUT_FORMAT, + IC_MI_DATAMODE_YUV400 - + mi.path[0].out_mode); + switch (mi.path[0].out_mode) { + case (IC_MI_DATAMODE_RAW8): + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_RAW_8); + REG_SET_SLICE(mi_ctrl, MRV_MI_RAW_ENABLE, 1); + REG_SET_SLICE(mi_init, MRV_MI_MP_OUTPUT_FORMAT, + MRV_MI_MP_OUTPUT_FORMAT_RAW8); + break; + case (IC_MI_DATAMODE_RAW12): + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_RAW_12); + REG_SET_SLICE(mi_ctrl, MRV_MI_RAW_ENABLE, 1); + REG_SET_SLICE(mi_init, MRV_MI_MP_OUTPUT_FORMAT, + MRV_MI_MP_OUTPUT_FORMAT_RAW12); + isp_write_reg(dev, REG_ADDR(mi_output_align_format), 1); + break; + case (IC_MI_DATAMODE_RAW10): + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_RAW_12); + REG_SET_SLICE(mi_ctrl, MRV_MI_RAW_ENABLE, 1); + REG_SET_SLICE(mi_init, MRV_MI_MP_OUTPUT_FORMAT, + MRV_MI_MP_OUTPUT_FORMAT_RAW10); + isp_write_reg(dev, REG_ADDR(mi_output_align_format), 1); + break; + case (IC_MI_DATAMODE_JPEG): + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_PLANAR); + REG_SET_SLICE(mi_ctrl, MRV_MI_JPEG_ENABLE, 1); + break; + case (IC_MI_DATAMODE_YUV444): + case (IC_MI_DATAMODE_YUV422): + case (IC_MI_DATAMODE_YUV420): + case (IC_MI_DATAMODE_YUV400): + if (mi.path[0].data_layout == IC_MI_DATASTORAGE_PLANAR) { + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_PLANAR); + } else if (mi.path[0].data_layout == + IC_MI_DATASTORAGE_SEMIPLANAR) { + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_SEMIPLANAR); + } else if (mi.path[0].data_layout == + IC_MI_DATASTORAGE_INTERLEAVED) { + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_INTERLEAVED); + } else { + break; + } + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_ENABLE, 1); + break; + default: + break; + } + + out_stride = mi.path[0].data_layout == + IC_MI_DATASTORAGE_INTERLEAVED ? + (mi.path[0].out_width * 2) : (mi.path[0].out_width); + isp_write_reg(dev, REG_ADDR(mi_mp_y_pic_width), out_stride); + isp_write_reg(dev, REG_ADDR(mi_mp_y_llength), out_stride); + isp_write_reg(dev, REG_ADDR(mi_mp_y_pic_height), + mi.path[0].out_height); + isp_write_reg(dev, REG_ADDR(mi_mp_y_pic_size), + out_stride * mi.path[0].out_height); + + /* workaround to resolve the problem that the mi_mp_y_pic_width can't be written */ + for(i = 0; i < retry; i++) { + if(isp_read_reg(dev, REG_ADDR(mi_mp_y_pic_width)) != out_stride) { + isp_write_reg(dev, REG_ADDR(mi_mp_y_pic_width), out_stride); + } else { + break; + } + } + if(retry == i) { + pr_info("%s: update mi_mp_y_pic_width error!\n", __func__); + } + + /* enable frame end irq for main path */ + mi_imsc |= + (MRV_MI_MP_FRAME_END_MASK | MRV_MI_WRAP_MP_Y_MASK | + MRV_MI_WRAP_MP_CB_MASK | MRV_MI_WRAP_MP_CR_MASK); + } + + if (mi.path[1].enable) { + /* setup mi for self-path */ + mi_ctrl &= ~(MRV_MI_SP_WRITE_FORMAT_MASK); + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_INPUT_FORMAT, + mi.path[1].in_mode - 1); + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_OUTPUT_FORMAT, + mi.path[1].out_mode - 1); + + switch (mi.path[1].out_mode) { + case (IC_MI_DATAMODE_RGB888): + case (IC_MI_DATAMODE_RGB666): + case (IC_MI_DATAMODE_RGB565): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_RGB_INTERLEAVED); + break; + case (IC_MI_DATAMODE_YUV444): + case (IC_MI_DATAMODE_YUV400): + if (mi.path[1].data_layout == IC_MI_DATASTORAGE_PLANAR) { + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_PLANAR); + } + break; + case (IC_MI_DATAMODE_YUV422): + switch (mi.path[1].data_layout) { + case (IC_MI_DATASTORAGE_PLANAR): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_PLANAR); + break; + case (IC_MI_DATASTORAGE_SEMIPLANAR): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_SEMIPLANAR); + break; + case (IC_MI_DATASTORAGE_INTERLEAVED): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_INTERLEAVED); + break; + default: + break; + } + break; + case (IC_MI_DATAMODE_YUV420): + switch (mi.path[1].data_layout) { + case (IC_MI_DATASTORAGE_PLANAR): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_PLANAR); + break; + case (IC_MI_DATASTORAGE_SEMIPLANAR): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_SEMIPLANAR); + break; + default: + break; + } + break; + default: + break; + } + + out_stride = mi.path[1].data_layout == + IC_MI_DATASTORAGE_INTERLEAVED ? + mi.path[1].out_width * 2 : mi.path[1].out_width; + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(mi_sp_y_pic_width), out_stride); + isp_write_reg(dev, REG_ADDR(mi_sp_y_llength), out_stride); + isp_write_reg(dev, REG_ADDR(mi_sp_y_pic_height), + mi.path[1].out_height); + isp_write_reg(dev, REG_ADDR(mi_sp_y_pic_size), + out_stride * mi.path[1].out_height); + /* enable frame end interrupt on self path */ + mi_imsc |= + (MRV_MI_SP_FRAME_END_MASK | MRV_MI_WRAP_SP_Y_MASK | + MRV_MI_WRAP_SP_CB_MASK | MRV_MI_WRAP_SP_CR_MASK); + } + +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + for (i = 0; i < MI_PATH_NUM; ++i) { + dev->mi_buf[i] = NULL; + dev->mi_buf_shd[i] = NULL; + } + if (dev->state) + *dev->state |= STATE_DRIVER_STARTED; +#endif + + mi_ctrl |= (MRV_MI_INIT_BASE_EN_MASK | MRV_MI_INIT_OFFSET_EN_MASK); + REG_SET_SLICE(mi_ctrl, MRV_MI_BURST_LEN_CHROM, mi.burst_len); + REG_SET_SLICE(mi_ctrl, MRV_MI_BURST_LEN_LUM, mi.burst_len); + isp_write_reg(dev, REG_ADDR(mi_ctrl), mi_ctrl | 0x2000); + REG_SET_SLICE(mi_init, MRV_MI_MI_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(mi_imsc), mi_imsc); +#ifdef ISP_MI_BP + isp_bppath_start(dev); +#endif + isp_write_reg(dev, REG_ADDR(mi_init), mi_init); + return 0; +} + +int isp_mi_stop(struct isp_ic_dev *dev) +{ + u32 mi_ctrl = 0, mi_init = 0; + pr_info("enter %s\n", __func__); + + isp_write_reg(dev, REG_ADDR(mi_imsc), 0); + + /* disable mi path */ + mi_ctrl = isp_read_reg(dev, REG_ADDR(mi_ctrl)); + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_ENABLE, 0); + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_ENABLE, 0); + REG_SET_SLICE(mi_ctrl, MRV_MI_JPEG_ENABLE, 0); + REG_SET_SLICE(mi_ctrl, MRV_MI_RAW_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(mi_ctrl), mi_ctrl); + + mi_init = isp_read_reg(dev, REG_ADDR(mi_init)); + REG_SET_SLICE(mi_init, MRV_MI_MI_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(mi_init), mi_init); + +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + if (dev->state) + *dev->state &= ~STATE_DRIVER_STARTED; + clean_dma_buffer(dev); +#endif + return 0; +} + +int isp_set_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + u32 addr; + + if (!dev || !buf) { + pr_err("NULL pointer %s\n", __func__); + return -EINVAL; + } + + addr = buf->path == 0 ? + REG_ADDR(mi_mp_y_base_ad_init) : REG_ADDR(mi_sp_y_base_ad_init); + isp_write_reg(dev, addr, (buf->addr_y & MRV_MI_MP_Y_BASE_AD_INIT_MASK)); + isp_write_reg(dev, addr + 1 * 4, + (buf->size_y & MRV_MI_MP_Y_SIZE_INIT_MASK)); + isp_write_reg(dev, addr + 2 * 4, 0); + isp_write_reg(dev, addr + 5 * 4, + (buf->addr_cb & MRV_MI_MP_CB_BASE_AD_INIT_MASK)); + isp_write_reg(dev, addr + 6 * 4, + (buf->size_cb & MRV_MI_MP_CB_SIZE_INIT_MASK)); + isp_write_reg(dev, addr + 7 * 4, 0); + isp_write_reg(dev, addr + 9 * 4, + (buf->addr_cr & MRV_MI_MP_CR_BASE_AD_INIT_MASK)); + isp_write_reg(dev, addr + 10 * 4, + (buf->size_cr & MRV_MI_MP_CR_SIZE_INIT_MASK)); + isp_write_reg(dev, addr + 11 * 4, 0); + + return 0; +} + +int isp_set_bp_buffer(struct isp_ic_dev *dev, struct isp_bp_buffer_context *buf) +{ +#ifndef ISP_MI_BP + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + isp_write_reg(dev, REG_ADDR(mi_bp_r_base_ad_init), + (buf->addr_r & BP_R_BASE_AD_INIT_MASK)); + isp_write_reg(dev, REG_ADDR(mi_bp_gr_base_ad_init), + (buf->addr_gr & BP_GR_BASE_AD_INIT_MASK)); + + isp_write_reg(dev, REG_ADDR(mi_bp_gb_base_ad_init), + (buf->addr_gb & BP_GB_BASE_AD_INIT_MASK)); + isp_write_reg(dev, REG_ADDR(mi_bp_b_base_ad_init), + (buf->addr_b & BP_B_BASE_AD_INIT_MASK)); + return 0; +#endif +} + +u32 isp_read_mi_irq(struct isp_ic_dev * dev) +{ + return isp_read_reg(dev, REG_ADDR(mi_mis)); +} + +void isp_reset_mi_irq(struct isp_ic_dev *dev, u32 icr) +{ + isp_write_reg(dev, REG_ADDR(mi_icr), icr); +} + +#endif diff --git a/vvcam/isp/isp_miv2.c b/vvcam/isp/isp_miv2.c new file mode 100755 index 0000000..5dcfd7f --- /dev/null +++ b/vvcam/isp/isp_miv2.c @@ -0,0 +1,1213 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +#ifdef ISP_MIV2 + +static void mi_set_slice(u32* val, u32 mask, u32 slice); +extern MrvAllRegister_t *all_regs; + +static int getRawBit(u32 type, u32 *bit, u32 *len) +{ + *len = 16; + switch (type) { + case ISP_PICBUF_TYPE_RAW8: + *bit = 0; + *len = 8; + break; +#if 0 /* normal process, need pass type from engine. */ + case ISP_PICBUF_TYPE_RAW10: + *bit = 1; + break; + case ISP_PICBUF_TYPE_RAW12: + *bit = 2; + break; + case ISP_PICBUF_TYPE_RAW14: + *bit = 3; + break; + case ISP_PICBUF_TYPE_RAW16: + *bit = 4; + break; +#else /* WA */ + case ISP_PICBUF_TYPE_RAW10: + case ISP_PICBUF_TYPE_RAW12: + case ISP_PICBUF_TYPE_RAW14: + case ISP_PICBUF_TYPE_RAW16: + *bit = 4; + break; +#endif + default: + pr_err("unsupport raw formt: %d\n", type); + return -1; + } + return 0; +} + +static bool isYuv(int type) +{ + return (type == ISP_PICBUF_TYPE_YCbCr444) || + (type == ISP_PICBUF_TYPE_YCbCr422) || + (type == ISP_PICBUF_TYPE_YCbCr420) || + (type == ISP_PICBUF_TYPE_YCbCr400); +} + +static bool isRaw(u32 type) +{ + return (type == ISP_PICBUF_TYPE_RAW8) || + (type == ISP_PICBUF_TYPE_RAW10) || + (type == ISP_PICBUF_TYPE_RAW12) || + (type == ISP_PICBUF_TYPE_RAW14) || (type == ISP_PICBUF_TYPE_RAW16); + +} + +static void set_rgb_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + u32 addr = buf->path == 0 ? REG_ADDR(miv2_mp_y_base_ad_init) : + (buf->path == + 1) ? REG_ADDR(miv2_sp1_y_base_ad_init) : + REG_ADDR(miv2_sp2_y_base_ad_init); + if (buf->type == ISP_PICBUF_TYPE_RGB888) { + isp_write_reg(dev, addr, (buf->addr_y & MP_Y_BASE_AD_MASK)); + isp_write_reg(dev, addr + 1 * 4, + (buf->size_y & MP_Y_SIZE_MASK)); + isp_write_reg(dev, addr + 2 * 4, 0); + isp_write_reg(dev, addr + 7 * 4, + (buf->addr_cb & MP_CB_BASE_AD_MASK)); + isp_write_reg(dev, addr + 8 * 4, + (buf->size_cb & MP_CB_SIZE_MASK)); + isp_write_reg(dev, addr + 9 * 4, 0); + isp_write_reg(dev, addr + 10 * 4, + (buf->addr_cr & MP_CR_BASE_AD_MASK)); + isp_write_reg(dev, addr + 11 * 4, + (buf->size_cr & MP_CR_SIZE_MASK)); + isp_write_reg(dev, addr + 12 * 4, 0); + } +} +/*#define PP_LINE_ENTRY*/ +#define PP_LINE_NUM 80*2 + +static void set_yuv_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + + u32 addr = buf->path == 0 ? REG_ADDR(miv2_mp_y_base_ad_init) : + (buf->path == 1) ? REG_ADDR(miv2_sp1_y_base_ad_init) : + (buf->path == 2) ? REG_ADDR(miv2_sp2_y_base_ad_init) : + REG_ADDR(isp_mi_pp_y_base_ad_init); + + if (isYuv(buf->type)) { + isp_write_reg(dev, addr, (buf->addr_y & MP_Y_BASE_AD_MASK)); + isp_write_reg(dev, addr + 1 * 4, + (buf->size_y & MP_Y_SIZE_MASK)); + isp_write_reg(dev, addr + 2 * 4, 0); + isp_write_reg(dev, addr + 7 * 4, + (buf->addr_cb & MP_CB_BASE_AD_MASK)); + isp_write_reg(dev, addr + 8 * 4, + (buf->size_cb & MP_CB_SIZE_MASK)); + isp_write_reg(dev, addr + 9 * 4, 0); + isp_write_reg(dev, addr + 10 * 4, + (buf->addr_cr & MP_CR_BASE_AD_MASK)); + isp_write_reg(dev, addr + 11 * 4, + (buf->size_cr & MP_CR_SIZE_MASK)); + isp_write_reg(dev, addr + 12 * 4, 0); + + + } +} + +static void set_raw_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + u32 addr = buf->path == ISP_MI_PATH_MP ? REG_ADDR(miv2_mp_raw_base_ad_init) : + (buf->path == ISP_MI_PATH_SP2_BP) ? REG_ADDR(miv2_sp2_raw_base_ad_init) : + (buf->path == ISP_MI_PATH_PP) ?REG_ADDR(isp_mi_pp_y_base_ad_init): +#ifdef ISP_MI_MCM_WR + (buf->path == ISP_MI_MCM_WR0) ?REG_ADDR(miv2_mcm_raw0_base_ad_init): + (buf->path == ISP_MI_MCM_WR1) ?REG_ADDR(miv2_mcm_raw1_base_ad_init): +#endif +#ifdef ISP_MI_HDR + (buf->path == ISP_MI_HDR_L) ?REG_ADDR(isp_mi_hdr_l_base_ad_init): + (buf->path == ISP_MI_HDR_S) ?REG_ADDR(isp_mi_hdr_s_base_ad_init): + (buf->path == ISP_MI_HDR_VS) ?REG_ADDR(isp_mi_hdr_vs_base_ad_init): +#endif + 0; + uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num)); + if ((buf->path == ISP_MI_PATH_PP) && (line_num != 0)) { + buf->addr_y = dev->pp_write.buf_addr; + buf->size_y = dev->pp_write.buf_size; + } + /*pr_info("%s path %d type %d addr %08x line_num = %d buf_addr = 0x%x, buf_size = %d\n", + __func__, buf->path, buf->type, addr, line_num, buf->addr_y, buf->size_y);*/ + if (isRaw(buf->type)) { + if (addr != 0) { + isp_write_reg(dev, addr, + (buf->addr_y & MP_RAW_BASE_AD_MASK)); + isp_write_reg(dev, addr + 4, + (buf->size_y & MP_RAW_SIZE_MASK)); + isp_write_reg(dev, addr + 2 * 4, 0); + } + } + +} + +int isp_set_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + if (!dev || !buf) { + pr_err("NULL pointer %s\n", __func__); + return -1; + } + + set_yuv_buffer(dev, buf); + set_raw_buffer(dev, buf); + set_rgb_buffer(dev, buf); + return 0; +} + +static int calc_raw_lval(int width, int out_mode, int align_mode) +{ + u32 lval = 0; + + if (align_mode == ISP_MI_DATA_ALIGN_16BIT_MODE) { + if ((out_mode == IC_MI_DATAMODE_RAW10) || + (out_mode == IC_MI_DATAMODE_RAW12) || + (out_mode == IC_MI_DATAMODE_RAW14)) { + lval = (width + 7) / 8; + } + } else if (align_mode == ISP_MI_DATA_ALIGN_128BIT_MODE) { + if (out_mode == IC_MI_DATAMODE_RAW10){ + lval = (width + 12 - 1)/12; + }else if(out_mode == IC_MI_DATAMODE_RAW12){ + lval = (width + 10 - 1)/10; + }else if(out_mode == IC_MI_DATAMODE_RAW14){ + lval = (width + 9 - 1)/9; + }else{ + lval = (width + 128 - 1)/128; + } + } else { + if (out_mode == IC_MI_DATAMODE_RAW10) { + lval = (width * 10 + 127) / 128; + } else if (out_mode == IC_MI_DATAMODE_RAW12) { + lval = (width * 12 + 127) / 128; + } else if (out_mode == IC_MI_DATAMODE_RAW14) { + lval = (width * 14 + 127) / 128; + } else if (out_mode == IC_MI_DATAMODE_RAW16) { + lval = (width * 16 + 127) / 128; + } else { + lval = (width * 8 + 127) / 128; + } + } + + return lval; +} + +struct isp_dma_path_context{ + u32 ctrl_addr; + u32 fmt_addr; + u32 bus_cfg_addr; + u32 bus_id_addr; + u32 mi_imsc_addr; + u32 rd_fmt_align; + u32 rd_raw_bit; + u32 rd_cfg_upd; + u32 rd_auto_upd; + u32 pic_start_addr; + u32 pic_width; + u32 pic_height; + u32 pic_llength; + u32 pic_size; + u32 pic_lval; + u32 path_enable_mask; + u32 path_dma_start_mask; +}; + +int isp_ioc_cfg_dma(struct isp_ic_dev *dev, void __user *args) +{ + u32 llength, miv2_imsc, miv2_ctrl,path_ctrl,path_fmt; + struct isp_dma_context dma; + //u32 path_bus_cfg; + u32 bus_id; + u32 path_rd_fmt_bit = 0; + u8 id; + struct isp_dma_path_context dma_path_ctx[] = +#ifndef ISP_MI_PP_READ + {{REG_ADDR(miv2_mcm_ctrl), REG_ADDR(miv2_mcm_fmt), REG_ADDR(miv2_mcm_bus_cfg), REG_ADDR(miv2_mcm_bus_id), + REG_ADDR(miv2_imsc), MCM_RD_FMT_ALIGNED_MASK, MCM_RD_RAW_BIT_MASK, MCM_RD_CFG_UPD_MASK, MCM_RD_AUTO_UPDATE_MASK, \ + REG_ADDR(miv2_mcm_dma_raw_pic_start_ad), REG_ADDR(miv2_mcm_dma_raw_pic_width), 0, \ + REG_ADDR(miv2_mcm_dma_raw_pic_llength), REG_ADDR(miv2_mcm_dma_raw_pic_size), \ + REG_ADDR(miv2_mcm_dma_raw_pic_lval), MCM_RAW_RDMA_PATH_ENABLE_MASK, MCM_RAW_RDMA_START_MASK}, +#ifdef ISP_MI_HDR + {REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(miv2_imsc2), \ + HDR_RD_RAW_ALIGNED_MASK, HDR_RD_L_BIT_MASK, HDR_RD_RAW_CFG_UPDATE_MASK,HDR_RD_RAW_CFG_UPDATE_MASK, \ + REG_ADDR(isp_mi_hdr_dma_l_base_ad_init), REG_ADDR(isp_mi_hdr_dma_pic_width), REG_ADDR(isp_mi_hdr_dma_pic_height), \ + REG_ADDR(isp_mi_hdr_dma_l_llength), REG_ADDR(isp_mi_hdr_dma_l_size_init), \ + REG_ADDR(isp_mi_hdr_dma_l_lval), 0, HDR_DMA_START_MASK}, + + {REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(miv2_imsc2), \ + HDR_RD_RAW_ALIGNED_MASK, HDR_RD_S_BIT_MASK, HDR_RD_RAW_CFG_UPDATE_MASK,HDR_RD_RAW_CFG_UPDATE_MASK, \ + REG_ADDR(isp_mi_hdr_dma_s_base_ad_init), REG_ADDR(isp_mi_hdr_dma_pic_width), REG_ADDR(isp_mi_hdr_dma_pic_height), \ + REG_ADDR(isp_mi_hdr_dma_s_llength), REG_ADDR(isp_mi_hdr_dma_s_size_init), \ + REG_ADDR(isp_mi_hdr_dma_s_lval), 0, HDR_DMA_START_MASK}, + + {REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(miv2_imsc2), \ + HDR_RD_RAW_ALIGNED_MASK, HDR_RD_VS_BIT_MASK, HDR_RD_RAW_CFG_UPDATE_MASK,HDR_RD_RAW_CFG_UPDATE_MASK, \ + REG_ADDR(isp_mi_hdr_dma_vs_base_ad_init), REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_dma_pic_height), \ + REG_ADDR(isp_mi_hdr_dma_vs_llength), REG_ADDR(isp_mi_hdr_dma_vs_size_init), \ + REG_ADDR(isp_mi_hdr_dma_vs_lval), 0, HDR_DMA_START_MASK} +#endif + }; +#else + {{REG_ADDR(isp_mi_pp_ctrl), REG_ADDR(isp_mi_pp_fmt), 0, 0, REG_ADDR(miv2_imsc2), \ + PP_RD_RAW_ALIGNED_MASK, PP_RD_RAW_BIT_MASK, PP_MI_CFG_UPD_MASK, PP_RD_YUV_CFG_UPDATE_MASK, \ + REG_ADDR(isp_mi_pp_dma_y_pic_start_ad), REG_ADDR(isp_mi_pp_dma_y_pic_width), 0, \ + REG_ADDR(isp_mi_pp_dma_y_pic_llength), REG_ADDR(isp_mi_pp_dma_y_pic_size), \ + REG_ADDR(isp_mi_pp_dma_y_pic_lval), 0, PP_DMA_START_MASK}}; +#endif + if (dev == NULL || args == NULL) { + pr_info("input wrong parameter %s\n", __func__); + return -1; + } + + pr_info("enter %s\n", __func__); + + viv_check_retval(copy_from_user(&dma, args, sizeof(dma))); + id = dma.id; + if ( id > ISP_MI_DMA_ID_MAX){ + pr_info("id config wrong %s\n", __func__); + return -1; + } + path_fmt = isp_read_reg(dev, dma_path_ctx[id].fmt_addr); +#ifdef ISP_MI_PP_READ + path_fmt |= 0x80000000; +#endif + miv2_imsc = isp_read_reg(dev, dma_path_ctx[id].mi_imsc_addr); + miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + path_ctrl = isp_read_reg(dev, dma_path_ctx[id].ctrl_addr); + + //if ( dma_path_ctx[id].bus_cfg_addr != 0) { + // path_bus_cfg = isp_read_reg(dev, dma_path_ctx[id].bus_cfg_addr); + //} + if ( dma_path_ctx[id].bus_id_addr != 0) { + bus_id = isp_read_reg(dev, dma_path_ctx[id].bus_id_addr); + } + + if ( dma.align == ISP_MI_DATA_UNALIGN_MODE ) { + + switch(dma.type){ + case ISP_PICBUF_TYPE_RAW10: + llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW10, ISP_MI_DATA_UNALIGN_MODE); + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 1); + break; + case ISP_PICBUF_TYPE_RAW12: + llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW12,ISP_MI_DATA_UNALIGN_MODE); + if (id >= ISP_MI_DMA_ID_HDR_L && id <= ISP_MI_DMA_ID_HDR_VS) { + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 0); //mi dma hdr stitch raw only support raw12 and raw16 + } else { + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 2); + } + break; + case ISP_PICBUF_TYPE_RAW14: + llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW14, ISP_MI_DATA_UNALIGN_MODE); + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 3); + break; + case ISP_PICBUF_TYPE_RAW16: + llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW16, ISP_MI_DATA_UNALIGN_MODE); + if (id >= ISP_MI_DMA_ID_HDR_L && id <= ISP_MI_DMA_ID_HDR_VS) { + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 1); //mi dma hdr stitch raw only support raw12 and raw16 + } else { + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 4); + } + + break; + default: + return -EFAULT; + } + + llength <<= 4; + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_fmt_align, dma.align); + + } else { + getRawBit(dma.type, &path_rd_fmt_bit, &llength); //The old version load all kinds of raw format with raw16 format except raw8 + llength = dma.width * llength / 8; + if (id >= ISP_MI_DMA_ID_HDR_L && id <= ISP_MI_DMA_ID_HDR_VS) { + path_rd_fmt_bit = 1; + } + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, path_rd_fmt_bit); + } + +/* if (llength != 8) + REG_SET_SLICE(mcm_bus_cfg, MCM_RD_SWAP_RAW, 1);*/ + + //path_ctrl |= PP_RD_YUV_CFG_UPDATE_MASK; //PP_INIT_OFFSET_EN_MASK | PP_INIT_BASE_EN_MASK | + isp_write_reg(dev, dma_path_ctx[id].pic_start_addr, (MCM_DMA_RAW_PIC_START_AD_MASK & dma.base)); + isp_write_reg(dev,dma_path_ctx[id].pic_width, (MCM_DMA_RAW_PIC_WIDTH_MASK & dma.width)); + + if (dma_path_ctx[id].pic_height) { + isp_write_reg(dev,dma_path_ctx[id].pic_height, dma.height); + } + + isp_write_reg(dev, dma_path_ctx[id].pic_llength, (MCM_DMA_RAW_PIC_LLENGTH_MASK & llength)); + isp_write_reg(dev,dma_path_ctx[id].pic_size, (MCM_DMA_RAW_PIC_SIZE_MASK & (llength * dma.height))); + isp_write_reg(dev, dma_path_ctx[id].pic_lval, (MCM_DMA_RAW_PIC_WIDTH_MASK & llength)); + isp_write_reg(dev, dma_path_ctx[id].fmt_addr, path_fmt); + + //isp_write_reg(dev, REG_ADDR(miv2_mcm_bus_cfg), path_bus_cfg); +#ifdef ISP_MI_PP_READ + isp_write_reg(dev, REG_ADDR(mi_pp_dma_y_pic_height), dma.height); + isp_write_reg(dev, REG_ADDR(mi_pp_y_lval_bytes), llength); + + // isp_write_reg(dev, 0x55c0, dma.height); + // isp_write_reg(dev, 0x55c4, dma.height); + // isp_write_reg(dev, 0x55c8, dma.height); + // isp_write_reg(dev, 0x55cc, llength); + + isp_write_reg(dev, dma_path_ctx[id].mi_imsc_addr, miv2_imsc | PPR_DMA_READY_MASK); /* enabled pp dma */ +#else + isp_write_reg(dev, dma_path_ctx[id].mi_imsc_addr, miv2_imsc | 0x01800025); /* enabled jdp, sp2_raw, mp_raw, mcm */ +#endif + + if(id == ISP_MI_DMA_ID_MCM_PP) { + miv2_ctrl |= (dma_path_ctx[id].path_enable_mask );//| dma_path_ctx[id].path_dma_start_mask); + //path_ctrl |= 0xfa; + mi_set_slice(&path_ctrl, dma_path_ctx[id].rd_cfg_upd, 1); + mi_set_slice(&path_ctrl, dma_path_ctx[id].rd_auto_upd, 1); + + REG_SET_SLICE(bus_id, MCM_BUS_SW_EN, 1); + REG_SET_SLICE(bus_id, MCM_RD_ID_EN, 1); + if (dma_path_ctx[id].bus_id_addr) { + isp_write_reg(dev, dma_path_ctx[id].bus_id_addr, bus_id); + } + isp_write_reg(dev,dma_path_ctx[id].ctrl_addr, path_ctrl); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); +#ifdef ISP_MI_HDR + } else { + REG_SET_SLICE(path_fmt, HDR_RD_STR, dma.rd_wr_str); + //config wr str, l,s,vs bit and wr raw aligned same with rd str,l,s,vs bit and wr raw aligned + path_fmt |= ((path_fmt >> HDR_RD_STR_SHIFT) &0x3ff) ; + isp_write_reg(dev, dma_path_ctx[id].fmt_addr, path_fmt); + + /*hdr mi dma path enable in mi hdr ctrl register*/ + path_ctrl |= (dma_path_ctx[id].path_enable_mask) ; //| dma_path_ctx[id].path_dma_start_mask); + REG_SET_SLICE(path_ctrl, HDR_INIT_OFFSET_EN, 1); + REG_SET_SLICE(path_ctrl, HDR_INIT_BASE_EN, 1); + + REG_SET_SLICE(bus_id, HDR_BUS_SW_EN, 1); + REG_SET_SLICE(bus_id, HDR_RD_ID_EN, 1); + if (dma_path_ctx[id].bus_id_addr) { + isp_write_reg(dev, dma_path_ctx[id].bus_id_addr, bus_id); + } + isp_write_reg(dev,dma_path_ctx[id].ctrl_addr, path_ctrl); +#endif + } + + + return 0; + +} +/* only support read raw */ +int isp_ioc_start_dma_read(struct isp_ic_dev *dev, void __user *args) +{ + start_dma_path_t dma_path; + u32 mi_hdr_fmt; + u32 mi_path_ctrl; + u32 mi_hdr_ret_ctrl; + u32 rd_wr_str; + if (dev == NULL || args == NULL) { + pr_info("input wrong parameter %s\n", __func__); + return -1; + } + + pr_info("enter %s\n", __func__); + viv_check_retval(copy_from_user(&dma_path, args, sizeof(dma_path))); + if (dma_path == ISP_MI_DMA_PATH_MCM_PP) { +#ifndef ISP_MI_PP_READ + mi_path_ctrl = isp_read_reg(dev,REG_ADDR(miv2_ctrl)); + REG_SET_SLICE(mi_path_ctrl, MCM_RAW_RDMA_START, 1); + isp_write_reg(dev,REG_ADDR(miv2_ctrl), mi_path_ctrl); +#else + mi_path_ctrl = isp_read_reg(dev,REG_ADDR(miv2_ctrl)); + REG_SET_SLICE(mi_path_ctrl, PP_DMA_START, 1); + isp_write_reg(dev,REG_ADDR(miv2_ctrl), mi_path_ctrl); +#endif + } else if (dma_path == ISP_MI_DMA_PATH_HDR) { + + isp_write_reg(dev, REG_ADDR(isp_mi_hdr_ret_bus_timeo), 0x00000001); //disable bus time out interrupt + + mi_hdr_ret_ctrl = isp_read_reg(dev,REG_ADDR(isp_hdr_ret_ctrl)); + REG_SET_SLICE(mi_hdr_ret_ctrl, HDR_RT_VSYNC_POL, 1); + REG_SET_SLICE(mi_hdr_ret_ctrl, HDR_RETIMING_ENABLE, 1); + REG_SET_SLICE(mi_hdr_ret_ctrl, DUMP_MODE_EN, 1); + mi_hdr_fmt = isp_read_reg(dev,REG_ADDR(isp_mi_hdr_fmt)); + rd_wr_str = (mi_hdr_fmt & HDR_RD_STR_MASK)>>HDR_RD_STR_SHIFT; + if (rd_wr_str == 0) { + REG_SET_SLICE(mi_hdr_ret_ctrl, EXPOSURE_COUNT, 1); + } else if (rd_wr_str == 1|| rd_wr_str == 3) { + REG_SET_SLICE(mi_hdr_ret_ctrl, EXPOSURE_COUNT, 2); + if (rd_wr_str == 3) { + REG_SET_SLICE(mi_hdr_ret_ctrl, L_VS_COMBINING_ENABLE, 1); + } + } else if (rd_wr_str == 2) { + REG_SET_SLICE(mi_hdr_ret_ctrl, EXPOSURE_COUNT, 0); + } + isp_write_reg(dev, REG_ADDR(isp_mi_hdr_dma_start_by_lines), 0x360);//0x10); //the written lines count of the last appearing frame after which start dma read + isp_write_reg(dev,REG_ADDR(isp_hdr_ret_ctrl), mi_hdr_ret_ctrl); + mi_path_ctrl = isp_read_reg(dev,REG_ADDR(isp_mi_hdr_ctrl)); + REG_SET_SLICE(mi_path_ctrl, HDR_RD_RAW_CFG_UPDATE, 1); + REG_SET_SLICE(mi_path_ctrl, HDR_RD_RAW_AUTO_UPDATE, 1); + + REG_SET_SLICE(mi_path_ctrl, HDR_DMA_START, 1); + isp_write_reg(dev,REG_ADDR(isp_mi_hdr_ctrl), mi_path_ctrl); + + } + return 0; +} + +#define PATHNUM ISP_MI_PATH_ID_MAX// hw related + +// only config write bits, SP2 read bit at 3dnr.c +// read defined is same as write +struct miv2_format_bit { + u32 nyv, nv12; + u32 raw_aligned, yuv_aligned; + u32 raw_bit, yuv_str; + u32 yuv_fmt, yuv_bit, jdp_fmt; +}; + +static struct miv2_format_bit fmt_bit[PATHNUM] = { + { + .nyv = 3 << 13, .nv12 = 1 << 12, + .raw_aligned = 3 << 10, + .yuv_aligned = 1 << 9, + .raw_bit = 7 << 6, + .yuv_str = 3 << 4, + .yuv_fmt = 3 << 2, + .yuv_bit = 1 << 1, + .jdp_fmt = 1, + }, + { + .nyv = 3 << 7, + .nv12 = 1 << 6, + .yuv_aligned = 1 << 5, + .yuv_str = 3 << 3, + .yuv_fmt = 3 << 1, + .yuv_bit = 1, + }, + { + .nyv = 3 << 12, + .nv12 = 1 << 11, + .raw_aligned = 3 << 9, + .yuv_aligned = 1 << 8, + .raw_bit = 7 << 5, + .yuv_str = 3 << 3, + .yuv_fmt = 3 << 1, + .yuv_bit = 1, + }, +#ifdef ISP_MI_MCM_WR + { + .nyv = 0, + .nv12 = 0, + .raw_aligned = 3 << 14, + .raw_bit = 3 << 4, + .yuv_aligned = 0, + .yuv_str = 0, + .yuv_fmt = 0, + .yuv_bit = 0, + }, + { + .nyv = 0, + .nv12 = 0, + .raw_aligned = 3 << 16, + .raw_bit = 3 << 8, + .yuv_aligned = 0, + .yuv_str = 0, + .yuv_fmt = 0, + .yuv_bit = 0, + }, +#endif +#ifdef ISP_MI_PP_WRITE + { + .nyv = 3 << 7, + .nv12 = 1 << 6, + .raw_aligned = 3 << 14, + .raw_bit = 7 << 11, + .yuv_aligned = 1 << 5, + .yuv_str = 3 << 3, + .yuv_fmt = 3 << 1, + .yuv_bit = 1, + }, +#endif +#ifdef ISP_MI_HDR + { + .nyv = 0, + .nv12 = 0, + .raw_aligned = 3 << 8, + .raw_bit = 3 << 2, + .yuv_aligned = 0, + .yuv_str = 0, + .yuv_fmt = 0, + .yuv_bit = 0, + }, + { + .nyv = 0, + .nv12 = 0, + .raw_aligned = 3 << 8, + .raw_bit = 3 << 4, + .yuv_aligned = 0, + .yuv_str = 0, + .yuv_fmt = 0, + .yuv_bit = 0, + }, + { + .nyv = 0, + .nv12 = 0, + .raw_aligned = 3 << 8, + .raw_bit = 3 << 6, + .yuv_aligned = 0, + .yuv_str = 0, + .yuv_fmt = 0, + .yuv_bit = 0, + }, +#endif +}; + +static u32 bit_shift(u32 i) { + u32 shift = 0; + while(!(i&1)) { + shift++; + i >>= 1; + } + return shift; +} + +void mi_set_slice(u32* val, u32 mask, u32 slice) +{ + // mp, sp1, sp2 mcm postpath have different masks. + if (mask) { + *val &= ~mask; + *val |= (slice << bit_shift(mask)); + } +} + +struct miv2_path_address { + u32 bus_cfg_addr; + u32 bus_id_addr; + u32 bus_timeo_addr; //axi bus time out waiting ctrl register + u32 path_ctrl_addr; + u32 format_addr; + u32 y_length_addr; + u32 raw_llength_addr; + u32 raw_pic_width_addr; + u32 raw_pic_height_addr; + u32 raw_pic_size_addr; + u32 ycbcr_enable_bit; + u32 raw_enable_bit; + u32 format_conv_ctrl; + u32 wr_raw_swap_bit; +}; + +static void disable_bus_timeo_intr(struct isp_ic_dev *dev, u32 bus_addr) +{ + u32 val; + pr_info("%s bus timeo interrupt register addr 0x%08x\n", __func__, bus_addr); + val = isp_read_reg(dev, bus_addr); + REG_SET_SLICE(val, MP_BUS_TIMEO_INTERRUPT_DISABLE, 1); + isp_write_reg(dev, bus_addr, val); +} + +static void set_qos(struct isp_ic_dev *dev) +{ + pr_info("isp %s enter\n", __func__); + + isp_write_reg(dev, 0x1308, MI_QOS); + isp_write_reg(dev, 0x130C, MI_QOS2); + pr_info("isp %s exit\n", __func__); +} + +static void set_data_path(int id, struct isp_mi_data_path_context *path, + struct isp_ic_dev *dev) +{ + u32 bus_cfg, bus_id; + u32 format; + u32 miv2_ctrl; + u32 path_ctrl; + u32 lval; + u32 acq_proc; + u32 mcm_bus_cfg = isp_read_reg(dev, REG_ADDR(miv2_mcm_bus_cfg)); + u32 conv_format_ctrl = 0; + u32 y_length_addr; + u32 y_llength = 0; +#ifdef ISP_MI_PP_WRITE + u32 isp_ctrl; +#endif + // please take care the register order +#if 0 + struct miv2_path_address path_list[PATHNUM] = { + { 0x1318, 0x131c, 0x1310, 0x1314, 0x1330, 0x13a0, 0x13a4, 0x13a8, 0x13ac, 1, 0x0c6c }, + { 0x1434, 0x1438, 0x142c, 0x1430, 0x144c, 0, 0, 0, 8, 0x106c }, + { 0x14ec, 0x14f0, 0x14e4, 0x14e8, 0x1504, 0x1574, 0x1578, 0x157c, 0x1580, 0x10, 0x116c }, + }; +#else + //id 0 is mp path;id 1 is sp path;id 2 is sp2 path; + //id 3 is post process path write; + struct miv2_path_address path_list[PATHNUM] = { + { + REG_ADDR(miv2_mp_bus_cfg), REG_ADDR(miv2_mp_bus_id), REG_ADDR(miv2_mp_bus_timeo), REG_ADDR(miv2_mp_ctrl), + REG_ADDR(miv2_mp_fmt), REG_ADDR(miv2_mp_y_llength), REG_ADDR(miv2_mp_raw_llength), + REG_ADDR(miv2_mp_raw_pic_width), REG_ADDR(miv2_mp_raw_pic_height), REG_ADDR(miv2_mp_raw_pic_size), + MP_YCBCR_PATH_ENABLE_MASK, MP_RAW_PATH_ENABLE_MASK, REG_ADDR(mrsz_format_conv_ctrl), MP_WR_SWAP_RAW_MASK + }, + { + REG_ADDR(miv2_sp1_bus_cfg), REG_ADDR(miv2_sp1_bus_id), REG_ADDR(miv2_sp1_bus_timeo), REG_ADDR(miv2_sp1_ctrl), + REG_ADDR(miv2_sp1_fmt), REG_ADDR(miv2_sp1_y_llength), 0, + 0, 0, 0, + SP1_YCBCR_PATH_ENABLE_MASK, 0, REG_ADDR(srsz_phase_format_conv_ctr), 0, + }, + { + REG_ADDR(miv2_sp2_bus_cfg), REG_ADDR(miv2_sp2_bus_id), REG_ADDR(miv2_sp2_bus_timeo), REG_ADDR(miv2_sp2_ctrl), + REG_ADDR(miv2_sp2_fmt), REG_ADDR(miv2_sp2_y_llength), REG_ADDR(miv2_sp2_raw_llength), + REG_ADDR(miv2_sp2_raw_pic_width), REG_ADDR(miv2_sp2_raw_pic_height), REG_ADDR(miv2_sp2_raw_pic_size), + SP2_YCBCR_PATH_ENABLE_MASK, SP2_RAW_PATH_ENABLE_MASK, REG_ADDR(srsz2_phase_format_conv_ctr), + SP2_WR_SWAP_RAW_MASK + }, +#ifdef ISP_MI_MCM_WR + { + REG_ADDR(miv2_mcm_bus_cfg), REG_ADDR(miv2_mcm_bus_id), REG_ADDR(miv2_mcm_bus_timeo), REG_ADDR(miv2_mcm_ctrl), + REG_ADDR(miv2_mcm_fmt), 0, REG_ADDR(miv2_mcm_raw0_llength), + REG_ADDR(miv2_mcm_raw0_pic_width), REG_ADDR(miv2_mcm_raw0_pic_height), REG_ADDR(miv2_mcm_raw0_pic_size), + 0, MCM_RAW0_PATH_ENABLE_MASK, 0, MCM_WR0_SWAP_RAW_MASK + }, + + { + REG_ADDR(miv2_mcm_bus_cfg), REG_ADDR(miv2_mcm_bus_id), REG_ADDR(miv2_mcm_bus_timeo), REG_ADDR(miv2_mcm_ctrl), + REG_ADDR(miv2_mcm_fmt), 0, REG_ADDR(miv2_mcm_raw1_llength), + REG_ADDR(miv2_mcm_raw1_pic_width), REG_ADDR(miv2_mcm_raw1_pic_height), REG_ADDR(miv2_mcm_raw1_pic_size), + 0, MCM_RAW1_PATH_ENABLE_MASK, 0, MCM_WR1_SWAP_RAW_MASK + }, +#endif + { + REG_ADDR(isp_mi_pp_data_swap), REG_ADDR(miv2_sp1_bus_id), REG_ADDR(miv2_sp1_bus_timeo), REG_ADDR(isp_mi_pp_ctrl), + REG_ADDR(isp_mi_pp_fmt), REG_ADDR(isp_mi_pp_y_llength), REG_ADDR(mi_pp_y_lval_bytes), + REG_ADDR(isp_mi_pp_y_pic_width), REG_ADDR(isp_mi_pp_y_pic_height), REG_ADDR(isp_mi_pp_y_pic_size), + PP_WRITE_PATH_ENABLE_MASK, PP_WRITE_PATH_ENABLE_MASK, 0,PP_WR_SWAP_Y_MASK + }, +#ifdef ISP_MI_HDR + { + REG_ADDR(isp_mi_hdr_ret_bus_cfg), REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(isp_mi_hdr_ret_bus_timeo), + REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_l_llength), + REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_pic_height), REG_ADDR(isp_mi_hdr_l_size_init), + 0, HDR_WR_ENABLE_MASK, 0, HDR_WR_SWAP_RAW_MASK + }, + + { + REG_ADDR(isp_mi_hdr_ret_bus_cfg), REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(isp_mi_hdr_ret_bus_timeo), + REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_s_llength), + REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_pic_height), REG_ADDR(isp_mi_hdr_s_size_init), + 0, HDR_WR_ENABLE_MASK, 0, HDR_WR_SWAP_RAW_MASK + }, + { + REG_ADDR(isp_mi_hdr_ret_bus_cfg), REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(isp_mi_hdr_ret_bus_timeo), + REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_vs_llength), + REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_pic_height), REG_ADDR(isp_mi_hdr_vs_size_init), + 0, HDR_WR_ENABLE_MASK, 0, HDR_WR_SWAP_RAW_MASK + }, +#endif + + }; +#endif + + if (!path->enable) { + disable_bus_timeo_intr(dev, path_list[id].bus_timeo_addr); + return; + } + + + if (path->hscale || path->vscale || dev->is.enable) { + if (id <= ISP_MI_PATH_SP2_BP) + isp_set_scaling(id, dev, dev->is.enable, dev->crop[id].enabled); + else + isp_set_scaling(id, dev, dev->is.enable, 0); + + } + + miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + if(path_list[id].bus_cfg_addr) + bus_cfg = isp_read_reg(dev, path_list[id].bus_cfg_addr); + format = isp_read_reg(dev, path_list[id].format_addr); + if (path_list[id].format_conv_ctrl) { + conv_format_ctrl = isp_read_reg(dev, path_list[id].format_conv_ctrl); + } + pr_err("mi %s id %d fmt_bit[id].raw_bit 0x%08x miv2_ctrl 0x%08x ", __func__, id, path_list[id].raw_enable_bit, miv2_ctrl); + + path_ctrl = isp_read_reg(dev, path_list[id].path_ctrl_addr); + switch (path->out_mode) { + case IC_MI_DATAMODE_YUV444: + mi_set_slice(&format, fmt_bit[id].yuv_fmt, 2); + miv2_ctrl |= path_list[id].ycbcr_enable_bit; + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_OUTPUT, 3); + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_INPUT, 2); + break; + case IC_MI_DATAMODE_YUV422: + mi_set_slice(&format, fmt_bit[id].yuv_fmt, 1); + miv2_ctrl |= path_list[id].ycbcr_enable_bit; + break; + case IC_MI_DATAMODE_YUV420: + mi_set_slice(&format, fmt_bit[id].yuv_fmt, 0); + miv2_ctrl |= path_list[id].ycbcr_enable_bit; + break; + case IC_MI_DATAMODE_YUV400: + case IC_MI_DATAMODE_JPEG: + mi_set_slice(&format, fmt_bit[id].jdp_fmt, 1); + REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1); + break; + case IC_MI_DATAMODE_RAW8: + mi_set_slice(&format, fmt_bit[id].raw_bit, 0); + miv2_ctrl |= path_list[id].raw_enable_bit; + break; + case IC_MI_DATAMODE_RAW10: + mi_set_slice(&format, fmt_bit[id].raw_bit, 1); + miv2_ctrl |= path_list[id].raw_enable_bit; + + mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + break; + case IC_MI_DATAMODE_RAW12: +#ifdef ISP_MI_HDR + if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) { + mi_set_slice(&format, fmt_bit[id].raw_bit, 0); + path_ctrl |= path_list[id].raw_enable_bit; + //mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + } +#endif + if (id <= ISP_MI_PATH_PP) { + mi_set_slice(&format, fmt_bit[id].raw_bit, 2); + miv2_ctrl |= path_list[id].raw_enable_bit; + mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + } + break; + case IC_MI_DATAMODE_RAW14: + mi_set_slice(&format, fmt_bit[id].raw_bit, 3); + miv2_ctrl |= path_list[id].raw_enable_bit; + + mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + break; + case IC_MI_DATAMODE_RAW16: +#ifdef ISP_MI_HDR + if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) { + mi_set_slice(&format, fmt_bit[id].raw_bit, 1); + path_ctrl |= path_list[id].raw_enable_bit; + //mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + } +#endif + if (id <= ISP_MI_PATH_PP) { + mi_set_slice(&format, fmt_bit[id].raw_bit, 4); + miv2_ctrl |= path_list[id].raw_enable_bit; + mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + } + break; + case IC_MI_DATAMODE_RGB888: + mi_set_slice(&format, fmt_bit[id].yuv_fmt, 2); + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_OUTPUT, 6); + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_INPUT, 2); + miv2_ctrl |= path_list[id].ycbcr_enable_bit; + break; + default: + pr_err("mi %s unsupport format: %d", __func__, path->out_mode); + return; + } + + switch (path->data_layout) { + case IC_MI_DATASTORAGE_PLANAR: + mi_set_slice(&format, fmt_bit[id].yuv_str, 2); + break; + case IC_MI_DATASTORAGE_SEMIPLANAR: + mi_set_slice(&format, fmt_bit[id].yuv_str, 0); + break; + case IC_MI_DATASTORAGE_INTERLEAVED: + mi_set_slice(&format, fmt_bit[id].yuv_str, 1); + break; + default: + break; + } + + mi_set_slice(&format, fmt_bit[id].yuv_bit, path->yuv_bit); + if(path->yuv_bit){ + if(path->data_alignMode){ + mi_set_slice(&format, fmt_bit[id].yuv_aligned, 1); + }else{ + mi_set_slice(&format, fmt_bit[id].yuv_aligned, 0); + } + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_10_ENABLE, 1); + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_10_METHOD, 0); + } + + mi_set_slice(&format, fmt_bit[id].raw_aligned, path->data_alignMode); + if (id == ISP_MI_PATH_MP) { + REG_SET_SLICE(bus_cfg, MP_WR_BURST_LEN, dev->mi.burst_len); + } else if (id == ISP_MI_PATH_SP) { + REG_SET_SLICE(bus_cfg, SP1_WR_BURST_LEN, dev->mi.burst_len); + } else if (id == ISP_MI_PATH_SP2_BP) { + REG_SET_SLICE(bus_cfg, SP2_WR_BURST_LEN, dev->mi.burst_len); + } + REG_SET_SLICE(mcm_bus_cfg, MCM_WR_BURST_LEN, dev->mi.burst_len); + + if(path->yuv_bit){// + if(path->data_alignMode){//aligned mode + lval = (path->out_width + 12 - 1)/12; + //printf("zw debug lval = 0x%x\n",lval); + }else{ //unaligned mode + lval = (path->out_width * 10 + 127)/128; + } + y_llength =lval<<4; + //printf("zw debug y_llength = 0x%x\n",y_llength); + }else{ //8bit output + y_llength = ALIGN_16BYTE(path->out_width); + } + + y_length_addr = path_list[id].y_length_addr; + if (y_length_addr) { + isp_write_reg(dev, y_length_addr, y_llength); + isp_write_reg(dev, y_length_addr + 4, path->out_width); + isp_write_reg(dev, y_length_addr + 8, path->out_height); + isp_write_reg(dev, y_length_addr + 12, + y_llength * path->out_height); + } + // aev2, 3dnr + if (id == ISP_MI_PATH_MP) { + if (dev->exp2.enable) { + REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1); +#ifdef ISP_AEV2_V2 + REG_SET_SLICE(format, MP_WR_JDP_DP_BIT, 1); +#endif + } else { + REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 0); + } + } + + if ((id == ISP_MI_PATH_MP && (miv2_ctrl & MP_RAW_PATH_ENABLE_MASK)) || + (id == ISP_MI_PATH_SP2_BP && (miv2_ctrl & SP2_RAW_PATH_ENABLE_MASK)) +#ifdef ISP_MI_MCM_WR + || (id == ISP_MI_MCM_WR0 && (miv2_ctrl & MCM_RAW0_PATH_ENABLE_MASK)) || + (id == ISP_MI_MCM_WR1 && (miv2_ctrl & MCM_RAW1_PATH_ENABLE_MASK)) +#endif +#ifdef ISP_MI_PP_WRITE + || (id == ISP_MI_PATH_PP && ((path->out_mode == IC_MI_DATAMODE_RAW8) || + (path->out_mode == IC_MI_DATAMODE_RAW10) || (path->out_mode == IC_MI_DATAMODE_RAW12) || + (path->out_mode == IC_MI_DATAMODE_RAW14) || (path->out_mode == IC_MI_DATAMODE_RAW16))) +#endif +#ifdef ISP_MI_HDR + || (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) +#endif + ) { + lval = + calc_raw_lval(path->out_width, path->out_mode, + path->data_alignMode); + y_llength = lval <<4; + isp_write_reg(dev, path_list[id].raw_llength_addr, y_llength); + isp_write_reg(dev, path_list[id].raw_pic_width_addr, path->out_width); + isp_write_reg(dev, path_list[id].raw_pic_height_addr, path->out_height); + isp_write_reg(dev, path_list[id].raw_pic_size_addr, path->out_height * y_llength ); +#ifdef ISP_MI_MCM_WR + if (id == ISP_MI_MCM_WR0 || id == ISP_MI_MCM_WR1) { + isp_write_reg(dev, REG_ADDR(miv2_mcm_raw0_lval_bytes), y_llength); + } +#endif +#ifdef ISP_MI_PP_WRITE + //ppw line entry mode, llength need to align with 256. + //llength is line length, lval is line availble data. +#if 1/*should check by VV, if align with 256 is needed*/ + uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num)); + /*TODO shenweiyi to enable */ + // if (line_num != 0) { + // y_llength = y_llength & 0xff ? (y_llength & 0xffffff00 + 0x100):y_llength; + // } + pr_info("%s:line_num = %d y_llength = 0x%x\n", __func__, line_num, y_llength); + isp_write_reg(dev, REG_ADDR(isp_mi_pp_y_llength), y_llength); + isp_write_reg(dev, path_list[id].raw_pic_size_addr, path->out_height * y_llength ); +#else + if (id == ISP_MI_PATH_PP) { + uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num)); + if (line_num != 0) { + y_llength = (y_llength & 0xff) ? ((y_llength + 0xff) &(~0xff)):y_llength; + } + isp_write_reg(dev, REG_ADDR(isp_mi_pp_y_llength), y_llength); + isp_write_reg(dev, path_list[id].raw_pic_size_addr, path->out_height * y_llength ); + } +#endif +#endif +#if defined(ISP_MI_HDR) + if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) + isp_write_reg(dev, path_list[id].raw_llength_addr+4, y_llength); +#endif + } + +#ifdef ISP_MI_HDR + if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) { + REG_SET_SLICE(path_ctrl, HDR_MI_CFG_UPD, 1); + REG_SET_SLICE(path_ctrl, HDR_AUTO_UPDATE, 1); + path_ctrl |= (HDR_INIT_OFFSET_EN_MASK | HDR_INIT_BASE_EN_MASK); + } +#endif + if (id <= ISP_MI_PATH_PP) { + REG_SET_SLICE(path_ctrl, MP_MI_CFG_UPD, 1); + REG_SET_SLICE(path_ctrl, MP_AUTO_UPDATE, 1); + //path_ctrl |= 0x05; + path_ctrl |= (MP_INIT_BASE_EN_MASK | MP_INIT_OFFSET_EN_MASK); + } +#ifdef ISP_MI_MCM_WR + if (id <= ISP_MI_MCM_WR1 && id >= ISP_MI_MCM_WR0) { + REG_SET_SLICE(path_ctrl, MCM_WR_CFG_UPD, 1); + REG_SET_SLICE(path_ctrl, MCM_WR_AUTO_UPDATE, 1); + //path_ctrl |= 0x05; + path_ctrl |= (MCM_INIT_BASE_EN_MASK | MCM_INIT_OFFSET_EN_MASK); + } +#endif + + pr_info("%s:path_ctrl 0x%08x\n", __func__, path_ctrl); + acq_proc = isp_read_reg(dev, REG_ADDR(isp_acq_prop)); + isp_write_reg(dev, REG_ADDR(isp_acq_prop), + acq_proc & ~MRV_ISP_LATENCY_FIFO_SELECTION_MASK); + + bus_id = isp_read_reg(dev, path_list[id].bus_id_addr); + if (id == ISP_MI_PATH_SP) { + bus_id <<= 4; + } + bus_id |= MP_WR_ID_EN_MASK; + if (id == ISP_MI_PATH_SP2_BP) { + bus_id |= SP2_BUS_SW_EN_MASK; + // REG_SET_SLICE(bus_cfg, SP2_WR_SWAP_Y, 1); +#ifdef ISP_MI_HDR + } else if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS ) { + bus_id |= HDR_BUS_SW_EN_MASK; +#endif + } else { + bus_id |= MP_BUS_SW_EN_MASK; + } + if (path_list[id].bus_id_addr) + isp_write_reg(dev, path_list[id].bus_id_addr, bus_id); + + if (path_list[id].bus_cfg_addr) + isp_write_reg(dev, path_list[id].bus_cfg_addr, bus_cfg); + + isp_write_reg(dev, REG_ADDR(miv2_mcm_bus_cfg), mcm_bus_cfg); +#ifdef ISP_MI_PP_WRITE + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + if (id == ISP_MI_PATH_PP && ((path->out_mode == IC_MI_DATAMODE_RAW8) || + (path->out_mode == IC_MI_DATAMODE_RAW10) || (path->out_mode == IC_MI_DATAMODE_RAW12) || + (path->out_mode == IC_MI_DATAMODE_RAW14) || (path->out_mode == IC_MI_DATAMODE_RAW16))) { //pp path output raw + format |= PP_WR_RAW_SEL_MASK; + REG_SET_SLICE(format, PP_WR_RAW_SEL, 1); + REG_SET_SLICE(isp_ctrl, PP_WRITE_SEL, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + } else { + REG_SET_SLICE(format, PP_WR_RAW_SEL, 0); + REG_SET_SLICE(isp_ctrl, PP_WRITE_SEL, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } +#endif + isp_write_reg(dev, path_list[id].format_addr, format); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + isp_write_reg(dev, path_list[id].path_ctrl_addr, path_ctrl); + + /*config qos for isp*/ + set_qos(dev); + + if (path_list[id].format_conv_ctrl) + isp_write_reg(dev, path_list[id].format_conv_ctrl, conv_format_ctrl); + +} + +int isp_mi_start(struct isp_ic_dev *dev) +{ + int i; + struct isp_mi_context mi = *(&dev->mi); + u32 imsc, miv2_mcm_bus_id; + pr_info("enter %s\n", __func__); + + miv2_mcm_bus_id = isp_read_reg(dev, REG_ADDR(miv2_mcm_bus_id)); + miv2_mcm_bus_id |= MCM_BUS_SW_EN_MASK; + isp_write_reg(dev, REG_ADDR(miv2_mcm_bus_id), miv2_mcm_bus_id); + + for (i = 0; i < ISP_MI_PATH_ID_MAX; i++) { + set_data_path(i, &mi.path[i], dev); + } + uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num)); + + imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc)); + if (line_num == 0) { + isp_write_reg(dev, REG_ADDR(miv2_imsc), + imsc | (MP_YCBCR_FRAME_END_MASK | MP_RAW_FRAME_END_MASK | + WRAP_MP_Y_MASK | WRAP_MP_CB_MASK | WRAP_MP_CR_MASK | + WRAP_MP_RAW_MASK | WRAP_MP_JDP_MASK | MCM_RAW0_FRAME_END_MASK | + SP1_YCBCR_FRAME_END_MASK | WRAP_SP1_Y_MASK |MCM_RAW1_FRAME_END_MASK| + WRAP_SP1_CB_MASK | WRAP_SP1_CR_MASK | + SP2_YCBCR_FRAME_END_MASK | WRAP_SP2_Y_MASK | + WRAP_SP2_CB_MASK | WRAP_SP2_CR_MASK | + SP2_RAW_FRAME_END_MASK | MP_JDP_FRAME_END_MASK)); + } else { + isp_write_reg(dev, REG_ADDR(miv2_imsc), + imsc | (MP_YCBCR_FRAME_END_MASK | MP_RAW_FRAME_END_MASK | + WRAP_MP_Y_MASK | WRAP_MP_CB_MASK | WRAP_MP_CR_MASK | + WRAP_MP_RAW_MASK | WRAP_MP_JDP_MASK | MCM_RAW0_FRAME_END_MASK | + MCM_RAW1_FRAME_END_MASK| + SP2_YCBCR_FRAME_END_MASK | WRAP_SP2_Y_MASK | + WRAP_SP2_CB_MASK | WRAP_SP2_CR_MASK | + SP2_RAW_FRAME_END_MASK | MP_JDP_FRAME_END_MASK)); + } + + + //isp_write_reg(dev, REG_ADDR(miv2_imsc1), 0x7ffffff); + isp_write_reg(dev, REG_ADDR(miv2_imsc1), 0); +#ifdef ISP_MI_PP_WRITE + imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc2)); + if (line_num == 0) { + isp_write_reg(dev, REG_ADDR(miv2_imsc2), + imsc | ( PPW_U_BUF_FULL_MASK | PPW_Y_BUF_FULL_MASK | + PPW_V_BUF_FULL_MASK | PPR_Y_BUF_FULL_MASK | SP2_RAW2_W_BUF_FULL_MASK | + SP2_RAW2_R_BUF_FULL_MASK | HDR_W_BUF_FULL_MASK | HDR_R_BUF_FULL_MASK | + WRAP_SP2_RAW_MASK | WRAP_PPW_CR_MASK | WRAP_PPW_CB_MASK | //WRAP_PPW_Y_MASK | + SP2_RAW2_FRAME_END_MASK | PPW_FRAME_END_MASK | HDR_VS_DMA_READY_MASK | + HDR_S_DMA_READY_MASK | HDR_L_DMA_READY_MASK | HDR_L_DMA_READY_MASK | + WRAP_HDR_VS_MASK | WRAP_HDR_S_MASK | WRAP_HDR_L_MASK | HDR_VS_FRAME_END_MASK | + HDR_S_FRAME_END_MASK | HDR_L_FRAME_END_MASK | MI_RT_BUS_BUSERR_MASK | + MI_RT_BUS_TIMEO_MASK)); + } else { + isp_write_reg(dev, REG_ADDR(miv2_imsc2), + imsc | (SP2_RAW2_W_BUF_FULL_MASK | + SP2_RAW2_R_BUF_FULL_MASK | HDR_W_BUF_FULL_MASK | HDR_R_BUF_FULL_MASK | + WRAP_SP2_RAW_MASK |PPW_FRAME_END_MASK| + SP2_RAW2_FRAME_END_MASK | HDR_VS_DMA_READY_MASK | + HDR_S_DMA_READY_MASK | HDR_L_DMA_READY_MASK | HDR_L_DMA_READY_MASK | + WRAP_HDR_VS_MASK | WRAP_HDR_S_MASK | WRAP_HDR_L_MASK | HDR_VS_FRAME_END_MASK | + HDR_S_FRAME_END_MASK | HDR_L_FRAME_END_MASK | MI_RT_BUS_BUSERR_MASK | + MI_RT_BUS_TIMEO_MASK)); + } +#endif + isp_write_reg(dev, REG_ADDR(miv2_imsc3), 0x3f); + return 0; +} + +int isp_mi_stop(struct isp_ic_dev *dev) +{ + pr_info("enter %s\n", __func__); +#ifdef ISP_MI_PP_WRITE + isp_write_reg(dev, REG_ADDR(miv2_imsc2), 0); +#endif + isp_write_reg(dev, REG_ADDR(miv2_imsc3), 0); + isp_write_reg(dev, REG_ADDR(miv2_imsc), 0); + isp_write_reg(dev, REG_ADDR(miv2_imsc1), 0); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), 0UL); + return 0; +} + +u32 isp_read_mi_irq(struct isp_ic_dev *dev) +{ + return isp_read_reg(dev, REG_ADDR(miv2_mis)); +} + +void isp_reset_mi_irq(struct isp_ic_dev *dev, u32 icr) +{ + isp_write_reg(dev, REG_ADDR(miv2_icr), icr); +} + +int isp_set_bp_buffer(struct isp_ic_dev *dev, struct isp_bp_buffer_context *buf) +{ + return 0; +} +#ifdef ISP_MI_PP_WRITE + +int isp_set_ppw_line_num(struct isp_ic_dev *dev) +{ + if (dev == NULL) { + pr_err("Wrong input %s\n", __func__); + return -1; + } + pr_info("enter %s\n", __func__); + + isp_write_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num), dev->pp_write.entry_line_num); + pr_info("exit %s\n", __func__); + return 0; +} +int isp_get_ppw_pic_cnt(struct isp_ic_dev *dev, u16* pic_cnt) +{ + + if (dev == NULL) { + pr_err("Wrong input %s\n", __func__); + return -1; + } + pr_info("enter %s\n", __func__); + *pic_cnt = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_pic_cnt)); + pr_info("exit %s\n", __func__); + return 0; +} +#endif + +#ifdef ISP_MI_PP_READ + +int isp_cfg_pp_dma_line_entry(struct isp_ic_dev *dev) +{ + pp_dma_line_entry_t* pp_dam_line_entry = &dev->pp_dma_line_entry; + if (dev == NULL) { + pr_err("Wrong input %s\n", __func__); + return -1; + } + pr_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(mi_pp_dma_y_entry_line_num), pp_dam_line_entry->entry_line_num); + isp_write_reg(dev, REG_ADDR(mi_pp_dma_y_buf_line_num), pp_dam_line_entry->buf_line_num); + pr_info("exit %s\n", __func__); + return 0; +} +#endif +#endif diff --git a/vvcam/isp/isp_rgbgamma.c b/vvcam/isp/isp_rgbgamma.c new file mode 100755 index 0000000..1343770 --- /dev/null +++ b/vvcam/isp/isp_rgbgamma.c @@ -0,0 +1,216 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#else +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; + +int isp_enable_rgbgamma(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBGC + pr_err("unsupported function %s\n", __func__); + return -1; +#else + + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + REG_SET_SLICE(isp_ctrl, ISP_RGBGC_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + dev->rgbgamma.enable = true; + return 0; +#endif +} + +int isp_disable_rgbgamma(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBGC + pr_err("unsupported function %s\n", __func__); + return -1; +#else + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + REG_SET_SLICE(isp_ctrl, ISP_RGBGC_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + dev->rgbgamma.enable = false; + return 0; +#endif +} + +#ifdef ISP_RGBGC +static int isp_s_rgbgammapx(struct isp_ic_dev *dev, struct isp_rgbgamma_data *data) +{ + + u32 isp_gc_px_reg = REG_ADDR(isp_gcrgb_r_px_0); + u32 *p_table = NULL; + int i; + u32 gc_px_data = 0; + + p_table = (u32 *)&data->rgbgc_r_px; + for (i = 0; i < 64; i++) { + gc_px_data |= (*(p_table + i) << (i % 6 * 5)); + if (i % 6 == 5 || i == 63) { + isp_write_reg(dev, isp_gc_px_reg, gc_px_data); + isp_gc_px_reg += 4; + gc_px_data = 0; + } + } + + isp_gc_px_reg = REG_ADDR(isp_gcrgb_g_px_0); + p_table = (u32 *)&data->rgbgc_g_px; + for (i = 0; i < 64; i++) { + gc_px_data |= (*(p_table + i) << (i % 6 * 5)); + if (i % 6 == 5 || i == 63) { + isp_write_reg(dev, isp_gc_px_reg, gc_px_data); + isp_gc_px_reg += 4; + gc_px_data = 0; + } + } + isp_gc_px_reg = REG_ADDR(isp_gcrgb_b_px_0); + p_table = (u32 *)&data->rgbgc_b_px; + for (i = 0; i < 64; i++) { + gc_px_data |= (*(p_table + i) << (i % 6 * 5)); + if (i % 6 == 5 || i == 63) { + isp_write_reg(dev, isp_gc_px_reg, gc_px_data); + isp_gc_px_reg += 4; + gc_px_data = 0; + } + } + return 0; +} +#endif + +#ifdef ISP_RGBGC +static int isp_s_rgbgammaWriteData(struct isp_ic_dev *dev, + struct isp_rgbgamma_data *data) +{ + u32 isp_gc_y_data, isp_gc_x_data; + int i; + u32 *tblX, *tblY; + + isp_write_reg(dev, REG_ADDR(isp_gcrgb_r_x_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_r_y_addr), 0); + + isp_write_reg(dev, REG_ADDR(isp_gcrgb_g_x_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_g_y_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_b_x_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_b_y_addr), 0); + + tblX = data->rgbgc_r_datax; + tblY = data->rgbgc_r_datay; + for (i = 0; i < 64; i++) { + isp_gc_y_data = *(tblY + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_r_y_write_data), + isp_gc_y_data); + } + for (i = 0; i < 63; i++) { + isp_gc_x_data = *(tblX + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_r_x_write_data), + isp_gc_x_data); + } + + tblX = data->rgbgc_g_datax; + tblY = data->rgbgc_g_datay; + for (i = 0; i < 64; i++) { + isp_gc_y_data = *(tblY + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_g_y_write_data), + isp_gc_y_data); + } + for (i = 0; i < 63; i++) { + isp_gc_x_data = *(tblX + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_g_x_write_data), + isp_gc_x_data); + } + tblX = data->rgbgc_b_datax; + tblY = data->rgbgc_b_datay; + for (i = 0; i < 64; i++) { + isp_gc_y_data = *(tblY + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_b_y_write_data), + isp_gc_y_data); + } + for (i = 0; i < 63; i++) { + isp_gc_x_data = *(tblX + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_b_x_write_data), + isp_gc_x_data); + } + return 0; +} +#endif + +int isp_s_rgbgamma(struct isp_ic_dev *dev, struct isp_rgbgamma_data *data) +{ +#ifndef ISP_RGBGC + pr_err("unsupported function %s", __func__); + return -1; +#else + u8 ret; + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + REG_SET_SLICE(isp_ctrl, ISP_RGBGC_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + isp_s_rgbgammapx(dev, data); + isp_s_rgbgammaWriteData(dev, data); + ret = 0; + if (dev->rgbgamma.enable) { + ret = isp_enable_rgbgamma(dev); + } + return ret; +#endif +} diff --git a/vvcam/isp/isp_rgbir.c b/vvcam/isp/isp_rgbir.c new file mode 100755 index 0000000..3d9500f --- /dev/null +++ b/vvcam/isp/isp_rgbir.c @@ -0,0 +1,401 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; +enum { + ISP_RGBIR_OUT_BAT_RGGB = 0, + ISP_RGBIR_OUT_BAT_GRBG, + ISP_RGBIR_OUT_BAT_GBRG, + ISP_RGBIR_OUT_BAT_BGGR +}; + +enum { + ISP_RGBIR_BAT_BGGIR = 0, + ISP_RGBIR_BAT_GRIRG, + ISP_RGBIR_BAT_RGGIR, + ISP_RGBIR_BAT_GBIRG, + ISP_RGBIR_BAT_GIRRG, + ISP_RGBIR_BAT_IRGGB, + ISP_RGBIR_BAT_GIRBG, + ISP_RGBIR_BAT_IRGGR, + ISP_RGBIR_BAT_RGIRB, + ISP_RGBIR_BAT_GRBIR, + ISP_RGBIR_BAT_IRBRG, + ISP_RGBIR_BAT_BIRGR, + ISP_RGBIR_BAT_BGIRR, + ISP_RGBIR_BAT_GBRIR, + ISP_RGBIR_BAT_IRRBG, + ISP_RGBIR_BAT_RIRGB, +}; + +int isp_rgbir_s_bls(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_context rgbir = *(&dev->rgbir); + struct isp_rgbir_bls_context* bls = &rgbir.bls; + isp_info("enter %s\n", __func__); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_a), bls->a); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_b), bls->b); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_c), bls->c); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_d), bls->d); + return 0; +#endif +} + +int isp_rgbir_s_gain(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR + isp_err("unsupported function %s", __func__); + return -1; +#else + + struct isp_rgbir_context rgbir = *(&dev->rgbir); + struct isp_rgbir_rgb_gain_context* rgb_gain = &rgbir.rgb_gain; + isp_info("enter %s\n", __func__); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_gain_r), rgb_gain->r); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_gain_g), rgb_gain->g); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_gain_b), rgb_gain->b); + + return 0; +#endif +} + +int isp_rgbir_s_dpcc(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_dpcc_context *dpcc = &dev->rgbir.dpcc; + int i; + u32 isp_pre_filt_dpc_th_r; + + isp_info("enter %s\n", __func__); + + for (i = 0; i < 4; i++) { + isp_pre_filt_dpc_th_r = isp_read_reg(dev, REG_ADDR(isp_pre_filt_dpc_th_r) + i * ISP_REG_GAP); + REG_SET_SLICE(isp_pre_filt_dpc_th_r, ISP_PRE_FILT_DPC_TH_MED_R, dpcc->median_thr[i]); + REG_SET_SLICE(isp_pre_filt_dpc_th_r, ISP_PRE_FILT_DPC_TH_AVG_R, dpcc->avg_thr[i]); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_dpc_th_r) + i * ISP_REG_GAP, isp_pre_filt_dpc_th_r); + + } + return 0; +#endif +} + +int isp_rgbir_s_cc_matrix(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_cc_context *cc = &dev->rgbir.cc; //cc color correct + int i; + const u8 reg_gap = 8; + u32 isp_pre_filt_cc_00_01; + isp_info("enter %s\n", __func__); + + for (i = 0; i < 3; i++) { + + isp_pre_filt_cc_00_01 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + i * reg_gap); + REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_00, (u32)(cc->mtx[i][0] )); + REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_01, (u32)(cc->mtx[i][1] )); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + i * reg_gap, isp_pre_filt_cc_00_01); + + isp_pre_filt_cc_00_01 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + i * reg_gap + ISP_REG_GAP); + REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_02, (u32)(cc->mtx[i][2] )); + REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_03, (u32)(cc->mtx[i][3] )); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + (i * reg_gap) + ISP_REG_GAP, isp_pre_filt_cc_00_01); + } + return 0; +#endif +} + +int isp_rgbir_s_des(struct isp_ic_dev *dev) //de-saturation +{ +#ifndef ISP_RGBIR + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_des_context *des = &dev->rgbir.des; //cc color correct + int i; + u32 isp_pre_filt_ir_des_pd1; // isp_pre_filt_ir_des_px1, isp_pre_filt_ir_des_py1; + u32 isp_pre_filt_l_des_pd1; // isp_pre_filt_l_des_px1, isp_pre_filt_l_des_py1; + + isp_info("enter %s\n", __func__); + //register value + for (i = 0 ; i < 4; i++) { + isp_pre_filt_ir_des_pd1 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ir_des_pd1) + i * ISP_REG_GAP); + if (i != 3) { + isp_pre_filt_ir_des_pd1 = des->ir_pd[i *4] | des->ir_pd[i *4 + 1] << 8 | des->ir_pd[i * 4 + 2] << 16 |\ + des->ir_pd[i*4 + 3] << 24; + } else { + isp_pre_filt_ir_des_pd1 = des->ir_pd[i *4] | des->ir_pd[i *4 + 1] << 8 | des->ir_pd[i*4 + 2] << 16; + } + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_des_pd1) + i * ISP_REG_GAP, isp_pre_filt_ir_des_pd1); + } + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_des_px1), (des->ir_px1 & 0xffff)); + for (i = 0; i < 8; i++) + { + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_des_py1) + i * ISP_REG_GAP, des->ir_py[i]); + } + + for (i = 0 ; i < 4; i++) { + isp_pre_filt_l_des_pd1 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_l_des_pd1) + i * ISP_REG_GAP); + if (i != 3) { + isp_pre_filt_l_des_pd1 = des->l_pd[i *4] | des->l_pd[i*4 + 1] << 8 | des->l_pd[i*4 + 2] << 16 |\ + des->l_pd[i*4 + 3] << 24; + } else { + isp_pre_filt_l_des_pd1 = des->l_pd[i *4] | des->l_pd[i*4 + 1] << 8 | des->l_pd[i*4+2] << 16; + } + isp_write_reg(dev, REG_ADDR(isp_pre_filt_l_des_pd1) + i * ISP_REG_GAP, isp_pre_filt_l_des_pd1); + } + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_l_des_px1), (des->l_px1 & 0xffff)); + for ( i = 0; i < 8; i++) + { + isp_write_reg(dev, REG_ADDR(isp_pre_filt_l_des_py1) + i * 4, des->l_py[i]); + } + return 0; +#endif +} + +int isp_rgbir_s_sharpen(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_sharpen_context *sharpen = &dev->rgbir.sharpen; + u8 sharpl = sharpen->sharpen_lvl; + u32 isp_pre_filt_lum_weight; // isp_pre_filt_thresh_sh0, isp_pre_filt_thresh_sh1; + // u32 isp_pre_filt_thresh_bl0, isp_pre_filt_thresh_bl1; + // u32 isp_pre_filt_fac_sh0, isp_pre_filt_fac_sh1, isp_pre_filt_fac_mid; + // u32 isp_pre_filt_fac_bl0, isp_pre_filt_fac_bl1; + const unsigned int sharplevel[5][11] = { + { 0x4, 0x08, 0x0C, 0x10, 0x16, 0x1B, 0x20, 0x26, 0x2C, 0x30, 0x3F }, + { 0x4, 0x07, 0x0A, 0x0C, 0x10, 0x14, 0x1A, 0x1E, 0x24, 0x2A, 0x30 }, + { 0x4, 0x06, 0x08, 0x0A, 0x0C, 0x10, 0x13, 0x17, 0x1D, 0x22, 0x28 }, + { 0x2, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x10, 0x15, 0x1A, 0x24 }, + { 0x0, 0x00, 0x00, 0x02, 0x04, 0x04, 0x06, 0x08, 0x0D, 0x14, 0x20 } }; + + isp_info("enter %s\n", __func__); + + + //filter factor sharp + isp_pre_filt_lum_weight = isp_read_reg(dev, REG_ADDR(isp_pre_filt_lum_weight)); + + REG_SET_SLICE(isp_pre_filt_lum_weight, LUM_WEIGHT_GAIN, sharpen->lum_weight_gain); + REG_SET_SLICE(isp_pre_filt_lum_weight, LUM_WEIGHT_KINK, sharpen->lum_weight_kink); + REG_SET_SLICE(isp_pre_filt_lum_weight, LUM_WEIGHT_MIN, sharpen->lum_weight_min); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_lum_weight), isp_pre_filt_lum_weight); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_mid), sharpen->middle); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_sh0), sharpen->thresh_sh0); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_sh1), sharpen->thresh_sh1); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_bl0), sharpen->thresh_bl0); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_bl1), sharpen->thresh_bl1); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_sh1), (unsigned int)(sharplevel[0][sharpl])); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_sh0), (unsigned int)(sharplevel[1][sharpl])); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_mid), (unsigned int)(sharplevel[2][sharpl])); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_bl0), (unsigned int)(sharplevel[3][sharpl])); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_bl1), (unsigned int)(sharplevel[4][sharpl])); + return 0; +#endif +} + +int isp_rgbir_s_ir_dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_ir_dnr_context* ir_dnr = &dev->rgbir.ir_dnr; + //u16 imgwidth, imgheight; + u32 ir_denoise_reg_03; + u32 ir_denoise_reg_45; + + ir_denoise_reg_03 = (ir_dnr->winweight[0] | (ir_dnr->winweight[1] << 8) | (ir_dnr->winweight[2] << 16) | (ir_dnr->winweight[3] << 24)); + ir_denoise_reg_45 = (ir_dnr->winweight[4] | (ir_dnr->winweight[5] << 8)); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_denoise_sw_03), (unsigned int)(ir_denoise_reg_03)); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_denoise_sw_45), ((unsigned int)(ir_denoise_reg_45) & 0xffff)); + + //imgwidth = isp_read_reg(dev, REG_ADDR(isp_out_h_size)); + //imgheight = isp_read_reg(dev, REG_ADDR(isp_out_v_size)); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_h_size), ir_dnr->width& 0x7fff); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_v_size), ir_dnr->height & 0x3fff); + return 0; +#endif +} + +int isp_rgbir_hw_init(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR + isp_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_pre_filt_ctrl; + struct isp_rgbir_context *rgbir = &dev->rgbir; + isp_info("enter %s\n", __func__); + + isp_rgbir_s_cc_matrix(dev); + isp_rgbir_s_bls(dev); + isp_rgbir_s_dpcc(dev); + isp_rgbir_s_des(dev); + isp_rgbir_s_gain(dev); + isp_rgbir_s_ir_dnr(dev); + isp_rgbir_s_sharpen(dev); + + isp_pre_filt_ctrl = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl));//pre filt ctrl + REG_SET_SLICE(isp_pre_filt_ctrl , ISP_PRE_FILT_ENABLE, rgbir->prefilt_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_MODE, rgbir->green_filt_mode); + REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_ENABLE, rgbir->green_filt_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , RGBIR_BAYER_PATTERN, rgbir->rgbirPattern ); + REG_SET_SLICE(isp_pre_filt_ctrl , OUT_RGB_BAYER_PATTERN, rgbir->out_rgb_pattern); + REG_SET_SLICE(isp_pre_filt_ctrl , STAGE1_SELECT, rgbir->green_filt_stage1_select); + REG_SET_SLICE(isp_pre_filt_ctrl , DEMOSAIC_THRESHOLD, rgbir->demosaic_threshold); + REG_SET_SLICE(isp_pre_filt_ctrl , PART_ONE_ENABLE, rgbir->part1_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , PART_TWO_ENABLE,rgbir->part2_enable); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ctrl), (unsigned int)(isp_pre_filt_ctrl));//pre filt ctrl + return 0; +#endif +} + +int isp_enable_rgbir(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_context *rgbir = &dev->rgbir; + u32 isp_pre_filt_ctrl; + isp_info("enter %s\n", __func__); + + isp_pre_filt_ctrl = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl));//pre filt ctrl + REG_SET_SLICE(isp_pre_filt_ctrl , ISP_PRE_FILT_ENABLE, rgbir->prefilt_enable); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ctrl), isp_pre_filt_ctrl);//pre filt ctrl + return 0; +#endif +} + +int isp_rgbir_out_ir_raw(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_context *rgbir = &dev->rgbir; + u32 isp_ctrl; + isp_info("enter %s\n", __func__); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));//isp ctrl + REG_SET_SLICE(isp_ctrl , ISP_IR_RAW_OUT, rgbir->enable_ir_raw_out); + REG_SET_SLICE(isp_ctrl , MRV_ISP_ISP_MODE, MRV_ISP_ISP_MODE_RGB); //there need to config rgb mode. + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);//isp_ctrl + return 0; +#endif +} + +int isp_s_rgbir(struct isp_ic_dev *dev) +{ + +#ifndef ISP_WDR_V4 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_rgbir_context *rgbir = &dev->rgbir; + u32 isp_pre_filt_ctrl; + isp_info("enter %s\n", __func__); + isp_rgbir_s_cc_matrix(dev); + isp_rgbir_s_bls(dev); + isp_rgbir_s_dpcc(dev); + isp_rgbir_s_des(dev); + isp_rgbir_s_gain(dev); + isp_rgbir_s_ir_dnr(dev); + isp_rgbir_s_sharpen(dev); + + isp_pre_filt_ctrl = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl));//pre filt ctrl + REG_SET_SLICE(isp_pre_filt_ctrl , ISP_PRE_FILT_ENABLE, rgbir->prefilt_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_MODE, rgbir->green_filt_mode); + REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_ENABLE, rgbir->green_filt_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , RGBIR_BAYER_PATTERN, rgbir->rgbirPattern ); + REG_SET_SLICE(isp_pre_filt_ctrl , OUT_RGB_BAYER_PATTERN, rgbir->out_rgb_pattern); + REG_SET_SLICE(isp_pre_filt_ctrl , STAGE1_SELECT, rgbir->green_filt_stage1_select); + REG_SET_SLICE(isp_pre_filt_ctrl , DEMOSAIC_THRESHOLD, rgbir->demosaic_threshold); + REG_SET_SLICE(isp_pre_filt_ctrl , PART_ONE_ENABLE, rgbir->part1_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , PART_TWO_ENABLE,rgbir->part2_enable); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ctrl), (unsigned int)(isp_pre_filt_ctrl));//pre filt ctrl + return 0; +#endif +} + + diff --git a/vvcam/isp/isp_tdnr3.c b/vvcam/isp/isp_tdnr3.c new file mode 100755 index 0000000..75f8f15 --- /dev/null +++ b/vvcam/isp/isp_tdnr3.c @@ -0,0 +1,646 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "isp_ioctl.h" +#include "mrv_all_bits.h" + +#include "isp_types.h" +#ifdef ISP_3DNR_V3 +extern MrvAllRegister_t *all_regs; + +int isp_tdnr_cfg_gamma(struct isp_ic_dev *dev) +{ + //write to regs + struct isp_tdnr_context *tdnr = &dev->tdnr; + u32 regVal; + u8 bit_width; + u8 i; + u16 val_a, val_b; + + //const u8 tdnrRegGap = 8; + bit_width = 12; + + //pr_info("enter %s\n", __func__); + + for (i = 0; i < DENOISE3D_GAMMA_BIN - 3; i += 5) + { + val_a = tdnr->curve.preGamma_y[i + 2] >> 6; val_b = tdnr->curve.preGamma_y[i + 2] & 0x3f; + regVal = (val_a << 24) | ((tdnr->curve.preGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.preGamma_y[i] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_0) + (i / 5) *8 , regVal); + + regVal = (val_b << 24) | ((tdnr->curve.preGamma_y[i + 4] & 0xfff) << bit_width) | (tdnr->curve.preGamma_y[i + 3] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_1) + (i / 5 ) *8, regVal); + } + + val_a = tdnr->curve.preGamma_y[i + 2] >> 6; val_b = tdnr->curve.preGamma_y[i + 2] & 0x3f; + regVal = (val_a << 24) | ((tdnr->curve.preGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.preGamma_y[i] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_12), regVal); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_13), val_b); + + + i = 0; + for (i = 0; i < DENOISE3D_GAMMA_BIN - 3; i += 5) + { + val_a = tdnr->curve.invGamma_y[i + 2] >> 6; val_b = tdnr->curve.invGamma_y[i + 2] & 0x3f; + regVal = (val_a << 24) | ((tdnr->curve.invGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.invGamma_y[i] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_0) + (i / 5) *8 , regVal); + + regVal = (val_b << 24) | ((tdnr->curve.invGamma_y[i + 4] & 0xfff) << bit_width) | (tdnr->curve.invGamma_y[i + 3] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_1) + (i / 5) *8 , regVal); + } + + val_a = tdnr->curve.invGamma_y[i + 2] >> 6; val_b = tdnr->curve.invGamma_y[i + 2] & 0x3f; + regVal = (val_a << 24) | ((tdnr->curve.invGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.invGamma_y[i] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_12), regVal); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_13), val_b); + return 0; +} + +int isp_s_tdnr(struct isp_ic_dev *dev) +{ + u32 isp_denoise3d2_ctrl; + struct isp_tdnr_context *tdnr = &dev->tdnr; + u32 regVal = 0; + /* spacial */ + u32 strength = tdnr->strength; + + //pr_info("enter %s\n", __func__); + strength = MIN(MAX(strength, 0), 128); + + isp_denoise3d2_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); +#if 0 + if (!tdnr->enable) { + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), isp_denoise3d2_ctrl); + return 0; + } +#endif + +#if 1 + if (dev->tdnr.enable_tnr) { + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), strength); + } else { + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), 0); + if (dev->tdnr.frames == 2) + return 0 ; + } +#endif + //isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), strength); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_level); + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->noise_mean); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_noise), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_threshold); + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->motion_mean); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_RANGE_H, tdnr->range_h); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_RANGE_V, tdnr->range_v); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_DILATE_RANGE_H, tdnr->dilate_range_h); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_DILATE_RANGE_V, tdnr->dilate_range_v); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_range), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_INV, tdnr->motion_inv_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion_inv), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_THR_UPDATE, tdnr->update_factor); + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_THR_UPDATE, tdnr->motion_update_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_update), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_PRE_WEIGHT, tdnr->pre_motion_weight); + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_SLOPE, tdnr->motion_slope); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_tnr), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_CONV_SHIFT, tdnr->motion_converage_shift); + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_CONV_MAX, tdnr->motion_converage_max); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_VAL_SHIFT_BIT, tdnr->tnr_val_shift_bit); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT, tdnr->tnr_diff_shift_bit); + REG_SET_SLICE(regVal, DENOISE3D_V20_SAD_WEIGHT, tdnr->sad_weight); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_shift), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_VAL_SHIFT, tdnr->luma_pixel_val_shift); + REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_SLOP, tdnr->luma_pixel_slope); + REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT, tdnr->luma_pixel_slope_shift); + REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_SLOP_MIN, tdnr->luma_pixel_slope_min); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_luma), regVal); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_dummy_hblank), 0x63); + + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_INVGAMMA_EN, tdnr->enable_inv_gamma); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_PREGAMMA_EN, tdnr->enable_pre_gamma); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_ERODE_EN, tdnr->enable_motion_erosion); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_MOTION_CONV_EN, tdnr->enable_motion_converage); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_INV_DGAIN_EN, 0); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_INV_AWB_GAIN_EN, 1); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_COMP_LUMA_EN, 0); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_MOTION_DILATE_ENABLE, tdnr->enable_motion_dilation); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_NLM_ENABLE, dev->tdnr.enable_2dnr); + //REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_NLM_ENABLE, 1); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_TNR_ENABLE, dev->tdnr.enable_tnr); + + if (!dev->tdnr.enable_tnr) { + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_REF_RESET, 1); + } + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_ENABLE, 1); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), isp_denoise3d2_ctrl); + + return 0; +} + +int isp_tdnr_set_strength(struct isp_ic_dev *dev) +{ + u32 isp_denoise3d2_strength; + struct isp_tdnr_context *tdnr = &dev->tdnr; + //pr_info("enter %s\n", __func__); + + isp_denoise3d2_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_strength)); + REG_SET_SLICE(isp_denoise3d2_strength, DENOISE3D_V20_TNR_STRENGTH, tdnr->strength); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), isp_denoise3d2_strength); + + return 0; +} + +int isp_tdnr_set_motion(struct isp_ic_dev *dev) +{ + struct isp_tdnr_context *tdnr = &dev->tdnr; + u32 isp_denoise3d2_motion_inv; + pr_info("enter %s\n", __func__); + + isp_denoise3d2_motion_inv = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_motion_inv)); + REG_SET_SLICE(isp_denoise3d2_motion_inv, DENOISE3D_V20_MOTION_INV, tdnr->motion_inv_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion_inv), isp_denoise3d2_motion_inv); + + return 0; +} + +int isp_tdnr_enable(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + u32 strength = dev->tdnr.strength; + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(regVal, DENOISE3D_V20_ENABLE, 1); + // REG_SET_SLICE(regVal, DENOISE3D_V20_REF_RESET, 1); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal); + + strength = MIN(MAX(strength, 0), 128); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), strength); //clear strength + dev->tdnr.enable = true; + + return 0; +} + +int isp_tdnr_disable(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + // REG_SET_SLICE(regVal, DENOISE3D_V20_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), 0); //clear strength + dev->tdnr.enable = false; + + return 0; +} + +int isp_tdnr_enable_tdnr(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal); + + dev->tdnr.enable_tnr= true; + + return 0; +} + +int isp_tdnr_disable_tdnr(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal); + dev->tdnr.enable = false; + + return 0; +} + +int isp_tdnr_enable_2dnr(struct isp_ic_dev *dev) +{ + //u32 regVal = 0; + + pr_info("enter %s\n", __func__); + /*regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(regVal, DENOISE3D_V20_NLM_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal);*/ + + dev->tdnr.enable_tnr= true; + + return 0; +} + +int isp_tdnr_disable_2dnr(struct isp_ic_dev *dev) +{ + //u32 regVal = 0; + + pr_info("enter %s\n", __func__); + /*regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(regVal, DENOISE3D_V20_NLM_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal);*/ + dev->tdnr.enable = false; + + return 0; +} + + + +int isp_tdnr_g_stats(struct isp_ic_dev *dev, struct isp_tdnr_stats *stats) +{ + //pr_info("enter %s\n", __func__); + if (!dev || !stats) { + return -EINVAL; + } + + stats->bg_sum = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_bg_val_sum)); + stats->motion_sum = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_mo_val_sum)); + stats->bg_pixel_cnt = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_bg_cnt)); + stats->motion_pixel_cnt = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_mo_cnt)); + stats->frame_avg = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_frame_avg)); + return 0; +} + +int isp_tdnr_u_noise(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + struct isp_tdnr_context *tdnr = &dev->tdnr; + pr_info("enter %s\n", __func__); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_level); + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->noise_mean); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_noise), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_threshold); + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->motion_mean); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion), regVal); + + return 0; + +} + +int isp_tdnr_u_thr(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + struct isp_tdnr_context *tdnr = &dev->tdnr; + pr_info("enter %s\n", __func__); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_THR_UPDATE, tdnr->update_factor); + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_THR_UPDATE, tdnr->motion_update_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_update), regVal); + + return 0; + +} + +int isp_tdnr_s_buf(struct isp_ic_dev *dev) +{ + struct isp_tdnr_buffer* buf = &dev->tdnr.buf; + u32 in_width, in_height; + u32 size, lval; + u32 miv2_sp2_bus_id ; + u32 miv2_sp2_fmt; + u32 miv2_imsc2; + + u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc)); + u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl)); + u32 isp_mi_sp2_raw2_ctrl = isp_read_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl)); + pr_info("enter %s\n", __func__); + + /* + + ENABLE MIV2 SP2 RAW1 RAW2 WRITE/READ + + */ + + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW_PATH_ENABLE, 1); + miv2_ctrl |= 0x00100000; // sp2_raw2_path_enable + + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + + in_width = isp_read_reg(dev, REG_ADDR(isp_out_h_size)); + in_height = isp_read_reg(dev, REG_ADDR(isp_out_v_size)); + + lval = (in_width * 12 + 127)/ 128; + lval <<= 4; + size = in_height * lval; //raw12 unaligned + //write reference frame config + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_base_ad_init), buf->pa_refer); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_size_init), size); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_offs_cnt_init), 0); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_height), in_height); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_size), size); + + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), buf->pa_refer); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_lval), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_size), size); + + in_width /= 2; + in_height /= 2; + lval = (in_width); // RAW8 output + size = in_height * lval; + pr_info("%s 0x%08x\n", __func__, REG_ADDR(isp_mi_sp2_raw2_base_ad_init)); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_base_ad_init), buf->pa_motion); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_size_init), size); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_offs_cnt_init), 0); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_llength), lval); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_pic_height), in_height); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_pic_size), size); + + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_start_ad), buf->pa_motion); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_llength), lval); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_lval), lval); // align to 128 + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_size), size); + +#if 0 + isp_write_reg(dev, 0x5620, buf->pa_motion); + isp_write_reg(dev, 0x5624, size); + isp_write_reg(dev, 0x5628, 0); + isp_write_reg(dev, 0x562c, lval); + isp_write_reg(dev, 0x5630, in_width); + isp_write_reg(dev, 0x5634, in_height); + isp_write_reg(dev, 0x5638, size); + + isp_write_reg(dev, 0x5660, buf->pa_motion); + isp_write_reg(dev, 0x5664, in_width); + isp_write_reg(dev, 0x5668, lval); + isp_write_reg(dev, 0x5680, lval); // align to 128 + isp_write_reg(dev, 0x566c, size); +#endif + miv2_sp2_bus_id = isp_read_reg(dev, REG_ADDR(miv2_sp2_bus_id)); + + REG_SET_SLICE(miv2_sp2_bus_id, SP2_WR_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_BURST_LEN, 2); //sp2 rd burst lenghth 16 + REG_SET_SLICE(miv2_sp2_bus_id, SP2_BUS_SW_EN, 1); + + isp_write_reg(dev, REG_ADDR(miv2_sp2_bus_id), miv2_sp2_bus_id); + + miv2_sp2_fmt = isp_read_reg(dev, REG_ADDR(miv2_sp2_fmt)); + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_ALIGNED, 0); //unaligned + + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_ALIGNED, 0); //unaligned + + isp_write_reg(dev, REG_ADDR(miv2_sp2_fmt), miv2_sp2_fmt); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_fmt), 0); + + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1); + //REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_AUTO_UPDATE, 1); + + miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK); + //miv2_sp2_ctrl |= 0x2fa; + isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl); + + isp_mi_sp2_raw2_ctrl |= 0x23a; + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl), isp_mi_sp2_raw2_ctrl); + miv2_imsc |= SP2_RAW_FRAME_END_MASK|SP2_DMA_RAW_READY_MASK; + + isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc); + miv2_imsc2 = isp_read_reg(dev, REG_ADDR(miv2_imsc2)); + + miv2_imsc2 |= SP2_RAW2_FRAME_END_MASK | SP2_RAW2_DMA_READY_MASK; //0x41000 + isp_write_reg(dev, REG_ADDR(miv2_imsc2), miv2_imsc2); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), 0x480); + +// isp_write_reg(dev, 0x00000730, 0x00001edf); + //isp_write_reg(dev, 0x000014ec, 0x04b30000); + //isp_write_reg(dev, 0x000014f0, 0x0807e521); + return 0; +} + +int isp_r_tdnr_refer(struct isp_ic_dev *dev) +{ + struct isp_tdnr_buffer* buf = &dev->tdnr.buf; + u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc)); + u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl)); + u32 isp_mi_sp2_raw2_ctrl = isp_read_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl)); + pr_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), buf->pa_refer); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_start_ad), buf->pa_motion); + + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1); + + miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK); + miv2_sp2_ctrl |= 0xf0; + isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl); + + isp_mi_sp2_raw2_ctrl |= 0x238; + + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl), isp_mi_sp2_raw2_ctrl); + + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_START_CON, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_START, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START_CON, 1); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + + miv2_imsc |= SP2_DMA_RAW_READY_MASK; + isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc); + return 0; +} + +int isp_r_tdnr_motion(struct isp_ic_dev *dev) +{ + struct isp_tdnr_buffer* buf = &dev->tdnr.buf; + u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + u32 isp_mi_sp2_raw2_ctrl = isp_read_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl)); + pr_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_start_ad), buf->pa_motion); + + REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START_CON, 1); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + + isp_mi_sp2_raw2_ctrl |= 0x238; + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl), isp_mi_sp2_raw2_ctrl); + + return 0; +} + +int isp_tdnr_s_2dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_2DNR_V5 + pr_info("unsupported function: %s\n", __func__); + return -EINVAL; +#else + struct isp_2dnr_context *dnr2 = &dev->dnr2; + u32 isp_denoise2d_control = + isp_read_reg(dev, REG_ADDR(isp_denoise2d_control)); + u32 value, addr, strength; + u32 isp_ctrl; + int i; + + if (!dnr2->enable) { + value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 0); + if((value & DENOISE3D_V20_TNR_ENABLE_MASK) == 0) + REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), + value); + return 0; + } + + strength = isp_read_reg(dev, REG_ADDR(isp_denoise2d_strength)); + REG_SET_SLICE(strength, ISP_2DNR_PRGAMMA_STRENGTH, 1); + REG_SET_SLICE(strength, ISP_2DNR_STRENGTH, 0xff); + + isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength), strength); + pr_debug("%s: write strength addr =0x%08x value = 0x%08x \n", __func__, REG_ADDR(isp_denoise2d_strength), strength); + + addr = REG_ADDR(isp_denoise2d_sigma_y[0]); + for (i = 0; i < 60; i += 5) { + value = 0; + REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i]); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 1]); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY2A, + dnr2->sigma[i + 2] >> 6); + isp_write_reg(dev, addr, value); + value = 0; + addr += 4; + REG_SET_SLICE(value, ISP_2DNR_SIGMAY2B, + dnr2->sigma[i + 2] & 0x3f); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i + 3]); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 4]); + isp_write_reg(dev, addr, value); + addr += 4; + } + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 1); + + isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr), dnr2->sigma_sqr); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr_shd), + dnr2->sigma_sqr); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor), + dnr2->weight); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor_shd), + dnr2->weight); + /* refer to HW spec for HBLANK */ + //isp_write_reg(dev, REG_ADDR(isp_denoise2d_dummy_hblank), 0); + + isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength_shd), strength); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_control_shd), + isp_denoise2d_control); + + + value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_blending)); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_OFFSET, dnr2->str_off); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_MAX, dnr2->str_max); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_SLOPE, dnr2->str_slope); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_blending), value); + pr_debug("%s:write blending addr = 0x%08x, value = 0x%08x \n", __func__, REG_ADDR(isp_denoise3d2_blending), value); + value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 1); + REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), + value); + pr_debug("%s:write isp_denoise3d2_ctrl addr = 0x%08x, value = 0x%08x \n", __func__, REG_ADDR(isp_denoise3d2_ctrl), value); + + pr_debug("exit %s\n", __func__); + return 0; +#endif +} + +#endif diff --git a/vvcam/isp/isp_types.h b/vvcam/isp/isp_types.h new file mode 100755 index 0000000..b9958e4 --- /dev/null +++ b/vvcam/isp/isp_types.h @@ -0,0 +1,176 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_TYPES_H_ +#define _ISP_TYPES_H_ + +enum { + IC_MI_PATH_INVALID = -1, /**< lower border (only for an internal evaluation) */ + IC_MI_PATH_MAIN = 0, /**< main path index */ + IC_MI_PATH_SELF = 1, /**< self path index */ + IC_MI_PATH_SELF2 = 2, /**< self path index */ + IC_MI_PATH_MAX /**< upper border (only for an internal evaluation) */ +}; + +enum { + IC_MI_DATAMODE_INVALID = 0, /**< lower border (only for an internal evaluation) */ + IC_MI_DATAMODE_DISABLED = 1, /**< disables the path */ + IC_MI_DATAMODE_JPEG = 2, /**< data output format is JPEG (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_YUV444 = 3, /**< data output format is YUV444 */ + IC_MI_DATAMODE_YUV422 = 4, /**< data output format is YUV422 */ + IC_MI_DATAMODE_YUV420 = 5, /**< data output format is YUV420 */ + IC_MI_DATAMODE_YUV400 = 6, /**< data output format is YUV400 */ + IC_MI_DATAMODE_RGB888 = 7, /**< data output format is RGB888 (only valid for selpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RGB666 = 8, /**< data output format is RGB666 (only valid for selpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RGB565 = 9, /**< data output format is RGB565 (only valid for selpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RAW8 = 10, /**< data output format is RAW8 (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RAW12 = 11, /**< data output format is RAW12 (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_DPCC = 12, /**< path dumps out the current measured defect pixel table */ + IC_MI_DATAMODE_RAW10 = 13, /**< data output format is RAW10 (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RAW14 = 14, /**< data output format is RAW14 (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RAW16 = 15, /**< data output format is RAW16 (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_MAX /**< upper border (only for an internal evaluation) */ +}; + +enum { + IC_MI_DATASTORAGE_INVALID = 0, /**< lower border (only for an internal evaluation) */ + IC_MI_DATASTORAGE_PLANAR = 1, /**< YUV values are packed together as: YYYY......, UVUVUVUV...... */ + IC_MI_DATASTORAGE_SEMIPLANAR = 2, /**< YUV values are packed together as: YUV, YUV, YUV, ...... */ + IC_MI_DATASTORAGE_INTERLEAVED = 3, /**< Y values for all pixels are put together, as well as U and V, + like: YYYYYY......, UUUUUUU......., VVVVVV...... */ + IC_MI_DATASTORAGE_MAX /**< upper border (only for an internal evaluation) */ +}; + +enum { + ISP_PICBUF_TYPE_INVALID = 0x00, + ISP_PICBUF_TYPE_DATA = 0x08, /* just some sequential data */ + ISP_PICBUF_TYPE_RAW8 = 0x10, + ISP_PICBUF_TYPE_RAW16 = 0x11, /* includes: 9..16bits, MSBit aligned, LSByte first! */ + ISP_PICBUF_TYPE_RAW10 = 0x12, /* includes: 10bits, MSBit aligned, LSByte first! */ + ISP_PICBUF_TYPE_RAW12 = 0x13, + ISP_PICBUF_TYPE_RAW14 = 0x14, + ISP_PICBUF_TYPE_JPEG = 0x20, + ISP_PICBUF_TYPE_YCbCr444 = 0x30, + ISP_PICBUF_TYPE_YCbCr422 = 0x31, + ISP_PICBUF_TYPE_YCbCr420 = 0x32, + ISP_PICBUF_TYPE_YCbCr400 = 0x33, + ISP_PICBUF_TYPE_YCbCr32 = 0x3f, + ISP_PICBUF_TYPE_RGB888 = 0x40, + ISP_PICBUF_TYPE_RGB666 = 0x41, /* R, G & B are LSBit aligned! */ + ISP_PICBUF_TYPE_RGB565 = 0x42, /* TODO: don't know the memory layout right now, investigate! */ + ISP_PICBUF_TYPE_RGB32 = 0x4f, + _ISP_PICBUF_TYPE_DUMMY_ +}; + +enum { + ISP_PICBUF_LAYOUT_INVALID = 0, + ISP_PICBUF_LAYOUT_COMBINED = 0x10, /* ISP_PICBUF_TYPE_DATA: Data: D0 D1 D2... */ + /* ISP_PICBUF_TYPE_RAW8: Data: D0 D1 D2... */ + /* ISP_PICBUF_TYPE_RAW16/10: Data: D0L D0H D1L D1H... */ + /* ISP_PICBUF_TYPE_JPEG: Data: J0 J1 J2... */ + /* ISP_PICBUF_TYPE_YCbCr444: Data: Y0 Cb0 Cr0 Y1 Cb1Cr1... */ + /* ISP_PICBUF_TYPE_YCbCr422: Data: Y0 Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1... */ + /* ISP_PICBUF_TYPE_YCbCr32: Data: Cr0 Cb0 Y0 A0 Cr1 Cb1 Y1 A1... */ + /* ISP_PICBUF_TYPE_RGB888: Data: R0 G0 B0 R1 B2 G1... */ + /* ISP_PICBUF_TYPE_RGB666: Data: {00,R0[5:0]} {00,G0[5:0]} {00,B0[5:0]} {00,R1[5:0]} {00,G2[5:0]} {00,B3[5:0]}... */ + /* ISP_PICBUF_TYPE_RGB565: Data: {R0[4:0],G0[5:3]} {G0[2:0],B0[4:0]} {R1[4:0],G1[5:3]} {G1[2:0],B1[4:0]}... (is this correct?) */ + /* ISP_PICBUF_TYPE_RGB32: Data: B0 G0 R0 A0 B1 G1 R1 A1... */ + ISP_PICBUF_LAYOUT_BAYER_RGRGGBGB = 0x11, /* 1st line: RGRG... , 2nd line GBGB... , etc. */ + ISP_PICBUF_LAYOUT_BAYER_GRGRBGBG = 0x12, /* 1st line: GRGR... , 2nd line BGBG... , etc. */ + ISP_PICBUF_LAYOUT_BAYER_GBGBRGRG = 0x13, /* 1st line: GBGB... , 2nd line RGRG... , etc. */ + ISP_PICBUF_LAYOUT_BAYER_BGBGGRGR = 0x14, /* 1st line: BGBG... , 2nd line GRGR... , etc. */ + ISP_PICBUF_LAYOUT_SEMIPLANAR = 0x20, /* ISP_PICBUF_TYPE_YCbCr422: Luma: Y0 Y1 Y2 Y3... ; Chroma: Cb0 Cr0 Cb1 Cr1... */ + /* ISP_PICBUF_TYPE_YCbCr420: Luma: Y0 Y1 Y2 Y3... ; Chroma: Cb0 Cr0 Cb1 Cr1... */ + /* ISP_PICBUF_TYPE_YCbCr400: Luma: Y0 Y1 Y2 Y3... ; Chroma: not used */ + ISP_PICBUF_LAYOUT_PLANAR = 0x30, /* ISP_PICBUF_TYPE_YCbCr444: Y: Y0 Y1 Y2 Y3...; Cb: Cb0 Cb1 Cb2 Cb3...; Cr: Cr0 Cr1 Cr2 Cr3... */ + /* ISP_PICBUF_TYPE_YCbCr422: Y: Y0 Y1 Y2 Y3...; Cb: Cb0 Cb1 Cb2 Cb3...; Cr: Cr0 Cr1 Cr2 Cr3... */ + /* ISP_PICBUF_TYPE_YCbCr420: Y: Y0 Y1 Y2 Y3...; Cb: Cb0 Cb1 Cb2 Cb3...; Cr: Cr0 Cr1 Cr2 Cr3... */ + /* ISP_PICBUF_TYPE_YCbCr400: Y: Y0 Y1 Y2 Y3...; Cb: not used; Cr: not used... */ + /* ISP_PICBUF_TYPE_RGB888: R: R0 R1 R2 R3...; G: G0 G1 G2 G3...; B: B0 B1 B2 B3... */ + /* ISP_PICBUF_TYPE_RGB666: R: {00,R0[5:0]}...; G: {00,G0[5:0]}...; B: {00,B0[5:0]}... */ + _ISP_PICBUF_LAYOUT_DUMMY_ +}; + +enum { + IC_DPF_RB_FILTERSIZE_INVALID = 0, /**< lower border (only for an internal evaluation) */ + IC_DPF_RB_FILTERSIZE_9x9 = 1, /**< red and blue filter kernel size 9x9 (means 5x5 active pixel) */ + IC_DPF_RB_FILTERSIZE_13x9 = 2, /**< red and blue filter kernel size 13x9 (means 7x5 active pixel) */ + IC_DPF_RB_FILTERSIZE_MAX /**< upper border (only for an internal evaluation) */ +}; + +enum { + ISP_MI_DATA_ALIGN_MODE_INVALID = -1, + ISP_MI_DATA_UNALIGN_MODE = 0, /* pixel data not aligned. */ + ISP_MI_DATA_ALIGN_128BIT_MODE = 1, /* pixel data aligned with 128 bit. */ + ISP_MI_DATA_ALIGN_16BIT_MODE = 2, /* pixel data aligned with 16 bit. */ + ISP_MI_DATA_ALIGN_MODE_MAX +}; + +enum { + IC_DPF_GAIN_USAGE_INVALID = 0, /**< lower border (only for an internal evaluation) */ + IC_DPF_GAIN_USAGE_DISABLED = 1, /**< don't use any gains in preprocessing stage */ + IC_DPF_GAIN_USAGE_NF_GAINS = 2, /**< use only the noise function gains from registers DPF_NF_GAIN_R, ... */ + IC_DPF_GAIN_USAGE_LSC_GAINS = 3, /**< use only the gains from LSC module */ + IC_DPF_GAIN_USAGE_NF_LSC_GAINS = 4, /**< use the moise function gains and the gains from LSC module */ + IC_DPF_GAIN_USAGE_AWB_GAINS = 5, /**< use only the gains from AWB module */ + IC_DPF_GAIN_USAGE_AWB_LSC_GAINS = 6, /**< use the gains from AWB and LSC module */ + IC_DPF_GAIN_USAGE_MAX /**< upper border (only for an internal evaluation) */ +}; + +enum { + IC_NLL_SCALE_INVALID = 0, /**< lower border (only for an internal evaluation) */ + IC_NLL_SCALE_LINEAR = 1, /**< use a linear scaling */ + IC_NLL_SCALE_LOGARITHMIC = 2, /**< use a logarithmic scaling */ + IC_NLL_SCALE_MAX /**< upper border (only for an internal evaluation) */ +}; + +#endif /* _ISP_TYPES_H_ */ diff --git a/vvcam/isp/isp_version.h b/vvcam/isp/isp_version.h new file mode 100755 index 0000000..07a8d9f --- /dev/null +++ b/vvcam/isp/isp_version.h @@ -0,0 +1,190 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_VERSION_H_ +#define _ISP_VERSION_H_ + +#define ISP_EE_SUPPORT 1 +#define ISP_2DNR_SUPPORT (1 << 1) +#define ISP_3DNR_SUPPORT (1 << 2) +#define ISP_WDR3_SUPPORT (1 << 3) +#define ISP_MIV2_SUPPORT (1 << 4) +#define ISP_AEV2_SUPPORT (1 << 5) +#define ISP_COMPAND_SUPPORT (1 << 6) +#define ISP_HDR_STITCH_SUPPORT (1 << 7) + + +/*****************************************************************************/ +/** + * @brief HDR module version type + */ +/*****************************************************************************/ +#define VSI_ISP_HDR_NOTSUPPORT 0 //!< Not support HDR +#define VSI_ISP_HDR_V10 1 //!< Version V10 +#define VSI_ISP_HDR_V11 2 //!< Version V11 +#define VSI_ISP_HDR_V12 3 //!< Version V12 +#define VSI_ISP_HDR_V13 4 //!< Version V13 + + +///////////////////////////////////////// +//add Version defines +///////////////////////////////////////// + +/* add Version defines(Mrv_all_regs.h) +ISP8000L_V2002、ISP8000_V2003、 +ISP8000NANO_V1801、ISP8000NANO_V1802、 +ISP8000_V1901、ISP8000L_V1901、ISP8000L_V1902、 +ISP8000L_V1903、ISP8000L_V1905、ISP8000L_V2001、ISP8000L_V2006 +*/ +#define MRV_IMAGE_EFFECTS_VERSION 1 +#define MRV_SUPER_IMPOSE_VERSION 1 +#define MRV_BLACK_LEVEL_VERSION 1 +#define MRV_AUTO_EXPOSURE_VERSION 1 +#define MRV_AEV2_VERSION 1 +#define MRV_OUTPUT_FORMATTER_VERSION 1 +#define MRV_GAMMA_OUT_VERSION 1 +#define MRV_FLASH_LIGHT_VERSION 1 +#define MRV_SHUTTER_VERSION 1 +#define MRV_MAINPATH_SCALER_VERSION 1 +#define MRV_SELFPATH_SCALER_VERSION 1 +#define MRV_MI_VERSION 1 +//#define MRV_JPE_VERSION 1 +#define MRV_SMIA_VERSION 1 +#define MRV_MIPI_VERSION 1 +#define MRV_AUTOFOCUS_VERSION 1 +#define MRV_LSC_VERSION 1 +#define MRV_IS_VERSION 1 +#define MRV_HISTOGRAM_VERSION 1 +#define MRV_FILTER_VERSION 1 +#define MRV_CAC_VERSION 1 +#define MRV_DPF_VERSION 1 +#define MRV_DPCC_VERSION 1 +#define MRV_WDR_VERSION 1 +#define MRV_CSM_VERSION 1 +#define MRV_AWB_VERSION 1 +#define MRV_ELAWB_VERSION 1 +#define MRV_GAMMA_IN_VERSION 1 +#define MRV_SHUTTER_CTRL_VERSION 1 +#define MRV_CT_VERSION 1 +#define MRV_COLOR_PROCESSING_VERSION 1 +#define MRV_VSM_VERSION 1 +#define MRV_CNR_VERSION 1 + +#define MRV_WDR2_VERSION 1 +#define MRV_WDR3_VERSION 1 +#define MRV_CMPD_VERSION 1 /* compand */ +#define MRV_TPG_VERSION 1 +//#define MRV_STITCHING_VERSION 1 +#define MRV_EE_VERSION 1 +#define MRV_2DNR_VERSION 1 + +#ifdef ISP_3DNR +#define MRV_3DNR_VERSION 1 +#endif + +#ifdef ISP_GCMONO +#define MRV_GCMONO_VERSION 1 +#endif +#ifdef ISP_RGBGC +#define MRV_RGBGAMMA_VERSION 1 +#endif +#ifdef ISP_DEC +#define MRV_DEC_VERSION 1 +#endif +#ifdef ISP_DEMOSAIC2 +#define MRV_DEMOSAIC_VERSION 1 +#endif +#ifdef ISP_GREENEQUILIBRATE +#define MRV_GREENEQUILIBRATION_VERSION 1 +#endif +#ifdef ISP_CA +#define MRV_COLOR_ADJUST_VERSION 1 +#endif + +#ifdef ISP_SP2 +#define MRV_SP2_VERSION 1 +#endif + +#ifdef ISP_HDR_STITCH_V2 +#undef MRV_STITCHING_VERSION +#define MRV_STITCHING_VERSION 2 //1--V11, 2--V12 + +#elif defined(ISP_HDR_STITCH_V3) +#undef MRV_STITCHING_VERSION +#define MRV_STITCHING_VERSION 3 //1--V11, 2--V12 3--V13 +#elif defined(ISP_HDR_STITCH) + +#undef MRV_STITCHING_VERSION +#define MRV_STITCHING_VERSION 1 //1--V11, 2--V12 3--V13 +#endif + +#ifdef ISP_3DNR_V2 +#define MRV_3DNR_VERSION 1 +#endif + +#ifdef ISP_WDR_V4 +#define MRV_WDR4_VERSION 1 +#endif + +#ifdef ISP_3DNR_V3 +#define MRV_TDNR3_VERSION 1 +#endif + +#ifdef ISP_RGBIR +#define MRV_RGBIR_VERSION 1 +#endif + +#ifdef ISP_HIST64 + +#define MRV_HISTOGRAM64_VERSION 1 +#endif +#endif /* _ISP_VERSION_H_ */ diff --git a/vvcam/isp/isp_wdr.c b/vvcam/isp/isp_wdr.c new file mode 100755 index 0000000..37dc267 --- /dev/null +++ b/vvcam/isp/isp_wdr.c @@ -0,0 +1,136 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include "isp_wdr.h" +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" +#include "ic_dev.h" + +extern MrvAllRegister_t *all_regs; + + +int isp_s_wdr(struct isp_ic_dev *dev) +{ + isp_wdr_context_t* wdr = &dev->wdr; + + pr_info(" enter %s\n", __func__); + + /*update wdr configuration after frame end when isp enable*/ + if (!is_isp_enable(dev) || wdr->changed) { + uint32_t isp_wdr_offset, isp_wdr_ctrl; + + isp_wdr_offset = isp_read_reg(dev, REG_ADDR(isp_wdr_offset)); + REG_SET_SLICE( isp_wdr_offset, MRV_WDR_LUM_OFFSET, wdr->LumOffset ); + REG_SET_SLICE( isp_wdr_offset, MRV_WDR_RGB_OFFSET, wdr->RgbOffset ); + isp_write_reg(dev, REG_ADDR(isp_wdr_offset), isp_wdr_offset); + + isp_wdr_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr_ctrl)); + REG_SET_SLICE(isp_wdr_ctrl, MRV_WDR_ENABLE, wdr->enabled); + isp_write_reg(dev, REG_ADDR(isp_wdr_ctrl), isp_wdr_ctrl); + wdr->changed = false; + } else { + wdr->changed = true; + } + pr_info(" %s wdr.changed %d \n", __func__, wdr->changed); + return 0; +} + +int isp_s_wdr_curve(struct isp_ic_dev *dev) +{ + + isp_wdr_context_t* wdr = &dev->wdr; + + int i, j; + uint32_t dYi = 0U; + for ( i=0; i<4; i++ ) + { + for ( j=8; j>0; j-- ) + { + dYi <<= 4; + dYi += wdr->dY[ (i*8 + j) ]; + } + + if (i == 0) + { + + isp_write_reg(dev, REG_ADDR(isp_wdr_tonecurve_1), dYi); + } + else if (i == 1) + { + isp_write_reg(dev, REG_ADDR(isp_wdr_tonecurve_2), dYi); + } + else if (i == 2) + { + isp_write_reg(dev, REG_ADDR(isp_wdr_tonecurve_3), dYi); + } + else /* if (i == 3) */ + { + isp_write_reg(dev, REG_ADDR(isp_wdr_tonecurve_4), dYi); + } + } + + for ( i=0; i<33; i++ ) + { + isp_write_reg(dev, REG_ADDR(wdr_tone_mapping_curve_y_block_arr[i]), wdr->Ym[i]); + } + + dYi = 0x00000000; + + isp_write_reg(dev, REG_ADDR(isp_wdr_offset), dYi); + isp_write_reg(dev, REG_ADDR(isp_wdr_deltamin), 0x00100000); + + return 0; + +} + + diff --git a/vvcam/isp/isp_wdr.h b/vvcam/isp/isp_wdr.h new file mode 100755 index 0000000..eb2d741 --- /dev/null +++ b/vvcam/isp/isp_wdr.h @@ -0,0 +1,67 @@ + +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_WDR_H +#define _ISP_WDR_H + +#include "isp_version.h" +#include "vvdefs.h" +#include "ic_dev.h" + + +int isp_s_wdr(struct isp_ic_dev *dev); +int isp_s_wdr_curve(struct isp_ic_dev *dev); + + +#endif + diff --git a/vvcam/isp/isp_wdr3.c b/vvcam/isp/isp_wdr3.c new file mode 100755 index 0000000..90bb772 --- /dev/null +++ b/vvcam/isp/isp_wdr3.c @@ -0,0 +1,502 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +#define WDR3_WW (32) +#define WDR3_HH (32) +#define WDR3_MAX_VALUE (1023) +#define WDR3_GAIN_SHIFT (2) +#define WDR3_NORMALIZE (1024) +#define WDR3_NORMALIZE_SHIFT (10) +#ifdef ISP_WDR_V3_20BIT +#define MODULE_INPUT_BIT_DEPTH (20) +#else +#define MODULE_INPUT_BIT_DEPTH (12) +#endif +#define MODULE_OUTPUT_BIT_DEPTH (12) + +extern MrvAllRegister_t *all_regs; + +#ifdef ISP_WDR_V3 +static void wdr3_hw_init(struct isp_ic_dev *dev) +{ + + struct isp_wdr3_context *wdr3 = &dev->wdr3; + u32 isp_wdr3_shift_0; + u32 isp_wdr3_shift_1; + + u32 width, height; + u32 slice_block_area_factor; + u32 slice_value_weight[4]; + u32 slice_pixel_slope_merge; + u32 slice_pixel_base_merge; + u32 slice_pixel_slope_adjust; + u32 slice_pixel_base_adjust; + u32 slice_pixel_slope_entropy; + u32 slice_pixel_base_entropy; + u32 slice_sigma_height; + u32 slice_sigma_width; + u32 slice_sigma_value; + u32 slice_block_width; + u32 slice_block_height; + u32 isp_wdr3_block_size; + u32 isp_wdr3_block_area_factor; + u32 isp_wdr3_value_weight; + u32 isp_wdr3_pixel_slope; + u32 isp_wdr3_entropy_slope; + u32 isp_wdr3_sigma_width; + u32 isp_wdr3_sigma_height; + u32 isp_wdr3_sigma_value; + u32 isp_wdr3_block_flag_width; + u32 isp_wdr3_block_flag_height; + u32 isp_wdr3_strength; + u32 width_left; + u32 width_count = 0; + u32 height_left; + u32 height_count = 0; + u32 val; + bool reg_flag = false; + int i, pos; + + pr_info("enter %s\n", __func__); + + width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size)); + height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size)); + + pr_info("wdr3 res: %d %d \n", width, height); + /* firware initilization */ + slice_pixel_slope_merge = 128; + slice_pixel_base_merge = 0; + slice_pixel_slope_adjust = 128; + slice_pixel_base_adjust = 0; + slice_pixel_slope_entropy = 204; + slice_pixel_base_entropy = 716; + + slice_value_weight[0] = 6; + slice_value_weight[1] = 5; + slice_value_weight[2] = 5; + slice_value_weight[3] = 16; + + slice_block_width = width / WDR3_WW; + slice_block_height = height / WDR3_HH; + slice_block_area_factor = + WDR3_NORMALIZE * WDR3_NORMALIZE / (slice_block_width * + slice_block_height); + slice_sigma_height = + WDR3_NORMALIZE * WDR3_NORMALIZE / slice_block_height; + slice_sigma_width = WDR3_NORMALIZE * WDR3_NORMALIZE / slice_block_width; + slice_sigma_value = WDR3_NORMALIZE * WDR3_NORMALIZE / WDR3_MAX_VALUE; + + /* block flag configuration */ + width_left = width - slice_block_width * WDR3_WW; + height_left = height - slice_block_height * WDR3_HH; + isp_wdr3_block_flag_width = 0; + isp_wdr3_block_flag_height = 0; + + for (i = 0, width_count = 0; + (i < WDR3_WW) && (width_count < width_left); i++, width_count++) { + isp_wdr3_block_flag_width |= (1 << i); + } + + for (i = 0, height_count = 0; + (i < WDR3_HH) && (height_count < height_left); + i++, height_count++) { + isp_wdr3_block_flag_height |= (1 << i); + } + + slice_pixel_base_adjust += 255; + slice_pixel_base_merge += 255; + +#ifndef __KERNEL__ + //NOTE: register isp_wdr3_shift is read-only register on fpga, can not write + //NOTE: it is used by cmodel, So it should be config. + u32 slice_pixel_shift; + u32 slice_output_shift; + u32 isp_wdr3_shift; + + slice_pixel_shift = MODULE_INPUT_BIT_DEPTH - 5; + slice_output_shift = MODULE_INPUT_BIT_DEPTH - MODULE_OUTPUT_BIT_DEPTH; + + isp_wdr3_shift = isp_read_reg(dev, REG_ADDR(isp_wdr3_shift)); + REG_SET_SLICE(isp_wdr3_shift, WDR3_PIXEL_SHIFT_BIT, slice_pixel_shift); + REG_SET_SLICE(isp_wdr3_shift, WDR3_OUTPUT_SHIFT_BIT, + slice_output_shift); + isp_write_reg(dev, REG_ADDR(isp_wdr3_shift), isp_wdr3_shift); +#endif + + isp_wdr3_block_size = isp_read_reg(dev, REG_ADDR(isp_wdr3_block_size)); + REG_SET_SLICE(isp_wdr3_block_size, WDR3_BLOCK_WIDTH, slice_block_width); + REG_SET_SLICE(isp_wdr3_block_size, WDR3_BLOCK_HEIGHT, + slice_block_height); + isp_write_reg(dev, REG_ADDR(isp_wdr3_block_size), isp_wdr3_block_size); + + isp_wdr3_block_area_factor = + isp_read_reg(dev, REG_ADDR(isp_wdr3_block_area_factor)); + REG_SET_SLICE(isp_wdr3_block_area_factor, WDR3_BLOCK_AREA_INVERSE, + slice_block_area_factor); + isp_write_reg(dev, REG_ADDR(isp_wdr3_block_area_factor), + isp_wdr3_block_area_factor); + isp_wdr3_value_weight = + isp_read_reg(dev, REG_ADDR(isp_wdr3_value_weight)); + REG_SET_SLICE(isp_wdr3_value_weight, WDR3_VALUE_WEIGHT_0, + slice_value_weight[0]); + REG_SET_SLICE(isp_wdr3_value_weight, WDR3_VALUE_WEIGHT_1, + slice_value_weight[1]); + REG_SET_SLICE(isp_wdr3_value_weight, WDR3_VALUE_WEIGHT_2, + slice_value_weight[2]); + REG_SET_SLICE(isp_wdr3_value_weight, WDR3_VALUE_WEIGHT_3, + slice_value_weight[3]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_value_weight), + isp_wdr3_value_weight); + + isp_wdr3_strength = isp_read_reg(dev, REG_ADDR(isp_wdr3_strength)); + REG_SET_SLICE(isp_wdr3_strength, WDR3_MAXIMUM_GAIN, wdr3->max_gain); + REG_SET_SLICE(isp_wdr3_strength, WDR3_GLOBAL_STRENGTH, + wdr3->global_strength); + REG_SET_SLICE(isp_wdr3_strength, WDR3_LOCAL_STRENGTH, + 128); + REG_SET_SLICE(isp_wdr3_strength, WDR3_TOTAL_STRENGTH, wdr3->strength); + isp_write_reg(dev, REG_ADDR(isp_wdr3_strength), isp_wdr3_strength); + + isp_wdr3_pixel_slope = + isp_read_reg(dev, REG_ADDR(isp_wdr3_pixel_slope)); + REG_SET_SLICE(isp_wdr3_pixel_slope, WDR3_PIXEL_ADJUST_BASE, + slice_pixel_base_adjust); + REG_SET_SLICE(isp_wdr3_pixel_slope, WDR3_PIXEL_ADJUST_SLOPE, + slice_pixel_slope_adjust); + REG_SET_SLICE(isp_wdr3_pixel_slope, WDR3_PIXEL_MERGE_BASE, + slice_pixel_base_merge); + REG_SET_SLICE(isp_wdr3_pixel_slope, WDR3_PIXEL_MERGE_SLOPE, + slice_pixel_slope_merge); + isp_write_reg(dev, REG_ADDR(isp_wdr3_pixel_slope), + isp_wdr3_pixel_slope); + + isp_wdr3_entropy_slope = + isp_read_reg(dev, REG_ADDR(isp_wdr3_entropy_slope)); + REG_SET_SLICE(isp_wdr3_entropy_slope, WDR3_ENTROPY_BASE, + slice_pixel_base_entropy); + REG_SET_SLICE(isp_wdr3_entropy_slope, WDR3_ENTROPY_SLOPE, + slice_pixel_slope_entropy); + isp_write_reg(dev, REG_ADDR(isp_wdr3_entropy_slope), + isp_wdr3_entropy_slope); + + isp_wdr3_sigma_width = + isp_read_reg(dev, REG_ADDR(isp_wdr3_sigma_width)); + REG_SET_SLICE(isp_wdr3_sigma_width, WDR3_BILITERAL_WIDTH_SIGMA, + slice_sigma_width); + isp_write_reg(dev, REG_ADDR(isp_wdr3_sigma_width), + isp_wdr3_sigma_width); + + isp_wdr3_sigma_height = + isp_read_reg(dev, REG_ADDR(isp_wdr3_sigma_height)); + REG_SET_SLICE(isp_wdr3_sigma_height, WDR3_BILITERAL_HEIGHT_SIGMA, + slice_sigma_height); + isp_write_reg(dev, REG_ADDR(isp_wdr3_sigma_height), + isp_wdr3_sigma_height); + + isp_wdr3_sigma_value = + isp_read_reg(dev, REG_ADDR(isp_wdr3_sigma_value)); + REG_SET_SLICE(isp_wdr3_sigma_value, WDR3_BILITERAL_VALUE_SIGMA, + slice_sigma_value); + isp_write_reg(dev, REG_ADDR(isp_wdr3_sigma_value), + isp_wdr3_sigma_value); + + isp_write_reg(dev, REG_ADDR(isp_wdr3_block_flag_width), + isp_wdr3_block_flag_width); + isp_write_reg(dev, REG_ADDR(isp_wdr3_block_flag_height), + isp_wdr3_block_flag_height); + + for (i = 0; i < 5; i++) { + reg_flag = i < 4; + pos = i * 3; + val = + wdr3->histogram[pos] << (reg_flag ? + WDR3_HISTOGRAM_CURVE0_SHIFT : + WDR3_HISTOGRAM_CURVE1_SHIFT); + val |= + wdr3->histogram[pos + + 1] << (reg_flag ? + WDR3_HISTOGRAM_CURVE1_SHIFT : + WDR3_HISTOGRAM_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_HISTOGRAM_CURVE2, + wdr3->histogram[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_histogram[i]), val); + + val = + wdr3->entropy[pos] << (reg_flag ? + WDR3_ENTROPY_CONVERT0_SHIFT : + WDR3_ENTROPY_CONVERT1_SHIFT); + val |= + wdr3->entropy[pos + + 1] << (reg_flag ? WDR3_ENTROPY_CONVERT1_SHIFT + : WDR3_ENTROPY_CONVERT2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_ENTROPY_CONVERT2, + wdr3->entropy[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_entropy[i]), val); + + val = + wdr3->gamma_pre[pos] << (reg_flag ? + WDR3_GAMMA_PRE_CURVE0_SHIFT : + WDR3_GAMMA_PRE_CURVE1_SHIFT); + val |= + wdr3->gamma_pre[pos + + 1] << (reg_flag ? + WDR3_GAMMA_PRE_CURVE1_SHIFT : + WDR3_GAMMA_PRE_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_GAMMA_PRE_CURVE2, + wdr3->gamma_pre[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_gamma_pre[i]), val); + + val = + wdr3->gamma_up[pos] << (reg_flag ? + WDR3_GAMMA_UP_CURVE0_SHIFT : + WDR3_GAMMA_UP_CURVE1_SHIFT); + val |= + wdr3->gamma_up[pos + + 1] << (reg_flag ? WDR3_GAMMA_UP_CURVE1_SHIFT + : WDR3_GAMMA_UP_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_GAMMA_UP_CURVE2, + wdr3->gamma_up[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_gamma_up[i]), val); + + val = + wdr3->gamma_down[pos] << (reg_flag ? + WDR3_GAMMA_DOWN_CURVE0_SHIFT : + WDR3_GAMMA_DOWN_CURVE1_SHIFT); + val |= + wdr3->gamma_down[pos + + 1] << (reg_flag ? + WDR3_GAMMA_DOWN_CURVE1_SHIFT : + WDR3_GAMMA_DOWN_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_GAMMA_DOWN_CURVE2, + wdr3->gamma_down[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_gamma_down[i]), val); + + val = + wdr3->distance_weight[pos] << (reg_flag ? + WDR3_DISTANCE_WEIGHT_CURVE0_SHIFT + : + WDR3_DISTANCE_WEIGHT_CURVE1_SHIFT); + val |= + wdr3->distance_weight[pos + + 1] << (reg_flag ? + WDR3_DISTANCE_WEIGHT_CURVE1_SHIFT + : + WDR3_DISTANCE_WEIGHT_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_DISTANCE_WEIGHT_CURVE2, + wdr3->distance_weight[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_distance_weight[i]), val); + + val = + wdr3->difference_weight[pos] << (reg_flag ? + WDR3_DIFFERENCE_WEIGHT_CURVE0_SHIFT + : + WDR3_DIFFERENCE_WEIGHT_CURVE1_SHIFT); + val |= + wdr3->difference_weight[pos + + 1] << (reg_flag ? + WDR3_DIFFERENCE_WEIGHT_CURVE1_SHIFT + : + WDR3_DIFFERENCE_WEIGHT_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_DIFFERENCE_WEIGHT_CURVE2, + wdr3->difference_weight[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_difference_weight[i]), + val); + } + + for (i = 0; i < 7; i++) { + val = 0; + REG_SET_SLICE(val, WDR3_GLOBAL_CURVE_INVERT0, + wdr3->invert_curve[i * 2]); + REG_SET_SLICE(val, WDR3_GLOBAL_CURVE_INVERT1, + wdr3->invert_curve[i * 2 + 1]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_invert_curve[i]), val); + val = 0; + REG_SET_SLICE(val, WDR3_LINEAR_CURVE_INVERT0, + wdr3->invert_linear[i * 2]); + REG_SET_SLICE(val, WDR3_LINEAR_CURVE_INVERT1, + wdr3->invert_linear[i * 2 + 1]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_invert_linear[i]), val); + } + + isp_wdr3_shift_0 = 0; + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT0, wdr3->shift[0]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT1, wdr3->shift[1]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT2, wdr3->shift[2]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT3, wdr3->shift[3]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT4, wdr3->shift[4]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT5, wdr3->shift[5]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT6, wdr3->shift[6]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT7, wdr3->shift[7]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_shift_0), isp_wdr3_shift_0); + + isp_wdr3_shift_1 = 0; + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT8, wdr3->shift[8]); + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT9, wdr3->shift[9]); + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT10, + wdr3->shift[10]); + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT11, + wdr3->shift[11]); + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT12, + wdr3->shift[12]); + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT13, + wdr3->shift[13]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_shift_1), isp_wdr3_shift_1); + + { + uint32_t isp_wdr3_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr3_ctrl)); + REG_SET_SLICE(isp_wdr3_ctrl, WDR3_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_wdr3_ctrl), isp_wdr3_ctrl); + } +} +#endif + +int isp_enable_wdr3(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V3 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_wdr3_context *wdr3 = &dev->wdr3; + int32_t isp_wdr3_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr3_ctrl)); + wdr3->enable = true; + REG_SET_SLICE(isp_wdr3_ctrl, WDR3_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_wdr3_ctrl), isp_wdr3_ctrl); + + { + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } + return 0; +#endif +} + +int isp_disable_wdr3(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V3 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_wdr3_context *wdr3 = &dev->wdr3; + int32_t isp_wdr3_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr3_ctrl)); + wdr3->enable = false; + REG_SET_SLICE(isp_wdr3_ctrl, WDR3_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_wdr3_ctrl), isp_wdr3_ctrl); + + { + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } + return 0; +#endif +} + +int isp_u_wdr3(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V3 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + wdr3_hw_init(dev); + return 0; +#endif +} + +int isp_s_wdr3(struct isp_ic_dev *dev) +{ + +#ifndef ISP_WDR_V3 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_wdr3_context *wdr3 = &dev->wdr3; + u32 isp_wdr3_strength = isp_read_reg(dev, REG_ADDR(isp_wdr3_strength)); + u32 width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size)); + u32 height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size)); + width /= 32; + height /= 32; + + REG_SET_SLICE(isp_wdr3_strength, WDR3_MAXIMUM_GAIN, wdr3->max_gain); + REG_SET_SLICE(isp_wdr3_strength, WDR3_GLOBAL_STRENGTH, + wdr3->global_strength); + REG_SET_SLICE(isp_wdr3_strength, WDR3_LOCAL_STRENGTH, 128); + REG_SET_SLICE(isp_wdr3_strength, WDR3_TOTAL_STRENGTH, wdr3->strength); + + isp_write_reg(dev, REG_ADDR(isp_wdr3_block_size), + width | (height << 9)); + isp_write_reg(dev, REG_ADDR(isp_wdr3_strength), isp_wdr3_strength); + isp_write_reg(dev, REG_ADDR(isp_wdr3_strength_shd), isp_wdr3_strength); /* cmodel use */ + + { + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } + return 0; +#endif +} diff --git a/vvcam/isp/isp_wdr4.c b/vvcam/isp/isp_wdr4.c new file mode 100755 index 0000000..0ffc82c --- /dev/null +++ b/vvcam/isp/isp_wdr4.c @@ -0,0 +1,515 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +#ifdef ISP_WDR_V4 +#define WDR4_WW (32) +#define WDR4_HH (32) +#define WDR4_MAX_VALUE (1048575) +#define WDR4_GAIN_SHIFT (2) +#define WDR4_NORMALIZE (1024) +#define WDR4_NORMALIZE_SHIFT (10) +#ifdef ISP_WDR_V4_20BIT +#define MODULE_INPUT_BIT_DEPTH (20) +#else +#define MODULE_INPUT_BIT_DEPTH (12) +#endif +#define MODULE_OUTPUT_BIT_DEPTH (12) + +extern MrvAllRegister_t *all_regs; + +static void wdr4_config_curve(struct isp_ic_dev *dev) +{ + struct isp_wdr4_context *wdr4 = &dev->wdr4; + u32 pos, i , val; + //u32 isp_wdr4_shift_0; + //u32 isp_wdr4_shift0_0; + //initialize the histogram && entropy && gamma_pre && gamma_up && gamma_down && invert_linear + for (i = 0; i < 7; i++) { + u32 val_high_bit, val_low_bit; + pos = i * 3; + //get the curve that combined with high && low data + val_high_bit = (wdr4->histogram[pos] >> 10) & (0x3ff); + val_low_bit = wdr4->histogram[pos] & (0x3ff); + + val = val_low_bit << WDR4_HISTOGRAM_CURVE0_0_SHIFT ; + val |= wdr4->histogram[pos +1]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_histogram_0) + i * 2 * ISP_REG_GAP, val); + + val = val_high_bit << WDR4_HISTOGRAM_CURVE0_0_SHIFT ; + + if (pos + 2 < WDR4_BIN) { + val |= wdr4->histogram[pos +2]; + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_histogram_0) + (i *2 + 1) * ISP_REG_GAP, val); + + //get the value that combined with high && low data + val_high_bit = (wdr4->gamma_pre[pos] >> 10) & 0x3ff; + val_low_bit = (wdr4->gamma_pre[pos] & 0x3ff) ; + + val = val_low_bit << WDR4_GAMMA_PRE_CURVE0_1_SHIFT ; + val |= wdr4->gamma_pre[pos +1]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_gamma_pre_0) + (i * 2) * ISP_REG_GAP, val); + + val = val_high_bit << WDR4_GAMMA_PRE_CURVE0_1_SHIFT ; + + if (pos + 2 < WDR4_BIN) + val |= wdr4->gamma_pre[pos +2]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_gamma_pre_0) + (i *2 + 1) * ISP_REG_GAP, val); + + + //get the value that combined with high && low data + val_high_bit = (wdr4->gamma_up[pos] >> 10) & 0x3ff; + val_low_bit = (wdr4->gamma_up[pos] & 0x3ff); + + val = val_low_bit <gamma_up[pos +1]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_gamma_up_0) + (i * 2) * ISP_REG_GAP, val); + val = val_high_bit <gamma_up[pos +2]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_gamma_up_0) + (i *2 + 1) * ISP_REG_GAP, val); + + + //get the value that combined with high && low data + val_high_bit = (wdr4->invert_linear[pos] >> 9) & 0x1ff; + val_low_bit = (wdr4->invert_linear[pos] & 0x1ff); + + val = val_low_bit << WDR4_LINEAR_CURVE_INVERT0_0_SHIFT; + val |= wdr4->invert_linear[pos +1]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_invert_linear_0) + (i * 2) * ISP_REG_GAP, val); + val = val_high_bit << WDR4_LINEAR_CURVE_INVERT0_0_SHIFT; + if (pos + 2 < WDR4_BIN) + val |= wdr4->invert_linear[pos +2]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_invert_linear_0) + (i *2 + 1) * ISP_REG_GAP, val); + + if (pos + 2 < WDR4_BIN) { + val = wdr4->entropy[pos] << WDR4_ENTROPY_CONVERT0_SHIFT ; + val |= wdr4->entropy[pos +1] << WDR4_ENTROPY_CONVERT1_SHIFT; + + val |= wdr4->entropy[pos +2] << WDR4_ENTROPY_CONVERT2_SHIFT; + } else { //the lasw two entropy + val = wdr4->entropy[pos] << WDR4_ENTROPY_CONVERT18_SHIFT ; + val |= wdr4->entropy[pos +1] << WDR4_ENTROPY_CONVERT19_SHIFT; + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_entropy_0) + i * ISP_REG_GAP, val); + + if (pos + 2 < WDR4_BIN) { + val = wdr4->gamma_down[pos] << WDR4_GAMMA_DOWN_CURVE0_SHIFT ; + val |= wdr4->gamma_down[pos +1] << WDR4_GAMMA_DOWN_CURVE1_SHIFT; + + val |= wdr4->gamma_down[pos +2] << WDR4_GAMMA_DOWN_CURVE2_SHIFT; + } else { //the lasw two entropy + val = wdr4->gamma_down[pos] << WDR4_GAMMA_DOWN_CURVE18_SHIFT ; + val |= wdr4->gamma_down[pos +1] << WDR4_GAMMA_DOWN_CURVE19_SHIFT; + + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_gamma_down_0) + i * ISP_REG_GAP, val); + } + + //config the distance weight && different weight && SMOOTH INVERT + for (i = 0 ; i < 5 ; i++) { + pos = i * ISP_REG_GAP; + val = wdr4->distance_weight[pos] << WDR4_DISTANCE_WEIGHT_CURVE0_SHIFT ; + val |= wdr4->distance_weight[pos +1] << WDR4_DISTANCE_WEIGHT_CURVE1_SHIFT; + val |= wdr4->distance_weight[pos +2] << WDR4_DISTANCE_WEIGHT_CURVE2_SHIFT; + val |= wdr4->distance_weight[pos +3] << WDR4_DISTANCE_WEIGHT_CURVE3_SHIFT; + isp_write_reg(dev, REG_ADDR(isp_wdr4_distance_weight_0) + i * ISP_REG_GAP, val); + + val = wdr4->difference_weight[pos] << WDR4_DIFFERENCE_WEIGHT_CURVE0_SHIFT ; + val |= wdr4->difference_weight[pos +1] << WDR4_DIFFERENCE_WEIGHT_CURVE1_SHIFT; + val |= wdr4->difference_weight[pos +2] << WDR4_DIFFERENCE_WEIGHT_CURVE2_SHIFT; + val |= wdr4->difference_weight[pos +3] << WDR4_DIFFERENCE_WEIGHT_CURVE3_SHIFT; + + + isp_write_reg(dev, REG_ADDR(isp_wdr4_difference_weight_0) + i * ISP_REG_GAP, val); + + + val = wdr4->smooth_invert[pos] << WDR4_SMOOTH_INVERT_CURVE0_SHIFT ; + val |= wdr4->smooth_invert[pos +1] << WDR4_SMOOTH_INVERT_CURVE1_SHIFT; + val |= wdr4->smooth_invert[pos +2] << WDR4_SMOOTH_INVERT_CURVE2_SHIFT; + val |= wdr4->smooth_invert[pos +3] << WDR4_SMOOTH_INVERT_CURVE3_SHIFT; + isp_write_reg(dev, REG_ADDR(isp_wdr4_smooth_invert_0) + i * ISP_REG_GAP, val); + + } + for (i = 0; i < 10; i++) { + val = 0; + REG_SET_SLICE(val, WDR4_GLOBAL_CURVE_INVERT0, + wdr4->invert_curve[i * 2]); + REG_SET_SLICE(val, WDR4_GLOBAL_CURVE_INVERT1, + wdr4->invert_curve[i * 2 + 1]); + isp_write_reg(dev, REG_ADDR(isp_wdr4_invert_curve_0) + i * ISP_REG_GAP, val); + + } + + for (i = 0 ; i < 4; i++) { + val = 0 ; + pos = i * 6; + if (pos + 3 > WDR4_BIN) { + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT18, wdr4->shift[ pos +0]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT19, wdr4->shift[ pos +1]); + } else { + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT0, wdr4->shift[ pos +0]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT1, wdr4->shift[ pos +1]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT2, wdr4->shift[ pos +2]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT3, wdr4->shift[ pos +3]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT4, wdr4->shift[ pos +4]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT5, wdr4->shift[ pos +5]); + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_shift_0) + i * ISP_REG_GAP, val); + + } + + for (i = 0 ; i < 3; i++) { + val = 0 ; + pos = i * 8; + if (pos + 5 > WDR4_BIN) { + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT16, wdr4->shift0[ pos +0]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT17, wdr4->shift0[ pos +1]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT18, wdr4->shift0[ pos +2]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT19, wdr4->shift0[ pos +3]); + } else { + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT0, wdr4->shift0[ pos +0]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT1, wdr4->shift0[ pos +1]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT2, wdr4->shift0[ pos +2]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT3, wdr4->shift0[ pos +3]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT4, wdr4->shift0[ pos +4]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT5, wdr4->shift0[ pos +5]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT6, wdr4->shift0[ pos +6]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT7, wdr4->shift0[ pos +7]); + } + + isp_write_reg(dev, REG_ADDR(isp_wdr4_shift0_0) + i * ISP_REG_GAP, val); + } + +} +static void wdr4_hw_init(struct isp_ic_dev *dev) +{ + // struct isp_wdr4_context *wdr4 = &dev->wdr4; + u32 width, height; + u32 slice_sigma_height; + u32 slice_sigma_width; + u32 slice_sigma_value; + u32 slice_block_width; + u32 slice_block_height; + u32 isp_wdr4_block_size; + u32 slice_block_area_inverse; + u32 isp_wdr4_value_weight; + u32 isp_wdr4_pixel_slope; + u32 isp_wdr4_entropy_slope; + u32 isp_wdr4_sigma_width; + u32 isp_wdr4_sigma_height; + u32 isp_wdr4_sigma_value; + u32 isp_wdr4_block_flag_width; + u32 isp_wdr4_block_flag_height; + u32 isp_wdr4_strength; + u32 isp_wdr4_block_area_factor; + u32 width_left; + u32 width_count = 0; + u32 height_left; + u32 height_count = 0; + u32 isp_wdr4_strength_0 = 0, isp_wdr4_strength_1 = 0, isp_wdr4_contrast = 0; + int i; + u8 isp_wdr4_low_strength, isp_wdr4_high_strength, isp_wdr4_global_strength; + u8 isp_wdr4_local_strength; + + u32 slice_pixel_shift; + u32 slice_output_shift;// isp_wdr4_normalize_shift; + u32 isp_wdr4_shift;// isp_wdr4_gain_shift_bit; + pr_info("enter %s\n", __func__); + + width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size)); + height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size)); + + pr_info("isp_wdr4 res: %d %d \n", width, height); + /* firware initilization */ + + isp_wdr4_strength = 128; // valid values: [0,128]; isp_wdr4 will merge original and enhanced image + // together based on this value. + // 128: use enhanced image completely; 0: use original image completely + isp_wdr4_low_strength = 16; // Valid values: [0,255]; if hdr off, limit the maximum gain for image enhancement + // if hdr on, control low light area information. Higher:haver more low light information + isp_wdr4_high_strength = 60; //valid values:[0, 128]: control high light area information. Higher:have more high + // light information + isp_wdr4_global_strength = 128; // Valid values: [0,128] + // isp_wdr4 will increase global contrast based on this value. + // 128: use strongest contrast; 0: on contrast increasing. + isp_wdr4_local_strength = 128; // valid values: [0,128] + // wdr4 will increase local contrast based on this value. + // 128: use strongest contrast; 0: on contrast increasing. + + isp_wdr4_strength_0 = isp_read_reg(dev, REG_ADDR(isp_wdr4_strength_0)); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_LOCAL_STRENGTH, isp_wdr4_local_strength); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_GLOBAL_STRENGTH, isp_wdr4_global_strength); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_LOW_STRENGTH, isp_wdr4_low_strength); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_TOTAL_STRENGTH,isp_wdr4_strength); + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_0), isp_wdr4_strength_0); + + isp_wdr4_strength_1 = isp_read_reg(dev, REG_ADDR(isp_wdr4_strength_1)); + REG_SET_SLICE(isp_wdr4_strength_1, WDR4_HIGH_STRENGTH, isp_wdr4_high_strength); + REG_SET_SLICE(isp_wdr4_strength_1, WDR4_DRC_BAYER_RATIO, 14); + REG_SET_SLICE(isp_wdr4_strength_1, WDR4_DRC_BAYER_RATIOLSVS, 14); + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_1), isp_wdr4_strength_1); + + isp_wdr4_contrast = isp_read_reg(dev, REG_ADDR(isp_wdr4_contrast)); + REG_SET_SLICE(isp_wdr4_contrast , WDR4_CONTRAST ,0); //valid values:[-1023~1023]:control contrast of image,.higher:image have stronger contrast + REG_SET_SLICE(isp_wdr4_contrast , WDR4_FLAT_STRENGTH ,8);//valid values:[0, 19]:adjust flat area. Higher:flat area stretched more strong + REG_SET_SLICE(isp_wdr4_contrast , WDR4_FLAT_THR ,1); //valid values:[0, 20]:judge flat region. + + isp_write_reg(dev, REG_ADDR(isp_wdr4_contrast), isp_wdr4_contrast); + + isp_wdr4_pixel_slope = isp_read_reg(dev, REG_ADDR(isp_wdr4_pixel_slope)); + REG_SET_SLICE(isp_wdr4_pixel_slope , WDR4_PIXEL_MERGE_SLOPE , 128); + REG_SET_SLICE(isp_wdr4_pixel_slope , WDR4_PIXEL_MERGE_BASE , 128); + REG_SET_SLICE(isp_wdr4_pixel_slope , WDR4_PIXEL_ADJUST_SLOPE ,128); + REG_SET_SLICE(isp_wdr4_pixel_slope , WDR4_PIXEL_ADJUST_BASE , 128); + + isp_write_reg(dev, REG_ADDR(isp_wdr4_pixel_slope), isp_wdr4_pixel_slope); + + isp_wdr4_entropy_slope = isp_read_reg(dev, REG_ADDR(isp_wdr4_entropy_slope)); + REG_SET_SLICE(isp_wdr4_entropy_slope , WDR4_ENTROPY_SLOPE , 0xc8); + REG_SET_SLICE(isp_wdr4_entropy_slope , WDR4_ENTROPY_BASE ,0x02bc); + isp_write_reg(dev, REG_ADDR(isp_wdr4_entropy_slope), isp_wdr4_entropy_slope); + + isp_wdr4_value_weight = isp_read_reg(dev, REG_ADDR(isp_wdr4_value_weight)); + REG_SET_SLICE(isp_wdr4_value_weight , WDR4_VALUE_WEIGHT_0 , 6); + REG_SET_SLICE(isp_wdr4_value_weight , WDR4_VALUE_WEIGHT_1 , 5); + REG_SET_SLICE(isp_wdr4_value_weight , WDR4_VALUE_WEIGHT_2 , 5); + REG_SET_SLICE(isp_wdr4_value_weight , WDR4_VALUE_WEIGHT_3 , 16); + isp_write_reg(dev, REG_ADDR(isp_wdr4_value_weight), isp_wdr4_value_weight); + + slice_block_width = width / WDR4_WW; + slice_block_height = height / WDR4_HH; + isp_wdr4_block_size = 0; + REG_SET_SLICE(isp_wdr4_block_size, WDR4_BLOCK_WIDTH, slice_block_width); + REG_SET_SLICE(isp_wdr4_block_size, WDR4_BLOCK_HEIGHT, slice_block_height); + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_size), isp_wdr4_block_size); + + slice_block_area_inverse = + WDR4_NORMALIZE * WDR4_NORMALIZE / (slice_block_width * + slice_block_height); + isp_wdr4_block_area_factor = isp_read_reg(dev, REG_ADDR(isp_wdr4_block_area_factor)); + REG_SET_SLICE(isp_wdr4_block_area_factor, WDR4_BLOCK_AREA_INVERSE, slice_block_area_inverse); + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_area_factor), isp_wdr4_block_area_factor); + + slice_sigma_height = + WDR4_NORMALIZE * WDR4_NORMALIZE / slice_block_height; + slice_sigma_width = WDR4_NORMALIZE * WDR4_NORMALIZE / slice_block_width; + slice_sigma_value = WDR4_NORMALIZE * WDR4_NORMALIZE/ WDR4_MAX_VALUE; + + isp_wdr4_sigma_width = + isp_read_reg(dev, REG_ADDR(isp_wdr4_sigma_width)); + REG_SET_SLICE(isp_wdr4_sigma_width, WDR4_BILITERAL_WIDTH_SIGMA, + slice_sigma_width); + isp_write_reg(dev, REG_ADDR(isp_wdr4_sigma_width), + isp_wdr4_sigma_width); + + isp_wdr4_sigma_height = isp_read_reg(dev, REG_ADDR(isp_wdr4_sigma_height)); + REG_SET_SLICE(isp_wdr4_sigma_height, WDR4_BILITERAL_HEIGHT_SIGMA, + slice_sigma_height); + isp_write_reg(dev, REG_ADDR(isp_wdr4_sigma_height), + isp_wdr4_sigma_height); + + isp_wdr4_sigma_value = isp_read_reg(dev, REG_ADDR(isp_wdr4_sigma_value)); + REG_SET_SLICE(isp_wdr4_sigma_value, WDR4_BILITERAL_VALUE_SIGMA, + slice_sigma_value); + isp_write_reg(dev, REG_ADDR(isp_wdr4_sigma_value), + isp_wdr4_sigma_value); + + /* block flag configuration */ + width_left = width - slice_block_width * WDR4_WW; + height_left = height - slice_block_height * WDR4_HH; + + + // isp_wdr4_gain_shift_bit = 8; + // isp_wdr4_normalize_shift = 10; + slice_pixel_shift = MODULE_INPUT_BIT_DEPTH - 15; + slice_output_shift = MODULE_INPUT_BIT_DEPTH - MODULE_OUTPUT_BIT_DEPTH; + + + isp_wdr4_shift = isp_read_reg(dev, REG_ADDR(isp_wdr4_shift)); + REG_SET_SLICE(isp_wdr4_shift, WDR4_PIXEL_SHIFT_BIT, slice_pixel_shift); + REG_SET_SLICE(isp_wdr4_shift, WDR4_OUTPUT_SHIFT_BIT, + slice_output_shift); + isp_write_reg(dev, REG_ADDR(isp_wdr4_shift), isp_wdr4_shift); + + + /* block flag configuration */ + width_left = width - slice_block_width * WDR4_WW; + height_left = height - slice_block_height * WDR4_HH; + + isp_wdr4_block_flag_width = 0; + isp_wdr4_block_flag_height = 0; + + for (i = 0, width_count = 0; + (i < WDR4_WW) && (width_count < width_left); i++, width_count++) { + isp_wdr4_block_flag_width |= (1 << i); + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_flag_width), isp_wdr4_block_flag_width); + + for (i = 0, height_count = 0; + (i < WDR4_HH) && (height_count < height_left); + i++, height_count++) { + isp_wdr4_block_flag_height |= (1 << i); + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_flag_height), isp_wdr4_block_flag_height); + + isp_wdr4_block_size = isp_read_reg(dev, REG_ADDR(isp_wdr4_block_size)); + REG_SET_SLICE(isp_wdr4_block_size, WDR4_BLOCK_WIDTH, slice_block_width); + REG_SET_SLICE(isp_wdr4_block_size, WDR4_BLOCK_HEIGHT, + slice_block_height); + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_size), isp_wdr4_block_size); + + wdr4_config_curve(dev); +#if 1 + { + uint32_t isp_wdr4_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr4_ctrl)); + REG_SET_SLICE(isp_wdr4_ctrl, WDR4_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_wdr4_ctrl), isp_wdr4_ctrl); + } +#endif +} + +int isp_enable_wdr4(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V4 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + int32_t isp_wdr4_ctrl; + struct isp_wdr4_context *wdr4 = &dev->wdr4; + isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl)); + isp_read_reg(dev, REG_ADDR(isp_dmsc_cac_y_norm_shd)); + + isp_wdr4_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr4_ctrl)); + wdr4->enable = true; + REG_SET_SLICE(isp_wdr4_ctrl, WDR4_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_wdr4_ctrl), isp_wdr4_ctrl); + + return 0; +#endif +} + +int isp_disable_wdr4(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V4 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_wdr4_context *wdr4 = &dev->wdr4; + int32_t isp_wdr4_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr4_ctrl)); + wdr4->enable = false; + REG_SET_SLICE(isp_wdr4_ctrl, WDR4_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_wdr4_ctrl), isp_wdr4_ctrl); + + return 0; +#endif +} + +int isp_u_wdr4(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V4 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + wdr4_hw_init(dev); + return 0; +#endif +} + +int isp_s_wdr4(struct isp_ic_dev *dev) +{ + +#ifndef ISP_WDR_V4 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_wdr4_context *wdr4 = &dev->wdr4; + u32 isp_wdr4_strength_0 = isp_read_reg(dev, REG_ADDR(isp_wdr4_strength_0)); + u32 isp_wdr4_strength_1 = isp_read_reg(dev, REG_ADDR(isp_wdr4_strength_1)); + u32 isp_wdr4_contrast = isp_read_reg(dev, REG_ADDR(isp_wdr4_contrast)); + u32 width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size)); + u32 height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size)); + width /= 32; + height /= 32; + + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_LOW_STRENGTH, wdr4->low_gain); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_GLOBAL_STRENGTH, + wdr4->global_strength); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_LOCAL_STRENGTH, 128); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_TOTAL_STRENGTH, wdr4->strength); + REG_SET_SLICE(isp_wdr4_strength_1, WDR4_HIGH_STRENGTH, wdr4->high_strength); + + REG_SET_SLICE(isp_wdr4_contrast , WDR4_CONTRAST, wdr4->contrast); //valid values:[-1023~1023]:control contrast of image,.higher:image have stronger contrast + REG_SET_SLICE(isp_wdr4_contrast , WDR4_FLAT_STRENGTH, wdr4->flat_strength);//valid values:[0, 19]:adjust flat area. Higher:flat area stretched more strong + REG_SET_SLICE(isp_wdr4_contrast , WDR4_FLAT_THR, wdr4->flat_threshold); //valid values:[0, 20]:judge flat region. + isp_write_reg(dev, REG_ADDR(isp_wdr4_contrast), isp_wdr4_contrast); + + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_size), + width | (height << 9)); + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_0), isp_wdr4_strength_0); + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_1), isp_wdr4_strength_1); + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_0_shd), isp_wdr4_strength_0); /* cmodel use */ + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_1_shd), isp_wdr4_strength_1); /* cmodel use */ + + return 0; +#endif +} +#endif + diff --git a/vvcam/isp/mrv_all_bits.h b/vvcam/isp/mrv_all_bits.h new file mode 100755 index 0000000..59d96ac --- /dev/null +++ b/vvcam/isp/mrv_all_bits.h @@ -0,0 +1,10446 @@ +/****************************************************************************** + * + * Copyright 2010, Dream Chip Technologies GmbH. All rights reserved. + * + **************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef __MRV_ALL_BITS_H__ +#define __MRV_ALL_BITS_H__ + +/*****************************************************************************/ +/* this includes the registermap generated by SIG-flow */ +/*****************************************************************************/ +#ifndef __KERNEL__ +#include +#else +#include +#endif +#include "mrv_all_regs.h" + +/*****************************************************************************/ +/* this includes the hw version information */ +/*****************************************************************************/ +#include "isp_version.h" + +/*****************************************************************************/ +/* Marvin Main Control Registers */ +/*****************************************************************************/ +#define ALIGN_16BYTE(width) (((width) + (0xF - 1)) & (~(0xF - 1))) +#define ALIGN_32BYTE(width) (((width) + 31) & (~31)) + +/*****************************************************************************/ +/** + * register: vi_ccl: Data path control register (0x0000) + * + *****************************************************************************/ +/* Slice: vi_ccl_dis:*/ +/* Clock Control Logic disable */ +/* 0: processing/cfg-clocks for all marvin sub modules enabled */ +/* 1: processing/cfg-clocks for all marvin sub modules disabled w/o access to ID and VI_CCL register */ +#ifdef MRV_VI_CCL_DIS +#define MRV_VI_CCL_ENABLE_CLOCKS 0 +#define MRV_VI_CCL_DISABLE_CLOCKS 1 +#endif /* MRV_VI_CCL_DIS */ + +/*****************************************************************************/ +/** + * register: vi_id: Revision identification register (0x0008) + * + *****************************************************************************/ +/* Slice: rev_id:*/ +/* MARVIN5 revision IDs */ +#ifdef MRV_REV_ID +#endif /* MRV_REV_ID */ + +/*****************************************************************************/ +/** + * register: vi_iccl: Internal clock control register (0x0010) + * + *****************************************************************************/ + /* Slice: vi_mipi_clk_enable: */ + /* MIPI interface clock enable */ + /* 1: processing mode */ + /* 0: power safe */ +#ifdef MRV_VI_MIPI_CLK_ENABLE +#endif /* MRV_VI_MIPI_CLK_ENABLE */ + +/* Slice: vi_smia_clk_enable:*/ +/* SMIA interface clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_SMIA_CLK_ENABLE +#endif /* MRV_VI_SMIA_CLK_ENABLE */ + +/* Slice: vi_simp_clk_enable:*/ +/* Superimpose clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_SIMP_CLK_ENABLE +#endif /* MRV_VI_SIMP_CLK_ENABLE */ + +/* Slice: vi_ie_clk_enable:*/ +/* Image effect clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_IE_CLK_ENABLE +#endif /* MRV_VI_IE_CLK_ENABLE */ + +/* Slice: vi_mi_clk_enable:*/ +/* memory interface clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_MI_CLK_ENABLE +#endif /* MRV_VI_MI_CLK_ENABLE */ + +/* Slice: vi_jpeg_clk_enable:*/ +/* JPEG encoder clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_JPEG_CLK_ENABLE +#endif /* MRV_VI_JPEG_CLK_ENABLE */ + +/* Slice: vi_srsz_clk_enable:*/ +/* main resize clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_SRSZ_CLK_ENABLE +#endif /* MRV_VI_SRSZ_CLK_ENABLE */ + +/* Slice: vi_mrsz_clk_enable:*/ +/* main resize clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_MRSZ_CLK_ENABLE +#endif /* MRV_VI_MRSZ_CLK_ENABLE */ + +/* Slice: vi_cp_clk_enable:*/ +/* color processing clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_CP_CLK_ENABLE +#endif /* MRV_VI_CP_CLK_ENABLE */ + +/* Slice: vi_isp_clk_enable:*/ +/* isp processing clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_ISP_CLK_ENABLE +#endif /* MRV_VI_ISP_CLK_ENABLE */ + +/*****************************************************************************/ +/** + * register: vi_ircl: Internal reset control register (0x0014) + * + *****************************************************************************/ +/* Slice: vi_mipi_soft_rst:*/ +/* MIPI Interface software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_MIPI_SOFT_RST +#endif /* MRV_VI_MIPI_SOFT_RST */ + +/* Slice: vi_smia_soft_rst:*/ +/* SMIA Interface software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_SMIA_SOFT_RST +#endif /* MRV_VI_SMIA_SOFT_RST */ + +/* Slice: vi_simp_soft_rst:*/ +/* Superimpose software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_SIMP_SOFT_RST +#endif /* MRV_VI_SIMP_SOFT_RST */ + +/* Slice: vi_ie_soft_rst:*/ +/* Image effect software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_IE_SOFT_RST +#endif /* MRV_VI_IE_SOFT_RST */ + +/* Slice: vi_marvin_rst:*/ +/* Soft reset of entire marvin */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_MARVIN_RST +#endif /* MRV_VI_MARVIN_RST */ + +/* Slice: vi_mi_soft_rst:*/ +/* memory interface software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_MI_SOFT_RST +#endif /* MRV_VI_MI_SOFT_RST */ + +/* Slice: vi_jpeg_soft_rst:*/ +/* JPEG encoder software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_JPEG_SOFT_RST +#endif /* MRV_VI_JPEG_SOFT_RST */ + +/* Slice: vi_srsz_soft_rst:*/ +/* Self-picture resize software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_SRSZ_SOFT_RST +#endif /* MRV_VI_SRSZ_SOFT_RST */ + +/* Slice: vi_mrsz_soft_rst:*/ +/* Main-picture resize software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_MRSZ_SOFT_RST +#endif /* MRV_VI_MRSZ_SOFT_RST */ + +/* Slice: vi_ycs_soft_rst:*/ +/* y/c splitter software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_YCS_SOFT_RST +#endif /* MRV_VI_YCS_SOFT_RST */ + +/* Slice: vi_cp_soft_rst:*/ +/* color processing software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_CP_SOFT_RST +#endif /* MRV_VI_CP_SOFT_RST */ + +/* Slice: vi_isp_soft_rst:*/ +/* isp software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_ISP_SOFT_RST +#endif /* MRV_VI_ISP_SOFT_RST */ + +/*****************************************************************************/ +/** + * register: vi_dpcl: Data path control register (0x0018) + * + *****************************************************************************/ +/* Slice: vi_dma_spmux:*/ +/* 0: data from camera interface to self resize */ +/* 1: data from DMA read port to self resize */ +#ifdef MRV_VI_DMA_SPMUX +#define MRV_VI_DMA_SPMUX_CAM 0 /* 0: data from camera interface to self resize */ +#define MRV_VI_DMA_SPMUX_DMA 1 /* 1: data from DMA read port to self resize */ +#endif /* MRV_VI_DMA_SPMUX */ + +/* Slice: vi_dma_iemux:*/ +/* 0: data from camera interface to image effects */ +/* 1: data from DMA read port to image effects */ +#ifdef MRV_VI_DMA_IEMUX +#define MRV_VI_DMA_IEMUX_CAM 0 /* 0: data from camera interface to image effects */ +#define MRV_VI_DMA_IEMUX_DMA 1 /* 1: data from DMA read port to image effects */ +#endif /* MRV_VI_DMA_IEMUX */ + +/* Slice: if_select:*/ +/* selects input interface */ +/* 0: parallel interface */ +/* 1: SMIA-interface */ +/* 2: MIPI-interface */ +#ifdef MRV_IF_SELECT +#define MRV_IF_SELECT_PAR 0 /* 0: parallel interface */ +#define MRV_IF_SELECT_SMIA 1 /* 1: SMIA-interface */ +#define MRV_IF_SELECT_MIPI 2 /* 2: MIPI-interface */ +#define MRV_IF_SELECT_HDR 3 /* 2: HDR-interface */ +#endif /* MRV_IF_SELECT */ + +/* Slice: vi_dma_switch:*/ +/* DMA read data path selector */ +/* 0: path to SPMUX */ +/* 1: path to Superimpose */ +/* 2: path to Image Effects */ +/* 3: reserved (for path to JPEG)*/ +/* 4..7: reserved */ +#ifdef MRV_VI_DMA_SWITCH +#define MRV_VI_DMA_SWITCH_SELF 0 /* 0: path to SPMUX */ +#define MRV_VI_DMA_SWITCH_SIMP 1 /* 1: path to Superimpose */ +#define MRV_VI_DMA_SWITCH_IE 2 /* 2: path to Image Effects */ +#define MRV_VI_DMA_SWITCH_JPG 3 /* 3: path to JPEG */ +#define MRV_VI_DMA_SWITCH_ISP 4 /* 4: path to ISP */ +#endif /* MRV_VI_DMA_SWITCH */ + +/* Slice: vi_chan_mode:*/ +/* Y/C splitter channel mode */ +/* 0: disabled */ +/* 1: main path and raw data mode */ +/* 2: self path mode */ +/* 3: main and self path mode */ +#ifdef MRV_VI_CHAN_MODE +#define MRV_VI_CHAN_MODE_OFF 0x00 /* 0: disabled */ +#define MRV_VI_CHAN_MODE_Y 0xFF /* not supported */ +#define MRV_VI_CHAN_MODE_MP_RAW 0x01 /* 1: main path and raw data mode */ +#define MRV_VI_CHAN_MODE_MP 0x01 /* 1: main path and raw data mode */ +#define MRV_VI_CHAN_MODE_SP 0x02 /* 2: self path mode */ +#define MRV_VI_CHAN_MODE_MP_SP 0x03 /* 3: main and self path mode */ +#define MRV_VI_CHAN_MODE_SP2 0x04 /* 4: self2 path mode */ +#define MRV_VI_CHAN_MODE_MP_SP2 0x05 /* 5: main and self2 path mode */ +#define MRV_VI_CHAN_MODE_SP_SP2 0x06 /* 6: self and self2 path mode */ +#define MRV_VI_CHAN_MODE_MP_SP_SP2 0x07 /* 7: main self and self2 path mode */ + +#endif /* MRV_VI_CHAN_MODE */ + +/* Slice: vi_mp_mux:*/ +/* data path selector for main path */ +/* 00: reserved (future: data from DMA read port to JPEG encoder)*/ +/* 01: data from main resize to MI, uncompressed */ +/* 10: data from main resize to JPEG encoder */ +/* 11: reserved */ +#ifdef MRV_VI_MP_MUX +#define MRV_VI_MP_MUX_JPGDIRECT 0x00 /* 00: reserved (future: data from DMA read port to JPEG encoder) */ +#define MRV_VI_MP_MUX_MP 0x01 /* 01: data from main resize to MI, uncompressed */ +#define MRV_VI_MP_MUX_RAW 0x01 /* (now also used for RAW data bypass) */ +#define MRV_VI_MP_MUX_JPEG 0x02 /* 10: data from main resize to JPEG encoder */ +#endif /* MRV_VI_MP_MUX */ + +/*****************************************************************************/ +/* Image Effects Registers */ +/*****************************************************************************/ + +/*****************************************************************************/ +/** + * register: img_eff_ctrl: Global control register (0x0000) + * + *****************************************************************************/ +/* Slice: full_range:*/ +/* write 0: pixel value range according to BT.601 */ +/* write 1: YCbCr full range 0...255 */ +#ifdef MRV_IMGEFF_FULL_RANGE +#define MRV_IMGEFF_FULL_RANGE_FULL 1 /* 1: YCbCr full range 0...255 */ +#define MRV_IMGEFF_FULL_RANGE_BT601 0 /* 0: pixel value range according to BT.601 */ +#endif /* MRV_IMGEFF_FULL_RANGE */ + +/* Slice: cfg_upd:*/ +/* write 0: nothing happens */ +/* write 1: update shadow registers */ +/* read: always 0 */ +#ifdef MRV_IMGEFF_CFG_UPD +#define MRV_IMGEFF_CFG_UPD_NOTHING 0 /* 0: nothing happens */ +#define MRV_IMGEFF_CFG_UPD_UPDATE 1 /* 1: update shadow registers */ +#endif /* MRV_IMGEFF_CFG_UPD */ + +/* Slice: effect_mode:*/ +/* effect mode */ +/* 000: black & white effect (grayscale)*/ +/* 001: negative effect */ +/* 010: sepia effect */ +/* 011: color selection effect */ +/* 100: emboss effect */ +/* 101: sketch effect */ +/* 110: sharpen effect */ +/* 111: reserved */ +#ifdef MRV_IMGEFF_EFFECT_MODE +#define MRV_IMGEFF_EFFECT_MODE_GRAY 0 /* 000: black & white effect (grayscale) */ +#define MRV_IMGEFF_EFFECT_MODE_NEGATIVE 1 /* 001: negative effect */ +#define MRV_IMGEFF_EFFECT_MODE_SEPIA 2 /* 010: sepia effect */ +#define MRV_IMGEFF_EFFECT_MODE_COLOR_SEL 3 /* 011: color selection effect */ +#define MRV_IMGEFF_EFFECT_MODE_EMBOSS 4 /* 100: emboss effect */ +#define MRV_IMGEFF_EFFECT_MODE_SKETCH 5 /* 101: sketch effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHARPEN 6 /* 110: sharpen effect */ +#endif /* MRV_IMGEFF_EFFECT_MODE */ + +/* Slice: bypass_mode:*/ +/* bypass mode */ +/* 1: processing is activated */ +/* 0: processing is deactivated, bypass mode is selected */ +#ifdef MRV_IMGEFF_BYPASS_MODE +#define MRV_IMGEFF_BYPASS_MODE_PROCESS 1 /* 1: processing is activated */ +#define MRV_IMGEFF_BYPASS_MODE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */ +#endif /* MRV_IMGEFF_BYPASS_MODE */ + +/*****************************************************************************/ +/** + * register: img_eff_color_sel: Color selection register (for + * color selection effect) (0x0004) + * + *****************************************************************************/ +/* Slice: color_threshold:*/ +/* Threshold value of the RGB colors for the color selection effect.*/ +#ifdef MRV_IMGEFF_COLOR_THRESHOLD +#endif /* MRV_IMGEFF_COLOR_THRESHOLD */ + +/* Slice: color_selection:*/ +/* Defining the maintained color:*/ +/* 000: red green and blue */ +/* 001: blue */ +/* 010: green */ +/* 011: green and blue */ +/* 100: red */ +/* 101: red and blue */ +/* 110: red and green */ +/* 111: red green and blue */ +#ifdef MRV_IMGEFF_COLOR_SELECTION +#define MRV_IMGEFF_COLOR_SELECTION_RGB 0 /* 000: red green and blue */ +#define MRV_IMGEFF_COLOR_SELECTION_B 1 /* 001: blue */ +#define MRV_IMGEFF_COLOR_SELECTION_G 2 /* 010: green */ +#define MRV_IMGEFF_COLOR_SELECTION_BG 3 /* 011: green and blue */ +#define MRV_IMGEFF_COLOR_SELECTION_R 4 /* 100: red */ +#define MRV_IMGEFF_COLOR_SELECTION_RB 5 /* 101: red and blue */ +#define MRV_IMGEFF_COLOR_SELECTION_RG 6 /* 110: red and green */ +#define MRV_IMGEFF_COLOR_SELECTION_BGR 7 /* 111: red green and blue */ +#endif /* MRV_IMGEFF_COLOR_SELECTION */ + +/* Slice: emb_coef_21_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_21_EN +#endif /* MRV_IMGEFF_EMB_COEF_21_EN */ + +/* Slice: emb_coef_21:*/ +/* second line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_21 +#define MRV_IMGEFF_EMB_COEF_21_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_21_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_21_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_21_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_21_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_21_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_21_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_21_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_21 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_21_4 +#define MRV_IMGEFF_EMB_COEF_21_4_MASK 0x0000F000 +#define MRV_IMGEFF_EMB_COEF_21_4_SHIFT 12 + +/* Slice: emb_coef_13_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_13_EN +#endif /* MRV_IMGEFF_EMB_COEF_13_EN */ + +/* Slice: emb_coef_13:*/ +/* first line, right entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_13 +#define MRV_IMGEFF_EMB_COEF_13_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_13_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_13_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_13_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_13_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_13_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_13_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_13_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_13 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_13_4 +#define MRV_IMGEFF_EMB_COEF_13_4_MASK 0x00000F00 +#define MRV_IMGEFF_EMB_COEF_13_4_SHIFT 8 + +/* Slice: emb_coef_12_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_12_EN +#endif /* MRV_IMGEFF_EMB_COEF_12_EN */ + +/* Slice: emb_coef_12:*/ +/* first line, middle entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_12 +#define MRV_IMGEFF_EMB_COEF_12_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_12_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_12_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_12_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_12_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_12_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_12_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_12_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_12 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_12_4 +#define MRV_IMGEFF_EMB_COEF_12_4_MASK 0x000000F0 +#define MRV_IMGEFF_EMB_COEF_12_4_SHIFT 4 + +/* Slice: emb_coef_11_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_11_EN +#define MRV_IMGEFF_EMB_COEF_11_EN_ON 1 +#define MRV_IMGEFF_EMB_COEF_11_EN_OFF 0 +#endif /* MRV_IMGEFF_EMB_COEF_11_EN */ + +/* Slice: emb_coef_11:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_11 +#define MRV_IMGEFF_EMB_COEF_11_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_11_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_11_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_11_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_11_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_11_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_11_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_11_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_11 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_11_4 +#define MRV_IMGEFF_EMB_COEF_11_4_MASK 0x0000000F +#define MRV_IMGEFF_EMB_COEF_11_4_SHIFT 0 + +/* Slice: emb_coef_32_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_32_EN +#endif /* MRV_IMGEFF_EMB_COEF_32_EN */ + +/* Slice: emb_coef_32:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_32 +#define MRV_IMGEFF_EMB_COEF_32_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_32_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_32_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_32_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_32_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_32_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_32_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_32_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_32 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_32_4 +#define MRV_IMGEFF_EMB_COEF_32_4_MASK 0x0000F000 +#define MRV_IMGEFF_EMB_COEF_32_4_SHIFT 12 + +/* Slice: emb_coef_31_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_31_EN +#endif /* MRV_IMGEFF_EMB_COEF_31_EN */ + +/* Slice: emb_coef_31:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_31 +#define MRV_IMGEFF_EMB_COEF_31_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_31_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_31_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_31_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_31_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_31_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_31_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_31_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_31 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_31_4 +#define MRV_IMGEFF_EMB_COEF_31_4_MASK 0x00000F00 +#define MRV_IMGEFF_EMB_COEF_31_4_SHIFT 8 + +/* Slice: emb_coef_23_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_23_EN +#endif /* MRV_IMGEFF_EMB_COEF_23_EN */ + +/* Slice: emb_coef_23:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_23 +#define MRV_IMGEFF_EMB_COEF_23_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_23_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_23_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_23_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_23_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_23_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_23_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_23_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_23 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_23_4 +#define MRV_IMGEFF_EMB_COEF_23_4_MASK 0x000000F0 +#define MRV_IMGEFF_EMB_COEF_23_4_SHIFT 4 + +/* Slice: emb_coef_22_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_22_EN +#endif /* MRV_IMGEFF_EMB_COEF_22_EN */ + +/* Slice: emb_coef_22:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_22 +#define MRV_IMGEFF_EMB_COEF_22_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_22_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_22_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_22_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_22_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_22_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_22_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_22_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_22 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_22_4 +#define MRV_IMGEFF_EMB_COEF_22_4_MASK 0x0000000F +#define MRV_IMGEFF_EMB_COEF_22_4_SHIFT 0 + +/*****************************************************************************/ +/** + * register: img_eff_mat_3: 3x3 matrix coefficients for emboss(3) effect / + * sketch(1) effect (0x0010) + * + *****************************************************************************/ +/* Slice: sket_coef_13_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_13_EN +#endif /* MRV_IMGEFF_SKET_COEF_13_EN */ + +/* Slice: sket_coef_13:*/ +/* first line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_13 +#define MRV_IMGEFF_SKET_COEF_13_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_13_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_13_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_13_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_13_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_13_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_13_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_13_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_13 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_13_4 +#define MRV_IMGEFF_SKET_COEF_13_4_MASK 0x0000F000 +#define MRV_IMGEFF_SKET_COEF_13_4_SHIFT 12 + +/* Slice: sket_coef_12_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_12_EN +#endif /* MRV_IMGEFF_SKET_COEF_13_EN */ + +/* Slice: sket_coef_12:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_12 +#define MRV_IMGEFF_SKET_COEF_12_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_12_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_12_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_12_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_12_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_12_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_12_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_12_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_12 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_12_4 +#define MRV_IMGEFF_SKET_COEF_12_4_MASK 0x00000F00 +#define MRV_IMGEFF_SKET_COEF_12_4_SHIFT 8 + +/* Slice: sket_coef_11_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_11_EN +#endif /* MRV_IMGEFF_SKET_COEF_13_EN */ + +/* Slice: sket_coef_11:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_11 +#define MRV_IMGEFF_SKET_COEF_11_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_11_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_11_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_11_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_11_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_11_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_11_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_11_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_11 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_11_4 +#define MRV_IMGEFF_SKET_COEF_11_4_MASK 0x000000F0 +#define MRV_IMGEFF_SKET_COEF_11_4_SHIFT 4 + +/* Slice: emb_coef_33_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_33_EN +#endif /* MRV_IMGEFF_EMB_COEF_33_EN */ + +/* Slice: emb_coef_33:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_3 +#define MRV_IMGEFF_EMB_COEF_33_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_33_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_33_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_33_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_33_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_33_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_33_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_33_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_33 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_33_4 +#define MRV_IMGEFF_EMB_COEF_33_4_MASK 0x0000000F +#define MRV_IMGEFF_EMB_COEF_33_4_SHIFT 0 + +/*****************************************************************************/ +/** + * register: img_eff_mat_4: 3x3 matrix coefficients for sketch effect (2) + * (0x0014) + * + *****************************************************************************/ +/* Slice: sket_coef_31_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_31_EN +#endif /* MRV_IMGEFF_SKET_COEF_31_EN */ + +/* Slice: sket_coef_31:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_31 +#define MRV_IMGEFF_SKET_COEF_31_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_31_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_31_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_31_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_31_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_31_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_31_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_31_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_31 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_31_4 +#define MRV_IMGEFF_SKET_COEF_31_4_MASK 0x0000F000 +#define MRV_IMGEFF_SKET_COEF_31_4_SHIFT 12 + +/* Slice: sket_coef_23_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_23_EN +#endif /* MRV_IMGEFF_SKET_COEF_23_EN */ + +/* Slice: sket_coef_23:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_23 +#define MRV_IMGEFF_SKET_COEF_23_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_23_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_23_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_23_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_23_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_23_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_23_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_23_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_23 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_23_4 +#define MRV_IMGEFF_SKET_COEF_23_4_MASK 0x00000F00 +#define MRV_IMGEFF_SKET_COEF_23_4_SHIFT 8 + +/* Slice: sket_coef_22_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_22_EN +#endif /* MRV_IMGEFF_SKET_COEF_22_EN */ + +/* Slice: sket_coef_22:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_22 +#define MRV_IMGEFF_SKET_COEF_22_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_22_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_22_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_22_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_22_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_22_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_22_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_22_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_22 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_22_4 +#define MRV_IMGEFF_SKET_COEF_22_4_MASK 0x000000F0 +#define MRV_IMGEFF_SKET_COEF_22_4_SHIFT 4 + +/* Slice: sket_coef_21_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_21_EN +#endif /* MRV_IMGEFF_SKET_COEF_21_EN */ + +/* Slice: sket_coef_21:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_21 +#define MRV_IMGEFF_SKET_COEF_21_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_21_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_21_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_21_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_21_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_21_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_21_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_21_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_21 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_21_4 +#define MRV_IMGEFF_SKET_COEF_21_4_MASK 0x0000000F +#define MRV_IMGEFF_SKET_COEF_21_4_SHIFT 0 + +/*****************************************************************************/ +/** + * register: img_eff_mat_5: 3x3 matrix coefficients for sketch effect (3) + * (0x0018) + * + *****************************************************************************/ +/* Slice: sket_coef_33_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_33_EN +#endif /* MRV_IMGEFF_SKET_COEF_33_EN */ + +/* Slice: sket_coef_33:*/ +/* third line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_33 +#define MRV_IMGEFF_SKET_COEF_33_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_33_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_33_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_33_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_33_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_33_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_33_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_33_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_33 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_33_4 +#define MRV_IMGEFF_SKET_COEF_33_4_MASK 0x000000F0 +#define MRV_IMGEFF_SKET_COEF_33_4_SHIFT 4 + +/* Slice: sket_coef_32_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_32_EN +#endif /* MRV_IMGEFF_SKET_COEF_32_EN */ + +/* Slice: sket_coef_32:*/ +/* third line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_32 +#define MRV_IMGEFF_SKET_COEF_32_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_32_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_32_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_32_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_32_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_32_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_32_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_32_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_32 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_32_4 +#define MRV_IMGEFF_SKET_COEF_32_4_MASK 0x0000000F +#define MRV_IMGEFF_SKET_COEF_32_4_SHIFT 0 + +/* valid for all coeffiecient definitions */ +#define MRV_IMGEFF_COEF +#define MRV_IMGEFF_COEF_ONE 0U +#define MRV_IMGEFF_COEF_TWO 1U /* 001: (2) */ +#define MRV_IMGEFF_COEF_FOUR 2U /* 010: (4) */ +#define MRV_IMGEFF_COEF_EIGHT 3U /* 011: (8) */ +#define MRV_IMGEFF_COEF_MIN_ONE 4U /* 100: (-1) */ +#define MRV_IMGEFF_COEF_MIN_TWO 5U /* 101: (-2) */ +#define MRV_IMGEFF_COEF_MIN_FOUR 6U /* 110: (-4) */ +#define MRV_IMGEFF_COEF_MIN_EIGHT 7U /* 111: (-8) */ + +#define MRV_IMGEFF_COEF_ON 1U /* 1: coefficient enabled */ +#define MRV_IMGEFF_COEF_OFF 0U /* 0: coefficient disabled */ +#define MRV_IMGEFF_COEF_SHIFT 3U /* shift for enable bit */ + +/*****************************************************************************/ +/** + * register: img_eff_tint: Chrominance increment values of a tint + * (used for sepia effect) (0x001c) + * + *****************************************************************************/ +/* Slice: incr_cr:*/ +/* Cr increment value of a tint. 7 bits for value, 1 sign bit.*/ +/* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/ +#ifdef MRV_IMGEFF_INCR_CR +#endif /* MRV_IMGEFF_INCR_CR */ + +/* Slice: incr_cb:*/ +/* Cb increment value of a tint. 7 bits for value, 1 sign bit.*/ +/* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/ +#ifdef MRV_IMGEFF_INCR_CB +#endif /* MRV_IMGEFF_INCR_CB */ + +/*****************************************************************************/ +/** + * register: img_eff_ctrl_shd: Shadow register for control register (0x0020) + * + *****************************************************************************/ +/* Slice: effect_mode_shd:*/ +/* effect mode */ +/* 000: black & white effect (grayscale)*/ +/* 001: negative effect */ +/* 010: sepia effect */ +/* 011: color selection effect */ +/* 100: emboss effect */ +/* 101: sketch effect */ +/* 110-111: not used */ +#ifdef MRV_IMGEFF_EFFECT_MODE_SHD +#define MRV_IMGEFF_EFFECT_MODE_SHD_GRAY 0 /* 000: black & white effect (grayscale) */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_NEGATIVE 1 /* 001: negative effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_SEPIA 2 /* 010: sepia effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_COLOR_SEL 3 /* 011: color selection effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_EMBOSS 4 /* 100: emboss effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_SKETCH 5 /* 101: sketch effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_SHARPEN 6 /* 110: sharpen effect */ +#endif /* MRV_IMGEFF_EFFECT_MODE_SHD */ + +/*****************************************************************************/ +/* Super Impose Registers */ +/*****************************************************************************/ + +/*****************************************************************************/ +/** + * register: super_imp_ctrl: Global control register (0x0000) + * + *****************************************************************************/ +/* Slice: transparency_mode:*/ +/* transparency mode */ +/* 1: transparency mode disabled */ +/* 0: transparency mode enabled */ +#ifdef MRV_SI_TRANSPARENCY_MODE +#define MRV_SI_TRANSPARENCY_MODE_DISABLED 1 /* 1: transparency mode disabled */ +#define MRV_SI_TRANSPARENCY_MODE_ENABLED 0 /* 0: transparency mode enabled */ +#endif /* MRV_SI_TRANSPARENCY_MODE */ + +/* Slice: ref_image:*/ +/* Define the reference image */ +/* 1: superimpose bitmap from main memory */ +/* 0: image from the Image Effect module */ +/* Note: the reference image defines the size of the output image */ +#ifdef MRV_SI_REF_IMAGE +#define MRV_SI_REF_IMAGE_MEM 1 /* 1: superimpose bitmap from main memory */ +#define MRV_SI_REF_IMAGE_IE 0 /* 0: image from the Image Effect module */ +#endif /* MRV_SI_REF_IMAGE */ + +/* Slice: bypass_mode:*/ +/* bypass mode */ +/* 1: processing is activated */ +/* 0: processing is deactivated, bypass mode is selected */ +#ifdef MRV_SI_BYPASS_MODE +#define MRV_SI_BYPASS_MODE_PROCESS 1 /* 1: processing is activated */ +#define MRV_SI_BYPASS_MODE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */ +#endif /* MRV_IMGEFF_BYPASS_MODE */ + +/*****************************************************************************/ +/** + * register: super_imp_offset_x: Offset x register (0x0004) + * + *****************************************************************************/ +/* Slice: offset_x:*/ +/* Offset X */ +/* Note: the bit 0 is don't care (write 1 doesn't have any effect, the read access always gives 0)*/ +/* Note: the offset_x is positive and refers to the reference image */ +#ifdef MRV_SI_OFFSET_X +#endif /* MRV_SI_OFFSET_X */ + +/*****************************************************************************/ +/** + * register: super_imp_offset_y: Offset y register (0x0008) + * + *****************************************************************************/ +/* Slice: offset_y:*/ +/* Offset Y */ +/* Note: the offset_y is positive and refers to the reference image */ +#ifdef MRV_SI_OFFSET_Y +#endif /* MRV_SI_OFFSET_Y */ + +/*****************************************************************************/ +/** + * register: super_imp_color_y: Y component of transparent key color (0x000c) + * + *****************************************************************************/ +/* Slice: y_comp:*/ +/* Y component of transparent key color */ +#ifdef MRV_SI_Y_COMP +#endif /* MRV_SI_Y_COMP */ + +/*****************************************************************************/ +/** + * register: super_imp_color_cb: Cb component of transparent key color (0x0010) + * + *****************************************************************************/ +/* Slice: cb_comp:*/ +/* Cb component of transparent key color */ +#ifdef MRV_SI_CB_COMP +#endif /* MRV_SI_CB_COMP */ + +/*****************************************************************************/ +/** + * register: super_imp_color_cr: Cr component of transparent key color (0x0014) + * + *****************************************************************************/ +/* Slice: cr_comp:*/ +/* Cr component of transparent key color */ +#ifdef MRV_SI_CR_COMP +#endif /* MRV_SI_CR_COMP */ + +/*****************************************************************************/ +/* ISP Registers */ +/*****************************************************************************/ + +/*****************************************************************************/ +/** + * register: isp_ctrl: global control register (0x0000) + * + *****************************************************************************/ +/* Slice: ISP_DPF_RAW_OUT */ +/*! Slice MRV_ISP_DPF_RAW_OUT:*/ +/*! 0: DPF RAW OUT is disable */ +/*! 1: DPF RAW OUT is enable */ +#ifdef ISP_DPF_RAW +#ifdef MRV_ISP_DPF_RAW_OUT +#define MRV_ISP_DPF_RAW_OUT_DISABLE 0 /* 0: DPF raw out is disable */ +#define MRV_ISP_DPF_RAW_OUT_ENABLE 1 /* 1: DPF raw out is enable */ +#endif +#endif +/* Slice: ISP_CSM_C_RANGE:*/ +/* Color Space Matrix chrominance clipping range for ISP output */ +/* 0: CbCr range 64..960 (16..240) according to ITU-R BT.601 standard */ +/* 1: full UV range 0..1023 (0..255)*/ +/* Numbers in brackets are for 8 bit resolution.*/ +#ifdef MRV_ISP_ISP_CSM_C_RANGE +#define MRV_ISP_ISP_CSM_C_RANGE_BT601 0 /* 0: CbCr range 64..960 (16..240) according to ITU-R BT.601 standard */ +#define MRV_ISP_ISP_CSM_C_RANGE_FULL 1 /* 1: full UV range 0..1023 (0..255) */ +#endif /* MRV_ISP_ISP_CSM_C_RANGE */ + +/* Slice: ISP_CSM_Y_RANGE:*/ +/* Color Space Matrix luminance clipping range for ISP output */ +/* 0: Y range 64..940 (16..235) according to ITU-R BT.601 standard */ +/* 1: full Y range 0..1023 (0..255)*/ +/* Numbers in brackets are for 8 bit resolution.*/ +#ifdef MRV_ISP_ISP_CSM_Y_RANGE +#define MRV_ISP_ISP_CSM_Y_RANGE_BT601 0 /* 0: Y range 64..940 (16..235) according to ITU-R BT.601 standard */ +#define MRV_ISP_ISP_CSM_Y_RANGE_FULL 1 /* 1: full Y range 0..1023 (0..255) */ +#endif /* MRV_ISP_ISP_CSM_Y_RANGE */ + +/* Slice: ISP_FLASH_MODE:*/ +/* 0: sensor interface works independently from flash control unit */ +/* 1: one frame is captured when signaled by flash control unit */ +#ifdef MRV_ISP_ISP_FLASH_MODE +#define MRV_ISP_ISP_FLASH_MODE_INDEP 0 /* 0: sensor interface works independently from flash control unit */ +#define MRV_ISP_ISP_FLASH_MODE_SYNC 1 /* 1: one frame is captured when signaled by flash control unit */ +#endif /* MRV_ISP_ISP_FLASH_MODE */ + +/* Slice: ISP_GAMMA_OUT_ENABLE:*/ +/* gamma ON/OFF */ +#ifdef MRV_ISP_ISP_GAMMA_OUT_ENABLE +#endif /* MRV_ISP_ISP_GAMMA_OUT_ENABLE */ + +/* Slice: ISP_GEN_CFG_UPD:*/ +/* generate vsynced config shadow signal at the output, write only */ +#ifdef MRV_ISP_ISP_GEN_CFG_UPD +#endif /* MRV_ISP_ISP_GEN_CFG_UPD */ + +/* Slice: ISP_CFG_UPD:*/ +/* immediate configure internal shadow registers, write only */ +#ifdef MRV_ISP_ISP_CFG_UPD +#endif /* MRV_ISP_ISP_CFG_UPD */ + +/* Slice: ISP_AE_ENABLE:*/ +/* auto exposure ON/OFF */ +#ifdef MRV_ISP_ISP_AE_ENABLE +#endif /* MRV_ISP_ISP_AE_ENABLE */ + +/* Slice: ISP_AWB_ENABLE:*/ +/* auto white balance ON/OFF */ +#ifdef MRV_ISP_ISP_AWB_ENABLE +#endif /* MRV_ISP_ISP_AWB_ENABLE */ + +/* Slice: ISP_GAMMA_IN_ENABLE:*/ +/* Sensor De-gamma ON/OFF */ +#ifdef MRV_ISP_ISP_GAMMA_IN_ENABLE +#define MRV_ISP_ISP_GAMMA_IN_ENABLE_ON 1U +#define MRV_ISP_ISP_GAMMA_IN_ENABLE_OFF 0U +#endif /* MRV_ISP_ISP_GAMMA_IN_ENABLE */ + +/* Slice: ISP_INFORM_ENABLE:*/ +/* input block ON/OFF (frame-synced on)*/ +#ifdef MRV_ISP_ISP_INFORM_ENABLE +#endif /* MRV_ISP_ISP_INFORM_ENABLE */ + +/* Slice: ISP_MODE:*/ +/* 000: RAW picture with BT.601 sync (ISP bypass)*/ +/* 001: ITU-R BT.656 (YUV with embedded sync)*/ +/* 010: ITU-R BT.601 (YUV input with H and Vsync signals)*/ +/* 011: Bayer RGB processing with H and Vsync signals */ +/* 100: data mode (ISP bypass, sync signals interpreted as data enable)*/ +/* 101: Bayer RGB processing with BT.656 synchronization */ +/* 110: RAW picture with ITU-R BT.656 synchronization (ISP bypass)*/ +/* 111: reserved */ + /**/ +/* Side effect:*/ +/* If RAW, BT.601, BT.656, or data mode is selected, the clock of the */ +/* ISP SRAMs (ISP line buffer, Lens Shading, Bad Pixel) is switched off.*/ +/* Only in Bayer RGB mode the clock to the SRAMs is enabled. This */ +/* further reduces power consumption.*/ +#ifdef MRV_ISP_ISP_MODE +#define MRV_ISP_ISP_MODE_RAW 0 /* 000 - RAW picture with BT.601 sync (ISP bypass) */ +#define MRV_ISP_ISP_MODE_656 1 /* 001 - ITU-R BT.656 (YUV with embedded sync) */ +#define MRV_ISP_ISP_MODE_601 2 /* 010 - ITU-R BT.601 (YUV input with H and Vsync signals) */ +#define MRV_ISP_ISP_MODE_RGB 3 /* 011 - Bayer RGB processing with H and Vsync signals */ +#define MRV_ISP_ISP_MODE_DATA 4 /* 100 - data mode (ISP bypass, sync signals interpreted as data enable) */ +#define MRV_ISP_ISP_MODE_RGB656 5 /* 101 - Bayer RGB processing with BT.656 synchronization */ +#define MRV_ISP_ISP_MODE_RAW656 6 /* 110 - RAW picture with ITU-R BT.656 synchronization (ISP bypass) */ +#endif /* MRV_ISP_ISP_MODE */ +/* Slice: ISP_ENABLE:*/ +/* MANUAL ON/OFF (controls output formatter, framesynced)*/ +#ifdef MRV_ISP_ISP_ENABLE +#endif /* MRV_ISP_ISP_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_acq_prop: ISP acquisition properties (0x0004) + * + *****************************************************************************/ +#ifdef ISP_DVP_PINMAPPING +/*! Slice: MRV_ISP_DVP_INPUT_PIN_MAPPING */ +/*! Bit Mapping for LSB to MSP for ISPNano.*/ +/*! 3'b000: normal 12-bit external interface */ +/*! 3'b001: mapping low 10 bit to high 10 bits, append 2 zeros as LSBs.*/ +/*! 3'b010: mapping low 8 bit to high 8 bits, append 4 zeros as LSBs.*/ +/*! 3'b011: mapping middle 8 bit to high 8 bits, append 4 zeros as LSBs.*/ +/*! 3'b100..3'b111: rsvd */ +#ifdef MRV_ISP_DVP_INPUT_PIN_MAPPING +#define MRV_ISP_DVP_INPUT_PIN_MAPPING_12TO12 0 +#define MRV_ISP_DVP_INPUT_PIN_MAPPING_L10TOH10 1 +#define MRV_ISP_DVP_INPUT_PIN_MAPPING_L8TOH8 2 +#define MRV_ISP_DVP_INPUT_PIN_MAPPING_M8TOH8 3 +#endif +#endif +/*! Slice: DMA_YUV_SELECTION */ +/*! 0: use align or conversion data for isp_is input */ +/*! 1: use dma yuv read data for isp_is input */ +#ifdef MRV_ISP_DMA_YUV_SELECTION +#define MRV_ISP_DMA_YUV_SELECTION_ALIGNED_CONV 0 +#define MRV_ISP_DMA_YUV_SELECTION_DMA_YUV 1 +#endif +/* Slice: LATENCY_FIFO_SELECTION:*/ +/* 0: use input formatter input for latency fifo.*/ +/* 1: use dma rgb read input for latency fifo.*/ +#ifdef MRV_ISP_LATENCY_FIFO_SELECTION +#define MRV_ISP_LATENCY_FIFO_SELECTION_INPUT_FORMATTER 0 +#define MRV_ISP_LATENCY_FIFO_SELECTION_DMA_READ 1 +#endif /* MRV_ISP_LATENCY_FIFO_SELECTION */ +/* Slice: INPUT_SELECTION:*/ +/* 000: 12Bit external Interface */ +/* 001: 10Bit Interface, append 2 zeroes as LSBs */ +/* 010: 10Bit Interface, append 2 MSBs as LSBs */ +/* 011: 8Bit Interface, append 4 zeroes as LSBs */ +/* 100: 8Bit Interface, append 4 MSBs as LSBs */ +/* 101...111: reserved */ +#ifdef MRV_ISP_INPUT_SELECTION +#define MRV_ISP_INPUT_SELECTION_12EXT 0 /* 000- 12Bit external Interface */ +#define MRV_ISP_INPUT_SELECTION_10ZERO 1 /* 001- 10Bit Interface, append 2 zeroes as LSBs */ +#define MRV_ISP_INPUT_SELECTION_10MSB 2 /* 010- 10Bit Interface, append 2 MSBs as LSBs */ +#define MRV_ISP_INPUT_SELECTION_8ZERO 3 /* 011- 8Bit Interface, append 4 zeroes as LSBs */ +#define MRV_ISP_INPUT_SELECTION_8MSB 4 /* 100- 8Bit Interface, append 4 MSBs as LSBs */ +#endif /* MRV_ISP_INPUT_SELECTION */ +/* Slice: FIELD_SELECTION:*/ +/* 00: sample all fields (don't care about fields)*/ +/* 01: sample only even fields */ +/* 10: sample only odd fields */ +/* 11: reserved */ +#ifdef MRV_ISP_FIELD_SELECTION +#define MRV_ISP_FIELD_SELECTION_BOTH 0 /* 00- sample all fields (don't care about fields) */ +#define MRV_ISP_FIELD_SELECTION_EVEN 1 /* 01- sample only even fields */ +#define MRV_ISP_FIELD_SELECTION_ODD 2 /* 10- sample only odd fields */ +#endif /* MRV_ISP_FIELD_SELECTION */ +/* Slice: CCIR_SEQ:*/ +/* 00: YCbYCr */ +/* 01: YCrYCb */ +/* 10: CbYCrY */ +/* 11: CrYCbY */ +#ifdef MRV_ISP_CCIR_SEQ +#define MRV_ISP_CCIR_SEQ_YCBYCR 0 /* 00 - YCbYCr */ +#define MRV_ISP_CCIR_SEQ_YCRYCB 1 /* 01 - YCrYCb */ +#define MRV_ISP_CCIR_SEQ_CBYCRY 2 /* 10 - CbYCrY */ +#define MRV_ISP_CCIR_SEQ_CRYCBY 3 /* 11 - CrYCbY */ +#endif /* MRV_ISP_CCIR_SEQ */ +/* Slice: CONV_422:*/ +/* 00- co-sited color subsampling Y0Cb0Cr0 - Y1 */ +/* 01- interleaved color subsampling Y0Cb0 - Y1Cr1 (not recommended)*/ +/* 10- non-cosited color subsampling Y0Cb(0+1)/2 - Y1Cr(0+1)/2 */ +/* 11- reserved */ +#ifdef MRV_ISP_CONV_422 +#define MRV_ISP_CONV_422_CO 0 /* 00- co-sited color subsampling Y0Cb0Cr0 - Y1 */ +#define MRV_ISP_CONV_422_INTER 1 /* 01- interleaved color subsampling Y0Cb0 - Y1Cr1 (not recommended) */ +#define MRV_ISP_CONV_422_NONCO 2 /* 10- non-cosited color subsampling Y0Cb(0+1)/2 - Y1Cr(0+1)/2 */ +#endif /* MRV_ISP_CONV_422 */ +/* Slice: BAYER_PAT:*/ +/* color components from sensor, starting with top left position in sampled frame */ +/* (reprogram with ISP_ACQ_H_OFFS, ISP_ACQ_V_OFFS)*/ + /**/ +/* 00: first line: RGRG, second line: GBGB, etc.*/ +/* 01: first line: GRGR, second line: BGBG, etc.*/ +/* 10: first line: GBGB, second line: RGRG, etc.*/ +/* 11: first line: BGBG, second line: GRGR, etc.*/ +/* This configuration applies for the black level area after cropping by the input formatter.*/ +#ifdef MRV_ISP_BAYER_PAT +#define MRV_ISP_BAYER_PAT_RG 0 /* 00 - first line: RGRG, second line: GBGB, etc. */ +#define MRV_ISP_BAYER_PAT_GR 1 /* 01 - first line: GRGR, second line: BGBG, etc. */ +#define MRV_ISP_BAYER_PAT_GB 2 /* 10 - first line: GBGB, second line: RGRG, etc. */ +#define MRV_ISP_BAYER_PAT_BG 3 /* 11 - first line: BGBG, second line: GRGR, etc. */ +#endif /* MRV_ISP_BAYER_PAT */ +/* Slice: VSYNC_POL:*/ +/* vertical sync polarity */ +/* 0: high active */ +/* 1: low active */ +#ifdef MRV_ISP_VSYNC_POL +#endif /* MRV_ISP_VSYNC_POL */ +/* Slice: HSYNC_POL:*/ +/* horizontal sync polarity */ +/* 0: high active */ +/* 1: low active */ +#ifdef MRV_ISP_HSYNC_POL +#endif /* MRV_ISP_HSYNC_POL */ +/* Slice: SAMPLE_EDGE:*/ +/* 0: negative edge sampling */ +/* 1: positive edge sampling */ +#ifdef MRV_ISP_SAMPLE_EDGE +#endif /* MRV_ISP_SAMPLE_EDGE */ +/*****************************************************************************/ +/** + * register: isp_acq_h_offs: horizontal input offset (0x0008) + * + *****************************************************************************/ +/* Slice: ACQ_H_OFFS:*/ +/* horizontal sample offset in 8-bit samples (yuv: 4 samples=2pix)*/ +#ifdef MRV_ISP_ACQ_H_OFFS +#endif /* MRV_ISP_ACQ_H_OFFS */ +/*****************************************************************************/ +/** + * register: isp_acq_v_offs: vertical input offset (0x000c) + * + *****************************************************************************/ +/* Slice: ACQ_V_OFFS:*/ +/* vertical sample offset in lines */ +#ifdef MRV_ISP_ACQ_V_OFFS +#endif /* MRV_ISP_ACQ_V_OFFS */ +/*****************************************************************************/ +/** + * register: isp_acq_h_size: horizontal input size (0x0010) + * + *****************************************************************************/ +/* Slice: ACQ_H_SIZE:*/ +/* horizontal sample size in 12-bit samples */ +/* YUV input: 2 samples = 1 pixel, else 1 sample = 1 pixel; So in YUV mode ACQ_H_SIZE must be twice as large as horizontal image size */ +/* horizontal image size must always be even exept in raw picture mode; if an odd size is programmed the value will be truncated to even size */ +#ifdef MRV_ISP_ACQ_H_SIZE +#endif /* MRV_ISP_ACQ_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_acq_v_size: vertical input size (0x0014) + * + *****************************************************************************/ +/* Slice: ACQ_V_SIZE:*/ +/* vertical sample size in lines */ +#ifdef MRV_ISP_ACQ_V_SIZE +#endif /* MRV_ISP_ACQ_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_acq_nr_frames: Number of frames to be captured (0x0018) + * + *****************************************************************************/ +/* Slice: ACQ_NR_FRAMES:*/ +/* number of input frames to be sampled (0 = continuous)*/ +#ifdef MRV_ISP_ACQ_NR_FRAMES +#endif /* MRV_ISP_ACQ_NR_FRAMES */ +/*****************************************************************************/ +/** + * register: isp_gamma_dx_lo: De-Gamma Curve definition lower x increments + * (sampling points) (0x001c) + * + *****************************************************************************/ +/* Slice: GAMMA_DX_8:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_8 +#endif /* MRV_ISP_GAMMA_DX_8 */ +/* Slice: GAMMA_DX_7:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_7 +#endif /* MRV_ISP_GAMMA_DX_7 */ +/* Slice: GAMMA_DX_6:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_6 +#endif /* MRV_ISP_GAMMA_DX_6 */ +/* Slice: GAMMA_DX_5:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_5 +#endif /* MRV_ISP_GAMMA_DX_5 */ +/* Slice: GAMMA_DX_4:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_4 +#endif /* MRV_ISP_GAMMA_DX_4 */ +/* Slice: GAMMA_DX_3:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_3 +#endif /* MRV_ISP_GAMMA_DX_3 */ +/* Slice: GAMMA_DX_2:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_2 +#endif /* MRV_ISP_GAMMA_DX_2 */ +/* Slice: GAMMA_DX_1:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_1 +#endif /* MRV_ISP_GAMMA_DX_1 */ +/*****************************************************************************/ +/** + * register: isp_gamma_dx_hi: De-Gamma Curve definition higher x increments + * (sampling points) (0x0020) + * + *****************************************************************************/ +/* Slice: GAMMA_DX_16:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_16 +#endif /* MRV_ISP_GAMMA_DX_16 */ +/* Slice: GAMMA_DX_15:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_15 +#endif /* MRV_ISP_GAMMA_DX_15 */ +/* Slice: GAMMA_DX_14:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_14 +#endif /* MRV_ISP_GAMMA_DX_14 */ +/* Slice: GAMMA_DX_13:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_13 +#endif /* MRV_ISP_GAMMA_DX_13 */ +/* Slice: GAMMA_DX_12:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_12 +#endif /* MRV_ISP_GAMMA_DX_12 */ +/* Slice: GAMMA_DX_11:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_11 +#endif /* MRV_ISP_GAMMA_DX_11 */ +/* Slice: GAMMA_DX_10:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_10 +#endif /* MRV_ISP_GAMMA_DX_10 */ +/* Slice: GAMMA_DX_9:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_9 +#endif /* MRV_ISP_GAMMA_DX_9 */ +/*****************************************************************************/ +/** + * register array: isp_gamma_r_y: De-Gamma Curve definition y red (0x0024+n (n=0..16)) + * + *****************************************************************************/ +/* Slice: GAMMA_R_Y:*/ +/* gamma curve point definition y-axis (output) for red */ +/* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/ +#ifdef MRV_ISP_GAMMA_R_Y +#endif /* MRV_ISP_GAMMA_R_Y */ +/*****************************************************************************/ +/** + * register array: isp_gamma_g_y: De-Gamma Curve definition y green (0x0068+n (n=0..16)) + * + *****************************************************************************/ +/* Slice: GAMMA_G_Y:*/ +/* gamma curve point definition y-axis (output) for green */ +/* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/ +#ifdef MRV_ISP_GAMMA_G_Y +#endif /* MRV_ISP_GAMMA_G_Y */ +/*****************************************************************************/ +/** + * register array: isp_gamma_b_y: De-Gamma Curve definition y blue (0x00AC+n (n=0..16)) + * + *****************************************************************************/ +/* Slice: GAMMA_B_Y:*/ +/* gamma curve point definition y-axis (output) for blue */ +/* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/ +#ifdef MRV_ISP_GAMMA_B_Y +#endif /* MRV_ISP_GAMMA_B_Y */ +/*****************************************************************************/ +/* ISP Auto White Balance Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_awb_prop: Auto white balance properties (0x0110) + * + *****************************************************************************/ +/* Slice: AWB_MEAS_MODE:*/ +/* 1: RGB based measurement mode */ +/* 0: near white discrimination mode using YCbCr color space */ +#ifdef MRV_ISP_AWB_MEAS_MODE +#define MRV_ISP_AWB_MEAS_MODE_RGB 1U /* 1: RGB based measurement mode */ +#define MRV_ISP_AWB_MEAS_MODE_YCBCR 0U /* 0: near white discrimination mode using YCbCr color space */ +#endif /* MRV_ISP_AWB_MEAS_MODE */ +/* Slice: AWB_MAX_EN:*/ +/* 1: enable Y_MAX compare */ +/* 0: disable Y_MAX compare */ +/* ignored if RGB measurement mode is enabled */ +#ifdef MRV_ISP_AWB_MAX_EN +#define MRV_ISP_AWB_MAX_EN_ENABLE 1U /* 1: enable Y_MAX compare */ +#define MRV_ISP_AWB_MAX_EN_DISABLE 0U /* 0: disable Y_MAX compare */ +#endif /* MRV_ISP_AWB_MAX_EN */ +/* Slice: AWB_MODE:*/ +/* AWB_MODE(1:0):*/ +/* 11: reserved */ +/* 10: white balance measurement of YCbCr means */ +/* 01: reserved */ +/* 00: manual white balance (gain adjust possible), no measurement */ +#ifdef MRV_ISP_AWB_MODE +#define MRV_ISP_AWB_MODE_MEAS 2U /* 10: white balance measurement of YCbCr or RGB means (dependent on MRV_ISP_AWB_MEAS_MODE) */ +#define MRV_ISP_AWB_MODE_NOMEAS 0U /* 00: manual white balance (gain adjust possible), no measurement */ +#endif /* MRV_ISP_AWB_MODE */ +/*****************************************************************************/ +/** + * register: isp_awb_h_offs: Auto white balance horizontal offset of measure + * window (0x0114) + * + *****************************************************************************/ +/* Slice: AWB_H_OFFS:*/ +/* horizontal window offset in pixel */ +#ifdef MRV_ISP_AWB_H_OFFS +#define MRV_ISP_AWB_H_OFFS_MIN 0U +#define MRV_ISP_AWB_H_OFFS_MAX (MRV_ISP_AWB_H_OFFS_MASK >> MRV_ISP_AWB_H_OFFS_SHIFT) +#endif /* MRV_ISP_AWB_H_OFFS */ +/*****************************************************************************/ +/** + * register: isp_awb_v_offs: Auto white balance vertical offset of measure + * window (0x0118) + * + *****************************************************************************/ +/* Slice: AWB_V_OFFS:*/ +/* vertical window offset in lines */ +#ifdef MRV_ISP_AWB_V_OFFS +#define MRV_ISP_AWB_V_OFFS_MIN 0U +#define MRV_ISP_AWB_V_OFFS_MAX (MRV_ISP_AWB_V_OFFS_MASK >> MRV_ISP_AWB_V_OFFS_SHIFT) +#endif /* MRV_ISP_AWB_V_OFFS */ +/*****************************************************************************/ +/** + * register: isp_awb_h_size: Auto white balance horizontal window size (0x011c) + * + *****************************************************************************/ +/* Slice: AWB_H_SIZE:*/ +/* horizontal measurement window size in pixel */ +#ifdef MRV_ISP_AWB_H_SIZE +#define MRV_ISP_AWB_H_SIZE_MIN 0U +#define MRV_ISP_AWB_H_SIZE_MAX (MRV_ISP_AWB_H_SIZE_MASK >> MRV_ISP_AWB_H_SIZE_SHIFT) +#endif /* MRV_ISP_AWB_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_awb_v_size: Auto white balance vertical window size (0x0120) + * + *****************************************************************************/ +/* Slice: AWB_V_SIZE:*/ +/* vertical measurement window size in lines */ +#ifdef MRV_ISP_AWB_V_SIZE +#define MRV_ISP_AWB_V_SIZE_MIN 0U +#define MRV_ISP_AWB_V_SIZE_MAX (MRV_ISP_AWB_V_SIZE_MASK >> MRV_ISP_AWB_V_SIZE_SHIFT) +#endif /* MRV_ISP_AWB_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_awb_frames: Auto white balance mean value over multiple frames (0x0124) + * + *****************************************************************************/ +/* Slice: AWB_FRAMES:*/ +/* number of frames-1 used for mean value calculation (value of 0 means 1 frame, value of 7 means 8 frames)*/ +#ifdef MRV_ISP_AWB_FRAMES +#endif /* MRV_ISP_AWB_FRAMES */ +/*****************************************************************************/ +/** + * register: isp_awb_ref: Auto white balance reference Cb/Cr values (0x0128) + * or maximum red/blue values + * + *****************************************************************************/ +/* Slice: AWB_REF_CR__MAX_R:*/ +/* - reference Cr value for AWB regulation, target for AWB */ +/* - maximum red value, if RGB measurement mode is selected */ +#ifdef MRV_ISP_AWB_REF_CR__MAX_R +#endif /* MRV_ISP_AWB_REF_CR__MAX_R */ +/* Slice: AWB_REF_CB__MAX_B:*/ +/* - reference Cb value for AWB regulation, target for AWB */ +/* - maximum blue value, if RGB measurement mode is selected */ +#ifdef MRV_ISP_AWB_REF_CB__MAX_B +#endif /* MRV_ISP_AWB_REF_CB__MAX_B */ +/*****************************************************************************/ +/** + * register: isp_awb_thresh: Auto white balance threshold values (0x012c) + * + *****************************************************************************/ +/* Slice: AWB_MAX_Y:*/ +/* - Luminance maximum value, only consider pixels with luminance smaller than threshold for the WB measurement (must be enabled by AWB_MODE(2)),*/ +/* - ignored if RGB measurement mode is enabled */ +#ifdef MRV_ISP_AWB_MAX_Y +#endif /* MRV_ISP_AWB_MAX_Y */ +/* Slice: AWB_MIN_Y__MAX_G:*/ +/* - Luminance minimum value, only consider pixels with luminance greater than threshold for the WB measurement */ +/* - maximum green value, if RGB measurement mode is selected */ +#ifdef MRV_ISP_AWB_MIN_Y__MAX_G +#endif /* MRV_ISP_AWB_MIN_Y__MAX_G */ +/* Slice: AWB_MAX_CSUM:*/ +/* - Chrominance sum maximum value, only consider pixels with Cb+Cr smaller than threshold for WB measurements */ +/* - ignored if RGB measurement mode is enabled */ +#ifdef MRV_ISP_AWB_MAX_CSUM +#endif /* MRV_ISP_AWB_MAX_CSUM */ +/* Slice: AWB_MIN_C:*/ +/* - Chrominance minimum value, only consider pixels with Cb/Cr each greater than threshold value for WB measurements */ +/* - ignored if RGB measurement mode is enabled */ +#ifdef MRV_ISP_AWB_MIN_C +#endif /* MRV_ISP_AWB_MIN_C */ +/*****************************************************************************/ +/** + * register: isp_awb_gain_g: Auto white balance gain green (0x0138) + * + *****************************************************************************/ +/* Slice: AWB_GAIN_GR:*/ +/* gain value for green component in red line 100h = 1 */ +#ifdef MRV_ISP_AWB_GAIN_GR +#define MRV_ISP_AWB_GAIN_GR_DEFAULT (0x100U) +#define MRV_ISP_AWB_GAIN_GR_MAX (MRV_ISP_AWB_GAIN_GR_MASK >> MRV_ISP_AWB_GAIN_GR_SHIFT) +#endif /* MRV_ISP_AWB_GAIN_GR */ +/* Slice: AWB_GAIN_GB:*/ +/* gain value for green component in blue line 100h = 1 */ +#ifdef MRV_ISP_AWB_GAIN_GB +#define MRV_ISP_AWB_GAIN_GB_DEFAULT (0x100U) +#define MRV_ISP_AWB_GAIN_GB_MAX (MRV_ISP_AWB_GAIN_GB_MASK >> MRV_ISP_AWB_GAIN_GB_SHIFT) +#endif /* MRV_ISP_AWB_GAIN_GB */ +/*****************************************************************************/ +/** + * register: isp_awb_gain_rb: Auto white balance gain red and blue (0x013c) + * + *****************************************************************************/ +/* Slice: AWB_GAIN_R:*/ +/* gain value for red component 100h = 1 */ +#ifdef MRV_ISP_AWB_GAIN_R +#define MRV_ISP_AWB_GAIN_R_DEFAULT (0x100U) +#define MRV_ISP_AWB_GAIN_R_MAX (MRV_ISP_AWB_GAIN_R_MASK >> MRV_ISP_AWB_GAIN_R_SHIFT) +#endif /* MRV_ISP_AWB_GAIN_R */ +/* Slice: AWB_GAIN_B:*/ +/* gain value for blue component 100h = 1 */ +#ifdef MRV_ISP_AWB_GAIN_B +#define MRV_ISP_AWB_GAIN_B_DEFAULT (0x100U) +#define MRV_ISP_AWB_GAIN_B_MAX (MRV_ISP_AWB_GAIN_B_MASK >> MRV_ISP_AWB_GAIN_B_SHIFT) +#endif /* MRV_ISP_AWB_GAIN_B */ +/*****************************************************************************/ +/** + * register: isp_awb_white_cnt: Auto white balance white pixel count (0x0140) + * + *****************************************************************************/ +/* Slice: AWB_WHITE_CNT:*/ +/* White pixel count, number of "white pixels" found during last measurement, i.e. pixels included in mean value calculation */ +#ifdef MRV_ISP_AWB_WHITE_CNT +#endif /* MRV_ISP_AWB_WHITE_CNT */ +/*****************************************************************************/ +/** + * register: isp_awb_mean: Auto white balance measured mean value (0x0144) + * + *****************************************************************************/ +/* Slice: AWB_MEAN_Y_G:*/ +/* - mean value of Y within window and frames */ +/* - mean value of green within window and frames if RGB measurement is enabled */ +#ifdef MRV_ISP_AWB_MEAN_Y__G +#endif /* MRV_ISP_AWB_MEAN_Y__G */ +/* Slice: AWB_MEAN_CB_B:*/ +/* - mean value of Cb within window and frames */ +/* - mean value of blue within window and frames if RGB measurement is enabled */ +#ifdef MRV_ISP_AWB_MEAN_CB__B +#endif /* MRV_ISP_AWB_MEAN_CB__B */ +/* Slice: AWB_MEAN_CR_R:*/ +/* - mean value of Cr within window and frames */ +/* - mean value of red within window and frames if RGB measurement is enabled */ +#ifdef MRV_ISP_AWB_MEAN_CR__R +#endif /* MRV_ISP_AWB_MEAN_CR__R */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_0: Color conversion coefficient 0 (0x0170) + * + *****************************************************************************/ +/* Slice: cc_coeff_0:*/ +/* coefficient 0 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_0 +#endif /* MRV_ISP_CC_COEFF_0 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_1: Color conversion coefficient 1 (0x0174) + * + *****************************************************************************/ +/* Slice: cc_coeff_1:*/ +/* coefficient 1 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_1 +#endif /* MRV_ISP_CC_COEFF_1 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_2: Color conversion coefficient 2 (0x0178) + * + *****************************************************************************/ +/* Slice: cc_coeff_2:*/ +/* coefficient 2 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_2 +#endif /* MRV_ISP_CC_COEFF_2 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_3: Color conversion coefficient 3 (0x017c) + * + *****************************************************************************/ +/* Slice: cc_coeff_3:*/ +/* coefficient 3 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_3 +#endif /* MRV_ISP_CC_COEFF_3 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_4: Color conversion coefficient 4 (0x0180) + * + *****************************************************************************/ +/* Slice: cc_coeff_4:*/ +/* coefficient 4 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_4 +#endif /* MRV_ISP_CC_COEFF_4 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_5: Color conversion coefficient 5 (0x0184) + * + *****************************************************************************/ +/* Slice: cc_coeff_5:*/ +/* coefficient 5 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_5 +#endif /* MRV_ISP_CC_COEFF_5 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_6: Color conversion coefficient 6 (0x0188) + * + *****************************************************************************/ +/* Slice: cc_coeff_6:*/ +/* coefficient 6 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_6 +#endif /* MRV_ISP_CC_COEFF_6 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_7: Color conversion coefficient 7 (0x018c) + * + *****************************************************************************/ +/* Slice: cc_coeff_7:*/ +/* coefficient 7 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_7 +#endif /* MRV_ISP_CC_COEFF_7 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_8: Color conversion coefficient 8 (0x0190) + * + *****************************************************************************/ +/* Slice: cc_coeff_8:*/ +/* coefficient 8 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_8 +#endif /* MRV_ISP_CC_COEFF_8 */ +/*****************************************************************************/ +/** + * register: isp_out_h_offs: Horizontal offset of output window (0x0194) + * + *****************************************************************************/ +/* Slice: ISP_OUT_H_OFFS:*/ +/* vertical pic offset in lines */ +#ifdef MRV_ISP_ISP_OUT_H_OFFS +#endif /* MRV_ISP_ISP_OUT_H_OFFS */ +/*****************************************************************************/ +/** + * register: isp_out_v_offs: Vertical offset of output window (0x0198) + * + *****************************************************************************/ +/* Slice: ISP_OUT_V_OFFS:*/ +/* vertical pic offset in lines */ +#ifdef MRV_ISP_ISP_OUT_V_OFFS +#endif /* MRV_ISP_ISP_OUT_V_OFFS */ +/*****************************************************************************/ +/** + * register: isp_out_h_size: Output horizontal picture size (0x019c) + * + *****************************************************************************/ +/* Slice: ISP_OUT_H_SIZE:*/ +/* horizontal picture size in pixel */ +/* if ISP_MODE is set to */ +/* 001: (ITU-R BT.656 YUV),*/ +/* 010: (ITU-R BT.601 YUV),*/ +/* 011: (ITU-R BT.601 Bayer RGB),*/ +/* 101: (ITU-R BT.656 Bayer RGB)*/ +/* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr)*/ +/* are needed for the 422 output. (if an odd size is programmed the value will */ +/* be truncated to an even size)*/ +#ifdef MRV_ISP_ISP_OUT_H_SIZE +#define MRV_ISP_ISP_OUT_H_SIZE_IS_EVEN(x) (!(x & 0x01U)) /* check is even value */ +#define MRV_ISP_ISP_OUT_H_SIZE_IS_ODD(x) (x & 0x01U) /* check is odd value */ +#endif /* MRV_ISP_ISP_OUT_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_out_v_size: Output vertical picture size (0x01a0) + * + *****************************************************************************/ +/* Slice: ISP_OUT_V_SIZE:*/ +/* vertical pic size in lines */ +#ifdef MRV_ISP_ISP_OUT_V_SIZE +#endif /* MRV_ISP_ISP_OUT_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_demosaic: Demosaic parameters (0x000001a4) + * + *****************************************************************************/ +/* Slice: DEMOSAIC_BYPASS:*/ +/* 0: normal operation for RGB Bayer Pattern input */ +/* 1: demosaicing bypass for Black&White input data */ +#ifdef MRV_ISP_DEMOSAIC_BYPASS +#define MRV_ISP_DEMOSAIC_MODE_STD 0 /* "0": standard */ +#define MRV_ISP_DEMOSAIC_MODE_ENH 1 /* "1": enhanced mode */ +#endif /* MRV_ISP_DEMOSAIC_BYPASS */ +/* Slice: DEMOSAIC_TH:*/ +/* Threshold for Bayer demosaicing texture detection. This value shifted left */ +/* 4bit is compared with the difference of the vertical and horizontal 12Bit */ +/* wide texture indicators, to decide if the vertical or horizontal texture */ +/* flag must be set.*/ +/* 0xFF: no texture detection */ +/* 0x00: maximum edge sensitivity */ +#ifdef MRV_ISP_DEMOSAIC_TH +#define MRV_ISP_DEMOSAIC_TH_MAX_TEXTURE_DETECTION 0xFFU /* 0xFF: no texture detection */ +#define MRV_ISP_DEMOSAIC_TH_MAX_EDGE_SENSITIVITY 0x00U /* 0x00: maximum edge sensitivity */ +#endif /* MRV_ISP_DEMOSAIC_TH */ +/*****************************************************************************/ +/** + * register: isp_flags_shd: Flags (current status) of certain signals and + * Shadow regs for enable signals (0x000001a8) + * + *****************************************************************************/ +/* Slice: S_HSYNC:*/ +/* state of ISP input port s_hsync, for test purposes */ +#ifdef MRV_ISP_S_HSYNC +#endif /* MRV_ISP_S_HSYNC */ +/* Slice: S_VSYNC:*/ +/* state of ISP input port s_vsync, for test purposes */ +#ifdef MRV_ISP_S_VSYNC +#endif /* MRV_ISP_S_VSYNC */ +/* Slice: S_DATA:*/ +/* state of ISP input port s_data, for test purposes */ +#ifdef MRV_ISP_S_DATA +#endif /* MRV_ISP_S_DATA */ +/* Slice: INFORM_FIELD:*/ +/* current field information */ +/* 0: odd */ +/* 1: even */ +#ifdef MRV_ISP_INFORM_FIELD +#define MRV_ISP_INFORM_FIELD_ODD 0 /* 0: odd field is sampled */ +#define MRV_ISP_INFORM_FIELD_EVEN 1 /* 1: even field is sampled */ +#endif /* MRV_ISP_INFORM_FIELD */ +/* Slice: INFORM_EN_SHD:*/ +/* Input formatter enable shadow register */ +#ifdef MRV_ISP_INFORM_EN_SHD +#endif /* MRV_ISP_INFORM_EN_SHD */ +/* Slice: ISP_ENABLE_SHD:*/ +/* ISP enable shadow register */ +/* shows, if ISP currently outputs data (1) or not (0)*/ +#ifdef MRV_ISP_ISP_ENABLE_SHD +#endif /* MRV_ISP_ISP_ENABLE_SHD */ +/*****************************************************************************/ +/** + * register: isp_out_h_offs_shd: current horizontal offset of output window + * (shadow register) (0x000001ac) + * + *****************************************************************************/ +/* Slice: ISP_OUT_H_OFFS_SHD:*/ +/* current vertical pic offset in lines */ +#ifdef MRV_ISP_ISP_OUT_H_OFFS_SHD +#endif /* MRV_ISP_ISP_OUT_H_OFFS_SHD */ +/*****************************************************************************/ +/** + * register: isp_out_v_offs_shd: current vertical offset of output window + * (shadow register) (0x000001b0) + * + *****************************************************************************/ +/* Slice: ISP_OUT_V_OFFS_SHD:*/ +/* current vertical pic offset in lines */ +#ifdef MRV_ISP_ISP_OUT_V_OFFS_SHD +#endif /* MRV_ISP_ISP_OUT_V_OFFS_SHD */ +/*****************************************************************************/ +/** + * register: isp_out_h_size_shd: current output horizontal picture size + * (shadow register) (0x000001b4) + * + *****************************************************************************/ +/* Slice: ISP_OUT_H_SIZE_SHD:*/ +/* current horizontal pic size in pixel */ +#ifdef MRV_ISP_ISP_OUT_H_SIZE_SHD +#endif /* MRV_ISP_ISP_OUT_H_SIZE_SHD */ +/*****************************************************************************/ +/** + * register: isp_out_v_size_shd: current output vertical picture size + * (shadow register) (0x000001b8) + * + *****************************************************************************/ +/* Slice: ISP_OUT_V_SIZE_SHD:*/ +/* vertical pic size in lines */ +#ifdef MRV_ISP_ISP_OUT_V_SIZE_SHD +#endif /* MRV_ISP_ISP_OUT_V_SIZE_SHD */ +/*****************************************************************************/ +/** + * register: isp_imsc: Interrupt mask (0x000001bc) + * + *****************************************************************************/ +/*! Slice: IMSC_VSM_END:*/ +/*! enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_VSM_END +#define MRV_ISP_IMSC_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_VSM_END */ +/* Slice: IMSC_EXP_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_EXP_END +#define MRV_ISP_IMSC_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_EXP_END */ +/* Slice: IMSC_FLASH_CAP:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_FLASH_CAP +#define MRV_ISP_IMSC_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_FLASH_CAP */ +/* Slice: IMSC_BP_DET:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_BP_DET +#define MRV_ISP_IMSC_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_BP_DET */ +/* Slice: IMSC_HIST_MEASURE_RDY:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_HIST_MEASURE_RDY +#define MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_HIST_MEASURE_RDY */ +/* Slice: IMSC_AFM_FIN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_AFM_FIN +#define MRV_ISP_IMSC_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !IMSC_AFM_FIN */ +/* Slice: IMSC_AFM_LUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_AFM_LUM_OF +#define MRV_ISP_IMSC_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_AFM_LUM_OF */ +/* Slice: IMSC_AFM_SUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_AFM_SUM_OF +#define MRV_ISP_IMSC_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_AFM_SUM_OF */ +/* Slice: IMSC_SHUTTER_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_SHUTTER_OFF +#define MRV_ISP_IMSC_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_SHUTTER_OFF */ +/* Slice: IMSC_SHUTTER_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_SHUTTER_ON +#define MRV_ISP_IMSC_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_SHUTTER_ON */ +/* Slice: IMSC_FLASH_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_FLASH_OFF +#define MRV_ISP_IMSC_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_FLASH_OFF */ +/* Slice: IMSC_FLASH_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_FLASH_ON +#define MRV_ISP_IMSC_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_FLASH_ON */ +/* Slice: IMSC_H_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_H_START +#define MRV_ISP_IMSC_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_H_START */ +/* Slice: IMSC_V_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_V_START +#define MRV_ISP_IMSC_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_V_START */ +/* Slice: IMSC_FRAME_IN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_FRAME_IN +#define MRV_ISP_IMSC_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_FRAME_IN */ +/* Slice: IMSC_AWB_DONE:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_AWB_DONE +#define MRV_ISP_IMSC_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_AWB_DONE */ +/* Slice: IMSC_PIC_SIZE_ERR:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_PIC_SIZE_ERR +#define MRV_ISP_IMSC_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_PIC_SIZE_ERR */ +/* Slice: IMSC_DATA_LOSS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_DATA_LOSS +#define MRV_ISP_IMSC_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_DATA_LOSS */ +/* Slice: IMSC_FRAME:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_FRAME +#define MRV_ISP_IMSC_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_FRAME */ +/* Slice: IMSC_ISP_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_ISP_OFF +#define MRV_ISP_IMSC_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_ISP_OFF */ +/* combination of all interrupt lines */ +#define MRV_ISP_IMSC_ALL_IRQS +#define MRV_ISP_IMSC_ALL_IRQS_MASK \ +(0 \ + | MRV_ISP_IMSC_VSM_END_MASK \ + | MRV_ISP_IMSC_EXP_END_MASK \ + | MRV_ISP_IMSC_FLASH_CAP_MASK \ + | MRV_ISP_IMSC_BP_DET_MASK \ + | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK \ + | MRV_ISP_IMSC_AFM_FIN_MASK \ + | MRV_ISP_IMSC_AFM_LUM_OF_MASK \ + | MRV_ISP_IMSC_AFM_SUM_OF_MASK \ + | MRV_ISP_IMSC_SHUTTER_OFF_MASK \ + | MRV_ISP_IMSC_SHUTTER_ON_MASK \ + | MRV_ISP_IMSC_FLASH_OFF_MASK \ + | MRV_ISP_IMSC_FLASH_ON_MASK \ + | MRV_ISP_IMSC_H_START_MASK \ + | MRV_ISP_IMSC_V_START_MASK \ + | MRV_ISP_IMSC_FRAME_IN_MASK \ + | MRV_ISP_IMSC_AWB_DONE_MASK \ + | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK \ + | MRV_ISP_IMSC_DATA_LOSS_MASK \ + | MRV_ISP_IMSC_FRAME_MASK \ + | MRV_ISP_IMSC_ISP_OFF_MASK \ +) +#define MRV_ISP_IMSC_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register: isp_ris: Raw interrupt status (0x000001c0) + * + *****************************************************************************/ +/*! Slice: RIS_VSM_END:*/ +/*! VSM measurement complete */ +#ifndef MRV_ISP_RIS_VSM_END +#define MRV_ISP_RIS_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_VSM_END */ +/* Slice: RIS_EXP_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_EXP_END +#define MRV_ISP_RIS_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_EXP_END */ +/* Slice: RIS_FLASH_CAP:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_FLASH_CAP +#define MRV_ISP_RIS_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_FLASH_CAP */ +/* Slice: RIS_BP_DET:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_BP_DET +#define MRV_ISP_RIS_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_BP_DET */ +/* Slice: RIS_HIST_MEASURE_RDY:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_HIST_MEASURE_RDY +#define MRV_ISP_RIS_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_HIST_MEASURE_RDY */ +/* Slice: RIS_AFM_FIN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_AFM_FIN +#define MRV_ISP_RIS_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !RIS_AFM_FIN */ +/* Slice: RIS_AFM_LUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_AFM_LUM_OF +#define MRV_ISP_RIS_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_AFM_LUM_OF */ +/* Slice: RIS_AFM_SUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_AFM_SUM_OF +#define MRV_ISP_RIS_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_AFM_SUM_OF */ +/* Slice: RIS_SHUTTER_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_SHUTTER_OFF +#define MRV_ISP_RIS_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_SHUTTER_OFF */ +/* Slice: RIS_SHUTTER_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_SHUTTER_ON +#define MRV_ISP_RIS_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_SHUTTER_ON */ +/* Slice: RIS_FLASH_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_FLASH_OFF +#define MRV_ISP_RIS_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_FLASH_OFF */ +/* Slice: RIS_FLASH_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_FLASH_ON +#define MRV_ISP_RIS_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_FLASH_ON */ +/* Slice: RIS_H_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_H_START +#define MRV_ISP_RIS_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_H_START */ +/* Slice: RIS_V_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_V_START +#define MRV_ISP_RIS_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_V_START */ +/* Slice: RIS_FRAME_IN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_FRAME_IN +#define MRV_ISP_RIS_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_FRAME_IN */ +/* Slice: RIS_AWB_DONE:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_AWB_DONE +#define MRV_ISP_RIS_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_AWB_DONE */ +/* Slice: RIS_PIC_SIZE_ERR:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_PIC_SIZE_ERR +#define MRV_ISP_RIS_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_PIC_SIZE_ERR */ +/* Slice: RIS_DATA_LOSS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_DATA_LOSS +#define MRV_ISP_RIS_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_DATA_LOSS */ +/* Slice: RIS_FRAME:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_FRAME +#define MRV_ISP_RIS_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_FRAME */ +/* Slice: RIS_ISP_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_ISP_OFF +#define MRV_ISP_RIS_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_ISP_OFF */ +/* combination of all interrupt lines */ +#define MRV_ISP_RIS_ALL_IRQS +#define MRV_ISP_RIS_ALL_IRQS_MASK \ +(0 \ + | MRV_ISP_RIS_VSM_END_MASK \ + | MRV_ISP_RIS_EXP_END_MASK \ + | MRV_ISP_RIS_FLASH_CAP_MASK \ + | MRV_ISP_RIS_BP_DET_MASK \ + | MRV_ISP_RIS_HIST_MEASURE_RDY_MASK \ + | MRV_ISP_RIS_AFM_FIN_MASK \ + | MRV_ISP_RIS_AFM_LUM_OF_MASK \ + | MRV_ISP_RIS_AFM_SUM_OF_MASK \ + | MRV_ISP_RIS_SHUTTER_OFF_MASK \ + | MRV_ISP_RIS_SHUTTER_ON_MASK \ + | MRV_ISP_RIS_FLASH_OFF_MASK \ + | MRV_ISP_RIS_FLASH_ON_MASK \ + | MRV_ISP_RIS_H_START_MASK \ + | MRV_ISP_RIS_V_START_MASK \ + | MRV_ISP_RIS_FRAME_IN_MASK \ + | MRV_ISP_RIS_AWB_DONE_MASK \ + | MRV_ISP_RIS_PIC_SIZE_ERR_MASK \ + | MRV_ISP_RIS_DATA_LOSS_MASK \ + | MRV_ISP_RIS_FRAME_MASK \ + | MRV_ISP_RIS_ISP_OFF_MASK \ +) +#define MRV_ISP_RIS_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register: isp_mis: Masked interrupt status (0x000001c4) + * + *****************************************************************************/ +/*! Slice: MIS_VSM_END:*/ +/*! VSM measurement complete */ +#ifndef MRV_ISP_MIS_VSM_END +#define MRV_ISP_MIS_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_VSM_END_MASK */ +/* Slice: MIS_EXP_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_EXP_END +#define MRV_ISP_MIS_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_EXP_END */ +/* Slice: MIS_FLASH_CAP:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_FLASH_CAP +#define MRV_ISP_MIS_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_FLASH_CAP */ +/* Slice: MIS_BP_DET:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_BP_DET +#define MRV_ISP_MIS_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_BP_DET */ +/* Slice: MIS_HIST_MEASURE_RDY:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_HIST_MEASURE_RDY +#define MRV_ISP_MIS_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_HIST_MEASURE_RDY */ +/* Slice: MIS_AFM_FIN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_AFM_FIN +#define MRV_ISP_MIS_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MIS_AFM_FIN */ +/* Slice: MIS_AFM_LUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_AFM_LUM_OF +#define MRV_ISP_MIS_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_AFM_LUM_OF */ +/* Slice: MIS_AFM_SUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_AFM_SUM_OF +#define MRV_ISP_MIS_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_AFM_SUM_OF */ +/* Slice: MIS_SHUTTER_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_SHUTTER_OFF +#define MRV_ISP_MIS_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_SHUTTER_OFF */ +/* Slice: MIS_SHUTTER_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_SHUTTER_ON +#define MRV_ISP_MIS_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_SHUTTER_ON */ +/* Slice: MIS_FLASH_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_FLASH_OFF +#define MRV_ISP_MIS_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_FLASH_OFF */ +/* Slice: MIS_FLASH_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_FLASH_ON +#define MRV_ISP_MIS_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_FLASH_ON */ +/* Slice: MIS_H_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_H_START +#define MRV_ISP_MIS_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_H_START */ +/* Slice: MIS_V_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_V_START +#define MRV_ISP_MIS_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_V_START */ +/* Slice: MIS_FRAME_IN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_FRAME_IN +#define MRV_ISP_MIS_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_FRAME_IN */ +/* Slice: MIS_AWB_DONE:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_AWB_DONE +#define MRV_ISP_MIS_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_AWB_DONE */ +/* Slice: MIS_PIC_SIZE_ERR:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_PIC_SIZE_ERR +#define MRV_ISP_MIS_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_PIC_SIZE_ERR */ +/* Slice: MIS_DATA_LOSS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_DATA_LOSS +#define MRV_ISP_MIS_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_DATA_LOSS */ +/* Slice: MIS_FRAME:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_FRAME +#define MRV_ISP_MIS_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_FRAME */ +/* Slice: MIS_ISP_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_ISP_OFF +#define MRV_ISP_MIS_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_ISP_OFF */ +/* combination of all interrupt lines */ +#define MRV_ISP_MIS_ALL_IRQS +#define MRV_ISP_MIS_ALL_IRQS_MASK \ + (0 \ + | MRV_ISP_MIS_VSM_END_MASK \ + | MRV_ISP_MIS_EXP_END_MASK \ + | MRV_ISP_MIS_FLASH_CAP_MASK \ + | MRV_ISP_MIS_BP_DET_MASK \ + | MRV_ISP_MIS_HIST_MEASURE_RDY_MASK \ + | MRV_ISP_MIS_AFM_FIN_MASK \ + | MRV_ISP_MIS_AFM_LUM_OF_MASK \ + | MRV_ISP_MIS_AFM_SUM_OF_MASK \ + | MRV_ISP_MIS_SHUTTER_OFF_MASK \ + | MRV_ISP_MIS_SHUTTER_ON_MASK \ + | MRV_ISP_MIS_FLASH_OFF_MASK \ + | MRV_ISP_MIS_FLASH_ON_MASK \ + | MRV_ISP_MIS_H_START_MASK \ + | MRV_ISP_MIS_V_START_MASK \ + | MRV_ISP_MIS_FRAME_IN_MASK \ + | MRV_ISP_MIS_AWB_DONE_MASK \ + | MRV_ISP_MIS_PIC_SIZE_ERR_MASK \ + | MRV_ISP_MIS_DATA_LOSS_MASK \ + | MRV_ISP_MIS_FRAME_MASK \ + | MRV_ISP_MIS_ISP_OFF_MASK \ + ) +#define MRV_ISP_MIS_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register: isp_icr: Interrupt clear register (0x000001c8) + * + *****************************************************************************/ +/*! Slice: ICR_VSM_END:*/ +/*! clear interrupt */ +#ifndef MRV_ISP_ICR_VSM_END +#define MRV_ISP_ICR_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_VSM_END */ +/* Slice: ICR_EXP_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_EXP_END +#define MRV_ISP_ICR_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_EXP_END */ +/* Slice: ICR_FLASH_CAP:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_FLASH_CAP +#define MRV_ISP_ICR_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_FLASH_CAP */ +/* Slice: ICR_BP_DET:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_BP_DET +#define MRV_ISP_ICR_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_BP_DET */ +/* Slice: ICR_HIST_MEASURE_RDY:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_HIST_MEASURE_RDY +#define MRV_ISP_ICR_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_HIST_MEASURE_RDY */ +/* Slice: ICR_AFM_FIN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_AFM_FIN +#define MRV_ISP_ICR_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !ICR_AFM_FIN */ +/* Slice: ICR_AFM_LUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_AFM_LUM_OF +#define MRV_ISP_ICR_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_AFM_LUM_OF */ +/* Slice: ICR_AFM_SUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_AFM_SUM_OF +#define MRV_ISP_ICR_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_AFM_SUM_OF */ +/* Slice: ICR_SHUTTER_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_SHUTTER_OFF +#define MRV_ISP_ICR_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_SHUTTER_OFF */ +/* Slice: ICR_SHUTTER_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_SHUTTER_ON +#define MRV_ISP_ICR_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_SHUTTER_ON */ +/* Slice: ICR_FLASH_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_FLASH_OFF +#define MRV_ISP_ICR_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_FLASH_OFF */ +/* Slice: ICR_FLASH_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_FLASH_ON +#define MRV_ISP_ICR_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_FLASH_ON */ +/* Slice: ICR_H_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_H_START +#define MRV_ISP_ICR_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_H_START */ +/* Slice: ICR_V_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_V_START +#define MRV_ISP_ICR_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_V_START */ +/* Slice: ICR_FRAME_IN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_FRAME_IN +#define MRV_ISP_ICR_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_FRAME_IN */ +/* Slice: ICR_AWB_DONE:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_AWB_DONE +#define MRV_ISP_ICR_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_AWB_DONE */ +/* Slice: ICR_PIC_SIZE_ERR:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_PIC_SIZE_ERR +#define MRV_ISP_ICR_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_PIC_SIZE_ERR */ +/* Slice: ICR_DATA_LOSS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_DATA_LOSS +#define MRV_ISP_ICR_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_DATA_LOSS */ +/* Slice: ICR_FRAME:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_FRAME +#define MRV_ISP_ICR_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_FRAME */ +/* Slice: ICR_ISP_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_ISP_OFF +#define MRV_ISP_ICR_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_ISP_OFF */ +/* combination of all interrupt lines */ +#define MRV_ISP_ICR_ALL_IRQS +#define MRV_ISP_ICR_ALL_IRQS_MASK \ +(0 \ + | MRV_ISP_ICR_VSM_END_MASK \ + | MRV_ISP_ICR_EXP_END_MASK \ + | MRV_ISP_ICR_FLASH_CAP_MASK \ + | MRV_ISP_ICR_BP_DET_MASK \ + | MRV_ISP_ICR_HIST_MEASURE_RDY_MASK \ + | MRV_ISP_ICR_AFM_FIN_MASK \ + | MRV_ISP_ICR_AFM_LUM_OF_MASK \ + | MRV_ISP_ICR_AFM_SUM_OF_MASK \ + | MRV_ISP_ICR_SHUTTER_OFF_MASK \ + | MRV_ISP_ICR_SHUTTER_ON_MASK \ + | MRV_ISP_ICR_FLASH_OFF_MASK \ + | MRV_ISP_ICR_FLASH_ON_MASK \ + | MRV_ISP_ICR_H_START_MASK \ + | MRV_ISP_ICR_V_START_MASK \ + | MRV_ISP_ICR_FRAME_IN_MASK \ + | MRV_ISP_ICR_AWB_DONE_MASK \ + | MRV_ISP_ICR_PIC_SIZE_ERR_MASK \ + | MRV_ISP_ICR_DATA_LOSS_MASK \ + | MRV_ISP_ICR_FRAME_MASK \ + | MRV_ISP_ICR_ISP_OFF_MASK \ +) +#define MRV_ISP_ICR_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register: isp_isr: Interrupt set register (0x000001cc) + * + *****************************************************************************/ +/*! Register: isp_isr: Interrupt set register (0x000001cc)*/ +/*! Slice: ISR_VSM_END:*/ +/*! set interrupt */ +#ifndef MRV_ISP_ISR_VSM_END +#define MRV_ISP_ISR_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_VSM_END */ +/* Slice: ISR_EXP_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_EXP_END +#define MRV_ISP_ISR_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_EXP_END */ +/* Slice: ISR_FLASH_CAP:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_FLASH_CAP +#define MRV_ISP_ISR_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_FLASH_CAP */ +/* Slice: ISR_BP_DET:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_BP_DET +#define MRV_ISP_ISR_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_BP_DET */ +/* Slice: ISR_HIST_MEASURE_RDY:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_HIST_MEASURE_RDY +#define MRV_ISP_ISR_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_HIST_MEASURE_RDY */ +/* Slice: ISR_AFM_FIN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_AFM_FIN +#define MRV_ISP_ISR_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !ISR_AFM_FIN */ +/* Slice: ISR_AFM_LUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_AFM_LUM_OF +#define MRV_ISP_ISR_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_AFM_LUM_OF */ +/* Slice: ISR_AFM_SUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_AFM_SUM_OF +#define MRV_ISP_ISR_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_AFM_SUM_OF */ +/* Slice: ISR_SHUTTER_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_SHUTTER_OFF +#define MRV_ISP_ISR_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_SHUTTER_OFF */ +/* Slice: ISR_SHUTTER_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_SHUTTER_ON +#define MRV_ISP_ISR_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_SHUTTER_ON */ +/* Slice: ISR_FLASH_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_FLASH_OFF +#define MRV_ISP_ISR_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_FLASH_OFF */ +/* Slice: ISR_FLASH_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_FLASH_ON +#define MRV_ISP_ISR_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_FLASH_ON */ +/* Slice: ISR_H_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_H_START +#define MRV_ISP_ISR_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_H_START */ +/* Slice: ISR_V_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_V_START +#define MRV_ISP_ISR_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_V_START */ +/* Slice: ISR_FRAME_IN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_FRAME_IN +#define MRV_ISP_ISR_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_FRAME_IN */ +/* Slice: ISR_AWB_DONE:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_AWB_DONE +#define MRV_ISP_ISR_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_AWB_DONE */ +/* Slice: ISR_PIC_SIZE_ERR:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_PIC_SIZE_ERR +#define MRV_ISP_ISR_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_PIC_SIZE_ERR */ +/* Slice: ISR_DATA_LOSS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_DATA_LOSS +#define MRV_ISP_ISR_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_DATA_LOSS */ +/* Slice: ISR_FRAME:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_FRAME +#define MRV_ISP_ISR_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_FRAME */ +/* Slice: ISR_ISP_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_ISP_OFF +#define MRV_ISP_ISR_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_ISP_OFF */ +/* combination of all interrupt lines */ +#define MRV_ISP_ISR_ALL_IRQS +#define MRV_ISP_ISR_ALL_IRQS_MASK \ +(0 \ + | MRV_ISP_ISR_VSM_END_MASK \ + | MRV_ISP_ISR_EXP_END_MASK \ + | MRV_ISP_ISR_FLASH_CAP_MASK \ + | MRV_ISP_ISR_BP_DET_MASK \ + | MRV_ISP_ISR_HIST_MEASURE_RDY_MASK \ + | MRV_ISP_ISR_AFM_FIN_MASK \ + | MRV_ISP_ISR_AFM_LUM_OF_MASK \ + | MRV_ISP_ISR_AFM_SUM_OF_MASK \ + | MRV_ISP_ISR_SHUTTER_OFF_MASK \ + | MRV_ISP_ISR_SHUTTER_ON_MASK \ + | MRV_ISP_ISR_FLASH_OFF_MASK \ + | MRV_ISP_ISR_FLASH_ON_MASK \ + | MRV_ISP_ISR_H_START_MASK \ + | MRV_ISP_ISR_V_START_MASK \ + | MRV_ISP_ISR_FRAME_IN_MASK \ + | MRV_ISP_ISR_AWB_DONE_MASK \ + | MRV_ISP_ISR_PIC_SIZE_ERR_MASK \ + | MRV_ISP_ISR_DATA_LOSS_MASK \ + | MRV_ISP_ISR_FRAME_MASK \ + | MRV_ISP_ISR_ISP_OFF_MASK \ +) +#define MRV_ISP_ISR_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register array: isp_ct_coeff: cross-talk configuration register (color + * correction matrix) (0x03A0 + n*0x4 (n=0..8)) + * + *****************************************************************************/ +/* Slice: ct_coeff:*/ +/* Coefficient n for cross talk matrix.*/ + /**/ +/* Values are 11-bit signed fixed-point numbers with 4 bit integer and */ +/* 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF).*/ +/* 0 is reprsented by 0x000 and a coefficient value of 1 as 0x080.*/ +#ifdef MRV_ISP_CT_COEFF +#define MRV_ISP_CT_COEFF_DEFAULT 0x080U /* default value */ +#endif /* MRV_ISP_CT_COEFF */ +/*****************************************************************************/ +/** + * register: isp_gamma_out_mode: gamma segmentation mode register for output + * gamma (0x000001f4) + * + *****************************************************************************/ +/* Slice: equ_segm:*/ +/* 0: logarithmic like segmentation of gamma curve (default after reset)*/ +/* segmentation from 0 to 4095: 64 64 64 64 128 128 128 128 256 256 256 512 512 512 512 512 */ +/* 1: equidistant segmentation (all 16 segments are 256)*/ +#ifdef MRV_ISP_EQU_SEGM +#define MRV_ISP_EQU_SEGM_LOG 0 /* 0: logarithmic like segmentation of gamma curve (default after reset) */ +#define MRV_ISP_EQU_SEGM_EQU 1 /* 1: equidistant segmentation (all 16 segments are 256) */ +#endif /* MRV_ISP_EQU_SEGM */ +/*****************************************************************************/ +/** + * register array: isp_gamma_out_y: Gamma Out Curve definition y (0x03F0 + n*0x4 (n=0..16)) + * + *****************************************************************************/ +/* Slice: isp_gamma_out_y:*/ +/* Gamma_out curve point definition y-axis (output) for all color */ +/* components (red, green, blue)*/ +/* RESTRICTION: each Y_n must be in the +511/-512 range compared */ +/* to its predecessor (so that dy is 10-bit signed !)*/ +#ifdef MRV_ISP_ISP_GAMMA_OUT_Y +#endif /* MRV_ISP_ISP_GAMMA_OUT_Y */ +/*****************************************************************************/ +/** + * register: isp_err: ISP error register (0x0000023c) + * + *****************************************************************************/ +/* Slice: outform_size_err:*/ +/* size error is generated in outmux submodule */ +#ifdef MRV_ISP_OUTFORM_SIZE_ERR +#endif /* MRV_ISP_OUTFORM_SIZE_ERR */ +/* Slice: is_size_err:*/ +/* size error is generated in image stabilization submodule */ +#ifdef MRV_ISP_IS_SIZE_ERR +#endif /* MRV_ISP_IS_SIZE_ERR */ +/* Slice: inform_size_err:*/ +/* size error is generated in inform submodule */ +#ifdef MRV_ISP_INFORM_SIZE_ERR +#endif /* MRV_ISP_INFORM_SIZE_ERR */ +/*****************************************************************************/ +/** + * register: isp_err_clr: ISP error clear register (0x00000240) + * + *****************************************************************************/ +/* Slice: outform_size_err_clr:*/ +/* size error is cleared */ +#ifdef MRV_ISP_OUTFORM_SIZE_ERR_CLR +#endif /* MRV_ISP_OUTFORM_SIZE_ERR_CLR */ +/* Slice: is_size_err_clr:*/ +/* size error is cleared */ +#ifdef MRV_ISP_IS_SIZE_ERR_CLR +#endif /* MRV_ISP_IS_SIZE_ERR_CLR */ +/* Slice: inform_size_err_clr:*/ +/* size error is cleared */ +#ifdef MRV_ISP_INFORM_SIZE_ERR_CLR +#endif /* MRV_ISP_INFORM_SIZE_ERR_CLR */ +/*****************************************************************************/ +/** + * register: isp_frame_count: Frame counter (0x00000244) + * + *****************************************************************************/ +/* Slice: frame_counter:*/ +/* Current frame count of processing */ +#ifdef MRV_ISP_FRAME_COUNTER +#endif /* MRV_ISP_FRAME_COUNTER */ +/*****************************************************************************/ +/** + * register: isp_ct_offset_r: cross-talk offset red (0x00000248) + * + *****************************************************************************/ +/* Slice: ct_offset_r:*/ +/* Offset red for cross talk matrix. Two's complement integer number ranging */ +/* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/ +#ifdef MRV_ISP_CT_OFFSET_R +#define MRV_ISP_CT_OFFSET_R_DEFAULT 0x000U /* default value */ +#endif /* MRV_ISP_CT_OFFSET_R */ +/*****************************************************************************/ +/** + * register: isp_ct_offset_g: cross-talk offset green (0x0000024c) + * + *****************************************************************************/ +/* Slice: ct_offset_g:*/ +/* Offset green for cross talk matrix. Two's complement integer number ranging */ +/* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/ +#ifdef MRV_ISP_CT_OFFSET_G +#define MRV_ISP_CT_OFFSET_G_DEFAULT 0x000U /* default value */ +#endif /* MRV_ISP_CT_OFFSET_G */ +/*****************************************************************************/ +/** + * register: isp_ct_offset_b: cross-talk offset blue (0x00000250) + * + *****************************************************************************/ +/* Slice: ct_offset_b:*/ +/* Offset blue for cross talk matrix. Two's complement integer number ranging */ +/* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/ +#ifdef MRV_ISP_CT_OFFSET_B +#define MRV_ISP_CT_OFFSET_B_DEFAULT 0x000U /* default value */ +#endif /* MRV_ISP_CT_OFFSET_B */ +/*****************************************************************************/ +/* ISP Flash Module Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_flash_cmd: Flash command (0x0000) + * + *****************************************************************************/ +/* Slice: preflash_on:*/ +/* preflash on */ +/* 0: no effect */ +/* 1: flash delay counter is started at next trigger event */ +/* No capture event is signaled to the sensor interface block.*/ +#ifdef MRV_FLASH_PREFLASH_ON +#endif /* MRV_FLASH_PREFLASH_ON */ +/* Slice: flash_on:*/ +/* flash on */ +/* 0: no effect */ +/* 1: flash delay counter is started at next trigger event */ +/* A capture event is signaled to the sensor interface block.*/ +#ifdef MRV_FLASH_FLASH_ON +#endif /* MRV_FLASH_FLASH_ON */ +/* Slice: prelight_on:*/ +/* prelight on */ +/* 0: prelight is switched off at next trigger event */ +/* 1: prelight is switched on at next trigger event */ +#ifdef MRV_FLASH_PRELIGHT_ON +#endif /* MRV_FLASH_PRELIGHT_ON */ +/*****************************************************************************/ +/** + * register: isp_flash_config: Flash config (0x0004) + * + *****************************************************************************/ +/* Slice: fl_cap_del:*/ +/* capture delay */ +/* frame number (0 to 15) to be captured after trigger event */ +#ifdef MRV_FLASH_FL_CAP_DEL +#endif /* MRV_FLASH_FL_CAP_DEL */ +/* Slice: fl_trig_src:*/ +/* trigger source for flash and prelight */ +/* 0: use "vds_vsync" for trigger event (with evaluation of vs_in_edge)*/ +/* 1: use "fl_trig" for trigger event (positive edge)*/ +#ifdef MRV_FLASH_FL_TRIG_SRC +#define MRV_FLASH_FL_TRIG_SRC_VDS 0 /* 0: use "vds_vsync" for trigger event (with evaluation of vs_in_edge) */ +#define MRV_FLASH_FL_TRIG_SRC_FL 1 /* 1: use "fl_trig" for trigger event (positive edge) */ +#endif /* MRV_FLASH_FL_TRIG_SRC */ +/* Slice: fl_pol:*/ +/* polarity of flash related signals */ +/* 0: flash_trig, prelight_trig are high active */ +/* 1: flash_trig, prelight_trig are low active */ +#ifdef MRV_FLASH_FL_POL +#define MRV_FLASH_FL_POL_HIGH 0 /* 0: flash_trig, prelight_trig are high active */ +#define MRV_FLASH_FL_POL_LOW 1 /* 1: flash_trig, prelight_trig are low active */ +#endif /* MRV_FLASH_FL_POL */ +/* Slice: vs_in_edge:*/ +/* VSYNC edge */ +/* 0: use negative edge of "vds_vsync" if generating a trigger event */ +/* 1: use positive edge of "vds_vsync" if generating a trigger event */ +#ifdef MRV_FLASH_VS_IN_EDGE +#define MRV_FLASH_VS_IN_EDGE_NEG 0 /* 0: use negative edge of "vds_vsync" if generating a trigger event */ +#define MRV_FLASH_VS_IN_EDGE_POS 1 /* 1: use positive edge of "vds_vsync" if generating a trigger event */ +#endif /* MRV_FLASH_VS_IN_EDGE */ +/* Slice: prelight_mode:*/ +/* prelight mode */ +/* 0: prelight is switched off at begin of flash */ +/* 1: prelight is switched off at end of flash */ +#ifdef MRV_FLASH_PRELIGHT_MODE +#define MRV_FLASH_PRELIGHT_MODE_OASF 0 /* 0: prelight is switched off at begin of flash */ +#define MRV_FLASH_PRELIGHT_MODE_OAEF 1 /* 1: prelight is switched off at end of flash */ +#endif /* MRV_FLASH_PRELIGHT_MODE */ +/*****************************************************************************/ +/** + * register: isp_flash_prediv: Flash Counter Pre-Divider (0x00000008) + * + *****************************************************************************/ +/* Slice: fl_pre_div:*/ +/* pre-divider for flush/preflash counter */ +#ifdef MRV_FLASH_FL_PRE_DIV +#endif /* MRV_FLASH_FL_PRE_DIV */ +/*****************************************************************************/ +/** + * register: isp_flash_delay: Flash Delay (0x000c) + * + *****************************************************************************/ +/* Slice: fl_delay:*/ +/* counter value for flash/preflash delay */ +/* open_delay = (fl_delay + 1) * (fl_pre_div+1) / clk_isp */ +/* fl_delay = (open_delay * clk_isp) / (fl_pre_div+1) - 1 */ +#ifdef MRV_FLASH_FL_DELAY +#endif /* MRV_FLASH_FL_DELAY */ +/*****************************************************************************/ +/** + * register: isp_flash_time: Flash time (0x00000010) + * + *****************************************************************************/ +/* Slice: fl_time:*/ +/* counter value for flash/preflash time */ +/* open_time = (fl_time + 1) * (fl_pre_div+1) / clk_isp */ +/* fl_time = (open_time * clk_isp) / (fl_pre_div+1) - 1 */ +#ifdef MRV_FLASH_FL_TIME +#endif /* MRV_FLASH_FL_TIME */ +/*****************************************************************************/ +/** + * register: isp_flash_maxp: Maximum value for flash or preflash (0x00000014) + * + *****************************************************************************/ +/* Slice: fl_maxp:*/ +/* maximum period value for flash or preflash */ +/* max. flash/preflash period = 214 * (fl_maxp + 1) / clk_isp */ +/* fl_maxp = (max_period * clk_isp) / 214 - 1 */ +#ifdef MRV_FLASH_FL_MAXP +#endif /* MRV_FLASH_FL_MAXP */ +/*****************************************************************************/ +/* ISP Shutter Module Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_sh_ctrl: mechanical shutter control (0x0000) + * + *****************************************************************************/ +/* Slice: sh_open_pol:*/ +/* shutter_open polarity */ +/* 0: shutter_open is high active */ +/* 1: shutter_open is low active */ +#ifdef MRV_SHUT_SH_OPEN_POL +#define MRV_SHUT_SH_OPEN_POL_HIGH 0 /* 0: shutter_open is high active */ +#define MRV_SHUT_SH_OPEN_POL_LOW 1 /* 1: shutter_open is low active */ +#endif /* MRV_SHUT_SH_OPEN_POL */ +/* Slice: sh_trig_en:*/ +/* mechanical shutter trigger edge */ +/* 0: use negative edge of trigger signal */ +/* 1: use positive edge of trigger signal */ +#ifdef MRV_SHUT_SH_TRIG_EN +#define MRV_SHUT_SH_TRIG_EN_NEG 0 /* 0: use negative edge of trigger signal */ +#define MRV_SHUT_SH_TRIG_EN_POS 1 /* 1: use positive edge of trigger signal */ +#endif /* MRV_SHUT_SH_TRIG_EN */ +/* Slice: sh_trig_src:*/ +/* mechanical shutter trigger source */ +/* 0: use "vds_vsync" for trigger event */ +/* 1: use "shutter_trig" for trigger event */ +#ifdef MRV_SHUT_SH_TRIG_SRC +#define MRV_SHUT_SH_TRIG_SRC_VDS 0 /* 0: use "vds_vsync" for trigger event */ +#define MRV_SHUT_SH_TRIG_SRC_SHUT 1 /* 1: use "shutter_trig" for trigger event */ +#endif /* MRV_SHUT_SH_TRIG_SRC */ +/* Slice: sh_rep_en:*/ +/* mechanical shutter repetition enable */ +/* 0: shutter is opened only once */ +/* 1: shutter is opened with the repetition rate of the trigger signal */ +#ifdef MRV_SHUT_SH_REP_EN +#define MRV_SHUT_SH_REP_EN_ONCE 0 /* 0: shutter is opened only once */ +#define MRV_SHUT_SH_REP_EN_REP 1 /* 1: shutter is opened with the repetition rate of the trigger signal */ +#endif /* MRV_SHUT_SH_REP_EN */ +/* Slice: sh_en:*/ +/* mechanical shutter enable */ +/* 0: mechanical shutter function is disabled */ +/* 1: mechanical shutter function is enabled */ +#ifdef MRV_SHUT_SH_EN +#endif /* MRV_SHUT_SH_EN */ +/*****************************************************************************/ +/** + * register: isp_sh_prediv: Mech. Shutter Counter Pre-Divider (0x0004) + * + *****************************************************************************/ +/* Slice: sh_pre_div:*/ +/* pre-divider for mechanical shutter open_delay and open_time counter */ +#ifdef MRV_SHUT_SH_PRE_DIV +#endif /* MRV_SHUT_SH_PRE_DIV */ +/*****************************************************************************/ +/** + * register: isp_sh_delay: Delay register (0x00000008) + * + *****************************************************************************/ +/* Slice: sh_delay:*/ +/* counter value for delay */ +/* open_delay = (sh_delay + 1) * (fl_pre_div+1) / clk_isp */ +/* sh_delay = (open_delay * clk_isp) / (sh_pre_div+1) – 1 */ +#ifdef MRV_SHUT_SH_DELAY +#endif /* MRV_SHUT_SH_DELAY */ +/*****************************************************************************/ +/** + * register: isp_sh_time: Time register (0x0000000c) + * + *****************************************************************************/ +/* Slice: sh_time:*/ +/* counter value for time */ +/* open_time = (sh_time + 1) * (fl_pre_div+1) / clk_isp */ +/* sh_time = (open_time * clk_isp) / (sh_pre_div+1) - 1 */ +#ifndef MRV_SHUT_SH_TIME +#endif /* MRV_SHUT_SH_TIME */ +/*****************************************************************************/ +/* Color Processing Module Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: c_proc_ctrl: Global control register (0x0000) + * + *****************************************************************************/ +/* Slice: cproc_c_out_range:*/ +/* Color processing chrominance pixel clipping range at output */ +/* 0: CbCr_out clipping range 16..240 according to ITU-R BT.601 standard */ +/* 1: full UV_out clipping range 0..255 */ +#ifdef MRV_CPROC_CPROC_C_OUT_RANGE +#define MRV_CPROC_CPROC_C_OUT_RANGE_BT601 0 /* 0: CbCr_out clipping range 16..240 according to ITU-R BT.601 standard */ +#define MRV_CPROC_CPROC_C_OUT_RANGE_FULL 1 /* 1: full UV_out clipping range 0..255 */ +#endif /* MRV_CPROC_CPROC_C_OUT_RANGE */ +/* Slice: cproc_y_in_range:*/ +/* Color processing luminance input range (offset processing)*/ +/* 0: Y_in range 64..940 according to ITU-R BT.601 standard;*/ +/* offset of 64 will be subtracted from Y_in */ +/* 1: Y_in full range 0..1023; no offset will be subtracted from Y_in */ +#ifdef MRV_CPROC_CPROC_Y_IN_RANGE +#define MRV_CPROC_CPROC_Y_IN_RANGE_BT601 0 /* 0: Y_in range 64..940 according to ITU-R BT.601 standard */ +#define MRV_CPROC_CPROC_Y_IN_RANGE_FULL 1 /* 1: Y_in full range 0..1023 */ +#endif /* MRV_CPROC_CPROC_Y_IN_RANGE */ +/* Slice: cproc_y_out_range:*/ +/* Color processing luminance output clipping range */ +/* 0: Y_out clipping range 16..235; offset of 16 is added to Y_out according to ITU-R BT.601 standard */ +/* 1: Y_out clipping range 0..255; no offset is added to Y_out */ +#ifdef MRV_CPROC_CPROC_Y_OUT_RANGE +#define MRV_CPROC_CPROC_Y_OUT_RANGE_BT601 0 /* 0: Y_out clipping range 16..235; offset of 16 is added to Y_out according to ITU-R BT.601 standard */ +#define MRV_CPROC_CPROC_Y_OUT_RANGE_FULL 1 /* 1: Y_out clipping range 0..255; no offset is added to Y_out */ +#endif /* MRV_CPROC_CPROC_Y_OUT_RANGE */ +/* Slice: cproc_enable:*/ +/* color processing enable */ +/* 0: color processing is bypassed */ +/* 2 * 10 Bit input data are truncated to 2 * 8Bit output data */ +/* 1: color processing is active */ +/* output data are rounded to 2 * 8Bit and clipping is active */ +#ifdef MRV_CPROC_CPROC_ENABLE +#define MRV_CPROC_CPROC_ENABLE_PROCESS 1 /* 1: processing is activated */ +#define MRV_CPROC_CPROC_ENABLE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */ +#endif /* MRV_CPROC_CPROC_ENABLE */ +/*****************************************************************************/ +/** + * register: c_proc_contrast: Color Processing contrast register (0x0004) + * + *****************************************************************************/ +/* Slice: cproc_contrast:*/ +/* contrast adjustment value */ +/* 00H equals x 0.0 */ +/* ...*/ +/* 80H equals x 1.0 */ +/* ...*/ +/* FFH equals x 1.992 */ +#ifdef MRV_CPROC_CPROC_CONTRAST +#endif /* MRV_CPROC_CPROC_CONTRAST */ +/*****************************************************************************/ +/** + * register: c_proc_brightness: Color Processing brightness register (0x0008) + * + *****************************************************************************/ +/* Slice: cproc_brightness:*/ +/* brightness adjustment value */ +/* 80H equals -128 */ +/* ...*/ +/* 00H equals +0 */ +/* ...*/ +/* 7FH equals +127 */ +#ifdef MRV_CPROC_CPROC_BRIGHTNESS +#endif /* MRV_CPROC_CPROC_BRIGHTNESS */ +/*****************************************************************************/ +/** + * register: c_proc_saturation: Color Processing saturation register (0x000c) + * + *****************************************************************************/ +/* Slice: cproc_saturation:*/ +/* saturation adjustment value */ +/* 00H equals x 0.0 */ +/* ...*/ +/* 80H equals x 1.0 */ +/* ...*/ +/* FFH equals x 1.992 */ +#ifdef MRV_CPROC_CPROC_SATURATION +#endif /* MRV_CPROC_CPROC_SATURATION */ +/*****************************************************************************/ +/** + * register: c_proc_hue: Color Processing hue register (0x0010) + * + *****************************************************************************/ +/* Slice: cproc_hue:*/ +/* hue adjustment value */ +/* 80H equals -90 deg */ +/* ...*/ +/* 00H equals 0 deg */ +/* ...*/ +/* 7FH equals +87.188 deg */ +#ifdef MRV_CPROC_CPROC_HUE +#endif /* MRV_CPROC_CPROC_HUE */ +/*****************************************************************************/ +/* Main Resizer/Scaler Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: mrsz_ctrl: global control register (0x00000000) + * + *****************************************************************************/ +/* Slice: cfg_upd:*/ +/* write 0: nothing happens */ +/* write 1: update shadow registers */ +/* read: always 0 */ +#ifdef MRV_MRSZ_CFG_UPD +#endif /* MRV_MRSZ_CFG_UPD */ +/* Slice: scale_vc_up:*/ +/* 1: vertical chrominance upscaling selected */ +/* 0: vertical chrominance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_VC_UP +#define MRV_MRSZ_SCALE_VC_UP_UPSCALE 1 /* 1: vertical chrominance upscaling selected */ +#define MRV_MRSZ_SCALE_VC_UP_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_VC_UP */ +/* Slice: scale_vy_up:*/ +/* 1: vertical luminance upscaling selected */ +/* 0: vertical luminance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_VY_UP +#define MRV_MRSZ_SCALE_VY_UP_UPSCALE 1 /* 1: vertical luminance upscaling selected */ +#define MRV_MRSZ_SCALE_VY_UP_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_VY_UP */ +/* Slice: scale_hc_up:*/ +/* 1: horizontal chrominance upscaling selected */ +/* 0: horizontal chrominance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_HC_UP +#define MRV_MRSZ_SCALE_HC_UP_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */ +#define MRV_MRSZ_SCALE_HC_UP_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_HC_UP */ +/* Slice: scale_hy_up:*/ +/* 1: horizontal luminance upscaling selected */ +/* 0: horizontal luminance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_HY_UP +#define MRV_MRSZ_SCALE_HY_UP_UPSCALE 1 /* 1: horizontal luminance upscaling selected */ +#define MRV_MRSZ_SCALE_HY_UP_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_HY_UP */ +/* Slice: scale_vc_enable:*/ +/* 0: bypass vertical chrominance scaling unit */ +/* 1: enable vertical chrominance scaling unit */ +#ifdef MRV_MRSZ_SCALE_VC_ENABLE +#define MRV_MRSZ_SCALE_VC_ENABLE_PROCESS 1 /* 1: enable vertical chrominance scaling unit */ +#define MRV_MRSZ_SCALE_VC_ENABLE_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */ +#endif /* MRV_MRSZ_SCALE_VC_ENABLE */ +/* Slice: scale_vy_enable:*/ +/* 0: bypass vertical luminance scaling unit */ +/* 1: enable vertical luminance scaling unit */ +#ifdef MRV_MRSZ_SCALE_VY_ENABLE +#define MRV_MRSZ_SCALE_VY_ENABLE_PROCESS 1 /* 1: enable vertical luminance scaling unit */ +#define MRV_MRSZ_SCALE_VY_ENABLE_BYPASS 0 /* 0: bypass vertical luminance scaling unit */ +#endif /* MRV_MRSZ_SCALE_VY_ENABLE */ +/* Slice: scale_hc_enable:*/ +/* 0: bypass horizontal chrominance scaling unit */ +/* 1: enable horizontal chrominance scaling unit */ +#ifdef MRV_MRSZ_SCALE_HC_ENABLE +#define MRV_MRSZ_SCALE_HC_ENABLE_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */ +#define MRV_MRSZ_SCALE_HC_ENABLE_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */ +#endif /* MRV_MRSZ_SCALE_HC_ENABLE */ +/* Slice: scale_hy_enable:*/ +/* 0: bypass horizontal luminance scaling unit */ +/* 1: enable horizontal luminance scaling unit */ +#ifdef MRV_MRSZ_SCALE_HY_ENABLE +#define MRV_MRSZ_SCALE_HY_ENABLE_PROCESS 1 /* 1: enable horizontal luminance scaling unit */ +#define MRV_MRSZ_SCALE_HY_ENABLE_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */ +#endif /* MRV_MRSZ_SCALE_HY_ENABLE */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hy: horizontal luminance scale factor register + * (0x00000004) + * + *****************************************************************************/ +/* Slice: scale_hy:*/ +/* This register is set to the horizontal luminance downscale factor or to */ +/* the reciprocal of the horizontal luminance upscale factor */ +#ifdef MRV_MRSZ_SCALE_HY +#endif /* MRV_MRSZ_SCALE_HY */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hcb: horizontal Cb scale factor register (0x00000008) + * + *****************************************************************************/ +/* Slice: scale_hcb:*/ +/* This register is set to the horizontal Cb downscale factor or to the */ +/* reciprocal of the horizontal Cb upscale factor */ +#ifdef MRV_MRSZ_SCALE_HCB +#endif /* MRV_MRSZ_SCALE_HCB */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hcr: horizontal Cr scale factor register (0x0000000c) + * + *****************************************************************************/ +/* Slice: scale_hcr:*/ +/* This register is set to the horizontal Cr downscale factor or to the */ +/* reciprocal of the horizontal Cr upscale factor */ +#ifdef MRV_MRSZ_SCALE_HCR +#endif /* MRV_MRSZ_SCALE_HCR */ +/*****************************************************************************/ +/** + * register: mrsz_scale_vy: vertical luminance scale factor register (0x00000010) + * + *****************************************************************************/ +/* Slice: scale_vy:*/ +/* This register is set to the vertical luminance downscale factor or to the */ +/* reciprocal of the vertical luminance upscale factor */ +#ifdef MRV_MRSZ_SCALE_VY +#endif /* MRV_MRSZ_SCALE_VY */ +/*****************************************************************************/ +/** + * register: mrsz_scale_vc: vertical chrominance scale factor register (0x00000014) + * + *****************************************************************************/ +/* Slice: scale_vc:*/ +/* This register is set to the vertical chrominance downscale factor or to the */ +/* reciprocal of the vertical chrominance upscale factor */ +#ifdef MRV_MRSZ_SCALE_VC +#endif /* MRV_MRSZ_SCALE_VC */ +/*****************************************************************************/ +/** + * register: mrsz_phase_hy: horizontal luminance phase register (0x00000018) + * + *****************************************************************************/ +/* Slice: phase_hy:*/ +/* This register is set to the horizontal luminance phase offset */ +#ifdef MRV_MRSZ_PHASE_HY +#endif /* MRV_MRSZ_PHASE_HY */ +/*****************************************************************************/ +/** + * register: mrsz_phase_hc: horizontal chrominance phase register (0x0000001c) + * + *****************************************************************************/ +/* Slice: phase_hc:*/ +/* This register is set to the horizontal chrominance phase offset */ +#ifdef MRV_MRSZ_PHASE_HC +#endif /* MRV_MRSZ_PHASE_HC */ +/*****************************************************************************/ +/** + * register: mrsz_phase_vy: vertical luminance phase register (0x00000020) + * + *****************************************************************************/ +/* Slice: phase_vy:*/ +/* This register is set to the vertical luminance phase offset */ +#ifdef MRV_MRSZ_PHASE_VY +#endif /* MRV_MRSZ_PHASE_VY */ +/*****************************************************************************/ +/** + * register: mrsz_phase_vc: vertical chrominance phase register (0x00000024) + * + *****************************************************************************/ +/* Slice: phase_vc:*/ +/* This register is set to the vertical chrominance phase offset */ +#ifdef MRV_MRSZ_PHASE_VC +#endif /* MRV_MRSZ_PHASE_VC */ +/*****************************************************************************/ +/** + * register: mrsz_scale_lut_addr: Address pointer of up-scaling look up table + * (0x00000028) + * + *****************************************************************************/ +/* Slice: scale_lut_addr:*/ +/* Pointer to entry of lookup table */ +#ifdef MRV_MRSZ_SCALE_LUT_ADDR +#endif /* MRV_MRSZ_SCALE_LUT_ADDR */ +/*****************************************************************************/ +/** + * register: mrsz_scale_lut: Entry of up-scaling look up table (0x0000002c) + * + *****************************************************************************/ +/* Slice: scale_lut:*/ +/* Entry of lookup table at position scale_lut_addr. The lookup table must be */ +/* filled with appropriate values before the up-scaling functionality can be */ +/* used.*/ +#ifdef MRV_MRSZ_SCALE_LUT +#endif /* MRV_MRSZ_SCALE_LUT */ +/*****************************************************************************/ +/** + * register: mrsz_ctrl_shd: global control shadow register (0x0030) + * + *****************************************************************************/ +/* Slice: scale_vc_up_shd:*/ +/* 1: vertical chrominance upscaling selected */ +/* 0: vertical chrominance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_VC_UP_SHD +#define MRV_MRSZ_SCALE_VC_UP_SHD_UPSCALE 1 /* 1: vertical chrominance upscaling selected */ +#define MRV_MRSZ_SCALE_VC_UP_SHD_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_VC_UP_SHD */ +/* Slice: scale_vy_up_shd:*/ +/* 1: vertical luminance upscaling selected */ +/* 0: vertical luminance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_VY_UP_SHD +#define MRV_MRSZ_SCALE_VY_UP_SHD_UPSCALE 1 /* 1: vertical luminance upscaling selected */ +#define MRV_MRSZ_SCALE_VY_UP_SHD_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_VY_UP_SHD */ +/* Slice: scale_hc_up_shd:*/ +/* 1: horizontal chrominance upscaling selected */ +/* 0: horizontal chrominance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_HC_UP_SHD +#define MRV_MRSZ_SCALE_HC_UP_SHD_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */ +#define MRV_MRSZ_SCALE_HC_UP_SHD_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_HC_UP_SHD */ +/* Slice: scale_hy_up_shd:*/ +/* 1: horizontal luminance upscaling selected */ +/* 0: horizontal luminance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_HY_UP_SHD +#define MRV_MRSZ_SCALE_HY_UP_SHD_UPSCALE 1 /* 1: horizontal luminance upscaling selected */ +#define MRV_MRSZ_SCALE_HY_UP_SHD_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_HY_UP_SHD */ +/* Slice: scale_vc_enable_shd:*/ +/* 0: bypass vertical chrominance scaling unit */ +/* 1: enable vertical chrominance scaling unit */ +#ifdef MRV_MRSZ_SCALE_VC_ENABLE_SHD +#define MRV_MRSZ_SCALE_VC_ENABLE_SHD_PROCESS 1 /* 1: enable vertical chrominance scaling unit */ +#define MRV_MRSZ_SCALE_VC_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */ +#endif /* MRV_MRSZ_SCALE_VC_ENABLE_SHD */ +/* Slice: scale_vy_enable_shd:*/ +/* 0: bypass vertical luminance scaling unit */ +/* 1: enable vertical luminance scaling unit */ +#ifdef MRV_MRSZ_SCALE_VY_ENABLE_SHD +#define MRV_MRSZ_SCALE_VY_ENABLE_SHD_PROCESS 1 /* 1: enable vertical luminance scaling unit */ +#define MRV_MRSZ_SCALE_VY_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical luminance scaling unit */ +#endif /* MRV_MRSZ_SCALE_VY_ENABLE_SHD */ +/* Slice: scale_hc_enable_shd:*/ +/* 0: bypass horizontal chrominance scaling unit */ +/* 1: enable horizontal chrominance scaling unit */ +#ifdef MRV_MRSZ_SCALE_HC_ENABLE_SHD +#define MRV_MRSZ_SCALE_HC_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */ +#define MRV_MRSZ_SCALE_HC_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */ +#endif /* MRV_MRSZ_SCALE_HC_ENABLE_SHD */ +/* Slice: scale_hy_enable_shd:*/ +/* 0: bypass horizontal luminance scaling unit */ +/* 1: enable horizontal luminance scaling unit */ +#ifdef MRV_MRSZ_SCALE_HY_ENABLE_SHD +#define MRV_MRSZ_SCALE_HY_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal luminance scaling unit */ +#define MRV_MRSZ_SCALE_HY_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */ +#endif /* MRV_MRSZ_SCALE_HY_ENABLE_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hy_shd: horizontal luminance scale factor shadow + * register (0x00000034) + * + *****************************************************************************/ +/* Slice: scale_hy_shd:*/ +/* This register is set to the horizontal luminance downscale factor or to the */ +/* reciprocal of the horizontal luminance upscale factor */ +#ifdef MRV_MRSZ_SCALE_HY_SHD +#endif /* MRV_MRSZ_SCALE_HY_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hcb_shd: horizontal Cb scale factor shadow register + * (0x00000038) + * + *****************************************************************************/ +/* Slice: scale_hcb_shd:*/ +/* This register is set to the horizontal Cb downscale factor or to the */ +/* reciprocal of the horizontal Cb upscale factor */ +#ifdef MRV_MRSZ_SCALE_HCB_SHD +#endif /* MRV_MRSZ_SCALE_HCB_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hcr_shd: horizontal Cr scale factor shadow register + * (0x0000003c) + * + *****************************************************************************/ +/* Slice: scale_hcr_shd:*/ +/* This register is set to the horizontal Cr downscale factor or to the */ +/* reciprocal of the horizontal Cr upscale factor */ +#ifdef MRV_MRSZ_SCALE_HCR_SHD +#endif /* MRV_MRSZ_SCALE_HCR_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_scale_vy_shd: vertical luminance scale factor shadow register + * (0x00000040) + * + *****************************************************************************/ +/* Slice: scale_vy_shd:*/ +/* This register is set to the vertical luminance downscale factor or to the */ +/* reciprocal of the vertical luminance upscale factor */ +#ifdef MRV_MRSZ_SCALE_VY_SHD +#endif /* MRV_MRSZ_SCALE_VY_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_scale_vc_shd: vertical chrominance scale factor shadow + * register (0x00000044) + * + *****************************************************************************/ +/* Slice: scale_vc_shd:*/ +/* This register is set to the vertical chrominance downscale factor or to */ +/* the reciprocal of the vertical chrominance upscale factor */ +#ifdef MRV_MRSZ_SCALE_VC_SHD +#endif /* MRV_MRSZ_SCALE_VC_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_phase_hy_shd: horizontal luminance phase shadow register + * (0x00000048) + * + *****************************************************************************/ +/* Slice: phase_hy_shd:*/ +/* This register is set to the horizontal luminance phase offset */ +#ifdef MRV_MRSZ_PHASE_HY_SHD +#endif /* MRV_MRSZ_PHASE_HY_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_phase_hc_shd: horizontal chrominance phase shadow register + * (0x0000004c) + * + *****************************************************************************/ +/* Slice: phase_hc_shd:*/ +/* This register is set to the horizontal chrominance phase offset */ +#ifdef MRV_MRSZ_PHASE_HC_SHD +#endif /* MRV_MRSZ_PHASE_HC_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_phase_vy_shd: vertical luminance phase shadow register + * (0x00000050) + * + *****************************************************************************/ +/* Slice: phase_vy_shd:*/ +/* This register is set to the vertical luminance phase offset */ +#ifdef MRV_MRSZ_PHASE_VY_SHD +#endif /* MRV_MRSZ_PHASE_VY_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_phase_vc_shd: vertical chrominance phase shadow register + * (0x00000054) + * + *****************************************************************************/ +/* Slice: phase_vc_shd:*/ +/* This register is set to the vertical chrominance phase offset */ +#ifdef MRV_MRSZ_PHASE_VC_SHD +#endif /* MRV_MRSZ_PHASE_VC_SHD */ +/*****************************************************************************/ +/* Self Resizer/Scaler Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: srsz_ctrl: global control register (0x00000000) + * + *****************************************************************************/ +/* Slice: cfg_upd:*/ +/* write 0: nothing happens */ +/* write 1: update shadow registers */ +/* read: always 0 */ +#ifdef MRV_SRSZ_CFG_UPD +#endif /* MRV_SRSZ_CFG_UPD */ +/* Slice: scale_vc_up:*/ +/* 1: vertical chrominance upscaling selected */ +/* 0: vertical chrominance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_VC_UP +#define MRV_SRSZ_SCALE_VC_UP_UPSCALE 1 /* 1: vertical chrominance upscaling selected */ +#define MRV_SRSZ_SCALE_VC_UP_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_VC_UP */ +/* Slice: scale_vy_up:*/ +/* 1: vertical luminance upscaling selected */ +/* 0: vertical luminance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_VY_UP +#define MRV_SRSZ_SCALE_VY_UP_UPSCALE 1 /* 1: vertical luminance upscaling selected */ +#define MRV_SRSZ_SCALE_VY_UP_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_VY_UP */ +/* Slice: scale_hc_up:*/ +/* 1: horizontal chrominance upscaling selected */ +/* 0: horizontal chrominance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_HC_UP +#define MRV_SRSZ_SCALE_HC_UP_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */ +#define MRV_SRSZ_SCALE_HC_UP_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_HC_UP */ +/* Slice: scale_hy_up:*/ +/* 1: horizontal luminance upscaling selected */ +/* 0: horizontal luminance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_HY_UP +#define MRV_SRSZ_SCALE_HY_UP_UPSCALE 1 /* 1: horizontal luminance upscaling selected */ +#define MRV_SRSZ_SCALE_HY_UP_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_HY_UP */ +/* Slice: scale_vc_enable:*/ +/* 0: bypass vertical chrominance scaling unit */ +/* 1: enable vertical chrominance scaling unit */ +#ifdef MRV_SRSZ_SCALE_VC_ENABLE +#define MRV_SRSZ_SCALE_VC_ENABLE_PROCESS 1 /* 1: enable vertical chrominance scaling unit */ +#define MRV_SRSZ_SCALE_VC_ENABLE_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */ +#endif /* MRV_SRSZ_SCALE_VC_ENABLE */ +/* Slice: scale_vy_enable:*/ +/* 0: bypass vertical luminance scaling unit */ +/* 1: enable vertical luminance scaling unit */ +#ifdef MRV_SRSZ_SCALE_VY_ENABLE +#define MRV_SRSZ_SCALE_VY_ENABLE_PROCESS 1 /* 1: enable vertical luminance scaling unit */ +#define MRV_SRSZ_SCALE_VY_ENABLE_BYPASS 0 /* 0: bypass vertical luminance scaling unit */ +#endif /* MRV_SRSZ_SCALE_VY_ENABLE */ +/* Slice: scale_hc_enable:*/ +/* 0: bypass horizontal chrominance scaling unit */ +/* 1: enable horizontal chrominance scaling unit */ +#ifdef MRV_SRSZ_SCALE_HC_ENABLE +#define MRV_SRSZ_SCALE_HC_ENABLE_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */ +#define MRV_SRSZ_SCALE_HC_ENABLE_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */ +#endif /* MRV_SRSZ_SCALE_HC_ENABLE */ +/* Slice: scale_hy_enable:*/ +/* 0: bypass horizontal luminance scaling unit */ +/* 1: enable horizontal luminance scaling unit */ +#ifdef MRV_SRSZ_SCALE_HY_ENABLE +#define MRV_SRSZ_SCALE_HY_ENABLE_PROCESS 1 /* 1: enable horizontal luminance scaling unit */ +#define MRV_SRSZ_SCALE_HY_ENABLE_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */ +#endif /* MRV_SRSZ_SCALE_HY_ENABLE */ +/*****************************************************************************/ +/** + * register: srsz_scale_hy: horizontal luminance scale factor register + * (0x00000004) + * + *****************************************************************************/ +/* Slice: scale_hy:*/ +/* This register is set to the horizontal luminance downscale factor or to */ +/* the reciprocal of the horizontal luminance upscale factor */ +#ifdef MRV_SRSZ_SCALE_HY +#endif /* MRV_SRSZ_SCALE_HY */ +/*****************************************************************************/ +/** + * register: srsz_scale_hcb: horizontal Cb scale factor register (0x00000008) + * + *****************************************************************************/ +/* Slice: scale_hcb:*/ +/* This register is set to the horizontal Cb downscale factor or to the */ +/* reciprocal of the horizontal Cb upscale factor */ +#ifdef MRV_SRSZ_SCALE_HCB +#endif /* MRV_SRSZ_SCALE_HCB */ +/*****************************************************************************/ +/** + * register: srsz_scale_hcr: horizontal Cr scale factor register (0x0000000c) + * + *****************************************************************************/ +/* Slice: scale_hcr:*/ +/* This register is set to the horizontal Cr downscale factor or to the */ +/* reciprocal of the horizontal Cr upscale factor */ +#ifdef MRV_SRSZ_SCALE_HCR +#endif /* MRV_SRSZ_SCALE_HCR */ +/*****************************************************************************/ +/** + * register: srsz_scale_vy: vertical luminance scale factor register (0x00000010) + * + *****************************************************************************/ +/* Slice: scale_vy:*/ +/* This register is set to the vertical luminance downscale factor or to the */ +/* reciprocal of the vertical luminance upscale factor */ +#ifdef MRV_SRSZ_SCALE_VY +#endif /* MRV_SRSZ_SCALE_VY */ +/*****************************************************************************/ +/** + * register: srsz_scale_vc: vertical chrominance scale factor register (0x00000014) + * + *****************************************************************************/ +/* Slice: scale_vc:*/ +/* This register is set to the vertical chrominance downscale factor or to the */ +/* reciprocal of the vertical chrominance upscale factor */ +#ifdef MRV_SRSZ_SCALE_VC +#endif /* MRV_SRSZ_SCALE_VC */ +/*****************************************************************************/ +/** + * register: srsz_phase_hy: horizontal luminance phase register (0x00000018) + * + *****************************************************************************/ +/* Slice: phase_hy:*/ +/* This register is set to the horizontal luminance phase offset */ +#ifdef MRV_SRSZ_PHASE_HY +#endif /* MRV_SRSZ_PHASE_HY */ +/*****************************************************************************/ +/** + * register: srsz_phase_hc: horizontal chrominance phase register (0x0000001c) + * + *****************************************************************************/ +/* Slice: phase_hc:*/ +/* This register is set to the horizontal chrominance phase offset */ +#ifdef MRV_SRSZ_PHASE_HC +#endif /* MRV_SRSZ_PHASE_HC */ +/*****************************************************************************/ +/** + * register: srsz_phase_vy: vertical luminance phase register (0x00000020) + * + *****************************************************************************/ +/* Slice: phase_vy:*/ +/* This register is set to the vertical luminance phase offset */ +#ifdef MRV_SRSZ_PHASE_VY +#endif /* MRV_SRSZ_PHASE_VY */ +/*****************************************************************************/ +/** + * register: srsz_phase_vc: vertical chrominance phase register (0x00000024) + * + *****************************************************************************/ +/* Slice: phase_vc:*/ +/* This register is set to the vertical chrominance phase offset */ +#ifdef MRV_SRSZ_PHASE_VC +#endif /* MRV_SRSZ_PHASE_VC */ +/*****************************************************************************/ +/** + * register: srsz_scale_lut_addr: Address pointer of up-scaling look up table + * (0x00000028) + * + *****************************************************************************/ +/* Slice: scale_lut_addr:*/ +/* Pointer to entry of lookup table */ +#ifdef MRV_SRSZ_SCALE_LUT_ADDR +#endif /* MRV_SRSZ_SCALE_LUT_ADDR */ +/*****************************************************************************/ +/** + * register: srsz_scale_lut: Entry of up-scaling look up table (0x0000002c) + * + *****************************************************************************/ +/* Slice: scale_lut:*/ +/* Entry of lookup table at position scale_lut_addr. The lookup table must be */ +/* filled with appropriate values before the up-scaling functionality can be */ +/* used.*/ +#ifdef MRV_SRSZ_SCALE_LUT +#endif /* MRV_SRSZ_SCALE_LUT */ +/*****************************************************************************/ +/** + * register: srsz_ctrl_shd: global control shadow register (0x0030) + * + *****************************************************************************/ +/* Slice: scale_vc_up_shd:*/ +/* 1: vertical chrominance upscaling selected */ +/* 0: vertical chrominance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_VC_UP_SHD +#define MRV_SRSZ_SCALE_VC_UP_SHD_UPSCALE 1 /* 1: vertical chrominance upscaling selected */ +#define MRV_SRSZ_SCALE_VC_UP_SHD_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_VC_UP_SHD */ +/* Slice: scale_vy_up_shd:*/ +/* 1: vertical luminance upscaling selected */ +/* 0: vertical luminance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_VY_UP_SHD +#define MRV_SRSZ_SCALE_VY_UP_SHD_UPSCALE 1 /* 1: vertical luminance upscaling selected */ +#define MRV_SRSZ_SCALE_VY_UP_SHD_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_VY_UP_SHD */ +/* Slice: scale_hc_up_shd:*/ +/* 1: horizontal chrominance upscaling selected */ +/* 0: horizontal chrominance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_HC_UP_SHD +#define MRV_SRSZ_SCALE_HC_UP_SHD_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */ +#define MRV_SRSZ_SCALE_HC_UP_SHD_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_HC_UP_SHD */ +/* Slice: scale_hy_up_shd:*/ +/* 1: horizontal luminance upscaling selected */ +/* 0: horizontal luminance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_HY_UP_SHD +#define MRV_SRSZ_SCALE_HY_UP_SHD_UPSCALE 1 /* 1: horizontal luminance upscaling selected */ +#define MRV_SRSZ_SCALE_HY_UP_SHD_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_HY_UP_SHD */ +/* Slice: scale_vc_enable_shd:*/ +/* 0: bypass vertical chrominance scaling unit */ +/* 1: enable vertical chrominance scaling unit */ +#ifdef MRV_SRSZ_SCALE_VC_ENABLE_SHD +#define MRV_SRSZ_SCALE_VC_ENABLE_SHD_PROCESS 1 /* 1: enable vertical chrominance scaling unit */ +#define MRV_SRSZ_SCALE_VC_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */ +#endif /* MRV_SRSZ_SCALE_VC_ENABLE_SHD */ +/* Slice: scale_vy_enable_shd:*/ +/* 0: bypass vertical luminance scaling unit */ +/* 1: enable vertical luminance scaling unit */ +#ifdef MRV_SRSZ_SCALE_VY_ENABLE_SHD +#define MRV_SRSZ_SCALE_VY_ENABLE_SHD_PROCESS 1 /* 1: enable vertical luminance scaling unit */ +#define MRV_SRSZ_SCALE_VY_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical luminance scaling unit */ +#endif /* MRV_SRSZ_SCALE_VY_ENABLE_SHD */ +/* Slice: scale_hc_enable_shd:*/ +/* 0: bypass horizontal chrominance scaling unit */ +/* 1: enable horizontal chrominance scaling unit */ +#ifdef MRV_SRSZ_SCALE_HC_ENABLE_SHD +#define MRV_SRSZ_SCALE_HC_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */ +#define MRV_SRSZ_SCALE_HC_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */ +#endif /* MRV_SRSZ_SCALE_HC_ENABLE_SHD */ +/* Slice: scale_hy_enable_shd:*/ +/* 0: bypass horizontal luminance scaling unit */ +/* 1: enable horizontal luminance scaling unit */ +#ifdef MRV_SRSZ_SCALE_HY_ENABLE_SHD +#define MRV_SRSZ_SCALE_HY_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal luminance scaling unit */ +#define MRV_SRSZ_SCALE_HY_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */ +#endif /* MRV_SRSZ_SCALE_HY_ENABLE_SHD */ +/*****************************************************************************/ +/** + * register: srsz_scale_hy_shd: horizontal luminance scale factor shadow + * register (0x00000034) + * + *****************************************************************************/ +/* Slice: scale_hy_shd:*/ +/* This register is set to the horizontal luminance downscale factor or to the */ +/* reciprocal of the horizontal luminance upscale factor */ +#ifdef MRV_SRSZ_SCALE_HY_SHD +#endif /* MRV_SRSZ_SCALE_HY_SHD */ +/*****************************************************************************/ +/** + * register: srsz_scale_hcb_shd: horizontal Cb scale factor shadow register + * (0x00000038) + * + *****************************************************************************/ +/* Slice: scale_hcb_shd:*/ +/* This register is set to the horizontal Cb downscale factor or to the */ +/* reciprocal of the horizontal Cb upscale factor */ +#ifdef MRV_SRSZ_SCALE_HCB_SHD +#endif /* MRV_SRSZ_SCALE_HCB_SHD */ +/*****************************************************************************/ +/** + * register: srsz_scale_hcr_shd: horizontal Cr scale factor shadow register + * (0x0000003c) + * + *****************************************************************************/ +/* Slice: scale_hcr_shd:*/ +/* This register is set to the horizontal Cr downscale factor or to the */ +/* reciprocal of the horizontal Cr upscale factor */ +#ifdef MRV_SRSZ_SCALE_HCR_SHD +#endif /* MRV_SRSZ_SCALE_HCR_SHD */ +/*****************************************************************************/ +/** + * register: srsz_scale_vy_shd: vertical luminance scale factor shadow register + * (0x00000040) + * + *****************************************************************************/ +/* Slice: scale_vy_shd:*/ +/* This register is set to the vertical luminance downscale factor or to the */ +/* reciprocal of the vertical luminance upscale factor */ +#ifdef MRV_SRSZ_SCALE_VY_SHD +#endif /* MRV_SRSZ_SCALE_VY_SHD */ +/*****************************************************************************/ +/** + * register: srsz_scale_vc_shd: vertical chrominance scale factor shadow + * register (0x00000044) + * + *****************************************************************************/ +/* Slice: scale_vc_shd:*/ +/* This register is set to the vertical chrominance downscale factor or to */ +/* the reciprocal of the vertical chrominance upscale factor */ +#ifdef MRV_SRSZ_SCALE_VC_SHD +#endif /* MRV_SRSZ_SCALE_VC_SHD */ +/*****************************************************************************/ +/** + * register: srsz_phase_hy_shd: horizontal luminance phase shadow register + * (0x00000048) + * + *****************************************************************************/ +/* Slice: phase_hy_shd:*/ +/* This register is set to the horizontal luminance phase offset */ +#ifdef MRV_SRSZ_PHASE_HY_SHD +#endif /* MRV_SRSZ_PHASE_HY_SHD */ +/*****************************************************************************/ +/** + * register: srsz_phase_hc_shd: horizontal chrominance phase shadow register + * (0x0000004c) + * + *****************************************************************************/ +/* Slice: phase_hc_shd:*/ +/* This register is set to the horizontal chrominance phase offset */ +#ifdef MRV_SRSZ_PHASE_HC_SHD +#endif /* MRV_SRSZ_PHASE_HC_SHD */ +/*****************************************************************************/ +/** + * register: srsz_phase_vy_shd: vertical luminance phase shadow register + * (0x00000050) + * + *****************************************************************************/ +/* Slice: phase_vy_shd:*/ +/* This register is set to the vertical luminance phase offset */ +#ifdef MRV_SRSZ_PHASE_VY_SHD +#endif /* MRV_SRSZ_PHASE_VY_SHD */ +/*****************************************************************************/ +/** + * register: srsz_phase_vc_shd: vertical chrominance phase shadow register + * (0x00000054) + * + *****************************************************************************/ +/* Slice: phase_vc_shd:*/ +/* This register is set to the vertical chrominance phase offset */ +#ifdef MRV_SRSZ_PHASE_VC_SHD +#endif /* MRV_SRSZ_PHASE_VC_SHD */ +/*****************************************************************************/ +/* Memory Interface Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: mi_ctrl: Global control register (0x0000) + * + *****************************************************************************/ +/* Slice: sp_output_format:*/ +/* Selects output format of self picture. For possible restrictions see sub-*/ +/* chapter "Picture Orientation" in chapter "Self Path Output Programming".*/ + /**/ +/* 111: reserved */ +/* 110: RGB 888 */ +/* 101: RGB 666 */ +/* 100: RGB 565 */ + /**/ +/* 011: YCbCr 4:4:4 */ +/* 010: YCbCr 4:2:2 */ +/* 001: YCbCr 4:2:0 */ +/* 000: YCbCr 4:0:0 */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +/* - for RGB output format the SP input format must be YCbCr 4:2:2 */ +#ifdef MRV_MI_SP_OUTPUT_FORMAT +#define MRV_MI_SP_OUTPUT_FORMAT_RGB888 6 /* 110: RGB 888 */ +#define MRV_MI_SP_OUTPUT_FORMAT_RGB666 5 /* 101: RGB 666 */ +#define MRV_MI_SP_OUTPUT_FORMAT_RGB565 4 /* 100: RGB 565 */ +#define MRV_MI_SP_OUTPUT_FORMAT_YUV444 3 /* 011: YCbCr 4:4:4 */ +#define MRV_MI_SP_OUTPUT_FORMAT_YUV422 2 /* 010: YCbCr 4:2:2 */ +#define MRV_MI_SP_OUTPUT_FORMAT_YUV420 1 /* 001: YCbCr 4:2:0 */ +#define MRV_MI_SP_OUTPUT_FORMAT_YUV400 0 /* 000: YCbCr 4:0:0 */ +#endif /* MRV_MI_SP_OUTPUT_FORMAT */ +/* Slice: sp_input_format:*/ +/* Selects input format of self picture. For possible restrictions see sub-*/ +/* chapter "Picture Orientation" in chapter "Self Path Output Programming".*/ + /**/ +/* 11: YCbCr 4:4:4 */ +/* 10: YCbCr 4:2:2 */ +/* 01: YCbCr 4:2:0 */ +/* 00: YCbCr 4:0:0 */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_INPUT_FORMAT +#define MRV_MI_SP_INPUT_FORMAT_YUV444 3 /* 11: YCbCr 4:4:4 */ +#define MRV_MI_SP_INPUT_FORMAT_YUV422 2 /* 10: YCbCr 4:2:2 */ +#define MRV_MI_SP_INPUT_FORMAT_YUV420 1 /* 01: YCbCr 4:2:0 */ +#define MRV_MI_SP_INPUT_FORMAT_YUV400 0 /* 00: YCbCr 4:0:0 */ +#endif /* MRV_MI_SP_INPUT_FORMAT */ +/* Slice: sp_write_format:*/ +/* Defines how YCbCr self picture data is written to memory. Ignored if */ +/* RGB conversion is chosen. With RGB conversion active the output format */ +/* is always interleaved.*/ + /**/ +/* 00: planar */ +/* 01: semi planar, for YCbCr 4:2:x */ +/* 10: interleaved (combined), for YCbCr 4:2:2 only */ +/* 11: reserved */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_WRITE_FORMAT +#define MRV_MI_SP_WRITE_FORMAT_PLANAR 0 /* 00: planar */ +#define MRV_MI_SP_WRITE_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */ +#define MRV_MI_SP_WRITE_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */ +#define MRV_MI_SP_WRITE_FORMAT_RGB_INTERLEAVED 0 /* 00: hw expects a 0 in RGB mode */ +#endif /* MRV_MI_SP_WRITE_FORMAT */ +/* Slice: mp_write_format:*/ +/* Defines how YCbCr main picture data is written to memory.*/ +/* Ignored if JPEG data is chosen.*/ +/* In YCbCr mode the following meaning is applicable */ +/* 00: planar */ +/* 01: semi planar, for YCbCr 4:2:x */ +/* 10: interleaved (combined), for YCbCr 4:2:2 only */ +/* 11: reserved */ +/* In RAW data mode the following meaning is applicable */ +/* 00: RAW 8 bit */ +/* 01: reserved */ +/* 10: RAW 12 bit */ +/* 11: reserved */ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the main path.*/ +#ifdef MRV_MI_MP_WRITE_FORMAT +#define MRV_MI_MP_WRITE_FORMAT_PLANAR 0 /* 00: planar */ +#define MRV_MI_MP_WRITE_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */ +#define MRV_MI_MP_WRITE_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */ +#define MRV_MI_MP_WRITE_FORMAT_RAW_8 0 /* 0x: RAW 8 bit */ +#define MRV_MI_MP_WRITE_FORMAT_RAW_12 2 /* 1x: RAW 12 bit */ +#endif /* MRV_MI_MP_WRITE_FORMAT */ +/* Slice: bp_write_format:*/ +/* In RAW data mode the following meaning is applicable */ +/* 00: RAW 8 bit */ +/* 01: RAW 10 bit */ +/* 10: RAW 12 bit */ +/* 11: reserved */ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the main path.*/ +#ifdef MRV_MI_BP_WRITE_RAWBIT +#define MRV_MI_BP_WRITE_RAWBIT_RAW_8 0 /* 0x: RAW 8 bit */ +#define MRV_MI_BP_WRITE_RAWBIT_RAW_10 1 /* 01x: RAW 10 bit */ +#define MRV_MI_BP_WRITE_RAWBIT_RAW_12 2 /* 10x: RAW 12 bit */ +#endif /* MRV_MI_BP_WRITE_RAWBIT */ +/* Slice: init_offset_en:*/ +/* Enables updating of the offset counters shadow registers for */ +/* main and self picture to the programmed register init values.*/ + /**/ +/* MI_MP/SP_Y/CB/CR_OFFS_CNT_INIT */ +/* -> MI_MP/SP_Y/CB/CR_OFFS_CNT_SHD */ + /**/ +/* The update will be executed either when a forced software */ +/* update occurs (in register MI_INIT bit cfg_upd = 1) or when */ +/* an automatic config update signal arrives at the MI input port.*/ +/* The latter is split into main and self picture. So only the */ +/* corresponding main/self shadow registers are affected.*/ +/* After a picture skip has been performed init_offset_en selects */ +/* between skip restart and skip init mode (see bit skip in */ +/* register MI_INIT).*/ +#ifdef MRV_MI_INIT_OFFSET_EN +#endif /* MRV_MI_INIT_OFFSET_EN */ +/* Slice: init_base_en:*/ +/* Enables updating of the base address and buffer size shadow */ +/* registers for main and self picture to the programmed register */ +/* init values.*/ + /**/ +/* MI_MP/SP_Y/CB/CR_BASE_AD_INIT */ +/* -> MI_MP/SP_Y/CB/CR_BASE_AD_SHD */ + /**/ +/* MI_MP/SP_Y/CB/CR_SIZE_INIT */ +/* -> MI_MP/SP_Y/CB/CR_SIZE_SHD */ + /**/ +/* The update will be executed either when a forced software */ +/* update occurs (in register MI_INIT bit cfg_upd = 1) or when */ +/* an automatic config update signal arrives at the MI input port.*/ +/* The latter is split into main and self picture. So only the */ +/* corresponding main/self shadow registers are affected.*/ +#ifdef MRV_MI_INIT_BASE_EN +#endif /* MRV_MI_INIT_BASE_EN */ +/* Slice: burst_len_chrom:*/ +/* Burst length for Cb or Cr data affecting write port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported. If rotation */ +/* is active, then only 4-beat bursts will be generated in self path,*/ +/* regardless of the setting here.*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the main and self path.*/ +#ifdef MRV_MI_BURST_LEN_CHROM +#define MRV_MI_BURST_LEN_CHROM_4 0 /* 0: 4-beat bursts */ +#define MRV_MI_BURST_LEN_CHROM_8 1 /* 1: 8-beat bursts */ +#define MRV_MI_BURST_LEN_CHROM_16 2 /* 2: 16-beat bursts */ +#endif /* MRV_MI_BURST_LEN_CHROM */ +/* Slice: burst_len_lum:*/ +/* Burst length for Y, JPEG, or raw data affecting write port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ + /**/ +/* Note: Programmed value becomes effective immediately. So write to */ +/* the register only if no picture data is sent to the main and self path.*/ +#ifdef MRV_MI_BURST_LEN_LUM +#define MRV_MI_BURST_LEN_LUM_4 0 /* 0: 4-beat bursts */ +#define MRV_MI_BURST_LEN_LUM_8 1 /* 1: 8-beat bursts */ +#define MRV_MI_BURST_LEN_LUM_16 2 /* 2: 16-beat bursts */ +#endif /* MRV_MI_BURST_LEN_LUM */ +/* Slice: last_pixel_sig_en:*/ +/* enables the last pixel signalization */ +/* 1: enabled */ +/* 0: disabled */ +#ifdef MRV_MI_LAST_PIXEL_SIG_EN +#define MRV_MI_LAST_PIXEL_SIG_EN_ENABLE 1 /* 1: enable last pixel signalization */ +#define MRV_MI_LAST_PIXEL_SIG_EN_DISABLE 0 /* 0: disable last pixel signalization */ +#endif /* MRV_MI_LAST_PIXEL_SIG_EN */ +/* Slice: 422noncosited:*/ +/* Enables self path YCbCr422non-co-sited -> YCbCr444 interpolation */ +/* 1: YCbCr422 data are non_co-sited (Cb and Cr samples */ +/* are centered between Y samples) so modified interpolation */ +/* is activated */ +/* 0: YCbCr422 data are co-sited (Y0 Cb0 and Cr0 are */ +/* sampled at the same position)*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_422NONCOSITED +#endif /* MRV_MI_422NONCOSITED */ +/* Slice: cbcr_full_range:*/ +/* Enables CbCr full range for self path YCbCr -> RGB conversion */ +/* 1: CbCr have full range (0..255)*/ +/* 0: CbCr have compressed range range (16..240)*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_CBCR_FULL_RANGE +#endif /* MRV_MI_CBCR_FULL_RANGE */ +/* Slice: y_full_range:*/ +/* Enables Y full range for self path YCbCr -> RGB conversion */ +/* 1: Y has full range (0..255)*/ +/* 0: Y has compressed range (16..235)*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_Y_FULL_RANGE +#endif /* MRV_MI_Y_FULL_RANGE */ +/* Slice: byte_swap:*/ +/* Enables change of byte order of the 32 bit output word at write port */ +/* 1: byte order is mirrored but the bit order within one byte doesn't */ +/* change */ +/* 0: no byte mirroring */ + /**/ +/* Note: Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the main and self path.*/ +#ifdef MRV_MI_BYTE_SWAP +#endif /* MRV_MI_BYTE_SWAP */ +/* Slice: rot:*/ +/* Rotation 90 degree counter clockwise of self picture, only in RGB */ +/* mode. For picture orientation and operation modes see sub-chapter */ +/* "Picture Orientation" in chapter "Self Path Output Programming".*/ + /**/ +/* For RGB 565 format the line length must be a multiple of 2. There */ +/* are no restrictions for RGB 888/666.*/ +/* 1: enabled */ +/* 0: disabled */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path. In */ +/* rotation mode only 4-beat bursts are supported for self-path.*/ +#ifdef MRV_MI_ROT +#endif /* MRV_MI_ROT */ +/* Slice: v_flip:*/ +/* Vertical flipping of self picture. For picture orientation and */ +/* operation modes see sub-chapter "Picture Orientation" in chapter */ +/* "Self Path Output Programming". For Y component the line length */ +/* in 4:2:x planar mode must be a multiple of 8, for all other component */ +/* modes a multiple of 4 and for RGB 565 a multiple of 2. There are */ +/* no restrictions for RGB 888/666.*/ + /**/ +/* 1: enabled */ +/* 0: disabled */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_V_FLIP +#endif /* MRV_MI_V_FLIP */ +/* Slice: h_flip:*/ +/* Horizontal flipping of self picture. For picture orientation and */ +/* operation modes see sub-chapter "Picture Orientation" in chapter */ +/* "Self Path Output Programming".*/ + /**/ +/* For Y component the line length in 4:2:x planar mode must be a */ +/* multiple of 8, for all other component modes a multiple of 4 and */ +/* for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/ + /**/ +/* 1: enabled */ +/* 0: disabled */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_H_FLIP +#endif /* MRV_MI_H_FLIP */ +/* Programmed value becomes effective (visible in shadow register)*/ +/* after a soft reset, a forced software update or an automatic */ +/* config update. Affects MI_IN and MI_OUT module.*/ +/* Slice: raw_enable:*/ +/* Enables raw data */ +/* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software update.*/ +/* Affects MI_IN and MI_OUT module.*/ +#ifndef MRV_MI_RAW_ENABLE +#define MRV_MI_RAW_ENABLE +#define MRV_MI_RAW_ENABLE_MASK 0x00000008 +#define MRV_MI_RAW_ENABLE_SHIFT 3 +#endif /* MRV_MI_RAW_ENABLE */ +/* Slice: dpcc_enable:*/ +/* Enables DPCC data */ +/* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software.*/ +/* Affects MI_IN and MI_OUT module.*/ +#ifndef MRV_MI_DPCC_ENABLE +#define MRV_MI_DPCC_ENABLE +#define MRV_MI_DPCC_ENABLE_MASK 0x0000000C +#define MRV_MI_DPCC_ENABLE_SHIFT 2 +#endif /* MRV_MI_JPEG_ENABLE */ +/* Slice: jpeg_enable:*/ +/* Enables JPEG data */ +/* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software.*/ +/* Affects MI_IN and MI_OUT module.*/ +#ifndef MRV_MI_JPEG_ENABLE +#define MRV_MI_JPEG_ENABLE +#define MRV_MI_JPEG_ENABLE_MASK 0x00000004 +#define MRV_MI_JPEG_ENABLE_SHIFT 2 +#endif /* MRV_MI_JPEG_ENABLE */ +/* Slice: sp_enable:*/ +/* Enables self picture data path.*/ +/* Programmed value becomes effective (visible in control shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Affects MI_IN and MI_OUT module.*/ +#ifndef MRV_MI_SP_ENABLE +#define MRV_MI_SP_ENABLE +#define MRV_MI_SP_ENABLE_MASK 0x00000002 +#define MRV_MI_SP_ENABLE_SHIFT 1 +#endif /* MRV_MI_SP_ENABLE */ +/* Slice: mp_enable:*/ +/* Enables main picture data path */ +/* Programmed value becomes effective (visible in control shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Affects MI_IN and MI_OUT module.*/ +#ifndef MRV_MI_MP_ENABLE +#define MRV_MI_MP_ENABLE +#define MRV_MI_MP_ENABLE_MASK 0x00000001 +#define MRV_MI_MP_ENABLE_SHIFT 0 +#endif /* MRV_MI_MP_ENABLE */ +/* Slice: path_enable:*/ +/* Enables data pathes of MI according to the following table:*/ + /**/ +/* 0000: disabled, no data is transferred */ +/* 0001: YUV data output, mainpath only (mp_enable only)*/ +/* 0010: self-path only, output data format depending on other settings (sp_enable only)*/ +/* 0011: YUV data output in mainpath and self-path image data active */ +/* 0100: JPEG data output, mainpath only (jpeg_enable only)*/ +/* 0101: not allowed */ +/* 0110: JPEG data output in mainpath and self-path image data active */ +/* 0111: not allowed */ +/* 1000: RAW data output, mainpath only (raw_enable only)*/ +/* 1001: defect pixel data on self-path, image data on mainpath */ +/* 1010: defect pixel data on mainpath, image data on self-path */ +/* 1011: not allowed */ +/* 1100: defect pixel data on self-path, JPEG data on mainpath */ +/* 1101: defect pixel data on mainpath only */ +/* 1110: defect pixel data on self-path only */ +/* 1111: defect pixel data on self-path, RAW data on mainpath */ +#ifdef MRV_MI_PATH_ENABLE +#endif /* MRV_MI_PATH_ENABLE */ +/*****************************************************************************/ +/** + * register: mi_init: Control register for address init and skip function + * (0x00000004) + * + *****************************************************************************/ +/* Slice: mi_cfg_upd:*/ +/* Forced configuration update. Leads to an immediate update of the shadow registers.*/ +/* Depending on the two init enable bits in the MI_CTRL register (init_offset_en and */ +/* init_base_en) the offset counter, base address and buffer size shadow registers */ +/* are also updated.*/ +#ifdef MRV_MI_MI_CFG_UPD +#endif /* MRV_MI_MI_CFG_UPD */ +/* Slice: mp_output_format:*/ +/* Selects output format of main picture.*/ +/* 1xxx: Reserved */ +/* 0111: RAW10 */ +/* 0110: JPEG */ +/* 0101: RAW8 */ +/* 0100: RAW12 */ + /**/ +/* 0011: YCbCr 4:4:4 */ +/* 0010: YCbCr 4:2:2 */ +/* 0001: YCbCr 4:2:0 */ +/* 0000: YCbCr 4:0:0 */ + /**/ +#ifdef MRV_MI_MP_OUTPUT_FORMAT +#define MRV_MI_MP_OUTPUT_FORMAT_RAW10 7 /* 0111: RAW10 */ +#define MRV_MI_MP_OUTPUT_FORMAT_JPEG 6 /* 0110: JPEG */ +#define MRV_MI_MP_OUTPUT_FORMAT_RAW8 5 /* 0101: RAW8 */ +#define MRV_MI_MP_OUTPUT_FORMAT_RAW12 4 /* 0100: RAW12 */ +#define MRV_MI_MP_OUTPUT_FORMAT_YUV444 3 /* 0011: YCbCr 4:4:4 */ +#define MRV_MI_MP_OUTPUT_FORMAT_YUV422 2 /* 0010: YCbCr 4:2:2 */ +#define MRV_MI_MP_OUTPUT_FORMAT_YUV420 1 /* 0001: YCbCr 4:2:0 */ +#define MRV_MI_MP_OUTPUT_FORMAT_YUV400 0 /* 0000: YCbCr 4:0:0 */ +#endif /* MRV_MI_MP_OUTPUT_FORMAT */ +/* Slice: mi_skip:*/ +/* Skip of current or next starting main picture:*/ +/* Aborts writing of main picture image data of the current frame to RAM (after the */ +/* current burst transmission has been completed). Further main picture data up to */ +/* the end of the current frame are discarded.*/ + /**/ +/* No further makroblock line interrupt (mblk_line), no wrap around interrupt for */ +/* main picture (wrap_mp_y/cb/cr) and no fill level interrupt (fill_mp_y) are generated.*/ + /**/ +/* Skip does not affect the generation of the main path frame end interrupt (mp_frame_end).*/ +/* Skip does not affect the processing of self picture and its corresponding interrupts */ +/* namely the self path frame end interrupt (sp_frame_end).*/ + /**/ +/* The byte counter (register MI_BYTE_CNT) is not affected. It produces the correct */ +/* number of JPEG or RAW data bytes at the end of the current (skipped) frame.*/ + /**/ +/* After a skip has been performed the offset counter for the main picture at the start */ +/* of the following frame are set depending on the bit init_offset_en in register MI_CTRL:*/ + /**/ +/* - Skip restart mode (init_offset_en = 0)*/ +/* The offset counters of the main picture are restarted at the old start values of */ +/* the previous skipped frame.*/ + /**/ +/* - Skip init mode (init_offset_en = 1)*/ +/* The offset counters of the main picture are initialized with the register contents */ +/* of the offset counter init registers without any additional forced software update */ +/* or automatic config update.*/ +#ifdef MRV_MI_MI_SKIP +#endif /* MRV_MI_MI_SKIP */ +/*****************************************************************************/ +/** + * register: mi_mp_y_base_ad_init: Base address for main picture Y component, + * JPEG or raw data (0x00000008) + * + *****************************************************************************/ +/* Slice: mp_y_base_ad_init:*/ +/* Base address of main picture Y component ring buffer, JPEG ring buffer or raw */ +/* data ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_BASE_AD_INIT +#define MRV_MI_MP_Y_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_Y_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_y_size_init: Size of main picture Y component, JPEG or raw + * data (0x0000000c) + * + *****************************************************************************/ +/* Slice: mp_y_size_init:*/ +/* Size of main picture Y component ring buffer, JPEG ring buffer or raw data */ +/* ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_SIZE_INIT +#define MRV_MI_MP_Y_SIZE_INIT_VALID_MASK (MRV_MI_MP_Y_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_y_offs_cnt_init: Offset counter init value for main picture + * Y, JPEG or raw data (0x00000010) + * + *****************************************************************************/ +/* Slice: mp_y_offs_cnt_init:*/ +/* Offset counter init value of main picture Y component ring buffer, JPEG ring */ +/* buffer or raw data ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_OFFS_CNT_INIT +#define MRV_MI_MP_Y_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_y_offs_cnt_start: Offset counter start value for main picture + * Y, JPEG or raw data (0x00000014) + * + *****************************************************************************/ +/* Slice: mp_y_offs_cnt_start:*/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (main picture Y component, JPEG or raw data). Updated at */ +/* frame end.*/ + /**/ +/* Note: A soft reset resets the contents to the reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_OFFS_CNT_START +#define MRV_MI_MP_Y_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_mp_y_irq_offs_init: Fill level interrupt offset value for main + * picture Y, JPEG or raw data (0x00000018) + * + *****************************************************************************/ +/* Slice: mp_y_irq_offs_init:*/ +/* Reaching this programmed value by the current offset counter for addressing */ +/* main picture Y component, JPEG or raw data leads to generation of fill level */ +/* interrupt fill_mp_y.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_IRQ_OFFS_INIT +#define MRV_MI_MP_Y_IRQ_OFFS_INIT_VALID_MASK (MRV_MI_MP_Y_IRQ_OFFS_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_IRQ_OFFS_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_base_ad_init: Base address for main picture Cb component + * ring buffer (0x0000001c) + * + *****************************************************************************/ +/* Slice: mp_cb_base_ad_init:*/ +/* Base address of main picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or */ +/* automatic update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_BASE_AD_INIT +#define MRV_MI_MP_CB_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_CB_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CB_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_size_init: Size of main picture Cb component ring buffer + * (0x00000020) + * + *****************************************************************************/ +/* Slice: mp_cb_size_init:*/ +/* Size of main picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or */ +/* automatic update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_SIZE_INIT +#define MRV_MI_MP_CB_SIZE_INIT_VALID_MASK (MRV_MI_MP_CB_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CB_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_offs_cnt_init: Offset counter init value for main picture + * Cb component ring buffer (0x00000024) + * + *****************************************************************************/ +/* Slice: mp_cb_offs_cnt_init:*/ +/* Offset counter init value of main picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect. Check exceptional handling in skip modes.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_OFFS_CNT_INIT +#define MRV_MI_MP_CB_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_CB_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CB_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_offs_cnt_start: Offset counter start value for main + * picture Cb component ring buffer (0x00000028) + * + *****************************************************************************/ +/* Slice: mp_cb_offs_cnt_start:*/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (main picture Cb component). Updated at frame end.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_OFFS_CNT_START +#define MRV_MI_MP_CB_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_CB_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CB_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_base_ad_init: Base address for main picture Cr component + * ring buffer (0x0000002c) + * + *****************************************************************************/ +/* Slice: mp_cr_base_ad_init:*/ +/* Base address of main picture Cr component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_BASE_AD_INIT +#define MRV_MI_MP_CR_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_CR_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CR_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_size_init: Size of main picture Cr component ring buffer + * (0x00000030) + * + *****************************************************************************/ +/* Slice: mp_cr_size_init:*/ +/* Size of main picture Cr component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_SIZE_INIT +#define MRV_MI_MP_CR_SIZE_INIT_VALID_MASK (MRV_MI_MP_CR_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CR_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_offs_cnt_init: Offset counter init value for main + * picture Cr component ring buffer (0x00000034) + * + *****************************************************************************/ +/* Slice: mp_cr_offs_cnt_init:*/ +/* Offset counter init value of main picture Cr component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect. Check exceptional handling in skip modes.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_OFFS_CNT_INIT +#define MRV_MI_MP_CR_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_CR_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CR_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_offs_cnt_start: Offset counter start value for main + * picture Cr component ring buffer (0x00000038) + * + *****************************************************************************/ +/* Slice: mp_cr_offs_cnt_start:*/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (main picture Cr component). Updated at frame end.*/ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_OFFS_CNT_START +#define MRV_MI_MP_CR_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_CR_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CR_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_sp_y_base_ad_init: Base address for self picture Y component + * ring buffer (0x0000003c) + * + *****************************************************************************/ +/* Slice: sp_y_base_ad_init:*/ +/* Base address of self picture Y component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_BASE_AD_INIT +#define MRV_MI_SP_Y_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_Y_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_Y_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_y_size_init: Size of self picture Y component ring buffer + * (0x00000040) + * + *****************************************************************************/ +/* Slice: sp_y_size_init:*/ +/* Size of self picture Y component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or */ +/* automatic update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_SIZE_INIT +#define MRV_MI_SP_Y_SIZE_INIT_VALID_MASK (MRV_MI_SP_Y_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_Y_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_y_offs_cnt_init: Offset counter init value for self + * picture Y component ring buffer (0x00000044) + * + *****************************************************************************/ +/* Slice: sp_y_offs_cnt_init:*/ +/* Offset counter init value of self picture Y component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or */ +/* automatic update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_OFFS_CNT_INIT +#define MRV_MI_SP_Y_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_Y_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_Y_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_y_offs_cnt_start: Offset counter start value for self + * picture Y component ring buffer (0x00000048) + * + *****************************************************************************/ +/* Slice: sp_y_offs_cnt_start:*/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (self picture Y component). Updated at frame end.*/ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_OFFS_CNT_START +#define MRV_MI_SP_Y_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_Y_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_SP_Y_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_sp_y_llength: Line length of self picture Y component (0x0000004c) + * + *****************************************************************************/ +/* Slice: sp_y_llength:*/ +/* Line length of self picture Y component or RGB picture in pixel, also */ +/* known as line stride.*/ + /**/ +/* If no line stride is used, line length must match image width.*/ + /**/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8,*/ +/* for all other component modes a multiple of 4 and for RGB 565 a multiple of 2.*/ +/* There are no restrictions for RGB 888/666.*/ + /**/ +/* In planar mode the line length of the Cb and Cr component is assumed according */ +/* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi */ +/* planar 4:2:x mode the line length of the Cb and Cr component is assumed the */ +/* same size.*/ + /**/ +/* Note:*/ +/* - Line length always refers to the line length of the output image. This */ +/* is particularly important when rotating.*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the register */ +/* only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_Y_LLENGTH +#define MRV_MI_SP_Y_LLENGTH_VALID_MASK (MRV_MI_SP_Y_LLENGTH_MASK & ~0x00000000) +#endif /* MRV_MI_SP_Y_LLENGTH */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_base_ad_init: Base address for self picture Cb component + * ring buffer (0x00000050) + * + *****************************************************************************/ +/* Slice: sp_cb_base_ad_init:*/ +/* Base address of self picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or */ +/* automatic update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_BASE_AD_INIT +#define MRV_MI_SP_CB_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_CB_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CB_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_size_init: Size of self picture Cb component ring buffer + * (0x00000054) + * + *****************************************************************************/ +/* Slice: sp_cb_size_init:*/ +/* Size of self picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_SIZE_INIT +#define MRV_MI_SP_CB_SIZE_INIT_VALID_MASK (MRV_MI_SP_CB_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CB_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_offs_cnt_init: Offset counter init value for self picture + * Cb component ring buffer (0x00000058) + * + *****************************************************************************/ +/* Slice: sp_cb_offs_cnt_init:*/ +/* Offset counter init value of self picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_OFFS_CNT_INIT +#define MRV_MI_SP_CB_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_CB_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CB_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_offs_cnt_start: Offset counter start value for self + * picture Cb component ring buffer (0x0000005c) + * + *****************************************************************************/ +/* Slice: sp_cb_offs_cnt_start:*/ + /**/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (self picture Cb component). Updated at frame end.*/ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_OFFS_CNT_START +#define MRV_MI_SP_CB_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_CB_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CB_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_base_ad_init: Base address for self picture Cr component + * ring buffer (0x00000060) + * + *****************************************************************************/ +/* Slice: sp_cr_base_ad_init:*/ +/* Base address of self picture Cr component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_BASE_AD_INIT +#define MRV_MI_SP_CR_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_CR_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CR_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_size_init: Size of self picture Cr component ring buffer + * (0x00000064) + * + *****************************************************************************/ +/* Slice: sp_cr_size_init:*/ +/* Size of self picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_SIZE_INIT +#define MRV_MI_SP_CR_SIZE_INIT_VALID_MASK (MRV_MI_SP_CR_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CR_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_offs_cnt_init: Offset counter init value for self + * picture Cr component ring buffer (0x00000068) + * + *****************************************************************************/ +/* Slice: sp_cr_offs_cnt_init:*/ +/* Offset counter init value of self picture Cr component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_OFFS_CNT_INIT +#define MRV_MI_SP_CR_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_CR_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CR_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_offs_cnt_start: Offset counter start value for self + * picture Cr component ring buffer (0x0000006c) + * + *****************************************************************************/ +/* Slice: sp_cr_offs_cnt_start:*/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (self picture Cr component). Updated at frame end.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_OFFS_CNT_START +#define MRV_MI_SP_CR_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_CR_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CR_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_byte_cnt: Counter value of JPEG or RAW data bytes (0x00000070) + * + *****************************************************************************/ +/* Slice: byte_cnt:*/ +/* Counter value specifies the number of JPEG or RAW data bytes of the last */ +/* transmitted frame. Updated at frame end.*/ + /**/ +/* A soft reset will set the byte counter to zero.*/ +#ifdef MRV_MI_BYTE_CNT +#endif /* MRV_MI_BYTE_CNT */ +/*****************************************************************************/ +/** + * register: mi_ctrl_shd: global control internal shadow register (0x00000074) + * + *****************************************************************************/ +/* Slice: path_enable_out:*/ +/* path_enable shadow register for module MI_OUT (former raw_enable_out,*/ +/* jpeg_enable_out, sp_enable_out, mp_enable_out)*/ +#ifdef MRV_MI_PATH_ENABLE_OUT +#endif /* MRV_MI_PATH_ENABLE_OUT */ +/* Slice: path_enable_in:*/ +/* path_enable shadow register for module MI_IN (former raw_enable_in,*/ +/* jpeg_enable_in, sp_enable_in, mp_enable_in)*/ +#ifdef MRV_MI_PATH_ENABLE_IN +#endif /* MRV_MI_PATH_ENABLE_IN */ +/*****************************************************************************/ +/** + * register: mi_mp_y_base_ad_shd: Base address shadow register for main + * picture Y component, JPEG or raw data ring buffer (0x00000078) + * + *****************************************************************************/ +/* Slice: mp_y_base_ad:*/ +/* Base address of main picture Y component ring buffer, JPEG ring buffer or */ +/* raw data ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_BASE_AD +#define MRV_MI_MP_Y_BASE_AD_VALID_MASK (MRV_MI_MP_Y_BASE_AD_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_mp_y_size_shd: Size shadow register of main picture Y component, + * JPEG or raw data (0x0000007c) + * + *****************************************************************************/ +/* Slice: mp_y_size:*/ +/* Size of main picture Y component ring buffer, JPEG ring buffer or raw data */ +/* ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_SIZE +#define MRV_MI_MP_Y_SIZE_VALID_MASK (MRV_MI_MP_Y_SIZE_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_SIZE */ +/*****************************************************************************/ +/** + * register: mi_mp_y_offs_cnt_shd: Current offset counter of main picture Y + * component, JPEG or raw data ring buffer (0x00000080) + * + *****************************************************************************/ +/* Slice: mp_y_offs_cnt:*/ +/* Current offset counter of main picture Y component, JPEG or raw data ring */ +/* buffer for address generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_OFFS_CNT +#define MRV_MI_MP_Y_OFFS_CNT_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_mp_y_irq_offs_shd: Shadow register of fill level interrupt + * offset value for main picture Y component, JPEG or raw data + * (0x00000084) + * + *****************************************************************************/ +/* Slice: mp_y_irq_offs:*/ +/* Reaching this offset value by the current offset counter for addressing */ +/* main picture Y component, JPEG or raw data leads to generation of fill */ +/* level interrupt fill_mp_y.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_IRQ_OFFS +#endif /* MRV_MI_MP_Y_IRQ_OFFS */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_base_ad_shd: Base address shadow register for main + * picture Cb component ring buffer (0x00000088) + * + *****************************************************************************/ +/* Slice: mp_cb_base_ad:*/ +/* Base address of main picture Cb component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_BASE_AD +#endif /* MRV_MI_MP_CB_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_size_shd: Size shadow register of main picture Cb + * component ring buffer (0x0000008c) + * + *****************************************************************************/ +/* Slice: mp_cb_size:*/ +/* Size of main picture Cb component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_SIZE +#endif /* MRV_MI_MP_CB_SIZE */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_offs_cnt_shd: Current offset counter of main picture Cb + * component ring buffer (0x00000090) + * + *****************************************************************************/ +/* Slice: mp_cb_offs_cnt:*/ +/* Current offset counter of main picture Cb component ring buffer for address */ +/* generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_OFFS_CNT +#endif /* MRV_MI_MP_CB_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_base_ad_shd: Base address shadow register for main + * picture Cr component ring buffer (0x00000094) + * + *****************************************************************************/ +/* Slice: mp_cr_base_ad:*/ +/* Base address of main picture Cr component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_BASE_AD +#endif /* MRV_MI_MP_CR_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_size_shd: Size shadow register of main picture Cr + * component ring buffer (0x00000098) + * + *****************************************************************************/ +/* Slice: mp_cr_size:*/ +/* Size of main picture Cr component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_SIZE +#endif /* MRV_MI_MP_CR_SIZE */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_offs_cnt_shd: Current offset counter of main picture Cr + * component ring buffer (0x0000009c) + * + *****************************************************************************/ +/* Slice: mp_cr_offs_cnt:*/ +/* Current offset counter of main picture Cr component ring buffer for */ +/* address generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_OFFS_CNT +#endif /* MRV_MI_MP_CR_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_sp_y_base_ad_shd: Base address shadow register for self + * picture Y component ring buffer (0x000000a0) + * + *****************************************************************************/ +/* Slice: sp_y_base_ad:*/ +/* Base address of self picture Y component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_BASE_AD +#endif /* MRV_MI_SP_Y_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_sp_y_size_shd: Size shadow register of self picture Y + * component ring buffer (0x000000a4) + * + *****************************************************************************/ +/* Slice: sp_y_size:*/ +/* Size of self picture Y component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_SIZE +#endif /* MRV_MI_SP_Y_SIZE */ +/*****************************************************************************/ +/** + * register: mi_sp_y_offs_cnt_shd: Current offset counter of self picture Y + * component ring buffer (0x000000a8) + * + *****************************************************************************/ +/* Slice: sp_y_offs_cnt:*/ +/* Current offset counter of self picture Y component ring buffer for address generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_OFFS_CNT +#endif /* MRV_MI_SP_Y_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_base_ad_shd: Base address shadow register for self + * picture Cb component ring buffer (0x000000b0) + * + *****************************************************************************/ +/* Slice: sp_cb_base_ad:*/ +/* Base address of self picture Cb component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_BASE_AD +#endif /* MRV_MI_SP_CB_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_size_shd: Size shadow register of self picture Cb + * component ring buffer (0x000000b4) + * + *****************************************************************************/ +/* Slice: sp_cb_size:*/ +/* Size of self picture Cb component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_SIZE +#endif /* MRV_MI_SP_CB_SIZE */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_offs_cnt_shd: Current offset counter of self picture + * Cb component ring buffer (0x000000b8) + * + *****************************************************************************/ +/* Slice: sp_cb_offs_cnt:*/ +/* Current offset counter of self picture Cb component ring buffer for */ +/* address generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_OFFS_CNT +#endif /* MRV_MI_SP_CB_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_base_ad_shd: Base address shadow register for self + * picture Cr component ring buffer (0x000000bc) + * + *****************************************************************************/ +/* Slice: sp_cr_base_ad:*/ +/* Base address of self picture Cr component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_BASE_AD +#endif /* MRV_MI_SP_CR_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_size_shd: Size shadow register of self picture Cr + * component ring buffer (0x000000c0) + * + *****************************************************************************/ +/* Slice: sp_cr_size:*/ +/* Size of self picture Cr component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_SIZE +#endif /* MRV_MI_SP_CR_SIZE */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_offs_cnt_shd: Current offset counter of self picture Cr + * component ring buffer (0x000000c4) + * + *****************************************************************************/ +/* Slice: sp_cr_offs_cnt:*/ +/* Current offset counter of self picture Cr component ring buffer for */ +/* address generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_OFFS_CNT +#endif /* MRV_MI_SP_CR_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_dma_y_pic_start_ad: Y component image start address (0x000000c8) + * + *****************************************************************************/ +/* Slice: dma_y_pic_start_ad:*/ +/* Image start address of the y component */ + /**/ +/* Note:*/ +/* - Must be multiple of 4 in interleaved mode.*/ +#ifdef MRV_MI_DMA_Y_PIC_START_AD +#endif /* MRV_MI_DMA_Y_PIC_START_AD */ +/*****************************************************************************/ +/** + * register: mi_dma_y_pic_width: Y component image width (0x000000cc) + * + *****************************************************************************/ +/* Slice: dma_y_pic_width:*/ +/* Image width of the Y component in pixel.*/ + /**/ +/* For YCbCr 4:2:x the image width must be a multiple of 2.*/ + /**/ +/* In planar mode the image width of the Cb and Cr component is assumed */ +/* according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/ + /**/ +/* In semi planar 4:2:x mode the image width of the Cb component (which includes Cr)*/ +/* is assumed the same size.*/ + /**/ +/* In interleave mode no Cb/Cr image width is used.*/ +#ifdef MRV_MI_DMA_Y_PIC_WIDTH +#endif /* MRV_MI_DMA_Y_PIC_WIDTH */ +/*****************************************************************************/ +/** + * register: mi_dma_y_llength: Y component original line length (0x000000d0) + * + *****************************************************************************/ +/* Slice: dma_y_llength:*/ +/* Line length of the Y component of the original image in memory */ + /**/ +/* For an uncropped image, where lines follow each other without offset */ +/* (no line stride), line length must match image width.*/ + /**/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8,*/ +/* for all other component modes a multiple of 4.*/ + /**/ +/* In planar mode the line length of the Cb and Cr component is assumed according */ +/* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/ + /**/ +/* In semi planar 4:2:x mode the line length of the Cb component (which includes Cr)*/ +/* is assumed the same size.*/ + /**/ +/* In interleave mode no Cb/Cr line length is used.*/ +#ifdef MRV_MI_DMA_Y_LLENGTH +#endif /* MRV_MI_DMA_Y_LLENGTH */ +/*****************************************************************************/ +/** + * register: mi_dma_y_pic_size: Y component image size (0x000000d4) + * + *****************************************************************************/ +/* Slice: dma_y_pic_size:*/ +/* Image size of the Y component in pixel which has to be the Y line length */ +/* multiplied by the Y image height (dma_y_llength * dma_y_pic_height).*/ + /**/ +/* In planar mode the image size of the Cb and Cr component is assumed according */ +/* to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same */ +/* for 4:4:4.*/ + /**/ +/* In semi planar mode the image size of the Cb component (which includes Cr)*/ +/* is assumed half for 4:2:0 and the same size for 4:2:2.*/ + /**/ +/* In interleave mode no Cb/Cr image size is used.*/ +#ifdef MRV_MI_DMA_Y_PIC_SIZE +#endif /* MRV_MI_DMA_Y_PIC_SIZE */ +/*****************************************************************************/ +/** + * register: mi_dma_cb_pic_start_ad: Cb component image start address (0x000000d8) + * + *****************************************************************************/ +/* Slice: dma_cb_pic_start_ad:*/ +/* Image start address of the Cb component */ + /**/ +/* Note:*/ +/* - Must be multiple of 2 in semi-planar mode.*/ +#ifdef MRV_MI_DMA_CB_PIC_START_AD +#endif /* MRV_MI_DMA_CB_PIC_START_AD */ +/*****************************************************************************/ +/** + * register: mi_dma_cr_pic_start_ad: Cr component image start address (0x000000e8) + * + *****************************************************************************/ +/* Slice: dma_cr_pic_start_ad:*/ +/* Image start address of the Cr component */ +#ifdef MRV_MI_DMA_CR_PIC_START_AD +#endif /* MRV_MI_DMA_CR_PIC_START_AD */ +/*****************************************************************************/ +/** + * register: mi_imsc: Interrupt Mask Register (0x000000f8) + * mi_ris : Raw Interrupt Status Register (0x000000fc) + * mi_mis : Masked Interrupt Status Register (0x00000100) + * mi_icr : Interrupt Clear Register (0x00000104) + * mi_isr : Interrupt Set Register (0x00000108) + * + * ('1': interrupt active, '0': interrupt masked) + * + *****************************************************************************/ +/* Slice: dma_ready:*/ +/* Mask bit for dma ready interrupt */ +#ifndef MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0 +#endif /* MRV_MI_DMA_READY */ +/* Slice: wrap_sp_cr:*/ +/* Mask bit for self picture Cr address wrap interrupt */ +#ifndef MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0 +#endif /* MRV_MI_WRAP_SP_CR */ +/* Slice: wrap_sp_cb:*/ +/* Mask bit for self picture Cb address wrap interrupt */ +#ifndef MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0 +#endif /* MRV_MI_WRAP_SP_CB */ +/* Slice: wrap_sp_y:*/ +/* Mask bit for self picture Y address wrap interrupt */ +#ifndef MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0 +#endif /* MRV_MI_WRAP_SP_Y */ +/* Slice: wrap_mp_cr:*/ +/* Mask bit for main picture Cr address wrap interrupt */ +#ifndef MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0 +#endif /* MRV_MI_WRAP_MP_CR */ +/* Slice: wrap_mp_cb:*/ +/* Mask bit for main picture Cb address wrap interrupt */ +#ifndef MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0 +#endif /* MRV_MI_WRAP_MP_CB */ +/* Slice: wrap_mp_y:*/ +/* Mask bit for main picture Y address wrap interrupt */ +#ifndef MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0 +#endif /* MRV_MI_WRAP_MP_Y */ +/* Slice: fill_mp_y:*/ +/* Mask bit for fill level interrupt of main picture Y,*/ +/* JPEG or raw data */ +#ifndef MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0 +#endif /* MRV_MI_FILL_MP_Y */ +/* Slice: mblk_line:*/ +/* Mask bit for makroblock line interrupt of main picture */ +/* (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written */ +/* into RAM)*/ +#ifndef MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0 +#endif /* MRV_MI_MBLK_LINE */ +/* Slice: sp_frame_end:*/ +/* Mask self picture end of frame interrupt */ +#ifndef MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0 +#endif /* MRV_MI_SP_FRAME_END */ +/* Slice: mp_frame_end:*/ +/* Mask main picture end of frame interrupt */ +#ifndef MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0 +#endif /* MRV_MI_MP_FRAME_END */ +/* combination of all interrupt lines */ +#define MRV_MI_ALL_IRQS +#define MRV_MI_ALL_IRQS_MASK \ +(0 \ + | MRV_MI_DMA_READY_MASK \ + | MRV_MI_AHB_ERROR_MASK \ + | MRV_MI_WRAP_SP_CR_MASK \ + | MRV_MI_WRAP_SP_CB_MASK \ + | MRV_MI_WRAP_SP_Y_MASK \ + | MRV_MI_WRAP_MP_CR_MASK \ + | MRV_MI_WRAP_MP_CB_MASK \ + | MRV_MI_WRAP_MP_Y_MASK \ + | MRV_MI_FILL_MP_Y_MASK \ + | MRV_MI_MBLK_LINE_MASK \ + | MRV_MI_SP_FRAME_END_MASK \ + | MRV_MI_DMA_FRAME_END_MASK \ + | MRV_MI_MP_FRAME_END_MASK \ +) +#define MRV_MI_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register: mi_status : MI Status Register (0x0000010c) + * mi_status_clr: MI Status Clear Register (0x00000110) + * + *****************************************************************************/ +/* Slice: sp_cr_fifo_full:*/ +/* FIFO full flag of Cr FIFO in self path asserted since last clear */ +#ifndef MRV_MI_SP_CR_FIFO_FULL +#define MRV_MI_SP_CR_FIFO_FULL_MASK 0U +#endif /* MRV_MI_SP_CR_FIFO_FULL */ +/* Slice: sp_cb_fifo_full:*/ +/* FIFO full flag of Cb FIFO in self path asserted since last clear */ +#ifndef MRV_MI_SP_CB_FIFO_FULL +#define MRV_MI_SP_CB_FIFO_FULL_MASK 0U +#endif /* MRV_MI_SP_CB_FIFO_FULL */ +/* Slice: sp_y_fifo_full:*/ +/* FIFO full flag of Y FIFO in self path asserted since last clear */ +#ifndef MRV_MI_SP_Y_FIFO_FULL +#define MRV_MI_SP_Y_FIFO_FULL_MASK 0U +#endif /* MRV_MI_SP_Y_FIFO_FULL */ +/* Slice: mp_cr_fifo_full:*/ +/* FIFO full flag of Cr FIFO in main path asserted since last clear */ +#ifndef MRV_MI_MP_CR_FIFO_FULL +#define MRV_MI_MP_CR_FIFO_FULL_MASK 0U +#endif /* MRV_MI_MP_CR_FIFO_FULL */ +/* Slice: mp_cb_fifo_full:*/ +/* FIFO full flag of Cb FIFO in main path asserted since last clear */ +#ifndef MRV_MI_MP_CB_FIFO_FULL +#define MRV_MI_MP_CB_FIFO_FULL_MASK 0U +#endif /* MRV_MI_MP_CB_FIFO_FULL */ +/* Slice: mp_y_fifo_full:*/ +/* FIFO full flag of Y FIFO in main path asserted since last clear */ +#ifndef MRV_MI_MP_Y_FIFO_FULL +#define MRV_MI_MP_Y_FIFO_FULL_MASK 0U +#endif /* MRV_MI_MP_Y_FIFO_FULL */ +/* combination of all MI status lines */ +#define MRV_MI_ALL_STAT +#define MRV_MI_ALL_STAT_MASK \ +(0 \ + | MRV_MI_SP_CR_FIFO_FULL_MASK \ + | MRV_MI_SP_CB_FIFO_FULL_MASK \ + | MRV_MI_SP_Y_FIFO_FULL_MASK \ + | MRV_MI_MP_CR_FIFO_FULL_MASK \ + | MRV_MI_MP_CB_FIFO_FULL_MASK \ + | MRV_MI_MP_Y_FIFO_FULL_MASK \ +) +#define MRV_MI_ALL_STAT_SHIFT 0U +/*****************************************************************************/ +/** + * register: mi_sp_y_pic_width: Y component image width (0x00000114) + * + *****************************************************************************/ +/* Slice: sp_y_pic_width:*/ +/* Image width of the self picture Y component or RGB picture in pixel.*/ + /**/ +/* For YCbCr 4:2:x and RGB 565 the image width must be a multiple of 2.*/ +/* If no line stride is used but flipping required, the image width must be */ +/* a multiple of 8 for 4:2:x planar or 4 for 4:4:4 planar/4:2:x semi planar.*/ + /**/ +/* There are no restrictions for RGB 888/666.*/ + /**/ +/* In planar mode the image width of the Cb and Cr component is assumed according */ +/* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/ + /**/ +/* In semi planar 4:2:x mode the image width of the Cb component (which includes Cr)*/ +/* is assumed the same size.*/ + /**/ +/* In interleave mode no Cb/Cr image width is used.*/ +/* Note:*/ +/* - Image width always refers to the picture width of the output image. This is */ +/* particularly important when rotating.*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the register */ +/* only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_Y_PIC_WIDTH +#endif /* MRV_MI_SP_Y_PIC_WIDTH */ +/*****************************************************************************/ +/** + * register: mi_sp_y_pic_height: Y component image height (0x00000118) + * + *****************************************************************************/ +/* Slice: sp_y_pic_height:*/ +/* Image height of the y component or RGB picture in pixel.*/ + /**/ +/* In planar and semi planar mode the image width of the cb and cr component */ +/* is assumed according to the YCbCr format, i.e. half for 4:2:0 and the same */ +/* for 4:2:2 and 4:4:4.*/ + /**/ +/* Note:*/ +/* - Image height always refers to the picture height of the output image.*/ +/* This is particularly important when rotating.*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the register */ +/* only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_Y_PIC_HEIGHT +#endif /* MRV_MI_SP_Y_PIC_HEIGHT */ +/*****************************************************************************/ +/** + * register: mi_sp_y_pic_size: Y component image size (0x0000011c) + * + *****************************************************************************/ +/* Slice: sp_y_pic_size:*/ +/* Image size of the Y component or RGB picture in pixel which has to be the */ +/* Y line length multiplied by the Y image height (sp_y_llength * sp_y_pic_height).*/ + /**/ +/* In planar mode the image size of the Cb and Cr component is assumed according */ +/* to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for */ +/* 4:4:4.*/ + /**/ +/* In semi planar mode the image size of the Cb and Cr component is assumed half */ +/* for 4:2:0 and the same size for 4:2:2.*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the register only */ +/* if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_Y_PIC_SIZE +#endif /* MRV_MI_SP_Y_PIC_SIZE */ +/*****************************************************************************/ +/** + * register: mi_dma_ctrl: DMA control register (0x00000120) + * + *****************************************************************************/ +/* Slice: dma_rgb_format:*/ +/* Selects RGB Bayer data of read DMA picture */ + /**/ +/* 00: no DMA RGB Bayer data */ +/* 01: 8 bit RGB Bayer data */ +/* 10: 16 bit RGB Bayer data (12 bit used)*/ + /**/ +/* bytes are organized MSB first and 4 lower bits of LSB remain unused:*/ +/* byte_even -> bayer[11:4], byte_odd[7:4] -> bayer[3:0]*/ + /**/ +/* 11: reserved.*/ +#ifdef MRV_MI_DMA_RGB_FORMAT +#define MRV_MI_DMA_RGB_FORMAT_NO_DATA 0 +#define MRV_MI_DMA_RGB_FORMAT_8BIT_BAYER 1 +#define MRV_MI_DMA_RGB_FORMAT_16BIT_BAYER 2 +#endif /* MRV_MI_DMA_RGB_FORMAT */ +/* Slice: dma_frame_end_disable:*/ +/* Suppresses v_end so that no frame end can be detected by following */ +/* instances. Note: The dma_ready interrupt is raised as usual, but the */ +/* dma_frame_end interrupt will not be generated until v_end has been */ +/* enabled again.*/ +#ifdef MRV_MI_DMA_FRAME_END_DISABLE +#endif /* MRV_MI_DMA_FRAME_END_DISABLE */ +/* Slice: dma_continuous_en:*/ +/* Enables continuous mode. If set the same frame is read back over and */ +/* over. A start pulse on dma_start is needed only for the first time.*/ +/* To stop continuous mode reset this bit (takes effect after the next */ +/* frame end) or execute a soft reset. This bit is intended to be used */ +/* in conjunction with the Superimpose feature.*/ +#ifdef MRV_MI_DMA_CONTINUOUS_EN +#endif /* MRV_MI_DMA_CONTINUOUS_EN */ +/* Slice: dma_byte_swap:*/ +/* Enables change of DMA byte order of the 32 bit input word at read port */ +/* 1: byte order is mirrored but the bit order within one byte doesn’t change */ +/* 0: no byte mirroring */ +#ifdef MRV_MI_DMA_BYTE_SWAP +#endif /* MRV_MI_DMA_BYTE_SWAP */ +/* Slice: dma_inout_format:*/ +/* Selects input/output format of DMA picture.*/ +/* 11: YCbCr 4:4:4 */ +/* 10: YCbCr 4:2:2 */ +/* 01: YCbCr 4:2:0 */ +/* 00: YCbCr 4:0:0 */ +#ifdef MRV_MI_DMA_INOUT_FORMAT +#define MRV_MI_DMA_INOUT_FORMAT_YUV444 3 /* 11: YCbCr 4:4:4 */ +#define MRV_MI_DMA_INOUT_FORMAT_YUV422 2 /* 10: YCbCr 4:2:2 */ +#define MRV_MI_DMA_INOUT_FORMAT_YUV420 1 /* 01: YCbCr 4:2:0 */ +#define MRV_MI_DMA_INOUT_FORMAT_YUV400 0 /* 00: YCbCr 4:0:0 */ +#endif /* MRV_MI_DMA_INOUT_FORMAT */ +/* Slice: dma_read_format:*/ +/* Defines how YCbCr picture data is read from memory.*/ +/* 00: planar */ +/* 01: semi planar, for YCbCr 4:2:x */ +/* 10: interleaved (combined), for YCbCr 4:2:2 and RGB only */ +/* 11: reserved */ +#ifdef MRV_MI_DMA_READ_FORMAT +#define MRV_MI_DMA_READ_FORMAT_PLANAR 0 /* 00: planar */ +#define MRV_MI_DMA_READ_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */ +#define MRV_MI_DMA_READ_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */ +#endif /* MRV_MI_DMA_READ_FORMAT */ +/* Slice: dma_burst_len_chrom:*/ +/* Burst length for Cb or Cr data affecting DMA read port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ +#ifdef MRV_MI_DMA_BURST_LEN_CHROM +#define MRV_MI_DMA_BURST_LEN_CHROM_4 0 /* 0: 4-beat bursts */ +#define MRV_MI_DMA_BURST_LEN_CHROM_8 1 /* 1: 8-beat bursts */ +#define MRV_MI_DMA_BURST_LEN_CHROM_16 2 /* 2: 16-beat bursts */ +#endif /* MRV_MI_DMA_BURST_LEN_CHROM */ +/* Slice: dma_burst_len_lum:*/ +/* Burst length for Y data affecting DMA read port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ +#ifdef MRV_MI_DMA_BURST_LEN_LUM +#define MRV_MI_DMA_BURST_LEN_LUM_4 0 /* 0: 4-beat bursts */ +#define MRV_MI_DMA_BURST_LEN_LUM_8 1 /* 1: 8-beat bursts */ +#define MRV_MI_DMA_BURST_LEN_LUM_16 2 /* 2: 16-beat bursts */ +#endif /* MRV_MI_DMA_BURST_LEN_LUM */ +/*****************************************************************************/ +/** + * register: mi_dma_start: DMA start register (0x00000124) + * + *****************************************************************************/ +/* Slice: dma_start:*/ +/* Enables DMA access. Additionally main or self path has to be enabled separately.*/ +#ifdef MRV_MI_DMA_START +#endif /* MRV_MI_DMA_START */ +/*****************************************************************************/ +/** + * register: mi_dma_status: DMA status register (0x00000128) + * + *****************************************************************************/ +/* Slice: dma_active:*/ +/* If set DMA access is active.*/ +#ifdef MRV_MI_DMA_ACTIVE +#endif /* MRV_MI_DMA_ACTIVE */ +/*****************************************************************************/ +/** + * register: mi_pixel_cnt: Counter value for defect pixel list (0x0000012c) + * + *****************************************************************************/ +/* Slice: pix_cnt:*/ +/* Counter value specifies the number of pixels of the defect pixel list */ +/* generated by DPCC of the last transmitted frame. Updated at frame end.*/ + /**/ +/* A soft reset will set the counter to zero.*/ +#ifdef MRV_MI_PIX_CNT +#endif /* MRV_MI_PIX_CNT */ +#ifdef ISP_MI_HANDSHAKE_NANO +/* Nano handshake */ +/*****************************************************************************/ +/** + * register: isp_handshake_ctrl_0: Nano handshake functions (0x0000014C) + * + *****************************************************************************/ + /*! Slice: mp_handshake_en: */ +/*! Enable mp handshake function for MI MP */ +#ifdef MRV_MI_MP_HANDSHK_EN +#define MRV_MI_MP_HANDSHK_EN_DISABLE 0 /* HANDSHAKE disable */ +#define MRV_MI_MP_HANDSHK_EN_ENABLE 1 /* HANDSHAKE enable, active high */ +#endif +/*! Slice: mp_handshk_storage_format */ +/*! Define how YCbCr picture data is stored in memory */ +/*! 00: Planar */ +/*! 01: Semi planar, for YCbCr4:2:x */ +/*! 10: Interleaved(combiled), for YCbCr 4:2:2 only or RAW format.*/ +/*! 11: not support */ +#ifdef MRV_MI_MP_HANDSHK_STORAGE_FORMAT +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_PLANAR 0 /* 00: Planar */ +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_SEMIPLANAR 1 /* 01: Semi-Planar */ +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_INTERLEAVED 2 /* 10: Interleaved */ +#endif +/*! Slice: mp_handshk_data_format */ +/*! Defines the video format */ +/*! 00: RAW format */ +/*! 01: reserved */ +/*! 10: YUV 422 */ +/*! 11: YUV 420 */ +#ifdef MRV_MI_MP_HANDSHK_DATA_FORMAT +#define MRV_MI_MP_HANDSHK_DATA_FORMAT_RAW 0 /* 00: raw format */ +#define MRV_MI_MP_HANDSHK_DATA_FORMAT_YUV422 2 /* 10: YUV422 */ +#define MRV_MI_MP_HANDSHK_DATA_FORMAT_YUV420 3 /* 11: YUV420 */ +#endif +/*! Slice: mp_handshk_slice_size */ +/*! Defines the slice size to generate handshake signals, minus 1 is used */ +#ifdef MRV_MI_MP_HANDSHK_SLICE_SIZE +#endif +/*! Slice: mp_handshk_slice_buf_size */ +/*! Defines the circular buffer size in number of defined slices per buffer, minus 1 is used */ +#ifdef MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE +#endif +/*! Slice: mp_handshk_ack_count */ +/*! Defines the acknowledage is not received in the defined cycles, it will generate handshake interrupt.*/ +#ifdef MRV_MI_MP_HANDSHK_ACK_COUNT +#endif +#endif +#ifdef ISP_MI_ALIGN_NANO +/* MI output Alignment */ +/*****************************************************************************/ +/** + * register: mi_output_alignment: Nano MI output alignment (0x0000015C) + * + *****************************************************************************/ +/* Slice: mp_lsb_alignment:*/ +/*! msb/lsb align for raw 10 and raw 12 formats control */ +/*! 0: MSB aligned for RAW10 and RAW12 formats */ +/*! 1: LSB aligned for RAW10 and RAW12 formats */ +#ifdef MRV_MI_LSB_ALIGNMENT +#define MRV_MI_LSB_ALIGNMENT_MSB 0 /* MSB aligned for raw 10 and raw 12 formats */ +#define MRV_MI_LSB_ALIGNMENT_LSB 1 /* LSB aligned for raw 10 and raw 12 formats */ +#endif +#endif +#ifdef ISP_MI_BYTESWAP +/*! Slice mp_byte_swap:*/ +/*! swap bytes for ISP Nano */ +/*! bit 0 to swap bytes */ +/*! bit 1 to swap words */ +/*! bit 2 to swap dwords */ +/*! 3'b001: ABCDEFGH => BADCFEHG */ +/*! 3'b000: ABCDEFGH => ABCDEFGH */ +/*! 3'b010: ABCDEFGH => CDABGHEF */ +/*! 3'b011: ABCDEFGH => DCBAHGFE */ +/*! 3'b100: ABCDEFGH => EFGHABCD */ +/*! 3'b101: ABCDEFGH => FEHGBADC */ +/*! 3'b110: ABCDEFGH => GHEFCDAB */ +/*! 3'b111: ABCDEFGH => HGFEDCBA */ +#ifdef MRV_MI_MP_BYTE_SWAP +#define MRV_MI_MP_BYTE_SWAP_NORMAL 0x0 /* normal mode */ +#define MRV_MI_MP_BYTE_SWAP_BYTE 0x1 /* bit 0 to swap bytes */ +#define MRV_MI_MP_BYTE_SWAP_WORD 0x2 /* bit 1 to swap words */ +#define MRV_MI_MP_BYTE_SWAP_DWORD 0x4 /* bit 2 to swap dwords */ +#endif +#endif +#ifdef ISP_MI_FIFO_DEPTH_NANO +/*****************************************************************************/ +/** + * register: mi_mp_output_fifo_size: Nano MI fifo control (0x00000160) + * + *****************************************************************************/ +/*! Slice output_fifo_depth:*/ +/*! Select output FIFO depth setting */ +/*! 00: FULL(2KBytes)*/ +/*! 01: HALF(1KBytes)*/ +/*! 10: 1/4(512Bytes)*/ +/*! 11: 1/8(256Bytes)*/ +#ifdef MRV_MI_OUTOUT_FIFO_DEPTH +#define MRV_MI_OUTOUT_FIFO_DEPTH_FULL 0 /* FULL(2KBytes) */ +#define MRV_MI_OUTOUT_FIFO_DEPTH_HALF 1 /* HALF(1KBytes) */ +#define MRV_MI_OUTOUT_FIFO_DEPTH_1_4 2 /* 1/4(512Bytes) */ +#define MRV_MI_OUTOUT_FIFO_DEPTH_1_8 3 /* 1/8(256Bytes) */ +#endif +#endif +/*****************************************************************************/ +/* JPEG Encoder Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: jpe_gen_header: command to start stream header generation (0x0000) + * + *****************************************************************************/ +/* Slice: gen_header:*/ +/* "1" = Start command to generate stream header */ +/* auto reset to zero after one clock cycle */ +#ifdef MRV_JPE_GEN_HEADER +#endif /* MRV_JPE_GEN_HEADER */ +/*****************************************************************************/ +/** + * register: jpe_encode: Start command to start JFIF stream encoding (0x0004) + * + *****************************************************************************/ +/* Slice: encode:*/ +/* "1" = Start command to start JFIF stream encoding;*/ +/* auto reset to zero after one clock cycle.*/ +/* This bit is write-only: reading result is always zero!*/ +#ifdef MRV_JPE_ENCODE +#endif /* MRV_JPE_ENCODE */ +/*****************************************************************************/ +/** + * register: jpe_init: Automatic configuration update (INIT) (0x0008) + * + *****************************************************************************/ +/* Slice: JP_INIT:*/ +/* "1" = Immediate start of JPEG encoder.*/ + /**/ +/* This bit has to be set after "Encode" to start the JPEG encoder. The "Encode"*/ +/* command becomes active either with JP_INIT or with the input signal "CFG_UPD".*/ +/* auto reset to zero after one clock cycle !!!*/ +#ifdef MRV_JPE_JP_INIT +#endif /* MRV_JPE_JP_INIT */ +/*****************************************************************************/ +/** + * register: jpe_y_scale_en: Y value scaling control register (0x0000000c) + * + *****************************************************************************/ +/* Slice: y_scale_en:*/ +/* Y scale flag */ +/* 1: scaling Y input from [16..235] to [0..255]*/ +/* 0: no Y input scaling */ +#ifdef MRV_JPE_Y_SCALE_EN +#endif /* MRV_JPE_Y_SCALE_EN */ +/*****************************************************************************/ +/** + * register: jpe_cbcr_scale_en: Cb/Cr value scaling control register (0x00000010) + * + *****************************************************************************/ +/* Slice: cbcr_scale_en:*/ +/* Cb/Cr scale flag */ +/* 1: scaling Cb/Cr input from [16..240] to [0..255]*/ +/* 0: no Cb/Cr input scaling */ +#ifdef MRV_JPE_CBCR_SCALE_EN +#endif /* MRV_JPE_CBCR_SCALE_EN */ +/*****************************************************************************/ +/** + * register: jpe_table_flush: header generation debug register (0x00000014) + * + *****************************************************************************/ +/* Slice: table_flush:*/ +/* header generation debug control flag */ +/* (controls transmission of last header bytes if the 64 bit output buffer */ +/* is not completely filled)*/ +/* 1: immediately transmit last header bytes */ +/* 0: wait for encoded image data to fill output buffer */ +#ifdef MRV_JPE_TABLE_FLUSH +#endif /* MRV_JPE_TABLE_FLUSH */ +/*****************************************************************************/ +/** + * register: jpe_enc_hsize: JPEG codec horizontal image size for encoding + * (0x00000018) + * + *****************************************************************************/ +/* Slice: enc_hsize:*/ +/* JPEG codec horizontal image size for R2B and SGEN blocks */ +#ifdef MRV_JPE_ENC_HSIZE +#endif /* MRV_JPE_ENC_HSIZE */ +/*****************************************************************************/ +/** + * register: jpe_enc_vsize: JPEG codec vertical image size for encoding + * (0x0000001c) + * + *****************************************************************************/ +/* Slice: enc_vsize:*/ +/* JPEG codec vertical image size for R2B and SGEN blocks */ +#ifdef MRV_JPE_ENC_VSIZE +#endif /* MRV_JPE_ENC_VSIZE */ +/*****************************************************************************/ +/** + * register: jpe_pic_format: JPEG picture encoding format (0x00000020) + * + *****************************************************************************/ +/* Slice: enc_pic_format:*/ +/* "0:0:1" = 4:2:2 format */ +/* "1:x:x" = 4:0:0 format */ +#ifdef MRV_JPE_ENC_PIC_FORMAT +#define MRV_JPE_ENC_PIC_FORMAT_422 1 /* "0:0:1" = 4:2:2 format */ +#define MRV_JPE_ENC_PIC_FORMAT_400 4 /* "1:x:x" = 4:0:0 format */ +#endif /* MRV_JPE_ENC_PIC_FORMAT */ +/*****************************************************************************/ +/** + * register: jpe_restart_interval: restart marker insertion register (0x0024) + * + *****************************************************************************/ +/* Slice: restart_interval:*/ +/* No of MCU in reset interval via host */ +#ifdef MRV_JPE_RESTART_INTERVAL +#endif /* MRV_JPE_RESTART_INTERVAL */ +/*****************************************************************************/ +/** + * register: jpe_tq_y_select: Q- table selector 0, quant. table for Y + * component (0x00000028) + * + *****************************************************************************/ +/* Slice: tq0_select:*/ +/* "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#ifdef MRV_JPE_TQ0_SELECT +#endif /* MRV_JPE_TQ0_SELECT */ +/*****************************************************************************/ +/** + * register: jpe_tq_u_select: Q- table selector 1, quant. table for U + * component (0x0000002c) + * + *****************************************************************************/ +/* Slice: tq1_select:*/ +/* "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#ifdef MRV_JPE_TQ1_SELECT +#endif /* MRV_JPE_TQ1_SELECT */ +/*****************************************************************************/ +/** + * register: jpe_tq_v_select: Q- table selector 2, quant. table for V + * component (0x00000030) + * + *****************************************************************************/ +/* Slice: tq2_select:*/ +/* "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#ifdef MRV_JPE_TQ2_SELECT +#endif /* MRV_JPE_TQ2_SELECT */ +#define MRV_JPE_TQ_SELECT_TAB3 3 /* "11": qtable 3 */ +#define MRV_JPE_TQ_SELECT_TAB2 2 /* "10": qtable 2 */ +#define MRV_JPE_TQ_SELECT_TAB1 1 /* "01": qtable 1 */ +#define MRV_JPE_TQ_SELECT_TAB0 0 /* "00": qtable 0 */ +/*****************************************************************************/ +/** + * register: jpe_dc_table_select: Huffman table selector for DC values + * (0x00000034) + * + *****************************************************************************/ +/* Slice: dc_table_select_v:*/ +/* "0" = dc table 0; color component 2 (V)*/ +/* "1" = dc table 1; color component 2 (V)*/ +#ifdef MRV_JPE_DC_TABLE_SELECT_V +#endif /* MRV_JPE_DC_TABLE_SELECT_V */ +/* Slice: dc_table_select_u:*/ +/* "0" = dc table 0; color component 1 (U)*/ +/* "1" = dc table 1; color component 1 (U)*/ +#ifdef MRV_JPE_DC_TABLE_SELECT_U +#endif /* MRV_JPE_DC_TABLE_SELECT_U */ +/* Slice: dc_table_select_y:*/ +/* "0" = dc table 0; color component 0 (Y)*/ +/* "1" = dc table 1; color component 0 (Y)*/ +#ifdef MRV_JPE_DC_TABLE_SELECT_Y +#endif /* MRV_JPE_DC_TABLE_SELECT_Y */ +/*****************************************************************************/ +/** + * register: jpe_ac_table_select: Huffman table selector for AC values + * (0x00000038) + * + *****************************************************************************/ +/* Slice: ac_table_select_v:*/ +/* "0" = ac table 0; component 2 (V)*/ +/* "1" = ac table 1; component 2 (V)*/ +#ifdef MRV_JPE_AC_TABLE_SELECT_V +#endif /* MRV_JPE_AC_TABLE_SELECT_V */ +/* Slice: ac_table_select_u:*/ +/* "0" = ac table 0; component 1 (U)*/ +/* "1" = ac table 1; component 1 (U)*/ +#ifdef MRV_JPE_AC_TABLE_SELECT_U +#endif /* MRV_JPE_AC_TABLE_SELECT_U */ +/* Slice: ac_table_select_y:*/ +/* "0" = ac table 0; component 0 (Y)*/ +/* "1" = ac table 1; component 0 (Y)*/ +#ifdef MRV_JPE_AC_TABLE_SELECT_Y +#endif /* MRV_JPE_AC_TABLE_SELECT_Y */ +/*****************************************************************************/ +/** + * register: jpe_table_data: table programming register (0x0000003c) + * + *****************************************************************************/ +/* Slice: table_wdata_h:*/ +/* Table data MSB */ +#ifdef MRV_JPE_TABLE_WDATA_H +#endif /* MRV_JPE_TABLE_WDATA_H */ +/* Slice: table_wdata_l:*/ +/* Table data LSB */ +#ifdef MRV_JPE_TABLE_WDATA_L +#endif /* MRV_JPE_TABLE_WDATA_L */ +/*****************************************************************************/ +/** + * register: jpe_table_id: table programming select register (0x00000040) + * + *****************************************************************************/ +/* Slice: table_id:*/ +/* select table */ +/* "0000" : Q-table 0 */ +/* "0001" : Q-table 1 */ +/* "0010" : Q-table 2 */ +/* "0011" : Q-table 3 */ +/* "0100" : VLC DC-table 0 */ +/* "0101" : VLC AC-table 0 */ +/* "0110" : VLC DC-table 1 */ +/* "0111" : VLC AC-table 1 */ +/* "1xxx" : reserved for debug */ +#ifdef MRV_JPE_TABLE_ID +#define MRV_JPE_TABLE_ID_QUANT0 0 /* "0000" : Q-table 0 */ +#define MRV_JPE_TABLE_ID_QUANT1 1 /* "0001" : Q-table 1 */ +#define MRV_JPE_TABLE_ID_QUANT2 2 /* "0010" : Q-table 2 */ +#define MRV_JPE_TABLE_ID_QUANT3 3 /* "0011" : Q-table 3 */ +#define MRV_JPE_TABLE_ID_VLC_DC0 4 /* "0100" : VLC DC-table 0 */ +#define MRV_JPE_TABLE_ID_VLC_AC0 5 /* "0101" : VLC AC-table 0 */ +#define MRV_JPE_TABLE_ID_VLC_DC1 6 /* "0110" : VLC DC-table 1 */ +#define MRV_JPE_TABLE_ID_VLC_AC1 7 /* "0111" : VLC AC-table 1 */ +#endif /* MRV_JPE_TABLE_ID */ +/*****************************************************************************/ +/** + * register: jpe_tac0_len: Huffman AC table 0 length (0x0044) + * + *****************************************************************************/ +/* Slice: tac0_len:*/ +/* Huffman table length for ac0 table */ +#ifdef MRV_JPE_TAC0_LEN +#endif /* MRV_JPE_TAC0_LEN */ +/*****************************************************************************/ +/** + * register: jpe_tdc0_len: Huffman DC table 0 length (0x00000048) + * + *****************************************************************************/ +/* Slice: tdc0_len:*/ +/* Huffman table length for dc0 table */ +#ifdef MRV_JPE_TDC0_LEN +#endif /* MRV_JPE_TDC0_LEN */ +/*****************************************************************************/ +/** + * register: jpe_tac1_len: Huffman AC table 1 length (0x0000004c) + * + *****************************************************************************/ +/* Slice: tac1_len:*/ +/* Huffman table length for ac1 table */ +#ifdef MRV_JPE_TAC1_LEN +#endif /* MRV_JPE_TAC1_LEN */ +/*****************************************************************************/ +/** + * register: jpe_tdc1_len: Huffman DC table 1 length (0x00000050) + * + *****************************************************************************/ +/* Slice: tdc1_len:*/ +/* Huffman table length for dc1 table */ +#ifdef MRV_JPE_TDC1_LEN +#endif /* MRV_JPE_TDC1_LEN */ +/*****************************************************************************/ +/** + * register: jpe_encoder_busy: encoder status flag (0x00000058) + * + *****************************************************************************/ +/* Slice: codec_busy:*/ +/* Bit 0 = "1" : JPEG codec in process */ +#ifdef MRV_JPE_CODEC_BUSY +#endif /* MRV_JPE_CODEC_BUSY */ +/*****************************************************************************/ +/** + * register: jpe_header_mode: header mode definition (0x0000005c) + * + *****************************************************************************/ +/* Slice: header_mode:*/ +/* "00" = no header */ +/* "01" = reserved */ +/* "10" = JFIF 1.02 header */ +/* "11" = reserved */ +#ifdef MRV_JPE_HEADER_MODE +#define MRV_JPE_HEADER_MODE_NONE 0 /* "00" = no APPn header */ +#define MRV_JPE_HEADER_MODE_JFIF 2 /* "10" = JFIF header */ +#endif /* MRV_JPE_HEADER_MODE */ +/*****************************************************************************/ +/** + * register: jpe_encode_mode: encode mode (0x00000060) + * + *****************************************************************************/ +/* Slice: encode_mode:*/ +/* Always "1", because this is the encoder only edition */ +#ifdef MRV_JPE_ENCODE_MODE +#endif /* MRV_JPE_ENCODE_MODE */ +/*****************************************************************************/ +/** + * register: jpe_debug: debug information register (0x00000064) + * + *****************************************************************************/ +/* Slice: deb_bad_table_access:*/ +/* Debug signal only (set if an access to the TABLE_DATA or to the TABLE_ID */ +/* register is performed, when the JPEG_ENCODER is busy. In this case a default */ +/* PVCI Acknowledge is generated. Thus the configuration bus is not blocked)*/ +#ifdef MRV_JPE_DEB_BAD_TABLE_ACCESS +#endif /* MRV_JPE_DEB_BAD_TABLE_ACCESS */ +/* Slice: deb_vlc_table_busy:*/ +/* Debug signal only (vlc access to huff-tables)*/ +#ifdef MRV_JPE_DEB_VLC_TABLE_BUSY +#endif /* MRV_JPE_DEB_VLC_TABLE_BUSY */ +/* Slice: deb_r2b_memory_full:*/ +/* Debug signal only (line memory status of r2b)*/ +#ifdef MRV_JPE_DEB_R2B_MEMORY_FULL +#endif /* MRV_JPE_DEB_R2B_MEMORY_FULL */ +/* Slice: deb_vlc_encode_busy:*/ +/* Debug signal only (vlc encode processing active)*/ +#ifdef MRV_JPE_DEB_VLC_ENCODE_BUSY +#endif /* MRV_JPE_DEB_VLC_ENCODE_BUSY */ +/* Slice: deb_qiq_table_acc:*/ +/* Debug signal only (QIQ table access)*/ +#ifdef MRV_JPE_DEB_QIQ_TABLE_ACC +#endif /* MRV_JPE_DEB_QIQ_TABLE_ACC */ +/*****************************************************************************/ +/** + * register: jpe_error_imr: JPEG error interrupt mask register (0x00000068) + * jpe_error_ris: JPEG error raw interrupt status register (0x0000006c) + * jpe_error_mis: JPEG error masked interrupt status register (0x00000070) + * jpe_error_icr: JPEG error interrupt set register (0x00000074) + * jpe_error_isr: JPEG error interrupt clear register (0x00000078) + * + *****************************************************************************/ +/* Slice: vlc_table_err:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_VLC_TABLE_ERR +#endif /* MRV_JPE_VLC_TABLE_ERR */ +/* Slice: r2b_IMG_size_err:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_R2B_IMG_SIZE_ERR +#endif /* MRV_JPE_R2B_IMG_SIZE_ERR */ +/* Slice: DCT_ERR:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_DCT_ERR +#endif /* MRV_JPE_DCT_ERR */ +/* Slice: vlc_symbol_err:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_VLC_SYMBOL_ERR +#endif /* MRV_JPE_VLC_SYMBOL_ERR */ +/*****************************************************************************/ +/** + * register: jpe_status_imr: JPEG status interrupt mask register (0x0000007c) + * jpe_status_ris: JPEG status raw interrupt status register (0x00000080) + * jpe_status_mis: JPEG status masked interrupt status register (0x00000084) + * jpe_status_icr: JPEG status interrupt clear register (0x00000088) + * jpe_status_isr: JPEG status interrupt set register (0x0000008c) + * + *****************************************************************************/ +/* Slice: gen_header_done:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_GEN_HEADER_DONE +#endif /* MRV_JPE_GEN_HEADER_DONE */ +/* Slice: encode_done:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_ENCODE_DONE +#endif /* MRV_JPE_ENCODE_DONE */ +/*****************************************************************************/ +/** + * register: jpe_config: JPEG configuration register (0x00000090) + * + *****************************************************************************/ +/* Slice: speedview_en:*/ +/* 1: speed view enabled */ +/* 0: speed view disabled */ +#ifdef MRV_JPE_SPEEDVIEW_EN +#define MRV_JPE_SPEEDVIEW_EN_DISABLE 0 /* "0": JPEG Stream Encoding according to JPEG standard */ +#define MRV_JPE_SPEEDVIEW_EN_ENABLE 1 /* "1": SpeedView JPEG Stream Encoding enabled */ +#endif /* MRV_JPE_SPEEDVIEW_EN */ +/* Slice: cont_mode:*/ +/* Encoder continous mode */ +/* "00": encoder stops at frame end (corresponds to former behavior)*/ +/* "01": encoder starts automatically to encode the next frame */ +/* "10": unused */ +/* "11": encoder first generates next header and then encodes automatically the next frame */ +/* These settings are checked after encoding one frame. They are not auto-reset by hardware.*/ +#ifdef MRV_JPE_CONT_MODE +#define MRV_JPE_CONT_MODE_STOP 0 /* "00": encoder stops at frame end (corresponds to former behavior) */ +#define MRV_JPE_CONT_MODE_NEXT 1 /* "01": encoder starts automatically to encode the next frame */ +#define MRV_JPE_CONT_MODE_HEADER 3 /* "11": encoder first generates next header and then encodes automatically the next frame */ +#endif /* MRV_JPE_CONT_MODE */ +/*****************************************************************************/ +/* MIPI Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: mipi_ctrl: global control register (0x0000) + * + *****************************************************************************/ +/* Slice: S_ENABLE_CLK */ +/* 1: enable sensor clock lane (DEFAULT)*/ +/* 0: disable sensor clock lane */ +#ifdef MRV_MIPI_S_ENABLE_CLK +#endif /* MRV_MIPI_S_ENABLE_CLK */ +/* Slice: ERR_SOT_SYNC_HS_SKIP:*/ +/* 1: data within the current transmission is skipped if ErrSotSyncHS is detected (default)*/ +/* 0: ErrSotSyncHS does not affect transmission */ +#ifdef MRV_MIPI_ERR_SOT_SYNC_HS_SKIP +#endif /* MRV_MIPI_ERR_SOT_SYNC_HS_SKIP */ +/* Slice: ERR_SOT_HS_SKIP:*/ +/* 1: data within the current transmission is skipped if ErrSotHS is detected */ +/* 0: ErrSotHS does not affect transmission (default)*/ +#ifdef MRV_MIPI_ERR_SOT_HS_SKIP +#endif /* MRV_MIPI_ERR_SOT_HS_SKIP */ +/* Slice: NUM_LANES:*/ +/* 00: Lane 1 is used;*/ +/* 01: Lanes 1 and 2 are used;*/ +/* 10: Lanes 1...3 are used;*/ +/* 11: Lanes 1...4 are used */ +#ifdef MRV_MIPI_NUM_LANES +#define MRV_MIPI_NUM_LANES_1 0 /* 00: Lane 1 is used */ +#define MRV_MIPI_NUM_LANES_2 1 /* 01: Lanes 1 and 2 are used */ +#define MRV_MIPI_NUM_LANES_3 2 /* 10: Lanes 1...3 are used */ +#define MRV_MIPI_NUM_LANES_4 3 /* 11: Lanes 1...4 are used */ +#endif /* MRV_MIPI_NUM_LANES */ +/* Slice: SHUTDOWN_LANE:*/ +/* Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown[n-1:0]*/ +#ifdef MRV_MIPI_SHUTDOWN_LANE +#define MRV_MIPI_SHUTDOWN_LANE_1 1 /* 0001: shutdown lane 1 */ +#define MRV_MIPI_SHUTDOWN_LANE_2 2 /* 0010: shutdown lane 1 */ +#define MRV_MIPI_SHUTDOWN_LANE_3 4 /* 0100: shutdown lane 1 */ +#define MRV_MIPI_SHUTDOWN_LANE_4 8 /* 1000: shutdown lane 1 */ +#endif /* MRV_MIPI_SHUTDOWN_LANE */ +/* Slice: FLUSH_FIFO:*/ +/* writing '1' resets the write- and read pointers of the additional data fifo.*/ +#ifdef MRV_MIPI_FLUSH_FIFO +#endif /* MRV_MIPI_FLUSH_FIFO */ +/* Slice: OUTPUT_ENA:*/ +/* 1: output to add data fifo and to output interface is enabled */ +#ifdef MRV_MIPI_OUTPUT_ENA +#endif /* MRV_MIPI_OUTPUT_ENA */ +/*****************************************************************************/ +/** + * register: mipi_status: global status register (0x0004) + * + *****************************************************************************/ +/* Slice: S_ULP_ACTIVE_NOT_CLK:*/ +/* sensor clock lane is in ULP state. This register is directly connected to the synchronized input signal "s_ulpsactivenotclk"*/ +#ifdef MRV_MIPI_S_ULP_ACTIVE_NOT_CLK +#endif /* MRV_MIPI_S_ULP_ACTIVE_NOT_CLK */ +/* Slice: S_STOPSTATE_CLK:*/ +/* sensor clock lane is in stopstate. This register is directly connected to the synchronized input signal "s_stopstateclk"*/ +#ifdef MRV_MIPI_S_STOPSTATE_CLK +#endif /* MRV_MIPI_S_STOPSTATE_CLK */ +/* Slice: STOPSTATE:*/ +/* Lane is in stopstate. This register is directly connected to the synchronized input signal stopstate[n-1:0]*/ +#ifdef MRV_MIPI_STOPSTATE +#endif /* MRV_MIPI_STOPSTATE */ +/* Slice: ADD_DATA_AVAIL:*/ +/* 1: additional data fifo contains data */ +/* 0: additional data fifo is empty */ +#ifdef MRV_MIPI_ADD_DATA_AVAIL +#endif /* MRV_MIPI_ADD_DATA_AVAIL */ +/*****************************************************************************/ +/** + * register: mipi_imsc: Interrupt mask (0x00000008) + * + *****************************************************************************/ +/* Slice: IMSC_GEN_SHORT_PACK:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_GEN_SHORT_PACK +#define MRV_MIPI_IMSC_GEN_SHORT_PACK_MASK 0 +#endif /* MRV_MIPI_IMSC_GEN_SHORT_PACK */ +/* Slice: IMSC_ADD_DATA_FILL_LEVEL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK 0 +#endif /* MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL */ +/* Slice: IMSC_ADD_DATA_OVFLW:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ADD_DATA_OVFLW +#endif /* MRV_MIPI_IMSC_ADD_DATA_OVFLW */ +/* Slice: IMSC_FRAME_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_FRAME_END +#define MRV_MIPI_IMSC_FRAME_END_MASK 0 +#endif /* MRV_MIPI_IMSC_ADD_DATA_OVFLW */ +/* Slice: IMSC_ERR_CS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ERR_CS +#define MRV_MIPI_IMSC_ERR_CS_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_CS */ +/* Slice: IMSC_ERR_ECC1:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ERR_ECC1 +#define MRV_MIPI_IMSC_ERR_ECC1_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_ECC1 */ +/* Slice: IMSC_ERR_ECC2:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ERR_ECC2 +#define MRV_MIPI_IMSC_ERR_ECC2_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_ECC2 */ +/* Slice: IMSC_ERR_PROTOCOL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ERR_PROTOCOL +#define MRV_MIPI_IMSC_ERR_PROTOCOL_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_PROTOCOL */ +/* Slice: IMSC_ERR_CONTROL:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_IMSC_ERR_CONTROL +#define MRV_MIPI_IMSC_ERR_CONTROL_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_CONTROL */ +/* Slice: IMSC_ERR_EOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_IMSC_ERR_EOT_SYNC +#define MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_EOT_SYNC */ +/* Slice: IMSC_ERR_SOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_IMSC_ERR_SOT_SYNC +#define MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_SOT_SYNC */ +/* Slice: IMSC_ERR_SOT:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_IMSC_ERR_SOT +#define MRV_MIPI_IMSC_ERR_SOT_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_SOT */ +/* Slice: IMSC_SYNC_FIFO_OVFLW:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_IMSC_SYNC_FIFO_OVFLW +#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK 0 +#endif /* MRV_MIPI_IMSC_SYNC_FIFO_OVFLW */ +/* combination of all interrupt lines */ +#define MRV_MIPI_IMSC_ALL_IRQS +#define MRV_MIPI_IMSC_ALL_IRQS_MASK \ +(MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK \ + | MRV_MIPI_IMSC_ADD_DATA_OVFLW_MASK \ + | MRV_MIPI_IMSC_FRAME_END_MASK \ + | MRV_MIPI_IMSC_ERR_CS_MASK \ + | MRV_MIPI_IMSC_ERR_ECC1_MASK \ + | MRV_MIPI_IMSC_ERR_ECC2_MASK \ + | MRV_MIPI_IMSC_ERR_PROTOCOL_MASK \ + | MRV_MIPI_IMSC_ERR_CONTROL_MASK \ + | MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK \ + | MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK \ + | MRV_MIPI_IMSC_ERR_SOT_MASK \ + | MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK \ +) +#define MRV_MIPI_IMSC_ALL_IRQS_SHIFT 0 +/*****************************************************************************/ +/** + * register: mipi_ris: Raw interrupt status (0x0000000c) + * + *****************************************************************************/ +/* Slice: RIS_GEN_SHORT_PACK:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_GEN_SHORT_PACK +#define MRV_MIPI_RIS_GEN_SHORT_PACK_MASK 0 +#endif /* MRV_MIPI_RIS_GEN_SHORT_PACK */ +/* Slice: RIS_ADD_DATA_FILL_LEVEL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK 0 +#endif /* MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL */ +/* Slice: RIS_ADD_DATA_OVFLW:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ADD_DATA_OVFLW +#endif /* MRV_MIPI_RIS_ADD_DATA_OVFLW */ +/* Slice: RIS_FRAME_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_FRAME_END +#define MRV_MIPI_RIS_FRAME_END_MASK 0 +#endif /* MRV_MIPI_RIS_ADD_DATA_OVFLW */ +/* Slice: RIS_ERR_CS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ERR_CS +#define MRV_MIPI_RIS_ERR_CS_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_CS */ +/* Slice: RIS_ERR_ECC1:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ERR_ECC1 +#define MRV_MIPI_RIS_ERR_ECC1_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_ECC1 */ +/* Slice: RIS_ERR_ECC2:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ERR_ECC2 +#define MRV_MIPI_RIS_ERR_ECC2_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_ECC2 */ +/* Slice: RIS_ERR_PROTOCOL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ERR_PROTOCOL +#define MRV_MIPI_RIS_ERR_PROTOCOL_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_PROTOCOL */ +/* Slice: RIS_ERR_CONTROL:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_RIS_ERR_CONTROL +#define MRV_MIPI_RIS_ERR_CONTROL_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_CONTROL */ +/* Slice: RIS_ERR_EOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_RIS_ERR_EOT_SYNC +#define MRV_MIPI_RIS_ERR_EOT_SYNC_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_EOT_SYNC */ +/* Slice: RIS_ERR_SOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_RIS_ERR_SOT_SYNC +#define MRV_MIPI_RIS_ERR_SOT_SYNC_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_SOT_SYNC */ +/* Slice: RIS_ERR_SOT:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_RIS_ERR_SOT +#define MRV_MIPI_RIS_ERR_SOT_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_SOT */ +/* Slice: RIS_SYNC_FIFO_OVFLW:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_RIS_SYNC_FIFO_OVFLW +#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK 0 +#endif /* MRV_MIPI_RIS_SYNC_FIFO_OVFLW */ +/* combination of all interrupt lines */ +#define MRV_MIPI_RIS_ALL_IRQS +#define MRV_MIPI_RIS_ALL_IRQS_MASK \ +(MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK \ + | MRV_MIPI_RIS_ADD_DATA_OVFLW_MASK \ + | MRV_MIPI_RIS_FRAME_END_MASK \ + | MRV_MIPI_RIS_ERR_CS_MASK \ + | MRV_MIPI_RIS_ERR_ECC1_MASK \ + | MRV_MIPI_RIS_ERR_ECC2_MASK \ + | MRV_MIPI_RIS_ERR_PROTOCOL_MASK \ + | MRV_MIPI_RIS_ERR_CONTROL_MASK \ + | MRV_MIPI_RIS_ERR_EOT_SYNC_MASK \ + | MRV_MIPI_RIS_ERR_SOT_SYNC_MASK \ + | MRV_MIPI_RIS_ERR_SOT_MASK \ + | MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK \ +) +#define MRV_MIPI_RIS_ALL_IRQS_SHIFT 0 +/*****************************************************************************/ +/** + * register: mipi_mis: Masked interrupt status (0x00000010) + * + *****************************************************************************/ +/* Slice: MIS_GEN_SHORT_PACK:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_GEN_SHORT_PACK +#define MRV_MIPI_MIS_GEN_SHORT_PACK_MASK 0 +#endif /* MRV_MIPI_MIS_GEN_SHORT_PACK */ +/* Slice: MIS_ADD_DATA_FILL_LEVEL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK 0 +#endif /* MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL */ +/* Slice: MIS_ADD_DATA_OVFLW:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ADD_DATA_OVFLW +#endif /* MRV_MIPI_MIS_ADD_DATA_OVFLW */ +/* Slice: MIS_FRAME_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_FRAME_END +#define MRV_MIPI_MIS_FRAME_END_MASK 0 +#endif /* MRV_MIPI_MIS_ADD_DATA_OVFLW */ +/* Slice: MIS_ERR_CS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ERR_CS +#define MRV_MIPI_MIS_ERR_CS_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_CS */ +/* Slice: MIS_ERR_ECC1:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ERR_ECC1 +#define MRV_MIPI_MIS_ERR_ECC1_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_ECC1 */ +/* Slice: MIS_ERR_ECC2:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ERR_ECC2 +#define MRV_MIPI_MIS_ERR_ECC2_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_ECC2 */ +/* Slice: MIS_ERR_PROTOCOL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ERR_PROTOCOL +#define MRV_MIPI_MIS_ERR_PROTOCOL_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_PROTOCOL */ +/* Slice: MIS_ERR_CONTROL:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_MIS_ERR_CONTROL +#define MRV_MIPI_MIS_ERR_CONTROL_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_CONTROL */ +/* Slice: MIS_ERR_EOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_MIS_ERR_EOT_SYNC +#define MRV_MIPI_MIS_ERR_EOT_SYNC_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_EOT_SYNC */ +/* Slice: MIS_ERR_SOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_MIS_ERR_SOT_SYNC +#define MRV_MIPI_MIS_ERR_SOT_SYNC_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_SOT_SYNC */ +/* Slice: MIS_ERR_SOT:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_MIS_ERR_SOT +#define MRV_MIPI_MIS_ERR_SOT_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_SOT */ +/* Slice: MIS_SYNC_FIFO_OVFLW:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_MIS_SYNC_FIFO_OVFLW +#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK 0 +#endif /* MRV_MIPI_MIS_SYNC_FIFO_OVFLW */ +/* combination of all interrupt lines */ +#define MRV_MIPI_MIS_ALL_IRQS +#define MRV_MIPI_MIS_ALL_IRQS_MASK \ +(MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK \ + | MRV_MIPI_MIS_ADD_DATA_OVFLW_MASK \ + | MRV_MIPI_MIS_FRAME_END_MASK \ + | MRV_MIPI_MIS_ERR_CS_MASK \ + | MRV_MIPI_MIS_ERR_ECC1_MASK \ + | MRV_MIPI_MIS_ERR_ECC2_MASK \ + | MRV_MIPI_MIS_ERR_PROTOCOL_MASK \ + | MRV_MIPI_MIS_ERR_CONTROL_MASK \ + | MRV_MIPI_MIS_ERR_EOT_SYNC_MASK \ + | MRV_MIPI_MIS_ERR_SOT_SYNC_MASK \ + | MRV_MIPI_MIS_ERR_SOT_MASK \ + | MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK \ +) +#define MRV_MIPI_MIS_ALL_IRQS_SHIFT 0 +/*****************************************************************************/ +/** + * register: mipi_icr: Interrupt clear register (0x00000014) + * + *****************************************************************************/ +/* Slice: ICR_GEN_SHORT_PACK:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_GEN_SHORT_PACK +#define MRV_MIPI_ICR_GEN_SHORT_PACK_MASK 0 +#endif /* MRV_MIPI_ICR_GEN_SHORT_PACK */ +/* Slice: ICR_ADD_DATA_FILL_LEVEL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK 0 +#endif /* MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL */ +/* Slice: ICR_ADD_DATA_OVFLW:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ADD_DATA_OVFLW +#endif /* MRV_MIPI_ICR_ADD_DATA_OVFLW */ +/* Slice: ICR_FRAME_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_FRAME_END +#define MRV_MIPI_ICR_FRAME_END_MASK 0 +#endif /* MRV_MIPI_ICR_ADD_DATA_OVFLW */ +/* Slice: ICR_ERR_CS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ERR_CS +#define MRV_MIPI_ICR_ERR_CS_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_CS */ +/* Slice: ICR_ERR_ECC1:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ERR_ECC1 +#define MRV_MIPI_ICR_ERR_ECC1_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_ECC1 */ +/* Slice: ICR_ERR_ECC2:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ERR_ECC2 +#define MRV_MIPI_ICR_ERR_ECC2_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_ECC2 */ +/* Slice: ICR_ERR_PROTOCOL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ERR_PROTOCOL +#define MRV_MIPI_ICR_ERR_PROTOCOL_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_PROTOCOL */ +/* Slice: ICR_ERR_CONTROL:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ICR_ERR_CONTROL +#define MRV_MIPI_ICR_ERR_CONTROL_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_CONTROL */ +/* Slice: ICR_ERR_EOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ICR_ERR_EOT_SYNC +#define MRV_MIPI_ICR_ERR_EOT_SYNC_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_EOT_SYNC */ +/* Slice: ICR_ERR_SOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ICR_ERR_SOT_SYNC +#define MRV_MIPI_ICR_ERR_SOT_SYNC_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_SOT_SYNC */ +/* Slice: ICR_ERR_SOT:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ICR_ERR_SOT +#define MRV_MIPI_ICR_ERR_SOT_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_SOT */ +/* Slice: ICR_SYNC_FIFO_OVFLW:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ICR_SYNC_FIFO_OVFLW +#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK 0 +#endif /* MRV_MIPI_ICR_SYNC_FIFO_OVFLW */ +/* combination of all interrupt lines */ +#define MRV_MIPI_ICR_ALL_IRQS +#define MRV_MIPI_ICR_ALL_IRQS_MASK \ +(MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK \ + | MRV_MIPI_ICR_ADD_DATA_OVFLW_MASK \ + | MRV_MIPI_ICR_FRAME_END_MASK \ + | MRV_MIPI_ICR_ERR_CS_MASK \ + | MRV_MIPI_ICR_ERR_ECC1_MASK \ + | MRV_MIPI_ICR_ERR_ECC2_MASK \ + | MRV_MIPI_ICR_ERR_PROTOCOL_MASK \ + | MRV_MIPI_ICR_ERR_CONTROL_MASK \ + | MRV_MIPI_ICR_ERR_EOT_SYNC_MASK \ + | MRV_MIPI_ICR_ERR_SOT_SYNC_MASK \ + | MRV_MIPI_ICR_ERR_SOT_MASK \ + | MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK \ +) +#define MRV_MIPI_ICR_ALL_IRQS_SHIFT 0 +/*****************************************************************************/ +/** + * register: mipi_isr: Interrupt set register (0x00000018) + * + *****************************************************************************/ +/* Slice: ISR_GEN_SHORT_PACK:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_GEN_SHORT_PACK +#define MRV_MIPI_ISR_GEN_SHORT_PACK_MASK 0 +#endif /* MRV_MIPI_ISR_GEN_SHORT_PACK */ +/* Slice: ISR_ADD_DATA_FILL_LEVEL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK 0 +#endif /* MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL */ +/* Slice: ISR_ADD_DATA_OVFLW:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ADD_DATA_OVFLW +#endif /* MRV_MIPI_ISR_ADD_DATA_OVFLW */ +/* Slice: ISR_FRAME_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_FRAME_END +#define MRV_MIPI_ISR_FRAME_END_MASK 0 +#endif /* MRV_MIPI_ISR_ADD_DATA_OVFLW */ +/* Slice: ISR_ERR_CS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ERR_CS +#define MRV_MIPI_ISR_ERR_CS_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_CS */ +/* Slice: ISR_ERR_ECC1:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ERR_ECC1 +#define MRV_MIPI_ISR_ERR_ECC1_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_ECC1 */ +/* Slice: ISR_ERR_ECC2:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ERR_ECC2 +#define MRV_MIPI_ISR_ERR_ECC2_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_ECC2 */ +/* Slice: ISR_ERR_PROTOCOL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ERR_PROTOCOL +#define MRV_MIPI_ISR_ERR_PROTOCOL_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_PROTOCOL */ +/* Slice: ISR_ERR_CONTROL:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ISR_ERR_CONTROL +#define MRV_MIPI_ISR_ERR_CONTROL_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_CONTROL */ +/* Slice: ISR_ERR_EOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ISR_ERR_EOT_SYNC +#define MRV_MIPI_ISR_ERR_EOT_SYNC_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_EOT_SYNC */ +/* Slice: ISR_ERR_SOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ISR_ERR_SOT_SYNC +#define MRV_MIPI_ISR_ERR_SOT_SYNC_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_SOT_SYNC */ +/* Slice: ISR_ERR_SOT:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ISR_ERR_SOT +#define MRV_MIPI_ISR_ERR_SOT_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_SOT */ +/* Slice: ISR_SYNC_FIFO_OVFLW:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ISR_SYNC_FIFO_OVFLW +#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK 0 +#endif /* MRV_MIPI_ISR_SYNC_FIFO_OVFLW */ +/* combination of all interrupt lines */ +#define MRV_MIPI_ISR_ALL_IRQS +#define MRV_MIPI_ISR_ALL_IRQS_MASK \ +(MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK \ + | MRV_MIPI_ISR_ADD_DATA_OVFLW_MASK \ + | MRV_MIPI_ISR_FRAME_END_MASK \ + | MRV_MIPI_ISR_ERR_CS_MASK \ + | MRV_MIPI_ISR_ERR_ECC1_MASK \ + | MRV_MIPI_ISR_ERR_ECC2_MASK \ + | MRV_MIPI_ISR_ERR_PROTOCOL_MASK \ + | MRV_MIPI_ISR_ERR_CONTROL_MASK \ + | MRV_MIPI_ISR_ERR_EOT_SYNC_MASK \ + | MRV_MIPI_ISR_ERR_SOT_SYNC_MASK \ + | MRV_MIPI_ISR_ERR_SOT_MASK \ + | MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK \ +) +#define MRV_MIPI_ISR_ALL_IRQS_SHIFT 0 +/*****************************************************************************/ +/** + * register: mipi_cur_data_id: Current Data Identifier (0x0000001c) + * + *****************************************************************************/ +/* Slice: VIRTUAL_CHANNEL:*/ +/* virtual channel of currently received packet */ +#ifdef MRV_MIPI_VIRTUAL_CHANNEL +#endif /* MRV_MIPI_VIRTUAL_CHANNEL */ +/* Slice: DATA_TYPE:*/ +/* data type of currently received packet */ +#ifdef MRV_MIPI_DATA_TYPE +#endif /* MRV_MIPI_DATA_TYPE */ +/*****************************************************************************/ +/** + * register: mipi_img_data_sel: Image Data Selector (0x00000020) + * + *****************************************************************************/ +/* Slice: VIRTUAL_CHANNEL_SEL:*/ +/* virtual channel selector for image data output */ +#ifdef MRV_MIPI_VIRTUAL_CHANNEL_SEL +#endif /* MRV_MIPI_VIRTUAL_CHANNEL_SEL */ +/* Slice: DATA_TYPE_SEL:*/ +/* data type selector for image data output:*/ +/* 0x08...0x0F: generic short packets */ +/* 0x12: embedded 8-bit data */ +/* 0x18: YUV 420 8-bit */ +/* 0x19: YUV 420 10-bit */ +/* 0x1A: Legacy YUV 420 8-bit */ +/* 0x1C: YUV 420 8-bit (CSPS)*/ +/* 0x1D: YUV 420 10-bit (CSPS)*/ +/* 0x1E: YUV 422 8-bit */ +/* 0x1F: YUV 422 10-bit */ +/* 0x20: RGB 444 */ +/* 0x21: RGB 555 */ +/* 0x22: RGB 565 */ +/* 0x23: RGB 666 */ +/* 0x24: RGB 888 */ +/* 0x28: RAW 6 */ +/* 0x29: RAW 7 */ +/* 0x2A: RAW 8 */ +/* 0x2B: RAW 10 */ +/* 0x2C: RAW 12 */ +/* 0x30...0x37: User Defined Byte-based data */ +#ifdef MRV_MIPI_DATA_TYPE_SEL +#define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT 24 /* 0x18 YUV 420 8-bit */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV420_10BIT 25 /* 0x19 YUV 420 10-bit */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT_LEGACY 26 /* 0x1A Legacy YUV 420 8-bit */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT_CSPS 28 /* 0x1C YUV 420 8-bit (CSPS) */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV420_10BIT_CSPS 29 /* 0x1D YUV 420 10-bit (CSPS) */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV422_8BIT 30 /* 0x1E YUV 422 8-bit */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV422_10BIT 31 /* 0x1F YUV 422 10-bit */ +#define MRV_MIPI_DATA_TYPE_SEL_RGB444 32 /* 0x20 RGB 444 */ +#define MRV_MIPI_DATA_TYPE_SEL_RGB555 33 /* 0x21 RGB 555 */ +#define MRV_MIPI_DATA_TYPE_SEL_RGB565 34 /* 0x22 RGB 565 */ +#define MRV_MIPI_DATA_TYPE_SEL_RGB666 35 /* 0x23 RGB 666 */ +#define MRV_MIPI_DATA_TYPE_SEL_RGB888 36 /* 0x24 RGB 888 */ +#define MRV_MIPI_DATA_TYPE_SEL_RAW6 40 /* 0x28 RAW 6 */ +#define MRV_MIPI_DATA_TYPE_SEL_RAW7 41 /* 0x29 RAW 7 */ +#define MRV_MIPI_DATA_TYPE_SEL_RAW8 42 /* 0x2A RAW 8 */ +#define MRV_MIPI_DATA_TYPE_SEL_RAW10 43 /* 0x2B RAW 10 */ +#define MRV_MIPI_DATA_TYPE_SEL_RAW12 44 /* 0x2C RAW 12 */ +#define MRV_MIPI_DATA_TYPE_SEL_USER1 48 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER2 49 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER3 50 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER4 51 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER5 52 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER6 53 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER7 54 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER8 55 /* 0x30...0x37 User Defined Byte-based data */ +#endif /* MRV_MIPI_DATA_TYPE_SEL */ +/*****************************************************************************/ +/** + * register: mipi_add_data_sel_1: Additional Data Selector 1 (0x00000024) + * + *****************************************************************************/ +/* Slice: ADD_DATA_VC_1:*/ +/* virtual channel selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_VC_1 +#endif /* MRV_MIPI_ADD_DATA_VC_1 */ +/* Slice: ADD_DATA_TYPE_1:*/ +/* data type selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_TYPE_1 +#endif /* MRV_MIPI_ADD_DATA_TYPE_1 */ +/*****************************************************************************/ +/** + * register: mipi_add_data_sel_2: Additional Data Selector 2 (0x00000028) + * + *****************************************************************************/ +/* Slice: ADD_DATA_VC_2:*/ +/* virtual channel selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_VC_2 +#endif /* MRV_MIPI_ADD_DATA_VC_2 */ +/* Slice: ADD_DATA_TYPE_2:*/ +/* data type selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_TYPE_2 +#endif /* MRV_MIPI_ADD_DATA_TYPE_2 */ +/*****************************************************************************/ +/** + * register: mipi_add_data_sel_3: Additional Data Selector 3 (0x0000002c) + * + *****************************************************************************/ +/* Slice: ADD_DATA_VC_3:*/ +/* virtual channel selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_VC_3 +#endif /* MRV_MIPI_ADD_DATA_VC_3 */ +/* Slice: ADD_DATA_TYPE_3:*/ +/* data type selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_TYPE_3 +#endif /* MRV_MIPI_ADD_DATA_TYPE_3 */ +/*****************************************************************************/ +/** + * register: mipi_add_data_sel_4: Additional Data Selector 4 (0x00000030) + * + *****************************************************************************/ +/* Slice: ADD_DATA_VC_4:*/ +/* virtual channel selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_VC_4 +#endif /* MRV_MIPI_ADD_DATA_VC_4 */ +/* Slice: ADD_DATA_TYPE_4:*/ +/* data type selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_TYPE_4 +#endif /* MRV_MIPI_ADD_DATA_TYPE_4 */ +/*****************************************************************************/ +/** + * register: mipi_add_data_fifo: Additional Data Fifo (0x00000034) + * + *****************************************************************************/ +/* Slice: ADD_DATA_FIFO:*/ +/* lowest 4 bytes in additional data fifo;*/ +/* reading increments fifo read pointer.*/ +/* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/ +#ifdef MRV_MIPI_ADD_DATA_FIFO +#endif /* MRV_MIPI_ADD_DATA_FIFO */ +/*****************************************************************************/ +/** + * register: mipi_add_data_fill_level: additional data fifo fill level + * (0x00000038) + * + *****************************************************************************/ +/* Slice: ADD_DATA_FILL_LEVEL:*/ +/* FIFO level in dwords for triggering the FILL_LEVEL interrupt,*/ +/* must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/ +#ifdef MRV_MIPI_ADD_DATA_FILL_LEVEL +#endif /* MRV_MIPI_ADD_DATA_FILL_LEVEL */ +/*****************************************************************************/ +/** + * register: mipi_compressed_mode: controls processing of compressed raw data + * types (0x0000003c) + * + *****************************************************************************/ +/* Slice: predictor_sel:*/ +/* predictor to be used:*/ +/* 0: predictor 1 */ +/* 1: predictor 2 */ +#ifdef MRV_MIPI_PREDICTOR_SEL +#define MRV_MIPI_PREDICTOR_SEL_1 0 /* 0: predictor 1 */ +#define MRV_MIPI_PREDICTOR_SEL_2 1 /* 1: predictor 2 */ +#endif /* MRV_MIPI_PREDICTOR_SEL */ +/* Slice: MRV_MIPI_COMP_SCHEME:*/ +/* Compressed raw data types */ +/* 000: 12-8-12 */ +/* 001: 12-8-12 */ +/* 010: 12-8-12 */ +/* 011: 10-8-10 */ +/* 100: 10-7-10 */ +/* 101: 10-6-10 */ +#ifdef MRV_MIPI_COMP_SCHEME +#define MRV_MIPI_COMP_SCHEME_12_8_12 0 /* 000: 12-8-12 */ +#define MRV_MIPI_COMP_SCHEME_12_7_12 1 /* 001: 12-8-12 */ +#define MRV_MIPI_COMP_SCHEME_12_6_12 2 /* 010: 12-8-12 */ +#define MRV_MIPI_COMP_SCHEME_10_8_10 3 /* 011: 10-8-10 */ +#define MRV_MIPI_COMP_SCHEME_10_7_10 4 /* 100: 10-7-10 */ +#define MRV_MIPI_COMP_SCHEME_10_6_10 5 /* 101: 10-6-10 */ +#endif /* MRV_MIPI_COMP_SCHEME */ +/* Slice: compress_en:*/ +/* 1: enable compressed mode processing */ +/* 0: disable compressed mode */ +#ifdef MRV_MIPI_COMPRESS_EN +#endif /* MRV_MIPI_COMPRESS_EN */ +/*****************************************************************************/ +/* ISP Image Stabilization Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_is_ctrl: Image Stabilization Control Register (0x00000000) + * + *****************************************************************************/ +/* Slice: is_en:*/ +/* 1: image stabilization switched on */ +/* 0: image stabilization switched off */ +#ifdef MRV_IS_IS_EN +#define MRV_IS_IS_EN_PROCESS 1 +#define MRV_IS_IS_EN_BYPASS 0 +#endif /* MRV_IS_IS_EN */ +/*****************************************************************************/ +/** + * register: isp_is_recenter: Recenter register (0x00000004) + * + *****************************************************************************/ +/* Slice: is_recenter:*/ +/* 000: recenter feature switched off */ +/* 1..7: recentering by (cur_h/v_offs-H/V_OFFS)/2^RECENTER */ +#ifdef MRV_IS_IS_RECENTER +#define MRV_IS_IS_RECENTER_MAX (MRV_IS_IS_RECENTER_MASK >> MRV_IS_IS_RECENTER_SHIFT) +#endif /* MRV_IS_IS_RECENTER */ +/*****************************************************************************/ +/** + * register: isp_is_h_offs: Horizontal offset of output window (0x00000008) + * + *****************************************************************************/ +/* Slice: is_h_offs:*/ +/* horizontal picture offset in pixel */ +#ifdef MRV_IS_IS_H_OFFS +#define MRV_IS_IS_H_OFFS_MAX (MRV_IS_IS_H_OFFS_MASK >> MRV_IS_IS_H_OFFS_SHIFT) +#endif /* MRV_IS_IS_H_OFFS */ +/*****************************************************************************/ +/** + * register: isp_is_v_offs: Vertical offset of output window (0x0000000c) + * + *****************************************************************************/ +/* Slice: is_v_offs:*/ +/* vertical picture offset in lines */ +#ifdef MRV_IS_IS_V_OFFS +#define MRV_IS_IS_V_OFFS_MAX (MRV_IS_IS_V_OFFS_MASK >> MRV_IS_IS_V_OFFS_SHIFT) +#endif /* MRV_IS_IS_V_OFFS */ +/*****************************************************************************/ +/** + * register: isp_is_h_size: Output horizontal picture size (0x00000010) + * + *****************************************************************************/ +/* Slice: is_h_size:*/ +/* horizontal picture size in pixel */ +/* if ISP_MODE is set to */ +/* 001-(ITU-R BT.656 YUV),*/ +/* 010-(ITU-R BT.601 YUV),*/ +/* 011-(ITU-R BT.601 Bayer RGB),*/ +/* 101-(ITU-R BT.656 Bayer RGB)*/ +/* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr)*/ +/* are needed for the following modules. If an odd size is programmed the value */ +/* will be truncated to even size.*/ +#ifdef MRV_IS_IS_H_SIZE +#define MRV_IS_IS_H_SIZE_MAX (MRV_IS_IS_H_SIZE_MASK >> MRV_IS_IS_H_SIZE_SHIFT) +#endif /* MRV_IS_IS_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_is_v_size: Output vertical picture size (0x00000014) + * + *****************************************************************************/ +/* Slice: is_v_size:*/ +/* vertical picture size in lines */ +#ifdef MRV_IS_IS_V_SIZE +#define MRV_IS_IS_V_SIZE_MAX (MRV_IS_IS_V_SIZE_MASK >> MRV_IS_IS_V_SIZE_SHIFT) +#endif /* MRV_IS_IS_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_is_max_dx: Maximum Horizontal Displacement (0x00000018) + * + *****************************************************************************/ +/* Slice: is_max_dx:*/ +/* maximum allowed accumulated horizontal displacement in pixels */ +#ifdef MRV_IS_IS_MAX_DX +#define MRV_IS_IS_MAX_DX_MAX (MRV_IS_IS_MAX_DX_MASK >> MRV_IS_IS_MAX_DX_SHIFT) +#endif /* MRV_IS_IS_MAX_DX */ +/*****************************************************************************/ +/** + * register: isp_is_max_dy: Maximum Vertical Displacement (0x0000001c) + * + *****************************************************************************/ +/* Slice: is_max_dy:*/ +/* maximum allowed accumulated vertical displacement in lines */ +#ifdef MRV_IS_IS_MAX_DY +#define MRV_IS_IS_MAX_DY_MAX (MRV_IS_IS_MAX_DY_MASK >> MRV_IS_IS_MAX_DY_SHIFT) +#endif /* MRV_IS_IS_MAX_DY */ +/*****************************************************************************/ +/** + * register: isp_is_displace: Camera displacement (0x00000020) + * + *****************************************************************************/ +/* Slice: dy:*/ +/* ISP_IS will compensate for vertical camera displacement of DY lines in the next frame */ +#ifdef MRV_IS_DY +#define MRV_IS_DY_MAX 0x000007FF +#define MRV_IS_DY_MIN (~MRV_IS_DY_MAX) +#endif /* MRV_IS_DY */ +/* Slice: dx:*/ +/* ISP_IS will compensate for horizontal camera displacement of DX pixels in the next frame */ +#ifdef MRV_IS_DX +#define MRV_IS_DX_MAX 0x000007FF +#define MRV_IS_DX_MIN (~MRV_IS_DX_MAX) +#endif /* MRV_IS_DX */ +/*****************************************************************************/ +/** + * register: isp_is_h_offs_shd: current horizontal offset of output window + * (shadow register) (0x00000024) + * + *****************************************************************************/ +/* Slice: is_h_offs_shd:*/ +/* current horizonatl picture offset in lines */ +#ifdef MRV_IS_IS_H_OFFS_SHD +#endif /* MRV_IS_IS_H_OFFS_SHD */ +/*****************************************************************************/ +/** + * register: isp_is_v_offs_shd: current vertical offset of output window + * (shadow register) (0x00000028) + * + *****************************************************************************/ +/* Slice: is_v_offs_shd:*/ +/* current vertical picture offset in lines */ +#ifdef MRV_IS_IS_V_OFFS_SHD +#endif /* MRV_IS_IS_V_OFFS_SHD */ +/*****************************************************************************/ +/** + * register: isp_is_h_size_shd: current output horizontal picture size + * (shadow register) (0x0000002c) + * + *****************************************************************************/ +/* Slice: isp_h_size_shd:*/ +/* current horizontal picture size in pixel */ +#ifdef MRV_IS_ISP_H_SIZE_SHD +#endif /* MRV_IS_ISP_H_SIZE_SHD */ +/*****************************************************************************/ +/** + * register: isp_is_v_size_shd: current output vertical picture size + * (shadow register) (0x00000030) + * + *****************************************************************************/ +/* Slice: isp_v_size_shd:*/ +/* vertical picture size in lines */ +#ifdef MRV_IS_ISP_V_SIZE_SHD +#endif /* MRV_IS_ISP_V_SIZE_SHD */ +/*****************************************************************************/ +/* ISP Histogram Module Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_hist_prop: Histogram properties (0x00000000) + * + *****************************************************************************/ +/* Slice: stepsize:*/ +/* histogram predivider, process every (stepsize)th pixel, all other pixels are skipped */ +/* 0,1,2: not allowed */ +/* 3: process every third input pixel */ +/* 4: process every fourth input pixel */ +/* ...*/ +/* 7FH: process every 127th pixel */ +#ifdef MRV_HIST_STEPSIZE +#define MRV_HIST_STEPSIZE_MIN 0x00000003 +#define MRV_HIST_STEPSIZE_MAX 0x0000007F +#endif /* MRV_HIST_STEPSIZE */ +/* Slice: hist_mode:*/ +/* histogram mode, luminance is taken at ISP output before output formatter,*/ +/* RGB is taken at xtalk output */ + /**/ +/* 7, 6: must not be used */ +/* 5: Y (luminance) histogram */ +/* 4: B histogram */ +/* 3: G histogram */ +/* 2: R histogram */ +/* 1: RGB combined histogram */ +/* 0: disable, no measurements */ +#ifdef MRV_HIST_MODE +#define MRV_HIST_MODE_MAX 5 /* because 6 and 7 are reserved */ +#define MRV_HIST_MODE_LUM 5 /* 5: Y (luminance) histogram */ +#define MRV_HIST_MODE_B 4 /* 4: B histogram */ +#define MRV_HIST_MODE_G 3 /* 3: G histogram */ +#define MRV_HIST_MODE_R 2 /* 2: R histogram */ +#define MRV_HIST_MODE_RGB 1 /* 1: RGB combined histogram */ +#define MRV_HIST_MODE_NONE 0 /* 0: disable, no measurements */ +#endif /* MRV_HIST_MODE */ +/*****************************************************************************/ +/** + * register: isp_hist_h_offs: Histogram window horizontal offset for first + * window of 25 sub-windows (0x00000004) + * + *****************************************************************************/ +/* Slice: hist_h_offset:*/ +/* Horizontal offset of first window in pixels.*/ +#ifdef MRV_HIST_H_OFFSET +#endif /* MRV_HIST_H_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_hist_v_offs: Histogram window vertical offset for first + * window of 25 sub-windows (0x00000008) + * + *****************************************************************************/ +/* Slice: hist_v_offset:*/ +/* Vertical offset of first window in pixels.*/ +#ifdef MRV_HIST_V_OFFSET +#endif /* MRV_HIST_V_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_hist_h_size: Horizontal (sub-)window size (0x0000000c) + * + *****************************************************************************/ +/* Slice: hist_h_size:*/ +/* Horizontal size in pixels of one sub-window, if histogram version 3 is implemented.*/ +#ifdef MRV_HIST_H_SIZE +#endif /* MRV_HIST_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_hist_v_size: Vertical (sub-)window size (0x00000010) + * + *****************************************************************************/ +/* Slice: hist_v_size:*/ +/* Vertical size in lines of one sub-window, if histogram version 3 is implemented.*/ +#ifdef MRV_HIST_V_SIZE +#endif /* MRV_HIST_V_SIZE */ +/*****************************************************************************/ +/** + * register array: isp_hist_bin: histogram measurement result bin + * (0x028 + n*0x4 (n=0..15)) + * + *****************************************************************************/ +/* Slice: hist_bin_n:*/ +/* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */ +#ifdef MRV_HIST_BIN_N +#define MRV_HIST_BIN_N_MAX (MRV_HIST_BIN_N_MASK >> MRV_HIST_BIN_N_SHIFT) +#endif /* MRV_HIST_BIN_N */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_00to30: Weighting factor for sub-windows + * (0x00000054) + * + *****************************************************************************/ +/* Slice: hist_weight_30:*/ +/* weighting factor for sub-window 30 */ +#ifdef MRV_HIST_WEIGHT_30 +#endif /* MRV_HIST_WEIGHT_30 */ +/* Slice: hist_weight_20:*/ +/* weighting factor for sub-window 20 */ +#ifdef MRV_HIST_WEIGHT_20 +#endif /* MRV_HIST_WEIGHT_20 */ +/* Slice: hist_weight_10:*/ +/* weighting factor for sub-window 10 */ +#ifdef MRV_HIST_WEIGHT_10 +#endif /* MRV_HIST_WEIGHT_10 */ +/* Slice: hist_weight_00:*/ +/* weighting factor for sub-window 00 */ +#ifdef MRV_HIST_WEIGHT_00 +#endif /* MRV_HIST_WEIGHT_00 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_40to21: Weighting factor for sub-windows + * (0x00000058) + * + *****************************************************************************/ +/* Slice: hist_weight_21:*/ +/* weighting factor for sub-window 21 */ +#ifdef MRV_HIST_WEIGHT_21 +#endif /* MRV_HIST_WEIGHT_21 */ +/* Slice: hist_weight_11:*/ +/* weighting factor for sub-window 11 */ +#ifdef MRV_HIST_WEIGHT_11 +#endif /* MRV_HIST_WEIGHT_11 */ +/* Slice: hist_weight_01:*/ +/* weighting factor for sub-window 01 */ +#ifdef MRV_HIST_WEIGHT_01 +#endif /* MRV_HIST_WEIGHT_01 */ +/* Slice: hist_weight_40:*/ +/* weighting factor for sub-window 40 */ +#ifdef MRV_HIST_WEIGHT_40 +#endif /* MRV_HIST_WEIGHT_40 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_31to12: Weighting factor for sub-windows + * (0x0000005c) + * + *****************************************************************************/ +/* Slice: hist_weight_12:*/ +/* weighting factor for sub-window 12 */ +#ifdef MRV_HIST_WEIGHT_12 +#endif /* MRV_HIST_WEIGHT_12 */ +/* Slice: hist_weight_02:*/ +/* weighting factor for sub-window 02 */ +#ifdef MRV_HIST_WEIGHT_02 +#endif /* MRV_HIST_WEIGHT_02 */ +/* Slice: hist_weight_41:*/ +/* weighting factor for sub-window 41 */ +#ifdef MRV_HIST_WEIGHT_41 +#endif /* MRV_HIST_WEIGHT_41 */ +/* Slice: hist_weight_31:*/ +/* weighting factor for sub-window 31 */ +#ifdef MRV_HIST_WEIGHT_31 +#endif /* MRV_HIST_WEIGHT_31 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_22to03: Weighting factor for sub-windows + * (0x00000060) + * + *****************************************************************************/ +/* Slice: hist_weight_03:*/ +/* weighting factor for sub-window 03 */ +#ifdef MRV_HIST_WEIGHT_03 +#endif /* MRV_HIST_WEIGHT_03 */ +/* Slice: hist_weight_42:*/ +/* weighting factor for sub-window 42 */ +#ifdef MRV_HIST_WEIGHT_42 +#endif /* MRV_HIST_WEIGHT_42 */ +/* Slice: hist_weight_32:*/ +/* weighting factor for sub-window 32 */ +#ifdef MRV_HIST_WEIGHT_32 +#endif /* MRV_HIST_WEIGHT_32 */ +/* Slice: hist_weight_22:*/ +/* weighting factor for sub-window 22 */ +#ifdef MRV_HIST_WEIGHT_22 +#endif /* MRV_HIST_WEIGHT_22 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_13to43: Weighting factor for sub-windows + * (0x00000064) + * + *****************************************************************************/ +/* Slice: hist_weight_43:*/ +/* weighting factor for sub-window 43 */ +#ifdef MRV_HIST_WEIGHT_43 +#endif /* MRV_HIST_WEIGHT_43 */ +/* Slice: hist_weight_33:*/ +/* weighting factor for sub-window 33 */ +#ifdef MRV_HIST_WEIGHT_33 +#endif /* MRV_HIST_WEIGHT_33 */ +/* Slice: hist_weight_23:*/ +/* weighting factor for sub-window 23 */ +#ifdef MRV_HIST_WEIGHT_23 +#endif /* MRV_HIST_WEIGHT_23 */ +/* Slice: hist_weight_13:*/ +/* weighting factor for sub-window 13 */ +#ifdef MRV_HIST_WEIGHT_13 +#endif /* MRV_HIST_WEIGHT_13 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_04to34: Weighting factor for sub-windows + * (0x00000068) + * + *****************************************************************************/ +/* Slice: hist_weight_34:*/ +/* weighting factor for sub-window 34 */ +#ifdef MRV_HIST_WEIGHT_34 +#endif /* MRV_HIST_WEIGHT_34 */ +/* Slice: hist_weight_24:*/ +/* weighting factor for sub-window 24 */ +#ifdef MRV_HIST_WEIGHT_24 +#endif /* MRV_HIST_WEIGHT_24 */ +/* Slice: hist_weight_14:*/ +/* weighting factor for sub-window 14 */ +#ifdef MRV_HIST_WEIGHT_14 +#endif /* MRV_HIST_WEIGHT_14 */ +/* Slice: hist_weight_04:*/ +/* weighting factor for sub-window 04 */ +#ifdef MRV_HIST_WEIGHT_04 +#endif /* MRV_HIST_WEIGHT_04 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_44: Weighting factor for sub-windows (0x0000006c) + * + *****************************************************************************/ +/* Slice: hist_weight_44:*/ +/* weighting factor for sub-window 44 */ +#ifdef MRV_HIST_WEIGHT_44 +#endif /* MRV_HIST_WEIGHT_44 */ +#define MRV_HIST_WEIGHT_MAX 0x10 +/*****************************************************************************/ +/* ISP Filter Module Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_filt_mode: mode control register for the filter block + * (0x00000000) + * + *****************************************************************************/ +/* Slice: stage1_select:*/ +/* Green filter stage 1 select (range 0x0...0x8)*/ +/* 0x0 maximum blurring */ +/* 0x4 Default */ +/* 0x7 minimum blurring */ +/* 0x8 filter stage1 bypass */ +/* For a detailed description refer to chapter "ISP Filter Programming" of user manual */ +#ifdef MRV_FILT_STAGE1_SELECT +#define MRV_FILT_STAGE1_SELECT_MAX_BLUR 0U /* 0x0 maximum blurring */ +#define MRV_FILT_STAGE1_SELECT_DEFAULT 4U /* 0x4 Default */ +#define MRV_FILT_STAGE1_SELECT_MIN_BLUR 7U /* 0x7 minimum blurring */ +#define MRV_FILT_STAGE1_SELECT_BYPASS 8U /* 0x8 filter stage1 bypass */ +#endif /* MRV_FILT_STAGE1_SELECT */ +/* Slice: filt_chr_h_mode:*/ +/* Chroma filter horizontal mode */ +/* 00 horizontal chroma filter bypass */ +/* 01 horizontal chroma filter 1 static mask = [10 12 10]*/ +/* 10 horizontal chroma filter 2 (dynamic blur1)*/ +/* 11 horizontal chroma filter 3 (dynamic blur2) Default */ +#ifdef MRV_FILT_FILT_CHR_H_MODE +#define MRV_FILT_FILT_CHR_H_MODE_BYPASS 0U /* 00 horizontal chroma filter bypass */ +#define MRV_FILT_FILT_CHR_H_MODE_STATIC 1U /* 01 horizontal chroma filter 1 static mask = [10 12 10] */ +#define MRV_FILT_FILT_CHR_H_MODE_DYN_1 2U /* 10 horizontal chroma filter 2 (dynamic blur1) */ +#define MRV_FILT_FILT_CHR_H_MODE_DYN_2 3U /* 11 horizontal chroma filter 3 (dynamic blur2) Default */ +#endif /* MRV_FILT_FILT_CHR_H_MODE */ +/* Slice: filt_chr_v_mode:*/ +/* Chroma filter vertical mode */ +/* 00 vertical chroma filter bypass */ +/* 01 vertical chroma filter 1 static [8 16 8]*/ +/* 10 vertical chroma filter 2 static [10 12 10]*/ +/* 11 vertical chroma filter 3 static [12 8 12] Default */ +#ifdef MRV_FILT_FILT_CHR_V_MODE +#define MRV_FILT_FILT_CHR_V_MODE_BYPASS 0U /* 00 vertical chroma filter bypass */ +#define MRV_FILT_FILT_CHR_V_MODE_STATIC8 1U /* 01 vertical chroma filter 1 static [8 16 8] */ +#define MRV_FILT_FILT_CHR_V_MODE_STATIC10 2U /* 10 vertical chroma filter 2 static [10 12 10] */ +#define MRV_FILT_FILT_CHR_V_MODE_STATIC12 3U /* 11 vertical chroma filter 3 static [12 8 12] Default */ +#endif /* MRV_FILT_FILT_CHR_V_MODE */ +/* Slice: filt_mode:*/ +/* 0 green filter static mode (active filter factor = FILT_FAC_MID)*/ +/* 1 dynamic noise reduction/sharpen Default */ +#ifdef MRV_FILT_FILT_MODE +#define MRV_FILT_FILT_MODE_STATIC 0U /* 0 green filter static mode (active filter factor = FILT_FAC_MID) */ +#define MRV_FILT_FILT_MODE_DYNAMIC 1U /* 1 dynamic noise reduction/sharpen Default */ +#endif /* MRV_FILT_FILT_MODE */ +/* Slice: filt_enable:*/ +/* 1 enable filter */ +/* 0 bypass filter Default */ +#ifdef MRV_FILT_FILT_ENABLE +#define MRV_FILT_FILT_ENABLE_PROCESS 1U +#define MRV_FILT_FILT_ENABLE_BYPASS 0U +#endif /* MRV_FILT_FILT_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_filt_thresh_bl0: Blurring threshold 0 (0x00000028) + * + *****************************************************************************/ +/* Slice: filt_thresh_bl0:*/ +/* If filt_thresh_bl1 < sum_grad < filt_thresh_bl0 then filt_fac_bl0 is selected */ +#ifdef MRV_FILT_FILT_THRESH_BL0 +#endif /* MRV_FILT_FILT_THRESH_BL0 */ +/*****************************************************************************/ +/** + * register: isp_filt_thresh_bl1: Blurring threshold 1 (0x0000002c) + * + *****************************************************************************/ +/* Slice: filt_thresh_bl1:*/ +/* If sum_grad < filt_thresh_bl1 then filt_fac_bl1 is selected */ +#ifdef MRV_FILT_FILT_THRESH_BL1 +#endif /* MRV_FILT_FILT_THRESH_BL1 */ +/*****************************************************************************/ +/** + * register: isp_filt_thresh_sh0: Sharpening threshold 0 (0x00000030) + * + *****************************************************************************/ +/* Slice: filt_thresh_sh0:*/ +/* If filt_thresh_sh0 < sum_grad < filt_thresh_sh1 then filt_thresh_sh0 is selected */ +#ifdef MRV_FILT_FILT_THRESH_SH0 +#endif /* MRV_FILT_FILT_THRESH_SH0 */ +/*****************************************************************************/ +/** + * register: isp_filt_thresh_sh1: Sharpening threshold 1 (0x00000034) + * + *****************************************************************************/ +/* Slice: filt_thresh_sh1:*/ +/* If filt_thresh_sh1 < sum_grad then filt_thresh_sh1 is selected */ +#ifdef MRV_FILT_FILT_THRESH_SH1 +#endif /* MRV_FILT_FILT_THRESH_SH1 */ +/*****************************************************************************/ +/** + * register: isp_filt_lum_weight: Parameters for luminance weight function + * (0x00000038) + * + *****************************************************************************/ +/* Slice: lum_weight_gain:*/ +/* Gain select of luminance weight function */ +#ifdef MRV_FILT_LUM_WEIGHT_GAIN +#endif /* MRV_FILT_LUM_WEIGHT_GAIN */ +/* Slice: lum_weight_kink:*/ +/* Kink position of luminance weight function */ +#ifdef MRV_FILT_LUM_WEIGHT_KINK +#endif /* MRV_FILT_LUM_WEIGHT_KINK */ +/* Slice: lum_weight_min:*/ +/* Minimum value of luminance weight function */ +#ifdef MRV_FILT_LUM_WEIGHT_MIN +#endif /* MRV_FILT_LUM_WEIGHT_MIN */ +/*****************************************************************************/ +/** + * register: isp_filt_fac_sh1: filter factor sharp1 (0x0000003c) + * + *****************************************************************************/ +/* Slice: filt_fac_sh1:*/ +/* Filter factor for sharp1 level */ +#ifdef MRV_FILT_FILT_FAC_SH1 +#endif /* MRV_FILT_FILT_FAC_SH1 */ +/*****************************************************************************/ +/** + * register: isp_filt_fac_sh0: filter factor sharp0 (0x00000040) + * + *****************************************************************************/ +/* Slice: filt_fac_sh0:*/ +/* Filter factor for sharp0 level */ +#ifdef MRV_FILT_FILT_FAC_SH0 +#endif /* MRV_FILT_FILT_FAC_SH0 */ +/*****************************************************************************/ +/** + * register: isp_filt_fac_mid: filter factor middle (0x00000044) + * + *****************************************************************************/ +/* Slice: filt_fac_mid:*/ +/* Filter factor for mid level and for static filter mode */ +#ifdef MRV_FILT_FILT_FAC_MID +#endif /* MRV_FILT_FILT_FAC_MID */ +/*****************************************************************************/ +/** + * register: isp_filt_fac_bl0: Parameter for blur 0 filter (0x00000048) + * + *****************************************************************************/ +/* Slice: filt_fac_bl0:*/ +/* Filter factor for blur 0 level */ +#ifdef MRV_FILT_FILT_FAC_BL0 +#endif /* MRV_FILT_FILT_FAC_BL0 */ +/*****************************************************************************/ +/** + * register: isp_filt_fac_bl1: Parameter for blur 1 filter (0x0000004c) + * + *****************************************************************************/ +/* Slice: filt_fac_bl1:*/ +/* Filter factor for blur 1 level (max blur)*/ +#ifdef MRV_FILT_FILT_FAC_BL1 +#endif /* MRV_FILT_FILT_FAC_BL1 */ +/*****************************************************************************/ +/* ISP Auto Focus Measurement Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_afm_ctrl: This is the control register for AF measurement + * unit (0x00000000) + * + *****************************************************************************/ +/* Slice: afm_en:*/ +/* AF measurement enable */ +/* 0: AF measurement is disabled */ +/* 1: AF measurement is enabled */ +/* Writing a 1 to this register starts a new measurement and resets the afm_fin (measurement finished) interrupt to 0.*/ +/* As long as the afm_en is 1, the AFM unit calculates new sharpness values for each frame.*/ +#ifdef MRV_AFM_AFM_EN +#define MRV_AFM_AFM_EN_ENABLE 1 /* 1: enable AF measurment */ +#define MRV_AFM_AFM_EN_DISABLE 0 /* 0: processing is deactivated, bypass mode is selected */ +#endif /* MRV_AFM_AFM_EN */ +/*****************************************************************************/ +/** + * register: isp_afm_lt_a: Top Left corner of measure window A (0x00000004) + * + *****************************************************************************/ +/* Slice: a_h_l:*/ +/* first pixel of window A (horizontal left row), value must be greater or equal 5 */ +#ifdef MRV_AFM_A_H_L +#define MRV_AFM_A_H_L_MIN (5U) +#define MRV_AFM_A_H_L_MAX (MRV_AFM_A_H_L_MASK >> MRV_AFM_A_H_L_SHIFT) +#endif /* MRV_AFM_A_H_L */ +/* Slice: a_v_t:*/ +/* first line of window A (vertical top line), value must be greater or equal 2 */ +#ifdef MRV_AFM_A_V_T +#define MRV_AFM_A_V_T_MIN (2U) +#define MRV_AFM_A_V_T_MAX (MRV_AFM_A_V_T_MASK >> MRV_AFM_A_V_T_SHIFT) +#endif /* MRV_AFM_A_V_T */ +/*****************************************************************************/ +/** + * register: isp_afm_rb_a: Bottom right corner of measure window A (0x00000008) + * + *****************************************************************************/ +/* Slice: a_h_r:*/ +/* last pixel of window A (horizontal right row)*/ +#ifdef MRV_AFM_A_H_R +#define MRV_AFM_A_H_R_MIN (5U) +#define MRV_AFM_A_H_R_MAX (MRV_AFM_A_H_R_MASK >> MRV_AFM_A_H_R_SHIFT) +#endif /* MRV_AFM_A_H_R */ +/* Slice: a_v_b:*/ +/* last line of window A (vertical bottom line), value must be lower than */ +/* (number of lines -2)*/ +#ifdef MRV_AFM_A_V_B +#define MRV_AFM_A_V_B_MIN (2U) +#define MRV_AFM_A_V_B_MAX (MRV_AFM_A_V_B_MASK >> MRV_AFM_A_V_B_SHIFT) +#endif /* MRV_AFM_A_V_B */ +/*****************************************************************************/ +/** + * register: isp_afm_lt_b: Top left corner of measure window B (0x0000000c) + * + *****************************************************************************/ +/* Slice: b_h_l:*/ +/* first pixel of window B (horizontal left row), value must be greater or equal 5 */ +#ifdef MRV_AFM_B_H_L +#define MRV_AFM_B_H_L_MIN (5U) +#define MRV_AFM_B_H_L_MAX (MRV_AFM_B_H_L_MASK >> MRV_AFM_B_H_L_SHIFT) +#endif /* MRV_AFM_B_H_L */ +/* Slice: b_v_t:*/ +/* first line of window B (vertical top line), value must be greater or equal 2 */ +#ifdef MRV_AFM_B_V_T +#define MRV_AFM_B_V_T_MIN (2U) +#define MRV_AFM_B_V_T_MAX (MRV_AFM_B_V_T_MASK >> MRV_AFM_B_V_T_SHIFT) +#endif /* MRV_AFM_B_V_T */ +/*****************************************************************************/ +/** + * register: isp_afm_rb_b: Bottom right corner of measure window B (0x00000010) + * + *****************************************************************************/ +/* Slice: b_h_r:*/ +/* last pixel of window B (horizontal right row)*/ +#ifdef MRV_AFM_B_H_R +#define MRV_AFM_B_H_R_MIN (5U) +#define MRV_AFM_B_H_R_MAX (MRV_AFM_B_H_R_MASK >> MRV_AFM_B_H_R_SHIFT) +#endif /* MRV_AFM_B_H_R */ +/* Slice: b_v_b:*/ +/* last line of window B (vertical bottom line), value must be lower than */ +/* (number of lines -2)*/ +#ifdef MRV_AFM_B_V_B +#define MRV_AFM_B_V_B_MIN (2U) +#define MRV_AFM_B_V_B_MAX (MRV_AFM_B_V_B_MASK >> MRV_AFM_B_V_B_SHIFT) +#endif /* MRV_AFM_B_V_B */ +/*****************************************************************************/ +/** + * register: isp_afm_lt_c: Top left corner of measure window C (0x00000014) + * + *****************************************************************************/ +/* Slice: c_h_l:*/ +/* first pixel of window C (horizontal left row), value must be greater or equal 5 */ +#ifdef MRV_AFM_C_H_L +#define MRV_AFM_C_H_L_MIN (5U) +#define MRV_AFM_C_H_L_MAX (MRV_AFM_C_H_L_MASK >> MRV_AFM_C_H_L_SHIFT) +#endif /* MRV_AFM_C_H_L */ +/* Slice: c_v_t:*/ +/* first line of window C (vertical top line), value must be greater or equal 2 */ +#ifdef MRV_AFM_C_V_T +#define MRV_AFM_C_V_T_MIN (2U) +#define MRV_AFM_C_V_T_MAX (MRV_AFM_C_V_T_MASK >> MRV_AFM_C_V_T_SHIFT) +#endif /* MRV_AFM_C_V_T */ +/*****************************************************************************/ +/** + * register: isp_afm_rb_c: Bottom right corner of measure window C (0x00000018) + * + *****************************************************************************/ +/* Slice: c_h_r:*/ +/* last pixel of window C (horizontal right row)*/ +#ifdef MRV_AFM_C_H_R +#define MRV_AFM_C_H_R_MIN (5U) +#define MRV_AFM_C_H_R_MAX (MRV_AFM_C_H_R_MASK >> MRV_AFM_C_H_R_SHIFT) +#endif /* MRV_AFM_C_H_R */ +/* Slice: c_v_b:*/ +/* last line of window C (vertical bottom line), value must be lower than */ +/* (number of lines -2)*/ +#ifdef MRV_AFM_C_V_B +#define MRV_AFM_C_V_B_MIN (2U) +#define MRV_AFM_C_V_B_MAX (MRV_AFM_C_V_B_MASK >> MRV_AFM_C_V_B_SHIFT) +#endif /* MRV_AFM_C_V_B */ +/*****************************************************************************/ +/** + * register: isp_afm_thres: Threshold register (0x0000001c) + * + *****************************************************************************/ +/* Slice: afm_thres:*/ +/* AF measurement threshold */ +/* This register defines a threshold which can be used for minimizing the */ +/* influence of noise in the measurement result.*/ +#ifdef MRV_AFM_AFM_THRES +#endif /* MRV_AFM_AFM_THRES */ +/*****************************************************************************/ +/** + * register: isp_afm_var_shift: Variable shift register (0x00000020) + * + *****************************************************************************/ +/* Slice: lum_var_shift:*/ +/* variable shift for luminance summation */ +/* The lum_var_shift defines the number of bits for the shift operation of the */ +/* value of the current pixel before summation. The shift operation is used to */ +/* avoid a luminance sum overflow.*/ +#ifdef MRV_AFM_LUM_VAR_SHIFT +#endif /* MRV_AFM_LUM_VAR_SHIFT */ +/* Slice: afm_var_shift:*/ +/* variable shift for AF measurement */ +/* The afm_var_shift defines the number of bits for the shift operation at the */ +/* end of the calculation chain. The shift operation is used to avoid an AF */ +/* measurement sum overflow.*/ +#ifdef MRV_AFM_AFM_VAR_SHIFT +#endif /* MRV_AFM_AFM_VAR_SHIFT */ +/*****************************************************************************/ +/** + * register: isp_afm_sum_a: Sharpness Value Status Register of Window A (0x0024) + * + *****************************************************************************/ +/* Slice: afm_sum_a:*/ +/* sharpness value of window A */ +#ifdef MRV_AFM_AFM_SUM_A +#endif /* MRV_AFM_AFM_SUM_A */ +/*****************************************************************************/ +/** + * register: isp_afm_sum_b: Sharpness Value Status Register of Window B (0x0028) + * + *****************************************************************************/ +/* Slice: afm_sum_b:*/ +/* sharpness value of window B */ +#ifdef MRV_AFM_AFM_SUM_B +#endif /* MRV_AFM_AFM_SUM_B */ +/*****************************************************************************/ +/** + * register: isp_afm_sum_c: Sharpness Value Status Register of Window C (0x002c) + * + *****************************************************************************/ +/* Slice: afm_sum_c:*/ +/* sharpness value of window C */ +#ifdef MRV_AFM_AFM_SUM_C +#endif /* MRV_AFM_AFM_SUM_C */ +/*****************************************************************************/ +/** + * register: isp_afm_lum_a: Luminance Value Status Register of Window A (0x0030) + * + *****************************************************************************/ +/* Slice: afm_lum_a:*/ +/* luminance value of window A */ +#ifdef MRV_AFM_AFM_LUM_A +#endif /* MRV_AFM_AFM_LUM_A */ +/*****************************************************************************/ +/** + * register: isp_afm_lum_b: Luminance Value Status Register of Window B (0x0034) + * + *****************************************************************************/ +/* Slice: afm_lum_b:*/ +/* luminance value of window B */ +#ifdef MRV_AFM_AFM_LUM_B +#endif /* MRV_AFM_AFM_LUM_B */ +/*****************************************************************************/ +/** + * register: isp_afm_lum_c: Luminance Value Status Register of Window C (0x0038) + * + *****************************************************************************/ +/* Slice: afm_lum_c:*/ +/* luminance value of window C */ +#ifdef MRV_AFM_AFM_LUM_C +#endif /* MRV_AFM_AFM_LUM_C */ +/*****************************************************************************/ +/* ISP Lens Shade Correction Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_lsc_ctrl: Lens shade control (0x00000000) + * + *****************************************************************************/ +/* Slice: lsc_en:*/ +/* 0: activation request for lens shading correction */ +/* 1: deactivation reqeust for lens shading correction */ +/* Activation/Deactivation is object of a shadowing mechnism. The current */ +/* status is visible at ISP_LSC_STATUS::lsc_enable_status */ +#ifdef MRV_LSC_LSC_EN +#define MRV_LSC_LSC_EN_ENABLE 1U +#define MRV_LSC_LSC_EN_DISABLE 0U +#endif /* MRV_LSC_LSC_EN */ +/*****************************************************************************/ +/** + * register: isp_lsc_r_table_addr: Table RAM Address for red component (0x00000004) + * + *****************************************************************************/ +/* Slice: r_ram_addr:*/ +/* table address in RAM for samples of the R color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +/* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */ +/* (if available).*/ +#ifdef MRV_LSC_R_RAM_ADDR +#define MRV_LSC_R_RAM_ADDR_MIN_BANK0 (0x00000000U) +#define MRV_LSC_R_RAM_ADDR_MAX_BANK0 (0x00000098U) +#define MRV_LSC_R_RAM_ADDR_MIN_BANK1 (0x00000099U) +#define MRV_LSC_R_RAM_ADDR_MAX_BANK1 (0x00000132U) +#endif /* MRV_LSC_R_RAM_ADDR */ +/*****************************************************************************/ +/** + * register: isp_lsc_gr_table_addr: Table RAM Address for green (red) component + * (0x00000008) + * + *****************************************************************************/ +/* Slice: gr_ram_addr:*/ +/* table address in RAM for samples of the G_R color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +/* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */ +/* (if available).*/ +#ifdef MRV_LSC_GR_RAM_ADDR +#define MRV_LSC_GR_RAM_ADDR_MIN_BANK0 (0x00000000U) +#define MRV_LSC_GR_RAM_ADDR_MAX_BANK0 (0x00000098U) +#define MRV_LSC_GR_RAM_ADDR_MIN_BANK1 (0x00000099U) +#define MRV_LSC_GR_RAM_ADDR_MAX_BANK1 (0x00000131U) +#endif /* MRV_LSC_GR_RAM_ADDR */ +/*****************************************************************************/ +/** + * register: isp_lsc_b_table_addr: Table RAM Address for blue component + * (0x0000000c) + * + *****************************************************************************/ +/* Slice: b_ram_addr:*/ +/* table address in RAM for samples of the B color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +/* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */ +/* (if available).*/ +#ifdef MRV_LSC_B_RAM_ADDR +#define MRV_LSC_B_RAM_ADDR_MIN_BANK0 (0x00000000U) +#define MRV_LSC_B_RAM_ADDR_MAX_BANK0 (0x00000098U) +#define MRV_LSC_B_RAM_ADDR_MIN_BANK1 (0x00000099U) +#define MRV_LSC_B_RAM_ADDR_MAX_BANK1 (0x00000132U) +#endif /* MRV_LSC_B_RAM_ADDR */ +/*****************************************************************************/ +/** + * register: isp_lsc_gb_table_addr: Table RAM Address for green (blue) component + * (0x00000010) + * + *****************************************************************************/ +/* Slice: gb_ram_addr:*/ +/* table address in RAM for samples of the G_B color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +/* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */ +/* (if available).*/ +#ifdef MRV_LSC_GB_RAM_ADDR +#define MRV_LSC_GB_RAM_ADDR_MIN_BANK0 (0x00000000U) +#define MRV_LSC_GB_RAM_ADDR_MAX_BANK0 (0x00000098U) +#define MRV_LSC_GB_RAM_ADDR_MIN_BANK1 (0x00000099U) +#define MRV_LSC_GB_RAM_ADDR_MAX_BANK1 (0x00000132U) +#endif /* MRV_LSC_GB_RAM_ADDR */ +/*****************************************************************************/ +/** + * register: isp_lsc_r_table_data: Sample table red (0x00000014) + * + *****************************************************************************/ +/* Slice: r_sample_1:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_R_SAMPLE_1 +#endif /* MRV_LSC_R_SAMPLE_1 */ +/* Slice: r_sample_0:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_R_SAMPLE_0 +#endif /* MRV_LSC_R_SAMPLE_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_gr_table_data: Sample table green (red) (0x00000018) + * + *****************************************************************************/ +/* Slice: gr_sample_1:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_GR_SAMPLE_1 +#endif /* MRV_LSC_GR_SAMPLE_1 */ +/* Slice: gr_sample_0:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_GR_SAMPLE_0 +#endif /* MRV_LSC_GR_SAMPLE_0 */ +/*****************************************************************************/ +/** + * register: Register: isp_lsc_b_table_data: Sample table blue (0x0000001c) + * + *****************************************************************************/ +/* Slice: b_sample_1:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_B_SAMPLE_1 +#endif /* MRV_LSC_B_SAMPLE_1 */ +/* Slice: b_sample_0:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_B_SAMPLE_0 +#endif /* MRV_LSC_B_SAMPLE_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_gb_table_data: Sample table green (blue) (0x00000020) + * + *****************************************************************************/ +/* Slice: gb_sample_1:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_GB_SAMPLE_1 +#endif /* MRV_LSC_GB_SAMPLE_1 */ +/* Slice: gb_sample_0:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_GB_SAMPLE_0 +#endif /* MRV_LSC_GB_SAMPLE_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xgrad_01: Gradient table x (0x00000024) + * + *****************************************************************************/ +/* Slice: xgrad_1:*/ +/* factor for x-gradient calculation of sector 1 */ +#ifdef MRV_LSC_XGRAD_1 +#endif /* MRV_LSC_XGRAD_1 */ +/* Slice: xgrad_0:*/ +/* factor for x-gradient calculation of sector 0 */ +#ifdef MRV_LSC_XGRAD_0 +#endif /* MRV_LSC_XGRAD_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xgrad_23: Gradient table x (0x00000028) + * + *****************************************************************************/ +/* Slice: xgrad_3:*/ +/* factor for x-gradient calculation of sector 3 */ +#ifdef MRV_LSC_XGRAD_3 +#endif /* MRV_LSC_XGRAD_3 */ +/* Slice: xgrad_2:*/ +/* factor for x-gradient calculation of sector 2 */ +#ifdef MRV_LSC_XGRAD_2 +#endif /* MRV_LSC_XGRAD_2 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xgrad_45: Gradient table x (0x0000002c) + * + *****************************************************************************/ +/* Slice: xgrad_5:*/ +/* factor for x-gradient calculation of sector 5 */ +#ifdef MRV_LSC_XGRAD_5 +#endif /* MRV_LSC_XGRAD_5 */ +/* Slice: xgrad_4:*/ +/* factor for x-gradient calculation of sector 4 */ +#ifdef MRV_LSC_XGRAD_4 +#endif /* MRV_LSC_XGRAD_4 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xgrad_67: Gradient table x (0x00000030) + * + *****************************************************************************/ +/* Slice: xgrad_7:*/ +/* factor for x-gradient calculation of sector 7 */ +#ifdef MRV_LSC_XGRAD_7 +#endif /* MRV_LSC_XGRAD_7 */ +/* Slice: xgrad_6:*/ +/* factor for x-gradient calculation of sector 6 */ +#ifdef MRV_LSC_XGRAD_6 +#endif /* MRV_LSC_XGRAD_6 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ygrad_01: Gradient table y (0x00000034) + * + *****************************************************************************/ +/* Slice: ygrad_1:*/ +/* factor for y-gradient calculation of sector 1 */ +#ifdef MRV_LSC_YGRAD_1 +#endif /* MRV_LSC_YGRAD_1 */ +/* Slice: ygrad_0:*/ +/* factor for y-gradient calculation of sector 0 */ +#ifdef MRV_LSC_YGRAD_0 +#endif /* MRV_LSC_YGRAD_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ygrad_23: Gradient table y (0x00000038) + * + *****************************************************************************/ +/* Slice: ygrad_3:*/ +/* factor for y-gradient calculation of sector 3 */ +#ifdef MRV_LSC_YGRAD_3 +#endif /* MRV_LSC_YGRAD_3 */ +/* Slice: ygrad_2:*/ +/* factor for y-gradient calculation of sector 2 */ +#ifdef MRV_LSC_YGRAD_2 +#endif /* MRV_LSC_YGRAD_2 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ygrad_45: Gradient table y (0x0000003c) + * + *****************************************************************************/ +/* Slice: ygrad_5:*/ +/* factor for y-gradient calculation of sector 5 */ +#ifdef MRV_LSC_YGRAD_5 +#endif /* MRV_LSC_YGRAD_5 */ +/* Slice: ygrad_4:*/ +/* factor for y-gradient calculation of sector 4 */ +#ifdef MRV_LSC_YGRAD_4 +#endif /* MRV_LSC_YGRAD_4 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ygrad_67: Gradient table y (0x00000040) + * + *****************************************************************************/ +/* Slice: ygrad_7:*/ +/* factor for y-gradient calculation of sector 7 */ +#ifdef MRV_LSC_YGRAD_7 +#endif /* MRV_LSC_YGRAD_7 */ +/* Slice: ygrad_6:*/ +/* factor for y-gradient calculation of sector 6 */ +#ifdef MRV_LSC_YGRAD_6 +#endif /* MRV_LSC_YGRAD_6 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xsize_01: Size table (0x00000044) + * + *****************************************************************************/ +/* Slice: x_sect_size_1:*/ +/* sector size 1 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_1 +#endif /* MRV_LSC_X_SECT_SIZE_1 */ +/* Slice: x_sect_size_0:*/ +/* sector size 0 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_0 +#endif /* MRV_LSC_X_SECT_SIZE_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xsize_23: Size table (0x00000048) + * + *****************************************************************************/ +/* Slice: x_sect_size_3:*/ +/* sector size 3 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_3 +#endif /* MRV_LSC_X_SECT_SIZE_3 */ +/* Slice: x_sect_size_2:*/ +/* sector size 2 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_2 +#endif /* MRV_LSC_X_SECT_SIZE_2 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xsize_45: Size table (0x0000004c) + * + *****************************************************************************/ +/* Slice: x_sect_size_5:*/ +/* sector size 5 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_5 +#endif /* MRV_LSC_X_SECT_SIZE_5 */ +/* Slice: x_sect_size_4:*/ +/* sector size 4in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_4 +#endif /* MRV_LSC_X_SECT_SIZE_4 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xsize_67: Size table (0x00000050) + * + *****************************************************************************/ +/* Slice: x_sect_size_7:*/ +/* sector size 7 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_7 +#endif /* MRV_LSC_X_SECT_SIZE_7 */ +/* Slice: x_sect_size_6:*/ +/* sector size 6 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_6 +#endif /* MRV_LSC_X_SECT_SIZE_6 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ysize_01: Size table (0x00000054) + * + *****************************************************************************/ +/* Slice: y_sect_size_1:*/ +/* sector size 1 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_1 +#endif /* MRV_LSC_Y_SECT_SIZE_1 */ +/* Slice: y_sect_size_0:*/ +/* sector size 0 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_0 +#endif /* MRV_LSC_Y_SECT_SIZE_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ysize_23: Size table (0x00000058) + * + *****************************************************************************/ +/* Slice: y_sect_size_3:*/ +/* sector size 3 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_3 +#endif /* MRV_LSC_Y_SECT_SIZE_3 */ +/* Slice: y_sect_size_2:*/ +/* sector size 2 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_2 +#endif /* MRV_LSC_Y_SECT_SIZE_2 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ysize_45: Size table (0x0000005c) + * + *****************************************************************************/ +/* Slice: y_sect_size_5:*/ +/* sector size 5 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_5 +#endif /* MRV_LSC_Y_SECT_SIZE_5 */ +/* Slice: y_sect_size_4:*/ +/* sector size 4 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_4 +#endif /* MRV_LSC_Y_SECT_SIZE_4 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ysize_67: Size table (0x00000060) + * + *****************************************************************************/ +/* Slice: y_sect_size_7:*/ +/* sector size 7 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_7 +#endif /* MRV_LSC_Y_SECT_SIZE_7 */ +/* Slice: y_sect_size_6:*/ +/* sector size 6 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_6 +#endif /* MRV_LSC_Y_SECT_SIZE_6 */ +/*****************************************************************************/ +/** + * register: isp_lsc_table_sel: Lens shade table set selection (0x00000064) + * + *****************************************************************************/ +/* Slice: table_sel:*/ +/* 0: next active tables set is table set 0.*/ +/* 1: next active tables set is table set 1.*/ +/* Table selection is object of a shadowing mechnism. The current status is */ +/* visible at ISP_LSC_STATUS::active_table.*/ +#ifdef MRV_LSC_TABLE_SEL +#define MRV_LSC_TABLE_SEL_BANK0 (0U) +#define MRV_LSC_TABLE_SEL_BANK1 (1U) +#endif /* MRV_LSC_TABLE_SEL */ +/*****************************************************************************/ +/** + * register: isp_lsc_status: Lens shade status (0x00000068) + * + *****************************************************************************/ +/* Slice: active_table:*/ +/* 0: currently active tables set is table set 0 */ +/* 1: currently active tables set is table set 1 */ +#ifdef MRV_LSC_ACTIVE_TABLE +#define MRV_LSC_ACTIVE_TABLE_BANK0 (0U) +#define MRV_LSC_ACTIVE_TABLE_BANK1 (1U) +#endif /* MRV_LSC_ACTIVE_TABLE */ +/* Slice: lsc_en_status:*/ +/* 0: lens shading correction is currently off */ +/* 1: lens shading correction is currently on */ +#ifdef MRV_LSC_LSC_EN_STATUS +#endif /* MRV_LSC_LSC_EN_STATUS */ +/*****************************************************************************/ +/* ISP Chromatic Aberration Correction Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_cac_ctrl: Control register for chromatic aberration + * correction (0x00000000) + * + *****************************************************************************/ +/* Slice: h_clip_mode:*/ +/* Defines the maximum red/blue pixel shift in horizontal direction at pixel */ +/* positions, that require a larger displacement, the maximum shift value is */ +/* used instead (vector clipping)*/ + /**/ +/* 0: Set horizontal vector clipping to +/-4 pixel displacement (Default)*/ +/* 1: Set horizontal vector clipping to +/-4 or +/-5 pixel displacement */ +/* depending on pixel position inside the Bayer raster (dynamic switching */ +/* between +/-4 and +/-5)*/ +#ifdef MRV_CAC_H_CLIP_MODE +#define MRV_CAC_H_CLIP_MODE_FIX4 0 /* 0: Set horizontal vector clipping */ + /* to +/-4 pixel displacement (Default) */ +#define MRV_CAC_H_CLIP_MODE_DYN5 1 /* 1: Set horizontal vector clipping */ + /* to +/-4 or +/-5 pixel displacement depending on */ + /* pixel position inside the Bayer raster */ + /* (dynamic switching between +/-4 and +/-5) */ +#endif /* MRV_CAC_H_CLIP_MODE */ +/* Slice: v_clip_mode:*/ +/* Defines the maximum red/blue pixel shift in vertical direction */ +/* 00: Set vertical vector clipping to +/-2 pixel ; fix filter_enable (Default)*/ +/* 01: Set vertical vector clipping to +/-3 pixel; dynamic filter_enable for */ +/* chroma low pass filter */ +/* 10: Set vertical vector clipping +/-3 or +/-4 pixel displacement depending */ +/* on pixel position inside the Bayer raster (dynamic switching between +/-3 and +/-4)*/ +/* 11: reserved */ +#ifdef MRV_CAC_V_CLIP_MODE +#define MRV_CAC_V_CLIP_MODE_FIX2 0 /* 00: Set vertical vector clipping to +/-2 pixel; */ + /* fix filter_enable (Default) */ +#define MRV_CAC_V_CLIP_MODE_FIX3 1 /* 01: Set vertical vector clipping to +/-3 pixel; */ + /* dynamic filter_enable for chroma low pass filter */ +#define MRV_CAC_V_CLIP_MODE_DYN4 2 /* 10: Set vertical vector clipping +/-3 or +/-4 pixel */ + /* displacement depending on pixel position inside */ + /* the Bayer raster (dynamic switching between +/-3 and +/-4) */ +#endif /* MRV_CAC_V_CLIP_MODE */ +/* Slice: cac_en:*/ +/* 0: chromatic aberration correction off */ +/* 1: chromatic aberration correction on */ +#ifdef MRV_CAC_CAC_EN +#define MRV_CAC_CAC_EN_PROCESS 1 +#define MRV_CAC_CAC_EN_BYPASS 0 +#endif /* MRV_CAC_CAC_EN */ +/*****************************************************************************/ +/** + * register: isp_cac_count_start: Preload values for CAC pixel and line + * counter (0x00000004) + * + *****************************************************************************/ +/* Slice: v_count_start:*/ +/* 12 bit v_count preload value (range 4095 ... 1) of the vertical CAC line */ +/* counter. Before frame start v_count has to be preloaded with */ +/* (v_size/2 + v_center_offset), with v_size the image height and v_center_offset */ +/* the vertical distance between image center and optical center.*/ + /**/ +/* After frame start the v_count decrements with every line until a value of zero */ +/* is reached for the line in the optical center. Than the v_sign bit toggles and */ +/* the v_counter decrements with every line until end of frame.*/ +#ifdef MRV_CAC_V_COUNT_START +#define MRV_CAC_V_COUNT_START_MIN 1 +#define MRV_CAC_V_COUNT_START_MAX (MRV_CAC_V_COUNT_START_MASK >> MRV_CAC_V_COUNT_START_SHIFT) +#endif /* MRV_CAC_V_COUNT_START */ +/* Slice: h_count_start:*/ +/* 12 bit h_count preload value (range 4095 .. 1) of the horizontal CAC pixel */ +/* counter. Before line start h_count has to be preloaded with (h_size/2 + h_center_offset),*/ +/* with h_size the image width and h_center_offset the horizontal distance between image */ +/* center and optical center.*/ + /**/ +/* After line start the h_count decrements with every pixel until a value of zero is */ +/* reached for the column in the optical center. Than the h_sign bit toggles and the */ +/* h_counter increments with every pixel until end of line.*/ +#ifdef MRV_CAC_H_COUNT_START +#define MRV_CAC_H_COUNT_START_MIN 1 +#define MRV_CAC_H_COUNT_START_MAX (MRV_CAC_H_COUNT_START_MASK >> MRV_CAC_H_COUNT_START_SHIFT) +#endif /* MRV_CAC_H_COUNT_START */ +/*****************************************************************************/ +/** + * register: isp_cac_a: Linear Parameters for radial shift calculation (0x00000008) + * + *****************************************************************************/ +/* Slice: A_Blue:*/ +/* Parameter A_Blue for radial blue shift calculation, according to */ +/* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_A_BLUE +#define MRV_CAC_A_BLUE_MAX (MRV_CAC_A_BLUE_MASK >> (MRV_CAC_A_BLUE_SHIFT)) +#define MRV_CAC_A_BLUE_MIN 0 +#endif /* MRV_CAC_A_BLUE */ +/* Slice: A_Red:*/ +/* Parameter A_Red for radial red shift calculation, according to */ +/* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_A_RED +#define MRV_CAC_A_RED_MAX (MRV_CAC_A_RED_MASK >> (MRV_CAC_A_RED_SHIFT)) +#define MRV_CAC_A_RED_MIN 0 +#endif /* MRV_CAC_A_RED */ +/*****************************************************************************/ +/** + * register: isp_cac_b: Square Parameters for radial shift calculation (0x0000000c) + * + *****************************************************************************/ +/* Slice: B_Blue:*/ +/* Parameter B_Blue for radial blue shift calculation, according to */ +/* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_B_BLUE +#define MRV_CAC_B_BLUE_MAX (MRV_CAC_B_BLUE_MASK >> (MRV_CAC_B_BLUE_SHIFT)) +#define MRV_CAC_B_BLUE_MIN 0 +#endif /* MRV_CAC_B_BLUE */ +/* Slice: B_Red:*/ +/* Parameter B_Red for radial red shift calculation, according to */ +/* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_B_RED +#define MRV_CAC_B_RED_MAX (MRV_CAC_B_RED_MASK >> (MRV_CAC_B_RED_SHIFT)) +#define MRV_CAC_B_RED_MIN 0 +#endif /* MRV_CAC_B_RED */ +/*****************************************************************************/ +/** + * register: isp_cac_c: Cubical Parameters for radial shift calculation (0x00000010) + * + *****************************************************************************/ +/* Slice: C_Blue:*/ +/* Parameter C_Blue for radial blue shift calculation, according to */ +/* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_C_BLUE +#define MRV_CAC_C_BLUE_MAX (MRV_CAC_C_BLUE_MASK >> (MRV_CAC_C_BLUE_SHIFT)) +#define MRV_CAC_C_BLUE_MIN 0 +#endif /* MRV_CAC_C_BLUE */ +/* Slice: C_Red:*/ +/* Parameter C_Red for radial red shift calculation, according to */ +/* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_C_RED +#define MRV_CAC_C_RED_MAX (MRV_CAC_C_RED_MASK >> (MRV_CAC_C_RED_SHIFT)) +#define MRV_CAC_C_RED_MIN 0 +#endif /* MRV_CAC_C_RED */ +/*****************************************************************************/ +/** + * register: isp_cac_x_norm: Normalization parameters for calculation of image + * coordinate x_d relative to optical center (0x00000014) + * + *****************************************************************************/ +/* Slice: x_ns:*/ +/* Horizontal normalization shift parameter x_ns (4 bit unsigned integer)*/ +/* in equation x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */ +#ifdef MRV_CAC_X_NS +#define MRV_CAC_X_NS_MIN 0 +#define MRV_CAC_X_NS_MAX (MRV_CAC_X_NS_MASK >> MRV_CAC_X_NS_SHIFT) +#endif /* MRV_CAC_X_NS */ +/* Slice: x_nf:*/ +/* Horizontal scaling or normalization factor x_nf (5 bit unsigned integer)*/ +/* range 0 .. 31 in equation x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */ +#ifdef MRV_CAC_X_NF +#define MRV_CAC_X_NF_MIN 0 +#define MRV_CAC_X_NF_MAX 31 +#endif /* MRV_CAC_X_NF */ +/*****************************************************************************/ +/** + * register: isp_cac_y_norm: Normalization parameters for calculation of image + * coordinate y_d relative to optical center (0x00000018) + * + *****************************************************************************/ +/* Slice: y_ns:*/ +/* Vertical normalization shift parameter y_ns (4 bit unsigned integer)*/ +/* in equation y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */ +#ifdef MRV_CAC_Y_NS +#define MRV_CAC_Y_NS_MIN 0 +#define MRV_CAC_Y_NS_MAX (MRV_CAC_Y_NS_MASK >> MRV_CAC_Y_NS_SHIFT) +#endif /* MRV_CAC_Y_NS */ +/* Slice: y_nf:*/ +/* Vertical scaling or normalization factor y_nf (5 bit unsigned integer)*/ +/* range 0 .. 31 in equation y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */ +#ifdef MRV_CAC_Y_NF +#define MRV_CAC_Y_NF_MIN 0 +#define MRV_CAC_Y_NF_MAX 31 +#endif /* MRV_CAC_Y_NF */ +/*****************************************************************************/ +/* ISP Exposure Measurement Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_exp_ctrl: Exposure control (0x00000000) + * + *****************************************************************************/ +/* Slice: exp_meas_mode:*/ +/* '1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256)*/ +/* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */ +#ifdef MRV_AE_EXP_MEAS_MODE +#define MRV_AE_EXP_MEAS_MODE_1 1 /* '1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256) */ +#define MRV_AE_EXP_MEAS_MODE_0 0 /* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */ +#endif /* MRV_AE_EXP_MEAS_MODE */ +/* Slice: autostop:*/ +/* '1' stop measuring after a complete frame */ +/* '0' continous measurement */ +#ifdef MRV_AE_AUTOSTOP +#define MRV_AE_AUTOSTOP_STOP_MEASURING 1 /* stop measuring after a complete frame */ +#define MRV_AE_AUTOSTOP_CONTINOUS_MEASURING 0 /* don't stop measurement, continoue with next frame */ +#endif /* MRV_AE_AUTOSTOP */ +/* Slice: exp_start:*/ +/* '1' start measuring a frame. The exp block will reset this bit and halt */ +/* after completing one frame, if bit "autostop" is set to '1'.*/ +#ifdef MRV_AE_EXP_START +#define MRV_AE_EXP_START_PROCESS 1 /* 1: processing is activated */ +#define MRV_AE_EXP_START_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */ +#endif /* MRV_AE_EXP_START */ +/*****************************************************************************/ +/** + * register: isp_exp_h_offset: Horizontal offset for first block (0x00000004) + * + *****************************************************************************/ +/* Slice: isp_exp_h_offset:*/ +/* Horizontal offset of first block in pixels.*/ +/* 0 <= value <= 3920 */ +#ifdef MRV_AE_ISP_EXP_H_OFFSET +#define MRV_AE_ISP_EXP_H_OFFSET_MIN 0x00000000 +#define MRV_AE_ISP_EXP_H_OFFSET_MAX 0x00000F50 /* 4096-176 */ +#endif /* MRV_AE_ISP_EXP_H_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_exp_v_offset: Vertical offset for first block (0x00000008) + * + *****************************************************************************/ +/* Slice: isp_exp_v_offset:*/ +/* Vertical offset of first block in pixels.*/ +/* 0 <= value <= 1806 */ +#ifdef MRV_AE_ISP_EXP_V_OFFSET +#define MRV_AE_ISP_EXP_V_OFFSET_MIN 0x00000000 +#define MRV_AE_ISP_EXP_V_OFFSET_MAX 0x00000B74 /* 3072-140 */ +#endif /* MRV_AE_ISP_EXP_V_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_exp_h_size: Horizontal size of one block (0x0000000c) + * + *****************************************************************************/ +/* Slice: isp_exp_h_size:*/ +/* Horizontal size in pixels of one block.*/ +/* 35 <= value <= 516 */ +#ifdef MRV_AE_ISP_EXP_H_SIZE +#define MRV_AE_ISP_EXP_H_SIZE_MIN 0x00000023 +#define MRV_AE_ISP_EXP_H_SIZE_MAX 0x00000333 +#endif /* MRV_AE_ISP_EXP_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_exp_v_size: Vertical size of one block (0x00000010) + * + *****************************************************************************/ +/* Slice: isp_exp_v_size:*/ +/* Vertical size in pixels of one block.*/ +/* 28 <= value <= 390 */ +#ifdef MRV_AE_ISP_EXP_V_SIZE +#define MRV_AE_ISP_EXP_V_SIZE_VALID_MASK (MRV_AE_ISP_EXP_V_SIZE_MASK & ~0x00000001) +#define MRV_AE_ISP_EXP_V_SIZE_MIN 0x0000001C +#define MRV_AE_ISP_EXP_V_SIZE_MAX 0x00000266 +#endif /* MRV_AE_ISP_EXP_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_00: Mean luminance value of block 00 (0x00000014) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_00:*/ +/* Mean luminance value of block 00 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_00 +#endif /* MRV_AE_ISP_EXP_MEAN_00 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_10: Mean luminance value of block 10 (0x00000018) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_10:*/ +/* Mean luminance value of block 10 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_10 +#endif /* MRV_AE_ISP_EXP_MEAN_10 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_20: Mean luminance value of block 20 (0x0000001c) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_20:*/ +/* Mean luminance value of block 20 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_20 +#endif /* MRV_AE_ISP_EXP_MEAN_20 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_30: Mean luminance value of block 30 (0x00000020) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_30:*/ +/* Mean luminance value of block 30 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_30 +#endif /* MRV_AE_ISP_EXP_MEAN_30 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_40: Mean luminance value of block 40 (0x00000024) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_40:*/ +/* Mean luminance value of block 40 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_40 +#endif /* MRV_AE_ISP_EXP_MEAN_40 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_01: Mean luminance value of block 01 (0x00000028) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_01:*/ +/* Mean luminance value of block 01 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_01 +#endif /* MRV_AE_ISP_EXP_MEAN_01 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c) + * + *****************************************************************************/ +/* Register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c)*/ +/* Slice: isp_exp_mean_11:*/ +/* Mean luminance value of block 11 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_11 +#endif /* MRV_AE_ISP_EXP_MEAN_11 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_21: Mean luminance value of block 21 (0x00000030) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_21:*/ +/* Mean luminance value of block 21 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_21 +#endif /* MRV_AE_ISP_EXP_MEAN_21 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_31: Mean luminance value of block 31 (0x00000034) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_31:*/ +/* Mean luminance value of block 31 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_31 +#endif /* MRV_AE_ISP_EXP_MEAN_31 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_41: Mean luminance value of block 41 (0x00000038) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_41:*/ +/* Mean luminance value of block 41 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_41 +#endif /* MRV_AE_ISP_EXP_MEAN_41 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_02: Mean luminance value of block 02 (0x0000003c) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_02:*/ +/* Mean luminance value of block 02 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_02 +#endif /* MRV_AE_ISP_EXP_MEAN_02 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_12: Mean luminance value of block 12 (0x00000040) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_12:*/ +/* Mean luminance value of block 12 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_12 +#endif /* MRV_AE_ISP_EXP_MEAN_12 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_22: Mean luminance value of block 22 (0x00000044) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_22:*/ +/* Mean luminance value of block 22 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_22 +#endif /* MRV_AE_ISP_EXP_MEAN_22 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_32: Mean luminance value of block 32 (0x00000048) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_32:*/ +/* Mean luminance value of block 32 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_32 +#endif /* MRV_AE_ISP_EXP_MEAN_32 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_42: Mean luminance value of block 42 (0x0000004c) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_42:*/ +/* Mean luminance value of block 42 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_42 +#endif /* MRV_AE_ISP_EXP_MEAN_42 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_03: Mean luminance value of block 03 (0x00000050) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_03:*/ +/* Mean luminance value of block 03 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_03 +#endif /* MRV_AE_ISP_EXP_MEAN_03 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_13: Mean luminance value of block 13 (0x00000054) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_13:*/ +/* Mean luminance value of block 13 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_13 +#endif /* MRV_AE_ISP_EXP_MEAN_13 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_23: Mean luminance value of block 23 (0x00000058) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_23:*/ +/* Mean luminance value of block 23 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_23 +#endif /* MRV_AE_ISP_EXP_MEAN_23 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_33: Mean luminance value of block 33 (0x0000005c) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_33:*/ +/* Mean luminance value of block 33 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_33 +#endif /* MRV_AE_ISP_EXP_MEAN_33 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_43: Mean luminance value of block 43 (0x00000060) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_43:*/ +/* Mean luminance value of block 43 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_43 +#endif /* MRV_AE_ISP_EXP_MEAN_43 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_04: Mean luminance value of block 04 (0x00000064) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_04:*/ +/* Mean luminance value of block 04 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_04 +#endif /* MRV_AE_ISP_EXP_MEAN_04 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_14: Mean luminance value of block 14 (0x00000068) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_14:*/ +/* Mean luminance value of block 14 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_14 +#endif /* MRV_AE_ISP_EXP_MEAN_14 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_24: Mean luminance value of block 24 (0x0000006c) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_24:*/ +/* Mean luminance value of block 24 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_24 +#endif /* MRV_AE_ISP_EXP_MEAN_24 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_34: Mean luminance value of block 34 (0x00000070) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_34:*/ +/* Mean luminance value of block 34 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_34 +#endif /* MRV_AE_ISP_EXP_MEAN_34 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_44: Mean luminance value of block 44 (0x00000074) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_44:*/ +/* Mean luminance value of block 44 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_44 +#endif /* MRV_AE_ISP_EXP_MEAN_44 */ +/*****************************************************************************/ +/* ISP Black Level Subtraction Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_bls_ctrl: global control register (0x00000000) + * + *****************************************************************************/ +/* Slice: WINDOW_ENABLE:*/ +/* 0: no measuring is performed */ +/* 1: only window 1 is measured */ +/* 2: only window 2 is measured */ +/* 3: both windows are measured */ +#ifdef MRV_BLS_WINDOW_ENABLE +#define MRV_BLS_WINDOW_ENABLE_NONE 0U /* 0: no measuring is performed */ +#define MRV_BLS_WINDOW_ENABLE_WND1 1U /* 1: only window 1 is measured */ +#define MRV_BLS_WINDOW_ENABLE_WND2 2U /* 2: only window 2 is measured */ +#define MRV_BLS_WINDOW_ENABLE_BOTH 3U /* 3: both windows are measured */ +#define MRV_BLS_WINDOW_ENABLE_WND1_MASK 0x00000004U +#define MRV_BLS_WINDOW_ENABLE_WND1_SHIFT 2U +#define MRV_BLS_WINDOW_ENABLE_WND2_MASK 0x00000008U +#define MRV_BLS_WINDOW_ENABLE_WND2_SHIFT 3U +#endif /* MRV_BLS_WINDOW_ENABLE */ +/* Slice: BLS_MODE:*/ +/* 1: subtract measured values */ +/* 0: subtract fixed values */ +#ifdef MRV_BLS_BLS_MODE +#define MRV_BLS_BLS_MODE_MEAS 1U /* 1: subtract measured values */ +#define MRV_BLS_BLS_MODE_FIX 0U /* 0: subtract fixed values */ +#endif /* MRV_BLS_BLS_MODE */ +/* Slice: BLS_ENABLE:*/ +/* 1: black level subtraction is enabled */ +/* 0: bypass the black level processing */ +#ifdef MRV_BLS_BLS_ENABLE +#define MRV_BLS_BLS_ENABLE_PROCESS 1U /* 1: black level subtraction is enabled */ +#define MRV_BLS_BLS_ENABLE_BYPASS 0U /* 0: bypass the black level processing */ +#endif /* MRV_BLS_BLS_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_bls_samples: samples register (0x00000004) + * + *****************************************************************************/ +/* Slice: BLS_SAMPLES:*/ +/* This number to the power of two gives the number of measure samples for */ +/* each Bayer position. Range 0x00: 2^0=1 to 0x12: 2^18=262144. This number */ +/* is also the divider for the accumulator for each Bayer position.*/ + /**/ +/* The accumulation will be stopped, if the number of measured pixels for the */ +/* current Bayer position is equal to the number of samples.*/ + /**/ +/* The measure windows must be positioned that way that the number of included */ +/* pixels of each Bayer position included by both windows is equal or greater */ +/* than the number of measure samples calculated by 2^BLS_SAMPLES !*/ + /**/ +/* NOTE:*/ +/* - The number of pixels of one Bayer position is 1/4 of the number of all */ +/* Pixels included by the measure windows.*/ +#ifdef MRV_BLS_BLS_SAMPLES +#define MRV_BLS_BLS_SAMPLES_MAX (0x00000014U) /* maximum is 2^20 = 1048576 */ +#endif /* MRV_BLS_BLS_SAMPLES */ +/*****************************************************************************/ +/** + * register: isp_bls_h1_start: window 1 horizontal start (0x00000008) + * + *****************************************************************************/ +/* Slice: BLS_H1_START:*/ +/* Black pixel window 1 horizontal start position */ +#ifdef MRV_BLS_BLS_H1_START +#define MRV_BLS_BLS_H1_START_MAX (MRV_BLS_BLS_H1_START_MASK >> MRV_BLS_BLS_H1_START_SHIFT) +#endif /* MRV_BLS_BLS_H1_START */ +/*****************************************************************************/ +/** + * register: isp_bls_h1_stop: window 1 horizontal stop (0x0000000c) + * + *****************************************************************************/ +/* Slice: BLS_H1_STOP:*/ +/* Black pixel window 1 horizontal stop position */ +#ifdef MRV_BLS_BLS_H1_STOP +#define MRV_BLS_BLS_H1_STOP_MAX (MRV_BLS_BLS_H1_STOP_MASK >> MRV_BLS_BLS_H1_STOP_SHIFT) +#endif /* MRV_BLS_BLS_H1_STOP */ +/*****************************************************************************/ +/** + * register: isp_bls_v1_start: window 1 vertical start (0x00000010) + * + *****************************************************************************/ +/* Slice: BLS_V1_START:*/ +/* Black pixel window 1 vertical start position */ +#ifdef MRV_BLS_BLS_V1_START +#define MRV_BLS_BLS_V1_START_MAX (MRV_BLS_BLS_V1_START_MASK >> MRV_BLS_BLS_V1_START_SHIFT) +#endif /* MRV_BLS_BLS_V1_START */ +/*****************************************************************************/ +/** + * register: isp_bls_v1_stop: window 1 vertical stop (0x00000014) + * + *****************************************************************************/ +/* Slice: BLS_V1_STOP:*/ +/* Black pixel window 1 vertical stop position */ +#ifdef MRV_BLS_BLS_V1_STOP +#define MRV_BLS_BLS_V1_STOP_MAX (MRV_BLS_BLS_V1_STOP_MASK >> MRV_BLS_BLS_V1_STOP_SHIFT) +#endif /* MRV_BLS_BLS_V1_STOP */ +/*****************************************************************************/ +/** + * register: isp_bls_h2_start: window 2 horizontal start (0x00000018) + * + *****************************************************************************/ +/* Slice: BLS_H2_START:*/ +/* Black pixel window 2 horizontal start position */ +#ifdef MRV_BLS_BLS_H2_START +#define MRV_BLS_BLS_H2_START_MAX (MRV_BLS_BLS_H2_START_MASK >> MRV_BLS_BLS_H2_START_SHIFT) +#endif /* MRV_BLS_BLS_H2_START */ +/*****************************************************************************/ +/** + * register: isp_bls_h2_stop: window 2 horizontal stop (0x0000001c) + * + *****************************************************************************/ +/* Slice: BLS_H2_STOP:*/ +/* Black pixel window 2 horizontal stop position */ +#ifdef MRV_BLS_BLS_H2_STOP +#define MRV_BLS_BLS_H2_STOP_MAX (MRV_BLS_BLS_H2_STOP_MASK >> MRV_BLS_BLS_H2_STOP_SHIFT) +#endif /* MRV_BLS_BLS_H2_STOP */ +/*****************************************************************************/ +/** + * register: isp_bls_v2_start: window 2 vertical start (0x00000020) + * + *****************************************************************************/ +/* Slice: BLS_V2_START:*/ +/* Black pixel window 2 vertical start position */ +#ifdef MRV_BLS_BLS_V2_START +#define MRV_BLS_BLS_V2_START_MAX (MRV_BLS_BLS_V2_START_MASK >> MRV_BLS_BLS_V2_START_SHIFT) +#endif /* MRV_BLS_BLS_V2_START */ +/*****************************************************************************/ +/** + * register: isp_bls_v2_stop: window 2 vertical stop (0x00000024) + * + *****************************************************************************/ +/* Slice: BLS_V2_STOP:*/ +/* Black pixel window 2 vertical stop position */ +#ifdef MRV_BLS_BLS_V2_STOP +#define MRV_BLS_BLS_V2_STOP_MAX (MRV_BLS_BLS_V2_STOP_MASK >> MRV_BLS_BLS_V2_STOP_SHIFT) +#endif /* MRV_BLS_BLS_V2_STOP */ +/*****************************************************************************/ +/** + * register: isp_bls_a_fixed: fixed black level A (0x00000028) + * + *****************************************************************************/ +/* Slice: BLS_A_FIXED:*/ +/* Fixed black level for A pixels – signed */ +/* two's complement, value range from -4096 to +4095,*/ +/* a positive value will be subtracted from the pixel values */ +#ifdef MRV_BLS_BLS_A_FIXED +#endif /* MRV_BLS_BLS_A_FIXED */ +/*****************************************************************************/ +/** + * register: isp_bls_b_fixed: fixed black level B (0x0000002c) + * + *****************************************************************************/ +/* Slice: BLS_B_FIXED:*/ +/* Fixed black level for B pixels – signed */ +/* two's complement, value range from -4096 to +4095 */ +#ifdef MRV_BLS_BLS_B_FIXED +#endif /* MRV_BLS_BLS_B_FIXED */ +/*****************************************************************************/ +/** + * register: isp_bls_c_fixed: fixed black level C (0x00000030) + * + *****************************************************************************/ +/* Slice: BLS_C_FIXED:*/ +/* Fixed black level for C pixels – signed */ +/* two's complement, value range from -4096 to +4095 */ +#ifdef MRV_BLS_BLS_C_FIXED +#endif /* MRV_BLS_BLS_C_FIXED */ +/*****************************************************************************/ +/** + * register: isp_bls_d_fixed: fixed black level D (0x00000034) + * + *****************************************************************************/ +/* Slice: BLS_D_FIXED:*/ +/* Fixed black level for D pixels - signed */ +/* two's complement, value range from -4096 to +4095 */ +#ifdef MRV_BLS_BLS_D_FIXED +#endif /* MRV_BLS_BLS_D_FIXED */ +/*****************************************************************************/ +/** + * register: isp_bls_a_measured: measured black level A (0x00000038) + * + *****************************************************************************/ +/* Slice: BLS_A_MEASURED:*/ +/* Measured black level for A pixels */ +#ifdef MRV_BLS_BLS_A_MEASURED +#endif /* MRV_BLS_BLS_A_MEASURED */ +/*****************************************************************************/ +/** + * register: isp_bls_b_measured: measured black level B (0x0000003c) + * + *****************************************************************************/ +/* Slice: BLS_B_MEASURED:*/ +/* Measured black level for B pixels */ +#ifdef MRV_BLS_BLS_B_MEASURED +#endif /* MRV_BLS_BLS_B_MEASURED */ +/*****************************************************************************/ +/** + * register: isp_bls_c_measured: measured black level C (0x00000040) + * + *****************************************************************************/ +/* Slice: BLS_C_MEASURED:*/ +/* Measured black level for C pixels */ +#ifdef MRV_BLS_BLS_C_MEASURED +#endif /* MRV_BLS_BLS_C_MEASURED */ +/*****************************************************************************/ +/** + * register: isp_bls_d_measured: measured black level D (0x00000044) + * + *****************************************************************************/ +/* Slice: BLS_D_MEASURED:*/ +/* Measured black level for D pixels */ +#ifdef MRV_BLS_BLS_D_MEASURED +#endif /* MRV_BLS_BLS_D_MEASURED */ +/*****************************************************************************/ +/* ISP Denoising Pre-Filter Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_dpf_mode: Mode control for Denoising Pre-Filter block + * (0x00000000) + * + *****************************************************************************/ +/* Slice: USE_NF_GAIN:*/ +/* 1: dpf_nf_gain's will be used */ +/* 0: external AWB gains will be used *Default**/ +#ifdef MRV_DPF_USE_NF_GAIN +#endif /* MRV_DPF_USE_NF_GAIN */ +/* Slice: LSC_GAIN_COMP:*/ +/* 1: LSC gain will be processed */ +/* 0: LSC gain will not be processed *Default**/ +#ifdef MRV_DPF_LSC_GAIN_COMP +#endif /* MRV_DPF_LSC_GAIN_COMP */ +/* Slice: AWB_GAIN_COMP:*/ +/* 1: AWB gain or internal dpf_nf_gain will be processed */ +/* 0: AWB gain or internal dpf_nf_gain will not be processed *Default**/ +#ifdef MRV_DPF_AWB_GAIN_COMP +#endif /* MRV_DPF_AWB_GAIN_COMP */ +/* Slice: NLL_SEGMENTATION:*/ +/* 1: optimized logarithmic like segmentation for Noise Level Lookup (NLL)*/ +/* 0: equidistant segmentation for NLL *Default**/ +#ifdef MRV_DPF_NLL_SEGMENTATION +#endif /* MRV_DPF_NLL_SEGMENTATION */ +/* Slice: RB_FILTER_SIZE:*/ +/* 1: Red and Blue filter kernel size of 9x9 (5x5 active) pixels */ +/* 0: Wide Red and Blue filter kernel size of 13x9 (7x5 active) pixels *Default**/ +#ifdef MRV_DPF_RB_FILTER_SIZE +#endif /* MRV_DPF_RB_FILTER_SIZE */ +/* Slice: R_FILTER_OFF:*/ +/* 1: disable filter processing for red pixels (R)*/ +/* 0: filter R pixels *Default**/ +#ifdef MRV_DPF_R_FILTER_OFF +#endif /* MRV_DPF_R_FILTER_OFF */ +/* Slice: GR_FILTER_OFF:*/ +/* 1: disable filter processing for green pixels in green/red lines (GR)*/ +/* 0: filter GR pixels *Default**/ +#ifdef MRV_DPF_GR_FILTER_OFF +#endif /* MRV_DPF_GR_FILTER_OFF */ +/* Slice: GB_FILTER_OFF:*/ +/* 1: disable filter processing for green pixels in green/blue lines (GB)*/ +/* 0: filter GB pixels *Default**/ +#ifdef MRV_DPF_GB_FILTER_OFF +#endif /* MRV_DPF_GB_FILTER_OFF */ +/* Slice: B_FILTER_OFF:*/ +/* 1: disable filter processing for blue pixels (B)*/ +/* 0: filter B pixels *Default**/ +#ifdef MRV_DPF_B_FILTER_OFF +#endif /* MRV_DPF_B_FILTER_OFF */ +/* Slice: DPF_ENABLE:*/ +/* 1: enable dpf */ +/* 0: bypass dpf *Default**/ +#ifdef MRV_DPF_DPF_ENABLE +#endif /* MRV_DPF_DPF_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_dpf_strength_r: filter strength of the RED filter (0x00000004) + * + *****************************************************************************/ +/* Slice: INV_WEIGHT_R:*/ +/* Filter strength of the filter is determined by weight. Default is a */ +/* weight of 1. A higher weight increases the filter strength. In this */ +/* register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#ifdef MRV_DPF_INV_WEIGHT_R +#endif /* MRV_DPF_INV_WEIGHT_R */ +/*****************************************************************************/ +/** + * register: isp_dpf_strength_g: filter strength of the GREEN filter (0x00000008) + * + *****************************************************************************/ +/* Slice: INV_WEIGHT_G:*/ +/* Filter strength of the filter is determined by weight. Default is a */ +/* weight of 1. A higher weight increases the filter strength. In this */ +/* register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#ifdef MRV_DPF_INV_WEIGHT_G +#endif /* MRV_DPF_INV_WEIGHT_G */ +/*****************************************************************************/ +/** + * register: isp_dpf_strength_b: filter strength of the BLUE filter (0x0000000c) + * + *****************************************************************************/ +/* Slice: INV_WEIGHT_B:*/ +/* Filter strength of the filter is determined by weight. Default is a */ +/* weight of 1. A higher weight increases the filter strength. In this */ +/* register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#ifdef MRV_DPF_INV_WEIGHT_B +#endif /* MRV_DPF_INV_WEIGHT_B */ +/*****************************************************************************/ +/** + * register: isp_dpf_s_weight_g_1_4: Spatial Weights green channel 1 2 3 4 + * (0x00000010) + * + *****************************************************************************/ +/* Slice: S_WEIGHT_G4:*/ +/* Filter Coefficient green channel S_WEIGHT_G4 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G4 +#endif /* MRV_DPF_S_WEIGHT_G4 */ +/* Slice: S_WEIGHT_G3:*/ +/* Filter Coefficient green channel S_WEIGHT_G3 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G3 +#endif /* MRV_DPF_S_WEIGHT_G3 */ +/* Slice: S_WEIGHT_G2:*/ +/* Filter Coefficient green channel S_WEIGHT_G2 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G2 +#endif /* MRV_DPF_S_WEIGHT_G2 */ +/* Slice: S_WEIGHT_G1:*/ +/* Filter Coefficient green channel S_WEIGHT_G1 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G1 +#endif /* MRV_DPF_S_WEIGHT_G1 */ +/*****************************************************************************/ +/** + * register: isp_dpf_s_weight_g_5_6: Spatial Weights green channel 5 6 + * (0x00000014) + * + *****************************************************************************/ +/* Slice: S_WEIGHT_G6:*/ +/* Filter Coefficient green channel S_WEIGHT_G6 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G6 +#endif /* MRV_DPF_S_WEIGHT_G6 */ +/* Slice: S_WEIGHT_G5:*/ +/* Filter Coefficient green channel S_WEIGHT_G5 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G5 +#endif /* MRV_DPF_S_WEIGHT_G5 */ +/*****************************************************************************/ +/** + * register: isp_dpf_s_weight_rb_1_4: Spatial Weights red/blue channels 1 2 3 4 + * (0x00000018) + * + *****************************************************************************/ +/* Slice: S_WEIGHT_RB4:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB4 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB4 +#endif /* MRV_DPF_S_WEIGHT_RB4 */ +/* Slice: S_WEIGHT_RB3:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB3 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB3 +#endif /* MRV_DPF_S_WEIGHT_RB3 */ +/* Slice: S_WEIGHT_RB2:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB2 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB2 +#endif /* MRV_DPF_S_WEIGHT_RB2 */ +/* Slice: S_WEIGHT_RB1:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB1 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB1 +#endif /* MRV_DPF_S_WEIGHT_RB1 */ +/*****************************************************************************/ +/** + * register: isp_dpf_s_weight_rb_5_6: Spatial Weights red/blue channels 5 6 + * (0x0000001c) + * + *****************************************************************************/ +/* Slice: S_WEIGHT_RB6:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB6 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB6 +#endif /* MRV_DPF_S_WEIGHT_RB6 */ +/* Slice: S_WEIGHT_RB5:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB5 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB5 +#endif /* MRV_DPF_S_WEIGHT_RB5 */ +/*****************************************************************************/ +/** + * register array: isp_dpf_nll_coeff: Noise Level Lookup Coefficient + * (0x0040 + n*0x4 (n=0..16)) + * + *****************************************************************************/ +/* Slice: nll_coeff_n:*/ +/* Noise Level Lookup Table Coefficient nll_coeff_n */ +/* 10 bit unsigned, value range 1/1024 to 1023/1024 (*Default*)*/ +#ifdef MRV_DPF_NLL_COEFF_N +#endif /* MRV_DPF_NLL_COEFF_N */ +/*****************************************************************************/ +/** + * register: isp_dpf_nf_gain_r: noise function gain for red pixels (0x00000064) + * + *****************************************************************************/ +/* Slice: DPF_NF_GAIN_R:*/ +/* Noise Function (NF) Gain that replaces the AWB gain for red pixels.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#ifdef MRV_DPF_DPF_NF_GAIN_R +#endif /* MRV_DPF_DPF_NF_GAIN_R */ +/*****************************************************************************/ +/** + * register: isp_dpf_nf_gain_gr: noise function gain for green in red pixels + * (0x00000068) + * + *****************************************************************************/ +/* Slice: DPF_NF_GAIN_GR:*/ +/* Noise Function (NF) Gain that replaces the AWB gain for green pixels in a */ +/* red line.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#ifdef MRV_DPF_DPF_NF_GAIN_GR +#endif /* MRV_DPF_DPF_NF_GAIN_GR */ +/*****************************************************************************/ +/** + * register: isp_dpf_nf_gain_gb: noise function gain for green in blue pixels + * (0x0000006c) + * + *****************************************************************************/ +/* Slice: DPF_NF_GAIN_GB:*/ +/* Noise Function (NF) Gain that replaces the AWB gain for green pixels in a */ +/* blue line.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#ifdef MRV_DPF_DPF_NF_GAIN_GB +#endif /* MRV_DPF_DPF_NF_GAIN_GB */ +/*****************************************************************************/ +/** + * register: isp_dpf_nf_gain_b: noise function gain for blue pixels (0x00000070) + * + *****************************************************************************/ +/* Slice: DPF_NF_GAIN_B:*/ +/* Noise Function (NF) Gain that replaces the AWB gain for blue pixels.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#ifdef MRV_DPF_DPF_NF_GAIN_B +#endif /* MRV_DPF_DPF_NF_GAIN_B */ +/*****************************************************************************/ +/* ISP Defect Pixel Cluster Correction Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_dpcc_mode: mode control for DPCC block (0x0000) + * + *****************************************************************************/ +/* Slice: STAGE1_ENABLE:*/ +/* 1: enable stage1 *Default**/ +/* 0: bypass stage1 */ +#ifdef MRV_DPCC_STAGE1_ENABLE +#endif /* MRV_DPCC_STAGE1_ENABLE */ +/* Slice: GRAYSCALE_MODE:*/ +/* 1: enable gray scale data input from black and white sensors (without color filter array)*/ +/* 0: BAYER DATA INPUT *Default**/ +#ifdef MRV_DPCC_GRAYSCALE_MODE +#endif /* MRV_DPCC_GRAYSCALE_MODE */ +/* Slice: ISP_DPCC_enable:*/ +/* 1: enable DPCC */ +/* 0: bypass DPCC *Default**/ +#ifdef MRV_DPCC_ISP_DPCC_ENABLE +#endif /* MRV_DPCC_ISP_DPCC_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_dpcc_output_mode: interpolation mode for correction unit + * (0x00000004) + * + *****************************************************************************/ +/* Slice: STAGE1_RB_3x3:*/ +/* 1: stage1 red/blue 9 pixel (3x3) output median */ +/* 0: stage1 red/blue 4 or 5 pixel output median *Default**/ +#ifdef MRV_DPCC_STAGE1_RB_3X3 +#endif /* MRV_DPCC_STAGE1_RB_3X3 */ +/* Slice: STAGE1_G_3x3:*/ +/* 1: stage1 green 9 pixel (3x3) output median */ +/* 0: stage1 green 4 or 5 pixel output median *Default**/ +#ifdef MRV_DPCC_STAGE1_G_3X3 +#endif /* MRV_DPCC_STAGE1_G_3X3 */ +/* Slice: STAGE1_INCL_RB_CENTER:*/ +/* 1: stage1 include center pixel for red/blue output median 2x2+1 */ +/* *Default* 0: stage1 do not include center pixel for red/blue output median 2x2 */ +#ifdef MRV_DPCC_STAGE1_INCL_RB_CENTER +#endif /* MRV_DPCC_STAGE1_INCL_RB_CENTER */ +/* Slice: STAGE1_INCL_GREEN_CENTER:*/ +/* 1: stage1 include center pixel for green output median 2x2+1 *Default**/ +/* 0: stage1 do not include center pixel for green output median 2x2 */ +#ifdef MRV_DPCC_STAGE1_INCL_GREEN_CENTER +#endif /* MRV_DPCC_STAGE1_INCL_GREEN_CENTER */ +/*****************************************************************************/ +/** + * register: isp_dpcc_set_use: DPCC methods set usage for detection + * (0x00000008) + * + *****************************************************************************/ +/* Slice: STAGE1_USE_FIX_SET:*/ +/* 1: stage1 use hard coded methods set *Default**/ +/* 0: stage1 do not use hard coded methods set */ +#ifdef MRV_DPCC_STAGE1_USE_FIX_SET +#endif /* MRV_DPCC_STAGE1_USE_FIX_SET */ +/* Slice: STAGE1_USE_SET_3:*/ +/* 1: stage1 use methods set 3 */ +/* 0: stage1 do not use methods set 3 *Default**/ +#ifdef MRV_DPCC_STAGE1_USE_SET_3 +#endif /* MRV_DPCC_STAGE1_USE_SET_3 */ +/* Slice: STAGE1_USE_SET_2:*/ +/* 1: stage1 use methods set 2 */ +/* 0: stage1 do not use methods set 2 *Default**/ +#ifdef MRV_DPCC_STAGE1_USE_SET_2 +#endif /* MRV_DPCC_STAGE1_USE_SET_2 */ +/* Slice: STAGE1_USE_SET_1:*/ +/* 1: stage1 use methods set 1 *Default**/ +/* 0: stage1 do not use methods set 1 */ +#ifdef MRV_DPCC_STAGE1_USE_SET_1 +#endif /* MRV_DPCC_STAGE1_USE_SET_1 */ +/*****************************************************************************/ +/** + * register: isp_dpcc_methods_set_1: Methods enable bits for SET_1 + * (0x0000000c) + * + *****************************************************************************/ +/* Slice: RG_RED_BLUE1_ENABLE:*/ +/* 1: enable Rank Gradient check for red_blue *Default**/ +/* 0: bypass Rank Gradient check for red_blue */ +#ifdef MRV_DPCC_RG_RED_BLUE1_ENABLE +#endif /* MRV_DPCC_RG_RED_BLUE1_ENABLE */ +/* Slice: RND_RED_BLUE1_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for red_blue *Default**/ +/* 0: bypass Rank Neighbor Difference check for red_blue */ +#ifdef MRV_DPCC_RND_RED_BLUE1_ENABLE +#endif /* MRV_DPCC_RND_RED_BLUE1_ENABLE */ +/* Slice: RO_RED_BLUE1_ENABLE:*/ +/* 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#ifdef MRV_DPCC_RO_RED_BLUE1_ENABLE +#endif /* MRV_DPCC_RO_RED_BLUE1_ENABLE */ +/* Slice: LC_RED_BLUE1_ENABLE:*/ +/* 1: enable Line check for red_blue *Default**/ +/* 0: bypass Line check for red_blue */ +#ifdef MRV_DPCC_LC_RED_BLUE1_ENABLE +#endif /* MRV_DPCC_LC_RED_BLUE1_ENABLE */ +/* Slice: PG_RED_BLUE1_ENABLE:*/ +/* 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#ifdef MRV_DPCC_PG_RED_BLUE1_ENABLE +#endif /* MRV_DPCC_PG_RED_BLUE1_ENABLE */ +/* Slice: RG_GREEN1_ENABLE:*/ +/* 1: enable Rank Gradient check for green *Default**/ +/* 0: bypass Rank Gradient check for green */ +#ifdef MRV_DPCC_RG_GREEN1_ENABLE +#endif /* MRV_DPCC_RG_GREEN1_ENABLE */ +/* Slice: RND_GREEN1_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for green *Default**/ +/* 0: bypass Rank Neighbor Difference check for green */ +#ifdef MRV_DPCC_RND_GREEN1_ENABLE +#endif /* MRV_DPCC_RND_GREEN1_ENABLE */ +/* Slice: RO_GREEN1_ENABLE:*/ +/* 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#ifdef MRV_DPCC_RO_GREEN1_ENABLE +#endif /* MRV_DPCC_RO_GREEN1_ENABLE */ +/* Slice: LC_GREEN1_ENABLE:*/ +/* 1: enable Line check for green *Default**/ +/* 0: bypass Line check for green */ +#ifdef MRV_DPCC_LC_GREEN1_ENABLE +#endif /* MRV_DPCC_LC_GREEN1_ENABLE */ +/* Slice: PG_GREEN1_ENABLE:*/ +/* 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#ifdef MRV_DPCC_PG_GREEN1_ENABLE +#endif /* MRV_DPCC_PG_GREEN1_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_dpcc_methods_set_2: Methods enable bits for SET_2 + * (0x00000010) + * + *****************************************************************************/ +/* Slice: RG_RED_BLUE2_ENABLE:*/ +/* 1: enable Rank Gradient check for red_blue *Default**/ +/* 0: bypass Rank Gradient check for red_blue */ +#ifdef MRV_DPCC_RG_RED_BLUE2_ENABLE +#endif /* MRV_DPCC_RG_RED_BLUE2_ENABLE */ +/* Slice: RND_RED_BLUE2_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for red_blue *Default**/ +/* 0: bypass Rank Neighbor Difference check for red_blue */ +#ifdef MRV_DPCC_RND_RED_BLUE2_ENABLE +#endif /* MRV_DPCC_RND_RED_BLUE2_ENABLE */ +/* Slice: RO_RED_BLUE2_ENABLE:*/ +/* 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#ifdef MRV_DPCC_RO_RED_BLUE2_ENABLE +#endif /* MRV_DPCC_RO_RED_BLUE2_ENABLE */ +/* Slice: LC_RED_BLUE2_ENABLE:*/ +/* 1: enable Line check for red_blue *Default**/ +/* 0: bypass Line check for red_blue */ +#ifdef MRV_DPCC_LC_RED_BLUE2_ENABLE +#endif /* MRV_DPCC_LC_RED_BLUE2_ENABLE */ +/* Slice: PG_RED_BLUE2_ENABLE:*/ +/* 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#ifdef MRV_DPCC_PG_RED_BLUE2_ENABLE +#endif /* MRV_DPCC_PG_RED_BLUE2_ENABLE */ +/* Slice: RG_GREEN2_ENABLE:*/ +/* 1: enable Rank Gradient check for green *Default**/ +/* 0: bypass Rank Gradient check for green */ +#ifdef MRV_DPCC_RG_GREEN2_ENABLE +#endif /* MRV_DPCC_RG_GREEN2_ENABLE */ +/* Slice: RND_GREEN2_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for green *Default**/ +/* 0: bypass Rank Neighbor Difference check for green */ +#ifdef MRV_DPCC_RND_GREEN2_ENABLE +#endif /* MRV_DPCC_RND_GREEN2_ENABLE */ +/* Slice: RO_GREEN2_ENABLE:*/ +/* 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#ifdef MRV_DPCC_RO_GREEN2_ENABLE +#endif /* MRV_DPCC_RO_GREEN2_ENABLE */ +/* Slice: LC_GREEN2_ENABLE:*/ +/* 1: enable Line check for green *Default**/ +/* 0: bypass Line check for green */ +#ifdef MRV_DPCC_LC_GREEN2_ENABLE +#endif /* MRV_DPCC_LC_GREEN2_ENABLE */ +/* Slice: PG_GREEN2_ENABLE:*/ +/* 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#ifdef MRV_DPCC_PG_GREEN2_ENABLE +#endif /* MRV_DPCC_PG_GREEN2_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_dpcc_methods_set_3: Methods enable bits for SET_3 + * (0x00000014) + * + *****************************************************************************/ +/* Slice: RG_RED_BLUE3_ENABLE:*/ +/* 1: enable Rank Gradient check for red_blue *Default**/ +/* 0: bypass Rank Gradient check for red_blue */ +#ifdef MRV_DPCC_RG_RED_BLUE3_ENABLE +#endif /* MRV_DPCC_RG_RED_BLUE3_ENABLE */ +/* Slice: RND_RED_BLUE3_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for red_blue *Default**/ +/* 0: bypass Rank Neighbor Difference check for red_blue */ +#ifdef MRV_DPCC_RND_RED_BLUE3_ENABLE +#endif /* MRV_DPCC_RND_RED_BLUE3_ENABLE */ +/* Slice: RO_RED_BLUE3_ENABLE:*/ +/* 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#ifdef MRV_DPCC_RO_RED_BLUE3_ENABLE +#endif /* MRV_DPCC_RO_RED_BLUE3_ENABLE */ +/* Slice: LC_RED_BLUE3_ENABLE:*/ +/* 1: enable Line check for red_blue *Default**/ +/* 0: bypass Line check for red_blue */ +#ifdef MRV_DPCC_LC_RED_BLUE3_ENABLE +#endif /* MRV_DPCC_LC_RED_BLUE3_ENABLE */ +/* Slice: PG_RED_BLUE3_ENABLE:*/ +/* 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#ifdef MRV_DPCC_PG_RED_BLUE3_ENABLE +#endif /* MRV_DPCC_PG_RED_BLUE3_ENABLE */ +/* Slice: RG_GREEN3_ENABLE:*/ +/* 1: enable Rank Gradient check for green *Default**/ +/* 0: bypass Rank Gradient check for green */ +#ifdef MRV_DPCC_RG_GREEN3_ENABLE +#endif /* MRV_DPCC_RG_GREEN3_ENABLE */ +/* Slice: RND_GREEN3_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for green *Default**/ +/* 0: bypass Rank Neighbor Difference check for green */ +#ifdef MRV_DPCC_RND_GREEN3_ENABLE +#endif /* MRV_DPCC_RND_GREEN3_ENABLE */ +/* Slice: RO_GREEN3_ENABLE:*/ +/* 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#ifdef MRV_DPCC_RO_GREEN3_ENABLE +#endif /* MRV_DPCC_RO_GREEN3_ENABLE */ +/* Slice: LC_GREEN3_ENABLE:*/ +/* 1: enable Line check for green *Default**/ +/* 0: bypass Line check for green */ +#ifdef MRV_DPCC_LC_GREEN3_ENABLE +#endif /* MRV_DPCC_LC_GREEN3_ENABLE */ +/* Slice: PG_GREEN3_ENABLE:*/ +/* 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#ifdef MRV_DPCC_PG_GREEN3_ENABLE +#endif /* MRV_DPCC_PG_GREEN3_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_thresh_1: Line threshold SET_1 (0x00000018) + * + *****************************************************************************/ +/* Slice: LINE_THR_1_RB:*/ +/* line threshold for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_THR_1_RB +#endif /* MRV_DPCC_LINE_THR_1_RB */ +/* Slice: LINE_THR_1_G:*/ +/* line threshold for set 1 green */ +#ifdef MRV_DPCC_LINE_THR_1_G +#endif /* MRV_DPCC_LINE_THR_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_mad_fac_1: Mean Absolute Difference (MAD) factor + * for Line check set 1 (0x0000001c) + * + *****************************************************************************/ +/* Slice: LINE_MAD_FAC_1_RB:*/ +/* line MAD factor for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_MAD_FAC_1_RB +#endif /* MRV_DPCC_LINE_MAD_FAC_1_RB */ +/* Slice: LINE_MAD_FAC_1_G:*/ +/* line MAD factor for set 1 green */ +#ifdef MRV_DPCC_LINE_MAD_FAC_1_G +#endif /* MRV_DPCC_LINE_MAD_FAC_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_pg_fac_1: Peak gradient factor for set 1 (0x00000020) + * + *****************************************************************************/ +/* Slice: PG_FAC_1_RB:*/ +/* Peak gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_PG_FAC_1_RB +#endif /* MRV_DPCC_PG_FAC_1_RB */ +/* Slice: PG_FAC_1_G:*/ +/* Peak gradient factor for set 1 green */ +#ifdef MRV_DPCC_PG_FAC_1_G +#endif /* MRV_DPCC_PG_FAC_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rnd_thresh_1: Rank Neighbor Difference threshold for + * set 1 (0x00000024) + * + *****************************************************************************/ +/* Slice: RND_THR_1_RB:*/ +/* Rank Neighbor Difference threshold for set 1 red/blue */ +#ifdef MRV_DPCC_RND_THR_1_RB +#endif /* MRV_DPCC_RND_THR_1_RB */ +/* Slice: RND_THR_1_G:*/ +/* Rank Neighbor Difference threshold for set 1 green */ +#ifdef MRV_DPCC_RND_THR_1_G +#endif /* MRV_DPCC_RND_THR_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rg_fac_1: Rank gradient factor for set 1 (0x00000028) + * + *****************************************************************************/ +/* Slice: RG_FAC_1_RB:*/ +/* Rank gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_RG_FAC_1_RB +#endif /* MRV_DPCC_RG_FAC_1_RB */ +/* Slice: RG_FAC_1_G:*/ +/* Rank gradient factor for set 1 green */ +#ifdef MRV_DPCC_RG_FAC_1_G +#endif /* MRV_DPCC_RG_FAC_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_thresh_2: Line threshold SET_2 (0x0000002C) + * + *****************************************************************************/ +/* Slice: LINE_THR_2_RB:*/ +/* line threshold for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_THR_2_RB +#endif /* MRV_DPCC_LINE_THR_2_RB */ +/* Slice: LINE_THR_2_G:*/ +/* line threshold for set 1 green */ +#ifdef MRV_DPCC_LINE_THR_2_G +#endif /* MRV_DPCC_LINE_THR_2_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_mad_fac_2: Mean Absolute Difference (MAD) factor + * for Line check set 1 (0x00000030) + * + *****************************************************************************/ +/* Slice: LINE_MAD_FAC_2_RB:*/ +/* line MAD factor for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_MAD_FAC_2_RB +#endif /* MRV_DPCC_LINE_MAD_FAC_2_RB */ +/* Slice: LINE_MAD_FAC_2_G:*/ +/* line MAD factor for set 1 green */ +#ifdef MRV_DPCC_LINE_MAD_FAC_2_G +#endif /* MRV_DPCC_LINE_MAD_FAC_2_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_pg_fac_2: Peak gradient factor for set 1 (0x00000034) + * + *****************************************************************************/ +/* Slice: PG_FAC_2_RB:*/ +/* Peak gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_PG_FAC_2_RB +#endif /* MRV_DPCC_PG_FAC_2_RB */ +/* Slice: PG_FAC_2_G:*/ +/* Peak gradient factor for set 1 green */ +#ifdef MRV_DPCC_PG_FAC_2_G +#endif /* MRV_DPCC_PG_FAC_2_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rnd_thresh_2: Rank Neighbor Difference threshold for + * set 1 (0x00000038) + * + *****************************************************************************/ +/* Slice: RND_THR_2_RB:*/ +/* Rank Neighbor Difference threshold for set 1 red/blue */ +#ifdef MRV_DPCC_RND_THR_2_RB +#endif /* MRV_DPCC_RND_THR_2_RB */ +/* Slice: RND_THR_2_G:*/ +/* Rank Neighbor Difference threshold for set 1 green */ +#ifdef MRV_DPCC_RND_THR_2_G +#endif /* MRV_DPCC_RND_THR_2_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rg_fac_2: Rank gradient factor for set 1 (0x0000003C) + * + *****************************************************************************/ +/* Slice: RG_FAC_2_RB:*/ +/* Rank gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_RG_FAC_2_RB +#endif /* MRV_DPCC_RG_FAC_2_RB */ +/* Slice: RG_FAC_2_G:*/ +/* Rank gradient factor for set 1 green */ +#ifdef MRV_DPCC_RG_FAC_2_G +#endif /* MRV_DPCC_RG_FAC_2_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_thresh_3: Line threshold SET_3 (0x00000040) + * + *****************************************************************************/ +/* Slice: LINE_THR_3_RB:*/ +/* line threshold for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_THR_3_RB +#endif /* MRV_DPCC_LINE_THR_3_RB */ +/* Slice: LINE_THR_3_G:*/ +/* line threshold for set 1 green */ +#ifdef MRV_DPCC_LINE_THR_3_G +#endif /* MRV_DPCC_LINE_THR_3_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_mad_fac_3: Mean Absolute Difference (MAD) factor + * for Line check set 1 (0x00000044) + * + *****************************************************************************/ +/* Slice: LINE_MAD_FAC_3_RB:*/ +/* line MAD factor for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_MAD_FAC_3_RB +#endif /* MRV_DPCC_LINE_MAD_FAC_3_RB */ +/* Slice: LINE_MAD_FAC_3_G:*/ +/* line MAD factor for set 1 green */ +#ifdef MRV_DPCC_LINE_MAD_FAC_3_G +#endif /* MRV_DPCC_LINE_MAD_FAC_3_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_pg_fac_3: Peak gradient factor for set 1 (0x00000048) + * + *****************************************************************************/ +/* Slice: PG_FAC_3_RB:*/ +/* Peak gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_PG_FAC_3_RB +#endif /* MRV_DPCC_PG_FAC_3_RB */ +/* Slice: PG_FAC_3_G:*/ +/* Peak gradient factor for set 1 green */ +#ifdef MRV_DPCC_PG_FAC_3_G +#endif /* MRV_DPCC_PG_FAC_3_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rnd_thresh_3: Rank Neighbor Difference threshold for + * set 1 (0x0000004C) + * + *****************************************************************************/ +/* Slice: RND_THR_3_RB:*/ +/* Rank Neighbor Difference threshold for set 1 red/blue */ +#ifdef MRV_DPCC_RND_THR_3_RB +#endif /* MRV_DPCC_RND_THR_3_RB */ +/* Slice: RND_THR_3_G:*/ +/* Rank Neighbor Difference threshold for set 1 green */ +#ifdef MRV_DPCC_RND_THR_3_G +#endif /* MRV_DPCC_RND_THR_3_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rg_fac_3: Rank gradient factor for set 1 (0x00000050) + * + *****************************************************************************/ +/* Slice: RG_FAC_3_RB:*/ +/* Rank gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_RG_FAC_3_RB +#endif /* MRV_DPCC_RG_FAC_3_RB */ +/* Slice: RG_FAC_3_G:*/ +/* Rank gradient factor for set 1 green */ +#ifdef MRV_DPCC_RG_FAC_3_G +#endif /* MRV_DPCC_RG_FAC_3_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_ro_limits: Rank Order Limits (0x00000054) + * + *****************************************************************************/ +/* Slice: RO_LIM_3_RB:*/ +/* Rank order limit for set 3 red/blue */ +#ifdef MRV_DPCC_RO_LIM_3_RB +#endif /* MRV_DPCC_RO_LIM_3_RB */ +/* Slice: RO_LIM_3_G:*/ +/* Rank order limit for set 3 green */ +#ifdef MRV_DPCC_RO_LIM_3_G +#endif /* MRV_DPCC_RO_LIM_3_G */ +/* Slice: RO_LIM_2_RB:*/ +/* Rank order limit for set 2 red/blue */ +#ifdef MRV_DPCC_RO_LIM_2_RB +#endif /* MRV_DPCC_RO_LIM_2_RB */ +/* Slice: RO_LIM_2_G:*/ +/* Rank order limit for set 2 green */ +#ifdef MRV_DPCC_RO_LIM_2_G +#endif /* MRV_DPCC_RO_LIM_2_G */ +/* Slice: RO_LIM_1_RB:*/ +/* Rank order limit for set 1 red/blue */ +#ifdef MRV_DPCC_RO_LIM_1_RB +#endif /* MRV_DPCC_RO_LIM_1_RB */ +/* Slice: RO_LIM_1_G:*/ +/* Rank order limit for set 1 green */ +#ifdef MRV_DPCC_RO_LIM_1_G +#endif /* MRV_DPCC_RO_LIM_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rnd_offs: Differential Rank Offsets for Rank Neighbor + * Difference (0x00000058) + * + *****************************************************************************/ +/* Slice: RND_OFFS_3_RB:*/ +/* Rank Offset to Neighbor for set 3 red/blue */ +#ifdef MRV_DPCC_RND_OFFS_3_RB +#endif /* MRV_DPCC_RND_OFFS_3_RB */ +/* Slice: RND_OFFS_3_G:*/ +/* Rank Offset to Neighbor for set 3 green */ +#ifdef MRV_DPCC_RND_OFFS_3_G +#endif /* MRV_DPCC_RND_OFFS_3_G */ +/* Slice: RND_OFFS_2_RB:*/ +/* Rank Offset to Neighbor for set 2 red/blue */ +#ifdef MRV_DPCC_RND_OFFS_2_RB +#endif /* MRV_DPCC_RND_OFFS_2_RB */ +/* Slice: RND_OFFS_2_G:*/ +/* Rank Offset to Neighbor for set 2 green */ +#ifdef MRV_DPCC_RND_OFFS_2_G +#endif /* MRV_DPCC_RND_OFFS_2_G */ +/* Slice: RND_OFFS_1_RB:*/ +/* Rank Offset to Neighbor for set 1 red/blue */ +#ifdef MRV_DPCC_RND_OFFS_1_RB +#endif /* MRV_DPCC_RND_OFFS_1_RB */ +/* Slice: RND_OFFS_1_G:*/ +/* Rank Offset to Neighbor for set 1 green */ +#ifdef MRV_DPCC_RND_OFFS_1_G +#endif /* MRV_DPCC_RND_OFFS_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_bpt_ctrl: bad pixel table settings (0x0000005c) + * + *****************************************************************************/ +/* Slice: BPT_RB_3x3:*/ +/* 1: if BPT active red/blue 9 pixel (3x3) output median */ +/* 0: if BPT active red/blue 4 or 5 pixel output median *Default**/ +#ifdef MRV_DPCC_BPT_RB_3X3 +#endif /* MRV_DPCC_BPT_RB_3X3 */ +/* Slice: BPT_G_3x3:*/ +/* 1: if BPT active green 9 pixel (3x3) output median */ +/* 0: if BPT active green 4 or 5 pixel output median *Default**/ +#ifdef MRV_DPCC_BPT_G_3X3 +#endif /* MRV_DPCC_BPT_G_3X3 */ +/* Slice: BPT_INCL_RB_CENTER:*/ +/* 1: if BPT active include center pixel for red/blue output median 2x2+1 */ +/* 0: if BPT active do not include center pixel for red/blue output median 2x2 *Default**/ +#ifdef MRV_DPCC_BPT_INCL_RB_CENTER +#endif /* MRV_DPCC_BPT_INCL_RB_CENTER */ +/* Slice: BPT_INCL_GREEN_CENTER:*/ +/* 1: if BPT active include center pixel for green output median 2x2+1 */ +/* 0: if BPT active do not include center pixel for green output median 2x2 *Default**/ +#ifdef MRV_DPCC_BPT_INCL_GREEN_CENTER +#endif /* MRV_DPCC_BPT_INCL_GREEN_CENTER */ +/* Slice: BPT_USE_FIX_SET:*/ +/* 1: for BPT write use hard coded methods set */ +/* 0: for BPT write do not use hard coded methods set *Default**/ +#ifdef MRV_DPCC_BPT_USE_FIX_SET +#endif /* MRV_DPCC_BPT_USE_FIX_SET */ +/* Slice: BPT_USE_SET_3:*/ +/* 1: for BPT write use methods set 3 */ +/* 0: for BPT write do not use methods set 3 *Default**/ +#ifdef MRV_DPCC_BPT_USE_SET_3 +#endif /* MRV_DPCC_BPT_USE_SET_3 */ +/* Slice: BPT_USE_SET_2:*/ +/* 1: for BPT write use methods set 2 */ +/* 0: for BPT write do not use methods set 2 *Default**/ +#ifdef MRV_DPCC_BPT_USE_SET_2 +#endif /* MRV_DPCC_BPT_USE_SET_2 */ +/* Slice: BPT_USE_SET_1:*/ +/* 1: for BPT write use methods set 1 */ +/* 0: for BPT write do not use methods set 1 *Default**/ +#ifdef MRV_DPCC_BPT_USE_SET_1 +#endif /* MRV_DPCC_BPT_USE_SET_1 */ +/* Slice: bpt_cor_en:*/ +/* table based correction enable */ +/* 1: table based correction is enabled */ +/* 0: table based correction is disabled */ +#ifdef MRV_DPCC_BPT_COR_EN +#endif /* MRV_DPCC_BPT_COR_EN */ +/* Slice: bpt_det_en:*/ +/* Bad pixel detection write enable */ +/* 1: bad pixel detection write to memory is enabled */ +/* 0: bad pixel detection write to memory is disabled */ +#ifdef MRV_DPCC_BPT_DET_EN +#endif /* MRV_DPCC_BPT_DET_EN */ +/*****************************************************************************/ +/** + * register: isp_dpcc_bpt_addr: TABLE Start Address for table-based correction + * algorithm (0x00000064) + * + *****************************************************************************/ +/* Slice: bp_table_addr:*/ +/* Table RAM start address for read or write operations. The address counter */ +/* is incremented at each read or write access to the data register (auto-*/ +/* increment mechanism).*/ +#ifdef MRV_DPCC_BP_TABLE_ADDR +#endif /* MRV_DPCC_BP_TABLE_ADDR */ +/*****************************************************************************/ +/** + * register: isp_dpcc_bpt_data: TABLE DATA register for read and write access + * of table RAM (0x00000068) + * + *****************************************************************************/ +/* Slice: bpt_v_addr:*/ +/* Bad Pixel vertical address (pixel position)*/ +#ifdef MRV_DPCC_BPT_V_ADDR +#endif /* MRV_DPCC_BPT_V_ADDR */ +/* Slice: bpt_h_addr:*/ +/* Bad Pixel horizontal address (pixel position)*/ +#ifdef MRV_DPCC_BPT_H_ADDR +#endif /* MRV_DPCC_BPT_H_ADDR */ +/*****************************************************************************/ +/* ISP Wide Dynamic Range */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_wdr_ctrl: Control Bits for Wide Dynamic Range Unit (0x00000000) + * + *****************************************************************************/ +/* Slice: WDR_RGB_FACTOR:*/ +/* rgb_factor defines how much influence the RGBmax approach has in comparison */ +/* to Y. The illumination reference Iref is calculated according to the following */ +/* formula:*/ + /**/ +/* Iref = (WDR_RGB_FACTOR * RGBYmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */ + /**/ +/* So, rgb_factor = 0 means that the standard approach is used. Use of this */ +/* factor requires that Iref has been selected, see WDR_USE_IREF.*/ + /**/ +/* Value range of rgb_factor: 0...8 */ +#ifdef MRV_WDR_RGB_FACTOR +#endif /* MRV_WDR_RGB_FACTOR */ +/* Slice: WDR_DISABLE_TRANSIENT:*/ +/* 1: disable transient between Y and RGBY_max */ +/* 0: calculate transient between Y and RGBY_max (for noise reduction) *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#ifdef MRV_WDR_DISABLE_TRANSIENT +#endif /* MRV_WDR_DISABLE_TRANSIENT */ +/* Slice: WDR_USE_RGB7_8:*/ +/* 1: decrease RGBmax by 7/8 (for noise reduction)*/ +/* 0: do not modify RGBmax *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#ifdef MRV_WDR_USE_RGB7_8 +#endif /* MRV_WDR_USE_RGB7_8 */ +/* Slice: WDR_USE_Y9_8:*/ +/* 1: use R G B and Y*9/8 for maximum value calculation (for noise reduction)*/ +/* 0: only use R G B for maximum value calculation (RGBYmax approach) *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#ifdef MRV_WDR_USE_Y9_8 +#endif /* MRV_WDR_USE_Y9_8 */ +/* Slice: WDR_USE_IREF:*/ +/* 1: use Iref (Illumination reference) instead of Y for ToneMapping and Gain calculation */ +/* 0: use Y for ToneMapping and Gain calculation *Default**/ +/* Iref is calculated according to the following formula:*/ +/* Iref = (WDR_RGB_FACTOR * RGBmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */ +#ifdef MRV_WDR_USE_IREF +#endif /* MRV_WDR_USE_IREF */ +/* Slice: WDR_CR_MAPPING_DISABLE:*/ +/* 1: disable (bypass) Chrominance Mapping */ +/* 0: enable Chrominance Mapping *Default**/ +/* requires that Luminance/chrominance color space has been selected */ +#ifdef MRV_WDR_CR_MAPPING_DISABLE +#endif /* MRV_WDR_CR_MAPPING_DISABLE */ +/* Slice: WDR_COLOR_SPACE_SELECT:*/ +/* 1: R, G, B color space */ +/* 0: Luminance/Chrominance color space *Default**/ +#ifdef MRV_WDR_COLOR_SPACE_SELECT +#endif /* MRV_WDR_COLOR_SPACE_SELECT */ +/* Slice: WDR_ENABLE:*/ +/* 1: enable WDR */ +/* 0: bypass WDR *Default**/ +#ifdef MRV_WDR_ENABLE +#endif /* MRV_WDR_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_wdr_tonecurve_1: Tone Curve sample points dYn definition + * (part 1) (0x00000004) + * + * isp_wdr_tonecurve_1_shd: Tone Curve sample points dYn definition + * shadow register (part 1) (0x000000a0) + * + *****************************************************************************/ +/* Slice: WDR_dY8:*/ +/* Tone curve sample point definition dY8 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY8 +#endif /* MRV_WDR_DY8 */ +/* Slice: WDR_dY7:*/ +/* Tone curve sample point definition dY7 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY7 +#endif /* MRV_WDR_DY7 */ +/* Slice: WDR_dY6:*/ +/* Tone curve sample point definition dY6 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY6 +#endif /* MRV_WDR_DY6 */ +/* Slice: WDR_dY5:*/ +/* Tone curve sample point definition dY5 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY5 +#endif /* MRV_WDR_DY5 */ +/* Slice: WDR_dY4:*/ +/* Tone curve sample point definition dY4 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY4 +#endif /* MRV_WDR_DY4 */ +/* Slice: WDR_dY3:*/ +/* Tone curve sample point definition dY3 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY3 +#endif /* MRV_WDR_DY3 */ +/* Slice: WDR_dY2:*/ +/* Tone curve sample point definition dY2 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY2 +#endif /* MRV_WDR_DY2 */ +/* Slice: WDR_dY1:*/ +/* Tone curve sample point definition dY1 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY1 +#endif /* MRV_WDR_DY1 */ +/*****************************************************************************/ +/** + * register: isp_wdr_tonecurve_2: Tone Curve sample points dYn definition + * (part 2) (0x00000008) + * + * isp_wdr_tonecurve_2_shd: Tone Curve sample points dYn definition + * shadow register (part 2) (0x000000a4) + * + *****************************************************************************/ +/* Slice: WDR_dY16:*/ +/* Tone curve sample point definition dY16 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY16 +#endif /* MRV_WDR_DY16 */ +/* Slice: WDR_dY15:*/ +/* Tone curve sample point definition dY15 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY15 +#endif /* MRV_WDR_DY15 */ +/* Slice: WDR_dY14:*/ +/* Tone curve sample point definition dY14 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY14 +#endif /* MRV_WDR_DY14 */ +/* Slice: WDR_dY13:*/ +/* Tone curve sample point definition dY13 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY13 +#endif /* MRV_WDR_DY13 */ +/* Slice: WDR_dY12:*/ +/* Tone curve sample point definition dY12 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY12 +#endif /* MRV_WDR_DY12 */ +/* Slice: WDR_dY11:*/ +/* Tone curve sample point definition dY11 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY11 +#endif /* MRV_WDR_DY11 */ +/* Slice: WDR_dY10:*/ +/* Tone curve sample point definition dY10 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY10 +#endif /* MRV_WDR_DY10 */ +/* Slice: WDR_dY9:*/ +/* Tone curve sample point definition dY9 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY9 +#endif /* MRV_WDR_DY9 */ +/*****************************************************************************/ +/** + * register: isp_wdr_tonecurve_3: Tone Curve sample points dYn definition + * (part 3) (0x0000000c) + * + * isp_wdr_tonecurve_3_shd: Tone Curve sample points dYn definition + * shadow register (part 3) (0x000000a8) + * + *****************************************************************************/ +/* Slice: WDR_dY24:*/ +/* Tone curve sample point definition dY24 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY24 +#endif /* MRV_WDR_DY24 */ +/* Slice: WDR_dY23:*/ +/* Tone curve sample point definition dY23 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY23 +#endif /* MRV_WDR_DY23 */ +/* Slice: WDR_dY22:*/ +/* Tone curve sample point definition dY22 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY22 +#endif /* MRV_WDR_DY22 */ +/* Slice: WDR_dY21:*/ +/* Tone curve sample point definition dY21 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY21 +#endif /* MRV_WDR_DY21 */ +/* Slice: WDR_dY20:*/ +/* Tone curve sample point definition dY20 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY20 +#endif /* MRV_WDR_DY20 */ +/* Slice: WDR_dY19:*/ +/* Tone curve sample point definition dY19 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY19 +#endif /* MRV_WDR_DY19 */ +/* Slice: WDR_dY18:*/ +/* Tone curve sample point definition dY18 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY18 +#endif /* MRV_WDR_DY18 */ +/* Slice: WDR_dY17:*/ +/* Tone curve sample point definition dY17 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY17 +#endif /* MRV_WDR_DY17 */ +/*****************************************************************************/ +/** + * register: isp_wdr_tonecurve_4: Tone Curve sample points dYn definition + * (part 4) (0x00000010) + * + * isp_wdr_tonecurve_4_shd: Tone Curve sample points dYn definition + * shadow register(part 4) (0x000000ac) + * + *****************************************************************************/ +/* Slice: WDR_dY32:*/ +/* Tone curve sample point definition dY32 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY32 +#endif /* MRV_WDR_DY32 */ +/* Slice: WDR_dY31:*/ +/* Tone curve sample point definition dY31 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY31 +#endif /* MRV_WDR_DY31 */ +/* Slice: WDR_dY30:*/ +/* Tone curve sample point definition dY30 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY30 +#endif /* MRV_WDR_DY30 */ +/* Slice: WDR_dY29:*/ +/* Tone curve sample point definition dY29 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY29 +#endif /* MRV_WDR_DY29 */ +/* Slice: WDR_dY28:*/ +/* Tone curve sample point definition dY28 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY28 +#endif /* MRV_WDR_DY28 */ +/* Slice: WDR_dY27:*/ +/* Tone curve sample point definition dY27 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY27 +#endif /* MRV_WDR_DY27 */ +/* Slice: WDR_dY26:*/ +/* Tone curve sample point definition dY26 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY26 +#endif /* MRV_WDR_DY26 */ +/* Slice: WDR_dY25:*/ +/* Tone curve sample point definition dY25 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY25 +#endif /* MRV_WDR_DY25 */ +/*****************************************************************************/ +/** + * register array: isp_wdr_tonecurve_ym: Tonemapping curve coefficient Ym_ + * (0x0028 + n*0x4 (n=0..32)) + * + *****************************************************************************/ +/* Slice: tonecurve_ym_n:*/ +/* Tone curve value definition y-axis (output) of WDR unit */ +#ifdef MRV_WDR_TONECURVE_YM_N +#endif /* MRV_WDR_TONECURVE_YM_N */ +/*****************************************************************************/ +/** + * register: isp_wdr_offset: Offset values for RGB path (0x00000098) + * + *****************************************************************************/ +/* Slice: LUM_OFFSET:*/ +/* Luminance Offset value (a) for RGB operation mode */ +/* unsigned 12 bit value */ +#ifdef MRV_WDR_LUM_OFFSET +#endif /* MRV_WDR_LUM_OFFSET */ +/* Slice: RGB_OFFSET:*/ +/* RGB Offset value (b) for RGB operation mode */ +/* unsigned 12 bit value */ +#ifdef MRV_WDR_RGB_OFFSET +#endif /* MRV_WDR_RGB_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_wdr_deltamin: DeltaMin Threshold and Strength factor (0x0000009c) + * + *****************************************************************************/ +/* Slice: DMIN_STRENGTH:*/ +/* strength factor for DMIN */ +/* unsigned 5 bit value, range 0x00...0x10 */ +#ifdef MRV_WDR_DMIN_STRENGTH +#endif /* MRV_WDR_DMIN_STRENGTH */ +/* Slice: DMIN_THRESH:*/ +/* Lower threshold for deltaMin value */ +/* unsigned 12 bit value */ +#ifdef MRV_WDR_DMIN_THRESH +#endif /* MRV_WDR_DMIN_THRESH */ +/*****************************************************************************/ +/** + * register array: isp_wdr_tonecurve_ym_shd: Tonemapping curve coefficient + * shadow register (0x0160 + n*0x4 (n=0..32)) + * + *****************************************************************************/ +/* Slice: tonecurve_ym_n_shd:*/ +/* Tone curve value definition y-axis (output) of WDR unit */ +/* shadow register.*/ +#ifdef MRV_WDR_TONECURVE_YM_N_SHD +#endif /* MRV_WDR_TONECURVE_YM_N_SHD */ +/*****************************************************************************/ +/* ISP Elliptic Auto White Balance Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: awb_meas_mode: AWB Measure Mode (0x00000000) + * + *****************************************************************************/ +/*! Register: awb_meas_mode: AWB Measure Mode (0x00000000)*/ +/*! Slice: AWB_union_e5_and_e8:*/ +/*! unite ellipse 5 with ellipse 8. Accu and count for ellipse 8.*/ +#ifdef ISP_AWB_UNION_E5_AND_E8 +#define ISP_AWB_UNION_E5_AND_E8_ON 1 /* 1: enable unite ellipse 5 with ellipse 8 */ +#define ISP_AWB_UNION_E5_AND_E8_OFF 0 /* 0: disable unite ellipse 5 with ellipse 8 */ +#endif /* ISP_AWB_UNION_E5_AND_E8 */ +/*! Slice: AWB_union_e5_and_e7:*/ +/*! unite ellipse 5 with ellipse 7. Accu and count for ellipse 7.*/ +#ifdef ISP_AWB_UNION_E5_AND_E7 +#define ISP_AWB_UNION_E5_AND_E7_ON 1 /* 1: enable unite ellipse 5 with ellipse 7 */ +#define ISP_AWB_UNION_E5_AND_E7_OFF 0 /* 0: disable unite ellipse 5 with ellipse 7 */ +#endif /* ISP_AWB_UNION_E5_AND_E7 */ +/*! Slice: AWB_union_e5_and_e6:*/ +/*! unite ellipse 5 with ellipse 6. Accu and count for ellipse 6.*/ +#ifdef ISP_AWB_UNION_E5_AND_E6 +#define ISP_AWB_UNION_E5_AND_E6_ON 1 /* 1: enable unite ellipse 5 with ellipse 6 */ +#define ISP_AWB_UNION_E5_AND_E6_OFF 0 /* 0: disable unite ellipse 5 with ellipse 6 */ +#endif /* ISP_AWB_UNION_E5_AND_E6 */ +/*! Slice: AWB_union_e1_and_e4:*/ +/*! unite ellipse 1 with ellipse 4. Accu and count for ellipse 4.*/ +#ifdef ISP_AWB_UNION_E1_AND_E4 +#define ISP_AWB_UNION_E1_AND_E4_ON 1 /* 1: enable unite ellipse 1 with ellipse 4 */ +#define ISP_AWB_UNION_E1_AND_E4_OFF 0 /* 0: disable unite ellipse 1 with ellipse 4 */ +#endif /* ISP_AWB_UNION_E1_AND_E4 */ +/*! Slice: AWB_union_e1_and_e3:*/ +/*! unite ellipse 1 with ellipse 3. Accu and count for ellipse 3.*/ +#ifdef ISP_AWB_UNION_E1_AND_E3 +#define ISP_AWB_UNION_E1_AND_E3_ON 1 /* 1: enable unite ellipse 1 with ellipse 3 */ +#define ISP_AWB_UNION_E1_AND_E3_OFF 0 /* 0: disable unite ellipse 1 with ellipse 3 */ +#endif /* ISP_AWB_UNION_E1_AND_E3 */ +/*! Slice: AWB_union_e1_and_e2:*/ +/*! unite ellipse 1 with ellipse 2. Accu and count for ellipse 2.*/ +#ifdef ISP_AWB_UNION_E1_AND_E2 +#define ISP_AWB_UNION_E1_AND_E2_ON 1 /* 1: enable unite ellipse 1 with ellipse 2 */ +#define ISP_AWB_UNION_E1_AND_E2_OFF 0 /* 0: disable unite ellipse 1 with ellipse 2 */ +#endif /* ISP_AWB_UNION_E1_AND_E2 */ +/*! Slice: AWB_meas_chrom_switch:*/ +/*! Accumulates Q1 and Q2 chromaticies instead of R, G, B color signals. Results are written on AWB_ACCU registers as well.*/ +#ifdef ISP_AWB_MEAS_CHROM_SWITCH +#define ISP_AWB_MEAS_CHROM_SWITCH_ON 1 /* 1: accumulates Q1 and Q2 chromaticies */ +#define ISP_AWB_MEAS_CHROM_SWITCH_OFF 0 /* 0: accumulates R, G, B color signals */ +#endif /* ISP_AWB_MEAS_CHROM_SWITCH */ +/* Slice: AWB_meas_irq_enable:*/ +/* AWB measure done IRQ enable.*/ +#ifdef ISP_AWB_MEAS_IRQ_ENABLE +#define ISP_AWB_MEAS_IRQ_ENABLE_ON 1 /* 1: enable measuring done irq */ +#define ISP_AWB_MEAS_IRQ_ENABLE_OFF 0 /* 0: enable measuring done irq */ +#endif /* ISP_AWB_MEAS_IRQ_ENABLE */ +/* Slice: AWB_pre_filt_en:*/ +/* median pre filter enable.*/ +#ifdef ISP_AWB_PRE_FILT_EN +#define ISP_AWB_PRE_FILT_EN_ON 1 /* 1: enable median pre filter */ +#define ISP_AWB_PRE_FILT_EN_OFF 0 /* 0: disable median pre filter */ +#endif /* ISP_AWB_PRE_FILT_EN */ +/* Slice: AWB_meas_en:*/ +/* enable measure.*/ +#ifdef ISP_AWB_MEAS_EN +#define ISP_AWB_MEAS_EN_ON 1 /* 1: enable measuring */ +#define ISP_AWB_MEAS_EN_OFF 0 /* 0: disable measuring */ +#endif /* ISP_AWB_MEAS_EN */ +/*****************************************************************************/ +/** + * register: awb_meas_h_offs: AWB window horizontal offset (0x00000004) + * + *****************************************************************************/ +/* Slice: AWB_h_offset:*/ +/* Horizontal offset in pixels.*/ +#ifdef ISP_AWB_H_OFFSET +#define ISP_AWB_H_OFFSET_MIN 0U +#define ISP_AWB_H_OFFSET_MAX (ISP_AWB_H_OFFSET_MASK >> ISP_AWB_H_OFFSET_SHIFT) +#endif /* ISP_AWB_H_OFFSET */ +/*****************************************************************************/ +/** + * register: awb_meas_v_offs: AWB window vertical offset (0x00000008) + * + *****************************************************************************/ +/* Slice: AWB_v_offset:*/ +/* Vertical offset in pixels.*/ +#ifdef ISP_AWB_V_OFFSET +#define ISP_AWB_V_OFFSET_MIN 0U +#define ISP_AWB_V_OFFSET_MAX (ISP_AWB_V_OFFSET_MASK >> ISP_AWB_V_OFFSET_SHIFT) +#endif /* ISP_AWB_V_OFFSET */ +/*****************************************************************************/ +/** + * register: awb_meas_h_size: Horizontal window size (0x0000000c) + * + *****************************************************************************/ +/* Slice: AWB_h_size:*/ +/* Horizontal size in pixels.*/ +#ifdef ISP_AWB_H_SIZE +#define ISP_AWB_H_SIZE_MIN 0U +#define ISP_AWB_H_SIZE_MAX (ISP_AWB_H_SIZE_MASK >> ISP_AWB_H_SIZE_SHIFT) +#endif /* ISP_AWB_H_SIZE */ +/*****************************************************************************/ +/** + * register: awb_meas_v_size: Vertical window size (0x00000010) + * + *****************************************************************************/ +/* Slice: AWB_v_size:*/ +/* Vertical size.*/ +#ifdef ISP_AWB_V_SIZE +#define ISP_AWB_V_SIZE_MIN 0U +#define ISP_AWB_V_SIZE_MAX (ISP_AWB_V_SIZE_MASK >> ISP_AWB_V_SIZE_SHIFT) +#endif /* ISP_AWB_V_SIZE */ +/*****************************************************************************/ +/** + * register: awb_meas_r_min_max: Min Max Compare Red (0x00000014) + * + *****************************************************************************/ +/* Slice: r_max:*/ +/* max red value */ +#ifdef ISP_AWB_R_MAX +#endif /* ISP_AWB_R_MAX */ +/* Slice: r_min:*/ +/* min red value */ +#ifdef ISP_AWB_R_MIN +#endif /* ISP_AWB_R_MIN */ +/*****************************************************************************/ +/** + * register: awb_meas_g_min_max: Min Max Compare Green (0x00000018) + * + *****************************************************************************/ +/* Slice: g_max:*/ +/* max green value */ +#ifdef ISP_AWB_G_MAX +#endif /* ISP_AWB_G_MAX */ +/* Slice: g_min:*/ +/* min green value */ +#ifdef ISP_AWB_G_MIN +#endif /* ISP_AWB_G_MIN */ +/*****************************************************************************/ +/** + * register: awb_meas_b_min_max: Min Max Compare Blue (0x0000001c) + * + *****************************************************************************/ +/* Slice: b_max:*/ +/* max blue value */ +#ifdef ISP_AWB_B_MAX +#endif /* ISP_AWB_B_MAX */ +/*! Slice: b_min:*/ +/*! min blue value */ +#ifdef ISP_AWB_B_MIN +#endif /* ISP_AWB_B_MIN */ +/*****************************************************************************/ +/** + * register: awb_meas_divider_min: Min Compare Divider (0x00000020) + * + *****************************************************************************/ +/* Slice: div_min:*/ +/* min divider value unsigned integer with 10 fractional Bits range 0 to 0.999 */ +#ifdef ISP_AWB_DIV_MIN +#endif /* ISP_AWB_DIV_MIN */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_0: Color conversion coefficient 0 (0x00000024) + * + *****************************************************************************/ +/* Slice: cc_coeff_0:*/ +/* coefficient 0 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_0 +#endif /* ISP_AWB_CC_COEFF_0 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_1: Color conversion coefficient 1 (0x00000028) + * + *****************************************************************************/ +/* Slice: cc_coeff_1:*/ +/* coefficient 1 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_1 +#endif /* ISP_AWB_CC_COEFF_1 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_2: Color conversion coefficient 2 (0x0000002c) + * + *****************************************************************************/ +/* Slice: cc_coeff_2:*/ +/* coefficient 2 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_2 +#endif /* ISP_AWB_CC_COEFF_2 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_3: Color conversion coefficient 3 (0x00000030) + * + *****************************************************************************/ +/* Slice: cc_coeff_3:*/ +/* coefficient 3 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_3 +#endif /* ISP_AWB_CC_COEFF_3 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_4: Color conversion coefficient 4 (0x00000034) + * + *****************************************************************************/ +/* Slice: cc_coeff_4:*/ +/* coefficient 4 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_4 +#endif /* ISP_AWB_CC_COEFF_4 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_5: Color conversion coefficient 5 (0x00000038) + * + *****************************************************************************/ +/* Slice: cc_coeff_5:*/ +/* coefficient 5 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_5 +#endif /* ISP_AWB_CC_COEFF_5 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_6: Color conversion coefficient 6 (0x0000003c) + * + *****************************************************************************/ +/* Slice: cc_coeff_6:*/ +/* coefficient 6 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_6 +#endif /* ISP_AWB_CC_COEFF_6 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_7: Color conversion coefficient 7 (0x00000040) + * + *****************************************************************************/ +/* Slice: cc_coeff_7:*/ +/* coefficient 7 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_7 +#endif /* ISP_AWB_CC_COEFF_7 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_8: Color conversion coefficient 8 (0x00000044) + * + *****************************************************************************/ +/* Slice: cc_coeff_8:*/ +/* coefficient 8 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_8 +#endif /* ISP_AWB_CC_COEFF_8 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_cen_x: Ellipse 1 Center X (0x00000048) + * + *****************************************************************************/ +/* Slice: ellip1_cen_x:*/ +/* Ellipse 1 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP1_CEN_X +#endif /* ISP_AWB_ELLIP1_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_cen_y: Ellipse 1 Center Y (0x0000004c) + * + *****************************************************************************/ +/* Slice: ellip1_cen_y:*/ +/* Ellipse 1 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP1_CEN_Y +#endif /* ISP_AWB_ELLIP1_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_cen_x: Ellipse 2 Center X (0x00000050) + * + *****************************************************************************/ +/* Slice: ellip2_cen_x:*/ +/* Ellipse 2 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP2_CEN_X +#endif /* ISP_AWB_ELLIP2_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_cen_y: Ellipse 2 Center Y (0x00000054) + * + *****************************************************************************/ +/* Slice: ellip2_cen_y:*/ +/* Ellipse 2 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP2_CEN_Y +#endif /* ISP_AWB_ELLIP2_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_cen_x: Ellipse 3 Center X (0x00000058) + * + *****************************************************************************/ +/* Slice: ellip3_cen_x:*/ +/* Ellipse 3 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP3_CEN_X +#endif /* ISP_AWB_ELLIP3_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_cen_y: Ellipse 3 Center Y (0x0000005c) + * + *****************************************************************************/ +/* Slice: ellip3_cen_y:*/ +/* Ellipse 3 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP3_CEN_Y +#endif /* ISP_AWB_ELLIP3_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_cen_x: Ellipse 4 Center X (0x00000060) + * + *****************************************************************************/ +/* Slice: ellip4_cen_x:*/ +/* Ellipse 4 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP4_CEN_X +#endif /* ISP_AWB_ELLIP4_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_cen_y: Ellipse 4 Center Y (0x00000064) + * + *****************************************************************************/ +/* Register: awb_meas_ellip4_cen_y: Ellipse 4 Center Y (0x00000064)*/ +/* Slice: ellip4_cen_y:*/ +/* Ellipse 4 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP4_CEN_Y +#endif /* ISP_AWB_ELLIP4_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_cen_x: Ellipse 5 Center X (0x00000068) + * + *****************************************************************************/ +/* Slice: ellip5_cen_x:*/ +/* Ellipse 5 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP5_CEN_X +#endif /* ISP_AWB_ELLIP5_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_cen_y: Ellipse 5 Center Y (0x0000006c) + * + *****************************************************************************/ +/* Slice: ellip5_cen_y:*/ +/* Ellipse 5 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP5_CEN_Y +#endif /* ISP_AWB_ELLIP5_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_cen_x: Ellipse 6 Center X (0x00000070) + * + *****************************************************************************/ +/* Slice: ellip6_cen_x:*/ +/* Ellipse 6 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP6_CEN_X +#endif /* ISP_AWB_ELLIP6_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_cen_y: Ellipse 6 Center Y (0x00000074) + * + *****************************************************************************/ +/* Slice: ellip6_cen_y:*/ +/* Ellipse 6 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP6_CEN_Y +#endif /* ISP_AWB_ELLIP6_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_cen_x: Ellipse 7 Center X (0x00000078) + * + *****************************************************************************/ +/* Slice: ellip7_cen_x:*/ +/* Ellipse 7 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP7_CEN_X +#endif /* ISP_AWB_ELLIP7_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_cen_y: Ellipse 7 Center Y (0x0000007c) + * + *****************************************************************************/ +/* Slice: ellip7_cen_y:*/ +/* Ellipse 7 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP7_CEN_Y +#endif /* ISP_AWB_ELLIP7_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_cen_x: Ellipse 8 Center X (0x00000080) + * + *****************************************************************************/ +/* Slice: ellip8_cen_x:*/ +/* Ellipse 8 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP8_CEN_X +#endif /* ISP_AWB_ELLIP8_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_cen_y: Ellipse 8 Center Y (0x00000084) + * + *****************************************************************************/ +/* Slice: ellip8_cen_y:*/ +/* Ellipse 8 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP8_CEN_Y +#endif /* ISP_AWB_ELLIP8_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_a1: Ellipse 1 coefficient a1 (0x00000088) + * + *****************************************************************************/ +/* Slice: ellip1_a1:*/ +/* Ellipse 1 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP1_A1 +#endif /* ISP_AWB_ELLIP1_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_a2: Ellipse 1 coefficient a2 (0x0000008c) + * + *****************************************************************************/ +/* Slice: ellip1_a2:*/ +/* Ellipse 1 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP1_A2 +#endif /* ISP_AWB_ELLIP1_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_a3: Ellipse 1 coefficient a3 (0x00000090) + * + *****************************************************************************/ +/* Slice: ellip1_a3:*/ +/* Ellipse 1 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP1_A3 +#endif /* ISP_AWB_ELLIP1_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_a4: Ellipse 1 coefficient a4 (0x00000094) + * + *****************************************************************************/ +/* Slice: ellip1_a4:*/ +/* Ellipse 1 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP1_A4 +#endif /* ISP_AWB_ELLIP1_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_a1: Ellipse 2 coefficient a1 (0x00000098) + * + *****************************************************************************/ +/* Slice: ellip2_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP2_A1 +#endif /* ISP_AWB_ELLIP2_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_a2: Ellipse 2 coefficient a2 (0x0000009c) + * + *****************************************************************************/ +/* Slice: ellip2_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP2_A2 +#endif /* ISP_AWB_ELLIP2_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_a3: Ellipse 2 coefficient a3 (0x000000a0) + * + *****************************************************************************/ +/* Slice: ellip2_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP2_A3 +#endif /* ISP_AWB_ELLIP2_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_a4: Ellipse 2 coefficient a4 (0x000000a4) + * + *****************************************************************************/ +/* Slice: ellip2_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP2_A4 +#endif /* ISP_AWB_ELLIP2_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_a1: Ellipse 3 coefficient a1 (0x000000a8) + * + *****************************************************************************/ +/* Slice: ellip3_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP3_A1 +#endif /* ISP_AWB_ELLIP3_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_a2: Ellipse 3 coefficient a2 (0x000000ac) + * + *****************************************************************************/ +/* Slice: ellip3_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP3_A2 +#endif /* ISP_AWB_ELLIP3_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_a3: Ellipse 3 coefficient a3 (0x000000b0) + * + *****************************************************************************/ +/* Slice: ellip3_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP3_A3 +#endif /* ISP_AWB_ELLIP3_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_a4: Ellipse 3 coefficient a4 (0x000000b4) + * + *****************************************************************************/ +/* Slice: ellip3_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP3_A4 +#endif /* ISP_AWB_ELLIP3_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_a1: Ellipse 4 coefficient a1 (0x000000b8) + * + *****************************************************************************/ +/* Slice: ellip4_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP4_A1 +#endif /* ISP_AWB_ELLIP4_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_a2: Ellipse 4 coefficient a2 (0x000000bc) + * + *****************************************************************************/ +/* Slice: ellip4_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP4_A2 +#endif /* ISP_AWB_ELLIP4_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_a3: Ellipse 4 coefficient a3 (0x000000c0) + * + *****************************************************************************/ +/* Slice: ellip4_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP4_A3 +#endif /* ISP_AWB_ELLIP4_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_a4: Ellipse 4 coefficient a4 (0x000000c4) + * + *****************************************************************************/ +/* Slice: ellip4_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP4_A4 +#endif /* ISP_AWB_ELLIP4_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_a1: Ellipse 5 coefficient a1 (0x000000c8) + * + *****************************************************************************/ +/* Slice: ellip5_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP5_A1 +#endif /* ISP_AWB_ELLIP5_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_a2: Ellipse 5 coefficient a2 (0x000000cc) + * + *****************************************************************************/ +/* Slice: ellip5_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP5_A2 +#endif /* ISP_AWB_ELLIP5_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_a3: Ellipse 5 coefficient a3 (0x000000d0) + * + *****************************************************************************/ +/* Slice: ellip5_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP5_A3 +#endif /* ISP_AWB_ELLIP5_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_a4: Ellipse 5 coefficient a4 (0x000000d4) + * + *****************************************************************************/ +/* Slice: ellip5_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP5_A4 +#endif /* ISP_AWB_ELLIP5_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_a1: Ellipse 6 coefficient a1 (0x000000d8) + * + *****************************************************************************/ +/* Slice: ellip6_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP6_A1 +#endif /* ISP_AWB_ELLIP6_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_a2: Ellipse 6 coefficient a2 (0x000000dc) + * + *****************************************************************************/ +/* Slice: ellip6_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP6_A2 +#endif /* ISP_AWB_ELLIP6_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_a3: Ellipse 6 coefficient a3 (0x000000e0) + * + *****************************************************************************/ +/* Slice: ellip6_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP6_A3 +#endif /* ISP_AWB_ELLIP6_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_a4: Ellipse 6 coefficient a4 (0x000000e4) + * + *****************************************************************************/ +/* Slice: ellip6_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP6_A4 +#endif /* ISP_AWB_ELLIP6_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_a1: Ellipse 7 coefficient a1 (0x000000e8) + * + *****************************************************************************/ +/* Slice: ellip7_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP7_A1 +#endif /* ISP_AWB_ELLIP7_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_a2: Ellipse 7 coefficient a2 (0x000000ec) + * + *****************************************************************************/ +/* Slice: ellip7_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP7_A2 +#endif /* ISP_AWB_ELLIP7_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_a3: Ellipse 7 coefficient a3 (0x000000f0) + * + *****************************************************************************/ +/* Slice: ellip7_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP7_A3 +#endif /* ISP_AWB_ELLIP7_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_a4: Ellipse 7 coefficient a4 (0x000000f4) + * + *****************************************************************************/ +/* Slice: ellip7_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP7_A4 +#endif /* ISP_AWB_ELLIP7_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_a1: Ellipse 8 coefficient a1 (0x000000f8) + * + *****************************************************************************/ +/* Slice: ellip8_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP8_A1 +#endif /* ISP_AWB_ELLIP8_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_a2: Ellipse 8 coefficient a2 (0x000000fc) + * + *****************************************************************************/ +/* Slice: ellip8_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP8_A2 +#endif /* ISP_AWB_ELLIP8_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_a3: Ellipse 8 coefficient a3 (0x00000100) + * + *****************************************************************************/ +/* Slice: ellip8_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP8_A3 +#endif /* ISP_AWB_ELLIP8_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_a4: Ellipse 8 coefficient a4 (0x00000104) + * + *****************************************************************************/ +/* Slice: ellip8_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP8_A4 +#endif /* ISP_AWB_ELLIP8_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_rmax: Ellipse 1 r_max (0x00000108) + * + *****************************************************************************/ +/* Slice: ellip1_rmax:*/ +/* Ellipse 1 max radius square compare value */ +#ifdef ISP_AWB_ELLIP1_RMAX +#endif /* ISP_AWB_ELLIP1_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_rmax: Ellipse 2 r_max (0x0000010c) + * + *****************************************************************************/ +/* Slice: ellip2_rmax:*/ +/* Ellipse 2 max radius square compare value */ +#ifdef ISP_AWB_ELLIP2_RMAX +#endif /* ISP_AWB_ELLIP2_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_rmax: Ellipse 3 r_max (0x00000110) + * + *****************************************************************************/ +/* Slice: ellip3_rmax:*/ +/* Ellipse 3 max radius square compare value */ +#ifdef ISP_AWB_ELLIP3_RMAX +#endif /* ISP_AWB_ELLIP3_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_rmax: Ellipse 4 r_max (0x00000114) + * + *****************************************************************************/ +/* Slice: ellip4_rmax:*/ +/* Ellipse 4 max radius square compare value */ +#ifdef ISP_AWB_ELLIP4_RMAX +#endif /* ISP_AWB_ELLIP4_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_rmax: Ellipse 5 r_max (0x00000118) + * + *****************************************************************************/ +/* Slice: ellip5_rmax:*/ +/* Ellipse 5 max radius square compare value */ +#ifdef ISP_AWB_ELLIP5_RMAX +#endif /* ISP_AWB_ELLIP5_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_rmax: Ellipse 6 r_max (0x0000011c) + * + *****************************************************************************/ +/* Slice: ellip6_rmax:*/ +/* Ellipse 6 max radius square compare value */ +#ifdef ISP_AWB_ELLIP6_RMAX +#endif /* ISP_AWB_ELLIP6_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_rmax: Ellipse 7 r_max (0x00000120) + * + *****************************************************************************/ +/* Slice: ellip7_rmax:*/ +/* Ellipse 7 max radius square compare value */ +#ifdef ISP_AWB_ELLIP7_RMAX +#endif /* ISP_AWB_ELLIP7_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_rmax: Ellipse 8 r_max (0x00000124) + * + *****************************************************************************/ +/* Slice: ellip8_rmax:*/ +/* Ellipse 8 max radius square compare value */ +#ifdef ISP_AWB_ELLIP8_RMAX +#endif /* ISP_AWB_ELLIP8_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_1: AWB Counter 1 (0x00000128) + * + *****************************************************************************/ +/* Slice: count_1:*/ +/* counted Pixels of Ellipse 1 */ +#ifdef ISP_AWB_COUNT_1 +#endif /* ISP_AWB_COUNT_1 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_2: AWB Counter 2 (0x0000012c) + * + *****************************************************************************/ +/* Slice: count_2:*/ +/* counted Pixels of Ellipse 2 */ +#ifdef ISP_AWB_COUNT_2 +#endif /* ISP_AWB_COUNT_2 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_3: AWB Counter 3 (0x00000130) + * + *****************************************************************************/ +/* Slice: count_3:*/ +/* counted Pixels of Ellipse 3 */ +#ifdef ISP_AWB_COUNT_3 +#endif /* ISP_AWB_COUNT_3 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_4: AWB Counter 4 (0x00000134) + * + *****************************************************************************/ +/* Slice: count_4:*/ +/* counted Pixels of Ellipse 4 */ +#ifdef ISP_AWB_COUNT_4 +#endif /* ISP_AWB_COUNT_4 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_5: AWB Counter 5 (0x00000138) + * + *****************************************************************************/ +/* Slice: count_5:*/ +/* counted Pixels of Ellipse 5 */ +#ifdef ISP_AWB_COUNT_5 +#endif /* ISP_AWB_COUNT_5 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_6: AWB Counter 6 (0x0000013c) + * + *****************************************************************************/ +/* Slice: count_6:*/ +/* counted Pixels of Ellipse 6 */ +#ifdef ISP_AWB_COUNT_6 +#endif /* ISP_AWB_COUNT_6 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_7: AWB Counter 7 (0x00000140) + * + *****************************************************************************/ +/* Slice: count_7:*/ +/* counted Pixels of Ellipse 7 */ +#ifdef ISP_AWB_COUNT_7 +#endif /* ISP_AWB_COUNT_7 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_8: AWB Counter 8 (0x00000144) + * + *****************************************************************************/ +/* Slice: count_8:*/ +/* counted Pixels of Ellipse 8 */ +#ifdef ISP_AWB_COUNT_8 +#endif /* ISP_AWB_COUNT_8 */ +/*****************************************************************************/ +/** + * register array: awb_meas_accu: AWB Accu Read (0x298 + n*0x4 (n=0..23)) + * + *****************************************************************************/ +/* Slice: read_accu:*/ +/* measured sum[34:3] of RGB values.*/ +#ifdef ISP_AWB_READ_ACCU +#endif /* ISP_AWB_READ_ACCU */ +#ifdef EE_CTRL_ENABLE +#define EE_CTRL_ENABLE_SET 1 +#define EE_CTRL_ENABLE_CLEAR 0 +#endif +/*****************************************************************************/ +/** + * register array: awb_meas_accu: AWB Accu Read (0x298 + n*0x4 (n=0..23)) + * + *****************************************************************************/ +/* Slice: read_accu:*/ +/* measured sum[34:3] of RGB values.*/ +#ifdef ISP_VSM_DELTA_H +#endif /* ISP_AWB_READ_ACCU */ +/*****************************************************************************/ +/** + * register: isp_vsm_h_offs: VSM window horizontal offset + * + *****************************************************************************/ +/* Slice: vsm_h_offset:*/ +/* Horizontal offset in pixels.*/ +#ifdef ISP_VSM_H_OFFSET +#define ISP_VSM_H_OFFSET_MAX (ISP_VSM_H_OFFSET_MASK >> ISP_VSM_H_OFFSET_SHIFT) +#endif /* ISP_VSM_H_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_vsm_v_offs: VSM window vertical offset + * + *****************************************************************************/ +/* Slice: vsm_v_offset:*/ +/* Vertical offset in pixels.*/ +#ifdef ISP_VSM_V_OFFSET +#define ISP_VSM_V_OFFSET_MAX (ISP_VSM_V_OFFSET_MASK >> ISP_VSM_V_OFFSET_SHIFT) +#endif /* ISP_VSM_V_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_vsm_h_size: Horizontal measure window size + * + *****************************************************************************/ +/* Slice: vsm_h_size:*/ +/* Horizontal size in pixels..*/ +#ifdef ISP_VSM_H_SIZE +/* note: do not apply shift, since bit 0 is only excluded to get even values */ +#define ISP_VSM_H_SIZE_MAX ISP_VSM_H_SIZE_MASK +#endif /* ISP_VSM_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_vsm_v_size: Vertical measure window size + * + *****************************************************************************/ +/* Slice: vsm_v_size:*/ +/* Vertical size in pixels.*/ +#ifdef ISP_VSM_V_SIZE +/* note: do not apply shift, since bit 0 is only excluded to get even values */ +#define ISP_VSM_V_SIZE_MAX ISP_VSM_V_SIZE_MASK +#endif /* ISP_VSM_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_vsm_h_segments: Iteration 1 horizontal segments + * + *****************************************************************************/ +/* Slice: vsm_h_segments:*/ +/* number of 16 point wide segments enclosed by the first iteration sample */ +/* points in horizontal direction. Range: 1 ... 128 */ +#ifdef ISP_VSM_H_SEGMENTS +#define ISP_VSM_H_SEGMENTS_MIN 1 +#define ISP_VSM_H_SEGMENTS_MAX 128 +#endif /* ISP_VSM_H_SEGMENTS */ +/*****************************************************************************/ +/** + * register: isp_vsm_v_segments: Iteration 1 vertical segments + * + *****************************************************************************/ +/* Slice: vsm_v_segments:*/ +/* number of 16 point wide segments enclosed by the first iteration sample */ +/* points in vertical direction. Range: 1 ... 128 */ +/* Note: number of 1st iteration sample points = vsm_v_segments + 1.*/ +/* vsm_v_segments must be equal or smaller than vsm_h_segments.*/ +#ifdef ISP_VSM_V_SEGMENTS +#define ISP_VSM_V_SEGMENTS_MIN 1 +#define ISP_VSM_V_SEGMENTS_MAX 128 +#endif /* ISP_VSM_V_SEGMENTS */ +#ifdef ISP_GCMONO +/*****************************************************************************/ +/** + * register: isp_gcmono_ctrl: gcmono enable and lut table cfg + * + *****************************************************************************/ +/*! Slice: mono_gc_enable */ +/*! Control of gamma correction for mono sensor RAW data */ +/*! 1'b0: disable GC and enter bypass mode */ +/*! 1'b1: enable GC mode */ +#ifdef ISP_GCMONO_SWITCH +#define ISP_GCMONO_SWITCH_DISABLE 0 /* 0: disable GC */ +#define ISP_GCMONO_SWITCH_ENABLE 1 /* 1: enable GC */ +#endif +/*! Slice: mono_gc_cfg_done */ +/*! To notify the ISP HW the LUT configuration is done, ready to use, active high.*/ +/*! Writing ZERO reset teh internal read/write pointer and also indicates that the LUT can be configured or read from CPU.*/ +#ifdef ISP_GCMONO_CFG_DONE +#define ISP_GCMONO_CFG_DONE_CURVE_READY 1 /* 1: notify ISP HW LUT configuration is done */ +#define ISP_GCMONO_CFG_DONE_SET_CURVE 0 /* 0: Write ZERO reset the internal pointer and can cfg LUT. */ +#endif +#ifdef ISP_GCMONO_PARA_BASE +#endif +#endif +/*****************************************************************************/ +/* MIV2 Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: miv2_mp_fmt: main path pixel format control register (0x1314) + * + *****************************************************************************/ +// Slice: MP_WR_JDP_FMT +// 1: JPEG +// 0: DPCC +#ifdef MP_WR_JDP_FMT +#define MIV2_MP_WRITE_FORMAT_DPCC 0 //DPCC +#define MIV2_MP_WRITE_FORMAT_JPEG 1 //JPEG +#endif /* MP_WR_JDP_FMT */ +// Slice: MP_WR_YUV_BIT: +// 1: 10bit YUV/RGB +// 0: 8bit YUV/RGB +#ifdef MP_WR_YUV_BIT +#define MIV2_MP_WRITE_FORMAT_8BIT 0 //8bit YUV/RGB +#define MIV2_MP_WRITE_FORMAT_10BIT 1 //10bit YUV/RGB +#endif /* MP_WR_YUV_BIT */ +// Slice: MP_WR_YUV_FMT: +#ifdef MP_WR_YUV_FMT +#define MIV2_MP_WRITE_FORMAT_YUV420 0 // 00: YUV420 +#define MIV2_MP_WRITE_FORMAT_YUV422 1 // 01: YUV422 +#define MIV2_MP_WRITE_FORMAT_YUV444 2 // 10: YUV444 +#endif /* MP_WR_YUV_FMT */ +// Slice: MP_WR_YUV_STR: +#ifdef MP_WR_YUV_STR +#define MIV2_MP_WRITE_STRIDE_SEMIPLANAR 0 // 00: YUV/RGB SemiPlanar +#define MIV2_MP_WRITE_STRIDE_INTERLEAVE 1 // 01: YUV Interleave, RGB Raster +#define MIV2_MP_WRITE_STRIDE_PLANAR 2 // 10: YUV/RGB Planar +#endif /* MP_WR_YUV_STR */ +// Slice: MP_WR_RAW_BIT: +#ifdef MP_WR_RAW_BIT +#define MIV2_MP_WRITE_FORMAT_RAW8 0 // 000: RAW8 +#define MIV2_MP_WRITE_FORMAT_RAW10 1 // 001: RAW10 +#define MIV2_MP_WRITE_FORMAT_RAW12 2 // 010: RAW12 +#define MIV2_MP_WRITE_FORMAT_RAW14 3 // 011: RAW14 +#define MIV2_MP_WRITE_FORMAT_RAW16 4 // 100: RAW16 +#define MIV2_MP_WRITE_FORMAT_RAW20 5 // 101: RAW20 +#endif /* MP_WR_RAW_BIT */ +// Slice: MP_WR_YUV_ALIGNED +// 1: aligned +// 0: unaligned +#ifdef MP_WR_YUV_ALIGNED +#define MIV2_MP_WRITE_YUV_UNALIGNED 0 //unaligned +#define MIV2_MP_WRITE_YUV_ALIGNED 1 //aligned +#endif /* MP_WR_YUV_ALIGNED */ +// Slice: MP_WR_RAW_ALIGNED: +#ifdef MP_WR_RAW_ALIGNED +#define MIV2_MP_WRITE_RAW_UNALIGNED 0 // 00: unaligned +#define MIV2_MP_WRITE_RAW_ALIGNED_MODE1 1 // 01: aligned mode1 +#define MIV2_MP_WRITE_RAW_ALIGNED_MODE2 2 // 10: aligned mode2 +#endif /* MP_WR_RAW_ALIGNED */ +// Slice: MP_WR_YUV_NV21 +// 1: Put U before V +// 0: Put V before U +#ifdef MP_WR_YUV_NV21 +#define MIV2_MP_WRITE_YUV_NV21_UV 0 //Put U before V +#define MIV2_MP_WRITE_YUV_NV21_VU 1 //Put V before U +#endif /* MP_WR_YUV_NV21 */ +// Slice: MP_WR_YUV_NVY: +#ifdef MP_WR_YUV_NVY +#define MIV2_MP_WRITE_YUV_NVY_YC1C2 0 // 00: Put Y first => YC1C2 +#define MIV2_MP_WRITE_YUV_NVY_C1YC2 1 // 01: Put Y second => C1YC2 +#define MIV2_MP_WRITE_YUV_NVY_C1C2Y 2 // 10: Put Y Third => C1C2Y +#endif /* MP_WR_YUV_NVY */ +// ========================================================================================= +#ifdef ISP_DEMOSAIC_DENOISE_STRENGTH +#define ISP_DEMOSAIC_DENOISE_STRENGTH_MIN 0 +#define ISP_DEMOSAIC_DENOISE_STRENGTH_MAX 32 +#endif +#ifdef ISP_DEMOSAIC_SHARPEN_SIZE +#define ISP_DEMOSAIC_SHARPEN_SIZE_MIN 0 +#define ISP_DEMOSAIC_SHARPEN_SIZE_MAX 16 +#endif +#ifdef ISP_DMSC_DEMOIRE_AREA_THR +#define ISP_DMSC_DEMOIRE_AREA_THR_MIN 0 +#define ISP_DMSC_DEMOIRE_AREA_THR_MAX 32 +#endif +#ifdef ISP_DMSC_DEMOIRE_SAT_SHRINK +#define ISP_DMSC_DEMOIRE_SAT_SHRINK_MIN 0 +#define ISP_DMSC_DEMOIRE_SAT_SHRINK_MAX 32 +#endif +#ifdef ISP_DMSC_SHARPEN_T4_SHIFT +#define ISP_DMSC_SHARPEN_SHIFT_MIN 0 +#define ISP_DMSC_SHARPEN_SHIFT_MAX 11 +#endif +#ifdef ISP_DMSC_SHARPEN_LINE_SHIFT1 +#define ISP_DMSC_SHARPEN_LINE_SHIFT1_MIN 0 +#define ISP_DMSC_SHARPEN_LINE_SHIFT1_MAX 10 +#endif +#ifdef ISP_DMSC_HF_FILT_00 +#define ISP_DMSC_HF_FILT_MIN 0 +#define ISP_DMSC_HF_FILT_MAX 34 +#endif +#ifdef ISP_DMSC_CBCR_MODE +#define ISP_DMSC_CBCR_MODE_MIN 0 +#define ISP_DMSC_CBCR_MODE_MAX 3 +#endif +#ifdef ISP_DMSC_DEPURPLE_SAT_SHRINK +#define ISP_DMSC_DEPURPLE_SAT_SHRINK_MIN 0 +#define ISP_DMSC_DEPURPLE_SAT_SHRINK_MAX 8 +#endif +#ifdef ISP_DMSC_X_NF +#define ISP_DMSC_X_NF_MIN 0 +#define ISP_DMSC_X_NF_MAX 31 +#endif +#ifdef ISP_DMSC_X_NS +#define ISP_DMSC_X_NS_MIN 0 +#define ISP_DMSC_X_NS_MAX 15 +#endif +#ifdef ISP_DMSC_Y_NF +#define ISP_DMSC_Y_NF_MIN 0 +#define ISP_DMSC_Y_NF_MAX 31 +#endif +#ifdef ISP_DMSC_Y_NS +#define ISP_DMSC_Y_NS_MIN 0 +#define ISP_DMSC_Y_NS_MAX 15 +#endif +/* =========================================================================================*/ +/*! returns the value of slice \a name from register or variable \a reg + * \note "parameter" \a reg could be a hardware register or a (32bit) variable, but not a pointer! \n + * each slice (specified as "parameter" \a name) requires two \#defines: \n + * - \_MASK : defines the mask to use on register side + * - \_SHIFT : defines the shift value to use (left on write, right on read) + */ +#define REG_GET_SLICE(reg, name) \ + (((reg) & (name##_MASK)) >> (name##_SHIFT)) +/* =========================================================================================*/ +/*! writes the value \a value into slice \a name of register or variable \a reg + * \note "parameter" \a reg could be a hardware register or a (32bit) variable, but not a pointer! \n + * each slice (specified as "parameter" \a name) requires two \#defines: \n + * - \_MASK : defines the mask to use on register side + * - \_SHIFT : defines the shift value to use (left on write, right on read) + */ +#define REG_SET_SLICE(reg, name, value) \ + { \ + ((reg) = (((reg) & ~(name##_MASK)) | (((value) << (name##_SHIFT)) & (name##_MASK))));\ + } +#endif /* __MRV_ALL_BITS_H__ */ diff --git a/vvcam/isp/mrv_all_regs.h b/vvcam/isp/mrv_all_regs.h new file mode 100755 index 0000000..f1cdf5e --- /dev/null +++ b/vvcam/isp/mrv_all_regs.h @@ -0,0 +1,20364 @@ +/***************************************************************************** + * + * Copyright 2013, Dream Chip Technologies GmbH. All rights reserved. + * + **************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +/* +* NOTE: This file is automaticaly generated by sig of theflow Rev.: 1.1_dev_koehler. +* Modifications can be lost. +* +*****************************************************************************/ +/** +*----------------------------------------------------------------------------- +* $HeadURL$ +* $Author$ +* $Rev$ +* $Date$ +*----------------------------------------------------------------------------- +* @file mrv_all_regs.h +* +* 
+*
+* Description:
+*   This header file exports the module register structure and masks.
+*	It should not be included directly by your driver/application, it will be
+*   exported by the _regs_io.h header file.
+*
+*
+*/ +/*****************************************************************************/ + +#ifndef _MRV_ALL_REGS_H +#define _MRV_ALL_REGS_H + +/* Definitions of block register sizes */ +#define DEGAMMA_R_Y_BLOCK_ARR_SIZE 17 +#define DEGAMMA_G_Y_BLOCK_ARR_SIZE 17 +#define DEGAMMA_B_Y_BLOCK_ARR_SIZE 17 +#define CROSS_TALK_COEF_BLOCK_ARR_SIZE 9 +#define GAMMA_OUT_Y_BLOCK_ARR_SIZE 17 +#define HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE 16 +#define NLF_LOOKUP_TABLE_BLOCK_ARR_SIZE 17 +#define WDR_TONE_MAPPING_CURVE_Y_BLOCK_ARR_SIZE 33 +#define WDR_TONE_MAPPING_CURVE_Y_SHD_BLOCK_ARR_SIZE 33 +#define AWB_MEAS_ACCU_ARR_SIZE 24 +#define ISP64_HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE 32 +#define ISP_HDREXP_MEASUREMENT_RESULT_ARR_SIZE 25 + +/*! degamma_r_y_block register layout */ +typedef struct { + uint32_t isp_gamma_r_y; /*!< De-Gamma Curve definition y red (rw) MRV_ISP_BASE + 0x448 + (n*0x4) (n=0..16) */ +} degamma_r_y_block_t; + +/*! degamma_g_y_block register layout */ +typedef struct { + uint32_t isp_gamma_g_y; /*!< De-Gamma Curve definition y green (rw) MRV_ISP_BASE + 0x490 + (n*0x4) (n=0..16) */ +} degamma_g_y_block_t; + +/*! degamma_b_y_block register layout */ +typedef struct { + uint32_t isp_gamma_b_y; /*!< De-Gamma Curve definition y blue (rw) MRV_ISP_BASE + 0x4D8 + (n*0x4) (n=0..16) */ +} degamma_b_y_block_t; + +/*! cross_talk_coef_block register layout */ +typedef struct { + uint32_t isp_ct_coeff; /*!< cross-talk configuration register (color correction matrix) (rw) MRV_ISP_BASE + 0x7A0 + (n*0x4) (n=0..8) */ +} cross_talk_coef_block_t; + +/*! gamma_out_y_block register layout */ +typedef struct { + uint32_t isp_gamma_out_y; /*!< Gamma Out Curve definition y_ (rw) MRV_ISP_BASE + 0x7F0 + (n*0x4) (n=0..16) */ +} gamma_out_y_block_t; + +/*! histogram_measurement_result register layout */ +typedef struct { + uint32_t isp_hist_bin; /*!< histogram measurement result bin (r) MRV_HIST_BASE + 0x2428 + (n*0x4) (n=0..15) */ +} histogram_measurement_result_t; + +/*! nlf_lookup_table_block register layout */ +typedef struct { + uint32_t isp_dpf_nll_coeff; /*!< Noise Level Lookup Coefficient (rw) MRV_DPF_BASE + 0x2840 + (n*0x4) (n=0..16) */ +} nlf_lookup_table_block_t; + +/*! wdr_tone_mapping_curve_y_block register layout */ +typedef struct { + uint32_t isp_wdr_tonecurve_ym; /*!< Tonemapping curve coefficient Ym_ (rw) MRV_WDR_BASE + 0x2A28 + (n*0x4) (n=0..32) */ +} wdr_tone_mapping_curve_y_block_t; + +/*! wdr_tone_mapping_curve_y_shd_block register layout */ +typedef struct { + uint32_t isp_wdr_tonecurve_ym_shd; /*!< Tonemapping curve coefficient shadow register (r) MRV_WDR_BASE + 0x2B60 + (n*0x4) (n=0..32) */ +} wdr_tone_mapping_curve_y_shd_block_t; + +/*! AWB_MEAS_ACCU register layout */ +typedef struct { + uint32_t awb_meas_accu; /*!< AWB Accu Read (r) ISP_AWB_BASE + 0x2E90 + (n*0x4) (n=0..23) */ +} AWB_MEAS_ACCU_t; + +/*! isp64_histogram_measurement_result register layout */ +typedef struct { + uint32_t isp64_hist_bin; /*!< histogram measurement result bin (sh_r) MRV_HIST_BASE + 0x2EA8 + (n*0x4) (n=0..31) */ +} isp64_histogram_measurement_result_t; + +typedef struct { + uint32_t x, y; +} elawb_ellipse_pt; + +typedef struct { + uint32_t a1, a2, a3, a4; +} elawb_ellipse_axis; + +/*! MrvAll Register layout */ +typedef struct { + uint32_t vi_ccl; /*!< Clock control register (rw) MRV_BASE + 0x00000000 */ + uint32_t _notused_0[(0x00000008 - 0x00000004) / 4]; /* gap in address space */ + uint32_t vi_id; /*!< Revision identification register (r) MRV_BASE + 0x00000008 */ + uint32_t _notused_1[(0x00000010 - 0x0000000c) / 4]; /* gap in address space */ + uint32_t vi_iccl; /*!< Internal clock control register (rw) MRV_BASE + 0x00000010 */ + uint32_t vi_ircl; /*!< Internal reset control register (rw) MRV_BASE + 0x00000014 */ + uint32_t vi_dpcl; /*!< Data path control register (rw) MRV_BASE + 0x00000018 */ + uint32_t _notused_2[(0x00000200 - 0x0000001c) / 4]; /* gap in address space */ + uint32_t img_eff_ctrl; /*!< Global control register (rw) MRV_IMGEFF_BASE + 0x00000000 */ + uint32_t img_eff_color_sel; /*!< Color selection register (for color selection effect) (rw) MRV_IMGEFF_BASE + 0x00000004 */ + uint32_t img_eff_mat_1; /*!< 3x3 matrix coefficients for emboss effect (1) (rw) MRV_IMGEFF_BASE + 0x00000008 */ + uint32_t img_eff_mat_2; /*!< 3x3 matrix coefficients for emboss effect (2) (rw) MRV_IMGEFF_BASE + 0x0000000c */ + uint32_t img_eff_mat_3; /*!< 3x3 matrix coefficients for emboss(3) effect / sketch/sharpen(1) effect (rw) MRV_IMGEFF_BASE + 0x00000010 */ + uint32_t img_eff_mat_4; /*!< 3x3 matrix coefficients for sketch/sharpen effect (2) (rw) MRV_IMGEFF_BASE + 0x00000014 */ + uint32_t img_eff_mat_5; /*!< 3x3 matrix coefficients for sketch/sharpen effect (3) (rw) MRV_IMGEFF_BASE + 0x00000018 */ + uint32_t img_eff_tint; /*!< Chrominance increment values of a tint (used for sepia effect) (rw) MRV_IMGEFF_BASE + 0x0000001c */ + uint32_t img_eff_ctrl_shd; /*!< Shadow register for control register (r) MRV_IMGEFF_BASE + 0x00000020 */ + uint32_t img_eff_sharpen; /*!< Factor and threshold for sharpen effect (rw) MRV_IMGEFF_BASE + 0x00000024 */ + uint32_t _notused_3[(0x00000300 - 0x00000228) / 4]; /* gap in address space */ + uint32_t super_imp_ctrl; /*!< Global control register (rw) MRV_SI_BASE + 0x00000000 */ + uint32_t super_imp_offset_x; /*!< Offset x register (rw) MRV_SI_BASE + 0x00000004 */ + uint32_t super_imp_offset_y; /*!< Offset y register (rw) MRV_SI_BASE + 0x00000008 */ + uint32_t super_imp_color_y; /*!< Y component of transparent key color (rw) MRV_SI_BASE + 0x0000000c */ + uint32_t super_imp_color_cb; /*!< Cb component of transparent key color (rw) MRV_SI_BASE + 0x00000010 */ + uint32_t super_imp_color_cr; /*!< Cr component of transparent key color (rw) MRV_SI_BASE + 0x00000014 */ + uint32_t _notused_4[(0x00000400 - 0x00000318) / 4]; /* gap in address space */ + uint32_t isp_ctrl; /*!< global control register (rw) MRV_ISP_BASE + 0x00000000 */ + uint32_t isp_acq_prop; /*!< ISP acquisition properties (rw) MRV_ISP_BASE + 0x00000004 */ + uint32_t isp_acq_h_offs; /*!< horizontal input offset (rw) MRV_ISP_BASE + 0x00000008 */ + uint32_t isp_acq_v_offs; /*!< vertical input offset (rw) MRV_ISP_BASE + 0x0000000c */ + uint32_t isp_acq_h_size; /*!< horizontal input size (rw) MRV_ISP_BASE + 0x00000010 */ + uint32_t isp_acq_v_size; /*!< vertical input size (rw) MRV_ISP_BASE + 0x00000014 */ + uint32_t isp_acq_nr_frames; /*!< Number of frames to be captured (rw) MRV_ISP_BASE + 0x00000018 */ + uint32_t isp_gamma_dx_lo; /*!< De-Gamma Curve definition lower x increments (sampling points) (rw) MRV_ISP_BASE + 0x0000001c */ + uint32_t isp_gamma_dx_hi; /*!< De-Gamma Curve definition higher x increments (sampling points) (rw) MRV_ISP_BASE + 0x00000020 */ + degamma_r_y_block_t degamma_r_y_block_arr[DEGAMMA_R_Y_BLOCK_ARR_SIZE]; /*!< degamma_r_y_block MRV_ISP_BASE + 36 + (n*0x4) (n=0..16) */ + degamma_g_y_block_t degamma_g_y_block_arr[DEGAMMA_G_Y_BLOCK_ARR_SIZE]; /*!< degamma_g_y_block MRV_ISP_BASE + 104 + (n*0x4) (n=0..16) */ + degamma_b_y_block_t degamma_b_y_block_arr[DEGAMMA_B_Y_BLOCK_ARR_SIZE]; /*!< degamma_b_y_block MRV_ISP_BASE + 172 + (n*0x4) (n=0..16) */ + uint32_t isp_dgain_rb; /*!< (rw) MRV_ISP_BASE + 0x000000f0 */ + uint32_t isp_dgain_g; /*!< (rw) MRV_ISP_BASE + 0x000000f4 */ + uint32_t _notused_5[(0x00000510 - 0x000004f8) / 4]; /* gap in address space */ + uint32_t isp_awb_prop; /*!< Auto white balance properties (rw) MRV_ISP_BASE + 0x00000110 */ + uint32_t isp_awb_h_offs; /*!< Auto white balance horizontal offset of measure window (rw) MRV_ISP_BASE + 0x00000114 */ + uint32_t isp_awb_v_offs; /*!< Auto white balance vertical offset of measure window (rw) MRV_ISP_BASE + 0x00000118 */ + uint32_t isp_awb_h_size; /*!< Auto white balance horizontal window size (rw) MRV_ISP_BASE + 0x0000011c */ + uint32_t isp_awb_v_size; /*!< Auto white balance vertical window size (rw) MRV_ISP_BASE + 0x00000120 */ + uint32_t isp_awb_frames; /*!< Auto white balance mean value over multiple frames (rw) MRV_ISP_BASE + 0x00000124 */ + uint32_t isp_awb_ref; /*!< Auto white balance reference Cb/Cr values (rw) MRV_ISP_BASE + 0x00000128 */ + uint32_t isp_awb_thresh; /*!< Auto white balance threshold values (rw) MRV_ISP_BASE + 0x0000012c */ + uint32_t _notused_6[(0x00000538 - 0x00000530) / 4]; /* gap in address space */ + uint32_t isp_awb_gain_g; /*!< Auto white balance gain green (rw) MRV_ISP_BASE + 0x00000138 */ + uint32_t isp_awb_gain_rb; /*!< Auto white balance gain red and blue (rw) MRV_ISP_BASE + 0x0000013c */ + uint32_t isp_awb_white_cnt; /*!< Auto white balance white pixel count (r) MRV_ISP_BASE + 0x00000140 */ + uint32_t isp_awb_mean; /*!< Auto white balance measured mean value (r) MRV_ISP_BASE + 0x00000144 */ + uint32_t _notused_7[(0x00000570 - 0x00000548) / 4]; /* gap in address space */ + uint32_t isp_cc_coeff_0; /*!< Color conversion coefficient 0 (rw) MRV_ISP_BASE + 0x00000170 */ + uint32_t isp_cc_coeff_1; /*!< Color conversion coefficient 1 (rw) MRV_ISP_BASE + 0x00000174 */ + uint32_t isp_cc_coeff_2; /*!< Color conversion coefficient 2 (rw) MRV_ISP_BASE + 0x00000178 */ + uint32_t isp_cc_coeff_3; /*!< Color conversion coefficient 3 (rw) MRV_ISP_BASE + 0x0000017c */ + uint32_t isp_cc_coeff_4; /*!< Color conversion coefficient 4 (rw) MRV_ISP_BASE + 0x00000180 */ + uint32_t isp_cc_coeff_5; /*!< Color conversion coefficient 5 (rw) MRV_ISP_BASE + 0x00000184 */ + uint32_t isp_cc_coeff_6; /*!< Color conversion coefficient 6 (rw) MRV_ISP_BASE + 0x00000188 */ + uint32_t isp_cc_coeff_7; /*!< Color conversion coefficient 7 (rw) MRV_ISP_BASE + 0x0000018c */ + uint32_t isp_cc_coeff_8; /*!< Color conversion coefficient 8 (rw) MRV_ISP_BASE + 0x00000190 */ + uint32_t isp_out_h_offs; /*!< Horizontal offset of output window (rw) MRV_ISP_BASE + 0x00000194 */ + uint32_t isp_out_v_offs; /*!< Vertical offset of output window (rw) MRV_ISP_BASE + 0x00000198 */ + uint32_t isp_out_h_size; /*!< Output horizontal picture size (rw) MRV_ISP_BASE + 0x0000019c */ + uint32_t isp_out_v_size; /*!< Output vertical picture size (rw) MRV_ISP_BASE + 0x000001a0 */ + uint32_t isp_demosaic; /*!< Demosaic parameters (rw) MRV_ISP_BASE + 0x000001a4 */ + uint32_t isp_flags_shd; /*!< Flags (current status) of certain signals and Shadow regs for enable signals (r) MRV_ISP_BASE + 0x000001a8 */ + uint32_t isp_out_h_offs_shd; /*!< current horizontal offset of output window (shadow register) (r) MRV_ISP_BASE + 0x000001ac */ + uint32_t isp_out_v_offs_shd; /*!< current vertical offset of output window (shadow register) (r) MRV_ISP_BASE + 0x000001b0 */ + uint32_t isp_out_h_size_shd; /*!< current output horizontal picture size (shadow register) (r) MRV_ISP_BASE + 0x000001b4 */ + uint32_t isp_out_v_size_shd; /*!< current output vertical picture size (shadow register) (r) MRV_ISP_BASE + 0x000001b8 */ + uint32_t isp_imsc; /*!< Interrupt mask (rw) MRV_ISP_BASE + 0x000001bc */ + uint32_t isp_ris; /*!< Raw interrupt status (r) MRV_ISP_BASE + 0x000001c0 */ + uint32_t isp_mis; /*!< Masked interrupt status (r) MRV_ISP_BASE + 0x000001c4 */ + uint32_t isp_icr; /*!< Interrupt clear register (w) MRV_ISP_BASE + 0x000001c8 */ + uint32_t isp_isr; /*!< Interrupt set register (w) MRV_ISP_BASE + 0x000001cc */ + cross_talk_coef_block_t cross_talk_coef_block_arr[CROSS_TALK_COEF_BLOCK_ARR_SIZE]; /*!< cross_talk_coef_block MRV_ISP_BASE + 464 + (n*0x4) (n=0..8) */ + uint32_t isp_gamma_out_mode; /*!< gamma segmentation mode register for output gamma (rw) MRV_ISP_BASE + 0x000001f4 */ + gamma_out_y_block_t gamma_out_y_block_arr[GAMMA_OUT_Y_BLOCK_ARR_SIZE]; /*!< gamma_out_y_block MRV_ISP_BASE + 504 + (n*0x4) (n=0..16) */ + uint32_t isp_err; /*!< ISP error register (r) MRV_ISP_BASE + 0x0000023c */ + uint32_t isp_err_clr; /*!< ISP error clear register (w) MRV_ISP_BASE + 0x00000240 */ + uint32_t isp_frame_count; /*!< Frame counter (r) MRV_ISP_BASE + 0x00000244 */ + uint32_t isp_ct_offset_r; /*!< cross-talk offset red (rw) MRV_ISP_BASE + 0x00000248 */ + uint32_t isp_ct_offset_g; /*!< cross-talk offset green (rw) MRV_ISP_BASE + 0x0000024c */ + uint32_t isp_ct_offset_b; /*!< cross-talk offset blue (rw) MRV_ISP_BASE + 0x00000250 */ + uint32_t isp_cnr_linesize; /*!< chroma noise reduction line size (rw) MRV_ISP_BASE + 0x00000254 */ + uint32_t isp_cnr_threshold_c1; /*!< chroma noise reduction C1 Threshold (rw) MRV_ISP_BASE + 0x00000258 */ + uint32_t isp_cnr_threshold_c2; /*!< chroma noise reduction C2 Threshold (rw) MRV_ISP_BASE + 0x0000025c */ + uint32_t isp_flash_cmd; /*!< Flash command (w) MRV_FLASH_BASE + 0x00000000 */ + uint32_t isp_flash_config; /*!< Flash config (rw) MRV_FLASH_BASE + 0x00000004 */ + uint32_t isp_flash_prediv; /*!< Flash Counter Pre-Divider (rw) MRV_FLASH_BASE + 0x00000008 */ + uint32_t isp_flash_delay; /*!< Flash Delay (rw) MRV_FLASH_BASE + 0x0000000c */ + uint32_t isp_flash_time; /*!< Flash time (rw) MRV_FLASH_BASE + 0x00000010 */ + uint32_t isp_flash_maxp; /*!< Maximum value for flash or preflash (rw) MRV_FLASH_BASE + 0x00000014 */ + uint32_t _notused_8[(0x00000680 - 0x00000678) / 4]; /* gap in address space */ + uint32_t isp_sh_ctrl; /*!< mechanical shutter control (rw) MRV_SHUT_BASE + 0x00000000 */ + uint32_t isp_sh_prediv; /*!< Mech. Shutter Counter Pre-Divider (rw) MRV_SHUT_BASE + 0x00000004 */ + uint32_t isp_sh_delay; /*!< Delay register (rw) MRV_SHUT_BASE + 0x00000008 */ + uint32_t isp_sh_time; /*!< Time register (rw) MRV_SHUT_BASE + 0x0000000c */ + + /* TPG */ + uint32_t _notused_pre_tpg[(0x00000700 - 0x00000690) / 4]; /* gap in address space */ + + uint32_t isp_tpg_ctrl; /*!<(rw), 0x00000700 */ + uint32_t isp_tpg_total_in; /*!<(rw), 0x00000704 */ + uint32_t isp_tpg_act_in; /*!<(rw), 0x00000708 */ + uint32_t isp_tpg_fp_in; /*!<(rw), 0x0000070C */ + uint32_t isp_tpg_bp_in; /*!<(rw), 0x00000710 */ + uint32_t isp_tpg_w_in; /*!<(rw), 0x00000714 */ + uint32_t isp_tpg_gap_in; /*!<(rw), 0x00000718 */ + uint32_t isp_tpg_gap_std_in; /*!<(rw), 0x0000071C */ + uint32_t isp_tpg_random_seed; /*!<(rw), 0x00000720 */ + uint32_t _notused_mid_tpg1[(0x00000730 - 0x00000724) / 4]; /* gap in address space */ + uint32_t isp_vsync_delay; /*!<(rw), 0x00000730 */ + uint32_t _notused_mid_tpg2[(0x00000750 - 0x00000734) / 4]; /* gap in address space */ + uint32_t green_equilibrate_ctrl; /*!<(rw), 0x00000750 */ + uint32_t green_equilibrate_hcnt_dummy; /*!<(rw), 0x00000754 */ + uint32_t green_equilibrate_ctrl_shd; /*!<(rw), 0x00000758 */ + + uint32_t _notused_after_tpg[(0x00000800 - 0x0000075c) / 4]; /* gap in address space */ + /* uint32_t _notused_9[(0x00000800-0x00000690)/4]; gap in address space */ + + uint32_t cproc_ctrl; /*!< Global control register (rw) MRV_CPROC_BASE + 0x00000000 */ + uint32_t cproc_contrast; /*!< Color Processing contrast register (rw) MRV_CPROC_BASE + 0x00000004 */ + uint32_t cproc_brightness; /*!< Color Processing brightness register (rw) MRV_CPROC_BASE + 0x00000008 */ + uint32_t cproc_saturation; /*!< Color Processing saturation register (rw) MRV_CPROC_BASE + 0x0000000c */ + uint32_t cproc_hue; /*!< Color Processing hue register (rw) MRV_CPROC_BASE + 0x00000010 */ +#ifdef ISP_RGBGC + uint32_t _notused_10_0[(0x00000900 - 0x00000814) / 4]; /* gap in address space */ + uint32_t isp_gcrgb_r_px_0; /*! MI_MP/SP_Y/CB/CR_OFFS_CNT_SHD */ +/* The update will be executed either when a forced software update occurs (in register MI_INIT bit cfg_upd = 1) or when an automatic config update signal arrives at the MI input port. The latter is split into main and self picture. So only the corresponding main/self shadow registers are affected.*/ +/* After a picture skip has been performed init_offset_en selects between skip restart and skip init mode (see bit skip in register MI_INIT).*/ +#define MRV_MI_INIT_OFFSET_EN +#define MRV_MI_INIT_OFFSET_EN_MASK 0x00200000U +#define MRV_MI_INIT_OFFSET_EN_SHIFT 21U +/*! Slice: init_base_en:*/ +/*! Enables updating of the base address and buffer size shadow registers for main and self picture to the programmed register init values.*/ +/* MI_MP/SP_Y/CB/CR_BASE_AD_INIT */ +/* -> MI_MP/SP_Y/CB/CR_BASE_AD_SHD */ +/* MI_MP/SP_Y/CB/CR_SIZE_INIT */ +/* -> MI_MP/SP_Y/CB/CR_SIZE_SHD */ +/* The update will be executed either when a forced software update occurs (in register MI_INIT bit cfg_upd = 1) or when an automatic config update signal arrives at the MI input port. The latter is split into main and self picture. So only the corresponding main/self shadow registers are affected.*/ +#define MRV_MI_INIT_BASE_EN +#define MRV_MI_INIT_BASE_EN_MASK 0x00100000U +#define MRV_MI_INIT_BASE_EN_SHIFT 20U +/*! Slice: burst_len_chrom:*/ +/*! Burst length for Cb or Cr data affecting write port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported. If rotation is active, then only 4-beat bursts will be generated in self path, regardless of the setting here.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/ +#define MRV_MI_BURST_LEN_CHROM +#define MRV_MI_BURST_LEN_CHROM_MASK 0x000C0000U +#define MRV_MI_BURST_LEN_CHROM_SHIFT 18U +/*! Slice: burst_len_lum:*/ +/*! Burst length for Y, JPEG, or raw data affecting write port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/ +#define MRV_MI_BURST_LEN_LUM +#define MRV_MI_BURST_LEN_LUM_MASK 0x00030000U +#define MRV_MI_BURST_LEN_LUM_SHIFT 16U +/*! Slice: last_pixel_sig_en:*/ +/*! enables the last pixel signalization */ +/* 1: enabled */ +/* 0: disabled */ +#define MRV_MI_LAST_PIXEL_SIG_EN +#define MRV_MI_LAST_PIXEL_SIG_EN_MASK 0x00008000U +#define MRV_MI_LAST_PIXEL_SIG_EN_SHIFT 15U +/*! Slice: sp_auto_update:*/ +/*! automatic update of configuration registers for self path at frame end.*/ +/* 1: enabled */ +/* 0: disabled */ +#define MRV_MI_SP_AUTO_UPDATE +#define MRV_MI_SP_AUTO_UPDATE_MASK 0x00004000U +#define MRV_MI_SP_AUTO_UPDATE_SHIFT 14U +/*! Slice: mp_auto_update:*/ +/*! automatic update of configuration registers for main path at frame end.*/ +/* 1: enabled */ +/* 0: disabled */ +#define MRV_MI_MP_AUTO_UPDATE +#define MRV_MI_MP_AUTO_UPDATE_MASK 0x00002000U +#define MRV_MI_MP_AUTO_UPDATE_SHIFT 13U +/*! Slice: sp_pingpong_enable:*/ +/*! pingpong mode of configuration registers for self path at frame end.*/ +/* 1: enabled */ +/* 0: disabled */ +#define MRV_MI_SP_PINGPONG_ENABLE +#define MRV_MI_SP_PINGPONG_ENABLE_MASK 0x00001000U +#define MRV_MI_SP_PINGPONG_ENABLE_SHIFT 12U +/*! Slice: mp_pingpong_enable:*/ +/*! pingpong mode of configuration registers for main path at frame end.*/ +/* 1: enabled */ +/* 0: disabled */ +#define MRV_MI_MP_PINGPONG_ENABLE +#define MRV_MI_MP_PINGPONG_ENABLE_MASK 0x00000800U +#define MRV_MI_MP_PINGPONG_ENABLE_SHIFT 11U +/*! Slice: 422noncosited:*/ +/*! Enables self path YCbCr422non-co-sited -> YCbCr444 interpolation */ +/* (M5_v6, M5_v7 only)*/ +/* 1: YCbCr422 data are non_co-sited (Cb and Cr samples are centered between Y samples) so modified interpolation is activated */ +/* 0: YCbCr422 data are co-sited (Y0 Cb0 and Cr0 are sampled at the same position)*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_422NONCOSITED +#define MRV_MI_422NONCOSITED_MASK 0x00000400U +#define MRV_MI_422NONCOSITED_SHIFT 10U +/*! Slice: cbcr_full_range:*/ +/*! Enables CbCr full range for self path YCbCr -> RGB conversion */ +/* (M5_v6, M5_v7 only)*/ +/* 1: CbCr have full range (0..255)*/ +/* 0: CbCr have compressed range range (16..240)*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_CBCR_FULL_RANGE +#define MRV_MI_CBCR_FULL_RANGE_MASK 0x00000200U +#define MRV_MI_CBCR_FULL_RANGE_SHIFT 9U +/*! Slice: y_full_range:*/ +/*! Enables Y full range for self path YCbCr -> RGB conversion */ +/* (M5_v6, M5_v7 only)*/ +/* 1: Y has full range (0..255)*/ +/* 0: Y has compressed range (16..235)*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_Y_FULL_RANGE +#define MRV_MI_Y_FULL_RANGE_MASK 0x00000100U +#define MRV_MI_Y_FULL_RANGE_SHIFT 8U +/*! Slice: byte_swap:*/ +/*! Enables change of byte order of the 32 bit output word at write port */ +/* 1: byte order is mirrored but the bit order within one byte doesn’t change */ +/* 0: no byte mirroring */ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/ +#define MRV_MI_BYTE_SWAP +#define MRV_MI_BYTE_SWAP_MASK 0x00000080U +#define MRV_MI_BYTE_SWAP_SHIFT 7U +/*! Slice: rot:*/ +/*! Rotation 90 degree counter clockwise of self picture, only in RGB mode. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/ +/* For RGB 565 format the line length must be a multiple of 2. There are no restrictions for RGB 888/666.*/ +/* 1: enabled */ +/* 0: disabled */ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path. In rotation mode only 4-beat bursts are supported for self-path.*/ +#define MRV_MI_ROT +#define MRV_MI_ROT_MASK 0x00000040U +#define MRV_MI_ROT_SHIFT 6U +/*! Slice: v_flip:*/ +/*! Vertical flipping of self picture. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/ +/* 1: enabled */ +/* 0: disabled */ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_V_FLIP +#define MRV_MI_V_FLIP_MASK 0x00000020U +#define MRV_MI_V_FLIP_SHIFT 5U +/*! Slice: h_flip:*/ +/*! Horizontal flipping of self picture. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/ +/* 1: enabled */ +/* 0: disabled */ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_H_FLIP +#define MRV_MI_H_FLIP_MASK 0x00000010U +#define MRV_MI_H_FLIP_SHIFT 4U +/*! Slice: path_enable:*/ +/*! Enables data pathes of MI according to the following table:*/ + /**/ +/* 0000: disabled, no data is transferred */ +/* 0001: YUV data output, mainpath only (mp_enable only)*/ +/* 0010: self-path only, output data format depending on other settings (sp_enable only)*/ +/* 0011: YUV data output in mainpath and self-path image data active */ +/* 0100: JPEG data output, mainpath only (jpeg_enable only)*/ +/* 0101: not allowed */ +/* 0110: JPEG data output in mainpath and self-path image data active */ +/* 0111: not allowed */ +/* 1000: RAW data output, mainpath only (raw_enable only)*/ +/* 1001: defect pixel data on self-path, image data on mainpath */ +/* 1010: defect pixel data on mainpath, image data on self-path */ +/* 1011: not allowed */ +/* 1100: defect pixel data on self-path, JPEG data on mainpath */ +/* 1101: defect pixel data on mainpath only */ +/* 1110: defect pixel data on self-path only */ +/* 1111: defect pixel data on self-path, RAW data on mainpath */ + /**/ +/* Programmed value becomes effective (visible in shadow register) after a soft reset, a forced software update or an automatic config update. Affects MI_IN and MI_OUT module.*/ +#define MRV_MI_PATH_ENABLE +#define MRV_MI_PATH_ENABLE_MASK 0x0000000FU +#define MRV_MI_PATH_ENABLE_SHIFT 0U +/*! Register: mi_init: Control register for address init and skip function (0x00000004)*/ +/*! Slice: mi_output_format */ +#define MRV_MI_MP_OUTPUT_FORMAT +#define MRV_MI_MP_OUTPUT_FORMAT_MASK 0x000001E0U +#define MRV_MI_MP_OUTPUT_FORMAT_SHIFT 5U +/*! Slice: mi_cfg_upd:*/ +/*! Forced configuration update. Leads to an immediate update of the shadow registers.*/ +/* Depending on the two init enable bits in the MI_CTRL register (init_offset_en and init_base_en) the offset counter, base address and buffer size shadow registers are also updated.*/ +#define MRV_MI_MI_CFG_UPD +#define MRV_MI_MI_CFG_UPD_MASK 0x00000010U +#define MRV_MI_MI_CFG_UPD_SHIFT 4U +/*! Slice: mi_skip:*/ +/*! Skip of current or next starting main picture:*/ +/* Aborts writing of main picture image data of the current frame to RAM (after the current burst transmission has been completed). Further main picture data up to the end of the current frame are discarded.*/ + /**/ +/* No further makroblock line interrupt (mblk_line), no wrap around interrupt for main picture (wrap_mp_y/cb/cr) and no fill level interrupt (fill_mp_y) are generated.*/ + /**/ +/* Skip does not affect the generation of the main path frame end interrupt (mp_frame_end).*/ +/* Skip does not affect the processing of self picture and its corresponding interrupts namely the self path frame end interrupt (sp_frame_end).*/ + /**/ +/* The byte counter (register MI_BYTE_CNT) is not affected. It produces the correct number of JPEG or RAW data bytes at the end of the current (skipped) frame.*/ + /**/ +/* After a skip has been performed the offset counter for the main picture at the start of the following frame are set depending on the bit init_offset_en in register MI_CTRL:*/ + /**/ +/* - Skip restart mode (init_offset_en = 0)*/ +/* The offset counters of the main picture are restarted at the old start values of the previous skipped frame.*/ + /**/ +/* - Skip init mode (init_offset_en = 1)*/ +/* The offset counters of the main picture are initialized with the register contents of the offset counter init registers without any additional forced software update or automatic config update.*/ +#define MRV_MI_MI_SKIP +#define MRV_MI_MI_SKIP_MASK 0x00000004U +#define MRV_MI_MI_SKIP_SHIFT 2U +/*! Register: mi_mp_y_base_ad_init: Base address for main picture Y component, JPEG or raw data (0x00000008)*/ +/*! Slice: mp_y_base_ad_init:*/ +/*! Base address of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +#ifdef ISP_MP_34BIT +#define MRV_MI_MP_Y_BASE_AD_INIT +#define MRV_MI_MP_Y_BASE_AD_INIT_MASK 0xFFFFFFFEU +#define MRV_MI_MP_Y_BASE_AD_INIT_SHIFT 1U +#else +#define MRV_MI_MP_Y_BASE_AD_INIT +#define MRV_MI_MP_Y_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_MP_Y_BASE_AD_INIT_SHIFT 3U +#endif +/*! Register: mi_mp_y_size_init: Size of main picture Y component, JPEG or raw data (0x0000000c)*/ +/*! Slice: mp_y_size_init:*/ +/*! Size of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +#define MRV_MI_MP_Y_SIZE_INIT +#define MRV_MI_MP_Y_SIZE_INIT_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_SIZE_INIT_SHIFT 3U +/*! Register: mi_mp_y_offs_cnt_init: Offset counter init value for main picture Y, JPEG or raw data (0x00000010)*/ +/*! Slice: mp_y_offs_cnt_init:*/ +/*! Offset counter init value of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +#define MRV_MI_MP_Y_OFFS_CNT_INIT +#define MRV_MI_MP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_mp_y_offs_cnt_start: Offset counter start value for main picture Y, JPEG or raw data (0x00000014)*/ +/*! Slice: mp_y_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (main picture Y component, JPEG or raw data). Updated at frame end.*/ +/* Note: A soft reset resets the contents to the reset value.*/ +#define MRV_MI_MP_Y_OFFS_CNT_START +#define MRV_MI_MP_Y_OFFS_CNT_START_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_mp_y_irq_offs_init: Fill level interrupt offset value for main picture Y, JPEG or raw data (0x00000018)*/ +/*! Slice: mp_y_irq_offs_init:*/ +/*! Reaching this programmed value by the current offset counter for addressing main picture Y component, JPEG or raw data leads to generation of fill level interrupt fill_mp_y.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +#define MRV_MI_MP_Y_IRQ_OFFS_INIT +#define MRV_MI_MP_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: mi_mp_cb_base_ad_init: Base address for main picture Cb component ring buffer (0x0000001c)*/ +/*! Slice: mp_cb_base_ad_init:*/ +/*! Base address of main picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#ifdef ISP_MP_34BIT +#define MRV_MI_MP_CB_BASE_AD_INIT +#define MRV_MI_MP_CB_BASE_AD_INIT_MASK 0xFFFFFFFEU +#define MRV_MI_MP_CB_BASE_AD_INIT_SHIFT 1U +#else +#define MRV_MI_MP_CB_BASE_AD_INIT +#define MRV_MI_MP_CB_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CB_BASE_AD_INIT_SHIFT 3U +#endif +/*! Register: mi_mp_cb_size_init: Size of main picture Cb component ring buffer (0x00000020)*/ +/*! Slice: mp_cb_size_init:*/ +/*! Size of main picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_MP_CB_SIZE_INIT +#define MRV_MI_MP_CB_SIZE_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CB_SIZE_INIT_SHIFT 3U +/*! Register: mi_mp_cb_offs_cnt_init: Offset counter init value for main picture Cb component ring buffer (0x00000024)*/ +/*! Slice: mp_cb_offs_cnt_init:*/ +/*! Offset counter init value of main picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect. Check exceptional handling in skip modes.*/ +#define MRV_MI_MP_CB_OFFS_CNT_INIT +#define MRV_MI_MP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CB_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_mp_cb_offs_cnt_start: Offset counter start value for main picture Cb component ring buffer (0x00000028)*/ +/*! Slice: mp_cb_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (main picture Cb component). Updated at frame end.*/ +#define MRV_MI_MP_CB_OFFS_CNT_START +#define MRV_MI_MP_CB_OFFS_CNT_START_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CB_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_mp_cr_base_ad_init: Base address for main picture Cr component ring buffer (0x0000002c)*/ +/*! Slice: mp_cr_base_ad_init:*/ +/*! Base address of main picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#ifdef ISP_MP_34BIT +#define MRV_MI_MP_CR_BASE_AD_INIT +#define MRV_MI_MP_CR_BASE_AD_INIT_MASK 0xFFFFFFFEU +#define MRV_MI_MP_CR_BASE_AD_INIT_SHIFT 1U +#else +#define MRV_MI_MP_CR_BASE_AD_INIT +#define MRV_MI_MP_CR_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CR_BASE_AD_INIT_SHIFT 3U +#endif +/*! Register: mi_mp_cr_size_init: Size of main picture Cr component ring buffer (0x00000030)*/ +/*! Slice: mp_cr_size_init:*/ +/*! Size of main picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_MP_CR_SIZE_INIT +#define MRV_MI_MP_CR_SIZE_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CR_SIZE_INIT_SHIFT 3U +/*! Register: mi_mp_cr_offs_cnt_init: Offset counter init value for main picture Cr component ring buffer (0x00000034)*/ +/*! Slice: mp_cr_offs_cnt_init:*/ +/*! Offset counter init value of main picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect. Check exceptional handling in skip modes.*/ +#define MRV_MI_MP_CR_OFFS_CNT_INIT +#define MRV_MI_MP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CR_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_mp_cr_offs_cnt_start: Offset counter start value for main picture Cr component ring buffer (0x00000038)*/ +/*! Slice: mp_cr_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (main picture Cr component). Updated at frame end.*/ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_MP_CR_OFFS_CNT_START +#define MRV_MI_MP_CR_OFFS_CNT_START_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CR_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_sp_y_base_ad_init: Base address for self picture Y component ring buffer (0x0000003c)*/ +/*! Slice: sp_y_base_ad_init:*/ +/*! Base address of self picture Y component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_Y_BASE_AD_INIT +#define MRV_MI_SP_Y_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_SP_Y_BASE_AD_INIT_SHIFT 3U +/*! Register: mi_sp_y_size_init: Size of self picture Y component ring buffer (0x00000040)*/ +/*! Slice: sp_y_size_init:*/ +/*! Size of self picture Y component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_Y_SIZE_INIT +#define MRV_MI_SP_Y_SIZE_INIT_MASK 0x1FFFFFF8U +#define MRV_MI_SP_Y_SIZE_INIT_SHIFT 3U +/*! Register: mi_sp_y_offs_cnt_init: Offset counter init value for self picture Y component ring buffer (0x00000044)*/ +/*! Slice: sp_y_offs_cnt_init:*/ +/*! Offset counter init value of self picture Y component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_Y_OFFS_CNT_INIT +#define MRV_MI_SP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define MRV_MI_SP_Y_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_sp_y_offs_cnt_start: Offset counter start value for self picture Y component ring buffer (0x00000048)*/ +/*! Slice: sp_y_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (self picture Y component). Updated at frame end.*/ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_SP_Y_OFFS_CNT_START +#define MRV_MI_SP_Y_OFFS_CNT_START_MASK 0x1FFFFFF8U +#define MRV_MI_SP_Y_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_sp_y_llength: Line length of self picture Y component (0x0000004c)*/ +/*! Slice: sp_y_llength:*/ +/*! Line length of self picture Y component or RGB picture in pixel, also known as line stride.*/ +/* If no line stride is used, line length must match image width.*/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/ +/* In planar mode the line length of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the line length of the Cb and Cr component is assumed the same size.*/ +/* Note: Line length always refers to the line length of the output image. This is particularly important when rotating.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_SP_Y_LLENGTH +#define MRV_MI_SP_Y_LLENGTH_MASK 0x00007FFFU +#define MRV_MI_SP_Y_LLENGTH_SHIFT 0U +/*! Register: mi_sp_cb_base_ad_init: Base address for self picture Cb component ring buffer (0x00000050)*/ +/*! Slice: sp_cb_base_ad_init:*/ +/*! Base address of self picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CB_BASE_AD_INIT +#define MRV_MI_SP_CB_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CB_BASE_AD_INIT_SHIFT 3U +/*! Register: mi_sp_cb_size_init: Size of self picture Cb component ring buffer (0x00000054)*/ +/*! Slice: sp_cb_size_init:*/ +/*! Size of self picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CB_SIZE_INIT +#define MRV_MI_SP_CB_SIZE_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CB_SIZE_INIT_SHIFT 3U +/*! Register: mi_sp_cb_offs_cnt_init: Offset counter init value for self picture Cb component ring buffer (0x00000058)*/ +/*! Slice: sp_cb_offs_cnt_init:*/ +/*! Offset counter init value of self picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CB_OFFS_CNT_INIT +#define MRV_MI_SP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CB_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_sp_cb_offs_cnt_start: Offset counter start value for self picture Cb component ring buffer (0x0000005c)*/ +/*! Slice: sp_cb_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (self picture Cb component). Updated at frame end.*/ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_SP_CB_OFFS_CNT_START +#define MRV_MI_SP_CB_OFFS_CNT_START_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CB_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_sp_cr_base_ad_init: Base address for self picture Cr component ring buffer (0x00000060)*/ +/*! Slice: sp_cr_base_ad_init:*/ +/*! Base address of self picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CR_BASE_AD_INIT +#define MRV_MI_SP_CR_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CR_BASE_AD_INIT_SHIFT 3U +/*! Register: mi_sp_cr_size_init: Size of self picture Cr component ring buffer (0x00000064)*/ +/*! Slice: sp_cr_size_init:*/ +/*! Size of self picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CR_SIZE_INIT +#define MRV_MI_SP_CR_SIZE_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CR_SIZE_INIT_SHIFT 3U +/*! Register: mi_sp_cr_offs_cnt_init: Offset counter init value for self picture Cr component ring buffer (0x00000068)*/ +/*! Slice: sp_cr_offs_cnt_init:*/ +/*! Offset counter init value of self picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CR_OFFS_CNT_INIT +#define MRV_MI_SP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CR_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_sp_cr_offs_cnt_start: Offset counter start value for self picture Cr component ring buffer (0x0000006c)*/ +/*! Slice: sp_cr_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (self picture Cr component). Updated at frame end.*/ +#define MRV_MI_SP_CR_OFFS_CNT_START +#define MRV_MI_SP_CR_OFFS_CNT_START_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CR_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_byte_cnt: Counter value of JPEG or RAW data bytes (0x00000070)*/ +/*! Slice: byte_cnt:*/ +/*! Counter value specifies the number of JPEG or RAW data bytes of the last transmitted frame. Updated at frame end.*/ +/* A soft reset will set the byte counter to zero.*/ +#define MRV_MI_BYTE_CNT +#define MRV_MI_BYTE_CNT_MASK 0x0FFFFFFFU +#define MRV_MI_BYTE_CNT_SHIFT 0U +/*! Register: mi_ctrl_shd: global control internal shadow register (0x00000074)*/ +/*! Slice: path_enable_out:*/ +/*! path_enable shadow register for module MI_OUT (former raw_enable_out, jpeg_enable_out, sp_enable_out, mp_enable_out)*/ +#define MRV_MI_PATH_ENABLE_OUT +#define MRV_MI_PATH_ENABLE_OUT_MASK 0x000F0000U +#define MRV_MI_PATH_ENABLE_OUT_SHIFT 16U +/*! Slice: path_enable_in:*/ +/*! path_enable shadow register for module MI_IN (former raw_enable_in, jpeg_enable_in, sp_enable_in, mp_enable_in)*/ +#define MRV_MI_PATH_ENABLE_IN +#define MRV_MI_PATH_ENABLE_IN_MASK 0x0000000FU +#define MRV_MI_PATH_ENABLE_IN_SHIFT 0U +/*! Register: mi_mp_y_base_ad_shd: Base address shadow register for main picture Y component, JPEG or raw data ring buffer (0x00000078)*/ +/*! Slice: mp_y_base_ad:*/ +/*! Base address of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/ +#define MRV_MI_MP_Y_BASE_AD +#define MRV_MI_MP_Y_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_MP_Y_BASE_AD_SHIFT 3U +/*! Register: mi_mp_y_size_shd: Size shadow register of main picture Y component, JPEG or raw data (0x0000007c)*/ +/*! Slice: mp_y_size:*/ +/*! Size of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/ +#define MRV_MI_MP_Y_SIZE +#define MRV_MI_MP_Y_SIZE_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_SIZE_SHIFT 3U +/*! Register: mi_mp_y_offs_cnt_shd: Current offset counter of main picture Y component, JPEG or raw data ring buffer (0x00000080)*/ +/*! Slice: mp_y_offs_cnt:*/ +/*! Current offset counter of main picture Y component, JPEG or raw data ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_MP_Y_OFFS_CNT +#define MRV_MI_MP_Y_OFFS_CNT_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_OFFS_CNT_SHIFT 3U +/*! Register: mi_mp_y_irq_offs_shd: Shadow register of fill level interrupt offset value for main picture Y component, JPEG or raw data (0x00000084)*/ +/*! Slice: mp_y_irq_offs:*/ +/*! Reaching this offset value by the current offset counter for addressing main picture Y component, JPEG or raw data leads to generation of fill level interrupt fill_mp_y.*/ +#define MRV_MI_MP_Y_IRQ_OFFS +#define MRV_MI_MP_Y_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_IRQ_OFFS_SHIFT 3U +/*! Register: mi_mp_cb_base_ad_shd: Base address shadow register for main picture Cb component ring buffer (0x00000088)*/ +/*! Slice: mp_cb_base_ad:*/ +/*! Base address of main picture Cb component ring buffer.*/ +#define MRV_MI_MP_CB_BASE_AD +#define MRV_MI_MP_CB_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CB_BASE_AD_SHIFT 3U +/*! Register: mi_mp_cb_size_shd: Size shadow register of main picture Cb component ring buffer (0x0000008c)*/ +/*! Slice: mp_cb_size:*/ +/*! Size of main picture Cb component ring buffer.*/ +#define MRV_MI_MP_CB_SIZE +#define MRV_MI_MP_CB_SIZE_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CB_SIZE_SHIFT 3U +/*! Register: mi_mp_cb_offs_cnt_shd: Current offset counter of main picture Cb component ring buffer (0x00000090)*/ +/*! Slice: mp_cb_offs_cnt:*/ +/*! Current offset counter of main picture Cb component ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_MP_CB_OFFS_CNT +#define MRV_MI_MP_CB_OFFS_CNT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CB_OFFS_CNT_SHIFT 3U +/*! Register: mi_mp_cr_base_ad_shd: Base address shadow register for main picture Cr component ring buffer (0x00000094)*/ +/*! Slice: mp_cr_base_ad:*/ +/*! Base address of main picture Cr component ring buffer.*/ +#define MRV_MI_MP_CR_BASE_AD +#define MRV_MI_MP_CR_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CR_BASE_AD_SHIFT 3U +/*! Register: mi_mp_cr_size_shd: Size shadow register of main picture Cr component ring buffer (0x00000098)*/ +/*! Slice: mp_cr_size:*/ +/*! Size of main picture Cr component ring buffer.*/ +#define MRV_MI_MP_CR_SIZE +#define MRV_MI_MP_CR_SIZE_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CR_SIZE_SHIFT 3U +/*! Register: mi_mp_cr_offs_cnt_shd: Current offset counter of main picture Cr component ring buffer (0x0000009c)*/ +/*! Slice: mp_cr_offs_cnt:*/ +/*! Current offset counter of main picture Cr component ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_MP_CR_OFFS_CNT +#define MRV_MI_MP_CR_OFFS_CNT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CR_OFFS_CNT_SHIFT 3U +/*! Register: mi_sp_y_base_ad_shd: Base address shadow register for self picture Y component ring buffer (0x000000a0)*/ +/*! Slice: sp_y_base_ad:*/ +/*! Base address of self picture Y component ring buffer.*/ +#define MRV_MI_SP_Y_BASE_AD +#define MRV_MI_SP_Y_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_SP_Y_BASE_AD_SHIFT 3U +/*! Register: mi_sp_y_size_shd: Size shadow register of self picture Y component ring buffer (0x000000a4)*/ +/*! Slice: sp_y_size:*/ +/*! Size of self picture Y component ring buffer.*/ +#define MRV_MI_SP_Y_SIZE +#define MRV_MI_SP_Y_SIZE_MASK 0x1FFFFFF8U +#define MRV_MI_SP_Y_SIZE_SHIFT 3U +/*! Register: mi_sp_y_offs_cnt_shd: Current offset counter of self picture Y component ring buffer (0x000000a8)*/ +/*! Slice: sp_y_offs_cnt:*/ +/*! Current offset counter of self picture Y component ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_SP_Y_OFFS_CNT +#define MRV_MI_SP_Y_OFFS_CNT_MASK 0x1FFFFFF8U +#define MRV_MI_SP_Y_OFFS_CNT_SHIFT 3U +/*! Register: mi_sp_cb_base_ad_shd: Base address shadow register for self picture Cb component ring buffer (0x000000b0)*/ +/*! Slice: sp_cb_base_ad:*/ +/*! Base address of self picture Cb component ring buffer.*/ +#define MRV_MI_SP_CB_BASE_AD +#define MRV_MI_SP_CB_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CB_BASE_AD_SHIFT 3U +/*! Register: mi_sp_cb_size_shd: Size shadow register of self picture Cb component ring buffer (0x000000b4)*/ +/*! Slice: sp_cb_size:*/ +/*! Size of self picture Cb component ring buffer.*/ +#define MRV_MI_SP_CB_SIZE +#define MRV_MI_SP_CB_SIZE_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CB_SIZE_SHIFT 3U +/*! Register: mi_sp_cb_offs_cnt_shd: Current offset counter of self picture Cb component ring buffer (0x000000b8)*/ +/*! Slice: sp_cb_offs_cnt:*/ +/*! Current offset counter of self picture Cb component ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_SP_CB_OFFS_CNT +#define MRV_MI_SP_CB_OFFS_CNT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CB_OFFS_CNT_SHIFT 3U +/*! Register: mi_sp_cr_base_ad_shd: Base address shadow register for self picture Cr component ring buffer (0x000000bc)*/ +/*! Slice: sp_cr_base_ad:*/ +/*! Base address of self picture Cr component ring buffer.*/ +#define MRV_MI_SP_CR_BASE_AD +#define MRV_MI_SP_CR_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CR_BASE_AD_SHIFT 3U +/*! Register: mi_sp_cr_size_shd: Size shadow register of self picture Cr component ring buffer (0x000000c0)*/ +/*! Slice: sp_cr_size:*/ +/*! Size of self picture Cr component ring buffer.*/ +#define MRV_MI_SP_CR_SIZE +#define MRV_MI_SP_CR_SIZE_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CR_SIZE_SHIFT 3U +/*! Register: mi_sp_cr_offs_cnt_shd: Current offset counter of self picture Cr component ring buffer (0x000000c4)*/ +/*! Slice: sp_cr_offs_cnt:*/ +/*! Current offset counter of self picture Cr component ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_SP_CR_OFFS_CNT +#define MRV_MI_SP_CR_OFFS_CNT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CR_OFFS_CNT_SHIFT 3U +/*! Register: mi_dma_y_pic_start_ad: Y component image start address (0x000000c8)*/ +/*! Slice: dma_y_pic_start_ad:*/ +/*! Image start address of the y component */ +/* Note: Must be multiple of 4 in interleaved mode.*/ +#define MRV_MI_DMA_Y_PIC_START_AD +#define MRV_MI_DMA_Y_PIC_START_AD_MASK 0xFFFFFFFFU +#define MRV_MI_DMA_Y_PIC_START_AD_SHIFT 0U +/*! Register: mi_dma_y_pic_width: Y component image width (0x000000cc)*/ +/*! Slice: dma_y_pic_width:*/ +/*! Image width of the Y component in pixel.*/ +/* For YCbCr 4:2:x the image width must be a multiple of 2.*/ +/* In planar mode the image width of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the image width of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr image width is used.*/ +#define MRV_MI_DMA_Y_PIC_WIDTH +#define MRV_MI_DMA_Y_PIC_WIDTH_MASK 0x00007FFFU +#define MRV_MI_DMA_Y_PIC_WIDTH_SHIFT 0U +/*! Register: mi_dma_y_llength: Y component original line length (0x000000d0)*/ +/*! Slice: dma_y_llength:*/ +/*! Line length of the Y component of the original image in memory */ +/* For an uncropped image, where lines follow each other without offset (no line stride), line length must match image width.*/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4.*/ +/* In planar mode the line length of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the line length of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr line length is used.*/ +#define MRV_MI_DMA_Y_LLENGTH +#define MRV_MI_DMA_Y_LLENGTH_MASK 0x00007FFFU +#define MRV_MI_DMA_Y_LLENGTH_SHIFT 0U +/*! Register: mi_dma_y_pic_size: Y component image size (0x000000d4)*/ +/*! Slice: dma_y_pic_size:*/ +/*! Image size of the Y component in pixel which has to be the Y line length multiplied by the Y image height (dma_y_llength * dma_y_pic_height).*/ +/* In planar mode the image size of the Cb and Cr component is assumed according to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for 4:4:4. In semi planar mode the image size of the Cb component (which includes Cr) is assumed half for 4:2:0 and the same size for 4:2:2. In interleave mode no Cb/Cr image size is used.*/ +#define MRV_MI_DMA_Y_PIC_SIZE +#define MRV_MI_DMA_Y_PIC_SIZE_MASK 0x0FFFFFFFU +#define MRV_MI_DMA_Y_PIC_SIZE_SHIFT 0U +/*! Register: mi_dma_cb_pic_start_ad: Cb component image start address (0x000000d8)*/ +/*! Slice: dma_cb_pic_start_ad:*/ +/*! Image start address of the Cb component */ +/* Note: Must be multiple of 2 in semi-planar mode.*/ +#define MRV_MI_DMA_CB_PIC_START_AD +#define MRV_MI_DMA_CB_PIC_START_AD_MASK 0xFFFFFFFFU +#define MRV_MI_DMA_CB_PIC_START_AD_SHIFT 0U +/*! Register: mi_dma_cr_pic_start_ad: Cr component image start address (0x000000e8)*/ +/*! Slice: dma_cr_pic_start_ad:*/ +/*! Image start address of the Cr component */ +#define MRV_MI_DMA_CR_PIC_START_AD +#define MRV_MI_DMA_CR_PIC_START_AD_MASK 0xFFFFFFFFU +#define MRV_MI_DMA_CR_PIC_START_AD_SHIFT 0U +/*! Register: mi_imsc: Interrupt Mask (‘1’: interrupt active, ‘0’: interrupt masked) (0x000000f8)*/ +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Slice mp_handshk_int:*/ +/*! Mask bit for mp handshake interrupt */ +#define MRV_MI_MP_HANDSHK_INT +#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U +#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U +#endif +/*! Slice: dma_ready:*/ +/*! Mask bit for dma ready interrupt */ +#define MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0x00000800U +#define MRV_MI_DMA_READY_SHIFT 11U +/*! Slice: wrap_sp_cr:*/ +/*! Mask bit for self picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U +#define MRV_MI_WRAP_SP_CR_SHIFT 9U +/*! Slice: wrap_sp_cb:*/ +/*! Mask bit for self picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U +#define MRV_MI_WRAP_SP_CB_SHIFT 8U +/*! Slice: wrap_sp_y:*/ +/*! Mask bit for self picture Y address wrap interrupt */ +#define MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U +#define MRV_MI_WRAP_SP_Y_SHIFT 7U +/*! Slice: wrap_mp_cr:*/ +/*! Mask bit for main picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U +#define MRV_MI_WRAP_MP_CR_SHIFT 6U +/*! Slice: wrap_mp_cb:*/ +/*! Mask bit for main picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U +#define MRV_MI_WRAP_MP_CB_SHIFT 5U +/*! Slice: wrap_mp_y:*/ +/*! Mask bit for main picture Y address wrap interrupt */ +#define MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U +#define MRV_MI_WRAP_MP_Y_SHIFT 4U +/*! Slice: fill_mp_y:*/ +/*! Mask bit for fill level interrupt of main picture Y, JPEG or raw data */ +#define MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0x00000008U +#define MRV_MI_FILL_MP_Y_SHIFT 3U +/*! Slice: mblk_line:*/ +/*! Mask bit for makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM)*/ +#define MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0x00000004U +#define MRV_MI_MBLK_LINE_SHIFT 2U +/*! Slice: sp_frame_end:*/ +/*! Mask self picture end of frame interrupt */ +#define MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0x00000002U +#define MRV_MI_SP_FRAME_END_SHIFT 1U +/*! Slice: mp_frame_end:*/ +/*! Mask main picture end of frame interrupt */ +#define MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0x00000001U +#define MRV_MI_MP_FRAME_END_SHIFT 0U +/*! Register: mi_ris: Raw Interrupt Status (0x000000fc)*/ +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Slice mp_handshk_int:*/ +/*! Raw status of mp handshake interrupt */ +#define MRV_MI_MP_HANDSHK_INT +#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U +#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U +#endif +/*! Slice: dma_ready:*/ +/*! Raw status of dma ready interrupt */ +#define MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0x00000800U +#define MRV_MI_DMA_READY_SHIFT 11U +/*! Slice: wrap_sp_cr:*/ +/*! Raw status of self picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U +#define MRV_MI_WRAP_SP_CR_SHIFT 9U +/*! Slice: wrap_sp_cb:*/ +/*! Raw status of self picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U +#define MRV_MI_WRAP_SP_CB_SHIFT 8U +/*! Slice: wrap_sp_y:*/ +/*! Raw status of self picture Y address wrap interrupt */ +#define MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U +#define MRV_MI_WRAP_SP_Y_SHIFT 7U +/*! Slice: wrap_mp_cr:*/ +/*! Raw status of main picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U +#define MRV_MI_WRAP_MP_CR_SHIFT 6U +/*! Slice: wrap_mp_cb:*/ +/*! Raw status of main picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U +#define MRV_MI_WRAP_MP_CB_SHIFT 5U +/*! Slice: wrap_mp_y:*/ +/*! Raw status of main picture Y address wrap interrupt */ +#define MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U +#define MRV_MI_WRAP_MP_Y_SHIFT 4U +/*! Slice: fill_mp_y:*/ +/*! Raw status of fill level interrupt of main picture Y, JPEG or raw data */ +#define MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0x00000008U +#define MRV_MI_FILL_MP_Y_SHIFT 3U +/*! Slice: mblk_line:*/ +/*! Raw status of makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM, valid only for planar and semi-planar mode)*/ +#define MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0x00000004U +#define MRV_MI_MBLK_LINE_SHIFT 2U +/*! Slice: sp_frame_end:*/ +/*! Raw status of self picture end of frame interrupt */ +#define MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0x00000002U +#define MRV_MI_SP_FRAME_END_SHIFT 1U +/*! Slice: mp_frame_end:*/ +/*! Raw status of main picture end of frame interrupt */ +#define MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0x00000001U +#define MRV_MI_MP_FRAME_END_SHIFT 0U +#ifdef ISP_MI_BP +/*! Slice: bp_frame_end:*/ +/*! Raw status of bp picture end of frame interrupt */ +#define MRV_MI_BP_FRAME_END +#define MRV_MI_BP_FRAME_END_MASK 0x00004000U +#define MRV_MI_BP_FRAME_END_SHIFT 14U +/*! Slice: bp_wr_raw_aligned:*/ +#define BP_WR_RAW_ALIGNED +#define BP_WR_RAW_ALIGNED_MASK 0x000000c0U +#define BP_WR_RAW_ALIGNED_SHIFT 6U +/*! Slice: bp_wr_byte_swap:*/ +#define BP_WR_BYTE_SWAP +#define BP_WR_BYTE_SWAP_MASK 0x00007000U +#define BP_WR_BYTE_SWAP_SHIFT 12U +/*! Slice: bp_fill_r */ +#define MRV_MI_BP_FILL_R +#define MRV_MI_BP_FILL_R_MASK 0x00008000U +#define MRV_MI_BP_FILL_R_SHIFT 15U +/*! Slice: wrap_bp_r:*/ +#define MRV_MI_BP_WRAP_R +#define MRV_MI_BP_WRAP_R_MASK 0x00010000U +#define MRV_MI_BP_WRAP_R_SHIFT 16U +/*! Slice: wrap_bp_r:*/ +#define MRV_MI_BP_WRAP_R +#define MRV_MI_BP_WRAP_R_MASK 0x00010000U +#define MRV_MI_BP_WRAP_R_SHIFT 16U +/*! Slice: wrap_bp_gr:*/ +#define MRV_MI_BP_WRAP_GR +#define MRV_MI_BP_WRAP_GR_MASK 0x00020000U +#define MRV_MI_BP_WRAP_GR_SHIFT 17U +/*! Slice: wrap_bp_gb:*/ +#define MRV_MI_BP_WRAP_GB +#define MRV_MI_BP_WRAP_GB_MASK 0x00040000U +#define MRV_MI_BP_WRAP_GB_SHIFT 18U +/*! Slice: wrap_bp_b:*/ +#define MRV_MI_BP_WRAP_B +#define MRV_MI_BP_WRAP_B_MASK 0x00080000U +#define MRV_MI_BP_WRAP_B_SHIFT 19U +/*! Register: miv1_bp_r_base_ad_init (0x000015d8)*/ +/*! Slice: bp_r_base_ad_init:*/ +#define BP_R_BASE_AD_INIT +#define BP_R_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define BP_R_BASE_AD_INIT_SHIFT 3U +/*! Register: miv1_bp_gr_base_ad_init (0x000015dc)*/ +/*! Slice: bp_gr_base_ad_init:*/ +#define BP_GR_BASE_AD_INIT +#define BP_GR_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define BP_GR_BASE_AD_INIT_SHIFT 3U +/*! Register: miv1_bp_gb_base_ad_init (0x000015e0)*/ +/*! Slice: bp_gb_base_ad_init:*/ +#define BP_GB_BASE_AD_INIT +#define BP_GB_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define BP_GB_BASE_AD_INIT_SHIFT 3U +/*! Register: miv1_bp_b_base_ad_init (0x000015e4)*/ +/*! Slice: bp_b_base_ad_init:*/ +#define BP_B_BASE_AD_INIT +#define BP_B_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define BP_B_BASE_AD_INIT_SHIFT 3U +/*! Register: miv1_bp_r_offs_cnt_init (0x000015c8)*/ +/*! Slice: bp_r_offs_cnt_init:*/ +#define BP_R_OFFS_CNT_INIT +#define BP_R_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define BP_R_OFFS_CNT_INIT_SHIFT 3U +/*! Register: miv1_bp_gr_offs_cnt_init (0x000015cc)*/ +/*! Slice: bp_gr_offs_cnt_init:*/ +#define BP_GR_OFFS_CNT_INIT +#define BP_GR_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define BP_GR_OFFS_CNT_INIT_SHIFT 3U +/*! Register: miv1_bp_gb_offs_cnt_init (0x000015d0)*/ +/*! Slice: bp_gb_offs_cnt_init:*/ +#define BP_GB_OFFS_CNT_INIT +#define BP_GB_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define BP_GB_OFFS_CNT_INIT_SHIFT 3U +/*! Register: miv1_bp_b_offs_cnt_init (0x000015d4)*/ +/*! Slice: bp_b_offs_cnt_init:*/ +#define BP_B_OFFS_CNT_INIT +#define BP_B_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define BP_B_OFFS_CNT_INIT_SHIFT 3U +/*! Register: miv1_bp_wr_offs_cnt_init (0x000015A4)*/ +/*! Slice: mi_bp_wr_offs_cnt_init:*/ +#define BP_PIC_WR_OFFS_CNT_INIT +#define BP_PIC_WR_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define BP_PIC_WR_OFFS_CNT_INIT_SHIFT 3U +/*! Register: miv1_bp_wr_irq_offs_init (0x000015AC)*/ +/*! Slice: mi_bp_wr_irq_offs_init:*/ +#define BP_PIC_IRQ_OFFS_INIT +#define BP_PIC_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define BP_PIC_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv1_bp_wr_size_init (0x000015B4)*/ +/*! Slice: mi_bp_wr_size_init:*/ +#define BP_PIC_WR_SIZE_INIT +#define BP_PIC_WR_SIZE_INIT_MASK 0x1FFFFFF8U +#define BP_PIC_WR_SIZE_INIT_SHIFT 3U +/*! Register: miv1_bp_pic_width (0x000015bc)*/ +/*! Slice: bp_pic_width:*/ +#define BP_PIC_WIDTH +#define BP_PIC_WIDTH_MASK 0x4FFFU +#define BP_PIC_WIDTH_SHIFT 0U +/*! Register: miv1_bp_pic_height (0x000015c0)*/ +/*! Slice: bp_pic_height:*/ +#define BP_PIC_HEIGHT +#define BP_PIC_HEIGHT_MASK 0x4FFFU +#define BP_PIC_HEIGHT_SHIFT 0U +/*! Register: miv1_bp_pic_size (0x000015c4)*/ +/*! Slice: bp_pic_size:*/ +#define BP_PIC_SIZE +#define BP_PIC_SIZE_MASK 0x1FFFFFFU +#define BP_PIC_SIZE_SHIFT 0U +#endif +/*! Register: mi_mis: Masked Interrupt Status (0x00000100)*/ +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Slice mp_handshk_int:*/ +/*! Masked status for mp handshake interrupt */ +#define MRV_MI_MP_HANDSHK_INT +#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U +#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U +#endif +/*! Slice: dma_ready:*/ +/*! Masked status of dma ready interrupt */ +#define MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0x00000800U +#define MRV_MI_DMA_READY_SHIFT 11U +/*! Slice: wrap_sp_cr:*/ +/*! Masked status of self picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U +#define MRV_MI_WRAP_SP_CR_SHIFT 9U +/*! Slice: wrap_sp_cb:*/ +/*! Masked status of self picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U +#define MRV_MI_WRAP_SP_CB_SHIFT 8U +/*! Slice: wrap_sp_y:*/ +/*! Masked status of self picture Y address wrap interrupt */ +#define MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U +#define MRV_MI_WRAP_SP_Y_SHIFT 7U +/*! Slice: wrap_mp_cr:*/ +/*! Masked status of main picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U +#define MRV_MI_WRAP_MP_CR_SHIFT 6U +/*! Slice: wrap_mp_cb:*/ +/*! Masked status of main picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U +#define MRV_MI_WRAP_MP_CB_SHIFT 5U +/*! Slice: wrap_mp_y:*/ +/*! Masked status of main picture Y address wrap interrupt */ +#define MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U +#define MRV_MI_WRAP_MP_Y_SHIFT 4U +/*! Slice: fill_mp_y:*/ +/*! Masked status of fill level interrupt of main picture Y, JPEG or raw data */ +#define MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0x00000008U +#define MRV_MI_FILL_MP_Y_SHIFT 3U +/*! Slice: mblk_line:*/ +/*! Masked status of makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM, valid only for planar and semi-planar mode)*/ +#define MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0x00000004U +#define MRV_MI_MBLK_LINE_SHIFT 2U +/*! Slice: sp_frame_end:*/ +/*! Masked status of self picture end of frame interrupt */ +#define MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0x00000002U +#define MRV_MI_SP_FRAME_END_SHIFT 1U +/*! Slice: mp_frame_end:*/ +/*! Masked status of main picture end of frame interrupt */ +#define MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0x00000001U +#define MRV_MI_MP_FRAME_END_SHIFT 0U +/*! Register: mi_icr: Interrupt Clear Register (0x00000104)*/ +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Slice mp_handshk_int:*/ +/*! clear mp handshake interrupt */ +#define MRV_MI_MP_HANDSHK_INT +#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U +#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U +#endif +/*! Slice: dma_ready:*/ +/*! Clear dma ready interrupt */ +#define MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0x00000800U +#define MRV_MI_DMA_READY_SHIFT 11U +/*! Slice: wrap_sp_cr:*/ +/*! Clear self picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U +#define MRV_MI_WRAP_SP_CR_SHIFT 9U +/*! Slice: wrap_sp_cb:*/ +/*! Clear self picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U +#define MRV_MI_WRAP_SP_CB_SHIFT 8U +/*! Slice: wrap_sp_y:*/ +/*! Clear self picture Y address wrap interrupt */ +#define MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U +#define MRV_MI_WRAP_SP_Y_SHIFT 7U +/*! Slice: wrap_mp_cr:*/ +/*! Clear main picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U +#define MRV_MI_WRAP_MP_CR_SHIFT 6U +/*! Slice: wrap_mp_cb:*/ +/*! Clear main picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U +#define MRV_MI_WRAP_MP_CB_SHIFT 5U +/*! Slice: wrap_mp_y:*/ +/*! Clear main picture Y address wrap interrupt */ +#define MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U +#define MRV_MI_WRAP_MP_Y_SHIFT 4U +/*! Slice: fill_mp_y:*/ +/*! Clear fill level interrupt */ +#define MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0x00000008U +#define MRV_MI_FILL_MP_Y_SHIFT 3U +/*! Slice: mblk_line:*/ +/*! Clear makroblock line interrupt */ +#define MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0x00000004U +#define MRV_MI_MBLK_LINE_SHIFT 2U +/*! Slice: sp_frame_end:*/ +/*! Clear self picture end of frame interrupt */ +#define MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0x00000002U +#define MRV_MI_SP_FRAME_END_SHIFT 1U +/*! Slice: mp_frame_end:*/ +/*! Clear main picture end of frame interrupt */ +#define MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0x00000001U +#define MRV_MI_MP_FRAME_END_SHIFT 0U +/*! Register: mi_isr: Interrupt Set Register (0x00000108)*/ +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Slice mp_handshk_int:*/ +/*! Set mp handshake interrupt */ +#define MRV_MI_MP_HANDSHK_INT +#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U +#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U +#endif +/*! Slice: dma_ready:*/ +/*! Set dma ready interrupt */ +#define MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0x00000800U +#define MRV_MI_DMA_READY_SHIFT 11U +/*! Slice: wrap_sp_cr:*/ +/*! Set self picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U +#define MRV_MI_WRAP_SP_CR_SHIFT 9U +/*! Slice: wrap_sp_cb:*/ +/*! Set self picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U +#define MRV_MI_WRAP_SP_CB_SHIFT 8U +/*! Slice: wrap_sp_y:*/ +/*! Set self picture Y address wrap interrupt */ +#define MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U +#define MRV_MI_WRAP_SP_Y_SHIFT 7U +/*! Slice: wrap_mp_cr:*/ +/*! Set main picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U +#define MRV_MI_WRAP_MP_CR_SHIFT 6U +/*! Slice: wrap_mp_cb:*/ +/*! Set main picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U +#define MRV_MI_WRAP_MP_CB_SHIFT 5U +/*! Slice: wrap_mp_y:*/ +/*! Set main picture Y address wrap interrupt */ +#define MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U +#define MRV_MI_WRAP_MP_Y_SHIFT 4U +/*! Slice: fill_mp_y:*/ +/*! Set fill level interrupt */ +#define MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0x00000008U +#define MRV_MI_FILL_MP_Y_SHIFT 3U +/*! Slice: mblk_line:*/ +/*! Set makroblock line interrupt */ +#define MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0x00000004U +#define MRV_MI_MBLK_LINE_SHIFT 2U +/*! Slice: sp_frame_end:*/ +/*! Set self picture end of frame interrupt */ +#define MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0x00000002U +#define MRV_MI_SP_FRAME_END_SHIFT 1U +/*! Slice: mp_frame_end:*/ +/*! Set main picture end of frame interrupt */ +#define MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0x00000001U +#define MRV_MI_MP_FRAME_END_SHIFT 0U +/*! Register: mi_status: MI Status Register (0x0000010c)*/ +/*! Slice: sp_cr_fifo_full:*/ +/*! FIFO full flag of Cr FIFO in self path asserted since last clear */ +#define MRV_MI_SP_CR_FIFO_FULL +#define MRV_MI_SP_CR_FIFO_FULL_MASK 0x00000040U +#define MRV_MI_SP_CR_FIFO_FULL_SHIFT 6U +/*! Slice: sp_cb_fifo_full:*/ +/*! FIFO full flag of Cb FIFO in self path asserted since last clear */ +#define MRV_MI_SP_CB_FIFO_FULL +#define MRV_MI_SP_CB_FIFO_FULL_MASK 0x00000020U +#define MRV_MI_SP_CB_FIFO_FULL_SHIFT 5U +/*! Slice: sp_y_fifo_full:*/ +/*! FIFO full flag of Y FIFO in self path asserted since last clear */ +#define MRV_MI_SP_Y_FIFO_FULL +#define MRV_MI_SP_Y_FIFO_FULL_MASK 0x00000010U +#define MRV_MI_SP_Y_FIFO_FULL_SHIFT 4U +/*! Slice: mp_cr_fifo_full:*/ +/*! FIFO full flag of Cr FIFO in main path asserted since last clear */ +#define MRV_MI_MP_CR_FIFO_FULL +#define MRV_MI_MP_CR_FIFO_FULL_MASK 0x00000004U +#define MRV_MI_MP_CR_FIFO_FULL_SHIFT 2U +/*! Slice: mp_cb_fifo_full:*/ +/*! FIFO full flag of Cb FIFO in main path asserted since last clear */ +#define MRV_MI_MP_CB_FIFO_FULL +#define MRV_MI_MP_CB_FIFO_FULL_MASK 0x00000002U +#define MRV_MI_MP_CB_FIFO_FULL_SHIFT 1U +/*! Slice: mp_y_fifo_full:*/ +/*! FIFO full flag of Y FIFO in main path asserted since last clear */ +#define MRV_MI_MP_Y_FIFO_FULL +#define MRV_MI_MP_Y_FIFO_FULL_MASK 0x00000001U +#define MRV_MI_MP_Y_FIFO_FULL_SHIFT 0U +/*! Register: mi_status_clr: MI Status Clear Register (0x00000110)*/ +/*! Slice: sp_cr_fifo_full:*/ +/*! Clear status of Cr FIFO full flag in self path */ +#define MRV_MI_SP_CR_FIFO_FULL +#define MRV_MI_SP_CR_FIFO_FULL_MASK 0x00000040U +#define MRV_MI_SP_CR_FIFO_FULL_SHIFT 6U +/*! Slice: sp_cb_fifo_full:*/ +/*! Clear status of Cb FIFO full flag in self path */ +#define MRV_MI_SP_CB_FIFO_FULL +#define MRV_MI_SP_CB_FIFO_FULL_MASK 0x00000020U +#define MRV_MI_SP_CB_FIFO_FULL_SHIFT 5U +/*! Slice: sp_y_fifo_full:*/ +/*! Clear status of Y FIFO full flag in self path */ +#define MRV_MI_SP_Y_FIFO_FULL +#define MRV_MI_SP_Y_FIFO_FULL_MASK 0x00000010U +#define MRV_MI_SP_Y_FIFO_FULL_SHIFT 4U +/*! Slice: mp_cr_fifo_full:*/ +/*! Clear status of Cr FIFO full flag in main path */ +#define MRV_MI_MP_CR_FIFO_FULL +#define MRV_MI_MP_CR_FIFO_FULL_MASK 0x00000004U +#define MRV_MI_MP_CR_FIFO_FULL_SHIFT 2U +/*! Slice: mp_cb_fifo_full:*/ +/*! Clear status of Cb FIFO full flag in main path */ +#define MRV_MI_MP_CB_FIFO_FULL +#define MRV_MI_MP_CB_FIFO_FULL_MASK 0x00000002U +#define MRV_MI_MP_CB_FIFO_FULL_SHIFT 1U +/*! Slice: mp_y_fifo_full:*/ +/*! Clear status of Y FIFO full flag in main path */ +#define MRV_MI_MP_Y_FIFO_FULL +#define MRV_MI_MP_Y_FIFO_FULL_MASK 0x00000001U +#define MRV_MI_MP_Y_FIFO_FULL_SHIFT 0U +/*! Register: mi_sp_y_pic_width: Y component image width (0x00000114)*/ +/*! Slice: sp_y_pic_width:*/ +/*! Image width of the self picture Y component or RGB picture in pixel.*/ +/* For YCbCr 4:2:x and RGB 565 the image width must be a multiple of 2. If no line stride is used but flipping required, the image width must be a multiple of 8 for 4:2:x planar or 4 for 4:4:4 planar/4:2:x semi planar. There are no restrictions for RGB 888/666.*/ +/* In planar mode the image width of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the image width of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr image width is used.*/ +/* Note: Image width always refers to the picture width of the output image. This is particularly important when rotating.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_SP_Y_PIC_WIDTH +#define MRV_MI_SP_Y_PIC_WIDTH_MASK 0x00007FFFU +#define MRV_MI_SP_Y_PIC_WIDTH_SHIFT 0U +/*! Register: mi_sp_y_pic_height: Y component image height (0x00000118)*/ +/*! Slice: sp_y_pic_height:*/ +/*! Image height of the y component or RGB picture in pixel.*/ +/* In planar and semi planar mode the image width of the cb and cr component is assumed according to the YCbCr format, i.e. half for 4:2:0 and the same for 4:2:2 and 4:4:4.*/ +/* Note: Image height always refers to the picture height of the output image. This is particularly important when rotating.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_SP_Y_PIC_HEIGHT +#define MRV_MI_SP_Y_PIC_HEIGHT_MASK 0x00007FFFU +#define MRV_MI_SP_Y_PIC_HEIGHT_SHIFT 0U +/*! Register: mi_sp_y_pic_size: Y component image size (0x0000011c)*/ +/*! Slice: sp_y_pic_size:*/ +/*! Image size of the Y component or RGB picture in pixel which has to be the Y line length multiplied by the Y image height (sp_y_llength * sp_y_pic_height).*/ +/* In planar mode the image size of the Cb and Cr component is assumed according to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for 4:4:4. In semi planar mode the image size of the Cb and Cr component is assumed half for 4:2:0 and the same size for 4:2:2.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_SP_Y_PIC_SIZE +#define MRV_MI_SP_Y_PIC_SIZE_MASK 0x01FFFFFFU +#define MRV_MI_SP_Y_PIC_SIZE_SHIFT 0U +/*! Register: mi_dma_ctrl: DMA control register (0x00000120)*/ +/*! Slice: dma_rgb_format:*/ +/*! Selects RGB Bayer data of read DMA picture */ +/* 00: no DMA RGB Bayer data */ +/* 01: 8 bit RGB Bayer data */ +/* 10: 16 bit RGB Bayer data (12 bit used)*/ +/* bytes are organized MSB first and 4 lower bits of LSB remain unused:*/ +/* byte_even -> bayer[11:4], byte_odd[7:4] -> bayer[3:0]*/ +/* 11: reserved.*/ +#define MRV_MI_DMA_RGB_FORMAT +#define MRV_MI_DMA_RGB_FORMAT_MASK 0x00003000U +#define MRV_MI_DMA_RGB_FORMAT_SHIFT 12U +/*! Slice: dma_frame_end_disable:*/ +/*! Suppresses v_end so that no frame end can be detected by following instances. Note: The dma_ready interrupt is raised as usual, but the dma_frame_end interrupt will not be generated until v_end has been enabled again.*/ +#define MRV_MI_DMA_FRAME_END_DISABLE +#define MRV_MI_DMA_FRAME_END_DISABLE_MASK 0x00000400U +#define MRV_MI_DMA_FRAME_END_DISABLE_SHIFT 10U +/*! Slice: dma_continuous_en:*/ +/*! Enables continuous mode. If set the same frame is read back over and over. A start pulse on dma_start is needed only for the first time. To stop continuous mode reset this bit (takes effect after the next frame end) or execute a soft reset. This bit is intended to be used in conjunction with the Superimpose feature.*/ +#define MRV_MI_DMA_CONTINUOUS_EN +#define MRV_MI_DMA_CONTINUOUS_EN_MASK 0x00000200U +#define MRV_MI_DMA_CONTINUOUS_EN_SHIFT 9U +/*! Slice: dma_byte_swap:*/ +/*! Enables change of DMA byte order of the 32 bit input word at read port */ +/* 1: byte order is mirrored but the bit order within one byte doesn’t change */ +/* 0: no byte mirroring */ +#define MRV_MI_DMA_BYTE_SWAP +#define MRV_MI_DMA_BYTE_SWAP_MASK 0x00000100U +#define MRV_MI_DMA_BYTE_SWAP_SHIFT 8U +/*! Slice: dma_inout_format:*/ +/*! Selects input/output format of DMA picture.*/ +/* 11: YCbCr 4:4:4 */ +/* 10: YCbCr 4:2:2 */ +/* 01: YCbCr 4:2:0 */ +/* 00: YCbCr 4:0:0 */ +#define MRV_MI_DMA_INOUT_FORMAT +#define MRV_MI_DMA_INOUT_FORMAT_MASK 0x000000C0U +#define MRV_MI_DMA_INOUT_FORMAT_SHIFT 6U +/*! Slice: dma_read_format:*/ +/*! Defines how YCbCr picture data is read from memory.*/ +/* 00: planar */ +/* 01: semi planar, for YCbCr 4:2:x */ +/* 10: interleaved (combined), for YCbCr 4:2:2 and RGB only */ +/* 11: reserved */ +#define MRV_MI_DMA_READ_FORMAT +#define MRV_MI_DMA_READ_FORMAT_MASK 0x00000030U +#define MRV_MI_DMA_READ_FORMAT_SHIFT 4U +/*! Slice: dma_burst_len_chrom:*/ +/*! Burst length for Cb or Cr data affecting DMA read port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ +#define MRV_MI_DMA_BURST_LEN_CHROM +#define MRV_MI_DMA_BURST_LEN_CHROM_MASK 0x0000000CU +#define MRV_MI_DMA_BURST_LEN_CHROM_SHIFT 2U +/*! Slice: dma_burst_len_lum:*/ +/*! Burst length for Y data affecting DMA read port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ +#define MRV_MI_DMA_BURST_LEN_LUM +#define MRV_MI_DMA_BURST_LEN_LUM_MASK 0x00000003U +#define MRV_MI_DMA_BURST_LEN_LUM_SHIFT 0U +/*! Register: mi_dma_start: DMA start register (0x00000124)*/ +/*! Slice: dma_start:*/ +/*! Enables DMA access. Additionally main or self path has to be enabled separately.*/ +#define MRV_MI_DMA_START +#define MRV_MI_DMA_START_MASK 0x00000001U +#define MRV_MI_DMA_START_SHIFT 0U +/*! Register: mi_dma_status: DMA status register (0x00000128)*/ +/*! Slice: dma_active:*/ +/*! If set DMA access is active.*/ +#define MRV_MI_DMA_ACTIVE +#define MRV_MI_DMA_ACTIVE_MASK 0x00000001U +#define MRV_MI_DMA_ACTIVE_SHIFT 0U +/*! Register: mi_pixel_cnt: Counter value for defect pixel list (0x0000012c)*/ +/*! Slice: pix_cnt:*/ +/*! Counter value specifies the number of pixels of the defect pixel list generated by DPCC of the last transmitted frame. Updated at frame end.*/ +/* A soft reset will set the counter to zero.*/ +#define MRV_MI_PIX_CNT +#define MRV_MI_PIX_CNT_MASK 0x0FFFFFFFU +#define MRV_MI_PIX_CNT_SHIFT 0U +/*! Register: mi_mp_y_base_ad_init2: Base address 2 (ping pong) for main picture Y component, JPEG or raw data (0x00000130)*/ +/*! Slice: mp_y_base_ad_init2:*/ +/*! 2nd ping pong base address of main picture Y component buffer, JPEG buffer or raw data buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_MP_Y_BASE_AD_INIT2 +#define MRV_MI_MP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_MP_Y_BASE_AD_INIT2_SHIFT 3U +/*! Register: mi_mp_cb_base_ad_init2: Base address 2 (pingpong) for main picture Cb component (0x00000134)*/ +/*! Slice: mp_cb_base_ad_init2:*/ +/*! 2nd ping pong base address of main picture Cb component buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_MP_CB_BASE_AD_INIT2 +#define MRV_MI_MP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CB_BASE_AD_INIT2_SHIFT 3U +/*! Register: mi_mp_cr_base_ad_init2: Base address 2 (pingpong) for main picture Cr component ring buffer (0x00000138)*/ +/*! Slice: mp_cr_base_ad_init2:*/ +/*! 2nd ping pong Base address of main picture Cr component buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_MP_CR_BASE_AD_INIT2 +#define MRV_MI_MP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CR_BASE_AD_INIT2_SHIFT 3U +/*! Register: mi_sp_y_base_ad_init2: Base address 2 (ping pong) for main picture Y component, JPEG or raw data (0x0000013c)*/ +/*! Slice: sp_y_base_ad_init2:*/ +/*! 2nd ping pong base address of main picture Y component buffer, JPEG buffer or raw data buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_Y_BASE_AD_INIT2 +#define MRV_MI_SP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_SP_Y_BASE_AD_INIT2_SHIFT 3U +/*! Register: mi_sp_cb_base_ad_init2: Base address 2 (pingpong) for main picture Cb component (0x00000140)*/ +/*! Slice: sp_cb_base_ad_init2:*/ +/*! 2nd ping pong base address of main picture Cb component buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CB_BASE_AD_INIT2 +#define MRV_MI_SP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CB_BASE_AD_INIT2_SHIFT 3U +/*! Register: mi_sp_cr_base_ad_init2: Base address 2 (pingpong) for main picture Cr component ring buffer (0x00000144)*/ +/*! Slice: sp_cr_base_ad_init2:*/ +/*! 2nd ping pong Base address of main picture Cr component buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CR_BASE_AD_INIT2 +#define MRV_MI_SP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CR_BASE_AD_INIT2_SHIFT 3U +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Nano handshake */ +/*! Register: isp_handshake_ctrl_0: IspNano handshake functions (0x0000014C)*/ +/*! Slice: mp_handshake_en:*/ +/*! Enable mp handshake function for MI MP */ +#define MRV_MI_MP_HANDSHK_EN +#define MRV_MI_MP_HANDSHK_EN_MASK 0x00000001U +#define MRV_MI_MP_HANDSHK_EN_SHIFT 0U +/*! Slice: mp_handshk_storage_format */ +/*! Define how YCbCr picture data is stored in memory */ +/*! 00: Planar */ +/*! 01: Semi planar, for YCbCr4:2:x */ +/*! 10: Interleaved(combiled), for YCbCr 4:2:2 only or RAW format.*/ +/*! 11: not support */ +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_MASK 0x00000006U +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_SHIFT 1U +/*! Slice: mp_handshk_data_format */ +/*! Defines the video format */ +/*! 00: RAW format */ +/*! 01: reserved */ +/*! 10: YUV 422 */ +/*! 11: YUV 420 */ +#define MRV_MI_MP_HANDSHK_DATA_FORMAT +#define MRV_MI_MP_HANDSHK_DATA_FORMAT_MASK 0x00000018U +#define MRV_MI_MP_HANDSHK_DATA_FORMAT_SHIFT 3U +/*! Slice: mp_handshk_slice_size */ +/*! Defines the slice size to generate handshake signals, minus 1 is used */ +#define MRV_MI_MP_HANDSHK_SLICE_SIZE +#define MRV_MI_MP_HANDSHK_SLICE_SIZE_MASK 0x00001FE0U +#define MRV_MI_MP_HANDSHK_SLICE_SIZE_SHIFT 5U +/*! Slice: mp_handshk_slice_buf_size */ +/*! Defines the circular buffer size in number of defined slices per buffer, minus 1 is used */ +#define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE +#define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE_MASK 0x001FE000U +#define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE_SHIFT 13U +/*! Slice: mp_handshk_ack_count */ +/*! Defines the acknowledage is not received in the defined cycles, it will generate handshake interrupt.*/ +#define MRV_MI_MP_HANDSHK_ACK_COUNT +#define MRV_MI_MP_HANDSHK_ACK_COUNT_MASK 0x1FE00000U +#define MRV_MI_MP_HANDSHK_ACK_COUNT_SHIFT 21U +/*! Register: isp_handshake_mp_y_llength: IspNano handshake y_llength (0x00000150)*/ +/*! Slice: mp_y_llength, line length of main picture Y component or RGB picture in pixel.*/ +/*! Also knows as line stride, if no line stride is used, the line length must match image width.*/ +#define MRV_MI_MP_HANDSHK_Y_LLENGTH +#define MRV_MI_MP_HANDSHK_Y_LLENGTH_MASK 0x00007FFFU +#define MRV_MI_MP_HANDSHK_Y_LLENGTH_SHIFT 0U +/*! Register: isp_handshake_y_slice_offset: IspNano handshake y slice offset (0x00000154)*/ +/*! Slice: mp_y_slice_offset defines the offset bewteen two successive Y slice input buffers in bytes.*/ +#define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET +#define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET_MASK 0xFFFFFFF8U +#define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET_SHIFT 0U +/*! Register: isp_handshake_c_slice_offset: ISPNano handshake c slice offset (ox00000158)*/ +/*! Slice: mp_c_slice_offset defines the offset between two successive Cb/Cr slice input buffers in bytes.*/ +#define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET +#define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET_MASK 0xFFFFFFF8U +#define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET_SHIFT 0U +#endif +#ifdef ISP_MI_ALIGN_NANO +/*! Register mi_output_align_format for isp nano: (0x0000015C)*/ +/*! Slice mp_lsb_alignment:*/ +/*! msb/lsb align for raw 10 and raw 12 formats control */ +/*! 0: MSB aligned for RAW10 and RAW12 formats */ +/*! 1: LSB aligned for RAW10 and RAW12 formats */ +#define MRV_MI_LSB_ALIGNMENT +#define MRV_MI_LSB_ALIGNMENT_MASK 0x00000001U +#define MRV_MI_LSB_ALIGNMENT_SHIFT 0U +#endif +#ifdef ISP_MI_BYTESWAP +/*! Slice mp_byte_swap:*/ +/*! swap bytes for ISP Nano */ +/*! bit 0 to swap bytes */ +/*! bit 1 to swap words */ +/*! bit 2 to swap dwords */ +/*! 3'b001: ABCDEFGH => BADCFEHG */ +/*! 3'b000: ABCDEFGH => ABCDEFGH */ +/*! 3'b010: ABCDEFGH => CDABGHEF */ +/*! 3'b011: ABCDEFGH => DCBAHGFE */ +/*! 3'b100: ABCDEFGH => EFGHABCD */ +/*! 3'b101: ABCDEFGH => FEHGBADC */ +/*! 3'b110: ABCDEFGH => GHEFCDAB */ +/*! 3'b111: ABCDEFGH => HGFEDCBA */ +#define MRV_MI_MP_BYTE_SWAP +#define MRV_MI_MP_BYTE_SWAP_MASK 0x0000000EU +#define MRV_MI_MP_BYTE_SWAP_SHIFT 1U +#endif +#ifdef ISP_MI_FIFO_DEPTH_NANO +/*! Register mi_mp_output_fifo_size for isp nano: (0x00000160)*/ +/*! Slice output_fifo_depth:*/ +/*! Select output FIFO depth setting */ +/*! 00: FULL(2KBytes)*/ +/*! 01: HALF(1KBytes)*/ +/*! 10: 1/4(512Bytes)*/ +/*! 11: 1/8(256Bytes)*/ +#define MRV_MI_OUTOUT_FIFO_DEPTH +#define MRV_MI_OUTOUT_FIFO_DEPTH_MASK 0x00000003U +#define MRV_MI_OUTOUT_FIFO_DEPTH_SHIFT 0U +#endif +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Register mi_mp_y_pic_width: IspNano handshake mp_y_pic_width (0x00000164)*/ +/*! Slice mi_mp_y_pic_width:*/ +/*! Image width of the main picture Y component in pixel.*/ +#define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH +#define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH_SHIFT 0U +/*! Register mi_mp_y_pic_height: IspNano handshake mp_y_pic_height (0x00000168)*/ +/*! Slice mi_mp_y_pic_height:*/ +/*! Image height of the main picture Y component in pixel.*/ +#define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT +#define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT_SHIFT 0U +/*! Register mi_mp_y_pic_size: IspNano handshake mp_y_pic_size (0x0000016C)*/ +/*! Slice mi_mp_y_pic_size */ +/*! Image size of the Y component in pixel which has to be the Y line length multipled by */ +/*! the Y image height(mp_y_llength*mp_y_pic_height)*/ +#define MRV_MI_MP_HANDSHK_Y_PIC_ZISE +#define MRV_MI_MP_HANDSHK_Y_PIC_ZISE_MASK 0xFFFFFFFFU +#define MRV_MI_MP_HANDSHK_Y_PIC_ZISE_SHIFT 0U +#endif +/*! Register: jpe_gen_header: command to start stream header generation (0x00000000)*/ +/*! Slice: gen_header:*/ +/*! "1" = Start command to generate stream header;*/ +/* auto reset to zero after one clock cycle */ +#define MRV_JPE_GEN_HEADER +#define MRV_JPE_GEN_HEADER_MASK 0x00000001U +#define MRV_JPE_GEN_HEADER_SHIFT 0U +/*! Register: jpe_encode: Start command to start JFIF stream encoding (0x00000004)*/ +/*! Slice: encode:*/ +/*! "1" = Start command to start JFIF stream encoding;*/ +/* auto reset to zero after one clock cycle.*/ +/* This bit is write-only: reading result is always zero!*/ +#define MRV_JPE_ENCODE +#define MRV_JPE_ENCODE_MASK 0x00000001U +#define MRV_JPE_ENCODE_SHIFT 0U +/*! Register: jpe_init: Automatic configuration update (INIT) (0x00000008)*/ +/*! Slice: JP_INIT:*/ +/*! "1" = Immediate start of JPEG encoder.*/ +/* This bit has to be set after "Encode" to start the JPEG encoder. The "Encode" command becomes active either with JP_INIT or with the input signal "CFG_UPD".*/ +/* auto reset to zero after one clock cycle !!!*/ +#define MRV_JPE_JP_INIT +#define MRV_JPE_JP_INIT_MASK 0x00000001U +#define MRV_JPE_JP_INIT_SHIFT 0U +/*! Register: jpe_y_scale_en: Y value scaling control register (0x0000000c)*/ +/*! Slice: y_scale_en:*/ +/*! Y scale flag */ +/* 1: scaling Y input from[16..235] to[0..255]*/ +/* 0: no Y input scaling */ +#define MRV_JPE_Y_SCALE_EN +#define MRV_JPE_Y_SCALE_EN_MASK 0x00000001U +#define MRV_JPE_Y_SCALE_EN_SHIFT 0U +/*! Register: jpe_cbcr_scale_en: Cb/Cr value scaling control register (0x00000010)*/ +/*! Slice: cbcr_scale_en:*/ +/*! Cb/Cr scale flag */ +/* 1: scaling Cb/Cr input from[16..240] to[0..255]*/ +/* 0: no Cb/Cr input scaling */ +#define MRV_JPE_CBCR_SCALE_EN +#define MRV_JPE_CBCR_SCALE_EN_MASK 0x00000001U +#define MRV_JPE_CBCR_SCALE_EN_SHIFT 0U +/*! Register: jpe_table_flush: header generation debug register (0x00000014)*/ +/*! Slice: table_flush:*/ +/*! header generation debug control flag */ +/* (controls transmission of last header bytes if the 64 bit output buffer is not completely filled)*/ +/* 1: immediately transmit last header bytes */ +/* 0: wait for encoded image data to fill output buffer */ +#define MRV_JPE_TABLE_FLUSH +#define MRV_JPE_TABLE_FLUSH_MASK 0x00000001U +#define MRV_JPE_TABLE_FLUSH_SHIFT 0U +/*! Register: jpe_enc_hsize: JPEG codec horizontal image size for encoding (0x00000018)*/ +/*! Slice: enc_hsize:*/ +/*! JPEG codec horizontal image size for R2B and SGEN blocks.*/ +/* Note: If the active camerIC version does not support 64 megapixel only those bits will be used which are required and the respective most significant bits will be ignored. Example: 5MP camerIC uses only bits[12:0] and ignores bits[14:13].*/ +#define MRV_JPE_ENC_HSIZE +#define MRV_JPE_ENC_HSIZE_MASK 0x00007FFFU +#define MRV_JPE_ENC_HSIZE_SHIFT 0U +/*! Register: jpe_enc_vsize: JPEG codec vertical image size for encoding (0x0000001c)*/ +/*! Slice: enc_vsize:*/ +/*! JPEG codec vertical image size for R2B and SGEN blocks */ +#define MRV_JPE_ENC_VSIZE +#define MRV_JPE_ENC_VSIZE_MASK 0x00003FFFU +#define MRV_JPE_ENC_VSIZE_SHIFT 0U +/*! Register: jpe_pic_format: JPEG picture encoding format (0x00000020)*/ +/*! Slice: enc_pic_format:*/ +/*! "0:0:1" = 4:2:2 format */ +/* "1:x:x" = 4:0:0 format */ +#define MRV_JPE_ENC_PIC_FORMAT +#define MRV_JPE_ENC_PIC_FORMAT_MASK 0x00000007U +#define MRV_JPE_ENC_PIC_FORMAT_SHIFT 0U +/*! Register: jpe_restart_interval: restart marker insertion register (0x00000024)*/ +/*! Slice: restart_interval:*/ +/*! No of MCU in reset interval via host */ +#define MRV_JPE_RESTART_INTERVAL +#define MRV_JPE_RESTART_INTERVAL_MASK 0x0000FFFFU +#define MRV_JPE_RESTART_INTERVAL_SHIFT 0U +/*! Register: jpe_tq_y_select: Q- table selector 0, quant. table for Y component (0x00000028)*/ +/*! Slice: tq0_select:*/ +/*! "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#define MRV_JPE_TQ0_SELECT +#define MRV_JPE_TQ0_SELECT_MASK 0x00000003U +#define MRV_JPE_TQ0_SELECT_SHIFT 0U +/*! Register: jpe_tq_u_select: Q- table selector 1, quant. table for U component (0x0000002c)*/ +/*! Slice: tq1_select:*/ +/*! "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#define MRV_JPE_TQ1_SELECT +#define MRV_JPE_TQ1_SELECT_MASK 0x00000003U +#define MRV_JPE_TQ1_SELECT_SHIFT 0U +/*! Register: jpe_tq_v_select: Q- table selector 2, quant. table for V component (0x00000030)*/ +/*! Slice: tq2_select:*/ +/*! "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#define MRV_JPE_TQ2_SELECT +#define MRV_JPE_TQ2_SELECT_MASK 0x00000003U +#define MRV_JPE_TQ2_SELECT_SHIFT 0U +/*! Register: jpe_dc_table_select: Huffman table selector for DC values (0x00000034)*/ +/*! Slice: dc_table_select_v:*/ +/*! "0" = dc table 0; color component 2 (V)*/ +/* "1" = dc table 1; color component 2 (V)*/ +#define MRV_JPE_DC_TABLE_SELECT_V +#define MRV_JPE_DC_TABLE_SELECT_V_MASK 0x00000004U +#define MRV_JPE_DC_TABLE_SELECT_V_SHIFT 2U +/*! Slice: dc_table_select_u:*/ +/*! "0" = dc table 0; color component 1 (U)*/ +/* "1" = dc table 1; color component 1 (U)*/ +#define MRV_JPE_DC_TABLE_SELECT_U +#define MRV_JPE_DC_TABLE_SELECT_U_MASK 0x00000002U +#define MRV_JPE_DC_TABLE_SELECT_U_SHIFT 1U +/*! Slice: dc_table_select_y:*/ +/*! "0" = dc table 0; color component 0 (Y)*/ +/* "1" = dc table 1; color component 0 (Y)*/ +#define MRV_JPE_DC_TABLE_SELECT_Y +#define MRV_JPE_DC_TABLE_SELECT_Y_MASK 0x00000001U +#define MRV_JPE_DC_TABLE_SELECT_Y_SHIFT 0U +/*! Register: jpe_ac_table_select: Huffman table selector for AC values (0x00000038)*/ +/*! Slice: ac_table_select_v:*/ +/*! "0" = ac table 0; component 2 (V)*/ +/* "1" = ac table 1; component 2 (V)*/ +#define MRV_JPE_AC_TABLE_SELECT_V +#define MRV_JPE_AC_TABLE_SELECT_V_MASK 0x00000004U +#define MRV_JPE_AC_TABLE_SELECT_V_SHIFT 2U +/*! Slice: ac_table_select_u:*/ +/*! "0" = ac table 0; component 1 (U)*/ +/* "1" = ac table 1; component 1 (U)*/ +#define MRV_JPE_AC_TABLE_SELECT_U +#define MRV_JPE_AC_TABLE_SELECT_U_MASK 0x00000002U +#define MRV_JPE_AC_TABLE_SELECT_U_SHIFT 1U +/*! Slice: ac_table_select_y:*/ +/*! "0" = ac table 0; component 0 (Y)*/ +/* "1" = ac table 1; component 0 (Y)*/ +#define MRV_JPE_AC_TABLE_SELECT_Y +#define MRV_JPE_AC_TABLE_SELECT_Y_MASK 0x00000001U +#define MRV_JPE_AC_TABLE_SELECT_Y_SHIFT 0U +/*! Register: jpe_table_data: table programming register (0x0000003c)*/ +/*! Slice: table_wdata_h:*/ +/*! Table data MSB */ +#define MRV_JPE_TABLE_WDATA_H +#define MRV_JPE_TABLE_WDATA_H_MASK 0x0000FF00U +#define MRV_JPE_TABLE_WDATA_H_SHIFT 8U +/*! Slice: table_wdata_l:*/ +/*! Table data LSB */ +#define MRV_JPE_TABLE_WDATA_L +#define MRV_JPE_TABLE_WDATA_L_MASK 0x000000FFU +#define MRV_JPE_TABLE_WDATA_L_SHIFT 0U +/*! Register: jpe_table_id: table programming select register (0x00000040)*/ +/*! Slice: table_id:*/ +/*! select table */ +/* "0000" : Q-table 0 */ +/* "0001" : Q-table 1 */ +/* "0010" : Q-table 2 */ +/* "0011" : Q-table 3 */ +/* "0100" : VLC DC-table 0 */ +/* "0101" : VLC AC-table 0 */ +/* "0110" : VLC DC-table 1 */ +/* "0111" : VLC AC-table 1 */ +/* "1xxx" : reserved for debug */ +#define MRV_JPE_TABLE_ID +#define MRV_JPE_TABLE_ID_MASK 0x0000000FU +#define MRV_JPE_TABLE_ID_SHIFT 0U +/*! Register: jpe_tac0_len: Huffman AC table 0 length (0x00000044)*/ +/*! Slice: tac0_len:*/ +/*! Huffman table length for ac0 table */ +#define MRV_JPE_TAC0_LEN +#define MRV_JPE_TAC0_LEN_MASK 0x000000FFU +#define MRV_JPE_TAC0_LEN_SHIFT 0U +/*! Register: jpe_tdc0_len: Huffman DC table 0 length (0x00000048)*/ +/*! Slice: tdc0_len:*/ +/*! Huffman table length for dc0 table */ +#define MRV_JPE_TDC0_LEN +#define MRV_JPE_TDC0_LEN_MASK 0x000000FFU +#define MRV_JPE_TDC0_LEN_SHIFT 0U +/*! Register: jpe_tac1_len: Huffman AC table 1 length (0x0000004c)*/ +/*! Slice: tac1_len:*/ +/*! Huffman table length for ac1 table */ +#define MRV_JPE_TAC1_LEN +#define MRV_JPE_TAC1_LEN_MASK 0x000000FFU +#define MRV_JPE_TAC1_LEN_SHIFT 0U +/*! Register: jpe_tdc1_len: Huffman DC table 1 length (0x00000050)*/ +/*! Slice: tdc1_len:*/ +/*! Huffman table length for dc1 table */ +#define MRV_JPE_TDC1_LEN +#define MRV_JPE_TDC1_LEN_MASK 0x000000FFU +#define MRV_JPE_TDC1_LEN_SHIFT 0U +/*! Register: jpe_encoder_busy: encoder status flag (0x00000058)*/ +/*! Slice: codec_busy:*/ +/*! Bit 0 = "1" : JPEG codec in process */ +#define MRV_JPE_CODEC_BUSY +#define MRV_JPE_CODEC_BUSY_MASK 0x00000001U +#define MRV_JPE_CODEC_BUSY_SHIFT 0U +/*! Register: jpe_header_mode: header mode definition (0x0000005c)*/ +/*! Slice: header_mode:*/ +/*! "00" = no header */ +/* "01" = reserved */ +/* "10" = JFIF 1.02 header */ +/* "11" = reserved */ +#define MRV_JPE_HEADER_MODE +#define MRV_JPE_HEADER_MODE_MASK 0x00000003U +#define MRV_JPE_HEADER_MODE_SHIFT 0U +/*! Register: jpe_encode_mode: encode mode (0x00000060)*/ +/*! Slice: encode_mode:*/ +/*! Always "1", because this is the encoder only edition */ +#define MRV_JPE_ENCODE_MODE +#define MRV_JPE_ENCODE_MODE_MASK 0x00000001U +#define MRV_JPE_ENCODE_MODE_SHIFT 0U +/*! Register: jpe_debug: debug information register (0x00000064)*/ +/*! Slice: deb_bad_table_access:*/ +/*! Debug signal only (set if an access to the TABLE_DATA or to the TABLE_ID register is performed, when the JPEG_ENCODER is busy. In this case a default PVCI Acknowledge is generated. Thus the configuration bus is not blocked)*/ +#define MRV_JPE_DEB_BAD_TABLE_ACCESS +#define MRV_JPE_DEB_BAD_TABLE_ACCESS_MASK 0x00000100U +#define MRV_JPE_DEB_BAD_TABLE_ACCESS_SHIFT 8U +/*! Slice: deb_vlc_table_busy:*/ +/*! Debug signal only (vlc access to huff-tables)*/ +#define MRV_JPE_DEB_VLC_TABLE_BUSY +#define MRV_JPE_DEB_VLC_TABLE_BUSY_MASK 0x00000020U +#define MRV_JPE_DEB_VLC_TABLE_BUSY_SHIFT 5U +/*! Slice: deb_r2b_memory_full:*/ +/*! Debug signal only (line memory status of r2b)*/ +#define MRV_JPE_DEB_R2B_MEMORY_FULL +#define MRV_JPE_DEB_R2B_MEMORY_FULL_MASK 0x00000010U +#define MRV_JPE_DEB_R2B_MEMORY_FULL_SHIFT 4U +/*! Slice: deb_vlc_encode_busy:*/ +/*! Debug signal only (vlc encode processing active)*/ +#define MRV_JPE_DEB_VLC_ENCODE_BUSY +#define MRV_JPE_DEB_VLC_ENCODE_BUSY_MASK 0x00000008U +#define MRV_JPE_DEB_VLC_ENCODE_BUSY_SHIFT 3U +/*! Slice: deb_qiq_table_acc:*/ +/*! Debug signal only (QIQ table access)*/ +#define MRV_JPE_DEB_QIQ_TABLE_ACC +#define MRV_JPE_DEB_QIQ_TABLE_ACC_MASK 0x00000004U +#define MRV_JPE_DEB_QIQ_TABLE_ACC_SHIFT 2U +/*! Register: jpe_error_imr: JPEG error interrupt mask register (0x00000068)*/ +/*! Slice: vlc_table_err:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_VLC_TABLE_ERR +#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U +#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U +/*! Slice: r2b_IMG_size_err:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_R2B_IMG_SIZE_ERR +#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U +#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U +/*! Slice: DCT_ERR:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_DCT_ERR +#define MRV_JPE_DCT_ERR_MASK 0x00000080U +#define MRV_JPE_DCT_ERR_SHIFT 7U +/*! Slice: vlc_symbol_err:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_VLC_SYMBOL_ERR +#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U +#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U +/*! Register: jpe_error_ris: JPEG error raw interrupt status register (0x0000006c)*/ +/*! Slice: vlc_table_err:*/ +/*! "1" = illegal table detected */ +#define MRV_JPE_VLC_TABLE_ERR +#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U +#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U +/*! Slice: r2b_IMG_size_err:*/ +/*! "1" = mismatch of predefined h_size and v_size values with calculated values (encode mode)*/ +#define MRV_JPE_R2B_IMG_SIZE_ERR +#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U +#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U +/*! Slice: DCT_ERR:*/ +/*! "1" = block start mismatch */ +#define MRV_JPE_DCT_ERR +#define MRV_JPE_DCT_ERR_MASK 0x00000080U +#define MRV_JPE_DCT_ERR_SHIFT 7U +/*! Slice: vlc_symbol_err:*/ +/*! "1" = illegal symbol detected (encoding)*/ +#define MRV_JPE_VLC_SYMBOL_ERR +#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U +#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U +/*! Register: jpe_error_mis: JPEG error masked interrupt status register (0x00000070)*/ +/*! Slice: vlc_table_err:*/ +/*! "1" = illegal table detected */ +#define MRV_JPE_VLC_TABLE_ERR +#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U +#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U +/*! Slice: r2b_IMG_size_err:*/ +/*! "1" = mismatch of predefined h_size and v_size values with calculated values (encode mode)*/ +#define MRV_JPE_R2B_IMG_SIZE_ERR +#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U +#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U +/*! Slice: DCT_ERR:*/ +/*! "1" = block start mismatch */ +#define MRV_JPE_DCT_ERR +#define MRV_JPE_DCT_ERR_MASK 0x00000080U +#define MRV_JPE_DCT_ERR_SHIFT 7U +/*! Slice: vlc_symbol_err:*/ +/*! "1" = illegal symbol detected (encoding)*/ +#define MRV_JPE_VLC_SYMBOL_ERR +#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U +#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U +/*! Register: jpe_error_icr: JPEG error interrupt set register (0x00000074)*/ +/*! Slice: vlc_table_err:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_VLC_TABLE_ERR +#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U +#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U +/*! Slice: r2b_IMG_size_err:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_R2B_IMG_SIZE_ERR +#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U +#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U +/*! Slice: DCT_ERR:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_DCT_ERR +#define MRV_JPE_DCT_ERR_MASK 0x00000080U +#define MRV_JPE_DCT_ERR_SHIFT 7U +/*! Slice: vlc_symbol_err:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_VLC_SYMBOL_ERR +#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U +#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U +/*! Register: jpe_error_isr: JPEG error interrupt clear register (0x00000078)*/ +/*! Slice: vlc_table_err:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_VLC_TABLE_ERR +#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U +#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U +/*! Slice: r2b_IMG_size_err:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_R2B_IMG_SIZE_ERR +#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U +#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U +/*! Slice: dct_err:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_DCT_ERR +#define MRV_JPE_DCT_ERR_MASK 0x00000080U +#define MRV_JPE_DCT_ERR_SHIFT 7U +/*! Slice: vlc_symbol_err:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_VLC_SYMBOL_ERR +#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U +#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U +/*! Register: jpe_status_imr: JPEG status interrupt mask register (0x0000007c)*/ +/*! Slice: gen_header_done:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_GEN_HEADER_DONE +#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U +#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U +/*! Slice: encode_done:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_ENCODE_DONE +#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U +#define MRV_JPE_ENCODE_DONE_SHIFT 4U +/*! Register: jpe_status_ris: JPEG status raw interrupt status register (0x00000080)*/ +/*! Slice: gen_header_done:*/ +/*! "1" = Stream header generation finished */ +#define MRV_JPE_GEN_HEADER_DONE +#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U +#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U +/*! Slice: encode_done:*/ +/*! "1" = Encode processing finished */ +#define MRV_JPE_ENCODE_DONE +#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U +#define MRV_JPE_ENCODE_DONE_SHIFT 4U +/*! Register: jpe_status_mis: JPEG status masked interrupt status register (0x00000084)*/ +/*! Slice: gen_header_done:*/ +/*! "1" = Stream header generation finished */ +#define MRV_JPE_GEN_HEADER_DONE +#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U +#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U +/*! Slice: encode_done:*/ +/*! "1" = Encode processing finished */ +#define MRV_JPE_ENCODE_DONE +#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U +#define MRV_JPE_ENCODE_DONE_SHIFT 4U +/*! Register: jpe_status_icr: JPEG status interrupt clear register (0x00000088)*/ +/*! Slice: gen_header_done:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_GEN_HEADER_DONE +#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U +#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U +/*! Slice: encode_done:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_ENCODE_DONE +#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U +#define MRV_JPE_ENCODE_DONE_SHIFT 4U +/*! Register: jpe_status_isr: JPEG status interrupt set register (0x0000008c)*/ +/*! Slice: gen_header_done:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_GEN_HEADER_DONE +#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U +#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U +/*! Slice: encode_done:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_ENCODE_DONE +#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U +#define MRV_JPE_ENCODE_DONE_SHIFT 4U +/*! Register: jpe_config: JPEG configuration register (0x00000090)*/ +/*! Slice: speedview_en:*/ +/*! 1: speed view enabled */ +/* 0: speed view disabled */ +#define MRV_JPE_SPEEDVIEW_EN +#define MRV_JPE_SPEEDVIEW_EN_MASK 0x00000010U +#define MRV_JPE_SPEEDVIEW_EN_SHIFT 4U +/*! Slice: cont_mode:*/ +/*! Encoder continous mode */ +/* "00": encoder stops at frame end (corresponds to former behavior)*/ +/* "01": encoder starts automatically to encode the next frame */ +/* "10": unused */ +/* "11": encoder first generates next header and then encodes automatically the next frame */ +/* These settings are checked after encoding one frame. They are not auto-reset by hardware.*/ +#define MRV_JPE_CONT_MODE +#define MRV_JPE_CONT_MODE_MASK 0x00000003U +#define MRV_JPE_CONT_MODE_SHIFT 0U +/*! Register: smia_ctrl: global control register (0x00000000)*/ +/*! Slice: DMA_CHANNEL_SEL:*/ +/*! DMA channel selector for image data output */ +#define MRV_SMIA_DMA_CHANNEL_SEL +#define MRV_SMIA_DMA_CHANNEL_SEL_MASK 0x00000700U +#define MRV_SMIA_DMA_CHANNEL_SEL_SHIFT 8U +/*! Slice: SHUTDOWN_LANE:*/ +/*! Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown */ +#define MRV_SMIA_SHUTDOWN_LANE +#define MRV_SMIA_SHUTDOWN_LANE_MASK 0x00000008U +#define MRV_SMIA_SHUTDOWN_LANE_SHIFT 3U +/*! Slice: CFG_UPD_ENA:*/ +/*! enables generation of cfg_upd signal at frame end */ +#define MRV_SMIA_CFG_UPD_ENA +#define MRV_SMIA_CFG_UPD_ENA_MASK 0x00000004U +#define MRV_SMIA_CFG_UPD_ENA_SHIFT 2U +/*! Slice: FLUSH_FIFO:*/ +/*! writing '1' resets the write- and read pointers of the embedded data fifo.*/ +#define MRV_SMIA_FLUSH_FIFO +#define MRV_SMIA_FLUSH_FIFO_MASK 0x00000002U +#define MRV_SMIA_FLUSH_FIFO_SHIFT 1U +/*! Slice: OUTPUT_ENA:*/ +/*! '1': transmission to alomics output interface is enabled */ +/* '0': transmission is disabled */ +#define MRV_SMIA_OUTPUT_ENA +#define MRV_SMIA_OUTPUT_ENA_MASK 0x00000001U +#define MRV_SMIA_OUTPUT_ENA_SHIFT 0U +/*! Register: smia_status: global status register (0x00000004)*/ +/*! Slice: DMA_CHANNEL:*/ +/*! DMA channel of currently received packet */ +#define MRV_SMIA_DMA_CHANNEL +#define MRV_SMIA_DMA_CHANNEL_MASK 0x00000700U +#define MRV_SMIA_DMA_CHANNEL_SHIFT 8U +/*! Slice: EMB_DATA_AVAIL:*/ +/*! 1: embedded data fifo not empty */ +#define MRV_SMIA_EMB_DATA_AVAIL +#define MRV_SMIA_EMB_DATA_AVAIL_MASK 0x00000001U +#define MRV_SMIA_EMB_DATA_AVAIL_SHIFT 0U +/*! Register: smia_imsc: Interrupt mask (0x00000008)*/ +/*! Slice: IMSC_FIFO_FILL_LEVEL:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL +#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL_MASK 0x00000020U +#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL_SHIFT 5U +/*! Slice: IMSC_SYNC_FIFO_OVFLW:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW +#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_MASK 0x00000010U +#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_SHIFT 4U +/*! Slice: IMSC_ERR_CS:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_ERR_CS +#define MRV_SMIA_IMSC_ERR_CS_MASK 0x00000008U +#define MRV_SMIA_IMSC_ERR_CS_SHIFT 3U +/*! Slice: IMSC_ERR_PROTOCOL:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_ERR_PROTOCOL +#define MRV_SMIA_IMSC_ERR_PROTOCOL_MASK 0x00000004U +#define MRV_SMIA_IMSC_ERR_PROTOCOL_SHIFT 2U +/*! Slice: IMSC_EMB_DATA_OVFLW:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_EMB_DATA_OVFLW +#define MRV_SMIA_IMSC_EMB_DATA_OVFLW_MASK 0x00000002U +#define MRV_SMIA_IMSC_EMB_DATA_OVFLW_SHIFT 1U +/*! Slice: IMSC_FRAME_END:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_FRAME_END +#define MRV_SMIA_IMSC_FRAME_END_MASK 0x00000001U +#define MRV_SMIA_IMSC_FRAME_END_SHIFT 0U +/*! Register: smia_ris: Raw interrupt status (0x0000000c)*/ +/*! Slice: RIS_FIFO_FILL_LEVEL:*/ +/*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */ +#define MRV_SMIA_RIS_FIFO_FILL_LEVEL +#define MRV_SMIA_RIS_FIFO_FILL_LEVEL_MASK 0x00000020U +#define MRV_SMIA_RIS_FIFO_FILL_LEVEL_SHIFT 5U +/*! Slice: RIS_SYNC_FIFO_OVFLW:*/ +/*! Sync fifo overflow error */ +#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW +#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW_MASK 0x00000010U +#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW_SHIFT 4U +/*! Slice: RIS_ERR_CS:*/ +/*! Checksum error */ +#define MRV_SMIA_RIS_ERR_CS +#define MRV_SMIA_RIS_ERR_CS_MASK 0x00000008U +#define MRV_SMIA_RIS_ERR_CS_SHIFT 3U +/*! Slice: RIS_ERR_PROTOCOL:*/ +/*! Protocol error */ +#define MRV_SMIA_RIS_ERR_PROTOCOL +#define MRV_SMIA_RIS_ERR_PROTOCOL_MASK 0x00000004U +#define MRV_SMIA_RIS_ERR_PROTOCOL_SHIFT 2U +/*! Slice: RIS_EMB_DATA_OVFLW:*/ +/*! Embedded data fifo overflow error */ +#define MRV_SMIA_RIS_EMB_DATA_OVFLW +#define MRV_SMIA_RIS_EMB_DATA_OVFLW_MASK 0x00000002U +#define MRV_SMIA_RIS_EMB_DATA_OVFLW_SHIFT 1U +/*! Slice: RIS_FRAME_END:*/ +/*! Frame end reached */ +#define MRV_SMIA_RIS_FRAME_END +#define MRV_SMIA_RIS_FRAME_END_MASK 0x00000001U +#define MRV_SMIA_RIS_FRAME_END_SHIFT 0U +/*! Register: smia_mis: Masked interrupt status (0x00000010)*/ +/*! Slice: MIS_FIFO_FILL_LEVEL:*/ +/*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */ +#define MRV_SMIA_MIS_FIFO_FILL_LEVEL +#define MRV_SMIA_MIS_FIFO_FILL_LEVEL_MASK 0x00000020U +#define MRV_SMIA_MIS_FIFO_FILL_LEVEL_SHIFT 5U +/*! Slice: MIS_SYNC_FIFO_OVFLW:*/ +/*! Sync fifo overflow error */ +#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW +#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW_MASK 0x00000010U +#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW_SHIFT 4U +/*! Slice: MIS_ERR_CS:*/ +/*! Checksum error */ +#define MRV_SMIA_MIS_ERR_CS +#define MRV_SMIA_MIS_ERR_CS_MASK 0x00000008U +#define MRV_SMIA_MIS_ERR_CS_SHIFT 3U +/*! Slice: MIS_ERR_PROTOCOL:*/ +/*! Protocol error */ +#define MRV_SMIA_MIS_ERR_PROTOCOL +#define MRV_SMIA_MIS_ERR_PROTOCOL_MASK 0x00000004U +#define MRV_SMIA_MIS_ERR_PROTOCOL_SHIFT 2U +/*! Slice: MIS_EMB_DATA_OVFLW:*/ +/*! Embedded data fifo overflow error */ +#define MRV_SMIA_MIS_EMB_DATA_OVFLW +#define MRV_SMIA_MIS_EMB_DATA_OVFLW_MASK 0x00000002U +#define MRV_SMIA_MIS_EMB_DATA_OVFLW_SHIFT 1U +/*! Slice: MIS_FRAME_END:*/ +/*! Frame end reached */ +#define MRV_SMIA_MIS_FRAME_END +#define MRV_SMIA_MIS_FRAME_END_MASK 0x00000001U +#define MRV_SMIA_MIS_FRAME_END_SHIFT 0U +/*! Register: smia_icr: Interrupt clear register (0x00000014)*/ +/*! Slice: ICR_FIFO_FILL_LEVEL:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_FIFO_FILL_LEVEL +#define MRV_SMIA_ICR_FIFO_FILL_LEVEL_MASK 0x00000020U +#define MRV_SMIA_ICR_FIFO_FILL_LEVEL_SHIFT 5U +/*! Slice: ICR_SYNC_FIFO_OVFLW:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW +#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW_MASK 0x00000010U +#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW_SHIFT 4U +/*! Slice: ICR_ERR_CS:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_ERR_CS +#define MRV_SMIA_ICR_ERR_CS_MASK 0x00000008U +#define MRV_SMIA_ICR_ERR_CS_SHIFT 3U +/*! Slice: ICR_ERR_PROTOCOL:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_ERR_PROTOCOL +#define MRV_SMIA_ICR_ERR_PROTOCOL_MASK 0x00000004U +#define MRV_SMIA_ICR_ERR_PROTOCOL_SHIFT 2U +/*! Slice: ICR_EMB_DATA_OVFLW:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_EMB_DATA_OVFLW +#define MRV_SMIA_ICR_EMB_DATA_OVFLW_MASK 0x00000002U +#define MRV_SMIA_ICR_EMB_DATA_OVFLW_SHIFT 1U +/*! Slice: ICR_FRAME_END:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_FRAME_END +#define MRV_SMIA_ICR_FRAME_END_MASK 0x00000001U +#define MRV_SMIA_ICR_FRAME_END_SHIFT 0U +/*! Register: smia_isr: Interrupt set register (0x00000018)*/ +/*! Slice: ISR_FIFO_FILL_LEVEL:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_FIFO_FILL_LEVEL +#define MRV_SMIA_ISR_FIFO_FILL_LEVEL_MASK 0x00000020U +#define MRV_SMIA_ISR_FIFO_FILL_LEVEL_SHIFT 5U +/*! Slice: ISR_SYNC_FIFO_OVFLW:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW +#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW_MASK 0x00000010U +#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW_SHIFT 4U +/*! Slice: ISR_ERR_CS:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_ERR_CS +#define MRV_SMIA_ISR_ERR_CS_MASK 0x00000008U +#define MRV_SMIA_ISR_ERR_CS_SHIFT 3U +/*! Slice: ISR_ERR_PROTOCOL:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_ERR_PROTOCOL +#define MRV_SMIA_ISR_ERR_PROTOCOL_MASK 0x00000004U +#define MRV_SMIA_ISR_ERR_PROTOCOL_SHIFT 2U +/*! Slice: ISR_EMB_DATA_OVFLW:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_EMB_DATA_OVFLW +#define MRV_SMIA_ISR_EMB_DATA_OVFLW_MASK 0x00000002U +#define MRV_SMIA_ISR_EMB_DATA_OVFLW_SHIFT 1U +/*! Slice: ISR_FRAME_END:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_FRAME_END +#define MRV_SMIA_ISR_FRAME_END_MASK 0x00000001U +#define MRV_SMIA_ISR_FRAME_END_SHIFT 0U +/*! Register: smia_data_format_sel: data format selector register (0x0000001c)*/ +/*! Slice: DATA_FORMAT_SEL:*/ +/*! data format selector:*/ +/* 0x0: YUV 422 */ +/* 0x1: YUV 420 */ +/* 0x4: RGB 444 */ +/* 0x5: RGB 565 */ +/* 0x6: RGB 888 */ +/* 0x8: RAW 6 */ +/* 0x9: RAW 7 */ +/* 0xA: RAW 8 */ +/* 0xB: RAW 10 */ +/* 0xC: RAW 12 */ +/* 0xD: RAW 8-bit to 10-bit decompression */ +/* 0xF: compressed */ +/* 0x2, 0x3, 0x7, 0xE: reserved, no output */ +#define MRV_SMIA_DATA_FORMAT_SEL +#define MRV_SMIA_DATA_FORMAT_SEL_MASK 0x0000000FU +#define MRV_SMIA_DATA_FORMAT_SEL_SHIFT 0U +/*! Register: smia_sof_emb_data_lines: start of frame embedded data lines register (0x00000020)*/ +/*! Slice: SOF_EMB_DATA_LINES:*/ +/*! number of embedded data lines at frame start */ +#define MRV_SMIA_SOF_EMB_DATA_LINES +#define MRV_SMIA_SOF_EMB_DATA_LINES_MASK 0x00000007U +#define MRV_SMIA_SOF_EMB_DATA_LINES_SHIFT 0U +/*! Register: smia_emb_hstart: embedded data hstart register (0x00000024)*/ +/*! Slice: EMB_HSTART:*/ +/*! horizontal start position of captured embedded data.*/ +/* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/ +#define MRV_SMIA_EMB_HSTART +#define MRV_SMIA_EMB_HSTART_MASK 0x00007FFCU +#define MRV_SMIA_EMB_HSTART_SHIFT 2U +/*! Register: smia_emb_hsize: embedded data hsize register (0x00000028)*/ +/*! Slice: EMB_HSIZE:*/ +/*! number of captured embedded data dwords per line */ +/* '0' means no capturing of embedded data.*/ +/* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/ +#define MRV_SMIA_EMB_HSIZE +#define MRV_SMIA_EMB_HSIZE_MASK 0x00007FFCU +#define MRV_SMIA_EMB_HSIZE_SHIFT 2U +/*! Register: smia_emb_vstart: embedded data vstart register (0x0000002c)*/ +/*! Slice: EMB_VSTART:*/ +/*! start line of embedded data extraction.*/ +/* '0' means no capturing of embedded data */ +#define MRV_SMIA_EMB_VSTART +#define MRV_SMIA_EMB_VSTART_MASK 0x00003FFFU +#define MRV_SMIA_EMB_VSTART_SHIFT 0U +/*! Register: smia_num_lines: image data lines register (0x00000030)*/ +/*! Slice: NUM_LINES:*/ +/*! number of image data lines per frame */ +#define MRV_SMIA_NUM_LINES +#define MRV_SMIA_NUM_LINES_MASK 0x00003FFFU +#define MRV_SMIA_NUM_LINES_SHIFT 0U +/*! Register: smia_emb_data_fifo: Embedded Data Fifo (0x00000034)*/ +/*! Slice: EMB_DATA_FIFO:*/ +/*! lowest 4 bytes in embedded data fifo;*/ +/* reading increments fifo read pointer.*/ +/* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/ +#define MRV_SMIA_EMB_DATA_FIFO +#define MRV_SMIA_EMB_DATA_FIFO_MASK 0xFFFFFFFFU +#define MRV_SMIA_EMB_DATA_FIFO_SHIFT 0U +/*! Register: smia_fifo_fill_level: Embedded Data FIFO Fill Level (0x00000038)*/ +/*! Slice: FIFO_FILL_LEVEL:*/ +/*! FIFO level in dwords for triggering the fill level interrupt.*/ +/* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/ +#define MRV_SMIA_FIFO_FILL_LEVEL +#define MRV_SMIA_FIFO_FILL_LEVEL_MASK 0x000003FFU +#define MRV_SMIA_FIFO_FILL_LEVEL_SHIFT 0U +/*! Register: mipi_ctrl: global control register (0x00000000)*/ +/*! Slice: S_ENABLE_CLK:*/ +/*! Sensor clock lane enable signal. This register is directly connected to the output port "s_enableclk".*/ +/* '1': enable sensor clock lane (DEFAULT)*/ +/* '0': disable sensor clock lane */ +#define MRV_MIPI_S_ENABLE_CLK +#define MRV_MIPI_S_ENABLE_CLK_MASK 0x00040000U +#define MRV_MIPI_S_ENABLE_CLK_SHIFT 18U +/*! Slice: ERR_SOT_SYNC_HS_SKIP:*/ +/*! 1: data within the current transmission is skipped if ErrSotSyncHS is detected (default)*/ +/* 0: ErrSotSyncHS does not affect transmission */ +#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP +#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP_MASK 0x00020000U +#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP_SHIFT 17U +/*! Slice: ERR_SOT_HS_SKIP:*/ +/*! 1: data within the current transmission is skipped if ErrSotHS is detected */ +/* 0: ErrSotHS does not affect transmission (default)*/ +#define MRV_MIPI_ERR_SOT_HS_SKIP +#define MRV_MIPI_ERR_SOT_HS_SKIP_MASK 0x00010000U +#define MRV_MIPI_ERR_SOT_HS_SKIP_SHIFT 16U +/*! Slice: NUM_LANES:*/ +/*! 00: Lane 1 is used */ +/* 01: Lanes 1 and 2 are used */ +/* 10: Lanes 1, 2 and 3 are used */ +/* 11: Lanes 1, 2, 3 and 4 are used (default)*/ +#define MRV_MIPI_NUM_LANES +#define MRV_MIPI_NUM_LANES_MASK 0x00003000U +#define MRV_MIPI_NUM_LANES_SHIFT 12U +/*! Slice: SHUTDOWN_LANE:*/ +/*! Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown[n-1:0] where n denotes the lane number 1..4 */ +#define MRV_MIPI_SHUTDOWN_LANE +#define MRV_MIPI_SHUTDOWN_LANE_MASK 0x00000F00U +#define MRV_MIPI_SHUTDOWN_LANE_SHIFT 8U +/*! Slice: FLUSH_FIFO:*/ +/*! writing '1' resets the write- and read pointers of the additional data fifo, reading returns the status of the flush_fifo bit. This bit must be reset by software.*/ +#define MRV_MIPI_FLUSH_FIFO +#define MRV_MIPI_FLUSH_FIFO_MASK 0x00000002U +#define MRV_MIPI_FLUSH_FIFO_SHIFT 1U +/*! Slice: OUTPUT_ENA:*/ +/*! 1: output to add data fifo and to output interface is enabled */ +/* 0: output is disabled */ +#define MRV_MIPI_OUTPUT_ENA +#define MRV_MIPI_OUTPUT_ENA_MASK 0x00000001U +#define MRV_MIPI_OUTPUT_ENA_SHIFT 0U +/*! Register: mipi_status: global status register (0x00000004)*/ +/*! Slice: S_ULP_ACTIVE_NOT_CLK:*/ +/*! sensor clock lane is in ULP state. This register is directly connected to the synchronized input signal "s_ulpsactivenotclk"*/ +#define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK +#define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK_MASK 0x00002000U +#define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK_SHIFT 13U +/*! Slice: S_STOPSTATE_CLK:*/ +/*! sensor clock lane is in stopstate. This register is directly connected to the synchronized input signal "s_stopstateclk"*/ +#define MRV_MIPI_S_STOPSTATE_CLK +#define MRV_MIPI_S_STOPSTATE_CLK_MASK 0x00001000U +#define MRV_MIPI_S_STOPSTATE_CLK_SHIFT 12U +/*! Slice: STOPSTATE:*/ +/*! Data Lane is in stopstate. This register is directly connected to the synchronized input signal stopstate[n-1:0] where n denotes the lane number 1..4 */ +#define MRV_MIPI_STOPSTATE +#define MRV_MIPI_STOPSTATE_MASK 0x00000F00U +#define MRV_MIPI_STOPSTATE_SHIFT 8U +/*! Slice: ADD_DATA_AVAIL:*/ +/*! 1: additional data fifo contains data */ +/* 0: additional data fifo is empty */ +#define MRV_MIPI_ADD_DATA_AVAIL +#define MRV_MIPI_ADD_DATA_AVAIL_MASK 0x00000001U +#define MRV_MIPI_ADD_DATA_AVAIL_SHIFT 0U +/*! Register: mipi_imsc: Interrupt mask (0x00000008)*/ +/*! Slice: IMSC_GEN_SHORT_PACK:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_GEN_SHORT_PACK +#define MRV_MIPI_IMSC_GEN_SHORT_PACK_MASK 0x08000000U +#define MRV_MIPI_IMSC_GEN_SHORT_PACK_SHIFT 27U +/*! Slice: IMSC_ADD_DATA_FILL_LEVEL:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK 0x04000000U +#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_SHIFT 26U +/*! Slice: IMSC_ADD_DATA_OVFLW:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ADD_DATA_OVFLW +#define MRV_MIPI_IMSC_ADD_DATA_OVFLW_MASK 0x02000000U +#define MRV_MIPI_IMSC_ADD_DATA_OVFLW_SHIFT 25U +/*! Slice: IMSC_FRAME_END:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_FRAME_END +#define MRV_MIPI_IMSC_FRAME_END_MASK 0x01000000U +#define MRV_MIPI_IMSC_FRAME_END_SHIFT 24U +/*! Slice: IMSC_ERR_CS:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ERR_CS +#define MRV_MIPI_IMSC_ERR_CS_MASK 0x00800000U +#define MRV_MIPI_IMSC_ERR_CS_SHIFT 23U +/*! Slice: IMSC_ERR_ECC1:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ERR_ECC1 +#define MRV_MIPI_IMSC_ERR_ECC1_MASK 0x00400000U +#define MRV_MIPI_IMSC_ERR_ECC1_SHIFT 22U +/*! Slice: IMSC_ERR_ECC2:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ERR_ECC2 +#define MRV_MIPI_IMSC_ERR_ECC2_MASK 0x00200000U +#define MRV_MIPI_IMSC_ERR_ECC2_SHIFT 21U +/*! Slice: IMSC_ERR_PROTOCOL:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ERR_PROTOCOL +#define MRV_MIPI_IMSC_ERR_PROTOCOL_MASK 0x00100000U +#define MRV_MIPI_IMSC_ERR_PROTOCOL_SHIFT 20U +/*! Slice: IMSC_ERR_CONTROL:*/ +/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#define MRV_MIPI_IMSC_ERR_CONTROL +#define MRV_MIPI_IMSC_ERR_CONTROL_MASK 0x000F0000U +#define MRV_MIPI_IMSC_ERR_CONTROL_SHIFT 16U +/*! Slice: IMSC_ERR_EOT_SYNC:*/ +/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#define MRV_MIPI_IMSC_ERR_EOT_SYNC +#define MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK 0x0000F000U +#define MRV_MIPI_IMSC_ERR_EOT_SYNC_SHIFT 12U +/*! Slice: IMSC_ERR_SOT_SYNC:*/ +/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#define MRV_MIPI_IMSC_ERR_SOT_SYNC +#define MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK 0x00000F00U +#define MRV_MIPI_IMSC_ERR_SOT_SYNC_SHIFT 8U +/*! Slice: IMSC_ERR_SOT:*/ +/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#define MRV_MIPI_IMSC_ERR_SOT +#define MRV_MIPI_IMSC_ERR_SOT_MASK 0x000000F0U +#define MRV_MIPI_IMSC_ERR_SOT_SHIFT 4U +/*! Slice: IMSC_SYNC_FIFO_OVFLW:*/ +/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW +#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK 0x0000000FU +#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_SHIFT 0U +/*! Register: mipi_ris: Raw interrupt status (0x0000000c)*/ +/*! Slice: RIS_GEN_SHORT_PACK:*/ +/*! generic short packet was received (only available in version 2 of MIPI interface)*/ + /**/ +/* When this interrupt is cleared, all the bits of the MIPI_GEN_SHORT_DT status register are cleared as well; Setting of this interrupt via MIPI_ISR register will set all the bits of the MIPI_GEN_SHORT_DT register.*/ +#define MRV_MIPI_RIS_GEN_SHORT_PACK +#define MRV_MIPI_RIS_GEN_SHORT_PACK_MASK 0x08000000U +#define MRV_MIPI_RIS_GEN_SHORT_PACK_SHIFT 27U +/*! Slice: RIS_ADD_DATA_FILL_LEVEL:*/ +/*! Programmed fill level was reached; will be raised as long as the fill level is greater than the programmed value */ +#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK 0x04000000U +#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_SHIFT 26U +/*! Slice: RIS_ADD_DATA_OVFLW:*/ +/*! additional data fifo overflow occurred */ +#define MRV_MIPI_RIS_ADD_DATA_OVFLW +#define MRV_MIPI_RIS_ADD_DATA_OVFLW_MASK 0x02000000U +#define MRV_MIPI_RIS_ADD_DATA_OVFLW_SHIFT 25U +/*! Slice: RIS_FRAME_END:*/ +/*! frame end send to output interface */ +#define MRV_MIPI_RIS_FRAME_END +#define MRV_MIPI_RIS_FRAME_END_MASK 0x01000000U +#define MRV_MIPI_RIS_FRAME_END_SHIFT 24U +/*! Slice: RIS_ERR_CS:*/ +/*! checksum error occurred */ +#define MRV_MIPI_RIS_ERR_CS +#define MRV_MIPI_RIS_ERR_CS_MASK 0x00800000U +#define MRV_MIPI_RIS_ERR_CS_SHIFT 23U +/*! Slice: RIS_ERR_ECC1:*/ +/*! 1-bit ecc error occurred */ +#define MRV_MIPI_RIS_ERR_ECC1 +#define MRV_MIPI_RIS_ERR_ECC1_MASK 0x00400000U +#define MRV_MIPI_RIS_ERR_ECC1_SHIFT 22U +/*! Slice: RIS_ERR_ECC2:*/ +/*! 2-bit ecc error occurred */ +#define MRV_MIPI_RIS_ERR_ECC2 +#define MRV_MIPI_RIS_ERR_ECC2_MASK 0x00200000U +#define MRV_MIPI_RIS_ERR_ECC2_SHIFT 21U +/*! Slice: RIS_ERR_PROTOCOL:*/ +/*! packet start detected within current packet */ +#define MRV_MIPI_RIS_ERR_PROTOCOL +#define MRV_MIPI_RIS_ERR_PROTOCOL_MASK 0x00100000U +#define MRV_MIPI_RIS_ERR_PROTOCOL_SHIFT 20U +/*! Slice: RIS_ERR_CONTROL:*/ +/*! PPI interface control error occured, one bit for each lane */ +#define MRV_MIPI_RIS_ERR_CONTROL +#define MRV_MIPI_RIS_ERR_CONTROL_MASK 0x000F0000U +#define MRV_MIPI_RIS_ERR_CONTROL_SHIFT 16U +/*! Slice: RIS_ERR_EOT_SYNC:*/ +/*! PPI interface eot sync error occured, one bit for each lane */ +#define MRV_MIPI_RIS_ERR_EOT_SYNC +#define MRV_MIPI_RIS_ERR_EOT_SYNC_MASK 0x0000F000U +#define MRV_MIPI_RIS_ERR_EOT_SYNC_SHIFT 12U +/*! Slice: RIS_ERR_SOT_SYNC:*/ +/*! PPI interface sot sync error occured, one bit for each lane */ +#define MRV_MIPI_RIS_ERR_SOT_SYNC +#define MRV_MIPI_RIS_ERR_SOT_SYNC_MASK 0x00000F00U +#define MRV_MIPI_RIS_ERR_SOT_SYNC_SHIFT 8U +/*! Slice: RIS_ERR_SOT:*/ +/*! PPI interface sot error occured, one bit for each lane */ +#define MRV_MIPI_RIS_ERR_SOT +#define MRV_MIPI_RIS_ERR_SOT_MASK 0x000000F0U +#define MRV_MIPI_RIS_ERR_SOT_SHIFT 4U +/*! Slice: RIS_SYNC_FIFO_OVFLW:*/ +/*! synchronization fifo overflow occurred, one bit for each lane */ +#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW +#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK 0x0000000FU +#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_SHIFT 0U +/*! Register: mipi_mis: Masked interrupt status (0x00000010)*/ +/*! Slice: MIS_GEN_SHORT_PACK:*/ +/*! generic short packet was received (only available in version 2 of MIPI interface)*/ +#define MRV_MIPI_MIS_GEN_SHORT_PACK +#define MRV_MIPI_MIS_GEN_SHORT_PACK_MASK 0x08000000U +#define MRV_MIPI_MIS_GEN_SHORT_PACK_SHIFT 27U +/*! Slice: MIS_ADD_DATA_FILL_LEVEL:*/ +/*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */ +#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK 0x04000000U +#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_SHIFT 26U +/*! Slice: MIS_ADD_DATA_OVFLW:*/ +/*! additional data fifo overflow */ +#define MRV_MIPI_MIS_ADD_DATA_OVFLW +#define MRV_MIPI_MIS_ADD_DATA_OVFLW_MASK 0x02000000U +#define MRV_MIPI_MIS_ADD_DATA_OVFLW_SHIFT 25U +/*! Slice: MIS_FRAME_END:*/ +/*! frame end send to output interface */ +#define MRV_MIPI_MIS_FRAME_END +#define MRV_MIPI_MIS_FRAME_END_MASK 0x01000000U +#define MRV_MIPI_MIS_FRAME_END_SHIFT 24U +/*! Slice: MIS_ERR_CS:*/ +/*! checksum error occurred */ +#define MRV_MIPI_MIS_ERR_CS +#define MRV_MIPI_MIS_ERR_CS_MASK 0x00800000U +#define MRV_MIPI_MIS_ERR_CS_SHIFT 23U +/*! Slice: MIS_ERR_ECC1:*/ +/*! 1-bit ecc error occurred */ +#define MRV_MIPI_MIS_ERR_ECC1 +#define MRV_MIPI_MIS_ERR_ECC1_MASK 0x00400000U +#define MRV_MIPI_MIS_ERR_ECC1_SHIFT 22U +/*! Slice: MIS_ERR_ECC2:*/ +/*! 2-bit ecc error occurred */ +#define MRV_MIPI_MIS_ERR_ECC2 +#define MRV_MIPI_MIS_ERR_ECC2_MASK 0x00200000U +#define MRV_MIPI_MIS_ERR_ECC2_SHIFT 21U +/*! Slice: MIS_ERR_PROTOCOL:*/ +/*! packet start detected within current packet */ +#define MRV_MIPI_MIS_ERR_PROTOCOL +#define MRV_MIPI_MIS_ERR_PROTOCOL_MASK 0x00100000U +#define MRV_MIPI_MIS_ERR_PROTOCOL_SHIFT 20U +/*! Slice: MIS_ERR_CONTROL:*/ +/*! PPI interface control error occured, one bit for each lane */ +#define MRV_MIPI_MIS_ERR_CONTROL +#define MRV_MIPI_MIS_ERR_CONTROL_MASK 0x000F0000U +#define MRV_MIPI_MIS_ERR_CONTROL_SHIFT 16U +/*! Slice: MIS_ERR_EOT_SYNC:*/ +/*! PPI interface eot sync error occured, one bit for each lane */ +#define MRV_MIPI_MIS_ERR_EOT_SYNC +#define MRV_MIPI_MIS_ERR_EOT_SYNC_MASK 0x0000F000U +#define MRV_MIPI_MIS_ERR_EOT_SYNC_SHIFT 12U +/*! Slice: MIS_ERR_SOT_SYNC:*/ +/*! PPI interface sot sync error occured, one bit for each lane */ +#define MRV_MIPI_MIS_ERR_SOT_SYNC +#define MRV_MIPI_MIS_ERR_SOT_SYNC_MASK 0x00000F00U +#define MRV_MIPI_MIS_ERR_SOT_SYNC_SHIFT 8U +/*! Slice: MIS_ERR_SOT:*/ +/*! PPI interface sot error occured, one bit for each lane */ +#define MRV_MIPI_MIS_ERR_SOT +#define MRV_MIPI_MIS_ERR_SOT_MASK 0x000000F0U +#define MRV_MIPI_MIS_ERR_SOT_SHIFT 4U +/*! Slice: MIS_SYNC_FIFO_OVFLW:*/ +/*! synchronization fifo overflow occurred, one bit for each lane */ +#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW +#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK 0x0000000FU +#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_SHIFT 0U +/*! Register: mipi_icr: Interrupt clear register (0x00000014)*/ +/*! Slice: ICR_GEN_SHORT_PACK:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_GEN_SHORT_PACK +#define MRV_MIPI_ICR_GEN_SHORT_PACK_MASK 0x08000000U +#define MRV_MIPI_ICR_GEN_SHORT_PACK_SHIFT 27U +/*! Slice: ICR_ADD_DATA_FILL_LEVEL:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK 0x04000000U +#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_SHIFT 26U +/*! Slice: ICR_ADD_DATA_OVFLW:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ADD_DATA_OVFLW +#define MRV_MIPI_ICR_ADD_DATA_OVFLW_MASK 0x02000000U +#define MRV_MIPI_ICR_ADD_DATA_OVFLW_SHIFT 25U +/*! Slice: ICR_FRAME_END:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_FRAME_END +#define MRV_MIPI_ICR_FRAME_END_MASK 0x01000000U +#define MRV_MIPI_ICR_FRAME_END_SHIFT 24U +/*! Slice: ICR_ERR_CS:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ERR_CS +#define MRV_MIPI_ICR_ERR_CS_MASK 0x00800000U +#define MRV_MIPI_ICR_ERR_CS_SHIFT 23U +/*! Slice: ICR_ERR_ECC1:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ERR_ECC1 +#define MRV_MIPI_ICR_ERR_ECC1_MASK 0x00400000U +#define MRV_MIPI_ICR_ERR_ECC1_SHIFT 22U +/*! Slice: ICR_ERR_ECC2:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ERR_ECC2 +#define MRV_MIPI_ICR_ERR_ECC2_MASK 0x00200000U +#define MRV_MIPI_ICR_ERR_ECC2_SHIFT 21U +/*! Slice: ICR_ERR_PROTOCOL:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ERR_PROTOCOL +#define MRV_MIPI_ICR_ERR_PROTOCOL_MASK 0x00100000U +#define MRV_MIPI_ICR_ERR_PROTOCOL_SHIFT 20U +/*! Slice: ICR_ERR_CONTROL:*/ +/*! 1: clear register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ICR_ERR_CONTROL +#define MRV_MIPI_ICR_ERR_CONTROL_MASK 0x000F0000U +#define MRV_MIPI_ICR_ERR_CONTROL_SHIFT 16U +/*! Slice: ICR_ERR_EOT_SYNC:*/ +/*! 1: clear register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ICR_ERR_EOT_SYNC +#define MRV_MIPI_ICR_ERR_EOT_SYNC_MASK 0x0000F000U +#define MRV_MIPI_ICR_ERR_EOT_SYNC_SHIFT 12U +/*! Slice: ICR_ERR_SOT_SYNC:*/ +/*! 1: clear register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ICR_ERR_SOT_SYNC +#define MRV_MIPI_ICR_ERR_SOT_SYNC_MASK 0x00000F00U +#define MRV_MIPI_ICR_ERR_SOT_SYNC_SHIFT 8U +/*! Slice: ICR_ERR_SOT:*/ +/*! 1: clear register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ICR_ERR_SOT +#define MRV_MIPI_ICR_ERR_SOT_MASK 0x000000F0U +#define MRV_MIPI_ICR_ERR_SOT_SHIFT 4U +/*! Slice: ICR_SYNC_FIFO_OVFLW:*/ +/*! 1: clear register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW +#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK 0x0000000FU +#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_SHIFT 0U +/*! Register: mipi_isr: Interrupt set register (0x00000018)*/ +/*! Slice: ISR_GEN_SHORT_PACK:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_GEN_SHORT_PACK +#define MRV_MIPI_ISR_GEN_SHORT_PACK_MASK 0x08000000U +#define MRV_MIPI_ISR_GEN_SHORT_PACK_SHIFT 27U +/*! Slice: ISR_ADD_DATA_FILL_LEVEL:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK 0x04000000U +#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_SHIFT 26U +/*! Slice: ISR_ADD_DATA_OVFLW:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ADD_DATA_OVFLW +#define MRV_MIPI_ISR_ADD_DATA_OVFLW_MASK 0x02000000U +#define MRV_MIPI_ISR_ADD_DATA_OVFLW_SHIFT 25U +/*! Slice: ISR_FRAME_END:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_FRAME_END +#define MRV_MIPI_ISR_FRAME_END_MASK 0x01000000U +#define MRV_MIPI_ISR_FRAME_END_SHIFT 24U +/*! Slice: ISR_ERR_CS:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ERR_CS +#define MRV_MIPI_ISR_ERR_CS_MASK 0x00800000U +#define MRV_MIPI_ISR_ERR_CS_SHIFT 23U +/*! Slice: ISR_ERR_ECC1:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ERR_ECC1 +#define MRV_MIPI_ISR_ERR_ECC1_MASK 0x00400000U +#define MRV_MIPI_ISR_ERR_ECC1_SHIFT 22U +/*! Slice: ISR_ERR_ECC2:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ERR_ECC2 +#define MRV_MIPI_ISR_ERR_ECC2_MASK 0x00200000U +#define MRV_MIPI_ISR_ERR_ECC2_SHIFT 21U +/*! Slice: ISR_ERR_PROTOCOL:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ERR_PROTOCOL +#define MRV_MIPI_ISR_ERR_PROTOCOL_MASK 0x00100000U +#define MRV_MIPI_ISR_ERR_PROTOCOL_SHIFT 20U +/*! Slice: ISR_ERR_CONTROL:*/ +/*! 1: set register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ISR_ERR_CONTROL +#define MRV_MIPI_ISR_ERR_CONTROL_MASK 0x000F0000U +#define MRV_MIPI_ISR_ERR_CONTROL_SHIFT 16U +/*! Slice: ISR_ERR_EOT_SYNC:*/ +/*! 1: set register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ISR_ERR_EOT_SYNC +#define MRV_MIPI_ISR_ERR_EOT_SYNC_MASK 0x0000F000U +#define MRV_MIPI_ISR_ERR_EOT_SYNC_SHIFT 12U +/*! Slice: ISR_ERR_SOT_SYNC:*/ +/*! 1: set register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ISR_ERR_SOT_SYNC +#define MRV_MIPI_ISR_ERR_SOT_SYNC_MASK 0x00000F00U +#define MRV_MIPI_ISR_ERR_SOT_SYNC_SHIFT 8U +/*! Slice: ISR_ERR_SOT:*/ +/*! 1: set register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ISR_ERR_SOT +#define MRV_MIPI_ISR_ERR_SOT_MASK 0x000000F0U +#define MRV_MIPI_ISR_ERR_SOT_SHIFT 4U +/*! Slice: ISR_SYNC_FIFO_OVFLW:*/ +/*! 1: set register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW +#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK 0x0000000FU +#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_SHIFT 0U +/*! Register: mipi_cur_data_id: Current Data Identifier (0x0000001c)*/ +/*! Slice: VIRTUAL_CHANNEL:*/ +/*! virtual channel of currently received packet */ +#define MRV_MIPI_VIRTUAL_CHANNEL +#define MRV_MIPI_VIRTUAL_CHANNEL_MASK 0x000000C0U +#define MRV_MIPI_VIRTUAL_CHANNEL_SHIFT 6U +/*! Slice: DATA_TYPE:*/ +/*! data type of currently received packet */ +#define MRV_MIPI_DATA_TYPE +#define MRV_MIPI_DATA_TYPE_MASK 0x0000003FU +#define MRV_MIPI_DATA_TYPE_SHIFT 0U +/*! Register: mipi_img_data_sel: Image Data Selector (0x00000020)*/ +/*! Slice: VIRTUAL_CHANNEL_SEL:*/ +/*! virtual channel selector for image data output */ +#define MRV_MIPI_VIRTUAL_CHANNEL_SEL +#define MRV_MIPI_VIRTUAL_CHANNEL_SEL_MASK 0x000000C0U +#define MRV_MIPI_VIRTUAL_CHANNEL_SEL_SHIFT 6U +/*! Slice: DATA_TYPE_SEL:*/ +/*! data type selector for image data output:*/ +/* 0x08...0x0F generic short packets */ +/* 0x12 embedded 8-bit data */ +/* 0x18 YUV 420 8-bit */ +/* 0x19 YUV 420 10-bit */ +/* 0x1A Legacy YUV 420 8-bit */ +/* 0x1C YUV 420 8-bit (CSPS)*/ +/* 0x1D YUV 420 10-bit (CSPS)*/ +/* 0x1E YUV 422 8-bit */ +/* 0x1F YUV 422 10-bit */ +/* 0x20 RGB 444 */ +/* 0x21 RGB 555 */ +/* 0x22 RGB 565 */ +/* 0x23 RGB 666 */ +/* 0x24 RGB 888 */ +/* 0x28 RAW 6 */ +/* 0x29 RAW 7 */ +/* 0x2A RAW 8 */ +/* 0x2B RAW 10 */ +/* 0x2C RAW 12 */ +/* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL +#define MRV_MIPI_DATA_TYPE_SEL_MASK 0x0000003FU +#define MRV_MIPI_DATA_TYPE_SEL_SHIFT 0U +/*! Register: mipi_add_data_sel_1: Additional Data Selector 1 (0x00000024)*/ +/*! Slice: ADD_DATA_VC_1:*/ +/*! virtual channel selector for additional data output */ +#define MRV_MIPI_ADD_DATA_VC_1 +#define MRV_MIPI_ADD_DATA_VC_1_MASK 0x000000C0U +#define MRV_MIPI_ADD_DATA_VC_1_SHIFT 6U +/*! Slice: ADD_DATA_TYPE_1:*/ +/*! data type selector for additional data output */ +#define MRV_MIPI_ADD_DATA_TYPE_1 +#define MRV_MIPI_ADD_DATA_TYPE_1_MASK 0x0000003FU +#define MRV_MIPI_ADD_DATA_TYPE_1_SHIFT 0U +/*! Register: mipi_add_data_sel_2: Additional Data Selector 2 (0x00000028)*/ +/*! Slice: ADD_DATA_VC_2:*/ +/*! virtual channel selector for additional data output */ +#define MRV_MIPI_ADD_DATA_VC_2 +#define MRV_MIPI_ADD_DATA_VC_2_MASK 0x000000C0U +#define MRV_MIPI_ADD_DATA_VC_2_SHIFT 6U +/*! Slice: ADD_DATA_TYPE_2:*/ +/*! data type selector for additional data output */ +#define MRV_MIPI_ADD_DATA_TYPE_2 +#define MRV_MIPI_ADD_DATA_TYPE_2_MASK 0x0000003FU +#define MRV_MIPI_ADD_DATA_TYPE_2_SHIFT 0U +/*! Register: mipi_add_data_sel_3: Additional Data Selector 3 (0x0000002c)*/ +/*! Slice: ADD_DATA_VC_3:*/ +/*! virtual channel selector for additional data output */ +#define MRV_MIPI_ADD_DATA_VC_3 +#define MRV_MIPI_ADD_DATA_VC_3_MASK 0x000000C0U +#define MRV_MIPI_ADD_DATA_VC_3_SHIFT 6U +/*! Slice: ADD_DATA_TYPE_3:*/ +/*! data type selector for additional data output */ +#define MRV_MIPI_ADD_DATA_TYPE_3 +#define MRV_MIPI_ADD_DATA_TYPE_3_MASK 0x0000003FU +#define MRV_MIPI_ADD_DATA_TYPE_3_SHIFT 0U +/*! Register: mipi_add_data_sel_4: Additional Data Selector 4 (0x00000030)*/ +/*! Slice: ADD_DATA_VC_4:*/ +/*! virtual channel selector for additional data output */ +#define MRV_MIPI_ADD_DATA_VC_4 +#define MRV_MIPI_ADD_DATA_VC_4_MASK 0x000000C0U +#define MRV_MIPI_ADD_DATA_VC_4_SHIFT 6U +/*! Slice: ADD_DATA_TYPE_4:*/ +/*! data type selector for additional data output */ +#define MRV_MIPI_ADD_DATA_TYPE_4 +#define MRV_MIPI_ADD_DATA_TYPE_4_MASK 0x0000003FU +#define MRV_MIPI_ADD_DATA_TYPE_4_SHIFT 0U +/*! Register: mipi_add_data_fifo: Additional Data Fifo (0x00000034)*/ +/*! Slice: ADD_DATA_FIFO:*/ +/*! lowest 4 bytes in additional data fifo;*/ +/* reading increments fifo read pointer.*/ +/* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/ +#define MRV_MIPI_ADD_DATA_FIFO +#define MRV_MIPI_ADD_DATA_FIFO_MASK 0xFFFFFFFFU +#define MRV_MIPI_ADD_DATA_FIFO_SHIFT 0U +/*! Register: mipi_add_data_fill_level: Additional Data FIFO Fill Level (0x00000038)*/ +/*! Slice: ADD_DATA_FILL_LEVEL:*/ +/*! FIFO level in dwords for triggering the FILL_LEVEL interrupt,*/ +/* must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/ +#define MRV_MIPI_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_ADD_DATA_FILL_LEVEL_MASK 0x00001FFFU +#define MRV_MIPI_ADD_DATA_FILL_LEVEL_SHIFT 0U +/*! Register: mipi_compressed_mode: controls processing of compressed raw data types (0x0000003c)*/ +/*! Slice: predictor_sel:*/ +/*! predictor to be used:*/ +/* 0: predictor 1 */ +/* 1: predictor 2 */ +#define MRV_MIPI_PREDICTOR_SEL +#define MRV_MIPI_PREDICTOR_SEL_MASK 0x00000100U +#define MRV_MIPI_PREDICTOR_SEL_SHIFT 8U +/*! Slice: comp_scheme:*/ +/*! data compression scheme:*/ +/* 0: 12–8–12 */ +/* 1: 12–7–12 */ +/* 2: 12–6–12 */ +/* 3: 10–8–10 */ +/* 4: 10–7–10 */ +/* 5: 10–6–10 */ +/* 6..7: reserved */ +#define MRV_MIPI_COMP_SCHEME +#define MRV_MIPI_COMP_SCHEME_MASK 0x00000070U +#define MRV_MIPI_COMP_SCHEME_SHIFT 4U +/*! Slice: compress_en:*/ +/*! 1: enable compressed mode processing */ +/* 0: disable compressed mode */ +#define MRV_MIPI_COMPRESS_EN +#define MRV_MIPI_COMPRESS_EN_MASK 0x00000001U +#define MRV_MIPI_COMPRESS_EN_SHIFT 0U +/*! Register: mipi_frame: frame number from frame start and frame end short packets (0x00000040)*/ +/*! Slice: frame_number_fe:*/ +/*! 16 bit frame number from Frame End (FE) short packet */ +#define MRV_MIPI_FRAME_NUMBER_FE +#define MRV_MIPI_FRAME_NUMBER_FE_MASK 0xFFFF0000U +#define MRV_MIPI_FRAME_NUMBER_FE_SHIFT 16U +/*! Slice: frame_number_fs:*/ +/*! 16 bit frame number from Frame Start (FS) short packet */ +#define MRV_MIPI_FRAME_NUMBER_FS +#define MRV_MIPI_FRAME_NUMBER_FS_MASK 0x0000FFFFU +#define MRV_MIPI_FRAME_NUMBER_FS_SHIFT 0U +/*! Register: mipi_gen_short_dt: data type flags for received generic short packets (0x00000044)*/ +/*! Slice: GEN_SHORT_DT_0xF:*/ +/*! 1: generic short packet of data type 0xF received */ +/* 0: data type 0xF not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XF +#define MRV_MIPI_GEN_SHORT_DT_0XF_MASK 0x00000080U +#define MRV_MIPI_GEN_SHORT_DT_0XF_SHIFT 7U +/*! Slice: GEN_SHORT_DT_0xE:*/ +/*! 1: generic short packet of data type 0xE received */ +/* 0: data type 0xE not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XE +#define MRV_MIPI_GEN_SHORT_DT_0XE_MASK 0x00000040U +#define MRV_MIPI_GEN_SHORT_DT_0XE_SHIFT 6U +/*! Slice: GEN_SHORT_DT_0xD:*/ +/*! 1: generic short packet of data type 0xD received */ +/* 0: data type 0xD not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XD +#define MRV_MIPI_GEN_SHORT_DT_0XD_MASK 0x00000020U +#define MRV_MIPI_GEN_SHORT_DT_0XD_SHIFT 5U +/*! Slice: GEN_SHORT_DT_0xC:*/ +/*! 1: generic short packet of data type 0xC received */ +/* 0: data type 0xC not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XC +#define MRV_MIPI_GEN_SHORT_DT_0XC_MASK 0x00000010U +#define MRV_MIPI_GEN_SHORT_DT_0XC_SHIFT 4U +/*! Slice: GEN_SHORT_DT_0xB:*/ +/*! 1: generic short packet of data type 0xB received */ +/* 0: data type 0xB not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XB +#define MRV_MIPI_GEN_SHORT_DT_0XB_MASK 0x00000008U +#define MRV_MIPI_GEN_SHORT_DT_0XB_SHIFT 3U +/*! Slice: GEN_SHORT_DT_0xA:*/ +/*! 1: generic short packet of data type 0xA received */ +/* 0: data type 0xA not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XA +#define MRV_MIPI_GEN_SHORT_DT_0XA_MASK 0x00000004U +#define MRV_MIPI_GEN_SHORT_DT_0XA_SHIFT 2U +/*! Slice: GEN_SHORT_DT_0x9:*/ +/*! 1: generic short packet of data type 0x9 received */ +/* 0: data type 0x9 not received */ +#define MRV_MIPI_GEN_SHORT_DT_0X9 +#define MRV_MIPI_GEN_SHORT_DT_0X9_MASK 0x00000002U +#define MRV_MIPI_GEN_SHORT_DT_0X9_SHIFT 1U +/*! Slice: GEN_SHORT_DT_0x8:*/ +/*! 1: generic short packet of data type 0x8 received */ +/* 0: data type 0x8 not received */ +#define MRV_MIPI_GEN_SHORT_DT_0X8 +#define MRV_MIPI_GEN_SHORT_DT_0X8_MASK 0x00000001U +#define MRV_MIPI_GEN_SHORT_DT_0X8_SHIFT 0U +/*! Register: mipi_gen_short_8_9: data field for generic short packets of data type 0x8 and 0x9 (0x00000048)*/ +/*! Slice: data_field_9:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0x9 */ +#define MRV_MIPI_DATA_FIELD_9 +#define MRV_MIPI_DATA_FIELD_9_MASK 0xFFFF0000U +#define MRV_MIPI_DATA_FIELD_9_SHIFT 16U +/*! Slice: data_field_8:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0x8 */ +#define MRV_MIPI_DATA_FIELD_8 +#define MRV_MIPI_DATA_FIELD_8_MASK 0x0000FFFFU +#define MRV_MIPI_DATA_FIELD_8_SHIFT 0U +/*! Register: mipi_gen_short_a_b: data field for generic short packets of data type 0xA and 0xB (0x0000004c)*/ +/*! Slice: data_field_B:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xB */ +#define MRV_MIPI_DATA_FIELD_B +#define MRV_MIPI_DATA_FIELD_B_MASK 0xFFFF0000U +#define MRV_MIPI_DATA_FIELD_B_SHIFT 16U +/*! Slice: data_field_A:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xA */ +#define MRV_MIPI_DATA_FIELD_A +#define MRV_MIPI_DATA_FIELD_A_MASK 0x0000FFFFU +#define MRV_MIPI_DATA_FIELD_A_SHIFT 0U +/*! Register: mipi_gen_short_c_d: data field for generic short packets of data type 0xC and 0xD (0x00000050)*/ +/*! Slice: data_field_D:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xD */ +#define MRV_MIPI_DATA_FIELD_D +#define MRV_MIPI_DATA_FIELD_D_MASK 0xFFFF0000U +#define MRV_MIPI_DATA_FIELD_D_SHIFT 16U +/*! Slice: data_field_C:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xC */ +#define MRV_MIPI_DATA_FIELD_C +#define MRV_MIPI_DATA_FIELD_C_MASK 0x0000FFFFU +#define MRV_MIPI_DATA_FIELD_C_SHIFT 0U +/*! Register: mipi_gen_short_e_f: data field for generic short packets of data type 0xE and 0xF (0x00000054)*/ +/*! Slice: data_field_F:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xF */ +#define MRV_MIPI_DATA_FIELD_F +#define MRV_MIPI_DATA_FIELD_F_MASK 0xFFFF0000U +#define MRV_MIPI_DATA_FIELD_F_SHIFT 16U +/*! Slice: data_field_E:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xE */ +#define MRV_MIPI_DATA_FIELD_E +#define MRV_MIPI_DATA_FIELD_E_MASK 0x0000FFFFU +#define MRV_MIPI_DATA_FIELD_E_SHIFT 0U +/*! Register: isp_afm_ctrl: This is the control register for AF measurement unit (0x00000000)*/ +/*! Slice: afm_en:*/ +/*! AF measurement enable */ +/* 0: AF measurement is disabled */ +/* 1: AF measurement is enabled */ +/* Writing a 1 to this register starts a new measurement and resets the afm_fin (measurement finished) interrupt to 0.*/ +/* As long as the afm_en is 1, the AFM unit calculates new sharpness values for each frame.*/ +#define MRV_AFM_AFM_EN +#define MRV_AFM_AFM_EN_MASK 0x00000001U +#define MRV_AFM_AFM_EN_SHIFT 0U +/*! Register: isp_afm_lt_a: Top Left corner of measure window A (0x00000004)*/ +/*! Slice: a_h_l:*/ +/*! first pixel of window A (horizontal left row), value must be greater or equal 5 */ +#define MRV_AFM_A_H_L +#define MRV_AFM_A_H_L_MASK 0x1FFF0000U +#define MRV_AFM_A_H_L_SHIFT 16U +/*! Slice: a_v_t:*/ +/*! first line of window A (vertical top line), value must be greater or equal 2 */ +#define MRV_AFM_A_V_T +#define MRV_AFM_A_V_T_MASK 0x00001FFFU +#define MRV_AFM_A_V_T_SHIFT 0U +/*! Register: isp_afm_rb_a: Bottom right corner of measure window A (0x00000008)*/ +/*! Slice: a_h_r:*/ +/*! last pixel of window A (horizontal right row)*/ +#define MRV_AFM_A_H_R +#define MRV_AFM_A_H_R_MASK 0x1FFF0000U +#define MRV_AFM_A_H_R_SHIFT 16U +/*! Slice: a_v_b:*/ +/*! last line of window A (vertical bottom line), value must be lower than (number of lines – 2)*/ +#define MRV_AFM_A_V_B +#define MRV_AFM_A_V_B_MASK 0x00001FFFU +#define MRV_AFM_A_V_B_SHIFT 0U +/*! Register: isp_afm_lt_b: Top left corner of measure window B (0x0000000c)*/ +/*! Slice: b_h_l:*/ +/*! first pixel of window B (horizontal left row), value must be greater or equal 5 */ +#define MRV_AFM_B_H_L +#define MRV_AFM_B_H_L_MASK 0x1FFF0000U +#define MRV_AFM_B_H_L_SHIFT 16U +/*! Slice: b_v_t:*/ +/*! first line of window B (vertical top line), value must be greater or equal 2 */ +#define MRV_AFM_B_V_T +#define MRV_AFM_B_V_T_MASK 0x00001FFFU +#define MRV_AFM_B_V_T_SHIFT 0U +/*! Register: isp_afm_rb_b: Bottom right corner of measure window B (0x00000010)*/ +/*! Slice: b_h_r:*/ +/*! last pixel of window B (horizontal right row)*/ +#define MRV_AFM_B_H_R +#define MRV_AFM_B_H_R_MASK 0x1FFF0000U +#define MRV_AFM_B_H_R_SHIFT 16U +/*! Slice: b_v_b:*/ +/*! last line of window B (vertical bottom line), value must be lower than (number of lines – 2)*/ +#define MRV_AFM_B_V_B +#define MRV_AFM_B_V_B_MASK 0x00001FFFU +#define MRV_AFM_B_V_B_SHIFT 0U +/*! Register: isp_afm_lt_c: Top left corner of measure window C (0x00000014)*/ +/*! Slice: c_h_l:*/ +/*! first pixel of window C (horizontal left row), value must be greater or equal 5 */ +#define MRV_AFM_C_H_L +#define MRV_AFM_C_H_L_MASK 0x1FFF0000U +#define MRV_AFM_C_H_L_SHIFT 16U +/*! Slice: c_v_t:*/ +/*! first line of window C (vertical top line), value must be greater or equal 2 */ +#define MRV_AFM_C_V_T +#define MRV_AFM_C_V_T_MASK 0x00001FFFU +#define MRV_AFM_C_V_T_SHIFT 0U +/*! Register: isp_afm_rb_c: Bottom right corner of measure window C (0x00000018)*/ +/*! Slice: c_h_r:*/ +/*! last pixel of window C (horizontal right row)*/ +#define MRV_AFM_C_H_R +#define MRV_AFM_C_H_R_MASK 0x1FFF0000U +#define MRV_AFM_C_H_R_SHIFT 16U +/*! Slice: c_v_b:*/ +/*! last line of window C (vertical bottom line), value must be lower than (number of lines – 2)*/ +#define MRV_AFM_C_V_B +#define MRV_AFM_C_V_B_MASK 0x00001FFFU +#define MRV_AFM_C_V_B_SHIFT 0U +/*! Register: isp_afm_thres: Threshold register (0x0000001c)*/ +/*! Slice: afm_thres:*/ +/*! AF measurement threshold */ +/* This register defines a threshold which can be used for minimizing the influence of noise in the measurement result.*/ +#define MRV_AFM_AFM_THRES +#define MRV_AFM_AFM_THRES_MASK 0x0000FFFFU +#define MRV_AFM_AFM_THRES_SHIFT 0U +/*! Register: isp_afm_var_shift: Variable shift register (0x00000020)*/ +/*! Slice: lum_var_shift:*/ +/*! variable shift for luminance summation */ +/* The lum_var_shift defines the number of bits for the shift operation of the value of the current pixel before summation. The shift operation is used to avoid a luminance sum overflow.*/ +#define MRV_AFM_LUM_VAR_SHIFT +#define MRV_AFM_LUM_VAR_SHIFT_MASK 0x00070000U +#define MRV_AFM_LUM_VAR_SHIFT_SHIFT 16U +/*! Slice: afm_var_shift:*/ +/*! variable shift for AF measurement */ +/* The afm_var_shift defines the number of bits for the shift operation at the end of the calculation chain. The shift operation is used to avoid an AF measurement sum overflow.*/ +#define MRV_AFM_AFM_VAR_SHIFT +#define MRV_AFM_AFM_VAR_SHIFT_MASK 0x00000007U +#define MRV_AFM_AFM_VAR_SHIFT_SHIFT 0U +/*! Register: isp_afm_sum_a: Sharpness Value Status Register of Window A (0x00000024)*/ +/*! Slice: afm_sum_a:*/ +/*! sharpness value of window A */ +#define MRV_AFM_AFM_SUM_A +#define MRV_AFM_AFM_SUM_A_MASK 0xFFFFFFFFU +#define MRV_AFM_AFM_SUM_A_SHIFT 0U +/*! Register: isp_afm_sum_b: Sharpness Value Status Register of Window B (0x00000028)*/ +/*! Slice: afm_sum_b:*/ +/*! sharpness value of window B */ +#define MRV_AFM_AFM_SUM_B +#define MRV_AFM_AFM_SUM_B_MASK 0xFFFFFFFFU +#define MRV_AFM_AFM_SUM_B_SHIFT 0U +/*! Register: isp_afm_sum_c: Sharpness Value Status Register of Window C (0x0000002c)*/ +/*! Slice: afm_sum_c:*/ +/*! sharpness value of window C */ +#define MRV_AFM_AFM_SUM_C +#define MRV_AFM_AFM_SUM_C_MASK 0xFFFFFFFFU +#define MRV_AFM_AFM_SUM_C_SHIFT 0U +/*! Register: isp_afm_lum_a: Luminance Value Status Register of Window A (0x00000030)*/ +/*! Slice: afm_lum_a:*/ +/*! luminance value of window A */ +#define MRV_AFM_AFM_LUM_A +#define MRV_AFM_AFM_LUM_A_MASK 0x00FFFFFFU +#define MRV_AFM_AFM_LUM_A_SHIFT 0U +/*! Register: isp_afm_lum_b: Luminance Value Status Register of Window B (0x00000034)*/ +/*! Slice: afm_lum_b:*/ +/*! luminance value of window B */ +#define MRV_AFM_AFM_LUM_B +#define MRV_AFM_AFM_LUM_B_MASK 0x00FFFFFFU +#define MRV_AFM_AFM_LUM_B_SHIFT 0U +/*! Register: isp_afm_lum_c: Luminance Value Status Register of Window C (0x00000038)*/ +/*! Slice: afm_lum_c:*/ +/*! luminance value of window C */ +#define MRV_AFM_AFM_LUM_C +#define MRV_AFM_AFM_LUM_C_MASK 0x00FFFFFFU +#define MRV_AFM_AFM_LUM_C_SHIFT 0U +/*! Register: isp_lsc_ctrl: Lens shade control (0x00000000)*/ +/*! Slice: lsc_en:*/ +/*! 0: activation request for lens shading correction */ +/* 1: deactivation reqeust for lens shading correction */ +/* Activation/Deactivation is object of a shadowing mechnism. The current status is visible at ISP_LSC_STATUS::lsc_enable_status */ +#define MRV_LSC_LSC_EN +#define MRV_LSC_LSC_EN_MASK 0x00000001U +#define MRV_LSC_LSC_EN_SHIFT 0U +/*! Register: isp_lsc_r_table_addr: Table RAM Address for red component (0x00000004)*/ +/*! Slice: r_ram_addr:*/ +/*! table address in RAM for samples of the R color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +/* Valid addresses are in the range 0 to 152.*/ +#define MRV_LSC_R_RAM_ADDR +#define MRV_LSC_R_RAM_ADDR_MASK 0x000001FFU +#define MRV_LSC_R_RAM_ADDR_SHIFT 0U +/*! Register: isp_lsc_gr_table_addr: Table RAM Address for green (red) component (0x00000008)*/ +/*! Slice: gr_ram_addr:*/ +/*! table address in RAM for samples of the G_R color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +#define MRV_LSC_GR_RAM_ADDR +#define MRV_LSC_GR_RAM_ADDR_MASK 0x000001FFU +#define MRV_LSC_GR_RAM_ADDR_SHIFT 0U +/*! Register: isp_lsc_b_table_addr: Table RAM Address for blue component (0x0000000c)*/ +/*! Slice: b_ram_addr:*/ +/*! table address in RAM for samples of the B color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +#define MRV_LSC_B_RAM_ADDR +#define MRV_LSC_B_RAM_ADDR_MASK 0x000001FFU +#define MRV_LSC_B_RAM_ADDR_SHIFT 0U +/*! Register: isp_lsc_gb_table_addr: Table RAM Address for green (blue) component (0x00000010)*/ +/*! Slice: gb_ram_addr:*/ +/*! table address in RAM for samples of the G_B color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +#define MRV_LSC_GB_RAM_ADDR +#define MRV_LSC_GB_RAM_ADDR_MASK 0x000001FFU +#define MRV_LSC_GB_RAM_ADDR_SHIFT 0U +/*! Register: isp_lsc_r_table_data: Sample table red (0x00000014)*/ +/*! Slice: r_sample_1:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_R_SAMPLE_1 +#define MRV_LSC_R_SAMPLE_1_MASK 0x00FFF000U +#define MRV_LSC_R_SAMPLE_1_SHIFT 12U +/*! Slice: r_sample_0:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_R_SAMPLE_0 +#define MRV_LSC_R_SAMPLE_0_MASK 0x00000FFFU +#define MRV_LSC_R_SAMPLE_0_SHIFT 0U +/*! Register: isp_lsc_gr_table_data: Sample table green (red) (0x00000018)*/ +/*! Slice: gr_sample_1:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_GR_SAMPLE_1 +#define MRV_LSC_GR_SAMPLE_1_MASK 0x00FFF000U +#define MRV_LSC_GR_SAMPLE_1_SHIFT 12U +/*! Slice: gr_sample_0:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_GR_SAMPLE_0 +#define MRV_LSC_GR_SAMPLE_0_MASK 0x00000FFFU +#define MRV_LSC_GR_SAMPLE_0_SHIFT 0U +/*! Register: isp_lsc_b_table_data: Sample table blue (0x0000001c)*/ +/*! Slice: b_sample_1:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_B_SAMPLE_1 +#define MRV_LSC_B_SAMPLE_1_MASK 0x00FFF000U +#define MRV_LSC_B_SAMPLE_1_SHIFT 12U +/*! Slice: b_sample_0:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_B_SAMPLE_0 +#define MRV_LSC_B_SAMPLE_0_MASK 0x00000FFFU +#define MRV_LSC_B_SAMPLE_0_SHIFT 0U +/*! Register: isp_lsc_gb_table_data: Sample table green (blue) (0x00000020)*/ +/*! Slice: gb_sample_1:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_GB_SAMPLE_1 +#define MRV_LSC_GB_SAMPLE_1_MASK 0x00FFF000U +#define MRV_LSC_GB_SAMPLE_1_SHIFT 12U +/*! Slice: gb_sample_0:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_GB_SAMPLE_0 +#define MRV_LSC_GB_SAMPLE_0_MASK 0x00000FFFU +#define MRV_LSC_GB_SAMPLE_0_SHIFT 0U +/*! Register: isp_lsc_xgrad_01: Gradient table x (0x00000024)*/ +/*! Slice: xgrad_1:*/ +/*! factor for x-gradient calculation of sector 1 */ +#define MRV_LSC_XGRAD_1 +#define MRV_LSC_XGRAD_1_MASK 0x0FFF0000U +#define MRV_LSC_XGRAD_1_SHIFT 16U +/*! Slice: xgrad_0:*/ +/*! factor for x-gradient calculation of sector 0 */ +#define MRV_LSC_XGRAD_0 +#define MRV_LSC_XGRAD_0_MASK 0x00000FFFU +#define MRV_LSC_XGRAD_0_SHIFT 0U +/*! Register: isp_lsc_xgrad_23: Gradient table x (0x00000028)*/ +/*! Slice: xgrad_3:*/ +/*! factor for x-gradient calculation of sector 3 */ +#define MRV_LSC_XGRAD_3 +#define MRV_LSC_XGRAD_3_MASK 0x0FFF0000U +#define MRV_LSC_XGRAD_3_SHIFT 16U +/*! Slice: xgrad_2:*/ +/*! factor for x-gradient calculation of sector 2 */ +#define MRV_LSC_XGRAD_2 +#define MRV_LSC_XGRAD_2_MASK 0x00000FFFU +#define MRV_LSC_XGRAD_2_SHIFT 0U +/*! Register: isp_lsc_xgrad_45: Gradient table x (0x0000002c)*/ +/*! Slice: xgrad_5:*/ +/*! factor for x-gradient calculation of sector 5 */ +#define MRV_LSC_XGRAD_5 +#define MRV_LSC_XGRAD_5_MASK 0x0FFF0000U +#define MRV_LSC_XGRAD_5_SHIFT 16U +/*! Slice: xgrad_4:*/ +/*! factor for x-gradient calculation of sector 4 */ +#define MRV_LSC_XGRAD_4 +#define MRV_LSC_XGRAD_4_MASK 0x00000FFFU +#define MRV_LSC_XGRAD_4_SHIFT 0U +/*! Register: isp_lsc_xgrad_67: Gradient table x (0x00000030)*/ +/*! Slice: xgrad_7:*/ +/*! factor for x-gradient calculation of sector 7 */ +#define MRV_LSC_XGRAD_7 +#define MRV_LSC_XGRAD_7_MASK 0x0FFF0000U +#define MRV_LSC_XGRAD_7_SHIFT 16U +/*! Slice: xgrad_6:*/ +/*! factor for x-gradient calculation of sector 6 */ +#define MRV_LSC_XGRAD_6 +#define MRV_LSC_XGRAD_6_MASK 0x00000FFFU +#define MRV_LSC_XGRAD_6_SHIFT 0U +/*! Register: isp_lsc_ygrad_01: Gradient table y (0x00000034)*/ +/*! Slice: ygrad_1:*/ +/*! factor for y-gradient calculation of sector 1 */ +#define MRV_LSC_YGRAD_1 +#define MRV_LSC_YGRAD_1_MASK 0x0FFF0000U +#define MRV_LSC_YGRAD_1_SHIFT 16U +/*! Slice: ygrad_0:*/ +/*! factor for y-gradient calculation of sector 0 */ +#define MRV_LSC_YGRAD_0 +#define MRV_LSC_YGRAD_0_MASK 0x00000FFFU +#define MRV_LSC_YGRAD_0_SHIFT 0U +/*! Register: isp_lsc_ygrad_23: Gradient table y (0x00000038)*/ +/*! Slice: ygrad_3:*/ +/*! factor for y-gradient calculation of sector 3 */ +#define MRV_LSC_YGRAD_3 +#define MRV_LSC_YGRAD_3_MASK 0x0FFF0000U +#define MRV_LSC_YGRAD_3_SHIFT 16U +/*! Slice: ygrad_2:*/ +/*! factor for y-gradient calculation of sector 2 */ +#define MRV_LSC_YGRAD_2 +#define MRV_LSC_YGRAD_2_MASK 0x00000FFFU +#define MRV_LSC_YGRAD_2_SHIFT 0U +/*! Register: isp_lsc_ygrad_45: Gradient table y (0x0000003c)*/ +/*! Slice: ygrad_5:*/ +/*! factor for y-gradient calculation of sector 5 */ +#define MRV_LSC_YGRAD_5 +#define MRV_LSC_YGRAD_5_MASK 0x0FFF0000U +#define MRV_LSC_YGRAD_5_SHIFT 16U +/*! Slice: ygrad_4:*/ +/*! factor for y-gradient calculation of sector 4 */ +#define MRV_LSC_YGRAD_4 +#define MRV_LSC_YGRAD_4_MASK 0x00000FFFU +#define MRV_LSC_YGRAD_4_SHIFT 0U +/*! Register: isp_lsc_ygrad_67: Gradient table y (0x00000040)*/ +/*! Slice: ygrad_7:*/ +/*! factor for y-gradient calculation of sector 7 */ +#define MRV_LSC_YGRAD_7 +#define MRV_LSC_YGRAD_7_MASK 0x0FFF0000U +#define MRV_LSC_YGRAD_7_SHIFT 16U +/*! Slice: ygrad_6:*/ +/*! factor for y-gradient calculation of sector 6 */ +#define MRV_LSC_YGRAD_6 +#define MRV_LSC_YGRAD_6_MASK 0x00000FFFU +#define MRV_LSC_YGRAD_6_SHIFT 0U +/*! Register: isp_lsc_xsize_01: Size table (0x00000044)*/ +/*! Slice: x_sect_size_1:*/ +/*! sector size 1 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_1 +#define MRV_LSC_X_SECT_SIZE_1_MASK 0x03FF0000U +#define MRV_LSC_X_SECT_SIZE_1_SHIFT 16U +/*! Slice: x_sect_size_0:*/ +/*! sector size 0 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_0 +#define MRV_LSC_X_SECT_SIZE_0_MASK 0x000003FFU +#define MRV_LSC_X_SECT_SIZE_0_SHIFT 0U +/*! Register: isp_lsc_xsize_23: Size table (0x00000048)*/ +/*! Slice: x_sect_size_3:*/ +/*! sector size 3 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_3 +#define MRV_LSC_X_SECT_SIZE_3_MASK 0x03FF0000U +#define MRV_LSC_X_SECT_SIZE_3_SHIFT 16U +/*! Slice: x_sect_size_2:*/ +/*! sector size 2 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_2 +#define MRV_LSC_X_SECT_SIZE_2_MASK 0x000003FFU +#define MRV_LSC_X_SECT_SIZE_2_SHIFT 0U +/*! Register: isp_lsc_xsize_45: Size table (0x0000004c)*/ +/*! Slice: x_sect_size_5:*/ +/*! sector size 5 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_5 +#define MRV_LSC_X_SECT_SIZE_5_MASK 0x03FF0000U +#define MRV_LSC_X_SECT_SIZE_5_SHIFT 16U +/*! Slice: x_sect_size_4:*/ +/*! sector size 4in x-direction */ +#define MRV_LSC_X_SECT_SIZE_4 +#define MRV_LSC_X_SECT_SIZE_4_MASK 0x000003FFU +#define MRV_LSC_X_SECT_SIZE_4_SHIFT 0U +/*! Register: isp_lsc_xsize_67: Size table (0x00000050)*/ +/*! Slice: x_sect_size_7:*/ +/*! sector size 7 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_7 +#define MRV_LSC_X_SECT_SIZE_7_MASK 0x03FF0000U +#define MRV_LSC_X_SECT_SIZE_7_SHIFT 16U +/*! Slice: x_sect_size_6:*/ +/*! sector size 6 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_6 +#define MRV_LSC_X_SECT_SIZE_6_MASK 0x000003FFU +#define MRV_LSC_X_SECT_SIZE_6_SHIFT 0U +/*! Register: isp_lsc_ysize_01: Size table (0x00000054)*/ +/*! Slice: y_sect_size_1:*/ +/*! sector size 1 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_1 +#define MRV_LSC_Y_SECT_SIZE_1_MASK 0x03FF0000U +#define MRV_LSC_Y_SECT_SIZE_1_SHIFT 16U +/*! Slice: y_sect_size_0:*/ +/*! sector size 0 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_0 +#define MRV_LSC_Y_SECT_SIZE_0_MASK 0x000003FFU +#define MRV_LSC_Y_SECT_SIZE_0_SHIFT 0U +/*! Register: isp_lsc_ysize_23: Size table (0x00000058)*/ +/*! Slice: y_sect_size_3:*/ +/*! sector size 3 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_3 +#define MRV_LSC_Y_SECT_SIZE_3_MASK 0x03FF0000U +#define MRV_LSC_Y_SECT_SIZE_3_SHIFT 16U +/*! Slice: y_sect_size_2:*/ +/*! sector size 2 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_2 +#define MRV_LSC_Y_SECT_SIZE_2_MASK 0x000003FFU +#define MRV_LSC_Y_SECT_SIZE_2_SHIFT 0U +/*! Register: isp_lsc_ysize_45: Size table (0x0000005c)*/ +/*! Slice: y_sect_size_5:*/ +/*! sector size 5 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_5 +#define MRV_LSC_Y_SECT_SIZE_5_MASK 0x03FF0000U +#define MRV_LSC_Y_SECT_SIZE_5_SHIFT 16U +/*! Slice: y_sect_size_4:*/ +/*! sector size 4 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_4 +#define MRV_LSC_Y_SECT_SIZE_4_MASK 0x000003FFU +#define MRV_LSC_Y_SECT_SIZE_4_SHIFT 0U +/*! Register: isp_lsc_ysize_67: Size table (0x00000060)*/ +/*! Slice: y_sect_size_7:*/ +/*! sector size 7 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_7 +#define MRV_LSC_Y_SECT_SIZE_7_MASK 0x03FF0000U +#define MRV_LSC_Y_SECT_SIZE_7_SHIFT 16U +/*! Slice: y_sect_size_6:*/ +/*! sector size 6 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_6 +#define MRV_LSC_Y_SECT_SIZE_6_MASK 0x000003FFU +#define MRV_LSC_Y_SECT_SIZE_6_SHIFT 0U +/*! Register: isp_lsc_table_sel: Lens shade table set selection (0x00000064)*/ +/*! Slice: table_sel:*/ +/*! 0: next active tables set is table set 0.*/ +/* 1: next active tables set is table set 1.*/ +/* Table selection is object of a shadowing mechnism. The current status is visible at ISP_LSC_STATUS::active_table.*/ +#define MRV_LSC_TABLE_SEL +#define MRV_LSC_TABLE_SEL_MASK 0x00000001U +#define MRV_LSC_TABLE_SEL_SHIFT 0U +/*! Register: isp_lsc_status: Lens shade status (0x00000068)*/ +/*! Slice: active_table:*/ +/*! 0: currently active tables set is table set 0 */ +/* 1: currently active tables set is table set 1 */ +#define MRV_LSC_ACTIVE_TABLE +#define MRV_LSC_ACTIVE_TABLE_MASK 0x00000002U +#define MRV_LSC_ACTIVE_TABLE_SHIFT 1U +/*! Slice: lsc_en_status:*/ +/*! 0: lens shading correction is currently off */ +/* 1: lens shading correction is currently on */ +#define MRV_LSC_LSC_EN_STATUS +#define MRV_LSC_LSC_EN_STATUS_MASK 0x00000001U +#define MRV_LSC_LSC_EN_STATUS_SHIFT 0U +/*! Register: isp_is_ctrl: Image Stabilization Control Register (0x00000000)*/ +/*! Slice: is_en:*/ +/*! 1: image stabilization switched on */ +/* 0: image stabilization switched off */ +#define MRV_IS_IS_EN +#define MRV_IS_IS_EN_MASK 0x00000001U +#define MRV_IS_IS_EN_SHIFT 0U +/*! Register: isp_is_recenter: Recenter register (0x00000004)*/ +/*! Slice: is_recenter:*/ +/*! 000: recenter feature switched off */ +/* 1..7: recentering by (cur_h/v_offs-H/V_OFFS)/2^RECENTER */ +#define MRV_IS_IS_RECENTER +#define MRV_IS_IS_RECENTER_MASK 0x00000007U +#define MRV_IS_IS_RECENTER_SHIFT 0U +/*! Register: isp_is_h_offs: Horizontal offset of output window (0x00000008)*/ +/*! Slice: is_h_offs:*/ +/*! horizontal picture offset in pixel */ +#define MRV_IS_IS_H_OFFS +#define MRV_IS_IS_H_OFFS_MASK 0x00003FFFU +#define MRV_IS_IS_H_OFFS_SHIFT 0U +/*! Register: isp_is_v_offs: Vertical offset of output window (0x0000000c)*/ +/*! Slice: is_v_offs:*/ +/*! vertical picture offset in lines */ +#define MRV_IS_IS_V_OFFS +#define MRV_IS_IS_V_OFFS_MASK 0x00003FFFU +#define MRV_IS_IS_V_OFFS_SHIFT 0U +/*! Register: isp_is_h_size: Output horizontal picture size (0x00000010)*/ +/*! Slice: is_h_size:*/ +/*! horizontal picture size in pixel */ +/* if ISP_MODE is set to */ +/* 001-(ITU-R BT.656 YUV),*/ +/* 010-( ITU-R BT.601 YUV),*/ +/* 011-( ITU-R BT.601 Bayer RGB),*/ +/* 101-( ITU-R BT.656 Bayer RGB)*/ +/* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr) are needed for the following modules. If an odd size is programmed the value will be truncated to even size.*/ +#define MRV_IS_IS_H_SIZE +#define MRV_IS_IS_H_SIZE_MASK 0x00003FFFU +#define MRV_IS_IS_H_SIZE_SHIFT 0U +/*! Register: isp_is_v_size: Output vertical picture size (0x00000014)*/ +/*! Slice: is_v_size:*/ +/*! vertical picture size in lines */ +#define MRV_IS_IS_V_SIZE +#define MRV_IS_IS_V_SIZE_MASK 0x00003FFFU +#define MRV_IS_IS_V_SIZE_SHIFT 0U +/*! Register: isp_is_max_dx: Maximum Horizontal Displacement (0x00000018)*/ +/*! Slice: is_max_dx:*/ +/*! maximum allowed accumulated horizontal displacement in pixels */ +#define MRV_IS_IS_MAX_DX +#define MRV_IS_IS_MAX_DX_MASK 0x00001FFFU +#define MRV_IS_IS_MAX_DX_SHIFT 0U +/*! Register: isp_is_max_dy: Maximum Vertical Displacement (0x0000001c)*/ +/*! Slice: is_max_dy:*/ +/*! maximum allowed accumulated vertical displacement in lines */ +#define MRV_IS_IS_MAX_DY +#define MRV_IS_IS_MAX_DY_MASK 0x00001FFFU +#define MRV_IS_IS_MAX_DY_SHIFT 0U +/*! Register: isp_is_displace: Camera displacement (0x00000020)*/ +/*! Slice: dy:*/ +/*! ISP_IS will compensate for vertical camera displacement of DY lines in the next frame */ +#define MRV_IS_DY +#define MRV_IS_DY_MASK 0x1FFF0000U +#define MRV_IS_DY_SHIFT 16U +/*! Slice: dx:*/ +/*! ISP_IS will compensate for horizontal camera displacement of DX pixels in the next frame */ +#define MRV_IS_DX +#define MRV_IS_DX_MASK 0x00001FFFU +#define MRV_IS_DX_SHIFT 0U +/*! Register: isp_is_h_offs_shd: current horizontal offset of output window (shadow register) (0x00000024)*/ +/*! Slice: is_h_offs_shd:*/ +/*! current horizonatl picture offset in lines */ +#define MRV_IS_IS_H_OFFS_SHD +#define MRV_IS_IS_H_OFFS_SHD_MASK 0x00003FFFU +#define MRV_IS_IS_H_OFFS_SHD_SHIFT 0U +/*! Register: isp_is_v_offs_shd: current vertical offset of output window (shadow register) (0x00000028)*/ +/*! Slice: is_v_offs_shd:*/ +/*! current vertical picture offset in lines */ +#define MRV_IS_IS_V_OFFS_SHD +#define MRV_IS_IS_V_OFFS_SHD_MASK 0x00003FFFU +#define MRV_IS_IS_V_OFFS_SHD_SHIFT 0U +/*! Register: isp_is_h_size_shd: current output horizontal picture size (shadow register) (0x0000002c)*/ +/*! Slice: isp_h_size_shd:*/ +/*! current horizontal picture size in pixel */ +#define MRV_IS_ISP_H_SIZE_SHD +#define MRV_IS_ISP_H_SIZE_SHD_MASK 0x00003FFFU +#define MRV_IS_ISP_H_SIZE_SHD_SHIFT 0U +/*! Register: isp_is_v_size_shd: current output vertical picture size (shadow register) (0x00000030)*/ +/*! Slice: isp_v_size_shd:*/ +/*! vertical picture size in lines */ +#define MRV_IS_ISP_V_SIZE_SHD +#define MRV_IS_ISP_V_SIZE_SHD_MASK 0x00003FFFU +#define MRV_IS_ISP_V_SIZE_SHD_SHIFT 0U +/*! Register: isp_hist_prop: Histogram properties (0x00000000)*/ +/*! Slice: stepsize:*/ +/*! histogram predivider, process every (stepsize)th pixel, all other pixels are skipped */ +/* 0,1,2: not allowed */ +/* 3: process every third input pixel */ +/* 4: process every fourth input pixel */ +/* ...*/ +/* 7FH: process every 127th pixel */ +#define MRV_HIST_STEPSIZE +#define MRV_HIST_STEPSIZE_MASK 0x000003F8U +#define MRV_HIST_STEPSIZE_SHIFT 3U +/*! Slice: hist_mode:*/ +/*! histogram mode, luminance is taken at ISP output before output formatter, RGB is taken at xtalk output */ +/* 7, 6: must not be used */ +/* 5: Y (luminance) histogram */ +/* 4: B histogram */ +/* 3: G histogram */ +/* 2: R histogram */ +/* 1: RGB combined histogram */ +/* 0: disable, no measurements */ +#define MRV_HIST_MODE +#define MRV_HIST_MODE_MASK 0x00000007U +#define MRV_HIST_MODE_SHIFT 0U +/*! Register: isp_hist_h_offs: Histogram window horizontal offset for first window of 25 sub-windows (0x00000004)*/ +/*! Slice: hist_h_offset:*/ +/*! Horizontal offset of first window in pixels.*/ +#define MRV_HIST_H_OFFSET +#define MRV_HIST_H_OFFSET_MASK 0x00001FFFU +#define MRV_HIST_H_OFFSET_SHIFT 0U +/*! Register: isp_hist_v_offs: Histogram window vertical offset for first window of 25 sub-windows (0x00000008)*/ +/*! Slice: hist_v_offset:*/ +/*! Vertical offset of first window in pixels.*/ +#define MRV_HIST_V_OFFSET +#define MRV_HIST_V_OFFSET_MASK 0x00001FFFU +#define MRV_HIST_V_OFFSET_SHIFT 0U +/*! Register: isp_hist_h_size: Horizontal (sub-)window size (0x0000000c)*/ +/*! Slice: hist_h_size:*/ +/*! Horizontal size in pixels of one sub-window, if histogram version 3 is implemented.*/ +#define MRV_HIST_H_SIZE +#define MRV_HIST_H_SIZE_MASK 0x000007FFU +#define MRV_HIST_H_SIZE_SHIFT 0U +/*! Register: isp_hist_v_size: Vertical (sub-)window size (0x00000010)*/ +/*! Slice: hist_v_size:*/ +/*! Vertical size in lines of one sub-window, if histogram version 3 is implemented.*/ +#define MRV_HIST_V_SIZE +#define MRV_HIST_V_SIZE_MASK 0x000007FFU +#define MRV_HIST_V_SIZE_SHIFT 0U +#ifndef ISP_HIST256 +/*! Register array: isp_hist_bin: histogram measurement result bin (0x028 + n*0x4 (n=0..15))*/ +/*! Slice: hist_bin_n:*/ +/* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */ +#define MRV_HIST_BIN_N +#define MRV_HIST_BIN_N_MASK 0x000FFFFFU +#define MRV_HIST_BIN_N_SHIFT 0U +#else +/*! Register array: isp_hist_bin: histogram measurement result bin (0x028 + n*0x4 (n=0..15))*/ +/*! Slice: hist_bin_n:*/ +/* measured bin count as 26-bit unsigned integer value plus 4 bit fractional part */ +#define MRV_HIST_BIN_N +#define MRV_HIST_BIN_N_MASK 0x3FFFFFFFU +#define MRV_HIST_BIN_N_SHIFT 0U +#endif +/*! Register: isp_hist_weight_00to30: Weighting factor for sub-windows (0x00000054)*/ +/*! Slice: hist_weight_30:*/ +/*! weighting factor for sub-window 30 */ +#define MRV_HIST_WEIGHT_30 +#define MRV_HIST_WEIGHT_30_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_30_SHIFT 24U +/*! Slice: hist_weight_20:*/ +/*! weighting factor for sub-window 20 */ +#define MRV_HIST_WEIGHT_20 +#define MRV_HIST_WEIGHT_20_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_20_SHIFT 16U +/*! Slice: hist_weight_10:*/ +/*! weighting factor for sub-window 10 */ +#define MRV_HIST_WEIGHT_10 +#define MRV_HIST_WEIGHT_10_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_10_SHIFT 8U +/*! Slice: hist_weight_00:*/ +/*! weighting factor for sub-window 00 */ +#define MRV_HIST_WEIGHT_00 +#define MRV_HIST_WEIGHT_00_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_00_SHIFT 0U +/*! Register: isp_hist_weight_40to21: Weighting factor for sub-windows (0x00000058)*/ +/*! Slice: hist_weight_21:*/ +/*! weighting factor for sub-window 21 */ +#define MRV_HIST_WEIGHT_21 +#define MRV_HIST_WEIGHT_21_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_21_SHIFT 24U +/*! Slice: hist_weight_11:*/ +/*! weighting factor for sub-window 11 */ +#define MRV_HIST_WEIGHT_11 +#define MRV_HIST_WEIGHT_11_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_11_SHIFT 16U +/*! Slice: hist_weight_01:*/ +/*! weighting factor for sub-window 01 */ +#define MRV_HIST_WEIGHT_01 +#define MRV_HIST_WEIGHT_01_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_01_SHIFT 8U +/*! Slice: hist_weight_40:*/ +/*! weighting factor for sub-window 40 */ +#define MRV_HIST_WEIGHT_40 +#define MRV_HIST_WEIGHT_40_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_40_SHIFT 0U +/*! Register: isp_hist_weight_31to12: Weighting factor for sub-windows (0x0000005c)*/ +/*! Slice: hist_weight_12:*/ +/*! weighting factor for sub-window 12 */ +#define MRV_HIST_WEIGHT_12 +#define MRV_HIST_WEIGHT_12_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_12_SHIFT 24U +/*! Slice: hist_weight_02:*/ +/*! weighting factor for sub-window 02 */ +#define MRV_HIST_WEIGHT_02 +#define MRV_HIST_WEIGHT_02_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_02_SHIFT 16U +/*! Slice: hist_weight_41:*/ +/*! weighting factor for sub-window 41 */ +#define MRV_HIST_WEIGHT_41 +#define MRV_HIST_WEIGHT_41_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_41_SHIFT 8U +/*! Slice: hist_weight_31:*/ +/*! weighting factor for sub-window 31 */ +#define MRV_HIST_WEIGHT_31 +#define MRV_HIST_WEIGHT_31_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_31_SHIFT 0U +/*! Register: isp_hist_weight_22to03: Weighting factor for sub-windows (0x00000060)*/ +/*! Slice: hist_weight_03:*/ +/*! weighting factor for sub-window 03 */ +#define MRV_HIST_WEIGHT_03 +#define MRV_HIST_WEIGHT_03_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_03_SHIFT 24U +/*! Slice: hist_weight_42:*/ +/*! weighting factor for sub-window 42 */ +#define MRV_HIST_WEIGHT_42 +#define MRV_HIST_WEIGHT_42_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_42_SHIFT 16U +/*! Slice: hist_weight_32:*/ +/*! weighting factor for sub-window 32 */ +#define MRV_HIST_WEIGHT_32 +#define MRV_HIST_WEIGHT_32_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_32_SHIFT 8U +/*! Slice: hist_weight_22:*/ +/*! weighting factor for sub-window 22 */ +#define MRV_HIST_WEIGHT_22 +#define MRV_HIST_WEIGHT_22_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_22_SHIFT 0U +/*! Register: isp_hist_weight_13to43: Weighting factor for sub-windows (0x00000064)*/ +/*! Slice: hist_weight_43:*/ +/*! weighting factor for sub-window 43 */ +#define MRV_HIST_WEIGHT_43 +#define MRV_HIST_WEIGHT_43_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_43_SHIFT 24U +/*! Slice: hist_weight_33:*/ +/*! weighting factor for sub-window 33 */ +#define MRV_HIST_WEIGHT_33 +#define MRV_HIST_WEIGHT_33_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_33_SHIFT 16U +/*! Slice: hist_weight_23:*/ +/*! weighting factor for sub-window 23 */ +#define MRV_HIST_WEIGHT_23 +#define MRV_HIST_WEIGHT_23_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_23_SHIFT 8U +/*! Slice: hist_weight_13:*/ +/*! weighting factor for sub-window 13 */ +#define MRV_HIST_WEIGHT_13 +#define MRV_HIST_WEIGHT_13_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_13_SHIFT 0U +/*! Register: isp_hist_weight_04to34: Weighting factor for sub-windows (0x00000068)*/ +/*! Slice: hist_weight_34:*/ +/*! weighting factor for sub-window 34 */ +#define MRV_HIST_WEIGHT_34 +#define MRV_HIST_WEIGHT_34_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_34_SHIFT 24U +/*! Slice: hist_weight_24:*/ +/*! weighting factor for sub-window 24 */ +#define MRV_HIST_WEIGHT_24 +#define MRV_HIST_WEIGHT_24_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_24_SHIFT 16U +/*! Slice: hist_weight_14:*/ +/*! weighting factor for sub-window 14 */ +#define MRV_HIST_WEIGHT_14 +#define MRV_HIST_WEIGHT_14_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_14_SHIFT 8U +/*! Slice: hist_weight_04:*/ +/*! weighting factor for sub-window 04 */ +#define MRV_HIST_WEIGHT_04 +#define MRV_HIST_WEIGHT_04_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_04_SHIFT 0U +/*! Register: isp_hist_weight_44: Weighting factor for sub-windows (0x0000006c)*/ +/*! Slice: hist_weight_44:*/ +/*! weighting factor for sub-window 44 */ +#define MRV_HIST_WEIGHT_44 +#define MRV_HIST_WEIGHT_44_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_44_SHIFT 0U +/*! Register: isp_filt_mode: mode control register for the filter block (0x00000000)*/ +/*! Slice: stage1_select:*/ +/*! Green filter stage 1 select (range 0x0...0x8)*/ +/* 0x0 maximum blurring */ +/* 0x4 Default */ +/* 0x7 minimum blurring */ +/* 0x8 filter stage1 bypass */ +/* For a detailed description refer to chapter "ISP Filter Programming" of user manual */ +#define MRV_FILT_STAGE1_SELECT +#define MRV_FILT_STAGE1_SELECT_MASK 0x00000F00U +#define MRV_FILT_STAGE1_SELECT_SHIFT 8U +/*! Slice: filt_chr_h_mode:*/ +/*! Chroma filter horizontal mode */ +/* 00 horizontal chroma filter bypass */ +/* 01 horizontal chroma filter 1 static mask =[10 12 10]*/ +/* 10 horizontal chroma filter 2 (dynamic blur1)*/ +/* 11 horizontal chroma filter 3 (dynamic blur2) Default */ +#define MRV_FILT_FILT_CHR_H_MODE +#define MRV_FILT_FILT_CHR_H_MODE_MASK 0x000000C0U +#define MRV_FILT_FILT_CHR_H_MODE_SHIFT 6U +/*! Slice: filt_chr_v_mode:*/ +/*! Chroma filter vertical mode */ +/* 00 vertical chroma filter bypass */ +/* 01 vertical chroma filter 1 static[8 16 8]*/ +/* 10 vertical chroma filter 2 static[10 12 10]*/ +/* 11 vertical chroma filter 3 static[12 8 12] Default */ +#define MRV_FILT_FILT_CHR_V_MODE +#define MRV_FILT_FILT_CHR_V_MODE_MASK 0x00000030U +#define MRV_FILT_FILT_CHR_V_MODE_SHIFT 4U +/*! Slice: filt_mode:*/ +/*! 0 green filter static mode (active filter factor = FILT_FAC_MID)*/ +/* 1 dynamic noise reduction/sharpen Default */ +#define MRV_FILT_FILT_MODE +#define MRV_FILT_FILT_MODE_MASK 0x00000002U +#define MRV_FILT_FILT_MODE_SHIFT 1U +/*! Slice: filt_enable:*/ +/*! 1 enable filter */ +/* 0 bypass filter Default */ +#define MRV_FILT_FILT_ENABLE +#define MRV_FILT_FILT_ENABLE_MASK 0x00000001U +#define MRV_FILT_FILT_ENABLE_SHIFT 0U +/*! Register: isp_filt_thresh_bl0: Blurring threshold 0 (0x00000028)*/ +/*! Slice: filt_thresh_bl0:*/ +/*! If filt_thresh_bl1 < sum_grad < filt_thresh_bl0 then filt_fac_bl0 is selected */ +#define MRV_FILT_FILT_THRESH_BL0 +#define MRV_FILT_FILT_THRESH_BL0_MASK 0x000003FFU +#define MRV_FILT_FILT_THRESH_BL0_SHIFT 0U +/*! Register: isp_filt_thresh_bl1: Blurring threshold 1 (0x0000002c)*/ +/*! Slice: filt_thresh_bl1:*/ +/*! If sum_grad < filt_thresh_bl1 then filt_fac_bl1 is selected */ +#define MRV_FILT_FILT_THRESH_BL1 +#define MRV_FILT_FILT_THRESH_BL1_MASK 0x000003FFU +#define MRV_FILT_FILT_THRESH_BL1_SHIFT 0U +/*! Register: isp_filt_thresh_sh0: Sharpening threshold 0 (0x00000030)*/ +/*! Slice: filt_thresh_sh0:*/ +/*! If filt_thresh_sh0 < sum_grad < filt_thresh_sh1 then filt_thresh_sh0 is selected */ +#define MRV_FILT_FILT_THRESH_SH0 +#define MRV_FILT_FILT_THRESH_SH0_MASK 0x000003FFU +#define MRV_FILT_FILT_THRESH_SH0_SHIFT 0U +/*! Register: isp_filt_thresh_sh1: Sharpening threshold 1 (0x00000034)*/ +/*! Slice: filt_thresh_sh1:*/ +/*! If filt_thresh_sh1 < sum_grad then filt_thresh_sh1 is selected */ +#define MRV_FILT_FILT_THRESH_SH1 +#define MRV_FILT_FILT_THRESH_SH1_MASK 0x000003FFU +#define MRV_FILT_FILT_THRESH_SH1_SHIFT 0U +/*! Register: isp_filt_lum_weight: Parameters for luminance weight function (0x00000038)*/ +/*! Slice: lum_weight_gain:*/ +/*! Gain select of luminance weight function */ +#define MRV_FILT_LUM_WEIGHT_GAIN +#define MRV_FILT_LUM_WEIGHT_GAIN_MASK 0x00070000U +#define MRV_FILT_LUM_WEIGHT_GAIN_SHIFT 16U +/*! Slice: lum_weight_kink:*/ +/*! Kink position of luminance weight function */ +#define MRV_FILT_LUM_WEIGHT_KINK +#define MRV_FILT_LUM_WEIGHT_KINK_MASK 0x0000FF00U +#define MRV_FILT_LUM_WEIGHT_KINK_SHIFT 8U +/*! Slice: lum_weight_min:*/ +/*! Minimum value of luminance weight function */ +#define MRV_FILT_LUM_WEIGHT_MIN +#define MRV_FILT_LUM_WEIGHT_MIN_MASK 0x000000FFU +#define MRV_FILT_LUM_WEIGHT_MIN_SHIFT 0U +/*! Register: isp_filt_fac_sh1: filter factor sharp1 (0x0000003c)*/ +/*! Slice: filt_fac_sh1:*/ +/*! Filter factor for sharp1 level */ +#define MRV_FILT_FILT_FAC_SH1 +#define MRV_FILT_FILT_FAC_SH1_MASK 0x0000003FU +#define MRV_FILT_FILT_FAC_SH1_SHIFT 0U +/*! Register: isp_filt_fac_sh0: filter factor sharp0 (0x00000040)*/ +/*! Slice: filt_fac_sh0:*/ +/*! Filter factor for sharp0 level */ +#define MRV_FILT_FILT_FAC_SH0 +#define MRV_FILT_FILT_FAC_SH0_MASK 0x0000003FU +#define MRV_FILT_FILT_FAC_SH0_SHIFT 0U +/*! Register: isp_filt_fac_mid: filter factor middle (0x00000044)*/ +/*! Slice: filt_fac_mid:*/ +/*! Filter factor for mid level and for static filter mode */ +#define MRV_FILT_FILT_FAC_MID +#define MRV_FILT_FILT_FAC_MID_MASK 0x0000003FU +#define MRV_FILT_FILT_FAC_MID_SHIFT 0U +/*! Register: isp_filt_fac_bl0: Parameter for blur 0 filter (0x00000048)*/ +/*! Slice: filt_fac_bl0:*/ +/*! Filter factor for blur 0 level */ +#define MRV_FILT_FILT_FAC_BL0 +#define MRV_FILT_FILT_FAC_BL0_MASK 0x0000003FU +#define MRV_FILT_FILT_FAC_BL0_SHIFT 0U +/*! Register: isp_filt_fac_bl1: Parameter for blur 1 filter (0x0000004c)*/ +/*! Slice: filt_fac_bl1:*/ +/*! Filter factor for blur 1 level (max blur)*/ +#define MRV_FILT_FILT_FAC_BL1 +#define MRV_FILT_FILT_FAC_BL1_MASK 0x0000003FU +#define MRV_FILT_FILT_FAC_BL1_SHIFT 0U +/*! Register: isp_cac_ctrl: Control register for chromatic aberration correction (0x00000000)*/ +/*! Slice: h_clip_mode:*/ +/*! Defines the maximum red/blue pixel shift in horizontal direction At pixel positions, that require a larger displacement, the maximum shift value is used instead (vector clipping)*/ +/* 0: Set horizontal vector clipping to +/-4 pixel displacement (Default)*/ +/* 1: Set horizontal vector clipping to +/-4 or +/-5 pixel displacement depending on pixel position inside the Bayer raster (dynamic switching between +/-4 and +/-5)*/ +#define MRV_CAC_H_CLIP_MODE +#define MRV_CAC_H_CLIP_MODE_MASK 0x00000008U +#define MRV_CAC_H_CLIP_MODE_SHIFT 3U +/*! Slice: v_clip_mode:*/ +/*! Defines the maximum red/blue pixel shift in vertical direction */ +/* 00: Set vertical vector clipping to +/-2 pixel ; fix filter_enable (Default)*/ +/* 01: Set vertical vector clipping to +/-3 pixel; dynamic filter_enable for chroma low pass filter */ +/* 10: Set vertical vector clipping +/-3 or +/-4 pixel displacement depending on pixel position inside the Bayer raster (dynamic switching between +/-3 and +/-4)*/ +/* 11: reserved */ +#define MRV_CAC_V_CLIP_MODE +#define MRV_CAC_V_CLIP_MODE_MASK 0x00000006U +#define MRV_CAC_V_CLIP_MODE_SHIFT 1U +/*! Slice: cac_en:*/ +/*! 0: chromatic aberration correction off */ +/* 1: chromatic aberration correction on */ +#define MRV_CAC_CAC_EN +#define MRV_CAC_CAC_EN_MASK 0x00000001U +#define MRV_CAC_CAC_EN_SHIFT 0U +/*! Register: isp_cac_count_start: Preload values for CAC pixel and line counter (0x00000004)*/ +/*! Slice: v_count_start:*/ +/*! 13 bit v_count preload value (range 8191 ... 1) of the vertical CAC line counter. Before frame start v_count has to be preloaded with (v_size/2 + v_center_offset), with */ +/* v_size the image height and */ +/* v_center_offset the vertical distance between image center and optical center.*/ + /**/ +/* After frame start the v_count decrements with every line until a value of zero is reached for the line in the optical center. Than the v_sign bit toggles and the v_counter decrements with every line until end of frame.*/ +#define MRV_CAC_V_COUNT_START +#define MRV_CAC_V_COUNT_START_MASK 0x1FFF0000U +#define MRV_CAC_V_COUNT_START_SHIFT 16U +/*! Slice: h_count_start:*/ +/*! 13 bit h_count preload value (range 8191 .. 1) of the horizontal CAC pixel counter. Before line start h_count has to be preloaded with (h_size/2 + h_center_offset), with */ +/* h_size the image width and */ +/* h_center_offset the horizontal distance between image center and optical center.*/ + /**/ +/* After line start the h_count decrements with every pixel until a value of zero is reached for the column in the optical center. Than the h_sign bit toggles and the h_counter increments with every pixel until end of line.*/ +#define MRV_CAC_H_COUNT_START +#define MRV_CAC_H_COUNT_START_MASK 0x00001FFFU +#define MRV_CAC_H_COUNT_START_SHIFT 0U +/*! Register: isp_cac_a: Linear Parameters for radial shift calculation (0x00000008)*/ +/*! Slice: A_Blue:*/ +/*! Parameter A_Blue for radial blue shift calculation, according to */ +/*(A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_A_BLUE +#define MRV_CAC_A_BLUE_MASK 0x01FF0000U +#define MRV_CAC_A_BLUE_SHIFT 16U +/*! Slice: A_Red:*/ +/*! Parameter A_Red for radial red shift calculation, according to */ +/*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_A_RED +#define MRV_CAC_A_RED_MASK 0x000001FFU +#define MRV_CAC_A_RED_SHIFT 0U +/*! Register: isp_cac_b: Square Parameters for radial shift calculation (0x0000000c)*/ +/*! Slice: B_Blue:*/ +/*! Parameter B_Blue for radial blue shift calculation, according to */ +/*(A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_B_BLUE +#define MRV_CAC_B_BLUE_MASK 0x01FF0000U +#define MRV_CAC_B_BLUE_SHIFT 16U +/*! Slice: B_Red:*/ +/*! Parameter B_Red for radial red shift calculation, according to */ +/*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_B_RED +#define MRV_CAC_B_RED_MASK 0x000001FFU +#define MRV_CAC_B_RED_SHIFT 0U +/*! Register: isp_cac_c: Cubical Parameters for radial shift calculation (0x00000010)*/ +/*! Slice: C_Blue:*/ +/*! Parameter C_Blue for radial blue shift calculation, according to */ +/*(A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_C_BLUE +#define MRV_CAC_C_BLUE_MASK 0x01FF0000U +#define MRV_CAC_C_BLUE_SHIFT 16U +/*! Slice: C_Red:*/ +/*! Parameter C_Red for radial red shift calculation, according to */ +/*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_C_RED +#define MRV_CAC_C_RED_MASK 0x000001FFU +#define MRV_CAC_C_RED_SHIFT 0U +/*! Register: isp_cac_x_norm: Normalization parameters for calculation of image coordinate x_d relative to optical center (0x00000014)*/ +/*! Slice: x_ns:*/ +/*! Horizontal normalization shift parameter x_ns (4 bit unsigned integer) in equation */ +/* x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */ +#define MRV_CAC_X_NS +#define MRV_CAC_X_NS_MASK 0x000F0000U +#define MRV_CAC_X_NS_SHIFT 16U +/*! Slice: x_nf:*/ +/*! Horizontal scaling or normalization factor x_nf (5 bit unsigned integer) range 0 .. 31 in equation */ +/* x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */ +#define MRV_CAC_X_NF +#define MRV_CAC_X_NF_MASK 0x0000001FU +#define MRV_CAC_X_NF_SHIFT 0U +/*! Register: isp_cac_y_norm: Normalization parameters for calculation of image coordinate y_d relative to optical center (0x00000018)*/ +/*! Slice: y_ns:*/ +/*! Vertical normalization shift parameter y_ns (4 bit unsigned integer) in equation */ +/* y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */ +#define MRV_CAC_Y_NS +#define MRV_CAC_Y_NS_MASK 0x000F0000U +#define MRV_CAC_Y_NS_SHIFT 16U +/*! Slice: y_nf:*/ +/*! Vertical scaling or normalization factor y_nf (5 bit unsigned integer) range 0 .. 31 in equation */ +/* y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */ +#define MRV_CAC_Y_NF +#define MRV_CAC_Y_NF_MASK 0x0000001FU +#define MRV_CAC_Y_NF_SHIFT 0U +/*! Register: isp_exp_ctrl: Exposure control (0x00000000)*/ +/*! Slice: exp_meas_mode:*/ +/*! '1' luminance calculation according to */ +/* Y=(R+G+B) x 0.332 (85/256)*/ +/* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */ +#define MRV_AE_EXP_MEAS_MODE +#define MRV_AE_EXP_MEAS_MODE_MASK 0x80000000U +#define MRV_AE_EXP_MEAS_MODE_SHIFT 31U +/*! Slice: autostop:*/ +/*! '1' stop measuring after a complete frame */ +/* '0' continous measurement */ +#define MRV_AE_AUTOSTOP +#define MRV_AE_AUTOSTOP_MASK 0x00000002U +#define MRV_AE_AUTOSTOP_SHIFT 1U +/*! Slice: exp_start:*/ +/*! '1' start measuring a frame. The exp block will reset this bit and halt after completing one frame, if bit "autostop" is set to '1'.*/ +#define MRV_AE_EXP_START +#define MRV_AE_EXP_START_MASK 0x00000001U +#define MRV_AE_EXP_START_SHIFT 0U +/*! Register: isp_exp_h_offset: Horizontal offset for first block (0x00000004)*/ +/*! Slice: isp_exp_h_offset:*/ +/*! Horizontal offset of first block in pixels.*/ +/* 0 <= value <= 2424 */ +#define MRV_AE_ISP_EXP_H_OFFSET +#define MRV_AE_ISP_EXP_H_OFFSET_MASK 0x00001FFFU +#define MRV_AE_ISP_EXP_H_OFFSET_SHIFT 0U +/*! Register: isp_exp_v_offset: Vertical offset for first block (0x00000008)*/ +/*! Slice: isp_exp_v_offset:*/ +/*! Vertical offset of first block in pixels.*/ +/* 0 <= value <= 1806 */ +#define MRV_AE_ISP_EXP_V_OFFSET +#define MRV_AE_ISP_EXP_V_OFFSET_MASK 0x00001FFFU +#define MRV_AE_ISP_EXP_V_OFFSET_SHIFT 0U +/*! Register: isp_exp_h_size: Horizontal size of one block (0x0000000c)*/ +/*! Slice: isp_exp_h_size:*/ +/*! Horizontal size in pixels of one block.*/ +/* 35 <= value <= 516 */ +#define MRV_AE_ISP_EXP_H_SIZE +#define MRV_AE_ISP_EXP_H_SIZE_MASK 0x000007FFU +#define MRV_AE_ISP_EXP_H_SIZE_SHIFT 0U +/*! Register: isp_exp_v_size: Vertical size of one block (0x00000010)*/ +/*! Slice: isp_exp_v_size:*/ +/*! Vertical size in pixels of one block.*/ +/* 28 <= value <= 390 */ +#define MRV_AE_ISP_EXP_V_SIZE +#define MRV_AE_ISP_EXP_V_SIZE_MASK 0x000007FEU +#define MRV_AE_ISP_EXP_V_SIZE_SHIFT 0U +/*! Register: isp_exp_mean_00: Mean luminance value of block 00 (0x00000014)*/ +/*! Slice: isp_exp_mean_00:*/ +/*! Mean luminance value of block 00 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_00 +#define MRV_AE_ISP_EXP_MEAN_00_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_00_SHIFT 0U +/*! Register: isp_exp_mean_10: Mean luminance value of block 10 (0x00000018)*/ +/*! Slice: isp_exp_mean_10:*/ +/*! Mean luminance value of block 10 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_10 +#define MRV_AE_ISP_EXP_MEAN_10_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_10_SHIFT 0U +/*! Register: isp_exp_mean_20: Mean luminance value of block 20 (0x0000001c)*/ +/*! Slice: isp_exp_mean_20:*/ +/*! Mean luminance value of block 20 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_20 +#define MRV_AE_ISP_EXP_MEAN_20_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_20_SHIFT 0U +/*! Register: isp_exp_mean_30: Mean luminance value of block 30 (0x00000020)*/ +/*! Slice: isp_exp_mean_30:*/ +/*! Mean luminance value of block 30 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_30 +#define MRV_AE_ISP_EXP_MEAN_30_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_30_SHIFT 0U +/*! Register: isp_exp_mean_40: Mean luminance value of block 40 (0x00000024)*/ +/*! Slice: isp_exp_mean_40:*/ +/*! Mean luminance value of block 40 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_40 +#define MRV_AE_ISP_EXP_MEAN_40_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_40_SHIFT 0U +/*! Register: isp_exp_mean_01: Mean luminance value of block 01 (0x00000028)*/ +/*! Slice: isp_exp_mean_01:*/ +/*! Mean luminance value of block 01 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_01 +#define MRV_AE_ISP_EXP_MEAN_01_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_01_SHIFT 0U +/*! Register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c)*/ +/*! Slice: isp_exp_mean_11:*/ +/*! Mean luminance value of block 11 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_11 +#define MRV_AE_ISP_EXP_MEAN_11_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_11_SHIFT 0U +/*! Register: isp_exp_mean_21: Mean luminance value of block 21 (0x00000030)*/ +/*! Slice: isp_exp_mean_21:*/ +/*! Mean luminance value of block 21 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_21 +#define MRV_AE_ISP_EXP_MEAN_21_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_21_SHIFT 0U +/*! Register: isp_exp_mean_31: Mean luminance value of block 31 (0x00000034)*/ +/*! Slice: isp_exp_mean_31:*/ +/*! Mean luminance value of block 31 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_31 +#define MRV_AE_ISP_EXP_MEAN_31_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_31_SHIFT 0U +/*! Register: isp_exp_mean_41: Mean luminance value of block 41 (0x00000038)*/ +/*! Slice: isp_exp_mean_41:*/ +/*! Mean luminance value of block 41 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_41 +#define MRV_AE_ISP_EXP_MEAN_41_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_41_SHIFT 0U +/*! Register: isp_exp_mean_02: Mean luminance value of block 02 (0x0000003c)*/ +/*! Slice: isp_exp_mean_02:*/ +/*! Mean luminance value of block 02 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_02 +#define MRV_AE_ISP_EXP_MEAN_02_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_02_SHIFT 0U +/*! Register: isp_exp_mean_12: Mean luminance value of block 12 (0x00000040)*/ +/*! Slice: isp_exp_mean_12:*/ +/*! Mean luminance value of block 12 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_12 +#define MRV_AE_ISP_EXP_MEAN_12_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_12_SHIFT 0U +/*! Register: isp_exp_mean_22: Mean luminance value of block 22 (0x00000044)*/ +/*! Slice: isp_exp_mean_22:*/ +/*! Mean luminance value of block 22 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_22 +#define MRV_AE_ISP_EXP_MEAN_22_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_22_SHIFT 0U +/*! Register: isp_exp_mean_32: Mean luminance value of block 32 (0x00000048)*/ +/*! Slice: isp_exp_mean_32:*/ +/*! Mean luminance value of block 32 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_32 +#define MRV_AE_ISP_EXP_MEAN_32_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_32_SHIFT 0U +/*! Register: isp_exp_mean_42: Mean luminance value of block 42 (0x0000004c)*/ +/*! Slice: isp_exp_mean_42:*/ +/*! Mean luminance value of block 42 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_42 +#define MRV_AE_ISP_EXP_MEAN_42_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_42_SHIFT 0U +/*! Register: isp_exp_mean_03: Mean luminance value of block 03 (0x00000050)*/ +/*! Slice: isp_exp_mean_03:*/ +/*! Mean luminance value of block 03 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_03 +#define MRV_AE_ISP_EXP_MEAN_03_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_03_SHIFT 0U +/*! Register: isp_exp_mean_13: Mean luminance value of block 13 (0x00000054)*/ +/*! Slice: isp_exp_mean_13:*/ +/*! Mean luminance value of block 13 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_13 +#define MRV_AE_ISP_EXP_MEAN_13_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_13_SHIFT 0U +/*! Register: isp_exp_mean_23: Mean luminance value of block 23 (0x00000058)*/ +/*! Slice: isp_exp_mean_23:*/ +/*! Mean luminance value of block 23 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_23 +#define MRV_AE_ISP_EXP_MEAN_23_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_23_SHIFT 0U +/*! Register: isp_exp_mean_33: Mean luminance value of block 33 (0x0000005c)*/ +/*! Slice: isp_exp_mean_33:*/ +/*! Mean luminance value of block 33 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_33 +#define MRV_AE_ISP_EXP_MEAN_33_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_33_SHIFT 0U +/*! Register: isp_exp_mean_43: Mean luminance value of block 43 (0x00000060)*/ +/*! Slice: isp_exp_mean_43:*/ +/*! Mean luminance value of block 43 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_43 +#define MRV_AE_ISP_EXP_MEAN_43_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_43_SHIFT 0U +/*! Register: isp_exp_mean_04: Mean luminance value of block 04 (0x00000064)*/ +/*! Slice: isp_exp_mean_04:*/ +/*! Mean luminance value of block 04 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_04 +#define MRV_AE_ISP_EXP_MEAN_04_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_04_SHIFT 0U +/*! Register: isp_exp_mean_14: Mean luminance value of block 14 (0x00000068)*/ +/*! Slice: isp_exp_mean_14:*/ +/*! Mean luminance value of block 14 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_14 +#define MRV_AE_ISP_EXP_MEAN_14_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_14_SHIFT 0U +/*! Register: isp_exp_mean_24: Mean luminance value of block 24 (0x0000006c)*/ +/*! Slice: isp_exp_mean_24:*/ +/*! Mean luminance value of block 24 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_24 +#define MRV_AE_ISP_EXP_MEAN_24_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_24_SHIFT 0U +/*! Register: isp_exp_mean_34: Mean luminance value of block 34 (0x00000070)*/ +/*! Slice: isp_exp_mean_34:*/ +/*! Mean luminance value of block 34 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_34 +#define MRV_AE_ISP_EXP_MEAN_34_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_34_SHIFT 0U +/*! Register: isp_exp_mean_44: Mean luminance value of block 44 (0x00000074)*/ +/*! Slice: isp_exp_mean_44:*/ +/*! Mean luminance value of block 44 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_44 +#define MRV_AE_ISP_EXP_MEAN_44_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_44_SHIFT 0U +/*! Register: isp_expv2_ctrl: (0x00002680)*/ +/*! Slice: isp_expv2_ctrl:*/ +#define MRV_AE_ISP_EXPV2_INPUT_SELECT +#define MRV_AE_ISP_EXPV2_INPUT_SELECT_MASK 0x0000000CU +#define MRV_AE_ISP_EXPV2_INPUT_SELECT_SHIFT 2U +#define MRV_AE_ISP_EXPV2_AUTO_STOP +#define MRV_AE_ISP_EXPV2_AUTO_STOP_MASK 0x00000002U +#define MRV_AE_ISP_EXPV2_AUTO_STOP_SHIFT 1U +#define MRV_AE_ISP_EXPV2_ENABLE +#define MRV_AE_ISP_EXPV2_ENABLE_MASK 0x00000001U +#define MRV_AE_ISP_EXPV2_ENABLE_SHIFT 0U +/*! Register: isp_expv2_offset: (0x00002684)*/ +/*! Slice: isp_expv2_offset:*/ +#define MRV_AE_ISP_EXPV2_OFFSET_V +#define MRV_AE_ISP_EXPV2_OFFSET_V_MASK 0x1FFF0000U +#define MRV_AE_ISP_EXPV2_OFFSET_V_SHIFT 16U +#define MRV_AE_ISP_EXPV2_OFFSET_H +#define MRV_AE_ISP_EXPV2_OFFSET_H_MASK 0x00001FFFU +#define MRV_AE_ISP_EXPV2_OFFSET_H_SHIFT 0 +/*! Register: isp_expv2_size: (0x00002688)*/ +/*! Slice: isp_expv2_size:*/ +#define MRV_AE_ISP_EXPV2_SIZE_V +#define MRV_AE_ISP_EXPV2_SIZE_V_MASK 0x01FF0000U +#define MRV_AE_ISP_EXPV2_SIZE_V_SHIFT 16U +#define MRV_AE_ISP_EXPV2_SIZE_H +#define MRV_AE_ISP_EXPV2_SIZE_H_MASK 0x000001FFU +#define MRV_AE_ISP_EXPV2_SIZE_H_SHIFT 0U +/*! Register: isp_expv2_size_invert: (0x0000268c)*/ +/*! Slice: isp_expv2_size_invert:*/ +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_V +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_V_MASK 0xFFFF0000U +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_V_SHIFT 16U +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_H +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_H_MASK 0x0000FFFFU +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_H_SHIFT 0U +/*! Register: isp_expv2_pixel_weight: (0x00002690)*/ +/*! Slice: isp_expv2_pixel_weight:*/ +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R_MASK 0x3F000000U +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R_SHIFT 24U +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR_MASK 0x003F0000U +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR_SHIFT 16 +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB_MASK 0x00003F00U +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB_SHIFT 8U +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B_MASK 0x0000003FU +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B_SHIFT 0U +/*! Register: isp_bls_ctrl: global control register (0x00000000)*/ +/*! Slice: WINDOW_ENABLE:*/ +/*! 0: no measuring is performed */ +/* 1: only window 1 is measured */ +/* 2: only window 2 is measured */ +/* 3: both windows are measured */ +#define MRV_BLS_WINDOW_ENABLE +#define MRV_BLS_WINDOW_ENABLE_MASK 0x0000000CU +#define MRV_BLS_WINDOW_ENABLE_SHIFT 2U +/*! Slice: BLS_MODE:*/ +/*! 1: subtract measured values */ +/* 0: subtract fixed values */ +#define MRV_BLS_BLS_MODE +#define MRV_BLS_BLS_MODE_MASK 0x00000002U +#define MRV_BLS_BLS_MODE_SHIFT 1U +/*! Slice: BLS_ENABLE:*/ +/*! 1: black level subtraction is enabled */ +/* 0: bypass the black level processing */ +#define MRV_BLS_BLS_ENABLE +#define MRV_BLS_BLS_ENABLE_MASK 0x00000001U +#define MRV_BLS_BLS_ENABLE_SHIFT 0U +/*! Register: isp_bls_samples: samples register (0x00000004)*/ +/*! Slice: BLS_SAMPLES:*/ +/*! This number to the power of two gives the number of measure samples for each Bayer position. Range 0x00: 2^0=1 to 0x12: 2^18=262144. This number is also the divider for the accumulator for each Bayer position.*/ +/* The accumulation will be stopped, if the number of measured pixels for the current Bayer position is equal to the number of samples.*/ +/* The measure windows must be positioned that way that the number of included pixels of each Bayer position included by both windows is equal or greater than the number of measure samples calculated by 2^BLS_SAMPLES !*/ +/* NOTE: The number of pixels of one Bayer position is 1/4 of the number of all Pixels included by the measure windows.*/ +#define MRV_BLS_BLS_SAMPLES +#define MRV_BLS_BLS_SAMPLES_MASK 0x0000001FU +#define MRV_BLS_BLS_SAMPLES_SHIFT 0U +/*! Register: isp_bls_h1_start: window 1 horizontal start (0x00000008)*/ +/*! Slice: BLS_H1_START:*/ +/*! Black pixel window 1 horizontal start position */ +#define MRV_BLS_BLS_H1_START +#define MRV_BLS_BLS_H1_START_MASK 0x00003FFFU +#define MRV_BLS_BLS_H1_START_SHIFT 0U +/*! Register: isp_bls_h1_stop: window 1 horizontal stop (0x0000000c)*/ +/*! Slice: BLS_H1_STOP:*/ +/*! Black pixel window 1 horizontal stop position */ +#define MRV_BLS_BLS_H1_STOP +#define MRV_BLS_BLS_H1_STOP_MASK 0x00003FFFU +#define MRV_BLS_BLS_H1_STOP_SHIFT 0U +/*! Register: isp_bls_v1_start: window 1 vertical start (0x00000010)*/ +/*! Slice: BLS_V1_START:*/ +/*! Black pixel window 1 vertical start position */ +#define MRV_BLS_BLS_V1_START +#define MRV_BLS_BLS_V1_START_MASK 0x00003FFFU +#define MRV_BLS_BLS_V1_START_SHIFT 0U +/*! Register: isp_bls_v1_stop: window 1 vertical stop (0x00000014)*/ +/*! Slice: BLS_V1_STOP:*/ +/*! Black pixel window 1 vertical stop position */ +#define MRV_BLS_BLS_V1_STOP +#define MRV_BLS_BLS_V1_STOP_MASK 0x00003FFFU +#define MRV_BLS_BLS_V1_STOP_SHIFT 0U +/*! Register: isp_bls_h2_start: window 2 horizontal start (0x00000018)*/ +/*! Slice: BLS_H2_START:*/ +/*! Black pixel window 2 horizontal start position */ +#define MRV_BLS_BLS_H2_START +#define MRV_BLS_BLS_H2_START_MASK 0x00003FFFU +#define MRV_BLS_BLS_H2_START_SHIFT 0U +/*! Register: isp_bls_h2_stop: window 2 horizontal stop (0x0000001c)*/ +/*! Slice: BLS_H2_STOP:*/ +/*! Black pixel window 2 horizontal stop position */ +#define MRV_BLS_BLS_H2_STOP +#define MRV_BLS_BLS_H2_STOP_MASK 0x00003FFFU +#define MRV_BLS_BLS_H2_STOP_SHIFT 0U +/*! Register: isp_bls_v2_start: window 2 vertical start (0x00000020)*/ +/*! Slice: BLS_V2_START:*/ +/*! Black pixel window 2 vertical start position */ +#define MRV_BLS_BLS_V2_START +#define MRV_BLS_BLS_V2_START_MASK 0x00003FFFU +#define MRV_BLS_BLS_V2_START_SHIFT 0U +/*! Register: isp_bls_v2_stop: window 2 vertical stop (0x00000024)*/ +/*! Slice: BLS_V2_STOP:*/ +/*! Black pixel window 2 vertical stop position */ +#define MRV_BLS_BLS_V2_STOP +#define MRV_BLS_BLS_V2_STOP_MASK 0x00003FFFU +#define MRV_BLS_BLS_V2_STOP_SHIFT 0U +/*! Register: isp_bls_a_fixed: fixed black level A (0x00000028)*/ +/*! Slice: BLS_A_FIXED:*/ +/*! Fixed black level for A pixels – signed */ +/* two's complement, value range from -4096 to +4095,*/ +/* a positive value will be subtracted from the pixel values */ +#define MRV_BLS_BLS_A_FIXED +#define MRV_BLS_BLS_A_FIXED_MASK 0x00001FFFU +#define MRV_BLS_BLS_A_FIXED_SHIFT 0U +/*! Register: isp_bls_b_fixed: fixed black level B (0x0000002c)*/ +/*! Slice: BLS_B_FIXED:*/ +/*! Fixed black level for B pixels – signed */ +/* two's complement, value range from -4096 to +4095 */ +#define MRV_BLS_BLS_B_FIXED +#define MRV_BLS_BLS_B_FIXED_MASK 0x00001FFFU +#define MRV_BLS_BLS_B_FIXED_SHIFT 0U +/*! Register: isp_bls_c_fixed: fixed black level C (0x00000030)*/ +/*! Slice: BLS_C_FIXED:*/ +/*! Fixed black level for C pixels – signed */ +/* two's complement, value range from -4096 to +4095 */ +#define MRV_BLS_BLS_C_FIXED +#define MRV_BLS_BLS_C_FIXED_MASK 0x00001FFFU +#define MRV_BLS_BLS_C_FIXED_SHIFT 0U +/*! Register: isp_bls_d_fixed: fixed black level D (0x00000034)*/ +/*! Slice: BLS_D_FIXED:*/ +/*! Fixed black level for D pixels - signed */ +/* two's complement, value range from -4096 to +4095 */ +#define MRV_BLS_BLS_D_FIXED +#define MRV_BLS_BLS_D_FIXED_MASK 0x00001FFFU +#define MRV_BLS_BLS_D_FIXED_SHIFT 0U +/*! Register: isp_bls_a_measured: measured black level A (0x00000038)*/ +/*! Slice: BLS_A_MEASURED:*/ +/*! Measured black level for A pixels */ +#define MRV_BLS_BLS_A_MEASURED +#define MRV_BLS_BLS_A_MEASURED_MASK 0x00000FFFU +#define MRV_BLS_BLS_A_MEASURED_SHIFT 0U +/*! Register: isp_bls_b_measured: measured black level B (0x0000003c)*/ +/*! Slice: BLS_B_MEASURED:*/ +/*! Measured black level for B pixels */ +#define MRV_BLS_BLS_B_MEASURED +#define MRV_BLS_BLS_B_MEASURED_MASK 0x00000FFFU +#define MRV_BLS_BLS_B_MEASURED_SHIFT 0U +/*! Register: isp_bls_c_measured: measured black level C (0x00000040)*/ +/*! Slice: BLS_C_MEASURED:*/ +/*! Measured black level for C pixels */ +#define MRV_BLS_BLS_C_MEASURED +#define MRV_BLS_BLS_C_MEASURED_MASK 0x00000FFFU +#define MRV_BLS_BLS_C_MEASURED_SHIFT 0U +/*! Register: isp_bls_d_measured: measured black level D (0x00000044)*/ +/*! Slice: BLS_D_MEASURED:*/ +/*! Measured black level for D pixels */ +#define MRV_BLS_BLS_D_MEASURED +#define MRV_BLS_BLS_D_MEASURED_MASK 0x00000FFFU +#define MRV_BLS_BLS_D_MEASURED_SHIFT 0U +/*! Register: isp_dpf_mode: Mode control for Denoising Pre-Filter block (0x00000000)*/ +/*! Slice: USE_NF_GAIN:*/ +/*! 1: DPF_NF_GAINs will be used.*/ +/* 0: DPF_NF_GAINs will not be used. *Default**/ +#define MRV_DPF_USE_NF_GAIN +#define MRV_DPF_USE_NF_GAIN_MASK 0x00000200U +#define MRV_DPF_USE_NF_GAIN_SHIFT 9U +/*! Slice: LSC_GAIN_COMP:*/ +/*! 1: LSC gain will be processed */ +/* 0: LSC gain will not be processed. Use LSC gain factor of 1. *Default**/ +#define MRV_DPF_LSC_GAIN_COMP +#define MRV_DPF_LSC_GAIN_COMP_MASK 0x00000100U +#define MRV_DPF_LSC_GAIN_COMP_SHIFT 8U +/*! Slice: AWB_GAIN_COMP:*/ +/*! Only relevant when use_nf_gain == 0 && ISP_CTRL::ISP_AWB_ENABLE ==1 */ +/* 1: ISP_AWB gains will be processed */ +/* 0: ISP_AWB gains will not be processed. Use AWB gain factor of 1. *Default**/ +#define MRV_DPF_AWB_GAIN_COMP +#define MRV_DPF_AWB_GAIN_COMP_MASK 0x00000080U +#define MRV_DPF_AWB_GAIN_COMP_SHIFT 7U +/*! Slice: NLL_SEGMENTATION:*/ +/*! 1: optimized logarithmic like segmentation for Noise Level Lookup (NLL)*/ +/* 0: equidistant segmentation for NLL *Default**/ +#define MRV_DPF_NLL_SEGMENTATION +#define MRV_DPF_NLL_SEGMENTATION_MASK 0x00000040U +#define MRV_DPF_NLL_SEGMENTATION_SHIFT 6U +/*! Slice: RB_FILTER_SIZE:*/ +/*! 1: Red and Blue filter kernel size of 9x9 (5x5 active) pixels */ +/* 0: Wide Red and Blue filter kernel size of 13x9 (7x5 active) pixels *Default**/ +#define MRV_DPF_RB_FILTER_SIZE +#define MRV_DPF_RB_FILTER_SIZE_MASK 0x00000020U +#define MRV_DPF_RB_FILTER_SIZE_SHIFT 5U +/*! Slice: R_FILTER_OFF:*/ +/*! 1: disable filter processing for red pixels (R)*/ +/* 0: filter R pixels *Default**/ +#define MRV_DPF_R_FILTER_OFF +#define MRV_DPF_R_FILTER_OFF_MASK 0x00000010U +#define MRV_DPF_R_FILTER_OFF_SHIFT 4U +/*! Slice: GR_FILTER_OFF:*/ +/*! 1: disable filter processing for green pixels in green/red lines (GR)*/ +/* 0: filter GR pixels *Default**/ +#define MRV_DPF_GR_FILTER_OFF +#define MRV_DPF_GR_FILTER_OFF_MASK 0x00000008U +#define MRV_DPF_GR_FILTER_OFF_SHIFT 3U +/*! Slice: GB_FILTER_OFF:*/ +/*! 1: disable filter processing for green pixels in green/blue lines (GB)*/ +/* 0: filter GB pixels *Default**/ +#define MRV_DPF_GB_FILTER_OFF +#define MRV_DPF_GB_FILTER_OFF_MASK 0x00000004U +#define MRV_DPF_GB_FILTER_OFF_SHIFT 2U +/*! Slice: B_FILTER_OFF:*/ +/*! 1: disable filter processing for blue pixels (B)*/ +/* 0: filter B pixels *Default**/ +#define MRV_DPF_B_FILTER_OFF +#define MRV_DPF_B_FILTER_OFF_MASK 0x00000002U +#define MRV_DPF_B_FILTER_OFF_SHIFT 1U +/*! Slice: DPF_ENABLE:*/ +/*! 1: enable dpf */ +/* 0: bypass dpf *Default**/ +#define MRV_DPF_DPF_ENABLE +#define MRV_DPF_DPF_ENABLE_MASK 0x00000001U +#define MRV_DPF_DPF_ENABLE_SHIFT 0U +/*! Register: isp_dpf_strength_r: filter strength of the RED filter (0x00000004)*/ +/*! Slice: INV_WEIGHT_R:*/ +/*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#define MRV_DPF_INV_WEIGHT_R +#define MRV_DPF_INV_WEIGHT_R_MASK 0x000000FFU +#define MRV_DPF_INV_WEIGHT_R_SHIFT 0U +/*! Register: isp_dpf_strength_g: filter strength of the GREEN filter (0x00000008)*/ +/*! Slice: INV_WEIGHT_G:*/ +/*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#define MRV_DPF_INV_WEIGHT_G +#define MRV_DPF_INV_WEIGHT_G_MASK 0x000000FFU +#define MRV_DPF_INV_WEIGHT_G_SHIFT 0U +/*! Register: isp_dpf_strength_b: filter strength of the BLUE filter (0x0000000c)*/ +/*! Slice: INV_WEIGHT_B:*/ +/*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#define MRV_DPF_INV_WEIGHT_B +#define MRV_DPF_INV_WEIGHT_B_MASK 0x000000FFU +#define MRV_DPF_INV_WEIGHT_B_SHIFT 0U +/*! Register: isp_dpf_s_weight_g_1_4: Spatial Weights green channel 1 2 3 4 (0x00000010)*/ +/*! Slice: S_WEIGHT_G4:*/ +/*! Filter Coefficient green channel S_WEIGHT_G4 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G4 +#define MRV_DPF_S_WEIGHT_G4_MASK 0x1F000000U +#define MRV_DPF_S_WEIGHT_G4_SHIFT 24U +/*! Slice: S_WEIGHT_G3:*/ +/*! Filter Coefficient green channel S_WEIGHT_G3 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G3 +#define MRV_DPF_S_WEIGHT_G3_MASK 0x001F0000U +#define MRV_DPF_S_WEIGHT_G3_SHIFT 16U +/*! Slice: S_WEIGHT_G2:*/ +/*! Filter Coefficient green channel S_WEIGHT_G2 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G2 +#define MRV_DPF_S_WEIGHT_G2_MASK 0x00001F00U +#define MRV_DPF_S_WEIGHT_G2_SHIFT 8U +/*! Slice: S_WEIGHT_G1:*/ +/*! Filter Coefficient green channel S_WEIGHT_G1 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G1 +#define MRV_DPF_S_WEIGHT_G1_MASK 0x0000001FU +#define MRV_DPF_S_WEIGHT_G1_SHIFT 0U +/*! Register: isp_dpf_s_weight_g_5_6: Spatial Weights green channel 5 6 (0x00000014)*/ +/*! Slice: S_WEIGHT_G6:*/ +/*! Filter Coefficient green channel S_WEIGHT_G6 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G6 +#define MRV_DPF_S_WEIGHT_G6_MASK 0x00001F00U +#define MRV_DPF_S_WEIGHT_G6_SHIFT 8U +/*! Slice: S_WEIGHT_G5:*/ +/*! Filter Coefficient green channel S_WEIGHT_G5 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G5 +#define MRV_DPF_S_WEIGHT_G5_MASK 0x0000001FU +#define MRV_DPF_S_WEIGHT_G5_SHIFT 0U +/*! Register: isp_dpf_s_weight_rb_1_4: Spatial Weights red/blue channels 1 2 3 4 (0x00000018)*/ +/*! Slice: S_WEIGHT_RB4:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB4 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB4 +#define MRV_DPF_S_WEIGHT_RB4_MASK 0x1F000000U +#define MRV_DPF_S_WEIGHT_RB4_SHIFT 24U +/*! Slice: S_WEIGHT_RB3:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB3 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB3 +#define MRV_DPF_S_WEIGHT_RB3_MASK 0x001F0000U +#define MRV_DPF_S_WEIGHT_RB3_SHIFT 16U +/*! Slice: S_WEIGHT_RB2:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB2 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB2 +#define MRV_DPF_S_WEIGHT_RB2_MASK 0x00001F00U +#define MRV_DPF_S_WEIGHT_RB2_SHIFT 8U +/*! Slice: S_WEIGHT_RB1:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB1 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB1 +#define MRV_DPF_S_WEIGHT_RB1_MASK 0x0000001FU +#define MRV_DPF_S_WEIGHT_RB1_SHIFT 0U +/*! Register: isp_dpf_s_weight_rb_5_6: Spatial Weights red/blue channels 5 6 (0x0000001c)*/ +/*! Slice: S_WEIGHT_RB6:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB6 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB6 +#define MRV_DPF_S_WEIGHT_RB6_MASK 0x00001F00U +#define MRV_DPF_S_WEIGHT_RB6_SHIFT 8U +/*! Slice: S_WEIGHT_RB5:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB5 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB5 +#define MRV_DPF_S_WEIGHT_RB5_MASK 0x0000001FU +#define MRV_DPF_S_WEIGHT_RB5_SHIFT 0U +/*! Register array: isp_dpf_nll_coeff: Noise Level Lookup Coefficient (0x0040 + n*0x4 (n=0..16))*/ +/*! Slice: nll_coeff_n:*/ +/* Noise Level Lookup Table Coefficient nll_coeff_n */ +/* 10 bit unsigned, value range 1/1024 to 1023/1024 (*Default*)*/ +#define MRV_DPF_NLL_COEFF_N +#define MRV_DPF_NLL_COEFF_N_MASK 0x000003FFU +#define MRV_DPF_NLL_COEFF_N_SHIFT 0U +/*! Register: isp_dpf_nf_gain_r: noise function gain for red pixels (0x00000064)*/ +/*! Slice: DPF_NF_GAIN_R:*/ +/*! Noise Function (NF) Gain that replaces the AWB gain for red pixels.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#define MRV_DPF_DPF_NF_GAIN_R +#define MRV_DPF_DPF_NF_GAIN_R_MASK 0x00000FFFU +#define MRV_DPF_DPF_NF_GAIN_R_SHIFT 0U +/*! Register: isp_dpf_nf_gain_gr: noise function gain for green in red pixels (0x00000068)*/ +/*! Slice: DPF_NF_GAIN_GR:*/ +/*! Noise Function (NF) Gain that replaces the AWB gain for green pixels in a red line.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#define MRV_DPF_DPF_NF_GAIN_GR +#define MRV_DPF_DPF_NF_GAIN_GR_MASK 0x00000FFFU +#define MRV_DPF_DPF_NF_GAIN_GR_SHIFT 0U +/*! Register: isp_dpf_nf_gain_gb: noise function gain for green in blue pixels (0x0000006c)*/ +/*! Slice: DPF_NF_GAIN_GB:*/ +/*! Noise Function (NF) Gain that replaces the AWB gain for green pixels in a blue line.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#define MRV_DPF_DPF_NF_GAIN_GB +#define MRV_DPF_DPF_NF_GAIN_GB_MASK 0x00000FFFU +#define MRV_DPF_DPF_NF_GAIN_GB_SHIFT 0U +/*! Register: isp_dpf_nf_gain_b: noise function gain for blue pixels (0x00000070)*/ +/*! Slice: DPF_NF_GAIN_B:*/ +/*! Noise Function (NF) Gain that replaces the AWB gain for blue pixels.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#define MRV_DPF_DPF_NF_GAIN_B +#define MRV_DPF_DPF_NF_GAIN_B_MASK 0x00000FFFU +#define MRV_DPF_DPF_NF_GAIN_B_SHIFT 0U +/*! Register: isp_dpcc_mode: Mode control for DPCC detection unit (0x00000000)*/ +/*! Slice: STAGE1_ENABLE:*/ +/*! 1: enable stage1 *Default**/ +/* 0: bypass stage1 */ +#define MRV_DPCC_STAGE1_ENABLE +#define MRV_DPCC_STAGE1_ENABLE_MASK 0x00000004U +#define MRV_DPCC_STAGE1_ENABLE_SHIFT 2U +/*! Slice: GRAYSCALE_MODE:*/ +/*! 1: enable gray scale data input from black and white sensors (without color filter array)*/ +/* 0: BAYER DATA INPUT *Default**/ +#define MRV_DPCC_GRAYSCALE_MODE +#define MRV_DPCC_GRAYSCALE_MODE_MASK 0x00000002U +#define MRV_DPCC_GRAYSCALE_MODE_SHIFT 1U +/*! Slice: ISP_DPCC_enable:*/ +/*! 1: enable DPCC */ +/* 0: bypass DPCC *Default**/ +#define MRV_DPCC_ISP_DPCC_ENABLE +#define MRV_DPCC_ISP_DPCC_ENABLE_MASK 0x00000001U +#define MRV_DPCC_ISP_DPCC_ENABLE_SHIFT 0U +/*! Register: isp_dpcc_output_mode: Interpolation mode for correction unit (0x00000004)*/ +/*! Slice: STAGE1_RB_3x3:*/ +/*! 1: stage1 red/blue 9 pixel (3x3) output median */ +/* 0: stage1 red/blue 4 or 5 pixel output median *Default**/ +#define MRV_DPCC_STAGE1_RB_3X3 +#define MRV_DPCC_STAGE1_RB_3X3_MASK 0x00000008U +#define MRV_DPCC_STAGE1_RB_3X3_SHIFT 3U +/*! Slice: STAGE1_G_3x3:*/ +/*! 1: stage1 green 9 pixel (3x3) output median */ +/* 0: stage1 green 4 or 5 pixel output median *Default**/ +#define MRV_DPCC_STAGE1_G_3X3 +#define MRV_DPCC_STAGE1_G_3X3_MASK 0x00000004U +#define MRV_DPCC_STAGE1_G_3X3_SHIFT 2U +/*! Slice: STAGE1_INCL_RB_CENTER:*/ +/*! 1: stage1 include center pixel for red/blue output median 2x2+1 */ +/* *Default* 0: stage1 do not include center pixel for red/blue output median 2x2 */ +#define MRV_DPCC_STAGE1_INCL_RB_CENTER +#define MRV_DPCC_STAGE1_INCL_RB_CENTER_MASK 0x00000002U +#define MRV_DPCC_STAGE1_INCL_RB_CENTER_SHIFT 1U +/*! Slice: STAGE1_INCL_GREEN_CENTER:*/ +/*! 1: stage1 include center pixel for green output median 2x2+1 *Default**/ +/* 0: stage1 do not include center pixel for green output median 2x2 */ +#define MRV_DPCC_STAGE1_INCL_GREEN_CENTER +#define MRV_DPCC_STAGE1_INCL_GREEN_CENTER_MASK 0x00000001U +#define MRV_DPCC_STAGE1_INCL_GREEN_CENTER_SHIFT 0U +/*! Register: isp_dpcc_set_use: DPCC methods set usage for detection (0x00000008)*/ +/*! Slice: STAGE1_USE_FIX_SET:*/ +/*! 1: stage1 use hard coded methods set *Default**/ +/* 0: stage1 do not use hard coded methods set */ +#define MRV_DPCC_STAGE1_USE_FIX_SET +#define MRV_DPCC_STAGE1_USE_FIX_SET_MASK 0x00000008U +#define MRV_DPCC_STAGE1_USE_FIX_SET_SHIFT 3U +/*! Slice: STAGE1_USE_SET_3:*/ +/*! 1: stage1 use methods set 3 */ +/* 0: stage1 do not use methods set 3 *Default**/ +#define MRV_DPCC_STAGE1_USE_SET_3 +#define MRV_DPCC_STAGE1_USE_SET_3_MASK 0x00000004U +#define MRV_DPCC_STAGE1_USE_SET_3_SHIFT 2U +/*! Slice: STAGE1_USE_SET_2:*/ +/*! 1: stage1 use methods set 2 */ +/* 0: stage1 do not use methods set 2 *Default**/ +#define MRV_DPCC_STAGE1_USE_SET_2 +#define MRV_DPCC_STAGE1_USE_SET_2_MASK 0x00000002U +#define MRV_DPCC_STAGE1_USE_SET_2_SHIFT 1U +/*! Slice: STAGE1_USE_SET_1:*/ +/*! 1: stage1 use methods set 1 *Default**/ +/* 0: stage1 do not use methods set 1 */ +#define MRV_DPCC_STAGE1_USE_SET_1 +#define MRV_DPCC_STAGE1_USE_SET_1_MASK 0x00000001U +#define MRV_DPCC_STAGE1_USE_SET_1_SHIFT 0U +/*! Register: isp_dpcc_methods_set_1: Methods enable bits for SET_1 (0x0000000c)*/ +/*! Slice: RG_RED_BLUE1_ENABLE:*/ +/*! 1: enable Rank Gradient check for red_blue *Default**/ +/* 0: bypass Rank Gradient check for red_blue */ +#define MRV_DPCC_RG_RED_BLUE1_ENABLE +#define MRV_DPCC_RG_RED_BLUE1_ENABLE_MASK 0x00001000U +#define MRV_DPCC_RG_RED_BLUE1_ENABLE_SHIFT 12U +/*! Slice: RND_RED_BLUE1_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for red_blue *Default**/ +/* 0: bypass Rank Neighbor Difference check for red_blue */ +#define MRV_DPCC_RND_RED_BLUE1_ENABLE +#define MRV_DPCC_RND_RED_BLUE1_ENABLE_MASK 0x00000800U +#define MRV_DPCC_RND_RED_BLUE1_ENABLE_SHIFT 11U +/*! Slice: RO_RED_BLUE1_ENABLE:*/ +/*! 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#define MRV_DPCC_RO_RED_BLUE1_ENABLE +#define MRV_DPCC_RO_RED_BLUE1_ENABLE_MASK 0x00000400U +#define MRV_DPCC_RO_RED_BLUE1_ENABLE_SHIFT 10U +/*! Slice: LC_RED_BLUE1_ENABLE:*/ +/*! 1: enable Line check for red_blue *Default**/ +/* 0: bypass Line check for red_blue */ +#define MRV_DPCC_LC_RED_BLUE1_ENABLE +#define MRV_DPCC_LC_RED_BLUE1_ENABLE_MASK 0x00000200U +#define MRV_DPCC_LC_RED_BLUE1_ENABLE_SHIFT 9U +/*! Slice: PG_RED_BLUE1_ENABLE:*/ +/*! 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#define MRV_DPCC_PG_RED_BLUE1_ENABLE +#define MRV_DPCC_PG_RED_BLUE1_ENABLE_MASK 0x00000100U +#define MRV_DPCC_PG_RED_BLUE1_ENABLE_SHIFT 8U +/*! Slice: RG_GREEN1_ENABLE:*/ +/*! 1: enable Rank Gradient check for green *Default**/ +/* 0: bypass Rank Gradient check for green */ +#define MRV_DPCC_RG_GREEN1_ENABLE +#define MRV_DPCC_RG_GREEN1_ENABLE_MASK 0x00000010U +#define MRV_DPCC_RG_GREEN1_ENABLE_SHIFT 4U +/*! Slice: RND_GREEN1_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for green *Default**/ +/* 0: bypass Rank Neighbor Difference check for green */ +#define MRV_DPCC_RND_GREEN1_ENABLE +#define MRV_DPCC_RND_GREEN1_ENABLE_MASK 0x00000008U +#define MRV_DPCC_RND_GREEN1_ENABLE_SHIFT 3U +/*! Slice: RO_GREEN1_ENABLE:*/ +/*! 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#define MRV_DPCC_RO_GREEN1_ENABLE +#define MRV_DPCC_RO_GREEN1_ENABLE_MASK 0x00000004U +#define MRV_DPCC_RO_GREEN1_ENABLE_SHIFT 2U +/*! Slice: LC_GREEN1_ENABLE:*/ +/*! 1: enable Line check for green *Default**/ +/* 0: bypass Line check for green */ +#define MRV_DPCC_LC_GREEN1_ENABLE +#define MRV_DPCC_LC_GREEN1_ENABLE_MASK 0x00000002U +#define MRV_DPCC_LC_GREEN1_ENABLE_SHIFT 1U +/*! Slice: PG_GREEN1_ENABLE:*/ +/*! 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#define MRV_DPCC_PG_GREEN1_ENABLE +#define MRV_DPCC_PG_GREEN1_ENABLE_MASK 0x00000001U +#define MRV_DPCC_PG_GREEN1_ENABLE_SHIFT 0U +/*! Register: isp_dpcc_methods_set_2: Methods enable bits for SET_2 (0x00000010)*/ +/*! Slice: RG_RED_BLUE2_ENABLE:*/ +/*! 1: enable Rank Gradient check for red_blue *Default**/ +/* 0: bypass Rank Gradient check for red_blue */ +#define MRV_DPCC_RG_RED_BLUE2_ENABLE +#define MRV_DPCC_RG_RED_BLUE2_ENABLE_MASK 0x00001000U +#define MRV_DPCC_RG_RED_BLUE2_ENABLE_SHIFT 12U +/*! Slice: RND_RED_BLUE2_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for red_blue *Default**/ +/* 0: bypass Rank Neighbor Difference check for red_blue */ +#define MRV_DPCC_RND_RED_BLUE2_ENABLE +#define MRV_DPCC_RND_RED_BLUE2_ENABLE_MASK 0x00000800U +#define MRV_DPCC_RND_RED_BLUE2_ENABLE_SHIFT 11U +/*! Slice: RO_RED_BLUE2_ENABLE:*/ +/*! 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#define MRV_DPCC_RO_RED_BLUE2_ENABLE +#define MRV_DPCC_RO_RED_BLUE2_ENABLE_MASK 0x00000400U +#define MRV_DPCC_RO_RED_BLUE2_ENABLE_SHIFT 10U +/*! Slice: LC_RED_BLUE2_ENABLE:*/ +/*! 1: enable Line check for red_blue */ +/* 0: bypass Line check for red_blue *Default**/ +#define MRV_DPCC_LC_RED_BLUE2_ENABLE +#define MRV_DPCC_LC_RED_BLUE2_ENABLE_MASK 0x00000200U +#define MRV_DPCC_LC_RED_BLUE2_ENABLE_SHIFT 9U +/*! Slice: PG_RED_BLUE2_ENABLE:*/ +/*! 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#define MRV_DPCC_PG_RED_BLUE2_ENABLE +#define MRV_DPCC_PG_RED_BLUE2_ENABLE_MASK 0x00000100U +#define MRV_DPCC_PG_RED_BLUE2_ENABLE_SHIFT 8U +/*! Slice: RG_GREEN2_ENABLE:*/ +/*! 1: enable Rank Gradient check for green *Default**/ +/* 0: bypass Rank Gradient check for green */ +#define MRV_DPCC_RG_GREEN2_ENABLE +#define MRV_DPCC_RG_GREEN2_ENABLE_MASK 0x00000010U +#define MRV_DPCC_RG_GREEN2_ENABLE_SHIFT 4U +/*! Slice: RND_GREEN2_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for green *Default**/ +/* 0: bypass Rank Neighbor Difference check for green */ +#define MRV_DPCC_RND_GREEN2_ENABLE +#define MRV_DPCC_RND_GREEN2_ENABLE_MASK 0x00000008U +#define MRV_DPCC_RND_GREEN2_ENABLE_SHIFT 3U +/*! Slice: RO_GREEN2_ENABLE:*/ +/*! 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#define MRV_DPCC_RO_GREEN2_ENABLE +#define MRV_DPCC_RO_GREEN2_ENABLE_MASK 0x00000004U +#define MRV_DPCC_RO_GREEN2_ENABLE_SHIFT 2U +/*! Slice: LC_GREEN2_ENABLE:*/ +/*! 1: enable Line check for green */ +/* 0: bypass Line check for green *Default**/ +#define MRV_DPCC_LC_GREEN2_ENABLE +#define MRV_DPCC_LC_GREEN2_ENABLE_MASK 0x00000002U +#define MRV_DPCC_LC_GREEN2_ENABLE_SHIFT 1U +/*! Slice: PG_GREEN2_ENABLE:*/ +/*! 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#define MRV_DPCC_PG_GREEN2_ENABLE +#define MRV_DPCC_PG_GREEN2_ENABLE_MASK 0x00000001U +#define MRV_DPCC_PG_GREEN2_ENABLE_SHIFT 0U +/*! Register: isp_dpcc_methods_set_3: Methods enable bits for SET_3 (0x00000014)*/ +/*! Slice: RG_RED_BLUE3_ENABLE:*/ +/*! 1: enable Rank Gradient check for red_blue */ +/* 0: bypass Rank Gradient check for red_blue *Default**/ +#define MRV_DPCC_RG_RED_BLUE3_ENABLE +#define MRV_DPCC_RG_RED_BLUE3_ENABLE_MASK 0x00001000U +#define MRV_DPCC_RG_RED_BLUE3_ENABLE_SHIFT 12U +/*! Slice: RND_RED_BLUE3_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for red_blue */ +/* 0: bypass Rank Neighbor Difference check for red_blue *Default**/ +#define MRV_DPCC_RND_RED_BLUE3_ENABLE +#define MRV_DPCC_RND_RED_BLUE3_ENABLE_MASK 0x00000800U +#define MRV_DPCC_RND_RED_BLUE3_ENABLE_SHIFT 11U +/*! Slice: RO_RED_BLUE3_ENABLE:*/ +/*! 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#define MRV_DPCC_RO_RED_BLUE3_ENABLE +#define MRV_DPCC_RO_RED_BLUE3_ENABLE_MASK 0x00000400U +#define MRV_DPCC_RO_RED_BLUE3_ENABLE_SHIFT 10U +/*! Slice: LC_RED_BLUE3_ENABLE:*/ +/*! 1: enable Line check for red_blue *Default**/ +/* 0: bypass Line check for red_blue */ +#define MRV_DPCC_LC_RED_BLUE3_ENABLE +#define MRV_DPCC_LC_RED_BLUE3_ENABLE_MASK 0x00000200U +#define MRV_DPCC_LC_RED_BLUE3_ENABLE_SHIFT 9U +/*! Slice: PG_RED_BLUE3_ENABLE:*/ +/*! 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#define MRV_DPCC_PG_RED_BLUE3_ENABLE +#define MRV_DPCC_PG_RED_BLUE3_ENABLE_MASK 0x00000100U +#define MRV_DPCC_PG_RED_BLUE3_ENABLE_SHIFT 8U +/*! Slice: RG_GREEN3_ENABLE:*/ +/*! 1: enable Rank Gradient check for green */ +/* 0: bypass Rank Gradient check for green *Default**/ +#define MRV_DPCC_RG_GREEN3_ENABLE +#define MRV_DPCC_RG_GREEN3_ENABLE_MASK 0x00000010U +#define MRV_DPCC_RG_GREEN3_ENABLE_SHIFT 4U +/*! Slice: RND_GREEN3_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for green */ +/* 0: bypass Rank Neighbor Difference check for green *Default**/ +#define MRV_DPCC_RND_GREEN3_ENABLE +#define MRV_DPCC_RND_GREEN3_ENABLE_MASK 0x00000008U +#define MRV_DPCC_RND_GREEN3_ENABLE_SHIFT 3U +/*! Slice: RO_GREEN3_ENABLE:*/ +/*! 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#define MRV_DPCC_RO_GREEN3_ENABLE +#define MRV_DPCC_RO_GREEN3_ENABLE_MASK 0x00000004U +#define MRV_DPCC_RO_GREEN3_ENABLE_SHIFT 2U +/*! Slice: LC_GREEN3_ENABLE:*/ +/*! 1: enable Line check for green *Default**/ +/* 0: bypass Line check for green */ +#define MRV_DPCC_LC_GREEN3_ENABLE +#define MRV_DPCC_LC_GREEN3_ENABLE_MASK 0x00000002U +#define MRV_DPCC_LC_GREEN3_ENABLE_SHIFT 1U +/*! Slice: PG_GREEN3_ENABLE:*/ +/*! 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#define MRV_DPCC_PG_GREEN3_ENABLE +#define MRV_DPCC_PG_GREEN3_ENABLE_MASK 0x00000001U +#define MRV_DPCC_PG_GREEN3_ENABLE_SHIFT 0U +/*! Register: isp_dpcc_line_thresh_1: Line threshold SET_1 (0x00000018)*/ +/*! Slice: LINE_THR_1_RB:*/ +/*! line threshold for set 1 red/blue */ +#define MRV_DPCC_LINE_THR_1_RB +#define MRV_DPCC_LINE_THR_1_RB_MASK 0x0000FF00U +#define MRV_DPCC_LINE_THR_1_RB_SHIFT 8U +/*! Slice: LINE_THR_1_G:*/ +/*! line threshold for set 1 green */ +#define MRV_DPCC_LINE_THR_1_G +#define MRV_DPCC_LINE_THR_1_G_MASK 0x000000FFU +#define MRV_DPCC_LINE_THR_1_G_SHIFT 0U +/*! Register: isp_dpcc_line_mad_fac_1: Mean Absolute Difference (MAD) factor for Line check set 1 (0x0000001c)*/ +/*! Slice: LINE_MAD_FAC_1_RB:*/ +/*! line MAD factor for set 1 red/blue */ +#define MRV_DPCC_LINE_MAD_FAC_1_RB +#define MRV_DPCC_LINE_MAD_FAC_1_RB_MASK 0x00003F00U +#define MRV_DPCC_LINE_MAD_FAC_1_RB_SHIFT 8U +/*! Slice: LINE_MAD_FAC_1_G:*/ +/*! line MAD factor for set 1 green */ +#define MRV_DPCC_LINE_MAD_FAC_1_G +#define MRV_DPCC_LINE_MAD_FAC_1_G_MASK 0x0000003FU +#define MRV_DPCC_LINE_MAD_FAC_1_G_SHIFT 0U +/*! Register: isp_dpcc_pg_fac_1: Peak gradient factor for set 1 (0x00000020)*/ +/*! Slice: PG_FAC_1_RB:*/ +/*! Peak gradient factor for set 1 red/blue */ +#define MRV_DPCC_PG_FAC_1_RB +#define MRV_DPCC_PG_FAC_1_RB_MASK 0x00003F00U +#define MRV_DPCC_PG_FAC_1_RB_SHIFT 8U +/*! Slice: PG_FAC_1_G:*/ +/*! Peak gradient factor for set 1 green */ +#define MRV_DPCC_PG_FAC_1_G +#define MRV_DPCC_PG_FAC_1_G_MASK 0x0000003FU +#define MRV_DPCC_PG_FAC_1_G_SHIFT 0U +/*! Register: isp_dpcc_rnd_thresh_1: Rank Neighbor Difference threshold for set 1 (0x00000024)*/ +/*! Slice: RND_THR_1_RB:*/ +/*! Rank Neighbor Difference threshold for set 1 red/blue */ +#define MRV_DPCC_RND_THR_1_RB +#define MRV_DPCC_RND_THR_1_RB_MASK 0x0000FF00U +#define MRV_DPCC_RND_THR_1_RB_SHIFT 8U +/*! Slice: RND_THR_1_G:*/ +/*! Rank Neighbor Difference threshold for set 1 green */ +#define MRV_DPCC_RND_THR_1_G +#define MRV_DPCC_RND_THR_1_G_MASK 0x000000FFU +#define MRV_DPCC_RND_THR_1_G_SHIFT 0U +/*! Register: isp_dpcc_rg_fac_1: Rank gradient factor for set 1 (0x00000028)*/ +/*! Slice: RG_FAC_1_RB:*/ +/*! Rank gradient factor for set 1 red/blue */ +#define MRV_DPCC_RG_FAC_1_RB +#define MRV_DPCC_RG_FAC_1_RB_MASK 0x00003F00U +#define MRV_DPCC_RG_FAC_1_RB_SHIFT 8U +/*! Slice: RG_FAC_1_G:*/ +/*! Rank gradient factor for set 1 green */ +#define MRV_DPCC_RG_FAC_1_G +#define MRV_DPCC_RG_FAC_1_G_MASK 0x0000003FU +#define MRV_DPCC_RG_FAC_1_G_SHIFT 0U +/*! Register: isp_dpcc_line_thresh_2: Line threshold set 2 (0x0000002c)*/ +/*! Slice: LINE_THR_2_RB:*/ +/*! line threshold for set 2 red/blue */ +#define MRV_DPCC_LINE_THR_2_RB +#define MRV_DPCC_LINE_THR_2_RB_MASK 0x0000FF00U +#define MRV_DPCC_LINE_THR_2_RB_SHIFT 8U +/*! Slice: LINE_THR_2_G:*/ +/*! line threshold for set 2 green */ +#define MRV_DPCC_LINE_THR_2_G +#define MRV_DPCC_LINE_THR_2_G_MASK 0x000000FFU +#define MRV_DPCC_LINE_THR_2_G_SHIFT 0U +/*! Register: isp_dpcc_line_mad_fac_2: Mean Absolute Difference (MAD) factor for Line check set 2 (0x00000030)*/ +/*! Slice: LINE_MAD_FAC_2_RB:*/ +/*! line MAD factor for set 2 red/blue */ +#define MRV_DPCC_LINE_MAD_FAC_2_RB +#define MRV_DPCC_LINE_MAD_FAC_2_RB_MASK 0x00003F00U +#define MRV_DPCC_LINE_MAD_FAC_2_RB_SHIFT 8U +/*! Slice: LINE_MAD_FAC_2_G:*/ +/*! line MAD factor for set 2 green */ +#define MRV_DPCC_LINE_MAD_FAC_2_G +#define MRV_DPCC_LINE_MAD_FAC_2_G_MASK 0x0000003FU +#define MRV_DPCC_LINE_MAD_FAC_2_G_SHIFT 0U +/*! Register: isp_dpcc_pg_fac_2: Peak gradient factor for set 2 (0x00000034)*/ +/*! Slice: PG_FAC_2_RB:*/ +/*! Peak gradient factor for set 2 red/blue */ +#define MRV_DPCC_PG_FAC_2_RB +#define MRV_DPCC_PG_FAC_2_RB_MASK 0x00003F00U +#define MRV_DPCC_PG_FAC_2_RB_SHIFT 8U +/*! Slice: PG_FAC_2_G:*/ +/*! Peak gradient factor for set 2 green */ +#define MRV_DPCC_PG_FAC_2_G +#define MRV_DPCC_PG_FAC_2_G_MASK 0x0000003FU +#define MRV_DPCC_PG_FAC_2_G_SHIFT 0U +/*! Register: isp_dpcc_rnd_thresh_2: Rank Neighbor Difference threshold for set 2 (0x00000038)*/ +/*! Slice: RND_THR_2_RB:*/ +/*! Rank Neighbor Difference threshold for set 2 red/blue */ +#define MRV_DPCC_RND_THR_2_RB +#define MRV_DPCC_RND_THR_2_RB_MASK 0x0000FF00U +#define MRV_DPCC_RND_THR_2_RB_SHIFT 8U +/*! Slice: RND_THR_2_G:*/ +/*! Rank Neighbor Difference threshold for set 2 green */ +#define MRV_DPCC_RND_THR_2_G +#define MRV_DPCC_RND_THR_2_G_MASK 0x000000FFU +#define MRV_DPCC_RND_THR_2_G_SHIFT 0U +/*! Register: isp_dpcc_rg_fac_2: Rank gradient factor for set 2 (0x0000003c)*/ +/*! Slice: RG_FAC_2_RB:*/ +/*! Rank gradient factor for set 2 red/blue */ +#define MRV_DPCC_RG_FAC_2_RB +#define MRV_DPCC_RG_FAC_2_RB_MASK 0x00003F00U +#define MRV_DPCC_RG_FAC_2_RB_SHIFT 8U +/*! Slice: RG_FAC_2_G:*/ +/*! Rank gradient factor for set 2 green */ +#define MRV_DPCC_RG_FAC_2_G +#define MRV_DPCC_RG_FAC_2_G_MASK 0x0000003FU +#define MRV_DPCC_RG_FAC_2_G_SHIFT 0U +/*! Register: isp_dpcc_line_thresh_3: Line threshold set 3 (0x00000040)*/ +/*! Slice: LINE_THR_3_RB:*/ +/*! line threshold for set 3 red/blue */ +#define MRV_DPCC_LINE_THR_3_RB +#define MRV_DPCC_LINE_THR_3_RB_MASK 0x0000FF00U +#define MRV_DPCC_LINE_THR_3_RB_SHIFT 8U +/*! Slice: LINE_THR_3_G:*/ +/*! line threshold for set 3 green */ +#define MRV_DPCC_LINE_THR_3_G +#define MRV_DPCC_LINE_THR_3_G_MASK 0x000000FFU +#define MRV_DPCC_LINE_THR_3_G_SHIFT 0U +/*! Register: isp_dpcc_line_mad_fac_3: Mean Absolute Difference (MAD) factor for Line check set 3 (0x00000044)*/ +/*! Slice: LINE_MAD_FAC_3_RB:*/ +/*! line MAD factor for set 3 red/blue */ +#define MRV_DPCC_LINE_MAD_FAC_3_RB +#define MRV_DPCC_LINE_MAD_FAC_3_RB_MASK 0x00003F00U +#define MRV_DPCC_LINE_MAD_FAC_3_RB_SHIFT 8U +/*! Slice: LINE_MAD_FAC_3_G:*/ +/*! line MAD factor for set 3 green */ +#define MRV_DPCC_LINE_MAD_FAC_3_G +#define MRV_DPCC_LINE_MAD_FAC_3_G_MASK 0x0000003FU +#define MRV_DPCC_LINE_MAD_FAC_3_G_SHIFT 0U +/*! Register: isp_dpcc_pg_fac_3: Peak gradient factor for set 3 (0x00000048)*/ +/*! Slice: PG_FAC_3_RB:*/ +/*! Peak gradient factor for set 3 red/blue */ +#define MRV_DPCC_PG_FAC_3_RB +#define MRV_DPCC_PG_FAC_3_RB_MASK 0x00003F00U +#define MRV_DPCC_PG_FAC_3_RB_SHIFT 8U +/*! Slice: PG_FAC_3_G:*/ +/*! Peak gradient factor for set 3 green */ +#define MRV_DPCC_PG_FAC_3_G +#define MRV_DPCC_PG_FAC_3_G_MASK 0x0000003FU +#define MRV_DPCC_PG_FAC_3_G_SHIFT 0U +/*! Register: isp_dpcc_rnd_thresh_3: Rank Neighbor Difference threshold for set 3 (0x0000004c)*/ +/*! Slice: RND_THR_3_RB:*/ +/*! Rank Neighbor Difference threshold for set 3 red/blue */ +#define MRV_DPCC_RND_THR_3_RB +#define MRV_DPCC_RND_THR_3_RB_MASK 0x0000FF00U +#define MRV_DPCC_RND_THR_3_RB_SHIFT 8U +/*! Slice: RND_THR_3_G:*/ +/*! Rank Neighbor Difference threshold for set 3 green */ +#define MRV_DPCC_RND_THR_3_G +#define MRV_DPCC_RND_THR_3_G_MASK 0x000000FFU +#define MRV_DPCC_RND_THR_3_G_SHIFT 0U +/*! Register: isp_dpcc_rg_fac_3: Rank gradient factor for set 3 (0x00000050)*/ +/*! Slice: RG_FAC_3_RB:*/ +/*! Rank gradient factor for set 3 red/blue */ +#define MRV_DPCC_RG_FAC_3_RB +#define MRV_DPCC_RG_FAC_3_RB_MASK 0x00003F00U +#define MRV_DPCC_RG_FAC_3_RB_SHIFT 8U +/*! Slice: RG_FAC_3_G:*/ +/*! Rank gradient factor for set 3 green */ +#define MRV_DPCC_RG_FAC_3_G +#define MRV_DPCC_RG_FAC_3_G_MASK 0x0000003FU +#define MRV_DPCC_RG_FAC_3_G_SHIFT 0U +/*! Register: isp_dpcc_ro_limits: Rank Order Limits (0x00000054)*/ +/*! Slice: RO_LIM_3_RB:*/ +/*! Rank order limit for set 3 red/blue */ +#define MRV_DPCC_RO_LIM_3_RB +#define MRV_DPCC_RO_LIM_3_RB_MASK 0x00000C00U +#define MRV_DPCC_RO_LIM_3_RB_SHIFT 10U +/*! Slice: RO_LIM_3_G:*/ +/*! Rank order limit for set 3 green */ +#define MRV_DPCC_RO_LIM_3_G +#define MRV_DPCC_RO_LIM_3_G_MASK 0x00000300U +#define MRV_DPCC_RO_LIM_3_G_SHIFT 8U +/*! Slice: RO_LIM_2_RB:*/ +/*! Rank order limit for set 2 red/blue */ +#define MRV_DPCC_RO_LIM_2_RB +#define MRV_DPCC_RO_LIM_2_RB_MASK 0x000000C0U +#define MRV_DPCC_RO_LIM_2_RB_SHIFT 6U +/*! Slice: RO_LIM_2_G:*/ +/*! Rank order limit for set 2 green */ +#define MRV_DPCC_RO_LIM_2_G +#define MRV_DPCC_RO_LIM_2_G_MASK 0x00000030U +#define MRV_DPCC_RO_LIM_2_G_SHIFT 4U +/*! Slice: RO_LIM_1_RB:*/ +/*! Rank order limit for set 1 red/blue */ +#define MRV_DPCC_RO_LIM_1_RB +#define MRV_DPCC_RO_LIM_1_RB_MASK 0x0000000CU +#define MRV_DPCC_RO_LIM_1_RB_SHIFT 2U +/*! Slice: RO_LIM_1_G:*/ +/*! Rank order limit for set 1 green */ +#define MRV_DPCC_RO_LIM_1_G +#define MRV_DPCC_RO_LIM_1_G_MASK 0x00000003U +#define MRV_DPCC_RO_LIM_1_G_SHIFT 0U +/*! Register: isp_dpcc_rnd_offs: Differential Rank Offsets for Rank Neighbor Difference (0x00000058)*/ +/*! Slice: RND_OFFS_3_RB:*/ +/*! Rank Offset to Neighbor for set 3 red/blue */ +#define MRV_DPCC_RND_OFFS_3_RB +#define MRV_DPCC_RND_OFFS_3_RB_MASK 0x00000C00U +#define MRV_DPCC_RND_OFFS_3_RB_SHIFT 10U +/*! Slice: RND_OFFS_3_G:*/ +/*! Rank Offset to Neighbor for set 3 green */ +#define MRV_DPCC_RND_OFFS_3_G +#define MRV_DPCC_RND_OFFS_3_G_MASK 0x00000300U +#define MRV_DPCC_RND_OFFS_3_G_SHIFT 8U +/*! Slice: RND_OFFS_2_RB:*/ +/*! Rank Offset to Neighbor for set 2 red/blue */ +#define MRV_DPCC_RND_OFFS_2_RB +#define MRV_DPCC_RND_OFFS_2_RB_MASK 0x000000C0U +#define MRV_DPCC_RND_OFFS_2_RB_SHIFT 6U +/*! Slice: RND_OFFS_2_G:*/ +/*! Rank Offset to Neighbor for set 2 green */ +#define MRV_DPCC_RND_OFFS_2_G +#define MRV_DPCC_RND_OFFS_2_G_MASK 0x00000030U +#define MRV_DPCC_RND_OFFS_2_G_SHIFT 4U +/*! Slice: RND_OFFS_1_RB:*/ +/*! Rank Offset to Neighbor for set 1 red/blue */ +#define MRV_DPCC_RND_OFFS_1_RB +#define MRV_DPCC_RND_OFFS_1_RB_MASK 0x0000000CU +#define MRV_DPCC_RND_OFFS_1_RB_SHIFT 2U +/*! Slice: RND_OFFS_1_G:*/ +/*! Rank Offset to Neighbor for set 1 green */ +#define MRV_DPCC_RND_OFFS_1_G +#define MRV_DPCC_RND_OFFS_1_G_MASK 0x00000003U +#define MRV_DPCC_RND_OFFS_1_G_SHIFT 0U +/*! Register: isp_dpcc_bpt_ctrl: bad pixel table settings (0x0000005c)*/ +/*! Slice: BPT_RB_3x3:*/ +/*! 1: if BPT active red/blue 9 pixel (3x3) output median */ +/* 0: if BPT active red/blue 4 or 5 pixel output median *Default**/ +#define MRV_DPCC_BPT_RB_3X3 +#define MRV_DPCC_BPT_RB_3X3_MASK 0x00000800U +#define MRV_DPCC_BPT_RB_3X3_SHIFT 11U +/*! Slice: BPT_G_3x3:*/ +/*! 1: if BPT active green 9 pixel (3x3) output median */ +/* 0: if BPT active green 4 or 5 pixel output median *Default**/ +#define MRV_DPCC_BPT_G_3X3 +#define MRV_DPCC_BPT_G_3X3_MASK 0x00000400U +#define MRV_DPCC_BPT_G_3X3_SHIFT 10U +/*! Slice: BPT_INCL_RB_CENTER:*/ +/*! 1: if BPT active include center pixel for red/blue output median 2x2+1 */ +/* 0: if BPT active do not include center pixel for red/blue output median 2x2 *Default**/ +#define MRV_DPCC_BPT_INCL_RB_CENTER +#define MRV_DPCC_BPT_INCL_RB_CENTER_MASK 0x00000200U +#define MRV_DPCC_BPT_INCL_RB_CENTER_SHIFT 9U +/*! Slice: BPT_INCL_GREEN_CENTER:*/ +/*! 1: if BPT active include center pixel for green output median 2x2+1 */ +/* 0: if BPT active do not include center pixel for green output median 2x2 *Default**/ +#define MRV_DPCC_BPT_INCL_GREEN_CENTER +#define MRV_DPCC_BPT_INCL_GREEN_CENTER_MASK 0x00000100U +#define MRV_DPCC_BPT_INCL_GREEN_CENTER_SHIFT 8U +/*! Slice: BPT_USE_FIX_SET:*/ +/*! 1: for BPT write use hard coded methods set */ +/* 0: for BPT write do not use hard coded methods set *Default**/ +#define MRV_DPCC_BPT_USE_FIX_SET +#define MRV_DPCC_BPT_USE_FIX_SET_MASK 0x00000080U +#define MRV_DPCC_BPT_USE_FIX_SET_SHIFT 7U +/*! Slice: BPT_USE_SET_3:*/ +/*! 1: for BPT write use methods set 3 */ +/* 0: for BPT write do not use methods set 3 *Default**/ +#define MRV_DPCC_BPT_USE_SET_3 +#define MRV_DPCC_BPT_USE_SET_3_MASK 0x00000040U +#define MRV_DPCC_BPT_USE_SET_3_SHIFT 6U +/*! Slice: BPT_USE_SET_2:*/ +/*! 1: for BPT write use methods set 2 */ +/* 0: for BPT write do not use methods set 2 *Default**/ +#define MRV_DPCC_BPT_USE_SET_2 +#define MRV_DPCC_BPT_USE_SET_2_MASK 0x00000020U +#define MRV_DPCC_BPT_USE_SET_2_SHIFT 5U +/*! Slice: BPT_USE_SET_1:*/ +/*! 1: for BPT write use methods set 1 */ +/* 0: for BPT write do not use methods set 1 *Default**/ +#define MRV_DPCC_BPT_USE_SET_1 +#define MRV_DPCC_BPT_USE_SET_1_MASK 0x00000010U +#define MRV_DPCC_BPT_USE_SET_1_SHIFT 4U +/*! Slice: bpt_cor_en:*/ +/*! table based correction enable */ +/* 1: table based correction is enabled */ +/* 0: table based correction is disabled */ +#define MRV_DPCC_BPT_COR_EN +#define MRV_DPCC_BPT_COR_EN_MASK 0x00000002U +#define MRV_DPCC_BPT_COR_EN_SHIFT 1U +/*! Slice: bpt_det_en:*/ +/*! Bad pixel detection write enable */ +/* 1: bad pixel detection write to memory is enabled */ +/* 0: bad pixel detection write to memory is disabled */ +#define MRV_DPCC_BPT_DET_EN +#define MRV_DPCC_BPT_DET_EN_MASK 0x00000001U +#define MRV_DPCC_BPT_DET_EN_SHIFT 0U +/*! Register: isp_dpcc_bpt_number: Number of entries for bad pixel table (table based correction) (0x00000060)*/ +/*! Slice: bp_number:*/ +/*! Number of current Bad Pixel entries in bad pixel table (BPT)*/ +#define MRV_DPCC_BP_NUMBER +#define MRV_DPCC_BP_NUMBER_MASK 0x00000FFFU +#define MRV_DPCC_BP_NUMBER_SHIFT 0U +/*! Register: isp_dpcc_bpt_addr: TABLE Start Address for table-based correction algorithm (0x00000064)*/ +/*! Slice: bp_table_addr:*/ +/*! Table RAM start address for read or write operations. The address counter is incremented at each read or write access to the data register (auto-increment mechanism).*/ +#define MRV_DPCC_BP_TABLE_ADDR +#define MRV_DPCC_BP_TABLE_ADDR_MASK 0x000007FFU +#define MRV_DPCC_BP_TABLE_ADDR_SHIFT 0U +/*! Register: isp_dpcc_bpt_data: TABLE DATA register for read and write access of table RAM (0x00000068)*/ +/*! Slice: bpt_v_addr:*/ +/*! Bad Pixel vertical address (pixel position)*/ +#define MRV_DPCC_BPT_V_ADDR +#define MRV_DPCC_BPT_V_ADDR_MASK 0x0FFF0000U +#define MRV_DPCC_BPT_V_ADDR_SHIFT 16U +/*! Slice: bpt_h_addr:*/ +/*! Bad Pixel horizontal address (pixel position)*/ +#define MRV_DPCC_BPT_H_ADDR +#define MRV_DPCC_BPT_H_ADDR_MASK 0x00001FFFU +#define MRV_DPCC_BPT_H_ADDR_SHIFT 0U +/*! Register: isp_wdr_ctrl: Control Bits for Wide Dynamic Range Unit (0x00000000)*/ +/*! Slice: WDR_RGB_FACTOR:*/ +/*! rgb_factor defines how much influence the RGBmax approach has in comparison to Y. The illumination reference Iref is calculated according to the following formula:*/ +/* Iref = (WDR_RGB_FACTOR * RGBYmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */ +/* So, rgb_factor = 0 means that the standard approach is used. Use of this factor requires that Iref has been selected, see WDR_USE_IREF.*/ +/* Value range of rgb_factor: 0...8 */ +#define MRV_WDR_RGB_FACTOR +#define MRV_WDR_RGB_FACTOR_MASK 0x00000F00U +#define MRV_WDR_RGB_FACTOR_SHIFT 8U +/*! Slice: WDR_DISABLE_TRANSIENT:*/ +/*! 1: disable transient between Y and RGBY_max */ +/* 0: calculate transient between Y and RGBY_max (for noise reduction) *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#define MRV_WDR_DISABLE_TRANSIENT +#define MRV_WDR_DISABLE_TRANSIENT_MASK 0x00000040U +#define MRV_WDR_DISABLE_TRANSIENT_SHIFT 6U +/*! Slice: WDR_USE_RGB7_8:*/ +/*! 1: decrease RGBmax by 7/8 (for noise reduction)*/ +/* 0: do not modify RGBmax *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#define MRV_WDR_USE_RGB7_8 +#define MRV_WDR_USE_RGB7_8_MASK 0x00000020U +#define MRV_WDR_USE_RGB7_8_SHIFT 5U +/*! Slice: WDR_USE_Y9_8:*/ +/*! 1: use R G B and Y*9/8 for maximum value calculation (for noise reduction)*/ +/* 0: only use R G B for maximum value calculation (RGBYmax approach) *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#define MRV_WDR_USE_Y9_8 +#define MRV_WDR_USE_Y9_8_MASK 0x00000010U +#define MRV_WDR_USE_Y9_8_SHIFT 4U +/*! Slice: WDR_USE_IREF:*/ +/*! 1: use Iref (Illumination reference) instead of Y for ToneMapping and Gain calculation */ +/* 0: use Y for ToneMapping and Gain calculation *Default**/ +/* Iref is calculated according to the following formula:*/ +/* Iref = (WDR_RGB_FACTOR * RGBmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */ +#define MRV_WDR_USE_IREF +#define MRV_WDR_USE_IREF_MASK 0x00000008U +#define MRV_WDR_USE_IREF_SHIFT 3U +/*! Slice: WDR_CR_MAPPING_DISABLE:*/ +/*! 1: disable (bypass) Chrominance Mapping */ +/* 0: enable Chrominance Mapping *Default**/ +/* requires that Luminance/chrominance color space has been selected */ +#define MRV_WDR_CR_MAPPING_DISABLE +#define MRV_WDR_CR_MAPPING_DISABLE_MASK 0x00000004U +#define MRV_WDR_CR_MAPPING_DISABLE_SHIFT 2U +/*! Slice: WDR_COLOR_SPACE_SELECT:*/ +/*! 1: R, G, B color space */ +/* 0: Luminance/Chrominance color space *Default**/ +#define MRV_WDR_COLOR_SPACE_SELECT +#define MRV_WDR_COLOR_SPACE_SELECT_MASK 0x00000002U +#define MRV_WDR_COLOR_SPACE_SELECT_SHIFT 1U +/*! Slice: WDR_ENABLE:*/ +/*! 1: enable WDR */ +/* 0: bypass WDR *Default**/ +#define MRV_WDR_ENABLE +#define MRV_WDR_ENABLE_MASK 0x00000001U +#define MRV_WDR_ENABLE_SHIFT 0U +/*! Register: isp_wdr_tonecurve_1: Tone Curve sample points dYn definition (part 1) (0x00000004)*/ +/*! Slice: WDR_dY8:*/ +/*! Tone curve sample point definition dY8 on the horizontal axis (input)*/ +#define MRV_WDR_DY8 +#define MRV_WDR_DY8_MASK 0x70000000U +#define MRV_WDR_DY8_SHIFT 28U +/*! Slice: WDR_dY7:*/ +/*! Tone curve sample point definition dY7 on the horizontal axis (input)*/ +#define MRV_WDR_DY7 +#define MRV_WDR_DY7_MASK 0x07000000U +#define MRV_WDR_DY7_SHIFT 24U +/*! Slice: WDR_dY6:*/ +/*! Tone curve sample point definition dY6 on the horizontal axis (input)*/ +#define MRV_WDR_DY6 +#define MRV_WDR_DY6_MASK 0x00700000U +#define MRV_WDR_DY6_SHIFT 20U +/*! Slice: WDR_dY5:*/ +/*! Tone curve sample point definition dY5 on the horizontal axis (input)*/ +#define MRV_WDR_DY5 +#define MRV_WDR_DY5_MASK 0x00070000U +#define MRV_WDR_DY5_SHIFT 16U +/*! Slice: WDR_dY4:*/ +/*! Tone curve sample point definition dY4 on the horizontal axis (input)*/ +#define MRV_WDR_DY4 +#define MRV_WDR_DY4_MASK 0x00007000U +#define MRV_WDR_DY4_SHIFT 12U +/*! Slice: WDR_dY3:*/ +/*! Tone curve sample point definition dY3 on the horizontal axis (input)*/ +#define MRV_WDR_DY3 +#define MRV_WDR_DY3_MASK 0x00000700U +#define MRV_WDR_DY3_SHIFT 8U +/*! Slice: WDR_dY2:*/ +/*! Tone curve sample point definition dY2 on the horizontal axis (input)*/ +#define MRV_WDR_DY2 +#define MRV_WDR_DY2_MASK 0x00000070U +#define MRV_WDR_DY2_SHIFT 4U +/*! Slice: WDR_dY1:*/ +/*! Tone curve sample point definition dY1 on the horizontal axis (input)*/ +#define MRV_WDR_DY1 +#define MRV_WDR_DY1_MASK 0x00000007U +#define MRV_WDR_DY1_SHIFT 0U +/*! Register: isp_wdr_tonecurve_2: Tone Curve sample points dYn definition (part 2) (0x00000008)*/ +/*! Slice: WDR_dY16:*/ +/*! Tone curve sample point definition dY16 on the horizontal axis (input)*/ +#define MRV_WDR_DY16 +#define MRV_WDR_DY16_MASK 0x70000000U +#define MRV_WDR_DY16_SHIFT 28U +/*! Slice: WDR_dY15:*/ +/*! Tone curve sample point definition dY15 on the horizontal axis (input)*/ +#define MRV_WDR_DY15 +#define MRV_WDR_DY15_MASK 0x07000000U +#define MRV_WDR_DY15_SHIFT 24U +/*! Slice: WDR_dY14:*/ +/*! Tone curve sample point definition dY14 on the horizontal axis (input)*/ +#define MRV_WDR_DY14 +#define MRV_WDR_DY14_MASK 0x00700000U +#define MRV_WDR_DY14_SHIFT 20U +/*! Slice: WDR_dY13:*/ +/*! Tone curve sample point definition dY13 on the horizontal axis (input)*/ +#define MRV_WDR_DY13 +#define MRV_WDR_DY13_MASK 0x00070000U +#define MRV_WDR_DY13_SHIFT 16U +/*! Slice: WDR_dY12:*/ +/*! Tone curve sample point definition dY12 on the horizontal axis (input)*/ +#define MRV_WDR_DY12 +#define MRV_WDR_DY12_MASK 0x00007000U +#define MRV_WDR_DY12_SHIFT 12U +/*! Slice: WDR_dY11:*/ +/*! Tone curve sample point definition dY11 on the horizontal axis (input)*/ +#define MRV_WDR_DY11 +#define MRV_WDR_DY11_MASK 0x00000700U +#define MRV_WDR_DY11_SHIFT 8U +/*! Slice: WDR_dY10:*/ +/*! Tone curve sample point definition dY10 on the horizontal axis (input)*/ +#define MRV_WDR_DY10 +#define MRV_WDR_DY10_MASK 0x00000070U +#define MRV_WDR_DY10_SHIFT 4U +/*! Slice: WDR_dY9:*/ +/*! Tone curve sample point definition dY9 on the horizontal axis (input)*/ +#define MRV_WDR_DY9 +#define MRV_WDR_DY9_MASK 0x00000007U +#define MRV_WDR_DY9_SHIFT 0U +/*! Register: isp_wdr_tonecurve_3: Tone Curve sample points dYn definition (part 3) (0x0000000c)*/ +/*! Slice: WDR_dY24:*/ +/*! Tone curve sample point definition dY24 on the horizontal axis (input)*/ +#define MRV_WDR_DY24 +#define MRV_WDR_DY24_MASK 0x70000000U +#define MRV_WDR_DY24_SHIFT 28U +/*! Slice: WDR_dY23:*/ +/*! Tone curve sample point definition dY23 on the horizontal axis (input)*/ +#define MRV_WDR_DY23 +#define MRV_WDR_DY23_MASK 0x07000000U +#define MRV_WDR_DY23_SHIFT 24U +/*! Slice: WDR_dY22:*/ +/*! Tone curve sample point definition dY22 on the horizontal axis (input)*/ +#define MRV_WDR_DY22 +#define MRV_WDR_DY22_MASK 0x00700000U +#define MRV_WDR_DY22_SHIFT 20U +/*! Slice: WDR_dY21:*/ +/*! Tone curve sample point definition dY21 on the horizontal axis (input)*/ +#define MRV_WDR_DY21 +#define MRV_WDR_DY21_MASK 0x00070000U +#define MRV_WDR_DY21_SHIFT 16U +/*! Slice: WDR_dY20:*/ +/*! Tone curve sample point definition dY20 on the horizontal axis (input)*/ +#define MRV_WDR_DY20 +#define MRV_WDR_DY20_MASK 0x00007000U +#define MRV_WDR_DY20_SHIFT 12U +/*! Slice: WDR_dY19:*/ +/*! Tone curve sample point definition dY19 on the horizontal axis (input)*/ +#define MRV_WDR_DY19 +#define MRV_WDR_DY19_MASK 0x00000700U +#define MRV_WDR_DY19_SHIFT 8U +/*! Slice: WDR_dY18:*/ +/*! Tone curve sample point definition dY18 on the horizontal axis (input)*/ +#define MRV_WDR_DY18 +#define MRV_WDR_DY18_MASK 0x00000070U +#define MRV_WDR_DY18_SHIFT 4U +/*! Slice: WDR_dY17:*/ +/*! Tone curve sample point definition dY17 on the horizontal axis (input)*/ +#define MRV_WDR_DY17 +#define MRV_WDR_DY17_MASK 0x00000007U +#define MRV_WDR_DY17_SHIFT 0U +/*! Register: isp_wdr_tonecurve_4: Tone Curve sample points dYn definition (part 4) (0x00000010)*/ +/*! Slice: WDR_dY32:*/ +/*! Tone curve sample point definition dY32 on the horizontal axis (input)*/ +#define MRV_WDR_DY32 +#define MRV_WDR_DY32_MASK 0x70000000U +#define MRV_WDR_DY32_SHIFT 28U +/*! Slice: WDR_dY31:*/ +/*! Tone curve sample point definition dY31 on the horizontal axis (input)*/ +#define MRV_WDR_DY31 +#define MRV_WDR_DY31_MASK 0x07000000U +#define MRV_WDR_DY31_SHIFT 24U +/*! Slice: WDR_dY30:*/ +/*! Tone curve sample point definition dY30 on the horizontal axis (input)*/ +#define MRV_WDR_DY30 +#define MRV_WDR_DY30_MASK 0x00700000U +#define MRV_WDR_DY30_SHIFT 20U +/*! Slice: WDR_dY29:*/ +/*! Tone curve sample point definition dY29 on the horizontal axis (input)*/ +#define MRV_WDR_DY29 +#define MRV_WDR_DY29_MASK 0x00070000U +#define MRV_WDR_DY29_SHIFT 16U +/*! Slice: WDR_dY28:*/ +/*! Tone curve sample point definition dY28 on the horizontal axis (input)*/ +#define MRV_WDR_DY28 +#define MRV_WDR_DY28_MASK 0x00007000U +#define MRV_WDR_DY28_SHIFT 12U +/*! Slice: WDR_dY27:*/ +/*! Tone curve sample point definition dY27 on the horizontal axis (input)*/ +#define MRV_WDR_DY27 +#define MRV_WDR_DY27_MASK 0x00000700U +#define MRV_WDR_DY27_SHIFT 8U +/*! Slice: WDR_dY26:*/ +/*! Tone curve sample point definition dY26 on the horizontal axis (input)*/ +#define MRV_WDR_DY26 +#define MRV_WDR_DY26_MASK 0x00000070U +#define MRV_WDR_DY26_SHIFT 4U +/*! Slice: WDR_dY25:*/ +/*! Tone curve sample point definition dY25 on the horizontal axis (input)*/ +#define MRV_WDR_DY25 +#define MRV_WDR_DY25_MASK 0x00000007U +#define MRV_WDR_DY25_SHIFT 0U +/*! Register array: isp_wdr_tonecurve_ym: Tonemapping curve coefficient Ym_ (0x0028 + n*0x4 (n=0..32))*/ +/*! Slice: tonecurve_ym_n:*/ +/* Tone curve value definition y-axis (output) of WDR unit */ +#define MRV_WDR_TONECURVE_YM_N +#define MRV_WDR_TONECURVE_YM_N_MASK 0x00001FFFU +#define MRV_WDR_TONECURVE_YM_N_SHIFT 0U +/*! Register: isp_wdr_offset: Offset values for RGB path (0x00000098)*/ +/*! Slice: LUM_OFFSET:*/ +/*! Luminance Offset value (a) for RGB operation mode */ +/* unsigned 12 bit value */ +#define MRV_WDR_LUM_OFFSET +#define MRV_WDR_LUM_OFFSET_MASK 0x0FFF0000U +#define MRV_WDR_LUM_OFFSET_SHIFT 16U +/*! Slice: RGB_OFFSET:*/ +/*! RGB Offset value (b) for RGB operation mode */ +/* unsigned 12 bit value */ +#define MRV_WDR_RGB_OFFSET +#define MRV_WDR_RGB_OFFSET_MASK 0x00000FFFU +#define MRV_WDR_RGB_OFFSET_SHIFT 0U +/*! Register: isp_wdr_deltamin: DeltaMin Threshold and Strength factor (0x0000009c)*/ +/*! Slice: DMIN_STRENGTH:*/ +/*! strength factor for DMIN */ +/* unsigned 5 bit value, range 0x00...0x10 */ +#define MRV_WDR_DMIN_STRENGTH +#define MRV_WDR_DMIN_STRENGTH_MASK 0x001F0000U +#define MRV_WDR_DMIN_STRENGTH_SHIFT 16U +/*! Slice: DMIN_THRESH:*/ +/*! Lower threshold for deltaMin value */ +/* unsigned 12 bit value */ +#define MRV_WDR_DMIN_THRESH +#define MRV_WDR_DMIN_THRESH_MASK 0x00000FFFU +#define MRV_WDR_DMIN_THRESH_SHIFT 0U +/*! Register: isp_wdr_tonecurve_1_shd: Tone Curve sample points dYn definition shadow register (part 1) (0x000000a0)*/ +/*! Slice: WDR_dY8:*/ +/*! Tone curve sample point definition dY8 on the horizontal axis (input)*/ +#define MRV_WDR_DY8 +#define MRV_WDR_DY8_MASK 0x70000000U +#define MRV_WDR_DY8_SHIFT 28U +/*! Slice: WDR_dY7:*/ +/*! Tone curve sample point definition dY7 on the horizontal axis (input)*/ +#define MRV_WDR_DY7 +#define MRV_WDR_DY7_MASK 0x07000000U +#define MRV_WDR_DY7_SHIFT 24U +/*! Slice: WDR_dY6:*/ +/*! Tone curve sample point definition dY6 on the horizontal axis (input)*/ +#define MRV_WDR_DY6 +#define MRV_WDR_DY6_MASK 0x00700000U +#define MRV_WDR_DY6_SHIFT 20U +/*! Slice: WDR_dY5:*/ +/*! Tone curve sample point definition dY5 on the horizontal axis (input)*/ +#define MRV_WDR_DY5 +#define MRV_WDR_DY5_MASK 0x00070000U +#define MRV_WDR_DY5_SHIFT 16U +/*! Slice: WDR_dY4:*/ +/*! Tone curve sample point definition dY4 on the horizontal axis (input)*/ +#define MRV_WDR_DY4 +#define MRV_WDR_DY4_MASK 0x00007000U +#define MRV_WDR_DY4_SHIFT 12U +/*! Slice: WDR_dY3:*/ +/*! Tone curve sample point definition dY3 on the horizontal axis (input)*/ +#define MRV_WDR_DY3 +#define MRV_WDR_DY3_MASK 0x00000700U +#define MRV_WDR_DY3_SHIFT 8U +/*! Slice: WDR_dY2:*/ +/*! Tone curve sample point definition dY2 on the horizontal axis (input)*/ +#define MRV_WDR_DY2 +#define MRV_WDR_DY2_MASK 0x00000070U +#define MRV_WDR_DY2_SHIFT 4U +/*! Slice: WDR_dY1:*/ +/*! Tone curve sample point definition dY1 on the horizontal axis (input)*/ +#define MRV_WDR_DY1 +#define MRV_WDR_DY1_MASK 0x00000007U +#define MRV_WDR_DY1_SHIFT 0U +/*! Register: isp_wdr_tonecurve_2_shd: Tone Curve sample points dYn definition shadow register (part 2) (0x000000a4)*/ +/*! Slice: WDR_dY16:*/ +/*! Tone curve sample point definition dY16 on the horizontal axis (input)*/ +#define MRV_WDR_DY16 +#define MRV_WDR_DY16_MASK 0x70000000U +#define MRV_WDR_DY16_SHIFT 28U +/*! Slice: WDR_dY15:*/ +/*! Tone curve sample point definition dY15 on the horizontal axis (input)*/ +#define MRV_WDR_DY15 +#define MRV_WDR_DY15_MASK 0x07000000U +#define MRV_WDR_DY15_SHIFT 24U +/*! Slice: WDR_dY14:*/ +/*! Tone curve sample point definition dY14 on the horizontal axis (input)*/ +#define MRV_WDR_DY14 +#define MRV_WDR_DY14_MASK 0x00700000U +#define MRV_WDR_DY14_SHIFT 20U +/*! Slice: WDR_dY13:*/ +/*! Tone curve sample point definition dY13 on the horizontal axis (input)*/ +#define MRV_WDR_DY13 +#define MRV_WDR_DY13_MASK 0x00070000U +#define MRV_WDR_DY13_SHIFT 16U +/*! Slice: WDR_dY12:*/ +/*! Tone curve sample point definition dY12 on the horizontal axis (input)*/ +#define MRV_WDR_DY12 +#define MRV_WDR_DY12_MASK 0x00007000U +#define MRV_WDR_DY12_SHIFT 12U +/*! Slice: WDR_dY11:*/ +/*! Tone curve sample point definition dY11 on the horizontal axis (input)*/ +#define MRV_WDR_DY11 +#define MRV_WDR_DY11_MASK 0x00000700U +#define MRV_WDR_DY11_SHIFT 8U +/*! Slice: WDR_dY10:*/ +/*! Tone curve sample point definition dY10 on the horizontal axis (input)*/ +#define MRV_WDR_DY10 +#define MRV_WDR_DY10_MASK 0x00000070U +#define MRV_WDR_DY10_SHIFT 4U +/*! Slice: WDR_dY9:*/ +/*! Tone curve sample point definition dY9 on the horizontal axis (input)*/ +#define MRV_WDR_DY9 +#define MRV_WDR_DY9_MASK 0x00000007U +#define MRV_WDR_DY9_SHIFT 0U +/*! Register: isp_wdr_tonecurve_3_shd: Tone Curve sample points dYn definition shadow register (part 3) (0x000000a8)*/ +/*! Slice: WDR_dY24:*/ +/*! Tone curve sample point definition dY24 on the horizontal axis (input)*/ +#define MRV_WDR_DY24 +#define MRV_WDR_DY24_MASK 0x70000000U +#define MRV_WDR_DY24_SHIFT 28U +/*! Slice: WDR_dY23:*/ +/*! Tone curve sample point definition dY23 on the horizontal axis (input)*/ +#define MRV_WDR_DY23 +#define MRV_WDR_DY23_MASK 0x07000000U +#define MRV_WDR_DY23_SHIFT 24U +/*! Slice: WDR_dY22:*/ +/*! Tone curve sample point definition dY22 on the horizontal axis (input)*/ +#define MRV_WDR_DY22 +#define MRV_WDR_DY22_MASK 0x00700000U +#define MRV_WDR_DY22_SHIFT 20U +/*! Slice: WDR_dY21:*/ +/*! Tone curve sample point definition dY21 on the horizontal axis (input)*/ +#define MRV_WDR_DY21 +#define MRV_WDR_DY21_MASK 0x00070000U +#define MRV_WDR_DY21_SHIFT 16U +/*! Slice: WDR_dY20:*/ +/*! Tone curve sample point definition dY20 on the horizontal axis (input)*/ +#define MRV_WDR_DY20 +#define MRV_WDR_DY20_MASK 0x00007000U +#define MRV_WDR_DY20_SHIFT 12U +/*! Slice: WDR_dY19:*/ +/*! Tone curve sample point definition dY19 on the horizontal axis (input)*/ +#define MRV_WDR_DY19 +#define MRV_WDR_DY19_MASK 0x00000700U +#define MRV_WDR_DY19_SHIFT 8U +/*! Slice: WDR_dY18:*/ +/*! Tone curve sample point definition dY18 on the horizontal axis (input)*/ +#define MRV_WDR_DY18 +#define MRV_WDR_DY18_MASK 0x00000070U +#define MRV_WDR_DY18_SHIFT 4U +/*! Slice: WDR_dY17:*/ +/*! Tone curve sample point definition dY17 on the horizontal axis (input)*/ +#define MRV_WDR_DY17 +#define MRV_WDR_DY17_MASK 0x00000007U +#define MRV_WDR_DY17_SHIFT 0U +/*! Register: isp_wdr_tonecurve_4_shd: Tone Curve sample points dYn definition shadow register(part 4) (0x000000ac)*/ +/*! Slice: WDR_dY32:*/ +/*! Tone curve sample point definition dY32 on the horizontal axis (input)*/ +#define MRV_WDR_DY32 +#define MRV_WDR_DY32_MASK 0x70000000U +#define MRV_WDR_DY32_SHIFT 28U +/*! Slice: WDR_dY31:*/ +/*! Tone curve sample point definition dY31 on the horizontal axis (input)*/ +#define MRV_WDR_DY31 +#define MRV_WDR_DY31_MASK 0x07000000U +#define MRV_WDR_DY31_SHIFT 24U +/*! Slice: WDR_dY30:*/ +/*! Tone curve sample point definition dY30 on the horizontal axis (input)*/ +#define MRV_WDR_DY30 +#define MRV_WDR_DY30_MASK 0x00700000U +#define MRV_WDR_DY30_SHIFT 20U +/*! Slice: WDR_dY29:*/ +/*! Tone curve sample point definition dY29 on the horizontal axis (input)*/ +#define MRV_WDR_DY29 +#define MRV_WDR_DY29_MASK 0x00070000U +#define MRV_WDR_DY29_SHIFT 16U +/*! Slice: WDR_dY28:*/ +/*! Tone curve sample point definition dY28 on the horizontal axis (input)*/ +#define MRV_WDR_DY28 +#define MRV_WDR_DY28_MASK 0x00007000U +#define MRV_WDR_DY28_SHIFT 12U +/*! Slice: WDR_dY27:*/ +/*! Tone curve sample point definition dY27 on the horizontal axis (input)*/ +#define MRV_WDR_DY27 +#define MRV_WDR_DY27_MASK 0x00000700U +#define MRV_WDR_DY27_SHIFT 8U +/*! Slice: WDR_dY26:*/ +/*! Tone curve sample point definition dY26 on the horizontal axis (input)*/ +#define MRV_WDR_DY26 +#define MRV_WDR_DY26_MASK 0x00000070U +#define MRV_WDR_DY26_SHIFT 4U +/*! Slice: WDR_dY25:*/ +/*! Tone curve sample point definition dY25 on the horizontal axis (input)*/ +#define MRV_WDR_DY25 +#define MRV_WDR_DY25_MASK 0x00000007U +#define MRV_WDR_DY25_SHIFT 0U +/*! Register array: isp_wdr_tonecurve_ym_shd: Tonemapping curve coefficient shadow register (0x0160 + n*0x4 (n=0..32))*/ +/*! Slice: tonecurve_ym_n_shd:*/ +/* Tone curve value definition y-axis (output) of WDR unit */ +/* shadow register.*/ +#define MRV_WDR_TONECURVE_YM_N_SHD +#define MRV_WDR_TONECURVE_YM_N_SHD_MASK 0x00001FFFU +#define MRV_WDR_TONECURVE_YM_N_SHD_SHIFT 0U +/*! Register: awb_meas_mode: AWB Measure Mode (0x00000000)*/ +/*! Slice: AWB_union_e5_and_e8:*/ +/*! unite ellipse 5 with ellipse 8. Accu and count for ellipse 8.*/ +#define ISP_AWB_UNION_E5_AND_E8 +#define ISP_AWB_UNION_E5_AND_E8_MASK 0x00000200U +#define ISP_AWB_UNION_E5_AND_E8_SHIFT 9U +/*! Slice: AWB_union_e5_and_e7:*/ +/*! unite ellipse 5 with ellipse 7. Accu and count for ellipse 7.*/ +#define ISP_AWB_UNION_E5_AND_E7 +#define ISP_AWB_UNION_E5_AND_E7_MASK 0x00000100U +#define ISP_AWB_UNION_E5_AND_E7_SHIFT 8U +/*! Slice: AWB_union_e5_and_e6:*/ +/*! unite ellipse 5 with ellipse 6. Accu and count for ellipse 6.*/ +#define ISP_AWB_UNION_E5_AND_E6 +#define ISP_AWB_UNION_E5_AND_E6_MASK 0x00000080U +#define ISP_AWB_UNION_E5_AND_E6_SHIFT 7U +/*! Slice: AWB_union_e1_and_e4:*/ +/*! unite ellipse 1 with ellipse 4. Accu and count for ellipse 4.*/ +#define ISP_AWB_UNION_E1_AND_E4 +#define ISP_AWB_UNION_E1_AND_E4_MASK 0x00000040U +#define ISP_AWB_UNION_E1_AND_E4_SHIFT 6U +/*! Slice: AWB_union_e1_and_e3:*/ +/*! unite ellipse 1 with ellipse 3. Accu and count for ellipse 3.*/ +#define ISP_AWB_UNION_E1_AND_E3 +#define ISP_AWB_UNION_E1_AND_E3_MASK 0x00000020U +#define ISP_AWB_UNION_E1_AND_E3_SHIFT 5U +/*! Slice: AWB_union_e1_and_e2:*/ +/*! unite ellipse 1 with ellipse 2. Accu and count for ellipse 2.*/ +#define ISP_AWB_UNION_E1_AND_E2 +#define ISP_AWB_UNION_E1_AND_E2_MASK 0x00000010U +#define ISP_AWB_UNION_E1_AND_E2_SHIFT 4U +/*! Slice: AWB_meas_chrom_switch:*/ +/*! Accumulates Q1 and Q2 chromaticies instead of R, G, B color signals. Results are written on AWB_ACCU registers as well.*/ +#define ISP_AWB_MEAS_CHROM_SWITCH +#define ISP_AWB_MEAS_CHROM_SWITCH_MASK 0x00000008U +#define ISP_AWB_MEAS_CHROM_SWITCH_SHIFT 3U +/*! Slice: AWB_meas_irq_enable:*/ +/*! AWB measure done IRQ enable.*/ +#define ISP_AWB_MEAS_IRQ_ENABLE +#define ISP_AWB_MEAS_IRQ_ENABLE_MASK 0x00000004U +#define ISP_AWB_MEAS_IRQ_ENABLE_SHIFT 2U +/*! Slice: AWB_pre_filt_en:*/ +/*! median pre filter enable.*/ +#define ISP_AWB_PRE_FILT_EN +#define ISP_AWB_PRE_FILT_EN_MASK 0x00000002U +#define ISP_AWB_PRE_FILT_EN_SHIFT 1U +/*! Slice: AWB_meas_en:*/ +/*! enable measure.*/ +#define ISP_AWB_MEAS_EN +#define ISP_AWB_MEAS_EN_MASK 0x00000001U +#define ISP_AWB_MEAS_EN_SHIFT 0U +/*! Register: awb_meas_h_offs: AWB window horizontal offset (0x00000004)*/ +/*! Slice: AWB_h_offset:*/ +/*! Horizontal offset in pixels.*/ +#define ISP_AWB_H_OFFSET +#define ISP_AWB_H_OFFSET_MASK 0x00001FFFU +#define ISP_AWB_H_OFFSET_SHIFT 0U +/*! Register: awb_meas_v_offs: AWB window vertical offset (0x00000008)*/ +/*! Slice: AWB_v_offset:*/ +/*! Vertical offset in pixels.*/ +#define ISP_AWB_V_OFFSET +#define ISP_AWB_V_OFFSET_MASK 0x00001FFFU +#define ISP_AWB_V_OFFSET_SHIFT 0U +/*! Register: awb_meas_h_size: Horizontal window size (0x0000000c)*/ +/*! Slice: AWB_h_size:*/ +/*! Horizontal size in pixels.*/ +#define ISP_AWB_H_SIZE +#define ISP_AWB_H_SIZE_MASK 0x00003FFFU +#define ISP_AWB_H_SIZE_SHIFT 0U +/*! Register: awb_meas_v_size: Vertical window size (0x00000010)*/ +/*! Slice: AWB_v_size:*/ +/*! Vertical size.*/ +#define ISP_AWB_V_SIZE +#define ISP_AWB_V_SIZE_MASK 0x00003FFFU +#define ISP_AWB_V_SIZE_SHIFT 0U +/*! Register: awb_meas_r_min_max: Min Max Compare Red (0x00000014)*/ +/*! Slice: r_max:*/ +/*! max red value */ +#define ISP_AWB_R_MAX +#define ISP_AWB_R_MAX_MASK 0x0000FF00U +#define ISP_AWB_R_MAX_SHIFT 8U +/*! Slice: r_min:*/ +/*! min red value */ +#define ISP_AWB_R_MIN +#define ISP_AWB_R_MIN_MASK 0x000000FFU +#define ISP_AWB_R_MIN_SHIFT 0U +/*! Register: awb_meas_g_min_max: Min Max Compare Green (0x00000018)*/ +/*! Slice: g_max:*/ +/*! max green value */ +#define ISP_AWB_G_MAX +#define ISP_AWB_G_MAX_MASK 0x0000FF00U +#define ISP_AWB_G_MAX_SHIFT 8U +/*! Slice: g_min:*/ +/*! min green value */ +#define ISP_AWB_G_MIN +#define ISP_AWB_G_MIN_MASK 0x000000FFU +#define ISP_AWB_G_MIN_SHIFT 0U +/*! Register: awb_meas_b_min_max: Min Max Compare Blue (0x0000001c)*/ +/*! Slice: b_max:*/ +/*! max blue value */ +#define ISP_AWB_B_MAX +#define ISP_AWB_B_MAX_MASK 0x0000FF00U +#define ISP_AWB_B_MAX_SHIFT 8U +/*! Slice: b_min:*/ +/*! min blue value */ +#define ISP_AWB_B_MIN +#define ISP_AWB_B_MIN_MASK 0x000000FFU +#define ISP_AWB_B_MIN_SHIFT 0U +/*! Register: awb_meas_divider_min: Min Compare Divider (0x00000020)*/ +/*! Slice: div_min:*/ +/*! min divider value unsigned integer with 10 fractional Bits range 0 to 0.999 */ +#define ISP_AWB_DIV_MIN +#define ISP_AWB_DIV_MIN_MASK 0x000003FFU +#define ISP_AWB_DIV_MIN_SHIFT 0U +/*! Register: awb_meas_csc_coeff_0: Color conversion coefficient 0 (0x00000024)*/ +/*! Slice: cc_coeff_0:*/ +/*! coefficient 0 for color space conversion */ +#define ISP_AWB_CC_COEFF_0 +#define ISP_AWB_CC_COEFF_0_MASK 0x000007FFU +#define ISP_AWB_CC_COEFF_0_SHIFT 0U +/*! Register: awb_meas_ellip1_cen_x: Ellipse 1 Center X (0x00000048)*/ +/*! Slice: ellip1_cen_x:*/ +/*! Ellipse 1 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#define ISP_AWB_ELLIP1_CEN_X +#define ISP_AWB_ELLIP1_CEN_X_MASK 0x000003FFU +#define ISP_AWB_ELLIP1_CEN_X_SHIFT 0U +/*! Register: awb_meas_ellip1_cen_y: Ellipse 1 Center Y (0x0000004c)*/ +/*! Slice: ellip1_cen_y:*/ +/*! Ellipse 1 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#define ISP_AWB_ELLIP1_CEN_Y +#define ISP_AWB_ELLIP1_CEN_Y_MASK 0x000003FFU +#define ISP_AWB_ELLIP1_CEN_Y_SHIFT 0U +/*! Register: awb_meas_ellip1_a1: Ellipse 1 coefficient a1 (0x00000088)*/ +/*! Slice: ellip1_a1:*/ +/*! Ellipse 1 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#define ISP_AWB_ELLIP1_A1 +#define ISP_AWB_ELLIP1_A1_MASK 0x00000FFFU +#define ISP_AWB_ELLIP1_A1_SHIFT 0U +/*! Register: awb_meas_ellip1_a2: Ellipse 1 coefficient a2 (0x0000008c)*/ +/*! Slice: ellip1_a2:*/ +/*! Ellipse 1 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#define ISP_AWB_ELLIP1_A2 +#define ISP_AWB_ELLIP1_A2_MASK 0x000001FFU +#define ISP_AWB_ELLIP1_A2_SHIFT 0U +/*! Register: awb_meas_ellip1_a3: Ellipse 1 coefficient a3 (0x00000090)*/ +/*! Slice: ellip1_a3:*/ +/*! Ellipse 1 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#define ISP_AWB_ELLIP1_A3 +#define ISP_AWB_ELLIP1_A3_MASK 0x00000FFFU +#define ISP_AWB_ELLIP1_A3_SHIFT 0U +/*! Register: awb_meas_ellip1_a4: Ellipse 1 coefficient a4 (0x00000094)*/ +/*! Slice: ellip1_a4:*/ +/*! Ellipse 1 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#define ISP_AWB_ELLIP1_A4 +#define ISP_AWB_ELLIP1_A4_MASK 0x000001FFU +#define ISP_AWB_ELLIP1_A4_SHIFT 0U +/*! Register: awb_meas_ellip1_rmax: Ellipse 1 r_max (0x00000108)*/ +/*! Slice: ellip1_rmax:*/ +/*! Ellipse 1 max radius square compare value */ +#define ISP_AWB_ELLIP1_RMAX +#define ISP_AWB_ELLIP1_RMAX_MASK 0x00FFFFFFU +#define ISP_AWB_ELLIP1_RMAX_SHIFT 0U +/*! Register: awb_meas_counter_1: AWB Counter 1 (0x00000128)*/ +/*! Slice: count_1:*/ +/*! counted Pixels of Ellipse 1 */ +#define ISP_AWB_COUNT_1 +#define ISP_AWB_COUNT_1_MASK 0x00FFFFFFU +#define ISP_AWB_COUNT_1_SHIFT 0U +/*! Register array: awb_meas_accu: AWB Accu Read (0x290 + n*0x4 (n=0..23))*/ +/*! Slice: read_accu:*/ +/* measured sum[34:3] of RGB values.*/ +#define ISP_AWB_READ_ACCU +#define ISP_AWB_READ_ACCU_MASK 0xFFFFFFFFU +#define ISP_AWB_READ_ACCU_SHIFT 0U +/*! Register: isp64_hist_ctrl: Histogram control (0x00000000)*/ +/*! Slice: hist_update_enable:*/ +/*! 0: automatic register update at end of measuement ot frame denied */ +/* 1: automatic register update at end of measuement ot frame enabled.*/ +#define MRV_HIST_UPDATE_ENABLE +#define MRV_HIST_UPDATE_ENABLE_MASK 0x00000001U +#define MRV_HIST_UPDATE_ENABLE_SHIFT 0U +/*! Register: isp64_hist_prop: Histogram properties (0x00000004)*/ +/*! Slice: channel_select:*/ +/*! select 1 out of max. 8 input channels */ +/* 7: channel 7 */ +/* 6: channel 6 */ +/* 5: channel 5 */ +/* 4: channel 4 */ +/* 3: channel 3 */ +/* 2: channel 2 */ +/* 1: channel 1 */ +/* 0: channel 0 */ +/* The channels might be RGB or Bayer channels. Each channel provides 3 subchannels for tranfer the RGB component data. However if the channel operates in bayer mode only subchannel 0 is used transferring the interleaved bayer pattern data. Check with top level specification to discover the channel type.*/ +#define MRV_HIST_CHANNEL_SELECT +#define MRV_HIST_CHANNEL_SELECT_MASK 0x00000038U +#define MRV_HIST_CHANNEL_SELECT_SHIFT 3U +/*! Slice: hist_mode:*/ +/*! histogram mode (RGB/Bayer)*/ +/* 7, 6: reserved */ +/* 5: bayer Gb histogram */ +/* 4: bayer B histogram */ +/* 3: bayer Gr histogram */ +/* 2: bayer R histogram */ +/* 1: Y/R/G/B histogram controlled via coefficients coeff_r/g/b */ +/* 0: disable, no measurements */ +/* With histogram mode 1 all three subchannels are used. Modes 2...5 use only th subchannel 0 which transfers the bayer pattern data. Check with top level specification to discover the channel type.*/ +#define MRV_HIST_MODE +#define MRV_HIST_MODE_MASK 0x00000007U +#define MRV_HIST_MODE_SHIFT 0U +/*! Register: isp64_hist_subsampling: Subsampling properties (0x00000008)*/ +/*! Slice: v_stepsize:*/ +/*! histogram veritcal predivider, process every (stepsize)th line, all other lines are skipped */ +/* RGB mode:*/ +/* 0: not allowed */ +/* 1: process every input line */ +/* 2: process every second line */ +/* 3: process every third input line */ +/* 4: process every fourth input line */ +/* ...*/ +/* 7FH: process every 127th line */ +/* Bayer mode:*/ +/* 0: not allowed */ +/* 1: process every second input line */ +/* 2: process every fourth line */ +/* 3: process every sixth input line */ +/* 4: process every eighth input line */ +/* ...*/ +/* 7FH: process every 254th line */ +/* In bayer mode vertical subsampling will start at the 1st input line which contain the bayer component selected in ISP64_HIST_PROP::hist_mode.*/ +#define MRV_HIST_V_STEPSIZE +#define MRV_HIST_V_STEPSIZE_MASK 0x7F000000U +#define MRV_HIST_V_STEPSIZE_SHIFT 24U +/*! Slice: h_step_inc:*/ +/*! horizontal subsampling step counter increment.*/ +/* In RGB mode the subsampling counter cnt is incremented by h_step_inc with every input pixel (cnt %= cnt + h_step_inc). A valid subsampling position is reached when cnt would result in a value %= 2^16. In this case the new counter value is cnt = cnt + h_step_inc - 2^16. For example if every incoming pixel shall be selected configure h_step_inc = 2^16.*/ +/* In Bayer mode the behaviour is similar but for the fact that cnt is only incremented for pixels which belong to the bayer component selected in ISP64_HIST_PROP::hist_mode.*/ +#define MRV_HIST_H_STEP_INC +#define MRV_HIST_H_STEP_INC_MASK 0x0001FFFFU +#define MRV_HIST_H_STEP_INC_SHIFT 0U +/*! Register: isp64_hist_coeff_r: Color conversion coefficient for red (0x0000000c)*/ +/*! Slice: coeff_r:*/ +/*! coefficient for red for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/ +#define MRV_HIST_COEFF_R +#define MRV_HIST_COEFF_R_MASK 0x000000FFU +#define MRV_HIST_COEFF_R_SHIFT 0U +/*! Register: isp64_hist_coeff_g: Color conversion coefficient for green (0x00000010)*/ +/*! Slice: coeff_g:*/ +/*! coefficient for green for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/ +#define MRV_HIST_COEFF_G +#define MRV_HIST_COEFF_G_MASK 0x000000FFU +#define MRV_HIST_COEFF_G_SHIFT 0U +/*! Register: isp64_hist_coeff_b: Color conversion coefficient for blue (0x00000014)*/ +/*! Slice: coeff_b:*/ +/*! coefficient for blue for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/ +#define MRV_HIST_COEFF_B +#define MRV_HIST_COEFF_B_MASK 0x000000FFU +#define MRV_HIST_COEFF_B_SHIFT 0U +/*! Register: isp64_hist_h_offs: Histogram window horizontal offset for first window of 25 sub-windows (0x00000018)*/ +/*! Slice: hist_h_offset:*/ +/*! Horizontal offset of first window in pixels.*/ +#define MRV_HIST_H_OFFSET +#define MRV_HIST_H_OFFSET_MASK 0x00001FFFU +#define MRV_HIST_H_OFFSET_SHIFT 0U +/*! Register: isp64_hist_v_offs: Histogram window vertical offset for first window of 25 sub-windows (0x0000001c)*/ +/*! Slice: hist_v_offset:*/ +/*! Vertical offset of first window in pixels.*/ +#define MRV_HIST_V_OFFSET +#define MRV_HIST_V_OFFSET_MASK 0x00001FFFU +#define MRV_HIST_V_OFFSET_SHIFT 0U +/*! Register: isp64_hist_h_size: Horizontal (sub-)window size (0x00000020)*/ +/*! Slice: hist_h_size:*/ +/*! Horizontal size in pixels of one sub-window.*/ +#define MRV_HIST_H_SIZE +#define MRV_HIST_H_SIZE_MASK 0x000007FFU +#define MRV_HIST_H_SIZE_SHIFT 0U +/*! Register: isp64_hist_v_size: Vertical (sub-)window size (0x00000024)*/ +/*! Slice: hist_v_size:*/ +/*! Vertical size in lines of one sub-window.*/ +#define MRV_HIST_V_SIZE +#define MRV_HIST_V_SIZE_MASK 0x000007FFU +#define MRV_HIST_V_SIZE_SHIFT 0U +/*! Register: isp64_hist_sample_range: Weighting factor for sub-windows (0x00000028)*/ +/*! Slice: sample_shift:*/ +/*! sample (left) shift will be executed after offset subtraction and prior to histogram evaluation */ +#define MRV_HIST_SAMPLE_SHIFT +#define MRV_HIST_SAMPLE_SHIFT_MASK 0x00070000U +#define MRV_HIST_SAMPLE_SHIFT_SHIFT 16U +/*! Slice: sample_offset:*/ +/*! sample offset will be subtracted from input sample prior to shift and histogram evaluation */ +#define MRV_HIST_SAMPLE_OFFSET +#define MRV_HIST_SAMPLE_OFFSET_MASK 0x00000FFFU +#define MRV_HIST_SAMPLE_OFFSET_SHIFT 0U +/*! Register: isp64_hist_weight_00to30: Weighting factor for sub-windows (0x0000002c)*/ +/*! Slice: hist_weight_30:*/ +/*! weighting factor for sub-window 30 */ +#define MRV_HIST_WEIGHT_30 +#define MRV_HIST_WEIGHT_30_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_30_SHIFT 24U +/*! Slice: hist_weight_20:*/ +/*! weighting factor for sub-window 20 */ +#define MRV_HIST_WEIGHT_20 +#define MRV_HIST_WEIGHT_20_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_20_SHIFT 16U +/*! Slice: hist_weight_10:*/ +/*! weighting factor for sub-window 10 */ +#define MRV_HIST_WEIGHT_10 +#define MRV_HIST_WEIGHT_10_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_10_SHIFT 8U +/*! Slice: hist_weight_00:*/ +/*! weighting factor for sub-window 00 */ +#define MRV_HIST_WEIGHT_00 +#define MRV_HIST_WEIGHT_00_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_00_SHIFT 0U +/*! Register: isp64_hist_weight_40to21: Weighting factor for sub-windows (0x00000030)*/ +/*! Slice: hist_weight_21:*/ +/*! weighting factor for sub-window 21 */ +#define MRV_HIST_WEIGHT_21 +#define MRV_HIST_WEIGHT_21_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_21_SHIFT 24U +/*! Slice: hist_weight_11:*/ +/*! weighting factor for sub-window 11 */ +#define MRV_HIST_WEIGHT_11 +#define MRV_HIST_WEIGHT_11_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_11_SHIFT 16U +/*! Slice: hist_weight_01:*/ +/*! weighting factor for sub-window 01 */ +#define MRV_HIST_WEIGHT_01 +#define MRV_HIST_WEIGHT_01_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_01_SHIFT 8U +/*! Slice: hist_weight_40:*/ +/*! weighting factor for sub-window 40 */ +#define MRV_HIST_WEIGHT_40 +#define MRV_HIST_WEIGHT_40_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_40_SHIFT 0U +/*! Register: isp64_hist_weight_31to12: Weighting factor for sub-windows (0x00000034)*/ +/*! Slice: hist_weight_12:*/ +/*! weighting factor for sub-window 12 */ +#define MRV_HIST_WEIGHT_12 +#define MRV_HIST_WEIGHT_12_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_12_SHIFT 24U +/*! Slice: hist_weight_02:*/ +/*! weighting factor for sub-window 02 */ +#define MRV_HIST_WEIGHT_02 +#define MRV_HIST_WEIGHT_02_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_02_SHIFT 16U +/*! Slice: hist_weight_41:*/ +/*! weighting factor for sub-window 41 */ +#define MRV_HIST_WEIGHT_41 +#define MRV_HIST_WEIGHT_41_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_41_SHIFT 8U +/*! Slice: hist_weight_31:*/ +/*! weighting factor for sub-window 31 */ +#define MRV_HIST_WEIGHT_31 +#define MRV_HIST_WEIGHT_31_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_31_SHIFT 0U +/*! Register: isp64_hist_weight_22to03: Weighting factor for sub-windows (0x00000038)*/ +/*! Slice: hist_weight_03:*/ +/*! weighting factor for sub-window 03 */ +#define MRV_HIST_WEIGHT_03 +#define MRV_HIST_WEIGHT_03_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_03_SHIFT 24U +/*! Slice: hist_weight_42:*/ +/*! weighting factor for sub-window 42 */ +#define MRV_HIST_WEIGHT_42 +#define MRV_HIST_WEIGHT_42_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_42_SHIFT 16U +/*! Slice: hist_weight_32:*/ +/*! weighting factor for sub-window 32 */ +#define MRV_HIST_WEIGHT_32 +#define MRV_HIST_WEIGHT_32_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_32_SHIFT 8U +/*! Slice: hist_weight_22:*/ +/*! weighting factor for sub-window 22 */ +#define MRV_HIST_WEIGHT_22 +#define MRV_HIST_WEIGHT_22_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_22_SHIFT 0U +/*! Register: isp64_hist_weight_13to43: Weighting factor for sub-windows (0x0000003c)*/ +/*! Slice: hist_weight_43:*/ +/*! weighting factor for sub-window 43 */ +#define MRV_HIST_WEIGHT_43 +#define MRV_HIST_WEIGHT_43_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_43_SHIFT 24U +/*! Slice: hist_weight_33:*/ +/*! weighting factor for sub-window 33 */ +#define MRV_HIST_WEIGHT_33 +#define MRV_HIST_WEIGHT_33_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_33_SHIFT 16U +/*! Slice: hist_weight_23:*/ +/*! weighting factor for sub-window 23 */ +#define MRV_HIST_WEIGHT_23 +#define MRV_HIST_WEIGHT_23_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_23_SHIFT 8U +/*! Slice: hist_weight_13:*/ +/*! weighting factor for sub-window 13 */ +#define MRV_HIST_WEIGHT_13 +#define MRV_HIST_WEIGHT_13_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_13_SHIFT 0U +/*! Register: isp64_hist_weight_04to34: Weighting factor for sub-windows (0x00000040)*/ +/*! Slice: hist_weight_34:*/ +/*! weighting factor for sub-window 34 */ +#define MRV_HIST_WEIGHT_34 +#define MRV_HIST_WEIGHT_34_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_34_SHIFT 24U +/*! Slice: hist_weight_24:*/ +/*! weighting factor for sub-window 24 */ +#define MRV_HIST_WEIGHT_24 +#define MRV_HIST_WEIGHT_24_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_24_SHIFT 16U +/*! Slice: hist_weight_14:*/ +/*! weighting factor for sub-window 14 */ +#define MRV_HIST_WEIGHT_14 +#define MRV_HIST_WEIGHT_14_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_14_SHIFT 8U +/*! Slice: hist_weight_04:*/ +/*! weighting factor for sub-window 04 */ +#define MRV_HIST_WEIGHT_04 +#define MRV_HIST_WEIGHT_04_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_04_SHIFT 0U +/*! Register: isp64_hist_weight_44: Weighting factor for sub-windows (0x00000044)*/ +/*! Slice: hist_weight_44:*/ +/*! weighting factor for sub-window 44 */ +#define MRV_HIST_WEIGHT_44 +#define MRV_HIST_WEIGHT_44_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_44_SHIFT 0U +/*! Register: isp64_hist_forced_upd_start_line: Forced update start line limit (0x00000048)*/ +/*! Slice: forced_upd_start_line:*/ +/*! start line for histogram calculation in case of forced update. histogram is started as soon as current line < forced_upd_start_line. Used start line will be given in ISP64_HIST_VSTART_STATUS.*/ +#define MRV_HIST_FORCED_UPD_START_LINE +#define MRV_HIST_FORCED_UPD_START_LINE_MASK 0x00001FFFU +#define MRV_HIST_FORCED_UPD_START_LINE_SHIFT 0U +/*! Register: isp64_hist_forced_update: Histogram forced update (0x0000004c)*/ +/*! Slice: forced_upd:*/ +/*! 0: no effect */ +/* 1: forcing register update.*/ +#define MRV_HIST_FORCED_UPD +#define MRV_HIST_FORCED_UPD_MASK 0x00000001U +#define MRV_HIST_FORCED_UPD_SHIFT 0U +/*! Register: isp64_hist_vstart_status: Forced update start line status (0x00000050)*/ +/*! Slice: hist_vstart_status:*/ +/*! start line for histogram. Important in case of backward switching because 1st histogram after switch might not cover the complete image.*/ +#define MRV_HIST_VSTART_STATUS +#define MRV_HIST_VSTART_STATUS_MASK 0x00001FFFU +#define MRV_HIST_VSTART_STATUS_SHIFT 0U +/*! Register array: isp64_hist_bin: histogram measurement result bin (0x0A8 + n*0x4 (n=0..31))*/ +/*! Slice: hist_bin:*/ +/* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */ +#define MRV_HIST_BIN +#define MRV_HIST_BIN_MASK 0x000FFFFFU +#define MRV_HIST_BIN_SHIFT 0U +/*! Register: isp_vsm_mode: VS Measure Mode (0x00000000)*/ +/*! Slice: vsm_meas_irq_enable:*/ +/*! 1: VS measure done IRQ enable.*/ +#define ISP_VSM_MEAS_IRQ_ENABLE +#define ISP_VSM_MEAS_IRQ_ENABLE_MASK 0x00000002U +#define ISP_VSM_MEAS_IRQ_ENABLE_SHIFT 1U +/*! Slice: vsm_meas_en:*/ +/*! 1: enable measure.*/ +#define ISP_VSM_MEAS_EN +#define ISP_VSM_MEAS_EN_MASK 0x00000001U +#define ISP_VSM_MEAS_EN_SHIFT 0U +/*! Register: isp_vsm_h_offs: VSM window horizontal offset (0x00000004)*/ +/*! Slice: vsm_h_offset:*/ +/*! Horizontal offset in pixels.*/ +#define ISP_VSM_H_OFFSET +#define ISP_VSM_H_OFFSET_MASK 0x00001FFFU +#define ISP_VSM_H_OFFSET_SHIFT 0U +/*! Register: isp_vsm_v_offs: VSM window vertical offset (0x00000008)*/ +/*! Slice: vsm_v_offset:*/ +/*! Vertical offset in pixels.*/ +#define ISP_VSM_V_OFFSET +#define ISP_VSM_V_OFFSET_MASK 0x00001FFFU +#define ISP_VSM_V_OFFSET_SHIFT 0U +/*! Register: isp_vsm_h_size: Horizontal measure window size (0x0000000c)*/ +/*! Slice: vsm_h_size:*/ +/*! Horizontal size in pixels. Range 64..1920 */ +#define ISP_VSM_H_SIZE +#define ISP_VSM_H_SIZE_MASK 0x00000780U +#define ISP_VSM_H_SIZE_SHIFT 1U +/*! Register: isp_vsm_v_size: Vertical measure window size (0x00000010)*/ +/*! Slice: vsm_v_size:*/ +/*! Vertical size. Range 64..1088 */ +#define ISP_VSM_V_SIZE +#define ISP_VSM_V_SIZE_MASK 0x00000440U +#define ISP_VSM_V_SIZE_SHIFT 1U +/*! Register: isp_vsm_h_segments: Iteration 1 horizontal segments (0x00000014)*/ +/*! Slice: vsm_h_segments:*/ +/*! number of 16 point wide segments enclosed by the first iteration sample points in horizontal direction. Range: 1 ... 128 */ +#define ISP_VSM_H_SEGMENTS +#define ISP_VSM_H_SEGMENTS_MASK 0x000000FFU +#define ISP_VSM_H_SEGMENTS_SHIFT 0U +/*! Register: isp_vsm_v_segments: Iteration 1 vertical segments (0x00000018)*/ +/*! Slice: vsm_v_segments:*/ +/*! number of 16 point wide segments enclosed by the first iteration sample points in vertical direction. Range: 1 ... 128 */ +#define ISP_VSM_V_SEGMENTS +#define ISP_VSM_V_SEGMENTS_MASK 0x000000FFU +#define ISP_VSM_V_SEGMENTS_SHIFT 0U +/*! Register: isp_vsm_delta_h: estimated horizontal displacement (0x0000001c)*/ +/*! Slice: delta_h:*/ +/*! estimated horizontal displacement 12Bit two's complement. positive values indicate a displacement of the image from right to left (camera turns right)*/ +#define ISP_VSM_DELTA_H +#define ISP_VSM_DELTA_H_MASK 0x00000FFFU +#define ISP_VSM_DELTA_H_SHIFT 0U +/*! Register: isp_vsm_delta_v: estimated vertical displacement (0x00000020)*/ +/*! Slice: delta_v:*/ +/*! estimated vertical displacement 12Bit two's complement. positive values indicate a displacement of the image from bottom to top (camera turns down)*/ +#define ISP_VSM_DELTA_V +#define ISP_VSM_DELTA_V_MASK 0x00000FFFU +#define ISP_VSM_DELTA_V_SHIFT 0U +#ifdef ISP_RGBGC +/*! Register: isp_ctrl:isp control register (0x00000400)*/ +/*! Slice: rgb_gc_enable */ +/*! Control of rgb gamma correction */ +/*! 1'b0: disable rgb GC bypass mode */ +/*! 1'b1: enable rgb GC mode */ +#define ISP_RGBGC_ENABLE +#define ISP_RGBGC_ENABLE_MASK 0x00000800U +#define ISP_RGBGC_ENABLE_SHIFT 11U +#endif +#ifdef ISP_GCMONO +/*! Register: isp_ctrl:isp control register (0x00000400)*/ +/*! Slice: mono_gc_enable */ +/*! Control of gamma correction for mono sensor RAW data */ +/*! 1'b0: disable GC bypass mode */ +/*! 1'b1: enable GC mode */ +#define ISP_GCMONO_ENABLE +#define ISP_GCMONO_ENABLE_MASK 0x00080000U +#define ISP_GCMONO_ENABLE_SHIFT 19U +/*! Register: isp_ctrl:isp control register (0x00000400)*/ +/*! Slice: mono_gc_mode */ +/*! Control of gamma correction for mono sensor RAW data mode */ +/*! 1'b0: 0: 10->8 */ +/*! 1'b1: 12->10 */ +#define ISP_GCMONO_MODE +#define ISP_GCMONO_MODE_MASK 0x00100000U +#define ISP_GCMONO_MODE_SHIFT 20 +/*! Register: isp_gcmono_ctrl: GC Mono control register (0x00000000)*/ +/*! Slice: mono_gc_enable */ +/*! Control of gamma correction for mono sensor RAW data */ +/*! 1'b0: disable GC bypass mode */ +/*! 1'b1: enable GC mode */ +#define ISP_GCMONO_SWITCH +#define ISP_GCMONO_SWITCH_MASK 0x00000001U +#define ISP_GCMONO_SWITCH_SHIFT 0U +/*! Slice: mono_gc_cfg_done */ +/*! To notify the ISP HW the LUT configuration is done, ready to use, active high.*/ +/*! Writing ZERO reset teh internal read/write pointer and also indicates that the LUT can be configured or read from CPU.*/ +#define ISP_GCMONO_CFG_DONE +#define ISP_GCMONO_CFG_DONE_MASK 0x00000002U +#define ISP_GCMONO_CFG_DONE_SHIFT 1U +/*! Register: isp_gcmono_para_base: GC Mono Gamma LUT for mono sensor (0x00000004)*/ +/*! Slice: Base address of Gamma LUT for mono sensor, when AHB slave writes/reads this register address continuously, it means it will start to */ +/*! write or read the LUT.*/ +#define ISP_GCMONO_PARA_BASE +#define ISP_GCMONO_PARA_BASE_MASK 0xFFFFFFFFU +#define ISP_GCMONO_PARA_BASE_SHIFT 0U +#endif +/*! Register: isp_wdr2_ctrl (0x00003100)*/ +/*! Slice: wdr2_soft_reset_flag:*/ +#define WDR2_SOFT_RESET_FLAG +#define WDR2_SOFT_RESET_FLAG_MASK 0x00000004U +#define WDR2_SOFT_RESET_FLAG_SHIFT 2U +/*! Slice: wdr2_mono_input:*/ +#define WDR2_MONO_INPUT +#define WDR2_MONO_INPUT_MASK 0x00000002U +#define WDR2_MONO_INPUT_SHIFT 1U +/*! Slice: wdr2_enable:*/ +#define WDR2_ENABLE +#define WDR2_ENABLE_MASK 0x00000001U +#define WDR2_ENABLE_SHIFT 0U +/*! Register: isp_wdr2_blk_siz (0x00003104)*/ +/*! Slice: hist_block_width:*/ +#define HIST_BLOCK_WIDTH +#define HIST_BLOCK_WIDTH_MASK 0x000FFC00U +#define HIST_BLOCK_WIDTH_SHIFT 10U +/*! Slice: hist_block_height:*/ +#define HIST_BLOCK_HEIGHT +#define HIST_BLOCK_HEIGHT_MASK 0x000003FFU +#define HIST_BLOCK_HEIGHT_SHIFT 0U +/*! Register: isp_wdr2_color_weight (0x00003108)*/ +/*! Slice: wdr2_color_weight_2:*/ +#define WDR2_COLOR_WEIGHT_2 +#define WDR2_COLOR_WEIGHT_2_MASK 0x00FF0000U +#define WDR2_COLOR_WEIGHT_2_SHIFT 16U +/*! Slice: wdr2_color_weight_1:*/ +#define WDR2_COLOR_WEIGHT_1 +#define WDR2_COLOR_WEIGHT_1_MASK 0x0000FF00U +#define WDR2_COLOR_WEIGHT_1_SHIFT 8U +/*! Slice: wdr2_color_weight_0:*/ +#define WDR2_COLOR_WEIGHT_0 +#define WDR2_COLOR_WEIGHT_0_MASK 0x000000FFU +#define WDR2_COLOR_WEIGHT_0_SHIFT 0U +/*! Register: isp_wdr2_blt_sigma (0x0000310C)*/ +/*! Slice: wdr2_blt_range_sigma:*/ +#define WDR2_BLT_RANGE_SIGMA +#define WDR2_BLT_RANGE_SIGMA_MASK 0x000FFC00U +#define WDR2_BLT_RANGE_SIGMA_SHIFT 10U +/*! Slice: wdr2_blt_spatial_sigma:*/ +#define WDR2_BLT_SPATIAL_SIGMA +#define WDR2_BLT_SPATIAL_SIGMA_MASK 0x000003FFU +#define WDR2_BLT_SPATIAL_SIGMA_SHIFT 0U +/*! Register: isp_wdr2_blt_kernel_0 (0x00003110)*/ +/*! Slice: wdr2_blt_kernel_c:*/ +#define WDR2_BLT_KERNEL_C +#define WDR2_BLT_KERNEL_C_MASK 0x00FF0000U +#define WDR2_BLT_KERNEL_C_SHIFT 16U +/*! Slice: wdr2_blt_kernel_b:*/ +#define WDR2_BLT_KERNEL_B +#define WDR2_BLT_KERNEL_B_MASK 0x0000FF00U +#define WDR2_BLT_KERNEL_B_SHIFT 8U +/*! Slice: wdr2_blt_kernel_a:*/ +#define WDR2_BLT_KERNEL_A +#define WDR2_BLT_KERNEL_A_MASK 0x000000FFU +#define WDR2_BLT_KERNEL_A_SHIFT 0U +/*! Register: isp_wdr2_blt_kernel_1 (0x00003114)*/ +/*! Slice: wdr2_blt_kernel_f:*/ +#define WDR2_BLT_KERNEL_F +#define WDR2_BLT_KERNEL_F_MASK 0x00FF0000U +#define WDR2_BLT_KERNEL_F_SHIFT 16U +/*! Slice: wdr2_blt_kernel_e:*/ +#define WDR2_BLT_KERNEL_E +#define WDR2_BLT_KERNEL_E_MASK 0x0000FF00U +#define WDR2_BLT_KERNEL_E_SHIFT 8U +/*! Slice: wdr2_blt_kernel_d:*/ +#define WDR2_BLT_KERNEL_D +#define WDR2_BLT_KERNEL_D_MASK 0x000000FFU +#define WDR2_BLT_KERNEL_D_SHIFT 0U +/*! Register: isp_wdr2_vol_shift_bit (0x00003118)*/ +/*! Slice: wdr2_vol_shift_bit:*/ +#define WDR2_VOL_SHIFT_BIT +#define WDR2_VOL_SHIFT_BIT_MASK 0x0000001FU +#define WDR2_VOL_SHIFT_BIT_SHIFT 0U +/*! Register: isp_wdr2_bin_dist_0 (0x0000311C)*/ +/*! Slice: wdr2_bin_dist_1:*/ +#define WDR2_BIN_DIST_1 +#define WDR2_BIN_DIST_1_MASK 0x0FFF0000U +#define WDR2_BIN_DIST_1_SHIFT 16U +/*! Slice: wdr2_bin_dist_0:*/ +#define WDR2_BIN_DIST_0 +#define WDR2_BIN_DIST_0_MASK 0x00000FFFU +#define WDR2_BIN_DIST_0_SHIFT 0U +/*! Register: isp_wdr2_bin_dist_1 (0x00003120)*/ +/*! Slice: wdr2_bin_dist_3:*/ +#define WDR2_BIN_DIST_3 +#define WDR2_BIN_DIST_3_MASK 0x0FFF0000U +#define WDR2_BIN_DIST_3_SHIFT 16U +/*! Slice: wdr2_bin_dist_2:*/ +#define WDR2_BIN_DIST_2 +#define WDR2_BIN_DIST_2_MASK 0x00000FFFU +#define WDR2_BIN_DIST_2_SHIFT 0U +/*! Register: isp_wdr2_bin_dist_2 (0x00003124)*/ +/*! Slice: wdr2_bin_dist_5:*/ +#define WDR2_BIN_DIST_5 +#define WDR2_BIN_DIST_5_MASK 0x0FFF0000U +#define WDR2_BIN_DIST_5_SHIFT 16U +/*! Slice: wdr2_bin_dist_4:*/ +#define WDR2_BIN_DIST_4 +#define WDR2_BIN_DIST_4_MASK 0x00000FFFU +#define WDR2_BIN_DIST_4_SHIFT 0U +/*! Register: isp_wdr2_bin_dist_3 (0x00003128)*/ +/*! Slice: wdr2_bin_dist_7:*/ +#define WDR2_BIN_DIST_7 +#define WDR2_BIN_DIST_7_MASK 0x0FFF0000U +#define WDR2_BIN_DIST_7_SHIFT 16U +/*! Slice: wdr2_bin_dist_6:*/ +#define WDR2_BIN_DIST_6 +#define WDR2_BIN_DIST_6_MASK 0x00000FFFU +#define WDR2_BIN_DIST_6_SHIFT 0U +/*! Register: isp_wdr2_hist_norm_fac (0x0000312C)*/ +/*! Slice: wdr2_hist_norm_shift_bit:*/ +#define WDR2_HIST_NORM_SHIFT_BIT +#define WDR2_HIST_NORM_SHIFT_BIT_MASK 0x0FFF0000U +#define WDR2_HIST_NORM_SHIFT_BIT_SHIFT 16U +/*! Slice: wdr2_hist_norm_mul:*/ +#define WDR2_HIST_NORM_MUL +#define WDR2_HIST_NORM_MUL_MASK 0x00000FFFU +#define WDR2_HIST_NORM_MUL_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_lut (0x00003138)*/ +/*! Slice: wdr2_pre_gamma_lut:*/ +#define WDR2_PRE_GAMMA_LUT +#define WDR2_PRE_GAMMA_LUT_MASK 0xFFFFFFFFU +#define WDR2_PRE_GAMMA_LUT_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_write_data (0x0000313C)*/ +/*! Slice: wdr2_pre_gamma_write_data:*/ +#define WDR2_PRE_GAMMA_WRITE_DATA +#define WDR2_PRE_GAMMA_WRITE_DATA_MASK 0x00000FFFU +#define WDR2_PRE_GAMMA_WRITE_DATA_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_lut (0x00003140)*/ +/*! Slice: wdr2_tone_curve_lut:*/ +#define WDR2_TONE_CURVE_LUT +#define WDR2_TONE_CURVE_LUT_MASK 0xFFFFFFFFU +#define WDR2_TONE_CURVE_LUT_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_write_data (0x00003144)*/ +/*! Slice: wdr2_tone_curve_write_data:*/ +#define WDR2_TONE_CURVE_WRITE_DATA +#define WDR2_TONE_CURVE_WRITE_DATA_MASK 0x00000FFFU +#define WDR2_TONE_CURVE_WRITE_DATA_SHIFT 0U +/*! Register: isp_wdr2_merge_coeff_lut (0x00003148)*/ +/*! Slice: wdr2_merge_coeff_lut:*/ +#define WDR2_MERGE_COEFF_LUT +#define WDR2_MERGE_COEFF_LUT_MASK 0xFFFFFFFFU +#define WDR2_MERGE_COEFF_LUT_SHIFT 0U +/*! Register: isp_wdr2_merge_coeff_write_data (0x0000314C)*/ +/*! Slice: wdr2_merge_coeff_write_data:*/ +#define WDR2_MERGE_COEFF_WRITE_DATA +#define WDR2_MERGE_COEFF_WRITE_DATA_MASK 0x000000FFU +#define WDR2_MERGE_COEFF_WRITE_DATA_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_0 (0x00003150)*/ +/*! Slice: wdr2_pre_gamma_cx_5:*/ +#define WDR2_PRE_GAMMA_CX_5 +#define WDR2_PRE_GAMMA_CX_5_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_5_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_4:*/ +#define WDR2_PRE_GAMMA_CX_4 +#define WDR2_PRE_GAMMA_CX_4_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_4_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_3:*/ +#define WDR2_PRE_GAMMA_CX_3 +#define WDR2_PRE_GAMMA_CX_3_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_3_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_2:*/ +#define WDR2_PRE_GAMMA_CX_2 +#define WDR2_PRE_GAMMA_CX_2_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_2_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_1:*/ +#define WDR2_PRE_GAMMA_CX_1 +#define WDR2_PRE_GAMMA_CX_1_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_1_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_0:*/ +#define WDR2_PRE_GAMMA_CX_0 +#define WDR2_PRE_GAMMA_CX_0_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_0_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_1 (0x00003154)*/ +/*! Slice: wdr2_pre_gamma_cx_11:*/ +#define WDR2_PRE_GAMMA_CX_11 +#define WDR2_PRE_GAMMA_CX_11_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_11_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_10:*/ +#define WDR2_PRE_GAMMA_CX_10 +#define WDR2_PRE_GAMMA_CX_10_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_10_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_9:*/ +#define WDR2_PRE_GAMMA_CX_9 +#define WDR2_PRE_GAMMA_CX_9_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_9_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_8:*/ +#define WDR2_PRE_GAMMA_CX_8 +#define WDR2_PRE_GAMMA_CX_8_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_8_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_7:*/ +#define WDR2_PRE_GAMMA_CX_7 +#define WDR2_PRE_GAMMA_CX_7_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_7_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_6:*/ +#define WDR2_PRE_GAMMA_CX_6 +#define WDR2_PRE_GAMMA_CX_6_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_6_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_2 (0x00003158)*/ +/*! Slice: wdr2_pre_gamma_cx_17:*/ +#define WDR2_PRE_GAMMA_CX_17 +#define WDR2_PRE_GAMMA_CX_17_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_17_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_16:*/ +#define WDR2_PRE_GAMMA_CX_16 +#define WDR2_PRE_GAMMA_CX_16_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_16_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_15:*/ +#define WDR2_PRE_GAMMA_CX_15 +#define WDR2_PRE_GAMMA_CX_15_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_15_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_14:*/ +#define WDR2_PRE_GAMMA_CX_14 +#define WDR2_PRE_GAMMA_CX_14_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_14_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_13:*/ +#define WDR2_PRE_GAMMA_CX_13 +#define WDR2_PRE_GAMMA_CX_13_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_13_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_12:*/ +#define WDR2_PRE_GAMMA_CX_12 +#define WDR2_PRE_GAMMA_CX_12_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_12_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_3 (0x0000315C)*/ +/*! Slice: wdr2_pre_gamma_cx_23:*/ +#define WDR2_PRE_GAMMA_CX_23 +#define WDR2_PRE_GAMMA_CX_23_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_23_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_22:*/ +#define WDR2_PRE_GAMMA_CX_22 +#define WDR2_PRE_GAMMA_CX_22_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_22_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_21:*/ +#define WDR2_PRE_GAMMA_CX_21 +#define WDR2_PRE_GAMMA_CX_21_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_21_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_20:*/ +#define WDR2_PRE_GAMMA_CX_20 +#define WDR2_PRE_GAMMA_CX_20_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_20_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_19:*/ +#define WDR2_PRE_GAMMA_CX_19 +#define WDR2_PRE_GAMMA_CX_19_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_19_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_18:*/ +#define WDR2_PRE_GAMMA_CX_18 +#define WDR2_PRE_GAMMA_CX_18_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_18_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_4 (0x00003160)*/ +/*! Slice: wdr2_pre_gamma_cx_29:*/ +#define WDR2_PRE_GAMMA_CX_29 +#define WDR2_PRE_GAMMA_CX_29_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_29_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_28:*/ +#define WDR2_PRE_GAMMA_CX_28 +#define WDR2_PRE_GAMMA_CX_28_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_28_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_27:*/ +#define WDR2_PRE_GAMMA_CX_27 +#define WDR2_PRE_GAMMA_CX_27_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_27_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_26:*/ +#define WDR2_PRE_GAMMA_CX_26 +#define WDR2_PRE_GAMMA_CX_26_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_26_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_25:*/ +#define WDR2_PRE_GAMMA_CX_25 +#define WDR2_PRE_GAMMA_CX_25_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_25_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_24:*/ +#define WDR2_PRE_GAMMA_CX_24 +#define WDR2_PRE_GAMMA_CX_24_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_24_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_5 (0x00003164)*/ +/*! Slice: wdr2_pre_gamma_cx_35:*/ +#define WDR2_PRE_GAMMA_CX_35 +#define WDR2_PRE_GAMMA_CX_35_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_35_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_34:*/ +#define WDR2_PRE_GAMMA_CX_34 +#define WDR2_PRE_GAMMA_CX_34_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_34_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_33:*/ +#define WDR2_PRE_GAMMA_CX_33 +#define WDR2_PRE_GAMMA_CX_33_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_33_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_32:*/ +#define WDR2_PRE_GAMMA_CX_32 +#define WDR2_PRE_GAMMA_CX_32_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_32_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_31:*/ +#define WDR2_PRE_GAMMA_CX_31 +#define WDR2_PRE_GAMMA_CX_31_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_31_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_30:*/ +#define WDR2_PRE_GAMMA_CX_30 +#define WDR2_PRE_GAMMA_CX_30_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_30_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_6 (0x00003168)*/ +/*! Slice: wdr2_pre_gamma_cx_41:*/ +#define WDR2_PRE_GAMMA_CX_41 +#define WDR2_PRE_GAMMA_CX_41_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_41_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_40:*/ +#define WDR2_PRE_GAMMA_CX_40 +#define WDR2_PRE_GAMMA_CX_40_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_40_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_39:*/ +#define WDR2_PRE_GAMMA_CX_39 +#define WDR2_PRE_GAMMA_CX_39_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_39_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_38:*/ +#define WDR2_PRE_GAMMA_CX_38 +#define WDR2_PRE_GAMMA_CX_38_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_38_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_37:*/ +#define WDR2_PRE_GAMMA_CX_37 +#define WDR2_PRE_GAMMA_CX_37_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_37_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_36:*/ +#define WDR2_PRE_GAMMA_CX_36 +#define WDR2_PRE_GAMMA_CX_36_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_36_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_7 (0x0000316C)*/ +/*! Slice: wdr2_pre_gamma_cx_47:*/ +#define WDR2_PRE_GAMMA_CX_47 +#define WDR2_PRE_GAMMA_CX_47_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_47_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_46:*/ +#define WDR2_PRE_GAMMA_CX_46 +#define WDR2_PRE_GAMMA_CX_46_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_46_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_45:*/ +#define WDR2_PRE_GAMMA_CX_45 +#define WDR2_PRE_GAMMA_CX_45_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_45_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_44:*/ +#define WDR2_PRE_GAMMA_CX_44 +#define WDR2_PRE_GAMMA_CX_44_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_44_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_43:*/ +#define WDR2_PRE_GAMMA_CX_43 +#define WDR2_PRE_GAMMA_CX_43_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_43_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_42:*/ +#define WDR2_PRE_GAMMA_CX_42 +#define WDR2_PRE_GAMMA_CX_42_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_42_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_8 (0x00003170)*/ +/*! Slice: wdr2_pre_gamma_cx_53:*/ +#define WDR2_PRE_GAMMA_CX_53 +#define WDR2_PRE_GAMMA_CX_53_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_53_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_52:*/ +#define WDR2_PRE_GAMMA_CX_52 +#define WDR2_PRE_GAMMA_CX_52_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_52_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_51:*/ +#define WDR2_PRE_GAMMA_CX_51 +#define WDR2_PRE_GAMMA_CX_51_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_51_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_50:*/ +#define WDR2_PRE_GAMMA_CX_50 +#define WDR2_PRE_GAMMA_CX_50_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_50_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_49:*/ +#define WDR2_PRE_GAMMA_CX_49 +#define WDR2_PRE_GAMMA_CX_49_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_49_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_48:*/ +#define WDR2_PRE_GAMMA_CX_48 +#define WDR2_PRE_GAMMA_CX_48_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_48_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_9 (0x00003174)*/ +/*! Slice: wdr2_pre_gamma_cx_59:*/ +#define WDR2_PRE_GAMMA_CX_59 +#define WDR2_PRE_GAMMA_CX_59_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_59_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_58:*/ +#define WDR2_PRE_GAMMA_CX_58 +#define WDR2_PRE_GAMMA_CX_58_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_58_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_57:*/ +#define WDR2_PRE_GAMMA_CX_57 +#define WDR2_PRE_GAMMA_CX_57_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_57_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_56:*/ +#define WDR2_PRE_GAMMA_CX_56 +#define WDR2_PRE_GAMMA_CX_56_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_56_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_55:*/ +#define WDR2_PRE_GAMMA_CX_55 +#define WDR2_PRE_GAMMA_CX_55_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_55_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_54:*/ +#define WDR2_PRE_GAMMA_CX_54 +#define WDR2_PRE_GAMMA_CX_54_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_54_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_10 (0x00003178)*/ +/*! Slice: wdr2_pre_gamma_cx_63:*/ +#define WDR2_PRE_GAMMA_CX_63 +#define WDR2_PRE_GAMMA_CX_63_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_63_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_62:*/ +#define WDR2_PRE_GAMMA_CX_62 +#define WDR2_PRE_GAMMA_CX_62_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_62_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_61:*/ +#define WDR2_PRE_GAMMA_CX_61 +#define WDR2_PRE_GAMMA_CX_61_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_61_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_60:*/ +#define WDR2_PRE_GAMMA_CX_60 +#define WDR2_PRE_GAMMA_CX_60_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_60_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_cx_0 (0x0000317C)*/ +/*! Slice: wdr2_tone_curve_cx_7:*/ +#define WDR2_TONE_CURVE_CX_7 +#define WDR2_TONE_CURVE_CX_7_MASK 0xF0000000U +#define WDR2_TONE_CURVE_CX_7_SHIFT 28U +/*! Slice: wdr2_tone_curve_cx_6:*/ +#define WDR2_TONE_CURVE_CX_6 +#define WDR2_TONE_CURVE_CX_6_MASK 0x0F000000U +#define WDR2_TONE_CURVE_CX_6_SHIFT 24U +/*! Slice: wdr2_tone_curve_cx_5:*/ +#define WDR2_TONE_CURVE_CX_5 +#define WDR2_TONE_CURVE_CX_5_MASK 0x00F00000U +#define WDR2_TONE_CURVE_CX_5_SHIFT 20U +/*! Slice: wdr2_tone_curve_cx_4:*/ +#define WDR2_TONE_CURVE_CX_4 +#define WDR2_TONE_CURVE_CX_4_MASK 0x000F0000U +#define WDR2_TONE_CURVE_CX_4_SHIFT 16U +/*! Slice: wdr2_tone_curve_cx_3:*/ +#define WDR2_TONE_CURVE_CX_3 +#define WDR2_TONE_CURVE_CX_3_MASK 0x0000F000U +#define WDR2_TONE_CURVE_CX_3_SHIFT 12U +/*! Slice: wdr2_tone_curve_cx_2:*/ +#define WDR2_TONE_CURVE_CX_2 +#define WDR2_TONE_CURVE_CX_2_MASK 0x00000F00U +#define WDR2_TONE_CURVE_CX_2_SHIFT 8U +/*! Slice: wdr2_tone_curve_cx_1:*/ +#define WDR2_TONE_CURVE_CX_1 +#define WDR2_TONE_CURVE_CX_1_MASK 0x000000F0U +#define WDR2_TONE_CURVE_CX_1_SHIFT 4U +/*! Slice: wdr2_tone_curve_cx_0:*/ +#define WDR2_TONE_CURVE_CX_0 +#define WDR2_TONE_CURVE_CX_0_MASK 0x0000000FU +#define WDR2_TONE_CURVE_CX_0_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_cx_1 (0x00003180)*/ +/*! Slice: wdr2_tone_curve_cx_15:*/ +#define WDR2_TONE_CURVE_CX_15 +#define WDR2_TONE_CURVE_CX_15_MASK 0xF0000000U +#define WDR2_TONE_CURVE_CX_15_SHIFT 28U +/*! Slice: wdr2_tone_curve_cx_14:*/ +#define WDR2_TONE_CURVE_CX_14 +#define WDR2_TONE_CURVE_CX_14_MASK 0x0F000000U +#define WDR2_TONE_CURVE_CX_14_SHIFT 24U +/*! Slice: wdr2_tone_curve_cx_13:*/ +#define WDR2_TONE_CURVE_CX_13 +#define WDR2_TONE_CURVE_CX_13_MASK 0x00F00000U +#define WDR2_TONE_CURVE_CX_13_SHIFT 20U +/*! Slice: wdr2_tone_curve_cx_12:*/ +#define WDR2_TONE_CURVE_CX_12 +#define WDR2_TONE_CURVE_CX_12_MASK 0x000F0000U +#define WDR2_TONE_CURVE_CX_12_SHIFT 16U +/*! Slice: wdr2_tone_curve_cx_11:*/ +#define WDR2_TONE_CURVE_CX_11 +#define WDR2_TONE_CURVE_CX_11_MASK 0x0000F000U +#define WDR2_TONE_CURVE_CX_11_SHIFT 12U +/*! Slice: wdr2_tone_curve_cx_10:*/ +#define WDR2_TONE_CURVE_CX_10 +#define WDR2_TONE_CURVE_CX_10_MASK 0x00000F00U +#define WDR2_TONE_CURVE_CX_10_SHIFT 8U +/*! Slice: wdr2_tone_curve_cx_9:*/ +#define WDR2_TONE_CURVE_CX_9 +#define WDR2_TONE_CURVE_CX_9_MASK 0x000000F0U +#define WDR2_TONE_CURVE_CX_9_SHIFT 4U +/*! Slice: wdr2_tone_curve_cx_8:*/ +#define WDR2_TONE_CURVE_CX_8 +#define WDR2_TONE_CURVE_CX_8_MASK 0x0000000FU +#define WDR2_TONE_CURVE_CX_8_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_cx_2 (0x00003184)*/ +/*! Slice: wdr2_tone_curve_cx_23:*/ +#define WDR2_TONE_CURVE_CX_23 +#define WDR2_TONE_CURVE_CX_23_MASK 0xF0000000U +#define WDR2_TONE_CURVE_CX_23_SHIFT 28U +/*! Slice: wdr2_tone_curve_cx_22:*/ +#define WDR2_TONE_CURVE_CX_22 +#define WDR2_TONE_CURVE_CX_22_MASK 0x0F000000U +#define WDR2_TONE_CURVE_CX_22_SHIFT 24U +/*! Slice: wdr2_tone_curve_cx_21:*/ +#define WDR2_TONE_CURVE_CX_21 +#define WDR2_TONE_CURVE_CX_21_MASK 0x00F00000U +#define WDR2_TONE_CURVE_CX_21_SHIFT 20U +/*! Slice: wdr2_tone_curve_cx_20:*/ +#define WDR2_TONE_CURVE_CX_20 +#define WDR2_TONE_CURVE_CX_20_MASK 0x000F0000U +#define WDR2_TONE_CURVE_CX_20_SHIFT 16U +/*! Slice: wdr2_tone_curve_cx_19:*/ +#define WDR2_TONE_CURVE_CX_19 +#define WDR2_TONE_CURVE_CX_19_MASK 0x0000F000U +#define WDR2_TONE_CURVE_CX_19_SHIFT 12U +/*! Slice: wdr2_tone_curve_cx_18:*/ +#define WDR2_TONE_CURVE_CX_18 +#define WDR2_TONE_CURVE_CX_18_MASK 0x00000F00U +#define WDR2_TONE_CURVE_CX_18_SHIFT 8U +/*! Slice: wdr2_tone_curve_cx_17:*/ +#define WDR2_TONE_CURVE_CX_17 +#define WDR2_TONE_CURVE_CX_17_MASK 0x000000F0U +#define WDR2_TONE_CURVE_CX_17_SHIFT 4U +/*! Slice: wdr2_tone_curve_cx_16:*/ +#define WDR2_TONE_CURVE_CX_16 +#define WDR2_TONE_CURVE_CX_16_MASK 0x0000000FU +#define WDR2_TONE_CURVE_CX_16_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_cx_3 (0x00003188)*/ +/*! Slice: wdr2_tone_curve_cx_31:*/ +#define WDR2_TONE_CURVE_CX_31 +#define WDR2_TONE_CURVE_CX_31_MASK 0xF0000000U +#define WDR2_TONE_CURVE_CX_31_SHIFT 28U +/*! Slice: wdr2_tone_curve_cx_30:*/ +#define WDR2_TONE_CURVE_CX_30 +#define WDR2_TONE_CURVE_CX_30_MASK 0x0F000000U +#define WDR2_TONE_CURVE_CX_30_SHIFT 24U +/*! Slice: wdr2_tone_curve_cx_29:*/ +#define WDR2_TONE_CURVE_CX_29 +#define WDR2_TONE_CURVE_CX_29_MASK 0x00F00000U +#define WDR2_TONE_CURVE_CX_29_SHIFT 20U +/*! Slice: wdr2_tone_curve_cx_28:*/ +#define WDR2_TONE_CURVE_CX_28 +#define WDR2_TONE_CURVE_CX_28_MASK 0x000F0000U +#define WDR2_TONE_CURVE_CX_28_SHIFT 16U +/*! Slice: wdr2_tone_curve_cx_27:*/ +#define WDR2_TONE_CURVE_CX_27 +#define WDR2_TONE_CURVE_CX_27_MASK 0x0000F000U +#define WDR2_TONE_CURVE_CX_27_SHIFT 12U +/*! Slice: wdr2_tone_curve_cx_26:*/ +#define WDR2_TONE_CURVE_CX_26 +#define WDR2_TONE_CURVE_CX_26_MASK 0x00000F00U +#define WDR2_TONE_CURVE_CX_26_SHIFT 8U +/*! Slice: wdr2_tone_curve_cx_25:*/ +#define WDR2_TONE_CURVE_CX_25 +#define WDR2_TONE_CURVE_CX_25_MASK 0x000000F0U +#define WDR2_TONE_CURVE_CX_25_SHIFT 4U +/*! Slice: wdr2_tone_curve_cx_24:*/ +#define WDR2_TONE_CURVE_CX_24 +#define WDR2_TONE_CURVE_CX_24_MASK 0x0000000FU +#define WDR2_TONE_CURVE_CX_24_SHIFT 0U +/*! Register: isp_wdr2_merge_coeff_cx_0 (0x0000318C)*/ +/*! Slice: wdr2_merge_coeff_cx_7:*/ +#define WDR2_MERGE_COEFF_CX_7 +#define WDR2_MERGE_COEFF_CX_7_MASK 0xF0000000U +#define WDR2_MERGE_COEFF_CX_7_SHIFT 28U +/*! Slice: wdr2_merge_coeff_cx_6:*/ +#define WDR2_MERGE_COEFF_CX_6 +#define WDR2_MERGE_COEFF_CX_6_MASK 0x0F000000U +#define WDR2_MERGE_COEFF_CX_6_SHIFT 24U +/*! Slice: wdr2_merge_coeff_cx_5:*/ +#define WDR2_MERGE_COEFF_CX_5 +#define WDR2_MERGE_COEFF_CX_5_MASK 0x00F00000U +#define WDR2_MERGE_COEFF_CX_5_SHIFT 20U +/*! Slice: wdr2_merge_coeff_cx_4:*/ +#define WDR2_MERGE_COEFF_CX_4 +#define WDR2_MERGE_COEFF_CX_4_MASK 0x000F0000U +#define WDR2_MERGE_COEFF_CX_4_SHIFT 16U +/*! Slice: wdr2_merge_coeff_cx_3:*/ +#define WDR2_MERGE_COEFF_CX_3 +#define WDR2_MERGE_COEFF_CX_3_MASK 0x0000F000U +#define WDR2_MERGE_COEFF_CX_3_SHIFT 12U +/*! Slice: wdr2_merge_coeff_cx_2:*/ +#define WDR2_MERGE_COEFF_CX_2 +#define WDR2_MERGE_COEFF_CX_2_MASK 0x00000F00U +#define WDR2_MERGE_COEFF_CX_2_SHIFT 8U +/*! Slice: wdr2_merge_coeff_cx_1:*/ +#define WDR2_MERGE_COEFF_CX_1 +#define WDR2_MERGE_COEFF_CX_1_MASK 0x000000F0U +#define WDR2_MERGE_COEFF_CX_1_SHIFT 4U +/*! Slice: wdr2_merge_coeff_cx_0:*/ +#define WDR2_MERGE_COEFF_CX_0 +#define WDR2_MERGE_COEFF_CX_0_MASK 0x0000000FU +#define WDR2_MERGE_COEFF_CX_0_SHIFT 0U +/*! Register: isp_wdr2_merge_coeff_cx_1 (0x00003190)*/ +/*! Slice: wdr2_merge_coeff_cx_15:*/ +#define WDR2_MERGE_COEFF_CX_15 +#define WDR2_MERGE_COEFF_CX_15_MASK 0xF0000000U +#define WDR2_MERGE_COEFF_CX_15_SHIFT 28U +/*! Slice: wdr2_merge_coeff_cx_14:*/ +#define WDR2_MERGE_COEFF_CX_14 +#define WDR2_MERGE_COEFF_CX_14_MASK 0x0F000000U +#define WDR2_MERGE_COEFF_CX_14_SHIFT 24U +/*! Slice: wdr2_merge_coeff_cx_13:*/ +#define WDR2_MERGE_COEFF_CX_13 +#define WDR2_MERGE_COEFF_CX_13_MASK 0x00F00000U +#define WDR2_MERGE_COEFF_CX_13_SHIFT 20U +/*! Slice: wdr2_merge_coeff_cx_12:*/ +#define WDR2_MERGE_COEFF_CX_12 +#define WDR2_MERGE_COEFF_CX_12_MASK 0x000F0000U +#define WDR2_MERGE_COEFF_CX_12_SHIFT 16U +/*! Slice: wdr2_merge_coeff_cx_11:*/ +#define WDR2_MERGE_COEFF_CX_11 +#define WDR2_MERGE_COEFF_CX_11_MASK 0x0000F000U +#define WDR2_MERGE_COEFF_CX_11_SHIFT 12U +/*! Slice: wdr2_merge_coeff_cx_10:*/ +#define WDR2_MERGE_COEFF_CX_10 +#define WDR2_MERGE_COEFF_CX_10_MASK 0x00000F00U +#define WDR2_MERGE_COEFF_CX_10_SHIFT 8U +/*! Slice: wdr2_merge_coeff_cx_9:*/ +#define WDR2_MERGE_COEFF_CX_9 +#define WDR2_MERGE_COEFF_CX_9_MASK 0x000000F0U +#define WDR2_MERGE_COEFF_CX_9_SHIFT 4U +/*! Slice: wdr2_merge_coeff_cx_8:*/ +#define WDR2_MERGE_COEFF_CX_8 +#define WDR2_MERGE_COEFF_CX_8_MASK 0x0000000FU +#define WDR2_MERGE_COEFF_CX_8_SHIFT 0U +/*! Register: isp_wdr2_max_gain_cx (0x000031A8)*/ +/*! Slice: wdr2_max_gain_cx_4:*/ +#define WDR2_MAX_GAIN_CX_4 +#define WDR2_MAX_GAIN_CX_4_MASK 0xFF000000U +#define WDR2_MAX_GAIN_CX_4_SHIFT 24U +/*! Slice: wdr2_max_gain_cx_3:*/ +#define WDR2_MAX_GAIN_CX_3 +#define WDR2_MAX_GAIN_CX_3_MASK 0x00FF0000U +#define WDR2_MAX_GAIN_CX_3_SHIFT 16U +/*! Slice: wdr2_max_gain_cx_2:*/ +#define WDR2_MAX_GAIN_CX_2 +#define WDR2_MAX_GAIN_CX_2_MASK 0x0000FF00U +#define WDR2_MAX_GAIN_CX_2_SHIFT 8U +/*! Slice: wdr2_max_gain_cx_1:*/ +#define WDR2_MAX_GAIN_CX_1 +#define WDR2_MAX_GAIN_CX_1_MASK 0x000000FFU +#define WDR2_MAX_GAIN_CX_1_SHIFT 0U +/*! Register: isp_wdr2_max_gain_slope_0 (0x000031AC)*/ +/*! Slice: wdr2_max_gain_slope_1:*/ +#define WDR2_MAX_GAIN_SLOPE_1 +#define WDR2_MAX_GAIN_SLOPE_1_MASK 0x0FFF0000U +#define WDR2_MAX_GAIN_SLOPE_1_SHIFT 16U +/*! Slice: wdr2_max_gain_slope_0:*/ +#define WDR2_MAX_GAIN_SLOPE_0 +#define WDR2_MAX_GAIN_SLOPE_0_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_SLOPE_0_SHIFT 0U +/*! Register: isp_wdr2_max_gain_slope_1 (0x000031B0)*/ +/*! Slice: wdr2_max_gain_slope_3:*/ +#define WDR2_MAX_GAIN_SLOPE_3 +#define WDR2_MAX_GAIN_SLOPE_3_MASK 0x0FFF0000U +#define WDR2_MAX_GAIN_SLOPE_3_SHIFT 16U +/*! Slice: wdr2_max_gain_slope_2:*/ +#define WDR2_MAX_GAIN_SLOPE_2 +#define WDR2_MAX_GAIN_SLOPE_2_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_SLOPE_2_SHIFT 0U +/*! Register: isp_wdr2_max_gain_slope_2 (0x000031B4)*/ +/*! Slice: wdr2_max_gain_slope_4:*/ +#define WDR2_MAX_GAIN_SLOPE_4 +#define WDR2_MAX_GAIN_SLOPE_4_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_SLOPE_4_SHIFT 0U +/*! Register: isp_wdr2_max_gain_cy_0 (0x000031B8)*/ +/*! Slice: wdr2_max_gain_cy_1:*/ +#define WDR2_MAX_GAIN_CY_1 +#define WDR2_MAX_GAIN_CY_1_MASK 0x0FFF0000U +#define WDR2_MAX_GAIN_CY_1_SHIFT 16U +/*! Slice: wdr2_max_gain_cy_0:*/ +#define WDR2_MAX_GAIN_CY_0 +#define WDR2_MAX_GAIN_CY_0_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_CY_0_SHIFT 0U +/*! Register: isp_wdr2_max_gain_cy_1 (0x000031BC)*/ +/*! Slice: wdr2_max_gain_cy_3:*/ +#define WDR2_MAX_GAIN_CY_3 +#define WDR2_MAX_GAIN_CY_3_MASK 0x0FFF0000U +#define WDR2_MAX_GAIN_CY_3_SHIFT 16U +/*! Slice: wdr2_max_gain_cy_2:*/ +#define WDR2_MAX_GAIN_CY_2 +#define WDR2_MAX_GAIN_CY_2_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_CY_2_SHIFT 0U +/*! Register: isp_wdr2_max_gain_cy_2 (0x000031C0)*/ +/*! Slice: wdr2_max_gain_cy_5:*/ +#define WDR2_MAX_GAIN_CY_5 +#define WDR2_MAX_GAIN_CY_5_MASK 0x0FFF0000U +#define WDR2_MAX_GAIN_CY_5_SHIFT 16U +/*! Slice: wdr2_max_gain_cy_4:*/ +#define WDR2_MAX_GAIN_CY_4 +#define WDR2_MAX_GAIN_CY_4_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_CY_4_SHIFT 0U +/*! Register: isp_wdr2_norm_factor_mul_0 (0x000031C4)*/ +/*! Slice: wdr2_norm_factor_mul_3:*/ +#define WDR2_NORM_FACTOR_MUL_3 +#define WDR2_NORM_FACTOR_MUL_3_MASK 0xFF000000U +#define WDR2_NORM_FACTOR_MUL_3_SHIFT 24U +/*! Slice: wdr2_norm_factor_mul_2:*/ +#define WDR2_NORM_FACTOR_MUL_2 +#define WDR2_NORM_FACTOR_MUL_2_MASK 0x00FF0000U +#define WDR2_NORM_FACTOR_MUL_2_SHIFT 16U +/*! Slice: wdr2_norm_factor_mul_1:*/ +#define WDR2_NORM_FACTOR_MUL_1 +#define WDR2_NORM_FACTOR_MUL_1_MASK 0x0000FF00U +#define WDR2_NORM_FACTOR_MUL_1_SHIFT 8U +/*! Slice: wdr2_norm_factor_mul_0:*/ +#define WDR2_NORM_FACTOR_MUL_0 +#define WDR2_NORM_FACTOR_MUL_0_MASK 0x000000FFU +#define WDR2_NORM_FACTOR_MUL_0_SHIFT 0U +/*! Register: isp_wdr2_norm_factor_mul_1 (0x000031C8)*/ +/*! Slice: wdr2_norm_factor_mul_7:*/ +#define WDR2_NORM_FACTOR_MUL_7 +#define WDR2_NORM_FACTOR_MUL_7_MASK 0xFF000000U +#define WDR2_NORM_FACTOR_MUL_7_SHIFT 24U +/*! Slice: wdr2_norm_factor_mul_6:*/ +#define WDR2_NORM_FACTOR_MUL_6 +#define WDR2_NORM_FACTOR_MUL_6_MASK 0x00FF0000U +#define WDR2_NORM_FACTOR_MUL_6_SHIFT 16U +/*! Slice: wdr2_norm_factor_mul_5:*/ +#define WDR2_NORM_FACTOR_MUL_5 +#define WDR2_NORM_FACTOR_MUL_5_MASK 0x0000FF00U +#define WDR2_NORM_FACTOR_MUL_5_SHIFT 8U +/*! Slice: wdr2_norm_factor_mul_4:*/ +#define WDR2_NORM_FACTOR_MUL_4 +#define WDR2_NORM_FACTOR_MUL_4_MASK 0x000000FFU +#define WDR2_NORM_FACTOR_MUL_4_SHIFT 0U +/*! Register: isp_wdr2_norm_factor_shift_bit_0 (0x000031CC)*/ +/*! Slice: wdr2_norm_factor_shift_bit_3:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_3 +#define WDR2_NORM_FACTOR_SHIFT_BIT_3_MASK 0xFF000000U +#define WDR2_NORM_FACTOR_SHIFT_BIT_3_SHIFT 24U +/*! Slice: wdr2_norm_factor_shift_bit_2:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_2 +#define WDR2_NORM_FACTOR_SHIFT_BIT_2_MASK 0x00FF0000U +#define WDR2_NORM_FACTOR_SHIFT_BIT_2_SHIFT 16U +/*! Slice: wdr2_norm_factor_shift_bit_1:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_1 +#define WDR2_NORM_FACTOR_SHIFT_BIT_1_MASK 0x0000FF00U +#define WDR2_NORM_FACTOR_SHIFT_BIT_1_SHIFT 8U +/*! Slice: wdr2_norm_factor_shift_bit_0:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_0 +#define WDR2_NORM_FACTOR_SHIFT_BIT_0_MASK 0x000000FFU +#define WDR2_NORM_FACTOR_SHIFT_BIT_0_SHIFT 0U +/*! Register: isp_wdr2_norm_factor_shift_bit_1 (0x000031D0)*/ +/*! Slice: wdr2_norm_factor_shift_bit_7:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_7 +#define WDR2_NORM_FACTOR_SHIFT_BIT_7_MASK 0xFF000000U +#define WDR2_NORM_FACTOR_SHIFT_BIT_7_SHIFT 24U +/*! Slice: wdr2_norm_factor_shift_bit_6:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_6 +#define WDR2_NORM_FACTOR_SHIFT_BIT_6_MASK 0x00FF0000U +#define WDR2_NORM_FACTOR_SHIFT_BIT_6_SHIFT 16U +/*! Slice: wdr2_norm_factor_shift_bit_5:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_5 +#define WDR2_NORM_FACTOR_SHIFT_BIT_5_MASK 0x0000FF00U +#define WDR2_NORM_FACTOR_SHIFT_BIT_5_SHIFT 8U +/*! Slice: wdr2_norm_factor_shift_bit_4:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_4 +#define WDR2_NORM_FACTOR_SHIFT_BIT_4_MASK 0x000000FFU +#define WDR2_NORM_FACTOR_SHIFT_BIT_4_SHIFT 0U +/*! Register: isp_wdr2_bin_range_0 (0x000031D4)*/ +/*! Slice: wdr2_bin_range_2:*/ +#define WDR2_BIN_RANGE_2 +#define WDR2_BIN_RANGE_2_MASK 0x0FFF0000U +#define WDR2_BIN_RANGE_2_SHIFT 16U +/*! Slice: wdr2_bin_range_1:*/ +#define WDR2_BIN_RANGE_1 +#define WDR2_BIN_RANGE_1_MASK 0x00000FFFU +#define WDR2_BIN_RANGE_1_SHIFT 0U +/*! Register: isp_wdr2_bin_range_1 (0x000031D8)*/ +/*! Slice: wdr2_bin_range_4:*/ +#define WDR2_BIN_RANGE_4 +#define WDR2_BIN_RANGE_4_MASK 0x0FFF0000U +#define WDR2_BIN_RANGE_4_SHIFT 16U +/*! Slice: wdr2_bin_range_3:*/ +#define WDR2_BIN_RANGE_3 +#define WDR2_BIN_RANGE_3_MASK 0x00000FFFU +#define WDR2_BIN_RANGE_3_SHIFT 0U +/*! Register: isp_wdr2_bin_range_2 (0x000031DC)*/ +/*! Slice: wdr2_bin_range_6:*/ +#define WDR2_BIN_RANGE_6 +#define WDR2_BIN_RANGE_6_MASK 0x0FFF0000U +#define WDR2_BIN_RANGE_6_SHIFT 16U +/*! Slice: wdr2_bin_range_5:*/ +#define WDR2_BIN_RANGE_5 +#define WDR2_BIN_RANGE_5_MASK 0x00000FFFU +#define WDR2_BIN_RANGE_5_SHIFT 0U +/*! Register: isp_wdr2_bin_range_3 (0x000031E0)*/ +/*! Slice: wdr2_bin_range_8:*/ +#define WDR2_BIN_RANGE_8 +#define WDR2_BIN_RANGE_8_MASK 0x0FFF0000U +#define WDR2_BIN_RANGE_8_SHIFT 16U +/*! Slice: wdr2_bin_range_7:*/ +#define WDR2_BIN_RANGE_7 +#define WDR2_BIN_RANGE_7_MASK 0x00000FFFU +#define WDR2_BIN_RANGE_7_SHIFT 0U +/*! Register: isp_wdr2_hist_data_0 (0x000031E4)*/ +/*! Slice: wdr2_hist_data_3:*/ +#define WDR2_HIST_DATA_3 +#define WDR2_HIST_DATA_3_MASK 0xFF000000U +#define WDR2_HIST_DATA_3_SHIFT 24U +/*! Slice: wdr2_hist_data_2:*/ +#define WDR2_HIST_DATA_2 +#define WDR2_HIST_DATA_2_MASK 0x00FF0000U +#define WDR2_HIST_DATA_2_SHIFT 16U +/*! Slice: wdr2_hist_data_1:*/ +#define WDR2_HIST_DATA_1 +#define WDR2_HIST_DATA_1_MASK 0x0000FF00U +#define WDR2_HIST_DATA_1_SHIFT 8U +/*! Slice: wdr2_hist_data_0:*/ +#define WDR2_HIST_DATA_0 +#define WDR2_HIST_DATA_0_MASK 0x000000FFU +#define WDR2_HIST_DATA_0_SHIFT 0U +/*! Register: isp_wdr2_hist_data_1 (0x000031E8)*/ +/*! Slice: wdr2_hist_data_7:*/ +#define WDR2_HIST_DATA_7 +#define WDR2_HIST_DATA_7_MASK 0xFF000000U +#define WDR2_HIST_DATA_7_SHIFT 24U +/*! Slice: wdr2_hist_data_6:*/ +#define WDR2_HIST_DATA_6 +#define WDR2_HIST_DATA_6_MASK 0x00FF0000U +#define WDR2_HIST_DATA_6_SHIFT 16U +/*! Slice: wdr2_hist_data_5:*/ +#define WDR2_HIST_DATA_5 +#define WDR2_HIST_DATA_5_MASK 0x0000FF00U +#define WDR2_HIST_DATA_5_SHIFT 8U +/*! Slice: wdr2_hist_data_4:*/ +#define WDR2_HIST_DATA_4 +#define WDR2_HIST_DATA_4_MASK 0x000000FFU +#define WDR2_HIST_DATA_4_SHIFT 0U +/*! Register: isp_compand_ctrl (0x00003200)*/ +/*! Slice: compand_ctrl_bls_enable:*/ +#define COMPAND_CTRL_BLS_ENABLE +#define COMPAND_CTRL_BLS_ENABLE_MASK 0x00000008U +#define COMPAND_CTRL_BLS_ENABLE_SHIFT 3U +/*! Slice: compand_ctrl_soft_reset_flag:*/ +#define COMPAND_CTRL_SOFT_RESET_FLAG +#define COMPAND_CTRL_SOFT_RESET_FLAG_MASK 0x00000004U +#define COMPAND_CTRL_SOFT_RESET_FLAG_SHIFT 2U +/*! Slice: compand_ctrl_compress_enable:*/ +#define COMPAND_CTRL_COMPRESS_ENABLE +#define COMPAND_CTRL_COMPRESS_ENABLE_MASK 0x00000002U +#define COMPAND_CTRL_COMPRESS_ENABLE_SHIFT 1U +/*! Slice: compand_ctrl_expand_enable:*/ +#define COMPAND_CTRL_EXPAND_ENABLE +#define COMPAND_CTRL_EXPAND_ENABLE_MASK 0x00000001U +#define COMPAND_CTRL_EXPAND_ENABLE_SHIFT 0U +/*! Register: isp_compand_bls_a_fixed (0x00003204)*/ +/*! Slice: compand_bls_a_fixed:*/ +#define COMPAND_BLS_A_FIXED +#define COMPAND_BLS_A_FIXED_MASK 0x001FFFFFU +#define COMPAND_BLS_A_FIXED_SHIFT 0U +/*! Register: isp_compand_bls_b_fixed (0x00003208)*/ +/*! Slice: compand_bls_b_fixed:*/ +#define COMPAND_BLS_B_FIXED +#define COMPAND_BLS_B_FIXED_MASK 0x001FFFFFU +#define COMPAND_BLS_B_FIXED_SHIFT 0U +/*! Register: isp_compand_bls_c_fixed (0x0000320C)*/ +/*! Slice: compand_bls_c_fixed:*/ +#define COMPAND_BLS_C_FIXED +#define COMPAND_BLS_C_FIXED_MASK 0x001FFFFFU +#define COMPAND_BLS_C_FIXED_SHIFT 0U +/*! Register: isp_compand_bls_d_fixed (0x00003210)*/ +/*! Slice: compand_bls_d_fixed:*/ +#define COMPAND_BLS_D_FIXED +#define COMPAND_BLS_D_FIXED_MASK 0x001FFFFFU +#define COMPAND_BLS_D_FIXED_SHIFT 0U +/*! Register: isp_compand_expand_px_0 (0x00003214)*/ +/*! Slice: compand_expand_px_5:*/ +#define COMPAND_EXPAND_PX_5 +#define COMPAND_EXPAND_PX_5_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_5_SHIFT 25U +/*! Slice: compand_expand_px_4:*/ +#define COMPAND_EXPAND_PX_4 +#define COMPAND_EXPAND_PX_4_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_4_SHIFT 20U +/*! Slice: compand_expand_px_3:*/ +#define COMPAND_EXPAND_PX_3 +#define COMPAND_EXPAND_PX_3_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_3_SHIFT 15U +/*! Slice: compand_expand_px_2:*/ +#define COMPAND_EXPAND_PX_2 +#define COMPAND_EXPAND_PX_2_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_2_SHIFT 10U +/*! Slice: compand_expand_px_1:*/ +#define COMPAND_EXPAND_PX_1 +#define COMPAND_EXPAND_PX_1_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_1_SHIFT 5U +/*! Slice: compand_expand_px_0:*/ +#define COMPAND_EXPAND_PX_0 +#define COMPAND_EXPAND_PX_0_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_0_SHIFT 0U +/*! Register: isp_compand_expand_px_1 (0x00003218)*/ +/*! Slice: compand_expand_px_11:*/ +#define COMPAND_EXPAND_PX_11 +#define COMPAND_EXPAND_PX_11_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_11_SHIFT 25U +/*! Slice: compand_expand_px_10:*/ +#define COMPAND_EXPAND_PX_10 +#define COMPAND_EXPAND_PX_10_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_10_SHIFT 20U +/*! Slice: compand_expand_px_9:*/ +#define COMPAND_EXPAND_PX_9 +#define COMPAND_EXPAND_PX_9_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_9_SHIFT 15U +/*! Slice: compand_expand_px_8:*/ +#define COMPAND_EXPAND_PX_8 +#define COMPAND_EXPAND_PX_8_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_8_SHIFT 10U +/*! Slice: compand_expand_px_7:*/ +#define COMPAND_EXPAND_PX_7 +#define COMPAND_EXPAND_PX_7_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_7_SHIFT 5U +/*! Slice: compand_expand_px_6:*/ +#define COMPAND_EXPAND_PX_6 +#define COMPAND_EXPAND_PX_6_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_6_SHIFT 0U +/*! Register: isp_compand_expand_px_2 (0x0000321C)*/ +/*! Slice: compand_expand_px_17:*/ +#define COMPAND_EXPAND_PX_17 +#define COMPAND_EXPAND_PX_17_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_17_SHIFT 25U +/*! Slice: compand_expand_px_16:*/ +#define COMPAND_EXPAND_PX_16 +#define COMPAND_EXPAND_PX_16_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_16_SHIFT 20U +/*! Slice: compand_expand_px_15:*/ +#define COMPAND_EXPAND_PX_15 +#define COMPAND_EXPAND_PX_15_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_15_SHIFT 15U +/*! Slice: compand_expand_px_14:*/ +#define COMPAND_EXPAND_PX_14 +#define COMPAND_EXPAND_PX_14_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_14_SHIFT 10U +/*! Slice: compand_expand_px_13:*/ +#define COMPAND_EXPAND_PX_13 +#define COMPAND_EXPAND_PX_13_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_13_SHIFT 5U +/*! Slice: compand_expand_px_12:*/ +#define COMPAND_EXPAND_PX_12 +#define COMPAND_EXPAND_PX_12_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_12_SHIFT 0U +/*! Register: isp_compand_expand_px_3 (0x00003220)*/ +/*! Slice: compand_expand_px_23:*/ +#define COMPAND_EXPAND_PX_23 +#define COMPAND_EXPAND_PX_23_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_23_SHIFT 25U +/*! Slice: compand_expand_px_22:*/ +#define COMPAND_EXPAND_PX_22 +#define COMPAND_EXPAND_PX_22_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_22_SHIFT 20U +/*! Slice: compand_expand_px_21:*/ +#define COMPAND_EXPAND_PX_21 +#define COMPAND_EXPAND_PX_21_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_21_SHIFT 15U +/*! Slice: compand_expand_px_20:*/ +#define COMPAND_EXPAND_PX_20 +#define COMPAND_EXPAND_PX_20_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_20_SHIFT 10U +/*! Slice: compand_expand_px_19:*/ +#define COMPAND_EXPAND_PX_19 +#define COMPAND_EXPAND_PX_19_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_19_SHIFT 5U +/*! Slice: compand_expand_px_18:*/ +#define COMPAND_EXPAND_PX_18 +#define COMPAND_EXPAND_PX_18_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_18_SHIFT 0U +/*! Register: isp_compand_expand_px_4 (0x00003224)*/ +/*! Slice: compand_expand_px_29:*/ +#define COMPAND_EXPAND_PX_29 +#define COMPAND_EXPAND_PX_29_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_29_SHIFT 25U +/*! Slice: compand_expand_px_28:*/ +#define COMPAND_EXPAND_PX_28 +#define COMPAND_EXPAND_PX_28_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_28_SHIFT 20U +/*! Slice: compand_expand_px_27:*/ +#define COMPAND_EXPAND_PX_27 +#define COMPAND_EXPAND_PX_27_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_27_SHIFT 15U +/*! Slice: compand_expand_px_26:*/ +#define COMPAND_EXPAND_PX_26 +#define COMPAND_EXPAND_PX_26_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_26_SHIFT 10U +/*! Slice: compand_expand_px_25:*/ +#define COMPAND_EXPAND_PX_25 +#define COMPAND_EXPAND_PX_25_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_25_SHIFT 5U +/*! Slice: compand_expand_px_24:*/ +#define COMPAND_EXPAND_PX_24 +#define COMPAND_EXPAND_PX_24_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_24_SHIFT 0U +/*! Register: isp_compand_expand_px_5 (0x00003228)*/ +/*! Slice: compand_expand_px_35:*/ +#define COMPAND_EXPAND_PX_35 +#define COMPAND_EXPAND_PX_35_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_35_SHIFT 25U +/*! Slice: compand_expand_px_34:*/ +#define COMPAND_EXPAND_PX_34 +#define COMPAND_EXPAND_PX_34_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_34_SHIFT 20U +/*! Slice: compand_expand_px_33:*/ +#define COMPAND_EXPAND_PX_33 +#define COMPAND_EXPAND_PX_33_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_33_SHIFT 15U +/*! Slice: compand_expand_px_32:*/ +#define COMPAND_EXPAND_PX_32 +#define COMPAND_EXPAND_PX_32_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_32_SHIFT 10U +/*! Slice: compand_expand_px_31:*/ +#define COMPAND_EXPAND_PX_31 +#define COMPAND_EXPAND_PX_31_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_31_SHIFT 5U +/*! Slice: compand_expand_px_30:*/ +#define COMPAND_EXPAND_PX_30 +#define COMPAND_EXPAND_PX_30_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_30_SHIFT 0U +/*! Register: isp_compand_expand_px_6 (0x0000322C)*/ +/*! Slice: compand_expand_px_41:*/ +#define COMPAND_EXPAND_PX_41 +#define COMPAND_EXPAND_PX_41_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_41_SHIFT 25U +/*! Slice: compand_expand_px_40:*/ +#define COMPAND_EXPAND_PX_40 +#define COMPAND_EXPAND_PX_40_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_40_SHIFT 20U +/*! Slice: compand_expand_px_39:*/ +#define COMPAND_EXPAND_PX_39 +#define COMPAND_EXPAND_PX_39_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_39_SHIFT 15U +/*! Slice: compand_expand_px_38:*/ +#define COMPAND_EXPAND_PX_38 +#define COMPAND_EXPAND_PX_38_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_38_SHIFT 10U +/*! Slice: compand_expand_px_37:*/ +#define COMPAND_EXPAND_PX_37 +#define COMPAND_EXPAND_PX_37_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_37_SHIFT 5U +/*! Slice: compand_expand_px_36:*/ +#define COMPAND_EXPAND_PX_36 +#define COMPAND_EXPAND_PX_36_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_36_SHIFT 0U +/*! Register: isp_compand_expand_px_7 (0x00003230)*/ +/*! Slice: compand_expand_px_47:*/ +#define COMPAND_EXPAND_PX_47 +#define COMPAND_EXPAND_PX_47_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_47_SHIFT 25U +/*! Slice: compand_expand_px_46:*/ +#define COMPAND_EXPAND_PX_46 +#define COMPAND_EXPAND_PX_46_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_46_SHIFT 20U +/*! Slice: compand_expand_px_45:*/ +#define COMPAND_EXPAND_PX_45 +#define COMPAND_EXPAND_PX_45_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_45_SHIFT 15U +/*! Slice: compand_expand_px_44:*/ +#define COMPAND_EXPAND_PX_44 +#define COMPAND_EXPAND_PX_44_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_44_SHIFT 10U +/*! Slice: compand_expand_px_43:*/ +#define COMPAND_EXPAND_PX_43 +#define COMPAND_EXPAND_PX_43_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_43_SHIFT 5U +/*! Slice: compand_expand_px_42:*/ +#define COMPAND_EXPAND_PX_42 +#define COMPAND_EXPAND_PX_42_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_42_SHIFT 0U +/*! Register: isp_compand_expand_px_8 (0x00003234)*/ +/*! Slice: compand_expand_px_53:*/ +#define COMPAND_EXPAND_PX_53 +#define COMPAND_EXPAND_PX_53_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_53_SHIFT 25U +/*! Slice: compand_expand_px_52:*/ +#define COMPAND_EXPAND_PX_52 +#define COMPAND_EXPAND_PX_52_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_52_SHIFT 20U +/*! Slice: compand_expand_px_51:*/ +#define COMPAND_EXPAND_PX_51 +#define COMPAND_EXPAND_PX_51_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_51_SHIFT 15U +/*! Slice: compand_expand_px_50:*/ +#define COMPAND_EXPAND_PX_50 +#define COMPAND_EXPAND_PX_50_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_50_SHIFT 10U +/*! Slice: compand_expand_px_49:*/ +#define COMPAND_EXPAND_PX_49 +#define COMPAND_EXPAND_PX_49_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_49_SHIFT 5U +/*! Slice: compand_expand_px_48:*/ +#define COMPAND_EXPAND_PX_48 +#define COMPAND_EXPAND_PX_48_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_48_SHIFT 0U +/*! Register: isp_compand_expand_px_9 (0x00003238)*/ +/*! Slice: compand_expand_px_59:*/ +#define COMPAND_EXPAND_PX_59 +#define COMPAND_EXPAND_PX_59_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_59_SHIFT 25U +/*! Slice: compand_expand_px_58:*/ +#define COMPAND_EXPAND_PX_58 +#define COMPAND_EXPAND_PX_58_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_58_SHIFT 20U +/*! Slice: compand_expand_px_57:*/ +#define COMPAND_EXPAND_PX_57 +#define COMPAND_EXPAND_PX_57_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_57_SHIFT 15U +/*! Slice: compand_expand_px_56:*/ +#define COMPAND_EXPAND_PX_56 +#define COMPAND_EXPAND_PX_56_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_56_SHIFT 10U +/*! Slice: compand_expand_px_55:*/ +#define COMPAND_EXPAND_PX_55 +#define COMPAND_EXPAND_PX_55_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_55_SHIFT 5U +/*! Slice: compand_expand_px_54:*/ +#define COMPAND_EXPAND_PX_54 +#define COMPAND_EXPAND_PX_54_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_54_SHIFT 0U +/*! Register: isp_compand_expand_px_10 (0x0000323C)*/ +/*! Slice: compand_expand_px_63:*/ +#define COMPAND_EXPAND_PX_63 +#define COMPAND_EXPAND_PX_63_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_63_SHIFT 15U +/*! Slice: compand_expand_px_62:*/ +#define COMPAND_EXPAND_PX_62 +#define COMPAND_EXPAND_PX_62_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_62_SHIFT 10U +/*! Slice: compand_expand_px_61:*/ +#define COMPAND_EXPAND_PX_61 +#define COMPAND_EXPAND_PX_61_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_61_SHIFT 5U +/*! Slice: compand_expand_px_60:*/ +#define COMPAND_EXPAND_PX_60 +#define COMPAND_EXPAND_PX_60_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_60_SHIFT 0U +/*! Register: isp_compand_compress_px_0 (0x00003240)*/ +/*! Slice: compand_compress_px_5:*/ +#define COMPAND_COMPRESS_PX_5 +#define COMPAND_COMPRESS_PX_5_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_5_SHIFT 25U +/*! Slice: compand_compress_px_4:*/ +#define COMPAND_COMPRESS_PX_4 +#define COMPAND_COMPRESS_PX_4_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_4_SHIFT 20U +/*! Slice: compand_compress_px_3:*/ +#define COMPAND_COMPRESS_PX_3 +#define COMPAND_COMPRESS_PX_3_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_3_SHIFT 15U +/*! Slice: compand_compress_px_2:*/ +#define COMPAND_COMPRESS_PX_2 +#define COMPAND_COMPRESS_PX_2_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_2_SHIFT 10U +/*! Slice: compand_compress_px_1:*/ +#define COMPAND_COMPRESS_PX_1 +#define COMPAND_COMPRESS_PX_1_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_1_SHIFT 5U +/*! Slice: compand_compress_px_0:*/ +#define COMPAND_COMPRESS_PX_0 +#define COMPAND_COMPRESS_PX_0_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_0_SHIFT 0U +/*! Register: isp_compand_compress_px_1 (0x00003244)*/ +/*! Slice: compand_compress_px_11:*/ +#define COMPAND_COMPRESS_PX_11 +#define COMPAND_COMPRESS_PX_11_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_11_SHIFT 25U +/*! Slice: compand_compress_px_10:*/ +#define COMPAND_COMPRESS_PX_10 +#define COMPAND_COMPRESS_PX_10_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_10_SHIFT 20U +/*! Slice: compand_compress_px_9:*/ +#define COMPAND_COMPRESS_PX_9 +#define COMPAND_COMPRESS_PX_9_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_9_SHIFT 15U +/*! Slice: compand_compress_px_8:*/ +#define COMPAND_COMPRESS_PX_8 +#define COMPAND_COMPRESS_PX_8_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_8_SHIFT 10U +/*! Slice: compand_compress_px_7:*/ +#define COMPAND_COMPRESS_PX_7 +#define COMPAND_COMPRESS_PX_7_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_7_SHIFT 5U +/*! Slice: compand_compress_px_6:*/ +#define COMPAND_COMPRESS_PX_6 +#define COMPAND_COMPRESS_PX_6_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_6_SHIFT 0U +/*! Register: isp_compand_compress_px_2 (0x00003248)*/ +/*! Slice: compand_compress_px_17:*/ +#define COMPAND_COMPRESS_PX_17 +#define COMPAND_COMPRESS_PX_17_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_17_SHIFT 25U +/*! Slice: compand_compress_px_16:*/ +#define COMPAND_COMPRESS_PX_16 +#define COMPAND_COMPRESS_PX_16_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_16_SHIFT 20U +/*! Slice: compand_compress_px_15:*/ +#define COMPAND_COMPRESS_PX_15 +#define COMPAND_COMPRESS_PX_15_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_15_SHIFT 15U +/*! Slice: compand_compress_px_14:*/ +#define COMPAND_COMPRESS_PX_14 +#define COMPAND_COMPRESS_PX_14_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_14_SHIFT 10U +/*! Slice: compand_compress_px_13:*/ +#define COMPAND_COMPRESS_PX_13 +#define COMPAND_COMPRESS_PX_13_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_13_SHIFT 5U +/*! Slice: compand_compress_px_12:*/ +#define COMPAND_COMPRESS_PX_12 +#define COMPAND_COMPRESS_PX_12_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_12_SHIFT 0U +/*! Register: isp_compand_compress_px_3 (0x0000324C)*/ +/*! Slice: compand_compress_px_23:*/ +#define COMPAND_COMPRESS_PX_23 +#define COMPAND_COMPRESS_PX_23_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_23_SHIFT 25U +/*! Slice: compand_compress_px_22:*/ +#define COMPAND_COMPRESS_PX_22 +#define COMPAND_COMPRESS_PX_22_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_22_SHIFT 20U +/*! Slice: compand_compress_px_21:*/ +#define COMPAND_COMPRESS_PX_21 +#define COMPAND_COMPRESS_PX_21_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_21_SHIFT 15U +/*! Slice: compand_compress_px_20:*/ +#define COMPAND_COMPRESS_PX_20 +#define COMPAND_COMPRESS_PX_20_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_20_SHIFT 10U +/*! Slice: compand_compress_px_19:*/ +#define COMPAND_COMPRESS_PX_19 +#define COMPAND_COMPRESS_PX_19_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_19_SHIFT 5U +/*! Slice: compand_compress_px_18:*/ +#define COMPAND_COMPRESS_PX_18 +#define COMPAND_COMPRESS_PX_18_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_18_SHIFT 0U +/*! Register: isp_compand_compress_px_4 (0x00003250)*/ +/*! Slice: compand_compress_px_29:*/ +#define COMPAND_COMPRESS_PX_29 +#define COMPAND_COMPRESS_PX_29_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_29_SHIFT 25U +/*! Slice: compand_compress_px_28:*/ +#define COMPAND_COMPRESS_PX_28 +#define COMPAND_COMPRESS_PX_28_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_28_SHIFT 20U +/*! Slice: compand_compress_px_27:*/ +#define COMPAND_COMPRESS_PX_27 +#define COMPAND_COMPRESS_PX_27_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_27_SHIFT 15U +/*! Slice: compand_compress_px_26:*/ +#define COMPAND_COMPRESS_PX_26 +#define COMPAND_COMPRESS_PX_26_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_26_SHIFT 10U +/*! Slice: compand_compress_px_25:*/ +#define COMPAND_COMPRESS_PX_25 +#define COMPAND_COMPRESS_PX_25_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_25_SHIFT 5U +/*! Slice: compand_compress_px_24:*/ +#define COMPAND_COMPRESS_PX_24 +#define COMPAND_COMPRESS_PX_24_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_24_SHIFT 0U +/*! Register: isp_compand_compress_px_5 (0x00003254)*/ +/*! Slice: compand_compress_px_35:*/ +#define COMPAND_COMPRESS_PX_35 +#define COMPAND_COMPRESS_PX_35_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_35_SHIFT 25U +/*! Slice: compand_compress_px_34:*/ +#define COMPAND_COMPRESS_PX_34 +#define COMPAND_COMPRESS_PX_34_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_34_SHIFT 20U +/*! Slice: compand_compress_px_33:*/ +#define COMPAND_COMPRESS_PX_33 +#define COMPAND_COMPRESS_PX_33_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_33_SHIFT 15U +/*! Slice: compand_compress_px_32:*/ +#define COMPAND_COMPRESS_PX_32 +#define COMPAND_COMPRESS_PX_32_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_32_SHIFT 10U +/*! Slice: compand_compress_px_31:*/ +#define COMPAND_COMPRESS_PX_31 +#define COMPAND_COMPRESS_PX_31_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_31_SHIFT 5U +/*! Slice: compand_compress_px_30:*/ +#define COMPAND_COMPRESS_PX_30 +#define COMPAND_COMPRESS_PX_30_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_30_SHIFT 0U +/*! Register: isp_compand_compress_px_6 (0x00003258)*/ +/*! Slice: compand_compress_px_41:*/ +#define COMPAND_COMPRESS_PX_41 +#define COMPAND_COMPRESS_PX_41_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_41_SHIFT 25U +/*! Slice: compand_compress_px_40:*/ +#define COMPAND_COMPRESS_PX_40 +#define COMPAND_COMPRESS_PX_40_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_40_SHIFT 20U +/*! Slice: compand_compress_px_39:*/ +#define COMPAND_COMPRESS_PX_39 +#define COMPAND_COMPRESS_PX_39_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_39_SHIFT 15U +/*! Slice: compand_compress_px_38:*/ +#define COMPAND_COMPRESS_PX_38 +#define COMPAND_COMPRESS_PX_38_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_38_SHIFT 10U +/*! Slice: compand_compress_px_37:*/ +#define COMPAND_COMPRESS_PX_37 +#define COMPAND_COMPRESS_PX_37_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_37_SHIFT 5U +/*! Slice: compand_compress_px_36:*/ +#define COMPAND_COMPRESS_PX_36 +#define COMPAND_COMPRESS_PX_36_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_36_SHIFT 0U +/*! Register: isp_compand_compress_px_7 (0x0000325C)*/ +/*! Slice: compand_compress_px_47:*/ +#define COMPAND_COMPRESS_PX_47 +#define COMPAND_COMPRESS_PX_47_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_47_SHIFT 25U +/*! Slice: compand_compress_px_46:*/ +#define COMPAND_COMPRESS_PX_46 +#define COMPAND_COMPRESS_PX_46_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_46_SHIFT 20U +/*! Slice: compand_compress_px_45:*/ +#define COMPAND_COMPRESS_PX_45 +#define COMPAND_COMPRESS_PX_45_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_45_SHIFT 15U +/*! Slice: compand_compress_px_44:*/ +#define COMPAND_COMPRESS_PX_44 +#define COMPAND_COMPRESS_PX_44_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_44_SHIFT 10U +/*! Slice: compand_compress_px_43:*/ +#define COMPAND_COMPRESS_PX_43 +#define COMPAND_COMPRESS_PX_43_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_43_SHIFT 5U +/*! Slice: compand_compress_px_42:*/ +#define COMPAND_COMPRESS_PX_42 +#define COMPAND_COMPRESS_PX_42_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_42_SHIFT 0U +/*! Register: isp_compand_compress_px_8 (0x00003260)*/ +/*! Slice: compand_compress_px_53:*/ +#define COMPAND_COMPRESS_PX_53 +#define COMPAND_COMPRESS_PX_53_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_53_SHIFT 25U +/*! Slice: compand_compress_px_52:*/ +#define COMPAND_COMPRESS_PX_52 +#define COMPAND_COMPRESS_PX_52_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_52_SHIFT 20U +/*! Slice: compand_compress_px_51:*/ +#define COMPAND_COMPRESS_PX_51 +#define COMPAND_COMPRESS_PX_51_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_51_SHIFT 15U +/*! Slice: compand_compress_px_50:*/ +#define COMPAND_COMPRESS_PX_50 +#define COMPAND_COMPRESS_PX_50_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_50_SHIFT 10U +/*! Slice: compand_compress_px_49:*/ +#define COMPAND_COMPRESS_PX_49 +#define COMPAND_COMPRESS_PX_49_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_49_SHIFT 5U +/*! Slice: compand_compress_px_48:*/ +#define COMPAND_COMPRESS_PX_48 +#define COMPAND_COMPRESS_PX_48_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_48_SHIFT 0U +/*! Register: isp_compand_compress_px_9 (0x00003264)*/ +/*! Slice: compand_compress_px_59:*/ +#define COMPAND_COMPRESS_PX_59 +#define COMPAND_COMPRESS_PX_59_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_59_SHIFT 25U +/*! Slice: compand_compress_px_58:*/ +#define COMPAND_COMPRESS_PX_58 +#define COMPAND_COMPRESS_PX_58_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_58_SHIFT 20U +/*! Slice: compand_compress_px_57:*/ +#define COMPAND_COMPRESS_PX_57 +#define COMPAND_COMPRESS_PX_57_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_57_SHIFT 15U +/*! Slice: compand_compress_px_56:*/ +#define COMPAND_COMPRESS_PX_56 +#define COMPAND_COMPRESS_PX_56_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_56_SHIFT 10U +/*! Slice: compand_compress_px_55:*/ +#define COMPAND_COMPRESS_PX_55 +#define COMPAND_COMPRESS_PX_55_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_55_SHIFT 5U +/*! Slice: compand_compress_px_54:*/ +#define COMPAND_COMPRESS_PX_54 +#define COMPAND_COMPRESS_PX_54_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_54_SHIFT 0U +/*! Register: isp_compand_compress_px_10 (0x00003268)*/ +/*! Slice: compand_compress_px_63:*/ +#define COMPAND_COMPRESS_PX_63 +#define COMPAND_COMPRESS_PX_63_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_63_SHIFT 15U +/*! Slice: compand_compress_px_62:*/ +#define COMPAND_COMPRESS_PX_62 +#define COMPAND_COMPRESS_PX_62_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_62_SHIFT 10U +/*! Slice: compand_compress_px_61:*/ +#define COMPAND_COMPRESS_PX_61 +#define COMPAND_COMPRESS_PX_61_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_61_SHIFT 5U +/*! Slice: compand_compress_px_60:*/ +#define COMPAND_COMPRESS_PX_60 +#define COMPAND_COMPRESS_PX_60_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_60_SHIFT 0U +/*! Register: isp_compand_expand_y_addr (0x0000326C)*/ +/*! Slice: compand_expand_y_addr:*/ +#define COMPAND_EXPAND_Y_ADDR +#define COMPAND_EXPAND_Y_ADDR_MASK 0xFFFFFFFFU +#define COMPAND_EXPAND_Y_ADDR_SHIFT 0U +/*! Register: isp_compand_expand_y_write_data (0x00003270)*/ +/*! Slice: compand_expand_y_write_data:*/ +#define COMPAND_EXPAND_Y_WRITE_DATA +#define COMPAND_EXPAND_Y_WRITE_DATA_MASK 0x000FFFFFU +#define COMPAND_EXPAND_Y_WRITE_DATA_SHIFT 0U +/*! Register: isp_compand_compress_y_addr (0x00003274)*/ +/*! Slice: compand_compress_y_addr:*/ +#define COMPAND_COMPRESS_Y_ADDR +#define COMPAND_COMPRESS_Y_ADDR_MASK 0xFFFFFFFFU +#define COMPAND_COMPRESS_Y_ADDR_SHIFT 0U +/*! Register: isp_compand_compress_y_write_data (0x00003278)*/ +/*! Slice: compand_compress_y_write_data:*/ +#define COMPAND_COMPRESS_Y_WRITE_DATA +#define COMPAND_COMPRESS_Y_WRITE_DATA_MASK 0x0000FFFFU +#define COMPAND_COMPRESS_Y_WRITE_DATA_SHIFT 0U +/*! Register: isp_compand_expand_x_addr (0x0000327C)*/ +/*! Slice: compand_expand_x_addr:*/ +#define COMPAND_EXPAND_X_ADDR +#define COMPAND_EXPAND_X_ADDR_MASK 0xFFFFFFFFU +#define COMPAND_EXPAND_X_ADDR_SHIFT 0U +/*! Register: isp_compand_expand_x_write_data (0x00003280)*/ +/*! Slice: compand_expand_x_write_data:*/ +#define COMPAND_EXPAND_X_WRITE_DATA +#define COMPAND_EXPAND_X_WRITE_DATA_MASK 0x000FFFFFU +#define COMPAND_EXPAND_X_WRITE_DATA_SHIFT 0U +/*! Register: isp_compand_compress_x_addr (0x00003284)*/ +/*! Slice: compand_compress_x_addr:*/ +#define COMPAND_COMPRESS_X_ADDR +#define COMPAND_COMPRESS_X_ADDR_MASK 0xFFFFFFFFU +#define COMPAND_COMPRESS_X_ADDR_SHIFT 0U +/*! Register: isp_compand_compress_x_write_data (0x00003288)*/ +/*! Slice: compand_compress_x_write_data:*/ +#define COMPAND_COMPRESS_X_WRITE_DATA +#define COMPAND_COMPRESS_X_WRITE_DATA_MASK 0x000FFFFFU +#define COMPAND_COMPRESS_X_WRITE_DATA_SHIFT 0U +/*! Register: isp_wdr3_ctrl (0x00003500)*/ +/*! Slice: wdr3_dummmy_blk:*/ +#define WDR3_DUMMY_BLK +#define WDR3_DUMMY_BLK_MASK 0xffff0000U +#define WDR3_DUMMY_BLK_SHIFT 16U +/*! Register: isp_wdr3_ctrl (0x00003500)*/ +/*! Slice: wdr3_dummy_blk_en:*/ +#define WDR3_DUMMY_BLK_EN +#define WDR3_DUMMY_BLK_EN_MASK 0x00008000U +#define WDR3_DUMMY_BLK_EN_SHIFT 15U +/*! Register: isp_wdr3_ctrl (0x00003500)*/ +/*! Slice: wdr3_interrupt_en:*/ +#define WDR3_INTERRUPT_EN +#define WDR3_INTERRUPT_EN_MASK 0x00000200U +#define WDR3_INTERRUPT_EN_SHIFT 9U +/*! Slice: wdr3_soft_reset_flag:*/ +#define WDR3_SOFT_RESET_FLAG +#define WDR3_SOFT_RESET_FLAG_MASK 0x00000002U +#define WDR3_SOFT_RESET_FLAG_SHIFT 1U +/*! Slice: wdr3_enable:*/ +#define WDR3_ENABLE +#define WDR3_ENABLE_MASK 0x00000001U +#define WDR3_ENABLE_SHIFT 0U +/*! Register: isp_wdr3_shift (0x00003504)*/ +/*! Slice: wdr3_gain_shift_bit:*/ +#define WDR3_GAIN_SHIFT_BIT +#define WDR3_GAIN_SHIFT_BIT_MASK 0x00FC0000U +#define WDR3_GAIN_SHIFT_BIT_SHIFT 18U +/*! Slice: wdr3_normalize_shift_bit:*/ +#define WDR3_NORMALIZE_SHIFT_BIT +#define WDR3_NORMALIZE_SHIFT_BIT_MASK 0x0003F000U +#define WDR3_NORMALIZE_SHIFT_BIT_SHIFT 12U +/*! Slice: wdr3_output_shift_bit:*/ +#define WDR3_OUTPUT_SHIFT_BIT +#define WDR3_OUTPUT_SHIFT_BIT_MASK 0x00000FC0U +#define WDR3_OUTPUT_SHIFT_BIT_SHIFT 6U +/*! Slice: wdr3_pixel_shift_bit:*/ +#define WDR3_PIXEL_SHIFT_BIT +#define WDR3_PIXEL_SHIFT_BIT_MASK 0x0000003FU +#define WDR3_PIXEL_SHIFT_BIT_SHIFT 0U +/*! Register: isp_wdr3_block_size (0x00003508)*/ +/*! Slice: wdr3_block_height:*/ +#define WDR3_BLOCK_HEIGHT +#define WDR3_BLOCK_HEIGHT_MASK 0x0003FE00U +#define WDR3_BLOCK_HEIGHT_SHIFT 9U +/*! Slice: wdr3_block_width:*/ +#define WDR3_BLOCK_WIDTH +#define WDR3_BLOCK_WIDTH_MASK 0x000001FFU +#define WDR3_BLOCK_WIDTH_SHIFT 0U +/*! Register: isp_wdr3_block_area_factor (0x0000350C)*/ +/*! Slice: wdr3_block_area_inverse:*/ +#define WDR3_BLOCK_AREA_INVERSE +#define WDR3_BLOCK_AREA_INVERSE_MASK 0x000FFFFFU +#define WDR3_BLOCK_AREA_INVERSE_SHIFT 0U +/*! Register: isp_wdr3_value_weight (0x00003510)*/ +/*! Slice: wdr3_value_weight_3:*/ +#define WDR3_VALUE_WEIGHT_3 +#define WDR3_VALUE_WEIGHT_3_MASK 0x000F8000U +#define WDR3_VALUE_WEIGHT_3_SHIFT 15U +/*! Slice: wdr3_value_weight_2:*/ +#define WDR3_VALUE_WEIGHT_2 +#define WDR3_VALUE_WEIGHT_2_MASK 0x00007C00U +#define WDR3_VALUE_WEIGHT_2_SHIFT 10U +/*! Slice: wdr3_value_weight_1:*/ +#define WDR3_VALUE_WEIGHT_1 +#define WDR3_VALUE_WEIGHT_1_MASK 0x000003E0U +#define WDR3_VALUE_WEIGHT_1_SHIFT 5U +/*! Slice: wdr3_value_weight_0:*/ +#define WDR3_VALUE_WEIGHT_0 +#define WDR3_VALUE_WEIGHT_0_MASK 0x0000001FU +#define WDR3_VALUE_WEIGHT_0_SHIFT 0U +/*! Register: isp_wdr3_strength (0x00003514)*/ +/*! Slice: wdr3_total_strength:*/ +#define WDR3_TOTAL_STRENGTH +#define WDR3_TOTAL_STRENGTH_MASK 0xFF000000U +#define WDR3_TOTAL_STRENGTH_SHIFT 24U +/*! Slice: wdr3_local_strength:*/ +#define WDR3_LOCAL_STRENGTH +#define WDR3_LOCAL_STRENGTH_MASK 0x00FF0000U +#define WDR3_LOCAL_STRENGTH_SHIFT 16U +/*! Slice: wdr3_global_strength:*/ +#define WDR3_GLOBAL_STRENGTH +#define WDR3_GLOBAL_STRENGTH_MASK 0x0000FF00U +#define WDR3_GLOBAL_STRENGTH_SHIFT 8U +/*! Slice: wdr3_maximum_gain:*/ +#define WDR3_MAXIMUM_GAIN +#define WDR3_MAXIMUM_GAIN_MASK 0x000000FFU +#define WDR3_MAXIMUM_GAIN_SHIFT 0U +/*! Register: isp_wdr3_pixel_slope (0x00003518)*/ +/*! Slice: wdr3_pixel_merge_slope:*/ +#define WDR3_PIXEL_MERGE_SLOPE +#define WDR3_PIXEL_MERGE_SLOPE_MASK 0xFF000000U +#define WDR3_PIXEL_MERGE_SLOPE_SHIFT 24U +/*! Slice: wdr3_pixel_merge_base:*/ +#define WDR3_PIXEL_MERGE_BASE +#define WDR3_PIXEL_MERGE_BASE_MASK 0x00FF0000U +#define WDR3_PIXEL_MERGE_BASE_SHIFT 16U +/*! Slice: wdr3_pixel_adjust_slope:*/ +#define WDR3_PIXEL_ADJUST_SLOPE +#define WDR3_PIXEL_ADJUST_SLOPE_MASK 0x0000FF00U +#define WDR3_PIXEL_ADJUST_SLOPE_SHIFT 8U +/*! Slice: wdr3_pixel_adjust_base:*/ +#define WDR3_PIXEL_ADJUST_BASE +#define WDR3_PIXEL_ADJUST_BASE_MASK 0x000000FFU +#define WDR3_PIXEL_ADJUST_BASE_SHIFT 0U +/*! Register: isp_wdr3_entropy_slope (0x0000351C)*/ +/*! Slice: wdr3_entropy_slope:*/ +#define WDR3_ENTROPY_SLOPE +#define WDR3_ENTROPY_SLOPE_MASK 0x000FFC00U +#define WDR3_ENTROPY_SLOPE_SHIFT 10U +/*! Slice: wdr3_entropy_base:*/ +#define WDR3_ENTROPY_BASE +#define WDR3_ENTROPY_BASE_MASK 0x000003FFU +#define WDR3_ENTROPY_BASE_SHIFT 0U +/*! Register: isp_wdr3_sigma_width (0x00003520)*/ +/*! Slice: wdr3_biliteral_width_sigma:*/ +#define WDR3_BILITERAL_WIDTH_SIGMA +#define WDR3_BILITERAL_WIDTH_SIGMA_MASK 0x000FFFFFU +#define WDR3_BILITERAL_WIDTH_SIGMA_SHIFT 0U +/*! Register: isp_wdr3_sigma_height (0x00003524)*/ +/*! Slice: wdr3_biliteral_height_sigma:*/ +#define WDR3_BILITERAL_HEIGHT_SIGMA +#define WDR3_BILITERAL_HEIGHT_SIGMA_MASK 0x000FFFFFU +#define WDR3_BILITERAL_HEIGHT_SIGMA_SHIFT 0U +/*! Register: isp_wdr3_sigma_value (0x00003528)*/ +/*! Slice: wdr3_biliteral_value_sigma:*/ +#define WDR3_BILITERAL_VALUE_SIGMA +#define WDR3_BILITERAL_VALUE_SIGMA_MASK 0x000FFFFFU +#define WDR3_BILITERAL_VALUE_SIGMA_SHIFT 0U +/*! Register: isp_wdr3_block_flag_width (0x0000352C)*/ +/*! Slice: wdr3_block_col_flag:*/ +#define WDR3_BLOCK_COL_FLAG +#define WDR3_BLOCK_COL_FLAG_MASK 0xFFFFFFFFU +#define WDR3_BLOCK_COL_FLAG_SHIFT 0U +/*! Register: isp_wdr3_block_flag_height (0x00003530)*/ +/*! Slice: wdr3_block_row_flag:*/ +#define WDR3_BLOCK_ROW_FLAG +#define WDR3_BLOCK_ROW_FLAG_MASK 0xFFFFFFFFU +#define WDR3_BLOCK_ROW_FLAG_SHIFT 0U +/*! Register: isp_wdr3_frame_average (0x00003534)*/ +/*! Slice: wdr3_frame_average:*/ +#define WDR3_FRAME_AVERAGE +#define WDR3_FRAME_AVERAGE_MASK 0xFFFFFFFFU +#define WDR3_FRAME_AVERAGE_SHIFT 0U +/*! Register: isp_wdr3_frame_std (0x00003538)*/ +/*! Slice: wdr3_frame_std:*/ +#define WDR3_FRAME_STD +#define WDR3_FRAME_STD_MASK 0xFFFFFFFFU +#define WDR3_FRAME_STD_SHIFT 0U +/*! Register: isp_wdr3_histogram_0 (0x0000353C)*/ +/*! Slice: wdr3_histogram_curve0:*/ +#define WDR3_HISTOGRAM_CURVE0 +#define WDR3_HISTOGRAM_CURVE0_MASK 0x3FF00000U +#define WDR3_HISTOGRAM_CURVE0_SHIFT 20U +/*! Slice: wdr3_histogram_curve1:*/ +#define WDR3_HISTOGRAM_CURVE1 +#define WDR3_HISTOGRAM_CURVE1_MASK 0x000FFC00U +#define WDR3_HISTOGRAM_CURVE1_SHIFT 10U +/*! Slice: wdr3_histogram_curve2:*/ +#define WDR3_HISTOGRAM_CURVE2 +#define WDR3_HISTOGRAM_CURVE2_MASK 0x000003FFU +#define WDR3_HISTOGRAM_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_entropy_0 (0x00003550)*/ +/*! Slice: wdr3_entropy_convert0:*/ +#define WDR3_ENTROPY_CONVERT0 +#define WDR3_ENTROPY_CONVERT0_MASK 0x07FC0000U +#define WDR3_ENTROPY_CONVERT0_SHIFT 18U +/*! Slice: wdr3_entropy_convert1:*/ +#define WDR3_ENTROPY_CONVERT1 +#define WDR3_ENTROPY_CONVERT1_MASK 0x0003FE00U +#define WDR3_ENTROPY_CONVERT1_SHIFT 9U +/*! Slice: wdr3_entropy_convert2:*/ +#define WDR3_ENTROPY_CONVERT2 +#define WDR3_ENTROPY_CONVERT2_MASK 0x000001FFU +#define WDR3_ENTROPY_CONVERT2_SHIFT 0U +/*! Register: isp_wdr3_gamma_pre_0 (0x00003564)*/ +/*! Slice: wdr3_gamma_pre_curve0:*/ +#define WDR3_GAMMA_PRE_CURVE0 +#define WDR3_GAMMA_PRE_CURVE0_MASK 0x3FF00000U +#define WDR3_GAMMA_PRE_CURVE0_SHIFT 20U +/*! Slice: wdr3_gamma_pre_curve1:*/ +#define WDR3_GAMMA_PRE_CURVE1 +#define WDR3_GAMMA_PRE_CURVE1_MASK 0x000FFC00U +#define WDR3_GAMMA_PRE_CURVE1_SHIFT 10U +/*! Slice: wdr3_gamma_pre_curve2:*/ +#define WDR3_GAMMA_PRE_CURVE2 +#define WDR3_GAMMA_PRE_CURVE2_MASK 0x000003FFU +#define WDR3_GAMMA_PRE_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_gamma_up_0 (0x00003578)*/ +/*! Slice: wdr3_gamma_up_curve0:*/ +#define WDR3_GAMMA_UP_CURVE0 +#define WDR3_GAMMA_UP_CURVE0_MASK 0x3FF00000U +#define WDR3_GAMMA_UP_CURVE0_SHIFT 20U +/*! Slice: wdr3_gamma_up_curve1:*/ +#define WDR3_GAMMA_UP_CURVE1 +#define WDR3_GAMMA_UP_CURVE1_MASK 0x000FFC00U +#define WDR3_GAMMA_UP_CURVE1_SHIFT 10U +/*! Slice: wdr3_gamma_up_curve2:*/ +#define WDR3_GAMMA_UP_CURVE2 +#define WDR3_GAMMA_UP_CURVE2_MASK 0x000003FFU +#define WDR3_GAMMA_UP_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_gamma_down_0 (0x0000358C)*/ +/*! Slice: wdr3_gamma_down_curve0:*/ +#define WDR3_GAMMA_DOWN_CURVE0 +#define WDR3_GAMMA_DOWN_CURVE0_MASK 0x3FF00000U +#define WDR3_GAMMA_DOWN_CURVE0_SHIFT 20U +/*! Slice: wdr3_gamma_down_curve1:*/ +#define WDR3_GAMMA_DOWN_CURVE1 +#define WDR3_GAMMA_DOWN_CURVE1_MASK 0x000FFC00U +#define WDR3_GAMMA_DOWN_CURVE1_SHIFT 10U +/*! Slice: wdr3_gamma_down_curve2:*/ +#define WDR3_GAMMA_DOWN_CURVE2 +#define WDR3_GAMMA_DOWN_CURVE2_MASK 0x000003FFU +#define WDR3_GAMMA_DOWN_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_distance_weight_0 (0x000035A0)*/ +/*! Slice: wdr3_distance_weight_curve0:*/ +#define WDR3_DISTANCE_WEIGHT_CURVE0 +#define WDR3_DISTANCE_WEIGHT_CURVE0_MASK 0x001FC000U +#define WDR3_DISTANCE_WEIGHT_CURVE0_SHIFT 14U +/*! Slice: wdr3_distance_weight_curve1:*/ +#define WDR3_DISTANCE_WEIGHT_CURVE1 +#define WDR3_DISTANCE_WEIGHT_CURVE1_MASK 0x00003F80U +#define WDR3_DISTANCE_WEIGHT_CURVE1_SHIFT 7U +/*! Slice: wdr3_distance_weight_curve2:*/ +#define WDR3_DISTANCE_WEIGHT_CURVE2 +#define WDR3_DISTANCE_WEIGHT_CURVE2_MASK 0x0000007FU +#define WDR3_DISTANCE_WEIGHT_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_difference_weight_0 (0x000035B4)*/ +/*! Slice: wdr3_difference_weight_curve0:*/ +#define WDR3_DIFFERENCE_WEIGHT_CURVE0 +#define WDR3_DIFFERENCE_WEIGHT_CURVE0_MASK 0x001FC000U +#define WDR3_DIFFERENCE_WEIGHT_CURVE0_SHIFT 14U +/*! Slice: wdr3_difference_weight_curve1:*/ +#define WDR3_DIFFERENCE_WEIGHT_CURVE1 +#define WDR3_DIFFERENCE_WEIGHT_CURVE1_MASK 0x00003F80U +#define WDR3_DIFFERENCE_WEIGHT_CURVE1_SHIFT 7U +/*! Slice: wdr3_difference_weight_curve2:*/ +#define WDR3_DIFFERENCE_WEIGHT_CURVE2 +#define WDR3_DIFFERENCE_WEIGHT_CURVE2_MASK 0x0000007FU +#define WDR3_DIFFERENCE_WEIGHT_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_invert_curve_0 (0x000035C8)*/ +/*! Slice: wdr3_global_curve_invert0:*/ +#define WDR3_GLOBAL_CURVE_INVERT0 +#define WDR3_GLOBAL_CURVE_INVERT0_MASK 0x00FFF000U +#define WDR3_GLOBAL_CURVE_INVERT0_SHIFT 12U +/*! Slice: wdr3_global_curve_invert1:*/ +#define WDR3_GLOBAL_CURVE_INVERT1 +#define WDR3_GLOBAL_CURVE_INVERT1_MASK 0x00000FFFU +#define WDR3_GLOBAL_CURVE_INVERT1_SHIFT 0U +/*! Register: isp_wdr3_invert_curve_1 (0x000035CC)*/ +/*! Slice: wdr3_global_curve_invert2:*/ +#define WDR3_GLOBAL_CURVE_INVERT2 +#define WDR3_GLOBAL_CURVE_INVERT2_MASK 0x00FFF000U +#define WDR3_GLOBAL_CURVE_INVERT2_SHIFT 12U +/*! Register: isp_wdr3_invert_linear_0 (0x000035E4)*/ +/*! Slice: wdr3_linear_curve_invert0:*/ +#define WDR3_LINEAR_CURVE_INVERT0 +#define WDR3_LINEAR_CURVE_INVERT0_MASK 0x00FFF000U +#define WDR3_LINEAR_CURVE_INVERT0_SHIFT 12U +/*! Slice: wdr3_linear_curve_invert1:*/ +#define WDR3_LINEAR_CURVE_INVERT1 +#define WDR3_LINEAR_CURVE_INVERT1_MASK 0x00000FFFU +#define WDR3_LINEAR_CURVE_INVERT1_SHIFT 0U +/*! Register: isp_wdr3_invert_linear_1 (0x000035E8)*/ +/*! Slice: wdr3_linear_curve_invert2:*/ +#define WDR3_LINEAR_CURVE_INVERT2 +#define WDR3_LINEAR_CURVE_INVERT2_MASK 0x00FFF000U +#define WDR3_LINEAR_CURVE_INVERT2_SHIFT 12U +/*! Register: isp_wdr3_shift_0 (0x00003600)*/ +/*! Slice: wdr3_histogram_shift0:*/ +#define WDR3_HISTOGRAM_SHIFT0 +#define WDR3_HISTOGRAM_SHIFT0_MASK 0xF0000000U +#define WDR3_HISTOGRAM_SHIFT0_SHIFT 28U +/*! Slice: wdr3_histogram_shift1:*/ +#define WDR3_HISTOGRAM_SHIFT1 +#define WDR3_HISTOGRAM_SHIFT1_MASK 0x0F000000U +#define WDR3_HISTOGRAM_SHIFT1_SHIFT 24U +/*! Slice: wdr3_histogram_shift2:*/ +#define WDR3_HISTOGRAM_SHIFT2 +#define WDR3_HISTOGRAM_SHIFT2_MASK 0x00F00000U +#define WDR3_HISTOGRAM_SHIFT2_SHIFT 20U +/*! Slice: wdr3_histogram_shift3:*/ +#define WDR3_HISTOGRAM_SHIFT3 +#define WDR3_HISTOGRAM_SHIFT3_MASK 0x000F0000U +#define WDR3_HISTOGRAM_SHIFT3_SHIFT 16U +/*! Slice: wdr3_histogram_shift4:*/ +#define WDR3_HISTOGRAM_SHIFT4 +#define WDR3_HISTOGRAM_SHIFT4_MASK 0x0000F000U +#define WDR3_HISTOGRAM_SHIFT4_SHIFT 12U +/*! Slice: wdr3_histogram_shift5:*/ +#define WDR3_HISTOGRAM_SHIFT5 +#define WDR3_HISTOGRAM_SHIFT5_MASK 0x00000F00U +#define WDR3_HISTOGRAM_SHIFT5_SHIFT 8U +/*! Slice: wdr3_histogram_shift6:*/ +#define WDR3_HISTOGRAM_SHIFT6 +#define WDR3_HISTOGRAM_SHIFT6_MASK 0x000000F0U +#define WDR3_HISTOGRAM_SHIFT6_SHIFT 4U +/*! Slice: wdr3_histogram_shift7:*/ +#define WDR3_HISTOGRAM_SHIFT7 +#define WDR3_HISTOGRAM_SHIFT7_MASK 0x0000000FU +#define WDR3_HISTOGRAM_SHIFT7_SHIFT 0U +/*! Register: isp_wdr3_shift_1 (0x00003604)*/ +/*! Slice: wdr3_histogram_shift8:*/ +#define WDR3_HISTOGRAM_SHIFT8 +#define WDR3_HISTOGRAM_SHIFT8_MASK 0x00F00000U +#define WDR3_HISTOGRAM_SHIFT8_SHIFT 20U +/*! Slice: wdr3_histogram_shift9:*/ +#define WDR3_HISTOGRAM_SHIFT9 +#define WDR3_HISTOGRAM_SHIFT9_MASK 0x000F0000U +#define WDR3_HISTOGRAM_SHIFT9_SHIFT 16U +/*! Slice: wdr3_histogram_shift10:*/ +#define WDR3_HISTOGRAM_SHIFT10 +#define WDR3_HISTOGRAM_SHIFT10_MASK 0x0000F000U +#define WDR3_HISTOGRAM_SHIFT10_SHIFT 12U +/*! Slice: wdr3_histogram_shift11:*/ +#define WDR3_HISTOGRAM_SHIFT11 +#define WDR3_HISTOGRAM_SHIFT11_MASK 0x00000F00U +#define WDR3_HISTOGRAM_SHIFT11_SHIFT 8U +/*! Slice: wdr3_histogram_shift12:*/ +#define WDR3_HISTOGRAM_SHIFT12 +#define WDR3_HISTOGRAM_SHIFT12_MASK 0x000000F0U +#define WDR3_HISTOGRAM_SHIFT12_SHIFT 4U +/*! Slice: wdr3_histogram_shift13:*/ +#define WDR3_HISTOGRAM_SHIFT13 +#define WDR3_HISTOGRAM_SHIFT13_MASK 0x0000000FU +#define WDR3_HISTOGRAM_SHIFT13_SHIFT 0U +/*! Register: isp_wdr3_strength_shd (0x00003608)*/ +/*! Slice: wdr3_total_strength_shd:*/ +#define WDR3_TOTAL_STRENGTH_SHD +#define WDR3_TOTAL_STRENGTH_SHD_MASK 0xFF000000U +#define WDR3_TOTAL_STRENGTH_SHD_SHIFT 24U +/*! Slice: wdr3_local_strength_shd:*/ +#define WDR3_LOCAL_STRENGTH_SHD +#define WDR3_LOCAL_STRENGTH_SHD_MASK 0x00FF0000U +#define WDR3_LOCAL_STRENGTH_SHD_SHIFT 16U +/*! Slice: wdr3_global_strength_shd:*/ +#define WDR3_GLOBAL_STRENGTH_SHD +#define WDR3_GLOBAL_STRENGTH_SHD_MASK 0x0000FF00U +#define WDR3_GLOBAL_STRENGTH_SHD_SHIFT 8U +/*! Slice: wdr3_maximum_gain_shd:*/ +#define WDR3_MAXIMUM_GAIN_SHD +#define WDR3_MAXIMUM_GAIN_SHD_MASK 0x000000FFU +#define WDR3_MAXIMUM_GAIN_SHD_SHIFT 0U +/*! Register: isp_wdr3_pixel_slope_shd (0x0000360C)*/ +/*! Slice: wdr3_pixel_merge_slope_shd:*/ +#define WDR3_PIXEL_MERGE_SLOPE_SHD +#define WDR3_PIXEL_MERGE_SLOPE_SHD_MASK 0xFF000000U +#define WDR3_PIXEL_MERGE_SLOPE_SHD_SHIFT 24U +/*! Slice: wdr3_pixel_merge_base_shd:*/ +#define WDR3_PIXEL_MERGE_BASE_SHD +#define WDR3_PIXEL_MERGE_BASE_SHD_MASK 0x00FF0000U +#define WDR3_PIXEL_MERGE_BASE_SHD_SHIFT 16U +/*! Slice: wdr3_pixel_adjust_slope_shd:*/ +#define WDR3_PIXEL_ADJUST_SLOPE_SHD +#define WDR3_PIXEL_ADJUST_SLOPE_SHD_MASK 0x0000FF00U +#define WDR3_PIXEL_ADJUST_SLOPE_SHD_SHIFT 8U +/*! Slice: wdr3_pixel_adjust_base_shd:*/ +#define WDR3_PIXEL_ADJUST_BASE_SHD +#define WDR3_PIXEL_ADJUST_BASE_SHD_MASK 0x000000FFU +#define WDR3_PIXEL_ADJUST_BASE_SHD_SHIFT 0U +/*! Register: isp_wdr3_entropy_slope_shd (0x00003610)*/ +/*! Slice: wdr3_entropy_slope_shd:*/ +#define WDR3_ENTROPY_SLOPE_SHD +#define WDR3_ENTROPY_SLOPE_SHD_MASK 0x000FFC00U +#define WDR3_ENTROPY_SLOPE_SHD_SHIFT 10U +/*! Slice: wdr3_entropy_base_shd:*/ +#define WDR3_ENTROPY_BASE_SHD +#define WDR3_ENTROPY_BASE_SHD_MASK 0x000003FFU +#define WDR3_ENTROPY_BASE_SHD_SHIFT 0U +/* TPG */ +/*! Register: isp_tpg_ctrl (0x00000700)*/ +/*! Slice: tpg_resolution:*/ +#define TPG_RESOLUTION +#define TPG_RESOLUTION_MASK 0x00000C00U +#define TPG_RESOLUTION_SHIFT 10U +/*! Slice: tpg_max_sync:*/ +#define TPG_MAX_SYNC +#define TPG_MAX_SYNC_MASK 0x00000200U +#define TPG_MAX_SYNC_SHIFT 9U +/*! Slice: tpg_def_sync:*/ +#define TPG_DEF_SYNC +#define TPG_DEF_SYNC_MASK 0x00000100U +#define TPG_DEF_SYNC_SHIFT 8U +/*! Slice: tpg_color_depth:*/ +#define TPG_COLOR_DEPTH +#define TPG_COLOR_DEPTH_MASK 0x000000C0U +#define TPG_COLOR_DEPTH_SHIFT 6U +/*! Slice: tpg_cfa_pat:*/ +#define TPG_CFA_PAT +#define TPG_CFA_PAT_MASK 0x00000030U +#define TPG_CFA_PAT_SHIFT 4U +/*! Slice: tpg_img_num:*/ +#define TPG_IMG_NUM +#define TPG_IMG_NUM_MASK 0x0000000EU +#define TPG_IMG_NUM_SHIFT 1U +/*! Slice: tpg_frame_num:*/ +#define TPG_FRAME_NUM +#define TPG_FRAME_NUM_MASK 0xFFFF0000U +#define TPG_FRAME_NUM_SHIFT 16U +/*! Slice: tpg_enable:*/ +#define TPG_ENABLE +#define TPG_ENABLE_MASK 0x00000001U +#define TPG_ENABLE_SHIFT 0U +/*! Register: isp_tpg_total_in (0x00000704)*/ +/*! Slice: tpg_htotal_in:*/ +#define TPG_HTOTAL_IN +#define TPG_HTOTAL_IN_MASK 0x0FFFC000U +#define TPG_HTOTAL_IN_SHIFT 14U +/*! Slice: tpg_vtotal_in:*/ +#define TPG_VTOTAL_IN +#define TPG_VTOTAL_IN_MASK 0x00003FFFU +#define TPG_VTOTAL_IN_SHIFT 0U +/*! Register: isp_tpg_act_in (0x00000708)*/ +/*! Slice: tpg_hact_in:*/ +#define TPG_HACT_IN +#define TPG_HACT_IN_MASK 0x0FFFC000U +#define TPG_HACT_IN_SHIFT 14U +/*! Slice: tpg_vact_in:*/ +#define TPG_VACT_IN +#define TPG_VACT_IN_MASK 0x00003FFFU +#define TPG_VACT_IN_SHIFT 0U +/*! Register: isp_tpg_fp_in (0x0000070C)*/ +/*! Slice: tpg_fp_h_in:*/ +#define TPG_FP_H_IN +#define TPG_FP_H_IN_MASK 0x0FFFC000U +#define TPG_FP_H_IN_SHIFT 14U +/*! Slice: tpg_fp_v_in:*/ +#define TPG_FP_V_IN +#define TPG_FP_V_IN_MASK 0x00003FFFU +#define TPG_FP_V_IN_SHIFT 0U +/*! Register: isp_tpg_bp_in (0x00000710)*/ +/*! Slice: tpg_bp_h_in:*/ +#define TPG_BP_H_IN +#define TPG_BP_H_IN_MASK 0x0FFFC000U +#define TPG_BP_H_IN_SHIFT 14U +/*! Slice: tpg_bp_v_in:*/ +#define TPG_BP_V_IN +#define TPG_BP_V_IN_MASK 0x00003FFFU +#define TPG_BP_V_IN_SHIFT 0U +/*! Register: isp_tpg_w_in (0x00000714)*/ +/*! Slice: tpg_hs_w_in:*/ +#define TPG_HS_W_IN +#define TPG_HS_W_IN_MASK 0x0FFFC000U +#define TPG_HS_W_IN_SHIFT 14U +/*! Slice: tpg_vs_w_in:*/ +#define TPG_VS_W_IN +#define TPG_VS_W_IN_MASK 0x00003FFFU +#define TPG_VS_W_IN_SHIFT 0U +/*! Register: isp_tpg_gap_in (0x00000718)*/ +/*! Slice: tpg_pix_gap_in:*/ +#define TPG_PIX_GAP_IN +#define TPG_PIX_GAP_IN_MASK 0x0FFFC000U +#define TPG_PIX_GAP_IN_SHIFT 14U +/*! Slice: tpg_line_gap_in:*/ +#define TPG_LINE_GAP_IN +#define TPG_LINE_GAP_IN_MASK 0x00003FFFU +#define TPG_LINE_GAP_IN_SHIFT 0U +/*! Register: isp_tpg_gap_std_in (0x0000071C)*/ +/*! Slice: tpg_pix_gap_std_in:*/ +#define TPG_PIX_GAP_STD_IN +#define TPG_PIX_GAP_STD_IN_MASK 0x00003FFFU +#define TPG_PIX_GAP_STD_IN_SHIFT 0U +/*! Register: isp_tpg_random_seed (0x00000720)*/ +/*! Slice: tpg_random_seed:*/ +#define TPG_RANDOM_SEED +#define TPG_RANDOM_SEED_MASK 0xFFFFFFFFU +#define TPG_RANDOM_SEED_SHIFT 0U +/* MCM */ +/*! Register: mcm_ctrl (0x00001200)*/ +/*! Slice: MCM_SENSOR_MEM_BYPASS:*/ +#define MCM_SENSOR_MEM_BYPASS +#define MCM_SENSOR_MEM_BYPASS_MASK 0x00020000U +#define MCM_SENSOR_MEM_BYPASS_SHIFT 17U +/*! Slice: MCM_G2_WR1_FMT:*/ +#define MCM_G2_WR1_FMT +#define MCM_G2_WR1_FMT_MASK 0x0001C000U +#define MCM_G2_WR1_FMT_SHIFT 14U +/*! Slice: MCM_G2_WR0_FMT:*/ +#define MCM_G2_WR0_FMT +#define MCM_G2_WR0_FMT_MASK 0x00003800U +#define MCM_G2_WR0_FMT_SHIFT 11U +/*! Slice: MCM_WR1_FMT:*/ +#define MCM_WR1_FMT +#define MCM_WR1_FMT_MASK 0x00000700U +#define MCM_WR1_FMT_SHIFT 8U +/*! Slice: MCM_WR0_FMT:*/ +#define MCM_WR0_FMT +#define MCM_WR0_FMT_MASK 0x000000E0U +#define MCM_WR0_FMT_SHIFT 5U +/*! Slice: MCM_BYPASS_SWITCH:*/ +#define MCM_BYPASS_SWITCH +#define MCM_BYPASS_SWITCH_MASK 0x0000001EU +#define MCM_BYPASS_SWITCH_SHIFT 1U +/*! Slice: MCM_BYPASS_EN:*/ +#define MCM_BYPASS_EN +#define MCM_BYPASS_EN_MASK 0x00000001U +#define MCM_BYPASS_EN_SHIFT 0U +/*! Register: mcm_size0 (0x00001204)*/ +/*! Slice: MCM_HEIGHT0:*/ +#define MCM_HEIGHT0 +#define MCM_HEIGHT0_MASK 0x3FFF0000U +#define MCM_HEIGHT0_SHIFT 16U +/*! Slice: MCM_WIDTH0:*/ +#define MCM_WIDTH0 +#define MCM_WIDTH0_MASK 0x00003FFFU +#define MCM_WIDTH0_SHIFT 0U +/*! Register: mcm_size1 (0x00001208)*/ +/*! Slice: MCM_HEIGHT1:*/ +#define MCM_HEIGHT1 +#define MCM_HEIGHT1_MASK 0x3FFF0000U +#define MCM_HEIGHT1_SHIFT 16U +/*! Slice: MCM_WIDTH1:*/ +#define MCM_WIDTH1 +#define MCM_WIDTH1_MASK 0x00003FFFU +#define MCM_WIDTH1_SHIFT 0U +/*! Register: mcm_rd_cfg (0x00001280)*/ +/*! Slice: MCM_RD_FMT:*/ +#define MCM_RD_FMT +#define MCM_RD_FMT_MASK 0x00000007U +#define MCM_RD_FMT_SHIFT 0U +/*! Register: mcm_retiming0 (0x00001284)*/ +/*! Slice: MCM_VSYNC_BLANK:*/ +#define MCM_VSYNC_BLANK +#define MCM_VSYNC_BLANK_MASK 0xFFFFFF00U +#define MCM_VSYNC_BLANK_SHIFT 8U +/*! Slice: MCM_VSYNC_DURATION:*/ +#define MCM_VSYNC_DURATION +#define MCM_VSYNC_DURATION_MASK 0x000000FFU +#define MCM_VSYNC_DURATION_SHIFT 0U +/*! Register: mcm_retiming1 (0x00001288)*/ +/*! Slice: MCM_HSYNC_BLANK:*/ +#define MCM_HSYNC_BLANK +#define MCM_HSYNC_BLANK_MASK 0xFFFFFF00U +#define MCM_HSYNC_BLANK_SHIFT 8U +/*! Slice: MCM_HSYNC_PREAMPLE:*/ +#define MCM_HSYNC_PREAMPLE +#define MCM_HSYNC_PREAMPLE_MASK 0x000000FFU +#define MCM_HSYNC_PREAMPLE_SHIFT 0U +/*! Register: mcm_hsync_preample_ext (0x0000128c)*/ +/*! Slice: MCM_HSYNC_PREAMPLE_EXT:*/ +#define MCM_HSYNC_PREAMPLE_EXT +#define MCM_HSYNC_PREAMPLE_EXT_MASK 0x000FFFFFU +#define MCM_HSYNC_PREAMPLE_EXT_SHIFT 0U +/*! Register: mcm_wr_retiming0 (0x00001290)*/ +/*! Slice: MCM_WR_VSYNC_BLANK:*/ +#define MCM_WR_VSYNC_BLANK +#define MCM_WR_VSYNC_BLANK_MASK 0xFFFFFF00U +#define MCM_WR_VSYNC_BLANK_SHIFT 8U +/*! Slice: MCM_WR_VSYNC_DURATION:*/ +#define MCM_WR_VSYNC_DURATION +#define MCM_WR_VSYNC_DURATION_MASK 0x000000FFU +#define MCM_WR_VSYNC_DURATION_SHIFT 0U +/*! Register: mcm_wr_retiming1 (0x00001294)*/ +/*! Slice: MCM_WR_HSYNC_BLANK:*/ +#define MCM_WR_HSYNC_BLANK +#define MCM_WR_HSYNC_BLANK_MASK 0xFFFFFF00U +#define MCM_WR_HSYNC_BLANK_SHIFT 8U +/*! Slice: MCM_WR_HSYNC_PREAMPLE:*/ +#define MCM_WR_HSYNC_PREAMPLE +#define MCM_WR_HSYNC_PREAMPLE_MASK 0x000000FFU +#define MCM_WR_HSYNC_PREAMPLE_SHIFT 0U + +/*Stitching */ +/*!Register: isp_stitching_ctrl (0x00003300) */ +/*!Register: isp_stitching_ctrl (0x00003300) */ +/*!Slice: regs_inform_en */ +#define STITCHING_REGS_INFORM_EN +#define STITCHING_REGS_INFORM_EN_MASK 0x00400000U +#define STITCHING_REGS_INFORM_EN_SHIFT 22U +/*!Slice: vsync_pol */ +#define STITCHING_VSYNC_POL +#define STITCHING_VSYNC_POL_MASK 0x00200000U +#define STITCHING_VSYNC_POL_SHIFT 21U +/*!Slice: hsync_pol */ +#define STITCHING_HSYNC_POL +#define STITCHING_HSYNC_POL_MASK 0x00100000U +#define STITCHING_HSYNC_POL_SHIFT 20U +/*!Slice: awb_gain_enable */ +#define STITCHING_AWB_GAIN_ENABLE +#define STITCHING_AWB_GAIN_ENABLE_MASK 0x00080000U +#define STITCHING_AWB_GAIN_ENABLE_SHIFT 19U +/*!Slice: cfg_upd */ +#define STITCHING_CFG_UPD +#define STITCHING_CFG_UPD_MASK 0x00040000U +#define STITCHING_CFG_UPD_SHIFT 18U +/*!Slice: gen_cfg_upd */ +#define STITCHING_GEN_CFG_UPD +#define STITCHING_GEN_CFG_UPD_MASK 0x00020000U +#define STITCHING_GEN_CFG_UPD_SHIFT 17U +/*!Slice: gen_cfg_upd_fix */ +#define STITCHING_GEN_CFG_UPD_FIX +#define STITCHING_GEN_CFG_UPD_FIX_MASK 0x00010000U +#define STITCHING_GEN_CFG_UPD_FIX_SHIFT 16U +/*!Slice: bypass_select */ +#define STITCHING_BYPASS_SELECT +#define STITCHING_BYPASS_SELECT_MASK 0x00006000U +#define STITCHING_BYPASS_SELECT_SHIFT 13U +/*!Slice: linear_combine_enable */ +#define STITCHING_LINEAR_COMBINE_ENABLE +#define STITCHING_LINEAR_COMBINE_ENABLE_MASK 0x00001000U +#define STITCHING_LINEAR_COMBINE_ENABLE_SHIFT 12U +/*!Slice: base_frame_selection */ +#define STITCHING_BASE_FRAME_SELECTION +#define STITCHING_BASE_FRAME_SELECTION_MASK 0x00000800U +#define STITCHING_BASE_FRAME_SELECTION_SHIFT 11U +/*!Slice: combination_mode */ +#define STITCHING_COMBINATION_MODE +#define STITCHING_COMBINATION_MODE_MASK 0x00000600U +#define STITCHING_COMBINATION_MODE_SHIFT 9U +/*!Slice: channel_config_bit */ +#define STITCHING_CHANNEL_CONFIG_BIT +#define STITCHING_CHANNEL_CONFIG_BIT_MASK 0x00000100U +#define STITCHING_CHANNEL_CONFIG_BIT_SHIFT 8U +/*!Slice: B10_enable_bit */ +#define STITCHING_B10_ENABLE_BIT +#define STITCHING_B10_ENABLE_BIT_MASK 0x00000080U +#define STITCHING_B10_ENABLE_BIT_SHIFT 7U +/*!Slice: lin_enable_bit */ +#define STITCHING_LIN_ENABLE_BIT +#define STITCHING_LIN_ENABLE_BIT_MASK 0x00000040U +#define STITCHING_LIN_ENABLE_BIT_SHIFT 6U +/*!Slice: VS_enable_bit */ +#define STITCHING_VS_ENABLE_BIT +#define STITCHING_VS_ENABLE_BIT_MASK 0x00000020U +#define STITCHING_VS_ENABLE_BIT_SHIFT 5U +/*!Slice: bayer_pattern */ +#define STITCHING_BAYER_PATTERN +#define STITCHING_BAYER_PATTERN_MASK 0x00000018U +#define STITCHING_BAYER_PATTERN_SHIFT 3U +/*!Slice: soft_reset_flag */ +#define STITCHING_SOFT_RESET_FLAG +#define STITCHING_SOFT_RESET_FLAG_MASK 0x00000004U +#define STITCHING_SOFT_RESET_FLAG_SHIFT 2U +/*!Slice: mono_input_flag */ +#define STITCHING_MONO_INPUT_FLAG +#define STITCHING_MONO_INPUT_FLAG_MASK 0x00000002U +#define STITCHING_MONO_INPUT_FLAG_SHIFT 1U +/*!Slice: combine_enable_bit */ +#define STITCHING_COMBINE_ENABLE_BIT +#define STITCHING_COMBINE_ENABLE_BIT_MASK 0x00000001U +#define STITCHING_COMBINE_ENABLE_BIT_SHIFT 0U +/*!Slice: regs_inform_en */ +#define STITCHING_REGS_INFORM_EN +#define STITCHING_REGS_INFORM_EN_MASK 0x00400000U +#define STITCHING_REGS_INFORM_EN_SHIFT 22U +/*!Slice: vsync_pol */ +#define STITCHING_VSYNC_POL +#define STITCHING_VSYNC_POL_MASK 0x00200000U +#define STITCHING_VSYNC_POL_SHIFT 21U +/*!Slice: hsync_pol */ +#define STITCHING_HSYNC_POL +#define STITCHING_HSYNC_POL_MASK 0x00100000U +#define STITCHING_HSYNC_POL_SHIFT 20U +/*!Slice: awb_gain_enable */ +#define STITCHING_AWB_GAIN_ENABLE +#define STITCHING_AWB_GAIN_ENABLE_MASK 0x00080000U +#define STITCHING_AWB_GAIN_ENABLE_SHIFT 19U +/*!Slice: cfg_upd */ +#define STITCHING_CFG_UPD +#define STITCHING_CFG_UPD_MASK 0x00040000U +#define STITCHING_CFG_UPD_SHIFT 18U +/*!Slice: gen_cfg_upd */ +#define STITCHING_GEN_CFG_UPD +#define STITCHING_GEN_CFG_UPD_MASK 0x00020000U +#define STITCHING_GEN_CFG_UPD_SHIFT 17U +/*!Slice: gen_cfg_upd_fix */ +#define STITCHING_GEN_CFG_UPD_FIX +#define STITCHING_GEN_CFG_UPD_FIX_MASK 0x00010000U +#define STITCHING_GEN_CFG_UPD_FIX_SHIFT 16U +/*!Slice: bypass_select */ +#define STITCHING_BYPASS_SELECT +#define STITCHING_BYPASS_SELECT_MASK 0x00006000U +#define STITCHING_BYPASS_SELECT_SHIFT 13U +/*!Slice: linear_combine_enable */ +#define STITCHING_LINEAR_COMBINE_ENABLE +#define STITCHING_LINEAR_COMBINE_ENABLE_MASK 0x00001000U +#define STITCHING_LINEAR_COMBINE_ENABLE_SHIFT 12U +/*!Slice: base_frame_selection */ +#define STITCHING_BASE_FRAME_SELECTION +#define STITCHING_BASE_FRAME_SELECTION_MASK 0x00000800U +#define STITCHING_BASE_FRAME_SELECTION_SHIFT 11U +/*!Slice: combination_mode */ +#define STITCHING_COMBINATION_MODE +#define STITCHING_COMBINATION_MODE_MASK 0x00000600U +#define STITCHING_COMBINATION_MODE_SHIFT 9U +/*!Slice: channel_config_bit */ +#define STITCHING_CHANNEL_CONFIG_BIT +#define STITCHING_CHANNEL_CONFIG_BIT_MASK 0x00000100U +#define STITCHING_CHANNEL_CONFIG_BIT_SHIFT 8U +/*!Slice: B10_enable_bit */ +#define STITCHING_B10_ENABLE_BIT +#define STITCHING_B10_ENABLE_BIT_MASK 0x00000080U +#define STITCHING_B10_ENABLE_BIT_SHIFT 7U +/*!Slice: lin_enable_bit */ +#define STITCHING_LIN_ENABLE_BIT +#define STITCHING_LIN_ENABLE_BIT_MASK 0x00000040U +#define STITCHING_LIN_ENABLE_BIT_SHIFT 6U +/*!Slice: VS_enable_bit */ +#define STITCHING_VS_ENABLE_BIT +#define STITCHING_VS_ENABLE_BIT_MASK 0x00000020U +#define STITCHING_VS_ENABLE_BIT_SHIFT 5U +/*!Slice: bayer_pattern */ +#define STITCHING_BAYER_PATTERN +#define STITCHING_BAYER_PATTERN_MASK 0x00000018U +#define STITCHING_BAYER_PATTERN_SHIFT 3U +/*!Slice: soft_reset_flag */ +#define STITCHING_SOFT_RESET_FLAG +#define STITCHING_SOFT_RESET_FLAG_MASK 0x00000004U +#define STITCHING_SOFT_RESET_FLAG_SHIFT 2U +/*!Slice: mono_input_flag */ +#define STITCHING_MONO_INPUT_FLAG +#define STITCHING_MONO_INPUT_FLAG_MASK 0x00000002U +#define STITCHING_MONO_INPUT_FLAG_SHIFT 1U +/*!Slice: combine_enable_bit */ +#define STITCHING_COMBINE_ENABLE_BIT +#define STITCHING_COMBINE_ENABLE_BIT_MASK 0x00000001U +#define STITCHING_COMBINE_ENABLE_BIT_SHIFT 0U +/*!Register: isp_stitching_frame_width (0x00003304) */ +/*!Slice: stitching_frame_width */ +#define STITCHING_FRAME_WIDTH +#define STITCHING_FRAME_WIDTH_MASK 0x00003FFFU +#define STITCHING_FRAME_WIDTH_SHIFT 0U +/*!Register: isp_stitching_ctrl (0x00003300)*/ +/*!Slice: digital_gain_en_2 */ +#define STITCHING_DIGITAL_GAIN_EN2 +#define STITCHING_DIGITAL_GAIN_EN2_MASK 0x02000000U +#define STITCHING_DIGITAL_GAIN_EN2_SHIFT 25U +/*!Register: isp_stitching_ctrl (0x00003300)*/ +/*!Slice: digital_gain_en_1 */ +#define STITCHING_DIGITAL_GAIN_EN1 +#define STITCHING_DIGITAL_GAIN_EN1_MASK 0x01000000U +#define STITCHING_DIGITAL_GAIN_EN1_SHIFT 24U +/*!Register: isp_stitching_ctrl (0x00003300)*/ +/*!Slice: digital_gain_en_0 */ +#define STITCHING_DIGITAL_GAIN_EN0 +#define STITCHING_DIGITAL_GAIN_EN0_MASK 0x00800000U +#define STITCHING_DIGITAL_GAIN_EN0_SHIFT 23U +/*!Register: isp_stitching_ctrl (0x00003300)*/ +/*!Slice: digital_gain_en */ +#define STITCHING_DIGITAL_GAIN_EN +#define STITCHING_DIGITAL_GAIN_EN_MASK 0x00400000U +#define STITCHING_DIGITAL_GAIN_EN_SHIFT 22U +/*!Register: isp_stitching_frame_height (0x00003308) */ +/*!Slice: stitching_frame_height */ +#define STITCHING_FRAME_HEIGHT +#define STITCHING_FRAME_HEIGHT_MASK 0x00003FFFU +#define STITCHING_FRAME_HEIGHT_SHIFT 0U +/*Register: isp_stitching_exposure_bit (0x0000330C) */ +/*!Slice: stitching_l_bit_depth */ +#define STITCHING_L_BIT_DEPTH +#define STITCHING_L_BIT_DEPTH_MASK 0xFF000000U +#define STITCHING_L_BIT_DEPTH_SHIFT 24U +/*!Slice: stitching_s_bit_depth */ +#define STITCHING_S_BIT_DEPTH +#define STITCHING_S_BIT_DEPTH_MASK 0x00FF0000U +#define STITCHING_S_BIT_DEPTH_SHIFT 16U +/*!Slice: stitching_vs_bit_depth */ +#define STITCHING_VS_BIT_DEPTH +#define STITCHING_VS_BIT_DEPTH_MASK 0x0000FF00U +#define STITCHING_VS_BIT_DEPTH_SHIFT 8U +/*!Slice: stitching_ls_bit_depth */ +#define STITCHING_LS_BIT_DEPTH +#define STITCHING_LS_BIT_DEPTH_MASK 0x000000FFU +#define STITCHING_LS_BIT_DEPTH_SHIFT 0U +/*!Register: isp_stitching_color_weight */ +/*!Slice: stitching_color_weight_2 */ +#define STITCHING_COLOR_WEIGHT_2 +#define STITCHING_COLOR_WEIGHT_2_MASK 0x00FF0000U +#define STITCHING_COLOR_WEIGHT_2_SHIFT 16U +/*!Slice: stitching_color_weight_1 */ +#define STITCHING_COLOR_WEIGHT_1 +#define STITCHING_COLOR_WEIGHT_1_MASK 0x0000FF00U +#define STITCHING_COLOR_WEIGHT_1_SHIFT 8U +/*!Slice: stitching_color_weight_0 */ +#define STITCHING_COLOR_WEIGHT_0 +#define STITCHING_COLOR_WEIGHT_0_MASK 0x000000FFU +#define STITCHING_COLOR_WEIGHT_0_SHIFT 0U +/*!Register: isp_stitching_bls_exp_0_a (0x00003314)*/ +/*!Slice: stitching_digital_gain_exp_0_r */ +#define STITCHING_DIGITAL_GAIN_EXP_0_R +#define STITCHING_DIGITAL_GAIN_EXP_0_R_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_0_R_SHIFT 16U +/*!Register: isp_stitching_bls_exp_0_a (0x00003314)*/ +/*!Slice: stitching_bls_exp_0_a */ +#define STITCHING_BLS_EXP_0_A +#define STITCHING_BLS_EXP_0_A_MASK 0x000000FFFU +#define STITCHING_BLS_EXP_0_A_SHIFT 0U +/*!Register: isp_stitching_bls_exp_0_b (0x00003318)*/ +/*!Slice: stitching_digital_gain_exp_0_g */ +#define STITCHING_DIGITAL_GAIN_EXP_0_G +#define STITCHING_DIGITAL_GAIN_EXP_0_G_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_0_G_SHIFT 16U +/*!Register: isp_stitching_bls_exp_0_b (0x00003318)*/ +/*!Slice: stitching_bls_exp_0_b */ +#define STITCHING_BLS_EXP_0_B +#define STITCHING_BLS_EXP_0_B_MASK 0x000000FFFU +#define STITCHING_BLS_EXP_0_B_SHIFT 0U +/*!Register: isp_stitching_bls_exp_0_c (0x0000331c)*/ +/*!Slice: stitching_digital_gain_exp_0_gr */ +#define STITCHING_DIGITAL_GAIN_EXP_0_GR +#define STITCHING_DIGITAL_GAIN_EXP_0_GR_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_0_GR_SHIFT 16U +/*!Register: isp_stitching_bls_exp_0_c (0x0000331C)*/ +/*!Slice: stitching_bls_exp_0_c */ +#define STITCHING_BLS_EXP_0_C +#define STITCHING_BLS_EXP_0_C_MASK 0x000000FFFU +#define STITCHING_BLS_EXP_0_C_SHIFT 0U +/*!Register: isp_stitching_bls_exp_0_d (0x00003320)*/ +/*!Slice: stitching_digital_gain_exp_0_gb */ +#define STITCHING_DIGITAL_GAIN_EXP_0_GB +#define STITCHING_DIGITAL_GAIN_EXP_0_GB_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_0_GB_SHIFT 16U +/*!Register: isp_stitching_bls_exp_0_d (0x00003320)*/ +/*!Slice: stitching_bls_exp_0_d */ +#define STITCHING_BLS_EXP_0_D +#define STITCHING_BLS_EXP_0_D_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_0_D_SHIFT 0U +/*!Register: isp_stitching_bls_exp_1_a (0x00003324)*/ +/*!Slice: stitching_digital_gain_exp_1_r */ +#define STITCHING_DIGITAL_GAIN_EXP_1_R +#define STITCHING_DIGITAL_GAIN_EXP_1_R_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_1_R_SHIFT 16U +/*!Register: isp_stitching_bls_exp_1_a (0x00003324)*/ +/*!Slice: stitching_bls_exp_1_a */ +#define STITCHING_BLS_EXP_1_A +#define STITCHING_BLS_EXP_1_A_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_1_A_SHIFT 0U +/*!Register: isp_stitching_bls_exp_1_b (0x00003328)*/ +/*!Slice: stitching_digital_gain_exp_1_g */ +#define STITCHING_DIGITAL_GAIN_EXP_1_G +#define STITCHING_DIGITAL_GAIN_EXP_1_G_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_1_G_SHIFT 16U +/*!Register: isp_stitching_bls_exp_1_b (0x00003328)*/ +/*!Slice: stitching_bls_exp_1_b */ +#define STITCHING_BLS_EXP_1_B +#define STITCHING_BLS_EXP_1_B_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_1_B_SHIFT 0U +/*!Register: isp_stitching_bls_exp_1_c (0x0000332c)*/ +/*!Slice: stitching_digital_gain_exp_1_gr */ +#define STITCHING_DIGITAL_GAIN_EXP_1_GR +#define STITCHING_DIGITAL_GAIN_EXP_1_GR_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_1_GR_SHIFT 16U +/*!Register: isp_stitching_bls_exp_1_c (0x0000332C)*/ +/*!Slice: stitching_bls_exp_1_c */ +#define STITCHING_BLS_EXP_1_C +#define STITCHING_BLS_EXP_1_C_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_1_C_SHIFT 0U +/*!Register: isp_stitching_bls_exp_1_d (0x00003330)*/ +/*!Slice: stitching_digital_gain_exp_1_gb */ +#define STITCHING_DIGITAL_GAIN_EXP_1_GB +#define STITCHING_DIGITAL_GAIN_EXP_1_GB_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_1_GB_SHIFT 16U +/*!Register: isp_stitching_bls_exp_1_d (0x00003330)*/ +/*!Slice: stitching_bls_exp_1_d */ +#define STITCHING_BLS_EXP_1_D +#define STITCHING_BLS_EXP_1_D_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_1_D_SHIFT 0U +/*!Register: isp_stitching_bls_exp_2_a (0x00003334)*/ +/*!Slice: stitching_digital_gain_exp_2_r */ +#define STITCHING_DIGITAL_GAIN_EXP_2_R +#define STITCHING_DIGITAL_GAIN_EXP_2_R_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_2_R_SHIFT 16U +/*!Register: isp_stitching_bls_exp_2_a (0x00003334)*/ +/*!Slice: stitching_bls_exp_2_a */ +#define STITCHING_BLS_EXP_2_A +#define STITCHING_BLS_EXP_2_A_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_2_A_SHIFT 0U +/*!Register: isp_stitching_bls_exp_2_b (0x00003338)*/ +/*!Slice: stitching_digital_gain_exp_2_g */ +#define STITCHING_DIGITAL_GAIN_EXP_2_G +#define STITCHING_DIGITAL_GAIN_EXP_2_G_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_2_G_SHIFT 16U +/*!Register: isp_stitching_bls_exp_2_b (0x00003338)*/ +/*!Slice: stitching_bls_exp_2_b */ +#define STITCHING_BLS_EXP_2_B +#define STITCHING_BLS_EXP_2_B_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_2_B_SHIFT 0U +/*!Register: isp_stitching_bls_exp_2_c (0x0000333c)*/ +/*!Slice: stitching_digital_gain_exp_2_gr */ +#define STITCHING_DIGITAL_GAIN_EXP_2_GR +#define STITCHING_DIGITAL_GAIN_EXP_2_GR_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_2_GR_SHIFT 16U +/*!Register: isp_stitching_bls_exp_2_c (0x0000333C)*/ +/*!Slice: stitching_bls_exp_2_c */ +#define STITCHING_BLS_EXP_2_C +#define STITCHING_BLS_EXP_2_C_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_2_C_SHIFT 0U +/*!Register: isp_stitching_bls_exp_2_d (0x00003340)*/ +/*!Slice: stitching_digital_gain_exp_2_gb */ +#define STITCHING_DIGITAL_GAIN_EXP_2_GB +#define STITCHING_DIGITAL_GAIN_EXP_2_GB_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_2_GB_SHIFT 16U +/*!Register: isp_stitching_bls_exp_2_d (0x00003340)*/ +/*!Slice: stitching_bls_exp_2_d */ +#define STITCHING_BLS_EXP_2_D +#define STITCHING_BLS_EXP_2_D_MASK 0x000000FFFU +#define STITCHING_BLS_EXP_2_D_SHIFT 0U +/*!Reister: isp_stitching_ratio_ls (0x00003344)*/ +/*!Slice: stitching_ratio_long_short_1 */ +#define STITCHING_RATIO_LONG_SHORT_1 +#define STITCHING_RATIO_LONG_SHORT_1_MASK 0x00FFF000U +#define STITCHING_RATIO_LONG_SHORT_1_SHIFT 12U +/*!Slice: stitching_ratio_long_short_0 */ +#define STITCHING_RATIO_LONG_SHORT_0 +#define STITCHING_RATIO_LONG_SHORT_0_MASK 0x00000FFFU +#define STITCHING_RATIO_LONG_SHORT_0_SHIFT 0U +/*!Reister: isp_stitching_ratio_vs (0x00003348) */ +/*!Slice: stitching_ratio_veryshort_short_1 */ +#define STITCHING_RATIO_VERYSHORT_SHORT_1 +#define STITCHING_RATIO_VERYSHORT_SHORT_1_MASK 0x00FFF000U +#define STITCHING_RATIO_VERYSHORT_SHORT_1_SHIFT 12U +/*!Slice: stitching_ratio_veryshort_short_0 */ +#define STITCHING_RATIO_VERYSHORT_SHORT_0 +#define STITCHING_RATIO_VERYSHORT_SHORT_0_MASK 0x00000FFFU +#define STITCHING_RATIO_VERYSHORT_SHORT_0_SHIFT 0U +/*!Reister: isp_stitching_ratio_ls_shd (0x0000334C) */ +/*!Slice: stitching_ratio_long_short_shd_1 */ +#define STITCHING_RATIO_LONG_SHORT_SHD_1 +#define STITCHING_RATIO_LONG_SHORT_SHD_1_MASK 0x00FFF000U +#define STITCHING_RATIO_LONG_SHORT_SHD_1_SHIFT 12U +/*!Slice: stitching_ratio_long_short_shd_0 */ +#define STITCHING_RATIO_LONG_SHORT_SHD_0 +#define STITCHING_RATIO_LONG_SHORT_SHD_0_MASK 0x00000FFFU +#define STITCHING_RATIO_LONG_SHORT_SHD_0_SHIFT 0U +/*!Reister: isp_stitching_ratio_vs_shd (0x00003350) */ +/*!Slice: stitching_ratio_veryshort_short_shd_1 */ +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1 +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1_MASK 0x00FFF000U +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1_SHIFT 12U +/*!Slice: stitching_ratio_veryshort_short_shd_0 */ +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0 +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0_MASK 0x00000FFFU +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0_SHIFT 0U +/*!Register: isp_sitching_trans_range_linear (0x00003354) */ +/*!Slice: stitching_trans_range_start_linear */ +#define STITCHING_TRANS_RANGE_START_LINEAR +#define STITCHING_TRANS_RANGE_START_LINEAR_MASK 0xFFFF0000U +#define STITCHING_TRANS_RANGE_START_LINEAR_SHIFT 16U +/*!Slice:stitching_trans_range_norm_factor_mul_linear */ +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR_MASK 0x0000FFFFU +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR_SHIFT 0U +/*!Register: isp_sitching_trans_range_nonlinear (0x00003358) */ +/*!Slice: stitching_trans_range_start_nonlinear */ +#define STITCHING_TRANS_RANGE_START_NONLINEAR +#define STITCHING_TRANS_RANGE_START_NONLINEAR_MASK 0xFFFF0000U +#define STITCHING_TRANS_RANGE_START_NONLINEAR_SHIFT 16U +/*!Slice:stitching_trans_range_norm_factor_mul_nonlinear */ +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR_MASK 0x0000FFFFU +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR_SHIFT 0U +/*!Register: isp_stitching_sat_level (0x0000335C) */ +//Version-11 Stitching only support one type extend bit +//!Slice: stitching_short_vs_extend_bit +#define STITCHING_SHORT_EXTEND_BIT +#define STITCHING_SHORT_EXTEND_BIT_MASK 0xFF000000U +#define STITCHING_SHORT_EXTEND_BIT_SHIFT 24U +//Version-12 Stitching support two type extend bit +//!Slice: stitching_short_ls_extend_bit +#define STITCHING_SHORT_LS_EXTEND_BIT +#define STITCHING_SHORT_LS_EXTEND_BIT_MASK 0xF0000000U +#define STITCHING_SHORT_LS_EXTEND_BIT_SHIFT 28U +//!Slice: stitching_short_vs_extend_bit +#define STITCHING_SHORT_VS_EXTEND_BIT +#define STITCHING_SHORT_VS_EXTEND_BIT_MASK 0x0F000000U +#define STITCHING_SHORT_VS_EXTEND_BIT_SHIFT 24U +/*!Slice: stitching_veryshort_valid_thresh */ +#define STITCHING_VERYSHORT_VALID_THRESH +#define STITCHING_VERYSHORT_VALID_THRESH_MASK 0x00FFF000U +#define STITCHING_VERYSHORT_VALID_THRESH_SHIFT 12U +/*!Slice: stitching_veryshort_offset_val */ +#define STITCHING_VERYSHORT_OFFSET_VAL +#define STITCHING_VERYSHORT_OFFSET_VAL_MASK 0x00000FFFU +#define STITCHING_VERYSHORT_OFFSET_VAL_SHIFT 0U +/*!Register: isp_stitching_long_exposure (0x00003360) */ +/*!Slice: stitching_long_exposure_time */ +#define STITCHING_LONG_EXPOSURE_TIME +#define STITCHING_LONG_EXPOSURE_TIME_MASK 0x00000FFFU +#define STITCHING_LONG_EXPOSURE_TIME_SHIFT 0U +/*!Register: isp_stitching_short_exposure (0x00003364) */ +/*!Slice: stitching_short_exposure_time */ +#define STITCHING_SHORT_EXPOSURE_TIME +#define STITCHING_SHORT_EXPOSURE_TIME_MASK 0x00000FFFU +#define STITCHING_SHORT_EXPOSURE_TIME_SHIFT 0U +/*!Register: isp_stitching_very_short_exposure (0x00003368) */ +/*!Slice: stitching_very_short_exposure_time */ +#define STITCHING_VERY_SHORT_EXPOSURE_TIME +#define STITCHING_VERY_SHORT_EXPOSURE_TIME_MASK 0x00000FFFU +#define STITCHING_VERY_SHORT_EXPOSURE_TIME_SHIFT 0U +/*!Register: isp_stitching_hdr_mode (0x0000336C) */ +/*!Slice: stitching_hdr_mode */ +#define STITCHING_HDR_MODE_BIT +#define STITCHING_HDR_MODE_BIT_MASK 0x0000000FU +#define STITCHING_HDR_MODE_BIT_SHIFT 0U +/*!Register: isp_stitching_out_hblank (0x00003370) */ +/*!Slice: stitching_dummy_s_hblank */ +#define STITCHING_DUMMY_S_HBLANK +#define STITCHING_DUMMY_S_HBLANK_MASK 0xFFFF0000U +#define STITCHING_DUMMY_S_HBLANK_SHIFT 16U +/*!Slice: stitching_out_hblank */ +#define STITCHING_OUT_HBLANK +#define STITCHING_OUT_HBLANK_MASK 0x00003FFFU +#define STITCHING_OUT_HBLANK_SHIFT 0U +/*!Register: isp_stitching_out_vblank (0x00003374) */ +/*!Slice: stitching_dummy_vs_hblank */ +#define STITCHING_DUMMY_VS_HBLANK +#define STITCHING_DUMMY_VS_HBLANK_MASK 0xFFFF0000U +#define STITCHING_DUMMY_VS_HBLANK_SHIFT 16U +/*!Slice: stitching_out_vblank */ +#define STITCHING_OUT_VBLANK +#define STITCHING_OUT_VBLANK_MASK 0x00000FFFU +#define STITCHING_OUT_VBLANK_SHIFT 0U +/*!Register:ISP_STITCHING_OUT_HBLANK (0x00003370)*/ +/* Slice:stiching_dummy_hblank */ +#define STITCHING_DUMMY_HBLANK +#define STITCHING_DUMMY_HBLANK_MASK 0xFFFF0000U +#define STITCHING_DUMMY_HBLANK_SHIFT 16U +/*!Register: isp_stitching_interrupt_status (0x00003378) */ +/*!Slice: stitching_interrupt_status */ +#define STITCHING_INTERRUPT_STATUS +#define STITCHING_INTERRUPT_STATUS_MASK 0x00000007U +#define STITCHING_INTERRUPT_STATUS_SHIFT 0U +/*!Register: isp_stitching_compress_x0 (0x0000337C) */ +/*!Slice: stitching_compress_x0 */ +#define STITCHING_COMPRESS_X0 +#define STITCHING_COMPRESS_X0_MASK 0x000003FFU +#define STITCHING_COMPRESS_X0_SHIFT 0U +/*!Register: isp_stitching_compress_lut_0 (0x000033A0) */ +/*!Slice: stitching_compress_lut_2 */ +#define STITCHING_COMPRESS_LUT_2 +#define STITCHING_COMPRESS_LUT_2_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_2_SHIFT 20U +/*!Slice: stitching_compress_lut_1 */ +#define STITCHING_COMPRESS_LUT_1 +#define STITCHING_COMPRESS_LUT_1_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_1_SHIFT 10U +/*!Slice: stitching_compress_lut_0 */ +#define STITCHING_COMPRESS_LUT_0 +#define STITCHING_COMPRESS_LUT_0_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_0_SHIFT 0U +/*!Register: isp_stitching_compress_lut_1 (0x000033A4) */ +/*!Slice: stitching_compress_lut_5 */ +#define STITCHING_COMPRESS_LUT_5 +#define STITCHING_COMPRESS_LUT_5_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_5_SHIFT 20U +/*!Slice: stitching_compress_lut_4 */ +#define STITCHING_COMPRESS_LUT_4 +#define STITCHING_COMPRESS_LUT_4_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_4_SHIFT 10U +/*!Slice: stitching_compress_lut_3 */ +#define STITCHING_COMPRESS_LUT_3 +#define STITCHING_COMPRESS_LUT_3_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_3_SHIFT 0U +/*!Register: isp_stitching_compress_lut_2 (0x000033A8) */ +/*!Slice: stitching_compress_lut_8 */ +#define STITCHING_COMPRESS_LUT_8 +#define STITCHING_COMPRESS_LUT_8_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_8_SHIFT 20U +/*!Slice: stitching_compress_lut_7 */ +#define STITCHING_COMPRESS_LUT_7 +#define STITCHING_COMPRESS_LUT_7_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_7_SHIFT 10U +/*!Slice: stitching_compress_lut_6 */ +#define STITCHING_COMPRESS_LUT_6 +#define STITCHING_COMPRESS_LUT_6_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_6_SHIFT 0U +/*!Register: isp_stitching_compress_lut_3 (0x000033AC) */ +/*!Slice: stitching_compress_lut_11 */ +#define STITCHING_COMPRESS_LUT_11 +#define STITCHING_COMPRESS_LUT_11_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_11_SHIFT 20U +/*!Slice: stitching_compress_lut_10 */ +#define STITCHING_COMPRESS_LUT_10 +#define STITCHING_COMPRESS_LUT_10_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_10_SHIFT 10U +/*!Slice: stitching_compress_lut_9 */ +#define STITCHING_COMPRESS_LUT_9 +#define STITCHING_COMPRESS_LUT_9_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_9_SHIFT 0U +/*!Register: isp_stitching_compress_lut_4 (0x000033B0) */ +/*!Slice: stitching_compress_lut_14 */ +#define STITCHING_COMPRESS_LUT_14 +#define STITCHING_COMPRESS_LUT_14_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_14_SHIFT 20U +/*!Slice: stitching_compress_lut_13 */ +#define STITCHING_COMPRESS_LUT_13 +#define STITCHING_COMPRESS_LUT_13_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_13_SHIFT 10U +/*!Slice: stitching_compress_lut_12 */ +#define STITCHING_COMPRESS_LUT_12 +#define STITCHING_COMPRESS_LUT_12_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_12_SHIFT 0U +/*/*!Register: isp_stitching_compress_lut_shd_0 (0x000033B4) */ +/*!Slice: stitching_compress_lut_shd_2 */ +#define STITCHING_COMPRESS_LUT_SHD_2 +#define STITCHING_COMPRESS_LUT_SHD_2_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_SHD_2_SHIFT 20U +/*!Slice: stitching_compress_lut_shd_1 */ +#define STITCHING_COMPRESS_LUT_SHD_1 +#define STITCHING_COMPRESS_LUT_SHD_1_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_SHD_1_SHIFT 10U +/*!Slice: stitching_compress_lut_shd_0 */ +#define STITCHING_COMPRESS_LUT_SHD_0 +#define STITCHING_COMPRESS_LUT_SHD_0_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_SHD_0_SHIFT 0U +/*!Register: isp_stitching_compress_lut_shd_1 (0x000033B8) */ +/*!Slice: stitching_compress_lut_shd_5 */ +#define STITCHING_COMPRESS_LUT_SHD_5 +#define STITCHING_COMPRESS_LUT_SHD_5_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_SHD_5_SHIFT 20U +/*!Slice: stitching_compress_lut_shd_4 */ +#define STITCHING_COMPRESS_LUT_SHD_4 +#define STITCHING_COMPRESS_LUT_SHD_4_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_SHD_4_SHIFT 10U +/*!Slice: stitching_compress_lut_shd_3 */ +#define STITCHING_COMPRESS_LUT_SHD_3 +#define STITCHING_COMPRESS_LUT_SHD_3_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_SHD_3_SHIFT 0U +/*!Register: isp_stitching_compress_lut_shd_2 (0x000033BC) */ +/*!Slice: stitching_compress_lut_shd_8 */ +#define STITCHING_COMPRESS_LUT_SHD_8 +#define STITCHING_COMPRESS_LUT_SHD_8_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_SHD_8_SHIFT 20U +/*!Slice: stitching_compress_lut_shd_7 */ +#define STITCHING_COMPRESS_LUT_SHD_7 +#define STITCHING_COMPRESS_LUT_SHD_7_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_SHD_7_SHIFT 10U +/*!Slice: stitching_compress_lut_shd_6 */ +#define STITCHING_COMPRESS_LUT_SHD_6 +#define STITCHING_COMPRESS_LUT_SHD_6_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_SHD_6_SHIFT 0U +/*!Register: isp_stitching_compress_lut_shd_3 (0x000033C0) */ +/*!Slice: stitching_compress_lut_shd_11 */ +#define STITCHING_COMPRESS_LUT_SHD_11 +#define STITCHING_COMPRESS_LUT_SHD_11_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_SHD_11_SHIFT 20U +/*!Slice: stitching_compress_lut_shd_10 */ +#define STITCHING_COMPRESS_LUT_SHD_10 +#define STITCHING_COMPRESS_LUT_SHD_10_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_SHD_10_SHIFT 10U +/*!Slice: stitching_compress_lut_shd_9 */ +#define STITCHING_COMPRESS_LUT_SHD_9 +#define STITCHING_COMPRESS_LUT_SHD_9_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_SHD_9_SHIFT 0U +/*!Register: isp_stitching_compress_lut_shd_4 (0x000033C4) */ +/*!Slice: stitching_compress_lut_shd_14 */ +#define STITCHING_COMPRESS_LUT_SHD_14 +#define STITCHING_COMPRESS_LUT_SHD_14_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_SHD_14_SHIFT 20U +/*!Slice: stitching_compress_lut_shd_13 */ +#define STITCHING_COMPRESS_LUT_SHD_13 +#define STITCHING_COMPRESS_LUT_SHD_13_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_SHD_13_SHIFT 10U +/*!Slice: stitching_compress_lut_shd_12 */ +#define STITCHING_COMPRESS_LUT_SHD_12 +#define STITCHING_COMPRESS_LUT_SHD_12_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_SHD_12_SHIFT 0U +/*!Register:isp_stitching_exp0_awb_gain_g (0x000033C8) */ +/*Slice:stiching_exp0_awb_gain_gr */ +#define STITCHING_EXP0_AWB_GAIN_GR +#define STITCHING_EXP0_AWB_GAIN_GR_MASK 0x03FF0000U +#define STITCHING_EXP0_AWB_GAIN_GR_SHIFT 16U +/*Slice:stiching_exp0_awb_gain_gb */ +#define STITCHING_EXP0_AWB_GAIN_GB +#define STITCHING_EXP0_AWB_GAIN_GB_MASK 0x000003FFU +#define STITCHING_EXP0_AWB_GAIN_GB_SHIFT 0U +/*Slice:stiching_exp0_awb_gain_r */ +#define STITCHING_EXP0_AWB_GAIN_R +#define STITCHING_EXP0_AWB_GAIN_R_MASK 0x03FF0000U +#define STITCHING_EXP0_AWB_GAIN_R_SHIFT 16U +/*Slice:stiching_exp0_awb_gain_b */ +#define STITCHING_EXP0_AWB_GAIN_B +#define STITCHING_EXP0_AWB_GAIN_B_MASK 0x000003FFU +#define STITCHING_EXP0_AWB_GAIN_B_SHIFT 0U +/*Slice:stiching_exp1_awb_gain_gr */ +#define STITCHING_EXP1_AWB_GAIN_GR +#define STITCHING_EXP1_AWB_GAIN_GR_MASK 0x03FF0000U +#define STITCHING_EXP1_AWB_GAIN_GR_SHIFT 16U +/*Slice:stiching_exp1_awb_gain_gb */ +#define STITCHING_EXP1_AWB_GAIN_GB +#define STITCHING_EXP1_AWB_GAIN_GB_MASK 0x000003FFU +#define STITCHING_EXP1_AWB_GAIN_GB_SHIFT 0U +/*Slice:stiching_exp1_awb_gain_r */ +#define STITCHING_EXP1_AWB_GAIN_R +#define STITCHING_EXP1_AWB_GAIN_R_MASK 0x03FF0000U +#define STITCHING_EXP1_AWB_GAIN_R_SHIFT 16U +/*Slice:stiching_exp1_awb_gain_b */ +#define STITCHING_EXP1_AWB_GAIN_B +#define STITCHING_EXP1_AWB_GAIN_B_MASK 0x000003FFU +#define STITCHING_EXP1_AWB_GAIN_B_SHIFT 0U +/*Slice:stiching_exp2_awb_gain_gr */ +#define STITCHING_EXP2_AWB_GAIN_GR +#define STITCHING_EXP2_AWB_GAIN_GR_MASK 0x03FF0000U +#define STITCHING_EXP2_AWB_GAIN_GR_SHIFT 16U +/*Slice:stiching_exp2_awb_gain_gb */ +#define STITCHING_EXP2_AWB_GAIN_GB +#define STITCHING_EXP2_AWB_GAIN_GB_MASK 0x000003FFU +#define STITCHING_EXP2_AWB_GAIN_GB_SHIFT 0U +/*Slice:stiching_exp0_awb_gain_r */ +#define STITCHING_EXP2_AWB_GAIN_R +#define STITCHING_EXP2_AWB_GAIN_R_MASK 0x03FF0000U +#define STITCHING_EXP2_AWB_GAIN_R_SHIFT 16U +/*Slice:stiching_exp0_awb_gain_b */ +#define STITCHING_EXP2_AWB_GAIN_B +#define STITCHING_EXP2_AWB_GAIN_B_MASK 0x000003FFU +#define STITCHING_EXP2_AWB_GAIN_B_SHIFT 0U +/*Register: isp_stitching_long_sat_params */ +/*!Slice: stitching_long_sat_thresh */ +#define STITCHING_LONG_SAT_THRESH +#define STITCHING_LONG_SAT_THRESH_MASK 0x00FFF000U +#define STITCHING_LONG_SAT_THRESH_SHIFT 12U +/*!Slice: stitching_long_sat_combine_weight */ +#define STITCHING_LONG_SAT_COMBINE_WEIGHT +#define STITCHING_LONG_SAT_COMBINE_WEIGHT_MASK 0x000001FF +#define STITCHING_LONG_SAT_COMBINE_WEIGHT_SHIFT 0U +//!Register: isp_stitching_bls_exp_out_0 (0x000033F8) +//! Slice: stitching_bls_exp_out_a: +#define STITCHING_BLS_EXP_OUT_A +#define STITCHING_BLS_EXP_OUT_A_MASK 0x0FFF0000U +#define STITCHING_BLS_EXP_OUT_A_SHIFT 16U +//! Slice: stitching_bls_exp_out_b: +#define STITCHING_BLS_EXP_OUT_B +#define STITCHING_BLS_EXP_OUT_B_MASK 0x00000FFFU +#define STITCHING_BLS_EXP_OUT_B_SHIFT 0U +//!Register: isp_stitching_bls_exp_out_1 (0x000033FC) +//! Slice: stitching_bls_exp_out_c: +#define STITCHING_BLS_EXP_OUT_C +#define STITCHING_BLS_EXP_OUT_C_MASK 0x0FFF0000U +#define STITCHING_BLS_EXP_OUT_C_SHIFT 16U +//! Slice: stitching_bls_exp_out_d: +#define STITCHING_BLS_EXP_OUT_D +#define STITCHING_BLS_EXP_OUT_D_MASK 0x00000FFFU +#define STITCHING_BLS_EXP_OUT_D_SHIFT 0U + +/*! Slice: ISP_STITCHING0_EXP_IMSC:*/ +#define STITCHING_MIS_HDR_EXP_COMPLETE_L +#define STITCHING_MIS_HDR_EXP_COMPLETE_L_MASK 0x00000008U +#define STITCHING_MIS_HDR_EXP_COMPLETE_L_SHIFT 3U +#define STITCHING_MIS_HDR_EXP_COMPLETE_S +#define STITCHING_MIS_HDR_EXP_COMPLETE_S_MASK 0x00000010U +#define STITCHING_MIS_HDR_EXP_COMPLETE_S_SHIFT 4U +#define STITCHING_MIS_HDR_EXP_COMPLETE_VS +#define STITCHING_MIS_HDR_EXP_COMPLETE_VS_MASK 0x00000020U +#define STITCHING_MIS_HDR_EXP_COMPLETE_VS_SHIFT 5U + +/*! Slice: ISP_STITCHING0_HIST_MIS:*/ +#define STITCHING_MIS_HDR_HIST_COMPLETE_VS +#define STITCHING_MIS_HDR_HIST_COMPLETE_VS_MASK 0x00000100U +#define STITCHING_MIS_HDR_HIST_COMPLETE_VS_SHIFT 8U +#define STITCHING_MIS_HDR_HIST_COMPLETE_S +#define STITCHING_MIS_HDR_HIST_COMPLETE_S_MASK 0x00000080U +#define STITCHING_MIS_HDR_HIST_COMPLETE_S_SHIFT 7U +#define STITCHING_MIS_HDR_HIST_COMPLETE_L +#define STITCHING_MIS_HDR_HIST_COMPLETE_L_MASK 0x00000040U +#define STITCHING_MIS_HDR_HIST_COMPLETE_L_SHIFT 6U + +/*!Slice: 2DNR ENABLE */ +#define ISP_2DNR_ENABLE +#define ISP_2DNR_ENABLE_MASK 0x00000001 +#define ISP_2DNR_ENABLE_SHIFT 0U +/*!Slice: 2DNR PRGAMMA STRENGTH */ +#define ISP_2DNR_PRGAMMA_STRENGTH +#define ISP_2DNR_PRGAMMA_STRENGTH_MASK 0x00003F80 +#define ISP_2DNR_PRGAMMA_STRENGTH_SHIFT 7U +/*!Slice: 2DNR STRENGTH */ +#define ISP_2DNR_STRENGTH +#define ISP_2DNR_STRENGTH_MASK 0x0000007F +#define ISP_2DNR_STRENGTH_SHIFT 0U +/*!Slice: 2DNR SIGMAY0 */ +#define ISP_2DNR_SIGMAY0 +#define ISP_2DNR_SIGMAY0_MASK 0x00000FFF +#define ISP_2DNR_SIGMAY0_SHIFT 0U +/*!Slice: 2DNR SIGMAY1 */ +#define ISP_2DNR_SIGMAY1 +#define ISP_2DNR_SIGMAY1_MASK 0x00FFF000 +#define ISP_2DNR_SIGMAY1_SHIFT 12U +/*!Slice: 2DNR SIGMAY2A */ +#define ISP_2DNR_SIGMAY2A +#define ISP_2DNR_SIGMAY2A_MASK 0x3F000000 +#define ISP_2DNR_SIGMAY2A_SHIFT 24U +/*!Slice: 2DNR SIGMAY2B */ +#define ISP_2DNR_SIGMAY2B +#define ISP_2DNR_SIGMAY2B_MASK 0x3F000000 +#define ISP_2DNR_SIGMAY2B_SHIFT 24U +/*!Slice: 2DNR SIGMAY3 */ +#define ISP_2DNR_SIGMAY3 +#define ISP_2DNR_SIGMAY3_MASK 0x00000FFF +#define ISP_2DNR_SIGMAY3_SHIFT 0U +/*!Slice: 2DNR SIGMAY4 */ +#define ISP_2DNR_SIGMAY4 +#define ISP_2DNR_SIGMAY4_MASK 0x00FFF000 +#define ISP_2DNR_SIGMAY4_SHIFT 12U +/*!Slice: 2DNR denoise2d_dummy_hblank */ +#define ISP_2DNR_DUMMY_HBLANK +#define ISP_2DNR_DUMMY_HBLANK_MASK 0x0000FFFF +#define ISP_2DNR_DUMMY_HBLANK_SHIFT 0U + +/*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */ +#define DENOISE3D_V20_NLM_STRENGTH_OFFSET +#define DENOISE3D_V20_NLM_STRENGTH_OFFSET_MASK 0X3FF80000 +#define DENOISE3D_V20_NLM_STRENGTH_OFFSET_SHIFT 19U + +/*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */ +#define DENOISE3D_V20_NLM_STRENGTH_MAX +#define DENOISE3D_V20_NLM_STRENGTH_MAX_MASK 0X0007ff00 +#define DENOISE3D_V20_NLM_STRENGTH_MAX_SHIFT 8U + +/*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */ +#define DENOISE3D_V20_NLM_STRENGTH_SLOPE +#define DENOISE3D_V20_NLM_STRENGTH_SLOPE_MASK 0X000000ff +#define DENOISE3D_V20_NLM_STRENGTH_SLOPE_SHIFT 0U + +/* Register: ISP_DENOISE3D_CTRL 0x00003700 */ +/* Slice: 10:10 denoise3d_read_ref_en */ +#define DENOISE3D_READ_REF_EN +#define DENOISE3D_READ_REF_EN_MASK 0x00000400U +#define DENOISE3D_READ_REF_EN_SHIFT 10U + +/* Slice: 9:9 denoise3d_raw_decompress_en */ +#define DENOISE3D_RAW_DECOMPRESS_EN +#define DENOISE3D_RAW_DECOMPRESS_EN_MASK 0x00000200U +#define DENOISE3D_RAW_DECOMPRESS_EN_SHIFT 9U + +/* Slice: 8:8 denoise3d_rew_compress_en */ +#define DENOISE3D_RAW_COMPRESS_EN +#define DENOISE3D_RAW_COMPRESS_EN_MASK 0x00000100U +#define DENOISE3D_RAW_COMPRESS_EN_SHIFT 8U + +/* Slice: 7:7 denoise3d_write_ref_en */ +#define DENOISE3D_WRITE_REF_EN +#define DENOISE3D_WRITE_REF_EN_MASK 0x00000080U +#define DENOISE3D_WRITE_REF_EN_SHIFT 7U +/* Register: ISP_DENOISE3D_CTRL 0x00003700 */ +/* Slice: 5:5 denoise3d_soft_reset */ +#define DENOISE3D_SOFT_RESET +#define DENOISE3D_SOFT_RESET_MASK 0x00000020U +#define DENOISE3D_SOFT_RESET_SHIFT 5U +/* Slice: 4:4 denoise3d_horizontal_en */ +#define DENOISE3D_HORIZONTAL_EN +#define DENOISE3D_HORIZONTAL_EN_MASK 0x00000010U +#define DENOISE3D_HORIZONTAL_EN_SHIFT 4U +/* Slice: 3:3 denoise3d_vertical_en */ +#define DENOISE3D_VERTICAL_EN +#define DENOISE3D_VERTICAL_EN_MASK 0x00000008U +#define DENOISE3D_VERTICAL_EN_SHIFT 3U +/* Slice: 2:2 denoise3d_temperal_en */ +#define DENOISE3D_TEMPERAL_EN +#define DENOISE3D_TEMPERAL_EN_MASK 0x00000004U +#define DENOISE3D_TEMPERAL_EN_SHIFT 2U +/* Slice: 1:1 denoise3d_dilate_en */ +#define DENOISE3D_DILATE_EN +#define DENOISE3D_DILATE_EN_MASK 0x00000002U +#define DENOISE3D_DILATE_EN_SHIFT 1U +/* Slice: 0:0 denoise3d_enable */ +#define DENOISE3D_ENABLE +#define DENOISE3D_ENABLE_MASK 0x00000001U +#define DENOISE3D_ENABLE_SHIFT 0U +/* Register: ISP_DENOISE3D_STRENGTH 0x00003704 */ +/* Slice: 29:19 denoise3d_update_temperal */ +#define DENOISE3D_UPDATE_TEMPERAL +#define DENOISE3D_UPDATE_TEMPERAL_MASK 0x3FF80000U +#define DENOISE3D_UPDATE_TEMPERAL_SHIFT 19U +/* Slice: 18 : 8 denoise3d_update_spacial */ +#define DENOISE3D_UPDATE_SPACIAL +#define DENOISE3D_UPDATE_SPACIAL_MASK 0x0007FF00U +#define DENOISE3D_UPDATE_SPACIAL_SHIFT 8U +/* Slice: 7 : 0 denoise3d_strength */ +#define DENOISE3D_STRENGTH +#define DENOISE3D_STRENGTH_MASK 0x000000FFU +#define DENOISE3D_STRENGTH_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_H 0x00003708 */ +/* Slice: 27:20 denoise3d_strength_curve_spacial */ +#define DENOISE3D_STRENGTH_CURVE_SPACIAL +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_h_inv */ +#define DENOISE3D_THR_EDGE_H_INV +#define DENOISE3D_THR_EDGE_H_INV_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_H_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_V 0x0000370C */ +/* Slice: 27:20 denoise3d_strength_curve_temperal */ +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_v_inv */ +#define DENOISE3D_THR_EDGE_V_INV +#define DENOISE3D_THR_EDGE_V_INV_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_V_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_S 0x00003710 */ +/* Slice: 19:0 denoise3d_range_s_inv */ +#define DENOISE3D_RANGE_S_INV +#define DENOISE3D_RANGE_S_INV_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_S_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_T 0x00003714 */ +/* Slice: 29:25 denoise3d_range_t_h */ +#define DENOISE3D_RANGE_T_H +#define DENOISE3D_RANGE_T_H_MASK 0x3E000000U +#define DENOISE3D_RANGE_T_H_SHIFT 25U +/* Slice: 24:20 denoise3d_range_t_v */ +#define DENOISE3D_RANGE_T_V +#define DENOISE3D_RANGE_T_V_MASK 0x01F00000U +#define DENOISE3D_RANGE_T_V_SHIFT 20U +/* Slice: 19 : 0 denoise3d_range_t_inv */ +#define DENOISE3D_RANGE_T_INV +#define DENOISE3D_RANGE_T_INV_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_T_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_MOTION 0x00003718 */ +/* Slice: 24:20 denoise3d_range_d */ +#define DENOISE3D_RANGE_D +#define DENOISE3D_RANGE_D_MASK 0x01F00000U +#define DENOISE3D_RANGE_D_SHIFT 20U +/* Slice: 19 : 0 denoise3d_motion_inv */ +#define DENOISE3D_MOTION_INV +#define DENOISE3D_MOTION_INV_MASK 0x000FFFFFU +#define DENOISE3D_MOTION_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_DELTA_INV 0x0000371C */ +/* Slice: 29:20 denoise3d_delta_h_inv */ +#define DENOISE3D_DELTA_H_INV +#define DENOISE3D_DELTA_H_INV_MASK 0x3FF00000U +#define DENOISE3D_DELTA_H_INV_SHIFT 20U +/* Slice: 19 : 10 denoise3d_delta_v_inv */ +#define DENOISE3D_DELTA_V_INV +#define DENOISE3D_DELTA_V_INV_MASK 0x000FFC00U +#define DENOISE3D_DELTA_V_INV_SHIFT 10U +/* Slice: 9 : 0 denoise3d_delta_t_inv */ +#define DENOISE3D_DELTA_T_INV +#define DENOISE3D_DELTA_T_INV_MASK 0x000003FFU +#define DENOISE3D_DELTA_T_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_0 0x00003720 */ +/* Slice: 29:20 denoise3d_spacial_curve0 */ +#define DENOISE3D_SPACIAL_CURVE0 +#define DENOISE3D_SPACIAL_CURVE0_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE0_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve1 */ +#define DENOISE3D_SPACIAL_CURVE1 +#define DENOISE3D_SPACIAL_CURVE1_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE1_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve2 */ +#define DENOISE3D_SPACIAL_CURVE2 +#define DENOISE3D_SPACIAL_CURVE2_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE2_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_1 0x00003724 */ +/* Slice: 29 : 20 denoise3d_spacial_curve3 */ +#define DENOISE3D_SPACIAL_CURVE3 +#define DENOISE3D_SPACIAL_CURVE3_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE3_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve4 */ +#define DENOISE3D_SPACIAL_CURVE4 +#define DENOISE3D_SPACIAL_CURVE4_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE4_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve5 */ +#define DENOISE3D_SPACIAL_CURVE5 +#define DENOISE3D_SPACIAL_CURVE5_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE5_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_2 0x00003728 */ +/* Slice: 29 : 20 denoise3d_spacial_curve6 */ +#define DENOISE3D_SPACIAL_CURVE6 +#define DENOISE3D_SPACIAL_CURVE6_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE6_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve7 */ +#define DENOISE3D_SPACIAL_CURVE7 +#define DENOISE3D_SPACIAL_CURVE7_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE7_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve8 */ +#define DENOISE3D_SPACIAL_CURVE8 +#define DENOISE3D_SPACIAL_CURVE8_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE8_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_3 0x0000372C */ +/* Slice: 29 : 20 denoise3d_spacial_curve9 */ +#define DENOISE3D_SPACIAL_CURVE9 +#define DENOISE3D_SPACIAL_CURVE9_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE9_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve10 */ +#define DENOISE3D_SPACIAL_CURVE10 +#define DENOISE3D_SPACIAL_CURVE10_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE10_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve11 */ +#define DENOISE3D_SPACIAL_CURVE11 +#define DENOISE3D_SPACIAL_CURVE11_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE11_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_4 0x00003730 */ +/* Slice: 29 : 20 denoise3d_spacial_curve12 */ +#define DENOISE3D_SPACIAL_CURVE12 +#define DENOISE3D_SPACIAL_CURVE12_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE12_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve13 */ +#define DENOISE3D_SPACIAL_CURVE13 +#define DENOISE3D_SPACIAL_CURVE13_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE13_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve14 */ +#define DENOISE3D_SPACIAL_CURVE14 +#define DENOISE3D_SPACIAL_CURVE14_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE14_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_5 0x00003734 */ +/* Slice: 19 : 10 denoise3d_spacial_curve15 */ +#define DENOISE3D_SPACIAL_CURVE15 +#define DENOISE3D_SPACIAL_CURVE15_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE15_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve16 */ +#define DENOISE3D_SPACIAL_CURVE16 +#define DENOISE3D_SPACIAL_CURVE16_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE16_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_0 0x00003738 */ +/* Slice: 29 : 20 denoise3d_temperal_curve0 */ +#define DENOISE3D_TEMPERAL_CURVE0 +#define DENOISE3D_TEMPERAL_CURVE0_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE0_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve1 */ +#define DENOISE3D_TEMPERAL_CURVE1 +#define DENOISE3D_TEMPERAL_CURVE1_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE1_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve2 */ +#define DENOISE3D_TEMPERAL_CURVE2 +#define DENOISE3D_TEMPERAL_CURVE2_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE2_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_1 0x0000373C */ +/* Slice: 29 : 20 denoise3d_temperal_curve3 */ +#define DENOISE3D_TEMPERAL_CURVE3 +#define DENOISE3D_TEMPERAL_CURVE3_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE3_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve4 */ +#define DENOISE3D_TEMPERAL_CURVE4 +#define DENOISE3D_TEMPERAL_CURVE4_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE4_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve5 */ +#define DENOISE3D_TEMPERAL_CURVE5 +#define DENOISE3D_TEMPERAL_CURVE5_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE5_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_2 0x00003740 */ +/* Slice: 29 : 20 denoise3d_temperal_curve6 */ +#define DENOISE3D_TEMPERAL_CURVE6 +#define DENOISE3D_TEMPERAL_CURVE6_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE6_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve7 */ +#define DENOISE3D_TEMPERAL_CURVE7 +#define DENOISE3D_TEMPERAL_CURVE7_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE7_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve8 */ +#define DENOISE3D_TEMPERAL_CURVE8 +#define DENOISE3D_TEMPERAL_CURVE8_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE8_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_3 0x00003744 */ +/* Slice: 29 : 20 denoise3d_temperal_curve9 */ +#define DENOISE3D_TEMPERAL_CURVE9 +#define DENOISE3D_TEMPERAL_CURVE9_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE9_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve10 */ +#define DENOISE3D_TEMPERAL_CURVE10 +#define DENOISE3D_TEMPERAL_CURVE10_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE10_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve11 */ +#define DENOISE3D_TEMPERAL_CURVE11 +#define DENOISE3D_TEMPERAL_CURVE11_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE11_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_4 0x00003748 */ +/* Slice: 29 : 20 denoise3d_temperal_curve12 */ +#define DENOISE3D_TEMPERAL_CURVE12 +#define DENOISE3D_TEMPERAL_CURVE12_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE12_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve13 */ +#define DENOISE3D_TEMPERAL_CURVE13 +#define DENOISE3D_TEMPERAL_CURVE13_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE13_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve14 */ +#define DENOISE3D_TEMPERAL_CURVE14 +#define DENOISE3D_TEMPERAL_CURVE14_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE14_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_5 0x0000374C */ +/* Slice: 19 : 10 denoise3d_temperal_curve15 */ +#define DENOISE3D_TEMPERAL_CURVE15 +#define DENOISE3D_TEMPERAL_CURVE15_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE15_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve16 */ +#define DENOISE3D_TEMPERAL_CURVE16 +#define DENOISE3D_TEMPERAL_CURVE16_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE16_SHIFT 0U +/* Register: ISP_DENOISE3D_AVERAGE 0x00003750 */ +/* Slice: 31 : 0 denoise3d_frame_average */ +#define DENOISE3D_FRAME_AVERAGE +#define DENOISE3D_FRAME_AVERAGE_MASK 0xFFFFFFFFU +#define DENOISE3D_FRAME_AVERAGE_SHIFT 0U +/* Register: ISP_DENOISE3D_STRENGTH_SHD 0x00003754 */ +/* Slice: 29 : 19 denoise3d_update_temperal_shd */ +#define DENOISE3D_UPDATE_TEMPERAL_SHD +#define DENOISE3D_UPDATE_TEMPERAL_SHD_MASK 0x3FF80000U +#define DENOISE3D_UPDATE_TEMPERAL_SHD_SHIFT 19U +/* Slice: 18 : 8 denoise3d_update_spacial_shd */ +#define DENOISE3D_UPDATE_SPACIAL_SHD +#define DENOISE3D_UPDATE_SPACIAL_SHD_MASK 0x0007FF00U +#define DENOISE3D_UPDATE_SPACIAL_SHD_SHIFT 8U +/* Slice: 7 : 0 denoise3d_strength_shd */ +#define DENOISE3D_STRENGTH_SHD +#define DENOISE3D_STRENGTH_SHD_MASK 0x0000000FU +#define DENOISE3D_STRENGTH_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_H_SHD 0x00003758 */ +/* Slice: 27 : 20 denoise3d_strength_curve_spacial_shd */ +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_h_inv_shd */ +#define DENOISE3D_THR_EDGE_H_INV_SHD +#define DENOISE3D_THR_EDGE_H_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_H_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_V_SHD 0x0000375C */ +/* Slice: 27 : 20 denoise3d_strength_curve_temperal_shd */ +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_v_inv_shd */ +#define DENOISE3D_THR_EDGE_V_INV_SHD +#define DENOISE3D_THR_EDGE_V_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_V_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_S_SHD 0x00003760 */ +/* Slice: 19 : 0 denoise3d_range_s_inv_shd */ +#define DENOISE3D_RANGE_S_INV_SHD +#define DENOISE3D_RANGE_S_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_S_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_T_SHD 0x00003764 */ +/* Slice: 29 : 25 denoise3d_range_t_h_shd */ +#define DENOISE3D_RANGE_T_H_SHD +#define DENOISE3D_RANGE_T_H_SHD_MASK 0x3E000000U +#define DENOISE3D_RANGE_T_H_SHD_SHIFT 25U +/* Slice: 24 : 20 denoise3d_range_t_v_shd */ +#define DENOISE3D_RANGE_T_V_SHD +#define DENOISE3D_RANGE_T_V_SHD_MASK 0x01F00000U +#define DENOISE3D_RANGE_T_V_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_range_t_inv_shd */ +#define DENOISE3D_RANGE_T_INV_SHD +#define DENOISE3D_RANGE_T_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_T_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_MOTION_SHD 0x00003768 */ +/* Slice: 24 : 20 denoise3d_range_d_shd */ +#define DENOISE3D_RANGE_D_SHD +#define DENOISE3D_RANGE_D_SHD_MASK 0x01F00000U +#define DENOISE3D_RANGE_D_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_motion_inv_shd */ +#define DENOISE3D_MOTION_INV_SHD +#define DENOISE3D_MOTION_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_MOTION_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_DELTA_INV_SHD 0x0000376C */ +/* Slice: 29 : 20 denoise3d_delta_h_inv_shd */ +#define DENOISE3D_DELTA_H_INV_SHD +#define DENOISE3D_DELTA_H_INV_SHD_MASK 0x3FF00000U +#define DENOISE3D_DELTA_H_INV_SHD_SHIFT 20U +/* Slice: 19 : 10 denoise3d_delta_v_inv_shd */ +#define DENOISE3D_DELTA_V_INV_SHD +#define DENOISE3D_DELTA_V_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_DELTA_V_INV_SHD_SHIFT 10U +/* Slice: 9 : 0 denoise3d_delta_t_inv_shd */ +#define DENOISE3D_DELTA_T_INV_SHD +#define DENOISE3D_DELTA_T_INV_SHD_MASK 0x000003FFU +#define DENOISE3D_DELTA_T_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_DUMMY_HBLANK 0x00003770 */ +/* Slice: 14 : 0 denoise3d_H_Blank */ +#define DENOISE3D_H_BLANK +#define DENOISE3D_H_BLANK_MASK 0x0000FFFFU +#define DENOISE3D_H_BLANK_SHIFT 0U +/* Register: ISP_DENOISE3D_CTRL 0x00003700 */ +/* Slice: 5:5 denoise3d_soft_reset */ +#define DENOISE3D_SOFT_RESET +#define DENOISE3D_SOFT_RESET_MASK 0x00000020U +#define DENOISE3D_SOFT_RESET_SHIFT 5U +/* Slice: 4:4 denoise3d_horizontal_en */ +#define DENOISE3D_HORIZONTAL_EN +#define DENOISE3D_HORIZONTAL_EN_MASK 0x00000010U +#define DENOISE3D_HORIZONTAL_EN_SHIFT 4U +/* Slice: 3:3 denoise3d_vertical_en */ +#define DENOISE3D_VERTICAL_EN +#define DENOISE3D_VERTICAL_EN_MASK 0x00000008U +#define DENOISE3D_VERTICAL_EN_SHIFT 3U +/* Slice: 2:2 denoise3d_temperal_en */ +#define DENOISE3D_TEMPERAL_EN +#define DENOISE3D_TEMPERAL_EN_MASK 0x00000004U +#define DENOISE3D_TEMPERAL_EN_SHIFT 2U +/* Slice: 1:1 denoise3d_dilate_en */ +#define DENOISE3D_DILATE_EN +#define DENOISE3D_DILATE_EN_MASK 0x00000002U +#define DENOISE3D_DILATE_EN_SHIFT 1U +/* Slice: 0:0 denoise3d_enable */ +#define DENOISE3D_ENABLE +#define DENOISE3D_ENABLE_MASK 0x00000001U +#define DENOISE3D_ENABLE_SHIFT 0U +/* Register: ISP_DENOISE3D_STRENGTH 0x00003704 */ +/* Slice: 29:19 denoise3d_update_temperal */ +#define DENOISE3D_UPDATE_TEMPERAL +#define DENOISE3D_UPDATE_TEMPERAL_MASK 0x3FF80000U +#define DENOISE3D_UPDATE_TEMPERAL_SHIFT 19U +/* Slice: 18 : 8 denoise3d_update_spacial */ +#define DENOISE3D_UPDATE_SPACIAL +#define DENOISE3D_UPDATE_SPACIAL_MASK 0x0007FF00U +#define DENOISE3D_UPDATE_SPACIAL_SHIFT 8U +/* Slice: 7 : 0 denoise3d_strength */ +#define DENOISE3D_STRENGTH +#define DENOISE3D_STRENGTH_MASK 0x000000FFU +#define DENOISE3D_STRENGTH_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_H 0x00003708 */ +/* Slice: 27:20 denoise3d_strength_curve_spacial */ +#define DENOISE3D_STRENGTH_CURVE_SPACIAL +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_h_inv */ +#define DENOISE3D_THR_EDGE_H_INV +#define DENOISE3D_THR_EDGE_H_INV_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_H_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_V 0x0000370C */ +/* Slice: 27:20 denoise3d_strength_curve_temperal */ +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_v_inv */ +#define DENOISE3D_THR_EDGE_V_INV +#define DENOISE3D_THR_EDGE_V_INV_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_V_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_S 0x00003710 */ +/* Slice: 19:0 denoise3d_range_s_inv */ +#define DENOISE3D_RANGE_S_INV +#define DENOISE3D_RANGE_S_INV_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_S_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_T 0x00003714 */ +/* Slice: 29:25 denoise3d_range_t_h */ +#define DENOISE3D_RANGE_T_H +#define DENOISE3D_RANGE_T_H_MASK 0x3E000000U +#define DENOISE3D_RANGE_T_H_SHIFT 25U +/* Slice: 24:20 denoise3d_range_t_v */ +#define DENOISE3D_RANGE_T_V +#define DENOISE3D_RANGE_T_V_MASK 0x01F00000U +#define DENOISE3D_RANGE_T_V_SHIFT 20U +/* Slice: 19 : 0 denoise3d_range_t_inv */ +#define DENOISE3D_RANGE_T_INV +#define DENOISE3D_RANGE_T_INV_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_T_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_MOTION 0x00003718 */ +/* Slice: 24:20 denoise3d_range_d */ +#define DENOISE3D_RANGE_D +#define DENOISE3D_RANGE_D_MASK 0x01F00000U +#define DENOISE3D_RANGE_D_SHIFT 20U +/* Slice: 19 : 0 denoise3d_motion_inv */ +#define DENOISE3D_MOTION_INV +#define DENOISE3D_MOTION_INV_MASK 0x000FFFFFU +#define DENOISE3D_MOTION_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_DELTA_INV 0x0000371C */ +/* Slice: 29:20 denoise3d_delta_h_inv */ +#define DENOISE3D_DELTA_H_INV +#define DENOISE3D_DELTA_H_INV_MASK 0x3FF00000U +#define DENOISE3D_DELTA_H_INV_SHIFT 20U +/* Slice: 19 : 10 denoise3d_delta_v_inv */ +#define DENOISE3D_DELTA_V_INV +#define DENOISE3D_DELTA_V_INV_MASK 0x000FFC00U +#define DENOISE3D_DELTA_V_INV_SHIFT 10U +/* Slice: 9 : 0 denoise3d_delta_t_inv */ +#define DENOISE3D_DELTA_T_INV +#define DENOISE3D_DELTA_T_INV_MASK 0x000003FFU +#define DENOISE3D_DELTA_T_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_0 0x00003720 */ +/* Slice: 29:20 denoise3d_spacial_curve0 */ +#define DENOISE3D_SPACIAL_CURVE0 +#define DENOISE3D_SPACIAL_CURVE0_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE0_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve1 */ +#define DENOISE3D_SPACIAL_CURVE1 +#define DENOISE3D_SPACIAL_CURVE1_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE1_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve2 */ +#define DENOISE3D_SPACIAL_CURVE2 +#define DENOISE3D_SPACIAL_CURVE2_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE2_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_0 0x00003738 */ +/* Slice: 29 : 20 denoise3d_temperal_curve0 */ +#define DENOISE3D_TEMPERAL_CURVE0 +#define DENOISE3D_TEMPERAL_CURVE0_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE0_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve1 */ +#define DENOISE3D_TEMPERAL_CURVE1 +#define DENOISE3D_TEMPERAL_CURVE1_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE1_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve2 */ +#define DENOISE3D_TEMPERAL_CURVE2 +#define DENOISE3D_TEMPERAL_CURVE2_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE2_SHIFT 0U +/* Register: ISP_DENOISE3D_AVERAGE 0x00003750 */ +/* Slice: 31 : 0 denoise3d_frame_average */ +#define DENOISE3D_FRAME_AVERAGE +#define DENOISE3D_FRAME_AVERAGE_MASK 0xFFFFFFFFU +#define DENOISE3D_FRAME_AVERAGE_SHIFT 0U +/* Register: ISP_DENOISE3D_STRENGTH_SHD 0x00003754 */ +/* Slice: 29 : 19 denoise3d_update_temperal_shd */ +#define DENOISE3D_UPDATE_TEMPERAL_SHD +#define DENOISE3D_UPDATE_TEMPERAL_SHD_MASK 0x3FF80000U +#define DENOISE3D_UPDATE_TEMPERAL_SHD_SHIFT 19U +/* Slice: 18 : 8 denoise3d_update_spacial_shd */ +#define DENOISE3D_UPDATE_SPACIAL_SHD +#define DENOISE3D_UPDATE_SPACIAL_SHD_MASK 0x0007FF00U +#define DENOISE3D_UPDATE_SPACIAL_SHD_SHIFT 8U +/* Slice: 7 : 0 denoise3d_strength_shd */ +#define DENOISE3D_STRENGTH_SHD +#define DENOISE3D_STRENGTH_SHD_MASK 0x0000000FU +#define DENOISE3D_STRENGTH_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_H_SHD 0x00003758 */ +/* Slice: 27 : 20 denoise3d_strength_curve_spacial_shd */ +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_h_inv_shd */ +#define DENOISE3D_THR_EDGE_H_INV_SHD +#define DENOISE3D_THR_EDGE_H_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_H_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_V_SHD 0x0000375C */ +/* Slice: 27 : 20 denoise3d_strength_curve_temperal_shd */ +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_v_inv_shd */ +#define DENOISE3D_THR_EDGE_V_INV_SHD +#define DENOISE3D_THR_EDGE_V_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_V_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_S_SHD 0x00003760 */ +/* Slice: 19 : 0 denoise3d_range_s_inv_shd */ +#define DENOISE3D_RANGE_S_INV_SHD +#define DENOISE3D_RANGE_S_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_S_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_T_SHD 0x00003764 */ +/* Slice: 29 : 25 denoise3d_range_t_h_shd */ +#define DENOISE3D_RANGE_T_H_SHD +#define DENOISE3D_RANGE_T_H_SHD_MASK 0x3E000000U +#define DENOISE3D_RANGE_T_H_SHD_SHIFT 25U +/* Slice: 24 : 20 denoise3d_range_t_v_shd */ +#define DENOISE3D_RANGE_T_V_SHD +#define DENOISE3D_RANGE_T_V_SHD_MASK 0x01F00000U +#define DENOISE3D_RANGE_T_V_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_range_t_inv_shd */ +#define DENOISE3D_RANGE_T_INV_SHD +#define DENOISE3D_RANGE_T_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_T_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_MOTION_SHD 0x00003768 */ +/* Slice: 24 : 20 denoise3d_range_d_shd */ +#define DENOISE3D_RANGE_D_SHD +#define DENOISE3D_RANGE_D_SHD_MASK 0x01F00000U +#define DENOISE3D_RANGE_D_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_motion_inv_shd */ +#define DENOISE3D_MOTION_INV_SHD +#define DENOISE3D_MOTION_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_MOTION_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_DELTA_INV_SHD 0x0000376C */ +/* Slice: 29 : 20 denoise3d_delta_h_inv_shd */ +#define DENOISE3D_DELTA_H_INV_SHD +#define DENOISE3D_DELTA_H_INV_SHD_MASK 0x3FF00000U +#define DENOISE3D_DELTA_H_INV_SHD_SHIFT 20U +/* Slice: 19 : 10 denoise3d_delta_v_inv_shd */ +#define DENOISE3D_DELTA_V_INV_SHD +#define DENOISE3D_DELTA_V_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_DELTA_V_INV_SHD_SHIFT 10U +/* Slice: 9 : 0 denoise3d_delta_t_inv_shd */ +#define DENOISE3D_DELTA_T_INV_SHD +#define DENOISE3D_DELTA_T_INV_SHD_MASK 0x000003FFU +#define DENOISE3D_DELTA_T_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_DUMMY_HBLANK 0x00003770 */ +/* Slice: 14 : 0 denoise3d_H_Blank */ +#define DENOISE3D_H_BLANK +#define DENOISE3D_H_BLANK_MASK 0x0000FFFFU +#define DENOISE3D_H_BLANK_SHIFT 0U +/* Register: ISP_DENOISE3D_WEIGHT1 0x00003778 */ +/* Slice: denoise3d_weight_up_y0 */ +#define DENOISE3D_WEIGHT_UP_Y0 +#define DENOISE3D_WEIGHT_UP_Y0_MASK 0x00F00000U +#define DENOISE3D_WEIGHT_UP_Y0_SHIFT 20U +#define DENOISE3D_WEIGHT_UP_Y1 +#define DENOISE3D_WEIGHT_UP_Y1_MASK 0x000F0000U +#define DENOISE3D_WEIGHT_UP_Y1_SHIFT 16U +#define DENOISE3D_WEIGHT +#define DENOISE3D_WEIGHT_MASK 0x0000000FU +#define DENOISE3D_WEIGHT_SHIFT 0U +/*! for miv2 by shenchao */ +/*! Register: miv2_ctrl (0x00001300)*/ +/*! Slice: sp2_raw2_continous:*/ +#define SP2_RAW2_CONTINUOUS +#define SP2_RAW2_CONTINUOUS_MASK 0x1 << 24 +#define SP2_RAW2_CONTINUOUS_SHIFT 24U + +#define SP2_RAW2_START +#define SP2_RAW2_START_MASK 0x1 << 23 +#define SP2_RAW2_START_SHIFT 23U + +#define PP_DMA_CONTINUOUS +#define PP_DMA_CONTINUOUS_MASK 0x1 << 22 +#define PP_DMA_CONTINUOUS_SHIFT 22U + +#define PP_DMA_START +#define PP_DMA_START_MASK 0x1 << 21 +#define PP_DMA_START_SHIFT 21U + +#define SP2_RAW2_WRITE_PATH_ENABLE +#define SP2_RAW2_WRITE_PATH_ENABLE_MASK 0x1 << 20 +#define SP2_RAW2_WRITE_PATH_ENABLE_SHIFT 20U + +#define PP_WRITE_PATH_ENABLE +#define PP_WRITE_PATH_ENABLE_MASK 0x1 << 19 +#define PP_WRITE_PATH_ENABLE_SHIFT 19U + +#define MCM_G2_RAW1_PATH_ENABLE +#define MCM_G2_RAW1_PATH_ENABLE_MASK 0x1 << 18 +#define MCM_G2_RAW1_PATH_ENABLE_SHIFT 18U + +#define MCM_G2_RAW0_PATH_ENABLE +#define MCM_G2_RAW0_PATH_ENABLE_MASK 0x1 << 17 +#define MCM_G2_RAW0_PATH_ENABLE_SHIFT 17U + +//! Register: isp_hdr_exp_conf: Exposure control (0x00000000) +//! Slice: exp_meas_mode: +//! '1' luminance calculation according to +// Y=(R+G+B) x 0.332 (85/256) +// '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B +#define MRV_HDR_EXP_MEAS_MODE +#define MRV_HDR_EXP_MEAS_MODE_MASK 0x80000000U +#define MRV_HDR_EXP_MEAS_MODE_SHIFT 31U +//! Slice: src_select: +#define MRV_HDR_EXP_SRC_SEL +#define MRV_HDR_EXP_SRC_SEL_MASK 0x00000004U +#define MRV_HDR_EXP_SRC_SEL_SHIFT 2U +//! Slice: autostop: +//! '1' stop measuring after a complete frame +// '0' continous measurement +#define MRV_HDR_EXP_AUTOSTOP +#define MRV_HDR_EXP_AUTOSTOP_MASK 0x00000002U +#define MRV_HDR_EXP_AUTOSTOP_SHIFT 1U +//! Slice: exp_start: +//! '1' start measuring a frame. The exp block will reset this bit and halt after completing one frame, if bit "autostop" is set to '1'. +#define MRV_HDR_EXP_START +#define MRV_HDR_EXP_START_MASK 0x00000001U +#define MRV_HDR_EXP_START_SHIFT 0U + +//! Register: isp_hdr_exp_h_offset: Horizontal offset for first block (0x00000004) +#define MRV_ISP_HDR_EXP_H_OFFSET +#define MRV_ISP_HDR_EXP_H_OFFSET_MASK 0x00001FFFU +#define MRV_ISP_HDR_EXP_H_OFFSET_SHIFT 0U + +//! Register: isp_hdr_exp_v_offset: Vertical offset for first block (0x00000008) +#define MRV_ISP_HDR_EXP_V_OFFSET +#define MRV_ISP_HDR_EXP_V_OFFSET_MASK 0x00001FFFU +#define MRV_ISP_HDR_EXP_V_OFFSET_SHIFT 0U + +//! Register: isp_exp_h_size: Horizontal size of one block (0x0000000c) +#define MRV_ISP_HDR_EXP_H_SIZE +#define MRV_ISP_HDR_EXP_H_SIZE_MASK 0x000007FFU +#define MRV_ISP_HDR_EXP_H_SIZE_SHIFT 0U + +//! Register: isp_exp_v_size: Vertical size of one block (0x00000010) +#define MRV_ISP_HDR_EXP_V_SIZE +#define MRV_ISP_HDR_EXP_V_SIZE_MASK 0x000007FEU +#define MRV_ISP_HDR_EXP_V_SIZE_SHIFT 0U +/*! for miv2 by shenchao */ +/*! Register: miv2_ctrl (0x00001300)*/ +/*! Slice: mcm_raw_rdma_start_con:*/ +#define MCM_RAW_RDMA_START_CON +#define MCM_RAW_RDMA_START_CON_MASK 0x00010000U +#define MCM_RAW_RDMA_START_CON_SHIFT 16U +/*! Slice: mcm_raw_rdma_start:*/ +#define MCM_RAW_RDMA_START +#define MCM_RAW_RDMA_START_MASK 0x00008000U +#define MCM_RAW_RDMA_START_SHIFT 15U +/*! Slice: mcm_raw_rdma_path_enable:*/ +#define MCM_RAW_RDMA_PATH_ENABLE +#define MCM_RAW_RDMA_PATH_ENABLE_MASK 0x00004000U +#define MCM_RAW_RDMA_PATH_ENABLE_SHIFT 14U +/*! Slice: sp2_raw2_rdma_start_con:*/ +#define SP2_RAW2_RDMA_START_CON +#define SP2_RAW2_RDMA_START_CON_MASK 0x01000000U +#define SP2_RAW2_RDMA_START_CON_SHIFT 24U +/*! Slice: sp2_raw2_rdma_start:*/ +#define SP2_RAW2_RDMA_START +#define SP2_RAW2_RDMA_START_MASK 0x00800000U +#define SP2_RAW2_RDMA_START_SHIFT 23U +/*! Slice: sp2_raw_rdma_start_con:*/ +#define SP2_RAW_RDMA_START_CON +#define SP2_RAW_RDMA_START_CON_MASK 0x00002000U +#define SP2_RAW_RDMA_START_CON_SHIFT 13U +/*! Slice: sp2_raw_rdma_start:*/ +#define SP2_RAW_RDMA_START +#define SP2_RAW_RDMA_START_MASK 0x00001000U +#define SP2_RAW_RDMA_START_SHIFT 12U +/*! Slice: sp2_raw_rdma_path_enable:*/ +#define SP2_RAW_RDMA_PATH_ENABLE +#define SP2_RAW_RDMA_PATH_ENABLE_MASK 0x00000800U +#define SP2_RAW_RDMA_PATH_ENABLE_SHIFT 11U +/*! Slice: sp2_ycbcr_rdma_start_con:*/ +#define SP2_YCBCR_RDMA_START_CON +#define SP2_YCBCR_RDMA_START_CON_MASK 0x00000400U +#define SP2_YCBCR_RDMA_START_CON_SHIFT 10U +/*! Slice: sp2_ycbcr_rdma_start:*/ +#define SP2_YCBCR_RDMA_START +#define SP2_YCBCR_RDMA_START_MASK 0x00000200U +#define SP2_YCBCR_RDMA_START_SHIFT 9U +/*! Slice: sp2_ycbcr_rdma_path_enable:*/ +#define SP2_YCBCR_RDMA_PATH_ENABLE +#define SP2_YCBCR_RDMA_PATH_ENABLE_MASK 0x00000100U +#define SP2_YCBCR_RDMA_PATH_ENABLE_SHIFT 8U +/*! Slice: mcm_raw1_path_enable:*/ +#define MCM_RAW1_PATH_ENABLE +#define MCM_RAW1_PATH_ENABLE_MASK 0x00000080U +#define MCM_RAW1_PATH_ENABLE_SHIFT 7U +/*! Slice: mcm_raw0_path_enable:*/ +#define MCM_RAW0_PATH_ENABLE +#define MCM_RAW0_PATH_ENABLE_MASK 0x00000040U +#define MCM_RAW0_PATH_ENABLE_SHIFT 6U +/*! Slice: sp2_raw_path_enable:*/ +#define SP2_RAW_PATH_ENABLE +#define SP2_RAW_PATH_ENABLE_MASK 0x00000020U +#define SP2_RAW_PATH_ENABLE_SHIFT 5U +/*! Slice: sp2_ycbcr_path_enable:*/ +#define SP2_YCBCR_PATH_ENABLE +#define SP2_YCBCR_PATH_ENABLE_MASK 0x00000010U +#define SP2_YCBCR_PATH_ENABLE_SHIFT 4U +/*! Slice: sp1_ycbcr_path_enable:*/ +#define SP1_YCBCR_PATH_ENABLE +#define SP1_YCBCR_PATH_ENABLE_MASK 0x00000008U +#define SP1_YCBCR_PATH_ENABLE_SHIFT 3U +/*! Slice: mp_jdp_path_enable:*/ +#define MP_JDP_PATH_ENABLE +#define MP_JDP_PATH_ENABLE_MASK 0x00000004U +#define MP_JDP_PATH_ENABLE_SHIFT 2U +/*! Slice: mp_raw_path_enable:*/ +#define MP_RAW_PATH_ENABLE +#define MP_RAW_PATH_ENABLE_MASK 0x00000002U +#define MP_RAW_PATH_ENABLE_SHIFT 1U +/*! Slice: mp_ycbcr_path_enable:*/ +#define MP_YCBCR_PATH_ENABLE +#define MP_YCBCR_PATH_ENABLE_MASK 0x00000001U +#define MP_YCBCR_PATH_ENABLE_SHIFT 0U +/*! Register: miv2_ctrl_shd (0x00001304)*/ +/*! Slice: mcm_raw_rdma_start_con:*/ +#define MCM_RAW_RDMA_START_CON +#define MCM_RAW_RDMA_START_CON_MASK 0x00010000U +#define MCM_RAW_RDMA_START_CON_SHIFT 16U +/*! Slice: mcm_raw_rdma_start:*/ +#define MCM_RAW_RDMA_START +#define MCM_RAW_RDMA_START_MASK 0x00008000U +#define MCM_RAW_RDMA_START_SHIFT 15U +/*! Slice: mcm_raw_rdma_path_enable:*/ +#define MCM_RAW_RDMA_PATH_ENABLE +#define MCM_RAW_RDMA_PATH_ENABLE_MASK 0x00004000U +#define MCM_RAW_RDMA_PATH_ENABLE_SHIFT 14U +/*! Slice: sp2_raw_rdma_start_con:*/ +#define SP2_RAW_RDMA_START_CON +#define SP2_RAW_RDMA_START_CON_MASK 0x00002000U +#define SP2_RAW_RDMA_START_CON_SHIFT 13U +/*! Slice: sp2_raw_rdma_start:*/ +#define SP2_RAW_RDMA_START +#define SP2_RAW_RDMA_START_MASK 0x00001000U +#define SP2_RAW_RDMA_START_SHIFT 12U +/*! Slice: sp2_raw_rdma_path_enable:*/ +#define SP2_RAW_RDMA_PATH_ENABLE +#define SP2_RAW_RDMA_PATH_ENABLE_MASK 0x00000800U +#define SP2_RAW_RDMA_PATH_ENABLE_SHIFT 11U +/*! Slice: sp2_ycbcr_rdma_start_con:*/ +#define SP2_YCBCR_RDMA_START_CON +#define SP2_YCBCR_RDMA_START_CON_MASK 0x00000400U +#define SP2_YCBCR_RDMA_START_CON_SHIFT 10U +/*! Slice: sp2_ycbcr_rdma_start:*/ +#define SP2_YCBCR_RDMA_START +#define SP2_YCBCR_RDMA_START_MASK 0x00000200U +#define SP2_YCBCR_RDMA_START_SHIFT 9U +/*! Slice: sp2_ycbcr_rdma_path_enable:*/ +#define SP2_YCBCR_RDMA_PATH_ENABLE +#define SP2_YCBCR_RDMA_PATH_ENABLE_MASK 0x00000100U +#define SP2_YCBCR_RDMA_PATH_ENABLE_SHIFT 8U +/*! Slice: mcm_raw1_path_enable:*/ +#define MCM_RAW1_PATH_ENABLE +#define MCM_RAW1_PATH_ENABLE_MASK 0x00000080U +#define MCM_RAW1_PATH_ENABLE_SHIFT 7U +/*! Slice: mcm_raw0_path_enable:*/ +#define MCM_RAW0_PATH_ENABLE +#define MCM_RAW0_PATH_ENABLE_MASK 0x00000040U +#define MCM_RAW0_PATH_ENABLE_SHIFT 6U +/*! Slice: sp2_raw_path_enable:*/ +#define SP2_RAW_PATH_ENABLE +#define SP2_RAW_PATH_ENABLE_MASK 0x00000020U +#define SP2_RAW_PATH_ENABLE_SHIFT 5U +/*! Slice: sp2_ycbcr_path_enable:*/ +#define SP2_YCBCR_PATH_ENABLE +#define SP2_YCBCR_PATH_ENABLE_MASK 0x00000010U +#define SP2_YCBCR_PATH_ENABLE_SHIFT 4U +/*! Slice: sp1_ycbcr_path_enable:*/ +#define SP1_YCBCR_PATH_ENABLE +#define SP1_YCBCR_PATH_ENABLE_MASK 0x00000008U +#define SP1_YCBCR_PATH_ENABLE_SHIFT 3U +/*! Slice: mp_jdp_path_enable:*/ +#define MP_JDP_PATH_ENABLE +#define MP_JDP_PATH_ENABLE_MASK 0x00000004U +#define MP_JDP_PATH_ENABLE_SHIFT 2U +/*! Slice: mp_raw_path_enable:*/ +#define MP_RAW_PATH_ENABLE +#define MP_RAW_PATH_ENABLE_MASK 0x00000002U +#define MP_RAW_PATH_ENABLE_SHIFT 1U +/*! Slice: mp_ycbcr_path_enable:*/ +#define MP_YCBCR_PATH_ENABLE +#define MP_YCBCR_PATH_ENABLE_MASK 0x00000001U +#define MP_YCBCR_PATH_ENABLE_SHIFT 0U +/*! Register: miv2_mp_ctrl (0x00001310)*/ +/*! Slice: mp_init_offset_en:*/ +#define MP_INIT_OFFSET_EN +#define MP_INIT_OFFSET_EN_MASK 0x00000020U +#define MP_INIT_OFFSET_EN_SHIFT 5U +/*! Slice: mp_init_base_en:*/ +#define MP_INIT_BASE_EN +#define MP_INIT_BASE_EN_MASK 0x00000010U +#define MP_INIT_BASE_EN_SHIFT 4U +/*! Slice: mp_miv2_cfg_upd:*/ +#define MP_MI_CFG_UPD +#define MP_MI_CFG_UPD_MASK 0x00000008U +#define MP_MI_CFG_UPD_SHIFT 3U +/*! Slice: mp_miv2_skip:*/ +#define MP_MI_SKIP +#define MP_MI_SKIP_MASK 0x00000004U +#define MP_MI_SKIP_SHIFT 2U +/*! Slice: mp_auto_update:*/ +#define MP_AUTO_UPDATE +#define MP_AUTO_UPDATE_MASK 0x00000002U +#define MP_AUTO_UPDATE_SHIFT 1U +/*! Slice: mp_pingpong_enable:*/ +#define MP_PINGPONG_ENABLE +#define MP_PINGPONG_ENABLE_MASK 0x00000001U +#define MP_PINGPONG_ENABLE_SHIFT 0U +/*! Register: miv2_mp_fmt (0x00001314)*/ +/*! Slice: mp_wr_jdp_dp_bit:*/ +#define MP_WR_JDP_DP_BIT +#define MP_WR_JDP_DP_BIT_MASK 0x000020000U +#define MP_WR_JDP_DP_BIT_SHIFT 17U + +/*! Slice: mp_wr_yuv_nvy:*/ +#define MP_WR_YUV_NVY +#define MP_WR_YUV_NVY_MASK 0x00006000U +#define MP_WR_YUV_NVY_SHIFT 13U +/*! Slice: mp_wr_yuv_nv21:*/ +#define MP_WR_YUV_NV21 +#define MP_WR_YUV_NV21_MASK 0x00001000U +#define MP_WR_YUV_NV21_SHIFT 12U +/*! Slice: mp_wr_raw_aligned:*/ +#define MP_WR_RAW_ALIGNED +#define MP_WR_RAW_ALIGNED_MASK 0x00000C00U +#define MP_WR_RAW_ALIGNED_SHIFT 10U +/*! Slice: mp_wr_yuv_aligned:*/ +#define MP_WR_YUV_ALIGNED +#define MP_WR_YUV_ALIGNED_MASK 0x00000200U +#define MP_WR_YUV_ALIGNED_SHIFT 9U +/*! Slice: mp_wr_raw_bit:*/ +#define MP_WR_RAW_BIT +#define MP_WR_RAW_BIT_MASK 0x000001C0U +#define MP_WR_RAW_BIT_SHIFT 6U +/*! Slice: mp_wr_yuv_str:*/ +#define MP_WR_YUV_STR +#define MP_WR_YUV_STR_MASK 0x00000030U +#define MP_WR_YUV_STR_SHIFT 4U +/*! Slice: mp_wr_yuv_fmt:*/ +#define MP_WR_YUV_FMT +#define MP_WR_YUV_FMT_MASK 0x0000000CU +#define MP_WR_YUV_FMT_SHIFT 2U +/*! Slice: mp_wr_yuv_bit:*/ +#define MP_WR_YUV_BIT +#define MP_WR_YUV_BIT_MASK 0x00000002U +#define MP_WR_YUV_BIT_SHIFT 1U +/*! Slice: mp_wr_jdp_fmt:*/ +#define MP_WR_JDP_FMT +#define MP_WR_JDP_FMT_MASK 0x00000001U +#define MP_WR_JDP_FMT_SHIFT 0U +/*! Register: miv2_mp_bus_cfg (0x00001318)*/ +/*! Slice: mp_wr_swap_jdp:*/ +#define MP_WR_SWAP_JDP +#define MP_WR_SWAP_JDP_MASK 0x0F000000U +#define MP_WR_SWAP_JDP_SHIFT 24U +/*! Slice: mp_wr_swap_raw:*/ +#define MP_WR_SWAP_RAW +#define MP_WR_SWAP_RAW_MASK 0x00F00000U +#define MP_WR_SWAP_RAW_SHIFT 20U +/*! Slice: mp_wr_swap_v:*/ +#define MP_WR_SWAP_V +#define MP_WR_SWAP_V_MASK 0x000F0000U +#define MP_WR_SWAP_V_SHIFT 16U +/*! Slice: mp_wr_swap_u:*/ +#define MP_WR_SWAP_U +#define MP_WR_SWAP_U_MASK 0x0000F000U +#define MP_WR_SWAP_U_SHIFT 12U +/*! Slice: mp_wr_swap_y:*/ +#define MP_WR_SWAP_Y +#define MP_WR_SWAP_Y_MASK 0x00000F00U +#define MP_WR_SWAP_Y_SHIFT 8U +/*! Slice: mp_rd_issue_cap:*/ +#define MP_RD_ISSUE_CAP +#define MP_RD_ISSUE_CAP_MASK 0x000000C0U +#define MP_RD_ISSUE_CAP_SHIFT 6U +/*! Slice: mp_wr_issue_cap:*/ +#define MP_WR_ISSUE_CAP +#define MP_WR_ISSUE_CAP_MASK 0x00000030U +#define MP_WR_ISSUE_CAP_SHIFT 4U +/*! Slice: mp_rd_burst_len:*/ +#define MP_RD_BURST_LEN +#define MP_RD_BURST_LEN_MASK 0x0000000CU +#define MP_RD_BURST_LEN_SHIFT 2U +/*! Slice: mp_wr_burst_len:*/ +#define MP_WR_BURST_LEN +#define MP_WR_BURST_LEN_MASK 0x00000003U +#define MP_WR_BURST_LEN_SHIFT 0U +/*! Register: miv2_mp_bus_id (0x0000131c)*/ +/*! Slice: mp_bus_sw_en:*/ +#define MP_BUS_SW_EN +#define MP_BUS_SW_EN_MASK 0x02000000U +#define MP_BUS_SW_EN_SHIFT 25U +/*! Slice: mp_rd_id_en:*/ +#define MP_RD_ID_EN +#define MP_RD_ID_EN_MASK 0x01000000U +#define MP_RD_ID_EN_SHIFT 24U +/*! Slice: mp_rd_id_cfg:*/ +#define MP_RD_ID_CFG +#define MP_RD_ID_CFG_MASK 0x00FF0000U +#define MP_RD_ID_CFG_SHIFT 16U +/*! Slice: mp_wr_id_en:*/ +#define MP_WR_ID_EN +#define MP_WR_ID_EN_MASK 0x00000100U +#define MP_WR_ID_EN_SHIFT 8U +/*! Slice: mp_wr_id_cfg:*/ +#define MP_WR_ID_CFG +#define MP_WR_ID_CFG_MASK 0x000000FFU +#define MP_WR_ID_CFG_SHIFT 0U +/*! Register: miv2_mp_bus_timeo (0x00001320)*/ +/*! Slice: mp_bus_timeo_en:*/ +#define MP_BUS_TIMEO_EN +#define MP_BUS_TIMEO_EN_MASK 0x80000000U +#define MP_BUS_TIMEO_EN_SHIFT 31U +/*! Slice: mp_bus_timeo:*/ +#define MP_BUS_TIMEO +#define MP_BUS_TIMEO_MASK 0x7FFFFFFEU +#define MP_BUS_TIMEO_SHIFT 1U + +/*! Slice: mp_bus_timeo_interrupt_disable:*/ +/*! 0 enable 1 disable*/ +#define MP_BUS_TIMEO_INTERRUPT_DISABLE +#define MP_BUS_TIMEO_INTERRUPT_DISABLE_MASK 1U +#define MP_BUS_TIMEO_INTERRUPT_DISABLE_SHIFT 0U +/*! Register: miv2_mp_y_base_ad_init (0x00001324)*/ +/*! Slice: mp_y_base_ad_init:*/ +#define MP_Y_BASE_AD_INIT +#define MP_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MP_Y_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mp_y_size_init (0x00001328)*/ +/*! Slice: mp_y_size_init:*/ +#define MP_Y_SIZE_INIT +#define MP_Y_SIZE_INIT_MASK 0x1FFFFFF0U +#define MP_Y_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mp_y_offs_cnt_init (0x0000132c)*/ +/*! Slice: mp_y_offs_cnt_init:*/ +#define MP_Y_OFFS_CNT_INIT +#define MP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define MP_Y_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mp_y_llength (0x00001330)*/ +/*! Slice: mp_y_llengh:*/ +#define MP_Y_LLENGH +#define MP_Y_LLENGH_MASK 0x00007FFFU +#define MP_Y_LLENGH_SHIFT 0U +/*! Register: miv2_mp_y_pic_width (0x00001334)*/ +/*! Slice: mp_y_pic_width:*/ +#define MP_Y_PIC_WIDTH +#define MP_Y_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MP_Y_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mp_y_pic_height (0x00001338)*/ +/*! Slice: mp_y_pic_height:*/ +#define MP_Y_PIC_HEIGHT +#define MP_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MP_Y_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_mp_y_pic_size (0x0000133c)*/ +/*! Slice: mp_y_pic_size:*/ +#define MP_Y_PIC_SIZE +#define MP_Y_PIC_SIZE_MASK 0xFFFFFFFFU +#define MP_Y_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mp_cb_base_ad_init (0x00001340)*/ +/*! Slice: mp_cb_base_ad_init:*/ +#define MP_CB_BASE_AD_INIT +#define MP_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MP_CB_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mp_cb_size_init (0x00001344)*/ +/*! Slice: mp_cb_size_init:*/ +#define MP_CB_SIZE_INIT +#define MP_CB_SIZE_INIT_MASK 0x0FFFFFF0U +#define MP_CB_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mp_cb_offs_cnt_init (0x00001348)*/ +/*! Slice: mp_cb_offs_cnt_init:*/ +#define MP_CB_OFFS_CNT_INIT +#define MP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define MP_CB_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mp_cr_base_ad_init (0x0000134c)*/ +/*! Slice: mp_cr_base_ad_init:*/ +#define MP_CR_BASE_AD_INIT +#define MP_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MP_CR_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mp_cr_size_init (0x00001350)*/ +/*! Slice: mp_cr_size_init:*/ +#define MP_CR_SIZE_INIT +#define MP_CR_SIZE_INIT_MASK 0x0FFFFFF0U +#define MP_CR_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mp_cr_offs_cnt_init (0x00001354)*/ +/*! Slice: mp_cr_offs_cnt_init:*/ +#define MP_CR_OFFS_CNT_INIT +#define MP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define MP_CR_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mp_y_base_ad_init2 (0x00001358)*/ +/*! Slice: mp_y_base_ad_init2:*/ +#define MP_Y_BASE_AD_INIT2 +#define MP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define MP_Y_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_mp_cb_base_ad_init2 (0x0000135c)*/ +/*! Slice: mp_cb_base_ad_init2:*/ +#define MP_CB_BASE_AD_INIT2 +#define MP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define MP_CB_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_mp_cr_base_ad_init2 (0x00001360)*/ +/*! Slice: mp_cr_base_ad_init2:*/ +#define MP_CR_BASE_AD_INIT2 +#define MP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define MP_CR_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_mp_y_offs_cnt_start (0x00001364)*/ +/*! Slice: mp_y_offs_cnt_start:*/ +#define MP_Y_OFFS_CNT_START +#define MP_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define MP_Y_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mp_cb_offs_cnt_start (0x00001368)*/ +/*! Slice: mp_cb_offs_cnt_start:*/ +#define MP_CB_OFFS_CNT_START +#define MP_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define MP_CB_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mp_cr_offs_cnt_start (0x0000136c)*/ +/*! Slice: mp_cr_offs_cnt_start:*/ +#define MP_CR_OFFS_CNT_START +#define MP_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define MP_CR_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mp_y_base_ad_shd (0x00001370)*/ +/*! Slice: mp_y_base_ad:*/ +#define MP_Y_BASE_AD +#define MP_Y_BASE_AD_MASK 0xFFFFFFF0U +#define MP_Y_BASE_AD_SHIFT 4U +/*! Register: miv2_mp_y_size_shd (0x00001374)*/ +/*! Slice: mp_y_size:*/ +#define MP_Y_SIZE +#define MP_Y_SIZE_MASK 0x1FFFFFF0U +#define MP_Y_SIZE_SHIFT 4U +/*! Register: miv2_mp_y_offs_cnt_shd (0x00001378)*/ +/*! Slice: mp_y_offs_cnt:*/ +#define MP_Y_OFFS_CNT +#define MP_Y_OFFS_CNT_MASK 0x1FFFFFF0U +#define MP_Y_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mp_cb_base_ad_shd (0x0000137c)*/ +/*! Slice: mp_cb_base_ad:*/ +#define MP_CB_BASE_AD +#define MP_CB_BASE_AD_MASK 0xFFFFFFF0U +#define MP_CB_BASE_AD_SHIFT 4U +/*! Register: miv2_mp_cb_size_shd (0x00001380)*/ +/*! Slice: mp_cb_size:*/ +#define MP_CB_SIZE +#define MP_CB_SIZE_MASK 0x0FFFFFF0U +#define MP_CB_SIZE_SHIFT 4U +/*! Register: miv2_mp_cb_offs_cnt_shd (0x00001384)*/ +/*! Slice: mp_cb_offs_cnt:*/ +#define MP_CB_OFFS_CNT +#define MP_CB_OFFS_CNT_MASK 0x0FFFFFF0U +#define MP_CB_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mp_cr_base_ad_shd (0x00001388)*/ +/*! Slice: mp_cr_base_ad:*/ +#define MP_CR_BASE_AD +#define MP_CR_BASE_AD_MASK 0xFFFFFFF0U +#define MP_CR_BASE_AD_SHIFT 4U +/*! Register: miv2_mp_cr_size_shd (0x0000138c)*/ +/*! Slice: mp_cr_size:*/ +#define MP_CR_SIZE +#define MP_CR_SIZE_MASK 0x0FFFFFF0U +#define MP_CR_SIZE_SHIFT 4U +/*! Register: miv2_mp_cr_offs_cnt_shd (0x00001390)*/ +/*! Slice: mp_cr_offs_cnt:*/ +#define MP_CR_OFFS_CNT +#define MP_CR_OFFS_CNT_MASK 0x0FFFFFF0U +#define MP_CR_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mp_raw_base_ad_init (0x00001394)*/ +/*! Slice: mp_raw_base_ad_init:*/ +#define MP_RAW_BASE_AD_INIT +#define MP_RAW_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MP_RAW_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mp_raw_size_init (0x00001398)*/ +/*! Slice: mp_raw_size_init:*/ +#define MP_RAW_SIZE_INIT +#define MP_RAW_SIZE_INIT_MASK 0x1FFFFFF0U +#define MP_RAW_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mp_raw_offs_cnt_init (0x0000139c)*/ +/*! Slice: mp_raw_offs_cnt_init:*/ +#define MP_RAW_OFFS_CNT_INIT +#define MP_RAW_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define MP_RAW_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mp_raw_llength (0x000013a0)*/ +/*! Slice: mp_raw_llengh:*/ +#define MP_RAW_LLENGH +#define MP_RAW_LLENGH_MASK 0x00007FFFU +#define MP_RAW_LLENGH_SHIFT 0U +/*! Register: miv2_mp_raw_pic_width (0x000013a4)*/ +/*! Slice: mp_raw_pic_width:*/ +#define MP_RAW_PIC_WIDTH +#define MP_RAW_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MP_RAW_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mp_raw_pic_height (0x000013a8)*/ +/*! Slice: mp_raw_pic_height:*/ +#define MP_RAW_PIC_HEIGHT +#define MP_RAW_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MP_RAW_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_mp_raw_pic_size (0x000013ac)*/ +/*! Slice: mp_raw_pic_size:*/ +#define MP_RAW_PIC_SIZE +#define MP_RAW_PIC_SIZE_MASK 0xFFFFFFFFU +#define MP_RAW_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mp_raw_offs_cnt_start (0x000013b0)*/ +/*! Slice: mp_raw_offs_cnt_start:*/ +#define MP_RAW_OFFS_CNT_START +#define MP_RAW_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define MP_RAW_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mp_raw_base_ad_shd (0x000013b4)*/ +/*! Slice: mp_raw_base_ad:*/ +#define MP_RAW_BASE_AD +#define MP_RAW_BASE_AD_MASK 0xFFFFFFF0U +#define MP_RAW_BASE_AD_SHIFT 4U +/*! Register: miv2_mp_raw_size_shd (0x000013b8)*/ +/*! Slice: mp_raw_size:*/ +#define MP_RAW_SIZE +#define MP_RAW_SIZE_MASK 0x1FFFFFF0U +#define MP_RAW_SIZE_SHIFT 4U +/*! Register: miv2_mp_raw_offs_cnt_shd (0x000013bc)*/ +/*! Slice: mp_raw_offs_cnt:*/ +#define MP_RAW_OFFS_CNT +#define MP_RAW_OFFS_CNT_MASK 0x1FFFFFF0U +#define MP_RAW_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mp_jdp_base_ad_init (0x000013c0)*/ +/*! Slice: mp_jdp_base_ad_init:*/ +#define MP_JDP_BASE_AD_INIT +#define MP_JDP_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MP_JDP_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mp_jdp_size_init (0x000013c4)*/ +/*! Slice: mp_jdp_size_init:*/ +#define MP_JDP_SIZE_INIT +#define MP_JDP_SIZE_INIT_MASK 0x1FFFFFF0U +#define MP_JDP_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mp_jdp_offs_cnt_init (0x000013c8)*/ +/*! Slice: mp_jdp_offs_cnt_init:*/ +#define MP_JDP_OFFS_CNT_INIT +#define MP_JDP_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define MP_JDP_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mp_jdp_llength (0x000013cc)*/ +/*! Slice: mp_jdp_llengh:*/ +#define MP_JDP_LLENGH +#define MP_JDP_LLENGH_MASK 0x00007FFFU +#define MP_JDP_LLENGH_SHIFT 0U +/*! Register: miv2_mp_jdp_pic_width (0x000013d0)*/ +/*! Slice: mp_jdp_pic_width:*/ +#define MP_JDP_PIC_WIDTH +#define MP_JDP_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MP_JDP_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mp_jdp_pic_height (0x000013d4)*/ +/*! Slice: mp_jdp_pic_height:*/ +#define MP_JDP_PIC_HEIGHT +#define MP_JDP_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MP_JDP_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_mp_jdp_pic_size (0x000013d8)*/ +/*! Slice: mp_jdp_pic_size:*/ +#define MP_JDP_PIC_SIZE +#define MP_JDP_PIC_SIZE_MASK 0xFFFFFFFFU +#define MP_JDP_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mp_jdp_offs_cnt_start (0x000013dc)*/ +/*! Slice: mp_jdp_offs_cnt_start:*/ +#define MP_JDP_OFFS_CNT_START +#define MP_JDP_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define MP_JDP_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mp_jdp_base_ad_shd (0x000013e0)*/ +/*! Slice: mp_jdp_base_ad:*/ +#define MP_JDP_BASE_AD +#define MP_JDP_BASE_AD_MASK 0xFFFFFFF0U +#define MP_JDP_BASE_AD_SHIFT 4U +/*! Register: miv2_mp_jdp_size_shd (0x000013e4)*/ +/*! Slice: mp_jdp_size:*/ +#define MP_JDP_SIZE +#define MP_JDP_SIZE_MASK 0x1FFFFFF0U +#define MP_JDP_SIZE_SHIFT 4U +/*! Register: miv2_mp_jdp_offs_cnt_shd (0x000013e8)*/ +/*! Slice: mp_jdp_offs_cnt:*/ +#define MP_JDP_OFFS_CNT +#define MP_JDP_OFFS_CNT_MASK 0x1FFFFFF0U +#define MP_JDP_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mp_status_clr (0x000013ec) */ +/*! Slice: mp_jdp_fifo_full: */ +#define MP_JDP_FIFO_FULL +#define MP_JDP_FIFO_FULL_MASK 0x00000010U +#define MP_JDP_FIFO_FULL_SHIFT 4U +/*! Slice: mp_raw_fifo_full:*/ +#define MP_RAW_FIFO_FULL +#define MP_RAW_FIFO_FULL_MASK 0x00000008U +#define MP_RAW_FIFO_FULL_SHIFT 3U +/*! Slice: mp_cr_fifo_full:*/ +#define MP_CR_FIFO_FULL +#define MP_CR_FIFO_FULL_MASK 0x00000004U +#define MP_CR_FIFO_FULL_SHIFT 2U +/*! Slice: mp_cb_fifo_full:*/ +#define MP_CB_FIFO_FULL +#define MP_CB_FIFO_FULL_MASK 0x00000002U +#define MP_CB_FIFO_FULL_SHIFT 1U +/*! Slice: mp_y_fifo_full:*/ +#define MP_Y_FIFO_FULL +#define MP_Y_FIFO_FULL_MASK 0x00000001U +#define MP_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_mp_ctrl_status (0x000013f0) */ +/*! Slice: mp_jdp_fifo_full: */ +#define MP_JDP_FIFO_FULL +#define MP_JDP_FIFO_FULL_MASK 0x00000010U +#define MP_JDP_FIFO_FULL_SHIFT 4U +/*! Slice: mp_raw_fifo_full: */ +#define MP_RAW_FIFO_FULL +#define MP_RAW_FIFO_FULL_MASK 0x00000008U +#define MP_RAW_FIFO_FULL_SHIFT 3U +/*! Slice: mp_cr_fifo_full: */ +#define MP_CR_FIFO_FULL +#define MP_CR_FIFO_FULL_MASK 0x00000004U +#define MP_CR_FIFO_FULL_SHIFT 2U +/*! Slice: mp_cb_fifo_full: */ +#define MP_CB_FIFO_FULL +#define MP_CB_FIFO_FULL_MASK 0x00000002U +#define MP_CB_FIFO_FULL_SHIFT 1U +/*! Slice: mp_y_fifo_full: */ +#define MP_Y_FIFO_FULL +#define MP_Y_FIFO_FULL_MASK 0x00000001U +#define MP_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_mp_axi_status (0x000013f4) */ +/*! Slice: agsw_enc_pic_rdy: */ +#define AGSW_ENC_PIC_RDY +#define AGSW_ENC_PIC_RDY_MASK 0x00000002U +#define AGSW_ENC_PIC_RDY_SHIFT 1U +/*! Slice: agsw_enc_buf_full:*/ +#define AGSW_ENC_BUF_FULL +#define AGSW_ENC_BUF_FULL_MASK 0x00000001U +#define AGSW_ENC_BUF_FULL_SHIFT 0U +/*! Register: miv2_mp_raw_byte_cnt_status (0x000013f8)*/ +/*! Slice: mp_raw_byte_cnt_status:*/ +#define MP_RAW_BYTE_CNT_STATUS +#define MP_RAW_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU +#define MP_RAW_BYTE_CNT_STATUS_SHIFT 0U +/*! Register: miv2_mp_jdp_byte_cnt_status (0x000013fc)*/ +/*! Slice: mp_jdp_byte_cnt_status:*/ +#define MP_JDP_BYTE_CNT_STATUS +#define MP_JDP_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU +#define MP_JDP_BYTE_CNT_STATUS_SHIFT 0U +/*! Register: miv2_mp_dp_byte_cnt_status (0x00001400)*/ +/*! Slice: mp_dp_byte_cnt_status:*/ +#define MP_DP_BYTE_CNT_STATUS +#define MP_DP_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU +#define MP_DP_BYTE_CNT_STATUS_SHIFT 0U +/*! Register: miv2_sp1_ctrl (0x0000142c)*/ +/*! Slice: sp1_init_offset_en:*/ +#define SP1_INIT_OFFSET_EN +#define SP1_INIT_OFFSET_EN_MASK 0x00000020U +#define SP1_INIT_OFFSET_EN_SHIFT 5U +/*! Slice: sp1_init_base_en:*/ +#define SP1_INIT_BASE_EN +#define SP1_INIT_BASE_EN_MASK 0x00000010U +#define SP1_INIT_BASE_EN_SHIFT 4U +/*! Slice: sp1_miv2_cfg_upd:*/ +#define SP1_MI_CFG_UPD +#define SP1_MI_CFG_UPD_MASK 0x00000008U +#define SP1_MI_CFG_UPD_SHIFT 3U +/*! Slice: sp1_miv2_skip:*/ +#define SP1_MI_SKIP +#define SP1_MI_SKIP_MASK 0x00000004U +#define SP1_MI_SKIP_SHIFT 2U +/*! Slice: sp1_auto_update:*/ +#define SP1_AUTO_UPDATE +#define SP1_AUTO_UPDATE_MASK 0x00000002U +#define SP1_AUTO_UPDATE_SHIFT 1U +/*! Slice: sp1_pingpong_enable:*/ +#define SP1_PINGPONG_ENABLE +#define SP1_PINGPONG_ENABLE_MASK 0x00000001U +#define SP1_PINGPONG_ENABLE_SHIFT 0U +/*! Register: miv2_sp1_fmt (0x00001430)*/ +/*! Slice: sp1_wr_yuv_nvy:*/ +#define SP1_WR_YUV_NVY +#define SP1_WR_YUV_NVY_MASK 0x00000180U +#define SP1_WR_YUV_NVY_SHIFT 7U +/*! Slice: sp1_wr_yuv_nv21:*/ +#define SP1_WR_YUV_NV21 +#define SP1_WR_YUV_NV21_MASK 0x00000040U +#define SP1_WR_YUV_NV21_SHIFT 6U +/*! Slice: sp1_wr_yuv_aligned:*/ +#define SP1_WR_YUV_ALIGNED +#define SP1_WR_YUV_ALIGNED_MASK 0x00000020U +#define SP1_WR_YUV_ALIGNED_SHIFT 5U +/*! Slice: sp1_wr_yuv_str:*/ +#define SP1_WR_YUV_STR +#define SP1_WR_YUV_STR_MASK 0x00000018U +#define SP1_WR_YUV_STR_SHIFT 3U +/*! Slice: sp1_wr_yuv_fmt:*/ +#define SP1_WR_YUV_FMT +#define SP1_WR_YUV_FMT_MASK 0x00000006U +#define SP1_WR_YUV_FMT_SHIFT 1U +/*! Slice: sp1_wr_yuv_bit:*/ +#define SP1_WR_YUV_BIT +#define SP1_WR_YUV_BIT_MASK 0x00000001U +#define SP1_WR_YUV_BIT_SHIFT 0U +/*! Register: miv2_sp1_bus_cfg (0x00001434)*/ +/*! Slice: sp1_wr_swap_v:*/ +#define SP1_WR_SWAP_V +#define SP1_WR_SWAP_V_MASK 0x000F0000U +#define SP1_WR_SWAP_V_SHIFT 16U +/*! Slice: sp1_wr_swap_u:*/ +#define SP1_WR_SWAP_U +#define SP1_WR_SWAP_U_MASK 0x0000F000U +#define SP1_WR_SWAP_U_SHIFT 12U +/*! Slice: sp1_wr_swap_y:*/ +#define SP1_WR_SWAP_Y +#define SP1_WR_SWAP_Y_MASK 0x00000F00U +#define SP1_WR_SWAP_Y_SHIFT 8U +/*! Slice: sp1_rd_issue_cap:*/ +#define SP1_RD_ISSUE_CAP +#define SP1_RD_ISSUE_CAP_MASK 0x000000C0U +#define SP1_RD_ISSUE_CAP_SHIFT 6U +/*! Slice: sp1_wr_issue_cap:*/ +#define SP1_WR_ISSUE_CAP +#define SP1_WR_ISSUE_CAP_MASK 0x00000030U +#define SP1_WR_ISSUE_CAP_SHIFT 4U +/*! Slice: sp1_rd_burst_len:*/ +#define SP1_RD_BURST_LEN +#define SP1_RD_BURST_LEN_MASK 0x0000000CU +#define SP1_RD_BURST_LEN_SHIFT 2U +/*! Slice: sp1_wr_burst_len:*/ +#define SP1_WR_BURST_LEN +#define SP1_WR_BURST_LEN_MASK 0x00000003U +#define SP1_WR_BURST_LEN_SHIFT 0U +/*! Register: miv2_sp1_bus_id (0x00001438)*/ +/*! Slice: sp1_bus_sw_en:*/ +#define SP1_BUS_SW_EN +#define SP1_BUS_SW_EN_MASK 0x02000000U +#define SP1_BUS_SW_EN_SHIFT 25U + +/*! Slice: sp1_rd_id_en:*/ +#define SP1_RD_ID_EN +#define SP1_RD_ID_EN_MASK 0x01000000U +#define SP1_RD_ID_EN_SHIFT 24U +/*! Slice: sp1_rd_id_cfg:*/ +#define SP1_RD_ID_CFG +#define SP1_RD_ID_CFG_MASK 0x00FF0000U +#define SP1_RD_ID_CFG_SHIFT 16U +/*! Slice: sp1_wr_id_en:*/ +#define SP1_WR_ID_EN +#define SP1_WR_ID_EN_MASK 0x00000100U +#define SP1_WR_ID_EN_SHIFT 8U +/*! Slice: sp1_wr_id_cfg:*/ +#define SP1_WR_ID_CFG +#define SP1_WR_ID_CFG_MASK 0x000000FFU +#define SP1_WR_ID_CFG_SHIFT 0U +/*! Register: miv2_sp1_bus_timeo (0x0000143c)*/ +/*! Slice: sp1_bus_timeo_en:*/ +#define SP1_BUS_TIMEO_EN +#define SP1_BUS_TIMEO_EN_MASK 0x80000000U +#define SP1_BUS_TIMEO_EN_SHIFT 31U +/*! Slice: sp1_bus_timeo:*/ +#define SP1_BUS_TIMEO +#define SP1_BUS_TIMEO_MASK 0x7FFFFFFFU +#define SP1_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_sp1_y_base_ad_init (0x00001440)*/ +/*! Slice: sp1_y_base_ad_init:*/ +#define SP1_Y_BASE_AD_INIT +#define SP1_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP1_Y_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp1_y_size_init (0x00001444)*/ +/*! Slice: sp1_y_size_init:*/ +#define SP1_Y_SIZE_INIT +#define SP1_Y_SIZE_INIT_MASK 0x1FFFFFF0U +#define SP1_Y_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp1_y_offs_cnt_init (0x00001448)*/ +/*! Slice: sp1_y_offs_cnt_init:*/ +#define SP1_Y_OFFS_CNT_INIT +#define SP1_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define SP1_Y_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp1_y_llength (0x0000144c)*/ +/*! Slice: sp1_y_llengh:*/ +#define SP1_Y_LLENGH +#define SP1_Y_LLENGH_MASK 0x00007FFFU +#define SP1_Y_LLENGH_SHIFT 0U +/*! Register: miv2_sp1_y_pic_width (0x00001450)*/ +/*! Slice: sp1_y_pic_width:*/ +#define SP1_Y_PIC_WIDTH +#define SP1_Y_PIC_WIDTH_MASK 0xFFFFFFFFU +#define SP1_Y_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_sp1_y_pic_height (0x00001454)*/ +/*! Slice: sp1_y_pic_height:*/ +#define SP1_Y_PIC_HEIGHT +#define SP1_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define SP1_Y_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_sp1_y_pic_size (0x00001458)*/ +/*! Slice: sp1_y_pic_size:*/ +#define SP1_Y_PIC_SIZE +#define SP1_Y_PIC_SIZE_MASK 0xFFFFFFFFU +#define SP1_Y_PIC_SIZE_SHIFT 0U +/*! Register: miv2_sp1_cb_base_ad_init (0x0000145c)*/ +/*! Slice: sp1_cb_base_ad_init:*/ +#define SP1_CB_BASE_AD_INIT +#define SP1_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP1_CB_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp1_cb_size_init (0x00001460)*/ +/*! Slice: sp1_cb_size_init:*/ +#define SP1_CB_SIZE_INIT +#define SP1_CB_SIZE_INIT_MASK 0x0FFFFFF0U +#define SP1_CB_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp1_cb_offs_cnt_init (0x00001464)*/ +/*! Slice: sp1_cb_offs_cnt_init:*/ +#define SP1_CB_OFFS_CNT_INIT +#define SP1_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define SP1_CB_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp1_cr_base_ad_init (0x00001468)*/ +/*! Slice: sp1_cr_base_ad_init:*/ +#define SP1_CR_BASE_AD_INIT +#define SP1_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP1_CR_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp1_cr_size_init (0x0000146c)*/ +/*! Slice: sp1_cr_size_init:*/ +#define SP1_CR_SIZE_INIT +#define SP1_CR_SIZE_INIT_MASK 0x0FFFFFF0U +#define SP1_CR_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp1_cr_offs_cnt_init (0x00001470)*/ +/*! Slice: sp1_cr_offs_cnt_init:*/ +#define SP1_CR_OFFS_CNT_INIT +#define SP1_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define SP1_CR_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp1_y_base_ad_init2 (0x00001474)*/ +/*! Slice: sp1_y_base_ad_init2:*/ +#define SP1_Y_BASE_AD_INIT2 +#define SP1_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP1_Y_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp1_cb_base_ad_init2 (0x00001478)*/ +/*! Slice: sp1_cb_base_ad_init2:*/ +#define SP1_CB_BASE_AD_INIT2 +#define SP1_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP1_CB_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp1_cr_base_ad_init2 (0x0000147c)*/ +/*! Slice: sp1_cr_base_ad_init2:*/ +#define SP1_CR_BASE_AD_INIT2 +#define SP1_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP1_CR_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp1_y_offs_cnt_start (0x00001480)*/ +/*! Slice: sp1_y_offs_cnt_start:*/ +#define SP1_Y_OFFS_CNT_START +#define SP1_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define SP1_Y_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp1_cb_offs_cnt_start (0x00001484)*/ +/*! Slice: sp1_cb_offs_cnt_start:*/ +#define SP1_CB_OFFS_CNT_START +#define SP1_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define SP1_CB_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp1_cr_offs_cnt_start (0x00001488)*/ +/*! Slice: sp1_cr_offs_cnt_start:*/ +#define SP1_CR_OFFS_CNT_START +#define SP1_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define SP1_CR_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp1_y_base_ad_shd (0x0000148c)*/ +/*! Slice: sp1_y_base_ad:*/ +#define SP1_Y_BASE_AD +#define SP1_Y_BASE_AD_MASK 0xFFFFFFF0U +#define SP1_Y_BASE_AD_SHIFT 4U +/*! Register: miv2_sp1_y_size_shd (0x00001490)*/ +/*! Slice: sp1_y_size:*/ +#define SP1_Y_SIZE +#define SP1_Y_SIZE_MASK 0x1FFFFFF0U +#define SP1_Y_SIZE_SHIFT 4U +/*! Register: miv2_sp1_y_offs_cnt_shd (0x00001494)*/ +/*! Slice: sp1_y_offs_cnt:*/ +#define SP1_Y_OFFS_CNT +#define SP1_Y_OFFS_CNT_MASK 0x1FFFFFF0U +#define SP1_Y_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp1_cb_base_ad_shd (0x00001498)*/ +/*! Slice: sp1_cb_base_ad:*/ +#define SP1_CB_BASE_AD +#define SP1_CB_BASE_AD_MASK 0xFFFFFFF0U +#define SP1_CB_BASE_AD_SHIFT 4U +/*! Register: miv2_sp1_cb_size_shd (0x0000149c)*/ +/*! Slice: sp1_cb_size:*/ +#define SP1_CB_SIZE +#define SP1_CB_SIZE_MASK 0x0FFFFFF0U +#define SP1_CB_SIZE_SHIFT 4U +/*! Register: miv2_sp1_cb_offs_cnt_shd (0x000014a0)*/ +/*! Slice: sp1_cb_offs_cnt:*/ +#define SP1_CB_OFFS_CNT +#define SP1_CB_OFFS_CNT_MASK 0x0FFFFFF0U +#define SP1_CB_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp1_cr_base_ad_shd (0x000014a4)*/ +/*! Slice: sp1_cr_base_ad:*/ +#define SP1_CR_BASE_AD +#define SP1_CR_BASE_AD_MASK 0xFFFFFFF0U +#define SP1_CR_BASE_AD_SHIFT 4U +/*! Register: miv2_sp1_cr_size_shd (0x000014a8)*/ +/*! Slice: sp1_cr_size:*/ +#define SP1_CR_SIZE +#define SP1_CR_SIZE_MASK 0x0FFFFFF0U +#define SP1_CR_SIZE_SHIFT 4U +/*! Register: miv2_sp1_cr_offs_cnt_shd (0x000014ac)*/ +/*! Slice: sp1_cr_offs_cnt:*/ +#define SP1_CR_OFFS_CNT +#define SP1_CR_OFFS_CNT_MASK 0x0FFFFFF0U +#define SP1_CR_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp1_status_clr (0x000014b0)*/ +/*! Slice: sp1_cr_fifo_full:*/ +#define SP1_CR_FIFO_FULL +#define SP1_CR_FIFO_FULL_MASK 0x00000004U +#define SP1_CR_FIFO_FULL_SHIFT 2U +/*! Slice: sp1_cb_fifo_full:*/ +#define SP1_CB_FIFO_FULL +#define SP1_CB_FIFO_FULL_MASK 0x00000002U +#define SP1_CB_FIFO_FULL_SHIFT 1U +/*! Slice: sp1_y_fifo_full:*/ +#define SP1_Y_FIFO_FULL +#define SP1_Y_FIFO_FULL_MASK 0x00000001U +#define SP1_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_sp1_ctrl_status (0x000014b4)*/ +/*! Slice: sp1_cr_fifo_full:*/ +#define SP1_CR_FIFO_FULL +#define SP1_CR_FIFO_FULL_MASK 0x00000004U +#define SP1_CR_FIFO_FULL_SHIFT 2U +/*! Slice: sp1_cb_fifo_full:*/ +#define SP1_CB_FIFO_FULL +#define SP1_CB_FIFO_FULL_MASK 0x00000002U +#define SP1_CB_FIFO_FULL_SHIFT 1U +/*! Slice: sp1_y_fifo_full:*/ +#define SP1_Y_FIFO_FULL +#define SP1_Y_FIFO_FULL_MASK 0x00000001U +#define SP1_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_sp1_axi_status (0x000014b8)*/ +/*! Slice: agsw_enc_pic_rdy:*/ +#define AGSW_ENC_PIC_RDY +#define AGSW_ENC_PIC_RDY_MASK 0x00000002U +#define AGSW_ENC_PIC_RDY_SHIFT 1U +/*! Slice: agsw_enc_buf_full:*/ +#define AGSW_ENC_BUF_FULL +#define AGSW_ENC_BUF_FULL_MASK 0x00000001U +#define AGSW_ENC_BUF_FULL_SHIFT 0U +/*! Register: miv2_sp2_ctrl (0x000014e4)*/ +/*! Slice: sp2_rd_raw_cfg_update */ +#define SP2_RD_RAW_CFG_UPDATE +#define SP2_RD_RAW_CFG_UPDATE_MASK 0x00000200U +#define SP2_RD_RAW_CFG_UPDATE_SHIFT 9U +/*! Slice: sp2_rd_raw_auto_update */ +#define SP2_RD_RAW_AUTO_UPDATE +#define SP2_RD_RAW_AUTO_UPDATE_MASK 0x00000100U +#define SP2_RD_RAW_AUTO_UPDATE_SHIFT 8U +/*! Slice: sp2_rd_yuv_cfg_update */ +#define SP2_RD_YUV_CFG_UPDATE +#define SP2_RD_YUV_CFG_UPDATE_MASK 0x00000080U +#define SP2_RD_YUV_CFG_UPDATE_SHIFT 7U +/*! Slice: sp2_rd_yuv_auto_update */ +#define SP2_RD_YUV_AUTO_UPDATE +#define SP2_RD_YUV_AUTO_UPDATE_MASK 0x00000040U +#define SP2_RD_YUV_AUTO_UPDATE_SHIFT 6U +/*! Slice: sp2_init_offset_en:*/ +#define SP2_INIT_OFFSET_EN +#define SP2_INIT_OFFSET_EN_MASK 0x00000020U +#define SP2_INIT_OFFSET_EN_SHIFT 5U +/*! Slice: sp2_init_base_en:*/ +#define SP2_INIT_BASE_EN +#define SP2_INIT_BASE_EN_MASK 0x00000010U +#define SP2_INIT_BASE_EN_SHIFT 4U +/*! Slice: sp2_miv2_cfg_upd:*/ +#define SP2_MI_CFG_UPD +#define SP2_MI_CFG_UPD_MASK 0x00000008U +#define SP2_MI_CFG_UPD_SHIFT 3U +/*! Slice: sp2_miv2_skip:*/ +#define SP2_MI_SKIP +#define SP2_MI_SKIP_MASK 0x00000004U +#define SP2_MI_SKIP_SHIFT 2U +/*! Slice: sp2_auto_update:*/ +#define SP2_AUTO_UPDATE +#define SP2_AUTO_UPDATE_MASK 0x00000002U +#define SP2_AUTO_UPDATE_SHIFT 1U +/*! Slice: sp2_pingpong_enable:*/ +#define SP2_PINGPONG_ENABLE +#define SP2_PINGPONG_ENABLE_MASK 0x00000001U +#define SP2_PINGPONG_ENABLE_SHIFT 0U +/*! Register: miv2_sp2_fmt (0x000014e8)*/ +/*! Slice: sp2_rd_yuv_nvy:*/ +#define SP2_RD_YUV_NVY +#define SP2_RD_YUV_NVY_MASK 0x0C000000U +#define SP2_RD_YUV_NVY_SHIFT 26U +/*! Slice: sp2_rd_yuv_nv21:*/ +#define SP2_RD_YUV_NV21 +#define SP2_RD_YUV_NV21_MASK 0x02000000U +#define SP2_RD_YUV_NV21_SHIFT 25U +/*! Slice: sp2_rd_raw_aligned:*/ +#define SP2_RD_RAW_ALIGNED +#define SP2_RD_RAW_ALIGNED_MASK 0x01800000U +#define SP2_RD_RAW_ALIGNED_SHIFT 23U +/*! Slice: sp2_rd_yuv_aligned:*/ +#define SP2_RD_YUV_ALIGNED +#define SP2_RD_YUV_ALIGNED_MASK 0x00400000U +#define SP2_RD_YUV_ALIGNED_SHIFT 22U +/*! Slice: sp2_rd_raw_bit:*/ +#define SP2_RD_RAW_BIT +#define SP2_RD_RAW_BIT_MASK 0x00380000U +#define SP2_RD_RAW_BIT_SHIFT 19U +/*! Slice: sp2_rd_yuv_str:*/ +#define SP2_RD_YUV_STR +#define SP2_RD_YUV_STR_MASK 0x00060000U +#define SP2_RD_YUV_STR_SHIFT 17U +/*! Slice: sp2_rd_yuv_fmt:*/ +#define SP2_RD_YUV_FMT +#define SP2_RD_YUV_FMT_MASK 0x00018000U +#define SP2_RD_YUV_FMT_SHIFT 15U +/*! Slice: sp2_rd_yuv_bit:*/ +#define SP2_RD_YUV_BIT +#define SP2_RD_YUV_BIT_MASK 0x00004000U +#define SP2_RD_YUV_BIT_SHIFT 14U +/*! Slice: sp2_wr_yuv_nvy:*/ +#define SP2_WR_YUV_NVY +#define SP2_WR_YUV_NVY_MASK 0x00003000U +#define SP2_WR_YUV_NVY_SHIFT 12U +/*! Slice: sp2_wr_yuv_nv21:*/ +#define SP2_WR_YUV_NV21 +#define SP2_WR_YUV_NV21_MASK 0x00000800U +#define SP2_WR_YUV_NV21_SHIFT 11U +/*! Slice: sp2_wr_raw_aligned:*/ +#define SP2_WR_RAW_ALIGNED +#define SP2_WR_RAW_ALIGNED_MASK 0x00000600U +#define SP2_WR_RAW_ALIGNED_SHIFT 9U +/*! Slice: sp2_wr_yuv_aligned:*/ +#define SP2_WR_YUV_ALIGNED +#define SP2_WR_YUV_ALIGNED_MASK 0x00000100U +#define SP2_WR_YUV_ALIGNED_SHIFT 8U +/*! Slice: sp2_wr_raw_bit:*/ +#define SP2_WR_RAW_BIT +#define SP2_WR_RAW_BIT_MASK 0x000000E0U +#define SP2_WR_RAW_BIT_SHIFT 5U +/*! Slice: sp2_wr_yuv_str:*/ +#define SP2_WR_YUV_STR +#define SP2_WR_YUV_STR_MASK 0x00000018U +#define SP2_WR_YUV_STR_SHIFT 3U +/*! Slice: sp2_wr_yuv_fmt:*/ +#define SP2_WR_YUV_FMT +#define SP2_WR_YUV_FMT_MASK 0x00000006U +#define SP2_WR_YUV_FMT_SHIFT 1U +/*! Slice: sp2_wr_yuv_bit:*/ +#define SP2_WR_YUV_BIT +#define SP2_WR_YUV_BIT_MASK 0x00000001U +#define SP2_WR_YUV_BIT_SHIFT 0U +/*! Register: miv2_sp2_bus_cfg (0x000014ec)*/ +/*! Slice: sp2_rd_swap_raw:*/ +#define SP2_RD_SWAP_RAW +#define SP2_RD_SWAP_RAW_MASK 0xF0000000U +#define SP2_RD_SWAP_RAW_SHIFT 28U +/*! Slice: sp2_rd_swap_v:*/ +#define SP2_RD_SWAP_V +#define SP2_RD_SWAP_V_MASK 0x0F000000U +#define SP2_RD_SWAP_V_SHIFT 24U +/*! Slice: sp2_rd_swap_u:*/ +#define SP2_RD_SWAP_U +#define SP2_RD_SWAP_U_MASK 0x00F00000U +#define SP2_RD_SWAP_U_SHIFT 20U +/*! Slice: sp2_rd_swap_y:*/ +#define SP2_RD_SWAP_Y +#define SP2_RD_SWAP_Y_MASK 0x000F0000U +#define SP2_RD_SWAP_Y_SHIFT 16U +/*! Slice: sp2_wr_swap_raw:*/ +#define SP2_WR_SWAP_RAW +#define SP2_WR_SWAP_RAW_MASK 0x0000F000U +#define SP2_WR_SWAP_RAW_SHIFT 12U +/*! Slice: sp2_wr_swap_v:*/ +#define SP2_WR_SWAP_V +#define SP2_WR_SWAP_V_MASK 0x00000F00U +#define SP2_WR_SWAP_V_SHIFT 8U +/*! Slice: sp2_wr_swap_u:*/ +#define SP2_WR_SWAP_U +#define SP2_WR_SWAP_U_MASK 0x000000F0U +#define SP2_WR_SWAP_U_SHIFT 4U +/*! Slice: sp2_wr_swap_y:*/ +#define SP2_WR_SWAP_Y +#define SP2_WR_SWAP_Y_MASK 0x0000000FU +#define SP2_WR_SWAP_Y_SHIFT 0U +/*! Register: miv2_sp2_bus_id (0x000014f0)*/ +/*! Slice: sp2_bus_sw_en:*/ +#define SP2_BUS_SW_EN +#define SP2_BUS_SW_EN_MASK 0x08000000U +#define SP2_BUS_SW_EN_SHIFT 27U +/*! Slice: sp2_rd_issue_cap:*/ +#define SP2_RD_ISSUE_CAP +#define SP2_RD_ISSUE_CAP_MASK 0x06000000U +#define SP2_RD_ISSUE_CAP_SHIFT 25U +/*! Slice: sp2_wr_issue_cap:*/ +#define SP2_WR_ISSUE_CAP +#define SP2_WR_ISSUE_CAP_MASK 0x01800000U +#define SP2_WR_ISSUE_CAP_SHIFT 23U +/*! Slice: sp2_rd_burst_len:*/ +#define SP2_RD_BURST_LEN +#define SP2_RD_BURST_LEN_MASK 0x00600000U +#define SP2_RD_BURST_LEN_SHIFT 21U +/*! Slice: sp2_wr_burst_len:*/ +#define SP2_WR_BURST_LEN +#define SP2_WR_BURST_LEN_MASK 0x00180000U +#define SP2_WR_BURST_LEN_SHIFT 19U +/*! Slice: sp2_rd_id_en:*/ +#define SP2_RD_ID_EN +#define SP2_RD_ID_EN_MASK 0x00040000U +#define SP2_RD_ID_EN_SHIFT 18U +/*! Slice: sp2_rd_id_cfg:*/ +#define SP2_RD_ID_CFG +#define SP2_RD_ID_CFG_MASK 0x0003FC00U +#define SP2_RD_ID_CFG_SHIFT 10U +/*! Slice: sp2_wr_id_en:*/ +#define SP2_WR_ID_EN +#define SP2_WR_ID_EN_MASK 0x00000100U +#define SP2_WR_ID_EN_SHIFT 8U +/*! Slice: sp2_wr_id_cfg:*/ +#define SP2_WR_ID_CFG +#define SP2_WR_ID_CFG_MASK 0x000000FFU +#define SP2_WR_ID_CFG_SHIFT 0U +/*! Register: miv2_sp2_bus_timeo (0x000014f4)*/ +/*! Slice: sp2_bus_timeo_en:*/ +#define SP2_BUS_TIMEO_EN +#define SP2_BUS_TIMEO_EN_MASK 0x80000000U +#define SP2_BUS_TIMEO_EN_SHIFT 31U +/*! Slice: sp2_bus_timeo:*/ +#define SP2_BUS_TIMEO +#define SP2_BUS_TIMEO_MASK 0x7FFFFFFFU +#define SP2_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_sp2_y_base_ad_init (0x000014f8)*/ +/*! Slice: sp2_y_base_ad_init:*/ +#define SP2_Y_BASE_AD_INIT +#define SP2_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP2_Y_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp2_y_size_init (0x000014fc)*/ +/*! Slice: sp2_y_size_init:*/ +#define SP2_Y_SIZE_INIT +#define SP2_Y_SIZE_INIT_MASK 0x1FFFFFF0U +#define SP2_Y_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp2_y_offs_cnt_init (0x00001500)*/ +/*! Slice: sp2_y_offs_cnt_init:*/ +#define SP2_Y_OFFS_CNT_INIT +#define SP2_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define SP2_Y_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp2_y_llength (0x00001504)*/ +/*! Slice: sp2_y_llengh:*/ +#define SP2_Y_LLENGH +#define SP2_Y_LLENGH_MASK 0x00007FFFU +#define SP2_Y_LLENGH_SHIFT 0U +/*! Register: miv2_sp2_y_pic_width (0x00001508)*/ +/*! Slice: sp2_y_pic_width:*/ +#define SP2_Y_PIC_WIDTH +#define SP2_Y_PIC_WIDTH_MASK 0xFFFFFFFFU +#define SP2_Y_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_sp2_y_pic_height (0x0000150c)*/ +/*! Slice: sp2_y_pic_height:*/ +#define SP2_Y_PIC_HEIGHT +#define SP2_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define SP2_Y_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_sp2_y_pic_size (0x00001510)*/ +/*! Slice: sp2_y_pic_size:*/ +#define SP2_Y_PIC_SIZE +#define SP2_Y_PIC_SIZE_MASK 0xFFFFFFFFU +#define SP2_Y_PIC_SIZE_SHIFT 0U +/*! Register: miv2_sp2_cb_base_ad_init (0x00001514)*/ +/*! Slice: sp2_cb_base_ad_init:*/ +#define SP2_CB_BASE_AD_INIT +#define SP2_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP2_CB_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp2_cb_size_init (0x00001518)*/ +/*! Slice: sp2_cb_size_init:*/ +#define SP2_CB_SIZE_INIT +#define SP2_CB_SIZE_INIT_MASK 0x0FFFFFF0U +#define SP2_CB_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp2_cb_offs_cnt_init (0x0000151c)*/ +/*! Slice: sp2_cb_offs_cnt_init:*/ +#define SP2_CB_OFFS_CNT_INIT +#define SP2_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define SP2_CB_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp2_cr_base_ad_init (0x00001520)*/ +/*! Slice: sp2_cr_base_ad_init:*/ +#define SP2_CR_BASE_AD_INIT +#define SP2_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP2_CR_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp2_cr_size_init (0x00001524)*/ +/*! Slice: sp2_cr_size_init:*/ +#define SP2_CR_SIZE_INIT +#define SP2_CR_SIZE_INIT_MASK 0x0FFFFFF0U +#define SP2_CR_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp2_cr_offs_cnt_init (0x00001528)*/ +/*! Slice: sp2_cr_offs_cnt_init:*/ +#define SP2_CR_OFFS_CNT_INIT +#define SP2_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define SP2_CR_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp2_y_base_ad_init2 (0x0000152c)*/ +/*! Slice: sp2_y_base_ad_init2:*/ +#define SP2_Y_BASE_AD_INIT2 +#define SP2_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP2_Y_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp2_cb_base_ad_init2 (0x00001530)*/ +/*! Slice: sp2_cb_base_ad_init2:*/ +#define SP2_CB_BASE_AD_INIT2 +#define SP2_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP2_CB_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp2_cr_base_ad_init2 (0x00001534)*/ +/*! Slice: sp2_cr_base_ad_init2:*/ +#define SP2_CR_BASE_AD_INIT2 +#define SP2_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP2_CR_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp2_y_offs_cnt_start (0x00001538)*/ +/*! Slice: sp2_y_offs_cnt_start:*/ +#define SP2_Y_OFFS_CNT_START +#define SP2_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define SP2_Y_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp2_cb_offs_cnt_start (0x0000153c)*/ +/*! Slice: sp2_cb_offs_cnt_start:*/ +#define SP2_CB_OFFS_CNT_START +#define SP2_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define SP2_CB_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp2_cr_offs_cnt_start (0x00001540)*/ +/*! Slice: sp2_cr_offs_cnt_start:*/ +#define SP2_CR_OFFS_CNT_START +#define SP2_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define SP2_CR_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp2_y_base_ad_shd (0x00001544)*/ +/*! Slice: sp2_y_base_ad:*/ +#define SP2_Y_BASE_AD +#define SP2_Y_BASE_AD_MASK 0xFFFFFFF0U +#define SP2_Y_BASE_AD_SHIFT 4U +/*! Register: miv2_sp2_y_size_shd (0x00001548)*/ +/*! Slice: sp2_y_size:*/ +#define SP2_Y_SIZE +#define SP2_Y_SIZE_MASK 0x1FFFFFF0U +#define SP2_Y_SIZE_SHIFT 4U +/*! Register: miv2_sp2_y_offs_cnt_shd (0x0000154c)*/ +/*! Slice: sp2_y_offs_cnt:*/ +#define SP2_Y_OFFS_CNT +#define SP2_Y_OFFS_CNT_MASK 0x1FFFFFF0U +#define SP2_Y_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp2_cb_base_ad_shd (0x00001550)*/ +/*! Slice: sp2_cb_base_ad:*/ +#define SP2_CB_BASE_AD +#define SP2_CB_BASE_AD_MASK 0xFFFFFFF0U +#define SP2_CB_BASE_AD_SHIFT 4U +/*! Register: miv2_sp2_cb_size_shd (0x00001554)*/ +/*! Slice: sp2_cb_size:*/ +#define SP2_CB_SIZE +#define SP2_CB_SIZE_MASK 0x0FFFFFF0U +#define SP2_CB_SIZE_SHIFT 4U +/*! Register: miv2_sp2_cb_offs_cnt_shd (0x00001558)*/ +/*! Slice: sp2_cb_offs_cnt:*/ +#define SP2_CB_OFFS_CNT +#define SP2_CB_OFFS_CNT_MASK 0x0FFFFFF0U +#define SP2_CB_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp2_cr_base_ad_shd (0x0000155c)*/ +/*! Slice: sp2_cr_base_ad:*/ +#define SP2_CR_BASE_AD +#define SP2_CR_BASE_AD_MASK 0xFFFFFFF0U +#define SP2_CR_BASE_AD_SHIFT 4U +/*! Register: miv2_sp2_cr_size_shd (0x00001560)*/ +/*! Slice: sp2_cr_size:*/ +#define SP2_CR_SIZE +#define SP2_CR_SIZE_MASK 0x0FFFFFF0U +#define SP2_CR_SIZE_SHIFT 4U +/*! Register: miv2_sp2_cr_offs_cnt_shd (0x00001564)*/ +/*! Slice: sp2_cr_offs_cnt:*/ +#define SP2_CR_OFFS_CNT +#define SP2_CR_OFFS_CNT_MASK 0x0FFFFFF0U +#define SP2_CR_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp2_raw_base_ad_init (0x00001568)*/ +/*! Slice: sp2_raw_base_ad_init:*/ +#define SP2_RAW_BASE_AD_INIT +#define SP2_RAW_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP2_RAW_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp2_raw_size_init (0x0000156c)*/ +/*! Slice: sp2_raw_size_init:*/ +#define SP2_RAW_SIZE_INIT +#define SP2_RAW_SIZE_INIT_MASK 0x1FFFFFF0U +#define SP2_RAW_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp2_raw_offs_cnt_init (0x00001570)*/ +/*! Slice: sp2_raw_offs_cnt_init:*/ +#define SP2_RAW_OFFS_CNT_INIT +#define SP2_RAW_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define SP2_RAW_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp2_raw_llength (0x00001574)*/ +/*! Slice: sp2_raw_llengh:*/ +#define SP2_RAW_LLENGH +#define SP2_RAW_LLENGH_MASK 0x00007FFFU +#define SP2_RAW_LLENGH_SHIFT 0U +/*! Register: miv2_sp2_raw_pic_width (0x00001578)*/ +/*! Slice: sp2_raw_pic_width:*/ +#define SP2_RAW_PIC_WIDTH +#define SP2_RAW_PIC_WIDTH_MASK 0xFFFFFFFFU +#define SP2_RAW_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_sp2_raw_pic_height (0x0000157c)*/ +/*! Slice: sp2_raw_pic_height:*/ +#define SP2_RAW_PIC_HEIGHT +#define SP2_RAW_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define SP2_RAW_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_sp2_raw_pic_size (0x00001580)*/ +/*! Slice: sp2_raw_pic_size:*/ +#define SP2_RAW_PIC_SIZE +#define SP2_RAW_PIC_SIZE_MASK 0xFFFFFFFFU +#define SP2_RAW_PIC_SIZE_SHIFT 0U +/*! Register: miv2_sp2_raw_offs_cnt_start (0x00001584)*/ +/*! Slice: sp2_raw_offs_cnt_start:*/ +#define SP2_RAW_OFFS_CNT_START +#define SP2_RAW_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define SP2_RAW_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp2_raw_base_ad_shd (0x0000158c)*/ +/*! Slice: sp2_raw_base_ad:*/ +#define SP2_RAW_BASE_AD +#define SP2_RAW_BASE_AD_MASK 0xFFFFFFF0U +#define SP2_RAW_BASE_AD_SHIFT 4U +/*! Register: miv2_sp2_raw_size_shd (0x00001590)*/ +/*! Slice: sp2_raw_size:*/ +#define SP2_RAW_SIZE +#define SP2_RAW_SIZE_MASK 0x1FFFFFF0U +#define SP2_RAW_SIZE_SHIFT 4U +/*! Register: miv2_sp2_raw_offs_cnt_shd (0x00001594)*/ +/*! Slice: sp2_raw_offs_cnt:*/ +#define SP2_RAW_OFFS_CNT +#define SP2_RAW_OFFS_CNT_MASK 0x1FFFFFF0U +#define SP2_RAW_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp2_dma_y_pic_start_ad (0x00001598)*/ +/*! Slice: sp2_dma_y_pic_start_ad:*/ +#define SP2_DMA_Y_PIC_START_AD +#define SP2_DMA_Y_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_Y_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_y_pic_width (0x0000159c)*/ +/*! Slice: sp2_dma_y_pic_width:*/ +#define SP2_DMA_Y_PIC_WIDTH +#define SP2_DMA_Y_PIC_WIDTH_MASK 0x00007FFFU +#define SP2_DMA_Y_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_sp2_dma_y_pic_llength (0x000015a0)*/ +/*! Slice: sp2_dma_y_pic_llength:*/ +#define SP2_DMA_Y_PIC_LLENGTH +#define SP2_DMA_Y_PIC_LLENGTH_MASK 0x00007FFFU +#define SP2_DMA_Y_PIC_LLENGTH_SHIFT 0U +/*! Register: miv2_sp2_dma_y_pic_size (0x000015a4)*/ +/*! Slice: sp2_dma_y_pic_size:*/ +#define SP2_DMA_Y_PIC_SIZE +#define SP2_DMA_Y_PIC_SIZE_MASK 0x0FFFFFFFU +#define SP2_DMA_Y_PIC_SIZE_SHIFT 0U +/*! Register: miv2_sp2_dma_cb_pic_start_ad (0x000015a8)*/ +/*! Slice: sp2_dma_cb_pic_start_ad:*/ +#define SP2_DMA_CB_PIC_START_AD +#define SP2_DMA_CB_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_CB_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_cr_pic_start_ad (0x000015ac)*/ +/*! Slice: sp2_dma_cr_pic_start_ad:*/ +#define SP2_DMA_CR_PIC_START_AD +#define SP2_DMA_CR_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_CR_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_y_pic_start_ad_shd (0x000015b0)*/ +/*! Slice: sp2_dma_y_pic_start_ad:*/ +#define SP2_DMA_Y_PIC_START_AD +#define SP2_DMA_Y_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_Y_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_cb_pic_start_ad_shd (0x000015b4)*/ +/*! Slice: sp2_dma_cb_pic_start_ad:*/ +#define SP2_DMA_CB_PIC_START_AD +#define SP2_DMA_CB_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_CB_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_cr_pic_start_ad_shd (0x000015b8)*/ +/*! Slice: sp2_dma_cr_pic_start_ad:*/ +#define SP2_DMA_CR_PIC_START_AD +#define SP2_DMA_CR_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_CR_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_raw_pic_start_ad (0x000015bc)*/ +/*! Slice: sp2_dma_raw_pic_start_ad:*/ +#define SP2_DMA_RAW_PIC_START_AD +#define SP2_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_RAW_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_raw_pic_width (0x000015c0)*/ +/*! Slice: sp2_dma_raw_pic_width:*/ +#define SP2_DMA_RAW_PIC_WIDTH +#define SP2_DMA_RAW_PIC_WIDTH_MASK 0x00007FFFU +#define SP2_DMA_RAW_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_sp2_dma_raw_pic_llength (0x000015c4)*/ +/*! Slice: sp2_dma_raw_pic_llength:*/ +#define SP2_DMA_RAW_PIC_LLENGTH +#define SP2_DMA_RAW_PIC_LLENGTH_MASK 0x00007FFFU +#define SP2_DMA_RAW_PIC_LLENGTH_SHIFT 0U +/*! Register: miv2_sp2_dma_raw_pic_size (0x000015c8)*/ +/*! Slice: sp2_dma_raw_pic_size:*/ +#define SP2_DMA_RAW_PIC_SIZE +#define SP2_DMA_RAW_PIC_SIZE_MASK 0x0FFFFFFFU +#define SP2_DMA_RAW_PIC_SIZE_SHIFT 0U +/*! Register: miv2_sp2_dma_raw_pic_start_ad_shd (0x000015cc)*/ +/*! Slice: sp2_dma_raw_pic_start_ad:*/ +#define SP2_DMA_RAW_PIC_START_AD +#define SP2_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_RAW_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_status_clr (0x000015d0)*/ +/*! Slice: sp2_jdp_fifo_full:*/ +#define SP2_JDP_FIFO_FULL +#define SP2_JDP_FIFO_FULL_MASK 0x00000010U +#define SP2_JDP_FIFO_FULL_SHIFT 4U +/*! Slice: sp2_raw_fifo_full:*/ +#define SP2_RAW_FIFO_FULL +#define SP2_RAW_FIFO_FULL_MASK 0x00000008U +#define SP2_RAW_FIFO_FULL_SHIFT 3U +/*! Slice: sp2_cr_fifo_full:*/ +#define SP2_CR_FIFO_FULL +#define SP2_CR_FIFO_FULL_MASK 0x00000004U +#define SP2_CR_FIFO_FULL_SHIFT 2U +/*! Slice: sp2_cb_fifo_full:*/ +#define SP2_CB_FIFO_FULL +#define SP2_CB_FIFO_FULL_MASK 0x00000002U +#define SP2_CB_FIFO_FULL_SHIFT 1U +/*! Slice: sp2_y_fifo_full:*/ +#define SP2_Y_FIFO_FULL +#define SP2_Y_FIFO_FULL_MASK 0x00000001U +#define SP2_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_sp2_ctrl_status (0x000015d4)*/ +/*! Slice: sp2_jdp_fifo_full:*/ +#define SP2_JDP_FIFO_FULL +#define SP2_JDP_FIFO_FULL_MASK 0x00000010U +#define SP2_JDP_FIFO_FULL_SHIFT 4U +/*! Slice: sp2_raw_fifo_full:*/ +#define SP2_RAW_FIFO_FULL +#define SP2_RAW_FIFO_FULL_MASK 0x00000008U +#define SP2_RAW_FIFO_FULL_SHIFT 3U +/*! Slice: sp2_cr_fifo_full:*/ +#define SP2_CR_FIFO_FULL +#define SP2_CR_FIFO_FULL_MASK 0x00000004U +#define SP2_CR_FIFO_FULL_SHIFT 2U +/*! Slice: sp2_cb_fifo_full:*/ +#define SP2_CB_FIFO_FULL +#define SP2_CB_FIFO_FULL_MASK 0x00000002U +#define SP2_CB_FIFO_FULL_SHIFT 1U +/*! Slice: sp2_y_fifo_full:*/ +#define SP2_Y_FIFO_FULL +#define SP2_Y_FIFO_FULL_MASK 0x00000001U +#define SP2_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_sp2_axi_status (0x000015d8)*/ +/*! Slice: agsw_enc_pic_rdy:*/ +#define AGSW_ENC_PIC_RDY +#define AGSW_ENC_PIC_RDY_MASK 0x00000002U +#define AGSW_ENC_PIC_RDY_SHIFT 1U +/*! Slice: agsw_enc_buf_full:*/ +#define AGSW_ENC_BUF_FULL +#define AGSW_ENC_BUF_FULL_MASK 0x00000001U +#define AGSW_ENC_BUF_FULL_SHIFT 0U +/*! Register: miv2_sp2_dma_yuv_status (0x000015dc)*/ +/*! Slice: sp2_dma_yuv_active:*/ +#define SP2_DMA_YUV_ACTIVE +#define SP2_DMA_YUV_ACTIVE_MASK 0x00000001U +#define SP2_DMA_YUV_ACTIVE_SHIFT 0U +/*! Register: miv2_sp2_dma_raw_status (0x000015e0)*/ +/*! Slice: sp2_dma_raw_active:*/ +#define SP2_DMA_RAW_ACTIVE +#define SP2_DMA_RAW_ACTIVE_MASK 0x00000001U +#define SP2_DMA_RAW_ACTIVE_SHIFT 0U +/*! Register: miv2_mcm_ctrl (0x00001600)*/ +/*! Slice: mcm_init_offset_en:*/ +#define MCM_RD_CFG_UPD +#define MCM_RD_CFG_UPD_MASK 0x00000040U +#define MCM_RD_CFG_UPD_SHIFT 6U +/*! Slice: mcm_init_offset_en:*/ +#define MCM_RD_AUTO_UPDATE +#define MCM_RD_AUTO_UPDATE_MASK 0x00000020U +#define MCM_RD_AUTO_UPDATE_SHIFT 5U +#define MCM_INIT_OFFSET_EN +#define MCM_INIT_OFFSET_EN_MASK 0x00000010U +#define MCM_INIT_OFFSET_EN_SHIFT 4U +/*! Slice: mcm_init_base_en:*/ +#define MCM_INIT_BASE_EN +#define MCM_INIT_BASE_EN_MASK 0x00000008U +#define MCM_INIT_BASE_EN_SHIFT 3U +/*! Slice: mcm_miv2_cfg_upd:*/ +#define MCM_WR_CFG_UPD +#define MCM_WR_CFG_UPD_MASK 0x00000004U +#define MCM_WR_CFG_UPD_SHIFT 2U +/*! Slice: mcm_miv2_skip:*/ +#define MCM_MI_SKIP +#define MCM_MI_SKIP_MASK 0x00000002U +#define MCM_MI_SKIP_SHIFT 1U +/*! Slice: mcm_auto_update:*/ +#define MCM_WR_AUTO_UPDATE +#define MCM_WR_AUTO_UPDATE_MASK 0x00000001U +#define MCM_WR_AUTO_UPDATE_SHIFT 0U +/*! Register: miv2_mcm_fmt (0x00001604)*/ +/*! Slice: mcm_wr1_fmt_aligned:*/ +#define MCM_WR1_FMT_ALIGNED +#define MCM_WR1_FMT_ALIGNED_MASK 0x00030000U +#define MCM_WR1_FMT_ALIGNED_SHIFT 16U +/*! Slice: mcm_wr0_fmt_aligned:*/ +#define MCM_WR0_FMT_ALIGNED +#define MCM_WR0_FMT_ALIGNED_MASK 0x0000C000U +#define MCM_WR0_FMT_ALIGNED_SHIFT 14U +/*! Slice: mcm_rd_fmt_aligned:*/ +#define MCM_RD_FMT_ALIGNED +#define MCM_RD_FMT_ALIGNED_MASK 0x00003000U +#define MCM_RD_FMT_ALIGNED_SHIFT 12U +/*! Slice: mcm_wr1_raw_bit:*/ +#define MCM_WR1_RAW_BIT +#define MCM_WR1_RAW_BIT_MASK 0x00000F00U +#define MCM_WR1_RAW_BIT_SHIFT 8U +/*! Slice: mcm_wr0_raw_bit:*/ +#define MCM_WR0_RAW_BIT +#define MCM_WR0_RAW_BIT_MASK 0x000000F0U +#define MCM_WR0_RAW_BIT_SHIFT 4U +/*! Slice: mcm_rd_raw_bit:*/ +#define MCM_RD_RAW_BIT +#define MCM_RD_RAW_BIT_MASK 0x0000000FU +#define MCM_RD_RAW_BIT_SHIFT 0U +/*! Register: miv2_mcm_bus_cfg (0x00001608)*/ +/*! Slice: mcm_rd_swap_raw:*/ +#define MCM_RD_SWAP_RAW +#define MCM_RD_SWAP_RAW_MASK 0x000F0000U +#define MCM_RD_SWAP_RAW_SHIFT 16U +/*! Slice: mcm_wr0_swap_raw:*/ +#define MCM_WR0_SWAP_RAW +#define MCM_WR0_SWAP_RAW_MASK 0x0000F000U +#define MCM_WR0_SWAP_RAW_SHIFT 12U +/*! Slice: mcm_wr1_swap_raw:*/ +#define MCM_WR1_SWAP_RAW +#define MCM_WR1_SWAP_RAW_MASK 0x00000F00U +#define MCM_WR1_SWAP_RAW_SHIFT 8U +/*! Slice: mcm_rd_issue_cap:*/ +#define MCM_RD_ISSUE_CAP +#define MCM_RD_ISSUE_CAP_MASK 0x000000C0U +#define MCM_RD_ISSUE_CAP_SHIFT 6U +/*! Slice: mcm_wr_issue_cap:*/ +#define MCM_WR_ISSUE_CAP +#define MCM_WR_ISSUE_CAP_MASK 0x00000030U +#define MCM_WR_ISSUE_CAP_SHIFT 4U +/*! Slice: mcm_rd_burst_len:*/ +#define MCM_RD_BURST_LEN +#define MCM_RD_BURST_LEN_MASK 0x0000000CU +#define MCM_RD_BURST_LEN_SHIFT 2U +/*! Slice: mcm_wr_burst_len:*/ +#define MCM_WR_BURST_LEN +#define MCM_WR_BURST_LEN_MASK 0x00000003U +#define MCM_WR_BURST_LEN_SHIFT 0U +/*! Register: miv2_mcm_bus_id (0x0000160c)*/ +/*! Slice: mcm_bus_sw_en:*/ +#define MCM_BUS_SW_EN +#define MCM_BUS_SW_EN_MASK 0x08000000U +#define MCM_BUS_SW_EN_SHIFT 27U +/*! Slice: mcm_rd_id_en:*/ +#define MCM_RD_ID_EN +#define MCM_RD_ID_EN_MASK 0x04000000U +#define MCM_RD_ID_EN_SHIFT 26U +/*! Slice: mcm_rd_id_cfg:*/ +#define MCM_RD_ID_CFG +#define MCM_RD_ID_CFG_MASK 0x03FC0000U +#define MCM_RD_ID_CFG_SHIFT 18U +/*! Slice: mcm_wr0_id_en:*/ +#define MCM_WR0_ID_EN +#define MCM_WR0_ID_EN_MASK 0x00020000U +#define MCM_WR0_ID_EN_SHIFT 17U +/*! Slice: mcm_wr0_id_cfg:*/ +#define MCM_WR0_ID_CFG +#define MCM_WR0_ID_CFG_MASK 0x0001FE00U +#define MCM_WR0_ID_CFG_SHIFT 9U +/*! Slice: mcm_wr1_id_en:*/ +#define MCM_WR1_ID_EN +#define MCM_WR1_ID_EN_MASK 0x00000100U +#define MCM_WR1_ID_EN_SHIFT 8U +/*! Slice: mcm_wr1_id_cfg:*/ +#define MCM_WR1_ID_CFG +#define MCM_WR1_ID_CFG_MASK 0x000000FFU +#define MCM_WR1_ID_CFG_SHIFT 0U +/*! Register: miv2_mcm_bus_timeo (0x00001610)*/ +/*! Slice: mcm_bus_timeo_en:*/ +#define MCM_BUS_TIMEO_EN +#define MCM_BUS_TIMEO_EN_MASK 0x80000000U +#define MCM_BUS_TIMEO_EN_SHIFT 31U +/*! Slice: mcm_bus_timeo:*/ +#define MCM_BUS_TIMEO +#define MCM_BUS_TIMEO_MASK 0x7FFFFFFFU +#define MCM_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_mcm_raw0_base_ad_init (0x00001614)*/ +/*! Slice: mcm_raw0_base_ad_init:*/ +#define MCM_RAW0_BASE_AD_INIT +#define MCM_RAW0_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MCM_RAW0_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw0_size_init (0x00001618)*/ +/*! Slice: mcm_raw0_size_init:*/ +#define MCM_RAW0_SIZE_INIT +#define MCM_RAW0_SIZE_INIT_MASK 0x1FFFFFF0U +#define MCM_RAW0_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw0_offs_cnt_init (0x0000161c)*/ +/*! Slice: mcm_raw0_offs_cnt_init:*/ +#define MCM_RAW0_OFFS_CNT_INIT +#define MCM_RAW0_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define MCM_RAW0_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw0_llength (0x00001620)*/ +/*! Slice: mcm_raw0_llengh:*/ +#define MCM_RAW0_LLENGH +#define MCM_RAW0_LLENGH_MASK 0x00007FFFU +#define MCM_RAW0_LLENGH_SHIFT 0U +/*! Register: miv2_mcm_raw0_pic_width (0x00001624)*/ +/*! Slice: mcm_raw0_pic_width:*/ +#define MCM_RAW0_PIC_WIDTH +#define MCM_RAW0_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MCM_RAW0_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mcm_raw0_pic_height (0x00001628)*/ +/*! Slice: mcm_raw0_pic_height:*/ +#define MCM_RAW0_PIC_HEIGHT +#define MCM_RAW0_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MCM_RAW0_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_mcm_raw0_pic_size (0x0000162c)*/ +/*! Slice: mcm_raw0_pic_size:*/ +#define MCM_RAW0_PIC_SIZE +#define MCM_RAW0_PIC_SIZE_MASK 0xFFFFFFFFU +#define MCM_RAW0_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mcm_raw0_offs_cnt_start (0x00001630)*/ +/*! Slice: mcm_raw0_offs_cnt_start:*/ +#define MCM_RAW0_OFFS_CNT_START +#define MCM_RAW0_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define MCM_RAW0_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mcm_raw0_base_ad_shd (0x00001634)*/ +/*! Slice: mcm_raw0_base_ad:*/ +#define MCM_RAW0_BASE_AD +#define MCM_RAW0_BASE_AD_MASK 0xFFFFFFF0U +#define MCM_RAW0_BASE_AD_SHIFT 4U +/*! Register: miv2_mcm_raw0_size_shd (0x00001638)*/ +/*! Slice: mcm_raw0_size:*/ +#define MCM_RAW0_SIZE +#define MCM_RAW0_SIZE_MASK 0x1FFFFFF0U +#define MCM_RAW0_SIZE_SHIFT 4U +/*! Register: miv2_mcm_raw0_offs_cnt_shd (0x0000163c)*/ +/*! Slice: mcm_raw0_offs_cnt:*/ +#define MCM_RAW0_OFFS_CNT +#define MCM_RAW0_OFFS_CNT_MASK 0x1FFFFFF0U +#define MCM_RAW0_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mcm_raw1_base_ad_init (0x00001640)*/ +/*! Slice: mcm_raw1_base_ad_init:*/ +#define MCM_RAW1_BASE_AD_INIT +#define MCM_RAW1_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MCM_RAW1_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw1_size_init (0x00001644)*/ +/*! Slice: mcm_raw1_size_init:*/ +#define MCM_RAW1_SIZE_INIT +#define MCM_RAW1_SIZE_INIT_MASK 0x1FFFFFF0U +#define MCM_RAW1_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw1_offs_cnt_init (0x00001648)*/ +/*! Slice: mcm_raw1_offs_cnt_init:*/ +#define MCM_RAW1_OFFS_CNT_INIT +#define MCM_RAW1_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define MCM_RAW1_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw1_llength (0x0000164c)*/ +/*! Slice: mcm_raw1_llengh:*/ +#define MCM_RAW1_LLENGH +#define MCM_RAW1_LLENGH_MASK 0x00007FFFU +#define MCM_RAW1_LLENGH_SHIFT 0U +/*! Register: miv2_mcm_raw1_pic_width (0x00001650)*/ +/*! Slice: mcm_raw1_pic_width:*/ +#define MCM_RAW1_PIC_WIDTH +#define MCM_RAW1_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MCM_RAW1_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mcm_raw1_pic_height (0x00001654)*/ +/*! Slice: mcm_raw1_pic_height:*/ +#define MCM_RAW1_PIC_HEIGHT +#define MCM_RAW1_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MCM_RAW1_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_mcm_raw1_pic_size (0x00001658)*/ +/*! Slice: mcm_raw1_pic_size:*/ +#define MCM_RAW1_PIC_SIZE +#define MCM_RAW1_PIC_SIZE_MASK 0xFFFFFFFFU +#define MCM_RAW1_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mcm_raw1_offs_cnt_start (0x0000165c)*/ +/*! Slice: mcm_raw1_offs_cnt_start:*/ +#define MCM_RAW1_OFFS_CNT_START +#define MCM_RAW1_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define MCM_RAW1_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mcm_raw1_base_ad_shd (0x00001660)*/ +/*! Slice: mcm_raw1_base_ad:*/ +#define MCM_RAW1_BASE_AD +#define MCM_RAW1_BASE_AD_MASK 0xFFFFFFF0U +#define MCM_RAW1_BASE_AD_SHIFT 4U +/*! Register: miv2_mcm_raw1_size_shd (0x00001664)*/ +/*! Slice: mcm_raw1_size:*/ +#define MCM_RAW1_SIZE +#define MCM_RAW1_SIZE_MASK 0x1FFFFFF0U +#define MCM_RAW1_SIZE_SHIFT 4U +/*! Register: miv2_mcm_raw1_offs_cnt_shd (0x00001668)*/ +/*! Slice: mcm_raw1_offs_cnt:*/ +#define MCM_RAW1_OFFS_CNT +#define MCM_RAW1_OFFS_CNT_MASK 0x1FFFFFF0U +#define MCM_RAW1_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mcm_dma_raw_pic_start_ad (0x0000166c)*/ +/*! Slice: mcm_dma_raw_pic_start_ad:*/ +#define MCM_DMA_RAW_PIC_START_AD +#define MCM_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U +#define MCM_DMA_RAW_PIC_START_AD_SHIFT 4U +/*! Register: miv2_mcm_dma_raw_pic_width (0x00001670)*/ +/*! Slice: mcm_dma_raw_pic_width:*/ +#define MCM_DMA_RAW_PIC_WIDTH +#define MCM_DMA_RAW_PIC_WIDTH_MASK 0x00007FFFU +#define MCM_DMA_RAW_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mcm_dma_raw_pic_llength (0x00001674)*/ +/*! Slice: mcm_dma_raw_pic_llength:*/ +#define MCM_DMA_RAW_PIC_LLENGTH +#define MCM_DMA_RAW_PIC_LLENGTH_MASK 0x00007FFFU +#define MCM_DMA_RAW_PIC_LLENGTH_SHIFT 0U +/*! Register: miv2_mcm_dma_raw_pic_size (0x00001678)*/ +/*! Slice: mcm_dma_raw_pic_size:*/ +#define MCM_DMA_RAW_PIC_SIZE +#define MCM_DMA_RAW_PIC_SIZE_MASK 0x0FFFFFFFU +#define MCM_DMA_RAW_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mcm_dma_raw_pic_start_ad_shd (0x0000167c)*/ +/*! Slice: mcm_dma_raw_pic_start_ad:*/ +#define MCM_DMA_RAW_PIC_START_AD +#define MCM_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U +#define MCM_DMA_RAW_PIC_START_AD_SHIFT 4U +/*! Register: miv2_mcm_status_clr (0x00001680)*/ +/*! Slice: mcm_raw1_fifo_full:*/ +#define MCM_RAW1_FIFO_FULL +#define MCM_RAW1_FIFO_FULL_MASK 0x00000002U +#define MCM_RAW1_FIFO_FULL_SHIFT 1U +/*! Slice: mcm_raw0_fifo_full:*/ +#define MCM_RAW0_FIFO_FULL +#define MCM_RAW0_FIFO_FULL_MASK 0x00000001U +#define MCM_RAW0_FIFO_FULL_SHIFT 0U +/*! Register: miv2_mcm_ctrl_status (0x00001684)*/ +/*! Slice: mcm_raw1_fifo_full:*/ +#define MCM_RAW1_FIFO_FULL +#define MCM_RAW1_FIFO_FULL_MASK 0x00000002U +#define MCM_RAW1_FIFO_FULL_SHIFT 1U +/*! Slice: mcm_raw0_fifo_full:*/ +#define MCM_RAW0_FIFO_FULL +#define MCM_RAW0_FIFO_FULL_MASK 0x00000001U +#define MCM_RAW0_FIFO_FULL_SHIFT 0U +/*! Register: miv2_mcm_axi_status (0x00001688)*/ +/*! Slice: agsw_enc_pic_rdy:*/ +#define AGSW_ENC_PIC_RDY +#define AGSW_ENC_PIC_RDY_MASK 0x00000002U +#define AGSW_ENC_PIC_RDY_SHIFT 1U +/*! Slice: agsw_enc_buf_full:*/ +#define AGSW_ENC_BUF_FULL +#define AGSW_ENC_BUF_FULL_MASK 0x00000001U +#define AGSW_ENC_BUF_FULL_SHIFT 0U +/*! Register: miv2_mcm_dma_status (0x0000168c)*/ +/*! Slice: mcm_dma_active:*/ +#define MCM_DMA_ACTIVE +#define MCM_DMA_ACTIVE_MASK 0x00000001U +#define MCM_DMA_ACTIVE_SHIFT 0U +/*! Register: miv2_imsc (0x000016c0)*/ +/*! Slice: fill_mp_y:*/ +#define FILL_MP_Y +#define FILL_MP_Y_MASK 0x08000000U +#define FILL_MP_Y_SHIFT 27U +/*! Slice: mblk_line:*/ +#define MBLK_LINE +#define MBLK_LINE_MASK 0x04000000U +#define MBLK_LINE_SHIFT 26U +/*! Slice: mp_handshk_int:*/ +#define MP_HANDSHK_INT +#define MP_HANDSHK_INT_MASK 0x02000000U +#define MP_HANDSHK_INT_SHIFT 25U +/*! Slice: mcm_dma_raw_ready:*/ +#define MCM_DMA_RAW_READY +#define MCM_DMA_RAW_READY_MASK 0x01000000U +#define MCM_DMA_RAW_READY_SHIFT 24U +/*! Slice: sp2_dma_raw_ready:*/ +#define SP2_DMA_RAW_READY +#define SP2_DMA_RAW_READY_MASK 0x00800000U +#define SP2_DMA_RAW_READY_SHIFT 23U +/*! Slice: sp2_dma_ycbcr_ready:*/ +#define SP2_DMA_YCBCR_READY +#define SP2_DMA_YCBCR_READY_MASK 0x00400000U +#define SP2_DMA_YCBCR_READY_SHIFT 22U +/*! Slice: wrap_mcm_raw1:*/ +#define WRAP_MCM_RAW1 +#define WRAP_MCM_RAW1_MASK 0x00200000U +#define WRAP_MCM_RAW1_SHIFT 21U +/*! Slice: wrap_mcm_raw0:*/ +#define WRAP_MCM_RAW0 +#define WRAP_MCM_RAW0_MASK 0x00100000U +#define WRAP_MCM_RAW0_SHIFT 20U +/*! Slice: wrap_sp2_cr:*/ +#define WRAP_SP2_CR +#define WRAP_SP2_CR_MASK 0x00040000U +#define WRAP_SP2_CR_SHIFT 18U +/*! Slice: wrap_sp2_cb:*/ +#define WRAP_SP2_CB +#define WRAP_SP2_CB_MASK 0x00020000U +#define WRAP_SP2_CB_SHIFT 17U +/*! Slice: wrap_sp2_y:*/ +#define WRAP_SP2_Y +#define WRAP_SP2_Y_MASK 0x00010000U +#define WRAP_SP2_Y_SHIFT 16U +/*! Slice: wrap_sp1_cr:*/ +#define WRAP_SP1_CR +#define WRAP_SP1_CR_MASK 0x00008000U +#define WRAP_SP1_CR_SHIFT 15U +/*! Slice: wrap_sp1_cb:*/ +#define WRAP_SP1_CB +#define WRAP_SP1_CB_MASK 0x00004000U +#define WRAP_SP1_CB_SHIFT 14U +/*! Slice: wrap_sp1_y:*/ +#define WRAP_SP1_Y +#define WRAP_SP1_Y_MASK 0x00002000U +#define WRAP_SP1_Y_SHIFT 13U +/*! Slice: wrap_mp_jdp:*/ +#define WRAP_MP_JDP +#define WRAP_MP_JDP_MASK 0x00001000U +#define WRAP_MP_JDP_SHIFT 12U +/*! Slice: wrap_mp_raw:*/ +#define WRAP_MP_RAW +#define WRAP_MP_RAW_MASK 0x00000800U +#define WRAP_MP_RAW_SHIFT 11U +/*! Slice: wrap_mp_cr:*/ +#define WRAP_MP_CR +#define WRAP_MP_CR_MASK 0x00000400U +#define WRAP_MP_CR_SHIFT 10U +/*! Slice: wrap_mp_cb:*/ +#define WRAP_MP_CB +#define WRAP_MP_CB_MASK 0x00000200U +#define WRAP_MP_CB_SHIFT 9U +/*! Slice: wrap_mp_y:*/ +#define WRAP_MP_Y +#define WRAP_MP_Y_MASK 0x00000100U +#define WRAP_MP_Y_SHIFT 8U +/*! Slice: mcm_raw1_frame_end:*/ +#define MCM_RAW1_FRAME_END +#define MCM_RAW1_FRAME_END_MASK 0x00000080U +#define MCM_RAW1_FRAME_END_SHIFT 7U +/*! Slice: mcm_raw0_frame_end:*/ +#define MCM_RAW0_FRAME_END +#define MCM_RAW0_FRAME_END_MASK 0x00000040U +#define MCM_RAW0_FRAME_END_SHIFT 6U +/*! Slice: sp2_raw_frame_end:*/ +#define SP2_RAW_FRAME_END +#define SP2_RAW_FRAME_END_MASK 0x00000020U +#define SP2_RAW_FRAME_END_SHIFT 5U +/*! Slice: sp2_ycbcr_frame_end:*/ +#define SP2_YCBCR_FRAME_END +#define SP2_YCBCR_FRAME_END_MASK 0x00000010U +#define SP2_YCBCR_FRAME_END_SHIFT 4U +/*! Slice: sp1_ycbcr_frame_end:*/ +#define SP1_YCBCR_FRAME_END +#define SP1_YCBCR_FRAME_END_MASK 0x00000008U +#define SP1_YCBCR_FRAME_END_SHIFT 3U +/*! Slice: mp_jdp_frame_end:*/ +#define MP_JDP_FRAME_END +#define MP_JDP_FRAME_END_MASK 0x00000004U +#define MP_JDP_FRAME_END_SHIFT 2U +/*! Slice: mp_raw_frame_end:*/ +#define MP_RAW_FRAME_END +#define MP_RAW_FRAME_END_MASK 0x00000002U +#define MP_RAW_FRAME_END_SHIFT 1U +/*! Slice: mp_ycbcr_frame_end:*/ +#define MP_YCBCR_FRAME_END +#define MP_YCBCR_FRAME_END_MASK 0x00000001U +#define MP_YCBCR_FRAME_END_SHIFT 0U +/*! Register: miv2_imsc1 (0x000016c4)*/ +/*! Slice: miv2_mcm_bus_buserr:*/ +#define MI_MCM_BUS_BUSERR +#define MI_MCM_BUS_BUSERR_MASK 0x00000080U +#define MI_MCM_BUS_BUSERR_SHIFT 7U +/*! Slice: miv2_mcm_bus_timeo:*/ +#define MI_MCM_BUS_TIMEO +#define MI_MCM_BUS_TIMEO_MASK 0x00000040U +#define MI_MCM_BUS_TIMEO_SHIFT 6U +/*! Slice: miv2_sp2_bus_buserr:*/ +#define MI_SP2_BUS_BUSERR +#define MI_SP2_BUS_BUSERR_MASK 0x00000020U +#define MI_SP2_BUS_BUSERR_SHIFT 5U +/*! Slice: miv2_sp2_bus_timeo:*/ +#define MI_SP2_BUS_TIMEO +#define MI_SP2_BUS_TIMEO_MASK 0x00000010U +#define MI_SP2_BUS_TIMEO_SHIFT 4U +/*! Slice: miv2_sp1_bus_buserr:*/ +#define MI_SP1_BUS_BUSERR +#define MI_SP1_BUS_BUSERR_MASK 0x00000008U +#define MI_SP1_BUS_BUSERR_SHIFT 3U +/*! Slice: miv2_sp1_bus_timeo:*/ +#define MI_SP1_BUS_TIMEO +#define MI_SP1_BUS_TIMEO_MASK 0x00000004U +#define MI_SP1_BUS_TIMEO_SHIFT 2U +/*! Slice: miv2_mp_bus_buserr:*/ +#define MI_MP_BUS_BUSERR +#define MI_MP_BUS_BUSERR_MASK 0x00000002U +#define MI_MP_BUS_BUSERR_SHIFT 1U +/*! Slice: miv2_mp_bus_timeo:*/ +#define MI_MP_BUS_TIMEO +#define MI_MP_BUS_TIMEO_MASK 0x00000001U +#define MI_MP_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_isr (0x000016c8)*/ +/*! Slice: fill_mp_y:*/ +#define FILL_MP_Y +#define FILL_MP_Y_MASK 0x08000000U +#define FILL_MP_Y_SHIFT 27U +/*! Slice: mblk_line:*/ +#define MBLK_LINE +#define MBLK_LINE_MASK 0x04000000U +#define MBLK_LINE_SHIFT 26U +/*! Slice: mp_handshk_int:*/ +#define MP_HANDSHK_INT +#define MP_HANDSHK_INT_MASK 0x02000000U +#define MP_HANDSHK_INT_SHIFT 25U +/*! Slice: mcm_dma_raw_ready:*/ +#define MCM_DMA_RAW_READY +#define MCM_DMA_RAW_READY_MASK 0x01000000U +#define MCM_DMA_RAW_READY_SHIFT 24U +/*! Slice: sp2_dma_raw_ready:*/ +#define SP2_DMA_RAW_READY +#define SP2_DMA_RAW_READY_MASK 0x00800000U +#define SP2_DMA_RAW_READY_SHIFT 23U +/*! Slice: sp2_dma_ycbcr_ready:*/ +#define SP2_DMA_YCBCR_READY +#define SP2_DMA_YCBCR_READY_MASK 0x00400000U +#define SP2_DMA_YCBCR_READY_SHIFT 22U +/*! Slice: wrap_mcm_raw1:*/ +#define WRAP_MCM_RAW1 +#define WRAP_MCM_RAW1_MASK 0x00200000U +#define WRAP_MCM_RAW1_SHIFT 21U +/*! Slice: wrap_mcm_raw0:*/ +#define WRAP_MCM_RAW0 +#define WRAP_MCM_RAW0_MASK 0x00100000U +#define WRAP_MCM_RAW0_SHIFT 20U +/*! Slice: wrap_sp2_cr:*/ +#define WRAP_SP2_CR +#define WRAP_SP2_CR_MASK 0x00040000U +#define WRAP_SP2_CR_SHIFT 18U +/*! Slice: wrap_sp2_cb:*/ +#define WRAP_SP2_CB +#define WRAP_SP2_CB_MASK 0x00020000U +#define WRAP_SP2_CB_SHIFT 17U +/*! Slice: wrap_sp2_y:*/ +#define WRAP_SP2_Y +#define WRAP_SP2_Y_MASK 0x00010000U +#define WRAP_SP2_Y_SHIFT 16U +/*! Slice: wrap_sp1_cr:*/ +#define WRAP_SP1_CR +#define WRAP_SP1_CR_MASK 0x00008000U +#define WRAP_SP1_CR_SHIFT 15U +/*! Slice: wrap_sp1_cb:*/ +#define WRAP_SP1_CB +#define WRAP_SP1_CB_MASK 0x00004000U +#define WRAP_SP1_CB_SHIFT 14U +/*! Slice: wrap_sp1_y:*/ +#define WRAP_SP1_Y +#define WRAP_SP1_Y_MASK 0x00002000U +#define WRAP_SP1_Y_SHIFT 13U +/*! Slice: wrap_mp_jdp:*/ +#define WRAP_MP_JDP +#define WRAP_MP_JDP_MASK 0x00001000U +#define WRAP_MP_JDP_SHIFT 12U +/*! Slice: wrap_mp_raw:*/ +#define WRAP_MP_RAW +#define WRAP_MP_RAW_MASK 0x00000800U +#define WRAP_MP_RAW_SHIFT 11U +/*! Slice: wrap_mp_cr:*/ +#define WRAP_MP_CR +#define WRAP_MP_CR_MASK 0x00000400U +#define WRAP_MP_CR_SHIFT 10U +/*! Slice: wrap_mp_cb:*/ +#define WRAP_MP_CB +#define WRAP_MP_CB_MASK 0x00000200U +#define WRAP_MP_CB_SHIFT 9U +/*! Slice: wrap_mp_y:*/ +#define WRAP_MP_Y +#define WRAP_MP_Y_MASK 0x00000100U +#define WRAP_MP_Y_SHIFT 8U +/*! Slice: mcm_raw1_frame_end:*/ +#define MCM_RAW1_FRAME_END +#define MCM_RAW1_FRAME_END_MASK 0x00000080U +#define MCM_RAW1_FRAME_END_SHIFT 7U +/*! Slice: mcm_raw0_frame_end:*/ +#define MCM_RAW0_FRAME_END +#define MCM_RAW0_FRAME_END_MASK 0x00000040U +#define MCM_RAW0_FRAME_END_SHIFT 6U +/*! Slice: sp2_raw_frame_end:*/ +#define SP2_RAW_FRAME_END +#define SP2_RAW_FRAME_END_MASK 0x00000020U +#define SP2_RAW_FRAME_END_SHIFT 5U +/*! Slice: sp2_ycbcr_frame_end:*/ +#define SP2_YCBCR_FRAME_END +#define SP2_YCBCR_FRAME_END_MASK 0x00000010U +#define SP2_YCBCR_FRAME_END_SHIFT 4U +/*! Slice: sp1_ycbcr_frame_end:*/ +#define SP1_YCBCR_FRAME_END +#define SP1_YCBCR_FRAME_END_MASK 0x00000008U +#define SP1_YCBCR_FRAME_END_SHIFT 3U +/*! Slice: mp_jdp_frame_end:*/ +#define MP_JDP_FRAME_END +#define MP_JDP_FRAME_END_MASK 0x00000004U +#define MP_JDP_FRAME_END_SHIFT 2U +/*! Slice: mp_raw_frame_end:*/ +#define MP_RAW_FRAME_END +#define MP_RAW_FRAME_END_MASK 0x00000002U +#define MP_RAW_FRAME_END_SHIFT 1U +/*! Slice: mp_ycbcr_frame_end:*/ +#define MP_YCBCR_FRAME_END +#define MP_YCBCR_FRAME_END_MASK 0x00000001U +#define MP_YCBCR_FRAME_END_SHIFT 0U +/*! Register: miv2_isr1 (0x000016cc)*/ +/*! Slice: miv2_mcm_bus_buserr:*/ +#define MI_MCM_BUS_BUSERR +#define MI_MCM_BUS_BUSERR_MASK 0x00000080U +#define MI_MCM_BUS_BUSERR_SHIFT 7U +/*! Slice: miv2_mcm_bus_timeo:*/ +#define MI_MCM_BUS_TIMEO +#define MI_MCM_BUS_TIMEO_MASK 0x00000040U +#define MI_MCM_BUS_TIMEO_SHIFT 6U +/*! Slice: miv2_sp2_bus_buserr:*/ +#define MI_SP2_BUS_BUSERR +#define MI_SP2_BUS_BUSERR_MASK 0x00000020U +#define MI_SP2_BUS_BUSERR_SHIFT 5U +/*! Slice: miv2_sp2_bus_timeo:*/ +#define MI_SP2_BUS_TIMEO +#define MI_SP2_BUS_TIMEO_MASK 0x00000010U +#define MI_SP2_BUS_TIMEO_SHIFT 4U +/*! Slice: miv2_sp1_bus_buserr:*/ +#define MI_SP1_BUS_BUSERR +#define MI_SP1_BUS_BUSERR_MASK 0x00000008U +#define MI_SP1_BUS_BUSERR_SHIFT 3U +/*! Slice: miv2_sp1_bus_timeo:*/ +#define MI_SP1_BUS_TIMEO +#define MI_SP1_BUS_TIMEO_MASK 0x00000004U +#define MI_SP1_BUS_TIMEO_SHIFT 2U +#define MRV_MI_BP_PATH_ENABLE +#define MRV_MI_BP_PATH_ENABLE_MASK 0x00000001U +#define MRV_MI_BP_PATH_ENABLE_SHIFT 0U +/*! Register: bp_ctrl: Control register */ +/*! Slice: bp_output_format */ +/* 000 raw8 + 001 raw10 + 010 raw12 +*/ +#define MRV_MI_BP_WRITE_RAWBIT +#define MRV_MI_BP_WRITE_RAWBIT_MASK 0x0000001cU +#define MRV_MI_BP_WRITE_RAWBIT_SHIFT 2U +#define MRV_MI_BP_WRITE_FORMAT +#define MRV_MI_BP_WRITE_FORMAT_MASK 0x00000300U +#define MRV_MI_BP_WRITE_FORMAT_SHIFT 8U +#define MRV_MI_BP_WRITE_PLANAR_FORMAT 1 +#define MRV_MI_BP_WRITE_INTERLEAVE_FORMAT 2 +/*! Slice: miv2_mp_bus_buserr:*/ +#define MI_MP_BUS_BUSERR +#define MI_MP_BUS_BUSERR_MASK 0x00000002U +#define MI_MP_BUS_BUSERR_SHIFT 1U +/*! Slice: miv2_mp_bus_timeo:*/ +#define MI_MP_BUS_TIMEO +#define MI_MP_BUS_TIMEO_MASK 0x00000001U +#define MI_MP_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_mis (0x000016d0) */ +/*! Slice: fill_mp_y: */ +#define FILL_MP_Y +#define FILL_MP_Y_MASK 0x08000000U +#define FILL_MP_Y_SHIFT 27U +/*! Slice: mblk_line: */ +#define MBLK_LINE +#define MBLK_LINE_MASK 0x04000000U +#define MBLK_LINE_SHIFT 26U +/*! Slice: mp_handshk_int: */ +#define MP_HANDSHK_INT +#define MP_HANDSHK_INT_MASK 0x02000000U +#define MP_HANDSHK_INT_SHIFT 25U +/*! Slice: mcm_dma_raw_ready: */ +#define MCM_DMA_RAW_READY +#define MCM_DMA_RAW_READY_MASK 0x01000000U +#define MCM_DMA_RAW_READY_SHIFT 24U +/*! Slice: sp2_dma_raw_ready: */ +#define SP2_DMA_RAW_READY +#define SP2_DMA_RAW_READY_MASK 0x00800000U +#define SP2_DMA_RAW_READY_SHIFT 23U +/*! Slice: sp2_dma_ycbcr_ready: */ +#define SP2_DMA_YCBCR_READY +#define SP2_DMA_YCBCR_READY_MASK 0x00400000U +#define SP2_DMA_YCBCR_READY_SHIFT 22U +/*! Slice: wrap_mcm_raw1: */ +#define WRAP_MCM_RAW1 +#define WRAP_MCM_RAW1_MASK 0x00200000U +#define WRAP_MCM_RAW1_SHIFT 21U +/*! Slice: wrap_mcm_raw0: */ +#define WRAP_MCM_RAW0 +#define WRAP_MCM_RAW0_MASK 0x00100000U +#define WRAP_MCM_RAW0_SHIFT 20U +/*! Slice: wrap_sp2_cr: */ +#define WRAP_SP2_CR +#define WRAP_SP2_CR_MASK 0x00040000U +#define WRAP_SP2_CR_SHIFT 18U +/*! Slice: wrap_sp2_cb: */ +#define WRAP_SP2_CB +#define WRAP_SP2_CB_MASK 0x00020000U +#define WRAP_SP2_CB_SHIFT 17U +/*! Slice: wrap_sp2_y: */ +#define WRAP_SP2_Y +#define WRAP_SP2_Y_MASK 0x00010000U +#define WRAP_SP2_Y_SHIFT 16U +/*! Slice: wrap_sp1_cr: */ +#define WRAP_SP1_CR +#define WRAP_SP1_CR_MASK 0x00008000U +#define WRAP_SP1_CR_SHIFT 15U +/*! Slice: wrap_sp1_cb: */ +#define WRAP_SP1_CB +#define WRAP_SP1_CB_MASK 0x00004000U +#define WRAP_SP1_CB_SHIFT 14U +/*! Slice: wrap_sp1_y: */ +#define WRAP_SP1_Y +#define WRAP_SP1_Y_MASK 0x00002000U +#define WRAP_SP1_Y_SHIFT 13U +/*! Slice: wrap_mp_jdp: */ +#define WRAP_MP_JDP +#define WRAP_MP_JDP_MASK 0x00001000U +#define WRAP_MP_JDP_SHIFT 12U +/*! Slice: wrap_mp_raw: */ +#define WRAP_MP_RAW +#define WRAP_MP_RAW_MASK 0x00000800U +#define WRAP_MP_RAW_SHIFT 11U +/*! Slice: wrap_mp_cr: */ +#define WRAP_MP_CR +#define WRAP_MP_CR_MASK 0x00000400U +#define WRAP_MP_CR_SHIFT 10U +/*! Slice: wrap_mp_cb: */ +#define WRAP_MP_CB +#define WRAP_MP_CB_MASK 0x00000200U +#define WRAP_MP_CB_SHIFT 9U +/*! Slice: wrap_mp_y: */ +#define WRAP_MP_Y +#define WRAP_MP_Y_MASK 0x00000100U +#define WRAP_MP_Y_SHIFT 8U +/*! Slice: mcm_raw1_frame_end: */ +#define MCM_RAW1_FRAME_END +#define MCM_RAW1_FRAME_END_MASK 0x00000080U +#define MCM_RAW1_FRAME_END_SHIFT 7U +/*! Slice: mcm_raw0_frame_end: */ +#define MCM_RAW0_FRAME_END +#define MCM_RAW0_FRAME_END_MASK 0x00000040U +#define MCM_RAW0_FRAME_END_SHIFT 6U +/*! Slice: sp2_raw_frame_end: */ +#define SP2_RAW_FRAME_END +#define SP2_RAW_FRAME_END_MASK 0x00000020U +#define SP2_RAW_FRAME_END_SHIFT 5U +/*! Slice: sp2_ycbcr_frame_end: */ +#define SP2_YCBCR_FRAME_END +#define SP2_YCBCR_FRAME_END_MASK 0x00000010U +#define SP2_YCBCR_FRAME_END_SHIFT 4U +/*! Slice: sp1_ycbcr_frame_end: */ +#define SP1_YCBCR_FRAME_END +#define SP1_YCBCR_FRAME_END_MASK 0x00000008U +#define SP1_YCBCR_FRAME_END_SHIFT 3U +/*! Slice: mp_jdp_frame_end: */ +#define MP_JDP_FRAME_END +#define MP_JDP_FRAME_END_MASK 0x00000004U +#define MP_JDP_FRAME_END_SHIFT 2U +/*! Slice: mp_raw_frame_end: */ +#define MP_RAW_FRAME_END +#define MP_RAW_FRAME_END_MASK 0x00000002U +#define MP_RAW_FRAME_END_SHIFT 1U +/*! Slice: mp_ycbcr_frame_end: */ +#define MP_YCBCR_FRAME_END +#define MP_YCBCR_FRAME_END_MASK 0x00000001U +#define MP_YCBCR_FRAME_END_SHIFT 0U +/*! Register: miv2_mis1 (0x000016d4) */ +/*! Slice: miv2_mcm_bus_buserr: */ +#define MI_MCM_BUS_BUSERR +#define MI_MCM_BUS_BUSERR_MASK 0x00000080U +#define MI_MCM_BUS_BUSERR_SHIFT 7U +/*! Slice: miv2_mcm_bus_timeo: */ +#define MI_MCM_BUS_TIMEO +#define MI_MCM_BUS_TIMEO_MASK 0x00000040U +#define MI_MCM_BUS_TIMEO_SHIFT 6U +/*! Slice: miv2_sp2_bus_buserr: */ +#define MI_SP2_BUS_BUSERR +#define MI_SP2_BUS_BUSERR_MASK 0x00000020U +#define MI_SP2_BUS_BUSERR_SHIFT 5U +/*! Slice: miv2_sp2_bus_timeo: */ +#define MI_SP2_BUS_TIMEO +#define MI_SP2_BUS_TIMEO_MASK 0x00000010U +#define MI_SP2_BUS_TIMEO_SHIFT 4U +/*! Slice: miv2_sp1_bus_buserr: */ +#define MI_SP1_BUS_BUSERR +#define MI_SP1_BUS_BUSERR_MASK 0x00000008U +#define MI_SP1_BUS_BUSERR_SHIFT 3U +/*! Slice: miv2_sp1_bus_timeo: */ +#define MI_SP1_BUS_TIMEO +#define MI_SP1_BUS_TIMEO_MASK 0x00000004U +#define MI_SP1_BUS_TIMEO_SHIFT 2U +/*! Slice: miv2_mp_bus_buserr: */ +#define MI_MP_BUS_BUSERR +#define MI_MP_BUS_BUSERR_MASK 0x00000002U +#define MI_MP_BUS_BUSERR_SHIFT 1U +/*! Slice: miv2_mp_bus_timeo: */ +#define MI_MP_BUS_TIMEO +#define MI_MP_BUS_TIMEO_MASK 0x00000001U +#define MI_MP_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_icr (0x000016d8) */ +/*! Slice: fill_mp_y: */ +#define FILL_MP_Y +#define FILL_MP_Y_MASK 0x08000000U +#define FILL_MP_Y_SHIFT 27U +/*! Slice: mblk_line: */ +#define MBLK_LINE +#define MBLK_LINE_MASK 0x04000000U +#define MBLK_LINE_SHIFT 26U +/*! Slice: mp_handshk_int: */ +#define MP_HANDSHK_INT +#define MP_HANDSHK_INT_MASK 0x02000000U +#define MP_HANDSHK_INT_SHIFT 25U +/*! Slice: mcm_dma_raw_ready: */ +#define MCM_DMA_RAW_READY +#define MCM_DMA_RAW_READY_MASK 0x01000000U +#define MCM_DMA_RAW_READY_SHIFT 24U +/*! Slice: sp2_dma_raw_ready: */ +#define SP2_DMA_RAW_READY +#define SP2_DMA_RAW_READY_MASK 0x00800000U +#define SP2_DMA_RAW_READY_SHIFT 23U +/*! Slice: sp2_dma_ycbcr_ready: */ +#define SP2_DMA_YCBCR_READY +#define SP2_DMA_YCBCR_READY_MASK 0x00400000U +#define SP2_DMA_YCBCR_READY_SHIFT 22U +/*! Slice: wrap_mcm_raw1: */ +#define WRAP_MCM_RAW1 +#define WRAP_MCM_RAW1_MASK 0x00200000U +#define WRAP_MCM_RAW1_SHIFT 21U +/*! Slice: wrap_mcm_raw0: */ +#define WRAP_MCM_RAW0 +#define WRAP_MCM_RAW0_MASK 0x00100000U +#define WRAP_MCM_RAW0_SHIFT 20U +/*! Slice: wrap_sp2_cr: */ +#define WRAP_SP2_CR +#define WRAP_SP2_CR_MASK 0x00040000U +#define WRAP_SP2_CR_SHIFT 18U +/*! Slice: wrap_sp2_cb: */ +#define WRAP_SP2_CB +#define WRAP_SP2_CB_MASK 0x00020000U +#define WRAP_SP2_CB_SHIFT 17U +/*! Slice: wrap_sp2_y: */ +#define WRAP_SP2_Y +#define WRAP_SP2_Y_MASK 0x00010000U +#define WRAP_SP2_Y_SHIFT 16U +/*! Slice: wrap_sp1_cr: */ +#define WRAP_SP1_CR +#define WRAP_SP1_CR_MASK 0x00008000U +#define WRAP_SP1_CR_SHIFT 15U +/*! Slice: wrap_sp1_cb: */ +#define WRAP_SP1_CB +#define WRAP_SP1_CB_MASK 0x00004000U +#define WRAP_SP1_CB_SHIFT 14U +/*! Slice: wrap_sp1_y: */ +#define WRAP_SP1_Y +#define WRAP_SP1_Y_MASK 0x00002000U +#define WRAP_SP1_Y_SHIFT 13U +/*! Slice: wrap_mp_jdp: */ +#define WRAP_MP_JDP +#define WRAP_MP_JDP_MASK 0x00001000U +#define WRAP_MP_JDP_SHIFT 12U +/*! Slice: wrap_mp_raw: */ +#define WRAP_MP_RAW +#define WRAP_MP_RAW_MASK 0x00000800U +#define WRAP_MP_RAW_SHIFT 11U +/*! Slice: wrap_mp_cr: */ +#define WRAP_MP_CR +#define WRAP_MP_CR_MASK 0x00000400U +#define WRAP_MP_CR_SHIFT 10U +/*! Slice: wrap_mp_cb: */ +#define WRAP_MP_CB +#define WRAP_MP_CB_MASK 0x00000200U +#define WRAP_MP_CB_SHIFT 9U +/*! Slice: wrap_mp_y: */ +#define WRAP_MP_Y +#define WRAP_MP_Y_MASK 0x00000100U +#define WRAP_MP_Y_SHIFT 8U +/*! Slice: mcm_raw1_frame_end: */ +#define MCM_RAW1_FRAME_END +#define MCM_RAW1_FRAME_END_MASK 0x00000080U +#define MCM_RAW1_FRAME_END_SHIFT 7U +/*! Slice: mcm_raw0_frame_end: */ +#define MCM_RAW0_FRAME_END +#define MCM_RAW0_FRAME_END_MASK 0x00000040U +#define MCM_RAW0_FRAME_END_SHIFT 6U +/*! Slice: sp2_raw_frame_end: */ +#define SP2_RAW_FRAME_END +#define SP2_RAW_FRAME_END_MASK 0x00000020U +#define SP2_RAW_FRAME_END_SHIFT 5U +/*! Slice: sp2_ycbcr_frame_end: */ +#define SP2_YCBCR_FRAME_END +#define SP2_YCBCR_FRAME_END_MASK 0x00000010U +#define SP2_YCBCR_FRAME_END_SHIFT 4U +/*! Slice: sp1_ycbcr_frame_end: */ +#define SP1_YCBCR_FRAME_END +#define SP1_YCBCR_FRAME_END_MASK 0x00000008U +#define SP1_YCBCR_FRAME_END_SHIFT 3U +/*! Slice: mp_jdp_frame_end: */ +#define MP_JDP_FRAME_END +#define MP_JDP_FRAME_END_MASK 0x00000004U +#define MP_JDP_FRAME_END_SHIFT 2U +/*! Slice: mp_raw_frame_end: */ +#define MP_RAW_FRAME_END +#define MP_RAW_FRAME_END_MASK 0x00000002U +#define MP_RAW_FRAME_END_SHIFT 1U +/*! Slice: mp_ycbcr_frame_end: */ +#define MP_YCBCR_FRAME_END +#define MP_YCBCR_FRAME_END_MASK 0x00000001U +#define MP_YCBCR_FRAME_END_SHIFT 0U +/*! Register: miv2_icr1 (0x000016dc) */ +/*! Slice: miv2_mcm_bus_buserr: */ +#define MI_MCM_BUS_BUSERR +#define MI_MCM_BUS_BUSERR_MASK 0x00000080U +#define MI_MCM_BUS_BUSERR_SHIFT 7U +/*! Slice: miv2_mcm_bus_timeo: */ +#define MI_MCM_BUS_TIMEO +#define MI_MCM_BUS_TIMEO_MASK 0x00000040U +#define MI_MCM_BUS_TIMEO_SHIFT 6U +/*! Slice: miv2_sp2_bus_buserr: */ +#define MI_SP2_BUS_BUSERR +#define MI_SP2_BUS_BUSERR_MASK 0x00000020U +#define MI_SP2_BUS_BUSERR_SHIFT 5U +/*! Slice: miv2_sp2_bus_timeo: */ +#define MI_SP2_BUS_TIMEO +#define MI_SP2_BUS_TIMEO_MASK 0x00000010U +#define MI_SP2_BUS_TIMEO_SHIFT 4U +/*! Slice: miv2_sp1_bus_buserr: */ +#define MI_SP1_BUS_BUSERR +#define MI_SP1_BUS_BUSERR_MASK 0x00000008U +#define MI_SP1_BUS_BUSERR_SHIFT 3U +/*! Slice: miv2_sp1_bus_timeo: */ +#define MI_SP1_BUS_TIMEO +#define MI_SP1_BUS_TIMEO_MASK 0x00000004U +#define MI_SP1_BUS_TIMEO_SHIFT 2U +/*! Slice: miv2_mp_bus_buserr: */ +#define MI_MP_BUS_BUSERR +#define MI_MP_BUS_BUSERR_MASK 0x00000002U +#define MI_MP_BUS_BUSERR_SHIFT 1U +/*! Slice: miv2_mp_bus_timeo: */ +#define MI_MP_BUS_TIMEO +#define MI_MP_BUS_TIMEO_MASK 0x00000001U +#define MI_MP_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_ris (0x000016e0) */ +/*! Slice: fill_mp_y: */ +#define FILL_MP_Y +#define FILL_MP_Y_MASK 0x08000000U +#define FILL_MP_Y_SHIFT 27U +/*! Slice: mblk_line: */ +#define MBLK_LINE +#define MBLK_LINE_MASK 0x04000000U +#define MBLK_LINE_SHIFT 26U +/*! Slice: mp_handshk_int: */ +#define MP_HANDSHK_INT +#define MP_HANDSHK_INT_MASK 0x02000000U +#define MP_HANDSHK_INT_SHIFT 25U +/*! Slice: mcm_dma_raw_ready: */ +#define MCM_DMA_RAW_READY +#define MCM_DMA_RAW_READY_MASK 0x01000000U +#define MCM_DMA_RAW_READY_SHIFT 24U +/*! Slice: sp2_dma_raw_ready: */ +#define SP2_DMA_RAW_READY +#define SP2_DMA_RAW_READY_MASK 0x00800000U +#define SP2_DMA_RAW_READY_SHIFT 23U +/*! Slice: sp2_dma_ycbcr_ready: */ +#define SP2_DMA_YCBCR_READY +#define SP2_DMA_YCBCR_READY_MASK 0x00400000U +#define SP2_DMA_YCBCR_READY_SHIFT 22U +/*! Slice: wrap_mcm_raw1: */ +#define WRAP_MCM_RAW1 +#define WRAP_MCM_RAW1_MASK 0x00200000U +#define WRAP_MCM_RAW1_SHIFT 21U +/*! Slice: wrap_mcm_raw0: */ +#define WRAP_MCM_RAW0 +#define WRAP_MCM_RAW0_MASK 0x00100000U +#define WRAP_MCM_RAW0_SHIFT 20U +/*! Slice: wrap_sp2_raw: */ +#define WRAP_SP2_RAW +#define WRAP_SP2_RAW_MASK (0x1 << 16) +#define WRAP_SP2_RAW_SHIFT 16U +/*! Slice: wrap_sp2_cr: */ +#define WRAP_SP2_CR +#define WRAP_SP2_CR_MASK 0x00040000U +#define WRAP_SP2_CR_SHIFT 18U +/*! Slice: wrap_sp2_cb: */ +#define WRAP_SP2_CB +#define WRAP_SP2_CB_MASK 0x00020000U +#define WRAP_SP2_CB_SHIFT 17U +/*! Slice: wrap_sp2_y: */ +#define WRAP_SP2_Y +#define WRAP_SP2_Y_MASK 0x00010000U +#define WRAP_SP2_Y_SHIFT 16U +/*! Slice: wrap_sp1_cr: */ +#define WRAP_SP1_CR +#define WRAP_SP1_CR_MASK 0x00008000U +#define WRAP_SP1_CR_SHIFT 15U +/*! Slice: wrap_sp1_cb: */ +#define WRAP_SP1_CB +#define WRAP_SP1_CB_MASK 0x00004000U +#define WRAP_SP1_CB_SHIFT 14U +/*! Slice: wrap_sp1_y: */ +#define WRAP_SP1_Y +#define WRAP_SP1_Y_MASK 0x00002000U +#define WRAP_SP1_Y_SHIFT 13U +/*! Slice: wrap_mp_jdp: */ +#define WRAP_MP_JDP +#define WRAP_MP_JDP_MASK 0x00001000U +#define WRAP_MP_JDP_SHIFT 12U +/*! Slice: wrap_mp_raw: */ +#define WRAP_MP_RAW +#define WRAP_MP_RAW_MASK 0x00000800U +#define WRAP_MP_RAW_SHIFT 11U +/*! Slice: wrap_mp_cr: */ +#define WRAP_MP_CR +#define WRAP_MP_CR_MASK 0x00000400U +#define WRAP_MP_CR_SHIFT 10U +/*! Slice: wrap_mp_cb: */ +#define WRAP_MP_CB +#define WRAP_MP_CB_MASK 0x00000200U +#define WRAP_MP_CB_SHIFT 9U +/*! Slice: wrap_mp_y: */ +#define WRAP_MP_Y +#define WRAP_MP_Y_MASK 0x00000100U +#define WRAP_MP_Y_SHIFT 8U +/*! Slice: mcm_raw1_frame_end: */ +#define MCM_RAW1_FRAME_END +#define MCM_RAW1_FRAME_END_MASK 0x00000080U +#define MCM_RAW1_FRAME_END_SHIFT 7U +/*! Slice: mcm_raw0_frame_end: */ +#define MCM_RAW0_FRAME_END +#define MCM_RAW0_FRAME_END_MASK 0x00000040U +#define MCM_RAW0_FRAME_END_SHIFT 6U +/*! Slice: sp2_raw_frame_end: */ +#define SP2_RAW_FRAME_END +#define SP2_RAW_FRAME_END_MASK 0x00000020U +#define SP2_RAW_FRAME_END_SHIFT 5U +/*! Slice: sp2_ycbcr_frame_end: */ +#define SP2_YCBCR_FRAME_END +#define SP2_YCBCR_FRAME_END_MASK 0x00000010U +#define SP2_YCBCR_FRAME_END_SHIFT 4U +/*! Slice: sp1_ycbcr_frame_end: */ +#define SP1_YCBCR_FRAME_END +#define SP1_YCBCR_FRAME_END_MASK 0x00000008U +#define SP1_YCBCR_FRAME_END_SHIFT 3U +/*! Slice: mp_jdp_frame_end: */ +#define MP_JDP_FRAME_END +#define MP_JDP_FRAME_END_MASK 0x00000004U +#define MP_JDP_FRAME_END_SHIFT 2U +/*! Slice: mp_raw_frame_end: */ +#define MP_RAW_FRAME_END +#define MP_RAW_FRAME_END_MASK 0x00000002U +#define MP_RAW_FRAME_END_SHIFT 1U +/*! Slice: mp_ycbcr_frame_end: */ +#define MP_YCBCR_FRAME_END +#define MP_YCBCR_FRAME_END_MASK 0x00000001U +#define MP_YCBCR_FRAME_END_SHIFT 0U +/*! Register: miv2_ris1 (0x000016e4)*/ +/*! Slice: miv2_mcm_bus_buserr:*/ +#define MI_MCM_BUS_BUSERR +#define MI_MCM_BUS_BUSERR_MASK 0x00000080U +#define MI_MCM_BUS_BUSERR_SHIFT 7U +/*! Slice: miv2_mcm_bus_timeo:*/ +#define MI_MCM_BUS_TIMEO +#define MI_MCM_BUS_TIMEO_MASK 0x00000040U +#define MI_MCM_BUS_TIMEO_SHIFT 6U +/*! Slice: miv2_sp2_bus_buserr:*/ +#define MI_SP2_BUS_BUSERR +#define MI_SP2_BUS_BUSERR_MASK 0x00000020U +#define MI_SP2_BUS_BUSERR_SHIFT 5U +/*! Slice: miv2_sp2_bus_timeo:*/ +#define MI_SP2_BUS_TIMEO +#define MI_SP2_BUS_TIMEO_MASK 0x00000010U +#define MI_SP2_BUS_TIMEO_SHIFT 4U +/*! Slice: miv2_sp1_bus_buserr:*/ +#define MI_SP1_BUS_BUSERR +#define MI_SP1_BUS_BUSERR_MASK 0x00000008U +#define MI_SP1_BUS_BUSERR_SHIFT 3U +/*! Slice: miv2_sp1_bus_timeo:*/ +#define MI_SP1_BUS_TIMEO +#define MI_SP1_BUS_TIMEO_MASK 0x00000004U +#define MI_SP1_BUS_TIMEO_SHIFT 2U +/*! Slice: miv2_mp_bus_buserr:*/ +#define MI_MP_BUS_BUSERR +#define MI_MP_BUS_BUSERR_MASK 0x00000002U +#define MI_MP_BUS_BUSERR_SHIFT 1U +/*! Slice: miv2_mp_bus_timeo:*/ +#define MI_MP_BUS_TIMEO +#define MI_MP_BUS_TIMEO_MASK 0x00000001U +#define MI_MP_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_mp_y_irq_offs_init (0x00001700)*/ +/*! Slice: mp_y_irq_offs_init:*/ +#define MP_Y_IRQ_OFFS_INIT +#define MP_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MP_Y_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_mp_jdp_irq_offs_init (0x00001704)*/ +/*! Slice: mp_jdp_irq_offs_init:*/ +#define MP_JDP_IRQ_OFFS_INIT +#define MP_JDP_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MP_JDP_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_mp_raw_irq_offs_init (0x00001708)*/ +/*! Slice: mp_raw_irq_offs_init:*/ +#define MP_RAW_IRQ_OFFS_INIT +#define MP_RAW_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MP_RAW_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_sp1_y_irq_offs_init (0x0000170c)*/ +/*! Slice: sp1_y_irq_offs_init:*/ +#define SP1_Y_IRQ_OFFS_INIT +#define SP1_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define SP1_Y_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_sp2_y_irq_offs_init (0x00001710)*/ +/*! Slice: sp2_y_irq_offs_init:*/ +#define SP2_Y_IRQ_OFFS_INIT +#define SP2_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define SP2_Y_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_sp2_raw_irq_offs_init (0x00001714)*/ +/*! Slice: sp2_raw_irq_offs_init:*/ +#define SP2_RAW_IRQ_OFFS_INIT +#define SP2_RAW_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define SP2_RAW_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_mcm_raw0_irq_offs_init (0x00001718)*/ +/*! Slice: mcm_raw0_irq_offs_init:*/ +#define MCM_RAW0_IRQ_OFFS_INIT +#define MCM_RAW0_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MCM_RAW0_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_mcm_raw1_irq_offs_init (0x0000171c)*/ +/*! Slice: mcm_raw1_irq_offs_init:*/ +#define MCM_RAW1_IRQ_OFFS_INIT +#define MCM_RAW1_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MCM_RAW1_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_mp_y_irq_offs_shd (0x00001720)*/ +/*! Slice: mp_y_irq_offs:*/ +#define MP_Y_IRQ_OFFS +#define MP_Y_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MP_Y_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_mp_jdp_irq_offs_shd (0x00001724)*/ +/*! Slice: mp_jdp_irq_offs:*/ +#define MP_JDP_IRQ_OFFS +#define MP_JDP_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MP_JDP_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_mp_raw_irq_offs_shd (0x00001728)*/ +/*! Slice: mp_raw_irq_offs:*/ +#define MP_RAW_IRQ_OFFS +#define MP_RAW_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MP_RAW_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_sp1_y_irq_offs_shd (0x0000172c)*/ +/*! Slice: sp1_y_irq_offs:*/ +#define SP1_Y_IRQ_OFFS +#define SP1_Y_IRQ_OFFS_MASK 0x1FFFFFF8U +#define SP1_Y_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_sp2_y_irq_offs_shd (0x00001730)*/ +/*! Slice: sp2_y_irq_offs:*/ +#define SP2_Y_IRQ_OFFS +#define SP2_Y_IRQ_OFFS_MASK 0x1FFFFFF8U +#define SP2_Y_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_sp2_raw_irq_offs_shd (0x00001734)*/ +/*! Slice: sp2_raw_irq_offs:*/ +#define SP2_RAW_IRQ_OFFS +#define SP2_RAW_IRQ_OFFS_MASK 0x1FFFFFF8U +#define SP2_RAW_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_mcm_raw0_irq_offs_shd (0x00001738)*/ +/*! Slice: mcm_raw0_irq_offs:*/ +#define MCM_RAW0_IRQ_OFFS +#define MCM_RAW0_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MCM_RAW0_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_mcm_raw1_irq_offs_shd (0x0000173c)*/ +/*! Slice: mcm_raw1_irq_offs:*/ +#define MCM_RAW1_IRQ_OFFS +#define MCM_RAW1_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MCM_RAW1_IRQ_OFFS_SHIFT 3U +/*! Register: isp_ee_ctrl (0x00003900)*/ +/*! Slice: isp_ee_ctrl enable:*/ +#define EE_CTRL_ENABLE +#define EE_CTRL_ENABLE_MASK 0x00000001U +#define EE_CTRL_ENABLE_SHIFT 0U +/*! Slice: isp_ee_ctrl_input_sel_flag:*/ +#define EE_CTRL_INPUT_SEL +#define EE_CTRL_INPUT_SEL_MASK 0x00000002U +#define EE_CTRL_INPUT_SEL_SHIFT 1U +/*! Slice: isp_ee_ctrl_soft_reset_flag:*/ +#define EE_CTRL_SOFT_RESET_FLAG +#define EE_CTRL_SOFT_RESET_FLAG_MASK 0x00000004U +#define EE_CTRL_SOFT_RESET_FLAG_SHIFT 2U +/*! Slice: isp_ee_ctrl_strength:*/ +#define EE_CTRL_STRENGTH +#define EE_CTRL_STRENGTH_MASK 0x000007F8U +#define EE_CTRL_STRENGTH_SHIFT 3U +/*! Slice: isp_ee_ctrl_source_strength:*/ +#define EE_CTRL_SOURCE_STRENGTH +#define EE_CTRL_SOURCE_STRENGTH_MASK 0x0007F800U +#define EE_CTRL_SOURCE_STRENGTH_SHIFT 11U +/*! Register: isp_ee_y_gain (0x00003904)*/ +/*! Slice: ee_y_down_gain: */ +#define EE_Y_DOWN_GAIN +#define EE_Y_DOWN_GAIN_MASK 0xFFFF0000U +#define EE_Y_DOWN_GAIN_SHIFT 16U +/*! Slice: ee_y_up_gain: */ +#define EE_Y_UP_GAIN +#define EE_Y_UP_GAIN_MASK 0x0000FFFFU +#define EE_Y_UP_GAIN_SHIFT 0U +/*! Slice: ee_y_gain:*/ +#define EE_Y_GAIN +#define EE_Y_GAIN_MASK 0xFFFFFFFFU +#define EE_Y_GAIN_SHIFT 0U +/*! Register: isp_ee_edge_gain (0x00003908)*/ +/*! Slice: isp_ee_edge_gain:*/ +#define EE_EDGE_GAIN +#define EE_EDGE_GAIN_MASK 0xFFFF0000U +#define EE_EDGE_GAIN_SHIFT 16U +/*! Register: isp_ee_uv_gain (0x00003908)*/ +/*! Slice: isp_ee_uv_gain:*/ +#define EE_UV_GAIN +#define EE_UV_GAIN_MASK 0x0000FFFFU +#define EE_UV_GAIN_SHIFT 0U +/*! Register: isp_ee_dummy_hblank (0x00003918)*/ +/*! Slice: isp_ee_dummy_hblank:*/ +#define ISP_EE_DUMMY_HBLANK +#define ISP_EE_DUMMY_HBLANK_MASK 0x0000FFFFU +#define ISP_EE_DUMMY_HBLANK_SHIFT 0U +/*! Register: isp_ee_ctrl_shd (0x0000390c)*/ +/*! Slice: isp_ee_ctrl_shd enable:*/ +#define EE_CTRL_ENABLE_SHD +#define EE_CTRL_ENABLE_SHD_MASK 0x00000001U +#define EE_CTRL_ENABLE_SHD_SHIFT 0U +/*! Slice: isp_ee_ctrl_input_sel_shd:*/ +#define EE_CTRL_INPUT_SEL_SHD +#define EE_CTRL_INPUT_SEL_SHD_MASK 0x00000002U +#define EE_CTRL_INPUT_SEL_SHD_SHIFT 1U +/*! Slice: isp_ee_ctrl_soft_reset_flag_shd:*/ +#define EE_CTRL_SOFT_RESET_FLAG_SHD +#define EE_CTRL_SOFT_RESET_FLAG_SHD_MASK 0x00000004U +#define EE_CTRL_SOFT_RESET_FLAG_SHD_SHIFT 2U +/*! Slice: isp_ee_ctrl_strength_shd:*/ +#define EE_CTRL_STRENGTH_SHD +#define EE_CTRL_STRENGTH_SHD_MASK 0x000007F8U +#define EE_CTRL_STRENGTH_SHD_SHIFT 3U +/*! Slice: isp_ee_ctrl_source_strength_shd:*/ +#define EE_CTRL_SOURCE_STRENGTH_SHD +#define EE_CTRL_SOURCE_STRENGTH_SHD_MASK 0xFF000000U +#define EE_CTRL_SOURCE_STRENGTH_SHD_SHIFT 24U +/*! Register: isp_ee_y_gain_shd (0x00003910)*/ +/*! Slice: isp_ee_y_gain_shd:*/ +#define EE_Y_GAIN_SHD +#define EE_Y_GAIN_SHD_MASK 0xFFFFFFFFU +#define EE_Y_GAIN_SHD_SHIFT 0U +/*! Register: isp_ee_edge_gain_shd (0x00003908)*/ +/*! Slice: isp_ee_edge_gain_shd:*/ +#define EE_EDGE_GAIN_SHD +#define EE_EDGE_GAIN_SHD_MASK 0xFFFF0000U +#define EE_EDGE_GAIN_SHD_SHIFT 16U +/*! Register: isp_ee_uv_gain_shd (0x00003914)*/ +/*! Slice: isp_ee_uv_gain_shd:*/ +#define EE_UV_GAIN_SHD +#define EE_UV_GAIN_SHD_MASK 0x0000FFFFU +#define EE_UV_GAIN_SHD_SHIFT 0U +#define ISP_DEMOSAIC_THR +#define ISP_DEMOSAIC_THR_MASK 0xff000000U +#define ISP_DEMOSAIC_THR_SHIFT 24U +#define ISP_DEMOSAIC_DENOISE_STRENGTH +#define ISP_DEMOSAIC_DENOISE_STRENGTH_MASK 0x003f0000U +#define ISP_DEMOSAIC_DENOISE_STRENGTH_SHIFT 16U +#define ISP_DEMOSAIC_SHARPEN_SIZE +#define ISP_DEMOSAIC_SHARPEN_SIZE_MASK 0x00001f00U +#define ISP_DEMOSAIC_SHARPEN_SIZE_SHIFT 8U +#define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE +#define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE_MASK 0x00000020U +#define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE_SHIFT 5U +#define ISP_DEMOSAIC_SKIN_ENABLE +#define ISP_DEMOSAIC_SKIN_ENABLE_MASK 0x00000010U +#define ISP_DEMOSAIC_SKIN_ENABLE_SHIFT 4U +#define ISP_DEMOSAIC_DEPURPLE_ENABLE +#define ISP_DEMOSAIC_DEPURPLE_ENABLE_MASK 0x00000008U +#define ISP_DEMOSAIC_DEPURPLE_ENABLE_SHIFT 3U +#define ISP_DEMOSAIC_DEMOIRE_ENABLE +#define ISP_DEMOSAIC_DEMOIRE_ENABLE_MASK 0x00000004U +#define ISP_DEMOSAIC_DEMOIRE_ENABLE_SHIFT 2U +#define ISP_DEMOSAIC_SHARPEN_ENBALE +#define ISP_DEMOSAIC_SHARPEN_ENBALE_MASK 0x00000002U +#define ISP_DEMOSAIC_SHARPEN_ENBALE_SHIFT 1U +#define ISP_DEMOSAIC_BYPASS +#define ISP_DEMOSAIC_BYPASS_MASK 0x00000001U +#define ISP_DEMOSAIC_BYPASS_SHIFT 0U +#define ISP_DMSC_INTERPLATION_DIR_THR_MIN +#define ISP_DMSC_INTERPLATION_DIR_THR_MIN_MASK 0x00fff000U +#define ISP_DMSC_INTERPLATION_DIR_THR_MIN_SHIFT 12U +#define ISP_DMSC_INTERPLATION_DIR_THR_MAX +#define ISP_DMSC_INTERPLATION_DIR_THR_MAX_MASK 0x00000fffU +#define ISP_DMSC_INTERPLATION_DIR_THR_MAX_SHIFT 0U +#define ISP_DMSC_DEMOIRE_AREA_THR +#define ISP_DMSC_DEMOIRE_AREA_THR_MASK 0x00003f00U +#define ISP_DMSC_DEMOIRE_AREA_THR_SHIFT 8U +#define ISP_DMSC_DEMOIRE_SAT_SHRINK +#define ISP_DMSC_DEMOIRE_SAT_SHRINK_MASK 0x0000003fU +#define ISP_DMSC_DEMOIRE_SAT_SHRINK_SHIFT 0U +#define ISP_DMSC_DEMOIRE_R2 +#define ISP_DMSC_DEMOIRE_R2_MASK 0x3FE00000U +#define ISP_DMSC_DEMOIRE_R2_SHIFT 21U +#define ISP_DMSC_DEMOIRE_R1 +#define ISP_DMSC_DEMOIRE_R1_MASK 0x001ff000U +#define ISP_DMSC_DEMOIRE_R1_SHIFT 12U +#define ISP_DMSC_DEMOIRE_T2_SHIFT +#define ISP_DMSC_DEMOIRE_T2_SHIFT_MASK 0x00000f00U +#define ISP_DMSC_DEMOIRE_T2_SHIFT_SHIFT 8U +#define ISP_DMSC_DEMOIRE_T1 +#define ISP_DMSC_DEMOIRE_T1_MASK 0x000000FFU +#define ISP_DMSC_DEMOIRE_T1_SHIFT 0U +#define ISP_DMSC_DEMOIRE_EDGE_R2 +#define ISP_DMSC_DEMOIRE_EDGE_R2_MASK 0x7fc00000U +#define ISP_DMSC_DEMOIRE_EDGE_R2_SHIFT 22U +#define ISP_DMSC_DEMOIRE_EDGE_R1 +#define ISP_DMSC_DEMOIRE_EDGE_R1_MASK 0x003fe000U +#define ISP_DMSC_DEMOIRE_EDGE_R1_SHIFT 13U +#define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT +#define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT_MASK 0x00001e00U +#define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT_SHIFT 9U +#define ISP_DMSC_DEMOIRE_EDGE_T1 +#define ISP_DMSC_DEMOIRE_EDGE_T1_MASK 0x000001ffU +#define ISP_DMSC_DEMOIRE_EDGE_T1_SHIFT 0U +#define ISP_DMSC_SHARPEN_FACTOR_BLACK +#define ISP_DMSC_SHARPEN_FACTOR_BLACK_MASK 0x001ff000U +#define ISP_DMSC_SHARPEN_FACTOR_BLACK_SHIFT 12U +#define ISP_DMSC_SHARPEN_FACTOR_WHITE +#define ISP_DMSC_SHARPEN_FACTOR_WHITE_MASK 0x000001ffU +#define ISP_DMSC_SHARPEN_FACTOR_WHITE_SHIFT 0U +#define ISP_DMSC_SHARPEN_CLIP_BLACK +#define ISP_DMSC_SHARPEN_CLIP_BLACK_MASK 0x007ff000U +#define ISP_DMSC_SHARPEN_CLIP_BLACK_SHIFT 12U +#define ISP_DMSC_SHARPEN_CLIP_WHITE +#define ISP_DMSC_SHARPEN_CLIP_WHITE_MASK 0x000007ffU +#define ISP_DMSC_SHARPEN_CLIP_WHITE_SHIFT 0U +#define ISP_DMSC_SHARPEN_T4_SHIFT +#define ISP_DMSC_SHARPEN_T4_SHIFT_MASK 0xf0000000U +#define ISP_DMSC_SHARPEN_T4_SHIFT_SHIFT 28U +#define ISP_DMSC_SHARPEN_T3 +#define ISP_DMSC_SHARPEN_T3_MASK 0x07ff0000U +#define ISP_DMSC_SHARPEN_T3_SHIFT 16U +#define ISP_DMSC_SHARPEN_T2_SHIFT +#define ISP_DMSC_SHARPEN_T2_SHIFT_MASK 0x0000f000U +#define ISP_DMSC_SHARPEN_T2_SHIFT_SHIFT 12U +#define ISP_DMSC_SHARPEN_T1 +#define ISP_DMSC_SHARPEN_T1_MASK 0x000003ffU +#define ISP_DMSC_SHARPEN_T1_SHIFT 0U +#define ISP_DMSC_SHARPEN_R3 +#define ISP_DMSC_SHARPEN_R3_MASK 0x07fc0000 +#define ISP_DMSC_SHARPEN_R3_SHIFT 18U +#define ISP_DMSC_SHARPEN_R2 +#define ISP_DMSC_SHARPEN_R2_MASK 0x0003fe00 +#define ISP_DMSC_SHARPEN_R2_SHIFT 9U +#define ISP_DMSC_SHARPEN_R1 +#define ISP_DMSC_SHARPEN_R1_MASK 0x000001ffU +#define ISP_DMSC_SHARPEN_R1_SHIFT 0U +#define ISP_DMSC_SHARPEN_LINE_SHIFT2 +#define ISP_DMSC_SHARPEN_LINE_SHIFT2_MASK 0xf0000000U +#define ISP_DMSC_SHARPEN_LINE_SHIFT2_SHIFT 28U +#define ISP_DMSC_SHARPEN_LINE_SHIFT1 +#define ISP_DMSC_SHARPEN_LINE_SHIFT1_MASK 0x0f000000U +#define ISP_DMSC_SHARPEN_LINE_SHIFT1_SHIFT 24U +#define ISP_DMSC_SHARPEN_LINE_T1 +#define ISP_DMSC_SHARPEN_LINE_T1_MASK 0x007ff000U +#define ISP_DMSC_SHARPEN_LINE_T1_SHIFT 12U +#define ISP_DMSC_SHARPEN_LINE_STRENGTH +#define ISP_DMSC_SHARPEN_LINE_STRENGTH_MASK 0x00000fffU +#define ISP_DMSC_SHARPEN_LINE_STRENGTH_SHIFT 0U +#define ISP_DMSC_SHARPEN_LINE_R2 +#define ISP_DMSC_SHARPEN_LINE_R2_MASK 0x0003fe00 +#define ISP_DMSC_SHARPEN_LINE_R2_SHIFT 9U +#define ISP_DMSC_SHARPEN_LINE_R1 +#define ISP_DMSC_SHARPEN_LINE_R1_MASK 0x000001ffU +#define ISP_DMSC_SHARPEN_LINE_R1_SHIFT 0U +#define ISP_DMSC_HF_FILT_00 +#define ISP_DMSC_HF_FILT_00_MASK 0x3f000000U +#define ISP_DMSC_HF_FILT_00_SHIFT 24U +#define ISP_DMSC_HF_FILT_01 +#define ISP_DMSC_HF_FILT_01_MASK 0x00fc0000U +#define ISP_DMSC_HF_FILT_01_SHIFT 18U +#define ISP_DMSC_HF_FILT_02 +#define ISP_DMSC_HF_FILT_02_MASK 0x0003f000U +#define ISP_DMSC_HF_FILT_02_SHIFT 12U +#define ISP_DMSC_HF_FILT_10 +#define ISP_DMSC_HF_FILT_10_MASK 0x00000fc0U +#define ISP_DMSC_HF_FILT_10_SHIFT 6U +#define ISP_DMSC_HF_FILT_11 +#define ISP_DMSC_HF_FILT_11_MASK 0x0000003fU +#define ISP_DMSC_HF_FILT_11_SHIFT 0U +#define ISP_DMSC_HF_FILT_12 +#define ISP_DMSC_HF_FILT_12_MASK 0x00fc0000U +#define ISP_DMSC_HF_FILT_12_SHIFT 18U +#define ISP_DMSC_HF_FILT_20 +#define ISP_DMSC_HF_FILT_20_MASK 0x0003f000U +#define ISP_DMSC_HF_FILT_20_SHIFT 12U +#define ISP_DMSC_HF_FILT_21 +#define ISP_DMSC_HF_FILT_21_MASK 0x00000fc0U +#define ISP_DMSC_HF_FILT_21_SHIFT 6U +#define ISP_DMSC_HF_FILT_22 +#define ISP_DMSC_HF_FILT_22_MASK 0x0000003fU +#define ISP_DMSC_HF_FILT_22_SHIFT 0U +#define ISP_DMSC_DEPURPLE_RED_SAT +#define ISP_DMSC_DEPURPLE_RED_SAT_MASK 0x00001000U +#define ISP_DMSC_DEPURPLE_RED_SAT_SHIFT 12U +#define ISP_DMSC_DEPURPLE_BLUE_SAT +#define ISP_DMSC_DEPURPLE_BLUE_SAT_MASK 0x00002000U +#define ISP_DMSC_DEPURPLE_BLUE_SAT_SHIFT 13U +#define ISP_DMSC_DEPURPLE_SAT_SHRINK +#define ISP_DMSC_DEPURPLE_SAT_SHRINK_MASK 0x00000f00U +#define ISP_DMSC_DEPURPLE_SAT_SHRINK_SHIFT 8U +#define ISP_DMSC_DEPURPLE_THR +#define ISP_DMSC_DEPURPLE_THR_MASK 0x000000ffU +#define ISP_DMSC_DEPURPLE_THR_SHIFT 0U +#define ISP_DMSC_SKIN_CB_THR_MAX_2047 +#define ISP_DMSC_SKIN_CB_THR_MAX_2047_MASK 0x00FFF000U +#define ISP_DMSC_SKIN_CB_THR_MAX_2047_SHIFT 12U +#define ISP_DMSC_SKIN_CB_THR_MIN_2047 +#define ISP_DMSC_SKIN_CB_THR_MIN_2047_MASK 0x00000fffU +#define ISP_DMSC_SKIN_CB_THR_MIN_2047_SHIFT 0U +#define ISP_DMSC_SKIN_CR_THR_MAX_2047 +#define ISP_DMSC_SKIN_CR_THR_MAX_2047_MASK 0x00FFF000U +#define ISP_DMSC_SKIN_CR_THR_MAX_2047_SHIFT 12U +#define ISP_DMSC_SKIN_CR_THR_MIN_2047 +#define ISP_DMSC_SKIN_CR_THR_MIN_2047_MASK 0x00000fffU +#define ISP_DMSC_SKIN_CR_THR_MIN_2047_SHIFT 0U +#define ISP_DMSC_SKIN_Y_THR_MAX +#define ISP_DMSC_SKIN_Y_THR_MAX_MASK 0x00FFF000U +#define ISP_DMSC_SKIN_Y_THR_MAX_SHIFT 12U +#define ISP_DMSC_SKIN_Y_THR_MIN +#define ISP_DMSC_SKIN_Y_THR_MIN_MASK 0x00000fffU +#define ISP_DMSC_SKIN_Y_THR_MIN_SHIFT 0U +#define ISP_DMSC_CAC_ENABLE +#define ISP_DMSC_CAC_ENABLE_MASK 0x00000001U +#define ISP_DMSC_CAC_ENABLE_SHIFT 0U +#define ISP_DMSC_V_COUNT_START +#define ISP_DMSC_V_COUNT_START_MASK 0xffff0000U +#define ISP_DMSC_V_COUNT_START_SHIFT 16U +#define ISP_DMSC_H_COUNT_START +#define ISP_DMSC_H_COUNT_START_MASK 0x0000ffffU +#define ISP_DMSC_H_COUNT_START_SHIFT 0U +#define ISP_DMSC_A_RED +#define ISP_DMSC_A_RED_MASK 0x01ff0000U +#define ISP_DMSC_A_RED_SHIFT 16U +#define ISP_DMSC_A_BLUE +#define ISP_DMSC_A_BLUE_MASK 0x000001ffU +#define ISP_DMSC_A_BLUE_SHIFT 0U +#define ISP_DMSC_B_RED +#define ISP_DMSC_B_RED_MASK 0x01ff0000U +#define ISP_DMSC_B_RED_SHIFT 16U +#define ISP_DMSC_B_BLUE +#define ISP_DMSC_B_BLUE_MASK 0x000001ffU +#define ISP_DMSC_B_BLUE_SHIFT 0U +#define ISP_DMSC_C_RED +#define ISP_DMSC_C_RED_MASK 0x01ff0000U +#define ISP_DMSC_C_RED_SHIFT 16U +#define ISP_DMSC_C_BLUE +#define ISP_DMSC_C_BLUE_MASK 0x000001ffU +#define ISP_DMSC_C_BLUE_SHIFT 0U +#define ISP_DMSC_X_NS +#define ISP_DMSC_X_NS_MASK 0x000f0000U +#define ISP_DMSC_X_NS_SHIFT 16U +#define ISP_DMSC_X_NF +#define ISP_DMSC_X_NF_MASK 0x0000001f +#define ISP_DMSC_X_NF_SHIFT 0U +#define ISP_DMSC_Y_NS +#define ISP_DMSC_Y_NS_MASK 0x000f0000U +#define ISP_DMSC_Y_NS_SHIFT 16U +#define ISP_DMSC_Y_NF +#define ISP_DMSC_Y_NF_MASK 0x0000001fU +#define ISP_DMSC_Y_NF_SHIFT 0U +#define ISP_DMSC_Y_NF +#define ISP_DMSC_Y_NF_MASK 0x0000001fU +#define ISP_DMSC_Y_NF_SHIFT 0U +#define ISP_DMSC_IMAGE_H_SIZE +#define ISP_DMSC_IMAGE_H_SIZE_MASK 0x0000ffffU +#define ISP_DMSC_IMAGE_H_SIZE_SHIFT 0U +#define ISP_DMSC_IMAGE_H_BLANK +#define ISP_DMSC_IMAGE_H_BLANK_MASK 0xffff0000U +#define ISP_DMSC_IMAGE_H_BLANK_SHIFT 16U +#define ISP_DMSC_H_BLANK +#define ISP_DMSC_H_BLANK_MASK 0xffff0000U +#define ISP_DMSC_H_BLANK_SHIFT 16U +#define ISP_GREEN_EQUILIBTATE_TH +#define ISP_GREEN_EQUILIBTATE_TH_MASK 0x0001fffeU +#define ISP_GREEN_EQUILIBTATE_TH_SHIFT 1U +#define ISP_GREEN_EQUILIBTATE_ENABLE +#define ISP_GREEN_EQUILIBTATE_ENABLE_MASK 0x00000001U +#define ISP_GREEN_EQUILIBTATE_ENABLE_SHIFT 0U +#define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY +#define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY_MASK 0x0000ffffU +#define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY_SHIFT 0U +#define ISP_CURVE_MODE +#define ISP_CURVE_MODE_MASK 0x00000006U +#define ISP_CURVE_MODE_SHIFT 1U +#define ISP_CURVE_ENABLE +#define ISP_CURVE_ENABLE_MASK 0x00000001U +#define ISP_CURVE_ENABLE_SHIFT 0U +#define ISP_CURVE_LUT_X_ADDR +#define ISP_CURVE_LUT_X_ADDR_MASK 0x0000007fU +#define ISP_CURVE_LUT_X_ADDR_SHIFT 0U +#define ISP_CURVE_LUT_X_WRITE_DATA +#define ISP_CURVE_LUT_X_WRITE_DATA_MASK 0x000000fffU +#define ISP_CURVE_LUT_X_WRITE_DATA_SHIFT 0U +#define ISP_CURVE_LUT_LUMA_ADDR +#define ISP_CURVE_LUT_LUMA_ADDR_MASK 0x0000007fU +#define ISP_CURVE_LUT_LUMA_ADDR_SHIFT 0U +#define ISP_CURVE_LUT_LUMA_WRITE_DATA +#define ISP_CURVE_LUT_LUMA_WRITE_DATA_MASK 0x000007ffU +#define ISP_CURVE_LUT_LUMA_WRITE_DATA_SHIFT 0U +#define ISP_CURVE_LUT_CHROMA_ADDR +#define ISP_CURVE_LUT_CHROMA_ADDR_MASK 0x0000007fU +#define ISP_CURVE_LUT_CHROMA_ADDR_SHIFT 0U +#define ISP_CURVE_LUT_CHROMA_WRITE_DATA +#define ISP_CURVE_LUT_CHROMA_WRITE_DATA_MASK 0x00000fffU +#define ISP_CURVE_LUT_CHROMA_WRITE_DATA_SHIFT 0U +#define ISP_CURVE_LUT_SHIFT_ADDR +#define ISP_CURVE_LUT_SHIFT_ADDR_MASK 0x0000007fU +#define ISP_CURVE_LUT_SHIFT_ADDR_SHIFT 0U +#define ISP_CURVE_LUT_SHIFT_WRITE_DATA +#define ISP_CURVE_LUT_SHIFT_WRITE_DATA_MASK 0x0000001fU +#define ISP_CURVE_LUT_SHIFT_WRITE_DATA_SHIFT 0U +#define ISP_DIGITAL_GAIN_R +#define ISP_DIGITAL_GAIN_R_MASK 0xffff0000U +#define ISP_DIGITAL_GAIN_R_SHIFT 16U +#define ISP_DIGITAL_GAIN_B +#define ISP_DIGITAL_GAIN_B_MASK 0x0000ffffU +#define ISP_DIGITAL_GAIN_B_SHIFT 0U +#define ISP_DIGITAL_GAIN_GR +#define ISP_DIGITAL_GAIN_GR_MASK 0xffff0000U +#define ISP_DIGITAL_GAIN_GR_SHIFT 16U +#define ISP_DIGITAL_GAIN_GB +#define ISP_DIGITAL_GAIN_GB_MASK 0x0000ffffU +#define ISP_DIGITAL_GAIN_GB_SHIFT 0U +/*! Register: isp_vsync_delay: (0x00000730)*/ +/*! Slice: vsync_delya:*/ +#define ISP_VSYNC_DELAY +#define ISP_VSYNC_DELAY_MASK 0x01FFFFFFU +#define ISP_VSYNC_DELAY_SHIFT 0U +/*! Register: isp_vsync_delay: (0x00000730)*/ +/*! Slice: reg_vsync_sel:*/ +#define ISP_VSYNC_DELAY_SEL +#define ISP_VSYNC_DELAY_SEL_MASK 0x80000000U +#define ISP_VSYNC_DELAY_SEL_SHIFT 31U +#define WDR4_DUMMY_BLK +#define WDR4_DUMMY_BLK_MASK (0xffff << 16 ) +#define WDR4_DUMMY_BLK_SHIFT 16U + +#define WDR4_DUMMY_BLK_EN +#define WDR4_DUMMY_BLK_EN_MASK 0x1 << 15 +#define WDR4_DUMMY_BLK_EN_SHIFT 15U + +#define WDR4_SOFT_RESET_FLAG +#define WDR4_SOFT_RESET_FLAG_MASK 0x1 << 1 +#define WDR4_SOFT_RESET_FLAG_SHIFT 1U + +#define WDR4_ENABLE +#define WDR4_ENABLE_MASK 0x1 << 0 +#define WDR4_ENABLE_SHIFT 0U + +#define WDR4_OUTPUT_SHIFT_BIT +#define WDR4_OUTPUT_SHIFT_BIT_MASK (0x3f << 6 ) +#define WDR4_OUTPUT_SHIFT_BIT_SHIFT 6U + +#define WDR4_PIXEL_SHIFT_BIT +#define WDR4_PIXEL_SHIFT_BIT_MASK (0x3f << 0 ) +#define WDR4_PIXEL_SHIFT_BIT_SHIFT 0U + +#define WDR4_BLOCK_HEIGHT +#define WDR4_BLOCK_HEIGHT_MASK (0x1ff << 9 ) +#define WDR4_BLOCK_HEIGHT_SHIFT 9U + +#define WDR4_BLOCK_WIDTH +#define WDR4_BLOCK_WIDTH_MASK (0x1ff << 0 ) +#define WDR4_BLOCK_WIDTH_SHIFT 0U + +#define WDR4_BLOCK_AREA_INVERSE +#define WDR4_BLOCK_AREA_INVERSE_MASK (0xfffff << 0 ) +#define WDR4_BLOCK_AREA_INVERSE_SHIFT 0U + +#define WDR4_VALUE_WEIGHT_3 +#define WDR4_VALUE_WEIGHT_3_MASK (0x1f << 15 ) +#define WDR4_VALUE_WEIGHT_3_SHIFT 15U + +#define WDR4_VALUE_WEIGHT_2 +#define WDR4_VALUE_WEIGHT_2_MASK (0x1f << 10 ) +#define WDR4_VALUE_WEIGHT_2_SHIFT 10U + +#define WDR4_VALUE_WEIGHT_1 +#define WDR4_VALUE_WEIGHT_1_MASK (0x1f << 5 ) +#define WDR4_VALUE_WEIGHT_1_SHIFT 5U + +#define WDR4_VALUE_WEIGHT_0 +#define WDR4_VALUE_WEIGHT_0_MASK (0x1f << 0 ) +#define WDR4_VALUE_WEIGHT_0_SHIFT 0U + +#define WDR4_TOTAL_STRENGTH +#define WDR4_TOTAL_STRENGTH_MASK (0xff << 24 ) +#define WDR4_TOTAL_STRENGTH_SHIFT 24U + +#define WDR4_LOCAL_STRENGTH +#define WDR4_LOCAL_STRENGTH_MASK (0xff << 16 ) +#define WDR4_LOCAL_STRENGTH_SHIFT 16U + +#define WDR4_GLOBAL_STRENGTH +#define WDR4_GLOBAL_STRENGTH_MASK (0xff << 8 ) +#define WDR4_GLOBAL_STRENGTH_SHIFT 8U + +#define WDR4_LOW_STRENGTH +#define WDR4_LOW_STRENGTH_MASK (0xff << 0 ) +#define WDR4_LOW_STRENGTH_SHIFT 0U + +#define WDR4_HIGH_STRENGTH +#define WDR4_HIGH_STRENGTH_MASK (0xff << 16 ) +#define WDR4_HIGH_STRENGTH_SHIFT 16U + +#define WDR4_DRC_BAYER_RATIOLSVS +#define WDR4_DRC_BAYER_RATIOLSVS_MASK (0xff << 8 ) +#define WDR4_DRC_BAYER_RATIOLSVS_SHIFT 8U + +#define WDR4_DRC_BAYER_RATIO +#define WDR4_DRC_BAYER_RATIO_MASK (0xff << 0 ) +#define WDR4_DRC_BAYER_RATIO_SHIFT 0U + +#define WDR4_CONTRAST +#define WDR4_CONTRAST_MASK (0x7ff << 10 ) +#define WDR4_CONTRAST_SHIFT 10U + +#define WDR4_FLAT_STRENGTH +#define WDR4_FLAT_STRENGTH_MASK (0x1f << 5 ) +#define WDR4_FLAT_STRENGTH_SHIFT 5U + +#define WDR4_FLAT_THR +#define WDR4_FLAT_THR_MASK (0x1f << 0 ) +#define WDR4_FLAT_THR_SHIFT 0U + +#define WDR4_PIXEL_MERGE_SLOPE +#define WDR4_PIXEL_MERGE_SLOPE_MASK (0xff << 24 ) +#define WDR4_PIXEL_MERGE_SLOPE_SHIFT 24U + +#define WDR4_PIXEL_MERGE_BASE +#define WDR4_PIXEL_MERGE_BASE_MASK (0xff << 16 ) +#define WDR4_PIXEL_MERGE_BASE_SHIFT 16U + +#define WDR4_PIXEL_ADJUST_SLOPE +#define WDR4_PIXEL_ADJUST_SLOPE_MASK (0xff << 8 ) +#define WDR4_PIXEL_ADJUST_SLOPE_SHIFT 8U + +#define WDR4_PIXEL_ADJUST_BASE +#define WDR4_PIXEL_ADJUST_BASE_MASK (0xff << 0 ) +#define WDR4_PIXEL_ADJUST_BASE_SHIFT 0U + +#define WDR4_ENTROPY_SLOPE +#define WDR4_ENTROPY_SLOPE_MASK (0x3ff << 10 ) +#define WDR4_ENTROPY_SLOPE_SHIFT 10U + +#define WDR4_ENTROPY_BASE +#define WDR4_ENTROPY_BASE_MASK (0x3ff << 0 ) +#define WDR4_ENTROPY_BASE_SHIFT 0U + +#define WDR4_BILITERAL_WIDTH_SIGMA +#define WDR4_BILITERAL_WIDTH_SIGMA_MASK (0xfffff << 0 ) +#define WDR4_BILITERAL_WIDTH_SIGMA_SHIFT 0U + +#define WDR4_BILITERAL_HEIGHT_SIGMA +#define WDR4_BILITERAL_HEIGHT_SIGMA_MASK (0xfffff << 0 ) +#define WDR4_BILITERAL_HEIGHT_SIGMA_SHIFT 0U + +#define WDR4_BILITERAL_VALUE_SIGMA +#define WDR4_BILITERAL_VALUE_SIGMA_MASK (0xfffff << 0 ) +#define WDR4_BILITERAL_VALUE_SIGMA_SHIFT 0U + +#define WDR4_BLOCK_COL_FLAG +#define WDR4_BLOCK_COL_FLAG_MASK (0xffffffff << 0 ) +#define WDR4_BLOCK_COL_FLAG_SHIFT 0U + +#define WDR4_BLOCK_ROW_FLAG +#define WDR4_BLOCK_ROW_FLAG_MASK (0xffffffff << 0 ) +#define WDR4_BLOCK_ROW_FLAG_SHIFT 0U + +#define WDR4_FRAME_AVERAGE +#define WDR4_FRAME_AVERAGE_MASK (0xffffffff << 0 ) +#define WDR4_FRAME_AVERAGE_SHIFT 0U + +#define WDR4_FRAME_STD +#define WDR4_FRAME_STD_MASK (0xffffffff << 0 ) +#define WDR4_FRAME_STD_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE0_0 +#define WDR4_HISTOGRAM_CURVE0_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE0_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE1 +#define WDR4_HISTOGRAM_CURVE1_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE1_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE0_1 +#define WDR4_HISTOGRAM_CURVE0_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE0_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE2 +#define WDR4_HISTOGRAM_CURVE2_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE2_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE3_0 +#define WDR4_HISTOGRAM_CURVE3_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE3_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE4 +#define WDR4_HISTOGRAM_CURVE4_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE4_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE3_1 +#define WDR4_HISTOGRAM_CURVE3_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE3_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE5 +#define WDR4_HISTOGRAM_CURVE5_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE5_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE6_0 +#define WDR4_HISTOGRAM_CURVE6_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE6_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE7 +#define WDR4_HISTOGRAM_CURVE7_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE7_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE6_1 +#define WDR4_HISTOGRAM_CURVE6_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE6_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE8 +#define WDR4_HISTOGRAM_CURVE8_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE8_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE9_0 +#define WDR4_HISTOGRAM_CURVE9_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE9_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE10 +#define WDR4_HISTOGRAM_CURVE10_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE10_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE9_1 +#define WDR4_HISTOGRAM_CURVE9_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE9_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE11 +#define WDR4_HISTOGRAM_CURVE11_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE11_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE12_0 +#define WDR4_HISTOGRAM_CURVE12_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE12_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE13 +#define WDR4_HISTOGRAM_CURVE13_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE13_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE12_1 +#define WDR4_HISTOGRAM_CURVE12_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE12_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE14 +#define WDR4_HISTOGRAM_CURVE14_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE14_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE15_0 +#define WDR4_HISTOGRAM_CURVE15_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE15_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE16 +#define WDR4_HISTOGRAM_CURVE16_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE16_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE15_1 +#define WDR4_HISTOGRAM_CURVE15_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE15_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE17 +#define WDR4_HISTOGRAM_CURVE17_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE17_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE18_0 +#define WDR4_HISTOGRAM_CURVE18_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE18_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE19 +#define WDR4_HISTOGRAM_CURVE19_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE19_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE18_1 +#define WDR4_HISTOGRAM_CURVE18_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE18_1_SHIFT 20U + +#define WDR4_ENTROPY_CONVERT0 +#define WDR4_ENTROPY_CONVERT0_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT0_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT1 +#define WDR4_ENTROPY_CONVERT1_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT1_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT2 +#define WDR4_ENTROPY_CONVERT2_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT2_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT3 +#define WDR4_ENTROPY_CONVERT3_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT3_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT4 +#define WDR4_ENTROPY_CONVERT4_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT4_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT5 +#define WDR4_ENTROPY_CONVERT5_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT5_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT6 +#define WDR4_ENTROPY_CONVERT6_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT6_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT7 +#define WDR4_ENTROPY_CONVERT7_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT7_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT8 +#define WDR4_ENTROPY_CONVERT8_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT8_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT9 +#define WDR4_ENTROPY_CONVERT9_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT9_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT10 +#define WDR4_ENTROPY_CONVERT10_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT10_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT11 +#define WDR4_ENTROPY_CONVERT11_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT11_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT12 +#define WDR4_ENTROPY_CONVERT12_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT12_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT13 +#define WDR4_ENTROPY_CONVERT13_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT13_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT14 +#define WDR4_ENTROPY_CONVERT14_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT14_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT15 +#define WDR4_ENTROPY_CONVERT15_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT15_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT16 +#define WDR4_ENTROPY_CONVERT16_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT16_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT17 +#define WDR4_ENTROPY_CONVERT17_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT17_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT18 +#define WDR4_ENTROPY_CONVERT18_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT18_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT19 +#define WDR4_ENTROPY_CONVERT19_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT19_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE0_0 +#define WDR4_GAMMA_PRE_CURVE0_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE0_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE1 +#define WDR4_GAMMA_PRE_CURVE1_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE1_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE0_1 +#define WDR4_GAMMA_PRE_CURVE0_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE0_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE2 +#define WDR4_GAMMA_PRE_CURVE2_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE2_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE3_0 +#define WDR4_GAMMA_PRE_CURVE3_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE3_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE4 +#define WDR4_GAMMA_PRE_CURVE4_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE4_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE3_1 +#define WDR4_GAMMA_PRE_CURVE3_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE3_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE5 +#define WDR4_GAMMA_PRE_CURVE5_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE5_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE6_0 +#define WDR4_GAMMA_PRE_CURVE6_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE6_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE7 +#define WDR4_GAMMA_PRE_CURVE7_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE7_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE6_1 +#define WDR4_GAMMA_PRE_CURVE6_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE6_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE8 +#define WDR4_GAMMA_PRE_CURVE8_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE8_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE9_0 +#define WDR4_GAMMA_PRE_CURVE9_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE9_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE10 +#define WDR4_GAMMA_PRE_CURVE10_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE10_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE9_1 +#define WDR4_GAMMA_PRE_CURVE9_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE9_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE11 +#define WDR4_GAMMA_PRE_CURVE11_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE11_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE12_0 +#define WDR4_GAMMA_PRE_CURVE12_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE12_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE13 +#define WDR4_GAMMA_PRE_CURVE13_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE13_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE12_1 +#define WDR4_GAMMA_PRE_CURVE12_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE12_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE14 +#define WDR4_GAMMA_PRE_CURVE14_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE14_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE15_0 +#define WDR4_GAMMA_PRE_CURVE15_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE15_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE16 +#define WDR4_GAMMA_PRE_CURVE16_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE16_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE15_1 +#define WDR4_GAMMA_PRE_CURVE15_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE15_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE17 +#define WDR4_GAMMA_PRE_CURVE17_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE17_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE18_0 +#define WDR4_GAMMA_PRE_CURVE18_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE18_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE19 +#define WDR4_GAMMA_PRE_CURVE19_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE19_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE18_1 +#define WDR4_GAMMA_PRE_CURVE18_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE18_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE0_0 +#define WDR4_GAMMA_UP_CURVE0_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE0_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE1 +#define WDR4_GAMMA_UP_CURVE1_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE1_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE0_1 +#define WDR4_GAMMA_UP_CURVE0_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE0_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE2 +#define WDR4_GAMMA_UP_CURVE2_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE2_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE3_0 +#define WDR4_GAMMA_UP_CURVE3_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE3_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE4 +#define WDR4_GAMMA_UP_CURVE4_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE4_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE3_1 +#define WDR4_GAMMA_UP_CURVE3_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE3_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE5 +#define WDR4_GAMMA_UP_CURVE5_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE5_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE6_0 +#define WDR4_GAMMA_UP_CURVE6_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE6_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE7 +#define WDR4_GAMMA_UP_CURVE7_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE7_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE6_1 +#define WDR4_GAMMA_UP_CURVE6_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE6_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE8 +#define WDR4_GAMMA_UP_CURVE8_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE8_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE9_0 +#define WDR4_GAMMA_UP_CURVE9_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE9_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE10 +#define WDR4_GAMMA_UP_CURVE10_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE10_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE9_1 +#define WDR4_GAMMA_UP_CURVE9_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE9_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE11 +#define WDR4_GAMMA_UP_CURVE11_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE11_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE12_0 +#define WDR4_GAMMA_UP_CURVE12_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE12_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE13 +#define WDR4_GAMMA_UP_CURVE13_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE13_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE12_1 +#define WDR4_GAMMA_UP_CURVE12_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE12_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE14 +#define WDR4_GAMMA_UP_CURVE14_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE14_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE15_0 +#define WDR4_GAMMA_UP_CURVE15_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE15_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE16 +#define WDR4_GAMMA_UP_CURVE16_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE16_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE15_1 +#define WDR4_GAMMA_UP_CURVE15_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE15_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE17 +#define WDR4_GAMMA_UP_CURVE17_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE17_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE18_0 +#define WDR4_GAMMA_UP_CURVE18_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE18_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE19 +#define WDR4_GAMMA_UP_CURVE19_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE19_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE18_1 +#define WDR4_GAMMA_UP_CURVE18_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE18_1_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE0 +#define WDR4_GAMMA_DOWN_CURVE0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE0_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE1 +#define WDR4_GAMMA_DOWN_CURVE1_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE1_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE2 +#define WDR4_GAMMA_DOWN_CURVE2_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE2_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE3 +#define WDR4_GAMMA_DOWN_CURVE3_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE3_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE4 +#define WDR4_GAMMA_DOWN_CURVE4_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE4_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE5 +#define WDR4_GAMMA_DOWN_CURVE5_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE5_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE6 +#define WDR4_GAMMA_DOWN_CURVE6_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE6_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE7 +#define WDR4_GAMMA_DOWN_CURVE7_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE7_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE8 +#define WDR4_GAMMA_DOWN_CURVE8_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE8_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE9 +#define WDR4_GAMMA_DOWN_CURVE9_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE9_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE10 +#define WDR4_GAMMA_DOWN_CURVE10_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE10_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE11 +#define WDR4_GAMMA_DOWN_CURVE11_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE11_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE12 +#define WDR4_GAMMA_DOWN_CURVE12_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE12_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE13 +#define WDR4_GAMMA_DOWN_CURVE13_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE13_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE14 +#define WDR4_GAMMA_DOWN_CURVE14_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE14_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE15 +#define WDR4_GAMMA_DOWN_CURVE15_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE15_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE16 +#define WDR4_GAMMA_DOWN_CURVE16_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE16_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE17 +#define WDR4_GAMMA_DOWN_CURVE17_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE17_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE18 +#define WDR4_GAMMA_DOWN_CURVE18_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE18_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE19 +#define WDR4_GAMMA_DOWN_CURVE19_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE19_SHIFT 0U + +#define WDR4_DISTANCE_WEIGHT_CURVE0 +#define WDR4_DISTANCE_WEIGHT_CURVE0_MASK (0x7f << 21 ) +#define WDR4_DISTANCE_WEIGHT_CURVE0_SHIFT 21U + +#define WDR4_DISTANCE_WEIGHT_CURVE1 +#define WDR4_DISTANCE_WEIGHT_CURVE1_MASK (0x7f << 14 ) +#define WDR4_DISTANCE_WEIGHT_CURVE1_SHIFT 14U + +#define WDR4_DISTANCE_WEIGHT_CURVE2 +#define WDR4_DISTANCE_WEIGHT_CURVE2_MASK (0x7f << 7 ) +#define WDR4_DISTANCE_WEIGHT_CURVE2_SHIFT 7U + +#define WDR4_DISTANCE_WEIGHT_CURVE3 +#define WDR4_DISTANCE_WEIGHT_CURVE3_MASK (0x7f << 0 ) +#define WDR4_DISTANCE_WEIGHT_CURVE3_SHIFT 0U + +#define WDR4_DISTANCE_WEIGHT_CURVE4 +#define WDR4_DISTANCE_WEIGHT_CURVE4_MASK (0x7f << 21 ) +#define WDR4_DISTANCE_WEIGHT_CURVE4_SHIFT 21U + +#define WDR4_DISTANCE_WEIGHT_CURVE5 +#define WDR4_DISTANCE_WEIGHT_CURVE5_MASK (0x7f << 14 ) +#define WDR4_DISTANCE_WEIGHT_CURVE5_SHIFT 14U + +#define WDR4_DISTANCE_WEIGHT_CURVE6 +#define WDR4_DISTANCE_WEIGHT_CURVE6_MASK (0x7f << 7 ) +#define WDR4_DISTANCE_WEIGHT_CURVE6_SHIFT 7U + +#define WDR4_DISTANCE_WEIGHT_CURVE7 +#define WDR4_DISTANCE_WEIGHT_CURVE7_MASK (0x7f << 0 ) +#define WDR4_DISTANCE_WEIGHT_CURVE7_SHIFT 0U + +#define WDR4_DISTANCE_WEIGHT_CURVE8 +#define WDR4_DISTANCE_WEIGHT_CURVE8_MASK (0x7f << 21 ) +#define WDR4_DISTANCE_WEIGHT_CURVE8_SHIFT 21U + +#define WDR4_DISTANCE_WEIGHT_CURVE9 +#define WDR4_DISTANCE_WEIGHT_CURVE9_MASK (0x7f << 14 ) +#define WDR4_DISTANCE_WEIGHT_CURVE9_SHIFT 14U + +#define WDR4_DISTANCE_WEIGHT_CURVE10 +#define WDR4_DISTANCE_WEIGHT_CURVE10_MASK (0x7f << 7 ) +#define WDR4_DISTANCE_WEIGHT_CURVE10_SHIFT 7U + +#define WDR4_DISTANCE_WEIGHT_CURVE11 +#define WDR4_DISTANCE_WEIGHT_CURVE11_MASK (0x7f << 0 ) +#define WDR4_DISTANCE_WEIGHT_CURVE11_SHIFT 0U + +#define WDR4_DISTANCE_WEIGHT_CURVE12 +#define WDR4_DISTANCE_WEIGHT_CURVE12_MASK (0x7f << 21 ) +#define WDR4_DISTANCE_WEIGHT_CURVE12_SHIFT 21U + +#define WDR4_DISTANCE_WEIGHT_CURVE13 +#define WDR4_DISTANCE_WEIGHT_CURVE13_MASK (0x7f << 14 ) +#define WDR4_DISTANCE_WEIGHT_CURVE13_SHIFT 14U + +#define WDR4_DISTANCE_WEIGHT_CURVE14 +#define WDR4_DISTANCE_WEIGHT_CURVE14_MASK (0x7f << 7 ) +#define WDR4_DISTANCE_WEIGHT_CURVE14_SHIFT 7U + +#define WDR4_DISTANCE_WEIGHT_CURVE15 +#define WDR4_DISTANCE_WEIGHT_CURVE15_MASK (0x7f << 0 ) +#define WDR4_DISTANCE_WEIGHT_CURVE15_SHIFT 0U + +#define WDR4_DISTANCE_WEIGHT_CURVE16 +#define WDR4_DISTANCE_WEIGHT_CURVE16_MASK (0x7f << 21 ) +#define WDR4_DISTANCE_WEIGHT_CURVE16_SHIFT 21U + +#define WDR4_DISTANCE_WEIGHT_CURVE17 +#define WDR4_DISTANCE_WEIGHT_CURVE17_MASK (0x7f << 14 ) +#define WDR4_DISTANCE_WEIGHT_CURVE17_SHIFT 14U + +#define WDR4_DISTANCE_WEIGHT_CURVE18 +#define WDR4_DISTANCE_WEIGHT_CURVE18_MASK (0x7f << 7 ) +#define WDR4_DISTANCE_WEIGHT_CURVE18_SHIFT 7U + +#define WDR4_DISTANCE_WEIGHT_CURVE19 +#define WDR4_DISTANCE_WEIGHT_CURVE19_MASK (0x7f << 0 ) +#define WDR4_DISTANCE_WEIGHT_CURVE19_SHIFT 0U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE0 +#define WDR4_DIFFERENCE_WEIGHT_CURVE0_MASK (0x7f << 21 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE0_SHIFT 21U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE1 +#define WDR4_DIFFERENCE_WEIGHT_CURVE1_MASK (0x7f << 14 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE1_SHIFT 14U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE2 +#define WDR4_DIFFERENCE_WEIGHT_CURVE2_MASK (0x7f << 7 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE2_SHIFT 7U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE3 +#define WDR4_DIFFERENCE_WEIGHT_CURVE3_MASK (0x7f << 0 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE3_SHIFT 0U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE4 +#define WDR4_DIFFERENCE_WEIGHT_CURVE4_MASK (0x7f << 21 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE4_SHIFT 21U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE5 +#define WDR4_DIFFERENCE_WEIGHT_CURVE5_MASK (0x7f << 14 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE5_SHIFT 14U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE6 +#define WDR4_DIFFERENCE_WEIGHT_CURVE6_MASK (0x7f << 7 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE6_SHIFT 7U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE7 +#define WDR4_DIFFERENCE_WEIGHT_CURVE7_MASK (0x7f << 0 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE7_SHIFT 0U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE8 +#define WDR4_DIFFERENCE_WEIGHT_CURVE8_MASK (0x7f << 21 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE8_SHIFT 21U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE9 +#define WDR4_DIFFERENCE_WEIGHT_CURVE9_MASK (0x7f << 14 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE9_SHIFT 14U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE10 +#define WDR4_DIFFERENCE_WEIGHT_CURVE10_MASK (0x7f << 7 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE10_SHIFT 7U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE11 +#define WDR4_DIFFERENCE_WEIGHT_CURVE11_MASK (0x7f << 0 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE11_SHIFT 0U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE12 +#define WDR4_DIFFERENCE_WEIGHT_CURVE12_MASK (0x7f << 21 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE12_SHIFT 21U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE13 +#define WDR4_DIFFERENCE_WEIGHT_CURVE13_MASK (0x7f << 14 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE13_SHIFT 14U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE14 +#define WDR4_DIFFERENCE_WEIGHT_CURVE14_MASK (0x7f << 7 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE14_SHIFT 7U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE15 +#define WDR4_DIFFERENCE_WEIGHT_CURVE15_MASK (0x7f << 0 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE15_SHIFT 0U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE16 +#define WDR4_DIFFERENCE_WEIGHT_CURVE16_MASK (0x7f << 21 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE16_SHIFT 21U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE17 +#define WDR4_DIFFERENCE_WEIGHT_CURVE17_MASK (0x7f << 14 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE17_SHIFT 14U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE18 +#define WDR4_DIFFERENCE_WEIGHT_CURVE18_MASK (0x7f << 7 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE18_SHIFT 7U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE19 +#define WDR4_DIFFERENCE_WEIGHT_CURVE19_MASK (0x7f << 0 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE19_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT0 +#define WDR4_GLOBAL_CURVE_INVERT0_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT0_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT1 +#define WDR4_GLOBAL_CURVE_INVERT1_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT1_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT2 +#define WDR4_GLOBAL_CURVE_INVERT2_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT2_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT3 +#define WDR4_GLOBAL_CURVE_INVERT3_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT3_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT4 +#define WDR4_GLOBAL_CURVE_INVERT4_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT4_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT5 +#define WDR4_GLOBAL_CURVE_INVERT5_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT5_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT6 +#define WDR4_GLOBAL_CURVE_INVERT6_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT6_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT7 +#define WDR4_GLOBAL_CURVE_INVERT7_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT7_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT8 +#define WDR4_GLOBAL_CURVE_INVERT8_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT8_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT9 +#define WDR4_GLOBAL_CURVE_INVERT9_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT9_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT10 +#define WDR4_GLOBAL_CURVE_INVERT10_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT10_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT11 +#define WDR4_GLOBAL_CURVE_INVERT11_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT11_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT12 +#define WDR4_GLOBAL_CURVE_INVERT12_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT12_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT13 +#define WDR4_GLOBAL_CURVE_INVERT13_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT13_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT14 +#define WDR4_GLOBAL_CURVE_INVERT14_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT14_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT15 +#define WDR4_GLOBAL_CURVE_INVERT15_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT15_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT16 +#define WDR4_GLOBAL_CURVE_INVERT16_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT16_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT17 +#define WDR4_GLOBAL_CURVE_INVERT17_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT17_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT18 +#define WDR4_GLOBAL_CURVE_INVERT18_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT18_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT19 +#define WDR4_GLOBAL_CURVE_INVERT19_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT19_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT0_0 +#define WDR4_LINEAR_CURVE_INVERT0_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT0_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT1 +#define WDR4_LINEAR_CURVE_INVERT1_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT1_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT0_1 +#define WDR4_LINEAR_CURVE_INVERT0_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT0_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT2 +#define WDR4_LINEAR_CURVE_INVERT2_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT2_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT3_0 +#define WDR4_LINEAR_CURVE_INVERT3_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT3_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT4 +#define WDR4_LINEAR_CURVE_INVERT4_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT4_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT3_1 +#define WDR4_LINEAR_CURVE_INVERT3_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT3_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT5 +#define WDR4_LINEAR_CURVE_INVERT5_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT5_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT6_0 +#define WDR4_LINEAR_CURVE_INVERT6_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT6_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT7 +#define WDR4_LINEAR_CURVE_INVERT7_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT7_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT6_1 +#define WDR4_LINEAR_CURVE_INVERT6_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT6_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT8 +#define WDR4_LINEAR_CURVE_INVERT8_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT8_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT9_0 +#define WDR4_LINEAR_CURVE_INVERT9_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT9_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT10 +#define WDR4_LINEAR_CURVE_INVERT10_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT10_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT9_1 +#define WDR4_LINEAR_CURVE_INVERT9_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT9_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT11 +#define WDR4_LINEAR_CURVE_INVERT11_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT11_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT12_0 +#define WDR4_LINEAR_CURVE_INVERT12_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT12_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT13 +#define WDR4_LINEAR_CURVE_INVERT13_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT13_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT12_1 +#define WDR4_LINEAR_CURVE_INVERT12_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT12_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT14 +#define WDR4_LINEAR_CURVE_INVERT14_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT14_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT15_0 +#define WDR4_LINEAR_CURVE_INVERT15_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT15_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT16 +#define WDR4_LINEAR_CURVE_INVERT16_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT16_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT15_1 +#define WDR4_LINEAR_CURVE_INVERT15_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT15_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT17 +#define WDR4_LINEAR_CURVE_INVERT17_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT17_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT18_0 +#define WDR4_LINEAR_CURVE_INVERT18_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT18_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT19 +#define WDR4_LINEAR_CURVE_INVERT19_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT19_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT18_1 +#define WDR4_LINEAR_CURVE_INVERT18_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT18_1_SHIFT 18U + +#define WDR4_SMOOTH_INVERT_CURVE0 +#define WDR4_SMOOTH_INVERT_CURVE0_MASK (0xff << 24 ) +#define WDR4_SMOOTH_INVERT_CURVE0_SHIFT 24U + +#define WDR4_SMOOTH_INVERT_CURVE1 +#define WDR4_SMOOTH_INVERT_CURVE1_MASK (0xff << 16 ) +#define WDR4_SMOOTH_INVERT_CURVE1_SHIFT 16U + +#define WDR4_SMOOTH_INVERT_CURVE2 +#define WDR4_SMOOTH_INVERT_CURVE2_MASK (0xff << 8 ) +#define WDR4_SMOOTH_INVERT_CURVE2_SHIFT 8U + +#define WDR4_SMOOTH_INVERT_CURVE3 +#define WDR4_SMOOTH_INVERT_CURVE3_MASK (0xff << 0 ) +#define WDR4_SMOOTH_INVERT_CURVE3_SHIFT 0U + +#define WDR4_SMOOTH_INVERT_CURVE4 +#define WDR4_SMOOTH_INVERT_CURVE4_MASK (0xff << 24 ) +#define WDR4_SMOOTH_INVERT_CURVE4_SHIFT 24U + +#define WDR4_SMOOTH_INVERT_CURVE5 +#define WDR4_SMOOTH_INVERT_CURVE5_MASK (0xff << 16 ) +#define WDR4_SMOOTH_INVERT_CURVE5_SHIFT 16U + +#define WDR4_SMOOTH_INVERT_CURVE6 +#define WDR4_SMOOTH_INVERT_CURVE6_MASK (0xff << 8 ) +#define WDR4_SMOOTH_INVERT_CURVE6_SHIFT 8U + +#define WDR4_SMOOTH_INVERT_CURVE7 +#define WDR4_SMOOTH_INVERT_CURVE7_MASK (0xff << 0 ) +#define WDR4_SMOOTH_INVERT_CURVE7_SHIFT 0U + +#define WDR4_SMOOTH_INVERT_CURVE8 +#define WDR4_SMOOTH_INVERT_CURVE8_MASK (0xff << 24 ) +#define WDR4_SMOOTH_INVERT_CURVE8_SHIFT 24U + +#define WDR4_SMOOTH_INVERT_CURVE9 +#define WDR4_SMOOTH_INVERT_CURVE9_MASK (0xff << 16 ) +#define WDR4_SMOOTH_INVERT_CURVE9_SHIFT 16U + +#define WDR4_SMOOTH_INVERT_CURVE10 +#define WDR4_SMOOTH_INVERT_CURVE10_MASK (0xff << 8 ) +#define WDR4_SMOOTH_INVERT_CURVE10_SHIFT 8U + +#define WDR4_SMOOTH_INVERT_CURVE11 +#define WDR4_SMOOTH_INVERT_CURVE11_MASK (0xff << 0 ) +#define WDR4_SMOOTH_INVERT_CURVE11_SHIFT 0U + +#define WDR4_SMOOTH_INVERT_CURVE12 +#define WDR4_SMOOTH_INVERT_CURVE12_MASK (0xff << 24 ) +#define WDR4_SMOOTH_INVERT_CURVE12_SHIFT 24U + +#define WDR4_SMOOTH_INVERT_CURVE13 +#define WDR4_SMOOTH_INVERT_CURVE13_MASK (0xff << 16 ) +#define WDR4_SMOOTH_INVERT_CURVE13_SHIFT 16U + +#define WDR4_SMOOTH_INVERT_CURVE14 +#define WDR4_SMOOTH_INVERT_CURVE14_MASK (0xff << 8 ) +#define WDR4_SMOOTH_INVERT_CURVE14_SHIFT 8U + +#define WDR4_SMOOTH_INVERT_CURVE15 +#define WDR4_SMOOTH_INVERT_CURVE15_MASK (0xff << 0 ) +#define WDR4_SMOOTH_INVERT_CURVE15_SHIFT 0U + +#define WDR4_SMOOTH_INVERT_CURVE16 +#define WDR4_SMOOTH_INVERT_CURVE16_MASK (0xff << 24 ) +#define WDR4_SMOOTH_INVERT_CURVE16_SHIFT 24U + +#define WDR4_SMOOTH_INVERT_CURVE17 +#define WDR4_SMOOTH_INVERT_CURVE17_MASK (0xff << 16 ) +#define WDR4_SMOOTH_INVERT_CURVE17_SHIFT 16U + +#define WDR4_SMOOTH_INVERT_CURVE18 +#define WDR4_SMOOTH_INVERT_CURVE18_MASK (0xff << 8 ) +#define WDR4_SMOOTH_INVERT_CURVE18_SHIFT 8U + +#define WDR4_SMOOTH_INVERT_CURVE19 +#define WDR4_SMOOTH_INVERT_CURVE19_MASK (0xff << 0 ) +#define WDR4_SMOOTH_INVERT_CURVE19_SHIFT 0U + +#define WDR4_HISTOGRAM_SHIFT0 +#define WDR4_HISTOGRAM_SHIFT0_MASK (0x1f << 25 ) +#define WDR4_HISTOGRAM_SHIFT0_SHIFT 25U + +#define WDR4_HISTOGRAM_SHIFT1 +#define WDR4_HISTOGRAM_SHIFT1_MASK (0x1f << 20 ) +#define WDR4_HISTOGRAM_SHIFT1_SHIFT 20U + +#define WDR4_HISTOGRAM_SHIFT2 +#define WDR4_HISTOGRAM_SHIFT2_MASK (0x1f << 15 ) +#define WDR4_HISTOGRAM_SHIFT2_SHIFT 15U + +#define WDR4_HISTOGRAM_SHIFT3 +#define WDR4_HISTOGRAM_SHIFT3_MASK (0x1f << 10 ) +#define WDR4_HISTOGRAM_SHIFT3_SHIFT 10U + +#define WDR4_HISTOGRAM_SHIFT4 +#define WDR4_HISTOGRAM_SHIFT4_MASK (0x1f << 5 ) +#define WDR4_HISTOGRAM_SHIFT4_SHIFT 5U + +#define WDR4_HISTOGRAM_SHIFT5 +#define WDR4_HISTOGRAM_SHIFT5_MASK (0x1f << 0 ) +#define WDR4_HISTOGRAM_SHIFT5_SHIFT 0U + +#define WDR4_HISTOGRAM_SHIFT6 +#define WDR4_HISTOGRAM_SHIFT6_MASK (0x1f << 25 ) +#define WDR4_HISTOGRAM_SHIFT6_SHIFT 25U + +#define WDR4_HISTOGRAM_SHIFT7 +#define WDR4_HISTOGRAM_SHIFT7_MASK (0x1f << 20 ) +#define WDR4_HISTOGRAM_SHIFT7_SHIFT 20U + +#define WDR4_HISTOGRAM_SHIFT8 +#define WDR4_HISTOGRAM_SHIFT8_MASK (0x1f << 15 ) +#define WDR4_HISTOGRAM_SHIFT8_SHIFT 15U + +#define WDR4_HISTOGRAM_SHIFT9 +#define WDR4_HISTOGRAM_SHIFT9_MASK (0x1f << 10 ) +#define WDR4_HISTOGRAM_SHIFT9_SHIFT 10U + +#define WDR4_HISTOGRAM_SHIFT10 +#define WDR4_HISTOGRAM_SHIFT10_MASK (0x1f << 5 ) +#define WDR4_HISTOGRAM_SHIFT10_SHIFT 5U + +#define WDR4_HISTOGRAM_SHIFT11 +#define WDR4_HISTOGRAM_SHIFT11_MASK (0x1f << 0 ) +#define WDR4_HISTOGRAM_SHIFT11_SHIFT 0U + +#define WDR4_HISTOGRAM_SHIFT12 +#define WDR4_HISTOGRAM_SHIFT12_MASK (0x1f << 25 ) +#define WDR4_HISTOGRAM_SHIFT12_SHIFT 25U + +#define WDR4_HISTOGRAM_SHIFT13 +#define WDR4_HISTOGRAM_SHIFT13_MASK (0x1f << 20 ) +#define WDR4_HISTOGRAM_SHIFT13_SHIFT 20U + +#define WDR4_HISTOGRAM_SHIFT14 +#define WDR4_HISTOGRAM_SHIFT14_MASK (0x1f << 15 ) +#define WDR4_HISTOGRAM_SHIFT14_SHIFT 15U + +#define WDR4_HISTOGRAM_SHIFT15 +#define WDR4_HISTOGRAM_SHIFT15_MASK (0x1f << 10 ) +#define WDR4_HISTOGRAM_SHIFT15_SHIFT 10U + +#define WDR4_HISTOGRAM_SHIFT16 +#define WDR4_HISTOGRAM_SHIFT16_MASK (0x1f << 5 ) +#define WDR4_HISTOGRAM_SHIFT16_SHIFT 5U + +#define WDR4_HISTOGRAM_SHIFT17 +#define WDR4_HISTOGRAM_SHIFT17_MASK (0x1f << 0 ) +#define WDR4_HISTOGRAM_SHIFT17_SHIFT 0U + +#define WDR4_HISTOGRAM_SHIFT18 +#define WDR4_HISTOGRAM_SHIFT18_MASK (0x1f << 5 ) +#define WDR4_HISTOGRAM_SHIFT18_SHIFT 5U + +#define WDR4_HISTOGRAM_SHIFT19 +#define WDR4_HISTOGRAM_SHIFT19_MASK (0x1f << 0 ) +#define WDR4_HISTOGRAM_SHIFT19_SHIFT 0U + +#define WDR4_HISTOGRAM0_SHIFT0 +#define WDR4_HISTOGRAM0_SHIFT0_MASK (0xf << 28 ) +#define WDR4_HISTOGRAM0_SHIFT0_SHIFT 28U + +#define WDR4_HISTOGRAM0_SHIFT1 +#define WDR4_HISTOGRAM0_SHIFT1_MASK (0xf << 24 ) +#define WDR4_HISTOGRAM0_SHIFT1_SHIFT 24U + +#define WDR4_HISTOGRAM0_SHIFT2 +#define WDR4_HISTOGRAM0_SHIFT2_MASK (0xf << 20 ) +#define WDR4_HISTOGRAM0_SHIFT2_SHIFT 20U + +#define WDR4_HISTOGRAM0_SHIFT3 +#define WDR4_HISTOGRAM0_SHIFT3_MASK (0xf << 16 ) +#define WDR4_HISTOGRAM0_SHIFT3_SHIFT 16U + +#define WDR4_HISTOGRAM0_SHIFT4 +#define WDR4_HISTOGRAM0_SHIFT4_MASK (0xf << 12 ) +#define WDR4_HISTOGRAM0_SHIFT4_SHIFT 12U + +#define WDR4_HISTOGRAM0_SHIFT5 +#define WDR4_HISTOGRAM0_SHIFT5_MASK (0xf << 8 ) +#define WDR4_HISTOGRAM0_SHIFT5_SHIFT 8U + +#define WDR4_HISTOGRAM0_SHIFT6 +#define WDR4_HISTOGRAM0_SHIFT6_MASK (0xf << 4 ) +#define WDR4_HISTOGRAM0_SHIFT6_SHIFT 4U + +#define WDR4_HISTOGRAM0_SHIFT7 +#define WDR4_HISTOGRAM0_SHIFT7_MASK (0xf << 0 ) +#define WDR4_HISTOGRAM0_SHIFT7_SHIFT 0U + +#define WDR4_HISTOGRAM0_SHIFT8 +#define WDR4_HISTOGRAM0_SHIFT8_MASK (0xf << 28 ) +#define WDR4_HISTOGRAM0_SHIFT8_SHIFT 28U + +#define WDR4_HISTOGRAM0_SHIFT9 +#define WDR4_HISTOGRAM0_SHIFT9_MASK (0xf << 24 ) +#define WDR4_HISTOGRAM0_SHIFT9_SHIFT 24U + +#define WDR4_HISTOGRAM0_SHIFT10 +#define WDR4_HISTOGRAM0_SHIFT10_MASK (0xf << 20 ) +#define WDR4_HISTOGRAM0_SHIFT10_SHIFT 20U + +#define WDR4_HISTOGRAM0_SHIFT11 +#define WDR4_HISTOGRAM0_SHIFT11_MASK (0xf << 16 ) +#define WDR4_HISTOGRAM0_SHIFT11_SHIFT 16U + +#define WDR4_HISTOGRAM0_SHIFT12 +#define WDR4_HISTOGRAM0_SHIFT12_MASK (0xf << 12 ) +#define WDR4_HISTOGRAM0_SHIFT12_SHIFT 12U + +#define WDR4_HISTOGRAM0_SHIFT13 +#define WDR4_HISTOGRAM0_SHIFT13_MASK (0xf << 8 ) +#define WDR4_HISTOGRAM0_SHIFT13_SHIFT 8U + +#define WDR4_HISTOGRAM0_SHIFT14 +#define WDR4_HISTOGRAM0_SHIFT14_MASK (0xf << 4 ) +#define WDR4_HISTOGRAM0_SHIFT14_SHIFT 4U + +#define WDR4_HISTOGRAM0_SHIFT15 +#define WDR4_HISTOGRAM0_SHIFT15_MASK (0xf << 0 ) +#define WDR4_HISTOGRAM0_SHIFT15_SHIFT 0U + +#define WDR4_HISTOGRAM0_SHIFT16 +#define WDR4_HISTOGRAM0_SHIFT16_MASK (0xf << 12 ) +#define WDR4_HISTOGRAM0_SHIFT16_SHIFT 12U + +#define WDR4_HISTOGRAM0_SHIFT17 +#define WDR4_HISTOGRAM0_SHIFT17_MASK (0xf << 8 ) +#define WDR4_HISTOGRAM0_SHIFT17_SHIFT 8U + +#define WDR4_HISTOGRAM0_SHIFT18 +#define WDR4_HISTOGRAM0_SHIFT18_MASK (0xf << 4 ) +#define WDR4_HISTOGRAM0_SHIFT18_SHIFT 4U + +#define WDR4_HISTOGRAM0_SHIFT19 +#define WDR4_HISTOGRAM0_SHIFT19_MASK (0xf << 0 ) +#define WDR4_HISTOGRAM0_SHIFT19_SHIFT 0U + +#define WDR4_TOTAL_STRENGTH_SHD +#define WDR4_TOTAL_STRENGTH_SHD_MASK (0xff << 24 ) +#define WDR4_TOTAL_STRENGTH_SHD_SHIFT 24U + +#define WDR4_LOCAL_STRENGTH_SHD +#define WDR4_LOCAL_STRENGTH_SHD_MASK (0xff << 16 ) +#define WDR4_LOCAL_STRENGTH_SHD_SHIFT 16U + +#define WDR4_GLOBAL_STRENGTH_SHD +#define WDR4_GLOBAL_STRENGTH_SHD_MASK (0xff << 8 ) +#define WDR4_GLOBAL_STRENGTH_SHD_SHIFT 8U + +#define WDR4_LOW_STRENGTH_SHD +#define WDR4_LOW_STRENGTH_SHD_MASK (0xff << 0 ) +#define WDR4_LOW_STRENGTH_SHD_SHIFT 0U + +#define WDR4_HIGH_STRENGTH_SHD +#define WDR4_HIGH_STRENGTH_SHD_MASK (0xff << 16 ) +#define WDR4_HIGH_STRENGTH_SHD_SHIFT 16U + +#define WDR4_DRC_BAYER_RATIOLSVS_SHD +#define WDR4_DRC_BAYER_RATIOLSVS_SHD_MASK (0xff << 8 ) +#define WDR4_DRC_BAYER_RATIOLSVS_SHD_SHIFT 8U + +#define WDR4_DRC_BAYER_RATIO_SHD +#define WDR4_DRC_BAYER_RATIO_SHD_MASK (0xff << 0 ) +#define WDR4_DRC_BAYER_RATIO_SHD_SHIFT 0U + +#define WDR4_CONTRAST_SHD +#define WDR4_CONTRAST_SHD_MASK (0x7ff << 10 ) +#define WDR4_CONTRAST_SHD_SHIFT 10U + +#define WDR4_FLAT_STRENGTH_SHD +#define WDR4_FLAT_STRENGTH_SHD_MASK (0x1f << 5 ) +#define WDR4_FLAT_STRENGTH_SHD_SHIFT 5U + +#define WDR4_FLAT_THR_SHD +#define WDR4_FLAT_THR_SHD_MASK (0x1f << 0 ) +#define WDR4_FLAT_THR_SHD_SHIFT 0U + +#define WDR4_PIXEL_MERGE_SLOPE_SHD +#define WDR4_PIXEL_MERGE_SLOPE_SHD_MASK (0xff << 24 ) +#define WDR4_PIXEL_MERGE_SLOPE_SHD_SHIFT 24U + +#define WDR4_PIXEL_MERGE_BASE_SHD +#define WDR4_PIXEL_MERGE_BASE_SHD_MASK (0xff << 16 ) +#define WDR4_PIXEL_MERGE_BASE_SHD_SHIFT 16U + +#define WDR4_PIXEL_ADJUST_SLOPE_SHD +#define WDR4_PIXEL_ADJUST_SLOPE_SHD_MASK (0xff << 8 ) +#define WDR4_PIXEL_ADJUST_SLOPE_SHD_SHIFT 8U + +#define WDR4_PIXEL_ADJUST_BASE_SHD +#define WDR4_PIXEL_ADJUST_BASE_SHD_MASK (0xff << 0 ) +#define WDR4_PIXEL_ADJUST_BASE_SHD_SHIFT 0U + +#define WDR4_ENABLE_SHD +#define WDR4_ENABLE_SHD_MASK 0x1 << 20 +#define WDR4_ENABLE_SHD_SHIFT 20U + +#define WDR4_ENTROPY_SLOPE_SHD +#define WDR4_ENTROPY_SLOPE_SHD_MASK (0x3ff << 10 ) +#define WDR4_ENTROPY_SLOPE_SHD_SHIFT 10U + +#define WDR4_ENTROPY_BASE_SHD +#define WDR4_ENTROPY_BASE_SHD_MASK (0x3ff << 0 ) +#define WDR4_ENTROPY_BASE_SHD_SHIFT 0U + +#define DENOISE3D_V20_INVGAMMA_EN +#define DENOISE3D_V20_INVGAMMA_EN_MASK (0x1 << 11) +#define DENOISE3D_V20_INVGAMMA_EN_SHIFT 11U + +#define DENOISE3D_V20_PREGAMMA_EN +#define DENOISE3D_V20_PREGAMMA_EN_MASK (0x1 << 10) +#define DENOISE3D_V20_PREGAMMA_EN_SHIFT 10U + +#define DENOISE3D_V20_ERODE_EN +#define DENOISE3D_V20_ERODE_EN_MASK (0x1 << 9) +#define DENOISE3D_V20_ERODE_EN_SHIFT 9U + +#define DENOISE3D_V20_MOTION_CONV_EN +#define DENOISE3D_V20_MOTION_CONV_EN_MASK (0x1 << 8) +#define DENOISE3D_V20_MOTION_CONV_EN_SHIFT 8U + +#define DENOISE3D_V20_INV_DGAIN_EN +#define DENOISE3D_V20_INV_DGAIN_EN_MASK (0x1 << 7) +#define DENOISE3D_V20_INV_DGAIN_EN_SHIFT 7U + +#define DENOISE3D_V20_INV_AWB_GAIN_EN +#define DENOISE3D_V20_INV_AWB_GAIN_EN_MASK (0x1 << 6) +#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHIFT 6U + +#define DENOISE3D_V20_COMP_LUMA_EN +#define DENOISE3D_V20_COMP_LUMA_EN_MASK (0x1 << 5) +#define DENOISE3D_V20_COMP_LUMA_EN_SHIFT 5U + +#define DENOISE3D_V20_REF_RESET +#define DENOISE3D_V20_REF_RESET_MASK (0x1 << 4) +#define DENOISE3D_V20_REF_RESET_SHIFT 4U + +#define DENOISE3D_V20_MOTION_DILATE_ENABLE +#define DENOISE3D_V20_MOTION_DILATE_ENABLE_MASK (0x1 << 3) +#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHIFT 3U + +#define DENOISE3D_V20_NLM_ENABLE +#define DENOISE3D_V20_NLM_ENABLE_MASK (0x1 << 2) +#define DENOISE3D_V20_NLM_ENABLE_SHIFT 2U + +#define DENOISE3D_V20_TNR_ENABLE +#define DENOISE3D_V20_TNR_ENABLE_MASK (0x1 << 1) +#define DENOISE3D_V20_TNR_ENABLE_SHIFT 1U + +#define DENOISE3D_V20_ENABLE +#define DENOISE3D_V20_ENABLE_MASK (0x1 << 0) +#define DENOISE3D_V20_ENABLE_SHIFT 0U + +#define DENOISE3D_V20_TNR_STRENGTH +#define DENOISE3D_V20_TNR_STRENGTH_MASK (0xff << 0 ) +#define DENOISE3D_V20_TNR_STRENGTH_SHIFT 0U + +#define DENOISE3D_V20_NOISE_LEVEL +#define DENOISE3D_V20_NOISE_LEVEL_MASK (0xffff << 16 ) +#define DENOISE3D_V20_NOISE_LEVEL_SHIFT 16U + +#define DENOISE3D_V20_NOISE_MEAN +#define DENOISE3D_V20_NOISE_MEAN_MASK (0xffff << 0 ) +#define DENOISE3D_V20_NOISE_MEAN_SHIFT 0U + +#define DENOISE3D_V20_NOSIE_THRESH +#define DENOISE3D_V20_NOSIE_THRESH_MASK (0xffff << 16 ) +#define DENOISE3D_V20_NOSIE_THRESH_SHIFT 16U + +#define DENOISE3D_V20_MOTION_MEAN +#define DENOISE3D_V20_MOTION_MEAN_MASK (0xffff << 0 ) +#define DENOISE3D_V20_MOTION_MEAN_SHIFT 0U + +#define DENOISE3D_V20_TNR_RANGE_H +#define DENOISE3D_V20_TNR_RANGE_H_MASK (0xf << 12 ) +#define DENOISE3D_V20_TNR_RANGE_H_SHIFT 12U + +#define DENOISE3D_V20_TNR_RANGE_V +#define DENOISE3D_V20_TNR_RANGE_V_MASK (0xf << 8 ) +#define DENOISE3D_V20_TNR_RANGE_V_SHIFT 8U + +#define DENOISE3D_V20_TNR_DILATE_RANGE_H +#define DENOISE3D_V20_TNR_DILATE_RANGE_H_MASK (0xf << 4 ) +#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHIFT 4U + +#define DENOISE3D_V20_TNR_DILATE_RANGE_V +#define DENOISE3D_V20_TNR_DILATE_RANGE_V_MASK (0xf << 0 ) +#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHIFT 0U + +#define DENOISE3D_V20_MOTION_INV +#define DENOISE3D_V20_MOTION_INV_MASK (0xfffff << 0 ) +#define DENOISE3D_V20_MOTION_INV_SHIFT 0U + +#define DENOISE3D_V20_THR_UPDATE +#define DENOISE3D_V20_THR_UPDATE_MASK (0x7ff << 16 ) +#define DENOISE3D_V20_THR_UPDATE_SHIFT 16U + +#define DENOISE3D_V20_MOTION_THR_UPDATE +#define DENOISE3D_V20_MOTION_THR_UPDATE_MASK (0x7ff << 0 ) +#define DENOISE3D_V20_MOTION_THR_UPDATE_SHIFT 0U + +#define DENOISE3D_V20_MOTION_PRE_WEIGHT +#define DENOISE3D_V20_MOTION_PRE_WEIGHT_MASK (0x3f << 16 ) +#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHIFT 16U + +#define DENOISE3D_V20_MOTION_SLOPE +#define DENOISE3D_V20_MOTION_SLOPE_MASK (0x7ff << 0 ) +#define DENOISE3D_V20_MOTION_SLOPE_SHIFT 0U + +#define DENOISE3D_V20_MOTION_CONV_SHIFT +#define DENOISE3D_V20_MOTION_CONV_SHIFT_MASK (0xf << 28 ) +#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHIFT 28U + +#define DENOISE3D_V20_MOTION_CONV_MAX +#define DENOISE3D_V20_MOTION_CONV_MAX_MASK (0x7ff << 17 ) +#define DENOISE3D_V20_MOTION_CONV_MAX_SHIFT 17U + +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_MASK (0x3f << 11 ) +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHIFT 11U + +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_MASK (0x3f << 5 ) +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHIFT 5U + +#define DENOISE3D_V20_SAD_WEIGHT +#define DENOISE3D_V20_SAD_WEIGHT_MASK (0x1f << 0 ) +#define DENOISE3D_V20_SAD_WEIGHT_SHIFT 0U + +#define DENOISE3D_V20_PIXEL_VAL_SHIFT +#define DENOISE3D_V20_PIXEL_VAL_SHIFT_MASK (0x7ff << 20 ) +#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHIFT 20U + +#define DENOISE3D_V20_PIXEL_SLOP +#define DENOISE3D_V20_PIXEL_SLOP_MASK (0xff << 12 ) +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT 12U + +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT_MASK (0xf << 8 ) +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT_SHIFT 8U + +#define DENOISE3D_V20_PIXEL_SLOP_MIN +#define DENOISE3D_V20_PIXEL_SLOP_MIN_MASK (0xff << 0 ) +#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHIFT 0U + +#define DENOISE3D_V20_INVGAMMA_EN_SHD +#define DENOISE3D_V20_INVGAMMA_EN_SHD_MASK 0x1 << 11 +#define DENOISE3D_V20_INVGAMMA_EN_SHD_SHIFT 11U + +#define DENOISE3D_V20_PREGAMMA_EN_SHD +#define DENOISE3D_V20_PREGAMMA_EN_SHD_MASK 0x1 << 10 +#define DENOISE3D_V20_PREGAMMA_EN_SHD_SHIFT 10U + +#define DENOISE3D_V20_ERODE_EN_SHD +#define DENOISE3D_V20_ERODE_EN_SHD_MASK 0x1 << 9 +#define DENOISE3D_V20_ERODE_EN_SHD_SHIFT 9U + +#define DENOISE3D_V20_MOTION_CONV_EN_SHD +#define DENOISE3D_V20_MOTION_CONV_EN_SHD_MASK 0x1 << 8 +#define DENOISE3D_V20_MOTION_CONV_EN_SHD_SHIFT 8U + +#define DENOISE3D_V20_INV_DGAIN_EN_SHD +#define DENOISE3D_V20_INV_DGAIN_EN_SHD_MASK 0x1 << 7 +#define DENOISE3D_V20_INV_DGAIN_EN_SHD_SHIFT 7U + +#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD +#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD_MASK 0x1 << 6 +#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD_SHIFT 6U + +#define DENOISE3D_V20_COMP_LUMA_EN_SHD +#define DENOISE3D_V20_COMP_LUMA_EN_SHD_MASK 0x1 << 5 +#define DENOISE3D_V20_COMP_LUMA_EN_SHD_SHIFT 5U + +#define DENOISE3D_V20_REF_RESET_SHD +#define DENOISE3D_V20_REF_RESET_SHD_MASK 0x1 << 4 +#define DENOISE3D_V20_REF_RESET_SHD_SHIFT 4U + +#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD +#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD_MASK 0x1 << 3 +#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD_SHIFT 3U + +#define DENOISE3D_V20_NLM_ENABLE_SHD +#define DENOISE3D_V20_NLM_ENABLE_SHD_MASK 0x1 << 2 +#define DENOISE3D_V20_NLM_ENABLE_SHD_SHIFT 2U + +#define DENOISE3D_V20_TNR_ENABLE_SHD +#define DENOISE3D_V20_TNR_ENABLE_SHD_MASK 0x1 << 1 +#define DENOISE3D_V20_TNR_ENABLE_SHD_SHIFT 1U + +#define DENOISE3D_V20_ENABLE_SHD +#define DENOISE3D_V20_ENABLE_SHD_MASK 0x1 << 0 +#define DENOISE3D_V20_ENABLE_SHD_SHIFT 0U + +#define DENOISE3D_V20_TNR_STRENGTH_SHD +#define DENOISE3D_V20_TNR_STRENGTH_SHD_MASK (0xff << 0 ) +#define DENOISE3D_V20_TNR_STRENGTH_SHD_SHIFT 0U + +#define DENOISE3D_V20_NOISE_LEVEL_SHD +#define DENOISE3D_V20_NOISE_LEVEL_SHD_MASK (0x3fff << 16 ) +#define DENOISE3D_V20_NOISE_LEVEL_SHD_SHIFT 16U + +#define DENOISE3D_V20_NOISE_MEAN_SHD +#define DENOISE3D_V20_NOISE_MEAN_SHD_MASK (0x3fff << 0 ) +#define DENOISE3D_V20_NOISE_MEAN_SHD_SHIFT 0U + +#define DENOISE3D_V20_NOSIE_THRESH_SHD +#define DENOISE3D_V20_NOSIE_THRESH_SHD_MASK (0x3fff << 16 ) +#define DENOISE3D_V20_NOSIE_THRESH_SHD_SHIFT 16U + +#define DENOISE3D_V20_MOTION_MEAN_SHD +#define DENOISE3D_V20_MOTION_MEAN_SHD_MASK (0x3fff << 0 ) +#define DENOISE3D_V20_MOTION_MEAN_SHD_SHIFT 0U + +#define DENOISE3D_V20_TNR_RANGE_H_SHD +#define DENOISE3D_V20_TNR_RANGE_H_SHD_MASK (0x3 << 8 ) +#define DENOISE3D_V20_TNR_RANGE_H_SHD_SHIFT 8U + +#define DENOISE3D_V20_TNR_RANGE_V_SHD +#define DENOISE3D_V20_TNR_RANGE_V_SHD_MASK (0x3 << 6 ) +#define DENOISE3D_V20_TNR_RANGE_V_SHD_SHIFT 6U + +#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD +#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD_MASK (0x7 << 3 ) +#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD_SHIFT 3U + +#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD +#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD_MASK (0x7 << 0 ) +#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD_SHIFT 0U + +#define DENOISE3D_V20_MOTION_INV_SHD +#define DENOISE3D_V20_MOTION_INV_SHD_MASK (0xfffff << 0 ) +#define DENOISE3D_V20_MOTION_INV_SHD_SHIFT 0U + +#define DENOISE3D_V20_THR_UPDATE_SHD +#define DENOISE3D_V20_THR_UPDATE_SHD_MASK (0x7ff << 16 ) +#define DENOISE3D_V20_THR_UPDATE_SHD_SHIFT 16U + +#define DENOISE3D_V20_MOTION_THR_UPDATE_SHD +#define DENOISE3D_V20_MOTION_THR_UPDATE_SHD_MASK (0x7ff << 0 ) +#define DENOISE3D_V20_MOTION_THR_UPDATE_SHD_SHIFT 0U + +#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD +#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD_MASK (0x7ff << 16 ) +#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD_SHIFT 16U + +#define DENOISE3D_V20_MOTION_SLOPE_SHD +#define DENOISE3D_V20_MOTION_SLOPE_SHD_MASK (0x7ff << 0 ) +#define DENOISE3D_V20_MOTION_SLOPE_SHD_SHIFT 0U + +#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD +#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD_MASK (0xf << 28 ) +#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD_SHIFT 28U + +#define DENOISE3D_V20_MOTION_CONV_MAX_SHD +#define DENOISE3D_V20_MOTION_CONV_MAX_SHD_MASK (0x7ff << 17 ) +#define DENOISE3D_V20_MOTION_CONV_MAX_SHD_SHIFT 17U + +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD_MASK (0x3f << 11 ) +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD_SHIFT 11U + +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD_MASK (0x3f << 5 ) +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD_SHIFT 5U + +#define DENOISE3D_V20_SAD_WEIGHT_SHD +#define DENOISE3D_V20_SAD_WEIGHT_SHD_MASK (0x1f << 0 ) +#define DENOISE3D_V20_SAD_WEIGHT_SHD_SHIFT 0U + +#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD +#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD_MASK (0x7ff << 20 ) +#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD_SHIFT 20U + +#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD +#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD_MASK (0xff << 12 ) +#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD_SHIFT 12U + +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD_MASK (0xf << 8 ) +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD_SHIFT 8U + +#define DENOISE3D_V20_BG_VAL_SUM +#define DENOISE3D_V20_BG_VAL_SUM_MASK (0xffffffff << 0 ) +#define DENOISE3D_V20_BG_VAL_SUM_SHIFT 0U + +#define DENOISE3D_V20_MO_VAL_SUM +#define DENOISE3D_V20_MO_VAL_SUM_MASK (0xffffffff << 0 ) +#define DENOISE3D_V20_MO_VAL_SUM_SHIFT 0U + +#define DENOISE3D_V20_BG_PIX_CNT +#define DENOISE3D_V20_BG_PIX_CNT_MASK (0xffffffff << 0 ) +#define DENOISE3D_V20_BG_PIX_CNT_SHIFT 0U + +#define DENOISE3D_V20_MO_PIX_CNT +#define DENOISE3D_V20_MO_PIX_CNT_MASK (0xffffffff << 0 ) +#define DENOISE3D_V20_MO_PIX_CNT_SHIFT 0U + +#define DENOISE3D_V20_FRAME_AVG +#define DENOISE3D_V20_FRAME_AVG_MASK (0xffffffff << 0 ) +#define DENOISE3D_V20_FRAME_AVG_SHIFT 0U + +#define DENOISE3D_V20_DUMMY_HBLANK +#define DENOISE3D_V20_DUMMY_HBLANK_MASK (0xffff << 0 ) +#define DENOISE3D_V20_DUMMY_HBLANK_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_2_A +#define DENOISE3D2_PREGAMMA_Y_2_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_2_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_1 +#define DENOISE3D2_PREGAMMA_Y_1_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_1_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_0 +#define DENOISE3D2_PREGAMMA_Y_0_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_0_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_2_B +#define DENOISE3D2_PREGAMMA_Y_2_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_2_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_4 +#define DENOISE3D2_PREGAMMA_Y_4_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_4_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_3 +#define DENOISE3D2_PREGAMMA_Y_3_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_3_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_7_A +#define DENOISE3D2_PREGAMMA_Y_7_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_7_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_6 +#define DENOISE3D2_PREGAMMA_Y_6_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_6_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_5 +#define DENOISE3D2_PREGAMMA_Y_5_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_5_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_7_B +#define DENOISE3D2_PREGAMMA_Y_7_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_7_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_9 +#define DENOISE3D2_PREGAMMA_Y_9_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_9_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_8 +#define DENOISE3D2_PREGAMMA_Y_8_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_8_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_12_A +#define DENOISE3D2_PREGAMMA_Y_12_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_12_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_11 +#define DENOISE3D2_PREGAMMA_Y_11_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_11_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_10 +#define DENOISE3D2_PREGAMMA_Y_10_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_10_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_12_B +#define DENOISE3D2_PREGAMMA_Y_12_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_12_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_14 +#define DENOISE3D2_PREGAMMA_Y_14_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_14_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_13 +#define DENOISE3D2_PREGAMMA_Y_13_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_13_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_17_A +#define DENOISE3D2_PREGAMMA_Y_17_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_17_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_16 +#define DENOISE3D2_PREGAMMA_Y_16_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_16_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_15 +#define DENOISE3D2_PREGAMMA_Y_15_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_15_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_17_B +#define DENOISE3D2_PREGAMMA_Y_17_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_17_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_19 +#define DENOISE3D2_PREGAMMA_Y_19_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_19_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_18 +#define DENOISE3D2_PREGAMMA_Y_18_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_18_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_22_A +#define DENOISE3D2_PREGAMMA_Y_22_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_22_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_21 +#define DENOISE3D2_PREGAMMA_Y_21_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_21_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_20 +#define DENOISE3D2_PREGAMMA_Y_20_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_20_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_22_B +#define DENOISE3D2_PREGAMMA_Y_22_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_22_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_24 +#define DENOISE3D2_PREGAMMA_Y_24_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_24_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_23 +#define DENOISE3D2_PREGAMMA_Y_23_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_23_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_27_A +#define DENOISE3D2_PREGAMMA_Y_27_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_27_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_26 +#define DENOISE3D2_PREGAMMA_Y_26_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_26_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_25 +#define DENOISE3D2_PREGAMMA_Y_25_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_25_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_27_B +#define DENOISE3D2_PREGAMMA_Y_27_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_27_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_29 +#define DENOISE3D2_PREGAMMA_Y_29_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_29_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_28 +#define DENOISE3D2_PREGAMMA_Y_28_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_28_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_32_A +#define DENOISE3D2_PREGAMMA_Y_32_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_32_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_31 +#define DENOISE3D2_PREGAMMA_Y_31_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_31_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_30 +#define DENOISE3D2_PREGAMMA_Y_30_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_30_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_32_B +#define DENOISE3D2_PREGAMMA_Y_32_B_MASK (0x3f << 0 ) +#define DENOISE3D2_PREGAMMA_Y_32_B_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_2_A_SHD +#define DENOISE3D2_PREGAMMA_Y_2_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_2_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_1_SHD +#define DENOISE3D2_PREGAMMA_Y_1_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_1_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_0_SHD +#define DENOISE3D2_PREGAMMA_Y_0_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_0_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_2_B_SHD +#define DENOISE3D2_PREGAMMA_Y_2_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_2_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_4_SHD +#define DENOISE3D2_PREGAMMA_Y_4_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_4_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_3_SHD +#define DENOISE3D2_PREGAMMA_Y_3_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_3_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_7_A_SHD +#define DENOISE3D2_PREGAMMA_Y_7_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_7_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_6_SHD +#define DENOISE3D2_PREGAMMA_Y_6_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_6_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_5_SHD +#define DENOISE3D2_PREGAMMA_Y_5_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_5_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_7_B_SHD +#define DENOISE3D2_PREGAMMA_Y_7_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_7_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_9_SHD +#define DENOISE3D2_PREGAMMA_Y_9_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_9_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_8_SHD +#define DENOISE3D2_PREGAMMA_Y_8_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_8_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_12_A_SHD +#define DENOISE3D2_PREGAMMA_Y_12_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_12_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_11_SHD +#define DENOISE3D2_PREGAMMA_Y_11_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_11_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_10_SHD +#define DENOISE3D2_PREGAMMA_Y_10_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_10_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_12_B_SHD +#define DENOISE3D2_PREGAMMA_Y_12_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_12_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_14_SHD +#define DENOISE3D2_PREGAMMA_Y_14_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_14_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_13_SHD +#define DENOISE3D2_PREGAMMA_Y_13_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_13_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_17_A_SHD +#define DENOISE3D2_PREGAMMA_Y_17_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_17_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_16_SHD +#define DENOISE3D2_PREGAMMA_Y_16_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_16_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_15_SHD +#define DENOISE3D2_PREGAMMA_Y_15_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_15_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_17_B_SHD +#define DENOISE3D2_PREGAMMA_Y_17_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_17_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_19_SHD +#define DENOISE3D2_PREGAMMA_Y_19_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_19_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_18_SHD +#define DENOISE3D2_PREGAMMA_Y_18_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_18_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_22_A_SHD +#define DENOISE3D2_PREGAMMA_Y_22_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_22_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_21_SHD +#define DENOISE3D2_PREGAMMA_Y_21_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_21_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_20_SHD +#define DENOISE3D2_PREGAMMA_Y_20_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_20_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_22_B_SHD +#define DENOISE3D2_PREGAMMA_Y_22_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_22_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_24_SHD +#define DENOISE3D2_PREGAMMA_Y_24_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_24_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_23_SHD +#define DENOISE3D2_PREGAMMA_Y_23_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_23_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_27_A_SHD +#define DENOISE3D2_PREGAMMA_Y_27_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_27_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_26_SHD +#define DENOISE3D2_PREGAMMA_Y_26_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_26_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_25_SHD +#define DENOISE3D2_PREGAMMA_Y_25_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_25_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_27_B_SHD +#define DENOISE3D2_PREGAMMA_Y_27_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_27_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_29_SHD +#define DENOISE3D2_PREGAMMA_Y_29_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_29_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_28_SHD +#define DENOISE3D2_PREGAMMA_Y_28_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_28_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_32_A_SHD +#define DENOISE3D2_PREGAMMA_Y_32_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_32_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_31_SHD +#define DENOISE3D2_PREGAMMA_Y_31_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_31_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_30_SHD +#define DENOISE3D2_PREGAMMA_Y_30_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_30_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_32_B_SHD +#define DENOISE3D2_PREGAMMA_Y_32_B_SHD_MASK (0x3f << 0 ) +#define DENOISE3D2_PREGAMMA_Y_32_B_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_2_A +#define DENOISE3D2_INVGAMMA_Y_2_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_2_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_1 +#define DENOISE3D2_INVGAMMA_Y_1_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_1_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_0 +#define DENOISE3D2_INVGAMMA_Y_0_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_0_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_2_B +#define DENOISE3D2_INVGAMMA_Y_2_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_2_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_4 +#define DENOISE3D2_INVGAMMA_Y_4_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_4_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_3 +#define DENOISE3D2_INVGAMMA_Y_3_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_3_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_7_A +#define DENOISE3D2_INVGAMMA_Y_7_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_7_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_6 +#define DENOISE3D2_INVGAMMA_Y_6_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_6_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_5 +#define DENOISE3D2_INVGAMMA_Y_5_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_5_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_7_B +#define DENOISE3D2_INVGAMMA_Y_7_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_7_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_9 +#define DENOISE3D2_INVGAMMA_Y_9_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_9_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_8 +#define DENOISE3D2_INVGAMMA_Y_8_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_8_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_12_A +#define DENOISE3D2_INVGAMMA_Y_12_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_12_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_11 +#define DENOISE3D2_INVGAMMA_Y_11_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_11_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_10 +#define DENOISE3D2_INVGAMMA_Y_10_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_10_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_12_B +#define DENOISE3D2_INVGAMMA_Y_12_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_12_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_14 +#define DENOISE3D2_INVGAMMA_Y_14_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_14_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_13 +#define DENOISE3D2_INVGAMMA_Y_13_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_13_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_17_A +#define DENOISE3D2_INVGAMMA_Y_17_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_17_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_16 +#define DENOISE3D2_INVGAMMA_Y_16_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_16_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_15 +#define DENOISE3D2_INVGAMMA_Y_15_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_15_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_17_B +#define DENOISE3D2_INVGAMMA_Y_17_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_17_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_19 +#define DENOISE3D2_INVGAMMA_Y_19_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_19_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_18 +#define DENOISE3D2_INVGAMMA_Y_18_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_18_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_22_A +#define DENOISE3D2_INVGAMMA_Y_22_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_22_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_21 +#define DENOISE3D2_INVGAMMA_Y_21_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_21_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_20 +#define DENOISE3D2_INVGAMMA_Y_20_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_20_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_22_B +#define DENOISE3D2_INVGAMMA_Y_22_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_22_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_24 +#define DENOISE3D2_INVGAMMA_Y_24_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_24_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_23 +#define DENOISE3D2_INVGAMMA_Y_23_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_23_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_27_A +#define DENOISE3D2_INVGAMMA_Y_27_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_27_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_26 +#define DENOISE3D2_INVGAMMA_Y_26_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_26_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_25 +#define DENOISE3D2_INVGAMMA_Y_25_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_25_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_27_B +#define DENOISE3D2_INVGAMMA_Y_27_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_27_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_29 +#define DENOISE3D2_INVGAMMA_Y_29_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_29_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_28 +#define DENOISE3D2_INVGAMMA_Y_28_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_28_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_32_A +#define DENOISE3D2_INVGAMMA_Y_32_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_32_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_31 +#define DENOISE3D2_INVGAMMA_Y_31_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_31_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_30 +#define DENOISE3D2_INVGAMMA_Y_30_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_30_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_32_B +#define DENOISE3D2_INVGAMMA_Y_32_B_MASK (0x3f << 0 ) +#define DENOISE3D2_INVGAMMA_Y_32_B_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_2_A_SHD +#define DENOISE3D2_INVGAMMA_Y_2_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_2_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_1_SHD +#define DENOISE3D2_INVGAMMA_Y_1_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_1_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_0_SHD +#define DENOISE3D2_INVGAMMA_Y_0_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_0_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_2_B_SHD +#define DENOISE3D2_INVGAMMA_Y_2_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_2_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_4_SHD +#define DENOISE3D2_INVGAMMA_Y_4_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_4_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_3_SHD +#define DENOISE3D2_INVGAMMA_Y_3_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_3_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_7_A_SHD +#define DENOISE3D2_INVGAMMA_Y_7_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_7_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_6_SHD +#define DENOISE3D2_INVGAMMA_Y_6_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_6_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_5_SHD +#define DENOISE3D2_INVGAMMA_Y_5_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_5_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_7_B_SHD +#define DENOISE3D2_INVGAMMA_Y_7_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_7_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_9_SHD +#define DENOISE3D2_INVGAMMA_Y_9_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_9_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_8_SHD +#define DENOISE3D2_INVGAMMA_Y_8_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_8_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_12_A_SHD +#define DENOISE3D2_INVGAMMA_Y_12_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_12_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_11_SHD +#define DENOISE3D2_INVGAMMA_Y_11_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_11_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_10_SHD +#define DENOISE3D2_INVGAMMA_Y_10_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_10_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_12_B_SHD +#define DENOISE3D2_INVGAMMA_Y_12_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_12_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_14_SHD +#define DENOISE3D2_INVGAMMA_Y_14_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_14_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_13_SHD +#define DENOISE3D2_INVGAMMA_Y_13_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_13_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_17_A_SHD +#define DENOISE3D2_INVGAMMA_Y_17_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_17_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_16_SHD +#define DENOISE3D2_INVGAMMA_Y_16_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_16_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_15_SHD +#define DENOISE3D2_INVGAMMA_Y_15_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_15_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_17_B_SHD +#define DENOISE3D2_INVGAMMA_Y_17_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_17_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_19_SHD +#define DENOISE3D2_INVGAMMA_Y_19_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_19_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_18_SHD +#define DENOISE3D2_INVGAMMA_Y_18_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_18_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_22_A_SHD +#define DENOISE3D2_INVGAMMA_Y_22_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_22_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_21_SHD +#define DENOISE3D2_INVGAMMA_Y_21_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_21_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_20_SHD +#define DENOISE3D2_INVGAMMA_Y_20_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_20_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_22_B_SHD +#define DENOISE3D2_INVGAMMA_Y_22_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_22_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_24_SHD +#define DENOISE3D2_INVGAMMA_Y_24_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_24_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_23_SHD +#define DENOISE3D2_INVGAMMA_Y_23_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_23_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_27_A_SHD +#define DENOISE3D2_INVGAMMA_Y_27_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_27_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_26_SHD +#define DENOISE3D2_INVGAMMA_Y_26_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_26_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_25_SHD +#define DENOISE3D2_INVGAMMA_Y_25_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_25_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_27_B_SHD +#define DENOISE3D2_INVGAMMA_Y_27_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_27_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_29_SHD +#define DENOISE3D2_INVGAMMA_Y_29_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_29_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_28_SHD +#define DENOISE3D2_INVGAMMA_Y_28_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_28_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_32_A_SHD +#define DENOISE3D2_INVGAMMA_Y_32_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_32_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_31_SHD +#define DENOISE3D2_INVGAMMA_Y_31_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_31_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_30_SHD +#define DENOISE3D2_INVGAMMA_Y_30_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_30_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_32_B_SHD +#define DENOISE3D2_INVGAMMA_Y_32_B_SHD_MASK (0x3f << 0 ) +#define DENOISE3D2_INVGAMMA_Y_32_B_SHD_SHIFT 0U + +#define DENOISE3D2_NLM_STRENGTH_SLOPE +#define DENOISE3D2_NLM_STRENGTH_SLOPE_MASK (0xff << 0 ) +#define DENOISE3D2_NLM_STRENGTH_SLOPE_SHIFT 0U + +#define DENOISE3D2_TNR +#define DENOISE3D2_TNR_MASK (0x7ff << 0 ) +#define DENOISE3D2_TNR_SHIFT 0U + +#define PP_RD_YUV_CFG_UPDATE +#define PP_RD_YUV_CFG_UPDATE_MASK 0x1 << 7 +#define PP_RD_YUV_CFG_UPDATE_SHIFT 7U + +#define PP_RD_YUV_AUTO_UPDATE +#define PP_RD_YUV_AUTO_UPDATE_MASK 0x1 << 6 +#define PP_RD_YUV_AUTO_UPDATE_SHIFT 6U + +#define PP_INIT_OFFSET_EN +#define PP_INIT_OFFSET_EN_MASK 0x1 << 5 +#define PP_INIT_OFFSET_EN_SHIFT 5U + +#define PP_INIT_BASE_EN +#define PP_INIT_BASE_EN_MASK 0x1 << 4 +#define PP_INIT_BASE_EN_SHIFT 4U + +#define PP_MI_CFG_UPD +#define PP_MI_CFG_UPD_MASK 0x1 << 3 +#define PP_MI_CFG_UPD_SHIFT 3U + +#define PP_MI_SKIP +#define PP_MI_SKIP_MASK 0x1 << 2 +#define PP_MI_SKIP_SHIFT 2U + +#define PP_AUTO_UPDATE +#define PP_AUTO_UPDATE_MASK 0x1 << 1 +#define PP_AUTO_UPDATE_SHIFT 1U + +#define PP_PINGPONG_ENABLE +#define PP_PINGPONG_ENABLE_MASK 0x1 << 0 +#define PP_PINGPONG_ENABLE_SHIFT 0U + +#define PP_RD_RAW_ENABLE +#define PP_RD_RAW_ENABLE_MASK 0x1 << 31 +#define PP_RD_RAW_ENABLE_SHIFT 31U + +#define PP_RD_RAW_ALIGNED +#define PP_RD_RAW_ALIGNED_MASK (0x3 << 29 ) +#define PP_RD_RAW_ALIGNED_SHIFT 29U + +#define PP_RD_RAW_BIT +#define PP_RD_RAW_BIT_MASK (0x7 << 26 ) +#define PP_RD_RAW_BIT_SHIFT 26U + +#define PP_RD_YUV_NVY +#define PP_RD_YUV_NVY_MASK (0x3 << 24 ) +#define PP_RD_YUV_NVY_SHIFT 24U + +#define PP_RD_YUV_NV21 +#define PP_RD_YUV_NV21_MASK 0x1 << 23 +#define PP_RD_YUV_NV21_SHIFT 23U + +#define PP_RD_YUV_ALIGNED +#define PP_RD_YUV_ALIGNED_MASK 0x1 << 22 +#define PP_RD_YUV_ALIGNED_SHIFT 22U + +#define PP_RD_YUV_STR +#define PP_RD_YUV_STR_MASK (0x3 << 20 ) +#define PP_RD_YUV_STR_SHIFT 20U + +#define PP_RD_YUV_FMT +#define PP_RD_YUV_FMT_MASK (0x3 << 18 ) +#define PP_RD_YUV_FMT_SHIFT 18U + +#define PP_RD_YUV_BIT +#define PP_RD_YUV_BIT_MASK 0x1 << 17 +#define PP_RD_YUV_BIT_SHIFT 17U + +#define PP_WR_RAW_SEL +#define PP_WR_RAW_SEL_MASK 0x1 << 16 +#define PP_WR_RAW_SEL_SHIFT 16U + +#define PP_WR_RAW_ALIGNED +#define PP_WR_RAW_ALIGNED_MASK (0x3 << 14 ) +#define PP_WR_RAW_ALIGNED_SHIFT 14U + +#define PP_WR_RAW_BIT +#define PP_WR_RAW_BIT_MASK (0x7 << 11 ) +#define PP_WR_RAW_BIT_SHIFT 11U + +#define PP_WR_YUV_WORD_ALIGNED_MSB_EN +#define PP_WR_YUV_WORD_ALIGNED_MSB_EN_MASK 0x1 << 10 +#define PP_WR_YUV_WORD_ALIGNED_MSB_EN_SHIFT 10U + +#define PP_WR_YUV_WORD_ALIGNED +#define PP_WR_YUV_WORD_ALIGNED_MASK 0x1 << 9 +#define PP_WR_YUV_WORD_ALIGNED_SHIFT 9U + +#define PP_WR_YUV_NVY +#define PP_WR_YUV_NVY_MASK (0x3 << 7 ) +#define PP_WR_YUV_NVY_SHIFT 7U + +#define PP_WR_YUV_NV21 +#define PP_WR_YUV_NV21_MASK 0x1 << 6 +#define PP_WR_YUV_NV21_SHIFT 6U + +#define PP_WR_YUV_ALIGNED +#define PP_WR_YUV_ALIGNED_MASK 0x1 << 5 +#define PP_WR_YUV_ALIGNED_SHIFT 5U + +#define PP_WR_YUV_STR +#define PP_WR_YUV_STR_MASK (0x3 << 3 ) +#define PP_WR_YUV_STR_SHIFT 3U + +#define PP_WR_YUV_FMT +#define PP_WR_YUV_FMT_MASK (0x3 << 1 ) +#define PP_WR_YUV_FMT_SHIFT 1U + +#define PP_WR_YUV_BIT +#define PP_WR_YUV_BIT_MASK 0x1 << 0 +#define PP_WR_YUV_BIT_SHIFT 0U + +#define PP_RD_SWAP_V +#define PP_RD_SWAP_V_MASK 0xf << 24 +#define PP_RD_SWAP_V_SHIFT 24U + +#define PP_RD_SWAP_U +#define PP_RD_SWAP_U_MASK 0xf << 20 +#define PP_RD_SWAP_U_SHIFT 20U + +#define PP_RD_SWAP_Y +#define PP_RD_SWAP_Y_MASK 0xf << 16 +#define PP_RD_SWAP_Y_SHIFT 16U + +#define PP_WR_SWAP_V +#define PP_WR_SWAP_V_MASK 0xf << 8 +#define PP_WR_SWAP_V_SHIFT 8U + +#define PP_WR_SWAP_U +#define PP_WR_SWAP_U_MASK 0xf << 4 +#define PP_WR_SWAP_U_SHIFT 4U + +#define PP_WR_SWAP_Y +#define PP_WR_SWAP_Y_MASK 0xf << 0 +#define PP_WR_SWAP_Y_SHIFT 0U + +#define PP_Y_BASE_AD_INIT +#define PP_Y_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define PP_Y_BASE_AD_INIT_SHIFT 4U + +#define PP_Y_SIZE_INIT +#define PP_Y_SIZE_INIT_MASK (0x1ffffff << 4 ) +#define PP_Y_SIZE_INIT_SHIFT 4U + +#define PP_Y_OFFS_CNT_INIT +#define PP_Y_OFFS_CNT_INIT_MASK (0x1ffffff << 4 ) +#define PP_Y_OFFS_CNT_INIT_SHIFT 4U + +#define PP_Y_LLENGH +#define PP_Y_LLENGH_MASK (0xffffffff << 0 ) +#define PP_Y_LLENGH_SHIFT 0U + +#define PP_Y_PIC_WIDTH +#define PP_Y_PIC_WIDTH_MASK (0xffffffff << 0 ) +#define PP_Y_PIC_WIDTH_SHIFT 0U + +#define PP_Y_PIC_HEIGHT +#define PP_Y_PIC_HEIGHT_MASK (0xffffffff << 0 ) +#define PP_Y_PIC_HEIGHT_SHIFT 0U + +#define PP_Y_PIC_SIZE +#define PP_Y_PIC_SIZE_MASK (0xffffffff << 0 ) +#define PP_Y_PIC_SIZE_SHIFT 0U + +#define PP_CB_BASE_AD_INIT +#define PP_CB_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define PP_CB_BASE_AD_INIT_SHIFT 4U + +#define PP_CB_SIZE_INIT +#define PP_CB_SIZE_INIT_MASK (0xffffff << 4 ) +#define PP_CB_SIZE_INIT_SHIFT 4U + +#define PP_CB_OFFS_CNT_INIT +#define PP_CB_OFFS_CNT_INIT_MASK (0xffffff << 4 ) +#define PP_CB_OFFS_CNT_INIT_SHIFT 4U + +#define PP_CR_BASE_AD_INIT +#define PP_CR_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define PP_CR_BASE_AD_INIT_SHIFT 4U + +#define PP_CR_SIZE_INIT +#define PP_CR_SIZE_INIT_MASK (0xffffff << 4 ) +#define PP_CR_SIZE_INIT_SHIFT 4U + +#define PP_CR_OFFS_CNT_INIT +#define PP_CR_OFFS_CNT_INIT_MASK (0xffffff << 4 ) +#define PP_CR_OFFS_CNT_INIT_SHIFT 4U + +#define PP_Y_BASE_AD_INIT2 +#define PP_Y_BASE_AD_INIT2_MASK (0xfffffff << 4 ) +#define PP_Y_BASE_AD_INIT2_SHIFT 4U + +#define PP_CB_BASE_AD_INIT2 +#define PP_CB_BASE_AD_INIT2_MASK (0xfffffff << 4 ) +#define PP_CB_BASE_AD_INIT2_SHIFT 4U + +#define PP_CR_BASE_AD_INIT2 +#define PP_CR_BASE_AD_INIT2_MASK (0xfffffff << 4 ) +#define PP_CR_BASE_AD_INIT2_SHIFT 4U + +#define PP_Y_OFFS_CNT_START +#define PP_Y_OFFS_CNT_START_MASK (0x1ffffff << 4 ) +#define PP_Y_OFFS_CNT_START_SHIFT 4U + +#define PP_CB_OFFS_CNT_START +#define PP_CB_OFFS_CNT_START_MASK (0xffffff << 4 ) +#define PP_CB_OFFS_CNT_START_SHIFT 4U + +#define PP_CR_OFFS_CNT_START +#define PP_CR_OFFS_CNT_START_MASK (0xffffff << 4 ) +#define PP_CR_OFFS_CNT_START_SHIFT 4U + +#define PP_Y_BASE_AD +#define PP_Y_BASE_AD_MASK (0xfffffff << 4 ) +#define PP_Y_BASE_AD_SHIFT 4U + +#define PP_Y_SIZE +#define PP_Y_SIZE_MASK (0x1ffffff << 4 ) +#define PP_Y_SIZE_SHIFT 4U + +#define PP_Y_OFFS_CNT +#define PP_Y_OFFS_CNT_MASK (0x1ffffff << 4 ) +#define PP_Y_OFFS_CNT_SHIFT 4U + +#define PP_CB_BASE_AD +#define PP_CB_BASE_AD_MASK (0xfffffff << 4 ) +#define PP_CB_BASE_AD_SHIFT 4U + +#define PP_CB_SIZE +#define PP_CB_SIZE_MASK (0xffffff << 4 ) +#define PP_CB_SIZE_SHIFT 4U + +#define PP_CB_OFFS_CNT +#define PP_CB_OFFS_CNT_MASK (0xffffff << 4 ) +#define PP_CB_OFFS_CNT_SHIFT 4U + +#define PP_CR_BASE_AD +#define PP_CR_BASE_AD_MASK (0xfffffff << 4 ) +#define PP_CR_BASE_AD_SHIFT 4U + +#define PP_CR_SIZE +#define PP_CR_SIZE_MASK (0xffffff << 4 ) +#define PP_CR_SIZE_SHIFT 4U + +#define PP_CR_OFFS_CNT +#define PP_CR_OFFS_CNT_MASK (0xffffff << 4 ) +#define PP_CR_OFFS_CNT_SHIFT 4U + +#define PP_DMA_Y_PIC_WIDTH +#define PP_DMA_Y_PIC_WIDTH_MASK (0x7fff << 0 ) +#define PP_DMA_Y_PIC_WIDTH_SHIFT 0U + +#define PP_DMA_Y_PIC_LLENGTH +#define PP_DMA_Y_PIC_LLENGTH_MASK (0xffffffff << 0 ) +#define PP_DMA_Y_PIC_LLENGTH_SHIFT 0U + +#define PP_DMA_Y_PIC_SIZE +#define PP_DMA_Y_PIC_SIZE_MASK (0xfffffff << 0 ) +#define PP_DMA_Y_PIC_SIZE_SHIFT 0U + +#define PP_DMA_CB_PIC_START_AD +#define PP_DMA_CB_PIC_START_AD_MASK (0xfffffff << 4 ) +#define PP_DMA_CB_PIC_START_AD_SHIFT 4U + +#define PP_DMA_CR_PIC_START_AD +#define PP_DMA_CR_PIC_START_AD_MASK (0xfffffff << 4 ) +#define PP_DMA_CR_PIC_START_AD_SHIFT 4U + +#define PP_DMA_Y_PIC_START_AD +#define PP_DMA_Y_PIC_START_AD_MASK (0xfffffff << 4 ) +#define PP_DMA_Y_PIC_START_AD_SHIFT 4U + +#define PP_DMA_CB_PIC_START_AD +#define PP_DMA_CB_PIC_START_AD_MASK (0xfffffff << 4 ) +#define PP_DMA_CB_PIC_START_AD_SHIFT 4U + +#define PP_DMA_CR_PIC_START_AD +#define PP_DMA_CR_PIC_START_AD_MASK (0xfffffff << 4 ) +#define PP_DMA_CR_PIC_START_AD_SHIFT 4U + +#define PP_DMA_Y_PIC_LVAL +#define PP_DMA_Y_PIC_LVAL_MASK (0xffff << 0 ) +#define PP_DMA_Y_PIC_LVAL_SHIFT 0U + + + +#define HDR_DMA_START_CONTINUOUS +#define HDR_DMA_START_CONTINUOUS_MASK 0x1 << 8 +#define HDR_DMA_START_CONTINUOUS_SHIFT 8U + +#define HDR_DMA_START +#define HDR_DMA_START_MASK 0x1 << 7 +#define HDR_DMA_START_SHIFT 7U + +#define HDR_WR_ENABLE +#define HDR_WR_ENABLE_MASK 0x1 << 6 +#define HDR_WR_ENABLE_SHIFT 6U + +#define HDR_RD_RAW_CFG_UPDATE +#define HDR_RD_RAW_CFG_UPDATE_MASK 0x1 << 5 +#define HDR_RD_RAW_CFG_UPDATE_SHIFT 5U + +#define HDR_RD_RAW_AUTO_UPDATE +#define HDR_RD_RAW_AUTO_UPDATE_MASK 0x1 << 4 +#define HDR_RD_RAW_AUTO_UPDATE_SHIFT 4U + +#define HDR_INIT_OFFSET_EN +#define HDR_INIT_OFFSET_EN_MASK 0x1 << 3 +#define HDR_INIT_OFFSET_EN_SHIFT 3U + +#define HDR_INIT_BASE_EN +#define HDR_INIT_BASE_EN_MASK 0x1 << 2 +#define HDR_INIT_BASE_EN_SHIFT 2U + +#define HDR_MI_CFG_UPD +#define HDR_MI_CFG_UPD_MASK 0x1 << 1 +#define HDR_MI_CFG_UPD_SHIFT 1U + +#define HDR_AUTO_UPDATE +#define HDR_AUTO_UPDATE_MASK 0x1 << 0 +#define HDR_AUTO_UPDATE_SHIFT 0U + +#define HDR_RD_RAW_ALIGNED +#define HDR_RD_RAW_ALIGNED_MASK (0x3 << 24 ) +#define HDR_RD_RAW_ALIGNED_SHIFT 24U + +#define HDR_RD_VS_BIT +#define HDR_RD_VS_BIT_MASK (0x3 << 22 ) +#define HDR_RD_VS_BIT_SHIFT 22U + +#define HDR_RD_S_BIT +#define HDR_RD_S_BIT_MASK (0x3 << 20 ) +#define HDR_RD_S_BIT_SHIFT 20U + +#define HDR_RD_L_BIT +#define HDR_RD_L_BIT_MASK (0x3 << 18 ) +#define HDR_RD_L_BIT_SHIFT 18U + +#define HDR_RD_STR +#define HDR_RD_STR_MASK (0x3 << 16 ) +#define HDR_RD_STR_SHIFT 16U + +#define HDR_WR_RAW_ALIGNED +#define HDR_WR_RAW_ALIGNED_MASK (0x3 << 8 ) +#define HDR_WR_RAW_ALIGNED_SHIFT 8U + +#define HDR_WR_VS_BIT +#define HDR_WR_VS_BIT_MASK (0x3 << 6 ) +#define HDR_WR_VS_BIT_SHIFT 6U + +#define HDR_WR_S_BIT +#define HDR_WR_S_BIT_MASK (0x3 << 4 ) +#define HDR_WR_S_BIT_SHIFT 4U + +#define HDR_WR_L_BIT +#define HDR_WR_L_BIT_MASK (0x3 << 2 ) +#define HDR_WR_L_BIT_SHIFT 2U + +#define HDR_WR_STR +#define HDR_WR_STR_MASK (0x3 << 0 ) +#define HDR_WR_STR_SHIFT 0U + +#define HDR_DMA_START_BY_LINES +#define HDR_DMA_START_BY_LINES_MASK (0xffff << 0 ) +#define HDR_DMA_START_BY_LINES_SHIFT 0U + +#define HDR_RD_SWAP_RAW +#define HDR_RD_SWAP_RAW_MASK (0xf << 16 ) +#define HDR_RD_SWAP_RAW_SHIFT 16U + +#define HDR_WR_SWAP_RAW +#define HDR_WR_SWAP_RAW_MASK (0xf << 0 ) +#define HDR_WR_SWAP_RAW_SHIFT 0U + +#define HDR_BUS_SW_EN +#define HDR_BUS_SW_EN_MASK 0x1 << 23 +#define HDR_BUS_SW_EN_SHIFT 23U + +#define HDR_RD_BURST_LEN +#define HDR_RD_BURST_LEN_MASK (0x3 << 21 ) +#define HDR_RD_BURST_LEN_SHIFT 21U + +#define HDR_WR_BURST_LEN +#define HDR_WR_BURST_LEN_MASK (0x3 << 19 ) +#define HDR_WR_BURST_LEN_SHIFT 19U + +#define HDR_RD_ID_EN +#define HDR_RD_ID_EN_MASK 0x1 << 18 +#define HDR_RD_ID_EN_SHIFT 18U + +#define HDR_RD_ID_CFG +#define HDR_RD_ID_CFG_MASK (0xff << 10 ) +#define HDR_RD_ID_CFG_SHIFT 10U + +#define HDR_WR_ID_EN +#define HDR_WR_ID_EN_MASK 0x1 << 8 +#define HDR_WR_ID_EN_SHIFT 8U + +#define HDR_WR_ID_CFG +#define HDR_WR_ID_CFG_MASK (0xff << 0 ) +#define HDR_WR_ID_CFG_SHIFT 0U + +#define HDR_BUS_TIMEO_EN +#define HDR_BUS_TIMEO_EN_MASK 0x1 << 31 +#define HDR_BUS_TIMEO_EN_SHIFT 31U + +#define HDR_BUS_TIMEO +#define HDR_BUS_TIMEO_MASK (0x7fffffff << 0 ) +#define HDR_BUS_TIMEO_SHIFT 0U + +#define HDR_L_PIC_WIDTH +#define HDR_L_PIC_WIDTH_MASK (0xffffffff << 0 ) +#define HDR_L_PIC_WIDTH_SHIFT 0U + +#define HDR_L_PIC_HEIGHT +#define HDR_L_PIC_HEIGHT_MASK (0xffffffff << 0 ) +#define HDR_L_PIC_HEIGHT_SHIFT 0U + +#define HDR_L_BASE_AD_INIT +#define HDR_L_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_L_BASE_AD_INIT_SHIFT 4U + +#define HDR_L_SIZE_INIT +#define HDR_L_SIZE_INIT_MASK (0x1ffffff << 4 ) +#define HDR_L_SIZE_INIT_SHIFT 4U + +#define HDR_L_OFFS_CNT_INIT +#define HDR_L_OFFS_CNT_INIT_MASK (0x1ffffff << 4 ) +#define HDR_L_OFFS_CNT_INIT_SHIFT 4U + +#define HDR_L_LLENGTH +#define HDR_L_LLENGTH_MASK (0xffffffff << 0 ) +#define HDR_L_LLENGTH_SHIFT 0U + +#define HDR_L_PIC_LVAL +#define HDR_L_PIC_LVAL_MASK (0xffff << 0 ) +#define HDR_L_PIC_LVAL_SHIFT 0U + +#define HDR_L_IRQ_OFFS_INIT +#define HDR_L_IRQ_OFFS_INIT_MASK (0xffffffff << 0 ) +#define HDR_L_IRQ_OFFS_INIT_SHIFT 0U + +#define HDR_L_OFFS_CNT_START +#define HDR_L_OFFS_CNT_START_MASK (0x1ffffff << 4 ) +#define HDR_L_OFFS_CNT_START_SHIFT 4U + +#define HDR_L_BASE_AD_SHD +#define HDR_L_BASE_AD_SHD_MASK (0xfffffff << 4 ) +#define HDR_L_BASE_AD_SHD_SHIFT 4U + +#define HDR_L_SIZE_SHD +#define HDR_L_SIZE_SHD_MASK (0x1ffffff << 4 ) +#define HDR_L_SIZE_SHD_SHIFT 4U + +#define HDR_L_OFFS_CNT +#define HDR_L_OFFS_CNT_MASK (0x1ffffff << 4 ) +#define HDR_L_OFFS_CNT_SHIFT 4U + +#define HDR_L_IRQ_OFFS_SHD +#define HDR_L_IRQ_OFFS_SHD_MASK (0xffffffff << 0 ) +#define HDR_L_IRQ_OFFS_SHD_SHIFT 0U + +#define HDR_S_BASE_AD_INIT +#define HDR_S_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_S_BASE_AD_INIT_SHIFT 4U + +#define HDR_S_SIZE_INIT +#define HDR_S_SIZE_INIT_MASK (0x1ffffff << 4 ) +#define HDR_S_SIZE_INIT_SHIFT 4U + +#define HDR_S_OFFS_CNT_INIT +#define HDR_S_OFFS_CNT_INIT_MASK (0x1ffffff << 4 ) +#define HDR_S_OFFS_CNT_INIT_SHIFT 4U + +#define HDR_S_LLENGTH +#define HDR_S_LLENGTH_MASK (0xffffffff << 0 ) +#define HDR_S_LLENGTH_SHIFT 0U + +#define HDR_S_PIC_LVAL +#define HDR_S_PIC_LVAL_MASK (0xffff << 0 ) +#define HDR_S_PIC_LVAL_SHIFT 0U + +#define HDR_S_IRQ_OFFS_INIT +#define HDR_S_IRQ_OFFS_INIT_MASK (0xffffffff << 0 ) +#define HDR_S_IRQ_OFFS_INIT_SHIFT 0U + +#define HDR_S_OFFS_CNT_START +#define HDR_S_OFFS_CNT_START_MASK (0x1ffffff << 4 ) +#define HDR_S_OFFS_CNT_START_SHIFT 4U + +#define HDR_S_BASE_AD_SHD +#define HDR_S_BASE_AD_SHD_MASK (0xfffffff << 4 ) +#define HDR_S_BASE_AD_SHD_SHIFT 4U + +#define HDR_S_SIZE_SHD +#define HDR_S_SIZE_SHD_MASK (0x1ffffff << 4 ) +#define HDR_S_SIZE_SHD_SHIFT 4U + +#define HDR_S_OFFS_CNT +#define HDR_S_OFFS_CNT_MASK (0x1ffffff << 4 ) +#define HDR_S_OFFS_CNT_SHIFT 4U + +#define HDR_S_IRQ_OFFS_SHD +#define HDR_S_IRQ_OFFS_SHD_MASK (0xffffffff << 0 ) +#define HDR_S_IRQ_OFFS_SHD_SHIFT 0U + +#define HDR_VS_BASE_AD_INIT +#define HDR_VS_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_VS_BASE_AD_INIT_SHIFT 4U + +#define HDR_VS_SIZE_INIT +#define HDR_VS_SIZE_INIT_MASK (0x1ffffff << 4 ) +#define HDR_VS_SIZE_INIT_SHIFT 4U + +#define HDR_VS_OFFS_CNT_INIT +#define HDR_VS_OFFS_CNT_INIT_MASK (0x1ffffff << 4 ) +#define HDR_VS_OFFS_CNT_INIT_SHIFT 4U + +#define HDR_VS_LLENGTH +#define HDR_VS_LLENGTH_MASK (0xffffffff << 0 ) +#define HDR_VS_LLENGTH_SHIFT 0U + +#define HDR_VS_PIC_LVAL +#define HDR_VS_PIC_LVAL_MASK (0xffff << 0 ) +#define HDR_VS_PIC_LVAL_SHIFT 0U + +#define HDR_VS_IRQ_OFFS_INIT +#define HDR_VS_IRQ_OFFS_INIT_MASK (0xffffffff << 0 ) +#define HDR_VS_IRQ_OFFS_INIT_SHIFT 0U + +#define HDR_VS_OFFS_CNT_START +#define HDR_VS_OFFS_CNT_START_MASK (0x1ffffff << 4 ) +#define HDR_VS_OFFS_CNT_START_SHIFT 4U + +#define HDR_VS_BASE_AD_SHD +#define HDR_VS_BASE_AD_SHD_MASK (0xfffffff << 4 ) +#define HDR_VS_BASE_AD_SHD_SHIFT 4U + +#define HDR_VS_SIZE_SHD +#define HDR_VS_SIZE_SHD_MASK (0x1ffffff << 4 ) +#define HDR_VS_SIZE_SHD_SHIFT 4U + +#define HDR_VS_OFFS_CNT +#define HDR_VS_OFFS_CNT_MASK (0x1ffffff << 4 ) +#define HDR_VS_OFFS_CNT_SHIFT 4U + +#define HDR_VS_IRQ_OFFS_SHD +#define HDR_VS_IRQ_OFFS_SHD_MASK (0xffffffff << 0 ) +#define HDR_VS_IRQ_OFFS_SHD_SHIFT 0U + +#define HDR_DMA_PIC_WIDTH +#define HDR_DMA_PIC_WIDTH_MASK (0x7fff << 0 ) +#define HDR_DMA_PIC_WIDTH_SHIFT 0U + +#define HDR_DMA_PIC_HEIGHT +#define HDR_DMA_PIC_HEIGHT_MASK (0x7fff << 0 ) +#define HDR_DMA_PIC_HEIGHT_SHIFT 0U + +#define HDR_DMA_L_BASE_AD_INIT +#define HDR_DMA_L_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_L_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_L_SIZE_INIT +#define HDR_DMA_L_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_L_SIZE_INIT_SHIFT 4U + +#define HDR_DMA_L_PIC_LLENGTH +#define HDR_DMA_L_PIC_LLENGTH_MASK (0xfffffff << 4 ) +#define HDR_DMA_L_PIC_LLENGTH_SHIFT 4U + +#define HDR_DMA_L_WIDTH_BYTES +#define HDR_DMA_L_WIDTH_BYTES_MASK (0xffff << 0 ) +#define HDR_DMA_L_WIDTH_BYTES_SHIFT 0U + +#define HDR_DMA_L_BASE_AD_INIT +#define HDR_DMA_L_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_L_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_L_SIZE_INIT +#define HDR_DMA_L_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_L_SIZE_INIT_SHIFT 4U + +#define HDR_DMA_S_BASE_AD_INIT +#define HDR_DMA_S_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_S_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_S_SIZE_INIT +#define HDR_DMA_S_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_S_SIZE_INIT_SHIFT 4U + +#define HDR_DMA_S_PIC_LLENGTH +#define HDR_DMA_S_PIC_LLENGTH_MASK (0xfffffff << 4 ) +#define HDR_DMA_S_PIC_LLENGTH_SHIFT 4U + +#define HDR_DMA_S_WIDTH_BYTES +#define HDR_DMA_S_WIDTH_BYTES_MASK (0xffff << 0 ) +#define HDR_DMA_S_WIDTH_BYTES_SHIFT 0U + +#define HDR_DMA_S_BASE_AD_INIT +#define HDR_DMA_S_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_S_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_S_SIZE_INIT +#define HDR_DMA_S_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_S_SIZE_INIT_SHIFT 4U + +#define HDR_DMA_VS_BASE_AD_INIT +#define HDR_DMA_VS_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_VS_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_VS_SIZE_INIT +#define HDR_DMA_VS_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_VS_SIZE_INIT_SHIFT 4U + +#define HDR_DMA_VS_PIC_LLENGTH +#define HDR_DMA_VS_PIC_LLENGTH_MASK (0xfffffff << 4 ) +#define HDR_DMA_VS_PIC_LLENGTH_SHIFT 4U + +#define HDR_DMA_VS_WIDTH_BYTES +#define HDR_DMA_VS_WIDTH_BYTES_MASK (0xffff << 0 ) +#define HDR_DMA_VS_WIDTH_BYTES_SHIFT 0U + +#define HDR_DMA_VS_BASE_AD_INIT +#define HDR_DMA_VS_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_VS_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_VS_SIZE_INIT +#define HDR_DMA_VS_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_VS_SIZE_INIT_SHIFT 4U + +#define HDR_RT_VSYNC_POL +#define HDR_RT_VSYNC_POL_MASK (0x1 << 8) +#define HDR_RT_VSYNC_POL_SHIFT 8U + +#define HDR_RT_HSYNC_POL +#define HDR_RT_HSYNC_POL_MASK (0x1 << 7) +#define HDR_RT_HSYNC_POL_SHIFT 7U + +#define HDR_RETIMING_ENABLE +#define HDR_RETIMING_ENABLE_MASK 0x1 << 6 +#define HDR_RETIMING_ENABLE_SHIFT 6U + +#define LONG_USE_DDR_ONLY_EN +#define LONG_USE_DDR_ONLY_EN_MASK 0x1 << 5 +#define LONG_USE_DDR_ONLY_EN_SHIFT 5U + +#define SHORT_USE_DDR_ONLY_EN +#define SHORT_USE_DDR_ONLY_EN_MASK 0x1 << 4 +#define SHORT_USE_DDR_ONLY_EN_SHIFT 4U + +#define DUMP_MODE_EN +#define DUMP_MODE_EN_MASK 0x1 << 3 +#define DUMP_MODE_EN_SHIFT 3U + +#define L_VS_COMBINING_ENABLE +#define L_VS_COMBINING_ENABLE_MASK 0x1 << 2 +#define L_VS_COMBINING_ENABLE_SHIFT 2U + +#define EXPOSURE_COUNT +#define EXPOSURE_COUNT_MASK (0x3 << 0 ) +#define EXPOSURE_COUNT_SHIFT 0U + +#define HDR_INTERVAL1 +#define HDR_INTERVAL1_MASK (0xffff << 16 ) +#define HDR_INTERVAL1_SHIFT 16U + +#define HDR_INTERVAL0 +#define HDR_INTERVAL0_MASK (0xffff << 0 ) +#define HDR_INTERVAL0_SHIFT 0U + +#define PART_TWO_ENABLE +#define PART_TWO_ENABLE_MASK 0x1 << 23 +#define PART_TWO_ENABLE_SHIFT 23U + +#define PART_ONE_ENABLE +#define PART_ONE_ENABLE_MASK 0x1 << 22 +#define PART_ONE_ENABLE_SHIFT 22U + +#define SOFT_RST_PRE_FILT +#define SOFT_RST_PRE_FILT_MASK 0x1 << 21 +#define SOFT_RST_PRE_FILT_SHIFT 21U + +#define DEMOSAIC_THRESHOLD +#define DEMOSAIC_THRESHOLD_MASK (0xff << 13 ) +#define DEMOSAIC_THRESHOLD_SHIFT 13U + +#define STAGE1_SELECT +#define STAGE1_SELECT_MASK (0xf << 9 ) +#define STAGE1_SELECT_SHIFT 9U + +#define OUT_RGB_BAYER_PATTERN +#define OUT_RGB_BAYER_PATTERN_MASK (0x3 << 7 ) +#define OUT_RGB_BAYER_PATTERN_SHIFT 7U + +#define RGBIR_BAYER_PATTERN +#define RGBIR_BAYER_PATTERN_MASK (0xf << 3 ) +#define RGBIR_BAYER_PATTERN_SHIFT 3U + +#define GREEN_FILT_ENABLE +#define GREEN_FILT_ENABLE_MASK 0x1 << 2 +#define GREEN_FILT_ENABLE_SHIFT 2U + +#define GREEN_FILT_MODE +#define GREEN_FILT_MODE_MASK 0x1 << 1 +#define GREEN_FILT_MODE_SHIFT 1U + +#define ISP_PRE_FILT_ENABLE +#define ISP_PRE_FILT_ENABLE_MASK 0x1 << 0 +#define ISP_PRE_FILT_ENABLE_SHIFT 0U + +#define ISP_PRE_FILT_BLS_A +#define ISP_PRE_FILT_BLS_A_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_BLS_A_SHIFT 0U + +#define ISP_PRE_FILT_BLS_B +#define ISP_PRE_FILT_BLS_B_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_BLS_B_SHIFT 0U + +#define ISP_PRE_FILT_BLS_C +#define ISP_PRE_FILT_BLS_C_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_BLS_C_SHIFT 0U + +#define ISP_PRE_FILT_BLS_D +#define ISP_PRE_FILT_BLS_D_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_BLS_D_SHIFT 0U + +#define ISP_PRE_FILT_GAIN_R +#define ISP_PRE_FILT_GAIN_R_MASK (0x3ff << 0 ) +#define ISP_PRE_FILT_GAIN_R_SHIFT 0U + +#define ISP_PRE_FILT_GAIN_G +#define ISP_PRE_FILT_GAIN_G_MASK (0x3ff << 0 ) +#define ISP_PRE_FILT_GAIN_G_SHIFT 0U + +#define ISP_PRE_FILT_GAIN_B +#define ISP_PRE_FILT_GAIN_B_MASK (0x3ff << 0 ) +#define ISP_PRE_FILT_GAIN_B_SHIFT 0U + +#define ISP_PRE_FILT_DPC_TH_MED_R +#define ISP_PRE_FILT_DPC_TH_MED_R_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_DPC_TH_MED_R_SHIFT 16U + +#define ISP_PRE_FILT_DPC_TH_AVG_R +#define ISP_PRE_FILT_DPC_TH_AVG_R_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_DPC_TH_AVG_R_SHIFT 0U + +#define ISP_PRE_FILT_DPC_TH_MED_G +#define ISP_PRE_FILT_DPC_TH_MED_G_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_DPC_TH_MED_G_SHIFT 16U + +#define ISP_PRE_FILT_DPC_TH_AVG_G +#define ISP_PRE_FILT_DPC_TH_AVG_G_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_DPC_TH_AVG_G_SHIFT 0U + +#define ISP_PRE_FILT_DPC_TH_MED_B +#define ISP_PRE_FILT_DPC_TH_MED_B_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_DPC_TH_MED_B_SHIFT 16U + +#define ISP_PRE_FILT_DPC_TH_AVG_B +#define ISP_PRE_FILT_DPC_TH_AVG_B_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_DPC_TH_AVG_B_SHIFT 0U + +#define ISP_PRE_FILT_DPC_TH_MED_IR +#define ISP_PRE_FILT_DPC_TH_MED_IR_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_DPC_TH_MED_IR_SHIFT 16U + +#define ISP_PRE_FILT_DPC_TH_AVG_IR +#define ISP_PRE_FILT_DPC_TH_AVG_IR_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_DPC_TH_AVG_IR_SHIFT 0U + +#define ISP_PRE_FILT_CC_00 +#define ISP_PRE_FILT_CC_00_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_00_SHIFT 16U + +#define ISP_PRE_FILT_CC_01 +#define ISP_PRE_FILT_CC_01_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_01_SHIFT 0U + +#define ISP_PRE_FILT_CC_02 +#define ISP_PRE_FILT_CC_02_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_02_SHIFT 16U + +#define ISP_PRE_FILT_CC_03 +#define ISP_PRE_FILT_CC_03_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_03_SHIFT 0U + +#define ISP_PRE_FILT_CC_10 +#define ISP_PRE_FILT_CC_10_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_10_SHIFT 16U + +#define ISP_PRE_FILT_CC_11 +#define ISP_PRE_FILT_CC_11_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_11_SHIFT 0U + +#define ISP_PRE_FILT_CC_12 +#define ISP_PRE_FILT_CC_12_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_12_SHIFT 16U + +#define ISP_PRE_FILT_CC_13 +#define ISP_PRE_FILT_CC_13_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_13_SHIFT 0U + +#define ISP_PRE_FILT_CC_20 +#define ISP_PRE_FILT_CC_20_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_20_SHIFT 16U + +#define ISP_PRE_FILT_CC_21 +#define ISP_PRE_FILT_CC_21_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_21_SHIFT 0U + +#define ISP_PRE_FILT_CC_22 +#define ISP_PRE_FILT_CC_22_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_22_SHIFT 16U + +#define ISP_PRE_FILT_CC_23 +#define ISP_PRE_FILT_CC_23_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_23_SHIFT 0U + +#define ISP_PRE_FILT_CC_00_SHD +#define ISP_PRE_FILT_CC_00_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_00_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_01_SHD +#define ISP_PRE_FILT_CC_01_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_01_SHD_SHIFT 0U + +#define ISP_PRE_FILT_CC_02_SHD +#define ISP_PRE_FILT_CC_02_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_02_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_03_SHD +#define ISP_PRE_FILT_CC_03_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_03_SHD_SHIFT 0U + +#define ISP_PRE_FILT_CC_10_SHD +#define ISP_PRE_FILT_CC_10_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_10_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_11_SHD +#define ISP_PRE_FILT_CC_11_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_11_SHD_SHIFT 0U + +#define ISP_PRE_FILT_CC_12_SHD +#define ISP_PRE_FILT_CC_12_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_12_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_13_SHD +#define ISP_PRE_FILT_CC_13_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_13_SHD_SHIFT 0U + +#define ISP_PRE_FILT_CC_20_SHD +#define ISP_PRE_FILT_CC_20_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_20_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_21_SHD +#define ISP_PRE_FILT_CC_21_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_21_SHD_SHIFT 0U + +#define ISP_PRE_FILT_CC_22_SHD +#define ISP_PRE_FILT_CC_22_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_22_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_23_SHD +#define ISP_PRE_FILT_CC_23_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_23_SHD_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PX1 +#define ISP_PRE_FILT_IR_DES_PX1_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PX1_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY2 +#define ISP_PRE_FILT_IR_DES_PY2_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY2_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY1 +#define ISP_PRE_FILT_IR_DES_PY1_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY1_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY4 +#define ISP_PRE_FILT_IR_DES_PY4_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY4_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY3 +#define ISP_PRE_FILT_IR_DES_PY3_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY3_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY6 +#define ISP_PRE_FILT_IR_DES_PY6_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY6_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY5 +#define ISP_PRE_FILT_IR_DES_PY5_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY5_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY8 +#define ISP_PRE_FILT_IR_DES_PY8_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY8_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY7 +#define ISP_PRE_FILT_IR_DES_PY7_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY7_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY10 +#define ISP_PRE_FILT_IR_DES_PY10_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY10_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY9 +#define ISP_PRE_FILT_IR_DES_PY9_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY9_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY12 +#define ISP_PRE_FILT_IR_DES_PY12_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY12_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY11 +#define ISP_PRE_FILT_IR_DES_PY11_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY11_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY14 +#define ISP_PRE_FILT_IR_DES_PY14_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY14_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY13 +#define ISP_PRE_FILT_IR_DES_PY13_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY13_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY16 +#define ISP_PRE_FILT_IR_DES_PY16_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY16_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY15 +#define ISP_PRE_FILT_IR_DES_PY15_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY15_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PD4 +#define ISP_PRE_FILT_IR_DES_PD4_MASK (0xff << 24 ) +#define ISP_PRE_FILT_IR_DES_PD4_SHIFT 24U + +#define ISP_PRE_FILT_IR_DES_PD3 +#define ISP_PRE_FILT_IR_DES_PD3_MASK (0xff << 16 ) +#define ISP_PRE_FILT_IR_DES_PD3_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PD2 +#define ISP_PRE_FILT_IR_DES_PD2_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DES_PD2_SHIFT 8U + +#define ISP_PRE_FILT_IR_DES_PD1 +#define ISP_PRE_FILT_IR_DES_PD1_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DES_PD1_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PD8 +#define ISP_PRE_FILT_IR_DES_PD8_MASK (0xff << 24 ) +#define ISP_PRE_FILT_IR_DES_PD8_SHIFT 24U + +#define ISP_PRE_FILT_IR_DES_PD7 +#define ISP_PRE_FILT_IR_DES_PD7_MASK (0xff << 16 ) +#define ISP_PRE_FILT_IR_DES_PD7_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PD6 +#define ISP_PRE_FILT_IR_DES_PD6_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DES_PD6_SHIFT 8U + +#define ISP_PRE_FILT_IR_DES_PD5 +#define ISP_PRE_FILT_IR_DES_PD5_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DES_PD5_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PD12 +#define ISP_PRE_FILT_IR_DES_PD12_MASK (0xff << 24 ) +#define ISP_PRE_FILT_IR_DES_PD12_SHIFT 24U + +#define ISP_PRE_FILT_IR_DES_PD11 +#define ISP_PRE_FILT_IR_DES_PD11_MASK (0xff << 16 ) +#define ISP_PRE_FILT_IR_DES_PD11_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PD10 +#define ISP_PRE_FILT_IR_DES_PD10_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DES_PD10_SHIFT 8U + +#define ISP_PRE_FILT_IR_DES_PD9 +#define ISP_PRE_FILT_IR_DES_PD9_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DES_PD9_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PD15 +#define ISP_PRE_FILT_IR_DES_PD15_MASK (0xff << 16 ) +#define ISP_PRE_FILT_IR_DES_PD15_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PD14 +#define ISP_PRE_FILT_IR_DES_PD14_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DES_PD14_SHIFT 8U + +#define ISP_PRE_FILT_IR_DES_PD13 +#define ISP_PRE_FILT_IR_DES_PD13_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DES_PD13_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PX1 +#define ISP_PRE_FILT_L_DES_PX1_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PX1_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY2 +#define ISP_PRE_FILT_L_DES_PY2_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY2_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY1 +#define ISP_PRE_FILT_L_DES_PY1_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY1_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY4 +#define ISP_PRE_FILT_L_DES_PY4_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY4_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY3 +#define ISP_PRE_FILT_L_DES_PY3_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY3_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY6 +#define ISP_PRE_FILT_L_DES_PY6_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY6_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY5 +#define ISP_PRE_FILT_L_DES_PY5_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY5_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY8 +#define ISP_PRE_FILT_L_DES_PY8_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY8_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY7 +#define ISP_PRE_FILT_L_DES_PY7_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY7_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY10 +#define ISP_PRE_FILT_L_DES_PY10_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY10_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY9 +#define ISP_PRE_FILT_L_DES_PY9_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY9_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY12 +#define ISP_PRE_FILT_L_DES_PY12_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY12_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY11 +#define ISP_PRE_FILT_L_DES_PY11_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY11_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY14 +#define ISP_PRE_FILT_L_DES_PY14_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY14_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY13 +#define ISP_PRE_FILT_L_DES_PY13_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY13_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY16 +#define ISP_PRE_FILT_L_DES_PY16_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY16_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY15 +#define ISP_PRE_FILT_L_DES_PY15_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY15_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PD4 +#define ISP_PRE_FILT_L_DES_PD4_MASK (0xff << 24 ) +#define ISP_PRE_FILT_L_DES_PD4_SHIFT 24U + +#define ISP_PRE_FILT_L_DES_PD3 +#define ISP_PRE_FILT_L_DES_PD3_MASK (0xff << 16 ) +#define ISP_PRE_FILT_L_DES_PD3_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PD2 +#define ISP_PRE_FILT_L_DES_PD2_MASK (0xff << 8 ) +#define ISP_PRE_FILT_L_DES_PD2_SHIFT 8U + +#define ISP_PRE_FILT_L_DES_PD1 +#define ISP_PRE_FILT_L_DES_PD1_MASK (0xff << 0 ) +#define ISP_PRE_FILT_L_DES_PD1_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PD8 +#define ISP_PRE_FILT_L_DES_PD8_MASK (0xff << 24 ) +#define ISP_PRE_FILT_L_DES_PD8_SHIFT 24U + +#define ISP_PRE_FILT_L_DES_PD7 +#define ISP_PRE_FILT_L_DES_PD7_MASK (0xff << 16 ) +#define ISP_PRE_FILT_L_DES_PD7_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PD6 +#define ISP_PRE_FILT_L_DES_PD6_MASK (0xff << 8 ) +#define ISP_PRE_FILT_L_DES_PD6_SHIFT 8U + +#define ISP_PRE_FILT_L_DES_PD5 +#define ISP_PRE_FILT_L_DES_PD5_MASK (0xff << 0 ) +#define ISP_PRE_FILT_L_DES_PD5_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PD12 +#define ISP_PRE_FILT_L_DES_PD12_MASK (0xff << 24 ) +#define ISP_PRE_FILT_L_DES_PD12_SHIFT 24U + +#define ISP_PRE_FILT_L_DES_PD11 +#define ISP_PRE_FILT_L_DES_PD11_MASK (0xff << 16 ) +#define ISP_PRE_FILT_L_DES_PD11_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PD10 +#define ISP_PRE_FILT_L_DES_PD10_MASK (0xff << 8 ) +#define ISP_PRE_FILT_L_DES_PD10_SHIFT 8U + +#define ISP_PRE_FILT_L_DES_PD9 +#define ISP_PRE_FILT_L_DES_PD9_MASK (0xff << 0 ) +#define ISP_PRE_FILT_L_DES_PD9_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PD15 +#define ISP_PRE_FILT_L_DES_PD15_MASK (0xff << 16 ) +#define ISP_PRE_FILT_L_DES_PD15_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PD14 +#define ISP_PRE_FILT_L_DES_PD14_MASK (0xff << 8 ) +#define ISP_PRE_FILT_L_DES_PD14_SHIFT 8U + +#define ISP_PRE_FILT_L_DES_PD13 +#define ISP_PRE_FILT_L_DES_PD13_MASK (0xff << 0 ) +#define ISP_PRE_FILT_L_DES_PD13_SHIFT 0U + +#define PREFILT_THRESH_BL0 +#define PREFILT_THRESH_BL0_MASK (0x3ff << 0 ) +#define PREFILT_THRESH_BL0_SHIFT 0U + +#define PREFILT_THRESH_BL1 +#define PREFILT_THRESH_BL1_MASK (0x3ff << 0 ) +#define PREFILT_THRESH_BL1_SHIFT 0U + +#define PREFILT_THRESH_SH0 +#define PREFILT_THRESH_SH0_MASK (0x3ff << 0 ) +#define PREFILT_THRESH_SH0_SHIFT 0U + +#define PREFILT_THRESH_SH1 +#define PREFILT_THRESH_SH1_MASK (0x3ff << 0 ) +#define PREFILT_THRESH_SH1_SHIFT 0U + +#define LUM_WEIGHT_GAIN +#define LUM_WEIGHT_GAIN_MASK (0x7 << 16 ) +#define LUM_WEIGHT_GAIN_SHIFT 16U + +#define LUM_WEIGHT_KINK +#define LUM_WEIGHT_KINK_MASK (0xff << 8 ) +#define LUM_WEIGHT_KINK_SHIFT 8U + +#define LUM_WEIGHT_MIN +#define LUM_WEIGHT_MIN_MASK (0xff << 0 ) +#define LUM_WEIGHT_MIN_SHIFT 0U + +#define PREFILT_FAC_SH1 +#define PREFILT_FAC_SH1_MASK (0x3f << 0 ) +#define PREFILT_FAC_SH1_SHIFT 0U + +#define PREFILT_FAC_SH0 +#define PREFILT_FAC_SH0_MASK (0x3f << 0 ) +#define PREFILT_FAC_SH0_SHIFT 0U + +#define PREFILT_FAC_MID +#define PREFILT_FAC_MID_MASK (0x3f << 0 ) +#define PREFILT_FAC_MID_SHIFT 0U + +#define PREFILT_FAC_BL0 +#define PREFILT_FAC_BL0_MASK (0x3f << 0 ) +#define PREFILT_FAC_BL0_SHIFT 0U + +#define PREFILT_FAC_BL1 +#define PREFILT_FAC_BL1_MASK (0x3f << 0 ) +#define PREFILT_FAC_BL1_SHIFT 0U + +#define ISP_PRE_FILT_IR_DENOISE_SW3 +#define ISP_PRE_FILT_IR_DENOISE_SW3_MASK (0xff << 24 ) +#define ISP_PRE_FILT_IR_DENOISE_SW3_SHIFT 24U + +#define ISP_PRE_FILT_IR_DENOISE_SW2 +#define ISP_PRE_FILT_IR_DENOISE_SW2_MASK (0xff << 16 ) +#define ISP_PRE_FILT_IR_DENOISE_SW2_SHIFT 16U + +#define ISP_PRE_FILT_IR_DENOISE_SW1 +#define ISP_PRE_FILT_IR_DENOISE_SW1_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DENOISE_SW1_SHIFT 8U + +#define ISP_PRE_FILT_IR_DENOISE_SW0 +#define ISP_PRE_FILT_IR_DENOISE_SW0_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DENOISE_SW0_SHIFT 0U + +#define ISP_PRE_FILT_IR_DENOISE_SW5 +#define ISP_PRE_FILT_IR_DENOISE_SW5_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DENOISE_SW5_SHIFT 8U + +#define ISP_PRE_FILT_IR_DENOISE_SW4 +#define ISP_PRE_FILT_IR_DENOISE_SW4_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DENOISE_SW4_SHIFT 0U + +#define PRE_FILT_H_SIZE +#define PRE_FILT_H_SIZE_MASK (0x7fff << 0 ) +#define PRE_FILT_H_SIZE_SHIFT 0U + +#define PRE_FILT_V_SIZE +#define PRE_FILT_V_SIZE_MASK (0x3fff << 0 ) +#define PRE_FILT_V_SIZE_SHIFT 0U + +#define PRE_FILT_DMY_HB +#define PRE_FILT_DMY_HB_MASK (0x1fff << 0 ) +#define PRE_FILT_DMY_HB_SHIFT 0U + + +#define SP2_DMA_RAW_WIDTH_BYTES +#define SP2_DMA_RAW_WIDTH_BYTES_MASK (0xffff << 0 ) +#define SP2_DMA_RAW_WIDTH_BYTES_SHIFT 0U + +#define PPW_Y_BUF_FULL +#define PPW_Y_BUF_FULL_MASK (0x1 << 26) +#define PPW_Y_BUF_FULL_SHIFT 26U + +#define PPW_U_BUF_FULL +#define PPW_U_BUF_FULL_MASK (0x1 << 25) +#define PPW_U_BUF_FULL_SHIFT 25U + +#define PPW_V_BUF_FULL +#define PPW_V_BUF_FULL_MASK (0x1 << 24) +#define PPW_V_BUF_FULL_SHIFT 24U + +#define PPR_Y_BUF_FULL +#define PPR_Y_BUF_FULL_MASK (0x1 << 23) +#define PPR_Y_BUF_FULL_SHIFT 23U + +#define SP2_RAW2_W_BUF_FULL +#define SP2_RAW2_W_BUF_FULL_MASK (0x1 << 22) +#define SP2_RAW2_W_BUF_FULL_SHIFT 22U + +#define SP2_RAW2_R_BUF_FULL +#define SP2_RAW2_R_BUF_FULL_MASK (0x1 << 21) +#define SP2_RAW2_R_BUF_FULL_SHIFT 21U + +#define HDR_W_BUF_FULL +#define HDR_W_BUF_FULL_MASK (0x1 << 20) +#define HDR_W_BUF_FULL_SHIFT 20U + +#define HDR_R_BUF_FULL +#define HDR_R_BUF_FULL_MASK (0x1 << 19) +#define HDR_R_BUF_FULL_SHIFT 19U + +#define SP2_RAW2_DMA_READY +#define SP2_RAW2_DMA_READY_MASK (0x1 << 18) +#define SP2_RAW2_DMA_READY_SHIFT 18U + +#define PPR_DMA_READY +#define PPR_DMA_READY_MASK (0x1 << 17) +#define PPR_DMA_READY_SHIFT 17U + +#define WRAP_PPW_CR +#define WRAP_PPW_CR_MASK (0x1 << 15) +#define WRAP_PPW_CR_SHIFT 15U + +#define WRAP_PPW_CB +#define WRAP_PPW_CB_MASK (0x1 << 14) +#define WRAP_PPW_CB_SHIFT 14U + +#define WRAP_PPW_Y +#define WRAP_PPW_Y_MASK (0x1 << 13) +#define WRAP_PPW_Y_SHIFT 13U + +#define SP2_RAW2_FRAME_END +#define SP2_RAW2_FRAME_END_MASK (0x1 << 12) +#define SP2_RAW2_FRAME_END_SHIFT 12U + +#define PPW_FRAME_END +#define PPW_FRAME_END_MASK (0x1 << 11) +#define PPW_FRAME_END_SHIFT 11U + +#define HDR_VS_DMA_READY +#define HDR_VS_DMA_READY_MASK (0x1 << 10) +#define HDR_VS_DMA_READY_SHIFT 10U + +#define HDR_S_DMA_READY +#define HDR_S_DMA_READY_MASK (0x1 << 9) +#define HDR_S_DMA_READY_SHIFT 9U + +#define HDR_L_DMA_READY +#define HDR_L_DMA_READY_MASK (0x1 << 8) +#define HDR_L_DMA_READY_SHIFT 8U + +#define WRAP_HDR_VS +#define WRAP_HDR_VS_MASK (0x1 << 7) +#define WRAP_HDR_VS_SHIFT 7U + +#define WRAP_HDR_S +#define WRAP_HDR_S_MASK (0x1 << 6) +#define WRAP_HDR_S_SHIFT 6U + +#define WRAP_HDR_L +#define WRAP_HDR_L_MASK (0x1 << 5) +#define WRAP_HDR_L_SHIFT 5U + +#define HDR_VS_FRAME_END +#define HDR_VS_FRAME_END_MASK (0x1 << 4) +#define HDR_VS_FRAME_END_SHIFT 4U + +#define HDR_S_FRAME_END +#define HDR_S_FRAME_END_MASK (0x1 << 3) +#define HDR_S_FRAME_END_SHIFT 3U + +#define HDR_L_FRAME_END +#define HDR_L_FRAME_END_MASK (0x1 << 2) +#define HDR_L_FRAME_END_SHIFT 2U + +#define MI_RT_BUS_BUSERR +#define MI_RT_BUS_BUSERR_MASK (0x1 << 1) +#define MI_RT_BUS_BUSERR_SHIFT 1U + +#define MI_RT_BUS_TIMEO +#define MI_RT_BUS_TIMEO_MASK (0x1 << 0) +#define MI_RT_BUS_TIMEO_SHIFT 0U + +#endif /* _MRV_ALL_REGS_H */ diff --git a/vvcam/isp/mrv_dec_all_regs.h b/vvcam/isp/mrv_dec_all_regs.h new file mode 100755 index 0000000..c4b6fcf --- /dev/null +++ b/vvcam/isp/mrv_dec_all_regs.h @@ -0,0 +1,1148 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +/** +*----------------------------------------------------------------------------- +* $HeadURL$ +* $Author$ +* $Rev$ +* $Date$ +*----------------------------------------------------------------------------- +* @file mrv_dec_all_regs.h +* +* 
+*
+* Description:
+*   This header file exports the module register structure and masks.
+*   it should not be included directly by your driver/application, it will be
+*   exported by the _regs_io.h header file.
+*
+*
+*/ +/*****************************************************************************/ + +#ifndef _MRV_DEC_ALL_REGS_H +#define _MRV_DEC_ALL_REGS_H + +/*! Mrv Dec All Register layout */ +typedef struct { + uint32_t _notused_0[(0x24 - 0x00) / 4]; + uint32_t isp_dec_chipRev; /*!<(r) */ + uint32_t isp_dec_chipDate; /*!<(r) */ + uint32_t _notused_1[(0x98 - 0x2c) / 4]; + uint32_t isp_dec_hichipPatchRev; /*!<(r) */ + uint32_t _notused_2[(0xA8 - 0x9c) / 4]; + uint32_t isp_dec_productId; /*!<(r) */ + + uint32_t _notused_3[(0x800 - 0xAc) / 4]; + uint32_t isp_dec_ctrl; /*!<(rw), DEC_BASE + 0x00000000 */ + uint32_t isp_dec_ctrl_ex; /*!<(rw), DEC_BASE + 0x00000004 */ + uint32_t isp_dec_ctrl_ex2; /*!<(rw), DEC_BASE + 0x00000008 */ + uint32_t isp_dec_intr_enbl; /*!<(rw), DEC_BASE + 0x0000000C */ + uint32_t isp_dec_intr_enbl_ex; /*!<(rw), DEC_BASE + 0x00000010 */ + uint32_t isp_dec_intr_enbl_ex2; /*!<(rw), DEC_BASE + 0x00000014 */ + uint32_t isp_dec_intr_acknowledge; /*!<(ro), DEC_BASE + 0x00000018 */ + uint32_t isp_dec_intr_acknowledge_ex; /*!<(ro), DEC_BASE + 0x0000001C */ + uint32_t isp_dec_intr_acknowledge_ex2; /*!<(ro), DEC_BASE + 0x00000020 */ + uint32_t isp_dec_tile_status_debug; /*!<(ro), DEC_BASE + 0x00000024 */ + uint32_t isp_dec_encoder_debug; /*!<(ro), DEC_BASE + 0x00000028 */ + uint32_t isp_dec_decoder_debug; /*!<(ro), DEC_BASE + 0x0000002C */ + uint32_t isp_dec_total_reads_in; /*!<(ro), DEC_BASE + 0x00000030 */ + uint32_t isp_dec_total_writes_in; /*!<(ro), DEC_BASE + 0x00000034 */ + uint32_t isp_dec_total_read_bursts_in; /*!<(ro), DEC_BASE + 0x00000038 */ + uint32_t isp_dec_total_write_bursts_in; /*!<(ro), DEC_BASE + 0x0000003C */ + uint32_t isp_dec_total_read_reqs_in; /*!<(ro), DEC_BASE + 0x00000040 */ + uint32_t isp_dec_total_write_reqs_in; /*!<(ro), DEC_BASE + 0x00000044 */ + uint32_t isp_dec_total_read_lasts_in; /*!<(ro), DEC_BASE + 0x00000048 */ + uint32_t isp_dec_total_write_lasts_in; /*!<(ro), DEC_BASE + 0x0000004C */ + uint32_t isp_dec_total_write_response_in; /*!<(ro), DEC_BASE + 0x00000050 */ + uint32_t isp_dec_total_reads_out; /*!<(ro), DEC_BASE + 0x00000054 */ + uint32_t isp_dec_total_writes_out; /*!<(ro), DEC_BASE + 0x00000058 */ + uint32_t isp_dec_total_read_bursts_out; /*!<(ro), DEC_BASE + 0x0000005C */ + uint32_t isp_dec_total_write_bursts_out; /*!<(ro), DEC_BASE + 0x00000060 */ + uint32_t isp_dec_total_read_reqs_out; /*!<(ro), DEC_BASE + 0x00000064 */ + uint32_t isp_dec_total_write_reqs_out; /*!<(ro), DEC_BASE + 0x00000068 */ + uint32_t isp_dec_total_read_lasts_out; /*!<(ro), DEC_BASE + 0x0000006C */ + uint32_t isp_dec_total_write_lasts_out; /*!<(ro), DEC_BASE + 0x00000070 */ + uint32_t isp_dec_total_write_response_out; /*!<(ro), DEC_BASE + 0x00000074 */ + uint32_t isp_dec_status; /*!<(ro), DEC_BASE + 0x00000078 */ + uint32_t isp_dec_debug_info_select; /*!<(rw), DEC_BASE + 0x0000007C */ + uint32_t isp_dec_read_config_0; /*!<(rw), DEC_BASE + 0x00000080 */ + uint32_t isp_dec_read_config_1; /*!<(rw), DEC_BASE + 0x00000084 */ + uint32_t isp_dec_read_config_2; /*!<(rw), DEC_BASE + 0x00000088 */ + uint32_t isp_dec_read_config_3; /*!<(rw), DEC_BASE + 0x0000008C */ + uint32_t isp_dec_read_config_4; /*!<(rw), DEC_BASE + 0x00000090 */ + uint32_t isp_dec_read_config_5; /*!<(rw), DEC_BASE + 0x00000094 */ + uint32_t isp_dec_read_config_6; /*!<(rw), DEC_BASE + 0x00000098 */ + uint32_t isp_dec_read_config_7; /*!<(rw), DEC_BASE + 0x0000009C */ + uint32_t isp_dec_read_config_8; /*!<(rw), DEC_BASE + 0x000000A0 */ + uint32_t isp_dec_read_config_9; /*!<(rw), DEC_BASE + 0x000000A4 */ + uint32_t isp_dec_read_config_10; /*!<(rw), DEC_BASE + 0x000000A8 */ + uint32_t isp_dec_read_config_11; /*!<(rw), DEC_BASE + 0x000000AC */ + uint32_t isp_dec_read_config_12; /*!<(rw), DEC_BASE + 0x000000B0 */ + uint32_t isp_dec_read_config_13; /*!<(rw), DEC_BASE + 0x000000B4 */ + uint32_t isp_dec_read_config_14; /*!<(rw), DEC_BASE + 0x000000B8 */ + uint32_t isp_dec_read_config_15; /*!<(rw), DEC_BASE + 0x000000BC */ + uint32_t isp_dec_read_config_16; /*!<(rw), DEC_BASE + 0x000000C0 */ + uint32_t isp_dec_read_config_17; /*!<(rw), DEC_BASE + 0x000000C4 */ + uint32_t isp_dec_read_config_18; /*!<(rw), DEC_BASE + 0x000000C8 */ + uint32_t isp_dec_read_config_19; /*!<(rw), DEC_BASE + 0x000000CC */ + uint32_t isp_dec_read_config_20; /*!<(rw), DEC_BASE + 0x000000D0 */ + uint32_t isp_dec_read_config_21; /*!<(rw), DEC_BASE + 0x000000D4 */ + uint32_t isp_dec_read_config_22; /*!<(rw), DEC_BASE + 0x000000D8 */ + uint32_t isp_dec_read_config_23; /*!<(rw), DEC_BASE + 0x000000DC */ + uint32_t isp_dec_read_config_24; /*!<(rw), DEC_BASE + 0x000000E0 */ + uint32_t isp_dec_read_config_25; /*!<(rw), DEC_BASE + 0x000000E4 */ + uint32_t isp_dec_read_config_26; /*!<(rw), DEC_BASE + 0x000000E8 */ + uint32_t isp_dec_read_config_27; /*!<(rw), DEC_BASE + 0x000000EC */ + uint32_t isp_dec_read_config_28; /*!<(rw), DEC_BASE + 0x000000F0 */ + uint32_t isp_dec_read_config_29; /*!<(rw), DEC_BASE + 0x000000F4 */ + uint32_t isp_dec_read_config_30; /*!<(rw), DEC_BASE + 0x000000F8 */ + uint32_t isp_dec_read_config_31; /*!<(rw), DEC_BASE + 0x000000FC */ + uint32_t isp_dec_read_ex_config_0; /*!<(rw), DEC_BASE + 0x00000100 */ + uint32_t isp_dec_read_ex_config_1; /*!<(rw), DEC_BASE + 0x00000104 */ + uint32_t isp_dec_read_ex_config_2; /*!<(rw), DEC_BASE + 0x00000108 */ + uint32_t isp_dec_read_ex_config_3; /*!<(rw), DEC_BASE + 0x0000010C */ + uint32_t isp_dec_read_ex_config_4; /*!<(rw), DEC_BASE + 0x00000110 */ + uint32_t isp_dec_read_ex_config_5; /*!<(rw), DEC_BASE + 0x00000114 */ + uint32_t isp_dec_read_ex_config_6; /*!<(rw), DEC_BASE + 0x00000118 */ + uint32_t isp_dec_read_ex_config_7; /*!<(rw), DEC_BASE + 0x0000011C */ + uint32_t isp_dec_read_ex_config_8; /*!<(rw), DEC_BASE + 0x00000120 */ + uint32_t isp_dec_read_ex_config_9; /*!<(rw), DEC_BASE + 0x00000124 */ + uint32_t isp_dec_read_ex_config_10; /*!<(rw), DEC_BASE + 0x00000128 */ + uint32_t isp_dec_read_ex_config_11; /*!<(rw), DEC_BASE + 0x0000012C */ + uint32_t isp_dec_read_ex_config_12; /*!<(rw), DEC_BASE + 0x00000130 */ + uint32_t isp_dec_read_ex_config_13; /*!<(rw), DEC_BASE + 0x00000134 */ + uint32_t isp_dec_read_ex_config_14; /*!<(rw), DEC_BASE + 0x00000138 */ + uint32_t isp_dec_read_ex_config_15; /*!<(rw), DEC_BASE + 0x0000013C */ + uint32_t isp_dec_read_ex_config_16; /*!<(rw), DEC_BASE + 0x00000140 */ + uint32_t isp_dec_read_ex_config_17; /*!<(rw), DEC_BASE + 0x00000144 */ + uint32_t isp_dec_read_ex_config_18; /*!<(rw), DEC_BASE + 0x00000148 */ + uint32_t isp_dec_read_ex_config_19; /*!<(rw), DEC_BASE + 0x0000014C */ + uint32_t isp_dec_read_ex_config_20; /*!<(rw), DEC_BASE + 0x00000150 */ + uint32_t isp_dec_read_ex_config_21; /*!<(rw), DEC_BASE + 0x00000154 */ + uint32_t isp_dec_read_ex_config_22; /*!<(rw), DEC_BASE + 0x00000158 */ + uint32_t isp_dec_read_ex_config_23; /*!<(rw), DEC_BASE + 0x0000015C */ + uint32_t isp_dec_read_ex_config_24; /*!<(rw), DEC_BASE + 0x00000160 */ + uint32_t isp_dec_read_ex_config_25; /*!<(rw), DEC_BASE + 0x00000164 */ + uint32_t isp_dec_read_ex_config_26; /*!<(rw), DEC_BASE + 0x00000168 */ + uint32_t isp_dec_read_ex_config_27; /*!<(rw), DEC_BASE + 0x0000016C */ + uint32_t isp_dec_read_ex_config_28; /*!<(rw), DEC_BASE + 0x00000170 */ + uint32_t isp_dec_read_ex_config_29; /*!<(rw), DEC_BASE + 0x00000174 */ + uint32_t isp_dec_read_ex_config_30; /*!<(rw), DEC_BASE + 0x00000178 */ + uint32_t isp_dec_read_ex_config_31; /*!<(rw), DEC_BASE + 0x0000017C */ + uint32_t isp_dec_write_config_0; /*!<(rw), DEC_BASE + 0x00000180 */ + uint32_t isp_dec_write_config_1; /*!<(rw), DEC_BASE + 0x00000184 */ + uint32_t isp_dec_write_config_2; /*!<(rw), DEC_BASE + 0x00000188 */ + uint32_t isp_dec_write_config_3; /*!<(rw), DEC_BASE + 0x0000018C */ + uint32_t isp_dec_write_config_4; /*!<(rw), DEC_BASE + 0x00000190 */ + uint32_t isp_dec_write_config_5; /*!<(rw), DEC_BASE + 0x00000194 */ + uint32_t isp_dec_write_config_6; /*!<(rw), DEC_BASE + 0x00000198 */ + uint32_t isp_dec_write_config_7; /*!<(rw), DEC_BASE + 0x0000019C */ + uint32_t isp_dec_write_config_8; /*!<(rw), DEC_BASE + 0x000001A0 */ + uint32_t isp_dec_write_config_9; /*!<(rw), DEC_BASE + 0x000001A4 */ + uint32_t isp_dec_write_config_10; /*!<(rw), DEC_BASE + 0x000001A8 */ + uint32_t isp_dec_write_config_11; /*!<(rw), DEC_BASE + 0x000001AC */ + uint32_t isp_dec_write_config_12; /*!<(rw), DEC_BASE + 0x000001B0 */ + uint32_t isp_dec_write_config_13; /*!<(rw), DEC_BASE + 0x000001B4 */ + uint32_t isp_dec_write_config_14; /*!<(rw), DEC_BASE + 0x000001B8 */ + uint32_t isp_dec_write_config_15; /*!<(rw), DEC_BASE + 0x000001BC */ + uint32_t isp_dec_write_config_16; /*!<(rw), DEC_BASE + 0x000001C0 */ + uint32_t isp_dec_write_config_17; /*!<(rw), DEC_BASE + 0x000001C4 */ + uint32_t isp_dec_write_config_18; /*!<(rw), DEC_BASE + 0x000001C8 */ + uint32_t isp_dec_write_config_19; /*!<(rw), DEC_BASE + 0x000001CC */ + uint32_t isp_dec_write_config_20; /*!<(rw), DEC_BASE + 0x000001D0 */ + uint32_t isp_dec_write_config_21; /*!<(rw), DEC_BASE + 0x000001D4 */ + uint32_t isp_dec_write_config_22; /*!<(rw), DEC_BASE + 0x000001D8 */ + uint32_t isp_dec_write_config_23; /*!<(rw), DEC_BASE + 0x000001DC */ + uint32_t isp_dec_write_config_24; /*!<(rw), DEC_BASE + 0x000001E0 */ + uint32_t isp_dec_write_config_25; /*!<(rw), DEC_BASE + 0x000001E4 */ + uint32_t isp_dec_write_config_26; /*!<(rw), DEC_BASE + 0x000001E8 */ + uint32_t isp_dec_write_config_27; /*!<(rw), DEC_BASE + 0x000001EC */ + uint32_t isp_dec_write_config_28; /*!<(rw), DEC_BASE + 0x000001F0 */ + uint32_t isp_dec_write_config_29; /*!<(rw), DEC_BASE + 0x000001F4 */ + uint32_t isp_dec_write_config_30; /*!<(rw), DEC_BASE + 0x000001F8 */ + uint32_t isp_dec_write_config_31; /*!<(rw), DEC_BASE + 0x000001FC */ + uint32_t isp_dec_write_ex_config_0; /*!<(rw), DEC_BASE + 0x00000200 */ + uint32_t isp_dec_write_ex_config_1; /*!<(rw), DEC_BASE + 0x00000204 */ + uint32_t isp_dec_write_ex_config_2; /*!<(rw), DEC_BASE + 0x00000208 */ + uint32_t isp_dec_write_ex_config_3; /*!<(rw), DEC_BASE + 0x0000020C */ + uint32_t isp_dec_write_ex_config_4; /*!<(rw), DEC_BASE + 0x00000210 */ + uint32_t isp_dec_write_ex_config_5; /*!<(rw), DEC_BASE + 0x00000214 */ + uint32_t isp_dec_write_ex_config_6; /*!<(rw), DEC_BASE + 0x00000218 */ + uint32_t isp_dec_write_ex_config_7; /*!<(rw), DEC_BASE + 0x0000021C */ + uint32_t isp_dec_write_ex_config_8; /*!<(rw), DEC_BASE + 0x00000220 */ + uint32_t isp_dec_write_ex_config_9; /*!<(rw), DEC_BASE + 0x00000224 */ + uint32_t isp_dec_write_ex_config_10; /*!<(rw), DEC_BASE + 0x00000228 */ + uint32_t isp_dec_write_ex_config_11; /*!<(rw), DEC_BASE + 0x0000022C */ + uint32_t isp_dec_write_ex_config_12; /*!<(rw), DEC_BASE + 0x00000230 */ + uint32_t isp_dec_write_ex_config_13; /*!<(rw), DEC_BASE + 0x00000234 */ + uint32_t isp_dec_write_ex_config_14; /*!<(rw), DEC_BASE + 0x00000238 */ + uint32_t isp_dec_write_ex_config_15; /*!<(rw), DEC_BASE + 0x0000023C */ + uint32_t isp_dec_write_ex_config_16; /*!<(rw), DEC_BASE + 0x00000240 */ + uint32_t isp_dec_write_ex_config_17; /*!<(rw), DEC_BASE + 0x00000244 */ + uint32_t isp_dec_write_ex_config_18; /*!<(rw), DEC_BASE + 0x00000248 */ + uint32_t isp_dec_write_ex_config_19; /*!<(rw), DEC_BASE + 0x0000024C */ + uint32_t isp_dec_write_ex_config_20; /*!<(rw), DEC_BASE + 0x00000250 */ + uint32_t isp_dec_write_ex_config_21; /*!<(rw), DEC_BASE + 0x00000254 */ + uint32_t isp_dec_write_ex_config_22; /*!<(rw), DEC_BASE + 0x00000258 */ + uint32_t isp_dec_write_ex_config_23; /*!<(rw), DEC_BASE + 0x0000025C */ + uint32_t isp_dec_write_ex_config_24; /*!<(rw), DEC_BASE + 0x00000260 */ + uint32_t isp_dec_write_ex_config_25; /*!<(rw), DEC_BASE + 0x00000264 */ + uint32_t isp_dec_write_ex_config_26; /*!<(rw), DEC_BASE + 0x00000268 */ + uint32_t isp_dec_write_ex_config_27; /*!<(rw), DEC_BASE + 0x0000026C */ + uint32_t isp_dec_write_ex_config_28; /*!<(rw), DEC_BASE + 0x00000270 */ + uint32_t isp_dec_write_ex_config_29; /*!<(rw), DEC_BASE + 0x00000274 */ + uint32_t isp_dec_write_ex_config_30; /*!<(rw), DEC_BASE + 0x00000278 */ + uint32_t isp_dec_write_ex_config_31; /*!<(rw), DEC_BASE + 0x0000027C */ + uint32_t isp_dec_read_buffer_base_0; /*!<(rw), DEC_BASE + 0x00000280 */ + uint32_t isp_dec_read_buffer_base_1; /*!<(rw), DEC_BASE + 0x00000284 */ + uint32_t isp_dec_read_buffer_base_2; /*!<(rw), DEC_BASE + 0x00000288 */ + uint32_t isp_dec_read_buffer_base_3; /*!<(rw), DEC_BASE + 0x0000028C */ + uint32_t isp_dec_read_buffer_base_4; /*!<(rw), DEC_BASE + 0x00000290 */ + uint32_t isp_dec_read_buffer_base_5; /*!<(rw), DEC_BASE + 0x00000294 */ + uint32_t isp_dec_read_buffer_base_6; /*!<(rw), DEC_BASE + 0x00000298 */ + uint32_t isp_dec_read_buffer_base_7; /*!<(rw), DEC_BASE + 0x0000029C */ + uint32_t isp_dec_read_buffer_base_8; /*!<(rw), DEC_BASE + 0x000002A0 */ + uint32_t isp_dec_read_buffer_base_9; /*!<(rw), DEC_BASE + 0x000002A4 */ + uint32_t isp_dec_read_buffer_base_10; /*!<(rw), DEC_BASE + 0x000002A8 */ + uint32_t isp_dec_read_buffer_base_11; /*!<(rw), DEC_BASE + 0x000002AC */ + uint32_t isp_dec_read_buffer_base_12; /*!<(rw), DEC_BASE + 0x000002B0 */ + uint32_t isp_dec_read_buffer_base_13; /*!<(rw), DEC_BASE + 0x000002B4 */ + uint32_t isp_dec_read_buffer_base_14; /*!<(rw), DEC_BASE + 0x000002B8 */ + uint32_t isp_dec_read_buffer_base_15; /*!<(rw), DEC_BASE + 0x000002BC */ + uint32_t isp_dec_read_buffer_base_16; /*!<(rw), DEC_BASE + 0x000002C0 */ + uint32_t isp_dec_read_buffer_base_17; /*!<(rw), DEC_BASE + 0x000002C4 */ + uint32_t isp_dec_read_buffer_base_18; /*!<(rw), DEC_BASE + 0x000002C8 */ + uint32_t isp_dec_read_buffer_base_19; /*!<(rw), DEC_BASE + 0x000002CC */ + uint32_t isp_dec_read_buffer_base_20; /*!<(rw), DEC_BASE + 0x000002D0 */ + uint32_t isp_dec_read_buffer_base_21; /*!<(rw), DEC_BASE + 0x000002D4 */ + uint32_t isp_dec_read_buffer_base_22; /*!<(rw), DEC_BASE + 0x000002D8 */ + uint32_t isp_dec_read_buffer_base_23; /*!<(rw), DEC_BASE + 0x000002DC */ + uint32_t isp_dec_read_buffer_base_24; /*!<(rw), DEC_BASE + 0x000002E0 */ + uint32_t isp_dec_read_buffer_base_25; /*!<(rw), DEC_BASE + 0x000002E4 */ + uint32_t isp_dec_read_buffer_base_26; /*!<(rw), DEC_BASE + 0x000002E8 */ + uint32_t isp_dec_read_buffer_base_27; /*!<(rw), DEC_BASE + 0x000002EC */ + uint32_t isp_dec_read_buffer_base_28; /*!<(rw), DEC_BASE + 0x000002F0 */ + uint32_t isp_dec_read_buffer_base_29; /*!<(rw), DEC_BASE + 0x000002F4 */ + uint32_t isp_dec_read_buffer_base_30; /*!<(rw), DEC_BASE + 0x000002F8 */ + uint32_t isp_dec_read_buffer_base_31; /*!<(rw), DEC_BASE + 0x000002FC */ + uint32_t isp_dec_read_buffer_base_ex_0; /*!<(rw), DEC_BASE + 0x00000300 */ + uint32_t isp_dec_read_buffer_base_ex_1; /*!<(rw), DEC_BASE + 0x00000304 */ + uint32_t isp_dec_read_buffer_base_ex_2; /*!<(rw), DEC_BASE + 0x00000308 */ + uint32_t isp_dec_read_buffer_base_ex_3; /*!<(rw), DEC_BASE + 0x0000030C */ + uint32_t isp_dec_read_buffer_base_ex_4; /*!<(rw), DEC_BASE + 0x00000310 */ + uint32_t isp_dec_read_buffer_base_ex_5; /*!<(rw), DEC_BASE + 0x00000314 */ + uint32_t isp_dec_read_buffer_base_ex_6; /*!<(rw), DEC_BASE + 0x00000318 */ + uint32_t isp_dec_read_buffer_base_ex_7; /*!<(rw), DEC_BASE + 0x0000031C */ + uint32_t isp_dec_read_buffer_base_ex_8; /*!<(rw), DEC_BASE + 0x00000320 */ + uint32_t isp_dec_read_buffer_base_ex_9; /*!<(rw), DEC_BASE + 0x00000324 */ + uint32_t isp_dec_read_buffer_base_ex_10; /*!<(rw), DEC_BASE + 0x00000328 */ + uint32_t isp_dec_read_buffer_base_ex_11; /*!<(rw), DEC_BASE + 0x0000032C */ + uint32_t isp_dec_read_buffer_base_ex_12; /*!<(rw), DEC_BASE + 0x00000330 */ + uint32_t isp_dec_read_buffer_base_ex_13; /*!<(rw), DEC_BASE + 0x00000334 */ + uint32_t isp_dec_read_buffer_base_ex_14; /*!<(rw), DEC_BASE + 0x00000338 */ + uint32_t isp_dec_read_buffer_base_ex_15; /*!<(rw), DEC_BASE + 0x0000033C */ + uint32_t isp_dec_read_buffer_base_ex_16; /*!<(rw), DEC_BASE + 0x00000340 */ + uint32_t isp_dec_read_buffer_base_ex_17; /*!<(rw), DEC_BASE + 0x00000344 */ + uint32_t isp_dec_read_buffer_base_ex_18; /*!<(rw), DEC_BASE + 0x00000348 */ + uint32_t isp_dec_read_buffer_base_ex_19; /*!<(rw), DEC_BASE + 0x0000034C */ + uint32_t isp_dec_read_buffer_base_ex_20; /*!<(rw), DEC_BASE + 0x00000350 */ + uint32_t isp_dec_read_buffer_base_ex_21; /*!<(rw), DEC_BASE + 0x00000354 */ + uint32_t isp_dec_read_buffer_base_ex_22; /*!<(rw), DEC_BASE + 0x00000358 */ + uint32_t isp_dec_read_buffer_base_ex_23; /*!<(rw), DEC_BASE + 0x0000035C */ + uint32_t isp_dec_read_buffer_base_ex_24; /*!<(rw), DEC_BASE + 0x00000360 */ + uint32_t isp_dec_read_buffer_base_ex_25; /*!<(rw), DEC_BASE + 0x00000364 */ + uint32_t isp_dec_read_buffer_base_ex_26; /*!<(rw), DEC_BASE + 0x00000368 */ + uint32_t isp_dec_read_buffer_base_ex_27; /*!<(rw), DEC_BASE + 0x0000036C */ + uint32_t isp_dec_read_buffer_base_ex_28; /*!<(rw), DEC_BASE + 0x00000370 */ + uint32_t isp_dec_read_buffer_base_ex_29; /*!<(rw), DEC_BASE + 0x00000374 */ + uint32_t isp_dec_read_buffer_base_ex_30; /*!<(rw), DEC_BASE + 0x00000378 */ + uint32_t isp_dec_read_buffer_base_ex_31; /*!<(rw), DEC_BASE + 0x0000037C */ + uint32_t isp_dec_read_buffer_end_0; /*!<(rw), DEC_BASE + 0x00000380 */ + uint32_t isp_dec_read_buffer_end_1; /*!<(rw), DEC_BASE + 0x00000384 */ + uint32_t isp_dec_read_buffer_end_2; /*!<(rw), DEC_BASE + 0x00000388 */ + uint32_t isp_dec_read_buffer_end_3; /*!<(rw), DEC_BASE + 0x0000038C */ + uint32_t isp_dec_read_buffer_end_4; /*!<(rw), DEC_BASE + 0x00000390 */ + uint32_t isp_dec_read_buffer_end_5; /*!<(rw), DEC_BASE + 0x00000394 */ + uint32_t isp_dec_read_buffer_end_6; /*!<(rw), DEC_BASE + 0x00000398 */ + uint32_t isp_dec_read_buffer_end_7; /*!<(rw), DEC_BASE + 0x0000039C */ + uint32_t isp_dec_read_buffer_end_8; /*!<(rw), DEC_BASE + 0x000003A0 */ + uint32_t isp_dec_read_buffer_end_9; /*!<(rw), DEC_BASE + 0x000003A4 */ + uint32_t isp_dec_read_buffer_end_10; /*!<(rw), DEC_BASE + 0x000003A8 */ + uint32_t isp_dec_read_buffer_end_11; /*!<(rw), DEC_BASE + 0x000003AC */ + uint32_t isp_dec_read_buffer_end_12; /*!<(rw), DEC_BASE + 0x000003B0 */ + uint32_t isp_dec_read_buffer_end_13; /*!<(rw), DEC_BASE + 0x000003B4 */ + uint32_t isp_dec_read_buffer_end_14; /*!<(rw), DEC_BASE + 0x000003B8 */ + uint32_t isp_dec_read_buffer_end_15; /*!<(rw), DEC_BASE + 0x000003BC */ + uint32_t isp_dec_read_buffer_end_16; /*!<(rw), DEC_BASE + 0x000003C0 */ + uint32_t isp_dec_read_buffer_end_17; /*!<(rw), DEC_BASE + 0x000003C4 */ + uint32_t isp_dec_read_buffer_end_18; /*!<(rw), DEC_BASE + 0x000003C8 */ + uint32_t isp_dec_read_buffer_end_19; /*!<(rw), DEC_BASE + 0x000003CC */ + uint32_t isp_dec_read_buffer_end_20; /*!<(rw), DEC_BASE + 0x000003D0 */ + uint32_t isp_dec_read_buffer_end_21; /*!<(rw), DEC_BASE + 0x000003D4 */ + uint32_t isp_dec_read_buffer_end_22; /*!<(rw), DEC_BASE + 0x000003D8 */ + uint32_t isp_dec_read_buffer_end_23; /*!<(rw), DEC_BASE + 0x000003DC */ + uint32_t isp_dec_read_buffer_end_24; /*!<(rw), DEC_BASE + 0x000003E0 */ + uint32_t isp_dec_read_buffer_end_25; /*!<(rw), DEC_BASE + 0x000003E4 */ + uint32_t isp_dec_read_buffer_end_26; /*!<(rw), DEC_BASE + 0x000003E8 */ + uint32_t isp_dec_read_buffer_end_27; /*!<(rw), DEC_BASE + 0x000003EC */ + uint32_t isp_dec_read_buffer_end_28; /*!<(rw), DEC_BASE + 0x000003F0 */ + uint32_t isp_dec_read_buffer_end_29; /*!<(rw), DEC_BASE + 0x000003F4 */ + uint32_t isp_dec_read_buffer_end_30; /*!<(rw), DEC_BASE + 0x000003F8 */ + uint32_t isp_dec_read_buffer_end_31; /*!<(rw), DEC_BASE + 0x000003FC */ + uint32_t isp_dec_read_buffer_end_ex_0; /*!<(rw), DEC_BASE + 0x00000400 */ + uint32_t isp_dec_read_buffer_end_ex_1; /*!<(rw), DEC_BASE + 0x00000404 */ + uint32_t isp_dec_read_buffer_end_ex_2; /*!<(rw), DEC_BASE + 0x00000408 */ + uint32_t isp_dec_read_buffer_end_ex_3; /*!<(rw), DEC_BASE + 0x0000040C */ + uint32_t isp_dec_read_buffer_end_ex_4; /*!<(rw), DEC_BASE + 0x00000410 */ + uint32_t isp_dec_read_buffer_end_ex_5; /*!<(rw), DEC_BASE + 0x00000414 */ + uint32_t isp_dec_read_buffer_end_ex_6; /*!<(rw), DEC_BASE + 0x00000418 */ + uint32_t isp_dec_read_buffer_end_ex_7; /*!<(rw), DEC_BASE + 0x0000041C */ + uint32_t isp_dec_read_buffer_end_ex_8; /*!<(rw), DEC_BASE + 0x00000420 */ + uint32_t isp_dec_read_buffer_end_ex_9; /*!<(rw), DEC_BASE + 0x00000424 */ + uint32_t isp_dec_read_buffer_end_ex_10; /*!<(rw), DEC_BASE + 0x00000428 */ + uint32_t isp_dec_read_buffer_end_ex_11; /*!<(rw), DEC_BASE + 0x0000042C */ + uint32_t isp_dec_read_buffer_end_ex_12; /*!<(rw), DEC_BASE + 0x00000430 */ + uint32_t isp_dec_read_buffer_end_ex_13; /*!<(rw), DEC_BASE + 0x00000434 */ + uint32_t isp_dec_read_buffer_end_ex_14; /*!<(rw), DEC_BASE + 0x00000438 */ + uint32_t isp_dec_read_buffer_end_ex_15; /*!<(rw), DEC_BASE + 0x0000043C */ + uint32_t isp_dec_read_buffer_end_ex_16; /*!<(rw), DEC_BASE + 0x00000440 */ + uint32_t isp_dec_read_buffer_end_ex_17; /*!<(rw), DEC_BASE + 0x00000444 */ + uint32_t isp_dec_read_buffer_end_ex_18; /*!<(rw), DEC_BASE + 0x00000448 */ + uint32_t isp_dec_read_buffer_end_ex_19; /*!<(rw), DEC_BASE + 0x0000044C */ + uint32_t isp_dec_read_buffer_end_ex_20; /*!<(rw), DEC_BASE + 0x00000450 */ + uint32_t isp_dec_read_buffer_end_ex_21; /*!<(rw), DEC_BASE + 0x00000454 */ + uint32_t isp_dec_read_buffer_end_ex_22; /*!<(rw), DEC_BASE + 0x00000458 */ + uint32_t isp_dec_read_buffer_end_ex_23; /*!<(rw), DEC_BASE + 0x0000045C */ + uint32_t isp_dec_read_buffer_end_ex_24; /*!<(rw), DEC_BASE + 0x00000460 */ + uint32_t isp_dec_read_buffer_end_ex_25; /*!<(rw), DEC_BASE + 0x00000464 */ + uint32_t isp_dec_read_buffer_end_ex_26; /*!<(rw), DEC_BASE + 0x00000468 */ + uint32_t isp_dec_read_buffer_end_ex_27; /*!<(rw), DEC_BASE + 0x0000046C */ + uint32_t isp_dec_read_buffer_end_ex_28; /*!<(rw), DEC_BASE + 0x00000470 */ + uint32_t isp_dec_read_buffer_end_ex_29; /*!<(rw), DEC_BASE + 0x00000474 */ + uint32_t isp_dec_read_buffer_end_ex_30; /*!<(rw), DEC_BASE + 0x00000478 */ + uint32_t isp_dec_read_buffer_end_ex_31; /*!<(rw), DEC_BASE + 0x0000047C */ + uint32_t isp_dec_read_flush_cache_0; /*!<(rw), DEC_BASE + 0x00000480 */ + uint32_t isp_dec_read_flush_cache_1; /*!<(rw), DEC_BASE + 0x00000484 */ + uint32_t isp_dec_read_flush_cache_2; /*!<(rw), DEC_BASE + 0x00000488 */ + uint32_t isp_dec_read_flush_cache_3; /*!<(rw), DEC_BASE + 0x0000048C */ + uint32_t isp_dec_read_flush_cache_4; /*!<(rw), DEC_BASE + 0x00000490 */ + uint32_t isp_dec_read_flush_cache_5; /*!<(rw), DEC_BASE + 0x00000494 */ + uint32_t isp_dec_read_flush_cache_6; /*!<(rw), DEC_BASE + 0x00000498 */ + uint32_t isp_dec_read_flush_cache_7; /*!<(rw), DEC_BASE + 0x0000049C */ + uint32_t isp_dec_read_flush_cache_8; /*!<(rw), DEC_BASE + 0x000004A0 */ + uint32_t isp_dec_read_flush_cache_9; /*!<(rw), DEC_BASE + 0x000004A4 */ + uint32_t isp_dec_read_flush_cache_10; /*!<(rw), DEC_BASE + 0x000004A8 */ + uint32_t isp_dec_read_flush_cache_11; /*!<(rw), DEC_BASE + 0x000004AC */ + uint32_t isp_dec_read_flush_cache_12; /*!<(rw), DEC_BASE + 0x000004B0 */ + uint32_t isp_dec_read_flush_cache_13; /*!<(rw), DEC_BASE + 0x000004B4 */ + uint32_t isp_dec_read_flush_cache_14; /*!<(rw), DEC_BASE + 0x000004B8 */ + uint32_t isp_dec_read_flush_cache_15; /*!<(rw), DEC_BASE + 0x000004BC */ + uint32_t isp_dec_read_flush_cache_16; /*!<(rw), DEC_BASE + 0x000004C0 */ + uint32_t isp_dec_read_flush_cache_17; /*!<(rw), DEC_BASE + 0x000004C4 */ + uint32_t isp_dec_read_flush_cache_18; /*!<(rw), DEC_BASE + 0x000004C8 */ + uint32_t isp_dec_read_flush_cache_19; /*!<(rw), DEC_BASE + 0x000004CC */ + uint32_t isp_dec_read_flush_cache_20; /*!<(rw), DEC_BASE + 0x000004D0 */ + uint32_t isp_dec_read_flush_cache_21; /*!<(rw), DEC_BASE + 0x000004D4 */ + uint32_t isp_dec_read_flush_cache_22; /*!<(rw), DEC_BASE + 0x000004D8 */ + uint32_t isp_dec_read_flush_cache_23; /*!<(rw), DEC_BASE + 0x000004DC */ + uint32_t isp_dec_read_flush_cache_24; /*!<(rw), DEC_BASE + 0x000004E0 */ + uint32_t isp_dec_read_flush_cache_25; /*!<(rw), DEC_BASE + 0x000004E4 */ + uint32_t isp_dec_read_flush_cache_26; /*!<(rw), DEC_BASE + 0x000004E8 */ + uint32_t isp_dec_read_flush_cache_27; /*!<(rw), DEC_BASE + 0x000004EC */ + uint32_t isp_dec_read_flush_cache_28; /*!<(rw), DEC_BASE + 0x000004F0 */ + uint32_t isp_dec_read_flush_cache_29; /*!<(rw), DEC_BASE + 0x000004F4 */ + uint32_t isp_dec_read_flush_cache_30; /*!<(rw), DEC_BASE + 0x000004F8 */ + uint32_t isp_dec_read_flush_cache_31; /*!<(rw), DEC_BASE + 0x000004FC */ + uint32_t isp_dec_read_flush_cache_ex_0; /*!<(rw), DEC_BASE + 0x00000500 */ + uint32_t isp_dec_read_flush_cache_ex_1; /*!<(rw), DEC_BASE + 0x00000504 */ + uint32_t isp_dec_read_flush_cache_ex_2; /*!<(rw), DEC_BASE + 0x00000508 */ + uint32_t isp_dec_read_flush_cache_ex_3; /*!<(rw), DEC_BASE + 0x0000050C */ + uint32_t isp_dec_read_flush_cache_ex_4; /*!<(rw), DEC_BASE + 0x00000510 */ + uint32_t isp_dec_read_flush_cache_ex_5; /*!<(rw), DEC_BASE + 0x00000514 */ + uint32_t isp_dec_read_flush_cache_ex_6; /*!<(rw), DEC_BASE + 0x00000518 */ + uint32_t isp_dec_read_flush_cache_ex_7; /*!<(rw), DEC_BASE + 0x0000051C */ + uint32_t isp_dec_read_flush_cache_ex_8; /*!<(rw), DEC_BASE + 0x00000520 */ + uint32_t isp_dec_read_flush_cache_ex_9; /*!<(rw), DEC_BASE + 0x00000524 */ + uint32_t isp_dec_read_flush_cache_ex_10; /*!<(rw), DEC_BASE + 0x00000528 */ + uint32_t isp_dec_read_flush_cache_ex_11; /*!<(rw), DEC_BASE + 0x0000052C */ + uint32_t isp_dec_read_flush_cache_ex_12; /*!<(rw), DEC_BASE + 0x00000530 */ + uint32_t isp_dec_read_flush_cache_ex_13; /*!<(rw), DEC_BASE + 0x00000534 */ + uint32_t isp_dec_read_flush_cache_ex_14; /*!<(rw), DEC_BASE + 0x00000538 */ + uint32_t isp_dec_read_flush_cache_ex_15; /*!<(rw), DEC_BASE + 0x0000053C */ + uint32_t isp_dec_read_flush_cache_ex_16; /*!<(rw), DEC_BASE + 0x00000540 */ + uint32_t isp_dec_read_flush_cache_ex_17; /*!<(rw), DEC_BASE + 0x00000544 */ + uint32_t isp_dec_read_flush_cache_ex_18; /*!<(rw), DEC_BASE + 0x00000548 */ + uint32_t isp_dec_read_flush_cache_ex_19; /*!<(rw), DEC_BASE + 0x0000054C */ + uint32_t isp_dec_read_flush_cache_ex_20; /*!<(rw), DEC_BASE + 0x00000550 */ + uint32_t isp_dec_read_flush_cache_ex_21; /*!<(rw), DEC_BASE + 0x00000554 */ + uint32_t isp_dec_read_flush_cache_ex_22; /*!<(rw), DEC_BASE + 0x00000558 */ + uint32_t isp_dec_read_flush_cache_ex_23; /*!<(rw), DEC_BASE + 0x0000055C */ + uint32_t isp_dec_read_flush_cache_ex_24; /*!<(rw), DEC_BASE + 0x00000560 */ + uint32_t isp_dec_read_flush_cache_ex_25; /*!<(rw), DEC_BASE + 0x00000564 */ + uint32_t isp_dec_read_flush_cache_ex_26; /*!<(rw), DEC_BASE + 0x00000568 */ + uint32_t isp_dec_read_flush_cache_ex_27; /*!<(rw), DEC_BASE + 0x0000056C */ + uint32_t isp_dec_read_flush_cache_ex_28; /*!<(rw), DEC_BASE + 0x00000570 */ + uint32_t isp_dec_read_flush_cache_ex_29; /*!<(rw), DEC_BASE + 0x00000574 */ + uint32_t isp_dec_read_flush_cache_ex_30; /*!<(rw), DEC_BASE + 0x00000578 */ + uint32_t isp_dec_read_flush_cache_ex_31; /*!<(rw), DEC_BASE + 0x0000057C */ + uint32_t isp_dec_write_buffer_base_0; /*!<(rw), DEC_BASE + 0x00000580 */ + uint32_t isp_dec_write_buffer_base_1; /*!<(rw), DEC_BASE + 0x00000584 */ + uint32_t isp_dec_write_buffer_base_2; /*!<(rw), DEC_BASE + 0x00000588 */ + uint32_t isp_dec_write_buffer_base_3; /*!<(rw), DEC_BASE + 0x0000058C */ + uint32_t isp_dec_write_buffer_base_4; /*!<(rw), DEC_BASE + 0x00000590 */ + uint32_t isp_dec_write_buffer_base_5; /*!<(rw), DEC_BASE + 0x00000594 */ + uint32_t isp_dec_write_buffer_base_6; /*!<(rw), DEC_BASE + 0x00000598 */ + uint32_t isp_dec_write_buffer_base_7; /*!<(rw), DEC_BASE + 0x0000059C */ + uint32_t isp_dec_write_buffer_base_8; /*!<(rw), DEC_BASE + 0x000005A0 */ + uint32_t isp_dec_write_buffer_base_9; /*!<(rw), DEC_BASE + 0x000005A4 */ + uint32_t isp_dec_write_buffer_base_10; /*!<(rw), DEC_BASE + 0x000005A8 */ + uint32_t isp_dec_write_buffer_base_11; /*!<(rw), DEC_BASE + 0x000005AC */ + uint32_t isp_dec_write_buffer_base_12; /*!<(rw), DEC_BASE + 0x000005B0 */ + uint32_t isp_dec_write_buffer_base_13; /*!<(rw), DEC_BASE + 0x000005B4 */ + uint32_t isp_dec_write_buffer_base_14; /*!<(rw), DEC_BASE + 0x000005B8 */ + uint32_t isp_dec_write_buffer_base_15; /*!<(rw), DEC_BASE + 0x000005BC */ + uint32_t isp_dec_write_buffer_base_16; /*!<(rw), DEC_BASE + 0x000005C0 */ + uint32_t isp_dec_write_buffer_base_17; /*!<(rw), DEC_BASE + 0x000005C4 */ + uint32_t isp_dec_write_buffer_base_18; /*!<(rw), DEC_BASE + 0x000005C8 */ + uint32_t isp_dec_write_buffer_base_19; /*!<(rw), DEC_BASE + 0x000005CC */ + uint32_t isp_dec_write_buffer_base_20; /*!<(rw), DEC_BASE + 0x000005D0 */ + uint32_t isp_dec_write_buffer_base_21; /*!<(rw), DEC_BASE + 0x000005D4 */ + uint32_t isp_dec_write_buffer_base_22; /*!<(rw), DEC_BASE + 0x000005D8 */ + uint32_t isp_dec_write_buffer_base_23; /*!<(rw), DEC_BASE + 0x000005DC */ + uint32_t isp_dec_write_buffer_base_24; /*!<(rw), DEC_BASE + 0x000005E0 */ + uint32_t isp_dec_write_buffer_base_25; /*!<(rw), DEC_BASE + 0x000005E4 */ + uint32_t isp_dec_write_buffer_base_26; /*!<(rw), DEC_BASE + 0x000005E8 */ + uint32_t isp_dec_write_buffer_base_27; /*!<(rw), DEC_BASE + 0x000005EC */ + uint32_t isp_dec_write_buffer_base_28; /*!<(rw), DEC_BASE + 0x000005F0 */ + uint32_t isp_dec_write_buffer_base_29; /*!<(rw), DEC_BASE + 0x000005F4 */ + uint32_t isp_dec_write_buffer_base_30; /*!<(rw), DEC_BASE + 0x000005F8 */ + uint32_t isp_dec_write_buffer_base_31; /*!<(rw), DEC_BASE + 0x000005FC */ + uint32_t isp_dec_write_buffer_base_ex_0; /*!<(rw), DEC_BASE + 0x00000600 */ + uint32_t isp_dec_write_buffer_base_ex_1; /*!<(rw), DEC_BASE + 0x00000604 */ + uint32_t isp_dec_write_buffer_base_ex_2; /*!<(rw), DEC_BASE + 0x00000608 */ + uint32_t isp_dec_write_buffer_base_ex_3; /*!<(rw), DEC_BASE + 0x0000060C */ + uint32_t isp_dec_write_buffer_base_ex_4; /*!<(rw), DEC_BASE + 0x00000610 */ + uint32_t isp_dec_write_buffer_base_ex_5; /*!<(rw), DEC_BASE + 0x00000614 */ + uint32_t isp_dec_write_buffer_base_ex_6; /*!<(rw), DEC_BASE + 0x00000618 */ + uint32_t isp_dec_write_buffer_base_ex_7; /*!<(rw), DEC_BASE + 0x0000061C */ + uint32_t isp_dec_write_buffer_base_ex_8; /*!<(rw), DEC_BASE + 0x00000620 */ + uint32_t isp_dec_write_buffer_base_ex_9; /*!<(rw), DEC_BASE + 0x00000624 */ + uint32_t isp_dec_write_buffer_base_ex_10; /*!<(rw), DEC_BASE + 0x00000628 */ + uint32_t isp_dec_write_buffer_base_ex_11; /*!<(rw), DEC_BASE + 0x0000062C */ + uint32_t isp_dec_write_buffer_base_ex_12; /*!<(rw), DEC_BASE + 0x00000630 */ + uint32_t isp_dec_write_buffer_base_ex_13; /*!<(rw), DEC_BASE + 0x00000634 */ + uint32_t isp_dec_write_buffer_base_ex_14; /*!<(rw), DEC_BASE + 0x00000638 */ + uint32_t isp_dec_write_buffer_base_ex_15; /*!<(rw), DEC_BASE + 0x0000063C */ + uint32_t isp_dec_write_buffer_base_ex_16; /*!<(rw), DEC_BASE + 0x00000640 */ + uint32_t isp_dec_write_buffer_base_ex_17; /*!<(rw), DEC_BASE + 0x00000644 */ + uint32_t isp_dec_write_buffer_base_ex_18; /*!<(rw), DEC_BASE + 0x00000648 */ + uint32_t isp_dec_write_buffer_base_ex_19; /*!<(rw), DEC_BASE + 0x0000064C */ + uint32_t isp_dec_write_buffer_base_ex_20; /*!<(rw), DEC_BASE + 0x00000650 */ + uint32_t isp_dec_write_buffer_base_ex_21; /*!<(rw), DEC_BASE + 0x00000654 */ + uint32_t isp_dec_write_buffer_base_ex_22; /*!<(rw), DEC_BASE + 0x00000658 */ + uint32_t isp_dec_write_buffer_base_ex_23; /*!<(rw), DEC_BASE + 0x0000065C */ + uint32_t isp_dec_write_buffer_base_ex_24; /*!<(rw), DEC_BASE + 0x00000660 */ + uint32_t isp_dec_write_buffer_base_ex_25; /*!<(rw), DEC_BASE + 0x00000664 */ + uint32_t isp_dec_write_buffer_base_ex_26; /*!<(rw), DEC_BASE + 0x00000668 */ + uint32_t isp_dec_write_buffer_base_ex_27; /*!<(rw), DEC_BASE + 0x0000066C */ + uint32_t isp_dec_write_buffer_base_ex_28; /*!<(rw), DEC_BASE + 0x00000670 */ + uint32_t isp_dec_write_buffer_base_ex_29; /*!<(rw), DEC_BASE + 0x00000674 */ + uint32_t isp_dec_write_buffer_base_ex_30; /*!<(rw), DEC_BASE + 0x00000678 */ + uint32_t isp_dec_write_buffer_base_ex_31; /*!<(rw), DEC_BASE + 0x0000067C */ + uint32_t isp_dec_write_buffer_end_0; /*!<(rw), DEC_BASE + 0x00000680 */ + uint32_t isp_dec_write_buffer_end_1; /*!<(rw), DEC_BASE + 0x00000684 */ + uint32_t isp_dec_write_buffer_end_2; /*!<(rw), DEC_BASE + 0x00000688 */ + uint32_t isp_dec_write_buffer_end_3; /*!<(rw), DEC_BASE + 0x0000068C */ + uint32_t isp_dec_write_buffer_end_4; /*!<(rw), DEC_BASE + 0x00000690 */ + uint32_t isp_dec_write_buffer_end_5; /*!<(rw), DEC_BASE + 0x00000694 */ + uint32_t isp_dec_write_buffer_end_6; /*!<(rw), DEC_BASE + 0x00000698 */ + uint32_t isp_dec_write_buffer_end_7; /*!<(rw), DEC_BASE + 0x0000069C */ + uint32_t isp_dec_write_buffer_end_8; /*!<(rw), DEC_BASE + 0x000006A0 */ + uint32_t isp_dec_write_buffer_end_9; /*!<(rw), DEC_BASE + 0x000006A4 */ + uint32_t isp_dec_write_buffer_end_10; /*!<(rw), DEC_BASE + 0x000006A8 */ + uint32_t isp_dec_write_buffer_end_11; /*!<(rw), DEC_BASE + 0x000006AC */ + uint32_t isp_dec_write_buffer_end_12; /*!<(rw), DEC_BASE + 0x000006B0 */ + uint32_t isp_dec_write_buffer_end_13; /*!<(rw), DEC_BASE + 0x000006B4 */ + uint32_t isp_dec_write_buffer_end_14; /*!<(rw), DEC_BASE + 0x000006B8 */ + uint32_t isp_dec_write_buffer_end_15; /*!<(rw), DEC_BASE + 0x000006BC */ + uint32_t isp_dec_write_buffer_end_16; /*!<(rw), DEC_BASE + 0x000006C0 */ + uint32_t isp_dec_write_buffer_end_17; /*!<(rw), DEC_BASE + 0x000006C4 */ + uint32_t isp_dec_write_buffer_end_18; /*!<(rw), DEC_BASE + 0x000006C8 */ + uint32_t isp_dec_write_buffer_end_19; /*!<(rw), DEC_BASE + 0x000006CC */ + uint32_t isp_dec_write_buffer_end_20; /*!<(rw), DEC_BASE + 0x000006D0 */ + uint32_t isp_dec_write_buffer_end_21; /*!<(rw), DEC_BASE + 0x000006D4 */ + uint32_t isp_dec_write_buffer_end_22; /*!<(rw), DEC_BASE + 0x000006D8 */ + uint32_t isp_dec_write_buffer_end_23; /*!<(rw), DEC_BASE + 0x000006DC */ + uint32_t isp_dec_write_buffer_end_24; /*!<(rw), DEC_BASE + 0x000006E0 */ + uint32_t isp_dec_write_buffer_end_25; /*!<(rw), DEC_BASE + 0x000006E4 */ + uint32_t isp_dec_write_buffer_end_26; /*!<(rw), DEC_BASE + 0x000006E8 */ + uint32_t isp_dec_write_buffer_end_27; /*!<(rw), DEC_BASE + 0x000006EC */ + uint32_t isp_dec_write_buffer_end_28; /*!<(rw), DEC_BASE + 0x000006F0 */ + uint32_t isp_dec_write_buffer_end_29; /*!<(rw), DEC_BASE + 0x000006F4 */ + uint32_t isp_dec_write_buffer_end_30; /*!<(rw), DEC_BASE + 0x000006F8 */ + uint32_t isp_dec_write_buffer_end_31; /*!<(rw), DEC_BASE + 0x000006FC */ + uint32_t isp_dec_write_buffer_end_ex_0; /*!<(rw), DEC_BASE + 0x00000700 */ + uint32_t isp_dec_write_buffer_end_ex_1; /*!<(rw), DEC_BASE + 0x00000704 */ + uint32_t isp_dec_write_buffer_end_ex_2; /*!<(rw), DEC_BASE + 0x00000708 */ + uint32_t isp_dec_write_buffer_end_ex_3; /*!<(rw), DEC_BASE + 0x0000070C */ + uint32_t isp_dec_write_buffer_end_ex_4; /*!<(rw), DEC_BASE + 0x00000710 */ + uint32_t isp_dec_write_buffer_end_ex_5; /*!<(rw), DEC_BASE + 0x00000714 */ + uint32_t isp_dec_write_buffer_end_ex_6; /*!<(rw), DEC_BASE + 0x00000718 */ + uint32_t isp_dec_write_buffer_end_ex_7; /*!<(rw), DEC_BASE + 0x0000071C */ + uint32_t isp_dec_write_buffer_end_ex_8; /*!<(rw), DEC_BASE + 0x00000720 */ + uint32_t isp_dec_write_buffer_end_ex_9; /*!<(rw), DEC_BASE + 0x00000724 */ + uint32_t isp_dec_write_buffer_end_ex_10; /*!<(rw), DEC_BASE + 0x00000728 */ + uint32_t isp_dec_write_buffer_end_ex_11; /*!<(rw), DEC_BASE + 0x0000072C */ + uint32_t isp_dec_write_buffer_end_ex_12; /*!<(rw), DEC_BASE + 0x00000730 */ + uint32_t isp_dec_write_buffer_end_ex_13; /*!<(rw), DEC_BASE + 0x00000734 */ + uint32_t isp_dec_write_buffer_end_ex_14; /*!<(rw), DEC_BASE + 0x00000738 */ + uint32_t isp_dec_write_buffer_end_ex_15; /*!<(rw), DEC_BASE + 0x0000073C */ + uint32_t isp_dec_write_buffer_end_ex_16; /*!<(rw), DEC_BASE + 0x00000740 */ + uint32_t isp_dec_write_buffer_end_ex_17; /*!<(rw), DEC_BASE + 0x00000744 */ + uint32_t isp_dec_write_buffer_end_ex_18; /*!<(rw), DEC_BASE + 0x00000748 */ + uint32_t isp_dec_write_buffer_end_ex_19; /*!<(rw), DEC_BASE + 0x0000074C */ + uint32_t isp_dec_write_buffer_end_ex_20; /*!<(rw), DEC_BASE + 0x00000750 */ + uint32_t isp_dec_write_buffer_end_ex_21; /*!<(rw), DEC_BASE + 0x00000754 */ + uint32_t isp_dec_write_buffer_end_ex_22; /*!<(rw), DEC_BASE + 0x00000758 */ + uint32_t isp_dec_write_buffer_end_ex_23; /*!<(rw), DEC_BASE + 0x0000075C */ + uint32_t isp_dec_write_buffer_end_ex_24; /*!<(rw), DEC_BASE + 0x00000760 */ + uint32_t isp_dec_write_buffer_end_ex_25; /*!<(rw), DEC_BASE + 0x00000764 */ + uint32_t isp_dec_write_buffer_end_ex_26; /*!<(rw), DEC_BASE + 0x00000768 */ + uint32_t isp_dec_write_buffer_end_ex_27; /*!<(rw), DEC_BASE + 0x0000076C */ + uint32_t isp_dec_write_buffer_end_ex_28; /*!<(rw), DEC_BASE + 0x00000770 */ + uint32_t isp_dec_write_buffer_end_ex_29; /*!<(rw), DEC_BASE + 0x00000774 */ + uint32_t isp_dec_write_buffer_end_ex_30; /*!<(rw), DEC_BASE + 0x00000778 */ + uint32_t isp_dec_write_buffer_end_ex_31; /*!<(rw), DEC_BASE + 0x0000077C */ + uint32_t isp_dec_write_flush_cache_0; /*!<(rw), DEC_BASE + 0x00000780 */ + uint32_t isp_dec_write_flush_cache_1; /*!<(rw), DEC_BASE + 0x00000784 */ + uint32_t isp_dec_write_flush_cache_2; /*!<(rw), DEC_BASE + 0x00000788 */ + uint32_t isp_dec_write_flush_cache_3; /*!<(rw), DEC_BASE + 0x0000078C */ + uint32_t isp_dec_write_flush_cache_4; /*!<(rw), DEC_BASE + 0x00000790 */ + uint32_t isp_dec_write_flush_cache_5; /*!<(rw), DEC_BASE + 0x00000794 */ + uint32_t isp_dec_write_flush_cache_6; /*!<(rw), DEC_BASE + 0x00000798 */ + uint32_t isp_dec_write_flush_cache_7; /*!<(rw), DEC_BASE + 0x0000079C */ + uint32_t isp_dec_write_flush_cache_8; /*!<(rw), DEC_BASE + 0x000007A0 */ + uint32_t isp_dec_write_flush_cache_9; /*!<(rw), DEC_BASE + 0x000007A4 */ + uint32_t isp_dec_write_flush_cache_10; /*!<(rw), DEC_BASE + 0x000007A8 */ + uint32_t isp_dec_write_flush_cache_11; /*!<(rw), DEC_BASE + 0x000007AC */ + uint32_t isp_dec_write_flush_cache_12; /*!<(rw), DEC_BASE + 0x000007B0 */ + uint32_t isp_dec_write_flush_cache_13; /*!<(rw), DEC_BASE + 0x000007B4 */ + uint32_t isp_dec_write_flush_cache_14; /*!<(rw), DEC_BASE + 0x000007B8 */ + uint32_t isp_dec_write_flush_cache_15; /*!<(rw), DEC_BASE + 0x000007BC */ + uint32_t isp_dec_write_flush_cache_16; /*!<(rw), DEC_BASE + 0x000007C0 */ + uint32_t isp_dec_write_flush_cache_17; /*!<(rw), DEC_BASE + 0x000007C4 */ + uint32_t isp_dec_write_flush_cache_18; /*!<(rw), DEC_BASE + 0x000007C8 */ + uint32_t isp_dec_write_flush_cache_19; /*!<(rw), DEC_BASE + 0x000007CC */ + uint32_t isp_dec_write_flush_cache_20; /*!<(rw), DEC_BASE + 0x000007D0 */ + uint32_t isp_dec_write_flush_cache_21; /*!<(rw), DEC_BASE + 0x000007D4 */ + uint32_t isp_dec_write_flush_cache_22; /*!<(rw), DEC_BASE + 0x000007D8 */ + uint32_t isp_dec_write_flush_cache_23; /*!<(rw), DEC_BASE + 0x000007DC */ + uint32_t isp_dec_write_flush_cache_24; /*!<(rw), DEC_BASE + 0x000007E0 */ + uint32_t isp_dec_write_flush_cache_25; /*!<(rw), DEC_BASE + 0x000007E4 */ + uint32_t isp_dec_write_flush_cache_26; /*!<(rw), DEC_BASE + 0x000007E8 */ + uint32_t isp_dec_write_flush_cache_27; /*!<(rw), DEC_BASE + 0x000007EC */ + uint32_t isp_dec_write_flush_cache_28; /*!<(rw), DEC_BASE + 0x000007F0 */ + uint32_t isp_dec_write_flush_cache_29; /*!<(rw), DEC_BASE + 0x000007F4 */ + uint32_t isp_dec_write_flush_cache_30; /*!<(rw), DEC_BASE + 0x000007F8 */ + uint32_t isp_dec_write_flush_cache_31; /*!<(rw), DEC_BASE + 0x000007FC */ + uint32_t isp_dec_write_flush_cache_ex_0; /*!<(rw), DEC_BASE + 0x00000800 */ + uint32_t isp_dec_write_flush_cache_ex_1; /*!<(rw), DEC_BASE + 0x00000804 */ + uint32_t isp_dec_write_flush_cache_ex_2; /*!<(rw), DEC_BASE + 0x00000808 */ + uint32_t isp_dec_write_flush_cache_ex_3; /*!<(rw), DEC_BASE + 0x0000080C */ + uint32_t isp_dec_write_flush_cache_ex_4; /*!<(rw), DEC_BASE + 0x00000810 */ + uint32_t isp_dec_write_flush_cache_ex_5; /*!<(rw), DEC_BASE + 0x00000814 */ + uint32_t isp_dec_write_flush_cache_ex_6; /*!<(rw), DEC_BASE + 0x00000818 */ + uint32_t isp_dec_write_flush_cache_ex_7; /*!<(rw), DEC_BASE + 0x0000081C */ + uint32_t isp_dec_write_flush_cache_ex_8; /*!<(rw), DEC_BASE + 0x00000820 */ + uint32_t isp_dec_write_flush_cache_ex_9; /*!<(rw), DEC_BASE + 0x00000824 */ + uint32_t isp_dec_write_flush_cache_ex_10; /*!<(rw), DEC_BASE + 0x00000828 */ + uint32_t isp_dec_write_flush_cache_ex_11; /*!<(rw), DEC_BASE + 0x0000082C */ + uint32_t isp_dec_write_flush_cache_ex_12; /*!<(rw), DEC_BASE + 0x00000830 */ + uint32_t isp_dec_write_flush_cache_ex_13; /*!<(rw), DEC_BASE + 0x00000834 */ + uint32_t isp_dec_write_flush_cache_ex_14; /*!<(rw), DEC_BASE + 0x00000838 */ + uint32_t isp_dec_write_flush_cache_ex_15; /*!<(rw), DEC_BASE + 0x0000083C */ + uint32_t isp_dec_write_flush_cache_ex_16; /*!<(rw), DEC_BASE + 0x00000840 */ + uint32_t isp_dec_write_flush_cache_ex_17; /*!<(rw), DEC_BASE + 0x00000844 */ + uint32_t isp_dec_write_flush_cache_ex_18; /*!<(rw), DEC_BASE + 0x00000848 */ + uint32_t isp_dec_write_flush_cache_ex_19; /*!<(rw), DEC_BASE + 0x0000084C */ + uint32_t isp_dec_write_flush_cache_ex_20; /*!<(rw), DEC_BASE + 0x00000850 */ + uint32_t isp_dec_write_flush_cache_ex_21; /*!<(rw), DEC_BASE + 0x00000854 */ + uint32_t isp_dec_write_flush_cache_ex_22; /*!<(rw), DEC_BASE + 0x00000858 */ + uint32_t isp_dec_write_flush_cache_ex_23; /*!<(rw), DEC_BASE + 0x0000085C */ + uint32_t isp_dec_write_flush_cache_ex_24; /*!<(rw), DEC_BASE + 0x00000860 */ + uint32_t isp_dec_write_flush_cache_ex_25; /*!<(rw), DEC_BASE + 0x00000864 */ + uint32_t isp_dec_write_flush_cache_ex_26; /*!<(rw), DEC_BASE + 0x00000868 */ + uint32_t isp_dec_write_flush_cache_ex_27; /*!<(rw), DEC_BASE + 0x0000086C */ + uint32_t isp_dec_write_flush_cache_ex_28; /*!<(rw), DEC_BASE + 0x00000870 */ + uint32_t isp_dec_write_flush_cache_ex_29; /*!<(rw), DEC_BASE + 0x00000874 */ + uint32_t isp_dec_write_flush_cache_ex_30; /*!<(rw), DEC_BASE + 0x00000878 */ + uint32_t isp_dec_write_flush_cache_ex_31; /*!<(rw), DEC_BASE + 0x0000087C */ + uint32_t isp_dec_read_cache_base_0; /*!<(rw), DEC_BASE + 0x00000880 */ + uint32_t isp_dec_read_cache_base_1; /*!<(rw), DEC_BASE + 0x00000884 */ + uint32_t isp_dec_read_cache_base_2; /*!<(rw), DEC_BASE + 0x00000888 */ + uint32_t isp_dec_read_cache_base_3; /*!<(rw), DEC_BASE + 0x0000088C */ + uint32_t isp_dec_read_cache_base_4; /*!<(rw), DEC_BASE + 0x00000890 */ + uint32_t isp_dec_read_cache_base_5; /*!<(rw), DEC_BASE + 0x00000894 */ + uint32_t isp_dec_read_cache_base_6; /*!<(rw), DEC_BASE + 0x00000898 */ + uint32_t isp_dec_read_cache_base_7; /*!<(rw), DEC_BASE + 0x0000089C */ + uint32_t isp_dec_read_cache_base_8; /*!<(rw), DEC_BASE + 0x000008A0 */ + uint32_t isp_dec_read_cache_base_9; /*!<(rw), DEC_BASE + 0x000008A4 */ + uint32_t isp_dec_read_cache_base_10; /*!<(rw), DEC_BASE + 0x000008A8 */ + uint32_t isp_dec_read_cache_base_11; /*!<(rw), DEC_BASE + 0x000008AC */ + uint32_t isp_dec_read_cache_base_12; /*!<(rw), DEC_BASE + 0x000008B0 */ + uint32_t isp_dec_read_cache_base_13; /*!<(rw), DEC_BASE + 0x000008B4 */ + uint32_t isp_dec_read_cache_base_14; /*!<(rw), DEC_BASE + 0x000008B8 */ + uint32_t isp_dec_read_cache_base_15; /*!<(rw), DEC_BASE + 0x000008BC */ + uint32_t isp_dec_read_cache_base_16; /*!<(rw), DEC_BASE + 0x000008C0 */ + uint32_t isp_dec_read_cache_base_17; /*!<(rw), DEC_BASE + 0x000008C4 */ + uint32_t isp_dec_read_cache_base_18; /*!<(rw), DEC_BASE + 0x000008C8 */ + uint32_t isp_dec_read_cache_base_19; /*!<(rw), DEC_BASE + 0x000008CC */ + uint32_t isp_dec_read_cache_base_20; /*!<(rw), DEC_BASE + 0x000008D0 */ + uint32_t isp_dec_read_cache_base_21; /*!<(rw), DEC_BASE + 0x000008D4 */ + uint32_t isp_dec_read_cache_base_22; /*!<(rw), DEC_BASE + 0x000008D8 */ + uint32_t isp_dec_read_cache_base_23; /*!<(rw), DEC_BASE + 0x000008DC */ + uint32_t isp_dec_read_cache_base_24; /*!<(rw), DEC_BASE + 0x000008E0 */ + uint32_t isp_dec_read_cache_base_25; /*!<(rw), DEC_BASE + 0x000008E4 */ + uint32_t isp_dec_read_cache_base_26; /*!<(rw), DEC_BASE + 0x000008E8 */ + uint32_t isp_dec_read_cache_base_27; /*!<(rw), DEC_BASE + 0x000008EC */ + uint32_t isp_dec_read_cache_base_28; /*!<(rw), DEC_BASE + 0x000008F0 */ + uint32_t isp_dec_read_cache_base_29; /*!<(rw), DEC_BASE + 0x000008F4 */ + uint32_t isp_dec_read_cache_base_30; /*!<(rw), DEC_BASE + 0x000008F8 */ + uint32_t isp_dec_read_cache_base_31; /*!<(rw), DEC_BASE + 0x000008FC */ + uint32_t isp_dec_read_cache_base_ex_0; /*!<(rw), DEC_BASE + 0x00000900 */ + uint32_t isp_dec_read_cache_base_ex_1; /*!<(rw), DEC_BASE + 0x00000904 */ + uint32_t isp_dec_read_cache_base_ex_2; /*!<(rw), DEC_BASE + 0x00000908 */ + uint32_t isp_dec_read_cache_base_ex_3; /*!<(rw), DEC_BASE + 0x0000090C */ + uint32_t isp_dec_read_cache_base_ex_4; /*!<(rw), DEC_BASE + 0x00000910 */ + uint32_t isp_dec_read_cache_base_ex_5; /*!<(rw), DEC_BASE + 0x00000914 */ + uint32_t isp_dec_read_cache_base_ex_6; /*!<(rw), DEC_BASE + 0x00000918 */ + uint32_t isp_dec_read_cache_base_ex_7; /*!<(rw), DEC_BASE + 0x0000091C */ + uint32_t isp_dec_read_cache_base_ex_8; /*!<(rw), DEC_BASE + 0x00000920 */ + uint32_t isp_dec_read_cache_base_ex_9; /*!<(rw), DEC_BASE + 0x00000924 */ + uint32_t isp_dec_read_cache_base_ex_10; /*!<(rw), DEC_BASE + 0x00000928 */ + uint32_t isp_dec_read_cache_base_ex_11; /*!<(rw), DEC_BASE + 0x0000092C */ + uint32_t isp_dec_read_cache_base_ex_12; /*!<(rw), DEC_BASE + 0x00000930 */ + uint32_t isp_dec_read_cache_base_ex_13; /*!<(rw), DEC_BASE + 0x00000934 */ + uint32_t isp_dec_read_cache_base_ex_14; /*!<(rw), DEC_BASE + 0x00000938 */ + uint32_t isp_dec_read_cache_base_ex_15; /*!<(rw), DEC_BASE + 0x0000093C */ + uint32_t isp_dec_read_cache_base_ex_16; /*!<(rw), DEC_BASE + 0x00000940 */ + uint32_t isp_dec_read_cache_base_ex_17; /*!<(rw), DEC_BASE + 0x00000944 */ + uint32_t isp_dec_read_cache_base_ex_18; /*!<(rw), DEC_BASE + 0x00000948 */ + uint32_t isp_dec_read_cache_base_ex_19; /*!<(rw), DEC_BASE + 0x0000094C */ + uint32_t isp_dec_read_cache_base_ex_20; /*!<(rw), DEC_BASE + 0x00000950 */ + uint32_t isp_dec_read_cache_base_ex_21; /*!<(rw), DEC_BASE + 0x00000954 */ + uint32_t isp_dec_read_cache_base_ex_22; /*!<(rw), DEC_BASE + 0x00000958 */ + uint32_t isp_dec_read_cache_base_ex_23; /*!<(rw), DEC_BASE + 0x0000095C */ + uint32_t isp_dec_read_cache_base_ex_24; /*!<(rw), DEC_BASE + 0x00000960 */ + uint32_t isp_dec_read_cache_base_ex_25; /*!<(rw), DEC_BASE + 0x00000964 */ + uint32_t isp_dec_read_cache_base_ex_26; /*!<(rw), DEC_BASE + 0x00000968 */ + uint32_t isp_dec_read_cache_base_ex_27; /*!<(rw), DEC_BASE + 0x0000096C */ + uint32_t isp_dec_read_cache_base_ex_28; /*!<(rw), DEC_BASE + 0x00000970 */ + uint32_t isp_dec_read_cache_base_ex_29; /*!<(rw), DEC_BASE + 0x00000974 */ + uint32_t isp_dec_read_cache_base_ex_30; /*!<(rw), DEC_BASE + 0x00000978 */ + uint32_t isp_dec_read_cache_base_ex_31; /*!<(rw), DEC_BASE + 0x0000097C */ + uint32_t isp_dec_write_cache_base_0; /*!<(rw), DEC_BASE + 0x00000980 */ + uint32_t isp_dec_write_cache_base_1; /*!<(rw), DEC_BASE + 0x00000984 */ + uint32_t isp_dec_write_cache_base_2; /*!<(rw), DEC_BASE + 0x00000988 */ + uint32_t isp_dec_write_cache_base_3; /*!<(rw), DEC_BASE + 0x0000098C */ + uint32_t isp_dec_write_cache_base_4; /*!<(rw), DEC_BASE + 0x00000990 */ + uint32_t isp_dec_write_cache_base_5; /*!<(rw), DEC_BASE + 0x00000994 */ + uint32_t isp_dec_write_cache_base_6; /*!<(rw), DEC_BASE + 0x00000998 */ + uint32_t isp_dec_write_cache_base_7; /*!<(rw), DEC_BASE + 0x0000099C */ + uint32_t isp_dec_write_cache_base_8; /*!<(rw), DEC_BASE + 0x000009A0 */ + uint32_t isp_dec_write_cache_base_9; /*!<(rw), DEC_BASE + 0x000009A4 */ + uint32_t isp_dec_write_cache_base_10; /*!<(rw), DEC_BASE + 0x000009A8 */ + uint32_t isp_dec_write_cache_base_11; /*!<(rw), DEC_BASE + 0x000009AC */ + uint32_t isp_dec_write_cache_base_12; /*!<(rw), DEC_BASE + 0x000009B0 */ + uint32_t isp_dec_write_cache_base_13; /*!<(rw), DEC_BASE + 0x000009B4 */ + uint32_t isp_dec_write_cache_base_14; /*!<(rw), DEC_BASE + 0x000009B8 */ + uint32_t isp_dec_write_cache_base_15; /*!<(rw), DEC_BASE + 0x000009BC */ + uint32_t isp_dec_write_cache_base_16; /*!<(rw), DEC_BASE + 0x000009C0 */ + uint32_t isp_dec_write_cache_base_17; /*!<(rw), DEC_BASE + 0x000009C4 */ + uint32_t isp_dec_write_cache_base_18; /*!<(rw), DEC_BASE + 0x000009C8 */ + uint32_t isp_dec_write_cache_base_19; /*!<(rw), DEC_BASE + 0x000009CC */ + uint32_t isp_dec_write_cache_base_20; /*!<(rw), DEC_BASE + 0x000009D0 */ + uint32_t isp_dec_write_cache_base_21; /*!<(rw), DEC_BASE + 0x000009D4 */ + uint32_t isp_dec_write_cache_base_22; /*!<(rw), DEC_BASE + 0x000009D8 */ + uint32_t isp_dec_write_cache_base_23; /*!<(rw), DEC_BASE + 0x000009DC */ + uint32_t isp_dec_write_cache_base_24; /*!<(rw), DEC_BASE + 0x000009E0 */ + uint32_t isp_dec_write_cache_base_25; /*!<(rw), DEC_BASE + 0x000009E4 */ + uint32_t isp_dec_write_cache_base_26; /*!<(rw), DEC_BASE + 0x000009E8 */ + uint32_t isp_dec_write_cache_base_27; /*!<(rw), DEC_BASE + 0x000009EC */ + uint32_t isp_dec_write_cache_base_28; /*!<(rw), DEC_BASE + 0x000009F0 */ + uint32_t isp_dec_write_cache_base_29; /*!<(rw), DEC_BASE + 0x000009F4 */ + uint32_t isp_dec_write_cache_base_30; /*!<(rw), DEC_BASE + 0x000009F8 */ + uint32_t isp_dec_write_cache_base_31; /*!<(rw), DEC_BASE + 0x000009FC */ + uint32_t isp_dec_write_cache_base_ex_0; /*!<(rw), DEC_BASE + 0x00000A00 */ + uint32_t isp_dec_write_cache_base_ex_1; /*!<(rw), DEC_BASE + 0x00000A04 */ + uint32_t isp_dec_write_cache_base_ex_2; /*!<(rw), DEC_BASE + 0x00000A08 */ + uint32_t isp_dec_write_cache_base_ex_3; /*!<(rw), DEC_BASE + 0x00000A0C */ + uint32_t isp_dec_write_cache_base_ex_4; /*!<(rw), DEC_BASE + 0x00000A10 */ + uint32_t isp_dec_write_cache_base_ex_5; /*!<(rw), DEC_BASE + 0x00000A14 */ + uint32_t isp_dec_write_cache_base_ex_6; /*!<(rw), DEC_BASE + 0x00000A18 */ + uint32_t isp_dec_write_cache_base_ex_7; /*!<(rw), DEC_BASE + 0x00000A1C */ + uint32_t isp_dec_write_cache_base_ex_8; /*!<(rw), DEC_BASE + 0x00000A20 */ + uint32_t isp_dec_write_cache_base_ex_9; /*!<(rw), DEC_BASE + 0x00000A24 */ + uint32_t isp_dec_write_cache_base_ex_10; /*!<(rw), DEC_BASE + 0x00000A28 */ + uint32_t isp_dec_write_cache_base_ex_11; /*!<(rw), DEC_BASE + 0x00000A2C */ + uint32_t isp_dec_write_cache_base_ex_12; /*!<(rw), DEC_BASE + 0x00000A30 */ + uint32_t isp_dec_write_cache_base_ex_13; /*!<(rw), DEC_BASE + 0x00000A34 */ + uint32_t isp_dec_write_cache_base_ex_14; /*!<(rw), DEC_BASE + 0x00000A38 */ + uint32_t isp_dec_write_cache_base_ex_15; /*!<(rw), DEC_BASE + 0x00000A3C */ + uint32_t isp_dec_write_cache_base_ex_16; /*!<(rw), DEC_BASE + 0x00000A40 */ + uint32_t isp_dec_write_cache_base_ex_17; /*!<(rw), DEC_BASE + 0x00000A44 */ + uint32_t isp_dec_write_cache_base_ex_18; /*!<(rw), DEC_BASE + 0x00000A48 */ + uint32_t isp_dec_write_cache_base_ex_19; /*!<(rw), DEC_BASE + 0x00000A4C */ + uint32_t isp_dec_write_cache_base_ex_20; /*!<(rw), DEC_BASE + 0x00000A50 */ + uint32_t isp_dec_write_cache_base_ex_21; /*!<(rw), DEC_BASE + 0x00000A54 */ + uint32_t isp_dec_write_cache_base_ex_22; /*!<(rw), DEC_BASE + 0x00000A58 */ + uint32_t isp_dec_write_cache_base_ex_23; /*!<(rw), DEC_BASE + 0x00000A5C */ + uint32_t isp_dec_write_cache_base_ex_24; /*!<(rw), DEC_BASE + 0x00000A60 */ + uint32_t isp_dec_write_cache_base_ex_25; /*!<(rw), DEC_BASE + 0x00000A64 */ + uint32_t isp_dec_write_cache_base_ex_26; /*!<(rw), DEC_BASE + 0x00000A68 */ + uint32_t isp_dec_write_cache_base_ex_27; /*!<(rw), DEC_BASE + 0x00000A6C */ + uint32_t isp_dec_write_cache_base_ex_28; /*!<(rw), DEC_BASE + 0x00000A70 */ + uint32_t isp_dec_write_cache_base_ex_29; /*!<(rw), DEC_BASE + 0x00000A74 */ + uint32_t isp_dec_write_cache_base_ex_30; /*!<(rw), DEC_BASE + 0x00000A78 */ + uint32_t isp_dec_write_cache_base_ex_31; /*!<(rw), DEC_BASE + 0x00000A7C */ + uint32_t isp_dec_debug_info_out; /*!<(ro), DEC_BASE + 0x00000A80 */ + uint32_t isp_dec_debug_0; /*!<(ro), DEC_BASE + 0x00000A84 */ + uint32_t isp_dec_debug_1; /*!<(ro), DEC_BASE + 0x00000A88 */ + uint32_t isp_dec_debug_2; /*!<(ro), DEC_BASE + 0x00000A8C */ + uint32_t isp_dec_debug_3; /*!<(ro), DEC_BASE + 0x00000A90 */ + uint32_t isp_dec_debug_4; /*!<(ro), DEC_BASE + 0x00000A94 */ + uint32_t isp_dec_debug_5; /*!<(ro), DEC_BASE + 0x00000A98 */ + uint32_t isp_dec_state_commit; /*!<(ro), DEC_BASE + 0x00000A9C */ + uint32_t isp_dec_debug_6; /*!<(ro), DEC_BASE + 0x00000AA0 */ + uint32_t isp_dec_debug_7; /*!<(ro), DEC_BASE + 0x00000AA4 */ + uint32_t isp_dec_tile_128_type_0; /*!<(ro), DEC_BASE + 0x00000AA8 */ + uint32_t isp_dec_tile_128_type_1; /*!<(ro), DEC_BASE + 0x00000AAC */ + uint32_t isp_dec_tile_128_type_2; /*!<(ro), DEC_BASE + 0x00000AB0 */ + uint32_t isp_dec_tile_128_type_3; /*!<(ro), DEC_BASE + 0x00000AB4 */ + uint32_t isp_dec_tile_256_type_0; /*!<(ro), DEC_BASE + 0x00000AB8 */ + uint32_t isp_dec_tile_256_type_1; /*!<(ro), DEC_BASE + 0x00000ABC */ + uint32_t isp_dec_tile_256_type_2; /*!<(ro), DEC_BASE + 0x00000AC0 */ + uint32_t isp_dec_tile_256_type_3; /*!<(ro), DEC_BASE + 0x00000AC4 */ + uint32_t isp_dec_tile_256_type_4; /*!<(ro), DEC_BASE + 0x00000AC8 */ + uint32_t isp_dec_tile_256_type_5; /*!<(ro), DEC_BASE + 0x00000ACC */ + uint32_t isp_dec_tile_256_type_6; /*!<(ro), DEC_BASE + 0x00000AD0 */ + uint32_t isp_dec_tile_256_type_7; /*!<(ro), DEC_BASE + 0x00000AD4 */ + uint32_t isp_dec_debug_read_gate_domain_clk_counter; /*!<(ro), DEC_BASE + 0x00000AD8 */ + uint32_t isp_dec_debug_write_gate_domain_clk_counter; /*!<(ro), DEC_BASE + 0x00000ADC */ + uint32_t isp_dec_debug_other_gate_domain_clk_counter; /*!<(ro), DEC_BASE + 0x00000AE0 */ + uint32_t isp_dec_fast_clear_value_0; /*!<(rw), DEC_BASE + 0x00000B00 */ + uint32_t isp_dec_fast_clear_value_1; /*!<(rw), DEC_BASE + 0x00000B04 */ + uint32_t isp_dec_fast_clear_value_2; /*!<(rw), DEC_BASE + 0x00000B08 */ + uint32_t isp_dec_fast_clear_value_3; /*!<(rw), DEC_BASE + 0x00000B0C */ + uint32_t isp_dec_fast_clear_value_4; /*!<(rw), DEC_BASE + 0x00000B10 */ + uint32_t isp_dec_fast_clear_value_5; /*!<(rw), DEC_BASE + 0x00000B14 */ + uint32_t isp_dec_fast_clear_value_6; /*!<(rw), DEC_BASE + 0x00000B18 */ + uint32_t isp_dec_fast_clear_value_7; /*!<(rw), DEC_BASE + 0x00000B1C */ + uint32_t isp_dec_fast_clear_value_8; /*!<(rw), DEC_BASE + 0x00000B20 */ + uint32_t isp_dec_fast_clear_value_9; /*!<(rw), DEC_BASE + 0x00000B24 */ + uint32_t isp_dec_fast_clear_value_10; /*!<(rw), DEC_BASE + 0x00000B28 */ + uint32_t isp_dec_fast_clear_value_11; /*!<(rw), DEC_BASE + 0x00000B2C */ + uint32_t isp_dec_fast_clear_value_12; /*!<(rw), DEC_BASE + 0x00000B30 */ + uint32_t isp_dec_fast_clear_value_13; /*!<(rw), DEC_BASE + 0x00000B34 */ + uint32_t isp_dec_fast_clear_value_14; /*!<(rw), DEC_BASE + 0x00000B38 */ + uint32_t isp_dec_fast_clear_value_15; /*!<(rw), DEC_BASE + 0x00000B3C */ + uint32_t isp_dec_fast_clear_value_16; /*!<(rw), DEC_BASE + 0x00000B40 */ + uint32_t isp_dec_fast_clear_value_17; /*!<(rw), DEC_BASE + 0x00000B44 */ + uint32_t isp_dec_fast_clear_value_18; /*!<(rw), DEC_BASE + 0x00000B48 */ + uint32_t isp_dec_fast_clear_value_19; /*!<(rw), DEC_BASE + 0x00000B4C */ + uint32_t isp_dec_fast_clear_value_20; /*!<(rw), DEC_BASE + 0x00000B50 */ + uint32_t isp_dec_fast_clear_value_21; /*!<(rw), DEC_BASE + 0x00000B54 */ + uint32_t isp_dec_fast_clear_value_22; /*!<(rw), DEC_BASE + 0x00000B58 */ + uint32_t isp_dec_fast_clear_value_23; /*!<(rw), DEC_BASE + 0x00000B5C */ + uint32_t isp_dec_fast_clear_value_24; /*!<(rw), DEC_BASE + 0x00000B60 */ + uint32_t isp_dec_fast_clear_value_25; /*!<(rw), DEC_BASE + 0x00000B64 */ + uint32_t isp_dec_fast_clear_value_26; /*!<(rw), DEC_BASE + 0x00000B68 */ + uint32_t isp_dec_fast_clear_value_27; /*!<(rw), DEC_BASE + 0x00000B6C */ + uint32_t isp_dec_fast_clear_value_28; /*!<(rw), DEC_BASE + 0x00000B70 */ + uint32_t isp_dec_fast_clear_value_29; /*!<(rw), DEC_BASE + 0x00000B74 */ + uint32_t isp_dec_fast_clear_value_30; /*!<(rw), DEC_BASE + 0x00000B78 */ + uint32_t isp_dec_fast_clear_value_31; /*!<(rw), DEC_BASE + 0x00000B7C */ + uint32_t isp_dec_fast_clear_value_ex_0; /*!<(rw), DEC_BASE + 0x00000B80 */ + uint32_t isp_dec_fast_clear_value_ex_1; /*!<(rw), DEC_BASE + 0x00000B84 */ + uint32_t isp_dec_fast_clear_value_ex_2; /*!<(rw), DEC_BASE + 0x00000B88 */ + uint32_t isp_dec_fast_clear_value_ex_3; /*!<(rw), DEC_BASE + 0x00000B8C */ + uint32_t isp_dec_fast_clear_value_ex_4; /*!<(rw), DEC_BASE + 0x00000B90 */ + uint32_t isp_dec_fast_clear_value_ex_5; /*!<(rw), DEC_BASE + 0x00000B94 */ + uint32_t isp_dec_fast_clear_value_ex_6; /*!<(rw), DEC_BASE + 0x00000B98 */ + uint32_t isp_dec_fast_clear_value_ex_7; /*!<(rw), DEC_BASE + 0x00000B9C */ + uint32_t isp_dec_fast_clear_value_ex_8; /*!<(rw), DEC_BASE + 0x00000BA0 */ + uint32_t isp_dec_fast_clear_value_ex_9; /*!<(rw), DEC_BASE + 0x00000BA4 */ + uint32_t isp_dec_fast_clear_value_ex_10; /*!<(rw), DEC_BASE + 0x00000BA8 */ + uint32_t isp_dec_fast_clear_value_ex_11; /*!<(rw), DEC_BASE + 0x00000BAC */ + uint32_t isp_dec_fast_clear_value_ex_12; /*!<(rw), DEC_BASE + 0x00000BB0 */ + uint32_t isp_dec_fast_clear_value_ex_13; /*!<(rw), DEC_BASE + 0x00000BB4 */ + uint32_t isp_dec_fast_clear_value_ex_14; /*!<(rw), DEC_BASE + 0x00000BB8 */ + uint32_t isp_dec_fast_clear_value_ex_15; /*!<(rw), DEC_BASE + 0x00000BBC */ + uint32_t isp_dec_fast_clear_value_ex_16; /*!<(rw), DEC_BASE + 0x00000BC0 */ + uint32_t isp_dec_fast_clear_value_ex_17; /*!<(rw), DEC_BASE + 0x00000BC4 */ + uint32_t isp_dec_fast_clear_value_ex_18; /*!<(rw), DEC_BASE + 0x00000BC8 */ + uint32_t isp_dec_fast_clear_value_ex_19; /*!<(rw), DEC_BASE + 0x00000BCC */ + uint32_t isp_dec_fast_clear_value_ex_20; /*!<(rw), DEC_BASE + 0x00000BD0 */ + uint32_t isp_dec_fast_clear_value_ex_21; /*!<(rw), DEC_BASE + 0x00000BD4 */ + uint32_t isp_dec_fast_clear_value_ex_22; /*!<(rw), DEC_BASE + 0x00000BD8 */ + uint32_t isp_dec_fast_clear_value_ex_23; /*!<(rw), DEC_BASE + 0x00000BDC */ + uint32_t isp_dec_fast_clear_value_ex_24; /*!<(rw), DEC_BASE + 0x00000BE0 */ + uint32_t isp_dec_fast_clear_value_ex_25; /*!<(rw), DEC_BASE + 0x00000BE4 */ + uint32_t isp_dec_fast_clear_value_ex_26; /*!<(rw), DEC_BASE + 0x00000BE8 */ + uint32_t isp_dec_fast_clear_value_ex_27; /*!<(rw), DEC_BASE + 0x00000BEC */ + uint32_t isp_dec_fast_clear_value_ex_28; /*!<(rw), DEC_BASE + 0x00000BF0 */ + uint32_t isp_dec_fast_clear_value_ex_29; /*!<(rw), DEC_BASE + 0x00000BF4 */ + uint32_t isp_dec_fast_clear_value_ex_30; /*!<(rw), DEC_BASE + 0x00000BF8 */ + uint32_t isp_dec_fast_clear_value_ex_31; /*!<(rw), DEC_BASE + 0x00000BFC */ + +} MrvDecAllRegister_t; + +/*! Register: isp_dec_ctrl (DEC_BASE + 0x00000000)*/ +/*! Slice: isp_dec_ctrl_flush:*/ +#define DEC_CTRL_FLUSH +#define DEC_CTRL_FLUSH_MASK 0x00000001U +#define DEC_CTRL_FLUSH_SHIFT 0U + +/*! Slice: isp_dec_ctrl_disable_compression:*/ +#define DEC_CTRL_DISABLE_COMPRESSION +#define DEC_CTRL_DISABLE_COMPRESSION_MASK 0x00000002U +#define DEC_CTRL_DISABLE_COMPRESSION_SHIFT 1U + +/*! Slice: isp_dec_ctrl_disable_ram_clock_gating:*/ +#define DEC_CTRL_DISABLE_RAM_CLOCK_GATING +#define DEC_CTRL_DISABLE_RAM_CLOCK_GATING_MASK 0x00000004U +#define DEC_CTRL_DISABLE_RAM_CLOCK_GATING_SHIFT 2U + +/*! Slice: isp_dec_ctrl_disable_debug_registers:*/ +#define DEC_CTRL_DISABLE_DEBUG_REGISTERS +#define DEC_CTRL_DISABLE_DEBUG_REGISTERS_MASK 0x00000008U +#define DEC_CTRL_DISABLE_DEBUG_REGISTERS_SHIFT 3U + +/*! Slice: isp_dec_ctrl_soft_reset:*/ +#define DEC_CTRL_SOFT_RESET +#define DEC_CTRL_SOFT_RESET_MASK 0x00000010U +#define DEC_CTRL_SOFT_RESET_SHIFT 4U + +/*! Slice: isp_dec_ctrl_flush_dcache:*/ +#define DEC_CTRL_FLUSH_DCACHE +#define DEC_CTRL_FLUSH_DCACHE_MASK 0x00000040U +#define DEC_CTRL_FLUSH_DCACHE_SHIFT 6U + +/*! Slice: isp_dec_ctrl_disable_dcache:*/ +#define DEC_CTRL_DISABLE_DCACHE +#define DEC_CTRL_DISABLE_DCACHE_MASK 0x00000080U +#define DEC_CTRL_DISABLE_DCACHE_SHIFT 7U + +/*! Slice: isp_dec_ctrl_disable_hw_flush:*/ +#define DEC_CTRL_DISABLE_HW_FLUSH +#define DEC_CTRL_DISABLE_HW_FLUSH_MASK 0x00010000U +#define DEC_CTRL_DISABLE_HW_FLUSH_SHIFT 16U + +/*! Slice: isp_dec_ctrl_clk_dis:*/ +#define DEC_CTRL_CLK_DIS +#define DEC_CTRL_CLK_DIS_MASK 0x00FC0000U +#define DEC_CTRL_CLK_DIS_SHIFT 17U + +/*! Slice: isp_dec_ctrl_sw_flush_id:*/ +#define DEC_CTRL_SW_FLUSH_ID +#define DEC_CTRL_SW_FLUSH_ID_MASK 0x00020000U +#define DEC_CTRL_SW_FLUSH_ID_SHIFT 18U + +/*! Slice: isp_dec_ctrl_disable_cache_prefetch:*/ +#define DEC_CTRL_DISABLE_CACHE_PREFETCH +#define DEC_CTRL_DISABLE_CACHE_PREFETCH_MASK 0x02000000U +#define DEC_CTRL_DISABLE_CACHE_PREFETCH_SHIFT 25U + +/*! Slice: isp_dec_ctrl_hw_update_shadow_reg_mode:*/ +#define DEC_CTRL_HW_UPDATE_SHADOW_REG_MODE +#define DEC_CTRL_HW_UPDATE_SHADOW_REG_MODE_MASK 0x10000000U +#define DEC_CTRL_HW_UPDATE_SHADOW_REG_MODE_SHIFT 28U + +/*! Slice: isp_dec_ctrl_soft_update_shadow_reg:*/ +#define DEC_CTRL_SOFT_UPDATE_SHADOW_REG +#define DEC_CTRL_SOFT_UPDATE_SHADOW_REG_MASK 0x20000000U +#define DEC_CTRL_SOFT_UPDATE_SHADOW_REG_SHIFT 29U + +/*! Slice: isp_dec_ctrl_disable_module_clock_gating:*/ +#define DEC_CTRL_DISABLE_MODULE_CLOCK_GATING +#define DEC_CTRL_DISABLE_MODULE_CLOCK_GATING_MASK 0x40000000U +#define DEC_CTRL_DISABLE_MODULE_CLOCK_GATING_SHIFT 30U + +/*! Slice: isp_dec_ctrl_disable_global_clock_gating:*/ +#define DEC_CTRL_DISABLE_GLOBAL_CLOCK_GATING +#define DEC_CTRL_DISABLE_GLOBAL_CLOCK_GATING_MASK 0x80000000U +#define DEC_CTRL_DISABLE_GLOBAL_CLOCK_GATING_SHIFT 31U + +/*! Register: isp_dec_ctrl_ex (DEC_BASE + 0x00000004)*/ +/*! Slice: isp_dec_ctrl_ex_enable_burst_split:*/ +#define DEC_CTRL_EX_ENABLE_BURST_SPLIT +#define DEC_CTRL_EX_ENABLE_BURST_SPLIT_MASK 0x00010000U +#define DEC_CTRL_EX_ENABLE_BURST_SPLIT_SHIFT 16U + +/*! Slice: isp_dec_ctrl_ex_enable_end_address_check:*/ +#define DEC_CTRL_EX_ENABLE_END_ADDRESS_RANGE_CHECK +#define DEC_CTRL_EX_ENABLE_END_ADDRESS_RANGE_CHECK_MASK 0x00020000U +#define DEC_CTRL_EX_ENABLE_END_ADDRESS_RANGE_CHECK_SHIFT 17U + +/*! Slice: isp_dec_ctrl_ex_write_miss_policy:*/ +#define DEC_CTRL_EX_WRITE_MISS_POLICY +#define DEC_CTRL_EX_WRITE_MISS_POLICY_MASK 0x00080000U +#define DEC_CTRL_EX_WRITE_MISS_POLICY_SHIFT 19U + +/*! Slice: isp_dec_ctrl_ex_read_miss_policy:*/ +#define DEC_CTRL_EX_READ_MISS_POLICY +#define DEC_CTRL_EX_READ_MISS_POLICY_MASK 0x20000000U +#define DEC_CTRL_EX_READ_MISS_POLICY_SHIFT 29U + +/*! Register: isp_dec_ctrl_ex2 (DEC_BASE + 0x00000008)*/ +/*! Slice: isp_dec_ctrl_ex2_tile_status_read_id:*/ +#define DEC_CTRL_EX2_TILE_STATUS_READ_ID +#define DEC_CTRL_EX2_TILE_STATUS_READ_ID_MASK 0x0000007FU +#define DEC_CTRL_EX2_TILE_STATUS_READ_ID_SHIFT 0U + +/*! Slice: isp_dec_ctrl_ex2_tile_status_write_id:*/ +#define DEC_CTRL_EX2_TILE_STATUS_WRITE_ID +#define DEC_CTRL_EX2_TILE_STATUS_WRITE_ID_MASK 0x0003F80U +#define DEC_CTRL_EX2_TILE_STATUS_WRITE_ID_SHIFT 7U + +/*! Register: isp_dec_intr_enbl (DEC_BASE + 0x0000000C)*/ +/*! Slice: isp_dec_intr_enbl_vec:*/ +#define DEC_INTR_ENBL_VEC +#define DEC_INTR_ENBL_VEC_MASK 0xFFFFFFFFU +#define DEC_INTR_ENBL_VEC_SHIFT 0U + +/*! Register: isp_dec_intr_enbl_ex (DEC_BASE + 0x00000010)*/ +/*! Slice: isp_dec_intr_enbl_ex_vec:*/ +#define DEC_INTR_ENBL_EX_VEC +#define DEC_INTR_ENBL_EX_VEC_MASK 0xFFFFFFFFU +#define DEC_INTR_ENBL_EX_VEC_SHIFT 0U + +/*! Register: isp_dec_intr_enbl_ex2 (DEC_BASE + 0x00000014)*/ +/*! Slice: isp_dec_intr_enbl_ex2_vec:*/ +#define DEC_INTR_ENBL_EX2_VEC +#define DEC_INTR_ENBL_EX2_VEC_MASK 0xFFFFFFFFU +#define DEC_INTR_ENBL_EX2_VEC_SHIFT 0U + +/*! Register: isp_dec_read_config (DEC_BASE + 0x00000080)*/ +/*! Slice: isp_dec_read_config_compression_enable:*/ +#define DEC_READ_CONFIG_COMPRESSION_ENABLE +#define DEC_READ_CONFIG_COMPRESSION_ENABLE_MASK 0x00000001U +#define DEC_READ_CONFIG_COMPRESSION_ENABLE_SHIFT 0U + +/*! Slice: isp_dec_read_config_compression_format:*/ +#define DEC_READ_CONFIG_COMPRESSION_FORMAT +#define DEC_READ_CONFIG_COMPRESSION_FORMAT_MASK 0x000000F8U +#define DEC_READ_CONFIG_COMPRESSION_FORMAT_SHIFT 3U + +/*! Slice: isp_dec_read_config_compression_align_mode:*/ +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE_MASK 0x00030000U +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE_SHIFT 16U + +/*! Slice: isp_dec_read_config_compression_align_mode1:*/ +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE1 +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE1_MASK 0x001C0000U +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE1_SHIFT 18U + +/*! Slice: isp_dec_read_config_tile_mode:*/ +#define DEC_READ_CONFIG_TILE_MODE +#define DEC_READ_CONFIG_TILE_MODE_MASK 0x7E000000U +#define DEC_READ_CONFIG_TILE_MODE_SHIFT 25U + +/*! Register: isp_dec_read_ex_config (DEC_BASE + 0x00000100)*/ +/*! Slice: isp_dec_read_ex_config_bit_depth:*/ +#define DEC_READ_EX_CONFIG_BIT_DEPTH +#define DEC_READ_EX_CONFIG_BIT_DEPTH_MASK 0x00070000U +#define DEC_READ_EX_CONFIG_BIT_DEPTH_SHIFT 16U + +/*! Slice: isp_dec_read_ex_config_tile_y:*/ +#define DEC_READ_EX_CONFIG_TILE_Y +#define DEC_READ_EX_CONFIG_TILE_Y_MASK 0x00080000U +#define DEC_READ_EX_CONFIG_TILE_Y_SHIFT 19U + +/*! Register: isp_dec_write_config (DEC_BASE + 0x00000180)*/ +/*! Slice: isp_dec_write_config_compression_enable:*/ +#define DEC_WRITE_CONFIG_COMPRESSION_ENABLE +#define DEC_WRITE_CONFIG_COMPRESSION_ENABLE_MASK 0x00000001U +#define DEC_WRITE_CONFIG_COMPRESSION_ENABLE_SHIFT 0U + +/*! Slice: isp_dec_write_config_compression_format:*/ +#define DEC_WRITE_CONFIG_COMPRESSION_FORMAT +#define DEC_WRITE_CONFIG_COMPRESSION_FORMAT_MASK 0x000000F8U +#define DEC_WRITE_CONFIG_COMPRESSION_FORMAT_SHIFT 3U + +/*! Slice: isp_dec_write_config_compression_align_mode:*/ +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE_MASK 0x00030000U +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE_SHIFT 16U + +/*! Slice: isp_dec_write_config_compression_align_mode1:*/ +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE1 +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE1_MASK 0x001C0000U +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE1_SHIFT 18U + +/*! Slice: isp_dec_write_config_tile_mode:*/ +#define DEC_WRITE_CONFIG_TILE_MODE +#define DEC_WRITE_CONFIG_TILE_MODE_MASK 0x7E000000U +#define DEC_WRITE_CONFIG_TILE_MODE_SHIFT 25U + +/*! Register: isp_dec_write_ex_config (DEC_BASE + 0x00000200)*/ +/*! Slice: isp_dec_write_ex_config_bit_depth:*/ +#define DEC_WRITE_EX_CONFIG_BIT_DEPTH +#define DEC_WRITE_EX_CONFIG_BIT_DEPTH_MASK 0x00070000U +#define DEC_WRITE_EX_CONFIG_BIT_DEPTH_SHIFT 16U + +/*! Slice: isp_dec_write_ex_config_tile_y:*/ +#define DEC_WRITE_EX_CONFIG_TILE_Y +#define DEC_WRITE_EX_CONFIG_TILE_Y_MASK 0x00080000U +#define DEC_WRITE_EX_CONFIG_TILE_Y_SHIFT 19U + +/*! Register: isp_dec_read_buffer_base (DEC_BASE + 0x00000280)*/ +/*! Slice: isp_dec_read_buffer_base:*/ +#define DEC_READ_BUFFER_BASE +#define DEC_READ_BUFFER_BASE_MASK 0xFFFFFFFFU +#define DEC_READ_BUFFER_BASE_SHIFT 0U + +/*! Register: isp_dec_read_buffer_base_ex (DEC_BASE + 0x00000300)*/ +/*! Slice: isp_dec_read_buffer_base_ex:*/ +#define DEC_READ_BUFFER_BASE_EX +#define DEC_READ_BUFFER_BASE_EX_MASK 0x000000FFU +#define DEC_READ_BUFFER_BASE_EX_SHIFT 0U + +/*! Register: isp_dec_read_buffer_end (DEC_BASE + 0x00000380)*/ +/*! Slice: isp_dec_read_buffer_end:*/ +#define DEC_READ_BUFFER_END +#define DEC_READ_BUFFER_END_MASK 0xFFFFFFFFU +#define DEC_READ_BUFFER_END_SHIFT 0U + +/*! Register: isp_dec_read_buffer_end_ex (DEC_BASE + 0x00000400)*/ +/*! Slice: isp_dec_read_buffer_end_ex:*/ +#define DEC_READ_BUFFER_END_EX +#define DEC_READ_BUFFER_END_EX_MASK 0x000000FFU +#define DEC_READ_BUFFER_END_EX_SHIFT 0U + +/*! Register: isp_dec_read_flush_cache (DEC_BASE + 0x00000480)*/ +/*! Slice: isp_dec_read_flush_cache:*/ +#define DEC_READ_FLUSH_CACHE +#define DEC_READ_FLUSH_CACHE_MASK 0xFFFFFFFFU +#define DEC_READ_FLUSH_CACHE_SHIFT 0U + +/*! Register: isp_dec_read_flush_cache_ex (DEC_BASE + 0x00000500)*/ +/*! Slice: isp_dec_read_flush_cache_ex:*/ +#define DEC_READ_FLUSH_CACHE_EX +#define DEC_READ_FLUSH_CACHE_EX_MASK 0xFFFFFFFFU +#define DEC_READ_FLUSH_CACHE_EX_SHIFT 0U + +/*! Register: isp_dec_write_buffer_base (DEC_BASE + 0x00000580)*/ +/*! Slice: isp_dec_write_buffer_base:*/ +#define DEC_WRITE_BUFFER_BASE +#define DEC_WRITE_BUFFER_BASE_MASK 0xFFFFFFFFU +#define DEC_WRITE_BUFFER_BASE_SHIFT 0U + +/*! Register: isp_dec_write_buffer_base_ex (DEC_BASE + 0x00000600)*/ +/*! Slice: isp_dec_write_buffer_base_ex:*/ +#define DEC_WRITE_BUFFER_BASE_EX +#define DEC_WRITE_BUFFER_BASE_EX_MASK 0x000000FFU +#define DEC_WRITE_BUFFER_BASE_EX_SHIFT 0U + +/*! Register: isp_dec_write_buffer_end (DEC_BASE + 0x00000680)*/ +/*! Slice: isp_dec_write_buffer_end:*/ +#define DEC_WRITE_BUFFER_END +#define DEC_WRITE_BUFFER_END_MASK 0xFFFFFFFFU +#define DEC_WRITE_BUFFER_END_SHIFT 0U + +/*! Register: isp_dec_write_buffer_end_ex (DEC_BASE + 0x00000700)*/ +/*! Slice: isp_dec_write_buffer_end_ex:*/ +#define DEC_WRITE_BUFFER_END_EX +#define DEC_WRITE_BUFFER_END_EX_MASK 0x000000FFU +#define DEC_WRITE_BUFFER_END_EX_SHIFT 0U + +/*! Register: isp_dec_write_flush_cache (DEC_BASE + 0x00000780)*/ +/*! Slice: isp_dec_write_flush_cache:*/ +#define DEC_WRITE_FLUSH_CACHE +#define DEC_WRITE_FLUSH_CACHE_MASK 0xFFFFFFFFU +#define DEC_WRITE_FLUSH_CACHE_SHIFT 0U + +/*! Register: isp_dec_write_flush_cache_ex (DEC_BASE + 0x00000800)*/ +/*! Slice: isp_dec_write_flush_cache_ex:*/ +#define DEC_WRITE_FLUSH_CACHE_EX +#define DEC_WRITE_FLUSH_CACHE_EX_MASK 0xFFFFFFFFU +#define DEC_WRITE_FLUSH_CACHE_EX_SHIFT 0U + +/*! Register: isp_dec_read_cache_base (DEC_BASE + 0x00000880)*/ +/*! Slice: isp_dec_read_cache_base:*/ +#define DEC_READ_CACHE_BASE +#define DEC_READ_CACHE_BASE_MASK 0xFFFFFFFFU +#define DEC_READ_CACHE_BASE_SHIFT 0U + +/*! Register: isp_dec_read_cache_base_ex (DEC_BASE + 0x00000900)*/ +/*! Slice: isp_dec_read_cache_base_ex:*/ +#define DEC_READ_CACHE_BASE_EX +#define DEC_READ_CACHE_BASE_EX_MASK 0xFFFFFFFFU +#define DEC_READ_CACHE_BASE_EX_SHIFT 0U + +/*! Register: isp_dec_write_cache_base (DEC_BASE + 0x00000980)*/ +/*! Slice: isp_dec_write_cache_base:*/ +#define DEC_WRITE_CACHE_BASE +#define DEC_WRITE_CACHE_BASE_MASK 0xFFFFFFFFU +#define DEC_WRITE_CACHE_BASE_SHIFT 0U + +/*! Register: isp_dec_write_cache_base_ex (DEC_BASE + 0x00000A00)*/ +/*! Slice: isp_dec_write_cache_base_ex:*/ +#define DEC_WRITE_CACHE_BASE_EX +#define DEC_WRITE_CACHE_BASE_EX_MASK 0xFFFFFFFFU +#define DEC_WRITE_CACHE_BASE_EX_SHIFT 0U + +#endif /* _MRV_DEC_DEC_ALL_REGS_H */ diff --git a/vvcam/native/Makefile b/vvcam/native/Makefile new file mode 100755 index 0000000..6a12c45 --- /dev/null +++ b/vvcam/native/Makefile @@ -0,0 +1,24 @@ +include Param.mk +all: + echo VERSION_CFG = $(VERSION_CFG) + @cd gpio_i2c; make || exit $$?; cp vvcam_i2c.ko ../bin/ + @cd sensor; make || exit $$?; cp vvcam_sensor.ko ../bin/ + @cd flash_led; make || exit $$?; cp vvcam_flash_led.ko ../bin/ + @cd isp; make || exit $$?; cp vvcam_isp.ko ../bin/ + @cd soc; make || exit $$?; cp vvcam_soc.ko ../bin/ + @cd dw200; make || exit $$?; cp vvcam_dw200.ko ../bin/ + @cd dec400; make || exit $$?; cp vvcam_dec400.ko ../bin/ + @cd vi_pre; make || exit $$?; cp vi_pre.ko ../bin/ + @cd video; make || exit $$?; cp thead_video.ko ../bin/ +clean: + @cd gpio_i2c; make clean + @cd csi; make clean + @cd sensor; make clean + @cd flash_led; make clean + @cd isp; make clean + @cd soc; make clean + @cd dw200; make clean + @cd dec400; make clean + @cd vi_pre; make clean + @cd video; make clean +cleanall: diff --git a/vvcam/native/Param.mk b/vvcam/native/Param.mk new file mode 100755 index 0000000..445c1b6 --- /dev/null +++ b/vvcam/native/Param.mk @@ -0,0 +1,66 @@ +#VERSION_CFG := ISP8000NANO_V1802 +#KERNEL :=/opt/vsi_isp_kernel_tree/4.8.0-41-generic-x86/build +#KERNEL :=/lib/modules/$(shell uname -r)/build +KERNEL :=$(LINUX_DIR) +KERNEL_SRC :=$(KERNEL) + +EXTRA_CFLAGS += -DWITH_VVCAM +EXTRA_CFLAGS += -DWITH_VVCAM_DUAL + +EXTRA_CFLAGS += -DVVCSI0_BASE=0xDE200000 +EXTRA_CFLAGS += -DVVCSI1_BASE=0xDE300000 +EXTRA_CFLAGS += -DVVCSI_SIZE=0x00200000 + +EXTRA_CFLAGS += -DVVCAM_I2C0_BASE=0xDE3080f0 +EXTRA_CFLAGS += -DVVCAM_I2C1_BASE=0xDE3080f4 +EXTRA_CFLAGS += -DVVCAM_I2C_SIZE=0x00000004 + +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS0=8 +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS1=9 + + +ifeq ($(VERSION_CFG), ISP8000_V2009) +EXTRA_CFLAGS += -DVVISP0_BASE=0xDE600000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xDE700000 +else +EXTRA_CFLAGS += -DVVISP0_BASE=0xFFE4100000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xFFE4110000 +endif +EXTRA_CFLAGS += -DISP_REG_SIZE=0x00010000 + +EXTRA_CFLAGS += -DDWE_REG_BASE=0xFFE4130C00 +EXTRA_CFLAGS += -DDWE_REG_SIZE=0x00010000 +#EXTRA_CFLAGS += -DDWE_REG_RESET=0xffe4130000 +EXTRA_CFLAGS += -DVSE_REG_BASE=0xFFE4130000 +EXTRA_CFLAGS += -DVSE_REG_SIZE=0x00010000 +#EXTRA_CFLAGS += -DVSE_REG_RESET=0xffe4130000 + +EXTRA_CFLAGS += -DRESERVED_ISP0_MEM_BASE=0xA0000000 +EXTRA_CFLAGS += -DRESERVED_ISP0_MEM_SIZE=0x1000000 + +EXTRA_CFLAGS += -DRESERVED_ISP1_MEM_BASE=0xB0000000 +EXTRA_CFLAGS += -DRESERVED_ISP1_MEM_SIZE=0x1000000 + +EXTRA_CFLAGS += -DVVCTRL_BASE=0xFFE4040000 +EXTRA_CFLAGS += -DVVCTRL_SIZE=0x00001000 + +EXTRA_CFLAGS += -DISP_HW_NUMBER=1 +EXTRA_CFLAGS += -DUSE_FPGA +EXTRA_CFLAGS += -D$(VERSION_CFG) + +#SENSR0_TYPE := ov2775 +#SENSR1_TYPE := ov2775 + +#SENSR0_TYPE := imx334 +#SENSR1_TYPE := imx334 + +SENSR0_TYPE := ov5693 +SENSR1_TYPE := ov5693 + +#SENSR0_TYPE := imx290 +#SENSR1_TYPE := imx290 + +PLATFORM := gen6 + +FLASH_LED_TYPE1 := aw36515 +FLASH_LED_TYPE2 := aw36413 diff --git a/vvcam/native/Param_base.mk b/vvcam/native/Param_base.mk new file mode 100755 index 0000000..b8781f2 --- /dev/null +++ b/vvcam/native/Param_base.mk @@ -0,0 +1,56 @@ +#VERSION_CFG := ISP8000NANO_V1802 +#KERNEL :=/opt/vsi_isp_kernel_tree/4.8.0-41-generic-x86/build +KERNEL :=/lib/modules/$(shell uname -r)/build + +EXTRA_CFLAGS += -DWITH_VVCAM +EXTRA_CFLAGS += -DWITH_VVCAM_DUAL + +EXTRA_CFLAGS += -DVVCSI0_BASE=0xDE200000 +EXTRA_CFLAGS += -DVVCSI1_BASE=0xDE300000 +EXTRA_CFLAGS += -DVVCSI_SIZE=0x00200000 + +EXTRA_CFLAGS += -DVVCAM_I2C0_BASE=0xDE3080f0 +EXTRA_CFLAGS += -DVVCAM_I2C1_BASE=0xDE3080f4 +EXTRA_CFLAGS += -DVVCAM_I2C_SIZE=0x00000004 + +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS0=8 +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS1=9 + + +ifeq ($(VERSION_CFG), ISP8000_V2009) +EXTRA_CFLAGS += -DVVISP0_BASE=0xDE600000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xDE700000 +else +EXTRA_CFLAGS += -DVVISP0_BASE=0xDE000000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xDE100000 +endif +EXTRA_CFLAGS += -DISP_REG_SIZE=0x00010000 + +EXTRA_CFLAGS += -DDWE_REG_BASE=0xDE380C00 +EXTRA_CFLAGS += -DDWE_REG_SIZE=0x00010000 +EXTRA_CFLAGS += -DDWE_REG_RESET=0xDE308250 +EXTRA_CFLAGS += -DVSE_REG_BASE=0xDE380000 +EXTRA_CFLAGS += -DVSE_REG_SIZE=0x00010000 +EXTRA_CFLAGS += -DVSE_REG_RESET=0xDE308250 + + +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0x10000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x10000000 + +EXTRA_CFLAGS += -DVVCTRL_BASE=0xFFE4040000 +EXTRA_CFLAGS += -DVVCTRL_SIZE=0x00001000 + +EXTRA_CFLAGS += -DISP_HW_NUMBER=1 +EXTRA_CFLAGS += -DUSE_FPGA +EXTRA_CFLAGS += -D$(VERSION_CFG) + +SENSR0_TYPE := ov2775 +SENSR1_TYPE := ov2775 + +#SENSR0_TYPE := ov5693 +#SENSR1_TYPE := ov5693 + +PLATFORM := gen6 + +FLASH_LED_TYPE1 : = aw36515 +FLASH_LED_TYPE2 : = aw36413 diff --git a/vvcam/native/Param_thead_light.mk b/vvcam/native/Param_thead_light.mk new file mode 100755 index 0000000..4aa488f --- /dev/null +++ b/vvcam/native/Param_thead_light.mk @@ -0,0 +1,62 @@ +#VERSION_CFG := ISP8000NANO_V1802 +#KERNEL :=/opt/vsi_isp_kernel_tree/4.8.0-41-generic-x86/build +#KERNEL :=/lib/modules/$(shell uname -r)/build +KERNEL :=$(LINUX_DIR) + +EXTRA_CFLAGS += -DWITH_VVCAM +EXTRA_CFLAGS += -DWITH_VVCAM_DUAL + +EXTRA_CFLAGS += -DVVCSI0_BASE=0xDE200000 +EXTRA_CFLAGS += -DVVCSI1_BASE=0xDE300000 +EXTRA_CFLAGS += -DVVCSI_SIZE=0x00200000 + +EXTRA_CFLAGS += -DVVCAM_I2C0_BASE=0xDE3080f0 +EXTRA_CFLAGS += -DVVCAM_I2C1_BASE=0xDE3080f4 +EXTRA_CFLAGS += -DVVCAM_I2C_SIZE=0x00000004 + +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS0=8 +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS1=9 + + +ifeq ($(VERSION_CFG), ISP8000_V2009) +EXTRA_CFLAGS += -DVVISP0_BASE=0xDE600000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xDE700000 +else +EXTRA_CFLAGS += -DVVISP0_BASE=0xFFE4100000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xFFE4110000 +endif +EXTRA_CFLAGS += -DISP_REG_SIZE=0x00010000 + +EXTRA_CFLAGS += -DDWE_REG_BASE=0xFFE4130C00 +EXTRA_CFLAGS += -DDWE_REG_SIZE=0x00010000 +#EXTRA_CFLAGS += -DDWE_REG_RESET=0xffe4130000 +EXTRA_CFLAGS += -DVSE_REG_BASE=0xFFE4130000 +EXTRA_CFLAGS += -DVSE_REG_SIZE=0x00010000 +#EXTRA_CFLAGS += -DVSE_REG_RESET=0xffe4130000 + +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0xC0000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x10000000 + +EXTRA_CFLAGS += -DVVCTRL_BASE=0xDE308000 +EXTRA_CFLAGS += -DVVCTRL_SIZE=0x00001000 + +EXTRA_CFLAGS += -DISP_HW_NUMBER=1 +EXTRA_CFLAGS += -DUSE_FPGA +EXTRA_CFLAGS += -D$(VERSION_CFG) + +SENSR0_TYPE := ov2775 +SENSR1_TYPE := ov2775 + +#SENSR0_TYPE := imx334 +#SENSR1_TYPE := imx334 + +#SENSR0_TYPE := ov5693 +#SENSR1_TYPE := ov5693 + +#SENSR0_TYPE := imx290 +#SENSR1_TYPE := imx290 + +PLATFORM := gen6 + +FLASH_LED_TYPE1 : = aw36515 +FLASH_LED_TYPE2 : = aw36413 diff --git a/vvcam/native/bin/insmod.sh b/vvcam/native/bin/insmod.sh new file mode 100755 index 0000000..869755d --- /dev/null +++ b/vvcam/native/bin/insmod.sh @@ -0,0 +1,15 @@ +#!/bin/sh +#insmod vvcam_i2c +modprobe vvcam_sensor +#insmod vvcam_csi +modprobe bm_visys +modprobe bm_csi +modprobe vvcam_isp +modprobe vvcam_isp_ry +modprobe vvcam_soc +modprobe vvcam_dw200 +modprobe vi_pre +modprobe vvcam_dec400 +modprobe thead_video +modprobe vidmem +modprobe vvcam_flash_led diff --git a/vvcam/native/bin/rmmod.sh b/vvcam/native/bin/rmmod.sh new file mode 100755 index 0000000..59362f1 --- /dev/null +++ b/vvcam/native/bin/rmmod.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rmmod vvcam_dw200 +rmmod vvcam_soc +rmmod vvcam_isp +rmmod vvcam_isp_ry +rmmod vvcam_sensor +rmmod vvcam_csi +rmmod vvcam_i2c +rmmod vi_pre +rmmod vvcam_dec400 +rmmod thead_video +rmmod vidmem +rmmod vvcam_flash_led diff --git a/vvcam/native/csi/Makefile b/vvcam/native/csi/Makefile new file mode 100755 index 0000000..e291f03 --- /dev/null +++ b/vvcam/native/csi/Makefile @@ -0,0 +1,23 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_csi + +#obj-m +=$(TARGET).o +# +#$(TARGET)-objs += csi_ioctl.o +#$(TARGET)-objs += ./nwl/platform_nwl_csi_driver.o +#$(TARGET)-objs += vvcam_csi_driver.o + +EXTRA_CFLAGS += -I$(PWD)/ +EXTRA_CFLAGS += -I$(PWD)/nwl/ + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) +# make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam/native/csi/Makefilee b/vvcam/native/csi/Makefilee new file mode 100755 index 0000000..c543904 --- /dev/null +++ b/vvcam/native/csi/Makefilee @@ -0,0 +1,23 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_csi + +obj-m +=$(TARGET).o + +$(TARGET)-objs += csi_ioctl.o +$(TARGET)-objs += ./nwl/platform_nwl_csi_driver.o +$(TARGET)-objs += vvcam_csi_driver.o + +EXTRA_CFLAGS += -I$(PWD)/ +EXTRA_CFLAGS += -I$(PWD)/nwl/ + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + # make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam/native/csi/bm_csi_dphy.c b/vvcam/native/csi/bm_csi_dphy.c new file mode 100755 index 0000000..6bcc5b5 --- /dev/null +++ b/vvcam/native/csi/bm_csi_dphy.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "bm_printk.h" +#include "bm_csi_ioctl.h" +#include "bm_csi_hw.h" +#include "bm_csi_dphy.h" +#include "dw-dphy-rx.h" + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +#define REG_DPHY_OFFSET 0x40 + +int bm_csi_dphy_write_reg(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct bm_csi_reg_t reg; + check_retval(copy_from_user(®, args, sizeof(reg))); + struct dw_dphy_rx *dphy = drvdata->dphy; + + writel(reg.value, dphy->base_address + reg.offset); + bm_info("%s addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value); +} + +int bm_csi_dphy_init(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct dw_dphy_rx *dphy = drvdata->dphy; +/* + dphy->dphy_freq = 20000000; + dphy->phy_type = 1; + dphy->dphy_te_len = BIT12; + dphy->lanes_config = CTRL_4_LANES; + dphy->dphy_gen = GEN3; + dphy->max_lanes = CTRL_4_LANES; + dphy->lp_time = 1000; //ns + dphy->base_address = drvdata->base + REG_DPHY_OFFSET; + //dphy->dphy1_if_addr =visysreg + dw_dphy_reset(dphy); + dw_dphy_power_on(dphy); + dw_dphy_init(dphy); + */ + return 0; +} + +int bm_csi_dphy_uinit(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct dw_dphy_rx *dphy = &drvdata->dphy; + dw_dphy_reset(dphy); + dw_dphy_power_off(dphy); +} + +int bm_csi_dphy_reset(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct dw_dphy_rx *dphy = &drvdata->dphy; + dw_dphy_reset(dphy); +} diff --git a/vvcam/native/csi/bm_csi_dphy.h b/vvcam/native/csi/bm_csi_dphy.h new file mode 100755 index 0000000..cc3890b --- /dev/null +++ b/vvcam/native/csi/bm_csi_dphy.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _BM_CSI_DPHY_H_ +#define _BM_CSI_DPHY_H_ + +#include + +int dw_dphy_rx_probe(struct platform_device *pdev, void __iomem *dphy1_if_addr); +int dw_dphy_rx_remove(struct platform_device *pdev); + +#endif /*_BM_CSI_DPHY_H_ */ + + diff --git a/vvcam/native/csi/bm_csi_driver.c b/vvcam/native/csi/bm_csi_driver.c new file mode 100755 index 0000000..d5d90dd --- /dev/null +++ b/vvcam/native/csi/bm_csi_driver.c @@ -0,0 +1,331 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "bm_printk.h" +#include "bm_csi_ioctl.h" +#include "bm_csi_hw.h" +#include "bm_csi_dphy.h" +//#include "dw-csi-plat.h" + +#define BM_DRIVER_NAME "vivcsi" +#define BM_DRIVER_MAXCNT 3 + +static struct class *bm_driver_class; +static unsigned int bm_driver_major = 0; +static unsigned int bm_driver_minor = 0; +static unsigned int device_register_index = 0; + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +static unsigned int bm_csi_poll(struct file * filp, poll_table *wait) +{ + return 0; +} + +void bm_csi_work(struct work_struct *work) +{ +} + +irqreturn_t bm_csi_irq(int irq, void *dev_id) +{ + bm_info("enter %s\n", __func__); + return IRQ_HANDLED; +} + +static int bm_csi_open(struct inode * inode, struct file * file) +{ + struct bm_csi_drvdata *drvdata; + + bm_info("enter %s\n", __func__); + + drvdata = container_of(inode->i_cdev, struct bm_csi_drvdata, cdev); + file->private_data = drvdata; + + return 0; +}; + +static long bm_csi_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct bm_csi_drvdata *drvdata; + bm_info("enter %s\n", __func__); + + drvdata = file->private_data; + if (drvdata == NULL) { + bm_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + mutex_lock(&drvdata->mutex); + switch (cmd) { + case BMCSI_IOC_WRITE_REG: + ret = bm_csi_write_reg(drvdata, (void *)arg); + break; + case BMCSI_IOC_READ_REG: + ret = bm_csi_read_reg(drvdata, (void *)arg); + break; + case BMCSI_IOC_INIT: + ret = bm_csi_init(drvdata, (void *)arg); + break; + case BMCSI_IOC_EXIT: + ret = bm_csi_exit(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_RESET: + ret = bm_csi_reset(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_POWER: + ret = bm_csi_set_power(drvdata, (void *)arg); + break; + case BMCSI_IOC_G_POWER: + ret = bm_csi_get_power(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_CLOCK: + ret = bm_csi_set_clock(drvdata, (void *)arg); + break; + case BMCSI_IOC_G_CLOCK: + ret = bm_csi_get_clock(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_STREAM: + ret = bm_csi_set_stream(drvdata, (void *)arg); + break; + case BMCSI_IOC_G_STREAM: + ret = bm_csi_get_stream(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_FMT: + ret = bm_csi_set_fmt(drvdata, (void *)arg); + break; + case BMCSI_IOC_G_FMT: + ret = bm_csi_get_fmt(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_VC_SELECT: + ret = bm_csi_set_vc_select(drvdata, (void *)arg); + break; + case BMCSI_IOC_G_VC_SELECT: + ret = bm_csi_get_vc_select(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_LANE_CFG: + ret = bm_csi_set_lane_cfg(drvdata, (void *)arg); + break; + case BMCSI_IOC_MAX: + break; + default: + ret = -EPERM; + bm_err("%s: unsupported command %d", __func__, cmd); + break; + } + mutex_unlock(&drvdata->mutex); + return ret; +}; + +static int bm_csi_release(struct inode * inode, struct file * file) +{ + bm_info("enter %s\n", __func__); + return 0; +}; + +static int bm_csi_mmap(struct file *pFile, struct vm_area_struct *vma) +{ + bm_info("enter %s\n", __func__); + return 0; +}; + +struct file_operations bm_csi_fops = { + .owner = THIS_MODULE, + .open = bm_csi_open, + .release = bm_csi_release, + .unlocked_ioctl = bm_csi_ioctl, + .mmap = bm_csi_mmap, + .poll = bm_csi_poll, +}; + +static int bm_csi_probe(struct platform_device *pdev) +{ + int ret = 0; + struct bm_csi_drvdata *drvdata; + struct resource *iores_mem; + void __iomem *visys_addr; + + u32 value; + + bm_info("enter %s\n", __func__); + pdev->id = device_register_index; + if (pdev->id >= BM_DRIVER_MAXCNT) { + bm_err("%s:pdev id is %d error\n", __func__, pdev->id); + return -EINVAL; + } + + drvdata = devm_kzalloc(&pdev->dev,sizeof(struct bm_csi_drvdata), GFP_KERNEL); + if (drvdata == NULL) { + bm_err("%s:alloc struct drvdata error\n", __func__); + return -ENOMEM; + } + + iores_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + drvdata->base = devm_ioremap_resource(&pdev->dev, iores_mem); + bm_info("%s: [%s%d]: drvdata->base=0x%px, phy_addr base=0x%llx\n", __func__, + BM_DRIVER_NAME, pdev->id, drvdata->base, iores_mem->start); + drvdata->device_idx = pdev->id; + mutex_init(&drvdata->mutex); + drvdata->irq_num = platform_get_irq(pdev, 0); + bm_info("%s:[%s%d]: pdriver_dev->irq_num=%d\n", __func__, "BM_CSI", pdev->id, drvdata->irq_num); + + platform_set_drvdata(pdev, drvdata); + + if (pdev->id == 0) { + if (bm_driver_major == 0) { + ret = alloc_chrdev_region(&drvdata->devt, 0, BM_DRIVER_MAXCNT, BM_DRIVER_NAME); + if (ret != 0) { + bm_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + bm_driver_major = MAJOR(drvdata->devt); + bm_driver_minor = MINOR(drvdata->devt); + } else { + drvdata->devt = MKDEV(bm_driver_major, bm_driver_minor); + ret = register_chrdev_region(drvdata->devt, BM_DRIVER_MAXCNT, BM_DRIVER_NAME); + if (ret) { + bm_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + bm_driver_class = class_create(THIS_MODULE, BM_DRIVER_NAME); + if (IS_ERR(bm_driver_class)) { + bm_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + + drvdata->devt = MKDEV(bm_driver_major, bm_driver_minor + pdev->id); + cdev_init(&drvdata->cdev, &bm_csi_fops); + ret = cdev_add(&drvdata->cdev, drvdata->devt, 1); + if ( ret ) { + bm_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } else { + bm_info("%s[%d]:cdev_add OK, major=%d, minor=%d\n", __func__, __LINE__, + bm_driver_major, bm_driver_minor + pdev->id); + } + drvdata->class = bm_driver_class; + device_create(drvdata->class, NULL, drvdata->devt, + drvdata, "%s%d", BM_DRIVER_NAME, pdev->id); + + /*read version*/ + value = readl(drvdata->base + 0x0); + bm_info("offset=04, value is:0x%08x\n", value); + + //visys_addr = platform_get_resource(pdev, IORESOURCE_MEM, 1); + + visys_addr = devm_platform_ioremap_resource(pdev, 1); + dw_dphy_rx_probe(pdev, visys_addr); + + drvdata->reset = visys_addr; + dw_csi_probe(pdev); + + device_register_index++; + bm_info("exit %s:[%s%d]\n", __func__, BM_DRIVER_NAME, pdev->id); + + return 0; +} + +static int bm_csi_remove(struct platform_device *pdev) +{ + struct bm_csi_drvdata *drvdata; + + bm_info("enter %s\n", __func__); + dw_dphy_rx_remove(pdev); + dw_csi_remove(pdev); + + device_register_index--; + drvdata = platform_get_drvdata(pdev); + free_irq(drvdata->irq_num, drvdata); + cdev_del(&drvdata->cdev); + device_destroy(drvdata->class, drvdata->devt); + unregister_chrdev_region(drvdata->devt, BM_DRIVER_MAXCNT); + mutex_destroy(&drvdata->mutex); + if (device_register_index == 0) { + class_destroy(drvdata->class); + } + devm_kfree(&pdev->dev, drvdata); + + bm_info("exit %s\n", __func__); + return 0; +} + +static const struct of_device_id bm_csi_of_match[] = { + { .compatible = "thead,light-bm-csi", }, + { /* sentinel */ }, +}; + +static struct platform_driver bm_csi_driver = { + .probe = bm_csi_probe, + .remove = bm_csi_remove, + .driver = { + .name = BM_DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(bm_csi_of_match), + } +}; + +static int __init bm_csi_init_module(void) +{ + int ret = 0; + + bm_info("enter %s\n", __func__); + ret = platform_driver_register(&bm_csi_driver); + if (ret) { + bm_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit bm_csi_exit_module(void) +{ + bm_info("enter %s\n", __func__); + platform_driver_unregister(&bm_csi_driver); +} + +module_init(bm_csi_init_module); +module_exit(bm_csi_exit_module); + +MODULE_AUTHOR("Liu Yitong"); +MODULE_DESCRIPTION("BAREMETAL-CSI"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/csi/bm_csi_hw.c b/vvcam/native/csi/bm_csi_hw.c new file mode 100755 index 0000000..fdc6c79 --- /dev/null +++ b/vvcam/native/csi/bm_csi_hw.c @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "bm_printk.h" +#include "bm_csi_ioctl.h" +#include "bm_csi_hw.h" +#include "dw-dphy-rx.h" +#include "bm_csi_dphy.h" + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +int bm_csi_write_reg(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct bm_csi_reg_t reg; + check_retval(copy_from_user(®, args, sizeof(reg))); + writel(reg.value, drvdata->base + reg.offset); + bm_info("%s addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value); + return 0; +} + +int bm_csi_read_reg(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct bm_csi_reg_t reg; + check_retval(copy_from_user(®, args, sizeof(reg))); + reg.value = readl(drvdata->base + reg.offset); + check_retval(copy_to_user(args, ®, sizeof(reg))); + bm_info("%s addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value); + return 0; +} + +int bm_csi_init(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: csi init\n", __func__); + return 0; +} + +int bm_csi_exit(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: csi exit\n", __func__); + return 0; +} + +int bm_csi_reset(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: csi reset success\n", __func__); + dw_csi_soc_reset(drvdata->reset); + //bm_csi_dphy_reset(); + return 0; +} + +static int csi_power_on_sta = 0; +int bm_csi_set_power(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: csi set power\n", __func__); + check_retval(copy_from_user(&csi_power_on_sta, args, sizeof(csi_power_on_sta))); + dw_mipi_csi_s_power(&drvdata->csi_dev, csi_power_on_sta); + return 0; +} + +int bm_csi_get_power(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: csi get power\n", __func__); + check_retval(copy_to_user(args, &csi_power_on_sta, sizeof(csi_power_on_sta))); + return 0; +} + +int bm_csi_set_clock(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + check_retval(copy_to_user(args, &csi_power_on_sta, sizeof(csi_power_on_sta))); + return 0; +} + +int bm_csi_get_clock(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_set_stream(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_get_stream(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_set_fmt(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_get_fmt(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_set_vc_select(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_get_vc_select(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_set_lane_cfg(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} diff --git a/vvcam/native/csi/bm_csi_hw.h b/vvcam/native/csi/bm_csi_hw.h new file mode 100755 index 0000000..caa7984 --- /dev/null +++ b/vvcam/native/csi/bm_csi_hw.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _BM_CSI_HW_H_ +#define _BM_CSI_HW_H_ + +#include +#include +#include "dw-dphy-rx.h" +#include "dw-mipi-csi.h" +#include "dw-csi-data.h" +#include "dw-dphy-data.h" + +struct bm_csi_drvdata { + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex mutex; + unsigned int device_idx; + void __iomem *base; + void __iomem *reset; + struct dw_dphy_rx *dphy; + struct dw_csi csi_dev; + struct dw_csih_pdata csi_pdata; + struct dw_phy_pdata dphy_pdata; + int irq_num; + void *private; // can be bm_csi_drvdata_private, but not use now +}; + +struct bm_csi_drvdata_private { + int private_tmp; +}; + +int bm_csi_write_reg(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_read_reg(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_init(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_exit(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_reset(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_power(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_get_power(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_clock(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_get_clock(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_stream(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_get_stream(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_fmt(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_get_fmt(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_vc_select(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_get_vc_select(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_lane_cfg(struct bm_csi_drvdata *drvdata, void *__user args); + +/*csi dphy*/ +int bm_csi_dphy_write_reg(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_dphy_init(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_dphy_uinit(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_dphy_reset(struct bm_csi_drvdata *drvdata, void *__user args); + +void dw_csi_soc_reset(void __iomem *io_mem); +int dw_csi_probe(struct platform_device *pdev); +int dw_csi_remove(struct platform_device *pdev); + +#endif /* _BM_CSI_HW_H_*/ diff --git a/vvcam/native/csi/bm_csi_ioctl.h b/vvcam/native/csi/bm_csi_ioctl.h new file mode 100755 index 0000000..086f97e --- /dev/null +++ b/vvcam/native/csi/bm_csi_ioctl.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _BM_CSI_IOCTL_H_ +#define _BM_CSI_IOCTL_H_ + +#include + +enum { + BMCSI_IOC_S_RESET = 0x100, + BMCSI_IOC_S_POWER, + BMCSI_IOC_G_POWER, + BMCSI_IOC_S_CLOCK, + BMCSI_IOC_G_CLOCK, + BMCSI_IOC_S_STREAM, + BMCSI_IOC_G_STREAM, + BMCSI_IOC_S_FMT, + BMCSI_IOC_G_FMT, + BMCSI_IOC_S_VC_SELECT, + BMCSI_IOC_G_VC_SELECT, + BMCSI_IOC_S_LANE_CFG, + BMCSI_IOC_INIT, + BMCSI_IOC_EXIT, + BMCSI_IOC_WRITE_REG, + BMCSI_IOC_READ_REG, + BMCSI_IOC_MAX, +}; + +struct bm_csi_reg_t { + unsigned int offset; + unsigned int value; +}; + +#endif /* _BM_CSI_IOCTL_H_*/ diff --git a/vvcam/native/csi/bm_printk.h b/vvcam/native/csi/bm_printk.h new file mode 100755 index 0000000..4490bee --- /dev/null +++ b/vvcam/native/csi/bm_printk.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: LuChongzhi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __BM_PRINTK__ +#define __BM_PRINTK__ + +#include +#include +#include +#include +#include + +/* + * These can be used to print at the various log levels. + * All of these will print unconditionally, although note that pr_debug() + * and other debug macros are compiled out unless either DEBUG is defined + * or CONFIG_DYNAMIC_DEBUG is set. + */ +#define bm_emerg(fmt, ...) \ + printk(KERN_EMERG pr_fmt(fmt), ##__VA_ARGS__) +#define bm_alert(fmt, ...) \ + printk(KERN_ALERT pr_fmt(fmt), ##__VA_ARGS__) +#define bm_crit(fmt, ...) \ + printk(KERN_CRIT pr_fmt(fmt), ##__VA_ARGS__) +#define bm_err(fmt, ...) \ + printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) +#define bm_warning(fmt, ...) \ + printk(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__) +#define bm_warn pr_warning + +#ifdef DEBUG +#define bm_notice(fmt, ...) \ + printk(KERN_NOTICE pr_fmt(fmt), ##__VA_ARGS__) +#define bm_info(fmt, ...) \ + printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__) +#else +#define bm_notice(fmt, ...) +#define bm_info(fmt, ...) +#endif + +#endif /* __BM_PRINTK__ */ diff --git a/vvcam/native/csi/csi_common.h b/vvcam/native/csi/csi_common.h new file mode 100755 index 0000000..68b8a1c --- /dev/null +++ b/vvcam/native/csi/csi_common.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _CSI_COMMON_H_ +#define _CSI_COMMON_H_ + +extern int vvnative_csi_module_init(void * dev); +extern int vvnative_csi_module_exit(void * dev); + +extern int vvnative_csi_set_stream_control(void * dev); +extern int vvnative_csi_set_cfg(void * dev); +extern int vvnative_csi_set_bit_shift(void *dev); + +#endif diff --git a/vvcam/native/csi/csi_ioctl.c b/vvcam/native/csi/csi_ioctl.c new file mode 100755 index 0000000..78fff25 --- /dev/null +++ b/vvcam/native/csi/csi_ioctl.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "csi_ioctl.h" +#include "csi_common.h" + +long csi_priv_ioctl(struct vvcam_csi_dev *dev, unsigned int cmd, void __user *args) +{ + long ret = 0; + + switch (cmd) + { + case VVCSI_IOC_S_STREAM: + copy_from_user(&dev->streaming_enable, args, sizeof(dev->streaming_enable)); + ret = vvnative_csi_set_stream_control(dev); + break; + + case VVCSI_IOC_S_LANE_CFG: + copy_from_user(&dev->csi_lane_cfg, args, sizeof(dev->csi_lane_cfg)); + ret = vvnative_csi_set_cfg(dev); + break; + + case VVCSI_IOC_S_BIT_SHIFT: + copy_from_user(&dev->bit_width, args, sizeof(dev->bit_width)); + ret = vvnative_csi_set_bit_shift(dev); + break; + + default: + ret = 0; + break; + + } + + return ret; +} + + + + diff --git a/vvcam/native/csi/csi_ioctl.h b/vvcam/native/csi/csi_ioctl.h new file mode 100755 index 0000000..37c54e0 --- /dev/null +++ b/vvcam/native/csi/csi_ioctl.h @@ -0,0 +1,143 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _CSI_IOC_H_ +#define _CSI_IOC_H_ + +#ifndef __KERNEL__ +#include +#endif +#include + +enum { + VVCSI_IOC_S_RESET = _IO('r', 0), + VVCSI_IOC_S_POWER, + VVCSI_IOC_G_POWER, + VVCSI_IOC_S_CLOCK, + VVCSI_IOC_G_CLOCK, + VVCSI_IOC_S_STREAM, + VVCSI_IOC_G_STREAM, + VVCSI_IOC_S_FMT, + VVCSI_IOC_G_FMT, + VVCSI_IOC_S_VC_SELECT, + VVCSI_IOC_G_VC_SELECT, + VVCSI_IOC_S_LANE_CFG, + VVCSI_IOC_S_BIT_SHIFT, + VVCSI_IOC_MAX, +}; + +struct csi_vc_select_context { + uint32_t csi_vc_select_mode; + uint32_t vc_channel; +}; + +struct csi_format_context { + uint32_t format; + uint32_t width; + uint32_t height; +}; + +struct vvcam_csi_hardware_function_s +{ + int (*init)(void* dev); + int (*exit)(void* dev); + int (*reset)(void* dev); + int (*set_power)(void* dev); + int (*get_power)(void* dev); + int (*set_clock)(void* dev); + int (*get_clock)(void* dev); + int (*set_stream_control)(void* dev); + int (*get_stream_control)(void* dev); + int (*set_fmt)(void* dev); + int (*get_fmt)(void* dev); + int (*set_vc_select)(void* dev); + int (*get_vc_select)(void* dev); + int (*set_lane_cfg)(void* dev); +}; + +struct vvcam_csi_lane_cfg +{ + uint32_t mipi_lane_num; +}; + +#ifdef __KERNEL__ + +struct vvcam_csi_dev { + void __iomem *base; + char name[16]; + + int present; + int device_idx; + + uint32_t power_status; + uint32_t clock; + uint32_t bit_width; + + uint32_t streaming_enable; + struct csi_vc_select_context csi_vc_select; + struct csi_format_context csi_format; + struct vvcam_csi_hardware_function_s csi_hard_func; + struct vvcam_csi_lane_cfg csi_lane_cfg; + void * csi_private; +}; + +// internal functions + +long csi_priv_ioctl(struct vvcam_csi_dev *dev, unsigned int cmd, void __user *args); + +#else +//User space connections + + +#endif + +#endif // _CSI_IOC_H_ diff --git a/vvcam/native/csi/dphy_gen b/vvcam/native/csi/dphy_gen new file mode 100755 index 0000000..e69de29 diff --git a/vvcam/native/csi/dw-csi-data.h b/vvcam/native/csi/dw-csi-data.h new file mode 100755 index 0000000..10015fd --- /dev/null +++ b/vvcam/native/csi/dw-csi-data.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 platform data + * + * Author: Luis Oliveira + */ + +#include +#include "dw-mipi-csi-pltfrm.h" + +#ifndef __DW_CSI_DATA__ +#define __DW_CSI_DATA__ + +struct dw_csih_pdata { + u8 eotp_enabled; + u32 hs_freq; + u32 lanes; + u32 pclk; + u32 fps; + u32 bpp; + u8 id; +}; + +static const struct pdata_names csis[] = { + { .name = "dw-csi.0", }, + { .name = "dw-csi.1", }, +}; + +#endif /*__DW_CSI_DATA__ */ diff --git a/vvcam/native/csi/dw-csi-plat.c b/vvcam/native/csi/dw-csi-plat.c new file mode 100755 index 0000000..881a810 --- /dev/null +++ b/vvcam/native/csi/dw-csi-plat.c @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 Host controller driver. + * Platform driver + * + * Author: Luis Oliveira + */ + +#include "dw-csi-data.h" +#include "dw-dphy-data.h" +#include "dw-csi-plat.h" + +#include "bm_csi_hw.h" + +const struct mipi_dt csi_dt[] = { + { + .hex = CSI_2_YUV420_8, + .name = "YUV420_8bits", + }, { + .hex = CSI_2_YUV420_10, + .name = "YUV420_10bits", + }, { + .hex = CSI_2_YUV420_8_LEG, + .name = "YUV420_8bits_LEGACY", + }, { + .hex = CSI_2_YUV420_8_SHIFT, + .name = "YUV420_8bits_SHIFT", + }, { + .hex = CSI_2_YUV420_10_SHIFT, + .name = "YUV420_10bits_SHIFT", + }, { + .hex = CSI_2_YUV422_8, + .name = "YUV442_8bits", + }, { + .hex = CSI_2_YUV422_10, + .name = "YUV442_10bits", + }, { + .hex = CSI_2_RGB444, + .name = "RGB444", + }, { + .hex = CSI_2_RGB555, + .name = "RGB555", + }, { + .hex = CSI_2_RGB565, + .name = "RGB565", + }, { + .hex = CSI_2_RGB666, + .name = "RGB666", + }, { + .hex = CSI_2_RGB888, + .name = "RGB888", + }, { + .hex = CSI_2_RAW6, + .name = "RAW6", + }, { + .hex = CSI_2_RAW7, + .name = "RAW7", + }, { + .hex = CSI_2_RAW8, + .name = "RAW8", + }, { + .hex = CSI_2_RAW10, + .name = "RAW10", + }, { + .hex = CSI_2_RAW12, + .name = "RAW12", + }, { + .hex = CSI_2_RAW14, + .name = "RAW14", + }, { + .hex = CSI_2_RAW16, + .name = "RAW16", + }, +}; + +static struct mipi_fmt * +find_dw_mipi_csi_format(uint32_t mbus_code) +{ + unsigned int i; + + pr_info("%s entered mbus: 0x%x\n", __func__, mbus_code); + + for (i = 0; i < ARRAY_SIZE(dw_mipi_csi_formats); i++) + if (mbus_code == dw_mipi_csi_formats[i].mbus_code) { + pr_info("Found mbus 0x%x\n", dw_mipi_csi_formats[i].mbus_code); + return &dw_mipi_csi_formats[i]; + } + return NULL; +} + +static int dw_mipi_csi_enum_mbus_code(int index, uint32_t *code) +{ + if (index != 0) + return -EINVAL; + + *code = dw_mipi_csi_formats[index].mbus_code; + return 0; +} + +static struct mipi_fmt * +dw_mipi_csi_try_format(uint32_t mbus_code) +{ + struct mipi_fmt *fmt; + + fmt = find_dw_mipi_csi_format(mbus_code); + if (!fmt) + fmt = &dw_mipi_csi_formats[0]; + + return fmt; +} + +struct mipi_fmt * +dw_mipi_csi_get_format(struct dw_csi *dev) +{ + dev_info(dev->dev, + "%s got v4l2_mbus_pixelcode. 0x%x\n", __func__, + dev->fmt->mbus_code); + dev_info(dev->dev, + "%s got width. 0x%x\n", __func__, + dev->fmt->width); + dev_info(dev->dev, + "%s got height. 0x%x\n", __func__, + dev->fmt->height); + return dev->fmt; +} + +static int +dw_mipi_csi_set_fmt(struct platform_device *pdev, + uint32_t mbus_code, uint32_t width, uint32_t height) +{ + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *dev = &drvdata->csi_dev; + + struct mipi_fmt *dev_fmt = NULL; + int i; + dev_info(dev->dev, + "%s got mbus_pixelcode. 0x%x\n", __func__, + mbus_code); + + dev_fmt = dw_mipi_csi_try_format(mbus_code); + + dev_info(dev->dev, + "%s got v4l2_mbus_pixelcode. 0x%x\n", __func__, + dev_fmt->mbus_code); + if (!dev_fmt) + return -EINVAL; + + if (dev_fmt) { + dev->fmt->mbus_code = dev_fmt->mbus_code; + dev->fmt->width = width; + dev->fmt->height = height; + dw_mipi_csi_set_ipi_fmt(dev); + } + dev_info(dev->dev, "Width: %d, Height: %d of Demo\n", width, height); + if (width > 0 && height > 0) { + dw_mipi_csi_fill_timings(dev, width, height); +/* + demo_writel(dev, + DEMO_ACTIVE_WIDTH, fmt->format.width); + demo_writel(dev, + DEMO_ACTIVE_HEIGHT, fmt->format.height); +*/ + dev_vdbg(dev->dev, + "(core/demosaic) : width=%d/%d, height=%d/%d\n", + dev->hw.htotal - (dev->hw.hbp + + dev->hw.hsd + + dev->hw.hsa), + width, + dev->hw.vactive, + height); + dev_info(dev->dev, + "(core/demosaic) : width=%d/%d, height=%d/%d\n", + dev->hw.htotal - (dev->hw.hbp + + dev->hw.hsd + + dev->hw.hsa), + width, + dev->hw.vactive, + height); + + } else { + dev_vdbg(dev->dev, "%s unacceptable values 0x%x.\n", + __func__, width); + dev_vdbg(dev->dev, "%s unacceptable values 0x%x.\n", + __func__, height); + dev_info(dev->dev, "%s unacceptable values 0x%x.\n", + __func__, width); + dev_info(dev->dev, "%s unacceptable values 0x%x.\n", + __func__, height); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(csi_dt); i++) + if (csi_dt[i].hex == dev->ipi_dt) { + dev_vdbg(dev->dev, "Using data type %s\n", + csi_dt[i].name); + dev_info(dev->dev, "Using data type %s\n", + csi_dt[i].name); + } + return 0; +} + +static int +dw_mipi_csi_get_fmt(struct platform_device *pdev, + struct mipi_fmt *fmt) +{ + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *dev = &drvdata->csi_dev; + + struct mipi_fmt *mf = dw_mipi_csi_get_format(dev); + if (!mf) + return -EINVAL; + + mutex_lock(&dev->lock); + *fmt = *mf; + mutex_unlock(&dev->lock); + + return 0; +} + +int dw_mipi_csi_s_power(struct dw_csi *dev, int on) +{ + dev_info(dev->dev, "%s: on=%d\n", __func__, on); + + if (on) { + dw_mipi_csi_hw_stdby(dev); + dw_mipi_csi_start(dev); + } else { + phy_power_off(dev->phy); + dw_mipi_csi_mask_irq_power_off(dev); + /* reset data type */ + dev->ipi_dt = 0x0; + } + return 0; +} + +int dw_mipi_csi_log_status(struct dw_csi *dev) +{ + dw_mipi_csi_dump(dev); + + return 0; +} + +#if IS_ENABLED(CONFIG_VIDEO_ADV_DEBUG) +int +dw_mipi_csi_g_register(struct v4l2_subdev *sd, uint32_t reg) +{ + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *dev = &drvdata->csi_dev; + + dev_vdbg(dev->dev, "%s: reg=%llu\n", __func__, reg); + reg->val = dw_mipi_csi_read(dev, reg); + + return 0; +} +#endif + +#if 0 +static int dw_mipi_csi_init_cfg(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg) +{ + struct v4l2_mbus_framefmt *format = + v4l2_subdev_get_try_format(sd, cfg, 0); + + format->colorspace = V4L2_COLORSPACE_SRGB; + format->code = MEDIA_BUS_FMT_RGB888_1X24; + format->field = V4L2_FIELD_NONE; + + return 0; +} +#endif + +static irqreturn_t dw_mipi_csi_irq1(int irq, void *dev_id) +{ + struct dw_csi *csi_dev = dev_id; + + dw_mipi_csi_irq_handler(csi_dev); + + return IRQ_HANDLED; +} + +void dw_csi_soc_reset(void __iomem *io_mem) +{ +#define VISYS_SW_RST 0x100 + uint32_t reg_val = 0; + reg_val = readl(io_mem + VISYS_SW_RST); + reg_val &= ~(1 << 16); + writel(reg_val, io_mem + VISYS_SW_RST); + reg_val |= 1 << 16; + writel(reg_val, io_mem + VISYS_SW_RST); +} + +static const struct of_device_id dw_mipi_csi_of_match[]; + +int dw_csi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dw_csi *csi; + struct dw_dphy_rx *dphy; + struct dw_csih_pdata *pdata; + struct bm_csi_drvdata *drvdata; + int ret; + + if (!IS_ENABLED(CONFIG_OF)) + + dev_vdbg(dev, "Probing started\n"); + + /* Resource allocation */ + drvdata = platform_get_drvdata(pdev); + + csi = &drvdata->csi_dev; + dphy = drvdata->dphy; + pdata = &drvdata->csi_pdata; + + mutex_init(&csi->lock); + spin_lock_init(&csi->slock); + csi->dev = dev; + + /*set csi phy*/ + csi->phy = dphy->phy; + csi->base_address = drvdata->base; + if (IS_ERR(csi->base_address)) { + dev_err(dev, "base address not set.\n"); + return PTR_ERR(csi->base_address); + } + + csi->ctrl_irq_number = drvdata->irq_num; + if (csi->ctrl_irq_number < 0) { + dev_err(dev, "irq number %d not set.\n", csi->ctrl_irq_number); + ret = csi->ctrl_irq_number; + goto end; + } + + ret = devm_request_irq(dev, csi->ctrl_irq_number, + dw_mipi_csi_irq1, IRQF_SHARED, + dev_name(dev), csi); + if (ret) { + dev_err(dev, "irq csi %d failed\n", pdata->id); + goto end; + } + + csi->fmt = &dw_mipi_csi_formats[0]; + csi->fmt->mbus_code = dw_mipi_csi_formats[0].mbus_code; +/* + to do pad init +*/ + csi->hw.num_lanes = pdata->lanes; + csi->hw.pclk = pdata->pclk; + csi->hw.fps = pdata->fps; + csi->hw.dphy_freq = pdata->hs_freq; + + //csi soc reset + dw_csi_soc_reset(drvdata->reset); + #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_csi_create_capabilities_sysfs(pdev); +#endif + dw_mipi_csi_get_version(csi); + dw_mipi_csi_specific_mappings(csi); + dw_mipi_csi_mask_irq_power_off(csi); + + dev_info(dev, "DW MIPI CSI-2 Host registered successfully HW v%u.%u\n", + csi->hw_version_major, csi->hw_version_minor); + + ret = phy_init(csi->phy); + if (ret) { + dev_err(&csi->phy->dev, "phy init failed --> %d\n", ret); + goto end; + } + + return 0; +end: + return ret; +} + +int dw_csi_remove(struct platform_device *pdev) +{ + struct bm_csi_drvdata *drvdata; + drvdata = platform_get_drvdata(pdev); + dw_csi_remove_capabilities_sysfs(pdev); + //struct dw_csi *mipi_csi = &drvdata->csi_dev; + //csi soc reset + dw_csi_soc_reset(drvdata->reset); + dev_info(&pdev->dev, "DW MIPI CSI-2 Host module removed\n"); + + return 0; +} + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Luis Oliveira "); +MODULE_DESCRIPTION("Synopsys DesignWare MIPI CSI-2 Host Platform driver"); diff --git a/vvcam/native/csi/dw-csi-plat.h b/vvcam/native/csi/dw-csi-plat.h new file mode 100755 index 0000000..cc8117b --- /dev/null +++ b/vvcam/native/csi/dw-csi-plat.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 Synopsys, Inc. + * + * Synopsys DesignWare MIPI CSI-2 Host controller driver. + * Supported bus formats + * + * Author: Luis Oliveira + */ + +#ifndef _DW_CSI_PLAT_H__ +#define _DW_CSI_PLAT_H__ + +#include "dw-mipi-csi.h" + +/** Color Space Converter Block **/ +#define CSC_UNIT_NR 1 +#define CSC_COREID 0x0000 +#define CSC_CFG 0x0004 +#define CSC_COEF_A(x) (0x0008 + ((x) * 4)) +#define CSC_COEF_B(x) (0x0018 + ((x) * 4)) +#define CSC_COEF_C(x) (0x0028 + ((x) * 4)) +#define CSC_LIMIT_DN 0x0038 +#define CSC_LIMIT_UP 0x003C +#define CSC_VID_CFG 0x0040 + +/** Demosaic Block **/ +#define DEMO_CONTROL 0x0 +#define DEMO_GLOBAL_INT_EN 0x4 +#define DEMO_IP_INT_EN_REG 0x8 +#define DEMO_IP_INT_SATUS_REG 0xC +#define DEMO_ACTIVE_WIDTH 0x10 +#define DEMO_ACTIVE_HEIGHT 0x18 +#define DEMO_BAYER_PHASE 0x28//0x20 + +#define BAYER_RGGB 0x0 +#define BAYER_GRBG 0x1 +#define BAYER_GBRG 0x2 +#define BAYER_BGGR 0x3 + +/* Video formats supported by the MIPI CSI-2 */ +static struct mipi_fmt dw_mipi_csi_formats[] = { + { + /* RAW 8 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .depth = 8, + }, { + /* RAW 6 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR6_1X8, + .depth = 8, + }, { + /* RAW 7 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR7_1X8, + .depth = 8, + }, { + /* RAW 10 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .depth = 10, + }, { + /* RAW 8 */ + .mbus_code = 0x3001, + .depth = 8, + }, { + /* RAW 12 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .depth = 12, + }, { + /* RAW 14 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR14_1X14, + .depth = 14, + }, { + /* RAW 16 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR16_1X16, + .depth = 16, + }, { + /* RGB 666 */ + .mbus_code = MEDIA_BUS_FMT_RGB666_1X18, + .depth = 18, + }, { + /* RGB 565 */ + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_BE, + .depth = 16, + }, { + /* BGR 565 */ + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, + .depth = 16, + }, { + /* RGB 555 */ + .mbus_code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, + .depth = 16, + }, { + /* BGR 555 */ + .mbus_code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, + .depth = 16, + }, { + /* RGB 444 */ + .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE, + .depth = 16, + }, { + /* RGB 444 */ + .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE, + .depth = 16, + }, { + /* RGB 888 */ + .mbus_code = MEDIA_BUS_FMT_RGB888_2X12_LE, + .depth = 24, + }, { + /* BGR 888 */ + .mbus_code = MEDIA_BUS_FMT_RGB888_2X12_BE, + .depth = 24, + }, { + /* BGR 888 */ + .mbus_code = MEDIA_BUS_FMT_RGB888_1X24, + .depth = 24, + }, { + /* YUV 422 8-bit */ + .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16, + .depth = 16, + }, { + /* YUV 422 10-bit */ + .mbus_code = MEDIA_BUS_FMT_UYVY10_1X20, + .depth = 24, + }, { + /* YUV 420 8-bit LEGACY */ + .mbus_code = MEDIA_BUS_FMT_Y8_1X8, + .depth = 8, + }, { + /* YUV 420 8-bit LEGACY */ + .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16, + .depth = 24, + }, { + /* YUV 420 10-bit */ + .mbus_code = MEDIA_BUS_FMT_VUY8_1X24, + .depth = 24, + }, { + /* YUV 420 8-bit */ + .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, + .depth = 24, + }, { + /* YUV 420 10-bit */ + .mbus_code = MEDIA_BUS_FMT_Y10_1X10, + .depth = 10, + }, +}; + +#endif /* _DW_CSI_PLAT_H__ */ diff --git a/vvcam/native/csi/dw-csi-sysfs.c b/vvcam/native/csi/dw-csi-sysfs.c new file mode 100755 index 0000000..7cbeca2 --- /dev/null +++ b/vvcam/native/csi/dw-csi-sysfs.c @@ -0,0 +1,673 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 Host controller driver. + * SysFS components for the platform driver + * + * Author: Luis Oliveira + */ + +#include "dw-mipi-csi.h" +#include "bm_csi_hw.h" + +static ssize_t core_version_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "v.%d.%d*\n", csi_dev->hw_version_major, + csi_dev->hw_version_minor); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t n_lanes_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long lanes; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &lanes); + if (ret < 0) + return ret; + + if (lanes > 8) { + dev_err(dev, "Invalid number of lanes %lu\n", lanes); + return count; + } + + dev_info(dev, "Lanes %lu\n", lanes); + csi_dev->hw.num_lanes = lanes; + + return count; +} + +static ssize_t n_lanes_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.num_lanes); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t core_reset_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + /* Reset Controller and DPHY */ + phy_reset(csi_dev->phy); + dw_mipi_csi_reset(csi_dev); + + snprintf(buffer, 10, "Reset\n"); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t data_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long dt; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &dt); + if (ret < 0) + return ret; + + if (dt < 0x18 || dt > 0x2F) { + dev_err(dev, "Invalid data type %lx\n", dt); + return count; + } + + dev_info(dev, "Data type 0x%lx\n", dt); + csi_dev->ipi_dt = dt; + + dw_mipi_csi_set_ipi_fmt(csi_dev); + + return count; +} + +static ssize_t data_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->ipi_dt); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t hsa_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long hsa; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &hsa); + if (ret < 0) + return ret; + + if (hsa > 0xFFF) { + dev_err(dev, "Invalid HSA time %lx\n", hsa); + return count; + } + + dev_info(dev, "HSA time 0x%lx\n", hsa); + csi_dev->hw.hsa = hsa; + + return count; +} + +static ssize_t hsa_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.hsa); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t hbp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long hbp; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &hbp); + if (ret < 0) + return ret; + + if (hbp > 0xFFF) { + dev_err(dev, "Invalid HBP time %lx\n", hbp); + return count; + } + + dev_info(dev, "HBP time 0x%lx\n", hbp); + csi_dev->hw.hbp = hbp; + + return count; +} + +static ssize_t hbp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.hbp); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t hsd_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long hsd; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &hsd); + if (ret < 0) + return ret; + + if (hsd > 0xFFF) { + dev_err(dev, "Invalid HSD time %lx\n", hsd); + return count; + } + + dev_info(dev, "HSD time 0x%lx\n", hsd); + csi_dev->hw.hsd = hsd; + + return count; +} + +static ssize_t hsd_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.hsd); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t vsa_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long vsa; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &vsa); + if (ret < 0) + return ret; + + if (vsa > 0x3FF) { + dev_err(dev, "Invalid VSA period %lx\n", vsa); + return count; + } + + dev_info(dev, "VSA period 0x%lx\n", vsa); + csi_dev->hw.vsa = vsa; + + return count; +} + +static ssize_t vsa_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.vsa); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t vbp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long vbp; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &vbp); + if (ret < 0) + return ret; + + if (vbp > 0x2FF) { + dev_err(dev, "Invalid VBP period %lx\n", vbp); + return count; + } + + dev_info(dev, "VBP period 0x%lx\n", vbp); + csi_dev->hw.vbp = vbp; + + return count; +} + +static ssize_t vbp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.vbp); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t vfp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long vfp; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &vfp); + if (ret < 0) + return ret; + + if (vfp > 0x3ff) { + dev_err(dev, "Invalid VFP period %lx\n", vfp); + return count; + } + + dev_info(dev, "VFP period 0x%lx\n", vfp); + csi_dev->hw.vfp = vfp; + + return count; +} + +static ssize_t vfp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.vfp); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t virtual_channel_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long virtual_ch; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &virtual_ch); + if (ret < 0) + return ret; + + if ((signed int)virtual_ch < 0 || (signed int)virtual_ch > 8) { + dev_err(dev, "Invalid Virtual Channel %lu\n", virtual_ch); + return count; + } + + dev_info(dev, "Virtual Channel %lu\n", virtual_ch); + csi_dev->hw.virtual_ch = virtual_ch; + + return count; +} + +static ssize_t virtual_channel_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.virtual_ch); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t ipi_color_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long ipi_color_mode; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &ipi_color_mode); + if (ret < 0) + return ret; + + if ((signed int)ipi_color_mode < 0 || (signed int)ipi_color_mode > 1) { + dev_err(dev, + "Wrong Color Mode %lu, (48 bits -> 0 or 16 bits -> 1\n", + ipi_color_mode); + return count; + } + + dev_info(dev, "IPI Color mode %lu\n", ipi_color_mode); + csi_dev->hw.ipi_color_mode = ipi_color_mode; + + return count; +} + +static ssize_t ipi_color_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.ipi_color_mode); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t ipi_auto_flush_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long ipi_auto_flush; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &ipi_auto_flush); + if (ret < 0) + return ret; + + if ((signed int)ipi_auto_flush < 0 || (signed int)ipi_auto_flush > 1) { + dev_err(dev, + "Invalid Auto Flush Mode %lu, (No -> 0 or Yes -> 1\n", + ipi_auto_flush); + return count; + } + + dev_info(dev, "IPI Auto Flush %lu\n", ipi_auto_flush); + csi_dev->hw.ipi_auto_flush = ipi_auto_flush; + + return count; +} + +static ssize_t ipi_auto_flush_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.ipi_auto_flush); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t ipi_timings_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long ipi_mode; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &ipi_mode); + if (ret < 0) + return ret; + + if ((signed int)ipi_mode < 0 || (signed int)ipi_mode > 1) { + dev_err(dev, + "Invalid Timing Source %lu (Camera:0|Controller:1)\n", + ipi_mode); + return count; + } + + dev_info(dev, "IPI Color mode %lu\n", ipi_mode); + csi_dev->hw.ipi_mode = ipi_mode; + + return count; +} + +static ssize_t ipi_timings_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.ipi_mode); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t output_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long output; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &output); + if (ret < 0) + return ret; + + if ((signed int)output < 0 || (signed int)output > 1) { + dev_err(dev, + "Invalid Core output %lu to be used \ + (IPI-> 0 or IDI->1 or BOTH- 2\n", + output); + return count; + } + + dev_info(dev, "IPI Color mode %lu\n", output); + csi_dev->hw.output = output; + + return count; +} + +static ssize_t output_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.output); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t csi_power_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + + int ret; + unsigned long on; + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &on); + if (ret < 0) + return ret; + + dw_mipi_csi_s_power(csi_dev, on); + printk("csi set power: %lu\n", on); + + return count; +} + +static DEVICE_ATTR_RO(core_version); +static DEVICE_ATTR_RO(core_reset); +static DEVICE_ATTR_RW(n_lanes); +static DEVICE_ATTR_RW(data_type); +static DEVICE_ATTR_RW(hsa); +static DEVICE_ATTR_RW(hbp); +static DEVICE_ATTR_RW(hsd); +static DEVICE_ATTR_RW(vsa); +static DEVICE_ATTR_RW(vbp); +static DEVICE_ATTR_RW(vfp); +static DEVICE_ATTR_RW(virtual_channel); +static DEVICE_ATTR_RW(ipi_color_mode); +static DEVICE_ATTR_RW(ipi_auto_flush); +static DEVICE_ATTR_RW(ipi_timings_mode); +static DEVICE_ATTR_RW(output_type); +static DEVICE_ATTR_WO(csi_power); + +int dw_csi_create_capabilities_sysfs(struct platform_device *pdev) +{ + device_create_file(&pdev->dev, &dev_attr_core_version); + device_create_file(&pdev->dev, &dev_attr_core_reset); + device_create_file(&pdev->dev, &dev_attr_n_lanes); + device_create_file(&pdev->dev, &dev_attr_data_type); + device_create_file(&pdev->dev, &dev_attr_hsa); + device_create_file(&pdev->dev, &dev_attr_hbp); + device_create_file(&pdev->dev, &dev_attr_hsd); + device_create_file(&pdev->dev, &dev_attr_vsa); + device_create_file(&pdev->dev, &dev_attr_vbp); + device_create_file(&pdev->dev, &dev_attr_vfp); + device_create_file(&pdev->dev, &dev_attr_virtual_channel); + device_create_file(&pdev->dev, &dev_attr_ipi_color_mode); + device_create_file(&pdev->dev, &dev_attr_ipi_auto_flush); + device_create_file(&pdev->dev, &dev_attr_ipi_timings_mode); + device_create_file(&pdev->dev, &dev_attr_output_type); + device_create_file(&pdev->dev, &dev_attr_csi_power); + + return 0; +} + +int dw_csi_remove_capabilities_sysfs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_core_version); + device_remove_file(&pdev->dev, &dev_attr_core_reset); + device_remove_file(&pdev->dev, &dev_attr_n_lanes); + device_remove_file(&pdev->dev, &dev_attr_data_type); + device_remove_file(&pdev->dev, &dev_attr_hsa); + device_remove_file(&pdev->dev, &dev_attr_hbp); + device_remove_file(&pdev->dev, &dev_attr_hsd); + device_remove_file(&pdev->dev, &dev_attr_vsa); + device_remove_file(&pdev->dev, &dev_attr_vbp); + device_remove_file(&pdev->dev, &dev_attr_vfp); + device_remove_file(&pdev->dev, &dev_attr_virtual_channel); + device_remove_file(&pdev->dev, &dev_attr_ipi_color_mode); + device_remove_file(&pdev->dev, &dev_attr_ipi_auto_flush); + device_remove_file(&pdev->dev, &dev_attr_ipi_timings_mode); + device_remove_file(&pdev->dev, &dev_attr_output_type); + device_remove_file(&pdev->dev, &dev_attr_csi_power); + + return 0; +} diff --git a/vvcam/native/csi/dw-dphy-data.h b/vvcam/native/csi/dw-dphy-data.h new file mode 100755 index 0000000..bddd5eb --- /dev/null +++ b/vvcam/native/csi/dw-dphy-data.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY platform data + * + * Author: Luis Oliveira + */ + +#include +#include +#include + +#ifndef __DW_DPHY_DATA_H__ +#define __DW_DPHY_DATA_H__ + +struct dw_phy_pdata { + u32 dphy_frequency; + u8 dphy_te_len; + u32 config_8l; + u8 dphy_gen; + u8 phy_type; + u8 id; +}; + +static const struct pdata_names phys[] = { + { .name = "phy-dw-dphy.0.0", }, + { .name = "phy-dw-dphy.1.1", }, +}; + +struct dw_dphy_rx; + +struct plat_dw_dphy { + int (*get_resources)(struct device *dev, struct dw_dphy_rx *dphy); +}; +#endif /*__DW_DPHY_DATA_H__ */ diff --git a/vvcam/native/csi/dw-dphy-plat.c b/vvcam/native/csi/dw-dphy-plat.c new file mode 100755 index 0000000..3706ed6 --- /dev/null +++ b/vvcam/native/csi/dw-dphy-plat.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY controller driver. + * Platform driver + * + * Author: Luis Oliveira + */ + +#include +#include +#include "dw-dphy-rx.h" +#include "bm_csi_hw.h" + +/* Global variable for compatibility mode, this could be override later */ +static int phy_type = 1; //Changed to fit single phy 0 - single | 1 - 8 lanes phy + +module_param(phy_type, int, 0664); +MODULE_PARM_DESC(phy_type, "Disable compatibility mode for D-PHY G128"); + +static struct phy_ops dw_dphy_ops = { + .init = dw_dphy_init, + .reset = dw_dphy_reset, + .power_on = dw_dphy_power_on, + .power_off = dw_dphy_power_off, + .owner = THIS_MODULE, +}; + +static int get_resources(struct device *dev, struct dw_dphy_rx *dphy) +{ + int ret = 0; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_phy_pdata *pdata = &drvdata->dphy_pdata; + + dphy->dphy_freq = pdata->dphy_frequency; + dphy->dphy_te_len = pdata->dphy_te_len; + dphy->dphy_gen = pdata->dphy_gen; + drvdata->dphy = dphy; + + return ret; +} + +static int phy_register(struct device *dev) +{ + int ret = 0; + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + struct dw_phy_pdata *pdata = &drvdata->dphy_pdata; + + ret = phy_create_lookup(dphy->phy, + phys[pdata->id].name, + csis[pdata->id].name); + if (ret) + dev_err(dev, "Failed to create dphy lookup\n"); + else + dev_warn(dev, "Created dphy lookup [%s] --> [%s]\n", + phys[pdata->id].name, csis[pdata->id].name); + + + return ret; +} + +static void phy_unregister(struct device *dev) +{ + if (!dev->of_node) { + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + struct dw_phy_pdata *pdata = &drvdata->dphy_pdata; + + phy_remove_lookup(dphy->phy, + phys[pdata->id].name, csis[pdata->id].name); + dev_warn(dev, "Removed dphy lookup [%s] --> [%s]\n", + phys[pdata->id].name, csis[pdata->id].name); + } +} + +#define REG_DPHY_OFFSET 0x40 +int dw_dphy_rx_probe(struct platform_device *pdev, void __iomem *dphy1_if_addr) +{ + struct device *dev = &pdev->dev; + struct dw_dphy_rx *dphy; + struct bm_csi_drvdata *drvdata; + + dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); + if (!dphy) + return -ENOMEM; + + drvdata = platform_get_drvdata(pdev); + dphy->base_address = drvdata->base + REG_DPHY_OFFSET; + drvdata->dphy= dphy; + dphy->dphy1_if_addr = dphy1_if_addr; + + if (IS_ERR(dphy->base_address)) { + dev_err(&pdev->dev, "error requesting base address\n"); + return PTR_ERR(dphy->base_address); + } + + if (get_resources(dev, dphy)) { + dev_err(dev, "failed to parse PHY resources\n"); + return -EINVAL; + } + + dphy->phy = devm_phy_create(dev, NULL, &dw_dphy_ops); + if (IS_ERR(dphy->phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(dphy->phy); + } + + phy_set_drvdata(dphy->phy, dphy); + + if (phy_register(dev)) { + dev_err(dev, "failed to register PHY\n"); + return -EINVAL; + } + + dphy->lp_time = 1000; /* 1000 ns */ + dphy->lanes_config = dw_dphy_setup_config(dphy); + + dev_info(&dphy->phy->dev, "Probing dphy finished\n"); + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_dphy_create_capabilities_sysfs(pdev); +#endif + + return 0; +} + +int dw_dphy_rx_remove(struct platform_device *pdev) +{ + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + + dev_info(&dphy->phy->dev, "phy removed\n"); + phy_unregister(&pdev->dev); + dw_dphy_remove_capabilities_sysfs(pdev); + + return 0; +} + +MODULE_DESCRIPTION("Synopsys DesignWare MIPI DPHY Rx driver"); +MODULE_AUTHOR("Luis Oliveira "); +MODULE_LICENSE("GPL v2"); diff --git a/vvcam/native/csi/dw-dphy-rx.c b/vvcam/native/csi/dw-dphy-rx.c new file mode 100755 index 0000000..79c5038 --- /dev/null +++ b/vvcam/native/csi/dw-dphy-rx.c @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY controller driver + * Core functions + * + * Author: Luis Oliveira + */ + +#include "dw-dphy-rx.h" +#include "bm_csi_dphy.h" +#include "bm_printk.h" + +struct range_dphy_gen2 { + u32 freq; + u8 hsfregrange; +}; + +struct range_dphy_gen2 range_gen2[] = { + { 80, 0x00 }, { 90, 0x10 }, { 100, 0x20 }, { 110, 0x30 }, + { 120, 0x01 }, { 130, 0x11 }, { 140, 0x21 }, { 150, 0x31 }, + { 160, 0x02 }, { 170, 0x12 }, { 180, 0x22 }, { 190, 0x32 }, + { 205, 0x03 }, { 220, 0x13 }, { 235, 0x23 }, { 250, 0x33 }, + { 275, 0x04 }, { 300, 0x14 }, { 325, 0x05 }, { 350, 0x15 }, + { 400, 0x25 }, { 450, 0x06 }, { 500, 0x16 }, { 550, 0x07 }, + { 600, 0x17 }, { 650, 0x08 }, { 700, 0x18 }, { 750, 0x09 }, + { 800, 0x19 }, { 850, 0x29 }, { 900, 0x39 }, { 950, 0x0A }, + { 1000, 0x1A }, { 1050, 0x2A }, { 1100, 0x3A }, { 1150, 0x0B }, + { 1200, 0x1B }, { 1250, 0x2B }, { 1300, 0x3B }, { 1350, 0x0C }, + { 1400, 0x1C }, { 1450, 0x2C }, { 1500, 0x3C }, { 1550, 0x0D }, + { 1600, 0x1D }, { 1650, 0x2D }, { 1700, 0x0E }, { 1750, 0x1E }, + { 1800, 0x2E }, { 1850, 0x3E }, { 1900, 0x0F }, { 1950, 0x1F }, + { 2000, 0x2F }, +}; + +struct range_dphy_gen3 { + u32 freq; + u8 hsfregrange; + u32 osc_freq_target; +}; + +struct range_dphy_gen3 range_gen3[] = { + { 80, 0x00, 0x1B6 }, { 90, 0x10, 0x1B6 }, { 100, 0x20, 0x1B6 }, + { 110, 0x30, 0x1B6 }, { 120, 0x01, 0x1B6 }, { 130, 0x11, 0x1B6 }, + { 140, 0x21, 0x1B6 }, { 150, 0x31, 0x1B6 }, { 160, 0x02, 0x1B6 }, + { 170, 0x12, 0x1B6 }, { 180, 0x22, 0x1B6 }, { 190, 0x32, 0x1B6 }, + { 205, 0x03, 0x1B6 }, { 220, 0x13, 0x1B6 }, { 235, 0x23, 0x1B6 }, + { 250, 0x33, 0x1B6 }, { 275, 0x04, 0x1B6 }, { 300, 0x14, 0x1B6 }, + { 325, 0x25, 0x1B6 }, { 350, 0x35, 0x1B6 }, { 400, 0x05, 0x1B6 }, + { 450, 0x16, 0x1B6 }, { 500, 0x26, 0x1B6 }, { 550, 0x37, 0x1B6 }, + { 600, 0x07, 0x1B6 }, { 650, 0x18, 0x1B6 }, { 700, 0x28, 0x1B6 }, + { 750, 0x39, 0x1B6 }, { 800, 0x09, 0x1B6 }, { 850, 0x19, 0x1B6 }, + { 900, 0x29, 0x1B6 }, { 950, 0x3A, 0x1B6 }, { 1000, 0x0A, 0x1B6 }, + { 1050, 0x1A, 0x1B6 }, { 1100, 0x2A, 0x1B6 }, { 1150, 0x3B, 0x1B6 }, + { 1200, 0x0B, 0x1B6 }, { 1250, 0x1B, 0x1B6 }, { 1300, 0x2B, 0x1B6 }, + { 1350, 0x3C, 0x1B6 }, { 1400, 0x0C, 0x1B6 }, { 1450, 0x1C, 0x1B6 }, + { 1500, 0x2C, 0x1B6 }, { 1550, 0x3D, 0x10F }, { 1600, 0x0D, 0x118 }, + { 1650, 0x1D, 0x121 }, { 1700, 0x2E, 0x12A }, { 1750, 0x3E, 0x132 }, + { 1800, 0x0E, 0x13B }, { 1850, 0x1E, 0x144 }, { 1900, 0x2F, 0x14D }, + { 1950, 0x3F, 0x155 }, { 2000, 0x0F, 0x15E }, { 2050, 0x40, 0x167 }, + { 2100, 0x41, 0x170 }, { 2150, 0x42, 0x178 }, { 2200, 0x43, 0x181 }, + { 2250, 0x44, 0x18A }, { 2300, 0x45, 0x193 }, { 2350, 0x46, 0x19B }, + { 2400, 0x47, 0x1A4 }, { 2450, 0x48, 0x1AD }, { 2500, 0x49, 0x1B6 } +}; + +u8 dw_dphy_setup_config(struct dw_dphy_rx *dphy) +{ +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +#if 0 + int ret; + + if (dphy->max_lanes == CTRL_4_LANES) { + dev_vdbg(&dphy->phy->dev, "CONFIG 4L\n"); + return CTRL_4_LANES; + } + if (IS_ENABLED(CONFIG_OF)) { + ret = gpio_request(dphy->config_8l, "config"); + if (ret < 0) { + dev_vdbg(&dphy->phy->dev, + "could not acquire config (err=%d)\n", ret); + return ret; + } + ret = gpio_get_value(dphy->config_8l); + gpio_free(dphy->config_8l); + } else { + ret = dphy->config_8l; + } + + dev_vdbg(&dphy->phy->dev, + "Booting in [%s] mode\n", + ret == CTRL_8_LANES ? "8L" : "4+4L"); + return ret; +#endif +#endif /* CONFIG_DWC_MIPI_TC_DPHY_GEN3 */ + return CTRL_4_LANES; +} + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +//extern int k_bm_visys_write_reg(uint32_t offset, uint32_t value); +//extern int k_bm_visys_read_reg(uint32_t offset, uint32_t *value); + +void dw_dphy_if_write(struct dw_dphy_rx *dphy, u32 address, u32 data) +{ + writel(data, dphy->dphy1_if_addr + address); + //k_bm_visys_write_reg(address, data); +} + +u32 dw_dphy_if_read(struct dw_dphy_rx *dphy, u32 address) +{ + u32 if1 = 0; + if1 = readl(dphy->dphy1_if_addr + address); + //k_bm_visys_read_reg(address, &if1); + return if1; +} +#endif + +void dw_dphy_write(struct dw_dphy_rx *dphy, u32 address, u32 data) +{ + iowrite32(data, dphy->base_address + address); + + if (dphy->lanes_config == CTRL_4_LANES) + return; + return; + + if (address == R_CSI2_DPHY_TST_CTRL0) + iowrite32(data, dphy->base_address + R_CSI2_DPHY2_TST_CTRL0); + else if (address == R_CSI2_DPHY_TST_CTRL1) + iowrite32(data, dphy->base_address + R_CSI2_DPHY2_TST_CTRL1); +} + +u32 dw_dphy_read(struct dw_dphy_rx *dphy, u32 address) +{ + int dphy1 = 0, dphy2 = 0; + + dphy1 = ioread32(dphy->base_address + address); + + if (dphy->lanes_config == CTRL_4_LANES) + goto end; + + goto end; + + if (address == R_CSI2_DPHY_TST_CTRL0) + dphy2 = ioread32(dphy->base_address + R_CSI2_DPHY2_TST_CTRL0); + else if (address == R_CSI2_DPHY_TST_CTRL1) + dphy2 = ioread32(dphy->base_address + R_CSI2_DPHY2_TST_CTRL1); + else + return -ENODEV; +end: + return dphy1; +} + +void dw_dphy_write_msk(struct dw_dphy_rx *dev, u32 address, u32 data, u8 shift, + u8 width) +{ + u32 temp = dw_dphy_read(dev, address); + u32 mask = (1 << width) - 1; + + temp &= ~(mask << shift); + temp |= (data & mask) << shift; + dw_dphy_write(dev, address, temp); +} + +static void dw_dphy_te_12b_write(struct dw_dphy_rx *dphy, u16 addr, u8 data) +{ + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, PHY_TESTDIN, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)(addr >> 8), + PHY_TESTDIN, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)addr, PHY_TESTDIN, + 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)data, PHY_TESTDIN, + 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); +} + +static void dw_dphy_te_8b_write(struct dw_dphy_rx *dphy, u8 addr, u8 data) +{ + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_TST_CTRL1, addr); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_TST_CTRL1, data); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); +} + +static void dw_dphy_te_write(struct dw_dphy_rx *dphy, u16 addr, u8 data) +{ + dphy->dphy_te_len = BIT12; + if (dphy->dphy_te_len == BIT12) + dw_dphy_te_12b_write(dphy, addr, data); + else + dw_dphy_te_8b_write(dphy, addr, data); +} + +static int dw_dphy_te_12b_read(struct dw_dphy_rx *dphy, u32 addr) +{ + u8 ret; + + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, PHY_TESTDIN, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)(addr >> 8), + PHY_TESTDIN, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)addr, PHY_TESTDIN, + 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, 0, PHY_TESTDIN); + ret = dw_dphy_read_msk(dphy, R_CSI2_DPHY_TST_CTRL1, PHY_TESTDOUT, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1); + + return ret; +} + +static int dw_dphy_te_8b_read(struct dw_dphy_rx *dphy, u32 addr) +{ + u8 ret; + + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, addr, PHY_TESTDIN, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTDIN, 8); + ret = dw_dphy_read_msk(dphy, R_CSI2_DPHY_TST_CTRL1, PHY_TESTDOUT, 8); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1); + + return ret; +} + +int dw_dphy_te_read(struct dw_dphy_rx *dphy, u32 addr) +{ + int ret; + + if (dphy->dphy_te_len == BIT12) + ret = dw_dphy_te_12b_read(dphy, addr); + else + ret = dw_dphy_te_12b_read(dphy, addr); + //ret = dw_dphy_te_8b_read(dphy, addr); + + return ret; +} + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +static void dw_dphy_if_init(struct dw_dphy_rx *dphy) +{ + bm_info("enter %s\n", __func__); + //dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + //dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, TX_PHY); + //dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1); + //dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, GLUELOGIC); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RX_PHY); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1); +} +#endif + +static void dw_dphy_gen3_12bit_tc_power_up(struct dw_dphy_rx *dphy, uint8_t hsfregrange) +{ +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, GLUELOGIC); +#endif + dw_dphy_te_write(dphy, CFGCLKFREQRANGE_RX, 0x1C); + dw_dphy_te_write(dphy, 0x6, hsfregrange); + + /* CLKSEL | UPDATEPLL | SHADOW_CLEAR | SHADOW_CTRL | FORCEPLL */ + //dw_dphy_te_write(dphy, BYPASS, 0x3F); + + /* IO_DS3 | IO_DS2 | IO_DS1 | IO_DS0 */ + if (dphy->dphy_freq > 1500) + dw_dphy_te_write(dphy, IO_DS, 0x0F); +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RX_PHY | 0x2); +#endif +} + +static void dw_dphy_gen3_8bit_tc_power_up(struct dw_dphy_rx *dphy) +{ + u32 input_freq = dphy->dphy_freq / 1000; +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, GLUELOGIC); + dw_dphy_te_write(dphy, CFGCLKFREQRANGE_RX, 0x1C); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RX_PHY); +#endif + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX0_MSB, 0x03); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX0_LSB, 0x02); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX1_MSB, 0x03); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX1_LSB, 0x02); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX2_MSB, 0x03); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX2_LSB, 0x02); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX3_MSB, 0x03); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX3_LSB, 0x02); + dw_dphy_te_write(dphy, BANDGAP_CTRL, 0x80); + + if (input_freq < 2000) + dw_dphy_te_write(dphy, HS_RX_CTRL_LANE0, 0xC0); + + if (input_freq < 1000) { + dw_dphy_te_write(dphy, HS_RX_CTRL_LANE1, 0xC0); + dw_dphy_te_write(dphy, HS_RX_CTRL_LANE2, 0xC0); + dw_dphy_te_write(dphy, HS_RX_CTRL_LANE3, 0xC0); + } +} + +int dw_dphy_g118_settle(struct dw_dphy_rx *dphy) +{ + u32 input_freq, total_settle, settle_time, byte_clk, lp_time; + + lp_time = dphy->lp_time; + input_freq = dphy->dphy_freq / 1000; + + settle_time = (8 * (1000000 / (input_freq))) + 115000; + byte_clk = (8000000 / (input_freq)); + total_settle = (settle_time + lp_time * 1000) / byte_clk; + + if (total_settle > 0xFF) + total_settle = 0xFF; + + return total_settle; +} + +static void dw_dphy_pwr_down(struct dw_dphy_rx *dphy) +{ + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + if (dphy->lanes_config == CTRL_8_LANES) + dw_dphy_write_msk(dphy, R_CSI2_DPHY2_TST_CTRL0, 0, PHY_TESTCLK, + 1); + + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0); +} + +static void dw_dphy_pwr_up(struct dw_dphy_rx *dphy) +{ + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + if (dphy->lanes_config == CTRL_8_LANES) + dw_dphy_write_msk(dphy, R_CSI2_DPHY2_TST_CTRL0, 1, PHY_TESTCLK, + 1); + dev_vdbg(&dphy->phy->dev, "DPHY power up.\n"); + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); +} + +static int dw_dphy_gen3_12bit_configure(struct dw_dphy_rx *dphy) +{ + u32 input_freq = dphy->dphy_freq; + u8 range = 0; + + dev_vdbg(&dphy->phy->dev, "12bit: PHY GEN 3: Freq: %u\n", input_freq); + for (range = 0; (range < ARRAY_SIZE(range_gen3) - 1) && + ((input_freq / 1000) > range_gen3[range].freq); + range++) + ; + + dw_dphy_gen3_12bit_tc_power_up(dphy, range_gen3[range].hsfregrange); + + uint8_t lp_time = dphy->lp_time; + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_17, lp_time);//SET SETTLE TIME + + dw_dphy_te_write(dphy, RX_SYS_1, range_gen3[range].hsfregrange); + dw_dphy_te_write(dphy, RX_SYS_0, 0x20); + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_2, + (u8)range_gen3[range].osc_freq_target); + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_3, + (u8)(range_gen3[range].osc_freq_target >> 8)); + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_4, 0x01); + + if (dphy->phy_type) { + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_1, 0x01); + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_0, 0x80); + } + + if (dphy->phy_type || input_freq <= 1500) + dw_dphy_te_write(dphy, RX_SYS_7, 0x38); + + return 0; +} + +static int dw_dphy_gen3_8bit_configure(struct dw_dphy_rx *dphy) +{ + u32 input_freq = dphy->dphy_freq; + u8 data; + u8 range = 0; + + dev_vdbg(&dphy->phy->dev, "8bit: PHY GEN 3: Freq: %u\n", input_freq); + for (range = 0; (range < ARRAY_SIZE(range_gen3) - 1) && + ((input_freq / 1000) > range_gen3[range].freq); + range++) + ; + + dw_dphy_te_write(dphy, RX_SKEW_CAL, dw_dphy_g118_settle(dphy)); + data = 1 << 7 | range_gen3[range].hsfregrange; + dw_dphy_te_write(dphy, HSFREQRANGE_8BIT, data); + dw_dphy_gen3_8bit_tc_power_up(dphy); + + return 0; +} + +static int dw_dphy_gen2_configure(struct dw_dphy_rx *dphy) +{ + u32 input_freq = dphy->dphy_freq; + u8 data; + u8 range = 0; + + /* provide an initial active-high test clear pulse in TESTCLR */ + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1); + + dev_vdbg(&dphy->phy->dev, "PHY GEN 2: Freq: %u\n", input_freq); + for (range = 0; (range < ARRAY_SIZE(range_gen2) - 1) && + ((input_freq / 1000) > range_gen2[range].freq); range++) + ; + + data = range_gen2[range].hsfregrange << 1; + dw_dphy_te_write(dphy, HSFREQRANGE_8BIT, data); + + return 0; +} + +static int dw_dphy_configure(struct dw_dphy_rx *dphy) +{ + + bm_info("enter %s\n", __func__); + dw_dphy_pwr_down(dphy); + dphy->dphy_gen = GEN3; + if (dphy->dphy_gen == GEN3) { +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_dphy_if_init(dphy); +#endif + dphy->dphy_te_len = BIT12; + if (dphy->dphy_te_len == BIT12) + dw_dphy_gen3_12bit_configure(dphy); + else + dw_dphy_gen3_8bit_configure(dphy); + } else { + dw_dphy_gen2_configure(dphy); + } + dw_dphy_pwr_up(dphy); + + return 0; +} + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + +#if 0 +int dw_dphy_if_set_idelay(struct dw_dphy_rx *dphy, u8 dly, u8 cells) +{ + u32 val = 0; + + dw_dphy_if_write(dphy, IDLYCFG, 0); + dw_dphy_if_write(dphy, IDLYSEL, cells); + dw_dphy_if_write(dphy, IDLYCNTINVAL, dly); + + /* Pulse Value Set */ + dw_dphy_if_write(dphy, IDLYCFG, 1); + usleep_range(10, 20); + dw_dphy_if_write(dphy, IDLYCFG, 0); + + /* Pulse IDELAY CTRL Reset */ + dw_dphy_if_write(dphy, DPHY1REGRSTN, 0); + usleep_range(10, 20); + dw_dphy_if_write(dphy, DPHY1REGRSTN, 1); + + /* Get Value*/ + val = dw_dphy_if_read(dphy, IDLYCNTOUTVAL); + + if (val != dly) { + dev_vdbg(&dphy->phy->dev, + "odelay config failed, set %d get %d", dly, val); + return -EINVAL; + } + + return 0; +} + +int dw_dphy_if_get_idelay(struct dw_dphy_rx *dphy) +{ + return dw_dphy_if_read(dphy, IDLYCNTOUTVAL); +} + +int dw_dphy_if_set_idelay_lane(struct dw_dphy_rx *dphy, u8 dly, u8 lane) +{ + int cell; + + switch (lane) { + case 0: + for (cell = 3; cell <= 10; cell++) + dw_dphy_if_set_idelay(dphy, dly, cell); + break; + case 1: + for (cell = 14; cell <= 21; cell++) + dw_dphy_if_set_idelay(dphy, dly, cell); + break; + case 2: + for (cell = 24; cell <= 31; cell++) + dw_dphy_if_set_idelay(dphy, dly, cell); + break; + case 3: + for (cell = 34; cell <= 41; cell++) + dw_dphy_if_set_idelay(dphy, dly, cell); + break; + case 4: /* ALL */ + dw_dphy_if_set_idelay(dphy, dly, 0x7F); + break; + default: + dev_err(&dphy->phy->dev, "Lane Value not recognized\n"); + return -1; + } + return 0; +} +#endif +#endif + +int dw_dphy_init(struct phy *phy) +{ + struct dw_dphy_rx *dphy = phy_get_drvdata(phy); + + dev_warn(&dphy->phy->dev, "Init DPHY.\n"); + + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0); + + return 0; +} + +static int dw_dphy_set_phy_state(struct dw_dphy_rx *dphy, u32 on) +{ + + u8 hs_freq; + + bm_info("enter %s\n", __func__); + dphy->lanes_config = dw_dphy_setup_config(dphy); + + if (dphy->dphy_te_len == BIT12) + hs_freq = RX_SYS_1; + else + hs_freq = HSFREQRANGE_8BIT; + + if (on) { + dw_dphy_configure(dphy); + dev_info(&dphy->phy->dev, + "HS Code: 0X%x\n", dw_dphy_te_read(dphy, hs_freq)); + } else { + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + } + + return 0; +} + +int dw_dphy_power_on(struct phy *phy) +{ + struct dw_dphy_rx *dphy = phy_get_drvdata(phy); + + dev_info(&dphy->phy->dev, "DPHY Power ON\n"); + bm_info("enter %s\n", __func__); + + return dw_dphy_set_phy_state(dphy, 1); +} + +int dw_dphy_power_off(struct phy *phy) +{ + struct dw_dphy_rx *dphy = phy_get_drvdata(phy); + + return dw_dphy_set_phy_state(dphy, 0); +} + +int dw_dphy_reset(struct phy *phy) +{ + struct dw_dphy_rx *dphy = phy_get_drvdata(phy); + + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + usleep_range(100, 200); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); + + return 0; +} diff --git a/vvcam/native/csi/dw-dphy-rx.h b/vvcam/native/csi/dw-dphy-rx.h new file mode 100755 index 0000000..5ee1999 --- /dev/null +++ b/vvcam/native/csi/dw-dphy-rx.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY controller driver + * + * Author: Luis Oliveira + */ + +#ifndef __PHY_SNPS_DPHY_RX_H__ +#define __PHY_SNPS_DPHY_RX_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* DPHY interface register bank*/ + +#define R_CSI2_DPHY_SHUTDOWNZ 0x0 +#define R_CSI2_DPHY_RSTZ 0x4 +#define R_CSI2_DPHY_RX 0x8 +#define R_CSI2_DPHY_STOPSTATE 0xC +#define R_CSI2_DPHY_TST_CTRL0 0x10 +#define R_CSI2_DPHY_TST_CTRL1 0x14 +#define R_CSI2_DPHY2_TST_CTRL0 0x18 +#define R_CSI2_DPHY2_TST_CTRL1 0x1C + +enum dphy_id_mask { + DPHY_ID_LANE_SUPPORT = 0, + DPHY_ID_IF = 4, + DPHY_ID_GEN = 8, +}; + +enum dphy_gen_values { + GEN1, + GEN2, + GEN3, +}; + +enum dphy_interface_length { + BIT8 = 8, + BIT12 = 12, +}; + +enum tst_ctrl0 { + PHY_TESTCLR, + PHY_TESTCLK, +}; + +enum tst_ctrl1 { + PHY_TESTDIN = 0, + PHY_TESTDOUT = 8, + PHY_TESTEN = 16, +}; + +enum lanes_config_values { + CTRL_4_LANES, + CTRL_8_LANES, +}; + +enum dphy_tc { + CFGCLKFREQRANGE_TX = 0x02, + CFGCLKFREQRANGE_RX = 0x05, + BYPASS = 0x20, + IO_DS = 0x30, +}; + +enum dphy_8bit_interface_addr { + BANDGAP_CTRL = 0x24, + HS_RX_CTRL_LANE0 = 0x42, + HSFREQRANGE_8BIT = 0x44, + OSC_FREQ_TARGET_RX0_LSB = 0x4e, + OSC_FREQ_TARGET_RX0_MSB = 0x4f, + HS_RX_CTRL_LANE1 = 0x52, + OSC_FREQ_TARGET_RX1_LSB = 0x5e, + OSC_FREQ_TARGET_RX1_MSB = 0x5f, + RX_SKEW_CAL = 0x7e, + HS_RX_CTRL_LANE2 = 0x82, + OSC_FREQ_TARGET_RX2_LSB = 0x8e, + OSC_FREQ_TARGET_RX2_MSB = 0x8f, + HS_RX_CTRL_LANE3 = 0x92, + OSC_FREQ_TARGET_RX3_LSB = 0x9e, + OSC_FREQ_TARGET_RX3_MSB = 0x9f, +}; + +enum dphy_12bit_interface_addr { + RX_SYS_0 = 0x01, + RX_SYS_1 = 0x02, + RX_SYS_7 = 0x08, + RX_RX_STARTUP_OVR_0 = 0xe0, + RX_RX_STARTUP_OVR_1 = 0xe1, + RX_RX_STARTUP_OVR_2 = 0xe2, + RX_RX_STARTUP_OVR_3 = 0xe3, + RX_RX_STARTUP_OVR_4 = 0xe4, + RX_RX_STARTUP_OVR_17 = 0xf1, +}; + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +/* Testchip interface register bank */ +#define IDLYCFG 0x00 +#define IDLYSEL 0x04 +#define IDLYCNTINVAL 0x08 +#define IDLYCNTOUTVAL 0x0c +#define DPHY1REGRSTN 0x10 +#define DPHYZCALSTAT 0x14 +#define DPHYZCALCTRL 0x18 +#define DPHYLANE0STAT 0x1c +#define DPHYLANE1STAT 0x20 +#define DPHYLANE2STAT 0x24 +#define DPHYLANE3STAT 0x28 +#define DPHYCLKSTAT 0x2c +#define DPHYZCLKCTRL 0x30 +#define TCGENPURPOSOUT 0x34 +#define TCGENPURPOSIN 0x38 +#define DPHYGENERICOUT 0x3c +#define DPHYGENERICIN 0x40 + +#define DPHYGLUEIFTESTER 0x180 +#define DPHYID 0x100 + +#define DPHY_DEFAULT_FREQ 300000 + +enum glueiftester { + RESET = 0, + TX_PHY = 0x100 | (0x1 << 4), + RX_PHY = 0x100 | (0x2 << 4), + GLUELOGIC = 0x100 | (0x4 << 4), +}; +#endif + +/** + * struct phy specifies associated phy component + * struct cfg to pass mipi dphy specific configurations + * @lanes_config lanes configuration + * @dphy_freq operating frequency of the d-phy (mbps) + * @phy_type dphy can be of two types, passed here + * @dphy_gen dphy can be of three generations, passed here + * @dphy_te_len bus width + * @max_lanes maximum number of lanes + * @lp_time time in low-power + * @base_address memmory address of dphy test interface + * @dphy1_if_addr gluelogic dphy 1 memmory address of interface + * @dphy2_if_addr gluelogic dphy 2 memmory address of interface + * @config_8l eight lanes configuration + */ + +struct dw_dphy_rx { + struct phy *phy; + struct phy_configure_opts_mipi_dphy *cfg; + u32 lanes_config; + u32 dphy_freq; //MBPS + u32 phy_type; + u32 dphy_gen; + u32 dphy_te_len; + u32 max_lanes; + u32 lp_time; + void __iomem *base_address; +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + void __iomem *dphy1_if_addr; + void __iomem *dphy2_if_addr; + u8 config_8l; + u8 (*get_config_8l)(struct device *dev, struct dw_dphy_rx *dphy); +#endif + u8 (*phy_register)(struct device *dev); + void (*phy_unregister)(struct device *dev); +}; + +int dw_dphy_init(struct phy *phy); +int dw_dphy_reset(struct phy *phy); +int dw_dphy_power_off(struct phy *phy); +int dw_dphy_power_on(struct phy *phy); +u8 dw_dphy_setup_config(struct dw_dphy_rx *dphy); +void dw_dphy_write(struct dw_dphy_rx *dphy, u32 address, u32 data); +u32 dw_dphy_read(struct dw_dphy_rx *dphy, u32 address); +int dw_dphy_te_read(struct dw_dphy_rx *dphy, u32 addr); + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +u32 dw_dphy_if_read(struct dw_dphy_rx *dphy, u32 address); +int dw_dphy_if_get_idelay(struct dw_dphy_rx *dphy); +int dw_dphy_if_set_idelay_lane(struct dw_dphy_rx *dphy, u8 dly, u8 lane); +int dw_dphy_create_capabilities_sysfs(struct platform_device *pdev); +int dw_dphy_remove_capabilities_sysfs(struct platform_device *pdev); + +static inline +u32 dw_dphy_if_read_msk(struct dw_dphy_rx *dphy, + u32 address, u8 shift, u8 width) +{ + return (dw_dphy_if_read(dphy, address) >> shift) & ((1 << width) - 1); +} +#endif /*IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)*/ + +static inline struct phy *dw_dphy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct dw_dphy_rx *dphy = dev_get_drvdata(dev); + + return dphy->phy; +} + +static inline +u32 dw_dphy_read_msk(struct dw_dphy_rx *dev, u32 address, u8 shift, u8 width) +{ + return (dw_dphy_read(dev, address) >> shift) & ((1 << width) - 1); +} +#endif /*__PHY_SNPS_DPHY_RX_H__*/ diff --git a/vvcam/native/csi/dw-dphy-sysfs.c b/vvcam/native/csi/dw-dphy-sysfs.c new file mode 100755 index 0000000..30aeae0 --- /dev/null +++ b/vvcam/native/csi/dw-dphy-sysfs.c @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY controller driver. + * SysFS components for the platform driver + * + * Author: Luis Oliveira + */ + +//#define DEBUG 1 +#include "dw-dphy-rx.h" +#include "bm_csi_hw.h" + +static ssize_t dphy_reset_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + char buffer[15]; + + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + usleep_range(100, 200); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t dphy_freq_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int ret; + unsigned long freq; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + + ret = kstrtoul(buf, 10, &freq); + if (ret < 0) + return ret; + + if (freq > 2500) { + dev_info(dev, "Freq must be under 2500 Mhz\n"); + return count; + } + if (freq < 80) { + dev_info(dev, "Freq must be over 80 Mhz\n"); + return count; + } + + dev_vdbg(dev, "Data Rate %lu Mbps\n", freq); + dphy->dphy_freq = freq*1000; + + return count; +} + +static ssize_t dphy_freq_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + char buffer[15]; + + snprintf(buffer, + sizeof(buffer), + "Freq %d\n", dphy->dphy_freq); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t dphy_addr_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + unsigned long addr; + int ret; + + ret = kstrtoul(buf, 10, &addr); + + if (ret < 0) + return ret; + + //payload = (u16)val; + //addr = (u16)(val >> 16); + + //dev_vdbg(dev, "addr 0x%lX\n", val); + //dev_vdbg(dev, "payload: 0x%X\n", addr); + //dev_vdbg(dev, "Addr [0x%x] -> 0x%x\n", (unsigned int)addr, + // dw_dphy_te_read(dphy, addr)); + + printk("<0>""addr 0x%lX\n", addr); + printk("<0>""Addr [0x%x] -> 0x%x\n", (unsigned int)addr, + dw_dphy_te_read(dphy, addr)); + + + return count; +} + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +#if 0 +static ssize_t idelay_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + char buffer[15]; + + snprintf(buffer, + sizeof(buffer), "idelay %d\n", dw_dphy_if_get_idelay(dphy)); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t idelay_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + unsigned long val; + u8 lane, delay; + int ret; + + ret = kstrtoul(buf, 16, &val); + if (ret < 0) + return ret; + + lane = (u8)val; + delay = (u8)(val >> 8); + + dev_vdbg(dev, "Lanes %u\n", lane); + dev_vdbg(dev, "Delay %u\n", delay); + + dw_dphy_if_set_idelay_lane(dphy, delay, lane); + + return count; +} +#endif +#endif + +static ssize_t len_config_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + unsigned long length; + int ret; + + ret = kstrtoul(buf, 10, &length); + if (ret < 0) + return ret; + + if (length == BIT8) + dev_vdbg(dev, "Configured for 8-bit interface\n"); + else if (length == BIT12) + dev_vdbg(dev, "Configured for 12-bit interface\n"); + else + return count; + + dphy->dphy_te_len = length; + + return count; +} + +static ssize_t len_config_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + char buffer[20]; + + snprintf(buffer, sizeof(buffer), "Length %d\n", dphy->dphy_te_len); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t dw_dphy_g118_settle_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + unsigned long lp_time; + int ret; + + ret = kstrtoul(buf, 10, &lp_time); + if (ret < 0) + return ret; + + if (lp_time > 1 && lp_time < 10000) { + dphy->lp_time = lp_time; + } else { + dev_vdbg(dev, "Invalid Value configuring for 1000 ns\n"); + dphy->lp_time = 1000; + } + + dphy->lp_time = lp_time; + + return count; +} + +static ssize_t dw_dphy_g118_settle_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + char buffer[10]; + + snprintf(buffer, sizeof(buffer), "Settle %d ns\n", dphy->lp_time); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static DEVICE_ATTR_RO(dphy_reset); +static DEVICE_ATTR_RW(dphy_freq); +static DEVICE_ATTR_WO(dphy_addr); +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +//static DEVICE_ATTR_RW(idelay); +#endif +static DEVICE_ATTR_RW(len_config); +static DEVICE_ATTR_RW(dw_dphy_g118_settle); + +int dw_dphy_create_capabilities_sysfs(struct platform_device *pdev) +{ + device_create_file(&pdev->dev, &dev_attr_dphy_reset); + device_create_file(&pdev->dev, &dev_attr_dphy_freq); + device_create_file(&pdev->dev, &dev_attr_dphy_addr); +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +// device_create_file(&pdev->dev, &dev_attr_idelay); +#endif + device_create_file(&pdev->dev, &dev_attr_len_config); + device_create_file(&pdev->dev, &dev_attr_dw_dphy_g118_settle); + return 0; +} + +int dw_dphy_remove_capabilities_sysfs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_dphy_reset); + device_remove_file(&pdev->dev, &dev_attr_dphy_freq); + device_remove_file(&pdev->dev, &dev_attr_dphy_addr); +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +// device_create_file(&pdev->dev, &dev_attr_idelay); +#endif + device_remove_file(&pdev->dev, &dev_attr_len_config); + device_remove_file(&pdev->dev, &dev_attr_dw_dphy_g118_settle); + return 0; +} diff --git a/vvcam/native/csi/dw-mipi-csi-pltfrm.h b/vvcam/native/csi/dw-mipi-csi-pltfrm.h new file mode 100755 index 0000000..948db4e --- /dev/null +++ b/vvcam/native/csi/dw-mipi-csi-pltfrm.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 Host media entities + * + * Author: Luis Oliveira + */ + +#ifndef __DW_MIPI_CSI_PLTFRM_INCLUDES_H_ +#define __DW_MIPI_CSI_PLTFRM_INCLUDES_H_ + +#include +#include +#include +#include + +#define MAX_WIDTH 3280 +#define MAX_HEIGHT 1852 + +/* The subdevices' group IDs. */ +#define GRP_ID_SENSOR (10) +#define GRP_ID_CSI (20) +#define GRP_ID_VIF (30) +#define GRP_ID_VIDEODEV (40) + +#define CSI_MAX_ENTITIES (2) +#define VIF_MAX_ENTITIES (2) +#define PLAT_MAX_SENSORS (2) + +struct pdata_names { + char *name; +}; + +enum video_dev_pads { + VIDEO_DEV_SD_PAD_SINK_VIF1, + VIDEO_DEV_SD_PAD_SINK_VIF2, + VIDEO_DEV_SD_PAD_SOURCE_DMA, + VIDEO_DEV_SD_PADS_NUM, +}; + +enum vif_pads { + VIF_PAD_SINK_CSI, + VIF_PAD_SOURCE_DMA, + VIF_PADS_NUM, +}; + +enum mipi_csi_pads { + CSI_PAD_SINK, + CSI_PAD_SOURCE, + CSI_PADS_NUM, +}; + +struct plat_csi_source_info { + u16 flags; + u16 mux_id; +}; + +struct plat_csi_fmt { + char *name; + u32 mbus_code; + u32 fourcc; + u8 depth; +}; + +struct plat_csi_media_pipeline; + +/* + * Media pipeline operations to be called from within a video node, i.e. the + * last entity within the pipeline. Implemented by related media device driver. + */ +struct plat_csi_media_pipeline_ops { + int (*prepare)(struct plat_csi_media_pipeline *p, + struct media_entity *me); + int (*unprepare)(struct plat_csi_media_pipeline *p); + int (*open)(struct plat_csi_media_pipeline *p, struct media_entity *me, + bool resume); + int (*close)(struct plat_csi_media_pipeline *p); + int (*set_stream)(struct plat_csi_media_pipeline *p, bool state); + int (*set_format)(struct plat_csi_media_pipeline *p, + struct v4l2_subdev_format *fmt); +}; + +struct plat_csi_video_entity { + struct video_device vdev; + struct plat_csi_media_pipeline *pipe; +}; + +struct plat_csi_media_pipeline { + struct media_pipeline mp; + const struct plat_csi_media_pipeline_ops *ops; +}; + +static inline struct plat_csi_video_entity +*vdev_to_plat_csi_video_entity(struct video_device *vdev) +{ + return container_of(vdev, struct plat_csi_video_entity, vdev); +} + +#define plat_csi_pipeline_call(ent, op, args...) \ + (!(ent) ? -ENOENT : (((ent)->pipe->ops && (ent)->pipe->ops->op) ? \ + (ent)->pipe->ops->op(((ent)->pipe), ##args) : -ENOIOCTLCMD)) \ + +#endif /* __DW_MIPI_CSI_PLTFRM_INCLUDES_H_ */ diff --git a/vvcam/native/csi/dw-mipi-csi.c b/vvcam/native/csi/dw-mipi-csi.c new file mode 100755 index 0000000..cea2c8b --- /dev/null +++ b/vvcam/native/csi/dw-mipi-csi.c @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 Host controller driver + * Core MIPI CSI-2 functions + * + * Author: Luis Oliveira + */ + +#include "dw-mipi-csi.h" + +static struct R_CSI2 reg = { + .VERSION = 0x00, + .N_LANES = 0x04, + .CTRL_RESETN = 0x08, + .INTERRUPT = 0x0C, + .DATA_IDS_1 = 0x10, + .DATA_IDS_2 = 0x14, + .IPI_MODE = 0x80, + .IPI_VCID = 0x84, + .IPI_DATA_TYPE = 0x88, + .IPI_MEM_FLUSH = 0x8C, + .IPI_HSA_TIME = 0x90, + .IPI_HBP_TIME = 0x94, + .IPI_HSD_TIME = 0x98, + .IPI_HLINE_TIME = 0x9C, + .IPI_SOFTRSTN = 0xA0, + .IPI_ADV_FEATURES = 0xAC, + .IPI_VSA_LINES = 0xB0, + .IPI_VBP_LINES = 0xB4, + .IPI_VFP_LINES = 0xB8, + .IPI_VACTIVE_LINES = 0xBC, + .INT_PHY_FATAL = 0xe0, + .MASK_INT_PHY_FATAL = 0xe4, + .FORCE_INT_PHY_FATAL = 0xe8, + .INT_PKT_FATAL = 0xf0, + .MASK_INT_PKT_FATAL = 0xf4, + .FORCE_INT_PKT_FATAL = 0xf8, + .INT_PHY = 0x110, + .MASK_INT_PHY = 0x114, + .FORCE_INT_PHY = 0x118, + .INT_LINE = 0x130, + .MASK_INT_LINE = 0x134, + .FORCE_INT_LINE = 0x138, + .INT_IPI = 0x140, + .MASK_INT_IPI = 0x144, + .FORCE_INT_IPI = 0x148, +}; + +struct interrupt_type csi_int = { + .PHY_FATAL = BIT(0), + .PKT_FATAL = BIT(1), + .PHY = BIT(16), +}; + +#define dw_print(VAR) \ + dev_info(csi_dev->dev, "%s: 0x%x: %X\n", "##VAR##",\ + VAR, dw_mipi_csi_read(csi_dev, VAR)) + +void dw_mipi_csi_write_part(struct dw_csi *dev, u32 address, u32 data, + u8 shift, u8 width) +{ + u32 mask = (1 << width) - 1; + u32 temp = dw_mipi_csi_read(dev, address); + + temp &= ~(mask << shift); + temp |= (data & mask) << shift; + dw_mipi_csi_write(dev, address, temp); +} + +void dw_mipi_csi_reset(struct dw_csi *csi_dev) +{ + dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 0); + usleep_range(100, 200); + dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 1); +} + +int dw_mipi_csi_mask_irq_power_off(struct dw_csi *csi_dev) +{ + if (csi_dev->hw_version_major == 1) { + /* set only one lane (lane 0) as active (ON) */ + dw_mipi_csi_write(csi_dev, reg.N_LANES, 0); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY_FATAL, 0); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PKT_FATAL, 0); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY, 0); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_LINE, 0); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_IPI, 0); + + /* only for version 1.30 */ + if (csi_dev->hw_version_minor == 30) + dw_mipi_csi_write(csi_dev, + reg.MASK_INT_FRAME_FATAL, 0); + + dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 0); + + /* only for version 1.40 */ + if (csi_dev->hw_version_minor == 40) { + dw_mipi_csi_write(csi_dev, + reg.MSK_BNDRY_FRAME_FATAL, 0); + dw_mipi_csi_write(csi_dev, + reg.MSK_SEQ_FRAME_FATAL, 0); + dw_mipi_csi_write(csi_dev, + reg.MSK_CRC_FRAME_FATAL, 0); + dw_mipi_csi_write(csi_dev, reg.MSK_PLD_CRC_FATAL, 0); + dw_mipi_csi_write(csi_dev, reg.MSK_DATA_ID, 0); + dw_mipi_csi_write(csi_dev, reg.MSK_ECC_CORRECT, 0); + } + } + + return 0; +} + +int dw_mipi_csi_hw_stdby(struct dw_csi *csi_dev) +{ + if (csi_dev->hw_version_major == 1) { + /* set only one lane (lane 0) as active (ON) */ + dw_mipi_csi_reset(csi_dev); + dw_mipi_csi_write(csi_dev, reg.N_LANES, 0); + phy_init(csi_dev->phy); + + /* only for version 1.30 */ + if (csi_dev->hw_version_minor == 30) + dw_mipi_csi_write(csi_dev, + reg.MASK_INT_FRAME_FATAL, + GENMASK(31, 0)); + + /* common */ + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY_FATAL, + GENMASK(8, 0)); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PKT_FATAL, + GENMASK(1, 0)); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY, GENMASK(23, 0)); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_LINE, GENMASK(23, 0)); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_IPI, GENMASK(5, 0)); + + /* only for version 1.40 */ + if (csi_dev->hw_version_minor == 40) { + dw_mipi_csi_write(csi_dev, + reg.MSK_BNDRY_FRAME_FATAL, + GENMASK(31, 0)); + dw_mipi_csi_write(csi_dev, + reg.MSK_SEQ_FRAME_FATAL, + GENMASK(31, 0)); + dw_mipi_csi_write(csi_dev, + reg.MSK_CRC_FRAME_FATAL, + GENMASK(31, 0)); + dw_mipi_csi_write(csi_dev, + reg.MSK_PLD_CRC_FATAL, + GENMASK(31, 0)); + dw_mipi_csi_write(csi_dev, + reg.MSK_DATA_ID, GENMASK(31, 0)); + dw_mipi_csi_write(csi_dev, + reg.MSK_ECC_CORRECT, GENMASK(31, 0)); + } + } + return 0; +} + +void dw_mipi_csi_set_ipi_fmt(struct dw_csi *csi_dev) +{ + struct device *dev = csi_dev->dev; + + if (csi_dev->ipi_dt) { + dw_mipi_csi_write(csi_dev, reg.IPI_DATA_TYPE, csi_dev->ipi_dt); + /*switch (csi_dev->ipi_dt) { + case CSI_2_YUV420_8: + //case CSI_2_YUV420_8_LEG: + case CSI_2_YUV420_8_SHIFT: + break; + case CSI_2_YUV420_10: + case CSI_2_YUV420_10_SHIFT: + break; + }*/ + } else { + switch (csi_dev->fmt->mbus_code) { + + case MEDIA_BUS_FMT_RGB666_1X18: + csi_dev->ipi_dt = CSI_2_RGB666; + break; + + case MEDIA_BUS_FMT_RGB565_2X8_BE: + case MEDIA_BUS_FMT_RGB565_2X8_LE: + csi_dev->ipi_dt = CSI_2_RGB565; + break; + + case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE: + case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: + csi_dev->ipi_dt = CSI_2_RGB555; + break; + + case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE: + case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE: + csi_dev->ipi_dt = CSI_2_RGB444; + break; + + break; + case MEDIA_BUS_FMT_RGB888_2X12_LE: + case MEDIA_BUS_FMT_RGB888_2X12_BE: + csi_dev->ipi_dt = CSI_2_RGB888; + break; + + case MEDIA_BUS_FMT_SBGGR10_1X10: + case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE: + csi_dev->ipi_dt = CSI_2_RAW10; + break; + + case MEDIA_BUS_FMT_SBGGR12_1X12: + csi_dev->ipi_dt = CSI_2_RAW12; + break; + + case MEDIA_BUS_FMT_SBGGR14_1X14: + csi_dev->ipi_dt = CSI_2_RAW14; + break; + + case MEDIA_BUS_FMT_SBGGR16_1X16: + csi_dev->ipi_dt = CSI_2_RAW16; + break; + + case MEDIA_BUS_FMT_SBGGR8_1X8: + csi_dev->ipi_dt = CSI_2_RAW8; + break; + + case MEDIA_BUS_FMT_YVYU8_1X16: + csi_dev->ipi_dt = CSI_2_YUV422_8; + break; + + case MEDIA_BUS_FMT_VYUY8_1X16: + csi_dev->ipi_dt = CSI_2_YUV422_8; + break; + + case MEDIA_BUS_FMT_UYVY10_1X20: + csi_dev->ipi_dt = CSI_2_YUV422_10; + break; + + case MEDIA_BUS_FMT_YUYV8_1X16: + csi_dev->ipi_dt = CSI_2_YUV420_8_LEG; + break; + + case MEDIA_BUS_FMT_UYVY8_1X16: + csi_dev->ipi_dt = CSI_2_YUV420_8; + break; + + case MEDIA_BUS_FMT_VUY8_1X24: + csi_dev->ipi_dt = CSI_2_YUV420_10; + break; + + case MEDIA_BUS_FMT_Y8_1X8: + csi_dev->ipi_dt = CSI_2_RAW8; + break; + + case MEDIA_BUS_FMT_Y10_1X10: + csi_dev->ipi_dt = CSI_2_RAW8; + break; + + case MEDIA_BUS_FMT_SBGGR6_1X8: + csi_dev->ipi_dt = CSI_2_RAW6; + break; + + case MEDIA_BUS_FMT_SBGGR7_1X8: + csi_dev->ipi_dt = CSI_2_RAW7; + break; + + default: + break; + } + dw_mipi_csi_write(csi_dev, reg.IPI_DATA_TYPE, csi_dev->ipi_dt); + } + dev_info(dev, "Selected IPI Data Type 0x%X\n", csi_dev->ipi_dt); +} + +void dw_mipi_csi_fill_timings(struct dw_csi *dev, uint32_t width, uint32_t height) +{ + dev->hw.virtual_ch = 0; + dev->hw.ipi_color_mode = COLOR48; + dev->hw.ipi_auto_flush = 1; + dev->hw.ipi_mode = CAMERA_TIMING; + dev->hw.ipi_cut_through = CTINACTIVE; + dev->hw.ipi_adv_features = LINE_EVENT_SELECTION(EVSELAUTO); + dev->hw.htotal = width + dev->hw.hsa + + dev->hw.hbp + dev->hw.hsd; + dev->hw.vactive = height; + dev->hw.output = 2; + + dev_dbg(dev->dev, "*********** timings *********\n"); + dev_dbg(dev->dev, "Horizontal Sync Active: %d\n", dev->hw.hsa); + dev_dbg(dev->dev, "Horizontal Back Porch: %d\n", dev->hw.hbp); + dev_dbg(dev->dev, "Horizontal Width: %d\n", width); + dev_dbg(dev->dev, "Horizontal Total: %d\n", dev->hw.htotal); + dev_dbg(dev->dev, "Vertical Sync Active: %d\n", dev->hw.vsa); + dev_dbg(dev->dev, "Vertical Back Porch: %d\n", dev->hw.vbp); + dev_dbg(dev->dev, "Vertical Front Porch: %d\n", dev->hw.vfp); + dev_dbg(dev->dev, "Vertical Active: %d\n", dev->hw.vactive); +} + +void dw_mipi_csi_start(struct dw_csi *csi_dev) +{ + struct device *dev = csi_dev->dev; + + dw_mipi_csi_write(csi_dev, reg.N_LANES, (csi_dev->hw.num_lanes - 1)); + dev_info(dev, "number of lanes: %d\n", csi_dev->hw.num_lanes); + + /* IPI Related Configuration */ + if (csi_dev->hw.output == IPI_OUT || csi_dev->hw.output == BOTH_OUT) { + if (csi_dev->hw_version_major >= 1) { + if (csi_dev->hw_version_minor >= 20) + dw_mipi_csi_write(csi_dev, + reg.IPI_ADV_FEATURES, + csi_dev->hw.ipi_adv_features); + if (csi_dev->hw_version_minor >= 30) + dw_mipi_csi_write(csi_dev, + reg.IPI_SOFTRSTN, 0x1); + } + /* address | data, | shift | width */ + dw_mipi_csi_write_part(csi_dev, reg.IPI_MODE, 1, 24, 1); + dw_mipi_csi_write_part(csi_dev, + reg.IPI_MODE, + csi_dev->hw.ipi_mode, + 0, 1); + if (csi_dev->hw.ipi_mode == CAMERA_TIMING) { + dw_mipi_csi_write(csi_dev, + reg.IPI_ADV_FEATURES, + LINE_EVENT_SELECTION(EVSELPROG) | + EN_VIDEO | + EN_LINE_START | + EN_NULL | + EN_BLANKING | + EN_EMBEDDED); + } + dw_mipi_csi_write_part(csi_dev, + reg.IPI_MODE, + csi_dev->hw.ipi_color_mode, + 8, 1); + dw_mipi_csi_write_part(csi_dev, + reg.IPI_MODE, + csi_dev->hw.ipi_cut_through, + 16, 1); + dw_mipi_csi_write_part(csi_dev, + reg.IPI_VCID, + csi_dev->hw.virtual_ch, + 0, 2); + dw_mipi_csi_write_part(csi_dev, + reg.IPI_MEM_FLUSH, + csi_dev->hw.ipi_auto_flush, + 8, 1); + + dev_vdbg(dev, "*********** config *********\n"); + dev_vdbg(dev, "IPI enable: %s\n", + csi_dev->hw.output ? "YES" : "NO"); + dev_vdbg(dev, "video mode transmission type: %s timming\n", + csi_dev->hw.ipi_mode ? "controller" : "camera"); + dev_vdbg(dev, "Color Mode: %s\n", + csi_dev->hw.ipi_color_mode ? "16 bits" : "48 bits"); + dev_vdbg(dev, "Cut Through Mode: %s\n", + csi_dev->hw.ipi_cut_through ? "enable" : "disable"); + dev_vdbg(dev, "Virtual Channel: %d\n", + csi_dev->hw.virtual_ch); + dev_vdbg(dev, "Auto-flush: %d\n", + csi_dev->hw.ipi_auto_flush); + dw_mipi_csi_write(csi_dev, reg.IPI_SOFTRSTN, 1); + + if (csi_dev->hw.ipi_mode == AUTO_TIMING) + phy_power_on(csi_dev->phy); + + dw_mipi_csi_write(csi_dev, + reg.IPI_HSA_TIME, csi_dev->hw.hsa); + dw_mipi_csi_write(csi_dev, + reg.IPI_HBP_TIME, csi_dev->hw.hbp); + dw_mipi_csi_write(csi_dev, + reg.IPI_HSD_TIME, csi_dev->hw.hsd); + dw_mipi_csi_write(csi_dev, + reg.IPI_HLINE_TIME, csi_dev->hw.htotal); + dw_mipi_csi_write(csi_dev, + reg.IPI_VSA_LINES, csi_dev->hw.vsa); + dw_mipi_csi_write(csi_dev, + reg.IPI_VBP_LINES, csi_dev->hw.vbp); + dw_mipi_csi_write(csi_dev, + reg.IPI_VFP_LINES, csi_dev->hw.vfp); + dw_mipi_csi_write(csi_dev, + reg.IPI_VACTIVE_LINES, csi_dev->hw.vactive); + } + phy_power_on(csi_dev->phy); +} + +int dw_mipi_csi_irq_handler(struct dw_csi *csi_dev) +{ + struct device *dev = csi_dev->dev; + u32 global_int_status, i_sts; + unsigned long flags; + + spin_lock_irqsave(&csi_dev->slock, flags); + global_int_status = dw_mipi_csi_read(csi_dev, reg.INTERRUPT); + + if (global_int_status & csi_int.PHY_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PHY_FATAL); + dev_err_ratelimited(dev, "int %08X: PHY FATAL: %08X\n", + reg.INT_PHY_FATAL, i_sts); + } + + if (global_int_status & csi_int.PKT_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PKT_FATAL); + dev_err_ratelimited(dev, "int %08X: PKT FATAL: %08X\n", + reg.INT_PKT_FATAL, i_sts); + } + + if (global_int_status & csi_int.FRAME_FATAL && + csi_dev->hw_version_major == 1 && + csi_dev->hw_version_minor == 30) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_FRAME_FATAL); + dev_err_ratelimited(dev, "int %08X: FRAME FATAL: %08X\n", + reg.INT_FRAME_FATAL, i_sts); + } + + if (global_int_status & csi_int.PHY) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PHY); + dev_err_ratelimited(dev, "int %08X: PHY: %08X\n", + reg.INT_PHY, i_sts); + } + + if (global_int_status & csi_int.PKT && + csi_dev->hw_version_major == 1 && + csi_dev->hw_version_minor <= 30) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PKT); + dev_err_ratelimited(dev, "int %08X: PKT: %08X\n", + reg.INT_PKT, i_sts); + } + + if (global_int_status & csi_int.LINE) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_LINE); + dev_err_ratelimited(dev, "int %08X: LINE: %08X\n", + reg.INT_LINE, i_sts); + } + + if (global_int_status & csi_int.IPI) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_IPI); + dev_err_ratelimited(dev, "int %08X: IPI: %08X\n", + reg.INT_IPI, i_sts); + } + + if (global_int_status & csi_int.BNDRY_FRAME_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_BNDRY_FRAME_FATAL); + dev_err_ratelimited(dev, + "int %08X: ST_BNDRY_FRAME_FATAL: %08X\n", + reg.ST_BNDRY_FRAME_FATAL, i_sts); + } + + if (global_int_status & csi_int.SEQ_FRAME_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_SEQ_FRAME_FATAL); + dev_err_ratelimited(dev, + "int %08X: ST_SEQ_FRAME_FATAL: %08X\n", + reg.ST_SEQ_FRAME_FATAL, i_sts); + } + + if (global_int_status & csi_int.CRC_FRAME_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_CRC_FRAME_FATAL); + dev_err_ratelimited(dev, + "int %08X: ST_CRC_FRAME_FATAL: %08X\n", + reg.ST_CRC_FRAME_FATAL, i_sts); + } + + if (global_int_status & csi_int.PLD_CRC_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_PLD_CRC_FATAL); + dev_err_ratelimited(dev, + "int %08X: ST_PLD_CRC_FATAL: %08X\n", + reg.ST_PLD_CRC_FATAL, i_sts); + } + + if (global_int_status & csi_int.DATA_ID) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_DATA_ID); + dev_err_ratelimited(dev, "int %08X: ST_DATA_ID: %08X\n", + reg.ST_DATA_ID, i_sts); + } + + if (global_int_status & csi_int.ECC_CORRECTED) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_ECC_CORRECT); + dev_err_ratelimited(dev, "int %08X: ST_ECC_CORRECT: %08X\n", + reg.ST_ECC_CORRECT, i_sts); + } + + spin_unlock_irqrestore(&csi_dev->slock, flags); + + return 1; +} + +void dw_mipi_csi_get_version(struct dw_csi *csi_dev) +{ + u32 hw_version; + + hw_version = dw_mipi_csi_read(csi_dev, reg.VERSION); + csi_dev->hw_version_major = (u8)((hw_version >> 24) - '0'); + csi_dev->hw_version_minor = (u8)((hw_version >> 16) - '0'); + csi_dev->hw_version_minor = csi_dev->hw_version_minor * 10; + csi_dev->hw_version_minor += (u8)((hw_version >> 8) - '0'); +} + +int dw_mipi_csi_specific_mappings(struct dw_csi *csi_dev) +{ + struct device *dev = csi_dev->dev; + + if (csi_dev->hw_version_major == 1) { + if (csi_dev->hw_version_minor == 30) { + /* + * Hardware registers that were + * exclusive to version < 1.40 + */ + reg.INT_FRAME_FATAL = 0x100; + reg.MASK_INT_FRAME_FATAL = 0x104; + reg.FORCE_INT_FRAME_FATAL = 0x108; + reg.INT_PKT = 0x120; + reg.MASK_INT_PKT = 0x124; + reg.FORCE_INT_PKT = 0x128; + + /* interrupt source present until this release */ + csi_int.PKT = BIT(17); + csi_int.LINE = BIT(18); + csi_int.IPI = BIT(19); + csi_int.FRAME_FATAL = BIT(2); + + } else if (csi_dev->hw_version_minor == 40) { + /* + * HW registers that were added + * to version 1.40 + */ + reg.ST_BNDRY_FRAME_FATAL = 0x280; + reg.MSK_BNDRY_FRAME_FATAL = 0x284; + reg.FORCE_BNDRY_FRAME_FATAL = 0x288; + reg.ST_SEQ_FRAME_FATAL = 0x290; + reg.MSK_SEQ_FRAME_FATAL = 0x294; + reg.FORCE_SEQ_FRAME_FATAL = 0x298; + reg.ST_CRC_FRAME_FATAL = 0x2a0; + reg.MSK_CRC_FRAME_FATAL = 0x2a4; + reg.FORCE_CRC_FRAME_FATAL = 0x2a8; + reg.ST_PLD_CRC_FATAL = 0x2b0; + reg.MSK_PLD_CRC_FATAL = 0x2b4; + reg.FORCE_PLD_CRC_FATAL = 0x2b8; + reg.ST_DATA_ID = 0x2c0; + reg.MSK_DATA_ID = 0x2c4; + reg.FORCE_DATA_ID = 0x2c8; + reg.ST_ECC_CORRECT = 0x2d0; + reg.MSK_ECC_CORRECT = 0x2d4; + reg.FORCE_ECC_CORRECT = 0x2d8; + reg.DATA_IDS_VC_1 = 0x0; + reg.DATA_IDS_VC_2 = 0x0; + reg.VC_EXTENSION = 0x0; + + /* interrupts map were changed */ + csi_int.LINE = BIT(17); + csi_int.IPI = BIT(18); + csi_int.BNDRY_FRAME_FATAL = BIT(2); + csi_int.SEQ_FRAME_FATAL = BIT(3); + csi_int.CRC_FRAME_FATAL = BIT(4); + csi_int.PLD_CRC_FATAL = BIT(5); + csi_int.DATA_ID = BIT(6); + csi_int.ECC_CORRECTED = BIT(7); + + } else { + dev_info(dev, "Version minor not supported."); + } + } else { + dev_info(dev, "Version major not supported."); + } + return 0; +} + +void dw_mipi_csi_dump(struct dw_csi *csi_dev) +{ + dw_print(reg.VERSION); + dw_print(reg.N_LANES); + dw_print(reg.CTRL_RESETN); + dw_print(reg.INTERRUPT); + dw_print(reg.DATA_IDS_1); + dw_print(reg.DATA_IDS_2); + dw_print(reg.IPI_MODE); + dw_print(reg.IPI_VCID); + dw_print(reg.IPI_DATA_TYPE); + dw_print(reg.IPI_MEM_FLUSH); + dw_print(reg.IPI_HSA_TIME); + dw_print(reg.IPI_HBP_TIME); + dw_print(reg.IPI_HSD_TIME); + dw_print(reg.IPI_HLINE_TIME); + dw_print(reg.IPI_SOFTRSTN); + dw_print(reg.IPI_ADV_FEATURES); + dw_print(reg.IPI_VSA_LINES); + dw_print(reg.IPI_VBP_LINES); + dw_print(reg.IPI_VFP_LINES); + dw_print(reg.IPI_VACTIVE_LINES); + dw_print(reg.IPI_DATA_TYPE); + dw_print(reg.VERSION); + dw_print(reg.IPI_ADV_FEATURES); +} diff --git a/vvcam/native/csi/dw-mipi-csi.h b/vvcam/native/csi/dw-mipi-csi.h new file mode 100755 index 0000000..5c5579f --- /dev/null +++ b/vvcam/native/csi/dw-mipi-csi.h @@ -0,0 +1,285 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 Host controller driver + * + * Author: Luis Oliveira + */ + +#ifndef _DW_MIPI_CSI_H__ +#define _DW_MIPI_CSI_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Advanced features */ +#define IPI_DT_OVERWRITE BIT(0) +#define DATA_TYPE_OVERWRITE(dt) (((dt) & GENMASK(5, 0)) << 8) +#define LINE_EVENT_SELECTION(n) ((n) << 16) + +enum line_event { + EVSELAUTO = 0, + EVSELPROG = 1, +}; + +#define EN_VIDEO BIT(17) +#define EN_LINE_START BIT(18) +#define EN_NULL BIT(19) +#define EN_BLANKING BIT(20) +#define EN_EMBEDDED BIT(21) +#define IPI_SYNC_EVENT_MODE(n) ((n) << 24) + +enum sync_event { + SYNCEVFSN = 0, + SYNCEVFS = 1, +}; + +/* DW MIPI CSI-2 register addresses*/ + +struct R_CSI2 { + u16 VERSION; + u16 N_LANES; + u16 CTRL_RESETN; + u16 INTERRUPT; + u16 DATA_IDS_1; + u16 DATA_IDS_2; + u16 DATA_IDS_VC_1; + u16 DATA_IDS_VC_2; + u16 IPI_MODE; + u16 IPI_VCID; + u16 IPI_DATA_TYPE; + u16 IPI_MEM_FLUSH; + u16 IPI_HSA_TIME; + u16 IPI_HBP_TIME; + u16 IPI_HSD_TIME; + u16 IPI_HLINE_TIME; + u16 IPI_SOFTRSTN; + u16 IPI_ADV_FEATURES; + u16 IPI_VSA_LINES; + u16 IPI_VBP_LINES; + u16 IPI_VFP_LINES; + u16 IPI_VACTIVE_LINES; + u16 VC_EXTENSION; + u16 INT_PHY_FATAL; + u16 MASK_INT_PHY_FATAL; + u16 FORCE_INT_PHY_FATAL; + u16 INT_PKT_FATAL; + u16 MASK_INT_PKT_FATAL; + u16 FORCE_INT_PKT_FATAL; + u16 INT_FRAME_FATAL; + u16 MASK_INT_FRAME_FATAL; + u16 FORCE_INT_FRAME_FATAL; + u16 INT_PHY; + u16 MASK_INT_PHY; + u16 FORCE_INT_PHY; + u16 INT_PKT; + u16 MASK_INT_PKT; + u16 FORCE_INT_PKT; + u16 INT_LINE; + u16 MASK_INT_LINE; + u16 FORCE_INT_LINE; + u16 INT_IPI; + u16 MASK_INT_IPI; + u16 FORCE_INT_IPI; + u16 ST_BNDRY_FRAME_FATAL; + u16 MSK_BNDRY_FRAME_FATAL; + u16 FORCE_BNDRY_FRAME_FATAL; + u16 ST_SEQ_FRAME_FATAL; + u16 MSK_SEQ_FRAME_FATAL; + u16 FORCE_SEQ_FRAME_FATAL; + u16 ST_CRC_FRAME_FATAL; + u16 MSK_CRC_FRAME_FATAL; + u16 FORCE_CRC_FRAME_FATAL; + u16 ST_PLD_CRC_FATAL; + u16 MSK_PLD_CRC_FATAL; + u16 FORCE_PLD_CRC_FATAL; + u16 ST_DATA_ID; + u16 MSK_DATA_ID; + u16 FORCE_DATA_ID; + u16 ST_ECC_CORRECT; + u16 MSK_ECC_CORRECT; + u16 FORCE_ECC_CORRECT; +}; + +/* Interrupt Masks */ +struct interrupt_type { + u32 PHY_FATAL; + u32 PKT_FATAL; + u32 FRAME_FATAL; + u32 PHY; + u32 PKT; + u32 LINE; + u32 IPI; + u32 BNDRY_FRAME_FATAL; + u32 SEQ_FRAME_FATAL; + u32 CRC_FRAME_FATAL; + u32 PLD_CRC_FATAL; + u32 DATA_ID; + u32 ECC_CORRECTED; +}; + +/* IPI Data Types */ +enum data_type { + CSI_2_YUV420_8 = 0x18, + CSI_2_YUV420_10 = 0x19, + CSI_2_YUV420_8_LEG = 0x1A, + CSI_2_YUV420_8_SHIFT = 0x1C, + CSI_2_YUV420_10_SHIFT = 0x1D, + CSI_2_YUV422_8 = 0x1E, + CSI_2_YUV422_10 = 0x1F, + CSI_2_RGB444 = 0x20, + CSI_2_RGB555 = 0x21, + CSI_2_RGB565 = 0x22, + CSI_2_RGB666 = 0x23, + CSI_2_RGB888 = 0x24, + CSI_2_RAW6 = 0x28, + CSI_2_RAW7 = 0x29, + CSI_2_RAW8 = 0x2A, + CSI_2_RAW10 = 0x2B, + CSI_2_RAW12 = 0x2C, + CSI_2_RAW14 = 0x2D, + CSI_2_RAW16 = 0x2E, + CSI_2_RAW20 = 0x2F, + USER_DEFINED_1 = 0x30, + USER_DEFINED_2 = 0x31, + USER_DEFINED_3 = 0x32, + USER_DEFINED_4 = 0x33, + USER_DEFINED_5 = 0x34, + USER_DEFINED_6 = 0x35, + USER_DEFINED_7 = 0x36, + USER_DEFINED_8 = 0x37, +}; + +/* DWC MIPI CSI-2 output types */ +enum output { + IPI_OUT = 0, + IDI_OUT = 1, + BOTH_OUT = 2 +}; + +/* IPI color components */ +enum color_mode { + COLOR48 = 0, + COLOR16 = 1 +}; + +/* IPI cut through */ +enum cut_through { + CTINACTIVE = 0, + CTACTIVE = 1 +}; + +/* IPI output types */ +enum ipi_output { + CAMERA_TIMING = 0, + AUTO_TIMING = 1 +}; + +/* Format template */ +struct mipi_fmt { + u32 mbus_code; + u8 depth; + u32 width; + u32 height; +}; + +struct mipi_dt { + u32 hex; + char *name; +}; + +/* CSI specific configuration */ +struct csi_data { + u32 num_lanes; + u32 dphy_freq; //MBPS + u32 pclk; + u32 fps; + u32 bpp; + u32 output; + u32 ipi_mode; + u32 ipi_adv_features; + u32 ipi_cut_through; + u32 ipi_color_mode; + u32 ipi_auto_flush; + u32 virtual_ch; + u32 hsa; + u32 hbp; + u32 hsd; + u32 htotal; + u32 vsa; + u32 vbp; + u32 vfp; + u32 vactive; +}; + +/* Structure to embed device driver information */ +struct dw_csi { + //struct v4l2_subdev sd; + //struct video_device vdev; + //struct v4l2_device v4l2_dev; + struct device *dev; + //struct media_pad pads[CSI_PADS_NUM]; + struct mipi_fmt *fmt; + //struct v4l2_mbus_framefmt format; + void __iomem *base_address; + void __iomem *demo; + void __iomem *csc; + int ctrl_irq_number; + int demosaic_irq; + struct csi_data hw; + struct reset_control *rst; + struct phy *phy; + struct dw_csih_pdata *config; + struct mutex lock; /* protect resources sharing */ + spinlock_t slock; /* interrupt handling lock */ + u8 ipi_dt; + u8 index; + u8 hw_version_major; + u16 hw_version_minor; +}; + +void dw_mipi_csi_reset(struct dw_csi *csi_dev); +int dw_mipi_csi_mask_irq_power_off(struct dw_csi *csi_dev); +int dw_mipi_csi_hw_stdby(struct dw_csi *csi_dev); +void dw_mipi_csi_set_ipi_fmt(struct dw_csi *csi_dev); +void dw_mipi_csi_start(struct dw_csi *csi_dev); +int dw_mipi_csi_irq_handler(struct dw_csi *csi_dev); +void dw_mipi_csi_get_version(struct dw_csi *csi_dev); +int dw_mipi_csi_specific_mappings(struct dw_csi *csi_dev); +void dw_mipi_csi_fill_timings(struct dw_csi *dev, uint32_t width, uint32_t height); +void dw_mipi_csi_dump(struct dw_csi *csi_dev); + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +int dw_csi_create_capabilities_sysfs(struct platform_device *pdev); +int dw_csi_remove_capabilities_sysfs(struct platform_device *pdev); +#endif + +int dw_mipi_csi_s_power(struct dw_csi *dev, int on); +int dw_mipi_csi_log_status(struct dw_csi *dev); + +static inline void dw_mipi_csi_write(struct dw_csi *dev, + u32 address, u32 data) +{ + writel(data, dev->base_address + address); +} + +static inline u32 dw_mipi_csi_read(struct dw_csi *dev, u32 address) +{ + return readl(dev->base_address + address); +} + +#endif /*_DW_MIPI_CSI_H__ */ diff --git a/vvcam/native/csi/nwl/nwl_regs.h b/vvcam/native/csi/nwl/nwl_regs.h new file mode 100755 index 0000000..371ce2f --- /dev/null +++ b/vvcam/native/csi/nwl/nwl_regs.h @@ -0,0 +1,115 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _NWL_REGS_H_ +#define _NWL_REGS_H_ + +/* + * MRV_MIPICSI1_NUM_LANES + * Config num lanes register [3:0] rw + * 0000b - controller off + * 0001b - 1 Lane + * 0010b - 2 Lanes + * 0011b - 3 Lanes + * 0100b - 4 Lanes + */ +#define MRV_MIPICSI_NUM_LANES 0x0 + +/* + * MRV_MIPICSI1_LANES_CLK + * Configure lanes clock [0] + * 0b - disable + * 1b - enable + */ +#define MRV_MIPICSI_LANES_CLK 0x4 + +/* + * MRV_MIPICSI1_LANES_DATA + * enable/disable lanes data [7:0] + * setting bits to a '1' value enable data lane + */ +#define MRV_MIPICSI_LANES_DATA 0x8 + +/* + * MRV_MIPICSI1_IGNORE_VC + * enable/disable lanes clock [0] + * setting bits to a '1' value enable data value + */ +#define MRV_MIPICSI_IGNORE_VC 0x80 + +/* + * MRV_MIPICSI1_OUT_SHIFT + * Configure csi_vid_out register + */ + +#define MRV_MIPICSI_FIFO_SENSD_LEVEL 0x88 + +#define MRV_MIPICSI_VID_VSYNC 0x8c + +#define MRV_MIPICSI_VID_HSYNC_FP 0x90 + +#define MRV_MIPICSI_VID_HSYNC 0x94 + +#define MRV_MIPICSI_VID_HSYNC_BP 0x98 + + + + + +#ifdef ISP8000L_V1801 +#define MRV_MIPICSI0_CTRL 0x8240 //0x308240 +#else +#define MRV_MIPICSI0_CTRL 0x108240 //0x308240 +#endif +#define MRV_MIPICSI1_CTRL 0x8244 //0x308244 + +#endif /* _NWL_REGS_H_ */ diff --git a/vvcam/native/csi/nwl/platform_nwl_csi_driver.c b/vvcam/native/csi/nwl/platform_nwl_csi_driver.c new file mode 100755 index 0000000..5dab521 --- /dev/null +++ b/vvcam/native/csi/nwl/platform_nwl_csi_driver.c @@ -0,0 +1,216 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#ifdef ISP8000L_V2008 +#include //Fix thead compile error. +#endif + + +#include "nwl_regs.h" +#include "csi_ioctl.h" + +int vvnative_csi_module_init(void * dev); +int vvnative_csi_module_exit(void * dev); + +int vvnative_csi_set_stream_control(void * dev); +int vvnative_csi_set_cfg(void * dev); +int vvnative_csi_set_bit_shift(void *dev); +static int nwl_register_write(void * dev,unsigned int addr, unsigned int data) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + writel(data, base_addr + addr); + + return 0; +} + +#if 0 +static int nwl_register_read(void * dev,unsigned int addr, unsigned int *data) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + *data = readl(base_addr + addr); + + return 0; +} +#endif + +int vvnative_csi_set_stream_control(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + u32 clock_status; + u32 data_status; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + if (nwl_csi_dev->streaming_enable) + { + clock_status = 0x01; + data_status = 0xFF; + } + else + { + clock_status = 0x00; + data_status = 0x00; + } + + nwl_register_write(dev,MRV_MIPICSI_LANES_CLK, clock_status); + nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, data_status); + return 0; +} + +int vvnative_csi_set_cfg(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + nwl_register_write(dev,MRV_MIPICSI_NUM_LANES, nwl_csi_dev->csi_lane_cfg.mipi_lane_num); + + switch (nwl_csi_dev->csi_lane_cfg.mipi_lane_num) + { + case 1: + nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, 0x01); + break; + case 2: + nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, 0x03); + break; + case 4: + nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, 0x0F); + break; + default: + break; + } + + return 0; +} + +int vvnative_csi_set_bit_shift(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + if (nwl_csi_dev->device_idx == 0) + { +#ifndef INPUT_SIGNAL_12_BIT + nwl_register_write(dev,MRV_MIPICSI0_CTRL, 16 - nwl_csi_dev->bit_width); //16bit high-aligned +#else + nwl_register_write(dev,MRV_MIPICSI0_CTRL, 0x0); //input signal 12 bit does not need to shift +#endif + }else + { +#ifndef INPUT_SIGNAL_12_BIT + nwl_register_write(dev,MRV_MIPICSI1_CTRL, 16 - nwl_csi_dev->bit_width); //16bit high-aligned +#else + nwl_register_write(dev,MRV_MIPICSI0_CTRL, 0x0); //input signal 12 bit does not need to shift +#endif + } + + return 0; +} + +int vvnative_csi_module_init(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + nwl_register_write(dev,MRV_MIPICSI_NUM_LANES, 0x04); + nwl_register_write(dev,MRV_MIPICSI_LANES_CLK, 0x01); + nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, 0x0F); + nwl_register_write(dev,MRV_MIPICSI_IGNORE_VC, 0x01); + + nwl_register_write(dev,MRV_MIPICSI_FIFO_SENSD_LEVEL, 0x41); + nwl_register_write(dev,MRV_MIPICSI_VID_VSYNC, 0x20); + nwl_register_write(dev,MRV_MIPICSI_VID_HSYNC_FP, 0x20); + nwl_register_write(dev,MRV_MIPICSI_VID_HSYNC, 0x01); + nwl_register_write(dev,MRV_MIPICSI_VID_HSYNC_BP, 0x20); + + if (nwl_csi_dev->device_idx == 0) + { + nwl_register_write(dev,MRV_MIPICSI0_CTRL, 0); + }else + { + nwl_register_write(dev,MRV_MIPICSI1_CTRL, 0); + } + + return 0; +} + +int vvnative_csi_module_exit(void * dev) +{ + + return 0; +} diff --git a/vvcam/native/csi/vvcam_csi_driver.c b/vvcam/native/csi/vvcam_csi_driver.c new file mode 100755 index 0000000..f7a597e --- /dev/null +++ b/vvcam/native/csi/vvcam_csi_driver.c @@ -0,0 +1,367 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "csi_ioctl.h" +#include "csi_common.h" + +#define VIVCAM_CSI_NAME "vivcsi" +#define VIVCAM_CSI_MAXCNT 2 + + +struct vvcam_csi_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + void *private; +}; + +static unsigned int vvcam_csi_major = 0; +static unsigned int vvcam_csi_minor = 0; +static struct class *vvcam_csi_class; +static unsigned int devise_register_index = 0; + + +static int vvcam_csi_open(struct inode * inode, struct file * file) +{ + struct vvcam_csi_driver_dev *pdriver_dev; + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_csi_driver_dev, cdev); + file->private_data = pdriver_dev; + + return 0; +}; + +static long vvcam_csi_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct vvcam_csi_driver_dev *pdriver_dev; + struct vvcam_csi_dev * pcsi_dev; + long ret; + + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + pcsi_dev = pdriver_dev->private; + + pr_info("%s:pdriver_dev =0x%px\n", __func__,pdriver_dev); + pr_info("%s:csi[%d] pcsi_dev =0x%px\n", __func__,pcsi_dev->device_idx,pcsi_dev); + + mutex_lock(&pdriver_dev->vvmutex); + ret = csi_priv_ioctl(pcsi_dev, cmd, (void __user *)arg); + mutex_unlock(&pdriver_dev->vvmutex); + + return ret; +}; + +static int vvcam_csi_release(struct inode * inode, struct file * file) +{ + return 0; +}; + +static struct file_operations vvcam_csi_fops = { + .owner = THIS_MODULE, + .open = vvcam_csi_open, + .release = vvcam_csi_release, + .unlocked_ioctl = vvcam_csi_ioctl, +}; + +static int vvcam_csi_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vvcam_csi_driver_dev *pdriver_dev; + struct vvcam_csi_dev * pcsi_dev; + + pr_info("enter %s\n", __func__); + + if (pdev->id >= VIVCAM_CSI_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_csi_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_csi_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_csi_driver_dev )); + pr_info("%s:csi[%d]: pdriver_dev =0x%px\n", __func__,pdev->id,pdriver_dev); + + pcsi_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_csi_dev), GFP_KERNEL); + if (pcsi_dev == NULL) + { + pr_err("%s:alloc struct vvcam_csi_dev error\n", __func__); + return -ENOMEM; + } + memset(pcsi_dev,0,sizeof(struct vvcam_csi_dev )); + pr_info("%s:csi[%d]: pcsi_dev =0x%px\n", __func__,pdev->id,pcsi_dev); + + pcsi_dev->device_idx = pdev->id; + //mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + //pcsi_dev->base = devm_ioremap_resource(&pdev->dev, mem); + if (pcsi_dev->device_idx == 0) + { + pcsi_dev->base = ioremap(VVCSI0_BASE, VVCSI_SIZE); + + }else + { + pcsi_dev->base = ioremap(VVCSI1_BASE, VVCSI_SIZE); + } + if (IS_ERR(pcsi_dev->base)) + return PTR_ERR(pcsi_dev->base); + + + pdriver_dev->private = pcsi_dev; + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + + ret = vvnative_csi_module_init(pcsi_dev); + if (ret != 0) + { + pr_err("%s:vvnative_csi_module_init error\n", __func__); + return -ENOMEM; + } + + if (devise_register_index == 0) + { + if (vvcam_csi_major == 0) + { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_CSI_MAXCNT, VIVCAM_CSI_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_csi_major = MAJOR(pdriver_dev->devt); + vvcam_csi_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_csi_major, vvcam_csi_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_CSI_MAXCNT, VIVCAM_CSI_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + vvcam_csi_class = class_create(THIS_MODULE, VIVCAM_CSI_NAME); + if (IS_ERR(vvcam_csi_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_csi_major, vvcam_csi_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_csi_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_csi_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VIVCAM_CSI_NAME, pdev->id); + + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int vvcam_csi_remove(struct platform_device *pdev) +{ + struct vvcam_csi_driver_dev *pdriver_dev; + struct vvcam_csi_dev * pcsi_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + pcsi_dev = pdriver_dev->private; + iounmap(pcsi_dev->base); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_CSI_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + + return 0; +} + +static struct platform_driver vvcam_csi_driver = { + .probe = vvcam_csi_probe, + .remove = vvcam_csi_remove, + .driver = { + .name = VIVCAM_CSI_NAME, + .owner = THIS_MODULE, + } +}; + +static void vvcam_csi_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +#ifdef WITH_VVCAM +static struct resource vvcam_csi0_resource[] = { + [0] = { + .start = VVCSI0_BASE, + .end = VVCSI0_BASE + VVCSI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; +static struct platform_device vvcam_csi_pdev = { + .name = VIVCAM_CSI_NAME, + .id = 0, + .resource = vvcam_csi0_resource, + .num_resources = 0, + .dev.release = vvcam_csi_pdev_release, +}; +#endif + +#ifdef WITH_VVCAM_DUAL +static struct resource vvcam_csi1_resource[] = { + [0] = { + .start = VVCSI1_BASE, + .end = VVCSI1_BASE + VVCSI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device vvcam_csi_dual_pdev = { + .name = VIVCAM_CSI_NAME, + .id = 1, + .resource = vvcam_csi1_resource, + .num_resources = 0, + .dev.release = vvcam_csi_pdev_release, +}; +#endif + +static int __init vvcam_csi_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); +#ifdef WITH_VVCAM + ret = platform_device_register(&vvcam_csi_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } +#endif + +#ifdef WITH_VVCAM_DUAL + ret = platform_device_register(&vvcam_csi_dual_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } +#endif + + ret = platform_driver_register(&vvcam_csi_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit vvcam_csi_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_csi_driver); +#ifdef WITH_VVCAM + platform_device_unregister(&vvcam_csi_pdev); +#endif + +#ifdef WITH_VVCAM_DUAL + platform_device_unregister(&vvcam_csi_dual_pdev); +#endif +} + +module_init(vvcam_csi_init_module); +module_exit(vvcam_csi_exit_module); + +MODULE_DESCRIPTION("CSI"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/dec400/Makefile b/vvcam/native/dec400/Makefile new file mode 100755 index 0000000..d17df4c --- /dev/null +++ b/vvcam/native/dec400/Makefile @@ -0,0 +1,19 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_dec400 + +obj-m +=$(TARGET).o + +$(TARGET)-objs += dec400.o +$(TARGET)-objs += dec400_ioctl.o +EXTRA_CFLAGS += -I$(PWD)/../../common + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean diff --git a/vvcam/native/dec400/dec400.c b/vvcam/native/dec400/dec400.c new file mode 100755 index 0000000..17cb4ed --- /dev/null +++ b/vvcam/native/dec400/dec400.c @@ -0,0 +1,212 @@ +/* + * Verisilicon DEC400 Driver for FalconLite. + * + * Author: Wei Weiyu + * + * Copyright (C) 2020 VeriSilicon Microelectronics (Shanghai) Co., Ltd. + * + */ + +#include "dec400.h" +#include "dec400_ioctl.h" + +static unsigned int dec400_major = 0; +static unsigned int dec400_minor = 0; +struct class *dec400_class; +static unsigned int device_register_index = 0; + +extern unsigned int dec400_priv_ioctl(struct dec400_dev *dev, unsigned int cmd, void *args); + +static int dec400_open(struct inode * inode, struct file * file) +{ + struct dec400_dev *pdriver_dev; + + pr_info("entry %s\n", __func__); + pdriver_dev = container_of(inode->i_cdev, struct dec400_dev, cdev); + file->private_data = pdriver_dev; + + pr_info("exit %s\n", __func__); + return 0; +}; + +static long dec400_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct dec400_dev *pdriver_dev; + + /*pr_info("enter %s\n", __func__);*/ + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + mutex_lock(&pdriver_dev->mutex); + ret = dec400_priv_ioctl(pdriver_dev, cmd ,(void *)arg); + mutex_unlock(&pdriver_dev->mutex); + + /*pr_info("exit %s\n", __func__);*/ + + return ret; +}; + +static int dec400_release(struct inode * inode, struct file * file) +{ + struct dec400_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + + pdriver_dev = container_of(inode->i_cdev, struct dec400_dev, cdev); + file->private_data = pdriver_dev; + + pr_info("exit %s\n", __func__); + + return 0; +}; + +struct file_operations dec400_fops = { + .owner = THIS_MODULE, + .open = dec400_open, + .release = dec400_release, + .unlocked_ioctl = dec400_ioctl, + .mmap = NULL, + .poll = NULL, +}; + +static int dec400_probe(struct platform_device *pdev) +{ + int ret = 0; + struct dec400_dev *pdriver_dev; + struct resource *mem; + + pr_info("enter %s\n", __func__); + pdev->id = device_register_index; + if (pdev->id >= DEC400_MAXCNT) { + pr_err("%s:pdev id is %d error\n", __func__, pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev, sizeof(struct dec400_dev), GFP_KERNEL); + if (pdriver_dev == NULL) { + pr_err("%s:alloc struct dec400_dev error\n", __func__); + return -ENOMEM; + } + pr_info("%s:isp[%d]: pdriver_dev =0x%px\n", __func__, pdev->id, pdriver_dev); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pdriver_dev->reg_base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(pdriver_dev->reg_base)) + return PTR_ERR(pdriver_dev->reg_base); + pr_info("%s:isp[%d]: pdriver_dev->base=0x%px\n", __func__, + pdev->id, pdriver_dev->reg_base); + + pdriver_dev->id = pdev->id; + mutex_init(&pdriver_dev->mutex); + platform_set_drvdata(pdev, pdriver_dev); + + if (device_register_index == 0) { + int ret; + + if (dec400_major == 0) { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, DEC400_MAXCNT, DEC400_NAME); + if (ret != 0) { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + dec400_major = MAJOR(pdriver_dev->devt); + dec400_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(dec400_major, dec400_minor); + ret = register_chrdev_region(pdriver_dev->devt, DEC400_MAXCNT, DEC400_NAME); + if (ret) { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + dec400_class = class_create(THIS_MODULE, DEC400_NAME); + if (IS_ERR(dec400_class)) { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(dec400_major, dec400_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &dec400_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = dec400_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", DEC400_NAME, pdev->id); + + device_register_index++; + pr_info("exit %s:[%d]\n", __func__, pdev->id); + + return ret; +} + + +static int dec400_remove(struct platform_device *pdev) +{ + struct dec400_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + device_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, DEC400_MAXCNT); + if (device_register_index == 0) { + class_destroy(pdriver_dev->class); + } + return 0; +} + + +static const struct of_device_id dec400_of_match_table[] = { + { .compatible = "thead,dec400", }, + { }, +}; + +static struct platform_driver dec400_driver = { + .probe = dec400_probe, + .remove = dec400_remove, + .driver = { + .owner = THIS_MODULE, + .name = DEC_DEV_NAME, + .of_match_table = dec400_of_match_table, + }, +}; + +static int __init dec400_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&dec400_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit dec400_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&dec400_driver); +} + +module_init(dec400_init_module); +module_exit(dec400_exit_module); + +MODULE_DESCRIPTION("DEC400"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/dec400/dec400.h b/vvcam/native/dec400/dec400.h new file mode 100755 index 0000000..63ec069 --- /dev/null +++ b/vvcam/native/dec400/dec400.h @@ -0,0 +1,101 @@ +/* + * Verisilicon DEC400 Driver for FalconLite. + * + * Author: Wei Weiyu + * + * Copyright (C) 2020 VeriSilicon Microelectronics (Shanghai) Co., Ltd. + * + */ + +#ifndef __DEC_H__ +#define __DEC_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEC_DEV_NAME "thead,dec400" +#define DEC400_NAME "dec" +#define DEC400_MAXCNT 3 + +#define DEC_CHIP_REV 0x00 +#define DEC_CHIP_DATA 0x04 +#define DEC_CONTROL 0x0800 +#define DEC_CONTROL_EX 0x0804 +#define DEC_CONTROL_EX2 0x0808 +#define DEC_INTR_EN 0x080c +#define DEC_INTR_EN_EX 0x0810 +#define DEC_INTR_EN_EX2 0x0814 +#define DEC_WRITE_CFG_CH(n) (0x0980 + (n) * 4) +#define DEC_WRITE_EX_CFG_CH(n) (0x0a00 + (n) * 4) +#define DEC_WRITE_BUF_BASE_CH(n) (0x0d80 + (n) * 4) +#define DEC_WRITE_BUF_END_CH(n) (0x0e80 + (n) * 4) +#define DEC_WRITE_CACHE_BASE_CH(n) (0x1180 + (n) * 4) +#define DEC_READ_CFG_CH(n) (0x0880 + (n) * 4) +#define DEC_READ_EX_CFG_CH(n) (0x0900 + (n) * 4) +#define DEC_READ_BUF_BASE_CH(n) (0x0A80 + (n) * 4) +#define DEC_READ_BUF_END_CH(n) (0x0B80 + (n) * 4) +#define DEC_FLUSH_CACHE_CH(n) (0x0F80 + (n) * 4) +#define DEC_READ_CACHE_BASE_CH(n) (0x1080 + (n) * 4) + +//gcregAHBDECControl +#define DEC_CONTROL_DISABLE_COMPRESSION_SHIFT 1 +#define DEC_CONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT 2 +#define DEC_CONTROL_DISABLE_DISABLE_DEBUG_REG_SHIFT 3 +#define DEC_CONTROL_DISABLE_HW_FLUSH_SHIFT 16 + +//gcregAHBDECControlEx2 +#define DEC_CONTROLEX2_TILE_STATUS_READ_ID 0 +#define DEC_CONTROLEX2_TILE_STATUS_WRITE_ID 7 +#define DEC_CONTROLEX2_WR_OT_CNT 14 + +#define DEC_READ_CONFIG_DECOMPRESS_ENABLE_SHIFT 0 +#define DEC_READ_CONFIG_DECOMPRESS_SIZE_SHIFT 1 +#define DEC_READ_CONFIG_DECOMPRESS_FORMAT_SHIFT 3 +#define DEC_READ_CONFIG_DECOMPRESS_ALIGN_SHIFT 16 +#define DEC_READ_CONFIG_DECOMPRESS_TILE_SHIFT 25 + +#define DEC_WRITE_CONFIG_COMPRESS_ENABLE_SHIFT 0 +#define DEC_WRITE_CONFIG_COMPRESS_SIZE_SHIFT 1 +#define DEC_WRITE_CONFIG_COMPRESS_FORMAT_SHIFT 3 +#define DEC_WRITE_CONFIG_COMPRESS_ALIGN_SHIFT 16 +#define DEC_WRITE_CONFIG_COMPRESS_TILE_SHIFT 25 + + +struct dec400_dev { + int id; + //int irq; + dev_t devt; + struct class *class; + struct cdev cdev; + struct mutex mutex; + + //enum dec_enable en; + + //enum vs_format fmt; + //enum vs_vdieo_resolution res; + + //struct device *dev; + void __iomem *reg_base; + + //struct v4l2_subdev sd; + //struct vs_video_device *vdev; + + //struct workqueue_struct *work_queue; + //struct delayed_work q_buf_wk; +}; + +#endif diff --git a/vvcam/native/dec400/dec400_ioctl.c b/vvcam/native/dec400/dec400_ioctl.c new file mode 100755 index 0000000..48c0c70 --- /dev/null +++ b/vvcam/native/dec400/dec400_ioctl.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include "dec400.h" +#include "dec400_ioctl.h" + +//#define DEBUG + +static void dec400_write(struct dec400_dev *dec, unsigned int addr, unsigned int val) +{ + writel(val, dec->reg_base + addr); +} + +static int dec400_mmu_config(struct dec400_dev *dec, void *args) +{ + unsigned int val = 0; + struct dec400_mmu_para para = {0}; + + copy_from_user(¶, args, sizeof(para)); + + pr_err("%s, entry\n", __func__); + val = 0; + val |= 0x100008c; //need confirm with VSI, no any description + dec400_write(dec, DEC_CONTROL, val); //val 0x100008c + + dec400_write(dec, 0x0388, 0x00000001); //0xE2 gcregMMUAHBControlRegAddrs + + // table array base address + dec400_write(dec, 0x038C, para.page_bable_addr); // 0xE3 gcregMMUAHBTableArrayBaseAddressLowRegAddrs + + //WriteRegister(reg_base, 0x00184, 0x00000001);//gcregMMUConfigurationRegAddrs, flush + dec400_write(dec, 0x01AC, 0x00000000);//dcreMMUConfigRegAddrs + + return 0; +} + +static int dec400_compress_init(struct dec400_dev *dec, void *args) +{ + unsigned int val = 0; + struct dec400_compress_init compress = {0}; + + copy_from_user(&compress, args, sizeof(compress)); + + val = 0x100008c; + val |= (compress.enable_global_bypass) << DEC_CONTROL_DISABLE_COMPRESSION_SHIFT; + val |= (!compress.enable_hw_flush) << DEC_CONTROL_DISABLE_HW_FLUSH_SHIFT; + dec400_write(dec, DEC_CONTROL, val); //0x101008c + + //info from VSI cmodel, don't modify + dec400_write(dec, DEC_CONTROL_EX, 0xa0000); + + //set tile status read/write ID, don't modity + val = 0x3fe840; + dec400_write(dec, DEC_CONTROL_EX2, val); + + //enable intr + dec400_write(dec, DEC_INTR_EN, 0xffffffff); + dec400_write(dec, DEC_INTR_EN_EX, 0xffffffff); + dec400_write(dec, DEC_INTR_EN_EX2, 0xffffffff); + + return 0; +} + +static int dec400_decompress_init(struct dec400_dev *dec, void *args) +{ + unsigned int val = 0; + struct dec400_compress_init compress = {0}; + + copy_from_user(&compress, args, sizeof(compress)); + + val = 0x100008c; + val |= (compress.enable_global_bypass) << DEC_CONTROL_DISABLE_COMPRESSION_SHIFT; + val |= (!compress.enable_hw_flush) << DEC_CONTROL_DISABLE_HW_FLUSH_SHIFT; + dec400_write(dec, DEC_CONTROL, val); //0x100008c + + //info from VSI cmodel, don't modify + dec400_write(dec, DEC_CONTROL_EX, 0xa0000); + + //set tile status read/write ID, don't modity + val = 0x3fe840; + dec400_write(dec, DEC_CONTROL_EX2, val); + + //enable intr + dec400_write(dec, DEC_INTR_EN, 0xffffffff); + dec400_write(dec, DEC_INTR_EN_EX, 0xffffffff); + dec400_write(dec, DEC_INTR_EN_EX2, 0xffffffff); + + return 0; +} + +static int dec400_compress_set_buffer(struct dec400_dev *dec, void *args) +{ + unsigned int val = 0; + struct dec400_compress_para para = {0}; + + copy_from_user(¶, args, sizeof(para)); + + val = 0; + val |= (para.enable) << DEC_WRITE_CONFIG_COMPRESS_ENABLE_SHIFT; + val |= (para.format) << DEC_WRITE_CONFIG_COMPRESS_FORMAT_SHIFT; + val |= (para.align_mode) << DEC_WRITE_CONFIG_COMPRESS_ALIGN_SHIFT; + val |= (para.tile_mode) << DEC_WRITE_CONFIG_COMPRESS_TILE_SHIFT; + dec400_write(dec, DEC_WRITE_CFG_CH(para.channel), val); + dec400_write(dec, DEC_WRITE_EX_CFG_CH(para.channel), 0); + dec400_write(dec, DEC_WRITE_BUF_BASE_CH(para.channel), para.physical_stream_start); + dec400_write(dec, DEC_WRITE_BUF_END_CH(para.channel), para.physical_stream_end); + dec400_write(dec, DEC_WRITE_CACHE_BASE_CH(para.channel), para.physical_tile_start); + dec400_write(dec, DEC_FLUSH_CACHE_CH(para.channel), 0xffffffff); + +#ifdef DEBUG + pr_info("%s, dec400 compress0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n", + __func__, + DEC_WRITE_CFG_CH(para.channel), val, + DEC_WRITE_EX_CFG_CH(para.channel), 0, + DEC_WRITE_BUF_BASE_CH(para.channel), para.physical_stream_start, + DEC_WRITE_BUF_END_CH(para.channel), para.physical_stream_end, + DEC_WRITE_CACHE_BASE_CH(para.channel), para.physical_tile_start); +#endif + + return 0; +} + +static int dec400_decompress_set_buffer(struct dec400_dev *dec, void *args) +{ + unsigned int val = 0; + struct dec400_decompress_para para = {0}; + + copy_from_user(¶, args, sizeof(para)); + + val = 0; + val |= (para.enable) << DEC_READ_CONFIG_DECOMPRESS_ENABLE_SHIFT; + val |= (para.format) << DEC_READ_CONFIG_DECOMPRESS_FORMAT_SHIFT; + val |= (para.align_mode) << DEC_READ_CONFIG_DECOMPRESS_ALIGN_SHIFT; + val |= (para.tile_mode) << DEC_READ_CONFIG_DECOMPRESS_TILE_SHIFT; + dec400_write(dec, DEC_READ_CFG_CH(para.channel), val); + dec400_write(dec, DEC_READ_EX_CFG_CH(para.channel), 0); + dec400_write(dec, DEC_READ_BUF_BASE_CH(para.channel), para.physical_stream_start); + dec400_write(dec, DEC_READ_BUF_END_CH(para.channel), para.physical_stream_end); + dec400_write(dec, DEC_READ_CACHE_BASE_CH(para.channel), para.physical_tile_start); + +#ifdef DEBUG + pr_info("%s, dec400 decompress 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n", + __func__, + DEC_READ_CFG_CH(para.channel), val, + DEC_READ_EX_CFG_CH(para.channel), 0, + DEC_READ_BUF_BASE_CH(para.channel), para.physical_stream_start, + DEC_READ_BUF_END_CH(para.channel), para.physical_stream_end, + DEC_READ_CACHE_BASE_CH(para.channel), para.physical_tile_start); +#endif + + return 0; +} + +unsigned int dec400_priv_ioctl(struct dec400_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + if (!dev) { + pr_err("%s invalid para\n", __func__); + return ret; + } + + switch (cmd) { + case DEC400IOC_RESET: + ret = 0; + break; + case DEC400IOC_COMPRESS_INIT: + ret = dec400_compress_init(dev, args); + break; + case DEC400IOC_COMPRESS_SET_BUFFER: + ret = dec400_compress_set_buffer(dev, args); + break; + case DEC400IOC_DECOMPRESS_INIT: + ret = dec400_decompress_init(dev, args); + break; + case DEC400IOC_DECOMPRESS_SET_BUFFER: + ret = dec400_decompress_set_buffer(dev, args); + break; + case DEC400IOC_MMU_CONFIG: + ret = dec400_mmu_config(dev, args); + break; + default: + pr_err("unsupported command %d\n", cmd); + break; + } + + return ret; +} diff --git a/vvcam/native/dec400/dec400_ioctl.h b/vvcam/native/dec400/dec400_ioctl.h new file mode 100755 index 0000000..eeecde6 --- /dev/null +++ b/vvcam/native/dec400/dec400_ioctl.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _DEC400_IOC_H_ +#define _DEC400_IOC_H_ +#include + +enum { + DEC400IOC_RESET = 0, + DEC400IOC_WRITE_REG, + DEC400IOC_READ_REG, + DEC400IOC_COMPRESS_INIT, + DEC400IOC_DECOMPRESS_INIT, + DEC400IOC_COMPRESS_SET_BUFFER, + DEC400IOC_DECOMPRESS_SET_BUFFER, + DEC400IOC_MMU_CONFIG +}; + +struct dec400_compress_init { + unsigned char enable_global_bypass; + unsigned char enable_hw_flush; +}; + +struct dec400_decompress_init { + unsigned char enable_global_bypass; + unsigned char enable_hw_flush; +}; + +struct dec400_mmu_para { + unsigned long long page_bable_addr; +}; + +enum dec400_compress_channel { + DEC400_COMPRESS_CHANNEL_0 = 0, + DEC400_COMPRESS_CHANNEL_1, + DEC400_COMPRESS_CHANNEL_2, + DEC400_COMPRESS_CHANNEL_3, + DEC400_COMPRESS_CHANNEL_4, + DEC400_COMPRESS_CHANNEL_5, + DEC400_COMPRESS_CHANNEL_6, + DEC400_COMPRESS_CHANNEL_7, + DEC400_COMPRESS_CHANNEL_8, + DEC400_COMPRESS_CHANNEL_9, + DEC400_COMPRESS_CHANNEL_10, + DEC400_COMPRESS_CHANNEL_11, + DEC400_COMPRESS_CHANNEL_12, + DEC400_COMPRESS_CHANNEL_13, + DEC400_COMPRESS_CHANNEL_14, + DEC400_COMPRESS_CHANNEL_15 +}; + +enum dec400_decompress_channel { + DEC400_DECOMPRESS_CHANNEL_0 = 0, + DEC400_DECOMPRESS_CHANNEL_1, + DEC400_DECOMPRESS_CHANNEL_2, + DEC400_DECOMPRESS_CHANNEL_3, + DEC400_DECOMPRESS_CHANNEL_4, + DEC400_DECOMPRESS_CHANNEL_5, + DEC400_DECOMPRESS_CHANNEL_6, + DEC400_DECOMPRESS_CHANNEL_7, + DEC400_DECOMPRESS_CHANNEL_8, + DEC400_DECOMPRESS_CHANNEL_9, + DEC400_DECOMPRESS_CHANNEL_10, + DEC400_DECOMPRESS_CHANNEL_11, + DEC400_DECOMPRESS_CHANNEL_12, + DEC400_DECOMPRESS_CHANNEL_13, + DEC400_DECOMPRESS_CHANNEL_14, + DEC400_DECOMPRESS_CHANNEL_15 +}; + +enum dec400_format { + DEC_FMT_ARGB8 = 0, + DEC_FMT_XRGB8 = 1, + DEC_FMT_AYUV = 2, + DEC_FMT_UYVY = 3, + DEC_FMT_YUY2 = 4, + DEC_FMT_YUV_ONLY = 5, + DEC_FMT_UV_MIX = 6, + DEC_FMT_ARGB4 = 7, + DEC_FMT_XRGB4 = 8, + DEC_FMT_A1RGB5 = 9, + DEC_FMT_X1RGB5 = 10, + DEC_FMT_R5G6B5 = 11, + DEC_FMT_A2R10G10B10 = 15, + DEC_FMT_BAYER = 16, + DEC_FMT_COEFFICIENT = 18, + DEC_FMT_ARGB16 = 19, + DEC_FMT_X2RGB10 = 21 +}; +enum dec400_tile_mode { + DEC_TILE8X8_XMAJOR = 0, + DEC_TILE8X8_YMAJOR = 1, + DEC_TILE16X4 = 2, + DEC_TILE8X4 = 3, + DEC_TILE4X8 = 4, + DEC_RASTER16X4 = 6, + DEC_TILE64X4 = 7, + DEC_TILE32X4 = 8, + DEC_RASTER256X1 = 9, + DEC_RASTER128X1 = 10, + DEC_RASTER64X4 = 11, + DEC_RASTER256X2 = 12, + DEC_RASTER128X2 = 13, + DEC_RASTER128X4 = 14, + DEC_RASTER64X1 = 15, + DEC_TILE16X8 = 16, + DEC_TILE8X16 = 17, + DEC_RASTER512X1 = 18, + DEC_RASTER32X4 = 19, + DEC_RASTER64X2 = 20, + DEC_RASTER32X2 = 21, + DEC_RASTER32X1 = 22, + DEC_RASTER16X1 = 23, + DEC_TILE128X4 = 24, + DEC_TILE256X4 = 25, + DEC_TILE512X4 = 26, + DEC_TILE16X16 = 27, + DEC_TILE32X16 = 28, + DEC_TILE64X16 = 29, + DEC_TILE128X8 = 30, + DEC_TILE8X4_S = 31, + DEC_TILE16X4_S = 32, + DEC_TILE32X4_S = 33, + DEC_TILE16X4_LSB = 34, + DEC_TILE32X4_LSB = 35, + DEC_TILE32X8 = 36 +}; + +enum dec400_aligh_mode { + DEC_ALIGN_1_BYTE = 0, + DEC_ALIGN_16_BYTE = 1, + DEC_ALIGN_32_BYTE = 2, + DEC_ALIGN_64_BYTE = 3, +}; + +struct dec400_compress_para { + unsigned char enable; + enum dec400_compress_channel channel; + enum dec400_format format; + enum dec400_tile_mode tile_mode; + enum dec400_aligh_mode align_mode; + unsigned long long physical_stream_start; + unsigned long long physical_stream_end; + unsigned long long physical_tile_start; +}; + +struct dec400_decompress_para { + unsigned char enable; + enum dec400_decompress_channel channel; + enum dec400_format format; + enum dec400_tile_mode tile_mode; + enum dec400_aligh_mode align_mode; + unsigned long long physical_stream_start; + unsigned long long physical_stream_end; + unsigned long long physical_tile_start; +}; + +#endif /* _DEC400_IOC_H_ */ diff --git a/vvcam/native/dw200/Makefile b/vvcam/native/dw200/Makefile new file mode 100644 index 0000000..b64e7d0 --- /dev/null +++ b/vvcam/native/dw200/Makefile @@ -0,0 +1,23 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_dw200 + +obj-m +=$(TARGET).o + +$(TARGET)-objs += vvcam_dwe_driver.o +$(TARGET)-objs += ../../dw200/vivdw200_irq_queue.o +$(TARGET)-objs += ../../dw200/dw200_ioctl.o +EXTRA_CFLAGS += -I$(PWD)/../../dw200 +EXTRA_CFLAGS += -I$(PWD)/../../common + + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam/native/dw200/vvcam_dwe_driver.c b/vvcam/native/dw200/vvcam_dwe_driver.c new file mode 100644 index 0000000..4a7c385 --- /dev/null +++ b/vvcam/native/dw200/vvcam_dwe_driver.c @@ -0,0 +1,597 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dw200_ioctl.h" +#include "vivdw200_irq_queue.h" + +#define VIVCAM_DWE_NAME "vivdw200" +#define VIVCAM_DWE_MAXCNT 1 +//#undef USE_RESERVED_MEM + +#ifdef __KERNEL__ +#define dw_info(...) +#else +#define dw_info(...) +#endif + +struct vvcam_dwe_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + unsigned int irq_num[2]; + struct vvcam_dwe_per_file_dev *current_file; + unsigned long long int dw200_userid; + struct platform_device *pdev; +#ifdef USE_RESERVED_MEM + struct resource mem; +#endif + struct clk *aclk; + struct clk *hclk; + struct clk *vseclk; + struct clk *dweclk; +}; + +struct vvcam_dwe_per_file_dev +{ + wait_queue_head_t irq_wait; + bool irq_trigger; + void *private; // point to dw200_subdev{} + int id; + struct vvcam_dwe_driver_dev *pdriver_dev; // point to global vvcam_dwe_driver_dev +}; + +static unsigned int vvcam_dwe_major = 0; +static unsigned int vvcam_dwe_minor = 0; +struct class *vvcam_dwe_class; +static unsigned int devise_register_index = 0; + +static unsigned int vvcam_dwe_poll(struct file * filp, poll_table *wait) +{ + unsigned int mask = 0; + struct vvcam_dwe_per_file_dev *per_file = (struct vvcam_dwe_per_file_dev *)filp->private_data; + poll_wait(filp, &per_file->irq_wait, wait); + + dw_info("poll dwe_irq %d for irq_wait %p id=%d\n", per_file->irq_trigger, &per_file->irq_wait, per_file->id); + + if (per_file->irq_trigger) { + mask |= POLLIN |POLLRDNORM; + dw_info("poll notify user space\n"); + per_file->irq_trigger = false; + } + + return mask; +} + +irqreturn_t vivdw200_interrupt(int irq, void* dev_id) +{ + dw_info(" %s enter\n", __func__); + vivdw200_mis_t node; + unsigned int dwe_mis, vse_mis; + struct vvcam_dwe_driver_dev *pdriver_dev = dev_id; + struct vvcam_dwe_per_file_dev *current_file = pdriver_dev->current_file; + struct dw200_subdev *pdw200 = (struct dw200_subdev *)current_file->private; + dw_info("%s current per_file=%p,pdw200=%p id=%d\n", __func__, current_file, pdw200, current_file->id); + dwe_mis = 0; + vse_mis = 0; + + dwe_read_irq((struct dw200_subdev *)pdw200, &dwe_mis); + dwe_mis = dwe_mis & (~0xff00); + + if (0 != dwe_mis) { + dw_info(" %s dwe mis 0x%08x\n", __func__, dwe_mis); + dwe_clear_irq((struct dw200_subdev *)pdw200, dwe_mis <<24); + + node.val = dwe_mis; + vivdw200_write_circle_queue(&node, &pdw200->dwe_circle_list); + current_file->irq_trigger |= true; + + } + + vse_read_irq((struct dw200_subdev *)pdw200, &vse_mis); + + if (0 != vse_mis) { + dw_info(" %s vse mis 0x%08x\n", __func__, vse_mis); + vse_clear_irq((struct dw200_subdev *)pdw200, vse_mis); + node.val = vse_mis; + vivdw200_write_circle_queue(&node, &pdw200->vse_circle_list); + current_file->irq_trigger |= true; + } + if (dwe_mis || vse_mis){ + wake_up_interruptible(¤t_file->irq_wait); + } else { + return IRQ_HANDLED; // return IRQ_NONE; + } + dw_info(" %s exit\n", __func__); + return IRQ_HANDLED; +} + +static int vvcam_dwe_open(struct inode * inode, struct file * file) +{ + struct vvcam_dwe_driver_dev *pdriver_dev = container_of(inode->i_cdev, struct vvcam_dwe_driver_dev, cdev); + struct dw200_subdev * pdw200 = kzalloc(sizeof(struct dw200_subdev), GFP_KERNEL); + struct vvcam_dwe_per_file_dev *per_file = kzalloc(sizeof(struct vvcam_dwe_per_file_dev), GFP_KERNEL); + per_file->id = pdriver_dev->dw200_userid++; + dw_info("%s per_file=%p,pdw200=%p id=%d\n", __func__, per_file, pdw200, per_file->id); + pdw200->dwe_base = ioremap(DWE_REG_BASE, DWE_REG_SIZE); + pdw200->vse_base = ioremap(VSE_REG_BASE, VSE_REG_SIZE); +#ifdef DWE_REG_RESET + pdwe_dev->dwe_reset = ioremap(DWE_REG_RESET, 4); +#endif +#ifdef VSE_REG_RESET + pdwe_dev->vse_reset = ioremap(VSE_REG_RESET, 4); +#endif + file->private_data = per_file; + per_file->private = pdw200; + per_file->pdriver_dev = pdriver_dev; + /*create circle queue*/ + vivdw200_create_circle_queue(&(pdw200->dwe_circle_list), QUEUE_NODE_COUNT); + vivdw200_create_circle_queue(&(pdw200->vse_circle_list), QUEUE_NODE_COUNT); + init_waitqueue_head(&per_file->irq_wait); + pdw200->vvmutex = &pdriver_dev->vvmutex; + return 0; +}; + +static long vvcam_dwe_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct dw200_subdev* pdwe_dev; + struct vvcam_dwe_per_file_dev *per_file = (struct vvcam_dwe_per_file_dev *)file->private_data; + struct vvcam_dwe_driver_dev *pdriver_dev = per_file->pdriver_dev; + struct device *dev = &pdriver_dev->pdev->dev; + + if (per_file == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + pdwe_dev = per_file->private; + dw_info("%s cmd=0x%x id=%d", __func__, cmd, per_file->id); + switch (cmd) { + case DW200IOC_UPDATECURR: + pdriver_dev->current_file = per_file; + dw_info("DW200IOC_UPDATECURR\n"); + break; +#ifdef USE_RESERVED_MEM + case DW200IOC_GET_RESERVE_ADDR: + copy_to_user(arg, &pdriver_dev->mem.start, sizeof(uint32_t)); + dw_info("DW200IOC_GET_RESERVE_ADDR copied pdriver_dev->mem.start 0x%x\n", pdriver_dev->mem.start); + break; +#endif + case DW200IOC_RUNTIME_RESUME: + pm_runtime_resume_and_get(dev); + break; + case DW200IOC_RUNTIME_SUSPEND: + pm_runtime_put_sync(dev); + break; + } + ret = dw200_priv_ioctl(pdwe_dev, cmd ,(void *)arg); + return ret; +}; + +static int vvcam_dwe_release(struct inode * inode, struct file * file) +{ + struct vvcam_dwe_per_file_dev *per_file = (struct vvcam_dwe_per_file_dev *)file->private_data; + struct dw200_subdev * pdw200; + pdw200 = (struct dw200_subdev *)per_file->private; + mutex_unlock(pdw200->vvmutex); + /*destory circle queue*/ + vivdw200_destroy_circle_queue(&(pdw200->dwe_circle_list)); + vivdw200_destroy_circle_queue(&(pdw200->vse_circle_list)); + kfree(per_file); + return 0; +}; + +static int vvcam_dwe_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct vvcam_dwe_per_file_dev *per_file = (struct vvcam_dwe_per_file_dev *)file->private_data; + struct vvcam_dwe_driver_dev *pdriver_dev = per_file->pdriver_dev; + int ret = 0; +#ifdef USE_RESERVED_MEM + unsigned long pfn_start = phys_to_pfn(pdriver_dev->mem.start) + vma->vm_pgoff; + unsigned long size = vma->vm_end - vma->vm_start; + dw_info("phy: 0x%lx, size: 0x%lx PAGE_SHIFT: %d vma->vm_pgoff: 0x%lx vma->vm_start: 0x%lx\n", pfn_to_phys(pfn_start), size, PAGE_SHIFT, vma->vm_pgoff, vma->vm_start); + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + if (remap_pfn_range(vma, vma->vm_start, pfn_start, size, vma->vm_page_prot)) + { + pr_err("-->%s: remap_pfn_range error!\n", __func__); + return -EIO; + } +#else + ret = -EIO; +#endif + return ret; +}; + +struct file_operations vvcam_dwe_fops = { + .owner = THIS_MODULE, + .open = vvcam_dwe_open, + .release = vvcam_dwe_release, + .unlocked_ioctl = vvcam_dwe_ioctl, + .poll = vvcam_dwe_poll, + .mmap = vvcam_dwe_mmap, +}; + +static int vvcam_dwe_runtime_suspend(struct device *dev) +{ + struct vvcam_dwe_driver_dev *pdriver_dev = dev_get_drvdata(dev); + + if (IS_ERR(pdriver_dev->dweclk) || IS_ERR(pdriver_dev->vseclk) + || IS_ERR(pdriver_dev->hclk) || IS_ERR(pdriver_dev->aclk)) { + return 0; + } + + dw_info("%s\n", __func__); + + clk_disable_unprepare(pdriver_dev->aclk); + clk_disable_unprepare(pdriver_dev->hclk); + clk_disable_unprepare(pdriver_dev->vseclk); + clk_disable_unprepare(pdriver_dev->dweclk); + + return 0; +} + +static int vvcam_dwe_runtime_resume(struct device *dev) +{ + struct vvcam_dwe_driver_dev *pdriver_dev = dev_get_drvdata(dev); + int ret = 0; + + if (IS_ERR(pdriver_dev->dweclk) || IS_ERR(pdriver_dev->vseclk) + || IS_ERR(pdriver_dev->hclk) || IS_ERR(pdriver_dev->aclk)) { + return 0; + } + + ret = clk_prepare_enable(pdriver_dev->dweclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable dwe clock\n"); + } + + ret = clk_prepare_enable(pdriver_dev->vseclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable vse clock\n"); + clk_disable_unprepare(pdriver_dev->dweclk); + //return ret; + } + + ret = clk_prepare_enable(pdriver_dev->hclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable ahb clock\n"); + clk_disable_unprepare(pdriver_dev->dweclk); + clk_disable_unprepare(pdriver_dev->vseclk); + //return ret; + } + + ret = clk_prepare_enable(pdriver_dev->aclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable axi clock\n"); + clk_disable_unprepare(pdriver_dev->dweclk); + clk_disable_unprepare(pdriver_dev->vseclk); + clk_disable_unprepare(pdriver_dev->hclk); + //return ret; + } + + dw_info("%s Enabled clock\n", __func__); + return ret; +} + +static const struct dev_pm_ops vvcam_dwe_runtime_pm_ops = { + SET_RUNTIME_PM_OPS(vvcam_dwe_runtime_suspend, vvcam_dwe_runtime_resume, NULL) +}; + +void __iomem *visys_sw_rst; +#ifdef USE_RESERVED_MEM +static int vvcam_dwe_of_parse(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np; + int ret = 0; + struct vvcam_dwe_driver_dev *pdriver_dev = platform_get_drvdata(pdev); + + np = of_parse_phandle(dev->of_node, "memory-region", 0); + if (!np) { + dev_err(dev, "No %s specified\n", "memory-region"); + return -EINVAL; + } + + ret = of_address_to_resource(np, 0, &pdriver_dev->mem); + if (ret) { + dev_err(dev, "of_address_to_resource fail\n"); + return ret; + } + dw_info("%s got mem start 0x%x size 0x%x\n", __func__, pdriver_dev->mem.start, resource_size(&pdriver_dev->mem)); + + return ret; +} +#endif +static int vvcam_dwe_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vvcam_dwe_driver_dev *pdriver_dev; + + dw_info("enter %s\n", __func__); + + if (pdev->id >= VIVCAM_DWE_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_dwe_driver_dev), GFP_KERNEL); + + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_soc_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_dwe_driver_dev )); + + visys_sw_rst = ioremap(0xffe4040100, 0x00001000); +#ifdef DWE_REG_RESET + pdwe_dev->dwe_reset = ioremap(DWE_REG_RESET, 4); +#endif +#ifdef VSE_REG_RESET + pdwe_dev->vse_reset = ioremap(VSE_REG_RESET, 4); +#endif + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + pdriver_dev->pdev = pdev; + pdriver_dev->irq_num[0] = platform_get_irq(pdev, 0); + if (pdriver_dev->irq_num[0] == 0) { + pr_err("%s:dw200_[%d]: could not map IRQ\n", __func__, pdev->id); + dev_err(&pdev->dev, "could not map IRQ.\n"); + return -ENXIO; + } + dw_info("%s:dw200_[%d]: pdriver_dev->irq_num[0]=%d\n", __func__, pdev->id, pdriver_dev->irq_num[0]); + + pdriver_dev->irq_num[1] = platform_get_irq(pdev, 1); + if (pdriver_dev->irq_num[1] == 0) { + pr_err("%s:dw200_[%d]: could not map IRQ\n", __func__, pdev->id); + dev_err(&pdev->dev, "could not map IRQ.\n"); + return -ENXIO; + } + dw_info("%s:dw200_[%d]: pdriver_dev->irq_num[1]=%d\n", __func__, pdev->id, pdriver_dev->irq_num[1]); + + ret = request_irq(pdriver_dev->irq_num[0], vivdw200_interrupt, + IRQF_SHARED|IRQF_TRIGGER_RISING, "DEWARP_IRQ", (char *)pdriver_dev); + if (ret) { + pr_err("%s[%d]:request irq error!\n", __func__, __LINE__); + return ret; + } + + ret = request_irq(pdriver_dev->irq_num[1], vivdw200_interrupt, + IRQF_SHARED|IRQF_TRIGGER_RISING, "SCALAR_IRQ", (char *)pdriver_dev); + if (ret) { + pr_err("%s[%d]:request irq error!\n", __func__, __LINE__); + return ret; + } +#ifdef USE_RESERVED_MEM + ret = vvcam_dwe_of_parse(pdev); + if (ret) { + pr_err("%s[%d]: vvcam_dwe_of_parse error!\n", __func__, __LINE__); + return ret; + } +#else + pr_info("%s:disable vvcam_dwe_of_parse reserved-memory\n", __func__); +#endif + if (devise_register_index == 0) + { + if (vvcam_dwe_major == 0) + { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_DWE_MAXCNT, VIVCAM_DWE_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_dwe_major = MAJOR(pdriver_dev->devt); + vvcam_dwe_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_dwe_major, vvcam_dwe_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_DWE_MAXCNT, VIVCAM_DWE_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + vvcam_dwe_class = class_create(THIS_MODULE, VIVCAM_DWE_NAME); + if (IS_ERR(vvcam_dwe_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_dwe_major, vvcam_dwe_minor + pdev->id + 1); // just in case platform instance num is -1 + + cdev_init(&pdriver_dev->cdev, &vvcam_dwe_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_dwe_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s", VIVCAM_DWE_NAME); + + devise_register_index++; + + pdriver_dev->dweclk = devm_clk_get(&pdev->dev, "dweclk"); + if (IS_ERR(pdriver_dev->dweclk)) { + dev_err(&pdev->dev, "failed to get dwe clk"); + //return -1; + } + + pdriver_dev->vseclk = devm_clk_get(&pdev->dev, "vseclk"); + if (IS_ERR(pdriver_dev->vseclk)) { + dev_err(&pdev->dev, "failed to get vse clk"); + //return -1; + } + + pdriver_dev->hclk = devm_clk_get(&pdev->dev, "hclk"); + if (IS_ERR(pdriver_dev->hclk)) { + dev_err(&pdev->dev, "failed to get hclk"); + //return -1; + } + + pdriver_dev->aclk = devm_clk_get(&pdev->dev, "aclk"); + if (IS_ERR(pdriver_dev->aclk)) { + dev_err(&pdev->dev, "failed to get aclk"); + //return -1; + } + + pm_runtime_enable(&pdev->dev); + pm_runtime_resume_and_get(&pdev->dev); + pm_runtime_put_sync(&pdev->dev); + + dw_info("exit %s:[%d]\n", __func__, pdev->id); + return ret; +} + +static int vvcam_dwe_remove(struct platform_device *pdev) +{ + struct vvcam_dwe_driver_dev *pdriver_dev; + //struct dw200_subdev * pdwe_dev; + + dw_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + free_irq(pdriver_dev->irq_num[0], pdriver_dev); + free_irq(pdriver_dev->irq_num[1], pdriver_dev); + + //pdwe_dev = pdriver_dev->private; + //iounmap(pdwe_dev->dwe_base); + //iounmap(pdwe_dev->vse_base); + //iounmap(pdwe_dev->dwe_reset); + //iounmap(pdwe_dev->vse_reset); + pm_runtime_disable(&pdev->dev); + if (!pm_runtime_status_suspended(&pdev->dev)) { // turn off the power regardless of the ref cnt + vvcam_dwe_runtime_suspend(&pdev->dev); + } + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_DWE_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + + return 0; +} + +static const struct of_device_id dewarp_of_match[] = { + { .compatible = "thead,light-dewarp", }, + { /* sentinel */ }, +}; + +static struct platform_driver vvcam_dwe_driver = { + .probe = vvcam_dwe_probe, + .remove = vvcam_dwe_remove, + .driver = { + .name = VIVCAM_DWE_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(dewarp_of_match), + .pm = &vvcam_dwe_runtime_pm_ops, + } +}; + +static int __init vvcam_dwe_init_module(void) +{ + int ret = 0; + + dw_info("enter %s\n", __func__); + + ret = platform_driver_register(&vvcam_dwe_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit vvcam_dwe_exit_module(void) +{ + dw_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_dwe_driver); +} + +module_init(vvcam_dwe_init_module); +module_exit(vvcam_dwe_exit_module); + +MODULE_DESCRIPTION("DWE"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/flash_led/Makefile b/vvcam/native/flash_led/Makefile new file mode 100755 index 0000000..1401a9c --- /dev/null +++ b/vvcam/native/flash_led/Makefile @@ -0,0 +1,43 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_flash_led + +obj-m +=$(TARGET).o +$(TARGET)-objs += flash_led_driver.o +$(TARGET)-objs += flash_led_ioctl.o +$(TARGET)-objs += flash_led_sysfs.o +$(TARGET)-objs += ntc.o + + +EXTRA_CFLAGS += -I$(PWD)/../../common + +ifeq ($(FLASH_LED_TYPE1), aw36515) +$(TARGET)-objs += ./aw36515/aw36515_driver.o +EXTRA_CFLAGS += -I$(PWD)/aw36515 +EXTRA_CFLAGS += -DPROJECTION_FUNCTION=aw36515_function +endif + +ifeq ($(FLASH_LED_TYPE2), aw36413) +$(TARGET)-objs += ./aw36413/aw36413_driver.o +EXTRA_CFLAGS += -I$(PWD)/aw36413 +EXTRA_CFLAGS += -DFLOODLIGHT_FUNCTION=aw36413_function +endif + + + +#EXTRA_CFLAGS += -DSENSR0_TYPE +EXTRA_CFLAGS += -I$(PWD)/ + +PWD :=$(shell pwd) + +$(info YANDONG KERNEL=$(KERNEL)) +$(info YANDONG KERNEL_SRC=$(KERNEL_SRC)) + +all: + make V=1 -C $(KERNEL_SRC) M=$(PWD) modules +modules_install: + make V=1 -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL_SRC) M=`pwd` clean + diff --git a/vvcam/native/flash_led/aw36413/aw36413_driver.c b/vvcam/native/flash_led/aw36413/aw36413_driver.c new file mode 100755 index 0000000..2eb7ce5 --- /dev/null +++ b/vvcam/native/flash_led/aw36413/aw36413_driver.c @@ -0,0 +1,268 @@ +#include +#include +#include "flash_led_driver.h" +#include "flash_led_ioctl.h" +#include "aw36413_driver.h" + +/* flashlight enable function */ +static volatile uint32_t aw_reg1_val = 0x0; +static int aw36413_enable(void *ctx, int channel) +{ + int ret; + struct flash_led_dev *dev = ctx; + unsigned char reg = 0; + uint32_t mask = 0; + + if (channel == 1) { + mask = AW36413_ENABLE_LED1; + } else if (channel == 2) { + mask = AW36413_ENABLE_LED2; + } else if (channel == 3) { + mask = AW36413_ENABLE_LED1 | AW36413_ENABLE_LED2; + } + + aw_reg1_val |= mask; + + reg = AW36413_REG_ENABLE; + + return flash_led_i2c_write(dev, reg, aw_reg1_val); +} + +/* flashlight disable function */ +static int aw36413_disable(void *ctx, int channel) +{ + int ret; + struct flash_led_dev *dev = ctx; + unsigned char reg = 0; + uint32_t mask = 0; + + if (channel == 1) { + mask = AW36413_ENABLE_LED1; + } else if (channel == 2) { + mask = AW36413_ENABLE_LED2; + } else if (channel == 3) { + mask = AW36413_ENABLE_LED1 | AW36413_ENABLE_LED2; + } + + aw_reg1_val &= ~mask; + + reg = AW36413_REG_ENABLE; + + return flash_led_i2c_write(dev, reg, aw_reg1_val); +} + +/* set flashlight level */ +static int aw36413_set_ch1_flash_brightness(void *ctx, int level) +{ + int ret; + uint32_t val = 0; + unsigned char reg = 0; + struct flash_led_dev *dev = ctx; + + /* set flash brightness level */ + reg = AW36413_REG_FLASH_LEVEL_LED1; + val = level & 0xff; + ret = flash_led_i2c_write(dev, reg, val); + + return ret; +} + +static int aw36413_set_ch1_torch_brightness(void *ctx, int level) +{ + int ret; + uint32_t val = 0; + unsigned char reg = 0; + struct flash_led_dev *dev = ctx; + + /* set torch brightness level */ + reg = AW36413_REG_TORCH_LEVEL_LED1; + val = level & 0xff; + ret = flash_led_i2c_write(dev, reg, val); + + return ret; +} + +static int aw36413_set_ch2_flash_brightness(void *ctx, int level) +{ + int ret; + uint32_t val = 0; + unsigned char reg = 0; + struct flash_led_dev *dev = ctx; + + reg = AW36413_REG_FLASH_LEVEL_LED2; + val = level & 0xff; + ret = flash_led_i2c_write(dev, reg, val); + + return ret; +} + +static int aw36413_set_ch2_torch_brightness(void *ctx, int level) +{ + int ret; + uint32_t val = 0; + unsigned char reg = 0; + struct flash_led_dev *dev = ctx; + + reg = AW36413_REG_TORCH_LEVEL_LED2; + val = level & 0xff; + ret = flash_led_i2c_write(dev, reg, val); + + return ret; +} + +static int aw36413_set_flash_brightness(void *ctx, int channel, uint32_t level) +{ + int ret = 0; + struct flash_led_dev *dev = ctx; + + if (channel == 1) { + ret = aw36413_set_ch1_flash_brightness(dev, level); + } else if (channel == 2) { + ret = aw36413_set_ch2_flash_brightness(dev, level); + } else if (channel == 3) { + ret = aw36413_set_ch1_flash_brightness(dev, level); + if (ret != 0) { + return -1; + } + ret = aw36413_set_ch2_flash_brightness(dev, level); + } else { + return -1; + } + + return ret; +} + +static int aw36413_set_torch_brightness(void *ctx, int channel, uint32_t level) +{ + int ret = 0; + struct flash_led_dev *dev = ctx; + + if (channel == 1) { + ret = aw36413_set_ch1_torch_brightness(dev, level); + } else if (channel == 2) { + ret = aw36413_set_ch2_torch_brightness(dev, level); + } else if (channel == 3) { + ret = aw36413_set_ch1_torch_brightness(dev, level); + if (ret != 0) { + return -1; + } + ret = aw36413_set_ch2_torch_brightness(dev, level); + } else { + return -1; + } + + return ret; +} + +#define AW36413_STANDBY_MODE 0x0 +#define AW36413_EXT_TORCH_MODE (0x1 << 4) +#define AW36413_EXT_FLASH_MODE (0x1 << 5) +#define AW36413_INT_TORCH_MODE (0x2 << 2) +#define AW36413_INT_FLASH_MODE (0x3 << 2) +#define AW36413_IR_STANDBY_MODE (0x1 << 2) +#define AW36413_IR_ENABLE_MODE ((0x1 << 2) | (1 << 5)) + +static int aw36413_set_mode(void *ctx, flash_led_mode_t mode) +{ + int ret = 0; + unsigned char reg = 0; + struct flash_led_dev *dev = ctx; + + reg = AW36413_REG_ENABLE; + aw_reg1_val &= 0x3; + + switch(mode) { + case FLASH_LED_STANDBY: + aw_reg1_val |= AW36413_STANDBY_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_EXT_TORCH: + aw_reg1_val |= AW36413_EXT_TORCH_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_EXT_FLASH: + aw_reg1_val |= AW36413_EXT_FLASH_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_INT_TORCH: + aw_reg1_val |= AW36413_INT_TORCH_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_INT_FLASH: + aw_reg1_val |= AW36413_INT_FLASH_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_IR_STANDBY: + aw_reg1_val |= AW36413_IR_STANDBY_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_IR_ENABLE: + aw_reg1_val |= AW36413_IR_ENABLE_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + default: + return -1; + } + + return ret; +} + +/* flashlight init */ +static int aw36413_init(void *ctx); + +/* flashlight uninit */ +static int aw36413_uninit(void *ctx) +{ + struct flash_led_dev *dev = ctx; + aw36413_disable(dev, 3); + + return 0; +} + +struct flash_led_function_s aw36413_function = +{ + .flash_led_name = "aw36413", + .reserve_id = 0x36, + .init = aw36413_init, + .uninit = aw36413_uninit, + .enable_channel = aw36413_enable, + .disable_channel = aw36413_disable, + .set_mode = aw36413_set_mode, + .set_flash_brightness = aw36413_set_flash_brightness, + .set_torch_brightness = aw36413_set_torch_brightness, +}; + +static int aw36413_init(void *ctx) +{ + struct flash_led_dev *dev = ctx; + int ret; + uint32_t val = 0; + unsigned char reg = 0; + + usleep_range(2000, 2500); + dev->flash_led_func = &aw36413_function; + + dev->flash_led_sccb_cfg.addr_byte = 1; + dev->flash_led_sccb_cfg.data_byte = 1; + dev->flash_led_sccb_cfg.slave_addr = AW36413_ADDR; + + /* clear enable register */ + reg = AW36413_REG_ENABLE; + aw_reg1_val = AW36413_DISABLE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + if (ret != 0) { + return -1; + } + + /* set torch current ramp time and flash timeout */ + reg = AW36413_REG_TIMING_CONF; + val = AW36413_TORCH_RAMP_TIME | AW36413_FLASH_TIMEOUT; + ret = flash_led_i2c_write(dev, reg, val); + if (ret != 0) { + return -1; + } + + ret = aw36413_set_mode(dev, FLASH_LED_IR_ENABLE); + return ret; +} + diff --git a/vvcam/native/flash_led/aw36413/aw36413_driver.h b/vvcam/native/flash_led/aw36413/aw36413_driver.h new file mode 100755 index 0000000..778c71f --- /dev/null +++ b/vvcam/native/flash_led/aw36413/aw36413_driver.h @@ -0,0 +1,36 @@ +#ifndef _AW36413_DRIVER_H_ +#define _AW36413_DRIVER_H_ + +/* define registers */ +#define AW36413_ADDR 0x6b + +#define AW36413_REG_ENABLE (0x01) +#define AW36413_MASK_ENABLE_LED1 (0x01) +#define AW36413_MASK_ENABLE_LED2 (0x02) +#define AW36413_DISABLE (0x00) +#define AW36413_ENABLE_LED1 (0x01) +#define AW36413_ENABLE_LED1_TORCH (0x09) +#define AW36413_ENABLE_LED1_FLASH (0x0D) +#define AW36413_ENABLE_LED2 (0x02) +#define AW36413_ENABLE_LED2_TORCH (0x0A) +#define AW36413_ENABLE_LED2_FLASH (0x0E) + +#define AW36413_REG_TORCH_LEVEL_LED1 (0x05) +#define AW36413_REG_FLASH_LEVEL_LED1 (0x03) +#define AW36413_REG_TORCH_LEVEL_LED2 (0x06) +#define AW36413_REG_FLASH_LEVEL_LED2 (0x04) + +#define AW36413_REG_TIMING_CONF (0x08) +#define AW36413_TORCH_RAMP_TIME (0x10) +#define AW36413_FLASH_TIMEOUT (0x0F) + +/* define channel, level */ +#define AW36413_CHANNEL_NUM 2 +#define AW36413_CHANNEL_CH1 0 +#define AW36413_CHANNEL_CH2 1 +#define AW36413_LEVEL_NUM 26 +#define AW36413_LEVEL_TORCH 26 //always in torch mode + +extern struct flash_led_function_s aw36413_function; + +#endif diff --git a/vvcam/native/flash_led/aw36515/aw36515_driver.c b/vvcam/native/flash_led/aw36515/aw36515_driver.c new file mode 100755 index 0000000..9558833 --- /dev/null +++ b/vvcam/native/flash_led/aw36515/aw36515_driver.c @@ -0,0 +1,268 @@ +#include +#include +#include "flash_led_driver.h" +#include "flash_led_ioctl.h" +#include "aw36515_driver.h" + +static volatile uint32_t aw_reg1_val = 0x0; + +/* flashlight enable function */ +static int aw36515_enable(void *ctx, int channel) +{ + int ret; + struct flash_led_dev *dev = ctx; + unsigned char reg = 0; + uint32_t mask = 0; + + if (channel == 1) { + mask = AW36515_ENABLE_LED1; + } else if (channel == 2) { + mask = AW36515_ENABLE_LED2; + } else if (channel == 3) { + mask = AW36515_ENABLE_LED1 | AW36515_ENABLE_LED2; + } + + aw_reg1_val |= mask; + + reg = AW36515_REG_ENABLE; + + return flash_led_i2c_write(dev, reg, aw_reg1_val); +} + +/* flashlight disable function */ +static int aw36515_disable(void *ctx, int channel) +{ + int ret; + struct flash_led_dev *dev = ctx; + unsigned char reg = 0; + uint32_t mask = 0; + + if (channel == 1) { + mask = AW36515_ENABLE_LED1; + } else if (channel == 2) { + mask = AW36515_ENABLE_LED2; + } else if (channel == 3) { + mask = AW36515_ENABLE_LED1 | AW36515_ENABLE_LED2; + } + + aw_reg1_val &= ~mask; + + reg = AW36515_REG_ENABLE; + + return flash_led_i2c_write(dev, reg, aw_reg1_val); +} + +/* set flashlight level */ +static int aw36515_set_ch1_flash_brightness(void *ctx, int level) +{ + int ret; + uint32_t val = 0; + unsigned char reg = 0; + struct flash_led_dev *dev = ctx; + + /* set flash brightness level */ + reg = AW36515_REG_FLASH_LEVEL_LED1; + val = level & 0xff; + ret = flash_led_i2c_write(dev, reg, val); + + return ret; +} + +static int aw36515_set_ch1_torch_brightness(void *ctx, int level) +{ + int ret; + uint32_t val = 0; + unsigned char reg = 0; + struct flash_led_dev *dev = ctx; + + /* set torch brightness level */ + reg = AW36515_REG_TORCH_LEVEL_LED1; + val = level & 0xff; + ret = flash_led_i2c_write(dev, reg, val); + + return ret; +} + +static int aw36515_set_ch2_flash_brightness(void *ctx, int level) +{ + int ret; + uint32_t val = 0; + unsigned char reg = 0; + struct flash_led_dev *dev = ctx; + + reg = AW36515_REG_FLASH_LEVEL_LED2; + val = level & 0xff; + ret = flash_led_i2c_write(dev, reg, val); + + return ret; +} + +static int aw36515_set_ch2_torch_brightness(void *ctx, int level) +{ + int ret; + uint32_t val = 0; + unsigned char reg = 0; + struct flash_led_dev *dev = ctx; + + reg = AW36515_REG_TORCH_LEVEL_LED2; + val = level & 0xff; + ret = flash_led_i2c_write(dev, reg, val); + + return ret; +} + +static int aw36515_set_flash_brightness(void *ctx, int channel, uint32_t level) +{ + int ret = 0; + struct flash_led_dev *dev = ctx; + + if (channel == 1) { + ret = aw36515_set_ch1_flash_brightness(dev, level); + } else if (channel == 2) { + ret = aw36515_set_ch2_flash_brightness(dev, level); + } else if (channel == 3) { + ret = aw36515_set_ch1_flash_brightness(dev, level); + if (ret != 0) { + return -1; + } + ret = aw36515_set_ch2_flash_brightness(dev, level); + } else { + return -1; + } + + return ret; +} + +static int aw36515_set_torch_brightness(void *ctx, int channel, uint32_t level) +{ + int ret = 0; + struct flash_led_dev *dev = ctx; + + if (channel == 1) { + ret = aw36515_set_ch1_torch_brightness(dev, level); + } else if (channel == 2) { + ret = aw36515_set_ch2_torch_brightness(dev, level); + } else if (channel == 3) { + ret = aw36515_set_ch1_torch_brightness(dev, level); + if (ret != 0) { + return -1; + } + ret = aw36515_set_ch2_torch_brightness(dev, level); + } else { + return -1; + } + + return ret; +} + +#define AW36515_STANDBY_MODE 0x0 +#define AW36515_EXT_TORCH_MODE (0x1 << 4) +#define AW36515_EXT_FLASH_MODE (0x1 << 5) +#define AW36515_INT_TORCH_MODE (0x2 << 2) +#define AW36515_INT_FLASH_MODE (0x3 << 2) +#define AW36515_IR_STANDBY_MODE (0x1 << 2) +#define AW36515_IR_ENABLE_MODE ((0x1 << 2) | (1 << 5)) + +static int aw36515_set_mode(void *ctx, flash_led_mode_t mode) +{ + int ret = 0; + unsigned char reg = 0; + struct flash_led_dev *dev = ctx; + + reg = AW36515_REG_ENABLE; + aw_reg1_val &= 0x3; + + switch(mode) { + case FLASH_LED_STANDBY: + aw_reg1_val |= AW36515_STANDBY_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_EXT_TORCH: + aw_reg1_val |= AW36515_EXT_TORCH_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_EXT_FLASH: + aw_reg1_val |= AW36515_EXT_FLASH_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_INT_TORCH: + aw_reg1_val |= AW36515_INT_TORCH_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_INT_FLASH: + aw_reg1_val |= AW36515_INT_FLASH_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_IR_STANDBY: + aw_reg1_val |= AW36515_IR_STANDBY_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + case FLASH_LED_IR_ENABLE: + aw_reg1_val |= AW36515_IR_ENABLE_MODE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + break; + default: + return -1; + } + + return ret; +} + +/* flashlight init */ +static int aw36515_init(void *ctx); + +/* flashlight uninit */ +static int aw36515_uninit(void *ctx) +{ + struct flash_led_dev *dev = ctx; + aw36515_disable(dev, 3); + + return 0; +} + +struct flash_led_function_s aw36515_function = +{ + .flash_led_name = "aw36515", + .reserve_id = 0x30, + .init = aw36515_init, + .uninit = aw36515_uninit, + .enable_channel = aw36515_enable, + .disable_channel = aw36515_disable, + .set_mode = aw36515_set_mode, + .set_flash_brightness = aw36515_set_flash_brightness, + .set_torch_brightness = aw36515_set_torch_brightness, +}; + +static int aw36515_init(void *ctx) +{ + struct flash_led_dev *dev = ctx; + int ret; + unsigned char reg = 0; + uint32_t val= 0; + + dev->flash_led_func = &aw36515_function; + + dev->flash_led_sccb_cfg.addr_byte = 1; + dev->flash_led_sccb_cfg.data_byte = 1; + dev->flash_led_sccb_cfg.slave_addr = AW36515_ADDR; + + /* clear enable register */ + reg = AW36515_REG_ENABLE; + aw_reg1_val = AW36515_DISABLE; + ret = flash_led_i2c_write(dev, reg, aw_reg1_val); + if (ret != 0) { + return -1; + } + + /* set torch current ramp time and flash timeout */ + reg = AW36515_REG_TIMING_CONF; + val = AW36515_TORCH_RAMP_TIME | AW36515_FLASH_TIMEOUT; + ret = flash_led_i2c_write(dev, reg, val); + if (ret != 0) { + return -1; + } + + ret = aw36515_set_mode(dev, FLASH_LED_IR_ENABLE); + return ret; +} + diff --git a/vvcam/native/flash_led/aw36515/aw36515_driver.h b/vvcam/native/flash_led/aw36515/aw36515_driver.h new file mode 100755 index 0000000..3a65428 --- /dev/null +++ b/vvcam/native/flash_led/aw36515/aw36515_driver.h @@ -0,0 +1,36 @@ +#ifndef _AW36515_DRIVER_H_ +#define _AW36515_DRIVER_H_ + +/* define registers */ +#define AW36515_ADDR 0x63 + +#define AW36515_REG_ENABLE (0x01) +#define AW36515_MASK_ENABLE_LED1 (0x01) +#define AW36515_MASK_ENABLE_LED2 (0x02) +#define AW36515_DISABLE (0x00) +#define AW36515_ENABLE_LED1 (0x01) +#define AW36515_ENABLE_LED1_TORCH (0x09) +#define AW36515_ENABLE_LED1_FLASH (0x0D) +#define AW36515_ENABLE_LED2 (0x02) +#define AW36515_ENABLE_LED2_TORCH (0x0A) +#define AW36515_ENABLE_LED2_FLASH (0x0E) + +#define AW36515_REG_TORCH_LEVEL_LED1 (0x05) +#define AW36515_REG_FLASH_LEVEL_LED1 (0x03) +#define AW36515_REG_TORCH_LEVEL_LED2 (0x06) +#define AW36515_REG_FLASH_LEVEL_LED2 (0x04) + +#define AW36515_REG_TIMING_CONF (0x08) +#define AW36515_TORCH_RAMP_TIME (0x10) +#define AW36515_FLASH_TIMEOUT (0x0F) + +/* define channel, level */ +#define AW36515_CHANNEL_NUM 2 +#define AW36515_CHANNEL_CH1 0 +#define AW36515_CHANNEL_CH2 1 +#define AW36515_LEVEL_NUM 26 +#define AW36515_LEVEL_TORCH 26 //always in torch mode + +extern struct flash_led_function_s aw36515_function; + +#endif diff --git a/vvcam/native/flash_led/flash_led_driver.c b/vvcam/native/flash_led/flash_led_driver.c new file mode 100755 index 0000000..7530b5f --- /dev/null +++ b/vvcam/native/flash_led/flash_led_driver.c @@ -0,0 +1,655 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "flash_led_driver.h" +#include "flash_led_ioctl.h" + + +#define FLASH_LED_NAME "flash_led" +#define FLASH_LED_MAXCNT 10 + +static unsigned int flash_led_major = 0; +static unsigned int flash_led_minor = 0; +struct class *flash_led_class; +static unsigned int devise_register_index = 0; +extern int get_ntc_temperature(int mv); + + +static int flash_led_open(struct inode * inode, struct file * file) +{ + int ret = 0; + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + + pdriver_dev = container_of(inode->i_cdev, struct flash_led_driver_dev, cdev); + file->private_data = pdriver_dev; + + pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + + struct flash_led_dev *floodlight = &pflash_led_dev->floodlight; + struct flash_led_dev *projection = &pflash_led_dev->projection; + + if (floodlight->flash_led_func != NULL) { + ret = floodlight->flash_led_func->init(floodlight); + if (ret != 0) { + pr_err("%s, %d, floodlight init error\n", __func__, __LINE__); + return ret; + } + } + + if (projection->flash_led_func != NULL) { + ret = projection->flash_led_func->init(projection); + if (ret != 0) { + pr_err("%s, %d, projection init error\n", __func__, __LINE__); + return ret; + } + } + + return 0; +}; + +static long flash_led_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + + mutex_lock(&pdriver_dev->vvmutex); + ret = flash_led_priv_ioctl(pflash_led_dev, cmd, (void __user *)arg); + mutex_unlock(&pdriver_dev->vvmutex); + + return ret; +}; + +static int flash_led_release(struct inode * inode, struct file * file) +{ + + struct flash_led_driver_dev *pdriver_dev; + pdriver_dev = container_of(inode->i_cdev, struct flash_led_driver_dev, cdev); + struct flash_led_ctrl *pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + + struct flash_led_dev *floodlight = &pflash_led_dev->floodlight; + struct flash_led_dev *projection = &pflash_led_dev->projection; + + pflash_led_dev->enable = 0; + + if (projection->flash_led_func != NULL) { + projection->flash_led_func->disable_channel(projection, 3); + } + + if (floodlight->flash_led_func != NULL) { + floodlight->flash_led_func->disable_channel(floodlight, 3); + } + + return 0; +}; + +struct file_operations flash_led_fops = { + .owner = THIS_MODULE, + .open = flash_led_open, + .release = flash_led_release, + .unlocked_ioctl = flash_led_ioctl, +}; + +static int flash_led_of_parse(struct platform_device *pdev) +{ + int ret = 0, regulator_num = 0; + struct device_node *np = pdev->dev.of_node; + struct flash_led_driver_dev *pdriver_dev = platform_get_drvdata(pdev); + struct flash_led_ctrl *pflash_led_dev = pdriver_dev->private; + struct flash_led_dev *floodlight = &pflash_led_dev->floodlight; + struct flash_led_dev *projection = &pflash_led_dev->projection; + + ret = of_property_read_string(np, "flash_led_name", &pflash_led_dev->flash_led_name); + if (ret < 0) { + pr_err("%s:property flash_led_name not defined for %s\n", __func__, pdev->name); + return ret; + } + + // the flash led touch pin used touch the io interrupt + pflash_led_dev->touch_pin = of_get_named_gpio(np, "flash_led_touch_pin", 0); + if (pflash_led_dev->touch_pin >= 0) { + ret = devm_gpio_request(&pdev->dev, pflash_led_dev->touch_pin, + "flash_led_touch_pin"); + if (ret < 0) { + pr_err("%s:flash_led_touch request failed\n", __func__); + } + } else { + pr_err("flash_led_touch not defined for %s\n", pflash_led_dev->flash_led_name); + } + + pflash_led_dev->floodlight_en_pin = of_get_named_gpio(np, "floodlight_en_pin", 0); + if (pflash_led_dev->floodlight_en_pin >= 0) { + ret = devm_gpio_request(&pdev->dev, pflash_led_dev->floodlight_en_pin, + "floodlight_en_pin"); + if (ret < 0) { + pr_err("%s:floodlight_en_pin request failed\n", __func__); + } + } else { + pflash_led_dev->floodlight_en_pin = -1; + pr_err("floodlight_en_pin not defined for %s\n", pflash_led_dev->flash_led_name); + } + + pflash_led_dev->projection_en_pin = of_get_named_gpio(np, "projection_en_pin", 0); + if (pflash_led_dev->projection_en_pin >= 0) { + ret = devm_gpio_request(&pdev->dev, pflash_led_dev->projection_en_pin, + "projection_en_pin"); + if (ret < 0) { + pr_err("%s:projection_en_pin request failed\n", __func__); + } + } else { + pflash_led_dev->projection_en_pin = -1; + pr_err("projection_en_pin not defined for %s\n", pflash_led_dev->flash_led_name); + } + + floodlight->regulators.num = of_property_count_strings(np, "floodlight_regulators"); + if (floodlight->regulators.num <= 0) { + pr_info("%s:property floodlight_regulators not defined for %s\n", __func__, pdev->name); + } else { + pr_info("%s num_of_regulators %d\n", __func__, floodlight->regulators.num); + ret = of_property_read_string_array(np, "floodlight_regulators", + floodlight->regulators.name, floodlight->regulators.num); + if (ret != floodlight->regulators.num) { + pr_err("%s:fail to read property floodlight_regulators\n", __func__); + return -1; + }; + + regulator_num = floodlight->regulators.num; + while (regulator_num) { + floodlight->regulators.supply[regulator_num - 1] = devm_regulator_get(&pdev->dev, + floodlight->regulators.name[regulator_num - 1]); + if (IS_ERR(floodlight->regulators.supply[regulator_num - 1])) { + pr_err("%s:fail to devm_regulator_get %s\n", __func__, floodlight->regulators.name[regulator_num - 1]); + return -1; + } + regulator_num--; + } + } + + projection->regulators.num = of_property_count_strings(np, "projection_regulators"); + if (projection->regulators.num <= 0) { + pr_info("%s:property projection_regulators not defined for %s\n", __func__, pdev->name); + } else { + pr_info("%s num_of_regulators %d\n", __func__, projection->regulators.num); + ret = of_property_read_string_array(np, "projection_regulators", + projection->regulators.name, projection->regulators.num); + if (ret != projection->regulators.num) { + pr_err("%s:fail to read property projection_regulators\n", __func__); + return -1; + }; + + regulator_num = projection->regulators.num; + while (regulator_num) { + projection->regulators.supply[regulator_num - 1] = devm_regulator_get(&pdev->dev, + projection->regulators.name[regulator_num - 1]); + if (IS_ERR(projection->regulators.supply[regulator_num - 1])) { + pr_err("%s:fail to devm_regulator_get %s\n", __func__, projection->regulators.name[regulator_num - 1]); + return -1; + } + regulator_num--; + } + } + + ret = of_property_read_u8(np, "floodlight_i2c_bus", + &floodlight->i2c_bus); + if (ret != 0) { + pr_err("fail to read property floodlight_i2c_bus\n"); + floodlight->i2c_bus = UNDEFINED_IN_DTS; + } + + ret = of_property_read_u8(np, "projection_i2c_bus", + &projection->i2c_bus); + if (ret != 0) { + pr_err("fail to read property projection_i2c_bus\n"); + projection->i2c_bus = UNDEFINED_IN_DTS; + } + + pflash_led_dev->projection_adc = iio_channel_get(&pdev->dev, "projection_adc"); + if (IS_ERR(pflash_led_dev->projection_adc)) { + pr_err("not define projection_adc adc\n"); + } + + pflash_led_dev->floodlight_adc = iio_channel_get(&pdev->dev, "floodlight_adc"); + if (IS_ERR(pflash_led_dev->floodlight_adc)) { + pr_err("not define iio floodlight_adc\n"); + } + + return 0; +} + +static volatile uint64_t falling_time_us[2] = {0}; + +uint64_t touch_pin_int_num(struct flash_led_ctrl *pflash_led_dev) +{ + return pflash_led_dev->frame_mark->frame_irq_cnt; +} + +void frame_irq_cnt_clear(struct flash_led_ctrl *pflash_led_dev) +{ + pflash_led_dev->frame_mark->frame_irq_cnt = 0; +} + +uint64_t touch_pin_high_time_us(void) +{ + return 0; +} + +uint64_t touch_pin_falling_int(void) +{ + return 0; +} + +uint64_t touch_pin_rising_int(void) +{ + return 0; +} + +uint64_t touch_pin_preiod_time_us(void) +{ + + if (falling_time_us[0] < falling_time_us[1]) { + return falling_time_us[1] - falling_time_us[0]; + } + + return falling_time_us[0] - falling_time_us[1]; +} + +uint64_t get_us_time(void) +{ + struct timespec64 ts; + static uint64_t us = 0; + ktime_get_real_ts64(&ts); + us = timespec64_to_ns(&ts) / 1000UL; + return us; +} + +static void flash_led_interrupt_func(struct work_struct *work) +{ + struct flash_led_ctrl *pflash_led_dev = container_of(work, struct flash_led_ctrl, flash_led_work); + struct flash_led_dev *floodlight = &pflash_led_dev->floodlight; + struct flash_led_dev *projection = &pflash_led_dev->projection; + frame_mark_t *frame_mark = pflash_led_dev->frame_mark; + + frame_mark->frame_irq_cnt += 1; + falling_time_us[frame_mark->frame_irq_cnt % 2] = get_us_time(); + frame_mark->frame_time_us = falling_time_us[frame_mark->frame_irq_cnt % 2]; + + if (!pflash_led_dev->enable) { + if (projection->flash_led_func != NULL) { + projection->flash_led_func->disable_channel(projection, 3); + } + + if (floodlight->flash_led_func != NULL) { + floodlight->flash_led_func->disable_channel(floodlight, 3); + } + return; + } + + if ((frame_mark->frame_irq_cnt % 2) == 0) { + if ((pflash_led_dev->enable & FLOODLIGHT_EN) && floodlight->flash_led_func != NULL) { + floodlight->flash_led_func->enable_channel(floodlight, 3); + } + + if ((pflash_led_dev->enable & PROJECTION_EN) && projection->flash_led_func != NULL) { + projection->flash_led_func->disable_channel(projection, 3); + } + if (!IS_ERR(pflash_led_dev->floodlight_adc)) { + iio_read_channel_processed(pflash_led_dev->floodlight_adc, + &frame_mark->floodlight_temperature); + frame_mark->floodlight_temperature = get_ntc_temperature(frame_mark->floodlight_temperature); + } + + } else { + if ((pflash_led_dev->enable & PROJECTION_EN) && projection->flash_led_func != NULL) { + projection->flash_led_func->enable_channel(projection, 3); + } + + if ((pflash_led_dev->enable & FLOODLIGHT_EN) && floodlight->flash_led_func != NULL) { + floodlight->flash_led_func->disable_channel(floodlight, 3); + } + + if (!IS_ERR(pflash_led_dev->projection_adc)) { + iio_read_channel_processed(pflash_led_dev->projection_adc, + &frame_mark->projection_temperature); + frame_mark->projection_temperature = get_ntc_temperature(frame_mark->projection_temperature); + } + } +} + +static irqreturn_t touch_pin_isr(int irq, void *dev) +{ + struct flash_led_ctrl *pflash_led_dev = dev; + + schedule_work(&pflash_led_dev->flash_led_work); + + return IRQ_HANDLED; +} + +static int flash_pin_init(struct flash_led_ctrl *dev) +{ + int irq = gpio_to_irq(dev->touch_pin); + gpio_request(dev->touch_pin, "flash led touch pin"); + + INIT_WORK(&dev->flash_led_work, flash_led_interrupt_func); + + request_irq(irq, touch_pin_isr, IRQF_TRIGGER_FALLING, + "flash led touch pin", + dev); + + if (dev->floodlight_en_pin != -1) { + gpio_request(dev->floodlight_en_pin, "floodlight enable pin"); + if (gpio_is_valid(dev->floodlight_en_pin)) { + gpio_direction_output(dev->floodlight_en_pin, 1); + } + } + + if (dev->projection_en_pin != -1) { + gpio_request(dev->projection_en_pin, "projection enable pin"); + if (gpio_is_valid(dev->projection_en_pin)) { + gpio_direction_output(dev->projection_en_pin, 1); + } + } + + return 0; +} + +static int touch_pin_uinit(struct flash_led_ctrl *dev) +{ + int irq = gpio_to_irq(dev->touch_pin); + dev->enable = 0; + free_irq(irq, dev); + cancel_work_sync(&dev->flash_led_work); + gpio_free(dev->touch_pin); + return 0; +} + +static int flash_led_probe(struct platform_device *pdev) +{ + int ret = 0; + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + struct device_node *np = pdev->dev.of_node; + + pr_info("enter %s\n", __func__); + + if (pdev->id >= FLASH_LED_MAXCNT) { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdev->id = of_alias_get_id(np, "flash_led"); + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct flash_led_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) { + pr_err("%s:alloc struct flash_led_driver_dev error\n", __func__); + return -ENOMEM; + } + + memset(pdriver_dev,0,sizeof(struct flash_led_driver_dev )); + pr_info("%s:flash_led[%d]: pdriver_dev =0x%px\n", __func__, pdev->id, pdriver_dev); + + pflash_led_dev = devm_kzalloc(&pdev->dev,sizeof(*pflash_led_dev), GFP_KERNEL); + if (pflash_led_dev == NULL) { + pr_err("%s:alloc struct flash_led_dev error\n", __func__); + return -ENOMEM; + } + + memset(pflash_led_dev,0,sizeof(*pflash_led_dev)); + pr_info("%s:flash_led[%d]: pflash_led_dev =0x%px\n", __func__,pdev->id,pflash_led_dev); + pflash_led_dev->device_idx = pdev->id; + + pdriver_dev->private = pflash_led_dev; + mutex_init(&pdriver_dev->vvmutex); + + frame_mark_t *frame_mark; + frame_mark = dma_alloc_coherent(&pdev->dev, sizeof(frame_mark_t), &pflash_led_dev->frame_mark_info_addr, GFP_KERNEL); + if (frame_mark == NULL ) { + pr_err("dma_alloc_coherent error\n"); + return -1; + } + memset(frame_mark, 0, sizeof(frame_mark_t)); + pflash_led_dev->frame_mark = frame_mark; + + platform_set_drvdata(pdev, pdriver_dev); + + ret = flash_led_of_parse(pdev); + if (ret < 0) { + pr_err("%s:flash_led_of_parse error\n", __func__); + return ret; + } + + ret = flash_pin_init(pflash_led_dev); + if (ret != 0) { + pr_err("%s:flash_pin_init error\n", __func__); + } + + ret = flash_led_init(pflash_led_dev); + if (ret != 0) { + pr_err("%s:vvnative_flash_led_init error\n", __func__); + } + + if (devise_register_index == 0) { + if (flash_led_major == 0) { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, FLASH_LED_MAXCNT, FLASH_LED_NAME); + if (ret != 0) { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + flash_led_major = MAJOR(pdriver_dev->devt); + flash_led_minor = MINOR(pdriver_dev->devt); + } else { + pdriver_dev->devt = MKDEV(flash_led_major, flash_led_minor); + ret = register_chrdev_region(pdriver_dev->devt, FLASH_LED_MAXCNT, FLASH_LED_NAME); + if (ret) { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + flash_led_class = class_create(THIS_MODULE, FLASH_LED_NAME); + if (IS_ERR(flash_led_class)) { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + + pdriver_dev->devt = MKDEV(flash_led_major, flash_led_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &flash_led_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if (ret) { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + + pdriver_dev->class = flash_led_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", FLASH_LED_NAME, pdev->id); + + extern int flash_led_create_capabilities_sysfs(struct platform_device *pdev); + flash_led_create_capabilities_sysfs(pdev); + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int flash_led_remove(struct platform_device *pdev) +{ + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + if (pdriver_dev == NULL) { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + pflash_led_dev = pdriver_dev->private; + flash_led_deinit(pflash_led_dev); + touch_pin_uinit(pflash_led_dev); + + dma_free_coherent(&pdev->dev, sizeof(*pflash_led_dev->frame_mark), pflash_led_dev->frame_mark, pflash_led_dev->frame_mark_info_addr); + + if (!IS_ERR(pflash_led_dev->projection_adc)) { + iio_channel_release(pflash_led_dev->projection_adc); + } + + if (!IS_ERR(pflash_led_dev->floodlight_adc)) { + iio_channel_release(pflash_led_dev->floodlight_adc); + } + + extern int flash_led_remove_capabilities_sysfs(struct platform_device *pdev); + flash_led_remove_capabilities_sysfs(pdev); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, FLASH_LED_MAXCNT); + if (devise_register_index == 0) { + class_destroy(pdriver_dev->class); + } + + devm_kfree(&pdev->dev, pdriver_dev); + devm_kfree(&pdev->dev, pflash_led_dev); + + pr_info("exit %s\n", __func__); + + return 0; +} + +static const struct of_device_id flash_led_of_match[] = { + {.compatible = "thead,light-vvcam-flash_led"}, +}; + +static struct platform_driver flash_led_driver = { + .probe = flash_led_probe, + .remove = flash_led_remove, + .driver = { + .name = FLASH_LED_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(flash_led_of_match), + } +}; + +/* +static void flash_led_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} +*/ + +static int __init flash_led_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&flash_led_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit flash_led_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&flash_led_driver); +} + +module_init(flash_led_init_module); +module_exit(flash_led_exit_module); + +MODULE_DESCRIPTION("FLASH_LED"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/flash_led/flash_led_driver.h b/vvcam/native/flash_led/flash_led_driver.h new file mode 100644 index 0000000..c5010cd --- /dev/null +++ b/vvcam/native/flash_led/flash_led_driver.h @@ -0,0 +1,86 @@ +#ifndef _FLASH_LED_DRIVER_H_ +#define _FLASH_LED_DRIVER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "flash_led_ioctl.h" + +#define UNDEFINED_IN_DTS 0xFF +#define FLASH_LED_MAX_REGULATORS 10 + +struct flash_led_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + void *private; +}; + +struct flash_led_regulators { + struct regulator *supply[FLASH_LED_MAX_REGULATORS]; + const char *name[FLASH_LED_MAX_REGULATORS]; + int num; +}; + +struct flash_led_function_s { + uint8_t flash_led_name[100]; + uint32_t reserve_id; + uint32_t time_out_ms; + int (*init) (void *cxt); + int (*uninit) (void *cxt); + int (*enable_channel) (void *cxt, int channel); + int (*disable_channel) (void *cxt, int channel); + int (*set_mode) (void *cxt, flash_led_mode_t mode); + int (*set_flash_brightness) (void *cxt, int channel, uint32_t val); + int (*set_torch_brightness) (void *cxt, int channel, uint32_t val); +}; + +struct flash_led_dev { + struct flash_led_function_s *flash_led_func; + uint8_t i2c_bus; + void *i2c_client; + struct flash_led_sccb_cfg_s flash_led_sccb_cfg; + struct flash_led_regulators regulators; +}; + +struct flash_led_ctrl { + struct work_struct flash_led_work; + const char *flash_led_name; + long reg_size; + void __iomem *base; + int32_t device_idx; + int touch_pin; + int floodlight_en_pin; + int projection_en_pin; + int enable; + struct iio_channel *floodlight_adc; + struct iio_channel *projection_adc; + struct flash_led_dev floodlight; + struct flash_led_dev projection; + dma_addr_t frame_mark_info_addr; + volatile frame_mark_t *frame_mark; +}; + +int flash_led_init(struct flash_led_ctrl *dev); +int flash_led_deinit(struct flash_led_ctrl *dev); +long flash_led_priv_ioctl(struct flash_led_ctrl *dev, unsigned int cmd, void __user *args); +int32_t flash_led_i2c_write(struct flash_led_dev *dev, uint32_t address, uint32_t data); +int32_t flash_led_i2c_read(struct flash_led_dev *dev, uint32_t address, uint32_t *pdata); + +#endif diff --git a/vvcam/native/flash_led/flash_led_ioctl.c b/vvcam/native/flash_led/flash_led_ioctl.c new file mode 100755 index 0000000..bfa9386 --- /dev/null +++ b/vvcam/native/flash_led/flash_led_ioctl.c @@ -0,0 +1,470 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "flash_led_ioctl.h" +#include "flash_led_driver.h" + +void frame_irq_cnt_clear(struct flash_led_ctrl *pflash_led_dev); +extern struct flash_led_function_s aw36515_function; +extern struct flash_led_function_s aw36413_function; + +static struct flash_led_function_s *floodlight_func = &aw36413_function; +static struct flash_led_function_s *projection_func = &aw36515_function; + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +/* +static int32_t flash_led_sccb_config(struct flash_led_dev *dev, struct flash_led_sccb_cfg_s *sccb_config) +{ + dev->flash_led_sccb_cfg.slave_addr = sccb_config->slave_addr; + dev->flash_led_sccb_cfg.addr_byte = sccb_config->addr_byte; + dev->flash_led_sccb_cfg.data_byte = sccb_config->data_byte; + return 0; +} +*/ + +static int i2c_write_reg(struct i2c_client *client,unsigned int slave_address, + unsigned int reg_addr,unsigned int reg_length, + unsigned int data, unsigned int data_length) +{ + int ret; + unsigned int i; + struct i2c_msg msgs[2]; + unsigned char sendbuf[16]; + unsigned int send_len = 0; + + if (client == NULL) + return -1; + memset(msgs,0,sizeof(msgs)); + memset(sendbuf,0,sizeof(sendbuf)); + + for (i=0; i < reg_length; i++) + { + sendbuf[send_len++] = (reg_addr >> ((reg_length -1 - i)<<3)) & 0xff; + } + for (i=0; i < data_length; i++) + { + sendbuf[send_len++] = (data >> ((data_length -1 - i)<<3)) & 0xff; + } + + msgs[0].addr = slave_address; + msgs[0].flags = client->flags & I2C_M_TEN; + msgs[0].len = send_len; + msgs[0].buf = sendbuf; + + ret = i2c_transfer(client->adapter, msgs, 1); + if (ret != 1) + { + return -1; + } + + return 0; +} + +static int i2c_read_reg(struct i2c_client *client,unsigned int slave_address, + unsigned int reg_addr,unsigned int reg_length, + unsigned char * pdata, unsigned int data_length) +{ + int ret; + unsigned int i; + struct i2c_msg msgs[2]; + unsigned char sendbuf[16]; + unsigned int send_len = 0; + unsigned char readbuf[16]; + + if (client == NULL || pdata == NULL) + return -1; + + memset(msgs,0,sizeof(msgs)); + memset(sendbuf,0,sizeof(sendbuf)); + memset(readbuf,0,sizeof(readbuf)); + + for (i=0; i < reg_length; i++) + { + sendbuf[send_len++] = (reg_addr >> ((reg_length -1 - i)<<3)) & 0xff; + } + + msgs[0].addr = slave_address; + msgs[0].flags = client->flags & I2C_M_TEN; + msgs[0].len = send_len; + msgs[0].buf = sendbuf; + + msgs[1].addr = slave_address; + msgs[1].flags = client->flags & I2C_M_TEN; + msgs[1].flags |= I2C_M_RD; + msgs[1].len = data_length; + msgs[1].buf = readbuf; + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret != 2) { + return -1; + } + + for (i = 0; i < data_length; i++) { + pdata[i] = readbuf[data_length -1 - i]; + } + + return 0; +} + +int32_t flash_led_i2c_write(struct flash_led_dev *dev, uint32_t address, uint32_t data) +{ + int32_t ret = 0; + + if((NULL == dev)) + { + return -1; + } + + ret = i2c_write_reg(dev->i2c_client,dev->flash_led_sccb_cfg.slave_addr, + address,dev->flash_led_sccb_cfg.addr_byte, + data,dev->flash_led_sccb_cfg.data_byte); + + return ret; +} + +int32_t flash_led_i2c_read(struct flash_led_dev *dev, uint32_t address, uint32_t *pdata) +{ + int32_t ret = 0; + + if((NULL == dev)) + { + return -1; + } + + ret = i2c_read_reg(dev->i2c_client,dev->flash_led_sccb_cfg.slave_addr, + address, dev->flash_led_sccb_cfg.addr_byte, + (unsigned char *)pdata, dev->flash_led_sccb_cfg.data_byte); + + return ret; +} + +long flash_led_priv_ioctl(struct flash_led_ctrl *dev, unsigned int cmd, void __user *args) +{ + int ret = -1; + flash_bright_cfg_t bright; + flash_led_reg_t reg; + flash_ch_t ch; + flash_mode_t mode; + flash_led_enable_mask_t flash_led; + + struct flash_led_dev *floodlight = &dev->floodlight; + struct flash_led_dev *projection = &dev->projection; + + if (!dev) { + pr_err("-->%s: null point!\n", __func__); + return ret; + } + + switch (cmd) { + case FLASH_LED_IOCTL_ENABLE_CH: + check_retval(copy_from_user(&ch, args, sizeof(ch))); + if (ch.type == FLOODLIGHT && floodlight->flash_led_func != NULL) { + ret = floodlight->flash_led_func->enable_channel(floodlight, ch.channel); + } else if (projection->flash_led_func != NULL) { + ret = projection->flash_led_func->enable_channel(projection, ch.channel); + } + break; + case FLASH_LED_IOCTL_DISABLE_CH: + check_retval(copy_from_user(&ch, args, sizeof(ch))); + if (ch.type == FLOODLIGHT && floodlight->flash_led_func != NULL) { + ret = floodlight->flash_led_func->disable_channel(floodlight, ch.channel); + } else if (projection->flash_led_func != NULL) { + ret = projection->flash_led_func->disable_channel(projection, ch.channel); + } + break; + case FLASH_LED_IOCTL_SET_MODE: + check_retval(copy_from_user(&mode, args, sizeof(mode))); + if (mode.type == FLOODLIGHT && floodlight->flash_led_func != NULL) { + ret = floodlight->flash_led_func->set_mode(floodlight, mode.mode); + } else if (projection->flash_led_func != NULL) { + ret = projection->flash_led_func->set_mode(projection, mode.mode); + } + break; + case FLASH_LED_IOCTL_SET_FLASH_BRIGHT: + check_retval(copy_from_user(&bright, args, sizeof(bright))); + if (bright.type == FLOODLIGHT && floodlight->flash_led_func != NULL) { + ret = floodlight->flash_led_func->set_flash_brightness(floodlight, bright.channel, bright.value); + } else if (projection->flash_led_func != NULL) { + ret = projection->flash_led_func->set_flash_brightness(projection, bright.channel, bright.value); + } + break; + case FLASH_LED_IOCTL_SET_TORCH_BRIGHT: + check_retval(copy_from_user(&bright, args, sizeof(bright))); + if (bright.type == FLOODLIGHT && floodlight->flash_led_func != NULL) { + ret = floodlight->flash_led_func->set_torch_brightness(floodlight, bright.channel, bright.value); + } else if (projection->flash_led_func != NULL) { + ret = projection->flash_led_func->set_torch_brightness(projection, bright.channel, bright.value); + } + break; + case FLASH_LED_IOCTL_WRITE_REG: + check_retval(copy_from_user(®, args, sizeof(reg))); + if (reg.type == FLOODLIGHT && floodlight->i2c_bus != UNDEFINED_IN_DTS) { + ret = flash_led_i2c_write(floodlight, reg.offset, reg.value); + } else if(projection->i2c_bus != UNDEFINED_IN_DTS) { + ret = flash_led_i2c_write(projection, reg.offset, reg.value); + } + break; + case FLASH_LED_IOCTL_READ_REG: + check_retval(copy_from_user(®, args, sizeof(reg))); + if (reg.type == FLOODLIGHT && floodlight->i2c_bus != UNDEFINED_IN_DTS) { + ret = flash_led_i2c_read(floodlight, reg.offset, ®.value); + } else if(projection->i2c_bus != UNDEFINED_IN_DTS) { + ret = flash_led_i2c_read(projection, reg.offset, ®.value); + } + check_retval(copy_to_user(args, ®, sizeof(reg))); + break; + case FLASH_LED_IOCTL_ENABLE: + check_retval(copy_from_user(&flash_led, args, sizeof(flash_led))); + frame_irq_cnt_clear(dev); + dev->enable |= flash_led; + ret = 0; + break; + case FLASH_LED_IOCTL_DISABLE: + check_retval(copy_from_user(&flash_led, args, sizeof(flash_led))); + dev->enable &= ~flash_led; + if (flash_led & FLOODLIGHT_EN && floodlight->flash_led_func != NULL) { + floodlight->flash_led_func->disable_channel(floodlight, 3); + } + + if (flash_led & PROJECTION_EN && projection->flash_led_func != NULL) { + projection->flash_led_func->disable_channel(projection, 3); + } + ret = 0; + break; + case FLASH_LED_IOCTL_GET_FRAME_MASK_INFO_ADDR: { + unsigned long addr; + addr = dev->frame_mark_info_addr; + pr_info("FLASH_LED_IOCTL_GET_FRAME_MASK_INFO_ADDR 0x%lx\n", addr); + check_retval(copy_to_user(args, &addr, sizeof(addr))); + ret = 0; + } + break; + default: + printk("%s, %d, flash led cmd error, cmd %u\n", __func__, __LINE__, cmd); + return -ENOTTY; + } + + return ret; +} + +static int register_i2c_client(struct flash_led_dev *dev) +{ + struct i2c_adapter *adap; + struct i2c_board_info flash_led_i2c_info = { + .type = "flash_led", + .addr = dev->flash_led_sccb_cfg.slave_addr, + }; + + if (dev->i2c_bus == UNDEFINED_IN_DTS) { + return 0; + } + + flash_led_i2c_info.addr &= 0xff; + + adap = i2c_get_adapter(dev->i2c_bus); + if (adap == NULL) + { + pr_err("[%s]:i2c_get_adapter i2c_bus %d failed\n",__func__,dev->i2c_bus); + return -1; + } + + strscpy(flash_led_i2c_info.type, dev->flash_led_func->flash_led_name, I2C_NAME_SIZE); + + dev->i2c_client = i2c_new_client_device(adap, &flash_led_i2c_info); + + i2c_put_adapter(adap); + + if (dev->i2c_client == NULL) { + pr_err("[%s]:i2c_new_client_device i2c_bus %d failed\n",__func__,dev->i2c_bus); + return -1; + } + return 0; +} + +static void unregister_i2c_client(struct flash_led_dev *dev) +{ + i2c_unregister_device(dev->i2c_client); +} + +int flash_led_init(struct flash_led_ctrl *dev) +{ + int ret = 0; + struct flash_led_dev *floodlight = &dev->floodlight; + struct flash_led_dev *projection = &dev->projection; + + floodlight->flash_led_sccb_cfg.slave_addr = dev->device_idx+1; + projection->flash_led_sccb_cfg.slave_addr = dev->device_idx+2; + + if (floodlight->i2c_bus == UNDEFINED_IN_DTS && projection->i2c_bus == UNDEFINED_IN_DTS) { + pr_err("%s, %d, flash_led i2c bus invalid\n",__func__, __LINE__); + return -1; + } + + floodlight->flash_led_func = NULL; + projection->flash_led_func = NULL; + + if (floodlight->i2c_bus != UNDEFINED_IN_DTS) { + floodlight->flash_led_func = floodlight_func; + } + + if (projection->i2c_bus != UNDEFINED_IN_DTS) { + projection->flash_led_func = projection_func; + } + + if (floodlight->i2c_bus == projection->i2c_bus) { + pr_info("%s, %d, floodlight->i2c_bus = %d projection->i2c_bus %d\n", __func__, __LINE__, floodlight->i2c_bus, projection->i2c_bus); + ret = register_i2c_client(floodlight); + if (ret != 0) { + pr_err("[%s]: register_i2c_client flash_led_idx = %d failed\n",__func__, dev->device_idx); + return -1; + } + + projection->i2c_client = floodlight->i2c_client; + } else { + if (floodlight->i2c_bus != UNDEFINED_IN_DTS) { + pr_info("%s, %d, floodlight->i2c_bus = %d \n", __func__, __LINE__, floodlight->i2c_bus); + ret = register_i2c_client(floodlight); + if (ret != 0) { + pr_err("[%s]: floodlight register_i2c_client flash_led_idx = %d failed\n",__func__, dev->device_idx); + return -1; + } + } + + if (projection->i2c_bus != UNDEFINED_IN_DTS) { + pr_info("%s, %d, projection->i2c_bus %d\n", __func__, __LINE__, projection->i2c_bus); + ret = register_i2c_client(projection); + if (ret != 0) { + pr_err("[%s]: projection register_i2c_client flash_led_idx = %d failed\n",__func__, dev->device_idx); + return -1; + } + } + } + + if (floodlight->flash_led_func != NULL) { + ret = floodlight->flash_led_func->init(floodlight); + if (ret != 0) { + pr_err("%s, %d, floodlight init error\n", __func__, __LINE__); + return ret; + } + } + + if (projection->flash_led_func != NULL) { + ret = projection->flash_led_func->init(projection); + if (ret != 0) { + pr_err("%s, %d, projection init error\n", __func__, __LINE__); + return ret; + } + } + + printk("%s,%d, exit\n", __func__, __LINE__); + + return ret; +} + +int flash_led_deinit(struct flash_led_ctrl *dev) +{ + int ret = 0, err = 0; + struct flash_led_dev *floodlight = &dev->floodlight; + struct flash_led_dev *projection = &dev->projection; + + if (floodlight->flash_led_func != NULL) { + ret = floodlight->flash_led_func->uninit(floodlight); + if (ret != 0) { + err |= ret; + } + } + + if (projection->flash_led_func != NULL) { + ret = projection->flash_led_func->uninit(projection); + if (ret != 0) { + err |= ret; + } + } + + if (floodlight->i2c_bus == projection->i2c_bus) { + unregister_i2c_client(floodlight); + } else { + if (floodlight->i2c_bus != UNDEFINED_IN_DTS) { + unregister_i2c_client(floodlight); + } + + if (projection->i2c_bus != UNDEFINED_IN_DTS) { + unregister_i2c_client(projection); + } + } + + return err; +} + diff --git a/vvcam/native/flash_led/flash_led_ioctl.h b/vvcam/native/flash_led/flash_led_ioctl.h new file mode 100755 index 0000000..0fa8777 --- /dev/null +++ b/vvcam/native/flash_led/flash_led_ioctl.h @@ -0,0 +1,75 @@ +#ifndef _FLASH_LED_IOCTL_H_ +#define _FLASH_LED_IOCTL_H_ + +#include + +#define FLASH_LED_IOCTL_MAGIC 'f' + +#define FLASH_LED_IOCTL_ENABLE_CH _IOWR(FLASH_LED_IOCTL_MAGIC, 1, int) +#define FLASH_LED_IOCTL_DISABLE_CH _IOWR(FLASH_LED_IOCTL_MAGIC, 2, int) +#define FLASH_LED_IOCTL_SET_MODE _IOWR(FLASH_LED_IOCTL_MAGIC, 3, int) +#define FLASH_LED_IOCTL_SET_FLASH_BRIGHT _IOWR(FLASH_LED_IOCTL_MAGIC, 4, int) +#define FLASH_LED_IOCTL_SET_TORCH_BRIGHT _IOWR(FLASH_LED_IOCTL_MAGIC, 5, int) +#define FLASH_LED_IOCTL_WRITE_REG _IOWR(FLASH_LED_IOCTL_MAGIC, 6, int) +#define FLASH_LED_IOCTL_READ_REG _IOWR(FLASH_LED_IOCTL_MAGIC, 7, int) +#define FLASH_LED_IOCTL_ENABLE _IOWR(FLASH_LED_IOCTL_MAGIC, 8, int) +#define FLASH_LED_IOCTL_DISABLE _IOWR(FLASH_LED_IOCTL_MAGIC, 9, int) +#define FLASH_LED_IOCTL_GET_FRAME_MASK_INFO_ADDR _IOWR(FLASH_LED_IOCTL_MAGIC, 10, int) + +struct flash_led_sccb_cfg_s { + unsigned char slave_addr; + unsigned char addr_byte; + unsigned char data_byte; +}; + +typedef enum { + FLASH_LED_STANDBY, + FLASH_LED_EXT_TORCH, + FLASH_LED_EXT_FLASH, + FLASH_LED_INT_TORCH, + FLASH_LED_INT_FLASH, + FLASH_LED_IR_STANDBY, + FLASH_LED_IR_ENABLE, +} flash_led_mode_t; + +typedef enum { + FLOODLIGHT, + PROJECTION, +} flash_led_type_t; + +typedef enum { + FLOODLIGHT_EN = 1, + PROJECTION_EN = 2, + FLOODLIGHT_PROJECTION_EN = 3, +} flash_led_enable_mask_t; + +typedef struct { + flash_led_type_t type; + unsigned int offset; + unsigned int value; +} flash_led_reg_t; + +typedef struct { + flash_led_type_t type; + int channel; + unsigned int value; +} flash_bright_cfg_t; + +typedef struct { + flash_led_type_t type; + int channel; +} flash_ch_t; + +typedef struct { + flash_led_type_t type; + flash_led_mode_t mode; +} flash_mode_t; + +typedef struct { + volatile uint64_t frame_irq_cnt; + volatile uint64_t frame_time_us; + int floodlight_temperature; + int projection_temperature; +} frame_mark_t; + +#endif diff --git a/vvcam/native/flash_led/flash_led_sysfs.c b/vvcam/native/flash_led/flash_led_sysfs.c new file mode 100755 index 0000000..18900e4 --- /dev/null +++ b/vvcam/native/flash_led/flash_led_sysfs.c @@ -0,0 +1,415 @@ + +#include "flash_led_driver.h" +#include "flash_led_ioctl.h" + +extern uint64_t touch_pin_int_num(struct flash_led_ctrl *pflash_led_dev); +extern uint64_t touch_pin_high_time_us(void); +extern uint64_t touch_pin_preiod_time_us(void); +extern uint64_t touch_pin_falling_int(void); +extern uint64_t touch_pin_rising_int(void); + +static ssize_t flash_led_falling_int_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + char buffer[100]; + printk("<0>""flash_led falling interrupt num: %d\n", touch_pin_falling_int()); + snprintf(buffer, sizeof(buffer), "falling num :%llu\n", touch_pin_falling_int()); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t flash_led_rising_int_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + char buffer[100]; + + printk("<0>""flash_led rising interrupt num: %d\n", touch_pin_rising_int()); + snprintf(buffer, sizeof(buffer), "rising interupt num :%llu\n", touch_pin_rising_int()); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t flash_led_info_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + struct flash_led_dev *floodlight; + struct flash_led_dev *projection; + char buffer[200]; + char name1[30] = {0}; + char name2[30] = {0}; + + pdriver_dev = platform_get_drvdata(pdev); + pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + + floodlight = &pflash_led_dev->floodlight; + projection = &pflash_led_dev->projection; + + if (floodlight->flash_led_func != NULL) { + strcpy(name1, floodlight->flash_led_func->flash_led_name); + } + + if (projection->flash_led_func != NULL) { + strcpy(name2, projection->flash_led_func->flash_led_name); + } + + snprintf(buffer, sizeof(buffer), "f_led_%s i2c is :%d, p_led_%s i2c is %d\n", + name1, + floodlight->i2c_bus, + name2, + projection->i2c_bus); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t flash_led_int_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + pdriver_dev = platform_get_drvdata(pdev); + pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + + char buffer[100]; + + printk("<0>""flash_led interrupt num: %d\n", touch_pin_int_num(pflash_led_dev)); + snprintf(buffer, sizeof(buffer), "interupt num :%llu\n", touch_pin_int_num(pflash_led_dev)); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t flash_led_pin_high_time_us_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + char buffer[100]; + snprintf(buffer, sizeof(buffer), "h time us is :%llu\n", touch_pin_high_time_us()); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t flash_led_pin_period_us_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + char buffer[100]; + snprintf(buffer, sizeof(buffer), "preiod us is :%llu\n", touch_pin_preiod_time_us()); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +int32_t flash_led_i2c_write(struct flash_led_dev *dev, uint32_t address, uint32_t data); +int32_t flash_led_i2c_read(struct flash_led_dev *dev, uint32_t address, uint32_t *pdata); + +static ssize_t floodlight_led_reg_read_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int ret = 0; + struct platform_device *pdev = to_platform_device(dev); + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + struct flash_led_dev *floodlight; + unsigned long addr; + uint32_t val; + + pdriver_dev = platform_get_drvdata(pdev); + pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + floodlight = &pflash_led_dev->floodlight; + + if(floodlight->i2c_bus == UNDEFINED_IN_DTS) { + return count; + } + + ret = kstrtoul(buf, 16, &addr); + if (ret < 0) { + return ret; + } + + ret = flash_led_i2c_read(floodlight, addr, &val); + if (ret < 0) { + return ret; + } + printk("read reg[0x%x]: 0x%x\n", addr, val); + + return count; +} + +static ssize_t floodlight_led_reg_write_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int ret = 0; + struct platform_device *pdev = to_platform_device(dev); + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + struct flash_led_dev *floodlight; + char buffer[100]; + unsigned long addr; + uint32_t val; + + pdriver_dev = platform_get_drvdata(pdev); + pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + floodlight = &pflash_led_dev->floodlight; + + if(floodlight->i2c_bus == UNDEFINED_IN_DTS) { + return count; + } + + ret = kstrtoul(buf, 16, &addr); + if (ret < 0) { + return ret; + } + + val = addr & 0xff; + addr = addr >> 8; + + ret = flash_led_i2c_write(floodlight, addr, val); + if (ret < 0) { + return ret; + } + + printk("write reg[0x%x] 0x%x\n", addr, val); + + return count; +} + +static ssize_t projection_led_reg_read_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int ret = 0; + struct platform_device *pdev = to_platform_device(dev); + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + struct flash_led_dev *projection; + unsigned long addr; + uint32_t val; + + pdriver_dev = platform_get_drvdata(pdev); + pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + projection = &pflash_led_dev->projection; + + if(projection->i2c_bus == UNDEFINED_IN_DTS) { + return count; + } + + ret = kstrtoul(buf, 16, &addr); + if (ret < 0) { + return ret; + } + + ret = flash_led_i2c_read(projection, addr, &val); + if (ret < 0) { + return ret; + } + printk("read reg[0x%x]: 0x%x\n", addr, val); + + return count; +} + +static ssize_t projection_led_reg_write_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int ret = 0; + struct platform_device *pdev = to_platform_device(dev); + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + struct flash_led_dev *projection; + char buffer[100]; + unsigned long addr; + uint32_t val; + + pdriver_dev = platform_get_drvdata(pdev); + pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + projection = &pflash_led_dev->projection; + + if(projection->i2c_bus == UNDEFINED_IN_DTS) { + return count; + } + + ret = kstrtoul(buf, 16, &addr); + if (ret < 0) { + return ret; + } + + val = addr & 0xff; + addr = addr >> 8; + + ret = flash_led_i2c_write(projection, addr, val); + if (ret < 0) { + return ret; + } + + printk("write reg[0x%x] 0x%x\n", addr, val); + + return count; +} + +static ssize_t flash_led_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int ret = 0; + struct platform_device *pdev = to_platform_device(dev); + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + char buffer[100]; + unsigned long en; + + pdriver_dev = platform_get_drvdata(pdev); + pflash_led_dev = (struct flash_led_ctrl *)pdriver_dev->private; + + ret = kstrtoul(buf, 10, &en); + if (ret < 0) { + return ret; + } + + pflash_led_dev->enable = en; + + return count; +} + +static ssize_t flash_led_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret = 0; + struct platform_device *pdev = to_platform_device(dev); + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + char buffer[100]; + unsigned long en; + + pdriver_dev = platform_get_drvdata(pdev); + pflash_led_dev = (struct flash_led_ctrl *)pdriver_dev->private; + snprintf(buffer, sizeof(buffer), "flash_led enable mask is 0x%x\n", pflash_led_dev->enable); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +uint64_t get_us_time(void); + +static ssize_t projection_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int ret = 0; + struct platform_device *pdev = to_platform_device(dev); + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + struct flash_led_dev *projection; + char buffer[100]; + unsigned long ch; + + pdriver_dev = platform_get_drvdata(pdev); + pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + projection = &pflash_led_dev->projection; + + ret = kstrtoul(buf, 10, &ch); + if (ret < 0) { + return ret; + } + + uint64_t us1 = get_us_time(); + + if (projection->flash_led_func != NULL) { + projection->flash_led_func->enable_channel(projection, ch); + } + uint64_t us2 = get_us_time(); + + printk("used time %llu us\n", us2 - us1); + + return count; +} + +static ssize_t floodlight_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int ret = 0; + struct platform_device *pdev = to_platform_device(dev); + struct flash_led_driver_dev *pdriver_dev; + struct flash_led_ctrl *pflash_led_dev; + struct flash_led_dev *floodlight; + unsigned long ch; + + pdriver_dev = platform_get_drvdata(pdev); + pflash_led_dev = (struct flash_led_ctrl*)pdriver_dev->private; + floodlight = &pflash_led_dev->floodlight; + + ret = kstrtoul(buf, 10, &ch); + if (ret < 0) { + return ret; + } + + uint64_t us1 = get_us_time(); + if (floodlight->flash_led_func != NULL) { + floodlight->flash_led_func->enable_channel(floodlight, ch); + } + uint64_t us2 = get_us_time(); + + printk("used time %llu us\n", us2 - us1); + return count; +} + +static DEVICE_ATTR_RO(flash_led_info); +static DEVICE_ATTR_RO(flash_led_int); +static DEVICE_ATTR_RO(flash_led_pin_high_time_us); +static DEVICE_ATTR_RO(flash_led_pin_period_us); +static DEVICE_ATTR_RO(flash_led_falling_int); +static DEVICE_ATTR_RO(flash_led_rising_int); +static DEVICE_ATTR_WO(projection_led_reg_write); +static DEVICE_ATTR_WO(projection_led_reg_read); +static DEVICE_ATTR_WO(floodlight_led_reg_write); +static DEVICE_ATTR_WO(floodlight_led_reg_read); +static DEVICE_ATTR_WO(projection_enable); +static DEVICE_ATTR_WO(floodlight_enable); +static DEVICE_ATTR_RW(flash_led_enable); + +int flash_led_create_capabilities_sysfs(struct platform_device *pdev) +{ + device_create_file(&pdev->dev, &dev_attr_flash_led_info); + device_create_file(&pdev->dev, &dev_attr_flash_led_int); + device_create_file(&pdev->dev, &dev_attr_flash_led_pin_high_time_us); + device_create_file(&pdev->dev, &dev_attr_flash_led_pin_period_us); + device_create_file(&pdev->dev, &dev_attr_flash_led_falling_int); + device_create_file(&pdev->dev, &dev_attr_flash_led_rising_int); + device_create_file(&pdev->dev, &dev_attr_projection_led_reg_write); + device_create_file(&pdev->dev, &dev_attr_projection_led_reg_read); + device_create_file(&pdev->dev, &dev_attr_floodlight_led_reg_write); + device_create_file(&pdev->dev, &dev_attr_floodlight_led_reg_read); + device_create_file(&pdev->dev, &dev_attr_projection_enable); + device_create_file(&pdev->dev, &dev_attr_floodlight_enable); + device_create_file(&pdev->dev, &dev_attr_flash_led_enable); + + return 0; +} + +int flash_led_remove_capabilities_sysfs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_flash_led_info); + device_remove_file(&pdev->dev, &dev_attr_flash_led_int); + device_remove_file(&pdev->dev, &dev_attr_flash_led_pin_high_time_us); + device_remove_file(&pdev->dev, &dev_attr_flash_led_pin_period_us); + device_remove_file(&pdev->dev, &dev_attr_flash_led_falling_int); + device_remove_file(&pdev->dev, &dev_attr_flash_led_rising_int); + device_remove_file(&pdev->dev, &dev_attr_projection_led_reg_write); + device_remove_file(&pdev->dev, &dev_attr_projection_led_reg_read); + device_remove_file(&pdev->dev, &dev_attr_floodlight_led_reg_write); + device_remove_file(&pdev->dev, &dev_attr_floodlight_led_reg_read); + device_remove_file(&pdev->dev, &dev_attr_projection_enable); + device_remove_file(&pdev->dev, &dev_attr_floodlight_enable); + device_remove_file(&pdev->dev, &dev_attr_flash_led_enable); + + return 0; +} + diff --git a/vvcam/native/flash_led/ntc.c b/vvcam/native/flash_led/ntc.c new file mode 100644 index 0000000..941fb47 --- /dev/null +++ b/vvcam/native/flash_led/ntc.c @@ -0,0 +1,207 @@ + +#include + +typedef struct { + int r; + int temperature; +} ntc_table_t; + +static ntc_table_t ntc[] = { + {188424, -40}, + {177892, -39}, + {168031, -38}, + {158793, -37}, + {150135, -36}, + {142016, -35}, + {134398, -34}, + {127247, -33}, + {120531, -32}, + {114221, -31}, + {108289, -30}, + {102711, -29}, + {97461, -28}, + {92519, -27}, + {87865, -26}, + {83480, -25}, + {79346, -24}, + {75447, -23}, + {71769, -22}, + {68297, -21}, + {65019, -20}, + {61922, -19}, + {58995, -18}, + {56228, -17}, + {53610, -16}, + {51133, -15}, + {48789, -14}, + {46568, -13}, + {44465, -12}, + {42472, -11}, + {40582, -10}, + {38789, -9}, + {37089, -8}, + {35475, -7}, + {33942, -6}, + {32486, -5}, + {31103, -4}, + {29789, -3}, + {28539, -2}, + {27350, -1}, + {26219, 0}, + {25142, 1}, + {24117, 2}, + {23140, 3}, + {22210, 4}, + {21324, 5}, + {20479, 6}, + {19673, 7}, + {18904, 8}, + {18170, 9}, + {17470, 10}, + {16801, 11}, + {16162, 12}, + {15552, 13}, + {14969, 14}, + {14412, 15}, + {13879, 16}, + {13369, 17}, + {12881, 18}, + {12414, 19}, + {11967, 20}, + {11539, 21}, + {11129, 22}, + {10737, 23}, + {10360, 24}, + {10000, 25}, + {9617, 26}, + {9252, 27}, + {8902, 28}, + {8569, 29}, + {8249, 30}, + {7944, 31}, + {7652, 32}, + {7372, 33}, + {7104, 34}, + {6848, 35}, + {6602, 36}, + {6367, 37}, + {6142, 38}, + {5926, 39}, + {5719, 40}, + {5520, 41}, + {5329, 42}, + {5147, 43}, + {4971, 44}, + {4803, 45}, + {4641, 46}, + {4486, 47}, + {4336, 48}, + {4193, 49}, + {4055, 50}, + {3923, 51}, + {3795, 52}, + {3673, 53}, + {3555, 54}, + {3442, 55}, + {3333, 56}, + {3228, 57}, + {3127, 58}, + {3029, 59}, + {2936, 60}, + {2845, 61}, + {2758, 62}, + {2674, 63}, + {2593, 64}, + {2516, 65}, + {2440, 66}, + {2368, 67}, + {2298, 68}, + {2230, 69}, + {2165, 70}, + {2103, 71}, + {2042, 72}, + {1983, 73}, + {1927, 74}, + {1872, 75}, + {1819, 76}, + {1768, 77}, + {1719, 78}, + {1671, 79}, + {1625, 80}, + {1580, 81}, + {1537, 82}, + {1496, 83}, + {1455, 84}, + {1416, 85}, + {1378, 86}, + {1342, 87}, + {1306, 88}, + {1272, 89}, + {1239, 90}, + {1207, 91}, + {1176, 92}, + {1145, 93}, + {1116, 94}, + {1088, 95}, + {1060, 96}, + {1034, 97}, + {1008, 98}, + {983, 99}, + {958, 100}, + {935, 101}, + {912, 102}, + {890, 103}, + {868, 104}, + {847, 105}, + {827, 106}, + {807, 107}, + {788, 108}, + {769, 109}, + {751, 110}, + {734, 111}, + {717, 112}, + {700, 113}, + {684, 114}, + {668, 115}, + {653, 116}, + {638, 117}, + {624, 118}, + {610, 119}, + {596, 120}, + {583, 121}, + {570, 122}, + {558, 123}, + {545, 124}, + {534, 125}, +}; + +static unsigned int ntc_abs(int a, int b) +{ + if(a > b) { + return (a - b); + } + return b - a; +} + +#define RX(mv) (10000*(mv)/(1800-mv)) + +int get_ntc_temperature(int mv) +{ + int num = sizeof(ntc) / sizeof(ntc[0]); + int i = 0; + unsigned int d = 0xfffffff; + int t; + int r = RX(mv); + + while(i < num) { + if (ntc_abs(r, ntc[i].r) < d) { + t = ntc[i].temperature; + d = ntc_abs(r, ntc[i].r); + } + i++; + } + + printk(KERN_DEBUG "v: %d, r: %d, t: %d\n", mv, r, t); + return t; +} + diff --git a/vvcam/native/flash_led/platform/platform_driver.c b/vvcam/native/flash_led/platform/platform_driver.c new file mode 100755 index 0000000..9234c76 --- /dev/null +++ b/vvcam/native/flash_led/platform/platform_driver.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include "../native/sensor/sensor_common.h" + +int32_t flash_led_reset(void *dev) +{ + /* + int ret = 0; + struct vvcam_sensor_dev *psensor_dev = (struct vvcam_sensor_dev *)dev; + + if (gpio_is_valid(psensor_dev->rst_pin)) { + gpio_direction_output(psensor_dev->rst_pin, 1); + } + + if (gpio_is_valid(psensor_dev->pdn_pin)) { + gpio_direction_output(psensor_dev->pdn_pin, 1); + } + + udelay(psensor_dev->pdn_delay_us); + */ + return 0; +} + +int32_t flash_led_set_power(void *dev, uint32_t power) +{ + /* + int ret = 0, i = 0; + struct vvcam_sensor_dev *psensor_dev = (struct vvcam_sensor_dev *)dev; + printk("sensor_set_power enter, power=%d\n", power); + + if (psensor_dev->regulators.num <= 0) { + printk("no regulator for %s", psensor_dev->sensor_name); + return -ENODEV; + } + + for (i = 0; i < psensor_dev->regulators.num; i++) { + if (gpio_is_valid(psensor_dev->rst_pin)) { + gpio_direction_output(psensor_dev->rst_pin, 0); // make sure reset is low before power up + } + + if (gpio_is_valid(psensor_dev->pdn_pin)) { + gpio_direction_output(psensor_dev->pdn_pin, 0); + } + + if (power == 1) { + ret = regulator_enable(psensor_dev->regulators.supply[i]); + printk("regulator_enable ret=%d\n", ret); + } else if (power == 0) { + ret = regulator_disable(psensor_dev->regulators.supply[i]); + } else { + return -1; + } + if (ret) + return ret; + udelay(psensor_dev->regulators.delay_us[i]); + } + */ + return 0; +} + +int32_t flash_led_get_power(void *dev, uint32_t *ppower) +{ + return 0; +} + diff --git a/vvcam/native/gpio_i2c/Makefile b/vvcam/native/gpio_i2c/Makefile new file mode 100755 index 0000000..9d70353 --- /dev/null +++ b/vvcam/native/gpio_i2c/Makefile @@ -0,0 +1,17 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_i2c + +obj-m +=$(TARGET).o +$(TARGET)-objs += soc_i2c_driver.o + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam/native/gpio_i2c/soc_i2c_driver.c b/vvcam/native/gpio_i2c/soc_i2c_driver.c new file mode 100755 index 0000000..e5c3e96 --- /dev/null +++ b/vvcam/native/gpio_i2c/soc_i2c_driver.c @@ -0,0 +1,437 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct soc_gpio_i2c{ + struct i2c_adapter adap; + unsigned long phy_base_addr; + unsigned long size; + void __iomem * virt_base_addr; + spinlock_t lock; +}; + + +static void i2c_gpio_setsda_val(void *source, int state) +{ + struct soc_gpio_i2c *i2c = source; + int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~0x1)) | (0x10 | (state & 0x01)); + + writel(reg_data, i2c->virt_base_addr); + return ; +} + +static void i2c_gpio_setscl_val(void *source, int state) +{ + struct soc_gpio_i2c *i2c = source; + int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~(0x1 << 8))) | ((0x10 | (state & 0x01)) << 8); + + writel(reg_data, i2c->virt_base_addr); + return ; +} + +static int i2c_gpio_getsda(void *source) +{ + struct soc_gpio_i2c *i2c = source; + unsigned int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~0x10)); + writel(reg_data, i2c->virt_base_addr); + + return (readl(i2c->virt_base_addr) & 0x01); +} +// Start :When SCL is High ,SDA Change to low +static void i2c_gpio_start(void *source) +{ + i2c_gpio_setscl_val(source, 1); + i2c_gpio_setsda_val(source, 1); + udelay(5); + i2c_gpio_setsda_val(source, 0); + udelay(1); + return; +} +//Send Bit : When SCL is LOW, sda change;When SCL is HIgh,SDA hold; +static void i2c_gpio_send_byte(void *source, unsigned char val) +{ + int bit_idx; + for (bit_idx=7; bit_idx >= 0; bit_idx--) + { + i2c_gpio_setscl_val(source, 0); + i2c_gpio_setsda_val(source, (val >> bit_idx) & 0x01); + udelay(1); + i2c_gpio_setscl_val(source, 1); + udelay(1); + } + i2c_gpio_setscl_val(source, 0); + i2c_gpio_setsda_val(source, 1); + return; +} +//Read Bit: When SCL is High read data; +static unsigned char i2c_gpio_read_byte(void *source) +{ + int bit_idx; + unsigned char data = 0; + + i2c_gpio_getsda(source);//SDA change to read + + for(bit_idx=7; bit_idx>=0; bit_idx--) + { + + i2c_gpio_setscl_val(source, 1); + udelay(1); + data = (data << 1) | i2c_gpio_getsda(source); + i2c_gpio_setscl_val(source, 0); + udelay(1); + } + return data; +} + +static int i2c_gpio_wait_ack(void *source) +{ + unsigned int i2c_retry_ack_cnt = 0; + + i2c_gpio_getsda(source);//SDA change to read + udelay(1); + i2c_gpio_setscl_val(source, 1); + + while(i2c_gpio_getsda(source) == 1) + { + udelay(1); + if (i2c_retry_ack_cnt++ > 20) + { + return 0; + } + } + i2c_gpio_setscl_val(source, 0); + return 1; +} + +static void i2c_gpio_stop(void *source) +{ + i2c_gpio_setsda_val(source, 0); + udelay(1); + i2c_gpio_setscl_val(source, 1); + udelay(1); + i2c_gpio_setsda_val(source, 1); + return; +} + +static int i2c_gpio_write(void *source,struct i2c_msg *msg) +{ + + unsigned char slave_address; + unsigned char *buf; + int i; + slave_address = (msg->addr) << 1; + buf = msg->buf; + + i2c_gpio_start(source); + i2c_gpio_send_byte(source, slave_address); + if (i2c_gpio_wait_ack(source) == 0) return -1; + + for (i = 0; i < msg->len; i++) + { + i2c_gpio_send_byte(source, buf[i]); + i2c_gpio_wait_ack(source); + } + + i2c_gpio_stop(source); + return 0; +} + +static int i2c_gpio_read(void *source,struct i2c_msg *msg) +{ + unsigned char slave_address; + unsigned char *buf; + int i; + slave_address = ((msg->addr) << 1) | 0x01; + buf = msg->buf; + + i2c_gpio_start(source); + i2c_gpio_send_byte(source, slave_address); + if (i2c_gpio_wait_ack(source) == 0) return -1; + + for (i = 0; i < msg->len; i++) + { + buf[i] = i2c_gpio_read_byte(source); + i2c_gpio_wait_ack(source); + } + + return 0; +} + +static int i2c_gpio_xfer(struct i2c_adapter *adapter, + struct i2c_msg *msgs, int num) +{ + int result; + int i; + struct soc_gpio_i2c *i2c; + void *source; + + source = i2c_get_adapdata(adapter); + i2c = source; + + for (i=0; idev, sizeof(struct soc_gpio_i2c), GFP_KERNEL); + if (!i2c) + { + return -ENOMEM; + } + memset(i2c, 0, sizeof(struct soc_gpio_i2c)); + //mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + //i2c->virt_base_addr = devm_ioremap_resource(&pdev->dev, mem); + if (pdev->id == VVSENSOR_I2C_BUS0) + { + i2c->virt_base_addr = ioremap(VVCAM_I2C0_BASE, VVCAM_I2C_SIZE); + + }else + { + i2c->virt_base_addr = ioremap(VVCAM_I2C1_BASE, VVCAM_I2C_SIZE); + } + + if (i2c->virt_base_addr == NULL) + { + return -1; + } + + if (IS_ERR(i2c->virt_base_addr)) + return PTR_ERR(i2c->virt_base_addr); + + + spin_lock_init(&(i2c->lock)); + + adap = &i2c->adap; + platform_set_drvdata(pdev, i2c); + + i2c_set_adapdata(adap, i2c); + adap->owner = THIS_MODULE; + snprintf(adap->name, sizeof(adap->name), "soc_gpio_i2c"); + adap->timeout = 2 * HZ; + adap->retries = 0; + adap->algo = &gpio_i2c_algo; + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + adap->dev.parent = &pdev->dev; + adap->nr = pdev->id; + adap->dev.of_node = pdev->dev.of_node; + + ret = i2c_add_numbered_adapter(adap); + if (ret) + { + pr_info("%s:i2c_add_adapter failed 0x%x\n", __func__, ret); + kfree(i2c); + return ret; + } + + return 0; +} + +static int soc_gpio_i2c_remove(struct platform_device *pdev) +{ + struct soc_gpio_i2c *i2c; + + i2c = platform_get_drvdata(pdev); + i2c_del_adapter(&(i2c->adap)); + + iounmap(i2c->virt_base_addr); + + return 0; +} + +static struct platform_driver soc_gpio_i2c_driver = { + .probe = soc_gpio_i2c_probe, + .remove = soc_gpio_i2c_remove, + .driver = { + .name = "soc_gpio_i2c", + .owner = THIS_MODULE, + }, +}; + +static void soc_gpio_i2c_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); + return; +} + + +#ifdef WITH_VVCAM +static struct resource soc_gpio_i2c0_resource[] = { + [0] = { + .start = VVCAM_I2C0_BASE, + .end = VVCAM_I2C0_BASE + VVCAM_I2C_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + + +static struct platform_device soc_gpio_i2c0_pdev = { + .name = "soc_gpio_i2c", + .id = VVSENSOR_I2C_BUS0, + .resource = soc_gpio_i2c0_resource, + .num_resources = 0, + .dev.release = soc_gpio_i2c_release, +}; +#endif + +#ifdef WITH_VVCAM_DUAL +static struct resource soc_gpio_i2c1_resource[] = { + [0] = { + .start = VVCAM_I2C1_BASE, + .end = VVCAM_I2C1_BASE + VVCAM_I2C_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device soc_gpio_i2c1_pdev = { + .name = "soc_gpio_i2c", + .id = VVSENSOR_I2C_BUS1, + .resource = soc_gpio_i2c1_resource, + .num_resources = 0, + .dev.release = soc_gpio_i2c_release, +}; +#endif + +static int __init soc_gpio_i2c_driver_init_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_register(&soc_gpio_i2c_driver); +#ifdef WITH_VVCAM + platform_device_register(&soc_gpio_i2c0_pdev); +#endif +#ifdef WITH_VVCAM_DUAL + platform_device_register(&soc_gpio_i2c1_pdev); +#endif + return 0; +} +static void __exit soc_gpio_i2c_driver_exit_module(void) +{ +#ifdef WITH_VVCAM + platform_device_unregister(&soc_gpio_i2c0_pdev); +#endif +#ifdef WITH_VVCAM_DUAL + platform_device_unregister(&soc_gpio_i2c1_pdev); +#endif + platform_driver_unregister(&soc_gpio_i2c_driver); + + + return; +} + +module_init(soc_gpio_i2c_driver_init_module); +module_exit(soc_gpio_i2c_driver_exit_module); + +MODULE_DESCRIPTION("SENSOR"); +MODULE_LICENSE("GPL"); + + + + diff --git a/vvcam/native/isp/Makefile b/vvcam/native/isp/Makefile new file mode 100755 index 0000000..c65fe83 --- /dev/null +++ b/vvcam/native/isp/Makefile @@ -0,0 +1,41 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_isp + +obj-m +=$(TARGET).o +$(TARGET)-objs += vvcam_isp_driver_of.o +$(TARGET)-objs += ../../isp/isp_miv1.o +$(TARGET)-objs += ../../isp/isp_miv2.o +$(TARGET)-objs += ../../isp/isp_wdr3.o +$(TARGET)-objs += ../../isp/isp_wdr4.o +$(TARGET)-objs += ../../isp/isp_wdr.o +$(TARGET)-objs += ../../isp/isp_3dnr.o +$(TARGET)-objs += ../../isp/isp_3dnr2.o +$(TARGET)-objs += ../../isp/isp_tdnr3.o +$(TARGET)-objs += ../../isp/isp_hdr.o +$(TARGET)-objs += ../../isp/isp_dpf.o +$(TARGET)-objs += ../../isp/isp_compand.o +$(TARGET)-objs += ../../isp/isp_gcmono.o +$(TARGET)-objs += ../../isp/isp_rgbgamma.o +$(TARGET)-objs += ../../isp/isp_ioctl.o +$(TARGET)-objs += ../../isp/isp_dmsc2.o +$(TARGET)-objs += ../../isp/isp_rgbir.o +$(TARGET)-objs += ../../isp/isp_irq_queue.o + + + +EXTRA_CFLAGS += -I$(PWD)/../../isp +EXTRA_CFLAGS += -I$(PWD)/../../driver +EXTRA_CFLAGS += -I$(PWD)/../../common + + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam/native/isp/vvcam_isp_driver.c b/vvcam/native/isp/vvcam_isp_driver.c new file mode 100755 index 0000000..fda40de --- /dev/null +++ b/vvcam/native/isp/vvcam_isp_driver.c @@ -0,0 +1,572 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "isp_ioctl.h" +#include "mrv_all_regs.h" +#include "isp_wdr.h" + +extern MrvAllRegister_t *all_regs; + +static ulong vvImgBufBase = 0x10000000; +module_param(vvImgBufBase, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvImgBufBase, "Base addrss of memory reserved for ISP"); + +static ulong vvImgBufSize = 0x10000000; +module_param(vvImgBufSize, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvImgBufSize, "Size of memory reserved for ISP"); + +#define VIVCAM_ISP_NAME "vivisp" +#define VIVCAM_ISP_MAXCNT 2 +#define VIVCAM_ISP_IRQ_NUMBER 16 + +struct vvcam_isp_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + unsigned int device_idx; + struct timer_list isp_timer; + struct work_struct vvnative_wq; + wait_queue_head_t irq_wait; + int irq_num; + void *private; +}; + +static unsigned int vvcam_isp_major = 0; +static unsigned int vvcam_isp_minor = 0; +static struct class *vvcam_isp_class; +static unsigned int devise_register_index = 0; +static bool isp_irq = false; +static unsigned int vvnative_isp_poll(struct file * filp, poll_table *wait) +{ + unsigned int mask = 0; + struct vvcam_isp_driver_dev *pdriver_dev = filp->private_data; + poll_wait(filp, &pdriver_dev->irq_wait, wait); + + //pr_info("poll isp_irq %d\n", isp_irq); + + if (isp_irq) { + mask |= POLLIN |POLLRDNORM; + isp_irq = false; + } + return mask; +} + +static void vvnative_isp_work(struct work_struct *work) +{ + /*Todo update those module that does not have shandow register*/ + struct vvcam_isp_driver_dev *pdriver_dev = container_of(work, struct vvcam_isp_driver_dev, vvnative_wq); + + struct isp_ic_dev * pisp_dev = pdriver_dev->private; + pr_info("%s enter \n", __func__); + + isp_irq = true; + wake_up_interruptible(&pdriver_dev->irq_wait); + if (pisp_dev->isp_mis & MRV_ISP_MIS_FRAME_MASK) { + if (pisp_dev->wdr.changed) { + pr_info("%s pisp_dev->wdr.changed %d\n", __func__, + pisp_dev->wdr.changed); + isp_s_wdr(pisp_dev); + } + if (pisp_dev->flt.changed) { + pr_info("%s pisp_dev->flt.changed %d\n", __func__, + pisp_dev->flt.changed); + isp_s_flt(pisp_dev); + } +#ifndef ISP_CPROC_SHD + if (pisp_dev->cproc.changed) { + pr_info("%s pisp_dev->cproc.changed %d\n", __func__, + pisp_dev->cproc.changed); + isp_s_cproc(pisp_dev); + } +#endif + if (pisp_dev->gamma_out.changed) { + pr_info("%s pisp_dev->gamma_out.changed %d\n", __func__, + pisp_dev->gamma_out.changed); + isp_s_gamma_out(pisp_dev); + } + + } + +} + +static irqreturn_t vvcam_isp_irq(int irq, void *dev_id) +{ + struct vvcam_isp_driver_dev *pdriver_dev ; + struct isp_ic_dev * pisp_dev; + u32 isp_mis, mi_mis, mi_mis_addr, mi_icr_addr; +#ifdef ISP_MIV2 + u32 miv2_mis1, miv2_mis3; +#endif + #if defined(ISP_MI_PP_READ) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE) || defined (ISP_MI_HDR) + u32 miv2_mis2; +#endif + pdriver_dev = (struct vvcam_isp_driver_dev *)dev_id; + pisp_dev = pdriver_dev->private; + isp_mis = isp_read_reg(pisp_dev, REG_ADDR(isp_mis)); +#ifdef ISP_MIV2 + mi_icr_addr = REG_ADDR(miv2_icr); + mi_mis_addr = REG_ADDR(miv2_mis); + miv2_mis1 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis1)); + if (miv2_mis1) { + pr_info("%s mi mis1 0x%08x\n", __func__, miv2_mis1); + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr1), miv2_mis1); + } + + miv2_mis3 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis3)); + if (miv2_mis3) { + pr_info("%s mi mis3 0x%08x\n", __func__, miv2_mis3); + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr3), miv2_mis3); + } +#elif defined(ISP_MIV1) + mi_icr_addr = REG_ADDR(mi_icr); + mi_mis_addr = REG_ADDR(mi_mis); +#endif + + mi_mis = isp_read_reg(pisp_dev, mi_mis_addr); + #if defined(ISP_MI_PP_READ) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE) || defined (ISP_MI_HDR) + miv2_mis2 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis2)); + pr_info("%s isp mis 0x%08x, mi mis 0x%08x post mis 0x%08x\n", __func__, \ + isp_mis, mi_mis, miv2_mis2); +#else + pr_info("%s isp mis 0x%08x, mi mis 0x%08x\n", __func__, \ + isp_mis, mi_mis); +#endif + + if (isp_mis) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_ISP_IRQ; + mis_data.val = isp_mis; + pisp_dev->isp_mis = isp_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + isp_write_reg(pisp_dev, REG_ADDR(isp_icr), isp_mis); + if(isp_mis & MRV_ISP_ISR_ISP_OFF_MASK) + isp_write_reg(pisp_dev, REG_ADDR(isp_imsc), isp_mis& (~MRV_ISP_ISR_ISP_OFF_MASK)); + } + + if (mi_mis) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI_IRQ; + mis_data.val = mi_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + + isp_write_reg(pisp_dev, mi_icr_addr, mi_mis); + } +#ifdef ISP_MIV2 + if (miv2_mis1) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI1_IRQ; + mis_data.val = mi_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + + isp_write_reg(pisp_dev, mi_icr_addr, mi_mis); + } +#endif + + #if defined(ISP_MI_PP_READ) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE) || defined (ISP_MI_HDR) + if (miv2_mis2) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI2_IRQ; + mis_data.val = miv2_mis2; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr2), miv2_mis2); + } +#endif + + #if defined(ISP_MI_PP_READ) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE) || defined (ISP_MI_HDR) + if (isp_mis != 0 ||mi_mis != 0 || miv2_mis2 != 0) { + #else + if (isp_mis != 0 ||mi_mis != 0 ) { +#endif + schedule_work(&pdriver_dev->vvnative_wq); + } else { + return IRQ_NONE; + } + return IRQ_HANDLED; +} + +static int vvcam_isp_open(struct inode * inode, struct file * file) +{ + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + pdriver_dev = container_of(inode->i_cdev, struct vvcam_isp_driver_dev, cdev); + file->private_data = pdriver_dev; + pisp_dev = pdriver_dev->private; + /*create circle queue*/ + isp_irq_create_circle_queue(&(pisp_dev->circle_list), QUEUE_NODE_COUNT); + return 0; +}; + +static long vvcam_isp_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + pisp_dev = pdriver_dev->private; + //pr_info("%s:isp[%d] pdriver_dev =0x%px\n", __func__,pdriver_dev->device_idx,pdriver_dev); + //pr_info("%s:pisp_dev =0x%px\n", __func__,pisp_dev); + + mutex_lock(&pdriver_dev->vvmutex); + ret = isp_priv_ioctl(pisp_dev, cmd ,(void __user *)arg); + mutex_unlock(&pdriver_dev->vvmutex); + + return ret; +}; + +static int vvcam_isp_release(struct inode * inode, struct file * file) +{ + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev *pisp_dev; + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_isp_driver_dev, cdev); + file->private_data = pdriver_dev; + pisp_dev = pdriver_dev->private; + pr_info("enter %s\n", __func__); + isp_irq_destroy_circle_queue(&(pisp_dev->circle_list)); + + return 0; +}; + +static int vvcam_isp_mmap(struct file *pFile, struct vm_area_struct *vma) +{ + int ret = 0; + + ulong phy_base_addr = 0; + + unsigned long pfn_start = (phy_base_addr >> PAGE_SHIFT) + vma->vm_pgoff; + unsigned long size = vma->vm_end - vma->vm_start; + pr_info("phy: 0x%lx, size: 0x%lx\n", pfn_start << PAGE_SHIFT, size); + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + if (remap_pfn_range(vma, vma->vm_start,pfn_start,size, vma->vm_page_prot)) + { + pr_err("-->%s: remap_pfn_range error!\n", __func__); + return -EIO; + } + + return ret; +}; + +static struct file_operations vvcam_isp_fops = { + .owner = THIS_MODULE, + .open = vvcam_isp_open, + .release = vvcam_isp_release, + .unlocked_ioctl = vvcam_isp_ioctl, + .mmap = vvcam_isp_mmap, + .poll = vvnative_isp_poll, +}; + +static int vvcam_isp_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + struct resource *mem; + + pr_info("enter %s\n", __func__); + + if (pdev->id >= VIVCAM_ISP_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_isp_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_isp_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_isp_driver_dev )); + pr_info("%s:isp[%d]: pdriver_dev =0x%px\n", __func__,pdev->id,pdriver_dev); + + pisp_dev = devm_kzalloc(&pdev->dev,sizeof(struct isp_ic_dev), GFP_KERNEL); + if (pisp_dev == NULL) + { + pr_err("%s:alloc struct isp_ic_dev error\n", __func__); + return -ENOMEM; + } + memset(pisp_dev,0,sizeof(struct isp_ic_dev )); + pr_info("%s:isp[%d]: psensor_dev =0x%px\n", __func__,pdev->id,pisp_dev); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pisp_dev->base = devm_ioremap_resource(&pdev->dev, mem); + pisp_dev->reset = NULL; + + pdriver_dev->private = pisp_dev; + pdriver_dev->device_idx = pdev->id; + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + + pdriver_dev->irq_num = platform_get_irq(pdev, 0); + + if (devise_register_index == 0) + { + /*init work queue*/ + INIT_WORK(&pdriver_dev->vvnative_wq, vvnative_isp_work); + + ret = devm_request_irq(&pdev->dev, pdriver_dev->irq_num, vvcam_isp_irq, + IRQF_TRIGGER_RISING|IRQF_SHARED, "ISP_IRQ", (char *)pdriver_dev); + if (ret) { + pr_err("%s[%d]:request irq error!\n", __func__, __LINE__); + return ret; + } + init_waitqueue_head(&pdriver_dev->irq_wait); + if (vvcam_isp_major == 0) + { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_ISP_MAXCNT, VIVCAM_ISP_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_isp_major = MAJOR(pdriver_dev->devt); + vvcam_isp_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_isp_major, vvcam_isp_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_ISP_MAXCNT, VIVCAM_ISP_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + vvcam_isp_class = class_create(THIS_MODULE, VIVCAM_ISP_NAME); + if (IS_ERR(vvcam_isp_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_isp_major, vvcam_isp_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_isp_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_isp_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VIVCAM_ISP_NAME, pdev->id); + + + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int vvcam_isp_remove(struct platform_device *pdev) +{ + struct vvcam_isp_driver_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + // free_irq(pdriver_dev->irq_num, pdriver_dev); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_ISP_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + return 0; +} + +static struct platform_driver vvcam_isp_driver = { + .probe = vvcam_isp_probe, + .remove = vvcam_isp_remove, + .driver = { + .name = VIVCAM_ISP_NAME, + .owner = THIS_MODULE, + } +}; + +static void vvcam_isp_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +#ifdef WITH_VVCAM +static struct resource vvcam_isp0_resource[] = { + [0] = { + .start = VVISP0_BASE, + .end = VVISP0_BASE + ISP_REG_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = VIVCAM_ISP_IRQ_NUMBER, + .end = VIVCAM_ISP_IRQ_NUMBER, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device vvcam_isp_pdev = { + .name = VIVCAM_ISP_NAME, + .id = 0, + .resource = vvcam_isp0_resource, + .num_resources = ARRAY_SIZE(vvcam_isp0_resource), + .dev.release = vvcam_isp_pdev_release, +}; +#endif + +#ifdef WITH_VVCAM_DUAL +static struct resource vvcam_isp1_resource[] = { + [0] = { + .start = VVISP1_BASE, + .end = VVISP1_BASE + ISP_REG_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = VIVCAM_ISP_IRQ_NUMBER, + .end = VIVCAM_ISP_IRQ_NUMBER, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device vvcam_isp_dual_pdev = { + .name = VIVCAM_ISP_NAME, + .id = 1, + .resource = vvcam_isp1_resource, + .num_resources = ARRAY_SIZE(vvcam_isp1_resource), + .dev.release = vvcam_isp_pdev_release, +}; +#endif + +static int __init vvcam_isp_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); +#ifdef WITH_VVCAM + ret = platform_device_register(&vvcam_isp_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } +#endif + +#ifdef WITH_VVCAM_DUAL + ret = platform_device_register(&vvcam_isp_dual_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } +#endif + + ret = platform_driver_register(&vvcam_isp_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit vvcam_isp_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_isp_driver); +#ifdef WITH_VVCAM + platform_device_unregister(&vvcam_isp_pdev); +#endif + +#ifdef WITH_VVCAM_DUAL + platform_device_unregister(&vvcam_isp_dual_pdev); +#endif +} + +module_init(vvcam_isp_init_module); +module_exit(vvcam_isp_exit_module); + +MODULE_DESCRIPTION("ISP"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/isp/vvcam_isp_driver_of.c b/vvcam/native/isp/vvcam_isp_driver_of.c new file mode 100755 index 0000000..4f9c149 --- /dev/null +++ b/vvcam/native/isp/vvcam_isp_driver_of.c @@ -0,0 +1,719 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "isp_ioctl.h" +#include "mrv_all_regs.h" +#include "isp_wdr.h" + +extern MrvAllRegister_t *all_regs; + + +#define VIVCAM_ISP_NAME "vivisp" +#define VIVCAM_ISP_MAXCNT 2 +#define VIVCAM_ISP_IRQ_NUMBER 16 + +typedef struct { + volatile uint64_t frame_irq_cnt; + volatile uint64_t frame_time_us; + volatile int x[2]; +} frame_mark_t; + +struct vvcam_isp_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + unsigned int device_idx; + struct timer_list isp_timer; + struct work_struct vvnative_wq; + wait_queue_head_t irq_wait; + int irq_num[2]; + void *private; + struct clk *aclk; + struct clk *hclk; + struct clk *isp0_pclk; + struct clk *cclk; + struct clk *isp1_pclk; + struct platform_device *pdev; + frame_mark_t *frame_mark; +}; + +static unsigned int vvcam_isp_major = 0; +static unsigned int vvcam_isp_minor = 0; +static struct class *vvcam_isp_class; +static unsigned int devise_register_index = 0; +static bool isp_irq = false; + +static unsigned int vvnative_isp_poll(struct file * filp, poll_table *wait) +{ + unsigned int mask = 0; + struct vvcam_isp_driver_dev *pdriver_dev = filp->private_data; + poll_wait(filp, &pdriver_dev->irq_wait, wait); + + //pr_info("poll isp_irq %d\n", isp_irq); + + if (isp_irq) { + mask |= POLLIN |POLLRDNORM; + isp_irq = false; + } + return mask; +} + +static uint64_t get_us_time(void) +{ + struct timespec64 ts; + static uint64_t us = 0; + ktime_get_real_ts64(&ts); + us = timespec64_to_ns(&ts) / 1000UL; + return us; +} + +static void vvnative_isp_work(struct work_struct *work) +{ + /*Todo update those module that does not have shandow register*/ + struct vvcam_isp_driver_dev *pdriver_dev = container_of(work, struct vvcam_isp_driver_dev, vvnative_wq); + + struct isp_ic_dev * pisp_dev = pdriver_dev->private; + + isp_irq = true; + wake_up_interruptible(&pdriver_dev->irq_wait); + + if (pisp_dev->isp_mis & MRV_ISP_MIS_FRAME_MASK) { + if (pisp_dev->wdr.changed) { + pr_info("%s pisp_dev->wdr.changed %d\n", __func__, + pisp_dev->wdr.changed); + isp_s_wdr(pisp_dev); + } + if (pisp_dev->flt.changed) { + pr_info("%s pisp_dev->flt.changed %d\n", __func__, + pisp_dev->flt.changed); + isp_s_flt(pisp_dev); + } +#ifndef ISP_CPROC_SHD + if (pisp_dev->cproc.changed) { + pr_info("%s pisp_dev->cproc.changed %d\n", __func__, + pisp_dev->cproc.changed); + isp_s_cproc(pisp_dev); + } +#endif + if (pisp_dev->gamma_out.changed) { + pr_info("%s pisp_dev->gamma_out.changed %d\n", __func__, + pisp_dev->gamma_out.changed); + isp_s_gamma_out(pisp_dev); + } + + } + +} + +static irqreturn_t vvcam_isp_irq(int irq, void *dev_id) +{ + struct vvcam_isp_driver_dev *pdriver_dev ; + struct isp_ic_dev * pisp_dev; + u32 isp_mis, mi_mis, mi_mis_addr, mi_icr_addr; +#ifdef ISP_MIV2 + u32 miv2_mis1, miv2_mis3; +#endif +#if defined(ISP_MI_PP_READ) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE) || defined (ISP_MI_HDR) + u32 miv2_mis2; +#endif + pdriver_dev = (struct vvcam_isp_driver_dev *)dev_id; + pisp_dev = pdriver_dev->private; + isp_mis = isp_read_reg(pisp_dev, REG_ADDR(isp_mis)); + +#ifdef ISP_MIV2 + mi_icr_addr = REG_ADDR(miv2_icr); + mi_mis_addr = REG_ADDR(miv2_mis); + miv2_mis1 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis1)); + if (miv2_mis1) { + /*pr_info("%s mi mis1 0x%08x\n", __func__, miv2_mis1);*/ + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr1), miv2_mis1); + } + + /*u32 miv2_mis3 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis3)); + if (miv2_mis3) { + pr_info("%s mi mis3 0x%08x\n", __func__, miv2_mis3); + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr3), miv2_mis3); + }*/ +#elif defined(ISP_MIV1) + mi_icr_addr = REG_ADDR(mi_icr); + mi_mis_addr = REG_ADDR(mi_mis); +#endif + + mi_mis = isp_read_reg(pisp_dev, mi_mis_addr); + #if defined(ISP_MI_PP_READ) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE) || defined (ISP_MI_HDR) + miv2_mis2 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis2)); + miv2_mis2 &= (~PPW_FRAME_END_MASK); + /*pr_info("%s isp mis 0x%08x, mi mis 0x%08x post mis 0x%08x\n", __func__, \ + isp_mis, mi_mis, miv2_mis2);*/ +#else + /*pr_info("%s isp mis 0x%08x, mi mis 0x%08x\n", __func__, \ + isp_mis, mi_mis);*/ +#endif + if (isp_mis & MRV_ISP_MIS_FLASH_ON_MASK) { + mi_mis |= 0x4; + } + + volatile frame_mark_t *frame_mark = pdriver_dev->frame_mark; + if (isp_mis & MRV_ISP_MIS_FRAME_IN_MASK) { + frame_mark->frame_time_us = get_us_time(); + frame_mark->frame_irq_cnt += 1; + } + + if (mi_mis) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI_IRQ; + mis_data.val = mi_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + + isp_write_reg(pisp_dev, mi_icr_addr, mi_mis); + } +#ifdef ISP_MIV2 + if (miv2_mis1) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI1_IRQ; + mis_data.val = mi_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + + isp_write_reg(pisp_dev, mi_icr_addr, mi_mis); + } +#endif + +#if defined(ISP_MI_PP_READ) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE) || defined (ISP_MI_HDR) + if (miv2_mis2) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI2_IRQ; + mis_data.val = miv2_mis2; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr2), miv2_mis2); + } +#endif + if (isp_mis) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_ISP_IRQ; + mis_data.val = isp_mis; + pisp_dev->isp_mis = isp_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + isp_write_reg(pisp_dev, REG_ADDR(isp_icr), isp_mis); + if(isp_mis & MRV_ISP_MIS_ISP_OFF_MASK) { + isp_write_reg(pisp_dev, REG_ADDR(isp_imsc), isp_read_reg(pisp_dev, REG_ADDR(isp_imsc))&(~MRV_ISP_MIS_ISP_OFF_MASK)); + } + } + +#if defined(ISP_MI_PP_READ) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE) || defined (ISP_MI_HDR) + if (isp_mis != 0 ||mi_mis != 0 || miv2_mis2 != 0) { +#else + if (isp_mis != 0 ||mi_mis != 0 ) { +#endif + schedule_work(&pdriver_dev->vvnative_wq); + } else { + return IRQ_HANDLED; // return IRQ_NONE; + } + return IRQ_HANDLED; +} + +static int vvcam_isp_runtime_suspend(struct device *dev) +{ + struct vvcam_isp_driver_dev *pdriver_dev = dev_get_drvdata(dev); + + clk_disable_unprepare(pdriver_dev->aclk); + clk_disable_unprepare(pdriver_dev->hclk); + clk_disable_unprepare(pdriver_dev->isp0_pclk); + clk_disable_unprepare(pdriver_dev->cclk); + if (IS_ERR(pdriver_dev->isp1_pclk)) + dev_err(dev, "isp1_pclk is null\n"); + else + clk_disable_unprepare(pdriver_dev->isp1_pclk); + pr_info("isp %s\n", __func__); + return 0; +} + +static int vvcam_isp_runtime_resume(struct device *dev) +{ + struct vvcam_isp_driver_dev *pdriver_dev = dev_get_drvdata(dev); + int ret = 0; + + ret = clk_prepare_enable(pdriver_dev->isp0_pclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable isp0 pixel clock\n"); + } + + ret = clk_prepare_enable(pdriver_dev->cclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable core clock\n"); + clk_disable_unprepare(pdriver_dev->isp0_pclk); + //return ret; + } + + ret = clk_prepare_enable(pdriver_dev->hclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable ahb clock\n"); + clk_disable_unprepare(pdriver_dev->isp0_pclk); + clk_disable_unprepare(pdriver_dev->cclk); + //return ret; + } + ret = clk_prepare_enable(pdriver_dev->aclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable axi clock\n"); + clk_disable_unprepare(pdriver_dev->isp0_pclk); + clk_disable_unprepare(pdriver_dev->cclk); + clk_disable_unprepare(pdriver_dev->hclk); + //return ret; + } + + if (IS_ERR(pdriver_dev->isp1_pclk)) { + dev_err(dev, "isp1_pclk is null\n"); + } else { + ret = clk_prepare_enable(pdriver_dev->isp1_pclk); + if (ret < 0) { + clk_disable_unprepare(pdriver_dev->isp0_pclk); + clk_disable_unprepare(pdriver_dev->cclk); + clk_disable_unprepare(pdriver_dev->hclk); + dev_err(dev, "could not prepare or enable isp1 pixel clock\n"); + } + } + + pr_info("%s isp Enabled clock\n", __func__); + return ret; +} +static const struct dev_pm_ops vvcam_isp_runtime_pm_ops = { + SET_RUNTIME_PM_OPS(vvcam_isp_runtime_suspend, vvcam_isp_runtime_resume, NULL) +}; + +static int vvcam_isp_open(struct inode * inode, struct file * file) +{ + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + int ret = 0; + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_isp_driver_dev, cdev); + file->private_data = pdriver_dev; + pisp_dev = pdriver_dev->private; + struct device *dev = &pdriver_dev->pdev->dev; + /*create circle queue*/ + isp_irq_create_circle_queue(&(pisp_dev->circle_list), QUEUE_NODE_COUNT); + if (pm_runtime_get_sync(dev)) { + ret = vvcam_isp_runtime_resume(dev); + if (ret) + pr_err("fail to resume isp %s %d\n", __func__, __LINE__); + } + + return 0; +}; + +static long vvcam_isp_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + pisp_dev = pdriver_dev->private; + //pr_info("%s:isp[%d] pdriver_dev =0x%px\n", __func__,pdriver_dev->device_idx,pdriver_dev); + //pr_info("%s:pisp_dev =0x%px\n", __func__,pisp_dev); + + mutex_lock(&pdriver_dev->vvmutex); + ret = isp_priv_ioctl(pisp_dev, cmd ,(void __user *)arg); + mutex_unlock(&pdriver_dev->vvmutex); + + return ret; +}; + +static int vvcam_isp_release(struct inode * inode, struct file * file) +{ + int ret = 0; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev *pisp_dev; + if ((inode == NULL) || (file == NULL) ) { + printk("%s: %dx\n", __func__, __LINE__); + return 0; + } + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_isp_driver_dev, cdev); + struct device *dev = &pdriver_dev->pdev->dev; + file->private_data = pdriver_dev; + pisp_dev = pdriver_dev->private; + pr_info("enter %s\n", __func__); + isp_irq_destroy_circle_queue(&(pisp_dev->circle_list)); + + ret = pm_runtime_put_sync(dev); + if (ret) { + pr_err("fail to suspen isp %s %d ret = %d\n", __func__, __LINE__, ret); + } + return 0; +}; + +static int vvcam_isp_mmap(struct file *pFile, struct vm_area_struct *vma) +{ + int ret = 0; + + ulong phy_base_addr = 0; + + unsigned long pfn_start = (phy_base_addr >> PAGE_SHIFT) + vma->vm_pgoff; + unsigned long size = vma->vm_end - vma->vm_start; + /*pr_info("phy: 0x%lx, size: 0x%lx\n", pfn_start << PAGE_SHIFT, size);*/ + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + if (remap_pfn_range(vma, vma->vm_start,pfn_start,size, vma->vm_page_prot)) + { + pr_err("-->%s: remap_pfn_range error!\n", __func__); + return -EIO; + } + + return ret; +}; + +static struct file_operations vvcam_isp_fops = { + .owner = THIS_MODULE, + .open = vvcam_isp_open, + .release = vvcam_isp_release, + .unlocked_ioctl = vvcam_isp_ioctl, + .mmap = vvcam_isp_mmap, + .poll = vvnative_isp_poll, +}; + +static int vvcam_isp_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device_node *np; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + struct resource *mem; + + pr_info("enter %s\n", __func__); + + pdev->id = devise_register_index; + if (pdev->id >= VIVCAM_ISP_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_isp_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_isp_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_isp_driver_dev )); + pr_info("%s:isp[%d]: pdriver_dev =0x%px\n", __func__,pdev->id,pdriver_dev); + + pisp_dev = devm_kzalloc(&pdev->dev,sizeof(struct isp_ic_dev), GFP_KERNEL); + if (pisp_dev == NULL) + { + pr_err("%s:alloc struct isp_ic_dev error\n", __func__); + return -ENOMEM; + } + memset(pisp_dev,0,sizeof(struct isp_ic_dev )); + pr_info("%s:isp[%d]: psensor_dev =0x%px\n", __func__,pdev->id,pisp_dev); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pisp_dev->base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(pisp_dev->base)) + return PTR_ERR(pisp_dev->base); + pr_info("%s:isp[%d]: pisp_dev->base=0x%px, phy_addr base=0x%llx\n", __func__, + pdev->id, pisp_dev->base, mem->start); + + pisp_dev->reset = NULL; + pisp_dev->device = &pdev->dev; + + pdriver_dev->private = pisp_dev; + pdriver_dev->device_idx = pdev->id; + mutex_init(&pdriver_dev->vvmutex); + + frame_mark_t *frame_mark = dma_alloc_coherent(&pdev->dev, sizeof(frame_mark_t), + &pisp_dev->frame_mark_info_addr, GFP_KERNEL); + if (frame_mark == NULL ) { + pr_err("dma_alloc_coherent error\n"); + return -1; + } + + printk("isp_frame_mark_info_addr = 0x%lx\n", pisp_dev->frame_mark_info_addr); + + memset(frame_mark, 0, sizeof(frame_mark_t)); + pdriver_dev->frame_mark = frame_mark; + + platform_set_drvdata(pdev, pdriver_dev); + pdriver_dev->pdev = pdev; + pdriver_dev->irq_num[0] = platform_get_irq(pdev, 0); + if (pdriver_dev->irq_num[0] == 0) { + pr_err("%s:isp[%d]: could not map IRQ\n", __func__, pdev->id); + dev_err(&pdev->dev, "could not map IRQ.\n"); + return -ENXIO; + } + pr_info("%s:isp[%d]: pdriver_dev->irq_num[0]=%d\n", __func__, pdev->id, pdriver_dev->irq_num[0]); + + pdriver_dev->irq_num[1] = platform_get_irq(pdev, 1); + if (pdriver_dev->irq_num[1] == 0) { + pr_err("%s:isp[%d]: could not map IRQ\n", __func__, pdev->id); + dev_err(&pdev->dev, "could not map IRQ.\n"); + return -ENXIO; + } + pr_info("%s:isp[%d]: pdriver_dev->irq_num[1]=%d\n", __func__, pdev->id, pdriver_dev->irq_num[1]); + + /*init work queue*/ + INIT_WORK(&pdriver_dev->vvnative_wq, vvnative_isp_work); + + ret = devm_request_irq(&pdev->dev, pdriver_dev->irq_num[0], vvcam_isp_irq, + IRQF_TRIGGER_RISING | IRQF_SHARED, "ISP_IRQ", (char *)pdriver_dev); + if (ret) { + pr_err("%s[%d]:request irq error!\n", __func__, __LINE__); + return ret; + } + + ret = devm_request_irq(&pdev->dev, pdriver_dev->irq_num[1], vvcam_isp_irq, + IRQF_TRIGGER_RISING, "MI_IRQ", (char *)pdriver_dev); + if (ret) { + pr_err("%s[%d]:request irq error!\n", __func__, __LINE__); + return ret; + } + + init_waitqueue_head(&pdriver_dev->irq_wait); + + +/*parse clk info from dts*/ + pdriver_dev->aclk = devm_clk_get(&pdev->dev, "aclk"); + if (IS_ERR(pdriver_dev->aclk)) { + dev_err(&pdev->dev, "failed to get aclk"); + //return -1; + } + pdriver_dev->hclk = devm_clk_get(&pdev->dev, "hclk"); + if (IS_ERR(pdriver_dev->hclk)) { + dev_err(&pdev->dev, "failed to get hclk"); + //return -1; + } + pdriver_dev->isp0_pclk = devm_clk_get(&pdev->dev, "isp0_pclk"); + if (IS_ERR(pdriver_dev->isp0_pclk)) { + dev_err(&pdev->dev, "failed to get isp0_pclk"); + //return -1; + } + pdriver_dev->cclk = devm_clk_get(&pdev->dev, "cclk"); + if (IS_ERR(pdriver_dev->cclk)) { + dev_err(&pdev->dev, "failed to get core_clk"); + //return -1; + } + + pdriver_dev->isp1_pclk = devm_clk_get(&pdev->dev, "isp1_pclk"); + if (IS_ERR(pdriver_dev->isp1_pclk)) { + dev_err(&pdev->dev, "failed to get isp1_pclk"); + //return -1; + } + + if ((devise_register_index == 0)) { + int ret; + if (vvcam_isp_major == 0) { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_ISP_MAXCNT, VIVCAM_ISP_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_isp_major = MAJOR(pdriver_dev->devt); + vvcam_isp_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_isp_major, vvcam_isp_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_ISP_MAXCNT, VIVCAM_ISP_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + vvcam_isp_class = class_create(THIS_MODULE, VIVCAM_ISP_NAME); + if (IS_ERR(vvcam_isp_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_isp_major, vvcam_isp_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_isp_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_isp_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VIVCAM_ISP_NAME, pdev->id); + + struct device *dev = &pdriver_dev->pdev->dev; + pm_runtime_enable(dev); + + ret = vvcam_isp_runtime_resume(dev); + if (ret < 0) { + dev_err(dev, "fail to resume isp\n"); + } + vvcam_isp_runtime_suspend(dev); + if (ret < 0) { + dev_err(dev, "fail to suspend isp\n"); + } + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int vvcam_isp_remove(struct platform_device *pdev) +{ + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + pisp_dev = pdriver_dev->private; + + dma_free_coherent(&pdev->dev, sizeof(*pdriver_dev->frame_mark), + pdriver_dev->frame_mark, pisp_dev->frame_mark_info_addr); + + if (pisp_dev->ut_addr != NULL) { + #define UT_USED_SIZE 0x01000000 + dma_free_coherent(&pdev->dev, UT_USED_SIZE, + pisp_dev->ut_addr, pisp_dev->ut_phy_addr); + } + + free_irq(pdriver_dev->irq_num[0], pdriver_dev); + free_irq(pdriver_dev->irq_num[1], pdriver_dev); + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + + + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_ISP_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + return 0; +} +static const struct of_device_id isp_of_match[] = { + { .compatible = "thead,light-isp", }, + { /* sentinel */ }, +}; + +static struct platform_driver vvcam_isp_driver = { + .probe = vvcam_isp_probe, + .remove = vvcam_isp_remove, + .driver = { + .name = VIVCAM_ISP_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(isp_of_match), + .pm = &vvcam_isp_runtime_pm_ops, + } +}; + +static int __init vvcam_isp_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&vvcam_isp_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit vvcam_isp_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_isp_driver); +} + +module_init(vvcam_isp_init_module); +module_exit(vvcam_isp_exit_module); + +MODULE_DESCRIPTION("ISP"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/omnivision_ov2778/ov2778_driver.c b/vvcam/native/omnivision_ov2778/ov2778_driver.c new file mode 100755 index 0000000..8405286 --- /dev/null +++ b/vvcam/native/omnivision_ov2778/ov2778_driver.c @@ -0,0 +1,440 @@ +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "ov2778_reg_cfg.h" + +#define SENSOR_CLK 51000000 + +static struct vvcam_mode_info pov2778_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_array *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pov2778_mode_info); + + memcpy(pmode_info_arry->modes,pov2778_mode_info,sizeof(pov2778_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pov2778_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pov2778_mode_info[i].index == pmode->index) + { + psensor_mode = &(pov2778_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&ov2778_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&ov2778_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3012, 0x01); + }else + { + ret = sensor_write_reg(ctx, 0x3012, 0x00); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s ov2778_function = +{ + .sensor_name = "ov2778", + .reserve_id = 0x2770, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam/native/omnivision_ov2778/ov2778_driver.h b/vvcam/native/omnivision_ov2778/ov2778_driver.h new file mode 100755 index 0000000..ca508d9 --- /dev/null +++ b/vvcam/native/omnivision_ov2778/ov2778_driver.h @@ -0,0 +1,7 @@ +#ifndef _OMNIVISION_OV2778_H_ +#define _OMNIVISION_OV2778_H_ + +extern struct vvcam_sensor_function_s ov2778_function; + + +#endif diff --git a/vvcam/native/omnivision_ov2778/ov2778_mipi4lane_1080p_30fps_linear.c b/vvcam/native/omnivision_ov2778/ov2778_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..8a386db --- /dev/null +++ b/vvcam/native/omnivision_ov2778/ov2778_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,1827 @@ +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data ov2778_mipi4lane_1080p_30fps_linear_reg[] = { + {0x3000, 0x02}, + {0x3001, 0x28}, + {0x3002, 0x03}, + {0x3003, 0x01}, + {0x3004, 0x05}, + {0x3005, 0x26}, + {0x3006, 0x00}, + {0x3007, 0x07}, + {0x3008, 0x01}, + {0x3009, 0x00}, + {0x300c, 0x6c}, + {0x300e, 0x80}, + {0x300f, 0x00}, + {0x3012, 0x00}, + {0x3013, 0x00}, + {0x3014, 0xc4}, + {0x3015, 0x00}, + {0x3017, 0x00}, + {0x3018, 0x00}, + {0x3019, 0x00}, + {0x301a, 0x00}, + {0x301b, 0x0e}, + {0x301e, 0x17}, + {0x301f, 0xe1}, + {0x3030, 0x02}, + {0x3031, 0x62}, + {0x3032, 0xf0}, + {0x3033, 0x30}, + {0x3034, 0x3f}, + {0x3035, 0x5f}, + {0x3036, 0x02}, + {0x3037, 0x9f}, + {0x3038, 0x04}, + {0x3039, 0xb7}, + {0x303a, 0x04}, + {0x303b, 0x07}, + {0x303c, 0xf0}, + {0x303d, 0x00}, + {0x303e, 0x0b}, + {0x303f, 0xe3}, + {0x3040, 0xf3}, + {0x3041, 0x29}, + {0x3042, 0xf6}, + {0x3043, 0x65}, + {0x3044, 0x06}, + {0x3045, 0x0f}, + {0x3046, 0x59}, + {0x3047, 0x07}, + {0x3048, 0x82}, + {0x3049, 0xcf}, + {0x304a, 0x12}, + {0x304b, 0x40}, + {0x304c, 0x33}, + {0x304d, 0xa4}, + {0x304e, 0x0b}, + {0x304f, 0x3d}, + {0x3050, 0x10}, + {0x3060, 0x00}, + {0x3061, 0x64}, + {0x3062, 0x00}, + {0x3063, 0xe4}, + {0x3066, 0x80}, + {0x3080, 0x00}, + {0x3081, 0x00}, + {0x3082, 0x01}, + {0x3083, 0xe3}, + {0x3084, 0x06}, + {0x3085, 0x00}, + {0x3086, 0x10}, + {0x3087, 0x10}, + {0x3089, 0x00}, + {0x308a, 0x01}, + {0x3093, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x00}, + {0x30aa, 0x00}, + {0x30ab, 0x00}, + {0x30ac, 0x07}, + {0x30ad, 0x90}, + {0x30ae, 0x04}, + {0x30af, 0x48}, + {0x30b0, 0x04}, + {0x30b1, 0x7e}, + {0x30b2, 0x04}, + {0x30b3, 0x65}, + {0x30b4, 0x00}, + {0x30b5, 0x00}, + {0x30b6, 0x00}, + {0x30b7, 0x10}, + {0x30b8, 0x00}, + {0x30b9, 0x02}, + {0x30ba, 0x10}, + {0x30bb, 0x00}, + {0x30bc, 0x00}, + {0x30bd, 0x03}, + {0x30be, 0x5c}, + {0x30bf, 0x00}, + {0x30c0, 0x05}, + {0x30c1, 0x00}, + {0x30c2, 0x20}, + {0x30c3, 0x00}, + {0x30c4, 0x4a}, + {0x30c5, 0x00}, + {0x30c7, 0x00}, + {0x30c8, 0x00}, + {0x30d1, 0x00}, + {0x30d2, 0x00}, + {0x30d3, 0x80}, + {0x30d4, 0x00}, + {0x30d9, 0x09}, + {0x30da, 0x64}, + {0x30dd, 0x00}, + {0x30de, 0x16}, + {0x30df, 0x00}, + {0x30e0, 0x17}, + {0x30e1, 0x00}, + {0x30e2, 0x18}, + {0x30e3, 0x10}, + {0x30e4, 0x04}, + {0x30e5, 0x00}, + {0x30e6, 0x00}, + {0x30e7, 0x00}, + {0x30e8, 0x00}, + {0x30e9, 0x00}, + {0x30ea, 0x00}, + {0x30eb, 0x00}, + {0x30ec, 0x00}, + {0x30ed, 0x00}, + {0x3101, 0x00}, + {0x3102, 0x00}, + {0x3103, 0x00}, + {0x3104, 0x00}, + {0x3105, 0x8c}, + {0x3106, 0x87}, + {0x3107, 0xc0}, + {0x3108, 0x9d}, + {0x3109, 0x8d}, + {0x310a, 0x8d}, + {0x310b, 0x6a}, + {0x310c, 0x3a}, + {0x310d, 0x5a}, + {0x310e, 0x00}, + {0x3120, 0x00}, + {0x3121, 0x00}, + {0x3122, 0x00}, + {0x3123, 0xf0}, + {0x3124, 0x00}, + {0x3125, 0x70}, + {0x3126, 0x1f}, + {0x3127, 0x0f}, + {0x3128, 0x00}, + {0x3129, 0x3a}, + {0x312a, 0x02}, + {0x312b, 0x0f}, + {0x312c, 0x00}, + {0x312d, 0x0f}, + {0x312e, 0x1d}, + {0x312f, 0x00}, + {0x3130, 0x00}, + {0x3131, 0x00}, + {0x3132, 0x00}, + {0x3140, 0x0a}, + {0x3141, 0x03}, + {0x3142, 0x00}, + {0x3143, 0x00}, + {0x3144, 0x00}, + {0x3145, 0x00}, + {0x3146, 0x00}, + {0x3147, 0x00}, + {0x3148, 0x00}, + {0x3149, 0x00}, + {0x314a, 0x00}, + {0x314b, 0x00}, + {0x314c, 0x00}, + {0x314d, 0x00}, + {0x314e, 0x1c}, + {0x314f, 0xff}, + {0x3150, 0xff}, + {0x3151, 0xff}, + {0x3152, 0x10}, + {0x3153, 0x10}, + {0x3154, 0x10}, + {0x3155, 0x00}, + {0x3156, 0x03}, + {0x3157, 0x00}, + {0x3158, 0x0f}, + {0x3159, 0xff}, + {0x315a, 0x01}, + {0x315b, 0x00}, + {0x315c, 0x01}, + {0x315d, 0x00}, + {0x315e, 0x01}, + {0x315f, 0x00}, + {0x3160, 0x00}, + {0x3161, 0x40}, + {0x3162, 0x00}, + {0x3163, 0x40}, + {0x3164, 0x00}, + {0x3165, 0x40}, + {0x3190, 0x08}, + {0x3191, 0x99}, + {0x3193, 0x08}, + {0x3194, 0x13}, + {0x3195, 0x33}, + {0x3196, 0x00}, + {0x3197, 0x10}, + {0x3198, 0x00}, + {0x3199, 0x7f}, + {0x319a, 0x80}, + {0x319b, 0xff}, + {0x319c, 0x80}, + {0x319d, 0xbf}, + {0x319e, 0xc0}, + {0x319f, 0xff}, + {0x31a0, 0x24}, + {0x31a1, 0x55}, + {0x31a2, 0x00}, + {0x31a3, 0x00}, + {0x31a6, 0x00}, + {0x31a7, 0x00}, + {0x31b0, 0x00}, + {0x31b1, 0x00}, + {0x31b2, 0x02}, + {0x31b3, 0x00}, + {0x31b4, 0x00}, + {0x31b5, 0x01}, + {0x31b6, 0x00}, + {0x31b7, 0x00}, + {0x31b8, 0x00}, + {0x31b9, 0x00}, + {0x31ba, 0x00}, + {0x31d0, 0x3c}, + {0x31d1, 0x34}, + {0x31d2, 0x3c}, + {0x31d3, 0x00}, + {0x31d4, 0x2d}, + {0x31d5, 0x00}, + {0x31d6, 0x01}, + {0x31d7, 0x06}, + {0x31d8, 0x00}, + {0x31d9, 0x64}, + {0x31da, 0x00}, + {0x31db, 0x30}, + {0x31dc, 0x04}, + {0x31dd, 0x69}, + {0x31de, 0x0a}, + {0x31df, 0x3c}, + {0x31e0, 0x04}, + {0x31e1, 0x32}, + {0x31e2, 0x00}, + {0x31e3, 0x00}, + {0x31e4, 0x08}, + {0x31e5, 0x80}, + {0x31e6, 0x00}, + {0x31e7, 0x2c}, + {0x31e8, 0x6c}, + {0x31e9, 0xac}, + {0x31ea, 0xec}, + {0x31eb, 0x3f}, + {0x31ec, 0x0f}, + {0x31ed, 0x20}, + {0x31ee, 0x04}, + {0x31ef, 0x48}, + {0x31f0, 0x07}, + {0x31f1, 0x90}, + {0x31f2, 0x04}, + {0x31f3, 0x48}, + {0x31f4, 0x07}, + {0x31f5, 0x90}, + {0x31f6, 0x04}, + {0x31f7, 0x48}, + {0x31f8, 0x07}, + {0x31f9, 0x90}, + {0x31fa, 0x04}, + {0x31fb, 0x48}, + {0x31fd, 0xcb}, + {0x31fe, 0x0f}, + {0x31ff, 0x03}, + {0x3200, 0x00}, + {0x3201, 0xff}, + {0x3202, 0x00}, + {0x3203, 0xff}, + {0x3204, 0xff}, + {0x3205, 0xff}, + {0x3206, 0xff}, + {0x3207, 0xff}, + {0x3208, 0xff}, + {0x3209, 0xff}, + {0x320a, 0xff}, + {0x320b, 0x1b}, + {0x320c, 0x1f}, + {0x320d, 0x1e}, + {0x320e, 0x30}, + {0x320f, 0x2d}, + {0x3210, 0x2c}, + {0x3211, 0x2b}, + {0x3212, 0x2a}, + {0x3213, 0x24}, + {0x3214, 0x22}, + {0x3215, 0x00}, + {0x3216, 0x04}, + {0x3217, 0x2c}, + {0x3218, 0x6c}, + {0x3219, 0xac}, + {0x321a, 0xec}, + {0x321b, 0x00}, + {0x3230, 0x3a}, + {0x3231, 0x00}, + {0x3232, 0x80}, + {0x3233, 0x00}, + {0x3234, 0x10}, + {0x3235, 0xaa}, + {0x3236, 0x55}, + {0x3237, 0x99}, + {0x3238, 0x66}, + {0x3239, 0x08}, + {0x323a, 0x88}, + {0x323b, 0x00}, + {0x323c, 0x00}, + {0x323d, 0x03}, + {0x3250, 0x33}, + {0x3251, 0x00}, + {0x3252, 0x20}, + {0x3253, 0x00}, + {0x3254, 0x00}, + {0x3255, 0x01}, + {0x3256, 0x00}, + {0x3257, 0x00}, + {0x3258, 0x00}, + {0x3270, 0x01}, + {0x3271, 0x60}, + {0x3272, 0xc0}, + {0x3273, 0x00}, + {0x3274, 0x80}, + {0x3275, 0x40}, + {0x3276, 0x02}, + {0x3277, 0x08}, + {0x3278, 0x10}, + {0x3279, 0x04}, + {0x327a, 0x00}, + {0x327b, 0x03}, + {0x327c, 0x10}, + {0x327d, 0x60}, + {0x327e, 0xc0}, + {0x327f, 0x06}, + {0x3288, 0x10}, + {0x3289, 0x00}, + {0x328a, 0x08}, + {0x328b, 0x00}, + {0x328c, 0x04}, + {0x328d, 0x00}, + {0x328e, 0x02}, + {0x328f, 0x00}, + {0x3290, 0x20}, + {0x3291, 0x00}, + {0x3292, 0x10}, + {0x3293, 0x00}, + {0x3294, 0x08}, + {0x3295, 0x00}, + {0x3296, 0x04}, + {0x3297, 0x00}, + {0x3298, 0x40}, + {0x3299, 0x00}, + {0x329a, 0x20}, + {0x329b, 0x00}, + {0x329c, 0x10}, + {0x329d, 0x00}, + {0x329e, 0x08}, + {0x329f, 0x00}, + {0x32a0, 0x7f}, + {0x32a1, 0xff}, + {0x32a2, 0x40}, + {0x32a3, 0x00}, + {0x32a4, 0x20}, + {0x32a5, 0x00}, + {0x32a6, 0x10}, + {0x32a7, 0x00}, + {0x32a8, 0x00}, + {0x32a9, 0x00}, + {0x32aa, 0x00}, + {0x32ab, 0x00}, + {0x32ac, 0x00}, + {0x32ad, 0x00}, + {0x32ae, 0x00}, + {0x32af, 0x00}, + {0x32b0, 0x00}, + {0x32b1, 0x00}, + {0x32b2, 0x00}, + {0x32b3, 0x00}, + {0x32b4, 0x00}, + {0x32b5, 0x00}, + {0x32b6, 0x00}, + {0x32b7, 0x00}, + {0x32b8, 0x00}, + {0x32b9, 0x00}, + {0x32ba, 0x00}, + {0x32bb, 0x00}, + {0x32bc, 0x00}, + {0x32bd, 0x00}, + {0x32be, 0x00}, + {0x32bf, 0x00}, + {0x32c0, 0x00}, + {0x32c1, 0x00}, + {0x32c2, 0x00}, + {0x32c3, 0x00}, + {0x32c4, 0x00}, + {0x32c5, 0x00}, + {0x32c6, 0x00}, + {0x32c7, 0x00}, + {0x32c8, 0x87}, + {0x32c9, 0x00}, + {0x3330, 0x03}, + {0x3331, 0xc8}, + {0x3332, 0x02}, + {0x3333, 0x24}, + {0x3334, 0x00}, + {0x3335, 0x00}, + {0x3336, 0x00}, + {0x3337, 0x00}, + {0x3338, 0x03}, + {0x3339, 0xc8}, + {0x333a, 0x02}, + {0x333b, 0x24}, + {0x333c, 0x00}, + {0x333d, 0x00}, + {0x333e, 0x00}, + {0x333f, 0x00}, + {0x3340, 0x03}, + {0x3341, 0xc8}, + {0x3342, 0x02}, + {0x3343, 0x24}, + {0x3344, 0x00}, + {0x3345, 0x00}, + {0x3346, 0x00}, + {0x3347, 0x00}, + {0x3348, 0x40}, + {0x3349, 0x00}, + {0x334a, 0x00}, + {0x334b, 0x00}, + {0x334c, 0x00}, + {0x334d, 0x00}, + {0x334e, 0x80}, + {0x3360, 0x01}, + {0x3361, 0x00}, + {0x3362, 0x01}, + {0x3363, 0x00}, + {0x3364, 0x01}, + {0x3365, 0x00}, + {0x3366, 0x01}, + {0x3367, 0x00}, + {0x3368, 0x01}, + {0x3369, 0x00}, + {0x336a, 0x01}, + {0x336b, 0x00}, + {0x336c, 0x01}, + {0x336d, 0x00}, + {0x336e, 0x01}, + {0x336f, 0x00}, + {0x3370, 0x01}, + {0x3371, 0x00}, + {0x3372, 0x01}, + {0x3373, 0x00}, + {0x3374, 0x01}, + {0x3375, 0x00}, + {0x3376, 0x01}, + {0x3377, 0x00}, + {0x3378, 0x00}, + {0x3379, 0x00}, + {0x337a, 0x00}, + {0x337b, 0x00}, + {0x337c, 0x00}, + {0x337d, 0x00}, + {0x337e, 0x00}, + {0x337f, 0x00}, + {0x3380, 0x00}, + {0x3381, 0x00}, + {0x3382, 0x00}, + {0x3383, 0x00}, + {0x3384, 0x00}, + {0x3385, 0x00}, + {0x3386, 0x00}, + {0x3387, 0x00}, + {0x3388, 0x00}, + {0x3389, 0x00}, + {0x338a, 0x00}, + {0x338b, 0x00}, + {0x338c, 0x00}, + {0x338d, 0x00}, + {0x338e, 0x00}, + {0x338f, 0x00}, + {0x3390, 0x00}, + {0x3391, 0x00}, + {0x3392, 0x00}, + {0x3393, 0x00}, + {0x3394, 0x00}, + {0x3395, 0x00}, + {0x3396, 0x00}, + {0x3397, 0x00}, + {0x3398, 0x00}, + {0x3399, 0x00}, + {0x339a, 0x00}, + {0x339b, 0x00}, + {0x33b0, 0x00}, + {0x33b1, 0x50}, + {0x33b2, 0x01}, + {0x33b3, 0xff}, + {0x33b4, 0xe0}, + {0x33b5, 0x6b}, + {0x33b6, 0x00}, + {0x33b7, 0x00}, + {0x33b8, 0x00}, + {0x33b9, 0x00}, + {0x33ba, 0x00}, + {0x33bb, 0x1f}, + {0x33bc, 0x01}, + {0x33bd, 0x01}, + {0x33be, 0x01}, + {0x33bf, 0x01}, + {0x33c0, 0x00}, + {0x33c1, 0x00}, + {0x33c2, 0x00}, + {0x33c3, 0x00}, + {0x33e0, 0x14}, + {0x33e1, 0x0f}, + {0x33e2, 0x02}, + {0x33e3, 0x01}, + {0x33e4, 0x01}, + {0x33e5, 0x01}, + {0x33e6, 0x00}, + {0x33e7, 0x04}, + {0x33e8, 0x0c}, + {0x33e9, 0x02}, + {0x33ea, 0x02}, + {0x33eb, 0x02}, + {0x33ec, 0x03}, + {0x33ed, 0x01}, + {0x33ee, 0x02}, + {0x33ef, 0x08}, + {0x33f0, 0x08}, + {0x33f1, 0x04}, + {0x33f2, 0x04}, + {0x33f3, 0x00}, + {0x33f4, 0x03}, + {0x33f5, 0x14}, + {0x33f6, 0x0f}, + {0x33f7, 0x02}, + {0x33f8, 0x01}, + {0x33f9, 0x01}, + {0x33fa, 0x01}, + {0x33fb, 0x00}, + {0x33fc, 0x04}, + {0x33fd, 0x0c}, + {0x33fe, 0x02}, + {0x33ff, 0x02}, + {0x3400, 0x02}, + {0x3401, 0x03}, + {0x3402, 0x01}, + {0x3403, 0x02}, + {0x3404, 0x08}, + {0x3405, 0x08}, + {0x3406, 0x04}, + {0x3407, 0x04}, + {0x3408, 0x00}, + {0x3409, 0x03}, + {0x340a, 0x14}, + {0x340b, 0x0f}, + {0x340c, 0x04}, + {0x340d, 0x02}, + {0x340e, 0x01}, + {0x340f, 0x01}, + {0x3410, 0x00}, + {0x3411, 0x04}, + {0x3412, 0x0c}, + {0x3413, 0x02}, + {0x3414, 0x02}, + {0x3415, 0x02}, + {0x3416, 0x03}, + {0x3417, 0x02}, + {0x3418, 0x05}, + {0x3419, 0x0a}, + {0x341a, 0x08}, + {0x341b, 0x04}, + {0x341c, 0x04}, + {0x341d, 0x00}, + {0x341e, 0x03}, + {0x3440, 0x00}, + {0x3441, 0x00}, + {0x3442, 0x00}, + {0x3443, 0x00}, + {0x3444, 0x02}, + {0x3445, 0xf0}, + {0x3446, 0x02}, + {0x3447, 0x08}, + {0x3448, 0x00}, + {0x3460, 0x40}, + {0x3461, 0x40}, + {0x3462, 0x40}, + {0x3463, 0x40}, + {0x3464, 0x03}, + {0x3465, 0x01}, + {0x3466, 0x01}, + {0x3467, 0x02}, + {0x3468, 0x30}, + {0x3469, 0x00}, + {0x346a, 0x33}, + {0x346b, 0xbf}, + {0x3480, 0x40}, + {0x3481, 0x00}, + {0x3482, 0x00}, + {0x3483, 0x00}, + {0x3484, 0x0d}, + {0x3485, 0x00}, + {0x3486, 0x00}, + {0x3487, 0x00}, + {0x3488, 0x00}, + {0x3489, 0x00}, + {0x348a, 0x00}, + {0x348b, 0x04}, + {0x348c, 0x00}, + {0x348d, 0x01}, + {0x348f, 0x01}, + {0x3030, 0x0a}, + {0x3030, 0x02}, + {0x7000, 0x58}, + {0x7001, 0x7a}, + {0x7002, 0x1a}, + {0x7003, 0xc1}, + {0x7004, 0x03}, + {0x7005, 0xda}, + {0x7006, 0xbd}, + {0x7007, 0x03}, + {0x7008, 0xbd}, + {0x7009, 0x06}, + {0x700a, 0xe6}, + {0x700b, 0xec}, + {0x700c, 0xbc}, + {0x700d, 0xff}, + {0x700e, 0xbc}, + {0x700f, 0x73}, + {0x7010, 0xda}, + {0x7011, 0x72}, + {0x7012, 0x76}, + {0x7013, 0xb6}, + {0x7014, 0xee}, + {0x7015, 0xcf}, + {0x7016, 0xac}, + {0x7017, 0xd0}, + {0x7018, 0xac}, + {0x7019, 0xd1}, + {0x701a, 0x50}, + {0x701b, 0xac}, + {0x701c, 0xd2}, + {0x701d, 0xbc}, + {0x701e, 0x2e}, + {0x701f, 0xb4}, + {0x7020, 0x00}, + {0x7021, 0xdc}, + {0x7022, 0xdf}, + {0x7023, 0xb0}, + {0x7024, 0x6e}, + {0x7025, 0xbd}, + {0x7026, 0x01}, + {0x7027, 0xd7}, + {0x7028, 0xed}, + {0x7029, 0xe1}, + {0x702a, 0x36}, + {0x702b, 0x30}, + {0x702c, 0xd3}, + {0x702d, 0x2e}, + {0x702e, 0x54}, + {0x702f, 0x46}, + {0x7030, 0xbc}, + {0x7031, 0x22}, + {0x7032, 0x66}, + {0x7033, 0xbc}, + {0x7034, 0x24}, + {0x7035, 0x2c}, + {0x7036, 0x28}, + {0x7037, 0xbc}, + {0x7038, 0x3c}, + {0x7039, 0xa1}, + {0x703a, 0xac}, + {0x703b, 0xd8}, + {0x703c, 0xd6}, + {0x703d, 0xb4}, + {0x703e, 0x04}, + {0x703f, 0x46}, + {0x7040, 0xb7}, + {0x7041, 0x04}, + {0x7042, 0xbe}, + {0x7043, 0x08}, + {0x7044, 0xc3}, + {0x7045, 0xd9}, + {0x7046, 0xad}, + {0x7047, 0xc3}, + {0x7048, 0xbc}, + {0x7049, 0x19}, + {0x704a, 0xc1}, + {0x704b, 0x27}, + {0x704c, 0xe7}, + {0x704d, 0x00}, + {0x704e, 0x50}, + {0x704f, 0x20}, + {0x7050, 0xb8}, + {0x7051, 0x02}, + {0x7052, 0xbc}, + {0x7053, 0x17}, + {0x7054, 0xdb}, + {0x7055, 0xc7}, + {0x7056, 0xb8}, + {0x7057, 0x00}, + {0x7058, 0x28}, + {0x7059, 0x54}, + {0x705a, 0xb4}, + {0x705b, 0x14}, + {0x705c, 0xab}, + {0x705d, 0xbe}, + {0x705e, 0x06}, + {0x705f, 0xd8}, + {0x7060, 0xd6}, + {0x7061, 0x00}, + {0x7062, 0xb4}, + {0x7063, 0xc7}, + {0x7064, 0x07}, + {0x7065, 0xb9}, + {0x7066, 0x05}, + {0x7067, 0xee}, + {0x7068, 0xe6}, + {0x7069, 0xad}, + {0x706a, 0xb4}, + {0x706b, 0x26}, + {0x706c, 0x19}, + {0x706d, 0xc1}, + {0x706e, 0x3a}, + {0x706f, 0xc3}, + {0x7070, 0xaf}, + {0x7071, 0x00}, + {0x7072, 0xc0}, + {0x7073, 0x3c}, + {0x7074, 0xc3}, + {0x7075, 0xbe}, + {0x7076, 0xe7}, + {0x7077, 0x00}, + {0x7078, 0x15}, + {0x7079, 0xc2}, + {0x707a, 0x40}, + {0x707b, 0xc3}, + {0x707c, 0xa4}, + {0x707d, 0xc0}, + {0x707e, 0x3c}, + {0x707f, 0x00}, + {0x7080, 0xb9}, + {0x7081, 0x64}, + {0x7082, 0x29}, + {0x7083, 0x00}, + {0x7084, 0xb8}, + {0x7085, 0x12}, + {0x7086, 0xbe}, + {0x7087, 0x01}, + {0x7088, 0xd0}, + {0x7089, 0xbc}, + {0x708a, 0x01}, + {0x708b, 0xac}, + {0x708c, 0x37}, + {0x708d, 0xd2}, + {0x708e, 0xac}, + {0x708f, 0x45}, + {0x7090, 0xad}, + {0x7091, 0x28}, + {0x7092, 0x00}, + {0x7093, 0xb8}, + {0x7094, 0x00}, + {0x7095, 0xbc}, + {0x7096, 0x01}, + {0x7097, 0x36}, + {0x7098, 0xd3}, + {0x7099, 0x30}, + {0x709a, 0x04}, + {0x709b, 0xe0}, + {0x709c, 0xd8}, + {0x709d, 0xb4}, + {0x709e, 0xe9}, + {0x709f, 0x00}, + {0x70a0, 0xbe}, + {0x70a1, 0x05}, + {0x70a2, 0x62}, + {0x70a3, 0x07}, + {0x70a4, 0xb9}, + {0x70a5, 0x05}, + {0x70a6, 0xad}, + {0x70a7, 0xc3}, + {0x70a8, 0xcf}, + {0x70a9, 0x00}, + {0x70aa, 0x15}, + {0x70ab, 0xc2}, + {0x70ac, 0x59}, + {0x70ad, 0xc3}, + {0x70ae, 0xc9}, + {0x70af, 0xc0}, + {0x70b0, 0x55}, + {0x70b1, 0x00}, + {0x70b2, 0x46}, + {0x70b3, 0xa1}, + {0x70b4, 0xb9}, + {0x70b5, 0x64}, + {0x70b6, 0x29}, + {0x70b7, 0x00}, + {0x70b8, 0xb8}, + {0x70b9, 0x02}, + {0x70ba, 0xbe}, + {0x70bb, 0x02}, + {0x70bc, 0xd0}, + {0x70bd, 0xdc}, + {0x70be, 0xac}, + {0x70bf, 0xbc}, + {0x70c0, 0x01}, + {0x70c1, 0x37}, + {0x70c2, 0xac}, + {0x70c3, 0xd2}, + {0x70c4, 0x45}, + {0x70c5, 0xad}, + {0x70c6, 0x28}, + {0x70c7, 0x00}, + {0x70c8, 0xb8}, + {0x70c9, 0x00}, + {0x70ca, 0xbc}, + {0x70cb, 0x01}, + {0x70cc, 0x36}, + {0x70cd, 0x30}, + {0x70ce, 0xe0}, + {0x70cf, 0xd8}, + {0x70d0, 0xb5}, + {0x70d1, 0x0b}, + {0x70d2, 0xd6}, + {0x70d3, 0xbe}, + {0x70d4, 0x07}, + {0x70d5, 0x00}, + {0x70d6, 0x62}, + {0x70d7, 0x07}, + {0x70d8, 0xb9}, + {0x70d9, 0x05}, + {0x70da, 0xad}, + {0x70db, 0xc3}, + {0x70dc, 0xcf}, + {0x70dd, 0x46}, + {0x70de, 0xcd}, + {0x70df, 0x07}, + {0x70e0, 0xcd}, + {0x70e1, 0x00}, + {0x70e2, 0xe3}, + {0x70e3, 0x18}, + {0x70e4, 0xc2}, + {0x70e5, 0xa2}, + {0x70e6, 0xb9}, + {0x70e7, 0x64}, + {0x70e8, 0xd1}, + {0x70e9, 0xdd}, + {0x70ea, 0xac}, + {0x70eb, 0xcf}, + {0x70ec, 0xdf}, + {0x70ed, 0xb5}, + {0x70ee, 0x19}, + {0x70ef, 0x46}, + {0x70f0, 0x50}, + {0x70f1, 0xb6}, + {0x70f2, 0xee}, + {0x70f3, 0xe8}, + {0x70f4, 0xe6}, + {0x70f5, 0xbc}, + {0x70f6, 0x31}, + {0x70f7, 0xe1}, + {0x70f8, 0x36}, + {0x70f9, 0x30}, + {0x70fa, 0xd3}, + {0x70fb, 0x2e}, + {0x70fc, 0x54}, + {0x70fd, 0xbd}, + {0x70fe, 0x03}, + {0x70ff, 0xec}, + {0x7100, 0x2c}, + {0x7101, 0x50}, + {0x7102, 0x20}, + {0x7103, 0x04}, + {0x7104, 0xb8}, + {0x7105, 0x02}, + {0x7106, 0xbc}, + {0x7107, 0x18}, + {0x7108, 0xc7}, + {0x7109, 0xb8}, + {0x710a, 0x00}, + {0x710b, 0x28}, + {0x710c, 0x54}, + {0x710d, 0xbc}, + {0x710e, 0x02}, + {0x710f, 0xb4}, + {0x7110, 0xda}, + {0x7111, 0xbe}, + {0x7112, 0x04}, + {0x7113, 0xd6}, + {0x7114, 0xd8}, + {0x7115, 0xab}, + {0x7116, 0x00}, + {0x7117, 0x62}, + {0x7118, 0x07}, + {0x7119, 0xb9}, + {0x711a, 0x05}, + {0x711b, 0xad}, + {0x711c, 0xc3}, + {0x711d, 0xbc}, + {0x711e, 0xe7}, + {0x711f, 0xb9}, + {0x7120, 0x64}, + {0x7121, 0x29}, + {0x7122, 0x00}, + {0x7123, 0xb8}, + {0x7124, 0x02}, + {0x7125, 0xbe}, + {0x7126, 0x00}, + {0x7127, 0x45}, + {0x7128, 0xad}, + {0x7129, 0xe2}, + {0x712a, 0x28}, + {0x712b, 0x00}, + {0x712c, 0xb8}, + {0x712d, 0x00}, + {0x712e, 0xe0}, + {0x712f, 0xd8}, + {0x7130, 0xb4}, + {0x7131, 0xe9}, + {0x7132, 0xbe}, + {0x7133, 0x03}, + {0x7134, 0x00}, + {0x7135, 0x30}, + {0x7136, 0x62}, + {0x7137, 0x07}, + {0x7138, 0xb9}, + {0x7139, 0x05}, + {0x713a, 0xad}, + {0x713b, 0xc3}, + {0x713c, 0xcf}, + {0x713d, 0x42}, + {0x713e, 0xe4}, + {0x713f, 0xcd}, + {0x7140, 0x07}, + {0x7141, 0xcd}, + {0x7142, 0x00}, + {0x7143, 0x00}, + {0x7144, 0x17}, + {0x7145, 0xc2}, + {0x7146, 0xbb}, + {0x7147, 0xde}, + {0x7148, 0xcf}, + {0x7149, 0xdf}, + {0x714a, 0xac}, + {0x714b, 0xd1}, + {0x714c, 0x44}, + {0x714d, 0xac}, + {0x714e, 0xb9}, + {0x714f, 0x76}, + {0x7150, 0xb8}, + {0x7151, 0x08}, + {0x7152, 0xb6}, + {0x7153, 0xfe}, + {0x7154, 0xb4}, + {0x7155, 0xca}, + {0x7156, 0xd6}, + {0x7157, 0xd8}, + {0x7158, 0xab}, + {0x7159, 0x00}, + {0x715a, 0xe1}, + {0x715b, 0x36}, + {0x715c, 0x30}, + {0x715d, 0xd3}, + {0x715e, 0xbc}, + {0x715f, 0x29}, + {0x7160, 0xb4}, + {0x7161, 0x1f}, + {0x7162, 0xaa}, + {0x7163, 0xbd}, + {0x7164, 0x01}, + {0x7165, 0xb8}, + {0x7166, 0x0c}, + {0x7167, 0x45}, + {0x7168, 0xa4}, + {0x7169, 0xbd}, + {0x716a, 0x03}, + {0x716b, 0xec}, + {0x716c, 0xbc}, + {0x716d, 0x3d}, + {0x716e, 0xc3}, + {0x716f, 0xcf}, + {0x7170, 0x42}, + {0x7171, 0xb8}, + {0x7172, 0x00}, + {0x7173, 0xe4}, + {0x7174, 0xd5}, + {0x7175, 0x00}, + {0x7176, 0xb6}, + {0x7177, 0x00}, + {0x7178, 0x74}, + {0x7179, 0xbd}, + {0x717a, 0x03}, + {0x717b, 0xb5}, + {0x717c, 0x39}, + {0x717d, 0x40}, + {0x717e, 0x58}, + {0x717f, 0xdd}, + {0x7180, 0x19}, + {0x7181, 0xc1}, + {0x7182, 0xc8}, + {0x7183, 0xbd}, + {0x7184, 0x06}, + {0x7185, 0x17}, + {0x7186, 0xc1}, + {0x7187, 0xc6}, + {0x7188, 0xe8}, + {0x7189, 0x00}, + {0x718a, 0xc0}, + {0x718b, 0xc8}, + {0x718c, 0xe6}, + {0x718d, 0x95}, + {0x718e, 0x15}, + {0x718f, 0x00}, + {0x7190, 0xbc}, + {0x7191, 0x19}, + {0x7192, 0xb9}, + {0x7193, 0xf6}, + {0x7194, 0x14}, + {0x7195, 0xc1}, + {0x7196, 0xd0}, + {0x7197, 0xd1}, + {0x7198, 0xac}, + {0x7199, 0x37}, + {0x719a, 0xbc}, + {0x719b, 0x35}, + {0x719c, 0x36}, + {0x719d, 0x30}, + {0x719e, 0xe1}, + {0x719f, 0xd3}, + {0x71a0, 0x7a}, + {0x71a1, 0xb6}, + {0x71a2, 0x0c}, + {0x71a3, 0xff}, + {0x71a4, 0xb4}, + {0x71a5, 0xc7}, + {0x71a6, 0xd9}, + {0x71a7, 0x00}, + {0x71a8, 0xbd}, + {0x71a9, 0x01}, + {0x71aa, 0x56}, + {0x71ab, 0xc0}, + {0x71ac, 0xda}, + {0x71ad, 0xb4}, + {0x71ae, 0x1f}, + {0x71af, 0x56}, + {0x71b0, 0xaa}, + {0x71b1, 0xbc}, + {0x71b2, 0x08}, + {0x71b3, 0x00}, + {0x71b4, 0x57}, + {0x71b5, 0xe8}, + {0x71b6, 0xb5}, + {0x71b7, 0x36}, + {0x71b8, 0x00}, + {0x71b9, 0x54}, + {0x71ba, 0xe7}, + {0x71bb, 0xc8}, + {0x71bc, 0xb4}, + {0x71bd, 0x1f}, + {0x71be, 0x56}, + {0x71bf, 0xaa}, + {0x71c0, 0xbc}, + {0x71c1, 0x08}, + {0x71c2, 0x57}, + {0x71c3, 0x00}, + {0x71c4, 0xb5}, + {0x71c5, 0x36}, + {0x71c6, 0x00}, + {0x71c7, 0x54}, + {0x71c8, 0xc8}, + {0x71c9, 0xb5}, + {0x71ca, 0x18}, + {0x71cb, 0xd9}, + {0x71cc, 0x00}, + {0x71cd, 0xbd}, + {0x71ce, 0x01}, + {0x71cf, 0x56}, + {0x71d0, 0x08}, + {0x71d1, 0x57}, + {0x71d2, 0xe8}, + {0x71d3, 0xb4}, + {0x71d4, 0x42}, + {0x71d5, 0x00}, + {0x71d6, 0x54}, + {0x71d7, 0xe7}, + {0x71d8, 0xc8}, + {0x71d9, 0xab}, + {0x71da, 0x00}, + {0x71db, 0x66}, + {0x71dc, 0x62}, + {0x71dd, 0x06}, + {0x71de, 0x74}, + {0x71df, 0xb9}, + {0x71e0, 0x05}, + {0x71e1, 0xb7}, + {0x71e2, 0x14}, + {0x71e3, 0x0e}, + {0x71e4, 0xb7}, + {0x71e5, 0x04}, + {0x71e6, 0xc8}, + {0x7600, 0x04}, + {0x7601, 0x80}, + {0x7602, 0x07}, + {0x7603, 0x44}, + {0x7604, 0x05}, + {0x7605, 0x33}, + {0x7606, 0x0f}, + {0x7607, 0x00}, + {0x7608, 0x07}, + {0x7609, 0x40}, + {0x760a, 0x04}, + {0x760b, 0xe5}, + {0x760c, 0x06}, + {0x760d, 0x50}, + {0x760e, 0x04}, + {0x760f, 0xe4}, + {0x7610, 0x00}, + {0x7611, 0x00}, + {0x7612, 0x06}, + {0x7613, 0x5c}, + {0x7614, 0x00}, + {0x7615, 0x0f}, + {0x7616, 0x06}, + {0x7617, 0x1c}, + {0x7618, 0x00}, + {0x7619, 0x02}, + {0x761a, 0x06}, + {0x761b, 0xa2}, + {0x761c, 0x00}, + {0x761d, 0x01}, + {0x761e, 0x06}, + {0x761f, 0xae}, + {0x7620, 0x00}, + {0x7621, 0x0e}, + {0x7622, 0x05}, + {0x7623, 0x30}, + {0x7624, 0x07}, + {0x7625, 0x00}, + {0x7626, 0x0f}, + {0x7627, 0x00}, + {0x7628, 0x04}, + {0x7629, 0xe5}, + {0x762a, 0x05}, + {0x762b, 0x33}, + {0x762c, 0x06}, + {0x762d, 0x12}, + {0x762e, 0x00}, + {0x762f, 0x01}, + {0x7630, 0x06}, + {0x7631, 0x52}, + {0x7632, 0x00}, + {0x7633, 0x01}, + {0x7634, 0x06}, + {0x7635, 0x5e}, + {0x7636, 0x04}, + {0x7637, 0xe4}, + {0x7638, 0x00}, + {0x7639, 0x01}, + {0x763a, 0x05}, + {0x763b, 0x30}, + {0x763c, 0x0f}, + {0x763d, 0x00}, + {0x763e, 0x06}, + {0x763f, 0xa6}, + {0x7640, 0x00}, + {0x7641, 0x02}, + {0x7642, 0x06}, + {0x7643, 0x26}, + {0x7644, 0x00}, + {0x7645, 0x02}, + {0x7646, 0x05}, + {0x7647, 0x33}, + {0x7648, 0x06}, + {0x7649, 0x20}, + {0x764a, 0x0f}, + {0x764b, 0x00}, + {0x764c, 0x06}, + {0x764d, 0x56}, + {0x764e, 0x00}, + {0x764f, 0x02}, + {0x7650, 0x06}, + {0x7651, 0x16}, + {0x7652, 0x05}, + {0x7653, 0x33}, + {0x7654, 0x06}, + {0x7655, 0x10}, + {0x7656, 0x0f}, + {0x7657, 0x00}, + {0x7658, 0x06}, + {0x7659, 0x10}, + {0x765a, 0x0f}, + {0x765b, 0x00}, + {0x765c, 0x06}, + {0x765d, 0x20}, + {0x765e, 0x0f}, + {0x765f, 0x00}, + {0x7660, 0x00}, + {0x7661, 0x00}, + {0x7662, 0x00}, + {0x7663, 0x02}, + {0x7664, 0x04}, + {0x7665, 0xe5}, + {0x7666, 0x04}, + {0x7667, 0xe4}, + {0x7668, 0x0f}, + {0x7669, 0x00}, + {0x766a, 0x00}, + {0x766b, 0x00}, + {0x766c, 0x00}, + {0x766d, 0x01}, + {0x766e, 0x04}, + {0x766f, 0xe5}, + {0x7670, 0x04}, + {0x7671, 0xe4}, + {0x7672, 0x0f}, + {0x7673, 0x00}, + {0x7674, 0x00}, + {0x7675, 0x02}, + {0x7676, 0x04}, + {0x7677, 0xe4}, + {0x7678, 0x00}, + {0x7679, 0x02}, + {0x767a, 0x04}, + {0x767b, 0xc4}, + {0x767c, 0x00}, + {0x767d, 0x02}, + {0x767e, 0x04}, + {0x767f, 0xc4}, + {0x7680, 0x05}, + {0x7681, 0x83}, + {0x7682, 0x0f}, + {0x7683, 0x00}, + {0x7684, 0x00}, + {0x7685, 0x02}, + {0x7686, 0x04}, + {0x7687, 0xe4}, + {0x7688, 0x00}, + {0x7689, 0x02}, + {0x768a, 0x04}, + {0x768b, 0xc4}, + {0x768c, 0x00}, + {0x768d, 0x02}, + {0x768e, 0x04}, + {0x768f, 0xc4}, + {0x7690, 0x05}, + {0x7691, 0x83}, + {0x7692, 0x03}, + {0x7693, 0x0b}, + {0x7694, 0x05}, + {0x7695, 0x83}, + {0x7696, 0x00}, + {0x7697, 0x07}, + {0x7698, 0x05}, + {0x7699, 0x03}, + {0x769a, 0x00}, + {0x769b, 0x05}, + {0x769c, 0x05}, + {0x769d, 0x32}, + {0x769e, 0x05}, + {0x769f, 0x30}, + {0x76a0, 0x00}, + {0x76a1, 0x02}, + {0x76a2, 0x05}, + {0x76a3, 0x78}, + {0x76a4, 0x00}, + {0x76a5, 0x01}, + {0x76a6, 0x05}, + {0x76a7, 0x7c}, + {0x76a8, 0x03}, + {0x76a9, 0x9a}, + {0x76aa, 0x05}, + {0x76ab, 0x83}, + {0x76ac, 0x00}, + {0x76ad, 0x04}, + {0x76ae, 0x05}, + {0x76af, 0x03}, + {0x76b0, 0x00}, + {0x76b1, 0x03}, + {0x76b2, 0x05}, + {0x76b3, 0x32}, + {0x76b4, 0x05}, + {0x76b5, 0x30}, + {0x76b6, 0x00}, + {0x76b7, 0x02}, + {0x76b8, 0x05}, + {0x76b9, 0x78}, + {0x76ba, 0x00}, + {0x76bb, 0x01}, + {0x76bc, 0x05}, + {0x76bd, 0x7c}, + {0x76be, 0x03}, + {0x76bf, 0x99}, + {0x76c0, 0x05}, + {0x76c1, 0x83}, + {0x76c2, 0x00}, + {0x76c3, 0x03}, + {0x76c4, 0x05}, + {0x76c5, 0x03}, + {0x76c6, 0x00}, + {0x76c7, 0x01}, + {0x76c8, 0x05}, + {0x76c9, 0x32}, + {0x76ca, 0x05}, + {0x76cb, 0x30}, + {0x76cc, 0x00}, + {0x76cd, 0x02}, + {0x76ce, 0x05}, + {0x76cf, 0x78}, + {0x76d0, 0x00}, + {0x76d1, 0x01}, + {0x76d2, 0x05}, + {0x76d3, 0x7c}, + {0x76d4, 0x03}, + {0x76d5, 0x98}, + {0x76d6, 0x05}, + {0x76d7, 0x83}, + {0x76d8, 0x00}, + {0x76d9, 0x00}, + {0x76da, 0x05}, + {0x76db, 0x03}, + {0x76dc, 0x00}, + {0x76dd, 0x01}, + {0x76de, 0x05}, + {0x76df, 0x32}, + {0x76e0, 0x05}, + {0x76e1, 0x30}, + {0x76e2, 0x00}, + {0x76e3, 0x02}, + {0x76e4, 0x05}, + {0x76e5, 0x78}, + {0x76e6, 0x00}, + {0x76e7, 0x01}, + {0x76e8, 0x05}, + {0x76e9, 0x7c}, + {0x76ea, 0x03}, + {0x76eb, 0x97}, + {0x76ec, 0x05}, + {0x76ed, 0x83}, + {0x76ee, 0x00}, + {0x76ef, 0x00}, + {0x76f0, 0x05}, + {0x76f1, 0x03}, + {0x76f2, 0x05}, + {0x76f3, 0x32}, + {0x76f4, 0x05}, + {0x76f5, 0x30}, + {0x76f6, 0x00}, + {0x76f7, 0x02}, + {0x76f8, 0x05}, + {0x76f9, 0x78}, + {0x76fa, 0x00}, + {0x76fb, 0x01}, + {0x76fc, 0x05}, + {0x76fd, 0x7c}, + {0x76fe, 0x03}, + {0x76ff, 0x96}, + {0x7700, 0x05}, + {0x7701, 0x83}, + {0x7702, 0x05}, + {0x7703, 0x03}, + {0x7704, 0x05}, + {0x7705, 0x32}, + {0x7706, 0x05}, + {0x7707, 0x30}, + {0x7708, 0x00}, + {0x7709, 0x02}, + {0x770a, 0x05}, + {0x770b, 0x78}, + {0x770c, 0x00}, + {0x770d, 0x01}, + {0x770e, 0x05}, + {0x770f, 0x7c}, + {0x7710, 0x03}, + {0x7711, 0x95}, + {0x7712, 0x05}, + {0x7713, 0x83}, + {0x7714, 0x05}, + {0x7715, 0x03}, + {0x7716, 0x05}, + {0x7717, 0x32}, + {0x7718, 0x05}, + {0x7719, 0x30}, + {0x771a, 0x00}, + {0x771b, 0x02}, + {0x771c, 0x05}, + {0x771d, 0x78}, + {0x771e, 0x00}, + {0x771f, 0x01}, + {0x7720, 0x05}, + {0x7721, 0x7c}, + {0x7722, 0x03}, + {0x7723, 0x94}, + {0x7724, 0x05}, + {0x7725, 0x83}, + {0x7726, 0x00}, + {0x7727, 0x01}, + {0x7728, 0x05}, + {0x7729, 0x03}, + {0x772a, 0x00}, + {0x772b, 0x01}, + {0x772c, 0x05}, + {0x772d, 0x32}, + {0x772e, 0x05}, + {0x772f, 0x30}, + {0x7730, 0x00}, + {0x7731, 0x02}, + {0x7732, 0x05}, + {0x7733, 0x78}, + {0x7734, 0x00}, + {0x7735, 0x01}, + {0x7736, 0x05}, + {0x7737, 0x7c}, + {0x7738, 0x03}, + {0x7739, 0x93}, + {0x773a, 0x05}, + {0x773b, 0x83}, + {0x773c, 0x00}, + {0x773d, 0x00}, + {0x773e, 0x05}, + {0x773f, 0x03}, + {0x7740, 0x00}, + {0x7741, 0x00}, + {0x7742, 0x05}, + {0x7743, 0x32}, + {0x7744, 0x05}, + {0x7745, 0x30}, + {0x7746, 0x00}, + {0x7747, 0x02}, + {0x7748, 0x05}, + {0x7749, 0x78}, + {0x774a, 0x00}, + {0x774b, 0x01}, + {0x774c, 0x05}, + {0x774d, 0x7c}, + {0x774e, 0x03}, + {0x774f, 0x92}, + {0x7750, 0x05}, + {0x7751, 0x83}, + {0x7752, 0x05}, + {0x7753, 0x03}, + {0x7754, 0x00}, + {0x7755, 0x00}, + {0x7756, 0x05}, + {0x7757, 0x32}, + {0x7758, 0x05}, + {0x7759, 0x30}, + {0x775a, 0x00}, + {0x775b, 0x02}, + {0x775c, 0x05}, + {0x775d, 0x78}, + {0x775e, 0x00}, + {0x775f, 0x01}, + {0x7760, 0x05}, + {0x7761, 0x7c}, + {0x7762, 0x03}, + {0x7763, 0x91}, + {0x7764, 0x05}, + {0x7765, 0x83}, + {0x7766, 0x05}, + {0x7767, 0x03}, + {0x7768, 0x05}, + {0x7769, 0x32}, + {0x776a, 0x05}, + {0x776b, 0x30}, + {0x776c, 0x00}, + {0x776d, 0x02}, + {0x776e, 0x05}, + {0x776f, 0x78}, + {0x7770, 0x00}, + {0x7771, 0x01}, + {0x7772, 0x05}, + {0x7773, 0x7c}, + {0x7774, 0x03}, + {0x7775, 0x90}, + {0x7776, 0x05}, + {0x7777, 0x83}, + {0x7778, 0x05}, + {0x7779, 0x03}, + {0x777a, 0x05}, + {0x777b, 0x32}, + {0x777c, 0x05}, + {0x777d, 0x30}, + {0x777e, 0x00}, + {0x777f, 0x02}, + {0x7780, 0x05}, + {0x7781, 0x78}, + {0x7782, 0x00}, + {0x7783, 0x01}, + {0x7784, 0x05}, + {0x7785, 0x7c}, + {0x7786, 0x02}, + {0x7787, 0x90}, + {0x7788, 0x05}, + {0x7789, 0x03}, + {0x778a, 0x07}, + {0x778b, 0x00}, + {0x778c, 0x0f}, + {0x778d, 0x00}, + {0x778e, 0x08}, + {0x778f, 0x30}, + {0x7790, 0x08}, + {0x7791, 0xee}, + {0x7792, 0x0f}, + {0x7793, 0x00}, + {0x7794, 0x05}, + {0x7795, 0x33}, + {0x7796, 0x04}, + {0x7797, 0xe5}, + {0x7798, 0x06}, + {0x7799, 0x52}, + {0x779a, 0x04}, + {0x779b, 0xe4}, + {0x779c, 0x00}, + {0x779d, 0x00}, + {0x779e, 0x06}, + {0x779f, 0x5e}, + {0x77a0, 0x00}, + {0x77a1, 0x0f}, + {0x77a2, 0x06}, + {0x77a3, 0x1e}, + {0x77a4, 0x00}, + {0x77a5, 0x02}, + {0x77a6, 0x06}, + {0x77a7, 0xa2}, + {0x77a8, 0x00}, + {0x77a9, 0x01}, + {0x77aa, 0x06}, + {0x77ab, 0xae}, + {0x77ac, 0x00}, + {0x77ad, 0x03}, + {0x77ae, 0x05}, + {0x77af, 0x30}, + {0x77b0, 0x09}, + {0x77b1, 0x19}, + {0x77b2, 0x0f}, + {0x77b3, 0x00}, + {0x77b4, 0x05}, + {0x77b5, 0x33}, + {0x77b6, 0x04}, + {0x77b7, 0xe5}, + {0x77b8, 0x06}, + {0x77b9, 0x52}, + {0x77ba, 0x04}, + {0x77bb, 0xe4}, + {0x77bc, 0x00}, + {0x77bd, 0x00}, + {0x77be, 0x06}, + {0x77bf, 0x5e}, + {0x77c0, 0x00}, + {0x77c1, 0x0f}, + {0x77c2, 0x06}, + {0x77c3, 0x1e}, + {0x77c4, 0x00}, + {0x77c5, 0x02}, + {0x77c6, 0x06}, + {0x77c7, 0xa2}, + {0x77c8, 0x00}, + {0x77c9, 0x01}, + {0x77ca, 0x06}, + {0x77cb, 0xae}, + {0x77cc, 0x00}, + {0x77cd, 0x03}, + {0x77ce, 0x05}, + {0x77cf, 0x30}, + {0x77d0, 0x0f}, + {0x77d1, 0x00}, + {0x77d2, 0x00}, + {0x77d3, 0x00}, + {0x77d4, 0x00}, + {0x77d5, 0x02}, + {0x77d6, 0x04}, + {0x77d7, 0xe5}, + {0x77d8, 0x04}, + {0x77d9, 0xe4}, + {0x77da, 0x05}, + {0x77db, 0x33}, + {0x77dc, 0x07}, + {0x77dd, 0x10}, + {0x77de, 0x00}, + {0x77df, 0x00}, + {0x77e0, 0x01}, + {0x77e1, 0xbb}, + {0x77e2, 0x00}, + {0x77e3, 0x00}, + {0x77e4, 0x01}, + {0x77e5, 0xaa}, + {0x77e6, 0x00}, + {0x77e7, 0x00}, + {0x77e8, 0x01}, + {0x77e9, 0x99}, + {0x77ea, 0x00}, + {0x77eb, 0x00}, + {0x77ec, 0x01}, + {0x77ed, 0x88}, + {0x77ee, 0x00}, + {0x77ef, 0x00}, + {0x77f0, 0x01}, + {0x77f1, 0x77}, + {0x77f2, 0x00}, + {0x77f3, 0x00}, + {0x77f4, 0x01}, + {0x77f5, 0x66}, + {0x77f6, 0x00}, + {0x77f7, 0x00}, + {0x77f8, 0x01}, + {0x77f9, 0x55}, + {0x77fa, 0x00}, + {0x77fb, 0x00}, + {0x77fc, 0x01}, + {0x77fd, 0x44}, + {0x77fe, 0x00}, + {0x77ff, 0x00}, + {0x7800, 0x01}, + {0x7801, 0x33}, + {0x7802, 0x00}, + {0x7803, 0x00}, + {0x7804, 0x01}, + {0x7805, 0x22}, + {0x7806, 0x00}, + {0x7807, 0x00}, + {0x7808, 0x01}, + {0x7809, 0x11}, + {0x780a, 0x00}, + {0x780b, 0x00}, + {0x780c, 0x01}, + {0x780d, 0x00}, + {0x780e, 0x01}, + {0x780f, 0xff}, + {0x7810, 0x07}, + {0x7811, 0x00}, + {0x7812, 0x02}, + {0x7813, 0xa0}, + {0x7814, 0x0f}, + {0x7815, 0x00}, + {0x7816, 0x08}, + {0x7817, 0x35}, + {0x7818, 0x06}, + {0x7819, 0x52}, + {0x781a, 0x04}, + {0x781b, 0xe4}, + {0x781c, 0x00}, + {0x781d, 0x00}, + {0x781e, 0x06}, + {0x781f, 0x5e}, + {0x7820, 0x05}, + {0x7821, 0x33}, + {0x7822, 0x09}, + {0x7823, 0x19}, + {0x7824, 0x06}, + {0x7825, 0x1e}, + {0x7826, 0x05}, + {0x7827, 0x33}, + {0x7828, 0x00}, + {0x7829, 0x01}, + {0x782a, 0x06}, + {0x782b, 0x24}, + {0x782c, 0x06}, + {0x782d, 0x20}, + {0x782e, 0x0f}, + {0x782f, 0x00}, + {0x7830, 0x08}, + {0x7831, 0x35}, + {0x7832, 0x07}, + {0x7833, 0x10}, + {0x7834, 0x00}, + {0x7835, 0x00}, + {0x7836, 0x01}, + {0x7837, 0xbb}, + {0x7838, 0x00}, + {0x7839, 0x00}, + {0x783a, 0x01}, + {0x783b, 0xaa}, + {0x783c, 0x00}, + {0x783d, 0x00}, + {0x783e, 0x01}, + {0x783f, 0x99}, + {0x7840, 0x00}, + {0x7841, 0x00}, + {0x7842, 0x01}, + {0x7843, 0x88}, + {0x7844, 0x00}, + {0x7845, 0x00}, + {0x7846, 0x01}, + {0x7847, 0x77}, + {0x7848, 0x00}, + {0x7849, 0x00}, + {0x784a, 0x01}, + {0x784b, 0x66}, + {0x784c, 0x00}, + {0x784d, 0x00}, + {0x784e, 0x01}, + {0x784f, 0x55}, + {0x7850, 0x00}, + {0x7851, 0x00}, + {0x7852, 0x01}, + {0x7853, 0x44}, + {0x7854, 0x00}, + {0x7855, 0x00}, + {0x7856, 0x01}, + {0x7857, 0x33}, + {0x7858, 0x00}, + {0x7859, 0x00}, + {0x785a, 0x01}, + {0x785b, 0x22}, + {0x785c, 0x00}, + {0x785d, 0x00}, + {0x785e, 0x01}, + {0x785f, 0x11}, + {0x7860, 0x00}, + {0x7861, 0x00}, + {0x7862, 0x01}, + {0x7863, 0x00}, + {0x7864, 0x07}, + {0x7865, 0x00}, + {0x7866, 0x01}, + {0x7867, 0xff}, + {0x7868, 0x02}, + {0x7869, 0xa0}, + {0x786a, 0x0f}, + {0x786b, 0x00}, + {0x786c, 0x08}, + {0x786d, 0x3a}, + {0x786e, 0x08}, + {0x786f, 0x6a}, + {0x7870, 0x0f}, + {0x7871, 0x00}, + {0x7872, 0x04}, + {0x7873, 0xc0}, + {0x7874, 0x09}, + {0x7875, 0x19}, + {0x7876, 0x04}, + {0x7877, 0x99}, + {0x7878, 0x07}, + {0x7879, 0x14}, + {0x787a, 0x00}, + {0x787b, 0x01}, + {0x787c, 0x04}, + {0x787d, 0xa4}, + {0x787e, 0x00}, + {0x787f, 0x07}, + {0x7880, 0x04}, + {0x7881, 0xa6}, + {0x7882, 0x00}, + {0x7883, 0x00}, + {0x7884, 0x04}, + {0x7885, 0xa0}, + {0x7886, 0x04}, + {0x7887, 0x80}, + {0x7888, 0x04}, + {0x7889, 0x00}, + {0x788a, 0x05}, + {0x788b, 0x03}, + {0x788c, 0x06}, + {0x788d, 0x00}, + {0x788e, 0x0f}, + {0x788f, 0x00}, + {0x7890, 0x0f}, + {0x7891, 0x00}, + {0x7892, 0x0f}, + {0x7893, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x05}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x88}, + {0x30ae, 0x04}, + {0x30af, 0x40}, + {0x30b0, 0x0d}, + {0x30b1, 0xde}, + {0x30b2, 0x04}, + {0x30b3, 0x66}, + {0x30b6, 0x01}, + {0x30b7, 0x15}, + {0x3196, 0x00}, + {0x3197, 0x0a}, + {0x3195, 0x29}, + {0x315a, 0x02}, + {0x315b, 0x00}, + {0x30bb, 0x40}, + {0x3250, 0xf7}, + {0x30a8, 0x00}, + {0x30a9, 0x04}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x80}, + {0x30ae, 0x04}, + {0x30af, 0x38}, + {0x3012, 0x01}, +}; + +struct vvcam_sccb_array ov2778_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(ov2778_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = ov2778_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam/native/omnivision_ov2778/ov2778_reg_cfg.h b/vvcam/native/omnivision_ov2778/ov2778_reg_cfg.h new file mode 100755 index 0000000..f957cb9 --- /dev/null +++ b/vvcam/native/omnivision_ov2778/ov2778_reg_cfg.h @@ -0,0 +1,6 @@ +#ifndef _OV2778_REG_CFG_H_ +#define _OV2778_REG_CFG_H_ + +extern struct vvcam_sccb_array ov2778_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam/native/sensor/Makefile b/vvcam/native/sensor/Makefile new file mode 100755 index 0000000..38554e1 --- /dev/null +++ b/vvcam/native/sensor/Makefile @@ -0,0 +1,92 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_sensor + +obj-m +=$(TARGET).o +$(TARGET)-objs += vvcam_sensor_driver.o +$(TARGET)-objs += sensor_ioctl.o +$(TARGET)-objs += vvcam_sensor_sysfs.o + + +EXTRA_CFLAGS += -I$(PWD)/../../common + +ifeq ($(SENSR0_TYPE), ov2775) +$(TARGET)-objs += ./omnivision_ov2775/ov2775_driver.o +$(TARGET)-objs += ./omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.o +EXTRA_CFLAGS += -I$(PWD)/omnivision_ov2775 +EXTRA_CFLAGS += -DSENSR0_FUNCTION=ov2775_function +endif + +ifeq ($(SENSR1_TYPE), ov2775) +#$(TARGET)-objs += ./omnivision_ov2775/ov2775_driver.o +#$(TARGET)-objs += ./omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.o +#EXTRA_CFLAGS += -I$(PWD)/omnivision_ov2775 +EXTRA_CFLAGS += -DSENSR1_FUNCTION=ov2775_function +endif + +ifeq ($(SENSR0_TYPE), imx334) +$(TARGET)-objs += ./sony_imx334/imx334_driver.o +$(TARGET)-objs += ./sony_imx334/imx334_mipi4lane_1080p_30fps_linear.o +EXTRA_CFLAGS += -I$(PWD)/sony_imx334 +EXTRA_CFLAGS += -DSENSR0_FUNCTION=imx334_function +endif + +ifeq ($(SENSR1_TYPE), imx334) +#$(TARGET)-objs += ./omnivision_ov5693/ov2775_driver.o +#$(TARGET)-objs += ./omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.o +#EXTRA_CFLAGS += -I$(PWD)/omnivision_ov2775 +EXTRA_CFLAGS += -DSENSR1_FUNCTION=imx334_function +endif + +ifeq ($(SENSR0_TYPE), ov5693) +$(TARGET)-objs += ./omnivision_ov5693/ov5693_driver.o +$(TARGET)-objs += ./omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.o +EXTRA_CFLAGS += -I$(PWD)/omnivision_ov5693 +EXTRA_CFLAGS += -DSENSR0_FUNCTION=ov5693_function +endif + +ifeq ($(SENSR1_TYPE), ov5693) +#$(TARGET)-objs += ./omnivision_ov5693/ov5693_driver.o +#$(TARGET)-objs += ./omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.o +#EXTRA_CFLAGS += -I$(PWD)/omnivision_ov5693 +EXTRA_CFLAGS += -DSENSR1_FUNCTION=ov5693_function +endif + + +ifeq ($(SENSR0_TYPE), imx290) +$(TARGET)-objs += ./sony_imx290/imx290_driver.o +$(TARGET)-objs += ./sony_imx290/imx290_mipi4lane_1080p_30fps_linear.o +EXTRA_CFLAGS += -I$(PWD)/sony_imx290 +EXTRA_CFLAGS += -DSENSR0_FUNCTION=imx290_function +endif + +ifeq ($(SENSR1_TYPE), imx290) +#$(TARGET)-objs += ./omnivision_ov5693/ov5693_driver.o +#$(TARGET)-objs += ./omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.o +#EXTRA_CFLAGS += -I$(PWD)/omnivision_ov5693 +EXTRA_CFLAGS += -DSENSR1_FUNCTION=imx290_function +endif + +ifeq ($(PLATFORM), gen6) +$(TARGET)-objs += ./platform/platform_gen6_driver.o +EXTRA_CFLAGS += -I$(PWD)/platform +endif + +EXTRA_CFLAGS += -DSENSR0_TYPE +EXTRA_CFLAGS += -DSENSR1_TYPE + +EXTRA_CFLAGS += -I$(PWD)/ + +PWD :=$(shell pwd) + +$(info YANDONG KERNEL=$(KERNEL)) +$(info YANDONG KERNEL_SRC=$(KERNEL_SRC)) + +all: + make V=1 -C $(KERNEL_SRC) M=$(PWD) modules +modules_install: + make V=1 -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL_SRC) M=`pwd` clean + diff --git a/vvcam/native/sensor/omnivision_os02k10/os02k10_driver.c b/vvcam/native/sensor/omnivision_os02k10/os02k10_driver.c new file mode 100755 index 0000000..d78d9a7 --- /dev/null +++ b/vvcam/native/sensor/omnivision_os02k10/os02k10_driver.c @@ -0,0 +1,493 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "os02k10_reg_cfg.h" + +#define SENSOR_CLK 63000000 + +static struct vvcam_mode_info pos02k10_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_array *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pos02k10_mode_info); + + memcpy(pmode_info_arry->modes,pos02k10_mode_info,sizeof(pos02k10_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pos02k10_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pos02k10_mode_info[i].index == pmode->index) + { + psensor_mode = &(pos02k10_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&os02k10_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&os02k10_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3012, 0x01); + }else + { + ret = sensor_write_reg(ctx, 0x3012, 0x00); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s os02k10_function = +{ + .sensor_name = "os02k10", + .reserve_id = 0x2770, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 2, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam/native/sensor/omnivision_os02k10/os02k10_driver.h b/vvcam/native/sensor/omnivision_os02k10/os02k10_driver.h new file mode 100755 index 0000000..56cdd59 --- /dev/null +++ b/vvcam/native/sensor/omnivision_os02k10/os02k10_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OMNIVISION_OS02k10_H_ +#define _OMNIVISION_OS02k10_H_ + +extern struct vvcam_sensor_function_s os02k10_function; + + +#endif diff --git a/vvcam/native/sensor/omnivision_os02k10/os02k10_mipi4lane_1080p_30fps_linear.c b/vvcam/native/sensor/omnivision_os02k10/os02k10_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..b75ff99 --- /dev/null +++ b/vvcam/native/sensor/omnivision_os02k10/os02k10_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,310 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data os02k10_mipi4lane_1080p_30fps_linear_reg[] = { +{0x0100,0x00}, +{0x302a,0x00}, +{0x0103,0x01}, +{0x0109,0x01}, +{0x0104,0x02}, +{0x0102,0x00}, +{0x0303,0x04}, +{0x0305,0x4c}, +{0x0306,0x00}, +{0x0317,0x0a}, +{0x0323,0x07}, +{0x0324,0x01}, +{0x0325,0xb0}, +{0x0327,0x07}, +{0x300f,0x11}, +{0x3012,0x21}, +{0x3026,0x10}, +{0x3027,0x08}, +{0x302d,0x24}, +{0x3106,0x10}, +{0x3400,0x00}, +{0x3406,0x08}, +{0x3408,0x05}, +{0x340c,0x05}, +{0x3425,0x51}, +{0x3426,0x10}, +{0x3427,0x14}, +{0x3428,0x50}, +{0x3429,0x10}, +{0x342a,0x10}, +{0x342b,0x04}, +{0x3504,0x08}, +{0x3508,0x01}, +{0x3509,0x00}, +{0x3544,0x08}, +{0x3548,0x01}, +{0x3549,0x00}, +{0x3584,0x08}, +{0x3588,0x01}, +{0x3589,0x00}, +{0x3601,0x70}, +{0x3604,0xe3}, +{0x3605,0xff}, +{0x3606,0x01}, +{0x3608,0xa8}, +{0x360a,0xd0}, +{0x360b,0x08}, +{0x360e,0xc8}, +{0x360f,0x66}, +{0x3610,0x81}, +{0x3611,0x89}, +{0x3612,0x4e}, +{0x3613,0xbd}, +{0x362a,0x0e}, +{0x362b,0x0e}, +{0x362c,0x0e}, +{0x362d,0x0e}, +{0x362e,0x0c}, +{0x362f,0x1a}, +{0x3630,0x32}, +{0x3631,0x64}, +{0x3638,0x00}, +{0x3643,0x00}, +{0x3644,0x00}, +{0x3645,0x00}, +{0x3646,0x00}, +{0x3647,0x00}, +{0x3648,0x00}, +{0x3649,0x00}, +{0x364a,0x04}, +{0x364c,0x0e}, +{0x364d,0x0e}, +{0x364e,0x0e}, +{0x364f,0x0e}, +{0x3650,0xff}, +{0x3651,0xff}, +{0x3661,0x07}, +{0x3662,0x00}, +{0x3663,0x20}, +{0x3665,0x12}, +{0x3667,0xd4}, +{0x3668,0x80}, +{0x366f,0x00}, +{0x3671,0x08}, +{0x3673,0x2a}, +{0x3681,0x80}, +{0x3700,0x26}, +{0x3701,0x1e}, +{0x3702,0x25}, +{0x3703,0x28}, +{0x3706,0xb1}, +{0x3707,0x0a}, +{0x3708,0x34}, +{0x3709,0x50}, +{0x370a,0x02}, +{0x370b,0x21}, +{0x3714,0x01}, +{0x371b,0x13}, +{0x371c,0x00}, +{0x371d,0x08}, +{0x3756,0xe7}, +{0x3757,0xe7}, +{0x3762,0x1d}, +{0x376c,0x00}, +{0x3776,0x03}, +{0x3777,0x22}, +{0x3779,0x60}, +{0x377c,0x48}, +{0x379c,0x4d}, +{0x3784,0x06}, +{0x3785,0x0a}, +{0x37d1,0xb1}, +{0x37d2,0x02}, +{0x37d3,0x21}, +{0x37d5,0xb1}, +{0x37d6,0x02}, +{0x37d7,0x21}, +{0x37d8,0x01}, +{0x37dc,0x00}, +{0x3790,0x10}, +{0x3793,0x04}, +{0x3794,0x07}, +{0x3796,0x00}, +{0x3797,0x02}, +{0x37a1,0x80}, +{0x37bb,0x88}, +{0x37be,0x01}, +{0x37bf,0x00}, +{0x37c0,0x01}, +{0x37c7,0x56}, +{0x37ca,0x21}, +{0x37cd,0x90}, +{0x37cf,0x02}, +{0x3800,0x00}, +{0x3801,0x00}, +{0x3802,0x00}, +{0x3803,0x04}, +{0x3804,0x07}, +{0x3805,0x8f}, +{0x3806,0x04}, +{0x3807,0x43}, +{0x3808,0x07}, +{0x3809,0x80}, +{0x380a,0x04}, +{0x380b,0x38}, +{0x380c,0x0e}, +{0x380d,0xc8}, +{0x380e,0x05}, +{0x380f,0xb4}, +{0x3811,0x08}, +{0x3813,0x04}, +{0x3814,0x01}, +{0x3815,0x01}, +{0x3816,0x01}, +{0x3817,0x01}, +{0x381c,0x00}, +{0x3820,0x02}, +{0x3821,0x00}, +{0x3822,0x14}, +{0x384c,0x04}, +{0x384d,0xc8}, +{0x3858,0x0d}, +{0x3865,0x00}, +{0x3866,0xc0}, +{0x3867,0x00}, +{0x3868,0xc0}, +{0x3900,0x13}, +{0x3940,0x13}, +{0x3980,0x13}, +{0x3c01,0x11}, +{0x3c05,0x00}, +{0x3c0f,0x1c}, +{0x3c12,0x0d}, +{0x3c19,0x01}, +{0x3c21,0x40}, +{0x3c3b,0x18}, +{0x3c3d,0xc9}, +{0x3c55,0xcb}, +{0x3c5d,0xec}, +{0x3c5e,0xec}, +{0x3ce0,0x00}, +{0x3ce1,0x00}, +{0x3ce2,0x00}, +{0x3ce3,0x00}, +{0x3d8c,0x70}, +{0x3d8d,0x10}, +{0x4001,0x2f}, +{0x4033,0x80}, +{0x4008,0x02}, +{0x4009,0x11}, +{0x4004,0x01}, +{0x4005,0x00}, +{0x400a,0x03}, +{0x400b,0x40}, +{0x410f,0x01}, +{0x402e,0x01}, +{0x402f,0x00}, +{0x4030,0x01}, +{0x4031,0x00}, +{0x4032,0x9f}, +{0x4050,0x00}, +{0x4051,0x07}, +{0x4288,0xcf}, +{0x4289,0x03}, +{0x428a,0x46}, +{0x430b,0xff}, +{0x430c,0xff}, +{0x430d,0x00}, +{0x430e,0x00}, +{0x4500,0x18}, +{0x4501,0x18}, +{0x4504,0x00}, +{0x4507,0x02}, +{0x4603,0x00}, +{0x4640,0x62}, +{0x4646,0xaa}, +{0x4647,0x55}, +{0x4648,0x99}, +{0x4649,0x66}, +{0x464d,0x00}, +{0x4654,0x11}, +{0x4655,0x22}, +{0x4800,0x04}, +{0x4810,0xff}, +{0x4811,0xff}, +{0x480e,0x00}, +{0x4813,0x00}, +{0x4837,0x0c}, +{0x484b,0x27}, +{0x4d00,0x4e}, +{0x4d01,0x0c}, +{0x4d09,0x4f}, +{0x5000,0x1f}, +{0x5080,0x00}, +{0x50c0,0x00}, +{0x5100,0x00}, +{0x5200,0x00}, +{0x5201,0x70}, +{0x5202,0x03}, +{0x5203,0x7f}, +{0x3501,0x01}, +{0x380e,0x18}, +{0x380f,0x18}, +{0x3501,0x03}, +{0x3502,0x74}, +{0x0100,0x01}, +}; + +struct vvcam_sccb_array os02k10_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(os02k10_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = os02k10_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam/native/sensor/omnivision_os02k10/os02k10_reg_cfg.h b/vvcam/native/sensor/omnivision_os02k10/os02k10_reg_cfg.h new file mode 100755 index 0000000..eff9c12 --- /dev/null +++ b/vvcam/native/sensor/omnivision_os02k10/os02k10_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OS02k10_REG_CFG_H_ +#define _OS02k10_REG_CFG_H_ + +extern struct vvcam_sccb_array os02k10_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam/native/sensor/omnivision_ov2775/ov2775_driver.c b/vvcam/native/sensor/omnivision_ov2775/ov2775_driver.c new file mode 100755 index 0000000..1194c71 --- /dev/null +++ b/vvcam/native/sensor/omnivision_ov2775/ov2775_driver.c @@ -0,0 +1,498 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "ov2775_reg_cfg.h" + +#define SENSOR_CLK 24000000 + +static struct vvcam_mode_info pov2775_mode_info[] = { + { + .index = 0, + .width = 640, + .height = 480, + .fps = 2,//30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 12, + .bayer_pattern = BAYER_BGGR, + .mipi_phy_freq = 408, //mbps + .mipi_line_num = 4, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 12, + .bayer_pattern = BAYER_BGGR, + .mipi_phy_freq = 408, //mbps + .mipi_line_num = 4, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 12, + .bayer_pattern = BAYER_BGGR, + .mipi_phy_freq = 408, //mbps + .mipi_line_num = 4, + } +}; + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_array *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pov2775_mode_info); + + memcpy(pmode_info_arry->modes,pov2775_mode_info,sizeof(pov2775_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pov2775_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pov2775_mode_info[i].index == pmode->index) + { + psensor_mode = &(pov2775_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&ov2775_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&ov2775_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3012, 0x01); + }else + { + ret = sensor_write_reg(ctx, 0x3012, 0x00); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s ov2775_function = +{ + .sensor_name = "ov2775", + .reserve_id = 0x2770, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam/native/sensor/omnivision_ov2775/ov2775_driver.h b/vvcam/native/sensor/omnivision_ov2775/ov2775_driver.h new file mode 100755 index 0000000..e027d75 --- /dev/null +++ b/vvcam/native/sensor/omnivision_ov2775/ov2775_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OMNIVISION_OV2775_H_ +#define _OMNIVISION_OV2775_H_ + +extern struct vvcam_sensor_function_s ov2775_function; + + +#endif diff --git a/vvcam/native/sensor/omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.c b/vvcam/native/sensor/omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..28c0ad3 --- /dev/null +++ b/vvcam/native/sensor/omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,1880 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data ov2775_mipi4lane_1080p_30fps_linear_reg[] = { + {0x3000, 0x02}, + {0x3001, 0x28}, + {0x3002, 0x03}, + {0x3003, 0x01}, + {0x3004, 0x05}, + {0x3005, 0x26}, + {0x3006, 0x00}, + {0x3007, 0x07}, + {0x3008, 0x01}, + {0x3009, 0x00}, + {0x300c, 0x6c}, + {0x300e, 0x80}, + {0x300f, 0x00}, + {0x3012, 0x00}, + {0x3013, 0x00}, + {0x3014, 0xc4}, + {0x3015, 0x00}, + {0x3017, 0x00}, + {0x3018, 0x00}, + {0x3019, 0x00}, + {0x301a, 0x00}, + {0x301b, 0x0e}, + {0x301e, 0x17}, + {0x301f, 0xe1}, + {0x3030, 0x02}, + {0x3031, 0x62}, + {0x3032, 0xf0}, + {0x3033, 0x30}, + {0x3034, 0x3f}, + {0x3035, 0x5f}, + {0x3036, 0x02}, + {0x3037, 0x9f}, + {0x3038, 0x04}, + {0x3039, 0xb7}, + {0x303a, 0x04}, + {0x303b, 0x07}, + {0x303c, 0xf0}, + {0x303d, 0x00}, + {0x303e, 0x0b}, + {0x303f, 0xe3}, + {0x3040, 0xf3}, + {0x3041, 0x29}, + {0x3042, 0xf6}, + {0x3043, 0x65}, + {0x3044, 0x06}, + {0x3045, 0x0f}, + {0x3046, 0x59}, + {0x3047, 0x07}, + {0x3048, 0x82}, + {0x3049, 0xcf}, + {0x304a, 0x12}, + {0x304b, 0x40}, + {0x304c, 0x33}, + {0x304d, 0xa4}, + {0x304e, 0x0b}, + {0x304f, 0x3d}, + {0x3050, 0x10}, + {0x3060, 0x00}, + {0x3061, 0x64}, + {0x3062, 0x00}, + {0x3063, 0xe4}, + {0x3066, 0x80}, + {0x3080, 0x00}, + {0x3081, 0x00}, + {0x3082, 0x01}, + {0x3083, 0xe3}, + {0x3084, 0x06}, + {0x3085, 0x00}, + {0x3086, 0x10}, + {0x3087, 0x10}, + {0x3089, 0x00}, + {0x308a, 0x01}, + {0x3093, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x00}, + {0x30aa, 0x00}, + {0x30ab, 0x00}, + {0x30ac, 0x07}, + {0x30ad, 0x90}, + {0x30ae, 0x04}, + {0x30af, 0x48}, + {0x30b0, 0x04}, + {0x30b1, 0x7e}, + {0x30b2, 0x04}, + {0x30b3, 0x65}, + {0x30b4, 0x00}, + {0x30b5, 0x00}, + {0x30b6, 0x00}, + {0x30b7, 0x10}, + {0x30b8, 0x00}, + {0x30b9, 0x02}, + {0x30ba, 0x10}, + {0x30bb, 0x00}, + {0x30bc, 0x00}, + {0x30bd, 0x03}, + {0x30be, 0x5c}, + {0x30bf, 0x00}, + {0x30c0, 0x05}, + {0x30c1, 0x00}, + {0x30c2, 0x20}, + {0x30c3, 0x00}, + {0x30c4, 0x4a}, + {0x30c5, 0x00}, + {0x30c7, 0x00}, + {0x30c8, 0x00}, + {0x30d1, 0x00}, + {0x30d2, 0x00}, + {0x30d3, 0x80}, + {0x30d4, 0x00}, + {0x30d9, 0x09}, + {0x30da, 0x64}, + {0x30dd, 0x00}, + {0x30de, 0x16}, + {0x30df, 0x00}, + {0x30e0, 0x17}, + {0x30e1, 0x00}, + {0x30e2, 0x18}, + {0x30e3, 0x10}, + {0x30e4, 0x04}, + {0x30e5, 0x00}, + {0x30e6, 0x00}, + {0x30e7, 0x00}, + {0x30e8, 0x00}, + {0x30e9, 0x00}, + {0x30ea, 0x00}, + {0x30eb, 0x00}, + {0x30ec, 0x00}, + {0x30ed, 0x00}, + {0x3101, 0x00}, + {0x3102, 0x00}, + {0x3103, 0x00}, + {0x3104, 0x00}, + {0x3105, 0x8c}, + {0x3106, 0x87}, + {0x3107, 0xc0}, + {0x3108, 0x9d}, + {0x3109, 0x8d}, + {0x310a, 0x8d}, + {0x310b, 0x6a}, + {0x310c, 0x3a}, + {0x310d, 0x5a}, + {0x310e, 0x00}, + {0x3120, 0x00}, + {0x3121, 0x00}, + {0x3122, 0x00}, + {0x3123, 0xf0}, + {0x3124, 0x00}, + {0x3125, 0x70}, + {0x3126, 0x1f}, + {0x3127, 0x0f}, + {0x3128, 0x00}, + {0x3129, 0x3a}, + {0x312a, 0x02}, + {0x312b, 0x0f}, + {0x312c, 0x00}, + {0x312d, 0x0f}, + {0x312e, 0x1d}, + {0x312f, 0x00}, + {0x3130, 0x00}, + {0x3131, 0x00}, + {0x3132, 0x00}, + {0x3140, 0x0a}, + {0x3141, 0x03}, + {0x3142, 0x00}, + {0x3143, 0x00}, + {0x3144, 0x00}, + {0x3145, 0x00}, + {0x3146, 0x00}, + {0x3147, 0x00}, + {0x3148, 0x00}, + {0x3149, 0x00}, + {0x314a, 0x00}, + {0x314b, 0x00}, + {0x314c, 0x00}, + {0x314d, 0x00}, + {0x314e, 0x1c}, + {0x314f, 0xff}, + {0x3150, 0xff}, + {0x3151, 0xff}, + {0x3152, 0x10}, + {0x3153, 0x10}, + {0x3154, 0x10}, + {0x3155, 0x00}, + {0x3156, 0x03}, + {0x3157, 0x00}, + {0x3158, 0x0f}, + {0x3159, 0xff}, + {0x315a, 0x01}, + {0x315b, 0x00}, + {0x315c, 0x01}, + {0x315d, 0x00}, + {0x315e, 0x01}, + {0x315f, 0x00}, + {0x3160, 0x00}, + {0x3161, 0x40}, + {0x3162, 0x00}, + {0x3163, 0x40}, + {0x3164, 0x00}, + {0x3165, 0x40}, + {0x3190, 0x08}, + {0x3191, 0x99}, + {0x3193, 0x08}, + {0x3194, 0x13}, + {0x3195, 0x33}, + {0x3196, 0x00}, + {0x3197, 0x10}, + {0x3198, 0x00}, + {0x3199, 0x7f}, + {0x319a, 0x80}, + {0x319b, 0xff}, + {0x319c, 0x80}, + {0x319d, 0xbf}, + {0x319e, 0xc0}, + {0x319f, 0xff}, + {0x31a0, 0x24}, + {0x31a1, 0x55}, + {0x31a2, 0x00}, + {0x31a3, 0x00}, + {0x31a6, 0x00}, + {0x31a7, 0x00}, + {0x31b0, 0x00}, + {0x31b1, 0x00}, + {0x31b2, 0x02}, + {0x31b3, 0x00}, + {0x31b4, 0x00}, + {0x31b5, 0x01}, + {0x31b6, 0x00}, + {0x31b7, 0x00}, + {0x31b8, 0x00}, + {0x31b9, 0x00}, + {0x31ba, 0x00}, + {0x31d0, 0x3c}, + {0x31d1, 0x34}, + {0x31d2, 0x3c}, + {0x31d3, 0x00}, + {0x31d4, 0x2d}, + {0x31d5, 0x00}, + {0x31d6, 0x01}, + {0x31d7, 0x06}, + {0x31d8, 0x00}, + {0x31d9, 0x64}, + {0x31da, 0x00}, + {0x31db, 0x30}, + {0x31dc, 0x04}, + {0x31dd, 0x69}, + {0x31de, 0x0a}, + {0x31df, 0x3c}, + {0x31e0, 0x04}, + {0x31e1, 0x32}, + {0x31e2, 0x00}, + {0x31e3, 0x00}, + {0x31e4, 0x08}, + {0x31e5, 0x80}, + {0x31e6, 0x00}, + {0x31e7, 0x2c}, + {0x31e8, 0x6c}, + {0x31e9, 0xac}, + {0x31ea, 0xec}, + {0x31eb, 0x3f}, + {0x31ec, 0x0f}, + {0x31ed, 0x20}, + {0x31ee, 0x04}, + {0x31ef, 0x48}, + {0x31f0, 0x07}, + {0x31f1, 0x90}, + {0x31f2, 0x04}, + {0x31f3, 0x48}, + {0x31f4, 0x07}, + {0x31f5, 0x90}, + {0x31f6, 0x04}, + {0x31f7, 0x48}, + {0x31f8, 0x07}, + {0x31f9, 0x90}, + {0x31fa, 0x04}, + {0x31fb, 0x48}, + {0x31fd, 0xcb}, + {0x31fe, 0x0f}, + {0x31ff, 0x03}, + {0x3200, 0x00}, + {0x3201, 0xff}, + {0x3202, 0x00}, + {0x3203, 0xff}, + {0x3204, 0xff}, + {0x3205, 0xff}, + {0x3206, 0xff}, + {0x3207, 0xff}, + {0x3208, 0xff}, + {0x3209, 0xff}, + {0x320a, 0xff}, + {0x320b, 0x1b}, + {0x320c, 0x1f}, + {0x320d, 0x1e}, + {0x320e, 0x30}, + {0x320f, 0x2d}, + {0x3210, 0x2c}, + {0x3211, 0x2b}, + {0x3212, 0x2a}, + {0x3213, 0x24}, + {0x3214, 0x22}, + {0x3215, 0x00}, + {0x3216, 0x04}, + {0x3217, 0x2c}, + {0x3218, 0x6c}, + {0x3219, 0xac}, + {0x321a, 0xec}, + {0x321b, 0x00}, + {0x3230, 0x3a}, + {0x3231, 0x00}, + {0x3232, 0x80}, + {0x3233, 0x00}, + {0x3234, 0x10}, + {0x3235, 0xaa}, + {0x3236, 0x55}, + {0x3237, 0x99}, + {0x3238, 0x66}, + {0x3239, 0x08}, + {0x323a, 0x88}, + {0x323b, 0x00}, + {0x323c, 0x00}, + {0x323d, 0x03}, + {0x3250, 0x33}, + {0x3251, 0x00}, + {0x3252, 0x20}, + {0x3253, 0x00}, + {0x3254, 0x00}, + {0x3255, 0x01}, + {0x3256, 0x00}, + {0x3257, 0x00}, + {0x3258, 0x00}, + {0x3270, 0x01}, + {0x3271, 0x60}, + {0x3272, 0xc0}, + {0x3273, 0x00}, + {0x3274, 0x80}, + {0x3275, 0x40}, + {0x3276, 0x02}, + {0x3277, 0x08}, + {0x3278, 0x10}, + {0x3279, 0x04}, + {0x327a, 0x00}, + {0x327b, 0x03}, + {0x327c, 0x10}, + {0x327d, 0x60}, + {0x327e, 0xc0}, + {0x327f, 0x06}, + {0x3288, 0x10}, + {0x3289, 0x00}, + {0x328a, 0x08}, + {0x328b, 0x00}, + {0x328c, 0x04}, + {0x328d, 0x00}, + {0x328e, 0x02}, + {0x328f, 0x00}, + {0x3290, 0x20}, + {0x3291, 0x00}, + {0x3292, 0x10}, + {0x3293, 0x00}, + {0x3294, 0x08}, + {0x3295, 0x00}, + {0x3296, 0x04}, + {0x3297, 0x00}, + {0x3298, 0x40}, + {0x3299, 0x00}, + {0x329a, 0x20}, + {0x329b, 0x00}, + {0x329c, 0x10}, + {0x329d, 0x00}, + {0x329e, 0x08}, + {0x329f, 0x00}, + {0x32a0, 0x7f}, + {0x32a1, 0xff}, + {0x32a2, 0x40}, + {0x32a3, 0x00}, + {0x32a4, 0x20}, + {0x32a5, 0x00}, + {0x32a6, 0x10}, + {0x32a7, 0x00}, + {0x32a8, 0x00}, + {0x32a9, 0x00}, + {0x32aa, 0x00}, + {0x32ab, 0x00}, + {0x32ac, 0x00}, + {0x32ad, 0x00}, + {0x32ae, 0x00}, + {0x32af, 0x00}, + {0x32b0, 0x00}, + {0x32b1, 0x00}, + {0x32b2, 0x00}, + {0x32b3, 0x00}, + {0x32b4, 0x00}, + {0x32b5, 0x00}, + {0x32b6, 0x00}, + {0x32b7, 0x00}, + {0x32b8, 0x00}, + {0x32b9, 0x00}, + {0x32ba, 0x00}, + {0x32bb, 0x00}, + {0x32bc, 0x00}, + {0x32bd, 0x00}, + {0x32be, 0x00}, + {0x32bf, 0x00}, + {0x32c0, 0x00}, + {0x32c1, 0x00}, + {0x32c2, 0x00}, + {0x32c3, 0x00}, + {0x32c4, 0x00}, + {0x32c5, 0x00}, + {0x32c6, 0x00}, + {0x32c7, 0x00}, + {0x32c8, 0x87}, + {0x32c9, 0x00}, + {0x3330, 0x03}, + {0x3331, 0xc8}, + {0x3332, 0x02}, + {0x3333, 0x24}, + {0x3334, 0x00}, + {0x3335, 0x00}, + {0x3336, 0x00}, + {0x3337, 0x00}, + {0x3338, 0x03}, + {0x3339, 0xc8}, + {0x333a, 0x02}, + {0x333b, 0x24}, + {0x333c, 0x00}, + {0x333d, 0x00}, + {0x333e, 0x00}, + {0x333f, 0x00}, + {0x3340, 0x03}, + {0x3341, 0xc8}, + {0x3342, 0x02}, + {0x3343, 0x24}, + {0x3344, 0x00}, + {0x3345, 0x00}, + {0x3346, 0x00}, + {0x3347, 0x00}, + {0x3348, 0x40}, + {0x3349, 0x00}, + {0x334a, 0x00}, + {0x334b, 0x00}, + {0x334c, 0x00}, + {0x334d, 0x00}, + {0x334e, 0x80}, + {0x3360, 0x01}, + {0x3361, 0x00}, + {0x3362, 0x01}, + {0x3363, 0x00}, + {0x3364, 0x01}, + {0x3365, 0x00}, + {0x3366, 0x01}, + {0x3367, 0x00}, + {0x3368, 0x01}, + {0x3369, 0x00}, + {0x336a, 0x01}, + {0x336b, 0x00}, + {0x336c, 0x01}, + {0x336d, 0x00}, + {0x336e, 0x01}, + {0x336f, 0x00}, + {0x3370, 0x01}, + {0x3371, 0x00}, + {0x3372, 0x01}, + {0x3373, 0x00}, + {0x3374, 0x01}, + {0x3375, 0x00}, + {0x3376, 0x01}, + {0x3377, 0x00}, + {0x3378, 0x00}, + {0x3379, 0x00}, + {0x337a, 0x00}, + {0x337b, 0x00}, + {0x337c, 0x00}, + {0x337d, 0x00}, + {0x337e, 0x00}, + {0x337f, 0x00}, + {0x3380, 0x00}, + {0x3381, 0x00}, + {0x3382, 0x00}, + {0x3383, 0x00}, + {0x3384, 0x00}, + {0x3385, 0x00}, + {0x3386, 0x00}, + {0x3387, 0x00}, + {0x3388, 0x00}, + {0x3389, 0x00}, + {0x338a, 0x00}, + {0x338b, 0x00}, + {0x338c, 0x00}, + {0x338d, 0x00}, + {0x338e, 0x00}, + {0x338f, 0x00}, + {0x3390, 0x00}, + {0x3391, 0x00}, + {0x3392, 0x00}, + {0x3393, 0x00}, + {0x3394, 0x00}, + {0x3395, 0x00}, + {0x3396, 0x00}, + {0x3397, 0x00}, + {0x3398, 0x00}, + {0x3399, 0x00}, + {0x339a, 0x00}, + {0x339b, 0x00}, + {0x33b0, 0x00}, + {0x33b1, 0x50}, + {0x33b2, 0x01}, + {0x33b3, 0xff}, + {0x33b4, 0xe0}, + {0x33b5, 0x6b}, + {0x33b6, 0x00}, + {0x33b7, 0x00}, + {0x33b8, 0x00}, + {0x33b9, 0x00}, + {0x33ba, 0x00}, + {0x33bb, 0x1f}, + {0x33bc, 0x01}, + {0x33bd, 0x01}, + {0x33be, 0x01}, + {0x33bf, 0x01}, + {0x33c0, 0x00}, + {0x33c1, 0x00}, + {0x33c2, 0x00}, + {0x33c3, 0x00}, + {0x33e0, 0x14}, + {0x33e1, 0x0f}, + {0x33e2, 0x02}, + {0x33e3, 0x01}, + {0x33e4, 0x01}, + {0x33e5, 0x01}, + {0x33e6, 0x00}, + {0x33e7, 0x04}, + {0x33e8, 0x0c}, + {0x33e9, 0x02}, + {0x33ea, 0x02}, + {0x33eb, 0x02}, + {0x33ec, 0x03}, + {0x33ed, 0x01}, + {0x33ee, 0x02}, + {0x33ef, 0x08}, + {0x33f0, 0x08}, + {0x33f1, 0x04}, + {0x33f2, 0x04}, + {0x33f3, 0x00}, + {0x33f4, 0x03}, + {0x33f5, 0x14}, + {0x33f6, 0x0f}, + {0x33f7, 0x02}, + {0x33f8, 0x01}, + {0x33f9, 0x01}, + {0x33fa, 0x01}, + {0x33fb, 0x00}, + {0x33fc, 0x04}, + {0x33fd, 0x0c}, + {0x33fe, 0x02}, + {0x33ff, 0x02}, + {0x3400, 0x02}, + {0x3401, 0x03}, + {0x3402, 0x01}, + {0x3403, 0x02}, + {0x3404, 0x08}, + {0x3405, 0x08}, + {0x3406, 0x04}, + {0x3407, 0x04}, + {0x3408, 0x00}, + {0x3409, 0x03}, + {0x340a, 0x14}, + {0x340b, 0x0f}, + {0x340c, 0x04}, + {0x340d, 0x02}, + {0x340e, 0x01}, + {0x340f, 0x01}, + {0x3410, 0x00}, + {0x3411, 0x04}, + {0x3412, 0x0c}, + {0x3413, 0x02}, + {0x3414, 0x02}, + {0x3415, 0x02}, + {0x3416, 0x03}, + {0x3417, 0x02}, + {0x3418, 0x05}, + {0x3419, 0x0a}, + {0x341a, 0x08}, + {0x341b, 0x04}, + {0x341c, 0x04}, + {0x341d, 0x00}, + {0x341e, 0x03}, + {0x3440, 0x00}, + {0x3441, 0x00}, + {0x3442, 0x00}, + {0x3443, 0x00}, + {0x3444, 0x02}, + {0x3445, 0xf0}, + {0x3446, 0x02}, + {0x3447, 0x08}, + {0x3448, 0x00}, + {0x3460, 0x40}, + {0x3461, 0x40}, + {0x3462, 0x40}, + {0x3463, 0x40}, + {0x3464, 0x03}, + {0x3465, 0x01}, + {0x3466, 0x01}, + {0x3467, 0x02}, + {0x3468, 0x30}, + {0x3469, 0x00}, + {0x346a, 0x33}, + {0x346b, 0xbf}, + {0x3480, 0x40}, + {0x3481, 0x00}, + {0x3482, 0x00}, + {0x3483, 0x00}, + {0x3484, 0x0d}, + {0x3485, 0x00}, + {0x3486, 0x00}, + {0x3487, 0x00}, + {0x3488, 0x00}, + {0x3489, 0x00}, + {0x348a, 0x00}, + {0x348b, 0x04}, + {0x348c, 0x00}, + {0x348d, 0x01}, + {0x348f, 0x01}, + {0x3030, 0x0a}, + {0x3030, 0x02}, + {0x7000, 0x58}, + {0x7001, 0x7a}, + {0x7002, 0x1a}, + {0x7003, 0xc1}, + {0x7004, 0x03}, + {0x7005, 0xda}, + {0x7006, 0xbd}, + {0x7007, 0x03}, + {0x7008, 0xbd}, + {0x7009, 0x06}, + {0x700a, 0xe6}, + {0x700b, 0xec}, + {0x700c, 0xbc}, + {0x700d, 0xff}, + {0x700e, 0xbc}, + {0x700f, 0x73}, + {0x7010, 0xda}, + {0x7011, 0x72}, + {0x7012, 0x76}, + {0x7013, 0xb6}, + {0x7014, 0xee}, + {0x7015, 0xcf}, + {0x7016, 0xac}, + {0x7017, 0xd0}, + {0x7018, 0xac}, + {0x7019, 0xd1}, + {0x701a, 0x50}, + {0x701b, 0xac}, + {0x701c, 0xd2}, + {0x701d, 0xbc}, + {0x701e, 0x2e}, + {0x701f, 0xb4}, + {0x7020, 0x00}, + {0x7021, 0xdc}, + {0x7022, 0xdf}, + {0x7023, 0xb0}, + {0x7024, 0x6e}, + {0x7025, 0xbd}, + {0x7026, 0x01}, + {0x7027, 0xd7}, + {0x7028, 0xed}, + {0x7029, 0xe1}, + {0x702a, 0x36}, + {0x702b, 0x30}, + {0x702c, 0xd3}, + {0x702d, 0x2e}, + {0x702e, 0x54}, + {0x702f, 0x46}, + {0x7030, 0xbc}, + {0x7031, 0x22}, + {0x7032, 0x66}, + {0x7033, 0xbc}, + {0x7034, 0x24}, + {0x7035, 0x2c}, + {0x7036, 0x28}, + {0x7037, 0xbc}, + {0x7038, 0x3c}, + {0x7039, 0xa1}, + {0x703a, 0xac}, + {0x703b, 0xd8}, + {0x703c, 0xd6}, + {0x703d, 0xb4}, + {0x703e, 0x04}, + {0x703f, 0x46}, + {0x7040, 0xb7}, + {0x7041, 0x04}, + {0x7042, 0xbe}, + {0x7043, 0x08}, + {0x7044, 0xc3}, + {0x7045, 0xd9}, + {0x7046, 0xad}, + {0x7047, 0xc3}, + {0x7048, 0xbc}, + {0x7049, 0x19}, + {0x704a, 0xc1}, + {0x704b, 0x27}, + {0x704c, 0xe7}, + {0x704d, 0x00}, + {0x704e, 0x50}, + {0x704f, 0x20}, + {0x7050, 0xb8}, + {0x7051, 0x02}, + {0x7052, 0xbc}, + {0x7053, 0x17}, + {0x7054, 0xdb}, + {0x7055, 0xc7}, + {0x7056, 0xb8}, + {0x7057, 0x00}, + {0x7058, 0x28}, + {0x7059, 0x54}, + {0x705a, 0xb4}, + {0x705b, 0x14}, + {0x705c, 0xab}, + {0x705d, 0xbe}, + {0x705e, 0x06}, + {0x705f, 0xd8}, + {0x7060, 0xd6}, + {0x7061, 0x00}, + {0x7062, 0xb4}, + {0x7063, 0xc7}, + {0x7064, 0x07}, + {0x7065, 0xb9}, + {0x7066, 0x05}, + {0x7067, 0xee}, + {0x7068, 0xe6}, + {0x7069, 0xad}, + {0x706a, 0xb4}, + {0x706b, 0x26}, + {0x706c, 0x19}, + {0x706d, 0xc1}, + {0x706e, 0x3a}, + {0x706f, 0xc3}, + {0x7070, 0xaf}, + {0x7071, 0x00}, + {0x7072, 0xc0}, + {0x7073, 0x3c}, + {0x7074, 0xc3}, + {0x7075, 0xbe}, + {0x7076, 0xe7}, + {0x7077, 0x00}, + {0x7078, 0x15}, + {0x7079, 0xc2}, + {0x707a, 0x40}, + {0x707b, 0xc3}, + {0x707c, 0xa4}, + {0x707d, 0xc0}, + {0x707e, 0x3c}, + {0x707f, 0x00}, + {0x7080, 0xb9}, + {0x7081, 0x64}, + {0x7082, 0x29}, + {0x7083, 0x00}, + {0x7084, 0xb8}, + {0x7085, 0x12}, + {0x7086, 0xbe}, + {0x7087, 0x01}, + {0x7088, 0xd0}, + {0x7089, 0xbc}, + {0x708a, 0x01}, + {0x708b, 0xac}, + {0x708c, 0x37}, + {0x708d, 0xd2}, + {0x708e, 0xac}, + {0x708f, 0x45}, + {0x7090, 0xad}, + {0x7091, 0x28}, + {0x7092, 0x00}, + {0x7093, 0xb8}, + {0x7094, 0x00}, + {0x7095, 0xbc}, + {0x7096, 0x01}, + {0x7097, 0x36}, + {0x7098, 0xd3}, + {0x7099, 0x30}, + {0x709a, 0x04}, + {0x709b, 0xe0}, + {0x709c, 0xd8}, + {0x709d, 0xb4}, + {0x709e, 0xe9}, + {0x709f, 0x00}, + {0x70a0, 0xbe}, + {0x70a1, 0x05}, + {0x70a2, 0x62}, + {0x70a3, 0x07}, + {0x70a4, 0xb9}, + {0x70a5, 0x05}, + {0x70a6, 0xad}, + {0x70a7, 0xc3}, + {0x70a8, 0xcf}, + {0x70a9, 0x00}, + {0x70aa, 0x15}, + {0x70ab, 0xc2}, + {0x70ac, 0x59}, + {0x70ad, 0xc3}, + {0x70ae, 0xc9}, + {0x70af, 0xc0}, + {0x70b0, 0x55}, + {0x70b1, 0x00}, + {0x70b2, 0x46}, + {0x70b3, 0xa1}, + {0x70b4, 0xb9}, + {0x70b5, 0x64}, + {0x70b6, 0x29}, + {0x70b7, 0x00}, + {0x70b8, 0xb8}, + {0x70b9, 0x02}, + {0x70ba, 0xbe}, + {0x70bb, 0x02}, + {0x70bc, 0xd0}, + {0x70bd, 0xdc}, + {0x70be, 0xac}, + {0x70bf, 0xbc}, + {0x70c0, 0x01}, + {0x70c1, 0x37}, + {0x70c2, 0xac}, + {0x70c3, 0xd2}, + {0x70c4, 0x45}, + {0x70c5, 0xad}, + {0x70c6, 0x28}, + {0x70c7, 0x00}, + {0x70c8, 0xb8}, + {0x70c9, 0x00}, + {0x70ca, 0xbc}, + {0x70cb, 0x01}, + {0x70cc, 0x36}, + {0x70cd, 0x30}, + {0x70ce, 0xe0}, + {0x70cf, 0xd8}, + {0x70d0, 0xb5}, + {0x70d1, 0x0b}, + {0x70d2, 0xd6}, + {0x70d3, 0xbe}, + {0x70d4, 0x07}, + {0x70d5, 0x00}, + {0x70d6, 0x62}, + {0x70d7, 0x07}, + {0x70d8, 0xb9}, + {0x70d9, 0x05}, + {0x70da, 0xad}, + {0x70db, 0xc3}, + {0x70dc, 0xcf}, + {0x70dd, 0x46}, + {0x70de, 0xcd}, + {0x70df, 0x07}, + {0x70e0, 0xcd}, + {0x70e1, 0x00}, + {0x70e2, 0xe3}, + {0x70e3, 0x18}, + {0x70e4, 0xc2}, + {0x70e5, 0xa2}, + {0x70e6, 0xb9}, + {0x70e7, 0x64}, + {0x70e8, 0xd1}, + {0x70e9, 0xdd}, + {0x70ea, 0xac}, + {0x70eb, 0xcf}, + {0x70ec, 0xdf}, + {0x70ed, 0xb5}, + {0x70ee, 0x19}, + {0x70ef, 0x46}, + {0x70f0, 0x50}, + {0x70f1, 0xb6}, + {0x70f2, 0xee}, + {0x70f3, 0xe8}, + {0x70f4, 0xe6}, + {0x70f5, 0xbc}, + {0x70f6, 0x31}, + {0x70f7, 0xe1}, + {0x70f8, 0x36}, + {0x70f9, 0x30}, + {0x70fa, 0xd3}, + {0x70fb, 0x2e}, + {0x70fc, 0x54}, + {0x70fd, 0xbd}, + {0x70fe, 0x03}, + {0x70ff, 0xec}, + {0x7100, 0x2c}, + {0x7101, 0x50}, + {0x7102, 0x20}, + {0x7103, 0x04}, + {0x7104, 0xb8}, + {0x7105, 0x02}, + {0x7106, 0xbc}, + {0x7107, 0x18}, + {0x7108, 0xc7}, + {0x7109, 0xb8}, + {0x710a, 0x00}, + {0x710b, 0x28}, + {0x710c, 0x54}, + {0x710d, 0xbc}, + {0x710e, 0x02}, + {0x710f, 0xb4}, + {0x7110, 0xda}, + {0x7111, 0xbe}, + {0x7112, 0x04}, + {0x7113, 0xd6}, + {0x7114, 0xd8}, + {0x7115, 0xab}, + {0x7116, 0x00}, + {0x7117, 0x62}, + {0x7118, 0x07}, + {0x7119, 0xb9}, + {0x711a, 0x05}, + {0x711b, 0xad}, + {0x711c, 0xc3}, + {0x711d, 0xbc}, + {0x711e, 0xe7}, + {0x711f, 0xb9}, + {0x7120, 0x64}, + {0x7121, 0x29}, + {0x7122, 0x00}, + {0x7123, 0xb8}, + {0x7124, 0x02}, + {0x7125, 0xbe}, + {0x7126, 0x00}, + {0x7127, 0x45}, + {0x7128, 0xad}, + {0x7129, 0xe2}, + {0x712a, 0x28}, + {0x712b, 0x00}, + {0x712c, 0xb8}, + {0x712d, 0x00}, + {0x712e, 0xe0}, + {0x712f, 0xd8}, + {0x7130, 0xb4}, + {0x7131, 0xe9}, + {0x7132, 0xbe}, + {0x7133, 0x03}, + {0x7134, 0x00}, + {0x7135, 0x30}, + {0x7136, 0x62}, + {0x7137, 0x07}, + {0x7138, 0xb9}, + {0x7139, 0x05}, + {0x713a, 0xad}, + {0x713b, 0xc3}, + {0x713c, 0xcf}, + {0x713d, 0x42}, + {0x713e, 0xe4}, + {0x713f, 0xcd}, + {0x7140, 0x07}, + {0x7141, 0xcd}, + {0x7142, 0x00}, + {0x7143, 0x00}, + {0x7144, 0x17}, + {0x7145, 0xc2}, + {0x7146, 0xbb}, + {0x7147, 0xde}, + {0x7148, 0xcf}, + {0x7149, 0xdf}, + {0x714a, 0xac}, + {0x714b, 0xd1}, + {0x714c, 0x44}, + {0x714d, 0xac}, + {0x714e, 0xb9}, + {0x714f, 0x76}, + {0x7150, 0xb8}, + {0x7151, 0x08}, + {0x7152, 0xb6}, + {0x7153, 0xfe}, + {0x7154, 0xb4}, + {0x7155, 0xca}, + {0x7156, 0xd6}, + {0x7157, 0xd8}, + {0x7158, 0xab}, + {0x7159, 0x00}, + {0x715a, 0xe1}, + {0x715b, 0x36}, + {0x715c, 0x30}, + {0x715d, 0xd3}, + {0x715e, 0xbc}, + {0x715f, 0x29}, + {0x7160, 0xb4}, + {0x7161, 0x1f}, + {0x7162, 0xaa}, + {0x7163, 0xbd}, + {0x7164, 0x01}, + {0x7165, 0xb8}, + {0x7166, 0x0c}, + {0x7167, 0x45}, + {0x7168, 0xa4}, + {0x7169, 0xbd}, + {0x716a, 0x03}, + {0x716b, 0xec}, + {0x716c, 0xbc}, + {0x716d, 0x3d}, + {0x716e, 0xc3}, + {0x716f, 0xcf}, + {0x7170, 0x42}, + {0x7171, 0xb8}, + {0x7172, 0x00}, + {0x7173, 0xe4}, + {0x7174, 0xd5}, + {0x7175, 0x00}, + {0x7176, 0xb6}, + {0x7177, 0x00}, + {0x7178, 0x74}, + {0x7179, 0xbd}, + {0x717a, 0x03}, + {0x717b, 0xb5}, + {0x717c, 0x39}, + {0x717d, 0x40}, + {0x717e, 0x58}, + {0x717f, 0xdd}, + {0x7180, 0x19}, + {0x7181, 0xc1}, + {0x7182, 0xc8}, + {0x7183, 0xbd}, + {0x7184, 0x06}, + {0x7185, 0x17}, + {0x7186, 0xc1}, + {0x7187, 0xc6}, + {0x7188, 0xe8}, + {0x7189, 0x00}, + {0x718a, 0xc0}, + {0x718b, 0xc8}, + {0x718c, 0xe6}, + {0x718d, 0x95}, + {0x718e, 0x15}, + {0x718f, 0x00}, + {0x7190, 0xbc}, + {0x7191, 0x19}, + {0x7192, 0xb9}, + {0x7193, 0xf6}, + {0x7194, 0x14}, + {0x7195, 0xc1}, + {0x7196, 0xd0}, + {0x7197, 0xd1}, + {0x7198, 0xac}, + {0x7199, 0x37}, + {0x719a, 0xbc}, + {0x719b, 0x35}, + {0x719c, 0x36}, + {0x719d, 0x30}, + {0x719e, 0xe1}, + {0x719f, 0xd3}, + {0x71a0, 0x7a}, + {0x71a1, 0xb6}, + {0x71a2, 0x0c}, + {0x71a3, 0xff}, + {0x71a4, 0xb4}, + {0x71a5, 0xc7}, + {0x71a6, 0xd9}, + {0x71a7, 0x00}, + {0x71a8, 0xbd}, + {0x71a9, 0x01}, + {0x71aa, 0x56}, + {0x71ab, 0xc0}, + {0x71ac, 0xda}, + {0x71ad, 0xb4}, + {0x71ae, 0x1f}, + {0x71af, 0x56}, + {0x71b0, 0xaa}, + {0x71b1, 0xbc}, + {0x71b2, 0x08}, + {0x71b3, 0x00}, + {0x71b4, 0x57}, + {0x71b5, 0xe8}, + {0x71b6, 0xb5}, + {0x71b7, 0x36}, + {0x71b8, 0x00}, + {0x71b9, 0x54}, + {0x71ba, 0xe7}, + {0x71bb, 0xc8}, + {0x71bc, 0xb4}, + {0x71bd, 0x1f}, + {0x71be, 0x56}, + {0x71bf, 0xaa}, + {0x71c0, 0xbc}, + {0x71c1, 0x08}, + {0x71c2, 0x57}, + {0x71c3, 0x00}, + {0x71c4, 0xb5}, + {0x71c5, 0x36}, + {0x71c6, 0x00}, + {0x71c7, 0x54}, + {0x71c8, 0xc8}, + {0x71c9, 0xb5}, + {0x71ca, 0x18}, + {0x71cb, 0xd9}, + {0x71cc, 0x00}, + {0x71cd, 0xbd}, + {0x71ce, 0x01}, + {0x71cf, 0x56}, + {0x71d0, 0x08}, + {0x71d1, 0x57}, + {0x71d2, 0xe8}, + {0x71d3, 0xb4}, + {0x71d4, 0x42}, + {0x71d5, 0x00}, + {0x71d6, 0x54}, + {0x71d7, 0xe7}, + {0x71d8, 0xc8}, + {0x71d9, 0xab}, + {0x71da, 0x00}, + {0x71db, 0x66}, + {0x71dc, 0x62}, + {0x71dd, 0x06}, + {0x71de, 0x74}, + {0x71df, 0xb9}, + {0x71e0, 0x05}, + {0x71e1, 0xb7}, + {0x71e2, 0x14}, + {0x71e3, 0x0e}, + {0x71e4, 0xb7}, + {0x71e5, 0x04}, + {0x71e6, 0xc8}, + {0x7600, 0x04}, + {0x7601, 0x80}, + {0x7602, 0x07}, + {0x7603, 0x44}, + {0x7604, 0x05}, + {0x7605, 0x33}, + {0x7606, 0x0f}, + {0x7607, 0x00}, + {0x7608, 0x07}, + {0x7609, 0x40}, + {0x760a, 0x04}, + {0x760b, 0xe5}, + {0x760c, 0x06}, + {0x760d, 0x50}, + {0x760e, 0x04}, + {0x760f, 0xe4}, + {0x7610, 0x00}, + {0x7611, 0x00}, + {0x7612, 0x06}, + {0x7613, 0x5c}, + {0x7614, 0x00}, + {0x7615, 0x0f}, + {0x7616, 0x06}, + {0x7617, 0x1c}, + {0x7618, 0x00}, + {0x7619, 0x02}, + {0x761a, 0x06}, + {0x761b, 0xa2}, + {0x761c, 0x00}, + {0x761d, 0x01}, + {0x761e, 0x06}, + {0x761f, 0xae}, + {0x7620, 0x00}, + {0x7621, 0x0e}, + {0x7622, 0x05}, + {0x7623, 0x30}, + {0x7624, 0x07}, + {0x7625, 0x00}, + {0x7626, 0x0f}, + {0x7627, 0x00}, + {0x7628, 0x04}, + {0x7629, 0xe5}, + {0x762a, 0x05}, + {0x762b, 0x33}, + {0x762c, 0x06}, + {0x762d, 0x12}, + {0x762e, 0x00}, + {0x762f, 0x01}, + {0x7630, 0x06}, + {0x7631, 0x52}, + {0x7632, 0x00}, + {0x7633, 0x01}, + {0x7634, 0x06}, + {0x7635, 0x5e}, + {0x7636, 0x04}, + {0x7637, 0xe4}, + {0x7638, 0x00}, + {0x7639, 0x01}, + {0x763a, 0x05}, + {0x763b, 0x30}, + {0x763c, 0x0f}, + {0x763d, 0x00}, + {0x763e, 0x06}, + {0x763f, 0xa6}, + {0x7640, 0x00}, + {0x7641, 0x02}, + {0x7642, 0x06}, + {0x7643, 0x26}, + {0x7644, 0x00}, + {0x7645, 0x02}, + {0x7646, 0x05}, + {0x7647, 0x33}, + {0x7648, 0x06}, + {0x7649, 0x20}, + {0x764a, 0x0f}, + {0x764b, 0x00}, + {0x764c, 0x06}, + {0x764d, 0x56}, + {0x764e, 0x00}, + {0x764f, 0x02}, + {0x7650, 0x06}, + {0x7651, 0x16}, + {0x7652, 0x05}, + {0x7653, 0x33}, + {0x7654, 0x06}, + {0x7655, 0x10}, + {0x7656, 0x0f}, + {0x7657, 0x00}, + {0x7658, 0x06}, + {0x7659, 0x10}, + {0x765a, 0x0f}, + {0x765b, 0x00}, + {0x765c, 0x06}, + {0x765d, 0x20}, + {0x765e, 0x0f}, + {0x765f, 0x00}, + {0x7660, 0x00}, + {0x7661, 0x00}, + {0x7662, 0x00}, + {0x7663, 0x02}, + {0x7664, 0x04}, + {0x7665, 0xe5}, + {0x7666, 0x04}, + {0x7667, 0xe4}, + {0x7668, 0x0f}, + {0x7669, 0x00}, + {0x766a, 0x00}, + {0x766b, 0x00}, + {0x766c, 0x00}, + {0x766d, 0x01}, + {0x766e, 0x04}, + {0x766f, 0xe5}, + {0x7670, 0x04}, + {0x7671, 0xe4}, + {0x7672, 0x0f}, + {0x7673, 0x00}, + {0x7674, 0x00}, + {0x7675, 0x02}, + {0x7676, 0x04}, + {0x7677, 0xe4}, + {0x7678, 0x00}, + {0x7679, 0x02}, + {0x767a, 0x04}, + {0x767b, 0xc4}, + {0x767c, 0x00}, + {0x767d, 0x02}, + {0x767e, 0x04}, + {0x767f, 0xc4}, + {0x7680, 0x05}, + {0x7681, 0x83}, + {0x7682, 0x0f}, + {0x7683, 0x00}, + {0x7684, 0x00}, + {0x7685, 0x02}, + {0x7686, 0x04}, + {0x7687, 0xe4}, + {0x7688, 0x00}, + {0x7689, 0x02}, + {0x768a, 0x04}, + {0x768b, 0xc4}, + {0x768c, 0x00}, + {0x768d, 0x02}, + {0x768e, 0x04}, + {0x768f, 0xc4}, + {0x7690, 0x05}, + {0x7691, 0x83}, + {0x7692, 0x03}, + {0x7693, 0x0b}, + {0x7694, 0x05}, + {0x7695, 0x83}, + {0x7696, 0x00}, + {0x7697, 0x07}, + {0x7698, 0x05}, + {0x7699, 0x03}, + {0x769a, 0x00}, + {0x769b, 0x05}, + {0x769c, 0x05}, + {0x769d, 0x32}, + {0x769e, 0x05}, + {0x769f, 0x30}, + {0x76a0, 0x00}, + {0x76a1, 0x02}, + {0x76a2, 0x05}, + {0x76a3, 0x78}, + {0x76a4, 0x00}, + {0x76a5, 0x01}, + {0x76a6, 0x05}, + {0x76a7, 0x7c}, + {0x76a8, 0x03}, + {0x76a9, 0x9a}, + {0x76aa, 0x05}, + {0x76ab, 0x83}, + {0x76ac, 0x00}, + {0x76ad, 0x04}, + {0x76ae, 0x05}, + {0x76af, 0x03}, + {0x76b0, 0x00}, + {0x76b1, 0x03}, + {0x76b2, 0x05}, + {0x76b3, 0x32}, + {0x76b4, 0x05}, + {0x76b5, 0x30}, + {0x76b6, 0x00}, + {0x76b7, 0x02}, + {0x76b8, 0x05}, + {0x76b9, 0x78}, + {0x76ba, 0x00}, + {0x76bb, 0x01}, + {0x76bc, 0x05}, + {0x76bd, 0x7c}, + {0x76be, 0x03}, + {0x76bf, 0x99}, + {0x76c0, 0x05}, + {0x76c1, 0x83}, + {0x76c2, 0x00}, + {0x76c3, 0x03}, + {0x76c4, 0x05}, + {0x76c5, 0x03}, + {0x76c6, 0x00}, + {0x76c7, 0x01}, + {0x76c8, 0x05}, + {0x76c9, 0x32}, + {0x76ca, 0x05}, + {0x76cb, 0x30}, + {0x76cc, 0x00}, + {0x76cd, 0x02}, + {0x76ce, 0x05}, + {0x76cf, 0x78}, + {0x76d0, 0x00}, + {0x76d1, 0x01}, + {0x76d2, 0x05}, + {0x76d3, 0x7c}, + {0x76d4, 0x03}, + {0x76d5, 0x98}, + {0x76d6, 0x05}, + {0x76d7, 0x83}, + {0x76d8, 0x00}, + {0x76d9, 0x00}, + {0x76da, 0x05}, + {0x76db, 0x03}, + {0x76dc, 0x00}, + {0x76dd, 0x01}, + {0x76de, 0x05}, + {0x76df, 0x32}, + {0x76e0, 0x05}, + {0x76e1, 0x30}, + {0x76e2, 0x00}, + {0x76e3, 0x02}, + {0x76e4, 0x05}, + {0x76e5, 0x78}, + {0x76e6, 0x00}, + {0x76e7, 0x01}, + {0x76e8, 0x05}, + {0x76e9, 0x7c}, + {0x76ea, 0x03}, + {0x76eb, 0x97}, + {0x76ec, 0x05}, + {0x76ed, 0x83}, + {0x76ee, 0x00}, + {0x76ef, 0x00}, + {0x76f0, 0x05}, + {0x76f1, 0x03}, + {0x76f2, 0x05}, + {0x76f3, 0x32}, + {0x76f4, 0x05}, + {0x76f5, 0x30}, + {0x76f6, 0x00}, + {0x76f7, 0x02}, + {0x76f8, 0x05}, + {0x76f9, 0x78}, + {0x76fa, 0x00}, + {0x76fb, 0x01}, + {0x76fc, 0x05}, + {0x76fd, 0x7c}, + {0x76fe, 0x03}, + {0x76ff, 0x96}, + {0x7700, 0x05}, + {0x7701, 0x83}, + {0x7702, 0x05}, + {0x7703, 0x03}, + {0x7704, 0x05}, + {0x7705, 0x32}, + {0x7706, 0x05}, + {0x7707, 0x30}, + {0x7708, 0x00}, + {0x7709, 0x02}, + {0x770a, 0x05}, + {0x770b, 0x78}, + {0x770c, 0x00}, + {0x770d, 0x01}, + {0x770e, 0x05}, + {0x770f, 0x7c}, + {0x7710, 0x03}, + {0x7711, 0x95}, + {0x7712, 0x05}, + {0x7713, 0x83}, + {0x7714, 0x05}, + {0x7715, 0x03}, + {0x7716, 0x05}, + {0x7717, 0x32}, + {0x7718, 0x05}, + {0x7719, 0x30}, + {0x771a, 0x00}, + {0x771b, 0x02}, + {0x771c, 0x05}, + {0x771d, 0x78}, + {0x771e, 0x00}, + {0x771f, 0x01}, + {0x7720, 0x05}, + {0x7721, 0x7c}, + {0x7722, 0x03}, + {0x7723, 0x94}, + {0x7724, 0x05}, + {0x7725, 0x83}, + {0x7726, 0x00}, + {0x7727, 0x01}, + {0x7728, 0x05}, + {0x7729, 0x03}, + {0x772a, 0x00}, + {0x772b, 0x01}, + {0x772c, 0x05}, + {0x772d, 0x32}, + {0x772e, 0x05}, + {0x772f, 0x30}, + {0x7730, 0x00}, + {0x7731, 0x02}, + {0x7732, 0x05}, + {0x7733, 0x78}, + {0x7734, 0x00}, + {0x7735, 0x01}, + {0x7736, 0x05}, + {0x7737, 0x7c}, + {0x7738, 0x03}, + {0x7739, 0x93}, + {0x773a, 0x05}, + {0x773b, 0x83}, + {0x773c, 0x00}, + {0x773d, 0x00}, + {0x773e, 0x05}, + {0x773f, 0x03}, + {0x7740, 0x00}, + {0x7741, 0x00}, + {0x7742, 0x05}, + {0x7743, 0x32}, + {0x7744, 0x05}, + {0x7745, 0x30}, + {0x7746, 0x00}, + {0x7747, 0x02}, + {0x7748, 0x05}, + {0x7749, 0x78}, + {0x774a, 0x00}, + {0x774b, 0x01}, + {0x774c, 0x05}, + {0x774d, 0x7c}, + {0x774e, 0x03}, + {0x774f, 0x92}, + {0x7750, 0x05}, + {0x7751, 0x83}, + {0x7752, 0x05}, + {0x7753, 0x03}, + {0x7754, 0x00}, + {0x7755, 0x00}, + {0x7756, 0x05}, + {0x7757, 0x32}, + {0x7758, 0x05}, + {0x7759, 0x30}, + {0x775a, 0x00}, + {0x775b, 0x02}, + {0x775c, 0x05}, + {0x775d, 0x78}, + {0x775e, 0x00}, + {0x775f, 0x01}, + {0x7760, 0x05}, + {0x7761, 0x7c}, + {0x7762, 0x03}, + {0x7763, 0x91}, + {0x7764, 0x05}, + {0x7765, 0x83}, + {0x7766, 0x05}, + {0x7767, 0x03}, + {0x7768, 0x05}, + {0x7769, 0x32}, + {0x776a, 0x05}, + {0x776b, 0x30}, + {0x776c, 0x00}, + {0x776d, 0x02}, + {0x776e, 0x05}, + {0x776f, 0x78}, + {0x7770, 0x00}, + {0x7771, 0x01}, + {0x7772, 0x05}, + {0x7773, 0x7c}, + {0x7774, 0x03}, + {0x7775, 0x90}, + {0x7776, 0x05}, + {0x7777, 0x83}, + {0x7778, 0x05}, + {0x7779, 0x03}, + {0x777a, 0x05}, + {0x777b, 0x32}, + {0x777c, 0x05}, + {0x777d, 0x30}, + {0x777e, 0x00}, + {0x777f, 0x02}, + {0x7780, 0x05}, + {0x7781, 0x78}, + {0x7782, 0x00}, + {0x7783, 0x01}, + {0x7784, 0x05}, + {0x7785, 0x7c}, + {0x7786, 0x02}, + {0x7787, 0x90}, + {0x7788, 0x05}, + {0x7789, 0x03}, + {0x778a, 0x07}, + {0x778b, 0x00}, + {0x778c, 0x0f}, + {0x778d, 0x00}, + {0x778e, 0x08}, + {0x778f, 0x30}, + {0x7790, 0x08}, + {0x7791, 0xee}, + {0x7792, 0x0f}, + {0x7793, 0x00}, + {0x7794, 0x05}, + {0x7795, 0x33}, + {0x7796, 0x04}, + {0x7797, 0xe5}, + {0x7798, 0x06}, + {0x7799, 0x52}, + {0x779a, 0x04}, + {0x779b, 0xe4}, + {0x779c, 0x00}, + {0x779d, 0x00}, + {0x779e, 0x06}, + {0x779f, 0x5e}, + {0x77a0, 0x00}, + {0x77a1, 0x0f}, + {0x77a2, 0x06}, + {0x77a3, 0x1e}, + {0x77a4, 0x00}, + {0x77a5, 0x02}, + {0x77a6, 0x06}, + {0x77a7, 0xa2}, + {0x77a8, 0x00}, + {0x77a9, 0x01}, + {0x77aa, 0x06}, + {0x77ab, 0xae}, + {0x77ac, 0x00}, + {0x77ad, 0x03}, + {0x77ae, 0x05}, + {0x77af, 0x30}, + {0x77b0, 0x09}, + {0x77b1, 0x19}, + {0x77b2, 0x0f}, + {0x77b3, 0x00}, + {0x77b4, 0x05}, + {0x77b5, 0x33}, + {0x77b6, 0x04}, + {0x77b7, 0xe5}, + {0x77b8, 0x06}, + {0x77b9, 0x52}, + {0x77ba, 0x04}, + {0x77bb, 0xe4}, + {0x77bc, 0x00}, + {0x77bd, 0x00}, + {0x77be, 0x06}, + {0x77bf, 0x5e}, + {0x77c0, 0x00}, + {0x77c1, 0x0f}, + {0x77c2, 0x06}, + {0x77c3, 0x1e}, + {0x77c4, 0x00}, + {0x77c5, 0x02}, + {0x77c6, 0x06}, + {0x77c7, 0xa2}, + {0x77c8, 0x00}, + {0x77c9, 0x01}, + {0x77ca, 0x06}, + {0x77cb, 0xae}, + {0x77cc, 0x00}, + {0x77cd, 0x03}, + {0x77ce, 0x05}, + {0x77cf, 0x30}, + {0x77d0, 0x0f}, + {0x77d1, 0x00}, + {0x77d2, 0x00}, + {0x77d3, 0x00}, + {0x77d4, 0x00}, + {0x77d5, 0x02}, + {0x77d6, 0x04}, + {0x77d7, 0xe5}, + {0x77d8, 0x04}, + {0x77d9, 0xe4}, + {0x77da, 0x05}, + {0x77db, 0x33}, + {0x77dc, 0x07}, + {0x77dd, 0x10}, + {0x77de, 0x00}, + {0x77df, 0x00}, + {0x77e0, 0x01}, + {0x77e1, 0xbb}, + {0x77e2, 0x00}, + {0x77e3, 0x00}, + {0x77e4, 0x01}, + {0x77e5, 0xaa}, + {0x77e6, 0x00}, + {0x77e7, 0x00}, + {0x77e8, 0x01}, + {0x77e9, 0x99}, + {0x77ea, 0x00}, + {0x77eb, 0x00}, + {0x77ec, 0x01}, + {0x77ed, 0x88}, + {0x77ee, 0x00}, + {0x77ef, 0x00}, + {0x77f0, 0x01}, + {0x77f1, 0x77}, + {0x77f2, 0x00}, + {0x77f3, 0x00}, + {0x77f4, 0x01}, + {0x77f5, 0x66}, + {0x77f6, 0x00}, + {0x77f7, 0x00}, + {0x77f8, 0x01}, + {0x77f9, 0x55}, + {0x77fa, 0x00}, + {0x77fb, 0x00}, + {0x77fc, 0x01}, + {0x77fd, 0x44}, + {0x77fe, 0x00}, + {0x77ff, 0x00}, + {0x7800, 0x01}, + {0x7801, 0x33}, + {0x7802, 0x00}, + {0x7803, 0x00}, + {0x7804, 0x01}, + {0x7805, 0x22}, + {0x7806, 0x00}, + {0x7807, 0x00}, + {0x7808, 0x01}, + {0x7809, 0x11}, + {0x780a, 0x00}, + {0x780b, 0x00}, + {0x780c, 0x01}, + {0x780d, 0x00}, + {0x780e, 0x01}, + {0x780f, 0xff}, + {0x7810, 0x07}, + {0x7811, 0x00}, + {0x7812, 0x02}, + {0x7813, 0xa0}, + {0x7814, 0x0f}, + {0x7815, 0x00}, + {0x7816, 0x08}, + {0x7817, 0x35}, + {0x7818, 0x06}, + {0x7819, 0x52}, + {0x781a, 0x04}, + {0x781b, 0xe4}, + {0x781c, 0x00}, + {0x781d, 0x00}, + {0x781e, 0x06}, + {0x781f, 0x5e}, + {0x7820, 0x05}, + {0x7821, 0x33}, + {0x7822, 0x09}, + {0x7823, 0x19}, + {0x7824, 0x06}, + {0x7825, 0x1e}, + {0x7826, 0x05}, + {0x7827, 0x33}, + {0x7828, 0x00}, + {0x7829, 0x01}, + {0x782a, 0x06}, + {0x782b, 0x24}, + {0x782c, 0x06}, + {0x782d, 0x20}, + {0x782e, 0x0f}, + {0x782f, 0x00}, + {0x7830, 0x08}, + {0x7831, 0x35}, + {0x7832, 0x07}, + {0x7833, 0x10}, + {0x7834, 0x00}, + {0x7835, 0x00}, + {0x7836, 0x01}, + {0x7837, 0xbb}, + {0x7838, 0x00}, + {0x7839, 0x00}, + {0x783a, 0x01}, + {0x783b, 0xaa}, + {0x783c, 0x00}, + {0x783d, 0x00}, + {0x783e, 0x01}, + {0x783f, 0x99}, + {0x7840, 0x00}, + {0x7841, 0x00}, + {0x7842, 0x01}, + {0x7843, 0x88}, + {0x7844, 0x00}, + {0x7845, 0x00}, + {0x7846, 0x01}, + {0x7847, 0x77}, + {0x7848, 0x00}, + {0x7849, 0x00}, + {0x784a, 0x01}, + {0x784b, 0x66}, + {0x784c, 0x00}, + {0x784d, 0x00}, + {0x784e, 0x01}, + {0x784f, 0x55}, + {0x7850, 0x00}, + {0x7851, 0x00}, + {0x7852, 0x01}, + {0x7853, 0x44}, + {0x7854, 0x00}, + {0x7855, 0x00}, + {0x7856, 0x01}, + {0x7857, 0x33}, + {0x7858, 0x00}, + {0x7859, 0x00}, + {0x785a, 0x01}, + {0x785b, 0x22}, + {0x785c, 0x00}, + {0x785d, 0x00}, + {0x785e, 0x01}, + {0x785f, 0x11}, + {0x7860, 0x00}, + {0x7861, 0x00}, + {0x7862, 0x01}, + {0x7863, 0x00}, + {0x7864, 0x07}, + {0x7865, 0x00}, + {0x7866, 0x01}, + {0x7867, 0xff}, + {0x7868, 0x02}, + {0x7869, 0xa0}, + {0x786a, 0x0f}, + {0x786b, 0x00}, + {0x786c, 0x08}, + {0x786d, 0x3a}, + {0x786e, 0x08}, + {0x786f, 0x6a}, + {0x7870, 0x0f}, + {0x7871, 0x00}, + {0x7872, 0x04}, + {0x7873, 0xc0}, + {0x7874, 0x09}, + {0x7875, 0x19}, + {0x7876, 0x04}, + {0x7877, 0x99}, + {0x7878, 0x07}, + {0x7879, 0x14}, + {0x787a, 0x00}, + {0x787b, 0x01}, + {0x787c, 0x04}, + {0x787d, 0xa4}, + {0x787e, 0x00}, + {0x787f, 0x07}, + {0x7880, 0x04}, + {0x7881, 0xa6}, + {0x7882, 0x00}, + {0x7883, 0x00}, + {0x7884, 0x04}, + {0x7885, 0xa0}, + {0x7886, 0x04}, + {0x7887, 0x80}, + {0x7888, 0x04}, + {0x7889, 0x00}, + {0x788a, 0x05}, + {0x788b, 0x03}, + {0x788c, 0x06}, + {0x788d, 0x00}, + {0x788e, 0x0f}, + {0x788f, 0x00}, + {0x7890, 0x0f}, + {0x7891, 0x00}, + {0x7892, 0x0f}, + {0x7893, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x05}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x88}, + {0x30ae, 0x04}, + {0x30af, 0x40}, + {0x30b0, 0x0d}, + {0x30b1, 0xde}, + {0x30b2, 0x04}, + {0x30b3, 0x66}, + {0x30b6, 0x01}, + {0x30b7, 0x15}, + {0x3196, 0x00}, + {0x3197, 0x0a}, + {0x3195, 0x29}, + {0x315a, 0x02}, + {0x315b, 0x00}, + {0x30bb, 0x40}, + {0x3250, 0xf7}, + {0x30a8, 0x00}, + {0x30a9, 0x04}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x80}, + {0x30ae, 0x04}, + {0x30af, 0x38}, + {0x3012, 0x01}, +}; + +struct vvcam_sccb_array ov2775_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(ov2775_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = ov2775_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam/native/sensor/omnivision_ov2775/ov2775_reg_cfg.h b/vvcam/native/sensor/omnivision_ov2775/ov2775_reg_cfg.h new file mode 100755 index 0000000..447b672 --- /dev/null +++ b/vvcam/native/sensor/omnivision_ov2775/ov2775_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OV2775_REG_CFG_H_ +#define _OV2775_REG_CFG_H_ + +extern struct vvcam_sccb_array ov2775_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam/native/sensor/omnivision_ov5693/ov5693_driver.c b/vvcam/native/sensor/omnivision_ov5693/ov5693_driver.c new file mode 100755 index 0000000..80cbd39 --- /dev/null +++ b/vvcam/native/sensor/omnivision_ov5693/ov5693_driver.c @@ -0,0 +1,442 @@ +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "ov5693_reg_cfg.h" + +#define SENSOR_CLK 51000000 + +static struct vvcam_mode_info pov5693_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_array *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pov5693_mode_info); + + memcpy(pmode_info_arry->modes,pov5693_mode_info,sizeof(pov5693_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} + +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pov5693_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pov5693_mode_info[i].index == pmode->index) + { + psensor_mode = &(pov5693_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&ov5693_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&ov5693_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x100, 0x01); + }else + { + ret = sensor_write_reg(ctx, 0x100, 0x0); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s ov5693_function = +{ + .sensor_name = "ov5693", + .reserve_id = 0x5600, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam/native/sensor/omnivision_ov5693/ov5693_driver.h b/vvcam/native/sensor/omnivision_ov5693/ov5693_driver.h new file mode 100755 index 0000000..f8e5acd --- /dev/null +++ b/vvcam/native/sensor/omnivision_ov5693/ov5693_driver.h @@ -0,0 +1,7 @@ +#ifndef _OMNIVISION_OV5693_H_ +#define _OMNIVISION_OV5693_H_ + +extern struct vvcam_sensor_function_s ov5693_function; + + +#endif diff --git a/vvcam/native/sensor/omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.c b/vvcam/native/sensor/omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..a9261be --- /dev/null +++ b/vvcam/native/sensor/omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,1827 @@ +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data ov5693_mipi4lane_1080p_30fps_linear_reg[] = { + {0x3000, 0x02}, + {0x3001, 0x28}, + {0x3002, 0x03}, + {0x3003, 0x01}, + {0x3004, 0x05}, + {0x3005, 0x26}, + {0x3006, 0x00}, + {0x3007, 0x07}, + {0x3008, 0x01}, + {0x3009, 0x00}, + {0x300c, 0x6c}, + {0x300e, 0x80}, + {0x300f, 0x00}, + {0x3012, 0x00}, + {0x3013, 0x00}, + {0x3014, 0xc4}, + {0x3015, 0x00}, + {0x3017, 0x00}, + {0x3018, 0x00}, + {0x3019, 0x00}, + {0x301a, 0x00}, + {0x301b, 0x0e}, + {0x301e, 0x17}, + {0x301f, 0xe1}, + {0x3030, 0x02}, + {0x3031, 0x62}, + {0x3032, 0xf0}, + {0x3033, 0x30}, + {0x3034, 0x3f}, + {0x3035, 0x5f}, + {0x3036, 0x02}, + {0x3037, 0x9f}, + {0x3038, 0x04}, + {0x3039, 0xb7}, + {0x303a, 0x04}, + {0x303b, 0x07}, + {0x303c, 0xf0}, + {0x303d, 0x00}, + {0x303e, 0x0b}, + {0x303f, 0xe3}, + {0x3040, 0xf3}, + {0x3041, 0x29}, + {0x3042, 0xf6}, + {0x3043, 0x65}, + {0x3044, 0x06}, + {0x3045, 0x0f}, + {0x3046, 0x59}, + {0x3047, 0x07}, + {0x3048, 0x82}, + {0x3049, 0xcf}, + {0x304a, 0x12}, + {0x304b, 0x40}, + {0x304c, 0x33}, + {0x304d, 0xa4}, + {0x304e, 0x0b}, + {0x304f, 0x3d}, + {0x3050, 0x10}, + {0x3060, 0x00}, + {0x3061, 0x64}, + {0x3062, 0x00}, + {0x3063, 0xe4}, + {0x3066, 0x80}, + {0x3080, 0x00}, + {0x3081, 0x00}, + {0x3082, 0x01}, + {0x3083, 0xe3}, + {0x3084, 0x06}, + {0x3085, 0x00}, + {0x3086, 0x10}, + {0x3087, 0x10}, + {0x3089, 0x00}, + {0x308a, 0x01}, + {0x3093, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x00}, + {0x30aa, 0x00}, + {0x30ab, 0x00}, + {0x30ac, 0x07}, + {0x30ad, 0x90}, + {0x30ae, 0x04}, + {0x30af, 0x48}, + {0x30b0, 0x04}, + {0x30b1, 0x7e}, + {0x30b2, 0x04}, + {0x30b3, 0x65}, + {0x30b4, 0x00}, + {0x30b5, 0x00}, + {0x30b6, 0x00}, + {0x30b7, 0x10}, + {0x30b8, 0x00}, + {0x30b9, 0x02}, + {0x30ba, 0x10}, + {0x30bb, 0x00}, + {0x30bc, 0x00}, + {0x30bd, 0x03}, + {0x30be, 0x5c}, + {0x30bf, 0x00}, + {0x30c0, 0x05}, + {0x30c1, 0x00}, + {0x30c2, 0x20}, + {0x30c3, 0x00}, + {0x30c4, 0x4a}, + {0x30c5, 0x00}, + {0x30c7, 0x00}, + {0x30c8, 0x00}, + {0x30d1, 0x00}, + {0x30d2, 0x00}, + {0x30d3, 0x80}, + {0x30d4, 0x00}, + {0x30d9, 0x09}, + {0x30da, 0x64}, + {0x30dd, 0x00}, + {0x30de, 0x16}, + {0x30df, 0x00}, + {0x30e0, 0x17}, + {0x30e1, 0x00}, + {0x30e2, 0x18}, + {0x30e3, 0x10}, + {0x30e4, 0x04}, + {0x30e5, 0x00}, + {0x30e6, 0x00}, + {0x30e7, 0x00}, + {0x30e8, 0x00}, + {0x30e9, 0x00}, + {0x30ea, 0x00}, + {0x30eb, 0x00}, + {0x30ec, 0x00}, + {0x30ed, 0x00}, + {0x3101, 0x00}, + {0x3102, 0x00}, + {0x3103, 0x00}, + {0x3104, 0x00}, + {0x3105, 0x8c}, + {0x3106, 0x87}, + {0x3107, 0xc0}, + {0x3108, 0x9d}, + {0x3109, 0x8d}, + {0x310a, 0x8d}, + {0x310b, 0x6a}, + {0x310c, 0x3a}, + {0x310d, 0x5a}, + {0x310e, 0x00}, + {0x3120, 0x00}, + {0x3121, 0x00}, + {0x3122, 0x00}, + {0x3123, 0xf0}, + {0x3124, 0x00}, + {0x3125, 0x70}, + {0x3126, 0x1f}, + {0x3127, 0x0f}, + {0x3128, 0x00}, + {0x3129, 0x3a}, + {0x312a, 0x02}, + {0x312b, 0x0f}, + {0x312c, 0x00}, + {0x312d, 0x0f}, + {0x312e, 0x1d}, + {0x312f, 0x00}, + {0x3130, 0x00}, + {0x3131, 0x00}, + {0x3132, 0x00}, + {0x3140, 0x0a}, + {0x3141, 0x03}, + {0x3142, 0x00}, + {0x3143, 0x00}, + {0x3144, 0x00}, + {0x3145, 0x00}, + {0x3146, 0x00}, + {0x3147, 0x00}, + {0x3148, 0x00}, + {0x3149, 0x00}, + {0x314a, 0x00}, + {0x314b, 0x00}, + {0x314c, 0x00}, + {0x314d, 0x00}, + {0x314e, 0x1c}, + {0x314f, 0xff}, + {0x3150, 0xff}, + {0x3151, 0xff}, + {0x3152, 0x10}, + {0x3153, 0x10}, + {0x3154, 0x10}, + {0x3155, 0x00}, + {0x3156, 0x03}, + {0x3157, 0x00}, + {0x3158, 0x0f}, + {0x3159, 0xff}, + {0x315a, 0x01}, + {0x315b, 0x00}, + {0x315c, 0x01}, + {0x315d, 0x00}, + {0x315e, 0x01}, + {0x315f, 0x00}, + {0x3160, 0x00}, + {0x3161, 0x40}, + {0x3162, 0x00}, + {0x3163, 0x40}, + {0x3164, 0x00}, + {0x3165, 0x40}, + {0x3190, 0x08}, + {0x3191, 0x99}, + {0x3193, 0x08}, + {0x3194, 0x13}, + {0x3195, 0x33}, + {0x3196, 0x00}, + {0x3197, 0x10}, + {0x3198, 0x00}, + {0x3199, 0x7f}, + {0x319a, 0x80}, + {0x319b, 0xff}, + {0x319c, 0x80}, + {0x319d, 0xbf}, + {0x319e, 0xc0}, + {0x319f, 0xff}, + {0x31a0, 0x24}, + {0x31a1, 0x55}, + {0x31a2, 0x00}, + {0x31a3, 0x00}, + {0x31a6, 0x00}, + {0x31a7, 0x00}, + {0x31b0, 0x00}, + {0x31b1, 0x00}, + {0x31b2, 0x02}, + {0x31b3, 0x00}, + {0x31b4, 0x00}, + {0x31b5, 0x01}, + {0x31b6, 0x00}, + {0x31b7, 0x00}, + {0x31b8, 0x00}, + {0x31b9, 0x00}, + {0x31ba, 0x00}, + {0x31d0, 0x3c}, + {0x31d1, 0x34}, + {0x31d2, 0x3c}, + {0x31d3, 0x00}, + {0x31d4, 0x2d}, + {0x31d5, 0x00}, + {0x31d6, 0x01}, + {0x31d7, 0x06}, + {0x31d8, 0x00}, + {0x31d9, 0x64}, + {0x31da, 0x00}, + {0x31db, 0x30}, + {0x31dc, 0x04}, + {0x31dd, 0x69}, + {0x31de, 0x0a}, + {0x31df, 0x3c}, + {0x31e0, 0x04}, + {0x31e1, 0x32}, + {0x31e2, 0x00}, + {0x31e3, 0x00}, + {0x31e4, 0x08}, + {0x31e5, 0x80}, + {0x31e6, 0x00}, + {0x31e7, 0x2c}, + {0x31e8, 0x6c}, + {0x31e9, 0xac}, + {0x31ea, 0xec}, + {0x31eb, 0x3f}, + {0x31ec, 0x0f}, + {0x31ed, 0x20}, + {0x31ee, 0x04}, + {0x31ef, 0x48}, + {0x31f0, 0x07}, + {0x31f1, 0x90}, + {0x31f2, 0x04}, + {0x31f3, 0x48}, + {0x31f4, 0x07}, + {0x31f5, 0x90}, + {0x31f6, 0x04}, + {0x31f7, 0x48}, + {0x31f8, 0x07}, + {0x31f9, 0x90}, + {0x31fa, 0x04}, + {0x31fb, 0x48}, + {0x31fd, 0xcb}, + {0x31fe, 0x0f}, + {0x31ff, 0x03}, + {0x3200, 0x00}, + {0x3201, 0xff}, + {0x3202, 0x00}, + {0x3203, 0xff}, + {0x3204, 0xff}, + {0x3205, 0xff}, + {0x3206, 0xff}, + {0x3207, 0xff}, + {0x3208, 0xff}, + {0x3209, 0xff}, + {0x320a, 0xff}, + {0x320b, 0x1b}, + {0x320c, 0x1f}, + {0x320d, 0x1e}, + {0x320e, 0x30}, + {0x320f, 0x2d}, + {0x3210, 0x2c}, + {0x3211, 0x2b}, + {0x3212, 0x2a}, + {0x3213, 0x24}, + {0x3214, 0x22}, + {0x3215, 0x00}, + {0x3216, 0x04}, + {0x3217, 0x2c}, + {0x3218, 0x6c}, + {0x3219, 0xac}, + {0x321a, 0xec}, + {0x321b, 0x00}, + {0x3230, 0x3a}, + {0x3231, 0x00}, + {0x3232, 0x80}, + {0x3233, 0x00}, + {0x3234, 0x10}, + {0x3235, 0xaa}, + {0x3236, 0x55}, + {0x3237, 0x99}, + {0x3238, 0x66}, + {0x3239, 0x08}, + {0x323a, 0x88}, + {0x323b, 0x00}, + {0x323c, 0x00}, + {0x323d, 0x03}, + {0x3250, 0x33}, + {0x3251, 0x00}, + {0x3252, 0x20}, + {0x3253, 0x00}, + {0x3254, 0x00}, + {0x3255, 0x01}, + {0x3256, 0x00}, + {0x3257, 0x00}, + {0x3258, 0x00}, + {0x3270, 0x01}, + {0x3271, 0x60}, + {0x3272, 0xc0}, + {0x3273, 0x00}, + {0x3274, 0x80}, + {0x3275, 0x40}, + {0x3276, 0x02}, + {0x3277, 0x08}, + {0x3278, 0x10}, + {0x3279, 0x04}, + {0x327a, 0x00}, + {0x327b, 0x03}, + {0x327c, 0x10}, + {0x327d, 0x60}, + {0x327e, 0xc0}, + {0x327f, 0x06}, + {0x3288, 0x10}, + {0x3289, 0x00}, + {0x328a, 0x08}, + {0x328b, 0x00}, + {0x328c, 0x04}, + {0x328d, 0x00}, + {0x328e, 0x02}, + {0x328f, 0x00}, + {0x3290, 0x20}, + {0x3291, 0x00}, + {0x3292, 0x10}, + {0x3293, 0x00}, + {0x3294, 0x08}, + {0x3295, 0x00}, + {0x3296, 0x04}, + {0x3297, 0x00}, + {0x3298, 0x40}, + {0x3299, 0x00}, + {0x329a, 0x20}, + {0x329b, 0x00}, + {0x329c, 0x10}, + {0x329d, 0x00}, + {0x329e, 0x08}, + {0x329f, 0x00}, + {0x32a0, 0x7f}, + {0x32a1, 0xff}, + {0x32a2, 0x40}, + {0x32a3, 0x00}, + {0x32a4, 0x20}, + {0x32a5, 0x00}, + {0x32a6, 0x10}, + {0x32a7, 0x00}, + {0x32a8, 0x00}, + {0x32a9, 0x00}, + {0x32aa, 0x00}, + {0x32ab, 0x00}, + {0x32ac, 0x00}, + {0x32ad, 0x00}, + {0x32ae, 0x00}, + {0x32af, 0x00}, + {0x32b0, 0x00}, + {0x32b1, 0x00}, + {0x32b2, 0x00}, + {0x32b3, 0x00}, + {0x32b4, 0x00}, + {0x32b5, 0x00}, + {0x32b6, 0x00}, + {0x32b7, 0x00}, + {0x32b8, 0x00}, + {0x32b9, 0x00}, + {0x32ba, 0x00}, + {0x32bb, 0x00}, + {0x32bc, 0x00}, + {0x32bd, 0x00}, + {0x32be, 0x00}, + {0x32bf, 0x00}, + {0x32c0, 0x00}, + {0x32c1, 0x00}, + {0x32c2, 0x00}, + {0x32c3, 0x00}, + {0x32c4, 0x00}, + {0x32c5, 0x00}, + {0x32c6, 0x00}, + {0x32c7, 0x00}, + {0x32c8, 0x87}, + {0x32c9, 0x00}, + {0x3330, 0x03}, + {0x3331, 0xc8}, + {0x3332, 0x02}, + {0x3333, 0x24}, + {0x3334, 0x00}, + {0x3335, 0x00}, + {0x3336, 0x00}, + {0x3337, 0x00}, + {0x3338, 0x03}, + {0x3339, 0xc8}, + {0x333a, 0x02}, + {0x333b, 0x24}, + {0x333c, 0x00}, + {0x333d, 0x00}, + {0x333e, 0x00}, + {0x333f, 0x00}, + {0x3340, 0x03}, + {0x3341, 0xc8}, + {0x3342, 0x02}, + {0x3343, 0x24}, + {0x3344, 0x00}, + {0x3345, 0x00}, + {0x3346, 0x00}, + {0x3347, 0x00}, + {0x3348, 0x40}, + {0x3349, 0x00}, + {0x334a, 0x00}, + {0x334b, 0x00}, + {0x334c, 0x00}, + {0x334d, 0x00}, + {0x334e, 0x80}, + {0x3360, 0x01}, + {0x3361, 0x00}, + {0x3362, 0x01}, + {0x3363, 0x00}, + {0x3364, 0x01}, + {0x3365, 0x00}, + {0x3366, 0x01}, + {0x3367, 0x00}, + {0x3368, 0x01}, + {0x3369, 0x00}, + {0x336a, 0x01}, + {0x336b, 0x00}, + {0x336c, 0x01}, + {0x336d, 0x00}, + {0x336e, 0x01}, + {0x336f, 0x00}, + {0x3370, 0x01}, + {0x3371, 0x00}, + {0x3372, 0x01}, + {0x3373, 0x00}, + {0x3374, 0x01}, + {0x3375, 0x00}, + {0x3376, 0x01}, + {0x3377, 0x00}, + {0x3378, 0x00}, + {0x3379, 0x00}, + {0x337a, 0x00}, + {0x337b, 0x00}, + {0x337c, 0x00}, + {0x337d, 0x00}, + {0x337e, 0x00}, + {0x337f, 0x00}, + {0x3380, 0x00}, + {0x3381, 0x00}, + {0x3382, 0x00}, + {0x3383, 0x00}, + {0x3384, 0x00}, + {0x3385, 0x00}, + {0x3386, 0x00}, + {0x3387, 0x00}, + {0x3388, 0x00}, + {0x3389, 0x00}, + {0x338a, 0x00}, + {0x338b, 0x00}, + {0x338c, 0x00}, + {0x338d, 0x00}, + {0x338e, 0x00}, + {0x338f, 0x00}, + {0x3390, 0x00}, + {0x3391, 0x00}, + {0x3392, 0x00}, + {0x3393, 0x00}, + {0x3394, 0x00}, + {0x3395, 0x00}, + {0x3396, 0x00}, + {0x3397, 0x00}, + {0x3398, 0x00}, + {0x3399, 0x00}, + {0x339a, 0x00}, + {0x339b, 0x00}, + {0x33b0, 0x00}, + {0x33b1, 0x50}, + {0x33b2, 0x01}, + {0x33b3, 0xff}, + {0x33b4, 0xe0}, + {0x33b5, 0x6b}, + {0x33b6, 0x00}, + {0x33b7, 0x00}, + {0x33b8, 0x00}, + {0x33b9, 0x00}, + {0x33ba, 0x00}, + {0x33bb, 0x1f}, + {0x33bc, 0x01}, + {0x33bd, 0x01}, + {0x33be, 0x01}, + {0x33bf, 0x01}, + {0x33c0, 0x00}, + {0x33c1, 0x00}, + {0x33c2, 0x00}, + {0x33c3, 0x00}, + {0x33e0, 0x14}, + {0x33e1, 0x0f}, + {0x33e2, 0x02}, + {0x33e3, 0x01}, + {0x33e4, 0x01}, + {0x33e5, 0x01}, + {0x33e6, 0x00}, + {0x33e7, 0x04}, + {0x33e8, 0x0c}, + {0x33e9, 0x02}, + {0x33ea, 0x02}, + {0x33eb, 0x02}, + {0x33ec, 0x03}, + {0x33ed, 0x01}, + {0x33ee, 0x02}, + {0x33ef, 0x08}, + {0x33f0, 0x08}, + {0x33f1, 0x04}, + {0x33f2, 0x04}, + {0x33f3, 0x00}, + {0x33f4, 0x03}, + {0x33f5, 0x14}, + {0x33f6, 0x0f}, + {0x33f7, 0x02}, + {0x33f8, 0x01}, + {0x33f9, 0x01}, + {0x33fa, 0x01}, + {0x33fb, 0x00}, + {0x33fc, 0x04}, + {0x33fd, 0x0c}, + {0x33fe, 0x02}, + {0x33ff, 0x02}, + {0x3400, 0x02}, + {0x3401, 0x03}, + {0x3402, 0x01}, + {0x3403, 0x02}, + {0x3404, 0x08}, + {0x3405, 0x08}, + {0x3406, 0x04}, + {0x3407, 0x04}, + {0x3408, 0x00}, + {0x3409, 0x03}, + {0x340a, 0x14}, + {0x340b, 0x0f}, + {0x340c, 0x04}, + {0x340d, 0x02}, + {0x340e, 0x01}, + {0x340f, 0x01}, + {0x3410, 0x00}, + {0x3411, 0x04}, + {0x3412, 0x0c}, + {0x3413, 0x02}, + {0x3414, 0x02}, + {0x3415, 0x02}, + {0x3416, 0x03}, + {0x3417, 0x02}, + {0x3418, 0x05}, + {0x3419, 0x0a}, + {0x341a, 0x08}, + {0x341b, 0x04}, + {0x341c, 0x04}, + {0x341d, 0x00}, + {0x341e, 0x03}, + {0x3440, 0x00}, + {0x3441, 0x00}, + {0x3442, 0x00}, + {0x3443, 0x00}, + {0x3444, 0x02}, + {0x3445, 0xf0}, + {0x3446, 0x02}, + {0x3447, 0x08}, + {0x3448, 0x00}, + {0x3460, 0x40}, + {0x3461, 0x40}, + {0x3462, 0x40}, + {0x3463, 0x40}, + {0x3464, 0x03}, + {0x3465, 0x01}, + {0x3466, 0x01}, + {0x3467, 0x02}, + {0x3468, 0x30}, + {0x3469, 0x00}, + {0x346a, 0x33}, + {0x346b, 0xbf}, + {0x3480, 0x40}, + {0x3481, 0x00}, + {0x3482, 0x00}, + {0x3483, 0x00}, + {0x3484, 0x0d}, + {0x3485, 0x00}, + {0x3486, 0x00}, + {0x3487, 0x00}, + {0x3488, 0x00}, + {0x3489, 0x00}, + {0x348a, 0x00}, + {0x348b, 0x04}, + {0x348c, 0x00}, + {0x348d, 0x01}, + {0x348f, 0x01}, + {0x3030, 0x0a}, + {0x3030, 0x02}, + {0x7000, 0x58}, + {0x7001, 0x7a}, + {0x7002, 0x1a}, + {0x7003, 0xc1}, + {0x7004, 0x03}, + {0x7005, 0xda}, + {0x7006, 0xbd}, + {0x7007, 0x03}, + {0x7008, 0xbd}, + {0x7009, 0x06}, + {0x700a, 0xe6}, + {0x700b, 0xec}, + {0x700c, 0xbc}, + {0x700d, 0xff}, + {0x700e, 0xbc}, + {0x700f, 0x73}, + {0x7010, 0xda}, + {0x7011, 0x72}, + {0x7012, 0x76}, + {0x7013, 0xb6}, + {0x7014, 0xee}, + {0x7015, 0xcf}, + {0x7016, 0xac}, + {0x7017, 0xd0}, + {0x7018, 0xac}, + {0x7019, 0xd1}, + {0x701a, 0x50}, + {0x701b, 0xac}, + {0x701c, 0xd2}, + {0x701d, 0xbc}, + {0x701e, 0x2e}, + {0x701f, 0xb4}, + {0x7020, 0x00}, + {0x7021, 0xdc}, + {0x7022, 0xdf}, + {0x7023, 0xb0}, + {0x7024, 0x6e}, + {0x7025, 0xbd}, + {0x7026, 0x01}, + {0x7027, 0xd7}, + {0x7028, 0xed}, + {0x7029, 0xe1}, + {0x702a, 0x36}, + {0x702b, 0x30}, + {0x702c, 0xd3}, + {0x702d, 0x2e}, + {0x702e, 0x54}, + {0x702f, 0x46}, + {0x7030, 0xbc}, + {0x7031, 0x22}, + {0x7032, 0x66}, + {0x7033, 0xbc}, + {0x7034, 0x24}, + {0x7035, 0x2c}, + {0x7036, 0x28}, + {0x7037, 0xbc}, + {0x7038, 0x3c}, + {0x7039, 0xa1}, + {0x703a, 0xac}, + {0x703b, 0xd8}, + {0x703c, 0xd6}, + {0x703d, 0xb4}, + {0x703e, 0x04}, + {0x703f, 0x46}, + {0x7040, 0xb7}, + {0x7041, 0x04}, + {0x7042, 0xbe}, + {0x7043, 0x08}, + {0x7044, 0xc3}, + {0x7045, 0xd9}, + {0x7046, 0xad}, + {0x7047, 0xc3}, + {0x7048, 0xbc}, + {0x7049, 0x19}, + {0x704a, 0xc1}, + {0x704b, 0x27}, + {0x704c, 0xe7}, + {0x704d, 0x00}, + {0x704e, 0x50}, + {0x704f, 0x20}, + {0x7050, 0xb8}, + {0x7051, 0x02}, + {0x7052, 0xbc}, + {0x7053, 0x17}, + {0x7054, 0xdb}, + {0x7055, 0xc7}, + {0x7056, 0xb8}, + {0x7057, 0x00}, + {0x7058, 0x28}, + {0x7059, 0x54}, + {0x705a, 0xb4}, + {0x705b, 0x14}, + {0x705c, 0xab}, + {0x705d, 0xbe}, + {0x705e, 0x06}, + {0x705f, 0xd8}, + {0x7060, 0xd6}, + {0x7061, 0x00}, + {0x7062, 0xb4}, + {0x7063, 0xc7}, + {0x7064, 0x07}, + {0x7065, 0xb9}, + {0x7066, 0x05}, + {0x7067, 0xee}, + {0x7068, 0xe6}, + {0x7069, 0xad}, + {0x706a, 0xb4}, + {0x706b, 0x26}, + {0x706c, 0x19}, + {0x706d, 0xc1}, + {0x706e, 0x3a}, + {0x706f, 0xc3}, + {0x7070, 0xaf}, + {0x7071, 0x00}, + {0x7072, 0xc0}, + {0x7073, 0x3c}, + {0x7074, 0xc3}, + {0x7075, 0xbe}, + {0x7076, 0xe7}, + {0x7077, 0x00}, + {0x7078, 0x15}, + {0x7079, 0xc2}, + {0x707a, 0x40}, + {0x707b, 0xc3}, + {0x707c, 0xa4}, + {0x707d, 0xc0}, + {0x707e, 0x3c}, + {0x707f, 0x00}, + {0x7080, 0xb9}, + {0x7081, 0x64}, + {0x7082, 0x29}, + {0x7083, 0x00}, + {0x7084, 0xb8}, + {0x7085, 0x12}, + {0x7086, 0xbe}, + {0x7087, 0x01}, + {0x7088, 0xd0}, + {0x7089, 0xbc}, + {0x708a, 0x01}, + {0x708b, 0xac}, + {0x708c, 0x37}, + {0x708d, 0xd2}, + {0x708e, 0xac}, + {0x708f, 0x45}, + {0x7090, 0xad}, + {0x7091, 0x28}, + {0x7092, 0x00}, + {0x7093, 0xb8}, + {0x7094, 0x00}, + {0x7095, 0xbc}, + {0x7096, 0x01}, + {0x7097, 0x36}, + {0x7098, 0xd3}, + {0x7099, 0x30}, + {0x709a, 0x04}, + {0x709b, 0xe0}, + {0x709c, 0xd8}, + {0x709d, 0xb4}, + {0x709e, 0xe9}, + {0x709f, 0x00}, + {0x70a0, 0xbe}, + {0x70a1, 0x05}, + {0x70a2, 0x62}, + {0x70a3, 0x07}, + {0x70a4, 0xb9}, + {0x70a5, 0x05}, + {0x70a6, 0xad}, + {0x70a7, 0xc3}, + {0x70a8, 0xcf}, + {0x70a9, 0x00}, + {0x70aa, 0x15}, + {0x70ab, 0xc2}, + {0x70ac, 0x59}, + {0x70ad, 0xc3}, + {0x70ae, 0xc9}, + {0x70af, 0xc0}, + {0x70b0, 0x55}, + {0x70b1, 0x00}, + {0x70b2, 0x46}, + {0x70b3, 0xa1}, + {0x70b4, 0xb9}, + {0x70b5, 0x64}, + {0x70b6, 0x29}, + {0x70b7, 0x00}, + {0x70b8, 0xb8}, + {0x70b9, 0x02}, + {0x70ba, 0xbe}, + {0x70bb, 0x02}, + {0x70bc, 0xd0}, + {0x70bd, 0xdc}, + {0x70be, 0xac}, + {0x70bf, 0xbc}, + {0x70c0, 0x01}, + {0x70c1, 0x37}, + {0x70c2, 0xac}, + {0x70c3, 0xd2}, + {0x70c4, 0x45}, + {0x70c5, 0xad}, + {0x70c6, 0x28}, + {0x70c7, 0x00}, + {0x70c8, 0xb8}, + {0x70c9, 0x00}, + {0x70ca, 0xbc}, + {0x70cb, 0x01}, + {0x70cc, 0x36}, + {0x70cd, 0x30}, + {0x70ce, 0xe0}, + {0x70cf, 0xd8}, + {0x70d0, 0xb5}, + {0x70d1, 0x0b}, + {0x70d2, 0xd6}, + {0x70d3, 0xbe}, + {0x70d4, 0x07}, + {0x70d5, 0x00}, + {0x70d6, 0x62}, + {0x70d7, 0x07}, + {0x70d8, 0xb9}, + {0x70d9, 0x05}, + {0x70da, 0xad}, + {0x70db, 0xc3}, + {0x70dc, 0xcf}, + {0x70dd, 0x46}, + {0x70de, 0xcd}, + {0x70df, 0x07}, + {0x70e0, 0xcd}, + {0x70e1, 0x00}, + {0x70e2, 0xe3}, + {0x70e3, 0x18}, + {0x70e4, 0xc2}, + {0x70e5, 0xa2}, + {0x70e6, 0xb9}, + {0x70e7, 0x64}, + {0x70e8, 0xd1}, + {0x70e9, 0xdd}, + {0x70ea, 0xac}, + {0x70eb, 0xcf}, + {0x70ec, 0xdf}, + {0x70ed, 0xb5}, + {0x70ee, 0x19}, + {0x70ef, 0x46}, + {0x70f0, 0x50}, + {0x70f1, 0xb6}, + {0x70f2, 0xee}, + {0x70f3, 0xe8}, + {0x70f4, 0xe6}, + {0x70f5, 0xbc}, + {0x70f6, 0x31}, + {0x70f7, 0xe1}, + {0x70f8, 0x36}, + {0x70f9, 0x30}, + {0x70fa, 0xd3}, + {0x70fb, 0x2e}, + {0x70fc, 0x54}, + {0x70fd, 0xbd}, + {0x70fe, 0x03}, + {0x70ff, 0xec}, + {0x7100, 0x2c}, + {0x7101, 0x50}, + {0x7102, 0x20}, + {0x7103, 0x04}, + {0x7104, 0xb8}, + {0x7105, 0x02}, + {0x7106, 0xbc}, + {0x7107, 0x18}, + {0x7108, 0xc7}, + {0x7109, 0xb8}, + {0x710a, 0x00}, + {0x710b, 0x28}, + {0x710c, 0x54}, + {0x710d, 0xbc}, + {0x710e, 0x02}, + {0x710f, 0xb4}, + {0x7110, 0xda}, + {0x7111, 0xbe}, + {0x7112, 0x04}, + {0x7113, 0xd6}, + {0x7114, 0xd8}, + {0x7115, 0xab}, + {0x7116, 0x00}, + {0x7117, 0x62}, + {0x7118, 0x07}, + {0x7119, 0xb9}, + {0x711a, 0x05}, + {0x711b, 0xad}, + {0x711c, 0xc3}, + {0x711d, 0xbc}, + {0x711e, 0xe7}, + {0x711f, 0xb9}, + {0x7120, 0x64}, + {0x7121, 0x29}, + {0x7122, 0x00}, + {0x7123, 0xb8}, + {0x7124, 0x02}, + {0x7125, 0xbe}, + {0x7126, 0x00}, + {0x7127, 0x45}, + {0x7128, 0xad}, + {0x7129, 0xe2}, + {0x712a, 0x28}, + {0x712b, 0x00}, + {0x712c, 0xb8}, + {0x712d, 0x00}, + {0x712e, 0xe0}, + {0x712f, 0xd8}, + {0x7130, 0xb4}, + {0x7131, 0xe9}, + {0x7132, 0xbe}, + {0x7133, 0x03}, + {0x7134, 0x00}, + {0x7135, 0x30}, + {0x7136, 0x62}, + {0x7137, 0x07}, + {0x7138, 0xb9}, + {0x7139, 0x05}, + {0x713a, 0xad}, + {0x713b, 0xc3}, + {0x713c, 0xcf}, + {0x713d, 0x42}, + {0x713e, 0xe4}, + {0x713f, 0xcd}, + {0x7140, 0x07}, + {0x7141, 0xcd}, + {0x7142, 0x00}, + {0x7143, 0x00}, + {0x7144, 0x17}, + {0x7145, 0xc2}, + {0x7146, 0xbb}, + {0x7147, 0xde}, + {0x7148, 0xcf}, + {0x7149, 0xdf}, + {0x714a, 0xac}, + {0x714b, 0xd1}, + {0x714c, 0x44}, + {0x714d, 0xac}, + {0x714e, 0xb9}, + {0x714f, 0x76}, + {0x7150, 0xb8}, + {0x7151, 0x08}, + {0x7152, 0xb6}, + {0x7153, 0xfe}, + {0x7154, 0xb4}, + {0x7155, 0xca}, + {0x7156, 0xd6}, + {0x7157, 0xd8}, + {0x7158, 0xab}, + {0x7159, 0x00}, + {0x715a, 0xe1}, + {0x715b, 0x36}, + {0x715c, 0x30}, + {0x715d, 0xd3}, + {0x715e, 0xbc}, + {0x715f, 0x29}, + {0x7160, 0xb4}, + {0x7161, 0x1f}, + {0x7162, 0xaa}, + {0x7163, 0xbd}, + {0x7164, 0x01}, + {0x7165, 0xb8}, + {0x7166, 0x0c}, + {0x7167, 0x45}, + {0x7168, 0xa4}, + {0x7169, 0xbd}, + {0x716a, 0x03}, + {0x716b, 0xec}, + {0x716c, 0xbc}, + {0x716d, 0x3d}, + {0x716e, 0xc3}, + {0x716f, 0xcf}, + {0x7170, 0x42}, + {0x7171, 0xb8}, + {0x7172, 0x00}, + {0x7173, 0xe4}, + {0x7174, 0xd5}, + {0x7175, 0x00}, + {0x7176, 0xb6}, + {0x7177, 0x00}, + {0x7178, 0x74}, + {0x7179, 0xbd}, + {0x717a, 0x03}, + {0x717b, 0xb5}, + {0x717c, 0x39}, + {0x717d, 0x40}, + {0x717e, 0x58}, + {0x717f, 0xdd}, + {0x7180, 0x19}, + {0x7181, 0xc1}, + {0x7182, 0xc8}, + {0x7183, 0xbd}, + {0x7184, 0x06}, + {0x7185, 0x17}, + {0x7186, 0xc1}, + {0x7187, 0xc6}, + {0x7188, 0xe8}, + {0x7189, 0x00}, + {0x718a, 0xc0}, + {0x718b, 0xc8}, + {0x718c, 0xe6}, + {0x718d, 0x95}, + {0x718e, 0x15}, + {0x718f, 0x00}, + {0x7190, 0xbc}, + {0x7191, 0x19}, + {0x7192, 0xb9}, + {0x7193, 0xf6}, + {0x7194, 0x14}, + {0x7195, 0xc1}, + {0x7196, 0xd0}, + {0x7197, 0xd1}, + {0x7198, 0xac}, + {0x7199, 0x37}, + {0x719a, 0xbc}, + {0x719b, 0x35}, + {0x719c, 0x36}, + {0x719d, 0x30}, + {0x719e, 0xe1}, + {0x719f, 0xd3}, + {0x71a0, 0x7a}, + {0x71a1, 0xb6}, + {0x71a2, 0x0c}, + {0x71a3, 0xff}, + {0x71a4, 0xb4}, + {0x71a5, 0xc7}, + {0x71a6, 0xd9}, + {0x71a7, 0x00}, + {0x71a8, 0xbd}, + {0x71a9, 0x01}, + {0x71aa, 0x56}, + {0x71ab, 0xc0}, + {0x71ac, 0xda}, + {0x71ad, 0xb4}, + {0x71ae, 0x1f}, + {0x71af, 0x56}, + {0x71b0, 0xaa}, + {0x71b1, 0xbc}, + {0x71b2, 0x08}, + {0x71b3, 0x00}, + {0x71b4, 0x57}, + {0x71b5, 0xe8}, + {0x71b6, 0xb5}, + {0x71b7, 0x36}, + {0x71b8, 0x00}, + {0x71b9, 0x54}, + {0x71ba, 0xe7}, + {0x71bb, 0xc8}, + {0x71bc, 0xb4}, + {0x71bd, 0x1f}, + {0x71be, 0x56}, + {0x71bf, 0xaa}, + {0x71c0, 0xbc}, + {0x71c1, 0x08}, + {0x71c2, 0x57}, + {0x71c3, 0x00}, + {0x71c4, 0xb5}, + {0x71c5, 0x36}, + {0x71c6, 0x00}, + {0x71c7, 0x54}, + {0x71c8, 0xc8}, + {0x71c9, 0xb5}, + {0x71ca, 0x18}, + {0x71cb, 0xd9}, + {0x71cc, 0x00}, + {0x71cd, 0xbd}, + {0x71ce, 0x01}, + {0x71cf, 0x56}, + {0x71d0, 0x08}, + {0x71d1, 0x57}, + {0x71d2, 0xe8}, + {0x71d3, 0xb4}, + {0x71d4, 0x42}, + {0x71d5, 0x00}, + {0x71d6, 0x54}, + {0x71d7, 0xe7}, + {0x71d8, 0xc8}, + {0x71d9, 0xab}, + {0x71da, 0x00}, + {0x71db, 0x66}, + {0x71dc, 0x62}, + {0x71dd, 0x06}, + {0x71de, 0x74}, + {0x71df, 0xb9}, + {0x71e0, 0x05}, + {0x71e1, 0xb7}, + {0x71e2, 0x14}, + {0x71e3, 0x0e}, + {0x71e4, 0xb7}, + {0x71e5, 0x04}, + {0x71e6, 0xc8}, + {0x7600, 0x04}, + {0x7601, 0x80}, + {0x7602, 0x07}, + {0x7603, 0x44}, + {0x7604, 0x05}, + {0x7605, 0x33}, + {0x7606, 0x0f}, + {0x7607, 0x00}, + {0x7608, 0x07}, + {0x7609, 0x40}, + {0x760a, 0x04}, + {0x760b, 0xe5}, + {0x760c, 0x06}, + {0x760d, 0x50}, + {0x760e, 0x04}, + {0x760f, 0xe4}, + {0x7610, 0x00}, + {0x7611, 0x00}, + {0x7612, 0x06}, + {0x7613, 0x5c}, + {0x7614, 0x00}, + {0x7615, 0x0f}, + {0x7616, 0x06}, + {0x7617, 0x1c}, + {0x7618, 0x00}, + {0x7619, 0x02}, + {0x761a, 0x06}, + {0x761b, 0xa2}, + {0x761c, 0x00}, + {0x761d, 0x01}, + {0x761e, 0x06}, + {0x761f, 0xae}, + {0x7620, 0x00}, + {0x7621, 0x0e}, + {0x7622, 0x05}, + {0x7623, 0x30}, + {0x7624, 0x07}, + {0x7625, 0x00}, + {0x7626, 0x0f}, + {0x7627, 0x00}, + {0x7628, 0x04}, + {0x7629, 0xe5}, + {0x762a, 0x05}, + {0x762b, 0x33}, + {0x762c, 0x06}, + {0x762d, 0x12}, + {0x762e, 0x00}, + {0x762f, 0x01}, + {0x7630, 0x06}, + {0x7631, 0x52}, + {0x7632, 0x00}, + {0x7633, 0x01}, + {0x7634, 0x06}, + {0x7635, 0x5e}, + {0x7636, 0x04}, + {0x7637, 0xe4}, + {0x7638, 0x00}, + {0x7639, 0x01}, + {0x763a, 0x05}, + {0x763b, 0x30}, + {0x763c, 0x0f}, + {0x763d, 0x00}, + {0x763e, 0x06}, + {0x763f, 0xa6}, + {0x7640, 0x00}, + {0x7641, 0x02}, + {0x7642, 0x06}, + {0x7643, 0x26}, + {0x7644, 0x00}, + {0x7645, 0x02}, + {0x7646, 0x05}, + {0x7647, 0x33}, + {0x7648, 0x06}, + {0x7649, 0x20}, + {0x764a, 0x0f}, + {0x764b, 0x00}, + {0x764c, 0x06}, + {0x764d, 0x56}, + {0x764e, 0x00}, + {0x764f, 0x02}, + {0x7650, 0x06}, + {0x7651, 0x16}, + {0x7652, 0x05}, + {0x7653, 0x33}, + {0x7654, 0x06}, + {0x7655, 0x10}, + {0x7656, 0x0f}, + {0x7657, 0x00}, + {0x7658, 0x06}, + {0x7659, 0x10}, + {0x765a, 0x0f}, + {0x765b, 0x00}, + {0x765c, 0x06}, + {0x765d, 0x20}, + {0x765e, 0x0f}, + {0x765f, 0x00}, + {0x7660, 0x00}, + {0x7661, 0x00}, + {0x7662, 0x00}, + {0x7663, 0x02}, + {0x7664, 0x04}, + {0x7665, 0xe5}, + {0x7666, 0x04}, + {0x7667, 0xe4}, + {0x7668, 0x0f}, + {0x7669, 0x00}, + {0x766a, 0x00}, + {0x766b, 0x00}, + {0x766c, 0x00}, + {0x766d, 0x01}, + {0x766e, 0x04}, + {0x766f, 0xe5}, + {0x7670, 0x04}, + {0x7671, 0xe4}, + {0x7672, 0x0f}, + {0x7673, 0x00}, + {0x7674, 0x00}, + {0x7675, 0x02}, + {0x7676, 0x04}, + {0x7677, 0xe4}, + {0x7678, 0x00}, + {0x7679, 0x02}, + {0x767a, 0x04}, + {0x767b, 0xc4}, + {0x767c, 0x00}, + {0x767d, 0x02}, + {0x767e, 0x04}, + {0x767f, 0xc4}, + {0x7680, 0x05}, + {0x7681, 0x83}, + {0x7682, 0x0f}, + {0x7683, 0x00}, + {0x7684, 0x00}, + {0x7685, 0x02}, + {0x7686, 0x04}, + {0x7687, 0xe4}, + {0x7688, 0x00}, + {0x7689, 0x02}, + {0x768a, 0x04}, + {0x768b, 0xc4}, + {0x768c, 0x00}, + {0x768d, 0x02}, + {0x768e, 0x04}, + {0x768f, 0xc4}, + {0x7690, 0x05}, + {0x7691, 0x83}, + {0x7692, 0x03}, + {0x7693, 0x0b}, + {0x7694, 0x05}, + {0x7695, 0x83}, + {0x7696, 0x00}, + {0x7697, 0x07}, + {0x7698, 0x05}, + {0x7699, 0x03}, + {0x769a, 0x00}, + {0x769b, 0x05}, + {0x769c, 0x05}, + {0x769d, 0x32}, + {0x769e, 0x05}, + {0x769f, 0x30}, + {0x76a0, 0x00}, + {0x76a1, 0x02}, + {0x76a2, 0x05}, + {0x76a3, 0x78}, + {0x76a4, 0x00}, + {0x76a5, 0x01}, + {0x76a6, 0x05}, + {0x76a7, 0x7c}, + {0x76a8, 0x03}, + {0x76a9, 0x9a}, + {0x76aa, 0x05}, + {0x76ab, 0x83}, + {0x76ac, 0x00}, + {0x76ad, 0x04}, + {0x76ae, 0x05}, + {0x76af, 0x03}, + {0x76b0, 0x00}, + {0x76b1, 0x03}, + {0x76b2, 0x05}, + {0x76b3, 0x32}, + {0x76b4, 0x05}, + {0x76b5, 0x30}, + {0x76b6, 0x00}, + {0x76b7, 0x02}, + {0x76b8, 0x05}, + {0x76b9, 0x78}, + {0x76ba, 0x00}, + {0x76bb, 0x01}, + {0x76bc, 0x05}, + {0x76bd, 0x7c}, + {0x76be, 0x03}, + {0x76bf, 0x99}, + {0x76c0, 0x05}, + {0x76c1, 0x83}, + {0x76c2, 0x00}, + {0x76c3, 0x03}, + {0x76c4, 0x05}, + {0x76c5, 0x03}, + {0x76c6, 0x00}, + {0x76c7, 0x01}, + {0x76c8, 0x05}, + {0x76c9, 0x32}, + {0x76ca, 0x05}, + {0x76cb, 0x30}, + {0x76cc, 0x00}, + {0x76cd, 0x02}, + {0x76ce, 0x05}, + {0x76cf, 0x78}, + {0x76d0, 0x00}, + {0x76d1, 0x01}, + {0x76d2, 0x05}, + {0x76d3, 0x7c}, + {0x76d4, 0x03}, + {0x76d5, 0x98}, + {0x76d6, 0x05}, + {0x76d7, 0x83}, + {0x76d8, 0x00}, + {0x76d9, 0x00}, + {0x76da, 0x05}, + {0x76db, 0x03}, + {0x76dc, 0x00}, + {0x76dd, 0x01}, + {0x76de, 0x05}, + {0x76df, 0x32}, + {0x76e0, 0x05}, + {0x76e1, 0x30}, + {0x76e2, 0x00}, + {0x76e3, 0x02}, + {0x76e4, 0x05}, + {0x76e5, 0x78}, + {0x76e6, 0x00}, + {0x76e7, 0x01}, + {0x76e8, 0x05}, + {0x76e9, 0x7c}, + {0x76ea, 0x03}, + {0x76eb, 0x97}, + {0x76ec, 0x05}, + {0x76ed, 0x83}, + {0x76ee, 0x00}, + {0x76ef, 0x00}, + {0x76f0, 0x05}, + {0x76f1, 0x03}, + {0x76f2, 0x05}, + {0x76f3, 0x32}, + {0x76f4, 0x05}, + {0x76f5, 0x30}, + {0x76f6, 0x00}, + {0x76f7, 0x02}, + {0x76f8, 0x05}, + {0x76f9, 0x78}, + {0x76fa, 0x00}, + {0x76fb, 0x01}, + {0x76fc, 0x05}, + {0x76fd, 0x7c}, + {0x76fe, 0x03}, + {0x76ff, 0x96}, + {0x7700, 0x05}, + {0x7701, 0x83}, + {0x7702, 0x05}, + {0x7703, 0x03}, + {0x7704, 0x05}, + {0x7705, 0x32}, + {0x7706, 0x05}, + {0x7707, 0x30}, + {0x7708, 0x00}, + {0x7709, 0x02}, + {0x770a, 0x05}, + {0x770b, 0x78}, + {0x770c, 0x00}, + {0x770d, 0x01}, + {0x770e, 0x05}, + {0x770f, 0x7c}, + {0x7710, 0x03}, + {0x7711, 0x95}, + {0x7712, 0x05}, + {0x7713, 0x83}, + {0x7714, 0x05}, + {0x7715, 0x03}, + {0x7716, 0x05}, + {0x7717, 0x32}, + {0x7718, 0x05}, + {0x7719, 0x30}, + {0x771a, 0x00}, + {0x771b, 0x02}, + {0x771c, 0x05}, + {0x771d, 0x78}, + {0x771e, 0x00}, + {0x771f, 0x01}, + {0x7720, 0x05}, + {0x7721, 0x7c}, + {0x7722, 0x03}, + {0x7723, 0x94}, + {0x7724, 0x05}, + {0x7725, 0x83}, + {0x7726, 0x00}, + {0x7727, 0x01}, + {0x7728, 0x05}, + {0x7729, 0x03}, + {0x772a, 0x00}, + {0x772b, 0x01}, + {0x772c, 0x05}, + {0x772d, 0x32}, + {0x772e, 0x05}, + {0x772f, 0x30}, + {0x7730, 0x00}, + {0x7731, 0x02}, + {0x7732, 0x05}, + {0x7733, 0x78}, + {0x7734, 0x00}, + {0x7735, 0x01}, + {0x7736, 0x05}, + {0x7737, 0x7c}, + {0x7738, 0x03}, + {0x7739, 0x93}, + {0x773a, 0x05}, + {0x773b, 0x83}, + {0x773c, 0x00}, + {0x773d, 0x00}, + {0x773e, 0x05}, + {0x773f, 0x03}, + {0x7740, 0x00}, + {0x7741, 0x00}, + {0x7742, 0x05}, + {0x7743, 0x32}, + {0x7744, 0x05}, + {0x7745, 0x30}, + {0x7746, 0x00}, + {0x7747, 0x02}, + {0x7748, 0x05}, + {0x7749, 0x78}, + {0x774a, 0x00}, + {0x774b, 0x01}, + {0x774c, 0x05}, + {0x774d, 0x7c}, + {0x774e, 0x03}, + {0x774f, 0x92}, + {0x7750, 0x05}, + {0x7751, 0x83}, + {0x7752, 0x05}, + {0x7753, 0x03}, + {0x7754, 0x00}, + {0x7755, 0x00}, + {0x7756, 0x05}, + {0x7757, 0x32}, + {0x7758, 0x05}, + {0x7759, 0x30}, + {0x775a, 0x00}, + {0x775b, 0x02}, + {0x775c, 0x05}, + {0x775d, 0x78}, + {0x775e, 0x00}, + {0x775f, 0x01}, + {0x7760, 0x05}, + {0x7761, 0x7c}, + {0x7762, 0x03}, + {0x7763, 0x91}, + {0x7764, 0x05}, + {0x7765, 0x83}, + {0x7766, 0x05}, + {0x7767, 0x03}, + {0x7768, 0x05}, + {0x7769, 0x32}, + {0x776a, 0x05}, + {0x776b, 0x30}, + {0x776c, 0x00}, + {0x776d, 0x02}, + {0x776e, 0x05}, + {0x776f, 0x78}, + {0x7770, 0x00}, + {0x7771, 0x01}, + {0x7772, 0x05}, + {0x7773, 0x7c}, + {0x7774, 0x03}, + {0x7775, 0x90}, + {0x7776, 0x05}, + {0x7777, 0x83}, + {0x7778, 0x05}, + {0x7779, 0x03}, + {0x777a, 0x05}, + {0x777b, 0x32}, + {0x777c, 0x05}, + {0x777d, 0x30}, + {0x777e, 0x00}, + {0x777f, 0x02}, + {0x7780, 0x05}, + {0x7781, 0x78}, + {0x7782, 0x00}, + {0x7783, 0x01}, + {0x7784, 0x05}, + {0x7785, 0x7c}, + {0x7786, 0x02}, + {0x7787, 0x90}, + {0x7788, 0x05}, + {0x7789, 0x03}, + {0x778a, 0x07}, + {0x778b, 0x00}, + {0x778c, 0x0f}, + {0x778d, 0x00}, + {0x778e, 0x08}, + {0x778f, 0x30}, + {0x7790, 0x08}, + {0x7791, 0xee}, + {0x7792, 0x0f}, + {0x7793, 0x00}, + {0x7794, 0x05}, + {0x7795, 0x33}, + {0x7796, 0x04}, + {0x7797, 0xe5}, + {0x7798, 0x06}, + {0x7799, 0x52}, + {0x779a, 0x04}, + {0x779b, 0xe4}, + {0x779c, 0x00}, + {0x779d, 0x00}, + {0x779e, 0x06}, + {0x779f, 0x5e}, + {0x77a0, 0x00}, + {0x77a1, 0x0f}, + {0x77a2, 0x06}, + {0x77a3, 0x1e}, + {0x77a4, 0x00}, + {0x77a5, 0x02}, + {0x77a6, 0x06}, + {0x77a7, 0xa2}, + {0x77a8, 0x00}, + {0x77a9, 0x01}, + {0x77aa, 0x06}, + {0x77ab, 0xae}, + {0x77ac, 0x00}, + {0x77ad, 0x03}, + {0x77ae, 0x05}, + {0x77af, 0x30}, + {0x77b0, 0x09}, + {0x77b1, 0x19}, + {0x77b2, 0x0f}, + {0x77b3, 0x00}, + {0x77b4, 0x05}, + {0x77b5, 0x33}, + {0x77b6, 0x04}, + {0x77b7, 0xe5}, + {0x77b8, 0x06}, + {0x77b9, 0x52}, + {0x77ba, 0x04}, + {0x77bb, 0xe4}, + {0x77bc, 0x00}, + {0x77bd, 0x00}, + {0x77be, 0x06}, + {0x77bf, 0x5e}, + {0x77c0, 0x00}, + {0x77c1, 0x0f}, + {0x77c2, 0x06}, + {0x77c3, 0x1e}, + {0x77c4, 0x00}, + {0x77c5, 0x02}, + {0x77c6, 0x06}, + {0x77c7, 0xa2}, + {0x77c8, 0x00}, + {0x77c9, 0x01}, + {0x77ca, 0x06}, + {0x77cb, 0xae}, + {0x77cc, 0x00}, + {0x77cd, 0x03}, + {0x77ce, 0x05}, + {0x77cf, 0x30}, + {0x77d0, 0x0f}, + {0x77d1, 0x00}, + {0x77d2, 0x00}, + {0x77d3, 0x00}, + {0x77d4, 0x00}, + {0x77d5, 0x02}, + {0x77d6, 0x04}, + {0x77d7, 0xe5}, + {0x77d8, 0x04}, + {0x77d9, 0xe4}, + {0x77da, 0x05}, + {0x77db, 0x33}, + {0x77dc, 0x07}, + {0x77dd, 0x10}, + {0x77de, 0x00}, + {0x77df, 0x00}, + {0x77e0, 0x01}, + {0x77e1, 0xbb}, + {0x77e2, 0x00}, + {0x77e3, 0x00}, + {0x77e4, 0x01}, + {0x77e5, 0xaa}, + {0x77e6, 0x00}, + {0x77e7, 0x00}, + {0x77e8, 0x01}, + {0x77e9, 0x99}, + {0x77ea, 0x00}, + {0x77eb, 0x00}, + {0x77ec, 0x01}, + {0x77ed, 0x88}, + {0x77ee, 0x00}, + {0x77ef, 0x00}, + {0x77f0, 0x01}, + {0x77f1, 0x77}, + {0x77f2, 0x00}, + {0x77f3, 0x00}, + {0x77f4, 0x01}, + {0x77f5, 0x66}, + {0x77f6, 0x00}, + {0x77f7, 0x00}, + {0x77f8, 0x01}, + {0x77f9, 0x55}, + {0x77fa, 0x00}, + {0x77fb, 0x00}, + {0x77fc, 0x01}, + {0x77fd, 0x44}, + {0x77fe, 0x00}, + {0x77ff, 0x00}, + {0x7800, 0x01}, + {0x7801, 0x33}, + {0x7802, 0x00}, + {0x7803, 0x00}, + {0x7804, 0x01}, + {0x7805, 0x22}, + {0x7806, 0x00}, + {0x7807, 0x00}, + {0x7808, 0x01}, + {0x7809, 0x11}, + {0x780a, 0x00}, + {0x780b, 0x00}, + {0x780c, 0x01}, + {0x780d, 0x00}, + {0x780e, 0x01}, + {0x780f, 0xff}, + {0x7810, 0x07}, + {0x7811, 0x00}, + {0x7812, 0x02}, + {0x7813, 0xa0}, + {0x7814, 0x0f}, + {0x7815, 0x00}, + {0x7816, 0x08}, + {0x7817, 0x35}, + {0x7818, 0x06}, + {0x7819, 0x52}, + {0x781a, 0x04}, + {0x781b, 0xe4}, + {0x781c, 0x00}, + {0x781d, 0x00}, + {0x781e, 0x06}, + {0x781f, 0x5e}, + {0x7820, 0x05}, + {0x7821, 0x33}, + {0x7822, 0x09}, + {0x7823, 0x19}, + {0x7824, 0x06}, + {0x7825, 0x1e}, + {0x7826, 0x05}, + {0x7827, 0x33}, + {0x7828, 0x00}, + {0x7829, 0x01}, + {0x782a, 0x06}, + {0x782b, 0x24}, + {0x782c, 0x06}, + {0x782d, 0x20}, + {0x782e, 0x0f}, + {0x782f, 0x00}, + {0x7830, 0x08}, + {0x7831, 0x35}, + {0x7832, 0x07}, + {0x7833, 0x10}, + {0x7834, 0x00}, + {0x7835, 0x00}, + {0x7836, 0x01}, + {0x7837, 0xbb}, + {0x7838, 0x00}, + {0x7839, 0x00}, + {0x783a, 0x01}, + {0x783b, 0xaa}, + {0x783c, 0x00}, + {0x783d, 0x00}, + {0x783e, 0x01}, + {0x783f, 0x99}, + {0x7840, 0x00}, + {0x7841, 0x00}, + {0x7842, 0x01}, + {0x7843, 0x88}, + {0x7844, 0x00}, + {0x7845, 0x00}, + {0x7846, 0x01}, + {0x7847, 0x77}, + {0x7848, 0x00}, + {0x7849, 0x00}, + {0x784a, 0x01}, + {0x784b, 0x66}, + {0x784c, 0x00}, + {0x784d, 0x00}, + {0x784e, 0x01}, + {0x784f, 0x55}, + {0x7850, 0x00}, + {0x7851, 0x00}, + {0x7852, 0x01}, + {0x7853, 0x44}, + {0x7854, 0x00}, + {0x7855, 0x00}, + {0x7856, 0x01}, + {0x7857, 0x33}, + {0x7858, 0x00}, + {0x7859, 0x00}, + {0x785a, 0x01}, + {0x785b, 0x22}, + {0x785c, 0x00}, + {0x785d, 0x00}, + {0x785e, 0x01}, + {0x785f, 0x11}, + {0x7860, 0x00}, + {0x7861, 0x00}, + {0x7862, 0x01}, + {0x7863, 0x00}, + {0x7864, 0x07}, + {0x7865, 0x00}, + {0x7866, 0x01}, + {0x7867, 0xff}, + {0x7868, 0x02}, + {0x7869, 0xa0}, + {0x786a, 0x0f}, + {0x786b, 0x00}, + {0x786c, 0x08}, + {0x786d, 0x3a}, + {0x786e, 0x08}, + {0x786f, 0x6a}, + {0x7870, 0x0f}, + {0x7871, 0x00}, + {0x7872, 0x04}, + {0x7873, 0xc0}, + {0x7874, 0x09}, + {0x7875, 0x19}, + {0x7876, 0x04}, + {0x7877, 0x99}, + {0x7878, 0x07}, + {0x7879, 0x14}, + {0x787a, 0x00}, + {0x787b, 0x01}, + {0x787c, 0x04}, + {0x787d, 0xa4}, + {0x787e, 0x00}, + {0x787f, 0x07}, + {0x7880, 0x04}, + {0x7881, 0xa6}, + {0x7882, 0x00}, + {0x7883, 0x00}, + {0x7884, 0x04}, + {0x7885, 0xa0}, + {0x7886, 0x04}, + {0x7887, 0x80}, + {0x7888, 0x04}, + {0x7889, 0x00}, + {0x788a, 0x05}, + {0x788b, 0x03}, + {0x788c, 0x06}, + {0x788d, 0x00}, + {0x788e, 0x0f}, + {0x788f, 0x00}, + {0x7890, 0x0f}, + {0x7891, 0x00}, + {0x7892, 0x0f}, + {0x7893, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x05}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x88}, + {0x30ae, 0x04}, + {0x30af, 0x40}, + {0x30b0, 0x0d}, + {0x30b1, 0xde}, + {0x30b2, 0x04}, + {0x30b3, 0x66}, + {0x30b6, 0x01}, + {0x30b7, 0x15}, + {0x3196, 0x00}, + {0x3197, 0x0a}, + {0x3195, 0x29}, + {0x315a, 0x02}, + {0x315b, 0x00}, + {0x30bb, 0x40}, + {0x3250, 0xf7}, + {0x30a8, 0x00}, + {0x30a9, 0x04}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x80}, + {0x30ae, 0x04}, + {0x30af, 0x38}, + {0x3012, 0x01}, +}; + +struct vvcam_sccb_array ov5693_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(ov5693_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = ov5693_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam/native/sensor/omnivision_ov5693/ov5693_reg_cfg.h b/vvcam/native/sensor/omnivision_ov5693/ov5693_reg_cfg.h new file mode 100755 index 0000000..243d8fb --- /dev/null +++ b/vvcam/native/sensor/omnivision_ov5693/ov5693_reg_cfg.h @@ -0,0 +1,6 @@ +#ifndef _OV5693_REG_CFG_H_ +#define _OV5693_REG_CFG_H_ + +extern struct vvcam_sccb_array ov5693_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam/native/sensor/ox03a10/ox03a10_driver.c b/vvcam/native/sensor/ox03a10/ox03a10_driver.c new file mode 100755 index 0000000..6ae1373 --- /dev/null +++ b/vvcam/native/sensor/ox03a10/ox03a10_driver.c @@ -0,0 +1,493 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "ox03a10_reg_cfg.h" + +#define SENSOR_CLK 51000000 + +static struct vvcam_mode_info pox03a10_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_array *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pox03a10_mode_info); + + memcpy(pmode_info_arry->modes,pox03a10_mode_info,sizeof(pox03a10_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pox03a10_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pox03a10_mode_info[i].index == pmode->index) + { + psensor_mode = &(pox03a10_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&ox03a10_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&ox03a10_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3012, 0x01); + }else + { + ret = sensor_write_reg(ctx, 0x3012, 0x00); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s ox03a10_function = +{ + .sensor_name = "ox03a10", + .reserve_id = 0x5803, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam/native/sensor/ox03a10/ox03a10_driver.h b/vvcam/native/sensor/ox03a10/ox03a10_driver.h new file mode 100755 index 0000000..c908b6b --- /dev/null +++ b/vvcam/native/sensor/ox03a10/ox03a10_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OMNIVISION_OX03a10_H_ +#define _OMNIVISION_OX03a10_H_ + +extern struct vvcam_sensor_function_s ox03a10_function; + + +#endif diff --git a/vvcam/native/sensor/ox03a10/ox03a10_mipi4lane_1080p_30fps_linear.c b/vvcam/native/sensor/ox03a10/ox03a10_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..364ed5c --- /dev/null +++ b/vvcam/native/sensor/ox03a10/ox03a10_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,1880 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data ox03a10_mipi4lane_1080p_30fps_linear_reg[] = { + {0x3000, 0x02}, + {0x3001, 0x28}, + {0x3002, 0x03}, + {0x3003, 0x01}, + {0x3004, 0x05}, + {0x3005, 0x26}, + {0x3006, 0x00}, + {0x3007, 0x07}, + {0x3008, 0x01}, + {0x3009, 0x00}, + {0x300c, 0x6c}, + {0x300e, 0x80}, + {0x300f, 0x00}, + {0x3012, 0x00}, + {0x3013, 0x00}, + {0x3014, 0xc4}, + {0x3015, 0x00}, + {0x3017, 0x00}, + {0x3018, 0x00}, + {0x3019, 0x00}, + {0x301a, 0x00}, + {0x301b, 0x0e}, + {0x301e, 0x17}, + {0x301f, 0xe1}, + {0x3030, 0x02}, + {0x3031, 0x62}, + {0x3032, 0xf0}, + {0x3033, 0x30}, + {0x3034, 0x3f}, + {0x3035, 0x5f}, + {0x3036, 0x02}, + {0x3037, 0x9f}, + {0x3038, 0x04}, + {0x3039, 0xb7}, + {0x303a, 0x04}, + {0x303b, 0x07}, + {0x303c, 0xf0}, + {0x303d, 0x00}, + {0x303e, 0x0b}, + {0x303f, 0xe3}, + {0x3040, 0xf3}, + {0x3041, 0x29}, + {0x3042, 0xf6}, + {0x3043, 0x65}, + {0x3044, 0x06}, + {0x3045, 0x0f}, + {0x3046, 0x59}, + {0x3047, 0x07}, + {0x3048, 0x82}, + {0x3049, 0xcf}, + {0x304a, 0x12}, + {0x304b, 0x40}, + {0x304c, 0x33}, + {0x304d, 0xa4}, + {0x304e, 0x0b}, + {0x304f, 0x3d}, + {0x3050, 0x10}, + {0x3060, 0x00}, + {0x3061, 0x64}, + {0x3062, 0x00}, + {0x3063, 0xe4}, + {0x3066, 0x80}, + {0x3080, 0x00}, + {0x3081, 0x00}, + {0x3082, 0x01}, + {0x3083, 0xe3}, + {0x3084, 0x06}, + {0x3085, 0x00}, + {0x3086, 0x10}, + {0x3087, 0x10}, + {0x3089, 0x00}, + {0x308a, 0x01}, + {0x3093, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x00}, + {0x30aa, 0x00}, + {0x30ab, 0x00}, + {0x30ac, 0x07}, + {0x30ad, 0x90}, + {0x30ae, 0x04}, + {0x30af, 0x48}, + {0x30b0, 0x04}, + {0x30b1, 0x7e}, + {0x30b2, 0x04}, + {0x30b3, 0x65}, + {0x30b4, 0x00}, + {0x30b5, 0x00}, + {0x30b6, 0x00}, + {0x30b7, 0x10}, + {0x30b8, 0x00}, + {0x30b9, 0x02}, + {0x30ba, 0x10}, + {0x30bb, 0x00}, + {0x30bc, 0x00}, + {0x30bd, 0x03}, + {0x30be, 0x5c}, + {0x30bf, 0x00}, + {0x30c0, 0x05}, + {0x30c1, 0x00}, + {0x30c2, 0x20}, + {0x30c3, 0x00}, + {0x30c4, 0x4a}, + {0x30c5, 0x00}, + {0x30c7, 0x00}, + {0x30c8, 0x00}, + {0x30d1, 0x00}, + {0x30d2, 0x00}, + {0x30d3, 0x80}, + {0x30d4, 0x00}, + {0x30d9, 0x09}, + {0x30da, 0x64}, + {0x30dd, 0x00}, + {0x30de, 0x16}, + {0x30df, 0x00}, + {0x30e0, 0x17}, + {0x30e1, 0x00}, + {0x30e2, 0x18}, + {0x30e3, 0x10}, + {0x30e4, 0x04}, + {0x30e5, 0x00}, + {0x30e6, 0x00}, + {0x30e7, 0x00}, + {0x30e8, 0x00}, + {0x30e9, 0x00}, + {0x30ea, 0x00}, + {0x30eb, 0x00}, + {0x30ec, 0x00}, + {0x30ed, 0x00}, + {0x3101, 0x00}, + {0x3102, 0x00}, + {0x3103, 0x00}, + {0x3104, 0x00}, + {0x3105, 0x8c}, + {0x3106, 0x87}, + {0x3107, 0xc0}, + {0x3108, 0x9d}, + {0x3109, 0x8d}, + {0x310a, 0x8d}, + {0x310b, 0x6a}, + {0x310c, 0x3a}, + {0x310d, 0x5a}, + {0x310e, 0x00}, + {0x3120, 0x00}, + {0x3121, 0x00}, + {0x3122, 0x00}, + {0x3123, 0xf0}, + {0x3124, 0x00}, + {0x3125, 0x70}, + {0x3126, 0x1f}, + {0x3127, 0x0f}, + {0x3128, 0x00}, + {0x3129, 0x3a}, + {0x312a, 0x02}, + {0x312b, 0x0f}, + {0x312c, 0x00}, + {0x312d, 0x0f}, + {0x312e, 0x1d}, + {0x312f, 0x00}, + {0x3130, 0x00}, + {0x3131, 0x00}, + {0x3132, 0x00}, + {0x3140, 0x0a}, + {0x3141, 0x03}, + {0x3142, 0x00}, + {0x3143, 0x00}, + {0x3144, 0x00}, + {0x3145, 0x00}, + {0x3146, 0x00}, + {0x3147, 0x00}, + {0x3148, 0x00}, + {0x3149, 0x00}, + {0x314a, 0x00}, + {0x314b, 0x00}, + {0x314c, 0x00}, + {0x314d, 0x00}, + {0x314e, 0x1c}, + {0x314f, 0xff}, + {0x3150, 0xff}, + {0x3151, 0xff}, + {0x3152, 0x10}, + {0x3153, 0x10}, + {0x3154, 0x10}, + {0x3155, 0x00}, + {0x3156, 0x03}, + {0x3157, 0x00}, + {0x3158, 0x0f}, + {0x3159, 0xff}, + {0x315a, 0x01}, + {0x315b, 0x00}, + {0x315c, 0x01}, + {0x315d, 0x00}, + {0x315e, 0x01}, + {0x315f, 0x00}, + {0x3160, 0x00}, + {0x3161, 0x40}, + {0x3162, 0x00}, + {0x3163, 0x40}, + {0x3164, 0x00}, + {0x3165, 0x40}, + {0x3190, 0x08}, + {0x3191, 0x99}, + {0x3193, 0x08}, + {0x3194, 0x13}, + {0x3195, 0x33}, + {0x3196, 0x00}, + {0x3197, 0x10}, + {0x3198, 0x00}, + {0x3199, 0x7f}, + {0x319a, 0x80}, + {0x319b, 0xff}, + {0x319c, 0x80}, + {0x319d, 0xbf}, + {0x319e, 0xc0}, + {0x319f, 0xff}, + {0x31a0, 0x24}, + {0x31a1, 0x55}, + {0x31a2, 0x00}, + {0x31a3, 0x00}, + {0x31a6, 0x00}, + {0x31a7, 0x00}, + {0x31b0, 0x00}, + {0x31b1, 0x00}, + {0x31b2, 0x02}, + {0x31b3, 0x00}, + {0x31b4, 0x00}, + {0x31b5, 0x01}, + {0x31b6, 0x00}, + {0x31b7, 0x00}, + {0x31b8, 0x00}, + {0x31b9, 0x00}, + {0x31ba, 0x00}, + {0x31d0, 0x3c}, + {0x31d1, 0x34}, + {0x31d2, 0x3c}, + {0x31d3, 0x00}, + {0x31d4, 0x2d}, + {0x31d5, 0x00}, + {0x31d6, 0x01}, + {0x31d7, 0x06}, + {0x31d8, 0x00}, + {0x31d9, 0x64}, + {0x31da, 0x00}, + {0x31db, 0x30}, + {0x31dc, 0x04}, + {0x31dd, 0x69}, + {0x31de, 0x0a}, + {0x31df, 0x3c}, + {0x31e0, 0x04}, + {0x31e1, 0x32}, + {0x31e2, 0x00}, + {0x31e3, 0x00}, + {0x31e4, 0x08}, + {0x31e5, 0x80}, + {0x31e6, 0x00}, + {0x31e7, 0x2c}, + {0x31e8, 0x6c}, + {0x31e9, 0xac}, + {0x31ea, 0xec}, + {0x31eb, 0x3f}, + {0x31ec, 0x0f}, + {0x31ed, 0x20}, + {0x31ee, 0x04}, + {0x31ef, 0x48}, + {0x31f0, 0x07}, + {0x31f1, 0x90}, + {0x31f2, 0x04}, + {0x31f3, 0x48}, + {0x31f4, 0x07}, + {0x31f5, 0x90}, + {0x31f6, 0x04}, + {0x31f7, 0x48}, + {0x31f8, 0x07}, + {0x31f9, 0x90}, + {0x31fa, 0x04}, + {0x31fb, 0x48}, + {0x31fd, 0xcb}, + {0x31fe, 0x0f}, + {0x31ff, 0x03}, + {0x3200, 0x00}, + {0x3201, 0xff}, + {0x3202, 0x00}, + {0x3203, 0xff}, + {0x3204, 0xff}, + {0x3205, 0xff}, + {0x3206, 0xff}, + {0x3207, 0xff}, + {0x3208, 0xff}, + {0x3209, 0xff}, + {0x320a, 0xff}, + {0x320b, 0x1b}, + {0x320c, 0x1f}, + {0x320d, 0x1e}, + {0x320e, 0x30}, + {0x320f, 0x2d}, + {0x3210, 0x2c}, + {0x3211, 0x2b}, + {0x3212, 0x2a}, + {0x3213, 0x24}, + {0x3214, 0x22}, + {0x3215, 0x00}, + {0x3216, 0x04}, + {0x3217, 0x2c}, + {0x3218, 0x6c}, + {0x3219, 0xac}, + {0x321a, 0xec}, + {0x321b, 0x00}, + {0x3230, 0x3a}, + {0x3231, 0x00}, + {0x3232, 0x80}, + {0x3233, 0x00}, + {0x3234, 0x10}, + {0x3235, 0xaa}, + {0x3236, 0x55}, + {0x3237, 0x99}, + {0x3238, 0x66}, + {0x3239, 0x08}, + {0x323a, 0x88}, + {0x323b, 0x00}, + {0x323c, 0x00}, + {0x323d, 0x03}, + {0x3250, 0x33}, + {0x3251, 0x00}, + {0x3252, 0x20}, + {0x3253, 0x00}, + {0x3254, 0x00}, + {0x3255, 0x01}, + {0x3256, 0x00}, + {0x3257, 0x00}, + {0x3258, 0x00}, + {0x3270, 0x01}, + {0x3271, 0x60}, + {0x3272, 0xc0}, + {0x3273, 0x00}, + {0x3274, 0x80}, + {0x3275, 0x40}, + {0x3276, 0x02}, + {0x3277, 0x08}, + {0x3278, 0x10}, + {0x3279, 0x04}, + {0x327a, 0x00}, + {0x327b, 0x03}, + {0x327c, 0x10}, + {0x327d, 0x60}, + {0x327e, 0xc0}, + {0x327f, 0x06}, + {0x3288, 0x10}, + {0x3289, 0x00}, + {0x328a, 0x08}, + {0x328b, 0x00}, + {0x328c, 0x04}, + {0x328d, 0x00}, + {0x328e, 0x02}, + {0x328f, 0x00}, + {0x3290, 0x20}, + {0x3291, 0x00}, + {0x3292, 0x10}, + {0x3293, 0x00}, + {0x3294, 0x08}, + {0x3295, 0x00}, + {0x3296, 0x04}, + {0x3297, 0x00}, + {0x3298, 0x40}, + {0x3299, 0x00}, + {0x329a, 0x20}, + {0x329b, 0x00}, + {0x329c, 0x10}, + {0x329d, 0x00}, + {0x329e, 0x08}, + {0x329f, 0x00}, + {0x32a0, 0x7f}, + {0x32a1, 0xff}, + {0x32a2, 0x40}, + {0x32a3, 0x00}, + {0x32a4, 0x20}, + {0x32a5, 0x00}, + {0x32a6, 0x10}, + {0x32a7, 0x00}, + {0x32a8, 0x00}, + {0x32a9, 0x00}, + {0x32aa, 0x00}, + {0x32ab, 0x00}, + {0x32ac, 0x00}, + {0x32ad, 0x00}, + {0x32ae, 0x00}, + {0x32af, 0x00}, + {0x32b0, 0x00}, + {0x32b1, 0x00}, + {0x32b2, 0x00}, + {0x32b3, 0x00}, + {0x32b4, 0x00}, + {0x32b5, 0x00}, + {0x32b6, 0x00}, + {0x32b7, 0x00}, + {0x32b8, 0x00}, + {0x32b9, 0x00}, + {0x32ba, 0x00}, + {0x32bb, 0x00}, + {0x32bc, 0x00}, + {0x32bd, 0x00}, + {0x32be, 0x00}, + {0x32bf, 0x00}, + {0x32c0, 0x00}, + {0x32c1, 0x00}, + {0x32c2, 0x00}, + {0x32c3, 0x00}, + {0x32c4, 0x00}, + {0x32c5, 0x00}, + {0x32c6, 0x00}, + {0x32c7, 0x00}, + {0x32c8, 0x87}, + {0x32c9, 0x00}, + {0x3330, 0x03}, + {0x3331, 0xc8}, + {0x3332, 0x02}, + {0x3333, 0x24}, + {0x3334, 0x00}, + {0x3335, 0x00}, + {0x3336, 0x00}, + {0x3337, 0x00}, + {0x3338, 0x03}, + {0x3339, 0xc8}, + {0x333a, 0x02}, + {0x333b, 0x24}, + {0x333c, 0x00}, + {0x333d, 0x00}, + {0x333e, 0x00}, + {0x333f, 0x00}, + {0x3340, 0x03}, + {0x3341, 0xc8}, + {0x3342, 0x02}, + {0x3343, 0x24}, + {0x3344, 0x00}, + {0x3345, 0x00}, + {0x3346, 0x00}, + {0x3347, 0x00}, + {0x3348, 0x40}, + {0x3349, 0x00}, + {0x334a, 0x00}, + {0x334b, 0x00}, + {0x334c, 0x00}, + {0x334d, 0x00}, + {0x334e, 0x80}, + {0x3360, 0x01}, + {0x3361, 0x00}, + {0x3362, 0x01}, + {0x3363, 0x00}, + {0x3364, 0x01}, + {0x3365, 0x00}, + {0x3366, 0x01}, + {0x3367, 0x00}, + {0x3368, 0x01}, + {0x3369, 0x00}, + {0x336a, 0x01}, + {0x336b, 0x00}, + {0x336c, 0x01}, + {0x336d, 0x00}, + {0x336e, 0x01}, + {0x336f, 0x00}, + {0x3370, 0x01}, + {0x3371, 0x00}, + {0x3372, 0x01}, + {0x3373, 0x00}, + {0x3374, 0x01}, + {0x3375, 0x00}, + {0x3376, 0x01}, + {0x3377, 0x00}, + {0x3378, 0x00}, + {0x3379, 0x00}, + {0x337a, 0x00}, + {0x337b, 0x00}, + {0x337c, 0x00}, + {0x337d, 0x00}, + {0x337e, 0x00}, + {0x337f, 0x00}, + {0x3380, 0x00}, + {0x3381, 0x00}, + {0x3382, 0x00}, + {0x3383, 0x00}, + {0x3384, 0x00}, + {0x3385, 0x00}, + {0x3386, 0x00}, + {0x3387, 0x00}, + {0x3388, 0x00}, + {0x3389, 0x00}, + {0x338a, 0x00}, + {0x338b, 0x00}, + {0x338c, 0x00}, + {0x338d, 0x00}, + {0x338e, 0x00}, + {0x338f, 0x00}, + {0x3390, 0x00}, + {0x3391, 0x00}, + {0x3392, 0x00}, + {0x3393, 0x00}, + {0x3394, 0x00}, + {0x3395, 0x00}, + {0x3396, 0x00}, + {0x3397, 0x00}, + {0x3398, 0x00}, + {0x3399, 0x00}, + {0x339a, 0x00}, + {0x339b, 0x00}, + {0x33b0, 0x00}, + {0x33b1, 0x50}, + {0x33b2, 0x01}, + {0x33b3, 0xff}, + {0x33b4, 0xe0}, + {0x33b5, 0x6b}, + {0x33b6, 0x00}, + {0x33b7, 0x00}, + {0x33b8, 0x00}, + {0x33b9, 0x00}, + {0x33ba, 0x00}, + {0x33bb, 0x1f}, + {0x33bc, 0x01}, + {0x33bd, 0x01}, + {0x33be, 0x01}, + {0x33bf, 0x01}, + {0x33c0, 0x00}, + {0x33c1, 0x00}, + {0x33c2, 0x00}, + {0x33c3, 0x00}, + {0x33e0, 0x14}, + {0x33e1, 0x0f}, + {0x33e2, 0x02}, + {0x33e3, 0x01}, + {0x33e4, 0x01}, + {0x33e5, 0x01}, + {0x33e6, 0x00}, + {0x33e7, 0x04}, + {0x33e8, 0x0c}, + {0x33e9, 0x02}, + {0x33ea, 0x02}, + {0x33eb, 0x02}, + {0x33ec, 0x03}, + {0x33ed, 0x01}, + {0x33ee, 0x02}, + {0x33ef, 0x08}, + {0x33f0, 0x08}, + {0x33f1, 0x04}, + {0x33f2, 0x04}, + {0x33f3, 0x00}, + {0x33f4, 0x03}, + {0x33f5, 0x14}, + {0x33f6, 0x0f}, + {0x33f7, 0x02}, + {0x33f8, 0x01}, + {0x33f9, 0x01}, + {0x33fa, 0x01}, + {0x33fb, 0x00}, + {0x33fc, 0x04}, + {0x33fd, 0x0c}, + {0x33fe, 0x02}, + {0x33ff, 0x02}, + {0x3400, 0x02}, + {0x3401, 0x03}, + {0x3402, 0x01}, + {0x3403, 0x02}, + {0x3404, 0x08}, + {0x3405, 0x08}, + {0x3406, 0x04}, + {0x3407, 0x04}, + {0x3408, 0x00}, + {0x3409, 0x03}, + {0x340a, 0x14}, + {0x340b, 0x0f}, + {0x340c, 0x04}, + {0x340d, 0x02}, + {0x340e, 0x01}, + {0x340f, 0x01}, + {0x3410, 0x00}, + {0x3411, 0x04}, + {0x3412, 0x0c}, + {0x3413, 0x02}, + {0x3414, 0x02}, + {0x3415, 0x02}, + {0x3416, 0x03}, + {0x3417, 0x02}, + {0x3418, 0x05}, + {0x3419, 0x0a}, + {0x341a, 0x08}, + {0x341b, 0x04}, + {0x341c, 0x04}, + {0x341d, 0x00}, + {0x341e, 0x03}, + {0x3440, 0x00}, + {0x3441, 0x00}, + {0x3442, 0x00}, + {0x3443, 0x00}, + {0x3444, 0x02}, + {0x3445, 0xf0}, + {0x3446, 0x02}, + {0x3447, 0x08}, + {0x3448, 0x00}, + {0x3460, 0x40}, + {0x3461, 0x40}, + {0x3462, 0x40}, + {0x3463, 0x40}, + {0x3464, 0x03}, + {0x3465, 0x01}, + {0x3466, 0x01}, + {0x3467, 0x02}, + {0x3468, 0x30}, + {0x3469, 0x00}, + {0x346a, 0x33}, + {0x346b, 0xbf}, + {0x3480, 0x40}, + {0x3481, 0x00}, + {0x3482, 0x00}, + {0x3483, 0x00}, + {0x3484, 0x0d}, + {0x3485, 0x00}, + {0x3486, 0x00}, + {0x3487, 0x00}, + {0x3488, 0x00}, + {0x3489, 0x00}, + {0x348a, 0x00}, + {0x348b, 0x04}, + {0x348c, 0x00}, + {0x348d, 0x01}, + {0x348f, 0x01}, + {0x3030, 0x0a}, + {0x3030, 0x02}, + {0x7000, 0x58}, + {0x7001, 0x7a}, + {0x7002, 0x1a}, + {0x7003, 0xc1}, + {0x7004, 0x03}, + {0x7005, 0xda}, + {0x7006, 0xbd}, + {0x7007, 0x03}, + {0x7008, 0xbd}, + {0x7009, 0x06}, + {0x700a, 0xe6}, + {0x700b, 0xec}, + {0x700c, 0xbc}, + {0x700d, 0xff}, + {0x700e, 0xbc}, + {0x700f, 0x73}, + {0x7010, 0xda}, + {0x7011, 0x72}, + {0x7012, 0x76}, + {0x7013, 0xb6}, + {0x7014, 0xee}, + {0x7015, 0xcf}, + {0x7016, 0xac}, + {0x7017, 0xd0}, + {0x7018, 0xac}, + {0x7019, 0xd1}, + {0x701a, 0x50}, + {0x701b, 0xac}, + {0x701c, 0xd2}, + {0x701d, 0xbc}, + {0x701e, 0x2e}, + {0x701f, 0xb4}, + {0x7020, 0x00}, + {0x7021, 0xdc}, + {0x7022, 0xdf}, + {0x7023, 0xb0}, + {0x7024, 0x6e}, + {0x7025, 0xbd}, + {0x7026, 0x01}, + {0x7027, 0xd7}, + {0x7028, 0xed}, + {0x7029, 0xe1}, + {0x702a, 0x36}, + {0x702b, 0x30}, + {0x702c, 0xd3}, + {0x702d, 0x2e}, + {0x702e, 0x54}, + {0x702f, 0x46}, + {0x7030, 0xbc}, + {0x7031, 0x22}, + {0x7032, 0x66}, + {0x7033, 0xbc}, + {0x7034, 0x24}, + {0x7035, 0x2c}, + {0x7036, 0x28}, + {0x7037, 0xbc}, + {0x7038, 0x3c}, + {0x7039, 0xa1}, + {0x703a, 0xac}, + {0x703b, 0xd8}, + {0x703c, 0xd6}, + {0x703d, 0xb4}, + {0x703e, 0x04}, + {0x703f, 0x46}, + {0x7040, 0xb7}, + {0x7041, 0x04}, + {0x7042, 0xbe}, + {0x7043, 0x08}, + {0x7044, 0xc3}, + {0x7045, 0xd9}, + {0x7046, 0xad}, + {0x7047, 0xc3}, + {0x7048, 0xbc}, + {0x7049, 0x19}, + {0x704a, 0xc1}, + {0x704b, 0x27}, + {0x704c, 0xe7}, + {0x704d, 0x00}, + {0x704e, 0x50}, + {0x704f, 0x20}, + {0x7050, 0xb8}, + {0x7051, 0x02}, + {0x7052, 0xbc}, + {0x7053, 0x17}, + {0x7054, 0xdb}, + {0x7055, 0xc7}, + {0x7056, 0xb8}, + {0x7057, 0x00}, + {0x7058, 0x28}, + {0x7059, 0x54}, + {0x705a, 0xb4}, + {0x705b, 0x14}, + {0x705c, 0xab}, + {0x705d, 0xbe}, + {0x705e, 0x06}, + {0x705f, 0xd8}, + {0x7060, 0xd6}, + {0x7061, 0x00}, + {0x7062, 0xb4}, + {0x7063, 0xc7}, + {0x7064, 0x07}, + {0x7065, 0xb9}, + {0x7066, 0x05}, + {0x7067, 0xee}, + {0x7068, 0xe6}, + {0x7069, 0xad}, + {0x706a, 0xb4}, + {0x706b, 0x26}, + {0x706c, 0x19}, + {0x706d, 0xc1}, + {0x706e, 0x3a}, + {0x706f, 0xc3}, + {0x7070, 0xaf}, + {0x7071, 0x00}, + {0x7072, 0xc0}, + {0x7073, 0x3c}, + {0x7074, 0xc3}, + {0x7075, 0xbe}, + {0x7076, 0xe7}, + {0x7077, 0x00}, + {0x7078, 0x15}, + {0x7079, 0xc2}, + {0x707a, 0x40}, + {0x707b, 0xc3}, + {0x707c, 0xa4}, + {0x707d, 0xc0}, + {0x707e, 0x3c}, + {0x707f, 0x00}, + {0x7080, 0xb9}, + {0x7081, 0x64}, + {0x7082, 0x29}, + {0x7083, 0x00}, + {0x7084, 0xb8}, + {0x7085, 0x12}, + {0x7086, 0xbe}, + {0x7087, 0x01}, + {0x7088, 0xd0}, + {0x7089, 0xbc}, + {0x708a, 0x01}, + {0x708b, 0xac}, + {0x708c, 0x37}, + {0x708d, 0xd2}, + {0x708e, 0xac}, + {0x708f, 0x45}, + {0x7090, 0xad}, + {0x7091, 0x28}, + {0x7092, 0x00}, + {0x7093, 0xb8}, + {0x7094, 0x00}, + {0x7095, 0xbc}, + {0x7096, 0x01}, + {0x7097, 0x36}, + {0x7098, 0xd3}, + {0x7099, 0x30}, + {0x709a, 0x04}, + {0x709b, 0xe0}, + {0x709c, 0xd8}, + {0x709d, 0xb4}, + {0x709e, 0xe9}, + {0x709f, 0x00}, + {0x70a0, 0xbe}, + {0x70a1, 0x05}, + {0x70a2, 0x62}, + {0x70a3, 0x07}, + {0x70a4, 0xb9}, + {0x70a5, 0x05}, + {0x70a6, 0xad}, + {0x70a7, 0xc3}, + {0x70a8, 0xcf}, + {0x70a9, 0x00}, + {0x70aa, 0x15}, + {0x70ab, 0xc2}, + {0x70ac, 0x59}, + {0x70ad, 0xc3}, + {0x70ae, 0xc9}, + {0x70af, 0xc0}, + {0x70b0, 0x55}, + {0x70b1, 0x00}, + {0x70b2, 0x46}, + {0x70b3, 0xa1}, + {0x70b4, 0xb9}, + {0x70b5, 0x64}, + {0x70b6, 0x29}, + {0x70b7, 0x00}, + {0x70b8, 0xb8}, + {0x70b9, 0x02}, + {0x70ba, 0xbe}, + {0x70bb, 0x02}, + {0x70bc, 0xd0}, + {0x70bd, 0xdc}, + {0x70be, 0xac}, + {0x70bf, 0xbc}, + {0x70c0, 0x01}, + {0x70c1, 0x37}, + {0x70c2, 0xac}, + {0x70c3, 0xd2}, + {0x70c4, 0x45}, + {0x70c5, 0xad}, + {0x70c6, 0x28}, + {0x70c7, 0x00}, + {0x70c8, 0xb8}, + {0x70c9, 0x00}, + {0x70ca, 0xbc}, + {0x70cb, 0x01}, + {0x70cc, 0x36}, + {0x70cd, 0x30}, + {0x70ce, 0xe0}, + {0x70cf, 0xd8}, + {0x70d0, 0xb5}, + {0x70d1, 0x0b}, + {0x70d2, 0xd6}, + {0x70d3, 0xbe}, + {0x70d4, 0x07}, + {0x70d5, 0x00}, + {0x70d6, 0x62}, + {0x70d7, 0x07}, + {0x70d8, 0xb9}, + {0x70d9, 0x05}, + {0x70da, 0xad}, + {0x70db, 0xc3}, + {0x70dc, 0xcf}, + {0x70dd, 0x46}, + {0x70de, 0xcd}, + {0x70df, 0x07}, + {0x70e0, 0xcd}, + {0x70e1, 0x00}, + {0x70e2, 0xe3}, + {0x70e3, 0x18}, + {0x70e4, 0xc2}, + {0x70e5, 0xa2}, + {0x70e6, 0xb9}, + {0x70e7, 0x64}, + {0x70e8, 0xd1}, + {0x70e9, 0xdd}, + {0x70ea, 0xac}, + {0x70eb, 0xcf}, + {0x70ec, 0xdf}, + {0x70ed, 0xb5}, + {0x70ee, 0x19}, + {0x70ef, 0x46}, + {0x70f0, 0x50}, + {0x70f1, 0xb6}, + {0x70f2, 0xee}, + {0x70f3, 0xe8}, + {0x70f4, 0xe6}, + {0x70f5, 0xbc}, + {0x70f6, 0x31}, + {0x70f7, 0xe1}, + {0x70f8, 0x36}, + {0x70f9, 0x30}, + {0x70fa, 0xd3}, + {0x70fb, 0x2e}, + {0x70fc, 0x54}, + {0x70fd, 0xbd}, + {0x70fe, 0x03}, + {0x70ff, 0xec}, + {0x7100, 0x2c}, + {0x7101, 0x50}, + {0x7102, 0x20}, + {0x7103, 0x04}, + {0x7104, 0xb8}, + {0x7105, 0x02}, + {0x7106, 0xbc}, + {0x7107, 0x18}, + {0x7108, 0xc7}, + {0x7109, 0xb8}, + {0x710a, 0x00}, + {0x710b, 0x28}, + {0x710c, 0x54}, + {0x710d, 0xbc}, + {0x710e, 0x02}, + {0x710f, 0xb4}, + {0x7110, 0xda}, + {0x7111, 0xbe}, + {0x7112, 0x04}, + {0x7113, 0xd6}, + {0x7114, 0xd8}, + {0x7115, 0xab}, + {0x7116, 0x00}, + {0x7117, 0x62}, + {0x7118, 0x07}, + {0x7119, 0xb9}, + {0x711a, 0x05}, + {0x711b, 0xad}, + {0x711c, 0xc3}, + {0x711d, 0xbc}, + {0x711e, 0xe7}, + {0x711f, 0xb9}, + {0x7120, 0x64}, + {0x7121, 0x29}, + {0x7122, 0x00}, + {0x7123, 0xb8}, + {0x7124, 0x02}, + {0x7125, 0xbe}, + {0x7126, 0x00}, + {0x7127, 0x45}, + {0x7128, 0xad}, + {0x7129, 0xe2}, + {0x712a, 0x28}, + {0x712b, 0x00}, + {0x712c, 0xb8}, + {0x712d, 0x00}, + {0x712e, 0xe0}, + {0x712f, 0xd8}, + {0x7130, 0xb4}, + {0x7131, 0xe9}, + {0x7132, 0xbe}, + {0x7133, 0x03}, + {0x7134, 0x00}, + {0x7135, 0x30}, + {0x7136, 0x62}, + {0x7137, 0x07}, + {0x7138, 0xb9}, + {0x7139, 0x05}, + {0x713a, 0xad}, + {0x713b, 0xc3}, + {0x713c, 0xcf}, + {0x713d, 0x42}, + {0x713e, 0xe4}, + {0x713f, 0xcd}, + {0x7140, 0x07}, + {0x7141, 0xcd}, + {0x7142, 0x00}, + {0x7143, 0x00}, + {0x7144, 0x17}, + {0x7145, 0xc2}, + {0x7146, 0xbb}, + {0x7147, 0xde}, + {0x7148, 0xcf}, + {0x7149, 0xdf}, + {0x714a, 0xac}, + {0x714b, 0xd1}, + {0x714c, 0x44}, + {0x714d, 0xac}, + {0x714e, 0xb9}, + {0x714f, 0x76}, + {0x7150, 0xb8}, + {0x7151, 0x08}, + {0x7152, 0xb6}, + {0x7153, 0xfe}, + {0x7154, 0xb4}, + {0x7155, 0xca}, + {0x7156, 0xd6}, + {0x7157, 0xd8}, + {0x7158, 0xab}, + {0x7159, 0x00}, + {0x715a, 0xe1}, + {0x715b, 0x36}, + {0x715c, 0x30}, + {0x715d, 0xd3}, + {0x715e, 0xbc}, + {0x715f, 0x29}, + {0x7160, 0xb4}, + {0x7161, 0x1f}, + {0x7162, 0xaa}, + {0x7163, 0xbd}, + {0x7164, 0x01}, + {0x7165, 0xb8}, + {0x7166, 0x0c}, + {0x7167, 0x45}, + {0x7168, 0xa4}, + {0x7169, 0xbd}, + {0x716a, 0x03}, + {0x716b, 0xec}, + {0x716c, 0xbc}, + {0x716d, 0x3d}, + {0x716e, 0xc3}, + {0x716f, 0xcf}, + {0x7170, 0x42}, + {0x7171, 0xb8}, + {0x7172, 0x00}, + {0x7173, 0xe4}, + {0x7174, 0xd5}, + {0x7175, 0x00}, + {0x7176, 0xb6}, + {0x7177, 0x00}, + {0x7178, 0x74}, + {0x7179, 0xbd}, + {0x717a, 0x03}, + {0x717b, 0xb5}, + {0x717c, 0x39}, + {0x717d, 0x40}, + {0x717e, 0x58}, + {0x717f, 0xdd}, + {0x7180, 0x19}, + {0x7181, 0xc1}, + {0x7182, 0xc8}, + {0x7183, 0xbd}, + {0x7184, 0x06}, + {0x7185, 0x17}, + {0x7186, 0xc1}, + {0x7187, 0xc6}, + {0x7188, 0xe8}, + {0x7189, 0x00}, + {0x718a, 0xc0}, + {0x718b, 0xc8}, + {0x718c, 0xe6}, + {0x718d, 0x95}, + {0x718e, 0x15}, + {0x718f, 0x00}, + {0x7190, 0xbc}, + {0x7191, 0x19}, + {0x7192, 0xb9}, + {0x7193, 0xf6}, + {0x7194, 0x14}, + {0x7195, 0xc1}, + {0x7196, 0xd0}, + {0x7197, 0xd1}, + {0x7198, 0xac}, + {0x7199, 0x37}, + {0x719a, 0xbc}, + {0x719b, 0x35}, + {0x719c, 0x36}, + {0x719d, 0x30}, + {0x719e, 0xe1}, + {0x719f, 0xd3}, + {0x71a0, 0x7a}, + {0x71a1, 0xb6}, + {0x71a2, 0x0c}, + {0x71a3, 0xff}, + {0x71a4, 0xb4}, + {0x71a5, 0xc7}, + {0x71a6, 0xd9}, + {0x71a7, 0x00}, + {0x71a8, 0xbd}, + {0x71a9, 0x01}, + {0x71aa, 0x56}, + {0x71ab, 0xc0}, + {0x71ac, 0xda}, + {0x71ad, 0xb4}, + {0x71ae, 0x1f}, + {0x71af, 0x56}, + {0x71b0, 0xaa}, + {0x71b1, 0xbc}, + {0x71b2, 0x08}, + {0x71b3, 0x00}, + {0x71b4, 0x57}, + {0x71b5, 0xe8}, + {0x71b6, 0xb5}, + {0x71b7, 0x36}, + {0x71b8, 0x00}, + {0x71b9, 0x54}, + {0x71ba, 0xe7}, + {0x71bb, 0xc8}, + {0x71bc, 0xb4}, + {0x71bd, 0x1f}, + {0x71be, 0x56}, + {0x71bf, 0xaa}, + {0x71c0, 0xbc}, + {0x71c1, 0x08}, + {0x71c2, 0x57}, + {0x71c3, 0x00}, + {0x71c4, 0xb5}, + {0x71c5, 0x36}, + {0x71c6, 0x00}, + {0x71c7, 0x54}, + {0x71c8, 0xc8}, + {0x71c9, 0xb5}, + {0x71ca, 0x18}, + {0x71cb, 0xd9}, + {0x71cc, 0x00}, + {0x71cd, 0xbd}, + {0x71ce, 0x01}, + {0x71cf, 0x56}, + {0x71d0, 0x08}, + {0x71d1, 0x57}, + {0x71d2, 0xe8}, + {0x71d3, 0xb4}, + {0x71d4, 0x42}, + {0x71d5, 0x00}, + {0x71d6, 0x54}, + {0x71d7, 0xe7}, + {0x71d8, 0xc8}, + {0x71d9, 0xab}, + {0x71da, 0x00}, + {0x71db, 0x66}, + {0x71dc, 0x62}, + {0x71dd, 0x06}, + {0x71de, 0x74}, + {0x71df, 0xb9}, + {0x71e0, 0x05}, + {0x71e1, 0xb7}, + {0x71e2, 0x14}, + {0x71e3, 0x0e}, + {0x71e4, 0xb7}, + {0x71e5, 0x04}, + {0x71e6, 0xc8}, + {0x7600, 0x04}, + {0x7601, 0x80}, + {0x7602, 0x07}, + {0x7603, 0x44}, + {0x7604, 0x05}, + {0x7605, 0x33}, + {0x7606, 0x0f}, + {0x7607, 0x00}, + {0x7608, 0x07}, + {0x7609, 0x40}, + {0x760a, 0x04}, + {0x760b, 0xe5}, + {0x760c, 0x06}, + {0x760d, 0x50}, + {0x760e, 0x04}, + {0x760f, 0xe4}, + {0x7610, 0x00}, + {0x7611, 0x00}, + {0x7612, 0x06}, + {0x7613, 0x5c}, + {0x7614, 0x00}, + {0x7615, 0x0f}, + {0x7616, 0x06}, + {0x7617, 0x1c}, + {0x7618, 0x00}, + {0x7619, 0x02}, + {0x761a, 0x06}, + {0x761b, 0xa2}, + {0x761c, 0x00}, + {0x761d, 0x01}, + {0x761e, 0x06}, + {0x761f, 0xae}, + {0x7620, 0x00}, + {0x7621, 0x0e}, + {0x7622, 0x05}, + {0x7623, 0x30}, + {0x7624, 0x07}, + {0x7625, 0x00}, + {0x7626, 0x0f}, + {0x7627, 0x00}, + {0x7628, 0x04}, + {0x7629, 0xe5}, + {0x762a, 0x05}, + {0x762b, 0x33}, + {0x762c, 0x06}, + {0x762d, 0x12}, + {0x762e, 0x00}, + {0x762f, 0x01}, + {0x7630, 0x06}, + {0x7631, 0x52}, + {0x7632, 0x00}, + {0x7633, 0x01}, + {0x7634, 0x06}, + {0x7635, 0x5e}, + {0x7636, 0x04}, + {0x7637, 0xe4}, + {0x7638, 0x00}, + {0x7639, 0x01}, + {0x763a, 0x05}, + {0x763b, 0x30}, + {0x763c, 0x0f}, + {0x763d, 0x00}, + {0x763e, 0x06}, + {0x763f, 0xa6}, + {0x7640, 0x00}, + {0x7641, 0x02}, + {0x7642, 0x06}, + {0x7643, 0x26}, + {0x7644, 0x00}, + {0x7645, 0x02}, + {0x7646, 0x05}, + {0x7647, 0x33}, + {0x7648, 0x06}, + {0x7649, 0x20}, + {0x764a, 0x0f}, + {0x764b, 0x00}, + {0x764c, 0x06}, + {0x764d, 0x56}, + {0x764e, 0x00}, + {0x764f, 0x02}, + {0x7650, 0x06}, + {0x7651, 0x16}, + {0x7652, 0x05}, + {0x7653, 0x33}, + {0x7654, 0x06}, + {0x7655, 0x10}, + {0x7656, 0x0f}, + {0x7657, 0x00}, + {0x7658, 0x06}, + {0x7659, 0x10}, + {0x765a, 0x0f}, + {0x765b, 0x00}, + {0x765c, 0x06}, + {0x765d, 0x20}, + {0x765e, 0x0f}, + {0x765f, 0x00}, + {0x7660, 0x00}, + {0x7661, 0x00}, + {0x7662, 0x00}, + {0x7663, 0x02}, + {0x7664, 0x04}, + {0x7665, 0xe5}, + {0x7666, 0x04}, + {0x7667, 0xe4}, + {0x7668, 0x0f}, + {0x7669, 0x00}, + {0x766a, 0x00}, + {0x766b, 0x00}, + {0x766c, 0x00}, + {0x766d, 0x01}, + {0x766e, 0x04}, + {0x766f, 0xe5}, + {0x7670, 0x04}, + {0x7671, 0xe4}, + {0x7672, 0x0f}, + {0x7673, 0x00}, + {0x7674, 0x00}, + {0x7675, 0x02}, + {0x7676, 0x04}, + {0x7677, 0xe4}, + {0x7678, 0x00}, + {0x7679, 0x02}, + {0x767a, 0x04}, + {0x767b, 0xc4}, + {0x767c, 0x00}, + {0x767d, 0x02}, + {0x767e, 0x04}, + {0x767f, 0xc4}, + {0x7680, 0x05}, + {0x7681, 0x83}, + {0x7682, 0x0f}, + {0x7683, 0x00}, + {0x7684, 0x00}, + {0x7685, 0x02}, + {0x7686, 0x04}, + {0x7687, 0xe4}, + {0x7688, 0x00}, + {0x7689, 0x02}, + {0x768a, 0x04}, + {0x768b, 0xc4}, + {0x768c, 0x00}, + {0x768d, 0x02}, + {0x768e, 0x04}, + {0x768f, 0xc4}, + {0x7690, 0x05}, + {0x7691, 0x83}, + {0x7692, 0x03}, + {0x7693, 0x0b}, + {0x7694, 0x05}, + {0x7695, 0x83}, + {0x7696, 0x00}, + {0x7697, 0x07}, + {0x7698, 0x05}, + {0x7699, 0x03}, + {0x769a, 0x00}, + {0x769b, 0x05}, + {0x769c, 0x05}, + {0x769d, 0x32}, + {0x769e, 0x05}, + {0x769f, 0x30}, + {0x76a0, 0x00}, + {0x76a1, 0x02}, + {0x76a2, 0x05}, + {0x76a3, 0x78}, + {0x76a4, 0x00}, + {0x76a5, 0x01}, + {0x76a6, 0x05}, + {0x76a7, 0x7c}, + {0x76a8, 0x03}, + {0x76a9, 0x9a}, + {0x76aa, 0x05}, + {0x76ab, 0x83}, + {0x76ac, 0x00}, + {0x76ad, 0x04}, + {0x76ae, 0x05}, + {0x76af, 0x03}, + {0x76b0, 0x00}, + {0x76b1, 0x03}, + {0x76b2, 0x05}, + {0x76b3, 0x32}, + {0x76b4, 0x05}, + {0x76b5, 0x30}, + {0x76b6, 0x00}, + {0x76b7, 0x02}, + {0x76b8, 0x05}, + {0x76b9, 0x78}, + {0x76ba, 0x00}, + {0x76bb, 0x01}, + {0x76bc, 0x05}, + {0x76bd, 0x7c}, + {0x76be, 0x03}, + {0x76bf, 0x99}, + {0x76c0, 0x05}, + {0x76c1, 0x83}, + {0x76c2, 0x00}, + {0x76c3, 0x03}, + {0x76c4, 0x05}, + {0x76c5, 0x03}, + {0x76c6, 0x00}, + {0x76c7, 0x01}, + {0x76c8, 0x05}, + {0x76c9, 0x32}, + {0x76ca, 0x05}, + {0x76cb, 0x30}, + {0x76cc, 0x00}, + {0x76cd, 0x02}, + {0x76ce, 0x05}, + {0x76cf, 0x78}, + {0x76d0, 0x00}, + {0x76d1, 0x01}, + {0x76d2, 0x05}, + {0x76d3, 0x7c}, + {0x76d4, 0x03}, + {0x76d5, 0x98}, + {0x76d6, 0x05}, + {0x76d7, 0x83}, + {0x76d8, 0x00}, + {0x76d9, 0x00}, + {0x76da, 0x05}, + {0x76db, 0x03}, + {0x76dc, 0x00}, + {0x76dd, 0x01}, + {0x76de, 0x05}, + {0x76df, 0x32}, + {0x76e0, 0x05}, + {0x76e1, 0x30}, + {0x76e2, 0x00}, + {0x76e3, 0x02}, + {0x76e4, 0x05}, + {0x76e5, 0x78}, + {0x76e6, 0x00}, + {0x76e7, 0x01}, + {0x76e8, 0x05}, + {0x76e9, 0x7c}, + {0x76ea, 0x03}, + {0x76eb, 0x97}, + {0x76ec, 0x05}, + {0x76ed, 0x83}, + {0x76ee, 0x00}, + {0x76ef, 0x00}, + {0x76f0, 0x05}, + {0x76f1, 0x03}, + {0x76f2, 0x05}, + {0x76f3, 0x32}, + {0x76f4, 0x05}, + {0x76f5, 0x30}, + {0x76f6, 0x00}, + {0x76f7, 0x02}, + {0x76f8, 0x05}, + {0x76f9, 0x78}, + {0x76fa, 0x00}, + {0x76fb, 0x01}, + {0x76fc, 0x05}, + {0x76fd, 0x7c}, + {0x76fe, 0x03}, + {0x76ff, 0x96}, + {0x7700, 0x05}, + {0x7701, 0x83}, + {0x7702, 0x05}, + {0x7703, 0x03}, + {0x7704, 0x05}, + {0x7705, 0x32}, + {0x7706, 0x05}, + {0x7707, 0x30}, + {0x7708, 0x00}, + {0x7709, 0x02}, + {0x770a, 0x05}, + {0x770b, 0x78}, + {0x770c, 0x00}, + {0x770d, 0x01}, + {0x770e, 0x05}, + {0x770f, 0x7c}, + {0x7710, 0x03}, + {0x7711, 0x95}, + {0x7712, 0x05}, + {0x7713, 0x83}, + {0x7714, 0x05}, + {0x7715, 0x03}, + {0x7716, 0x05}, + {0x7717, 0x32}, + {0x7718, 0x05}, + {0x7719, 0x30}, + {0x771a, 0x00}, + {0x771b, 0x02}, + {0x771c, 0x05}, + {0x771d, 0x78}, + {0x771e, 0x00}, + {0x771f, 0x01}, + {0x7720, 0x05}, + {0x7721, 0x7c}, + {0x7722, 0x03}, + {0x7723, 0x94}, + {0x7724, 0x05}, + {0x7725, 0x83}, + {0x7726, 0x00}, + {0x7727, 0x01}, + {0x7728, 0x05}, + {0x7729, 0x03}, + {0x772a, 0x00}, + {0x772b, 0x01}, + {0x772c, 0x05}, + {0x772d, 0x32}, + {0x772e, 0x05}, + {0x772f, 0x30}, + {0x7730, 0x00}, + {0x7731, 0x02}, + {0x7732, 0x05}, + {0x7733, 0x78}, + {0x7734, 0x00}, + {0x7735, 0x01}, + {0x7736, 0x05}, + {0x7737, 0x7c}, + {0x7738, 0x03}, + {0x7739, 0x93}, + {0x773a, 0x05}, + {0x773b, 0x83}, + {0x773c, 0x00}, + {0x773d, 0x00}, + {0x773e, 0x05}, + {0x773f, 0x03}, + {0x7740, 0x00}, + {0x7741, 0x00}, + {0x7742, 0x05}, + {0x7743, 0x32}, + {0x7744, 0x05}, + {0x7745, 0x30}, + {0x7746, 0x00}, + {0x7747, 0x02}, + {0x7748, 0x05}, + {0x7749, 0x78}, + {0x774a, 0x00}, + {0x774b, 0x01}, + {0x774c, 0x05}, + {0x774d, 0x7c}, + {0x774e, 0x03}, + {0x774f, 0x92}, + {0x7750, 0x05}, + {0x7751, 0x83}, + {0x7752, 0x05}, + {0x7753, 0x03}, + {0x7754, 0x00}, + {0x7755, 0x00}, + {0x7756, 0x05}, + {0x7757, 0x32}, + {0x7758, 0x05}, + {0x7759, 0x30}, + {0x775a, 0x00}, + {0x775b, 0x02}, + {0x775c, 0x05}, + {0x775d, 0x78}, + {0x775e, 0x00}, + {0x775f, 0x01}, + {0x7760, 0x05}, + {0x7761, 0x7c}, + {0x7762, 0x03}, + {0x7763, 0x91}, + {0x7764, 0x05}, + {0x7765, 0x83}, + {0x7766, 0x05}, + {0x7767, 0x03}, + {0x7768, 0x05}, + {0x7769, 0x32}, + {0x776a, 0x05}, + {0x776b, 0x30}, + {0x776c, 0x00}, + {0x776d, 0x02}, + {0x776e, 0x05}, + {0x776f, 0x78}, + {0x7770, 0x00}, + {0x7771, 0x01}, + {0x7772, 0x05}, + {0x7773, 0x7c}, + {0x7774, 0x03}, + {0x7775, 0x90}, + {0x7776, 0x05}, + {0x7777, 0x83}, + {0x7778, 0x05}, + {0x7779, 0x03}, + {0x777a, 0x05}, + {0x777b, 0x32}, + {0x777c, 0x05}, + {0x777d, 0x30}, + {0x777e, 0x00}, + {0x777f, 0x02}, + {0x7780, 0x05}, + {0x7781, 0x78}, + {0x7782, 0x00}, + {0x7783, 0x01}, + {0x7784, 0x05}, + {0x7785, 0x7c}, + {0x7786, 0x02}, + {0x7787, 0x90}, + {0x7788, 0x05}, + {0x7789, 0x03}, + {0x778a, 0x07}, + {0x778b, 0x00}, + {0x778c, 0x0f}, + {0x778d, 0x00}, + {0x778e, 0x08}, + {0x778f, 0x30}, + {0x7790, 0x08}, + {0x7791, 0xee}, + {0x7792, 0x0f}, + {0x7793, 0x00}, + {0x7794, 0x05}, + {0x7795, 0x33}, + {0x7796, 0x04}, + {0x7797, 0xe5}, + {0x7798, 0x06}, + {0x7799, 0x52}, + {0x779a, 0x04}, + {0x779b, 0xe4}, + {0x779c, 0x00}, + {0x779d, 0x00}, + {0x779e, 0x06}, + {0x779f, 0x5e}, + {0x77a0, 0x00}, + {0x77a1, 0x0f}, + {0x77a2, 0x06}, + {0x77a3, 0x1e}, + {0x77a4, 0x00}, + {0x77a5, 0x02}, + {0x77a6, 0x06}, + {0x77a7, 0xa2}, + {0x77a8, 0x00}, + {0x77a9, 0x01}, + {0x77aa, 0x06}, + {0x77ab, 0xae}, + {0x77ac, 0x00}, + {0x77ad, 0x03}, + {0x77ae, 0x05}, + {0x77af, 0x30}, + {0x77b0, 0x09}, + {0x77b1, 0x19}, + {0x77b2, 0x0f}, + {0x77b3, 0x00}, + {0x77b4, 0x05}, + {0x77b5, 0x33}, + {0x77b6, 0x04}, + {0x77b7, 0xe5}, + {0x77b8, 0x06}, + {0x77b9, 0x52}, + {0x77ba, 0x04}, + {0x77bb, 0xe4}, + {0x77bc, 0x00}, + {0x77bd, 0x00}, + {0x77be, 0x06}, + {0x77bf, 0x5e}, + {0x77c0, 0x00}, + {0x77c1, 0x0f}, + {0x77c2, 0x06}, + {0x77c3, 0x1e}, + {0x77c4, 0x00}, + {0x77c5, 0x02}, + {0x77c6, 0x06}, + {0x77c7, 0xa2}, + {0x77c8, 0x00}, + {0x77c9, 0x01}, + {0x77ca, 0x06}, + {0x77cb, 0xae}, + {0x77cc, 0x00}, + {0x77cd, 0x03}, + {0x77ce, 0x05}, + {0x77cf, 0x30}, + {0x77d0, 0x0f}, + {0x77d1, 0x00}, + {0x77d2, 0x00}, + {0x77d3, 0x00}, + {0x77d4, 0x00}, + {0x77d5, 0x02}, + {0x77d6, 0x04}, + {0x77d7, 0xe5}, + {0x77d8, 0x04}, + {0x77d9, 0xe4}, + {0x77da, 0x05}, + {0x77db, 0x33}, + {0x77dc, 0x07}, + {0x77dd, 0x10}, + {0x77de, 0x00}, + {0x77df, 0x00}, + {0x77e0, 0x01}, + {0x77e1, 0xbb}, + {0x77e2, 0x00}, + {0x77e3, 0x00}, + {0x77e4, 0x01}, + {0x77e5, 0xaa}, + {0x77e6, 0x00}, + {0x77e7, 0x00}, + {0x77e8, 0x01}, + {0x77e9, 0x99}, + {0x77ea, 0x00}, + {0x77eb, 0x00}, + {0x77ec, 0x01}, + {0x77ed, 0x88}, + {0x77ee, 0x00}, + {0x77ef, 0x00}, + {0x77f0, 0x01}, + {0x77f1, 0x77}, + {0x77f2, 0x00}, + {0x77f3, 0x00}, + {0x77f4, 0x01}, + {0x77f5, 0x66}, + {0x77f6, 0x00}, + {0x77f7, 0x00}, + {0x77f8, 0x01}, + {0x77f9, 0x55}, + {0x77fa, 0x00}, + {0x77fb, 0x00}, + {0x77fc, 0x01}, + {0x77fd, 0x44}, + {0x77fe, 0x00}, + {0x77ff, 0x00}, + {0x7800, 0x01}, + {0x7801, 0x33}, + {0x7802, 0x00}, + {0x7803, 0x00}, + {0x7804, 0x01}, + {0x7805, 0x22}, + {0x7806, 0x00}, + {0x7807, 0x00}, + {0x7808, 0x01}, + {0x7809, 0x11}, + {0x780a, 0x00}, + {0x780b, 0x00}, + {0x780c, 0x01}, + {0x780d, 0x00}, + {0x780e, 0x01}, + {0x780f, 0xff}, + {0x7810, 0x07}, + {0x7811, 0x00}, + {0x7812, 0x02}, + {0x7813, 0xa0}, + {0x7814, 0x0f}, + {0x7815, 0x00}, + {0x7816, 0x08}, + {0x7817, 0x35}, + {0x7818, 0x06}, + {0x7819, 0x52}, + {0x781a, 0x04}, + {0x781b, 0xe4}, + {0x781c, 0x00}, + {0x781d, 0x00}, + {0x781e, 0x06}, + {0x781f, 0x5e}, + {0x7820, 0x05}, + {0x7821, 0x33}, + {0x7822, 0x09}, + {0x7823, 0x19}, + {0x7824, 0x06}, + {0x7825, 0x1e}, + {0x7826, 0x05}, + {0x7827, 0x33}, + {0x7828, 0x00}, + {0x7829, 0x01}, + {0x782a, 0x06}, + {0x782b, 0x24}, + {0x782c, 0x06}, + {0x782d, 0x20}, + {0x782e, 0x0f}, + {0x782f, 0x00}, + {0x7830, 0x08}, + {0x7831, 0x35}, + {0x7832, 0x07}, + {0x7833, 0x10}, + {0x7834, 0x00}, + {0x7835, 0x00}, + {0x7836, 0x01}, + {0x7837, 0xbb}, + {0x7838, 0x00}, + {0x7839, 0x00}, + {0x783a, 0x01}, + {0x783b, 0xaa}, + {0x783c, 0x00}, + {0x783d, 0x00}, + {0x783e, 0x01}, + {0x783f, 0x99}, + {0x7840, 0x00}, + {0x7841, 0x00}, + {0x7842, 0x01}, + {0x7843, 0x88}, + {0x7844, 0x00}, + {0x7845, 0x00}, + {0x7846, 0x01}, + {0x7847, 0x77}, + {0x7848, 0x00}, + {0x7849, 0x00}, + {0x784a, 0x01}, + {0x784b, 0x66}, + {0x784c, 0x00}, + {0x784d, 0x00}, + {0x784e, 0x01}, + {0x784f, 0x55}, + {0x7850, 0x00}, + {0x7851, 0x00}, + {0x7852, 0x01}, + {0x7853, 0x44}, + {0x7854, 0x00}, + {0x7855, 0x00}, + {0x7856, 0x01}, + {0x7857, 0x33}, + {0x7858, 0x00}, + {0x7859, 0x00}, + {0x785a, 0x01}, + {0x785b, 0x22}, + {0x785c, 0x00}, + {0x785d, 0x00}, + {0x785e, 0x01}, + {0x785f, 0x11}, + {0x7860, 0x00}, + {0x7861, 0x00}, + {0x7862, 0x01}, + {0x7863, 0x00}, + {0x7864, 0x07}, + {0x7865, 0x00}, + {0x7866, 0x01}, + {0x7867, 0xff}, + {0x7868, 0x02}, + {0x7869, 0xa0}, + {0x786a, 0x0f}, + {0x786b, 0x00}, + {0x786c, 0x08}, + {0x786d, 0x3a}, + {0x786e, 0x08}, + {0x786f, 0x6a}, + {0x7870, 0x0f}, + {0x7871, 0x00}, + {0x7872, 0x04}, + {0x7873, 0xc0}, + {0x7874, 0x09}, + {0x7875, 0x19}, + {0x7876, 0x04}, + {0x7877, 0x99}, + {0x7878, 0x07}, + {0x7879, 0x14}, + {0x787a, 0x00}, + {0x787b, 0x01}, + {0x787c, 0x04}, + {0x787d, 0xa4}, + {0x787e, 0x00}, + {0x787f, 0x07}, + {0x7880, 0x04}, + {0x7881, 0xa6}, + {0x7882, 0x00}, + {0x7883, 0x00}, + {0x7884, 0x04}, + {0x7885, 0xa0}, + {0x7886, 0x04}, + {0x7887, 0x80}, + {0x7888, 0x04}, + {0x7889, 0x00}, + {0x788a, 0x05}, + {0x788b, 0x03}, + {0x788c, 0x06}, + {0x788d, 0x00}, + {0x788e, 0x0f}, + {0x788f, 0x00}, + {0x7890, 0x0f}, + {0x7891, 0x00}, + {0x7892, 0x0f}, + {0x7893, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x05}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x88}, + {0x30ae, 0x04}, + {0x30af, 0x40}, + {0x30b0, 0x0d}, + {0x30b1, 0xde}, + {0x30b2, 0x04}, + {0x30b3, 0x66}, + {0x30b6, 0x01}, + {0x30b7, 0x15}, + {0x3196, 0x00}, + {0x3197, 0x0a}, + {0x3195, 0x29}, + {0x315a, 0x02}, + {0x315b, 0x00}, + {0x30bb, 0x40}, + {0x3250, 0xf7}, + {0x30a8, 0x00}, + {0x30a9, 0x04}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x80}, + {0x30ae, 0x04}, + {0x30af, 0x38}, + {0x3012, 0x01}, +}; + +struct vvcam_sccb_array ox03a10_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(ox03a10_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = ox03a10_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam/native/sensor/ox03a10/ox03a10_reg_cfg.h b/vvcam/native/sensor/ox03a10/ox03a10_reg_cfg.h new file mode 100755 index 0000000..b8fef45 --- /dev/null +++ b/vvcam/native/sensor/ox03a10/ox03a10_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OX03a10_REG_CFG_H_ +#define _OX03a10_REG_CFG_H_ + +extern struct vvcam_sccb_array ox03a10_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam/native/sensor/platform/platform_gen6_driver.c b/vvcam/native/sensor/platform/platform_gen6_driver.c new file mode 100755 index 0000000..a3a8f66 --- /dev/null +++ b/vvcam/native/sensor/platform/platform_gen6_driver.c @@ -0,0 +1,130 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include "vvsensor.h" +#include "../native/sensor/sensor_common.h" + +int32_t sensor_reset(void *dev); +int32_t sensor_set_clk(void *dev, uint32_t clk); +int32_t sensor_get_clk(void *dev, uint32_t *pclk); +int32_t sensor_set_power(void *dev, uint32_t power); +int32_t sensor_get_power(void *dev, uint32_t *ppower); + +int32_t sensor_reset(void *dev) +{ + int ret = 0; + struct vvcam_sensor_dev *psensor_dev = (struct vvcam_sensor_dev *)dev; + + if (gpio_is_valid(psensor_dev->rst_pin)) { + gpio_direction_output(psensor_dev->rst_pin, 1); + } + + if (gpio_is_valid(psensor_dev->pdn_pin)) { + gpio_direction_output(psensor_dev->pdn_pin, 1); + } + + udelay(psensor_dev->pdn_delay_us); + return 0; +} + +int32_t sensor_set_clk(void *dev, uint32_t clk) +{ + return 0; +} + +int32_t sensor_get_clk(void *dev, uint32_t *pclk) +{ + return 0; +} + +int32_t sensor_set_power(void *dev, uint32_t power) +{ + int ret = 0, i = 0; + struct vvcam_sensor_dev *psensor_dev = (struct vvcam_sensor_dev *)dev; + printk("sensor_set_power enter, power=%d\n", power); + + if (psensor_dev->regulators.num <= 0) { + printk("no regulator for %s", psensor_dev->sensor_name); + return -ENODEV; + } + + for (i = 0; i < psensor_dev->regulators.num; i++) { + if (gpio_is_valid(psensor_dev->rst_pin)) { + gpio_direction_output(psensor_dev->rst_pin, 0); // make sure reset is low before power up + } + + if (gpio_is_valid(psensor_dev->pdn_pin)) { + gpio_direction_output(psensor_dev->pdn_pin, 0); + } + + if (power == 1) { + ret = regulator_enable(psensor_dev->regulators.supply[i]); + printk("regulator_enable ret=%d\n", ret); + } else if (power == 0) { + ret = regulator_disable(psensor_dev->regulators.supply[i]); + } else { + return -1; + } + if (ret) + return ret; + udelay(psensor_dev->regulators.delay_us[i]); + } + return 0; +} + +int32_t sensor_get_power(void *dev, uint32_t *ppower) +{ + return 0; +} + diff --git a/vvcam/native/sensor/sensor_common.h b/vvcam/native/sensor/sensor_common.h new file mode 100755 index 0000000..7ecbc3d --- /dev/null +++ b/vvcam/native/sensor/sensor_common.h @@ -0,0 +1,149 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _SENSOR_COMMON_H_ +#define _SENSOR_COMMON_H_ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#include "vvsensor.h" + +#define UNDEFINED_IN_DTS 0xFF + +struct vvcam_sensor_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + void *private; +}; + +struct vvcam_sensor_function_s +{ + uint8_t sensor_name[16]; + uint32_t reserve_id; + uint32_t sensor_clk; + struct sensor_mipi_info mipi_info; + + int32_t (*sensor_get_chip_id) (void *ctx, uint32_t *chip_id); + int32_t (*sensor_init) (void *ctx, struct vvcam_mode_info *pmode); + int32_t (*sensor_set_stream) (void *ctx, uint32_t status); + int32_t (*sensor_set_exp) (void *ctx, uint32_t exp_line); + int32_t (*sensor_set_vs_exp) (void *ctx, uint32_t exp_line); + int32_t (*sensor_set_gain) (void *ctx, uint32_t gain); + int32_t (*sensor_set_vs_gain) (void *ctx, uint32_t gain); + int32_t (*sensor_set_fps) (void *ctx, uint32_t fps); + int32_t (*sensor_set_resolution)(void *ctx, uint32_t width, uint32_t height); + int32_t (*sensor_set_hdr_mode) (void *ctx, uint32_t hdr_mode); + int32_t (*sensor_query) (void *ctx, struct vvcam_mode_info_array *pmode_info_arry); +}; + +#define VVCAM_SENSOR_MAX_REGULATORS 10 +struct vvcam_sensor_regulators { + struct regulator *supply[VVCAM_SENSOR_MAX_REGULATORS]; + const char *name[VVCAM_SENSOR_MAX_REGULATORS]; + unsigned int delay_us[VVCAM_SENSOR_MAX_REGULATORS]; + int num; +}; + +struct vvcam_sensor_dev { + long phy_addr; + long reg_size; + void __iomem *base; + int32_t device_idx; + + uint8_t i2c_bus; + void* i2c_client; + struct vvcam_sccb_cfg_s sensor_sccb_cfg; + struct vvcam_sccb_cfg_s focus_sccb_cfg; + struct vvcam_sensor_function_s sensor_func; + + struct vvcam_mode_info sensor_mode; + struct vvcam_ae_info_s ae_info; + const char *sensor_name; + struct vvcam_sensor_regulators regulators; + int pdn_pin; + unsigned int pdn_delay_us; + int rst_pin; +}; + +extern int32_t sensor_reset(void *dev); +extern int32_t sensor_set_clk(void *dev, uint32_t clk); +extern int32_t sensor_get_clk(void *dev, uint32_t *pclk); +extern int32_t sensor_set_power(void *dev, uint32_t power); +extern int32_t sensor_get_power(void *dev, uint32_t *ppower); + +int32_t vvcam_sensor_i2c_write(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t data); +int32_t vvcam_sensor_i2c_read(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t *pdata); + +int vvnative_sensor_init(struct vvcam_sensor_dev *dev); +int vvnative_sensor_deinit(struct vvcam_sensor_dev *dev); +long sensor_priv_ioctl(struct vvcam_sensor_dev *dev, unsigned int cmd, void __user *args); + + +#endif diff --git a/vvcam/native/sensor/sensor_ioctl.c b/vvcam/native/sensor/sensor_ioctl.c new file mode 100755 index 0000000..f055c20 --- /dev/null +++ b/vvcam/native/sensor/sensor_ioctl.c @@ -0,0 +1,708 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" + +extern struct vvcam_sensor_function_s SENSR0_FUNCTION; +extern struct vvcam_sensor_function_s SENSR1_FUNCTION; + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +static int32_t vvcam_sensor_sccb_config(struct vvcam_sensor_dev *dev, struct vvcam_sccb_cfg_s *sccb_config) +{ + dev->sensor_sccb_cfg.slave_addr = sccb_config->slave_addr; + dev->sensor_sccb_cfg.addr_byte = sccb_config->addr_byte; + dev->sensor_sccb_cfg.data_byte = sccb_config->data_byte; + return 0; +} +static int32_t vvcam_focus_sccb_config(struct vvcam_sensor_dev *dev, struct vvcam_sccb_cfg_s *sccb_config) +{ + dev->sensor_sccb_cfg.slave_addr = sccb_config->slave_addr; + dev->sensor_sccb_cfg.addr_byte = sccb_config->addr_byte; + dev->sensor_sccb_cfg.data_byte = sccb_config->data_byte; + return 0; +} + +static int vvcam_i2c_write_reg(struct i2c_client *client,unsigned int slave_address, + unsigned int reg_addr,unsigned int reg_length, + unsigned int data, unsigned int data_length) +{ + int ret; + unsigned int i; + struct i2c_msg msgs[2]; + unsigned char sendbuf[16]; + unsigned int send_len = 0; + + if (client == NULL) + return -1; + memset(msgs,0,sizeof(msgs)); + memset(sendbuf,0,sizeof(sendbuf)); + + for (i=0; i < reg_length; i++) + { + sendbuf[send_len++] = (reg_addr >> ((reg_length -1 - i)<<3)) & 0xff; + } + for (i=0; i < data_length; i++) + { + sendbuf[send_len++] = (data >> ((data_length -1 - i)<<3)) & 0xff; + } + + msgs[0].addr = slave_address; + msgs[0].flags = client->flags & I2C_M_TEN; + msgs[0].len = send_len; + msgs[0].buf = sendbuf; + + ret = i2c_transfer(client->adapter, msgs, 1); + if (ret != 1) + { + return -1; + } + //pr_info("-->%s: slave_address[0x%x] addr[0x%04x] = 0x%04x addr_byte[%d] data_byte[%d]!\n", __func__,slave_address,reg_addr,data,reg_length,data_length); + return 0; +} + +static int vvcam_i2c_read_reg(struct i2c_client *client,unsigned int slave_address, + unsigned int reg_addr,unsigned int reg_length, + unsigned char * pdata, unsigned int data_length) +{ + int ret; + unsigned int i; + struct i2c_msg msgs[2]; + unsigned char sendbuf[16]; + unsigned int send_len = 0; + unsigned char readbuf[16]; + + if (client == NULL || pdata == NULL) + return -1; + + memset(msgs,0,sizeof(msgs)); + memset(sendbuf,0,sizeof(sendbuf)); + memset(readbuf,0,sizeof(readbuf)); + + for (i=0; i < reg_length; i++) + { + sendbuf[send_len++] = (reg_addr >> ((reg_length -1 - i)<<3)) & 0xff; + } + + msgs[0].addr = slave_address; + msgs[0].flags = client->flags & I2C_M_TEN; + msgs[0].len = send_len; + msgs[0].buf = sendbuf; + + msgs[1].addr = slave_address; + msgs[1].flags = client->flags & I2C_M_TEN; + msgs[1].flags |= I2C_M_RD; + msgs[1].len = data_length; + msgs[1].buf = readbuf; + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret != 2) + { + return -1; + } + + for (i=0; i < data_length; i++) + { + pdata[i] = readbuf[data_length -1 - i]; + } + + return 0; +} + +int32_t vvcam_sensor_i2c_write(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t data) +{ + int32_t ret = 0; + struct vvcam_sccb_data; + + if((NULL == dev)) + { + return -1; + } + + ret = vvcam_i2c_write_reg(dev->i2c_client,dev->sensor_sccb_cfg.slave_addr, + address,dev->sensor_sccb_cfg.addr_byte, + data,dev->sensor_sccb_cfg.data_byte); + + return ret; +} + +int32_t vvcam_sensor_i2c_read(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t *pdata) +{ + int32_t ret = 0; + struct vvcam_sccb_data; + + if((NULL == dev)) + { + return -1; + } + + ret = vvcam_i2c_read_reg(dev->i2c_client,dev->sensor_sccb_cfg.slave_addr, + address, dev->sensor_sccb_cfg.addr_byte, + (unsigned char *)pdata, dev->sensor_sccb_cfg.data_byte); + + return ret; +} + +static int32_t vvcam_sensor_i2c_write_array(struct vvcam_sensor_dev *dev, void __user *args) +{ + int ret = 0; + int index =0; + struct vvcam_sccb_array array; + struct vvcam_sccb_data sccb_data; + + if((NULL == dev)||(NULL == args)) + { + return -1; + } + + copy_from_user(&array, args, sizeof(struct vvcam_sccb_array)); + + for (index = 0; index < array.count; index++) + { + copy_from_user(&sccb_data, &(array.sccb_data[index]), sizeof(struct vvcam_sccb_data)); + ret = vvcam_sensor_i2c_write(dev, sccb_data.addr, sccb_data.data); + if (ret != 0) + { +#if 1 + int i = 10; + while(i > 0) { + ret = vvcam_sensor_i2c_write(dev, sccb_data.addr, sccb_data.data); + if(ret == 0) { + break; + } + mdelay(10); + i--; + } +#endif + + if (ret != 0) { + printk("<0>""!!!!!!!write array error, sccb_data.addr: 0x%x, sccb_data.data: 0x%x\n", sccb_data.addr, sccb_data.data); + return ret; + } + } + } + + return 0; +} + +static int vvcam_sensor_i2c_read_array(struct vvcam_sensor_dev *dev, void __user *args) +{ + int ret = 0; + int index =0; + struct vvcam_sccb_array array; + struct vvcam_sccb_data sccb_data; + + if((NULL == dev)||(NULL == args)) + { + return -1; + } + + copy_from_user(&array, args, sizeof(struct vvcam_sccb_array)); + + for (index = 0; index < array.count; index++) + { + copy_from_user(&sccb_data, &(array.sccb_data[index]), sizeof(struct vvcam_sccb_data)); + ret = vvcam_sensor_i2c_read(dev, sccb_data.addr, &sccb_data.data); + if (ret != 0) + { + return ret; + } + copy_to_user(&(array.sccb_data[index]), &sccb_data, sizeof(struct vvcam_sccb_data)); + } + + return 0; + +} + +static int32_t vvcam_focus_i2c_write(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t data) +{ + int32_t ret = 0; + struct vvcam_sccb_data; + + if((NULL == dev)) + { + return -1; + } + + ret = vvcam_i2c_write_reg(dev->i2c_client,dev->focus_sccb_cfg.slave_addr, + address,dev->focus_sccb_cfg.addr_byte, + data,dev->focus_sccb_cfg.data_byte); + + return ret; +} + +static int32_t vvcam_focus_i2c_read(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t *pdata) +{ + int32_t ret = 0; + struct vvcam_sccb_data; + + if((NULL == dev)) + { + return -1; + } + + ret = vvcam_i2c_read_reg(dev->i2c_client,dev->focus_sccb_cfg.slave_addr, + address,dev->focus_sccb_cfg.addr_byte, + (unsigned char *)pdata,dev->focus_sccb_cfg.data_byte); + + return ret; +} + +long sensor_priv_ioctl(struct vvcam_sensor_dev *dev, unsigned int cmd, void __user *args) +{ + int ret = -1; + + if (!dev) + { + pr_err("-->%s: null point!\n", __func__); + return ret; + } + + //printk("-->%s: cmd = %d!\n", __func__,cmd); + switch (cmd) + { + case VVSENSORIOC_RESET: + { + ret = sensor_reset(dev); + break; + } + + case VVSENSORIOC_S_CLK: + { + uint32_t clk; + check_retval(copy_from_user(&clk, args, sizeof(clk))); + ret = sensor_set_clk(dev, clk); + break; + } + + case VVSENSORIOC_G_CLK: + { + uint32_t clk; + ret = sensor_get_clk(dev, &clk); + check_retval(copy_to_user(args, &clk, sizeof(clk))); + break; + } + + case VVSENSORIOC_S_POWER: + { + uint32_t power; + check_retval(copy_from_user(&power, args, sizeof(power))); + ret = sensor_set_power(dev, power); + break; + } + + case VVSENSORIOC_G_POWER: + { + uint32_t power; + ret = sensor_get_power(dev, &power); + check_retval(copy_to_user(args, &power, sizeof(power))); + break; + } + + case VVSENSORIOC_SENSOR_SCCB_CFG: + { + struct vvcam_sccb_cfg_s sccb_config; + check_retval(copy_from_user(&sccb_config, args, sizeof(sccb_config))); + ret = vvcam_sensor_sccb_config(dev,&sccb_config); + break; + } + + case VVSENSORIOC_FOCUS_SCCB_CFG: + { + struct vvcam_sccb_cfg_s sccb_config; + check_retval(copy_from_user(&sccb_config, args, sizeof(sccb_config))); + ret = vvcam_focus_sccb_config(dev,&sccb_config); + break; + } + + case VVSENSORIOC_WRITE_REG: + { + struct vvcam_sccb_data sccb_data; + check_retval(copy_from_user(&sccb_data, args, sizeof(sccb_data))); + ret = vvcam_sensor_i2c_write(dev, sccb_data.addr, sccb_data.data); + break; + } + + case VVSENSORIOC_READ_REG: + { + struct vvcam_sccb_data sccb_data; + check_retval(copy_from_user(&sccb_data, args, sizeof(sccb_data))); + ret = vvcam_sensor_i2c_read(dev, sccb_data.addr, &sccb_data.data); + check_retval(copy_to_user(args, &sccb_data, sizeof(sccb_data))); + break; + } + + case VVSENSORIOC_WRITE_ARRAY: + { + ret = vvcam_sensor_i2c_write_array(dev, args); + break; + } + + case VVSENSORIOC_READ_ARRAY: + { + ret = vvcam_sensor_i2c_read_array(dev, args); + break; + } + + case VVSENSORIOC_AF_WRITE_REG: + { + struct vvcam_sccb_data sccb_data; + check_retval(copy_from_user(&sccb_data, args, sizeof(sccb_data))); + ret = vvcam_focus_i2c_write(dev, sccb_data.addr, sccb_data.data); + break; + } + + case VVSENSORIOC_AF_READ_REG: + { + struct vvcam_sccb_data sccb_data; + check_retval(copy_from_user(&sccb_data, args, sizeof(sccb_data))); + ret = vvcam_focus_i2c_read(dev, sccb_data.addr, &sccb_data.data); + check_retval(copy_to_user(args, &sccb_data, sizeof(sccb_data))); + break; + } + + case VVSENSORIOC_G_MIPI: + { + ret = 0; + dev->sensor_func.mipi_info.sensor_data_bit = dev->sensor_mode.bit_width; + check_retval(copy_to_user(args,&(dev->sensor_func.mipi_info),sizeof(struct sensor_mipi_info))); + break; + } + + case VVSENSORIOC_G_NAME: + { + ret = 0; + check_retval(copy_to_user(args,dev->sensor_name,strlen(dev->sensor_name) + 1)); + break; + } + + case VVSENSORIOC_G_RESERVE_ID: + { + ret = 0; + check_retval(copy_to_user(args,&(dev->sensor_func.reserve_id),sizeof(uint32_t))); + break; + } + + case VVSENSORIOC_G_CHIP_ID: + { + uint32_t chip_id = 0; + if (dev->sensor_func.sensor_get_chip_id == NULL) + { + return -1; + } + ret = dev->sensor_func.sensor_get_chip_id(dev,&chip_id); + check_retval(copy_to_user(args, &chip_id, sizeof(chip_id))); + break; + } + + case VVSENSORIOC_S_INIT: + { + + struct vvcam_mode_info sensor_mode; + check_retval(copy_from_user(&sensor_mode, args, sizeof(struct vvcam_mode_info))); + if (dev->sensor_func.sensor_init == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_init(dev,&sensor_mode); + break; + } + + case VVSENSORIOC_S_STREAM: + { + uint32_t stream_status; + check_retval(copy_from_user(&stream_status, args, sizeof(stream_status))); + if (dev->sensor_func.sensor_set_stream == NULL) + { + return -1; + } + ret = dev->sensor_func.sensor_set_stream(dev, stream_status); + break; + } + + case VVSENSORIOC_S_EXP: + { + uint32_t exp_line; + check_retval(copy_from_user(&exp_line, args, sizeof(exp_line))); + + if (dev->sensor_func.sensor_set_exp == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_set_exp(dev,exp_line); + + break; + } + + case VVSENSORIOC_S_VSEXP: + { + uint32_t exp_line; + check_retval(copy_from_user(&exp_line, args, sizeof(exp_line))); + + if (dev->sensor_func.sensor_set_vs_exp == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_set_vs_exp(dev,exp_line); + + break; + } + + case VVSENSORIOC_S_GAIN: + { + uint32_t gain; + check_retval(copy_from_user(&gain, args, sizeof(gain))); + + if (dev->sensor_func.sensor_set_gain == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_set_gain(dev, gain); + + break; + } + + case VVSENSORIOC_S_VSGAIN: + { + uint32_t gain; + check_retval(copy_from_user(&gain, args, sizeof(gain))); + + if (dev->sensor_func.sensor_set_vs_gain == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_set_vs_gain(dev, gain); + break; + } + + case VVSENSORIOC_S_FPS: + { + uint32_t fps; + check_retval(copy_from_user(&fps, args, sizeof(fps))); + + if (dev->sensor_func.sensor_set_fps == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_set_fps(dev,fps); + + break; + } + + case VVSENSORIOC_G_FPS: + { + ret = 0; + check_retval(copy_to_user(args, &(dev->ae_info.cur_fps),sizeof(uint32_t))); + break; + } + + case VVSENSORIOC_S_FRAMESIZE: + { + ret = 0; + break; + } + + case VVSENSORIOC_ENUM_FRAMESIZES: + { + ret = 0; + break; + } + + case VVSENSORIOC_S_HDR_MODE: + { + uint32_t hdr_mode; + check_retval(copy_from_user(&hdr_mode, args, sizeof(hdr_mode))); + + if (dev->sensor_func.sensor_set_hdr_mode == NULL) + { + return -1; + } + ret = dev->sensor_func.sensor_set_hdr_mode(dev, hdr_mode); + + break; + } + + case VVSENSORIOC_G_HDR_MODE: + { + ret = 0; + check_retval(copy_to_user(args,&(dev->sensor_mode.hdr_mode),sizeof(uint32_t))); + break; + } + + case VVSENSORIOC_S_HDR_RADIO: + { + ret = 0; + check_retval(copy_from_user(&(dev->ae_info.hdr_radio),args,sizeof(uint32_t))); + break; + + } + + case VVSENSORIOC_G_AE_INFO: + { + ret = 0; + check_retval(copy_to_user(args,&(dev->ae_info),sizeof(struct vvcam_ae_info_s))); + break; + } + + case VVSENSORIOC_QUERY: + { + struct vvcam_mode_info_array sensor_mode_info_arry; + memset(&sensor_mode_info_arry,0,sizeof(sensor_mode_info_arry)); + + if (dev->sensor_func.sensor_query == NULL) + { + return -1; + } + ret = dev->sensor_func.sensor_query(dev, &sensor_mode_info_arry); + if (ret == 0) + { + check_retval(copy_to_user(args, &sensor_mode_info_arry, sizeof(sensor_mode_info_arry))); + } + + break; + } + + case VVSENSORIOC_G_SENSOR_MODE: + { + check_retval(copy_to_user(args, &(dev->sensor_mode), sizeof(struct vvcam_mode_info))); + break; + } + + default: + { + pr_err("unsupported command %d\n", cmd); + break; + } + + } + + return ret; +} + +static int vvcam_register_i2c_client(struct vvcam_sensor_dev *dev) +{ + struct i2c_adapter *adap; + struct i2c_board_info sensor_i2c_info = { + .type = "sensor", + .addr = dev->device_idx + 1 + }; + + adap = i2c_get_adapter(dev->i2c_bus); + if (adap == NULL) + { + pr_err("[%s]:i2c_get_adapter i2c_bus %d failed\n",__func__,dev->i2c_bus); + return -1; + } + + if (dev->i2c_bus != UNDEFINED_IN_DTS) { + strscpy(sensor_i2c_info.type, dev->sensor_name, I2C_NAME_SIZE); + } + + dev->i2c_client = i2c_new_client_device(adap, &sensor_i2c_info); + + i2c_put_adapter(adap); + + if (dev->i2c_client == NULL) + { + pr_err("[%s]:i2c_new_client_device i2c_bus %d failed\n",__func__,dev->i2c_bus); + return -1; + } + return 0; +} + +static void vvcam_unregister_i2c_client(struct vvcam_sensor_dev *dev) +{ + i2c_unregister_device(dev->i2c_client); +} + +int vvnative_sensor_init(struct vvcam_sensor_dev *dev) +{ + int ret = 0; + + if (dev->i2c_bus == UNDEFINED_IN_DTS) { + dev->sensor_sccb_cfg.addr_byte = 2; + dev->sensor_sccb_cfg.data_byte = 1; + } + + ret = vvcam_register_i2c_client(dev); + if (ret != 0) { + pr_err("[%s]: vvcam_register_i2c_client sensor_idx = %d failed\n",__func__, dev->device_idx); + return -1; + } + + return ret; +} + +int vvnative_sensor_deinit(struct vvcam_sensor_dev *dev) +{ + int ret = 0; + + vvcam_unregister_i2c_client(dev); + + return ret; +} diff --git a/vvcam/native/sensor/sony_imx290/imx290_driver.c b/vvcam/native/sensor/sony_imx290/imx290_driver.c new file mode 100755 index 0000000..e26db3e --- /dev/null +++ b/vvcam/native/sensor/sony_imx290/imx290_driver.c @@ -0,0 +1,494 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "imx290_reg_cfg.h" + +#define SENSOR_CLK 74250000 + +static struct vvcam_mode_info pimx290_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_array *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pimx290_mode_info); + + memcpy(pmode_info_arry->modes,pimx290_mode_info,sizeof(pimx290_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pimx290_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pimx290_mode_info[i].index == pmode->index) + { + psensor_mode = &(pimx290_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&imx290_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&imx290_mipi4lane_1080p_30fps_linear_arry); + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3002, 0x00); + ret = sensor_write_reg(ctx, 0x3000, 0x00); + }else + { + ret = sensor_write_reg(ctx, 0x3000, 0x01); + ret = sensor_write_reg(ctx, 0x3002, 0x01); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + // ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + // ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s imx290_function = +{ + .sensor_name = "imx290", + .reserve_id = 0x290, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam/native/sensor/sony_imx290/imx290_driver.h b/vvcam/native/sensor/sony_imx290/imx290_driver.h new file mode 100755 index 0000000..89d7626 --- /dev/null +++ b/vvcam/native/sensor/sony_imx290/imx290_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OMNIVISION_IMX290_H_ +#define _OMNIVISION_IMX290_H_ + +extern struct vvcam_sensor_function_s imx290_function; + + +#endif diff --git a/vvcam/native/sensor/sony_imx290/imx290_mipi4lane_1080p_30fps_linear.c b/vvcam/native/sensor/sony_imx290/imx290_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..8f846b0 --- /dev/null +++ b/vvcam/native/sensor/sony_imx290/imx290_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data imx290_mipi4lane_1080p_30fps_linear_reg[] = { + +{0x3000, 0x01}, +{0x3001, 0x00}, +{0x3002, 0x01}, +{0x3003, 0x00}, +{0x300C, 0x3B}, +{0x300D, 0x2A}, +{0x3030, 0xc4}, +{0x3031, 0x1c}, +{0x3034, 0xEC}, +{0x3035, 0x0a}, +{0x3058, 0x72}, +{0x3059, 0x06}, +{0x30E8, 0x14}, +{0x314C, 0x29}, +{0x314D, 0x01}, +{0x315A, 0x03}, +{0x3168, 0xA0}, +{0x316A, 0x7E}, +{0x31A1, 0x00}, +{0x3288, 0x21}, +{0x328A, 0x02}, +{0x3414, 0x05}, +{0x3416, 0x18}, +{0x35AC, 0x0E}, +{0x3648, 0x01}, +{0x364A, 0x04}, +{0x364C, 0x04}, +{0x3678, 0x01}, +{0x367C, 0x31}, +{0x367E, 0x31}, +{0x3708, 0x02}, +{0x3714, 0x01}, +{0x3715, 0x02}, +{0x3716, 0x02}, +{0x3717, 0x02}, +{0x371C, 0x3D}, +{0x371D, 0x3F}, +{0x372C, 0x00}, +{0x372D, 0x00}, +{0x372E, 0x46}, +{0x372F, 0x00}, +{0x3730, 0x89}, +{0x3731, 0x00}, +{0x3732, 0x08}, +{0x3733, 0x01}, +{0x3734, 0xFE}, +{0x3735, 0x05}, +{0x375D, 0x00}, +{0x375E, 0x00}, +{0x375F, 0x61}, +{0x3760, 0x06}, +{0x3768, 0x1B}, +{0x3769, 0x1B}, +{0x376A, 0x1A}, +{0x376B, 0x19}, +{0x376C, 0x18}, +{0x376D, 0x14}, +{0x376E, 0x0F}, +{0x3776, 0x00}, +{0x3777, 0x00}, +{0x3778, 0x46}, +{0x3779, 0x00}, +{0x377A, 0x08}, +{0x377B, 0x01}, +{0x377C, 0x45}, +{0x377D, 0x01}, +{0x377E, 0x23}, +{0x377F, 0x02}, +{0x3780, 0xD9}, +{0x3781, 0x03}, +{0x3782, 0xF5}, +{0x3783, 0x06}, +{0x3784, 0xA5}, +{0x3788, 0x0F}, +{0x378A, 0xD9}, +{0x378B, 0x03}, +{0x378C, 0xEB}, +{0x378D, 0x05}, +{0x378E, 0x87}, +{0x378F, 0x06}, +{0x3790, 0xF5}, +{0x3792, 0x43}, +{0x3794, 0x7A}, +{0x3796, 0xA1}, +{0x3E04, 0x0E}, +}; + +struct vvcam_sccb_array imx290_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(imx290_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = imx290_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam/native/sensor/sony_imx290/imx290_reg_cfg.h b/vvcam/native/sensor/sony_imx290/imx290_reg_cfg.h new file mode 100755 index 0000000..6f22812 --- /dev/null +++ b/vvcam/native/sensor/sony_imx290/imx290_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _IMX290_REG_CFG_H_ +#define _IMX290_REG_CFG_H_ + +extern struct vvcam_sccb_array imx290_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam/native/sensor/sony_imx327/imx327_driver.c b/vvcam/native/sensor/sony_imx327/imx327_driver.c new file mode 100755 index 0000000..c6369fa --- /dev/null +++ b/vvcam/native/sensor/sony_imx327/imx327_driver.c @@ -0,0 +1,449 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "imx327_reg_cfg.h" + +#define SENSOR_CLK 37125000 + +static struct vvcam_mode_info pimx327_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_arry *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pimx327_mode_info); + + memcpy(pmode_info_arry->modes,pimx327_mode_info,sizeof(pimx327_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + //ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + //ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + //*chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pimx327_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pimx327_mode_info[i].index == pmode->index) + { + psensor_mode = &(pimx327_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&imx327_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.MaxFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.MaxFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.interrgation_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&imx327_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.MaxFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.MaxFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.interrgation_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3002, 0x00); + ret = sensor_write_reg(ctx, 0x3000, 0x00); + }else + { + ret = sensor_write_reg(ctx, 0x3000, 0x01); + ret = sensor_write_reg(ctx, 0x3002, 0x01); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + //ret = sensor_write_reg(ctx, 0x3467, 0x00); + //ret |= sensor_write_reg(ctx, 0x3464, 0x04); +// ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + //ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + //ret |= sensor_write_reg(ctx, 0x3464, 0x14); + //ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + //ret = sensor_write_reg(ctx, 0x3467, 0x00); + //ret |= sensor_write_reg(ctx, 0x3464, 0x04); + //ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + //ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + //ret |= sensor_write_reg(ctx, 0x3464, 0x14); + //ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + // ret = sensor_write_reg(ctx, 0x3467, 0x00); + /// ret |= sensor_write_reg(ctx, 0x3464, 0x04); + // ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + // ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + // ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + // ret |= sensor_write_reg(ctx, 0x3464, 0x14); + // ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + // hcg_gain = gain * hdr_radio / 11; + // sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + // lcg_gain = gain; + /// sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + +// ret = sensor_read_reg(ctx, 0x30bb, ®_val); +// reg_val &= ~0x0f; +/// reg_val |= (lcg_again<<2)&0x03; +/// reg_val |= hcg_again & 0x03; +/// +/// ret = sensor_write_reg(ctx, 0x3467, 0x00); +// ret |= sensor_write_reg(ctx, 0x3464, 0x04); +// +// ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); +// ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); +// +// ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); +// ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); +// +/// ret |= sensor_write_reg(ctx, 0x30bb, reg_val); +// ret |= sensor_write_reg(ctx, 0x3464, 0x14); +// ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + +// reg_val &= ~0x30; +// reg_val |= (again & 0x03) << 4; +// ret = sensor_write_reg(ctx, 0x3467, 0x00); +// ret |= sensor_write_reg(ctx, 0x3464, 0x04); +/// ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); +// ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); +// ret |= sensor_write_reg(ctx, 0x30bb, reg_val); +// ret |= sensor_write_reg(ctx, 0x3464, 0x14); +// ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.MaxFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { +// ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); +// ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + // ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + // ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s imx327_function = +{ + .sensor_name = "imx327", + .reserve_id = 0x327, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam/native/sensor/sony_imx327/imx327_driver.h b/vvcam/native/sensor/sony_imx327/imx327_driver.h new file mode 100755 index 0000000..d2c7016 --- /dev/null +++ b/vvcam/native/sensor/sony_imx327/imx327_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _SONY_IMX327_H_ +#define _SONY_IMX327_H_ + +extern struct vvcam_sensor_function_s imx327_function; + + +#endif diff --git a/vvcam/native/sensor/sony_imx327/imx327_mipi4lane_1080p_30fps_linear.c b/vvcam/native/sensor/sony_imx327/imx327_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..b47475b --- /dev/null +++ b/vvcam/native/sensor/sony_imx327/imx327_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data imx327_mipi4lane_1080p_30fps_linear_reg[] = { + +{0x3000, 0x01}, +{0x3001, 0x00}, +{0x3002, 0x01}, +{0x3003, 0x00}, +{0x300C, 0x3B}, +{0x300D, 0x2A}, +{0x3030, 0xc4}, +{0x3031, 0x1c}, +{0x3034, 0xEC}, +{0x3035, 0x0a}, +{0x3058, 0x72}, +{0x3059, 0x06}, +{0x30E8, 0x14}, +{0x314C, 0x29}, +{0x314D, 0x01}, +{0x315A, 0x03}, +{0x3168, 0xA0}, +{0x316A, 0x7E}, +{0x31A1, 0x00}, +{0x3288, 0x21}, +{0x328A, 0x02}, +{0x3414, 0x05}, +{0x3416, 0x18}, +{0x35AC, 0x0E}, +{0x3648, 0x01}, +{0x364A, 0x04}, +{0x364C, 0x04}, +{0x3678, 0x01}, +{0x367C, 0x31}, +{0x367E, 0x31}, +{0x3708, 0x02}, +{0x3714, 0x01}, +{0x3715, 0x02}, +{0x3716, 0x02}, +{0x3717, 0x02}, +{0x371C, 0x3D}, +{0x371D, 0x3F}, +{0x372C, 0x00}, +{0x372D, 0x00}, +{0x372E, 0x46}, +{0x372F, 0x00}, +{0x3730, 0x89}, +{0x3731, 0x00}, +{0x3732, 0x08}, +{0x3733, 0x01}, +{0x3734, 0xFE}, +{0x3735, 0x05}, +{0x375D, 0x00}, +{0x375E, 0x00}, +{0x375F, 0x61}, +{0x3760, 0x06}, +{0x3768, 0x1B}, +{0x3769, 0x1B}, +{0x376A, 0x1A}, +{0x376B, 0x19}, +{0x376C, 0x18}, +{0x376D, 0x14}, +{0x376E, 0x0F}, +{0x3776, 0x00}, +{0x3777, 0x00}, +{0x3778, 0x46}, +{0x3779, 0x00}, +{0x377A, 0x08}, +{0x377B, 0x01}, +{0x377C, 0x45}, +{0x377D, 0x01}, +{0x377E, 0x23}, +{0x377F, 0x02}, +{0x3780, 0xD9}, +{0x3781, 0x03}, +{0x3782, 0xF5}, +{0x3783, 0x06}, +{0x3784, 0xA5}, +{0x3788, 0x0F}, +{0x378A, 0xD9}, +{0x378B, 0x03}, +{0x378C, 0xEB}, +{0x378D, 0x05}, +{0x378E, 0x87}, +{0x378F, 0x06}, +{0x3790, 0xF5}, +{0x3792, 0x43}, +{0x3794, 0x7A}, +{0x3796, 0xA1}, +{0x3E04, 0x0E}, +}; + +struct vvcam_sccb_array imx327_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(imx327_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = imx327_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam/native/sensor/sony_imx327/imx327_reg_cfg.h b/vvcam/native/sensor/sony_imx327/imx327_reg_cfg.h new file mode 100755 index 0000000..1cf0c67 --- /dev/null +++ b/vvcam/native/sensor/sony_imx327/imx327_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _IMX327_REG_CFG_H_ +#define _IMX327_REG_CFG_H_ + +extern struct vvcam_sccb_array imx327_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam/native/sensor/sony_imx334/imx334_driver.c b/vvcam/native/sensor/sony_imx334/imx334_driver.c new file mode 100755 index 0000000..f78965e --- /dev/null +++ b/vvcam/native/sensor/sony_imx334/imx334_driver.c @@ -0,0 +1,494 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "imx334_reg_cfg.h" + +#define SENSOR_CLK 74250000 + +static struct vvcam_mode_info pimx334_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_array *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pimx334_mode_info); + + memcpy(pmode_info_arry->modes,pimx334_mode_info,sizeof(pimx334_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pimx334_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pimx334_mode_info[i].index == pmode->index) + { + psensor_mode = &(pimx334_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&imx334_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&imx334_mipi4lane_1080p_30fps_linear_arry); + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3002, 0x00); + ret = sensor_write_reg(ctx, 0x3000, 0x00); + }else + { + ret = sensor_write_reg(ctx, 0x3000, 0x01); + ret = sensor_write_reg(ctx, 0x3002, 0x01); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + // ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + // ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s imx334_function = +{ + .sensor_name = "imx334", + .reserve_id = 0x334, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam/native/sensor/sony_imx334/imx334_driver.h b/vvcam/native/sensor/sony_imx334/imx334_driver.h new file mode 100755 index 0000000..104f95f --- /dev/null +++ b/vvcam/native/sensor/sony_imx334/imx334_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OMNIVISION_IMX334_H_ +#define _OMNIVISION_IMX334_H_ + +extern struct vvcam_sensor_function_s imx334_function; + + +#endif diff --git a/vvcam/native/sensor/sony_imx334/imx334_mipi4lane_1080p_30fps_linear.c b/vvcam/native/sensor/sony_imx334/imx334_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..c4ed859 --- /dev/null +++ b/vvcam/native/sensor/sony_imx334/imx334_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data imx334_mipi4lane_1080p_30fps_linear_reg[] = { + +{0x3000, 0x01}, +{0x3001, 0x00}, +{0x3002, 0x01}, +{0x3003, 0x00}, +{0x300C, 0x3B}, +{0x300D, 0x2A}, +{0x3030, 0xc4}, +{0x3031, 0x1c}, +{0x3034, 0xEC}, +{0x3035, 0x0a}, +{0x3058, 0x72}, +{0x3059, 0x06}, +{0x30E8, 0x14}, +{0x314C, 0x29}, +{0x314D, 0x01}, +{0x315A, 0x03}, +{0x3168, 0xA0}, +{0x316A, 0x7E}, +{0x31A1, 0x00}, +{0x3288, 0x21}, +{0x328A, 0x02}, +{0x3414, 0x05}, +{0x3416, 0x18}, +{0x35AC, 0x0E}, +{0x3648, 0x01}, +{0x364A, 0x04}, +{0x364C, 0x04}, +{0x3678, 0x01}, +{0x367C, 0x31}, +{0x367E, 0x31}, +{0x3708, 0x02}, +{0x3714, 0x01}, +{0x3715, 0x02}, +{0x3716, 0x02}, +{0x3717, 0x02}, +{0x371C, 0x3D}, +{0x371D, 0x3F}, +{0x372C, 0x00}, +{0x372D, 0x00}, +{0x372E, 0x46}, +{0x372F, 0x00}, +{0x3730, 0x89}, +{0x3731, 0x00}, +{0x3732, 0x08}, +{0x3733, 0x01}, +{0x3734, 0xFE}, +{0x3735, 0x05}, +{0x375D, 0x00}, +{0x375E, 0x00}, +{0x375F, 0x61}, +{0x3760, 0x06}, +{0x3768, 0x1B}, +{0x3769, 0x1B}, +{0x376A, 0x1A}, +{0x376B, 0x19}, +{0x376C, 0x18}, +{0x376D, 0x14}, +{0x376E, 0x0F}, +{0x3776, 0x00}, +{0x3777, 0x00}, +{0x3778, 0x46}, +{0x3779, 0x00}, +{0x377A, 0x08}, +{0x377B, 0x01}, +{0x377C, 0x45}, +{0x377D, 0x01}, +{0x377E, 0x23}, +{0x377F, 0x02}, +{0x3780, 0xD9}, +{0x3781, 0x03}, +{0x3782, 0xF5}, +{0x3783, 0x06}, +{0x3784, 0xA5}, +{0x3788, 0x0F}, +{0x378A, 0xD9}, +{0x378B, 0x03}, +{0x378C, 0xEB}, +{0x378D, 0x05}, +{0x378E, 0x87}, +{0x378F, 0x06}, +{0x3790, 0xF5}, +{0x3792, 0x43}, +{0x3794, 0x7A}, +{0x3796, 0xA1}, +{0x3E04, 0x0E}, +}; + +struct vvcam_sccb_array imx334_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(imx334_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = imx334_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam/native/sensor/sony_imx334/imx334_reg_cfg.h b/vvcam/native/sensor/sony_imx334/imx334_reg_cfg.h new file mode 100755 index 0000000..8cdf80f --- /dev/null +++ b/vvcam/native/sensor/sony_imx334/imx334_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _IMX334_REG_CFG_H_ +#define _IMX334_REG_CFG_H_ + +extern struct vvcam_sccb_array imx334_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam/native/sensor/vvcam_sensor_driver.c b/vvcam/native/sensor/vvcam_sensor_driver.c new file mode 100755 index 0000000..4a92cd7 --- /dev/null +++ b/vvcam/native/sensor/vvcam_sensor_driver.c @@ -0,0 +1,452 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vvsensor.h" +#include "sensor_common.h" + +#define VIVCAM_SENSOR_NAME "vivcam" +#define VIVCAM_SENSOR_MAXCNT 30 + +static unsigned int vvcam_sensor_major = 0; +static unsigned int vvcam_sensor_minor = 0; +struct class *vvcam_sensor_class; +static unsigned int devise_register_index = 0; + + +static int vvcam_sensor_open(struct inode * inode, struct file * file) +{ + struct vvcam_sensor_driver_dev *pdriver_dev; + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_sensor_driver_dev, cdev); + file->private_data = pdriver_dev; + + return 0; +}; + +static long vvcam_sensor_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vvcam_sensor_driver_dev *pdriver_dev; + struct vvcam_sensor_dev * psensor_dev; + + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + psensor_dev = pdriver_dev->private; + //pr_info("%s:pdriver_dev =0x%px\n", __func__,pdriver_dev); + //pr_info("%s:sensor[%d] psensor_dev =0x%px\n", __func__,psensor_dev->device_idx,psensor_dev); + + mutex_lock(&pdriver_dev->vvmutex); + ret = sensor_priv_ioctl(psensor_dev, cmd ,(void __user *)arg); + mutex_unlock(&pdriver_dev->vvmutex); + + return ret; +}; + +static int vvcam_sensor_release(struct inode * inode, struct file * file) +{ + return 0; +}; + +struct file_operations vvcam_sensor_fops = { + .owner = THIS_MODULE, + .open = vvcam_sensor_open, + .release = vvcam_sensor_release, + .unlocked_ioctl = vvcam_sensor_ioctl, +}; + +static int vvcam_sensor_of_parse(struct platform_device *pdev) +{ + int ret = 0, regulator_num = 0; + struct device_node *np = pdev->dev.of_node; + struct vvcam_sensor_driver_dev *pdriver_dev = platform_get_drvdata(pdev); + struct vvcam_sensor_dev * psensor_dev = pdriver_dev->private; + + ret = of_property_read_string(np, "sensor_name", &psensor_dev->sensor_name); + if (ret < 0) { + pr_err("%s:property sensor_name not defined for %s\n", __func__, pdev->name); + return ret; + } + psensor_dev->regulators.num = of_property_count_strings(np, "sensor_regulators"); + if (psensor_dev->regulators.num <= 0) { + pr_err("%s:property sensor_regulators not defined for %s\n", __func__, pdev->name); + } else { + pr_info("%s num_of_regulators %d\n", __func__, psensor_dev->regulators.num); + ret = of_property_read_string_array(np, "sensor_regulators", + psensor_dev->regulators.name, psensor_dev->regulators.num); + if (ret != psensor_dev->regulators.num) { + pr_err("%s:fail to read property sensor_regulators\n", __func__); + return -1; + }; + ret = of_property_read_u32_array(np, "sensor_regulator_timing_us", + psensor_dev->regulators.delay_us, psensor_dev->regulators.num); + if (ret != 0) { + pr_err("%s:fail to read property sensor_regulator_timing_us\n", __func__); + return ret; + } + regulator_num = psensor_dev->regulators.num; + while (regulator_num) { + pr_info("%s regulator %s delay %d\n", psensor_dev->sensor_name, psensor_dev->regulators.name[regulator_num - 1], + psensor_dev->regulators.delay_us[regulator_num - 1]); + psensor_dev->regulators.supply[regulator_num - 1] = devm_regulator_get(&pdev->dev, + psensor_dev->regulators.name[regulator_num - 1]); + if (IS_ERR(psensor_dev->regulators.supply[regulator_num - 1])) { + pr_err("%s:fail to devm_regulator_get %s\n", __func__, psensor_dev->regulators.name[regulator_num - 1]); + return -1; + } + regulator_num--; + } + } + + psensor_dev->pdn_pin = of_get_named_gpio(np, "sensor_pdn", 0); + if (psensor_dev->pdn_pin >= 0) { + ret = devm_gpio_request(&pdev->dev, psensor_dev->pdn_pin, + "sensor_pdn"); + if (ret < 0) { + pr_err("%s:sensor_pdn request failed\n", __func__); + } + } else { + pr_err("sensor_pdn not defined for %s\n", psensor_dev->sensor_name); + } + + ret = of_property_read_u32(np, "sensor_pdn_delay_us", + &psensor_dev->pdn_delay_us); + if (ret != 0) { + pr_err("fail to read property sensor_pdn_delay_us, assume zero\n"); + } + + psensor_dev->rst_pin = of_get_named_gpio(np, "sensor_rst", 0); + if (psensor_dev->rst_pin >= 0) { + ret = devm_gpio_request(&pdev->dev, psensor_dev->rst_pin, + "sensor_rst"); + if (ret < 0) { + pr_err("%s:sensor_rst request failed\n", __func__); + } + } else { + pr_err("sensor_rst not defined for %s\n", psensor_dev->sensor_name); + } + + ret = of_property_read_u8(np, "i2c_addr", + &psensor_dev->sensor_sccb_cfg.slave_addr); + if (ret != 0) { + pr_err("fail to read property i2c_addr, refer to %s.c\n", psensor_dev->sensor_name); + } + ret = of_property_read_u8(np, "i2c_reg_width", + &psensor_dev->sensor_sccb_cfg.addr_byte); + if (ret != 0) { + pr_err("fail to read property i2c_reg_width, refer to %s.c\n", psensor_dev->sensor_name); + } + ret = of_property_read_u8(np, "i2c_data_width", + &psensor_dev->sensor_sccb_cfg.data_byte); + if (ret != 0) { + pr_err("fail to read property i2c_data_width, refer to %s.c\n", psensor_dev->sensor_name); + } + ret = of_property_read_u8(np, "i2c_bus", + &psensor_dev->i2c_bus); + if (ret != 0) { + pr_err("fail to read property i2c_bus, refer to %s.c\n", psensor_dev->sensor_name); + psensor_dev->i2c_bus = UNDEFINED_IN_DTS; + return -1; + } + + return 0; +} + +static int vvcam_sensor_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vvcam_sensor_driver_dev *pdriver_dev; + struct vvcam_sensor_dev * psensor_dev; + struct device_node *np = pdev->dev.of_node; + + pr_info("enter %s\n", __func__); + + pdev->id = of_alias_get_id(np, "vivcam"); + + if (pdev->id >= VIVCAM_SENSOR_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_sensor_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_sensor_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_sensor_driver_dev )); + pr_info("%s:sensor[%d]: pdriver_dev =0x%px\n", __func__,pdev->id,pdriver_dev); + + psensor_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_sensor_dev), GFP_KERNEL); + if (psensor_dev == NULL) + { + pr_err("%s:alloc struct vvcam_sensor_dev error\n", __func__); + return -ENOMEM; + } + memset(psensor_dev,0,sizeof(struct vvcam_sensor_dev )); + pr_info("%s:sensor[%d]: psensor_dev =0x%px\n", __func__,pdev->id,psensor_dev); + psensor_dev->device_idx = pdev->id; + + pdriver_dev->private = psensor_dev; + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + + ret = vvcam_sensor_of_parse(pdev); + if (ret < 0) + { + pr_err("%s:vvcam_sensor_of_parse error\n", __func__); + return ret; + } + + ret = vvnative_sensor_init(psensor_dev); + if (ret != 0) + { + pr_err("%s:vvnative_sensor_init error\n", __func__); + return -EIO; + } + + if (devise_register_index == 0) + { + if (vvcam_sensor_major == 0) + { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_SENSOR_MAXCNT, VIVCAM_SENSOR_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_sensor_major = MAJOR(pdriver_dev->devt); + vvcam_sensor_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_sensor_major, vvcam_sensor_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_SENSOR_MAXCNT, VIVCAM_SENSOR_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + vvcam_sensor_class = class_create(THIS_MODULE, VIVCAM_SENSOR_NAME); + if (IS_ERR(vvcam_sensor_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_sensor_major, vvcam_sensor_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_sensor_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_sensor_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VIVCAM_SENSOR_NAME, pdev->id); + + extern int sensor_create_capabilities_sysfs(struct platform_device *pdev); + sensor_create_capabilities_sysfs(pdev); + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int vvcam_sensor_remove(struct platform_device *pdev) +{ + struct vvcam_sensor_driver_dev *pdriver_dev; + struct vvcam_sensor_dev * psensor_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + psensor_dev = pdriver_dev->private; + vvnative_sensor_deinit(psensor_dev); + + extern int sensor_remove_capabilities_sysfs(struct platform_device *pdev); + sensor_remove_capabilities_sysfs(pdev); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_SENSOR_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + + devm_kfree(&pdev->dev, pdriver_dev); + devm_kfree(&pdev->dev, psensor_dev); + + + return 0; +} + +static const struct of_device_id vvcam_sensor_of_match[] = { + {.compatible = "thead,light-vvcam-sensor"}, +}; + +static struct platform_driver vvcam_sensor_driver = { + .probe = vvcam_sensor_probe, + .remove = vvcam_sensor_remove, + .driver = { + .name = VIVCAM_SENSOR_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(vvcam_sensor_of_match), + } +}; + +static void vvcam_sensor_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +#if 0//def WITH_VVCAM +static struct platform_device vvcam_sensor_pdev = { + .name = VIVCAM_SENSOR_NAME, + .id = 0, + .dev.release = vvcam_sensor_pdev_release, +}; +#endif + +#if 0//def WITH_VVCAM_DUAL +static struct platform_device vvcam_sensor_dual_pdev = { + .name = VIVCAM_SENSOR_NAME, + .id = 1, + .dev.release = vvcam_sensor_pdev_release, +}; +#endif + +static int __init vvcam_sensor_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + +#if 0//def WITH_VVCAM + ret = platform_device_register(&vvcam_sensor_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } +#endif + +#if 0//def WITH_VVCAM_DUAL + ret = platform_device_register(&vvcam_sensor_dual_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } +#endif + + ret = platform_driver_register(&vvcam_sensor_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit vvcam_sensor_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_sensor_driver); + +#if 0//def WITH_VVCAM + platform_device_unregister(&vvcam_sensor_pdev); +#endif + +#if 0//def WITH_VVCAM_DUAL + platform_device_unregister(&vvcam_sensor_dual_pdev); +#endif + +} + +module_init(vvcam_sensor_init_module); +module_exit(vvcam_sensor_exit_module); + +MODULE_DESCRIPTION("SENSOR"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/sensor/vvcam_sensor_sysfs.c b/vvcam/native/sensor/vvcam_sensor_sysfs.c new file mode 100755 index 0000000..a1e1178 --- /dev/null +++ b/vvcam/native/sensor/vvcam_sensor_sysfs.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY controller driver. + * SysFS components for the platform driver + * + * Author: Luis Oliveira + */ + + +#include "sensor_common.h" + +static ssize_t cam_info_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct vvcam_sensor_driver_dev *pdriver_dev; + struct vvcam_sensor_dev * psensor_dev; + char buffer[15]; + + pdriver_dev = platform_get_drvdata(pdev); + psensor_dev = (struct vvcam_sensor_dev *)pdriver_dev->private; + + printk("<0>""sensor name: %s\n", psensor_dev->sensor_func.sensor_name); + snprintf(buffer, + sizeof(buffer), + "i2c id is :%d\n", psensor_dev->i2c_bus); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static DEVICE_ATTR_RO(cam_info); + +int sensor_create_capabilities_sysfs(struct platform_device *pdev) +{ + device_create_file(&pdev->dev, &dev_attr_cam_info); + return 0; +} + +int sensor_remove_capabilities_sysfs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_cam_info); + return 0; +} diff --git a/vvcam/native/soc/Makefile b/vvcam/native/soc/Makefile new file mode 100755 index 0000000..122a899 --- /dev/null +++ b/vvcam/native/soc/Makefile @@ -0,0 +1,20 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_soc + +obj-m +=$(TARGET).o +$(TARGET)-objs += vvcam_soc_driver.o +$(TARGET)-objs += soc_ioctl.o +$(TARGET)-objs += vivsoc_hub.o +$(TARGET)-objs += vsi_core_gen6.o + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam/native/soc/soc_ioctl.c b/vvcam/native/soc/soc_ioctl.c new file mode 100755 index 0000000..0efe1a3 --- /dev/null +++ b/vvcam/native/soc/soc_ioctl.c @@ -0,0 +1,266 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef __KERNEL__ +#include +#include +#include +#include + +#define pr_info printf +#define pr_err printf +#define copy_from_user(a, b, c) soc_copy_data(a, b, c) +#define copy_to_user(a, b, c) soc_copy_data(a, b, c) +#define __user +#define __iomem + +void soc_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); +} + +#else // __KERNEL__ +#include /* Module support */ +#include + +#endif + +#include "soc_ioctl.h" +#include "vivsoc_hub.h" + + +long soc_priv_ioctl(struct vvcam_soc_dev *dev, unsigned int cmd, void __user *args) +{ + int ret = -1; + struct soc_control_context soc_ctrl; + if (!dev) { + return ret; + } + + switch (cmd) { + /* ISP part */ + case VVSOC_IOC_S_RESET_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* DWE part */ + case VVSOC_IOC_S_RESET_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* VSE part */ + case VVSOC_IOC_S_RESET_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + + /* CSI part */ + case VVSOC_IOC_S_RESET_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* sensor part */ + case VVSOC_IOC_S_RESET_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /*ry part*/ + case VVSOC_IOC_S_RESET_ISP_RY: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_ry_reset(dev, &soc_ctrl); + break; + + default: + pr_err("unsupported command %d", cmd); + break; + } + + return ret; +} + +extern struct vvcam_soc_function_s gen6_soc_function; + +int vvnative_soc_init(struct vvcam_soc_dev *dev) +{ + if (dev == NULL) + { + pr_err("[%s] dev is NULL\n", __func__); + return -1; + } + + vivsoc_register_hardware(dev, &gen6_soc_function); + return 0; +} + +int vvnative_soc_deinit(struct vvcam_soc_dev *dev) +{ + return 0; +} + + diff --git a/vvcam/native/soc/soc_ioctl.h b/vvcam/native/soc/soc_ioctl.h new file mode 100755 index 0000000..bbe8de7 --- /dev/null +++ b/vvcam/native/soc/soc_ioctl.h @@ -0,0 +1,159 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _SOC_IOC_H_ +#define _SOC_IOC_H_ + +#ifndef __KERNEL__ +#include +#endif + +#include + +enum { + VVSOC_IOC_S_RESET_ISP = _IO('r', 0), + VVSOC_IOC_S_POWER_ISP, + VVSOC_IOC_G_POWER_ISP, + VVSOC_IOC_S_CLOCK_ISP, + VVSOC_IOC_G_CLOCK_ISP, + + VVSOC_IOC_S_RESET_DWE, + VVSOC_IOC_S_POWER_DWE, + VVSOC_IOC_G_POWER_DWE, + VVSOC_IOC_S_CLOCK_DWE, + VVSOC_IOC_G_CLOCK_DWE, + + VVSOC_IOC_S_RESET_VSE, + VVSOC_IOC_S_POWER_VSE, + VVSOC_IOC_G_POWER_VSE, + VVSOC_IOC_S_CLOCK_VSE, + VVSOC_IOC_G_CLOCK_VSE, + + VVSOC_IOC_S_RESET_CSI, + VVSOC_IOC_S_POWER_CSI, + VVSOC_IOC_G_POWER_CSI, + VVSOC_IOC_S_CLOCK_CSI, + VVSOC_IOC_G_CLOCK_CSI, + + VVSOC_IOC_S_RESET_SENSOR, + VVSOC_IOC_S_POWER_SENSOR, + VVSOC_IOC_G_POWER_SENSOR, + VVSOC_IOC_S_CLOCK_SENSOR, + VVSOC_IOC_G_CLOCK_SENSOR, + + VVSOC_IOC_S_RESET_ISP_RY, + VVSOC_IOC_S_POWER_ISP_RY, + VVSOC_IOC_G_POWER_ISP_RY, + VVSOC_IOC_S_CLOCK_ISP_RY, + VVSOC_IOC_G_CLOCK_ISP_RY, + + VVSOC_IOC_MAX, +}; + +struct soc_control_context { + uint32_t device_idx; + uint32_t control_value; +}; + +struct vvcam_soc_func_s +{ + int (*set_power)(void*,unsigned int,unsigned int); + int (*get_power)(void*,unsigned int,unsigned int *); + int (*set_reset)(void*,unsigned int,unsigned int); + int (*set_clk)(void*,unsigned int,unsigned int); + int (*get_clk)(void*,unsigned int,unsigned int *); +}; + +struct vvcam_soc_function_s +{ + struct vvcam_soc_func_s isp_func; + struct vvcam_soc_func_s dwe_func; + struct vvcam_soc_func_s vse_func; + struct vvcam_soc_func_s csi_func; + struct vvcam_soc_func_s sensor_func; + struct vvcam_soc_func_s isp_ry_func; +}; + +struct vvcam_soc_access_s +{ + int (*write)(void * ctx, uint32_t address, uint32_t data); + int (*read)(void * ctx, uint32_t address, uint32_t *data); +}; + + +#ifdef __KERNEL__ + +struct vvcam_soc_dev { + void __iomem *base; + struct soc_control_context isp0; + struct soc_control_context isp1; + struct soc_control_context dwe; + struct soc_control_context vse; + struct vvcam_soc_function_s soc_func; + struct vvcam_soc_access_s soc_access; + void * csi_private; +}; +// internal functions + +long soc_priv_ioctl(struct vvcam_soc_dev *dev, unsigned int cmd, void __user *args); +int vvnative_soc_init(struct vvcam_soc_dev *dev); +int vvnative_soc_deinit(struct vvcam_soc_dev *dev); + + + +#else +//User space connections + + +#endif + +#endif // _SOC_IOC_H_ diff --git a/vvcam/native/soc/vivsoc_hub.c b/vvcam/native/soc/vivsoc_hub.c new file mode 100755 index 0000000..082198c --- /dev/null +++ b/vvcam/native/soc/vivsoc_hub.c @@ -0,0 +1,604 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include + +#include "soc_ioctl.h" +#include "vivsoc_hub.h" +#include "vsi_core_gen6.h" + + +int vivsoc_hub_isp_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_ry_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_ry_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_ry_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_vse_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_csi_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +unsigned int vivsoc_register_hardware(struct vvcam_soc_dev *dev, struct vvcam_soc_function_s *func) +{ + if (func == NULL) + { + return -1; + } + + memcpy(&dev->soc_func,func,sizeof(struct vvcam_soc_function_s)); + + dev->soc_access.write = gen6_write_reg; + dev->soc_access.read = gen6_read_reg; + + return 0; +} + + + + diff --git a/vvcam/native/soc/vivsoc_hub.h b/vvcam/native/soc/vivsoc_hub.h new file mode 100755 index 0000000..27442bb --- /dev/null +++ b/vvcam/native/soc/vivsoc_hub.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VIVSOC_HUB_H_ +#define _VIVSOC_HUB_H_ + +int vivsoc_hub_isp_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_dwe_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_vse_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_csi_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_sensor_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_isp_ry_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_ry_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_ry_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_ry_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_ry_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +unsigned int vivsoc_register_hardware(struct vvcam_soc_dev *dev, struct vvcam_soc_function_s *func); + +#endif /* _VIVSOC_HUB_H_ */ diff --git a/vvcam/native/soc/vsi_core_gen6.c b/vvcam/native/soc/vsi_core_gen6.c new file mode 100755 index 0000000..f7195ab --- /dev/null +++ b/vvcam/native/soc/vsi_core_gen6.c @@ -0,0 +1,427 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#ifdef ISP8000L_V2008 +#include //Fix thead compile error. +#endif + +#include "soc_ioctl.h" +#include "vsi_core_gen6.h" + + int gen6_write_reg(void* dev,unsigned int addr,unsigned int val) +{ + struct vvcam_soc_dev *soc_dev; + + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + writel(val,soc_dev->base + addr); + + return 0; +} + + int gen6_read_reg(void* dev,unsigned int addr,unsigned int *val) +{ + struct vvcam_soc_dev *soc_dev; + + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + *val = readl(soc_dev->base + addr); + + return 0; +} + + +static int gen6_set_isp_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_isp_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_isp_reset(void* dev,unsigned int id,unsigned int status) +{ + + unsigned int reg_addr; + unsigned int reg_value; + unsigned int ret; + struct vvcam_soc_dev *soc_dev;; + + reg_addr = 0; + ret = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + pr_info("isp reset enter id = %d, status = %d\n", id, status); + if (soc_dev == NULL) + return -1; + + if (id == 0) + { + reg_addr = REG_TPG0; + }else{ + reg_addr = REG_TPG1; + } + + reg_addr = 0x100; + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<0); + + }else{ + reg_value |= (1<<0); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + pr_info("isp reset exit\n"); + + return ret; +} + +static int gen6_set_isp_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_isp_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + +static int gen6_set_isp_ry_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_isp_ry_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_isp_ry_reset(void* dev,unsigned int id,unsigned int status) +{ + + unsigned int reg_addr; + unsigned int reg_value; + unsigned int ret; + struct vvcam_soc_dev *soc_dev;; + + reg_addr = 0; + ret = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + pr_info("isp ry reset enter id = %d, status = %d\n", id, status); + if (soc_dev == NULL) + return -1; + + if (id == 0) + { + reg_addr = REG_TPG0; + }else{ + reg_addr = REG_TPG1; + } + + reg_addr = 0x100; + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<4); + + }else{ + reg_value |= (1<<4); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + pr_info("isp ry reset exit\n"); + + return ret; +} + +static int gen6_set_isp_ry_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_isp_ry_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + +static int gen6_set_dwe_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_dwe_power(void* dev, unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_dwe_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + unsigned int reg_addr; + unsigned int reg_value; + struct vvcam_soc_dev *soc_dev; + pr_info("dw200 reset enter id = %d, status = %d\n", id, status); + + soc_dev = (struct vvcam_soc_dev *)dev; + reg_addr = 0; + if (soc_dev == NULL) + return -1; + + reg_addr = REG_DWE_CTRL; + reg_addr = 0x100; + + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<31); + }else{ + reg_value |= (1<<31); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + pr_info("dw200 reset exit\n"); + + return ret; +} + +static int gen6_set_dwe_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_dwe_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +static int gen6_set_vse_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_vse_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_vse_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev; + unsigned int reg_addr; + unsigned int reg_value; + + soc_dev = (struct vvcam_soc_dev *)dev; + reg_addr = 0; + if (soc_dev == NULL) + return -1; + + reg_addr = REG_VSE_CTRL; + + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<0); + }else{ + reg_value |= (1<<0); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + + return ret; +} + +static int gen6_set_vse_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_vse_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +static int gen6_set_csi_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_csi_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_csi_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev; + unsigned int reg_addr; + unsigned int reg_value; + + soc_dev = (struct vvcam_soc_dev *)dev; + reg_addr = 0; + if (soc_dev == NULL) + return -1; + + if (id == 0) + { + reg_addr = REG_TPG0; + }else{ + reg_addr = REG_TPG1; + } + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<4 | 1<<28); + }else{ + reg_value |= 0x30000210; + } + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + + return ret; +} + +static int gen6_set_csi_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_csi_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + +static int gen6_set_sensor_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_sensor_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_sensor_reset(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_set_sensor_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_sensor_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +struct vvcam_soc_function_s gen6_soc_function = { + .isp_func.set_power = gen6_set_isp_power, + .isp_func.get_power = gen6_get_isp_power, + .isp_func.set_reset = gen6_set_isp_reset, + .isp_func.set_clk = gen6_set_isp_clk, + .isp_func.get_clk = gen6_get_isp_clk, + + .dwe_func.set_power = gen6_set_dwe_power, + .dwe_func.get_power = gen6_get_dwe_power, + .dwe_func.set_reset = gen6_set_dwe_reset, + .dwe_func.set_clk = gen6_set_dwe_clk, + .dwe_func.get_clk = gen6_get_dwe_clk, + + .vse_func.set_power = gen6_set_vse_power, + .vse_func.get_power = gen6_get_vse_power, + .vse_func.set_reset = gen6_set_vse_reset, + .vse_func.set_clk = gen6_set_vse_clk, + .vse_func.get_clk = gen6_get_vse_clk, + + .csi_func.set_power = gen6_set_csi_power, + .csi_func.get_power = gen6_get_csi_power, + .csi_func.set_reset = gen6_set_csi_reset, + .csi_func.set_clk = gen6_set_csi_clk, + .csi_func.get_clk = gen6_get_csi_clk, + + .sensor_func.set_power = gen6_set_sensor_power, + .sensor_func.get_power = gen6_get_sensor_power, + .sensor_func.set_reset = gen6_set_sensor_reset, + .sensor_func.set_clk = gen6_set_sensor_clk, + .sensor_func.get_clk = gen6_get_sensor_clk, + + .isp_ry_func.set_power = gen6_set_isp_ry_power, + .isp_ry_func.get_power = gen6_get_isp_ry_power, + .isp_ry_func.set_reset = gen6_set_isp_ry_reset, + .isp_ry_func.set_clk = gen6_set_isp_ry_clk, + .isp_ry_func.get_clk = gen6_get_isp_ry_clk, +}; + + + diff --git a/vvcam/native/soc/vsi_core_gen6.h b/vvcam/native/soc/vsi_core_gen6.h new file mode 100755 index 0000000..f1b6521 --- /dev/null +++ b/vvcam/native/soc/vsi_core_gen6.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VSI_CORE_GEN6_H +#define _VSI_CORE_GEN6_H + + +#define REG_TPG0 0x300 +#define REG_TPG1 0x310 +#define REG_DWE_CTRL 0x250 +#define REG_VSE_CTRL 0x254 + + + +extern struct vvcam_soc_function_s gen6_soc_function; +int gen6_write_reg(void* dev,unsigned int addr,unsigned int val); +int gen6_read_reg(void* dev,unsigned int addr,unsigned int *val); + +#endif diff --git a/vvcam/native/soc/vvcam_soc_driver.c b/vvcam/native/soc/vvcam_soc_driver.c new file mode 100755 index 0000000..46375f9 --- /dev/null +++ b/vvcam/native/soc/vvcam_soc_driver.c @@ -0,0 +1,308 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "soc_ioctl.h" + +#define VIVCAM_SOC_NAME "vivsoc" +#define VIVCAM_SOC_MAXCNT 2 + + +struct vvcam_soc_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + void *private; +}; + +static unsigned int vvcam_soc_major = 0; +static unsigned int vvcam_soc_minor = 0; +static struct class *vvcam_soc_class; +static unsigned int devise_register_index = 0; + + +static int vvcam_soc_open(struct inode * inode, struct file * file) +{ + struct vvcam_soc_driver_dev *pdriver_dev; + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_soc_driver_dev, cdev); + file->private_data = pdriver_dev; + + return 0; +}; + +static long vvcam_soc_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vvcam_soc_driver_dev *pdriver_dev; + struct vvcam_soc_dev* psoc_dev; + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + psoc_dev = pdriver_dev->private; + ret = soc_priv_ioctl(psoc_dev, cmd , (void __user *)arg); + return ret; +}; + +static int vvcam_soc_release(struct inode * inode, struct file * file) +{ + return 0; +}; + +static struct file_operations vvcam_soc_fops = { + .owner = THIS_MODULE, + .open = vvcam_soc_open, + .release = vvcam_soc_release, + .unlocked_ioctl = vvcam_soc_ioctl, +}; + +static int vvcam_soc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vvcam_soc_driver_dev *pdriver_dev; + struct vvcam_soc_dev * psoc_dev; +// struct resource *mem; + + pr_info("enter %s\n", __func__); + + if (pdev->id >= VIVCAM_SOC_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_soc_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_soc_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_soc_driver_dev )); + + + psoc_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_soc_dev), GFP_KERNEL); + if (psoc_dev == NULL) + { + pr_err("%s:alloc struct vvcam_soc_dev error\n", __func__); + return -ENOMEM; + } + memset(psoc_dev,0,sizeof(struct vvcam_soc_dev )); + + //mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + //psoc_dev->base = devm_ioremap_resource(&pdev->dev, mem); + psoc_dev->base = ioremap(VVCTRL_BASE, VVCTRL_SIZE); + if (IS_ERR(psoc_dev->base )) + return PTR_ERR(psoc_dev->base ); + + pdriver_dev->private = psoc_dev; + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + + vvnative_soc_init(psoc_dev); + if (devise_register_index == 0) + { + if (vvcam_soc_major == 0) + { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_SOC_MAXCNT, VIVCAM_SOC_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_soc_major = MAJOR(pdriver_dev->devt); + vvcam_soc_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_soc_major, vvcam_soc_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_SOC_MAXCNT, VIVCAM_SOC_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + vvcam_soc_class = class_create(THIS_MODULE, VIVCAM_SOC_NAME); + if (IS_ERR(vvcam_soc_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_soc_major, vvcam_soc_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_soc_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_soc_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VIVCAM_SOC_NAME, pdev->id); + + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int vvcam_soc_remove(struct platform_device *pdev) +{ + struct vvcam_soc_driver_dev *pdriver_dev; + struct vvcam_soc_dev * psoc_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + psoc_dev = pdriver_dev->private; + iounmap(psoc_dev->base); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_SOC_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + + return 0; +} + +static struct platform_driver vvcam_soc_driver = { + .probe = vvcam_soc_probe, + .remove = vvcam_soc_remove, + .driver = { + .name = VIVCAM_SOC_NAME, + .owner = THIS_MODULE, + } +}; + +static void vvcam_soc_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + + +static struct resource vvcam_soc_resource[] = { + [0] = { + .start = VVCTRL_BASE, + .end = VVCTRL_BASE + VVCTRL_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; +static struct platform_device vvcam_soc_pdev = { + .name = VIVCAM_SOC_NAME, + .id = 0, + .resource = vvcam_soc_resource, + .num_resources = 1, + .dev.release = vvcam_soc_pdev_release, +}; + +static int __init vvcam_soc_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_device_register(&vvcam_soc_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } + + ret = platform_driver_register(&vvcam_soc_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + platform_device_unregister(&vvcam_soc_pdev); + return ret; + } + + return ret; +} + +static void __exit vvcam_soc_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_soc_driver); + platform_device_unregister(&vvcam_soc_pdev); +} + +module_init(vvcam_soc_init_module); +module_exit(vvcam_soc_exit_module); + +MODULE_DESCRIPTION("ISP"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/vi_pre/Makefile b/vvcam/native/vi_pre/Makefile new file mode 100755 index 0000000..7846dcd --- /dev/null +++ b/vvcam/native/vi_pre/Makefile @@ -0,0 +1,20 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vi_pre + +obj-m +=$(TARGET).o + +$(TARGET)-objs += vi_pre_driver_of.o +$(TARGET)-objs += vi_pre_ioctl.o +$(TARGET)-objs += vi_pre_dma.o +EXTRA_CFLAGS += -I$(PWD)/../../common + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean diff --git a/vvcam/native/vi_pre/vi_pre.h b/vvcam/native/vi_pre/vi_pre.h new file mode 100755 index 0000000..df45fe4 --- /dev/null +++ b/vvcam/native/vi_pre/vi_pre.h @@ -0,0 +1,342 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: Shenwuyi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __VI_PRE_H__ +#define __VI_PRE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VI_PRE_DEV_NAME "vi_pre" +#define VI_PRE_NAME "vipre" +#define VI_PRE_MAXCNT 1 + +#define HDRPRO_CTRL(n) (0x0094 + (n-1) * 4) +#define HDRPRO_COE(n) (0x009c + (n-1) * 4) +#define HDRPRO_LINW(n) (0x00b0 + (n-1) * 4) +#define HDRPRO_LINA(n) (0x00d0 + (n-1) * 4) +#define HDRPRO_LINB(n) (0x0110 + (n-1) * 4) +#define MIPI2DMA_CTRL(n) (0x0198 + (n) * 4) + + +#define VIPRE_BUS_ERR (1 << 5) +#define VIPRE_FIFO_OVER (1 << 4) +#define VIPRE_IDLE_DONE (1 << 3) +#define VIPRE_NMOVERFLOW (1 << 2) +#define VIPRE_LINE_DONE (1 << 1) +#define VIPRE_FRAME_DONE (1 << 0) + +/* mipi2dma ctrl0 */ +enum mipi2dma_ctrl0_regval { + //RAWMOD + MIPI2DMA_CTRL0_RAW6 = 0 << 4, + MIPI2DMA_CTRL0_RAW7 = 1 << 4, + MIPI2DMA_CTRL0_RAW8 = 2 << 4, + MIPI2DMA_CTRL0_RAW10 = 3 << 4, + MIPI2DMA_CTRL0_RAW12 = 4 << 4, + + //RAWPOS + MIPI2DMA_CTRL0_LOW_BIT_MODE = 0 << 3, + MIPI2DMA_CTRL0_HIGH_BIT_MODE = 1 << 3, + //mnum + MIPI2DMA_CTRL0_1_FRAME = 0 << 1, + MIPI2DMA_CTRL0_2_FRAME = 1 << 1, + MIPI2DMA_CTRL0_3_FRAME = 2 << 1, + MIPI2DMA_CTRL0_4_FRAME = 3 << 1, + //mnmod + MIPI2DMA_CTRL0_MODE_M_FRAME = 0 << 0, + MIPI2DMA_CTRL0_MODE_N_LINE = 1 << 0, +}; + +/* mipi2dma ctrl1 */ +enum mipi2dma_ctrl1_regval { + //MIPI2DMA_WBURSTLEN + MIPI2DMA_CTRL1_WBURSTLEN_4 = 3 << 16, + MIPI2DMA_CTRL1_WBURSTLEN_8 = 7 << 16, + MIPI2DMA_CTRL1_WBURSTLEN_16 = 15 << 16, +}; + +/* mipi2dma ctrl10 */ +enum mipi2dma_ctrl10_regval { + MIPI2DMA_START = 1 << 0, + MIPI2DMA_STOP = 0 << 0, +}; + +/* mipi2dma ctrl51 */ +enum mipi2dma_ctrl51_regval { + MIPI2DMA_CTRL51_CROSS_4K_EN = 1 << 0, + MIPI2DMA_CTRL51_CROSS_4K_DIS = 0 << 0, +}; + +//MIPI2DMA +#define MIPI2DMA_CTRL1_WOSNUM_SHIFT 0 + +#define MIPI2DMA_CTRL3_VERTICAL_SHIFT 16 +#define MIPI2DMA_CTRL3_HORIZON_SHIFT 0 + +#define MIPI2DMA_CTRL4_BURSTREM_SHIFT 27 +#define MIPI2DMA_CTRL4_READNUM_SHIFT 16 +#define MIPI2DMA_CTRL4_HORIZON_CNT128_SHIFT 0 + +#define MIPI2DMA_CTRL5_N_NLINENUM_SHIFT 16 +#define MIPI2DMA_CTRL5_N_LINENUM_SHIFT 0 + +#define MIPI2DMA_CTRL6_N_STRIDE_SHIFT 0 + +#define MIPI2DMA_CTRL7_M0_STRIDE_SHIFT 16 +#define MIPI2DMA_CTRL7_M1_STRIDE_SHIFT 0 + +#define MIPI2DMA_CTRL8_M2_STRIDE_SHIFT 16 +#define MIPI2DMA_CTRL8_M3_STRIDE_SHIFT 0 + +#define MIPI2DMA_CTRL15_N_SADDR_ID0_H_SHIFT 0 +#define MIPI2DMA_CTRL16_N_SADDR_ID0_L_SHIFT 0 +#define MIPI2DMA_CTRL17_N_SADDR_ID1_H_SHIFT 0 +#define MIPI2DMA_CTRL18_N_SADDR_ID1_L_SHIFT 0 +#define MIPI2DMA_CTRL19_N_SADDR_ID2_H_SHIFT 0 +#define MIPI2DMA_CTRL20_N_SADDR_ID2_L_SHIFT 0 + +#define MIPI2DMA_CTRL25_M0_SADDR_ID0_H_SHIFT 0 +#define MIPI2DMA_CTRL26_M0_SADDR_ID0_L_SHIFT 0 +#define MIPI2DMA_CTRL27_M0_SADDR_ID1_H_SHIFT 0 +#define MIPI2DMA_CTRL28_M0_SADDR_ID1_L_SHIFT 0 +#define MIPI2DMA_CTRL29_M0_SADDR_ID2_H_SHIFT 0 +#define MIPI2DMA_CTRL30_M0_SADDR_ID2_L_SHIFT 0 + +#define MIPI2DMA_CTRL31_M1_SADDR_ID0_H_SHIFT 0 +#define MIPI2DMA_CTRL32_M1_SADDR_ID0_L_SHIFT 0 +#define MIPI2DMA_CTRL33_M1_SADDR_ID1_H_SHIFT 0 +#define MIPI2DMA_CTRL34_M1_SADDR_ID1_L_SHIFT 0 +#define MIPI2DMA_CTRL35_M1_SADDR_ID2_H_SHIFT 0 +#define MIPI2DMA_CTRL36_M1_SADDR_ID2_L_SHIFT 0 + +#define MIPI2DMA_CTRL37_M2_SADDR_ID0_H_SHIFT 0 +#define MIPI2DMA_CTRL38_M2_SADDR_ID0_L_SHIFT 0 +#define MIPI2DMA_CTRL39_M2_SADDR_ID1_H_SHIFT 0 +#define MIPI2DMA_CTRL40_M2_SADDR_ID1_L_SHIFT 0 +#define MIPI2DMA_CTRL41_M2_SADDR_ID2_H_SHIFT 0 +#define MIPI2DMA_CTRL42_M2_SADDR_ID2_L_SHIFT 0 + +#define MIPI2DMA_CTRL44_BUSERR_MASK_SHIFT 21 +#define MIPI2DMA_CTRL44_FIFO_OVERERR_MASK_SHIFT 20 +#define MIPI2DMA_CTRL44_IDLE_DONE_MASK_SHIFT 19 +#define MIPI2DMA_CTRL44_MN_OVERERR_MASK_SHIFT 18 +#define MIPI2DMA_CTRL44_NLINE_DONE_MASK_SHIFT 17 +#define MIPI2DMA_CTRL44_MFRAME_DONE_MASK_SHIFT 16 + +#define MIPI2DMA_CTRL45_M3_SADDR_ID0_H_SHIFT 0 +#define MIPI2DMA_CTRL46_M3_SADDR_ID0_L_SHIFT 0 +#define MIPI2DMA_CTRL47_M3_SADDR_ID1_H_SHIFT 0 +#define MIPI2DMA_CTRL48_M3_SADDR_ID1_L_SHIFT 0 +#define MIPI2DMA_CTRL49_M3_SADDR_ID2_H_SHIFT 0 +#define MIPI2DMA_CTRL50_M3_SADDR_ID2_L_SHIFT 0 + +//HDRPRO +#define HDRPRO_CTRL1_HDRPRO_RAWMOD_MASK 0x00e00000 +#define HDRPRO_CTRL1_BAYER_MODSEL_MASK 0x00180000 +#define HDRPRO_CTRL1_COLOR_MODSEL_MASK 0x00070000 +#define HDRPRO_CTRL1_LAST_DELAY_MASK 0x0000fff8 +#define HDRPRO_CTRL1_HDRPRO_ID_MASK 0x00000006 +#define HDRPRO_CTRL1_HDRPRO_EN_MASK 0x00000001 + +#define HDRPRO_CTRL1_HDRPRO_ID_SHIFT 1 + +#define HDRPRO_CTRL2_VERTICAL_MASK 0x1fff0000 +#define HDRPRO_CTRL2_HORIZON_MASK 0x00001fff + +#define HDRPRO_CTRL2_VERTICAL_SHIFT 16 +#define HDRPRO_CTRL2_HORIZON_SHIFT 0 + +#define HDRPRO_COE1_BE_BLACK_WR_MASK 0xf0000000 +#define HDRPRO_COE1_BE_BLACK_WB_MASK 0x0f000000 +#define HDRPRO_COE1_BE_BLACK_WG0_MASK 0x00f00000 +#define HDRPRO_COE1_BE_BLACK_WG1_MASK 0x000f0000 +#define HDRPRO_COE1_BE_COLOR_WG0_00_MASK 0x0000f000 +#define HDRPRO_COE1_BE_COLOR_WG0_01_MASK 0x00000f00 +#define HDRPRO_COE1_BE_COLOR_WG0_02_MASK 0x000000f0 +#define HDRPRO_COE1_BE_COLOR_WG0_10_MASK 0x0000000f + +#define HDRPRO_COE1_BE_BLACK_WR_SHIFT 28 +#define HDRPRO_COE1_BE_BLACK_WB_SHIFT 24 +#define HDRPRO_COE1_BE_BLACK_WG0_SHIFT 20 +#define HDRPRO_COE1_BE_BLACK_WG1_SHIFT 16 +#define HDRPRO_COE1_BE_COLOR_WG0_00_SHIFT 12 +#define HDRPRO_COE1_BE_COLOR_WG0_01_SHIFT 8 +#define HDRPRO_COE1_BE_COLOR_WG0_02_SHIFT 4 +#define HDRPRO_COE1_BE_COLOR_WG0_10_SHIFT 0 + +#define HDRPRO_COE2_BE_COLOR_WG0_11_SHIFT 28 +#define HDRPRO_COE2_BE_COLOR_WG0_12_SHIFT 24 +#define HDRPRO_COE2_BE_COLOR_WG0_20_SHIFT 20 +#define HDRPRO_COE2_BE_COLOR_WG0_21_SHIFT 16 +#define HDRPRO_COE2_BE_COLOR_WG0_22_SHIFT 12 +#define HDRPRO_COE2_BE_COLOR_WG1_00_SHIFT 8 +#define HDRPRO_COE2_BE_COLOR_WG1_01_SHIFT 4 +#define HDRPRO_COE2_BE_COLOR_WG1_02_SHIFT 0 + +#define HDRPRO_COE3_BE_COLOR_WG1_10_SHIFT 28 +#define HDRPRO_COE3_BE_COLOR_WG1_11_SHIFT 24 +#define HDRPRO_COE3_BE_COLOR_WG1_12_SHIFT 20 +#define HDRPRO_COE3_BE_COLOR_WG1_20_SHIFT 16 +#define HDRPRO_COE3_BE_COLOR_WG1_21_SHIFT 12 +#define HDRPRO_COE3_BE_COLOR_WG1_22_SHIFT 8 +#define HDRPRO_COE3_BE_COLOR_WR_00_SHIFT 4 +#define HDRPRO_COE3_BE_COLOR_WR_01_SHIFT 0 + +#define HDRPRO_COE4_BE_COLOR_WR_02_SHIFT 28 +#define HDRPRO_COE4_BE_COLOR_WR_10_SHIFT 24 +#define HDRPRO_COE4_BE_COLOR_WR_11_SHIFT 20 +#define HDRPRO_COE4_BE_COLOR_WR_12_SHIFT 16 +#define HDRPRO_COE4_BE_COLOR_WR_20_SHIFT 12 +#define HDRPRO_COE4_BE_COLOR_WR_21_SHIFT 8 +#define HDRPRO_COE4_BE_COLOR_WR_22_SHIFT 4 +#define HDRPRO_COE4_BE_COLOR_WB_00_SHIFT 0 + +#define HDRPRO_COE5_BE_COLOR_WB_01_SHIFT 28 +#define HDRPRO_COE5_BE_COLOR_WB_02_SHIFT 24 +#define HDRPRO_COE5_BE_COLOR_WB_10_SHIFT 20 +#define HDRPRO_COE5_BE_COLOR_WB_11_SHIFT 16 +#define HDRPRO_COE5_BE_COLOR_WB_12_SHIFT 12 +#define HDRPRO_COE5_BE_COLOR_WB_20_SHIFT 8 +#define HDRPRO_COE5_BE_COLOR_WB_21_SHIFT 4 +#define HDRPRO_COE5_BE_COLOR_WB_22_SHIFT 0 + +#define HDRPRO_LINW1_W1_MASK 0x0fff0000 +#define HDRPRO_LINW1_W2_MASK 0x00000fff +#define HDRPRO_LINW2_W3_MASK 0x0fff0000 +#define HDRPRO_LINW2_W4_MASK 0x00000fff +#define HDRPRO_LINW3_W5_MASK 0x0fff0000 +#define HDRPRO_LINW3_W6_MASK 0x00000fff +#define HDRPRO_LINW4_W7_MASK 0x0fff0000 +#define HDRPRO_LINW4_W8_MASK 0x00000fff +#define HDRPRO_LINW5_W9_MASK 0x0fff0000 +#define HDRPRO_LINW5_W10_MASK 0x00000fff +#define HDRPRO_LINW6_W11_MASK 0x0fff0000 +#define HDRPRO_LINW6_W12_MASK 0x00000fff +#define HDRPRO_LINW7_W13_MASK 0x0fff0000 +#define HDRPRO_LINW7_W14_MASK 0x00000fff +#define HDRPRO_LINW8_W15_MASK 0x0fff0000 +#define HDRPRO_LINW8_W16_MASK 0x00000fff + +#define HDRPRO_LINW1_W1_SHIFT 16 +#define HDRPRO_LINW1_W2_SHIFT 0 +#define HDRPRO_LINW2_W3_SHIFT 16 +#define HDRPRO_LINW2_W4_SHIFT 0 +#define HDRPRO_LINW3_W5_SHIFT 16 +#define HDRPRO_LINW3_W6_SHIFT 0 +#define HDRPRO_LINW4_W7_SHIFT 16 +#define HDRPRO_LINW4_W8_SHIFT 0 +#define HDRPRO_LINW5_W9_SHIFT 16 +#define HDRPRO_LINW5_W10_SHIFT 0 +#define HDRPRO_LINW6_W11_SHIFT 16 +#define HDRPRO_LINW6_W12_SHIFT 0 +#define HDRPRO_LINW7_W13_SHIFT 16 +#define HDRPRO_LINW7_W14_SHIFT 0 +#define HDRPRO_LINW8_W15_SHIFT 16 +#define HDRPRO_LINW8_W16_SHIFT 0 + +#define HDRPRO_LINA1_A1_MASK 0x000fffff +#define HDRPRO_LINA2_A2_MASK 0x000fffff +#define HDRPRO_LINA3_A3_MASK 0x000fffff +#define HDRPRO_LINA4_A4_MASK 0x000fffff +#define HDRPRO_LINA5_A5_MASK 0x000fffff +#define HDRPRO_LINA6_A6_MASK 0x000fffff +#define HDRPRO_LINA7_A7_MASK 0x000fffff +#define HDRPRO_LINA8_A8_MASK 0x000fffff +#define HDRPRO_LINA9_A9_MASK 0x000fffff +#define HDRPRO_LINA10_A10_MASK 0x000fffff +#define HDRPRO_LINA11_A11_MASK 0x000fffff +#define HDRPRO_LINA12_A12_MASK 0x000fffff +#define HDRPRO_LINA13_A13_MASK 0x000fffff +#define HDRPRO_LINA14_A14_MASK 0x000fffff +#define HDRPRO_LINA15_A15_MASK 0x000fffff +#define HDRPRO_LINA16_A16_MASK 0x000fffff + +#define HDRPRO_LINA1_A1_SHIFT 0 +#define HDRPRO_LINA2_A2_SHIFT 0 +#define HDRPRO_LINA3_A3_SHIFT 0 +#define HDRPRO_LINA4_A4_SHIFT 0 +#define HDRPRO_LINA5_A5_SHIFT 0 +#define HDRPRO_LINA6_A6_SHIFT 0 +#define HDRPRO_LINA7_A7_SHIFT 0 +#define HDRPRO_LINA8_A8_SHIFT 0 +#define HDRPRO_LINA9_A9_SHIFT 0 +#define HDRPRO_LINA10_A10_SHIFT 0 +#define HDRPRO_LINA11_A11_SHIFT 0 +#define HDRPRO_LINA12_A12_SHIFT 0 +#define HDRPRO_LINA13_A13_SHIFT 0 +#define HDRPRO_LINA14_A14_SHIFT 0 +#define HDRPRO_LINA15_A15_SHIFT 0 +#define HDRPRO_LINA16_A16_SHIFT 0 + +#define HDRPRO_LINB1_B1_MASK 0x0000ffff +#define HDRPRO_LINB2_B2_MASK 0x0000ffff +#define HDRPRO_LINB3_B3_MASK 0x0000ffff +#define HDRPRO_LINB4_B4_MASK 0x0000ffff +#define HDRPRO_LINB5_B5_MASK 0x0000ffff +#define HDRPRO_LINB6_B6_MASK 0x0000ffff +#define HDRPRO_LINB7_B7_MASK 0x0000ffff +#define HDRPRO_LINB8_B8_MASK 0x0000ffff +#define HDRPRO_LINB9_B9_MASK 0x0000ffff +#define HDRPRO_LINB10_B10_MASK 0x0000ffff +#define HDRPRO_LINB11_B11_MASK 0x0000ffff +#define HDRPRO_LINB12_B12_MASK 0x0000ffff +#define HDRPRO_LINB13_B13_MASK 0x0000ffff +#define HDRPRO_LINB14_B14_MASK 0x0000ffff +#define HDRPRO_LINB15_B15_MASK 0x0000ffff +#define HDRPRO_LINB16_B16_MASK 0x0000ffff + +#define HDRPRO_LINB1_B1_SHIFT 0 +#define HDRPRO_LINB2_B2_SHIFT 0 +#define HDRPRO_LINB3_B3_SHIFT 0 +#define HDRPRO_LINB4_B4_SHIFT 0 +#define HDRPRO_LINB5_B5_SHIFT 0 +#define HDRPRO_LINB6_B6_SHIFT 0 +#define HDRPRO_LINB7_B7_SHIFT 0 +#define HDRPRO_LINB8_B8_SHIFT 0 +#define HDRPRO_LINB9_B9_SHIFT 0 +#define HDRPRO_LINB10_B10_SHIFT 0 +#define HDRPRO_LINB11_B11_SHIFT 0 +#define HDRPRO_LINB12_B12_SHIFT 0 +#define HDRPRO_LINB13_B13_SHIFT 0 +#define HDRPRO_LINB14_B14_SHIFT 0 +#define HDRPRO_LINB15_B15_SHIFT 0 +#define HDRPRO_LINB16_B16_SHIFT 0 + +struct vi_pre_dev { + int id; + int irq; + dev_t devt; + struct class *class; + struct cdev cdev; + spinlock_t slock; /* interrupt handling lock */ + struct mutex mutex; + void __iomem *reg_base; + unsigned long cnt; //used to cnt frame num or line num; + bool is_mframe_mode; + struct clk *aclk; + struct clk *pclk; + struct clk *pixclk; + struct platform_device *pdev; +}; +#endif/*__VI_PRE_H__*/ diff --git a/vvcam/native/vi_pre/vi_pre_dma.c b/vvcam/native/vi_pre/vi_pre_dma.c new file mode 100755 index 0000000..4f3a15c --- /dev/null +++ b/vvcam/native/vi_pre/vi_pre_dma.c @@ -0,0 +1,760 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include + +#include "vi_pre.h" +#include "vi_pre_ioctl.h" + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + + +#define img_buf 0xf0000000 + +typedef struct { + u32 dma_ctl0; + u32 dma_ctl1; + u32 dma_ctl2; + u32 dma_ctl3; + u32 dma_ctl4; + u32 dma_ctl5; + u32 dma_ctl6; + u32 dma_ctl7; + u32 dma_ctl8; + u32 dma_ctl9; + u32 dma_ctl10; + u32 dma_ctl11; + u32 dma_ctl12; + u32 dma_ctl13; + u32 dma_ctl14; + u32 dma_ctl15; + u32 dma_ctl16; + u32 dma_ctl17; + u32 dma_ctl18; + u32 dma_ctl19; + u32 dma_ctl20; + u32 dma_ctl21; + u32 dma_ctl22; + u32 dma_ctl23; + u32 dma_ctl24; + u32 dma_ctl25; + u32 dma_ctl26; + u32 dma_ctl27; + u32 dma_ctl28; + u32 dma_ctl29; + u32 dma_ctl30; + u32 dma_ctl31; + u32 dma_ctl32; + u32 dma_ctl33; + u32 dma_ctl34; + u32 dma_ctl35; + u32 dma_ctl36; + u32 dma_ctl37; + u32 dma_ctl38; + u32 dma_ctl39; + u32 dma_ctl40; + u32 dma_ctl41; + u32 dma_ctl42; + u32 dma_ctl43; + u32 dma_ctl44; + u32 dma_ctl45; + u32 dma_ctl46; + u32 dma_ctl47; + u32 dma_ctl48; + u32 dma_ctl49; + u32 dma_ctl50; + u32 dma_ctl51; +} vi_dma_reg_t; + +typedef enum { + VI_PRE_RAW_6BIT, + VI_PRE_RAW_7BIT, + VI_PRE_RAW_8BIT, + VI_PRE_RAW_10BIT_16ALIGN, + VI_PRE_RAW_12BIT, + VI_PRE_RAW_10BIT, +} vi_pre_data_width_t; + +typedef enum { + VI_PRE_M_FRAME, + VI_PRE_N_LANE, +} vi_pre_dma_mode_t; + +typedef struct { + int vc_num; //1~3 + vi_pre_data_width_t width; + vi_pre_dma_mode_t mode; + u32 resolution_h; + u32 resolution_v; + u32 line_size; //Data size of one line, unit byte; Must be 256-byte aligned + u32 num; //n line num, or m frame num(m frme max is 4) + u32 n_line_int;//only used for nline mode.(Generate an interrupt every time when n lines are completed). n_line_int <= num + u32 buf_size; + u8 *buf; +} vi_pre_dma_cfg_t; + +static vi_dma_reg_t dma_reg = { + .dma_ctl0 = 0x198, + .dma_ctl1 = 0x19c, + .dma_ctl2 = 0x1a0, + .dma_ctl3 = 0x1a4, + .dma_ctl4 = 0x1a8, + .dma_ctl5 = 0x1ac, + .dma_ctl6 = 0x1b0, + .dma_ctl7 = 0x1b4, + .dma_ctl8 = 0x1b8, + .dma_ctl9 = 0x1bc, + + .dma_ctl10 = 0x1c0, + .dma_ctl11 = 0x1c4, + .dma_ctl12 = 0x1c8, + .dma_ctl13 = 0x1cc, + .dma_ctl14 = 0x1d0, + .dma_ctl15 = 0x1d4, + .dma_ctl16 = 0x1d8, + .dma_ctl17 = 0x1dc, + .dma_ctl18 = 0x1e0, + .dma_ctl19 = 0x1e4, + + .dma_ctl20 = 0x1e8, + .dma_ctl21 = 0x1ec, + .dma_ctl22 = 0x1f0, + .dma_ctl23 = 0x1f4, + .dma_ctl24 = 0x1f8, + .dma_ctl25 = 0x1fc, + .dma_ctl26 = 0x200, + .dma_ctl27 = 0x204, + .dma_ctl28 = 0x208, + .dma_ctl29 = 0x20c, + + .dma_ctl30 = 0x210, + .dma_ctl31 = 0x214, + .dma_ctl32 = 0x218, + .dma_ctl33 = 0x21c, + .dma_ctl34 = 0x220, + .dma_ctl35 = 0x224, + .dma_ctl36 = 0x228, + .dma_ctl37 = 0x22c, + .dma_ctl38 = 0x230, + .dma_ctl39 = 0x234, + + .dma_ctl40 = 0x238, + .dma_ctl41 = 0x23c, + .dma_ctl42 = 0x240, + .dma_ctl43 = 0x244, + .dma_ctl44 = 0x248, + .dma_ctl45 = 0x24c, + .dma_ctl46 = 0x250, + .dma_ctl47 = 0x254, + .dma_ctl48 = 0x258, + .dma_ctl49 = 0x25c, + + .dma_ctl50 = 0x260, + .dma_ctl51 = 0x264, +}; + +static inline void vi_pre_dma_write(struct vi_pre_dev *dev, + u32 address, u32 data) +{ + writel(data, dev->reg_base + address); +} + +static inline u32 vi_pre_dma_read(struct vi_pre_dev *dev, + u32 address) +{ + return readl(dev->reg_base + address); +} + +static void set_dma_mode(struct vi_pre_dev *dev, vi_pre_dma_mode_t mode) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl0); + + if(mode == VI_PRE_M_FRAME) { + reg_val &= ~1; + } else { + reg_val |= 1; + } + + vi_pre_dma_write(dev, dma_reg.dma_ctl0, reg_val); +} + +static void set_frame_num(struct vi_pre_dev *dev, u32 num) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl0); + num -= 1; + reg_val &= ~(3 << 1); + reg_val |= (num << 1); + + vi_pre_dma_write(dev, dma_reg.dma_ctl0, reg_val); +} + +static int get_frame_num(struct vi_pre_dev *dev) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl0); + reg_val &= (3 << 2); + return (reg_val >> 2) + 1; +} + + +/*big align ro little align*/ +static void set_bit_mode(struct vi_pre_dev *dev, bool is_big) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl0); + + if (is_big) { + reg_val |= (1 << 3); + } else { + reg_val &= ~(1 << 3); + } + + vi_pre_dma_write(dev, dma_reg.dma_ctl0, reg_val); +} + +static void set_dma_data_width(struct vi_pre_dev *dev, vi_pre_data_width_t width) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl0); + reg_val &= ~(0x7 <<4); + reg_val |= (width << 4); + vi_pre_dma_write(dev, dma_reg.dma_ctl0, reg_val); +} + +/*length is 4, 8, 16*/ +static void set_dma_burst_length(struct vi_pre_dev *dev, u8 len) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl1); + len -=1; + reg_val &= ~(0xff << 16); + reg_val |= (len << 16); + reg_val |= 0x3ff; + vi_pre_dma_write(dev, dma_reg.dma_ctl1, reg_val); +} + +static u32 read_dma_burst_length(struct vi_pre_dev *dev) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl1); + return ((reg_val >> 16) & 0xff) + 1; +} + +static void set_dma_resolution(struct vi_pre_dev *dev, u16 h, u16 v) +{ + u32 reg_val = 0; + h &= 0x1fff; + v &= 0x1fff; + reg_val = h | (v << 16); + + vi_pre_dma_write(dev, dma_reg.dma_ctl3, reg_val); +} + +static int set_nline_oneline_size(struct vi_pre_dev *dev, vi_pre_dma_cfg_t *cfg) +{ + u32 reg_val = 0; + u32 stream_min = 0; + u32 cnt_128 = 0; + u32 read_num = 0; + u32 burstrem = 0; + + stream_min = cfg->resolution_h; + if (cfg->width == VI_PRE_RAW_12BIT || + cfg->width == VI_PRE_RAW_10BIT_16ALIGN) { + stream_min = cfg->resolution_h * 2; + } + + if (stream_min > cfg->line_size) { + return -1; + } + + if (stream_min % 16) { + stream_min += 16 - (stream_min % 16); + } + + cnt_128 = stream_min / 16; + read_num = cnt_128 / read_dma_burst_length(dev); + burstrem = cnt_128 % read_dma_burst_length(dev); + + if (cnt_128 % read_dma_burst_length(dev)) { + read_num +=1; + } + + if (burstrem == 0) { + burstrem = read_dma_burst_length(dev); + } + + reg_val = cnt_128 | (read_num << 16) | (burstrem << 27); + vi_pre_dma_write(dev, dma_reg.dma_ctl4, reg_val); + vi_pre_dma_write(dev, dma_reg.dma_ctl6, cfg->line_size); + return 0; +} + +static void set_nline_period(struct vi_pre_dev *dev, u32 num) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl5); + reg_val &= ~0xfff; + reg_val |= num; + printk("vipre nline period num %d, reg_val 0x%x\n", num, reg_val); + vi_pre_dma_write(dev, dma_reg.dma_ctl5, reg_val); +} + +static void set_nline_int_period(struct vi_pre_dev *dev, u32 num) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl5); + reg_val &= ~(0x7ff << 16); + reg_val |= (num << 16); + printk("vipre nline int period num %d, reg_val 0x%x\n", num, reg_val); + vi_pre_dma_write(dev, dma_reg.dma_ctl5, reg_val); +} + +static u16 get_nline_period(struct vi_pre_dev *dev) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl5); + + return reg_val & 0xfff; +} + +static u16 get_nline_int_period(struct vi_pre_dev *dev) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl5); + + return (reg_val >> 16) & 0xfff; +} + +static int set_mfram_oneline_range(struct vi_pre_dev *dev, int frame_id, u32 size) +{ + u32 aligned = 0; + u32 reg_val = 0; + u32 reg = 0; + + aligned = read_dma_burst_length(dev) * 16; + /*set buf addr*/ + if(size % aligned) { + printk("<0>""###########error !!!!!!!!! %s, %d\n", __func__, __LINE__); + return -1; + } + + reg = frame_id / 2 * 4 + dma_reg.dma_ctl7; + reg_val = vi_pre_dma_read(dev, reg); + if (frame_id % 2 == 0) { + reg_val &= ~(0xffff << 16); + reg_val |= (size << 16); + } else { + reg_val &= ~0xffff; + reg_val |= size; + } + + vi_pre_dma_write(dev, reg, reg_val); + return 0; +} + +static int set_mframe_oneline_group(struct vi_pre_dev *dev, vi_pre_dma_cfg_t *cfg) +{ + u32 reg_val = 0; + u32 stream_min = 0; + u32 cnt_128 = 0; + u32 read_num = 0; + u32 burstrem = 0; + + stream_min = cfg->resolution_h; + if (cfg->width == VI_PRE_RAW_12BIT || + cfg->width == VI_PRE_RAW_10BIT_16ALIGN) { + stream_min = cfg->resolution_h * 2; + } + + if (stream_min > cfg->line_size) { + return -1; + } + + if (stream_min % 16) { + stream_min += 16 - (stream_min % 16); + } + + cnt_128 = stream_min / 16; + read_num = cnt_128 / read_dma_burst_length(dev); + burstrem = cnt_128 % read_dma_burst_length(dev); + + if (cnt_128 % read_dma_burst_length(dev)) { + read_num +=1; + } + + if (burstrem == 0) { + burstrem = read_dma_burst_length(dev); + } + + reg_val = cnt_128 | (read_num << 16) | (burstrem << 27); + vi_pre_dma_write(dev, dma_reg.dma_ctl4, reg_val); + + return 0; +} + +static void dma_reset(struct vi_pre_dev *dev) +{ + vi_pre_dma_write(dev, dma_reg.dma_ctl9, 1); + while(vi_pre_dma_read(dev, dma_reg.dma_ctl9) == 1); +} + +static void dma_enable(struct vi_pre_dev *dev, int en) +{ + if(en) { + vi_pre_dma_write(dev, dma_reg.dma_ctl10, 1); + } else { + vi_pre_dma_write(dev, dma_reg.dma_ctl10, 0); + } +} + +static void dma_period_clear(struct vi_pre_dev *dev, int ch) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl11); + if (reg_val & (1 << ch)) { + reg_val &= ~(1 << ch); + } else { + reg_val |= (1 << ch); + } + + vi_pre_dma_write(dev, dma_reg.dma_ctl11, reg_val); +} + +static void nline_mode_set_line_position(struct vi_pre_dev *dev, int ch, int p) +{ + u32 reg = dma_reg.dma_ctl12 + ch * 4; + vi_pre_dma_write(dev, reg, p); +} + +static void nline_mode_set_start_addr(struct vi_pre_dev *dev, int ch, unsigned long addr) +{ + u32 reg = dma_reg.dma_ctl15 + ch * 8; + u8 h = addr >> 32; + u32 l = addr & 0xffffffff; + vi_pre_dma_write(dev, reg, h); + vi_pre_dma_write(dev, reg + 4, l); +} + +static u16 nline_mode_period_cnt(struct vi_pre_dev *dev, int ch) +{ + u32 reg = dma_reg.dma_ctl21 + ch / 2 * 4; + + if(ch % 2) { + return (vi_pre_dma_read(dev, reg) >> 16) & 0xfff; + } else { + return vi_pre_dma_read(dev, reg) & 0xfff; + } +} + +static void mframe_mode_set_position(struct vi_pre_dev *dev, int ch, int f, int l) +{ + u32 reg = dma_reg.dma_ctl23 + ch / 2 * 4; + u32 reg_val = vi_pre_dma_read(dev, reg); + + f &= 3; + l &= 0xfff; + + if (ch % 2) { + reg_val &=~(0xffff << 16); + reg_val |= (l << 16) | (f << 29); + } else { + reg_val &=~0xffff; + reg_val |= l | (f << 13); + } + + vi_pre_dma_write(dev, reg, reg_val); +} + +static void mframe_set_start_addr(struct vi_pre_dev *dev, int frame_id, int vc_ch, unsigned long addr) +{ + u32 reg = 0; + u8 h = addr >> 32; + u32 l = addr & 0xffffffff; + + if (frame_id <= 2) { + reg = dma_reg.dma_ctl25 + frame_id * 24 + vc_ch * 8; + } else { + reg = dma_reg.dma_ctl45 + vc_ch * 8; + } + + + vi_pre_dma_write(dev, reg, h); + vi_pre_dma_write(dev, reg + 4, l); +} + +static u32 mframe_frame_done_flag(struct vi_pre_dev *dev) +{ + return vi_pre_dma_read(dev, dma_reg.dma_ctl43) & 0xfff; +} + +static void mframe_frame_done_flag_clear(struct vi_pre_dev *dev, u32 mask) +{ + + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl43); + reg_val |= mask; + + vi_pre_dma_write(dev, dma_reg.dma_ctl43, mask); +} + + +static void dma_interrupt_set(struct vi_pre_dev *dev, u32 mask, int en) +{ + u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl44); + if (en) { + reg_val &= ~(mask << 16); + } else { + reg_val |= (mask << 16); + } + + vi_pre_dma_write(dev, dma_reg.dma_ctl44, reg_val); +} + +static u16 dma_interrupt_status(struct vi_pre_dev *dev) +{ + return vi_pre_dma_read(dev, dma_reg.dma_ctl44) & 0xffff; +} + +static void dma_clear_interrupt_status(struct vi_pre_dev *dev, u32 sta) +{ + + u32 reg = vi_pre_dma_read(dev, dma_reg.dma_ctl44); + reg |= sta; + return vi_pre_dma_write(dev, dma_reg.dma_ctl44, reg); +} + +static int vi_pre_mframe_config(struct vi_pre_dev *dev, vi_pre_dma_cfg_t *cfg) +{ + unsigned long buf_base = (unsigned long)cfg->buf; + int ret = 0; + int i = 0; + int j = 0; + + if (cfg->num > 4) { + return -1; + } + + if (cfg->buf_size < cfg->line_size * cfg->resolution_v * cfg->num) { + return -1; + } + + set_frame_num(dev, cfg->num); + + ret = set_mframe_oneline_group(dev, cfg); + if (ret != 0) { + printk("<0>""!!!!!!!set mframe oneline size error!!!!!!!!!!!!!!!!\n"); + return -1; + } + + for(i = 0; i < cfg->num; i++) { + ret = set_mfram_oneline_range(dev, i, cfg->line_size); + if (ret != 0) { + printk("<0>""!!!!!!!set mframe oneline range error!!!!!!!!!!!!!!!!\n"); + return -1; + } + for (j = 0; j < cfg->vc_num; j++) { + mframe_set_start_addr(dev, i, j, buf_base); + buf_base += cfg->line_size * cfg->resolution_v; + } + } + + return 0; +} + +static int vi_pre_nline_config(struct vi_pre_dev *dev, vi_pre_dma_cfg_t *cfg) +{ + unsigned long buf_base = (unsigned long)cfg->buf; + int i = 0; + + if (cfg->line_size % 256) { + return -1; + } + + if (cfg->buf_size < cfg->line_size * cfg->num) { + return -1; + } + + if (set_nline_oneline_size(dev, cfg) != 0) { + return -1; + } + + set_nline_period(dev, cfg->num); + set_nline_int_period(dev, cfg->n_line_int); + for(i = 0; i < cfg->vc_num; i++) { + nline_mode_set_start_addr(dev, i, buf_base); + buf_base += cfg->line_size * cfg->resolution_v; + } + + return 0; +} + +int vi_pre_dma_init(struct vi_pre_dev *pdriver_dev) +{ + return 0; +} + +int vi_pre_dma_uninit(struct platform_device *pdev) +{ + struct vi_pre_dev *pdriver_dev; + pdriver_dev = platform_get_drvdata(pdev); + memset(pdriver_dev->cnt, 0, sizeof(pdriver_dev->cnt)); + return 0; +} + +static int dma_config(struct vi_pre_dev *pdriver_dev, vi_pre_dma_cfg_t *cfg) +{ + int ret = 0; + set_dma_burst_length(pdriver_dev, 16); + set_dma_data_width(pdriver_dev, cfg->width); + set_bit_mode(pdriver_dev, 1); + set_dma_mode(pdriver_dev, cfg->mode); + set_dma_resolution(pdriver_dev, cfg->resolution_h, cfg->resolution_v); + + if (cfg->mode == VI_PRE_M_FRAME) { + ret = vi_pre_mframe_config(pdriver_dev, cfg); + pdriver_dev->is_mframe_mode = true; + } else if (cfg->mode == VI_PRE_N_LANE) { + ret = vi_pre_nline_config(pdriver_dev, cfg); + pdriver_dev->is_mframe_mode = false; + } + + return ret; +} + +int vi_pre_dma_config(struct vi_pre_dev *pdriver_dev, void *arg) +{ + vi_pre_dma_cfg_t cfg; + check_retval(copy_from_user(&cfg, arg, sizeof(cfg))); + //cfg.buf_size = cfg.num * cfg.vc_num * cfg.line_size * cfg.resolution_v; + //cfg.buf = (u8 *)img_buf; + + return dma_config(pdriver_dev, &cfg); +} + +#define VIPRE_BUS_ERR (1 << 5) +#define VIPRE_FIFO_OVER (1 << 4) +#define VIPRE_IDLE_DONE (1 << 3) +#define VIPRE_NMOVERFLOW (1 << 2) +#define VIPRE_LINE_DONE (1 << 1) +#define VIPRE_FRAME_DONE (1 << 0) + +int vi_pre_dma_start(struct vi_pre_dev *pdriver_dev) +{ + u32 mask = VIPRE_BUS_ERR | VIPRE_FIFO_OVER | VIPRE_NMOVERFLOW; + + if (pdriver_dev->is_mframe_mode) { + mask |= VIPRE_FRAME_DONE; + } else { + mask |= VIPRE_LINE_DONE; + } + + dma_interrupt_set(pdriver_dev, mask, 1); + dma_enable(pdriver_dev, 1); + + return 0; +} + +int vi_pre_dma_stop(struct vi_pre_dev *pdriver_dev) +{ + u32 mask = VIPRE_BUS_ERR | VIPRE_FIFO_OVER | VIPRE_NMOVERFLOW; + dma_interrupt_set(pdriver_dev, mask, 0); + dma_enable(pdriver_dev, 0); + udelay(1000); + return 0; +} + +static int vipre_event = 0; + +int *vi_pre_event(void) +{ + return &vipre_event; +} + +void vi_pre_dma_interrupt_handler(struct vi_pre_dev *pdriver_dev) +{ + u32 status = 0; + u32 f_done_sta = 0; + unsigned long flags = 0; + //int i = 0; + + status = dma_interrupt_status(pdriver_dev); + //printk("<0>""vipre int sta %x\n", status ); + if (status & (1 << 4)) { + printk("<0>""vipre err int sta 0x%x\n", status); + } + dma_clear_interrupt_status(pdriver_dev, status); + spin_lock_irqsave(&pdriver_dev->slock, flags); + if (status & VIPRE_FRAME_DONE) { + pdriver_dev->cnt++; + if (pdriver_dev->cnt >= 4) { + pdriver_dev->cnt = 0; + vipre_event = 1; + } + f_done_sta = mframe_frame_done_flag(pdriver_dev); + //printk("<0>""f_done_sta int sta 0x%x\n", f_done_sta); + mframe_frame_done_flag_clear(pdriver_dev, f_done_sta); + //vi_pre_dma_stop(pdriver_dev); + /*TODO send event*/ + //printk("frame done %x\n", f_done_sta); + } else if (status & VIPRE_LINE_DONE) { + //u32 nline_done_sta =; + //pdriver_dev->cnt++; + //printk("line done %x\n", f_done_sta); + vipre_event = 1; + } + +#if 0 + //u32 line_cnt = pdriver_dev->cnt * get_nline_int_period(pdriver_dev); + + if (pdriver_dev->is_mframe_mode) { + for(i = 0; i < 3; i++) { + if(pdriver_dev->cnt[i] < get_frame_num(pdriver_dev)) { + continue; + } + pdriver_dev->cnt[i] = 0; + dma_period_clear(pdriver_dev, i); + } + } + else (pdriver_dev->is_mframe_mode == 0 && line_cnt >= get_nline_period(pdriver_dev)){ + dma_period_clear(struct vi_pre_dev *dev, int ch) + } +#endif + spin_unlock_irqrestore(&pdriver_dev->slock, flags); +} + +int vi_pore_vc_bind(struct platform_device *pdev, u8 buf_id, u8 vc_id) +{ + + return 0; +} + +int vi_pore_attach_callback(struct platform_device *pdev) +{ + + return 0; +} + +int vi_pore_deattach_callback(struct platform_device *pdev) +{ + + return 0; +} + +/////////////////demo/////////////////////// +void test(struct vi_pre_dev *pdev) +{ + vi_pre_dma_cfg_t cfg; + cfg.vc_num = 1; + cfg.width = VI_PRE_RAW_12BIT; + cfg.mode = VI_PRE_M_FRAME; + cfg.resolution_h = 1944; //1920;//3840; + cfg.resolution_v = 1100; //1080;//2160; + cfg.line_size = 2048 * 2; //必须256byte对齐 + cfg.num = 4; //n line num, or m frame num(m frme max is 4) + cfg.buf_size = 2048 * 1100 * 2 * 10; + cfg.buf = (u8 *)img_buf; + + dma_config(pdev, &cfg); + vi_pre_dma_start(pdev); +} diff --git a/vvcam/native/vi_pre/vi_pre_driver_of.c b/vvcam/native/vi_pre/vi_pre_driver_of.c new file mode 100755 index 0000000..a454342 --- /dev/null +++ b/vvcam/native/vi_pre/vi_pre_driver_of.c @@ -0,0 +1,394 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: Shenwuyi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include "vi_pre.h" +#include "vi_pre_ioctl.h" + +static unsigned int vi_pre_major = 0; +static unsigned int vi_pre_minor = 0; +struct class *vi_pre_class; +static unsigned int device_register_index = 0; + +static int vipre_runtime_suspend(struct device *dev) +{ + struct vi_pre_dev *pdriver_dev = dev_get_drvdata(dev); + pr_info("enter %s\n", __func__); + + if (pdriver_dev->aclk!= NULL) { + clk_disable_unprepare(pdriver_dev->aclk); + } + + if (pdriver_dev->pclk != NULL) { + clk_disable_unprepare(pdriver_dev->pclk); + } + + if (pdriver_dev->pixclk!= NULL) { + clk_disable_unprepare(pdriver_dev->pixclk); + } + + pr_info("exit %s\n", __func__); + return 0; +} +static int vipre_runtime_resume(struct device *dev) +{ + int ret = 0; + struct vi_pre_dev *pdriver_dev = dev_get_drvdata(dev); + + if (pdriver_dev->pclk != NULL) { + ret = clk_prepare_enable(pdriver_dev->pclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable csi pclk\n"); + clk_disable_unprepare(pdriver_dev->pclk); + } + } + + if (pdriver_dev->pixclk!= NULL) { + ret = clk_prepare_enable(pdriver_dev->pixclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable pixclk\n"); + clk_disable_unprepare(pdriver_dev->pixclk); + } + } + + if (pdriver_dev->aclk!= NULL) { + ret = clk_prepare_enable(pdriver_dev->aclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable aclk\n"); + clk_disable_unprepare(pdriver_dev->aclk); + } + } + + pr_info("%s Enabled clock\n", __func__); + return ret; +} + +static const struct dev_pm_ops vipre_runtime_pm_ops = { + SET_RUNTIME_PM_OPS(vipre_runtime_suspend, vipre_runtime_resume, NULL) +}; + +static int vi_pre_open(struct inode * inode, struct file * file) +{ + int ret = 0; + struct vi_pre_dev *pdriver_dev; + struct device *dev; + + pr_info("entry %s\n", __func__); + pdriver_dev = container_of(inode->i_cdev, struct vi_pre_dev, cdev); + file->private_data = pdriver_dev; + + dev = &pdriver_dev->pdev->dev; + if (pm_runtime_get_sync(dev)) { + ret = vipre_runtime_resume(dev); + if (ret) + pr_err("fail to resume csi %s %d\n", __func__, __LINE__); + } + + pr_info("exit %s\n", __func__); + return 0; +}; + +static long vi_pre_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vi_pre_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + //printk("%s, %d, vipre_cmd %u\n", __func__, __LINE__, cmd); + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + mutex_lock(&pdriver_dev->mutex); + + ret = vi_pre_priv_ioctl(pdriver_dev, cmd ,(void *)arg); + mutex_unlock(&pdriver_dev->mutex); + + pr_info("exit %s\n", __func__); + + return ret; +}; + +static int vi_pre_release(struct inode * inode, struct file * file) +{ + int ret = 0; + struct vi_pre_dev *pdriver_dev; + struct device *dev; + + pr_info("enter %s\n", __func__); + + pdriver_dev = container_of(inode->i_cdev, struct vi_pre_dev, cdev); + file->private_data = pdriver_dev; + + dev = &pdriver_dev->pdev->dev; + + ret = pm_runtime_put_sync(dev); + if (ret) { + pr_info("fail to resume vipre %s %d\n", __func__, __LINE__); + } + + pr_info("exit %s\n", __func__); + + return 0; +}; + +static int vi_pre_mmap(struct file *pFile, struct vm_area_struct *vma) +{ + #define img_buf 0xf0000000 + + pr_info("enter %s\n", __func__); + vma->vm_flags |= VM_IO; + vma->vm_flags |= (VM_DONTEXPAND | VM_DONTDUMP); + if(remap_pfn_range(vma, + vma->vm_start, + img_buf >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) { + return -EAGAIN; + } + + pr_info("exit %s\n", __func__); + return 0; +}; + +static DECLARE_WAIT_QUEUE_HEAD(vipre_waitq); +static unsigned vi_pre_poll(struct file *file, poll_table *wait) +{ + extern int *vi_pre_event(void); + int *event = 0; + unsigned int mask = 0; + event = vi_pre_event(); + poll_wait(file, &vipre_waitq, wait); + + if (*event) { + mask |= POLLIN | POLLRDNORM; + *event = 0; + } + + return mask; +} + +struct file_operations vi_pre_fops = { + .owner = THIS_MODULE, + .open = vi_pre_open, + .release = vi_pre_release, + .unlocked_ioctl = vi_pre_ioctl, + .mmap = vi_pre_mmap, + .poll = vi_pre_poll, +}; + +static irqreturn_t vi_pre_irq(int irq, void *dev_id) +{ + extern void vi_pre_dma_interrupt_handler(struct vi_pre_dev *pdriver_dev); + struct vi_pre_dev *pdriver_dev = dev_id; + vi_pre_dma_interrupt_handler(pdriver_dev); + wake_up_interruptible(&vipre_waitq); + + return IRQ_HANDLED; +} + +static int vi_pre_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vi_pre_dev *pdriver_dev; + struct resource *mem; + struct device *dev = NULL; + + pr_info("enter %s\n", __func__); + dev = &pdev->dev; + pdev->id = device_register_index; + if (pdev->id >= VI_PRE_MAXCNT) { + pr_err("%s:pdev id is %d error\n", __func__, pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev, sizeof(struct vi_pre_dev), GFP_KERNEL); + if (pdriver_dev == NULL) { + pr_err("%s:alloc struct vi_pre_dev error\n", __func__); + return -ENOMEM; + } + pr_info("%s:isp[%d]: pdriver_dev =0x%px\n", __func__, pdev->id, pdriver_dev); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pdriver_dev->reg_base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(pdriver_dev->reg_base)) + return PTR_ERR(pdriver_dev->reg_base); + pr_info("%s:isp[%d]: pdriver_dev->base=0x%px\n", __func__, + pdev->id, pdriver_dev->reg_base); + + pdriver_dev->id = pdev->id; + pdriver_dev->pdev = pdev; + mutex_init(&pdriver_dev->mutex); + + /*parse clk info from dts*/ + pdriver_dev->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(pdriver_dev->pclk)) { + dev_err(&pdev->dev, "failed to get pclk"); + pdriver_dev->pclk = NULL; + } + + pdriver_dev->pixclk = devm_clk_get(&pdev->dev, "pixclk"); + if (IS_ERR(pdriver_dev->pixclk)) { + dev_err(&pdev->dev, "failed to get pixclk"); + pdriver_dev->pixclk = NULL; + } + + pdriver_dev->aclk = devm_clk_get(&pdev->dev, "aclk"); + if (IS_ERR(pdriver_dev->aclk)) { + dev_err(&pdev->dev, "failed to get aclk"); + pdriver_dev->aclk = NULL; + } + + platform_set_drvdata(pdev, pdriver_dev); + + if (device_register_index == 0) { + int ret; + + if (vi_pre_major == 0) { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VI_PRE_MAXCNT, VI_PRE_NAME); + if (ret != 0) { + + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vi_pre_major = MAJOR(pdriver_dev->devt); + vi_pre_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vi_pre_major, vi_pre_minor); + ret = register_chrdev_region(pdriver_dev->devt, VI_PRE_MAXCNT, VI_PRE_NAME); + if (ret) { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + vi_pre_class = class_create(THIS_MODULE, VI_PRE_NAME); + if (IS_ERR(vi_pre_class)) { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vi_pre_major, vi_pre_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vi_pre_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vi_pre_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VI_PRE_NAME, pdev->id); + + pdriver_dev->irq = platform_get_irq(pdev, 0); + if (pdriver_dev->irq < 0) { + dev_err(dev, "vipre get irq error: %d\n", pdriver_dev->id); + ret = pdriver_dev->irq; + goto end; + } + + spin_lock_init(&pdriver_dev->slock); + if (device_property_read_bool(dev, "vi_pre_irq_en")) { + ret = devm_request_irq(dev, pdriver_dev->irq, + vi_pre_irq, IRQF_SHARED, + dev_name(dev), pdriver_dev); + if (ret) { + dev_err(dev, "irq vipre failed\n"); + goto end; + } + } + + pm_runtime_enable(&pdev->dev); + ret = vipre_runtime_resume(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "fail to resume vipre\n"); + } + + vipre_runtime_suspend(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "fail to suspend vipre\n"); + } + + device_register_index++; + pr_info("exit %s:[%d]\n", __func__, pdev->id); + +end: + return ret; +} + + +static int vi_pre_remove(struct platform_device *pdev) +{ + struct vi_pre_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + device_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VI_PRE_MAXCNT); + if (device_register_index == 0) { + class_destroy(pdriver_dev->class); + } + devm_kfree(&pdev->dev, pdriver_dev); + + return 0; +} + + +static const struct of_device_id vi_pre_of_match_table[] = { + { .compatible = "thead,vi_pre", }, + { }, +}; + +static struct platform_driver vi_pre_driver = { + .probe = vi_pre_probe, + .remove = vi_pre_remove, + .driver = { + .owner = THIS_MODULE, + .name = VI_PRE_DEV_NAME, + .of_match_table = vi_pre_of_match_table, + .pm = &vipre_runtime_pm_ops, + }, +}; + +static int __init vi_pre_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&vi_pre_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + pr_info("exit %s\n", __func__); + + return ret; +} + +static void __exit vi_pre_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vi_pre_driver); + pr_info("exit %s\n", __func__); +} + +module_init(vi_pre_init_module); +module_exit(vi_pre_exit_module); + +MODULE_DESCRIPTION("VI_PRE"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/vi_pre/vi_pre_ioctl.c b/vvcam/native/vi_pre/vi_pre_ioctl.c new file mode 100755 index 0000000..ccdcd7c --- /dev/null +++ b/vvcam/native/vi_pre/vi_pre_ioctl.c @@ -0,0 +1,984 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: Shenwuyi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include "vi_pre.h" +#include "vi_pre_ioctl.h" +#include "vi_pre_reg.h" + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +static void vi_pre_write(struct vi_pre_dev *dec, unsigned int addr, unsigned int val) +{ + writel(val, dec->reg_base + addr); +} + +static unsigned int vi_pre_read(struct vi_pre_dev *dev, unsigned int addr) +{ + return readl(dev->reg_base + addr); +} + +static int vi_pre_write_reg(struct vi_pre_dev *dev, void *__user args) +{ + struct vi_pre_reg_t reg; + unsigned int val; + + check_retval(copy_from_user(®, args, sizeof(reg))); + vi_pre_write(dev, reg.offset, reg.value); + pr_info("%s write addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value); + + val = vi_pre_read(dev, reg.offset); + pr_info("%s rad back addr 0x%08x val 0x%08x\n", __func__, reg.offset, val); + + return 0; +} + +static int vi_pre_read_reg(struct vi_pre_dev *dev, void *__user args) +{ + struct vi_pre_reg_t reg; + + check_retval(copy_from_user(®, args, sizeof(reg))); + reg.value = vi_pre_read(dev, reg.offset); + check_retval(copy_to_user(args, ®, sizeof(reg))); + + //pr_info("%s addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value); + return 0; +} + +static int vi_pre_set_hdrpro_merge_para(struct vi_pre_dev *dev, void *args) +{ + int ret = 0; + unsigned int i = 0, j = 0, val = 0; + struct hdrpro_merge_para merge_para; + struct hdrpro_para *w; + struct hdrpro_para *b; + struct hdrpro_para *a; + + check_retval(copy_from_user(&merge_para, args, sizeof(merge_para))); + a = &merge_para.a; + b = &merge_para.b; + w = &merge_para.w; + + for (i = HDRPRO_LINW(1); i <= HDRPRO_LINW(8); i += 4) { + val = 0; + val |= (w->para[j] << 16); + j++; + val |= w->para[j]; + j++; + vi_pre_write(dev, i, val); + } + + j = 0; + for (i = HDRPRO_LINA(1); i <= HDRPRO_LINA(16); i += 4) { + val = 0; + val |= a->para[j]; + vi_pre_write(dev, i, val); + j++; + } + + j = 0; + for (i = HDRPRO_LINB(1); i <= HDRPRO_LINB(16); i += 4) { + val = 0; + val |= b->para[j]; + vi_pre_write(dev, i, val); + j++; + } + + return ret; +} + +static int vi_pre_set_hdrpro_color_para(struct vi_pre_dev *dev, void *args) +{ + int ret = 0; + unsigned int val = 0; + struct hdrpro_color_para color_para; + + check_retval(copy_from_user(&color_para, args, sizeof(color_para))); + val = vi_pre_read(dev, HDRPRO_COE(1)); + val &= ~HDRPRO_COE1_BE_COLOR_WG0_00_MASK; + val |= (color_para.wg0.pattern_00 << HDRPRO_COE1_BE_COLOR_WG0_00_SHIFT); + val &= ~HDRPRO_COE1_BE_COLOR_WG0_01_MASK; + val |= (color_para.wg0.pattern_01 << HDRPRO_COE1_BE_COLOR_WG0_01_SHIFT); + val &= ~HDRPRO_COE1_BE_COLOR_WG0_02_MASK; + val |= (color_para.wg0.pattern_02 << HDRPRO_COE1_BE_COLOR_WG0_02_SHIFT); + val &= ~HDRPRO_COE1_BE_COLOR_WG0_10_MASK; + val |= (color_para.wg0.pattern_10 << HDRPRO_COE1_BE_COLOR_WG0_10_SHIFT); + vi_pre_write(dev, HDRPRO_COE(1), val); + + //val = vi_pre_read(dev, HDRPRO_COE(2)); + val = 0; + val |= (color_para.wg0.pattern_11 << HDRPRO_COE2_BE_COLOR_WG0_11_SHIFT); + val |= (color_para.wg0.pattern_12 << HDRPRO_COE2_BE_COLOR_WG0_12_SHIFT); + val |= (color_para.wg0.pattern_20 << HDRPRO_COE2_BE_COLOR_WG0_20_SHIFT); + val |= (color_para.wg0.pattern_21 << HDRPRO_COE2_BE_COLOR_WG0_21_SHIFT); + val |= (color_para.wg0.pattern_22 << HDRPRO_COE2_BE_COLOR_WG0_22_SHIFT); + val |= (color_para.wg1.pattern_00 << HDRPRO_COE2_BE_COLOR_WG1_00_SHIFT); + val |= (color_para.wg1.pattern_01 << HDRPRO_COE2_BE_COLOR_WG1_01_SHIFT); + val |= (color_para.wg1.pattern_02 << HDRPRO_COE2_BE_COLOR_WG1_02_SHIFT); + vi_pre_write(dev, HDRPRO_COE(2), val); + + //val = vi_pre_read(dev, HDRPRO_COE(3)); + val = 0; + val |= (color_para.wg1.pattern_10 << HDRPRO_COE3_BE_COLOR_WG1_10_SHIFT); + val |= (color_para.wg1.pattern_11 << HDRPRO_COE3_BE_COLOR_WG1_11_SHIFT); + val |= (color_para.wg1.pattern_12 << HDRPRO_COE3_BE_COLOR_WG1_12_SHIFT); + val |= (color_para.wg1.pattern_20 << HDRPRO_COE3_BE_COLOR_WG1_20_SHIFT); + val |= (color_para.wg1.pattern_21 << HDRPRO_COE3_BE_COLOR_WG1_21_SHIFT); + val |= (color_para.wg1.pattern_22 << HDRPRO_COE3_BE_COLOR_WG1_22_SHIFT); + val |= (color_para.wr.pattern_00 << HDRPRO_COE3_BE_COLOR_WR_00_SHIFT); + val |= (color_para.wr.pattern_01 << HDRPRO_COE3_BE_COLOR_WR_01_SHIFT); + vi_pre_write(dev, HDRPRO_COE(3), val); + + //val = vi_pre_read(dev, HDRPRO_COE(4)); + val = 0; + val |= (color_para.wr.pattern_02 << HDRPRO_COE4_BE_COLOR_WR_02_SHIFT); + val |= (color_para.wr.pattern_10 << HDRPRO_COE4_BE_COLOR_WR_10_SHIFT); + val |= (color_para.wr.pattern_11 << HDRPRO_COE4_BE_COLOR_WR_11_SHIFT); + val |= (color_para.wr.pattern_12 << HDRPRO_COE4_BE_COLOR_WR_12_SHIFT); + val |= (color_para.wr.pattern_20 << HDRPRO_COE4_BE_COLOR_WR_20_SHIFT); + val |= (color_para.wr.pattern_21 << HDRPRO_COE4_BE_COLOR_WR_21_SHIFT); + val |= (color_para.wr.pattern_22 << HDRPRO_COE4_BE_COLOR_WR_22_SHIFT); + val |= (color_para.wb.pattern_00 << HDRPRO_COE4_BE_COLOR_WB_00_SHIFT); + vi_pre_write(dev, HDRPRO_COE(4), val); + + //val = vi_pre_read(dev, HDRPRO_COE(5)); + val = 0; + val |= (color_para.wb.pattern_01 << HDRPRO_COE5_BE_COLOR_WB_01_SHIFT); + val |= (color_para.wb.pattern_02 << HDRPRO_COE5_BE_COLOR_WB_02_SHIFT); + val |= (color_para.wb.pattern_10 << HDRPRO_COE5_BE_COLOR_WB_10_SHIFT); + val |= (color_para.wb.pattern_11 << HDRPRO_COE5_BE_COLOR_WB_11_SHIFT); + val |= (color_para.wb.pattern_12 << HDRPRO_COE5_BE_COLOR_WB_12_SHIFT); + val |= (color_para.wb.pattern_20 << HDRPRO_COE5_BE_COLOR_WB_20_SHIFT); + val |= (color_para.wb.pattern_21 << HDRPRO_COE5_BE_COLOR_WB_21_SHIFT); + val |= (color_para.wb.pattern_22 << HDRPRO_COE5_BE_COLOR_WB_22_SHIFT); + vi_pre_write(dev, HDRPRO_COE(5), val); + +err: + return ret; +} + +static int vi_pre_set_hdrpro_black_para(struct vi_pre_dev *dev, void *args) +{ + int ret = 0; + unsigned int val = 0; + struct hdrpro_black_para black_para; + + check_retval(copy_from_user(&black_para, args, sizeof(black_para))); + val = vi_pre_read(dev, HDRPRO_COE(1)); + val &= ~HDRPRO_COE1_BE_BLACK_WR_MASK; + val |= (black_para.weight_para.wr << HDRPRO_COE1_BE_BLACK_WR_SHIFT); + val &= ~HDRPRO_COE1_BE_BLACK_WB_MASK; + val |= (black_para.weight_para.wb << HDRPRO_COE1_BE_BLACK_WB_SHIFT); + val &= ~HDRPRO_COE1_BE_BLACK_WG0_MASK; + val |= (black_para.weight_para.wg0 << HDRPRO_COE1_BE_BLACK_WG0_SHIFT); + val &= ~HDRPRO_COE1_BE_BLACK_WG1_MASK; + val |= (black_para.weight_para.wg1 << HDRPRO_COE1_BE_BLACK_WG1_SHIFT); + vi_pre_write(dev, HDRPRO_COE(1), val); + +err: + return ret; +} + +static int vi_pre_set_hdrpro_resolution(struct vi_pre_dev *dev, void *args) +{ + int ret = 0; + unsigned int val = 0; + struct hdrpro_resolution resolution; + + check_retval(copy_from_user(&resolution, args, sizeof(resolution))); + val = vi_pre_read(dev, HDRPRO_CTRL(2)); + val &= ~HDRPRO_CTRL2_VERTICAL_MASK; + val |= (resolution.height << HDRPRO_CTRL2_VERTICAL_SHIFT); + val &= ~HDRPRO_CTRL2_HORIZON_MASK; + val |= (resolution.width << HDRPRO_CTRL2_HORIZON_SHIFT); + vi_pre_write(dev, HDRPRO_CTRL(2), val); + + return ret; +} + +static int vi_pre_set_hdrpro_mode(struct vi_pre_dev *dev, void *args) +{ + int ret = 0; + unsigned int val = 0; + struct hdrpro_mode mode; + + check_retval(copy_from_user(&mode, args, sizeof(mode))); + val = vi_pre_read(dev, HDRPRO_CTRL(1)); + val &= ~HDRPRO_CTRL1_BAYER_MODSEL_MASK; + val |= mode.bayer_modesel; + val &= ~HDRPRO_CTRL1_COLOR_MODSEL_MASK; + val |= mode.color_modesel; + val &= ~HDRPRO_CTRL1_HDRPRO_RAWMOD_MASK; + val |= mode.raw_mode; + vi_pre_write(dev, HDRPRO_CTRL(1), val); + + return ret; +} + +static int vi_pre_hdrpro_en(struct vi_pre_dev *dev, int en) +{ + int ret = 0; + unsigned int val = 0; + val = vi_pre_read(dev, HDRPRO_CTRL(1)); + val &= ~HDRPRO_CTRL1_HDRPRO_EN_MASK; + val |= en; + vi_pre_write(dev, HDRPRO_CTRL(1), val); + + return ret; +} + +static int vi_pre_set_mipi2dma_n_line(struct vi_pre_dev *dev, void *args) +{ +#define WIDTH 640 +#define HEIGHT 480 +#define RAW_SIZE 16 //RAW12 +#define BURST_LEN 16 +#define OUT_STANDING 1024 +//K > N, N>2 +#define K_LINE 32 +#define N_LINE 16 + + int ret = 0; + unsigned int val = 0; + unsigned int stride = 0; + unsigned int horizon_cnt128 = 0; + unsigned int readnum = 0; + + stride = WIDTH * RAW_SIZE / 8; + horizon_cnt128 = stride / 16; + readnum = horizon_cnt128 / BURST_LEN; + + //base mode config + //val = vi_pre_read(dev, MIPI2DMA_CTRL(0)); + val = 0; + val |= MIPI2DMA_CTRL0_MODE_N_LINE; + val |= MIPI2DMA_CTRL0_RAW10; + val |= MIPI2DMA_CTRL0_HIGH_BIT_MODE; + //val |= MIPI2DMA_CTRL0_4_FRAME; + vi_pre_write(dev, MIPI2DMA_CTRL(0), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(1)); + val = 0; + val |= MIPI2DMA_CTRL1_WBURSTLEN_16; + val |= ((OUT_STANDING - 1) << MIPI2DMA_CTRL1_WOSNUM_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(1), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(3)); + val = 0; + val |= (WIDTH << MIPI2DMA_CTRL3_HORIZON_SHIFT); + val |= (HEIGHT << MIPI2DMA_CTRL3_VERTICAL_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(3), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(4)); + val = 0; + //need calculate BURSTREM by unsing the function from vipre doc + val |= (BURST_LEN << MIPI2DMA_CTRL4_BURSTREM_SHIFT); + val |= (readnum << MIPI2DMA_CTRL4_READNUM_SHIFT); + val |= (horizon_cnt128 << MIPI2DMA_CTRL4_HORIZON_CNT128_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(4), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(5)); + val = 0; + val |= (N_LINE << MIPI2DMA_CTRL5_N_NLINENUM_SHIFT); + val |= (K_LINE << MIPI2DMA_CTRL5_N_LINENUM_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(5), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(6)); + val = 0; + val |= (stride << MIPI2DMA_CTRL6_N_STRIDE_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(6), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(51)); + val |= MIPI2DMA_CTRL51_CROSS_4K_EN; + vi_pre_write(dev, MIPI2DMA_CTRL(51), val); + + //feedback config to default + //clear INV_FLAG + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(11), val); + + //clear N_LINENUM_NEW_ID0 + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(12), val); + //clear N_LINENUM_NEW_ID1 + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(13), val); + //clear N_LINENUM_NEW_ID2 + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(14), val); + + //clear N_num_done_idx + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(21), val); + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(22), val); + + //N ID0 address + //val = vi_pre_read(dev, MIPI2DMA_CTRL(15)); + val = 0; + val |= (0x0 << MIPI2DMA_CTRL15_N_SADDR_ID0_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(15), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(16)); + val = 0; + val |= (0xf0000000 << MIPI2DMA_CTRL16_N_SADDR_ID0_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(16), val); + + //N ID1 address + //val = vi_pre_read(dev, MIPI2DMA_CTRL(17)); + val = 0; + val |= (0x0 << MIPI2DMA_CTRL17_N_SADDR_ID1_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(17), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(18)); + val = 0; + val |= (0xf1000000 << MIPI2DMA_CTRL18_N_SADDR_ID1_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(18), val); + + //N ID2 address + //val = vi_pre_read(dev, MIPI2DMA_CTRL(19)); + val = 0; + val |= (0x0 << MIPI2DMA_CTRL19_N_SADDR_ID2_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(19), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(20)); + val = 0; + val |= (0xf2000000 << MIPI2DMA_CTRL20_N_SADDR_ID2_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(20), val); + + // int status clean & mask + //val = vi_pre_read(dev, MIPI2DMA_CTRL(44)); + //enable all interrupt + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(44), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(10)); + val |= MIPI2DMA_START; + vi_pre_write(dev, MIPI2DMA_CTRL(10), val); + + return ret; +} + +#if 0 +extern void test(struct vi_pre_dev *pdev); +static int vi_pre_set_mipi2dma_m_frame(struct vi_pre_dev *dev, void *args) +{ + int ret = 0; + test(dev); +#if 0 +#define WIDTH 640 +#define HEIGHT 480 +#define RAW_SIZE 16 //RAW12 +#define BURST_LEN 16 +#define OUT_STANDING 1024 + + int ret = 0; + unsigned int val = 0; + unsigned int stride = 0; + unsigned int horizon_cnt128 = 0; + unsigned int readnum = 0; + + stride = WIDTH * RAW_SIZE / 8; + horizon_cnt128 = stride / 16; + readnum = horizon_cnt128 / BURST_LEN; + + //base mode config + //val = vi_pre_read(dev, MIPI2DMA_CTRL(0)); + val = 0; + val |= MIPI2DMA_CTRL0_MODE_M_FRAME; + val |= MIPI2DMA_CTRL0_RAW10; + val |= MIPI2DMA_CTRL0_HIGH_BIT_MODE; + val |= MIPI2DMA_CTRL0_4_FRAME; + vi_pre_write(dev, MIPI2DMA_CTRL(0), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(1)); + val = 0; + val |= MIPI2DMA_CTRL1_WBURSTLEN_16; + val |= ((OUT_STANDING - 1) << MIPI2DMA_CTRL1_WOSNUM_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(1), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(3)); + val = 0; + val |= (WIDTH << MIPI2DMA_CTRL3_HORIZON_SHIFT); + val |= (HEIGHT << MIPI2DMA_CTRL3_VERTICAL_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(3), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(4)); + val = 0; + //need calculate BURSTREM by unsing the function from vipre doc + val |= (BURST_LEN << MIPI2DMA_CTRL4_BURSTREM_SHIFT); + val |= (readnum << MIPI2DMA_CTRL4_READNUM_SHIFT); + val |= (horizon_cnt128 << MIPI2DMA_CTRL4_HORIZON_CNT128_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(4), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(7)); + val = 0; + val |= (stride << MIPI2DMA_CTRL7_M0_STRIDE_SHIFT); + val |= (stride << MIPI2DMA_CTRL7_M1_STRIDE_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(7), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(8)); + val = 0; + val |= (stride << MIPI2DMA_CTRL8_M2_STRIDE_SHIFT); + val |= (stride << MIPI2DMA_CTRL8_M3_STRIDE_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(8), val); + + //M0 ADDR + val = vi_pre_read(dev, MIPI2DMA_CTRL(25)); + val |= (0x1 << MIPI2DMA_CTRL25_M0_SADDR_ID0_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(25), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(26)); + val |= (0x00000000 << MIPI2DMA_CTRL26_M0_SADDR_ID0_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(26), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(27)); + val |= (0x1 << MIPI2DMA_CTRL27_M0_SADDR_ID1_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(27), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(28)); + val |= (0x04000000 << MIPI2DMA_CTRL28_M0_SADDR_ID1_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(28), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(29)); + val |= (0x1 << MIPI2DMA_CTRL29_M0_SADDR_ID2_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(29), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(30)); + val |= (0x08000000 << MIPI2DMA_CTRL30_M0_SADDR_ID2_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(30), val); + + //M1 ADDR + val = vi_pre_read(dev, MIPI2DMA_CTRL(31)); + val |= (0x0 << MIPI2DMA_CTRL31_M1_SADDR_ID0_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(31), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(32)); + val |= (0xF3000000 << MIPI2DMA_CTRL32_M1_SADDR_ID0_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(32), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(33)); + val |= (0x0 << MIPI2DMA_CTRL33_M1_SADDR_ID1_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(33), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(34)); + val |= (0xF4000000 << MIPI2DMA_CTRL34_M1_SADDR_ID1_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(34), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(35)); + val |= (0x0 << MIPI2DMA_CTRL35_M1_SADDR_ID2_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(35), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(36)); + val |= (0xF5000000 << MIPI2DMA_CTRL36_M1_SADDR_ID2_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(36), val); + + //M2 ADDR + val = vi_pre_read(dev, MIPI2DMA_CTRL(37)); + val |= (0x0 << MIPI2DMA_CTRL37_M2_SADDR_ID0_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(37), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(38)); + val |= (0xF6000000 << MIPI2DMA_CTRL38_M2_SADDR_ID0_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(38), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(39)); + val |= (0x0 << MIPI2DMA_CTRL39_M2_SADDR_ID1_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(39), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(40)); + val |= (0xF7000000 << MIPI2DMA_CTRL40_M2_SADDR_ID1_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(40), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(41)); + val |= (0x0 << MIPI2DMA_CTRL41_M2_SADDR_ID2_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(41), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(42)); + val |= (0xF8000000 << MIPI2DMA_CTRL42_M2_SADDR_ID2_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(42), val); + + //M3 ADDR + val = vi_pre_read(dev, MIPI2DMA_CTRL(45)); + val |= (0x0 << MIPI2DMA_CTRL45_M3_SADDR_ID0_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(45), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(46)); + val |= (0xF9000000 << MIPI2DMA_CTRL46_M3_SADDR_ID0_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(46), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(47)); + val |= (0x0 << MIPI2DMA_CTRL47_M3_SADDR_ID1_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(47), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(48)); + val |= (0xFa000000 << MIPI2DMA_CTRL48_M3_SADDR_ID1_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(48), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(49)); + val |= (0x0 << MIPI2DMA_CTRL49_M3_SADDR_ID2_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(49), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(50)); + val |= (0xFb000000 << MIPI2DMA_CTRL50_M3_SADDR_ID2_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(50), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(51)); + val |= MIPI2DMA_CTRL51_CROSS_4K_EN; + vi_pre_write(dev, MIPI2DMA_CTRL(51), val); + + // feedback config to default + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(11), val); + + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(23), val); + + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(24), val); + + // int status clean & mask + //val = vi_pre_read(dev, MIPI2DMA_CTRL(44)); + //enable all interrupt + val = 0; //open all interrupt + vi_pre_write(dev, MIPI2DMA_CTRL(44), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(10)); + val |= MIPI2DMA_START; + vi_pre_write(dev, MIPI2DMA_CTRL(10), val); +#endif + return ret; +} +#endif + +static u16 read_interrupt_status(struct vi_pre_dev *dev) +{ + return vi_pre_read(dev, MIPI2DMA_CTRL(44)) & 0x1ff; +} + +static u32 mframe_frame_done_flag(struct vi_pre_dev *dev) +{ + return vi_pre_read(dev, MIPI2DMA_CTRL(43)) & 0xfff; +} + +static void mframe_frame_done_flag_clear(struct vi_pre_dev *dev, u32 mask) +{ + u32 reg_val = vi_pre_read(dev, MIPI2DMA_CTRL(43)); + reg_val |= mask; + vi_pre_write(dev, MIPI2DMA_CTRL(43), mask); +} +static int get_frame_num(struct vi_pre_dev *dev) +{ + u32 reg_val = vi_pre_read(dev, MIPI2DMA_CTRL(0)); + reg_val &= (3 << 2); + return (reg_val >> 2) + 1; +} + +static void dma_period_clear(struct vi_pre_dev *dev, int ch) +{ + u32 reg_val = vi_pre_read(dev, MIPI2DMA_CTRL(11)); + if (reg_val & (1 << ch)) { + reg_val &= ~(1 << ch); + } else { + reg_val |= (1 << ch); + } + vi_pre_write(dev, MIPI2DMA_CTRL(11), reg_val); +} +#if 0 +void vi_pre_interrupt_handler(struct vi_pre_dev *dev) +{ + u32 status = read_interrupt_status(dev); + u32 f_done_sta = 0; + int i = 0; + + if (status & VIPRE_FRAME_DONE) { + f_done_sta = mframe_frame_done_flag(dev); + for(i = 11; i >= 0; i--) { + if (f_done_sta & (1 << i)) { + if (i >= 8) { + dev->cnt[0]++; + } else if (i >= 4) { + dev->cnt[1]++; + } else { + dev->cnt[2]++; + } + } + } + mframe_frame_done_flag_clear(dev, f_done_sta); + /*TODO send event*/ + //printk("frame done %x\n", f_done_sta); + } else if (status & VIPRE_LINE_DONE) { + //u32 nline_done_sta =; + //pdriver_dev->cnt++; + //printk("line done %x\n", f_done_sta); + } + //u32 line_cnt = pdriver_dev->cnt * get_nline_int_period(pdriver_dev); + if (dev->is_mframe_mode) { + for(i = 0; i < 3; i++) { + if(dev->cnt[i] < get_frame_num(dev)) { + continue; + } + dev->cnt[i] = 0; + dma_period_clear(dev, i); + } + } +} +#endif + +typedef struct { + int glue_idx; + int h; + int v; +} vipre_resolution_cfg_t; + +int vi_pre_set_resolution(struct vi_pre_dev *dev, void *arg) +{ + u32 val = 0; + vipre_resolution_cfg_t cfg; + check_retval(copy_from_user(&cfg, arg, sizeof(cfg))); + + val = (cfg.h << 16) | cfg.v; + + if(cfg.glue_idx == 0) { + vi_pre_write(dev, G0_RESCFG, val); + vi_pre_write(dev, G0_RESCFG2, val); + vi_pre_write(dev, G0_RESCFG3, val); + } else if(cfg.glue_idx == 1) { + vi_pre_write(dev, G1_RESCFG, val); + vi_pre_write(dev, G1_RESCFG2, val); + vi_pre_write(dev, G1_RESCFG3, val); + } else if(cfg.glue_idx == 2) { + vi_pre_write(dev, G2_RESCFG, val); + vi_pre_write(dev, G2_RESCFG2, val); + vi_pre_write(dev, G2_RESCFG3, val); + } else { + return -1; + } + + return 0; +} + +typedef enum { + DDR, + ISP1, + ISP2, +}img_processor_e; + +typedef struct { + int csi_idx; + int glue_idx; + img_processor_e processor; +} vipre_pipline_t; + +static void glue0_select_csi(struct vi_pre_dev *dev, int csi_idx) +{ + unsigned int val = 0; + val = vi_pre_read(dev, G1_MUX3_2); + val &= ~(3 << 4); + val |= (csi_idx << 4); + vi_pre_write(dev, G1_MUX3_2, val); +} + +static void glue1_select_csi(struct vi_pre_dev *dev, int csi_idx) +{ + unsigned int val = 0; + val = vi_pre_read(dev, G1_MUX3_2); + val &= ~(3 << 2); + val |= (csi_idx << 2); + vi_pre_write(dev, G1_MUX3_2, val); +} + +static void glue2_select_csi(struct vi_pre_dev *dev, int csi_idx) +{ + unsigned int val = 0; + val = vi_pre_read(dev, G1_MUX3_2); + val &= ~3; + val |= csi_idx; + vi_pre_write(dev, G1_MUX3_2, val); +} + +static void isp2_select_glue(struct vi_pre_dev *dev, int glue_idx) +{ + unsigned int val = 0; + val = vi_pre_read(dev, G1_MUX3_2); + val &= ~(1 << 7); + if (glue_idx == 1) { + val |= (1 << 7); + } + vi_pre_write(dev, G1_MUX3_2, val); +} + +static void isp1_select_glue(struct vi_pre_dev *dev, int glue_idx) +{ + unsigned int val = 0; + val = vi_pre_read(dev, G1_MUX3_2); + val &= ~(1 << 6); + if (glue_idx == 2) { + val |= (1 << 6); + } + vi_pre_write(dev, G1_MUX3_2, val); +} + +static void ipi_enable(struct vi_pre_dev *dev, int ipi_idx) +{ + unsigned int val = 0; + val = vi_pre_read(dev, G1_MUX3_2); + val |= (1 << (10 - ipi_idx)); + vi_pre_write(dev, G1_MUX3_2, val); +} + +static void ipi_disable(struct vi_pre_dev *dev, int ipi_idx) +{ + unsigned int val = 0; + val = vi_pre_read(dev, G1_MUX3_2); + val &= ~(1 << (10 - ipi_idx)); + vi_pre_write(dev, G1_MUX3_2, val); +} + +static int vi_pre_reset(struct vi_pre_dev *dev, void *args) +{ + uint32_t ipi_idx = 0; + unsigned int val = 0; + check_retval(copy_from_user(&ipi_idx, args, sizeof(ipi_idx))); + + val = vi_pre_read(dev, MIPI2DMA_CTRL9); + val |= 1 << ipi_idx; + vi_pre_write(dev, MIPI2DMA_CTRL9, val); + + while(vi_pre_read(dev, MIPI2DMA_CTRL9)) { + ; + } + + val = (0x3f << 16); + vi_pre_write(dev, MIPI2DMA_CTRL44, val); + + vi_pre_write(dev, MIPI2DMA_CTRL23, 0); + vi_pre_write(dev, MIPI2DMA_CTRL24, 0); + vi_pre_write(dev, MIPI2DMA_CTRL11, 0); + vi_pre_write(dev, MIPI2DMA_CTRL12, 0); + vi_pre_write(dev, MIPI2DMA_CTRL13, 0); + vi_pre_write(dev, MIPI2DMA_CTRL14, 0); + + val = vi_pre_read(dev, MIPI2DMA_CTRL43); + vi_pre_write(dev,MIPI2DMA_CTRL43,val); + return 0; +} + +static int vi_pre_press_interror(struct vi_pre_dev *dev, void *args) +{ + uint32_t stat = (uint32_t)args; + int err_flag = 0; + + if (stat & VIPRE_BUS_ERR) { + pr_err("%s, %d, vipre bus error!\n", __func__, __LINE__); + err_flag = 1; + } + + if (stat & VIPRE_FIFO_OVER) { + pr_err("%s, %d, vipre fifo overflow!\n", __func__, __LINE__); + err_flag = 1; + } + + if (stat & VIPRE_NMOVERFLOW) { + pr_err("%s, %d, vipre nmoverflow!\n", __func__, __LINE__); + err_flag = 1; + } + + if(err_flag) { + return vi_pre_reset(dev, NULL); + } + + return 0; +} + +int vi_pre_set_pipline(struct vi_pre_dev *dev, void *arg) +{ + + vipre_pipline_t cfg; + check_retval(copy_from_user(&cfg, arg, sizeof(cfg))); + + if (cfg.glue_idx == 0) { + glue0_select_csi(dev, cfg.csi_idx); + } else if (cfg.glue_idx == 1) { + glue1_select_csi(dev, cfg.csi_idx); + if (cfg.processor == DDR) { + return -1; + } + } else if (cfg.glue_idx == 2) { + glue2_select_csi(dev, cfg.csi_idx); + if (cfg.processor == DDR) { + return -1; + } + } + + if (cfg.processor == ISP1) { + isp1_select_glue(dev, cfg.glue_idx); + } else if (cfg.processor == ISP2) { + isp2_select_glue(dev, cfg.glue_idx); + } + return 0; +} + +int vi_pre_set_ipi_mode(struct vi_pre_dev *dev, void *arg) +{ + ipi_mode_cfg_t ipi_mode; + check_retval(copy_from_user(&ipi_mode, arg, sizeof(ipi_mode))); + + switch(ipi_mode.glue_idx) { + case 0: + vi_pre_write(dev, G0_MODSEL, ipi_mode.mode); + break; + case 1: + vi_pre_write(dev, G1_MODSEL, ipi_mode.mode); + break; + case 2: + vi_pre_write(dev, G2_MODSEL, ipi_mode.mode); + break; + default: + return -1; + } + + return 0; +} + +int vi_pre_set_ipi_idnum(struct vi_pre_dev *dev, void *arg) +{ + ipi_idnum_cfg_t cfg; + uint32_t val = 0; + check_retval(copy_from_user(&cfg, arg, sizeof(cfg))); + val = cfg.id_1 | (cfg.id_2 << 2) | (cfg.id_3 << 4) + | (cfg.id_first_sync << 6) | (cfg.id_second_sync << 8) | (cfg.id_third_sync << 10); + + switch(cfg.glue_idx) { + case 0: + vi_pre_write(dev, G0_IDNUM, val); + break; + case 1: + vi_pre_write(dev, G1_IDNUM, val); + break; + case 2: + vi_pre_write(dev, G2_IDNUM, val); + break; + default: + return -1; + } + + return 0; +} + +int vi_pre_enable_ipi(struct vi_pre_dev *dev, void *arg) +{ + int ipi_idx; + check_retval(copy_from_user(&ipi_idx, arg, sizeof(ipi_idx))); + ipi_enable(dev, ipi_idx); + + return 0; +} + +int vi_pre_disable_ipi(struct vi_pre_dev *dev, void *arg) +{ + int ipi_idx; + check_retval(copy_from_user(&ipi_idx, arg, sizeof(ipi_idx))); + ipi_disable(dev, ipi_idx); + + return 0; +} + +extern int vi_pre_dma_config(struct vi_pre_dev *pdriver_dev, void *arg); +extern int vi_pre_dma_start(struct vi_pre_dev *pdriver_dev); +extern int vi_pre_dma_stop(struct vi_pre_dev *pdriver_dev); + + +unsigned int vi_pre_priv_ioctl(struct vi_pre_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + if (!dev) { + pr_err("%s invalid para\n", __func__); + return ret; + } + + switch (cmd) { + case VI_PRE_IOCTL_RESET: + ret = vi_pre_reset(dev, (void *)args); + break; + case VI_PRE_IOCTL_WRITE_REG: + ret = vi_pre_write_reg(dev, (void *)args); + break; + case VI_PRE_IOCTL_READ_REG: + ret = vi_pre_read_reg(dev, (void *)args); + break; + case VI_PRE_IOCTL_SET_IPI_RESOLUTION: + ret = vi_pre_set_resolution(dev, (void*)args); + break; + case VI_PRE_IOCTL_SET_PIPLINE: + ret = vi_pre_set_pipline(dev, (void*)args); + break; + case VI_PRE_IOCTL_SET_IPI_MODE: + ret = vi_pre_set_ipi_mode(dev, (void*)args); + break; + case VI_PRE_IOCTL_SET_IPI_IDNUM: + ret = vi_pre_set_ipi_idnum(dev, (void*)args); + break; + case VI_PRE_IOCTL_ENABLE_IPI: + ret = vi_pre_enable_ipi(dev, (void *)args); + break; + case VI_PRE_IOCTL_DISABLE_IPI: + ret = vi_pre_disable_ipi(dev, (void *)args); + break; + case VI_PRE_IOCTL_SET_MIPI2DMA_M_FRMAE: + ret = vi_pre_dma_config(dev, (void*)args); + break; + case VI_PRE_IOCTL_SET_MIPI2DMA_START: + ret = vi_pre_dma_start(dev); + break; + case VI_PRE_IOCTL_SET_MIPI2DMA_STOP: + ret = vi_pre_dma_stop(dev); + break; + case VI_PRE_IOCTL_SET_MIPI2DMA_N_LINE: + //ret = vi_pre_set_mipi2dma_n_line(dev, args); + ret = vi_pre_dma_config(dev, (void*)args); + break; + case VI_PRE_IOCTL_SET_HDRPRO_MODE: + ret = vi_pre_set_hdrpro_mode(dev, args); + break; + case VI_PRE_IOCTL_HDRPRO_ENABLE: + ret = vi_pre_hdrpro_en(dev, 1); + break; + case VI_PRE_IOCTL_HDRPRO_DISABLE: + ret = vi_pre_hdrpro_en(dev, 0); + break; + case VI_PRE_IOCTL_SET_HDRPRO_RESOLUTION: + ret = vi_pre_set_hdrpro_resolution(dev, args); + break; + case VI_PRE_IOCTL_SET_HDRPRO_BLACK_PARA: + ret = vi_pre_set_hdrpro_black_para(dev, args); + break; + case VI_PRE_IOCTL_SET_HDRPRO_COLOR_PARA: + ret = vi_pre_set_hdrpro_color_para(dev, args); + break; + case VI_PRE_IOCTL_SET_HDRPRO_MERGE_PARA: + ret = vi_pre_set_hdrpro_merge_para(dev, args); + break; + case VI_PRE_IOCTL_PRESS_INTERROR: + ret = vi_pre_press_interror(dev, args); + break; + default: + pr_err("unsupported command %d\n", cmd); + break; + } + + return ret; +} diff --git a/vvcam/native/vi_pre/vi_pre_ioctl.h b/vvcam/native/vi_pre/vi_pre_ioctl.h new file mode 100755 index 0000000..4b25b19 --- /dev/null +++ b/vvcam/native/vi_pre/vi_pre_ioctl.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: Shenwuyi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _VI_PRE_IOC_H_ +#define _VI_PRE_IOC_H_ +#include + +struct vi_pre_reg_t { + unsigned int offset; + unsigned int value; +}; + +#define VIPER_IOCTL_MAGIC 'r' + +#define VI_PRE_IOCTL_RESET _IOWR(VIPER_IOCTL_MAGIC, 1, int) +#define VI_PRE_IOCTL_WRITE_REG _IOWR(VIPER_IOCTL_MAGIC, 2, int) +#define VI_PRE_IOCTL_READ_REG _IOWR(VIPER_IOCTL_MAGIC, 3, int) +#define VI_PRE_IOCTL_SET_IPI_RESOLUTION _IOWR(VIPER_IOCTL_MAGIC, 4, int) +#define VI_PRE_IOCTL_SET_PIPLINE _IOWR(VIPER_IOCTL_MAGIC, 5, int) +#define VI_PRE_IOCTL_SET_IPI_MODE _IOWR(VIPER_IOCTL_MAGIC, 6, int) +#define VI_PRE_IOCTL_SET_IPI_IDNUM _IOWR(VIPER_IOCTL_MAGIC, 7, int) +#define VI_PRE_IOCTL_ENABLE_IPI _IOWR(VIPER_IOCTL_MAGIC, 8, int) +#define VI_PRE_IOCTL_DISABLE_IPI _IOWR(VIPER_IOCTL_MAGIC, 9, int) +#define VI_PRE_IOCTL_SET_MIPI2DMA_M_FRMAE _IOWR(VIPER_IOCTL_MAGIC, 10, int) +#define VI_PRE_IOCTL_SET_MIPI2DMA_N_LINE _IOWR(VIPER_IOCTL_MAGIC, 11, int) +#define VI_PRE_IOCTL_SET_MIPI2DMA_START _IOWR(VIPER_IOCTL_MAGIC, 12, int) +#define VI_PRE_IOCTL_SET_MIPI2DMA_STOP _IOWR(VIPER_IOCTL_MAGIC, 13, int) +#define VI_PRE_IOCTL_SET_HDRPRO_MODE _IOWR(VIPER_IOCTL_MAGIC, 14, int) +#define VI_PRE_IOCTL_SET_HDRPRO_RESOLUTION _IOWR(VIPER_IOCTL_MAGIC, 15, int) +#define VI_PRE_IOCTL_SET_HDRPRO_BLACK_PARA _IOWR(VIPER_IOCTL_MAGIC, 16, int) +#define VI_PRE_IOCTL_SET_HDRPRO_COLOR_PARA _IOWR(VIPER_IOCTL_MAGIC, 17, int) +#define VI_PRE_IOCTL_SET_HDRPRO_MERGE_PARA _IOWR(VIPER_IOCTL_MAGIC, 18, int) +#define VI_PRE_IOCTL_PRESS_INTERROR _IOWR(VIPER_IOCTL_MAGIC, 19, int) +#define VI_PRE_IOCTL_HDRPRO_ENABLE _IOWR(VIPER_IOCTL_MAGIC, 20, int) +#define VI_PRE_IOCTL_HDRPRO_DISABLE _IOWR(VIPER_IOCTL_MAGIC, 21, int) +#define VI_PRE_IOCTL_MAX _IOWR(VIPER_IOCTL_MAGIC, 22, int) + +typedef enum { + ipi_mode_nomal = 0, + ipi_mode_hdr_2_frame, + ipi_mode_hdr_3_frame, + ipi_mode_sony_dol_hdr_2_frame, + ipi_mode_sony_dol_hdr_3_frame, +} ipi_mode_t; + +typedef struct { + int glue_idx; + ipi_mode_t mode; +} ipi_mode_cfg_t; + +typedef struct { + int glue_idx; + int id_third_sync; + int id_second_sync; + int id_first_sync; + int id_3; + int id_2; + int id_1; +}ipi_idnum_cfg_t; + +enum hdrpro_raw_mode { + //RAWMOD_HDRPRO + HDRPRO_RAW6 = 0 << 21, + HDRPRO_RAW7 = 1 << 21, + HDRPRO_RAW8 = 2 << 21, + HDRPRO_RAW10 = 3 << 21, + HDRPRO_RAW12 = 4 << 21, +}; + +enum hdrpro_bayer_modesl { + //BAYER_MODSEL + HDRPRO_BAYER_MODSEL_BAYER_A = 0 << 19, + HDRPRO_BAYER_MODSEL_BAYER_B = 1 << 19, + HDRPRO_BAYER_MODSEL_BAYER_C = 2 << 19, + HDRPRO_BAYER_MODSEL_BAYER_D = 3 << 19, +}; + +enum hdrpro_color_modesl { + //COLOR_MODSEL + HDRPRO_COLOR_MODSEL_BLACK_NODOWN_2X2 = 0 << 16, + HDRPRO_COLOR_MODSEL_BLACK_DOWN_2X2 = 1 << 16, + HDRPRO_COLOR_MODSEL_RGB_NODOWN_2X2 = 2 << 16, + HDRPRO_COLOR_MODSEL_RGB_DOWN_2X2 = 3 << 16, + HDRPRO_COLOR_MODSEL_RGB_NODOWN_3X3 = 4 << 16, + HDRPRO_COLOR_MODSEL_RGB_DOWN_3X3 = 5 << 16, +}; + +enum hdrpro_enable { + //HDRPRO_EN + HDRPRO_BYPASS = 0 << 0, + HDRPRO_EN = 1 << 0 +}; + +// need to use bit length to define para after the final register map released +struct hdrpro_para { + unsigned int para[16]; +}; + +// need to use bit length to define para after the final register map released +struct hdrpro_black_weight_para { + unsigned int wr; + unsigned int wb; + unsigned int wg0; + unsigned int wg1; +}; + +// need to use bit length to define para after the final register map released +struct hdrpro_color_weight_para { + unsigned int pattern_00; + unsigned int pattern_01; + unsigned int pattern_02; + unsigned int pattern_10; + unsigned int pattern_11; + unsigned int pattern_12; + unsigned int pattern_20; + unsigned int pattern_21; + unsigned int pattern_22; +}; + +// need to use bit length to define para after the final register map released +struct hdrpro_black_para { + struct hdrpro_black_weight_para weight_para; +}; + +struct hdrpro_merge_para { + struct hdrpro_para a; + struct hdrpro_para b; + struct hdrpro_para w; +}; + +// need to use bit length to define para after the final register map released +struct hdrpro_color_para { + struct hdrpro_color_weight_para wr; + struct hdrpro_color_weight_para wb; + struct hdrpro_color_weight_para wg0; + struct hdrpro_color_weight_para wg1; +}; + +// need to use bit length to define para after the final register map released +struct hdrpro_mode { + enum hdrpro_raw_mode raw_mode; + enum hdrpro_bayer_modesl bayer_modesel; + enum hdrpro_color_modesl color_modesel; + unsigned int last_delay; + unsigned int id; +}; + +struct hdrpro_resolution { + unsigned int width; + unsigned int height; +}; + +extern unsigned int vi_pre_priv_ioctl(struct vi_pre_dev *dev, unsigned int cmd, void *args); + +#endif /* _VI_PRE_IOC_H_ */ diff --git a/vvcam/native/vi_pre/vi_pre_reg.h b/vvcam/native/vi_pre/vi_pre_reg.h new file mode 100755 index 0000000..d934457 --- /dev/null +++ b/vvcam/native/vi_pre/vi_pre_reg.h @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: Shenwuyi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _VI_PRE_REG_H_ +#define _VI_PRE_REG_H_ +#define G1_MUX3_2 0x0 +#define G1_MODSEL 0x4 +#define G1_IDNUM 0x8 +#define G1_RESCFG 0xC +#define G1_HDRCTRL0 0x10 +#define G1_HDRCTRL1 0x14 +#define G1_HDRCTRL2 0x18 +#define G1_HDRCTRL3 0x1C +#define G1_HDRCTRL4 0x20 +#define G1_ERR_MAKS 0x24 +#define G1_VMARGINCFG_IPI1 0x28 +#define G1_HMARGINCFG_IPI1 0x2C +#define G1_VMARGINCFG_IPI2 0x30 +#define G1_HMARGINCFG_IPI2 0x34 +#define G1_VMARGINCFG_IPI3 0x38 +#define G1_HMARGINCFG_IPI3 0x3C +#define G1_RESCFG2 0x40 +#define G1_RESCFG3 0x44 +#define G2_RESEV 0x48 +#define G2_MODSEL 0x4C +#define G2_IDNUM 0x50 +#define G2_RESCFG 0x54 +#define G2_HDRCTRL0 0x58 +#define G2_HDRCTRL1 0x5C +#define G2_HDRCTRL2 0x60 +#define G2_HDRCTRL3 0x64 +#define G2_HDRCTRL4 0x68 +#define G2_ERR_MAKS 0x6C +#define G2_VMARGINCFG_IPI1 0x70 +#define G2_HMARGINCFG_IPI1 0x74 +#define G2_VMARGINCFG_IPI2 0x78 +#define G2_HMARGINCFG_IPI2 0x7C +#define G2_VMARGINCFG_IPI3 0x80 +#define G2_HMARGINCFG_IPI3 0x84 +#define G2_RESCFG2 0x88 +#define G2_RESCFG3 0x8C +#define ISPSEL 0x90 +#define HDRPRO_CTRL1 0x94 +#define HDRPRO_CTRL2 0x98 +#define HDRPRO_COE1 0x9C +#define HDRPRO_COE2 0xA0 +#define HDRPRO_COE3 0xA4 +#define HDRPRO_COE4 0xA8 +#define HDRPRO_COE5 0xAC +#define HDRPRO_LINW1 0xB0 +#define HDRPRO_LINW2 0xB4 +#define HDRPRO_LINW3 0xB8 +#define HDRPRO_LINW4 0xBC +#define HDRPRO_LINW5 0xC0 +#define HDRPRO_LINW6 0xC4 +#define HDRPRO_LINW7 0xC8 +#define HDRPRO_LINW8 0xCC +#define HDRPRO_LINA1 0xD0 +#define HDRPRO_LINA2 0xD4 +#define HDRPRO_LINA3 0xD8 +#define HDRPRO_LINA4 0xDC +#define HDRPRO_LINA5 0xE0 +#define HDRPRO_LINA6 0xE4 +#define HDRPRO_LINA7 0xE8 +#define HDRPRO_LINA8 0xEC +#define HDRPRO_LINA9 0xF0 +#define HDRPRO_LINA10 0xF4 +#define HDRPRO_LINA11 0xF8 +#define HDRPRO_LINA12 0xFC +#define HDRPRO_LINA13 0x100 +#define HDRPRO_LINA14 0x104 +#define HDRPRO_LINA15 0x108 +#define HDRPRO_LINA16 0x10C +#define HDRPRO_LINB1 0x110 +#define HDRPRO_LINB2 0x114 +#define HDRPRO_LINB3 0x118 +#define HDRPRO_LINB4 0x11C +#define HDRPRO_LINB5 0x120 +#define HDRPRO_LINB6 0x124 +#define HDRPRO_LINB7 0x128 +#define HDRPRO_LINB8 0x12C +#define HDRPRO_LINB9 0x130 +#define HDRPRO_LINB10 0x134 +#define HDRPRO_LINB11 0x138 +#define HDRPRO_LINB12 0x13C +#define HDRPRO_LINB13 0x140 +#define HDRPRO_LINB14 0x144 +#define HDRPRO_LINB15 0x148 +#define HDRPRO_LINB16 0x14C +#define G0_RESEV 0x150 +#define G0_MODSEL 0x154 +#define G0_IDNUM 0x158 +#define G0_RESCFG 0x15C +#define G0_HDRCTRL0 0x160 +#define G0_HDRCTRL1 0x164 +#define G0_HDRCTRL2 0x168 +#define G0_HDRCTRL3 0x16C +#define G0_HDRCTRL4 0x170 +#define G0_ERR_MAKS 0x174 +#define G0_VMARGINCFG_IPI1 0x178 +#define G0_HMARGINCFG_IPI1 0x17C +#define G0_VMARGINCFG_IPI2 0x180 +#define G0_HMARGINCFG_IPI2 0x184 +#define G0_VMARGINCFG_IPI3 0x188 +#define G0_HMARGINCFG_IPI3 0x18C +#define G0_RESCFG2 0x190 +#define G0_RESCFG3 0x194 +#define MIPI2DMA_CTRL0 0x198 +#define MIPI2DMA_CTRL1 0x19C +#define MIPI2DMA_CTRL2 0x1A0 +#define MIPI2DMA_CTRL3 0x1A4 +#define MIPI2DMA_CTRL4 0x1A8 +#define MIPI2DMA_CTRL5 0x1AC +#define MIPI2DMA_CTRL6 0x1B0 +#define MIPI2DMA_CTRL7 0x1B4 +#define MIPI2DMA_CTRL8 0x1B8 +#define MIPI2DMA_CTRL9 0x1BC +#define MIPI2DMA_CTRL10 0x1C0 +#define MIPI2DMA_CTRL11 0x1C4 +#define MIPI2DMA_CTRL12 0x1C8 +#define MIPI2DMA_CTRL13 0x1CC +#define MIPI2DMA_CTRL14 0x1D0 +#define MIPI2DMA_CTRL15 0x1D4 +#define MIPI2DMA_CTRL16 0x1D8 +#define MIPI2DMA_CTRL17 0x1DC +#define MIPI2DMA_CTRL18 0x1E0 +#define MIPI2DMA_CTRL19 0x1E4 +#define MIPI2DMA_CTRL20 0x1E8 +#define MIPI2DMA_CTRL21 0x1EC +#define MIPI2DMA_CTRL22 0x1F0 +#define MIPI2DMA_CTRL23 0x1F4 +#define MIPI2DMA_CTRL24 0x1F8 +#define MIPI2DMA_CTRL25 0x1FC +#define MIPI2DMA_CTRL26 0x200 +#define MIPI2DMA_CTRL27 0x204 +#define MIPI2DMA_CTRL28 0x208 +#define MIPI2DMA_CTRL29 0x20C +#define MIPI2DMA_CTRL30 0x210 +#define MIPI2DMA_CTRL31 0x214 +#define MIPI2DMA_CTRL32 0x218 +#define MIPI2DMA_CTRL33 0x21C +#define MIPI2DMA_CTRL34 0x220 +#define MIPI2DMA_CTRL35 0x224 +#define MIPI2DMA_CTRL36 0x228 +#define MIPI2DMA_CTRL37 0x22C +#define MIPI2DMA_CTRL38 0x230 +#define MIPI2DMA_CTRL39 0x234 +#define MIPI2DMA_CTRL40 0x238 +#define MIPI2DMA_CTRL41 0x23C +#define MIPI2DMA_CTRL42 0x240 +#define MIPI2DMA_CTRL43 0x244 +#define MIPI2DMA_CTRL44 0x248 +#define MIPI2DMA_CTRL45 0x24C +#define MIPI2DMA_CTRL46 0x250 +#define MIPI2DMA_CTRL47 0x254 +#define MIPI2DMA_CTRL48 0x258 +#define MIPI2DMA_CTRL49 0x25C +#define MIPI2DMA_CTRL50 0x260 +#define MIPI2DMA_CTRL51 0x264 +#endif /*_VI_PRE_REG_H_*/ diff --git a/vvcam/native/video/Makefile b/vvcam/native/video/Makefile new file mode 100755 index 0000000..197fe85 --- /dev/null +++ b/vvcam/native/video/Makefile @@ -0,0 +1,22 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = thead_video + +obj-m +=$(TARGET).o + +$(TARGET)-objs += video.o +$(TARGET)-objs += video_sysfs.o +$(TARGET)-objs += video_hw_info.o +$(TARGET)-objs += subdev.o + +EXTRA_CFLAGS += -I$(PWD)/../../common + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean diff --git a/vvcam/native/video/subdev.c b/vvcam/native/video/subdev.c new file mode 100755 index 0000000..03b3a5e --- /dev/null +++ b/vvcam/native/video/subdev.c @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2021 Alibaba Group. All rights reserved. + * License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +#include +#include "video.h" +#include "video_ioctl.h" +#include "subdev.h" + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) ( sizeof(arr) / sizeof((arr)[0]) ) +#endif + +static void dump_dts_frame_cfg(subdev_dts_frame_cfg_t *frame_cfg) +{ + video_info(">>>> dump_dts_frame_cfg begin >>>>\n"); + + video_info("\t idx = %u\n", frame_cfg->idx); + video_info("\t name = %s\n", frame_cfg->output_name); + video_info("\t max_width = %u\n", frame_cfg->max_width); + video_info("\t max_height = %u\n", frame_cfg->max_height); + video_info("\t bit_per_pixel = %d\n", frame_cfg->bit_per_pixel); + video_info("\t frame_count = %u\n", frame_cfg->frame_count); + + video_info("<<<< dump_dts_frame_cfg end <<<<\n"); +} + +static void init_dts_frame_cfg(subdev_dts_frame_cfg_t *frame_cfg) +{ + if (frame_cfg == NULL) { + video_err("frame_cfg is NULL\n"); + return; + } + + frame_cfg->idx = -1; + frame_cfg->max_width = 0; + frame_cfg->max_height = 0; + frame_cfg->bit_per_pixel = 12; + frame_cfg->frame_count = 2; + strcpy(frame_cfg->output_name, "unknown"); +} + +static int subdev_get_dts_frame_cfg(struct fwnode_handle *node, subdev_dts_frame_cfg_t *frame_cfg) +{ + if (frame_cfg == NULL) { + video_err("frame_cfg is NULL\n"); + return -1; + } + + fwnode_property_read_u32_array(node, "max_width", &frame_cfg->max_width, 1); + fwnode_property_read_u32_array(node, "max_height", &frame_cfg->max_height, 1); + fwnode_property_read_u32_array(node, "bit_per_pixel", &frame_cfg->bit_per_pixel, 1); + fwnode_property_read_u32_array(node, "frame_count", &frame_cfg->frame_count, 1); + return 0; +} + +static int sensor_press_dts(struct fwnode_handle *node, sub_dev_info_t *subdev) +{ + //int ret = 0; + //const char *path; +/* + ret = fwnode_property_read_string(node, "path_type", &path); + if (ret != 0) { + video_err("sensor dts press error!!!!!, %s, %d\n", __func__, __LINE__); + goto error; + } + */ + int ret = 0; + + uint32_t csi_idx, flash_led_idx; + + ret = fwnode_property_read_u32_array(node, "csi_idx", &csi_idx, 1); + if(ret != 0) { + return -1; + } + + ret = fwnode_property_read_u32_array(node, "flash_led_idx", &flash_led_idx, 1); + if(ret != 0) { + flash_led_idx = -1; + } + + video_info("flash_led idx is %u\n", flash_led_idx); + + subdev->param[0] = (char)csi_idx; + subdev->param[1] = fwnode_property_read_bool(node, "skip_init"); + subdev->param[2] = (char)flash_led_idx; + video_info("subdev->param[0] is %d\n", subdev->param[0]); + video_info("subdev->param[2] is %d\n", subdev->param[2]); + subdev->param_size = 3; + return 0; +} + +static int vipre_press_dts(struct fwnode_handle *node, sub_dev_info_t *subdev) +{ + //int ret = 0; + //const char *path; + vipre_ipi_dts_arg_t param; + param.dma_mode = 111; +/* + ret = fwnode_property_read_string(node, "path_type", &path); + if (ret != 0) { + video_err("sensor dts press error!!!!!, %s, %d\n", __func__, __LINE__); + goto error; + } + */ + + memcpy(subdev->param, ¶m, sizeof(vipre_ipi_dts_arg_t)); + subdev->param_size = sizeof(vipre_ipi_dts_arg_t); + + return 0; +} + +static int isp_press_dts(struct fwnode_handle *node, sub_dev_info_t *subdev) +{ + int ret = 0; + int idx; + const char *path; + + isp_dts_arg_t param; + struct fwnode_handle *child; + + subdev_dts_frame_cfg_t *dts_frame_cfg = &(param.dts_path_frame_cfg); + init_dts_frame_cfg(dts_frame_cfg); + + child = fwnode_get_named_child_node(node, "output"); + if (child == NULL) { + subdev->param_size = 0; + return 0; // return with all default values + } + + ret = subdev_get_dts_frame_cfg(child, dts_frame_cfg); + if (ret == 0) { + fwnode_property_read_u32_array(node, "idx", &idx, 1); + dts_frame_cfg->idx = idx; + + fwnode_property_read_string(node, "path_type", &path); + snprintf(dts_frame_cfg->output_name, sizeof(dts_frame_cfg->output_name), "isp%d:%s", idx, path); + + dump_dts_frame_cfg(dts_frame_cfg); + } + else { + video_err("%s, subdev_get_dts_frame_cfg() failed, ret=%d\n", __func__, ret); + subdev->param_size = 0; + return -1; + } + + memcpy(subdev->param, ¶m, sizeof(subdev_dts_frame_cfg_t)); + subdev->param_size = sizeof(isp_dts_arg_t); + + return 0; +} + +static int ry_press_dts(struct fwnode_handle *node, sub_dev_info_t *subdev) +{ + int ret = 0; + int idx; + const char *path; + + ry_dts_arg_t param; + struct fwnode_handle *child; + + subdev_dts_frame_cfg_t *dts_frame_cfg = &(param.dts_path_frame_cfg); + init_dts_frame_cfg(dts_frame_cfg); + + child = fwnode_get_named_child_node(node, "output"); + if (child == NULL) { + subdev->param_size = 0; + return 0; // return with all default values + } + + ret = subdev_get_dts_frame_cfg(child, dts_frame_cfg); + if (ret == 0) { + fwnode_property_read_u32_array(node, "idx", &idx, 1); + dts_frame_cfg->idx = idx; + + fwnode_property_read_string(node, "path_type", &path); + snprintf(dts_frame_cfg->output_name, sizeof(dts_frame_cfg->output_name), "ry%d:%s", idx, path); + + dump_dts_frame_cfg(dts_frame_cfg); + } + else { + video_err("%s, subdev_get_dts_frame_cfg() failed, ret=%d\n", __func__, ret); + subdev->param_size = 0; + return -1; + } + + memcpy(subdev->param, ¶m, sizeof(subdev_dts_frame_cfg_t)); + subdev->param_size = sizeof(ry_dts_arg_t); + + return 0; +} + +static int dw_parse_dts(struct fwnode_handle *node, sub_dev_info_t *subdev) +{ + int idx; + const char *path; + int dw_dst_depth; + + dw_dts_arg_t param; + + dw_dst_depth = 2; // init + + fwnode_property_read_u32_array(node, "idx", &idx, 1); + fwnode_property_read_string(node, "path_type", &path); + fwnode_property_read_u32_array(node, "dw_dst_depth", &dw_dst_depth, 1); + param.dw_dst_depth = dw_dst_depth; + video_info(">>>> dump dw_dts_arg_t begin >>>>\n"); + video_info("\t idx = %d\n", idx); + video_info("\t path_type = %s\n", path); + video_info("\t dw_dst_depth = %d\n", dw_dst_depth); + video_info("<<<< dump dw_dts_arg_t end <<<<\n"); + + memcpy(subdev->param, ¶m, sizeof(dw_dts_arg_t)); + subdev->param_size = sizeof(dw_dts_arg_t); + + return 0; +} + +static int dsp_press_dts(struct fwnode_handle *node, sub_dev_info_t *subdev) +{ + int ret = 0; + int idx; + const char *path; + + dsp_dts_arg_t param; + struct fwnode_handle *child; + + subdev_dts_frame_cfg_t *dts_frame_cfg = &(param.dts_path_frame_cfg); + init_dts_frame_cfg(dts_frame_cfg); + + child = fwnode_get_named_child_node(node, "output"); + if (child == NULL) { + subdev->param_size = 0; + return 0; // return with all default values + } + + ret = subdev_get_dts_frame_cfg(child, dts_frame_cfg); + if (ret == 0) { + fwnode_property_read_u32_array(node, "idx", &idx, 1); + dts_frame_cfg->idx = idx; + + fwnode_property_read_string(node, "path_type", &path); + snprintf(dts_frame_cfg->output_name, sizeof(dts_frame_cfg->output_name), "dsp%d:%s", idx, path); + + dump_dts_frame_cfg(dts_frame_cfg); + } + else { + video_err("%s, subdev_get_dts_frame_cfg() failed, ret=%d\n", __func__, ret); + subdev->param_size = 0; + return -1; + } + + memcpy(subdev->param, ¶m, sizeof(dsp_dts_arg_t)); + subdev->param_size = sizeof(dsp_dts_arg_t); + + return 0; + +} + +static subdev_dts_press_t subdev_dts_press[] = { + {.subdev_name = "vivcam", .press = sensor_press_dts}, + {.subdev_name = "vipre", .press = vipre_press_dts}, + {.subdev_name = "isp", .press = isp_press_dts}, + {.subdev_name = "ry", .press = ry_press_dts}, + {.subdev_name = "dw", .press = dw_parse_dts}, + {.subdev_name = "dsp", .press = dsp_press_dts}, +}; + +int video_subdev_press_dts(struct fwnode_handle *node, sub_dev_info_t *subdev) +{ + int i = 0; + for (i = 0; i < sizeof(subdev_dts_press) / sizeof(subdev_dts_press[0]); i++) { + if (strcmp(subdev_dts_press[i].subdev_name, subdev->name) == 0) { + return subdev_dts_press[i].press(node, subdev); + } + } + + return -1; +} diff --git a/vvcam/native/video/subdev.h b/vvcam/native/video/subdev.h new file mode 100755 index 0000000..cccfddb --- /dev/null +++ b/vvcam/native/video/subdev.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2021 Alibaba Group. All rights reserved. + * License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +#ifndef _THEAD_SUBDEV_H_ +#define _THEAD_SUBDEV_H_ + +#ifdef __KERNEL__ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + char name[40]; + int path; + int idx; + int param_size; + char param[400]; +} sub_dev_info_t; + +typedef struct { + char subdev_name[40]; + int (*press)(struct fwnode_handle *node, sub_dev_info_t *subdev); +} subdev_dts_press_t; + +int video_subdev_press_dts(struct fwnode_handle *node, sub_dev_info_t *subdev); + +#endif // __KERNEL__ + +typedef enum { + VIPRE_MFRAME, + VIPRE_NLINE, +} vipre_dam_mode_e; + +typedef struct { + vipre_dam_mode_e dma_mode; +} vipre_ipi_dts_arg_t; + +typedef struct { + // Converting refer to TuningRyChlCfg + // Field Default Value (init_dts_frame_cfg) Sample + uint32_t idx; // default: 0 idx = <0>; + uint32_t max_width; // default: 0 (same as input) max_width = <640>; + uint32_t max_height; // default: 0 (same as input) max_height = <480>; + uint32_t frame_count; // default: 2 frame_count = <2>; + uint32_t bit_per_pixel; // default: 12 bit_per_pixel = 12; + char output_name[32]; // default: "unknown" name = "isp0:output[0]"; +} subdev_dts_frame_cfg_t; + +typedef struct { + subdev_dts_frame_cfg_t dts_path_frame_cfg; +} isp_dts_arg_t; + +typedef struct { + subdev_dts_frame_cfg_t dts_path_frame_cfg; +} ry_dts_arg_t; + +typedef struct { + uint32_t dw_dst_depth; +} dw_dts_arg_t; + +typedef struct { + subdev_dts_frame_cfg_t dts_path_frame_cfg; +} dsp_dts_arg_t; + +#endif /*_THEAD_SUBDEV_H_*/ diff --git a/vvcam/native/video/video.c b/vvcam/native/video/video.c new file mode 100755 index 0000000..c0236b5 --- /dev/null +++ b/vvcam/native/video/video.c @@ -0,0 +1,385 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "video.h" +#include "video_ioctl.h" + +#define VIDEO_DRIVER_NAME "video" +#define VIDEO_DRIVER_MAXCNT 100 + + +static struct class *video_driver_class; +static unsigned int video_driver_major = 0; +static unsigned int video_driver_minor = 0; +static unsigned int device_register_index = 0; + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +static unsigned int video_poll(struct file * filp, poll_table *wait) +{ + return 0; +} + +void video_work(struct work_struct *work) +{ + +} + +irqreturn_t video_irq(int irq, void *dev_id) +{ + video_info("enter %s\n", __func__); + return IRQ_HANDLED; +} + +static int video_open(struct inode * inode, struct file * file) +{ + struct video_drvdata *drvdata; + drvdata = container_of(inode->i_cdev, struct video_drvdata, cdev); + file->private_data = drvdata; + + return 0; +}; + +static int video_get_pipelines(struct video_drvdata *drvdata, void *__user args) +{ + pipline_t *usr_pip = (pipline_t *)args; + pipline_t *cam_pip = drvdata->piplines; + + check_retval(copy_to_user(usr_pip, cam_pip, sizeof(pipline_t) * drvdata->pipline_num)); + video_info("%s, %d, pipnmu: %d\n", __func__, __LINE__, drvdata->pipline_num); + return 0; +} + +static int video_get_pipelines_num (struct video_drvdata *drvdata, void *__user args) +{ + check_retval(copy_to_user(args, &drvdata->pipline_num, sizeof(int))); + return 0; +} + +static int video_set_path_type(struct video_drvdata *drvdata, void *__user args) +{ + pathtype_set_t pathtype_set; + check_retval(copy_from_user(&pathtype_set, args, sizeof(pathtype_set_t))); + video_info("VIDEO_SET_PATH_TYPE pipeline=%d sensor=%s path_type%d ", pathtype_set.pipeline_id , pathtype_set.sensor_name, pathtype_set.path_type); + return 0; +} + +static int video_get_mem_pool_region_id(struct video_drvdata *drvdata, void *__user args) +{ + check_retval(copy_to_user(args, &drvdata->vi_mem_pool_region_id, sizeof(int))); + return 0; +} + +static long video_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct video_drvdata *drvdata; + + drvdata = file->private_data; + if (drvdata == NULL) { + video_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + mutex_lock(&drvdata->mutex); + switch (cmd) { + case VIDEO_GET_PIPLANES: + ret = video_get_pipelines(drvdata, (void *)arg); + break; + case VIDEO_GET_PIPLANES_NUM: + ret = video_get_pipelines_num(drvdata, (void *)arg); + break; + case VIDEO_SET_PATH_TYPE: + ret = video_set_path_type(drvdata, (void *)arg); + break; + case VIDEO_GET_MEM_POOL_REGION_ID: + ret = video_get_mem_pool_region_id(drvdata, (void *)arg); + break; + default: + ret = -EPERM; + video_err("%s: unsupported command %d", __func__, cmd); + break; + } + mutex_unlock(&drvdata->mutex); + return ret; +}; + +static int video_release(struct inode * inode, struct file * file) +{ + return 0; +}; + +static int video_mmap(struct file *pFile, struct vm_area_struct *vma) +{ + video_info("enter %s\n", __func__); + return 0; +}; + +struct file_operations video_fops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .unlocked_ioctl = video_ioctl, + .mmap = video_mmap, + .poll = video_poll, +}; + +static int video_press_pipline(pipline_t *pipline, struct fwnode_handle *pip_node) +{ + int ret = 0; + const char *dev_name; + const char *path_name; + struct fwnode_handle *nodes; + sub_dev_info_t *sub_dev = pipline->sub_dev; + + + fwnode_for_each_available_child_node(pip_node, nodes) { + ret = fwnode_property_read_string(nodes, "subdev_name", &dev_name); + if (ret != 0) { + video_err("dts press error!!!!!, %s, %d\n", __func__, __LINE__); + return -1; + } + + strcpy(sub_dev->name, dev_name); + + ret = fwnode_property_read_u32_array(nodes, "idx", &sub_dev->idx, 1); + if (ret != 0) { + video_err("dts press device :%s error!!!!!, %d, %s\n", __func__, __LINE__,dev_name); + return -1; + } + + ret = fwnode_property_read_string(nodes, "path_type", &path_name); + if (ret != 0) { + video_err("%s, %d, dts parse %s->%s error!!!!!\n", __func__, __LINE__, dev_name, path_name); + return -1; + } + + video_info("%s, %d, dev: %s->%s !!!!!\n", __func__, __LINE__, dev_name, path_name); + sub_dev->path = vedio_get_path_type(dev_name, path_name); + if(sub_dev->path < 0) { + video_err("%s, %d, %s, parse path(%s) error!!!!!\n", __func__, __LINE__, dev_name, path_name); + return -1; + } + video_info("subdev:%s-%d,path:(%s,%d)\n",dev_name,sub_dev->idx, path_name,sub_dev->path); + + ret = video_subdev_press_dts(nodes, sub_dev); + if (ret != 0) { + video_err("dts press error!!!!!, %s, %d\n", __func__, __LINE__); + return -1; + } + + sub_dev++; + pipline->sub_dev_num++; + } + + return 0; +} + +static int video_press_dts(struct platform_device *pdev) +{ + int ret = 0; + struct device *dev = &pdev->dev; + struct fwnode_handle *child; + struct video_drvdata *drvdata; + pipline_t *pipline; + int pool_region_id; + + drvdata = platform_get_drvdata(pdev); + pipline = drvdata->piplines; + + //if (device_property_read_u32(&(pdev->dev), "vi_mem_pool_region", &pool_region_id) != 0) { + if (of_property_read_s32(dev->of_node, "vi_mem_pool_region", &pool_region_id) != 0) { + video_warn("%s, dev(%s) can't get vi_mem_pool_region id from dts, set to default -1(cma)\n", + __func__, pdev->name); + pool_region_id = -1; + } + drvdata->vi_mem_pool_region_id = pool_region_id; + + device_for_each_child_node(dev, child) { + video_info("pipleline(%d):",drvdata->pipline_num); + ret = video_press_pipline(pipline, child); + if (ret != 0) { + video_err("%s, %d, dts press pipe:%d error!\n", __func__, __LINE__, drvdata->pipline_num); + return -1; + } + pipline++; + drvdata->pipline_num++; + } + + return 0; +} + +static int video_probe(struct platform_device *pdev) +{ + int ret = 0; + struct video_drvdata *drvdata; + struct device_node *np = pdev->dev.of_node; + + video_info("enter %s\n", __func__); + pdev->id = of_alias_get_id(np, "viv_video"); + + video_info("%s:pdev id is %d\n", __func__, pdev->id); + + if (pdev->id >= VIDEO_DRIVER_MAXCNT) { + video_err("%s:pdev id is %d error\n", __func__, pdev->id); + return -EINVAL; + } + + drvdata = devm_kzalloc(&pdev->dev,sizeof(struct video_drvdata), GFP_KERNEL); + if (drvdata == NULL) { + video_err("%s:alloc struct drvdata error\n", __func__); + return -ENOMEM; + } + + drvdata->device_idx = pdev->id; + mutex_init(&drvdata->mutex); + platform_set_drvdata(pdev, drvdata); + + if (device_register_index == 0) { + if (video_driver_major == 0) { + ret = alloc_chrdev_region(&drvdata->devt, 0, VIDEO_DRIVER_MAXCNT, VIDEO_DRIVER_NAME); + if (ret != 0) { + video_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + video_driver_major = MAJOR(drvdata->devt); + video_driver_minor = MINOR(drvdata->devt); + } else { + drvdata->devt = MKDEV(video_driver_major, video_driver_minor); + ret = register_chrdev_region(drvdata->devt, VIDEO_DRIVER_MAXCNT, VIDEO_DRIVER_NAME); + if (ret) { + video_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + video_driver_class = class_create(THIS_MODULE, VIDEO_DRIVER_NAME); + if (IS_ERR(video_driver_class)) { + video_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + + drvdata->devt = MKDEV(video_driver_major, video_driver_minor + pdev->id); + cdev_init(&drvdata->cdev, &video_fops); + ret = cdev_add(&drvdata->cdev, drvdata->devt, 1); + if ( ret ) { + video_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } else { + video_info("%s[%d]:cdev_add OK, major=%d, minor=%d\n", __func__, __LINE__, + video_driver_major, video_driver_minor + pdev->id); + } + + drvdata->class = video_driver_class; + device_create(drvdata->class, NULL, drvdata->devt, + drvdata, "%s%d", VIDEO_DRIVER_NAME, pdev->id); + + ret = video_press_dts(pdev); + if (ret) { + video_err("%s[%d]:dts error!\n", __func__, __LINE__); + return ret; + } + + video_create_capabilities_sysfs(pdev); + device_register_index++; + + video_info("exit %s:[%s%d]\n", __func__, VIDEO_DRIVER_NAME, pdev->id); + + return 0; +} + +static int video_remove(struct platform_device *pdev) +{ + struct video_drvdata *drvdata; + + video_info("enter %s\n", __func__); + device_register_index--; + drvdata = platform_get_drvdata(pdev); + cdev_del(&drvdata->cdev); + device_destroy(drvdata->class, drvdata->devt); + unregister_chrdev_region(drvdata->devt, VIDEO_DRIVER_MAXCNT); + mutex_destroy(&drvdata->mutex); + video_remove_capabilities_sysfs(pdev); + if (device_register_index == 0) { + class_destroy(drvdata->class); + } + devm_kfree(&pdev->dev, drvdata); + video_info("exit %s\n", __func__); + return 0; +} + +static const struct of_device_id video_of_match[] = { + { .compatible = "thead,video", }, + { /* sentinel */ }, +}; + +static struct platform_driver video_driver = { + .probe = video_probe, + .remove = video_remove, + .driver = { + .name = VIDEO_DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(video_of_match), + } +}; + +static int __init video_init_module(void) +{ + int ret = 0; + + video_info("enter %s\n", __func__); + ret = platform_driver_register(&video_driver); + if (ret) { + video_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit video_exit_module(void) +{ + video_info("enter %s\n", __func__); + platform_driver_unregister(&video_driver); +} + +module_init(video_init_module); +module_exit(video_exit_module); + +MODULE_AUTHOR("Liu Yitong"); +MODULE_DESCRIPTION("THEAD-VIDEO"); +MODULE_LICENSE("GPL"); diff --git a/vvcam/native/video/video.h b/vvcam/native/video/video.h new file mode 100755 index 0000000..9b84e07 --- /dev/null +++ b/vvcam/native/video/video.h @@ -0,0 +1,54 @@ +#ifndef _THEAD_VIDEO_H_ +#define _THEAD_VIDEO_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "subdev.h" + +#define video_info(fmt, ...) printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__) +#define video_warn(fmt, ...) printk(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__) +#define video_err(fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) + +typedef struct { + int sub_dev_num; + sub_dev_info_t sub_dev[20]; +} pipline_t; + +typedef struct video_drvdata { + struct cdev cdev; + dev_t devt; + struct class *class; + int device_idx; + struct mutex mutex; + int pipline_num; + pipline_t piplines[20]; + int vi_mem_pool_region_id; + void *private; +} video_drvdata_t; + +typedef struct { + char *subdev_name; + char *sensor_name; + unsigned int path_type; + unsigned int pipeline_id; +} pathtype_set_t; + +int video_create_capabilities_sysfs(struct platform_device *pdev); +int video_remove_capabilities_sysfs(struct platform_device *pdev); +int vedio_get_path_type(const char *subdev_name, const char *path_name); + +#endif /* _THEAD_VIDEO_H_ */ diff --git a/vvcam/native/video/video_hw_info.c b/vvcam/native/video/video_hw_info.c new file mode 100755 index 0000000..87e3db8 --- /dev/null +++ b/vvcam/native/video/video_hw_info.c @@ -0,0 +1,156 @@ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "video.h" +#include "video_kernel_defs.h" +#include "video.h" + + +typedef struct describe_comm{ + unsigned id; + char *desc; +}describe_comm_t; + +static int get_id_by_desc( describe_comm_t *,const char* ); + +#define ENUM_DESC_MAPS_DECLATR(type) static describe_comm_t describe_map_##type[]={ +#define ENUM_DESC_MAPS_ADD(str) {str,#str}, +#define ENUM_DESC_MAPS_END {-1,"end"}}; +#define GET_ENUM_BY_DESC(type,str) get_id_by_desc(describe_map_##type,str) + +/****vedio_ip_type_e string to enum map*/ +ENUM_DESC_MAPS_DECLATR(subdev) + {SENSOR, "vivcam"}, + {VIPRE, "vipre"}, + {ISP, "isp"}, + {DW, "dw"}, + {DSP, "dsp"}, + {RY, "ry"}, +ENUM_DESC_MAPS_END + +/****sensor_path_type_e string to enum map*/ +ENUM_DESC_MAPS_DECLATR(sensor) +ENUM_DESC_MAPS_ADD(SENSOR_VGA_RAW12_LINER) +ENUM_DESC_MAPS_ADD(SENSOR_1080P_RAW12_LINER) +ENUM_DESC_MAPS_ADD(SENSOR_4K_RAW12_LINER) +ENUM_DESC_MAPS_ADD(SENSOR_VGA_RAW10_LINER) +ENUM_DESC_MAPS_ADD(SENSOR_1080P_RAW10_LINER) +ENUM_DESC_MAPS_ADD(SENSOR_4K_RAW10_LINER) +ENUM_DESC_MAPS_ADD(SENSOR_2592x1944_RAW10_LINER) +ENUM_DESC_MAPS_ADD(SENSOR_1280x720_RAW10_LINER) +ENUM_DESC_MAPS_ADD(SENSOR_VGA_RAW12_HDR_2DOL) +ENUM_DESC_MAPS_ADD(SENSOR_VGA_RAW12_HDR_3DOL) +ENUM_DESC_MAPS_END + +/****isp_path_type_e string to enum map*/ +ENUM_DESC_MAPS_DECLATR(isp) +ENUM_DESC_MAPS_ADD(ISP_MI_PATH_MP) +ENUM_DESC_MAPS_ADD(ISP_MI_PATH_SP) +ENUM_DESC_MAPS_ADD(ISP_MI_PATH_SP2_BP) +#ifdef ISP_MI_MCM_WR +ENUM_DESC_MAPS_ADD(ISP_MI_MCM_WR0) +ENUM_DESC_MAPS_ADD(ISP_MI_MCM_WR1) +#endif +ENUM_DESC_MAPS_ADD(ISP_MI_PATH_PP) +ENUM_DESC_MAPS_ADD(ISP_MI_HDR_L) +ENUM_DESC_MAPS_ADD(ISP_MI_HDR_S) +ENUM_DESC_MAPS_ADD(ISP_MI_HDR_VS) +ENUM_DESC_MAPS_END + +/****vipre_path_type_e string to enum map*/ +ENUM_DESC_MAPS_DECLATR(vipre) +ENUM_DESC_MAPS_ADD(VIPRE_CSI0_DDR) +ENUM_DESC_MAPS_ADD(VIPRE_CSI1_DDR) +ENUM_DESC_MAPS_ADD(VIPRE_CSI2_DDR) +ENUM_DESC_MAPS_ADD(VIPRE_CSI0_ISP0) +ENUM_DESC_MAPS_ADD(VIPRE_CSI1_ISP0) +ENUM_DESC_MAPS_ADD(VIPRE_CSI2_ISP0) +ENUM_DESC_MAPS_ADD(VIPRE_CSI0_ISP1) +ENUM_DESC_MAPS_ADD(VIPRE_CSI1_ISP1) +ENUM_DESC_MAPS_ADD(VIPRE_CSI2_ISP1) +ENUM_DESC_MAPS_ADD(VIPRE_CSI0_LOW_COAST_HDR_ISP0) +ENUM_DESC_MAPS_ADD(VIPRE_CSI1_LOW_COAST_HDR_ISP0) +ENUM_DESC_MAPS_ADD(VIPRE_CSI2_LOW_COAST_HDR_ISP0) +ENUM_DESC_MAPS_END + +/****ry_path_type_e string to enum map*/ +ENUM_DESC_MAPS_DECLATR(ry) +ENUM_DESC_MAPS_ADD(ISP_RY_MI_PATH_MP) +ENUM_DESC_MAPS_ADD(ISP_RY_MI_PATH_SP) +ENUM_DESC_MAPS_ADD(ISP_RY_MI_PATH_SP2_BP) +ENUM_DESC_MAPS_END + +/****dsp_path_type_e string to enum map*/ + +ENUM_DESC_MAPS_DECLATR(dsp) +ENUM_DESC_MAPS_ADD(DSP_PATH_ISP_RY) +ENUM_DESC_MAPS_ADD(DSP_PATH_ISP_CPU) +ENUM_DESC_MAPS_ADD(DSP_PATH_VIPRE_DDR) +ENUM_DESC_MAPS_ADD(DSP_PATH_VIPRE_EVEN) +ENUM_DESC_MAPS_ADD(DSP_PATH_VIPRE_ODD) +ENUM_DESC_MAPS_ADD(DSP_PATH_VIPRE_RY) +ENUM_DESC_MAPS_END + +ENUM_DESC_MAPS_DECLATR(dw) +ENUM_DESC_MAPS_ADD(DW_DWE_VSE0) +ENUM_DESC_MAPS_ADD(DW_DWE_VSE1) +ENUM_DESC_MAPS_ADD(DW_DWE_VSE2) +ENUM_DESC_MAPS_END +static int get_id_by_desc(describe_comm_t* desc_list,const char* str) + { + int i=0; + while(0!=strcmp(desc_list[i].desc,"end") ) + { + if(0==strcmp(desc_list[i].desc,str)) + { + return desc_list[i].id; + } + i++; + } + return -1; + } + +vedio_ip_type_e convert_subdev_name_to_id(const char* name) +{ + return GET_ENUM_BY_DESC(subdev,name); +} + +int vedio_get_path_type(const char*subdev_name,const char* path_name) +{ + vedio_ip_type_e ip_type = GET_ENUM_BY_DESC(subdev,subdev_name); + switch(ip_type) + { + case SENSOR: + return GET_ENUM_BY_DESC(sensor,path_name); + case VIPRE: + return GET_ENUM_BY_DESC(vipre,path_name); + case ISP: + return GET_ENUM_BY_DESC(isp,path_name); + case DW: + return GET_ENUM_BY_DESC(dw,path_name); + case DSP: + return GET_ENUM_BY_DESC(dsp,path_name); + case RY: + return GET_ENUM_BY_DESC(ry,path_name); + default: + // printk("No match sub device name\n"); + return -1; + } +} + + + + + diff --git a/vvcam/native/video/video_ioctl.h b/vvcam/native/video/video_ioctl.h new file mode 100755 index 0000000..6f3cec4 --- /dev/null +++ b/vvcam/native/video/video_ioctl.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _THEAD_VIDEO_IOCTL_H_ +#define _THEAD_VIDEO_IOCTL_H_ + +#include + +enum { + VIDEO_GET_PIPLANES = _IO('r', 0), + VIDEO_GET_PIPLANES_NUM, + VIDEO_GET_DEV_PARAM, + VIDEO_SET_PATH_TYPE, + VIDEO_GET_MEM_POOL_REGION_ID, +}; + +#endif /* _THEAD_VIDEO_IOCTL_H_*/ diff --git a/vvcam/native/video/video_kernel_defs.h b/vvcam/native/video/video_kernel_defs.h new file mode 100755 index 0000000..bdf7168 --- /dev/null +++ b/vvcam/native/video/video_kernel_defs.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _THEAD_VIDEO_KERNEL_DEFS_H_ +#define _THEAD_VIDEO_KERNEL_DEFS_H_ + +typedef enum sensor_path_type{ + SENSOR_VGA_RAW12_LINER = 0, + SENSOR_1080P_RAW12_LINER, + SENSOR_4K_RAW12_LINER, + SENSOR_VGA_RAW10_LINER = 20, + SENSOR_1080P_RAW10_LINER, + SENSOR_4K_RAW10_LINER, + SENSOR_2592x1944_RAW10_LINER, + SENSOR_1280x720_RAW10_LINER, + SENSOR_VGA_RAW12_HDR_2DOL, + SENSOR_VGA_RAW12_HDR_3DOL, + SENSOR_PATH_MAX, +} sensor_path_type_e; + +typedef enum vipre_path_type{ + VIPRE_CSI0_DDR, + VIPRE_CSI1_DDR, + VIPRE_CSI2_DDR, + VIPRE_CSI0_ISP0, + VIPRE_CSI1_ISP0, + VIPRE_CSI2_ISP0, + VIPRE_CSI0_ISP1, + VIPRE_CSI1_ISP1, + VIPRE_CSI2_ISP1, + VIPRE_CSI0_LOW_COAST_HDR_ISP0, + VIPRE_CSI1_LOW_COAST_HDR_ISP0, + VIPRE_CSI2_LOW_COAST_HDR_ISP0, + VIPRE_PATH_MAX, + +} vipre_path_type_e; + +typedef enum isp_path_type{ + // 指示IP 内部进出的通路，也可表征内部数据对齐等方式 + ISP_MI_PATH_MP = 0, + ISP_MI_PATH_SP, + ISP_MI_PATH_SP2_BP, +#ifdef ISP_MI_MCM_WR + ISP_MI_MCM_WR0, + ISP_MI_MCM_WR1, +#endif + ISP_MI_PATH_PP, +#ifdef ISP_MI_HDR + ISP_MI_HDR_L, + ISP_MI_HDR_S, + ISP_MI_HDR_VS, + ISP_MI_MAX, +#endif +} isp_path_type_e; + +typedef enum ry_path_type{ + ISP_RY_MI_PATH_MP = 0, + ISP_RY_MI_PATH_SP, + ISP_RY_MI_PATH_SP2_BP, + ISP_RY_PATH_MAX, +} isp_ry_path_type_e; + +typedef enum dsp_path_type{ + DSP_PATH_ISP_RY = 0, + DSP_PATH_ISP_CPU, + DSP_PATH_VIPRE_DDR, + + DSP_PATH_VIPRE_EVEN, + DSP_PATH_VIPRE_ODD, + DSP_PATH_VIPRE_RY, + DSP_PATH_CPU_CPU, + DSP_PATH_MAX, +} dsp_path_type_e; + +typedef enum dw_path_type{ + DW_DWE_VSE0 = 0, + DW_DWE_VSE1, + DW_DWE_VSE2, + DW_PATH_MAX, +} dw_path_type_e; + +typedef enum vedio_ip_type{ + SENSOR = 0, + VIPRE, + ISP, + DW, + RY, + DSP, +}vedio_ip_type_e; + +#endif /* _THEAD_VIDEO_KERNEL_DEFS_H_*/ diff --git a/vvcam/native/video/video_sysfs.c b/vvcam/native/video/video_sysfs.c new file mode 100755 index 0000000..a2ec8e2 --- /dev/null +++ b/vvcam/native/video/video_sysfs.c @@ -0,0 +1,105 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "video.h" +#include "video_kernel_defs.h" +#if 0 +static ssize_t n_lanes_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long lanes; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &lanes); + if (ret < 0) + return ret; + + if (lanes > 8) { + dev_err(dev, "Invalid number of lanes %lu\n", lanes); + return count; + } + + dev_info(dev, "Lanes %lu\n", lanes); + csi_dev->hw.num_lanes = lanes; + + return count; +} + +static ssize_t n_lanes_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct video_drvdata *drvdata = platform_get_drvdata(pdev); + + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.num_lanes); + + return strlcpy(buf, buffer, PAGE_SIZE); +} +#endif + +static void show_subdev(pipline_t *pipline) +{ + int i = 0; + sub_dev_info_t *sub_dev; + + sub_dev = pipline->sub_dev; + while(i < pipline->sub_dev_num) { + video_info("dev[%d]: %s%d\n", i, sub_dev->name, sub_dev->idx); + sub_dev++; + i++; + } +} + +static ssize_t piplines_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int i = 0; + struct platform_device *pdev = to_platform_device(dev); + struct video_drvdata *drvdata = platform_get_drvdata(pdev); + pipline_t *pipline = drvdata->piplines; + while(i < drvdata->pipline_num) { + video_info("/*pipline[%d]*******/\n", i); + show_subdev(pipline); + video_info("\n\n"); + pipline++; + i++; + } + + return 0; +} + +//static DEVICE_ATTR_RW(n_lanes); +static DEVICE_ATTR_RO(piplines); + +int video_create_capabilities_sysfs(struct platform_device *pdev) +{ + device_create_file(&pdev->dev, &dev_attr_piplines); + return 0; +} + +int video_remove_capabilities_sysfs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_piplines); + return 0; +} + diff --git a/vvcam/readme-android.txt b/vvcam/readme-android.txt new file mode 100755 index 0000000..2b979d0 --- /dev/null +++ b/vvcam/readme-android.txt @@ -0,0 +1,9 @@ +To build under android top dir, please follow below steps. +1. clone the git under ANDROID_ROOT/vendor/nxp-opensource +2. check out to branch integration_vsi_4.0.8p2_android +3. cd ANDROID_ROOT +4. source build/envsetup.sh +5. lunch evk_8mp-userdebug +6. ./imx-make.sh kernel -j8 +7. ./imx-make.sh vvcam (add "-c" for clean build) +8. generate the ko in ANDROID_ROOT/out/target/product/evk_8mp/obj/VVCAM_OBJ/vvcam.ko diff --git a/vvcam/readme.txt b/vvcam/readme.txt new file mode 100755 index 0000000..063fef4 --- /dev/null +++ b/vvcam/readme.txt @@ -0,0 +1,37 @@ +isp kernel driver (verisilicon) + +file description: + vvcam/common/video.c - register v4l2 video device, filename is /dev/videox, process standard v4l2 command. + vvcam/driver/isp_driver.c - register v4l2 subdev, filename is /dev/v4l-subdevx, supply full isp options for all modules. + units/ispdrv/isp/ic_dev.h - defined all isp main/sub modules structure. + units/ispdrv/isp/isp_ioctl.h - defined all isp ioctls and internal functions. + units/ispdrv/isp/isp_ioctl.c - dispatch ioctl and implement isp main functions.(need create new file if module code number larger than 100, such as wdr3, 3dnr) + units/ispdrv/isp/cma.h - continuous memory allocator, user may need replace it. + +setup environment: + cd appshell + source environment-setup--linux + source environment-setup-x86_64-linux + +build: + cd vvcam/native + make VERSION_CFG=ISP8000NANO_V1802 +clean: + cd vvcam/native + make clean + +install: + cd vvcam/native/bin + ./insmod.sh + +unistall: + cd vvcam/native/bin + ./rmmod.sh + + +porting guide: + 1. modify ISP_REG_BASE and ISP_REG_BASE in version.h + 2. modify RESERVED_MEM_BASE and RESERVED_MEM_SIZE in version.h + 3. for use cma, user need modify linux dts file to map the device memory. + or replace vb2_cma_alloc to default vb2 mem_ops. + diff --git a/vvcam/readme_v4l2.txt b/vvcam/readme_v4l2.txt new file mode 100755 index 0000000..7b1f0f2 --- /dev/null +++ b/vvcam/readme_v4l2.txt @@ -0,0 +1,53 @@ +build +x86 +make BUILD_TYPE=fpga WITH_DWE=1 VERSION=ISP8000NANO_V1802 +arm64 +make VERSION=ISP8000NANO_V1802 KERNEL_SRC=$(arm_kernel_src) + +generate kernel modules, support hot plug. +find -name *.ko +./v4l2/vvcam-dwe.ko +./v4l2/sensor/ov2775/ov2775.ko +./v4l2/sensor/os08a20/os08a20.ko +./v4l2/csi/samsung/vvcam-csis.ko +./v4l2/video/vvcam-video.ko +./v4l2/vvcam-isp.ko +.. + + + + +(1)编译imx8-media-dev.ko +mkdir build_v8 && cd build_v8 +make ARCH=arm64 menuconfig + Device Drivers ---> + [*] Staging drivers ---> + [*] Media staging drivers ---> + i.MX8QXP/QM Camera ISI/MIPI Features support ---> + IMX8 Media Device Driver +make -j4 + +(2)编译vvcam +DWE disable IRQ: +make VERSION=ISP8000NANO_V1802 KERNEL_SRC=$(arm_kernel_src) ENABLE_IRQ=no + +DWE enable IRQ: +make VERSION=ISP8000NANO_V1802 KERNEL_SRC=$(arm_kernel_src) ENABLE_IRQ=yes + +(3)加载KO +ov2775 insmod: +cp $Kernel_SRC/driver/staging/media/imx/imx8-media-dev.ko to your board directory +insmod vvcam-video.ko +insmod ov2775.ko +insmod vvcam-dwe.ko +insmod vvcam-isp.ko +insmod imx8-media-dev.ko + + +os08a20 insmod: +cp $Kernel_SRC/driver/staging/media/imx/imx8-media-dev.ko to your board directory +insmod vvcam-video.ko +insmod os08a20.ko +insmod vvcam-dwe.ko +insmod vvcam-isp.ko +insmod imx8-media-dev.ko \ No newline at end of file diff --git a/vvcam/soc/soc_ioctl.c b/vvcam/soc/soc_ioctl.c new file mode 100755 index 0000000..5c696c4 --- /dev/null +++ b/vvcam/soc/soc_ioctl.c @@ -0,0 +1,262 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef __KERNEL__ +#include +#include +#include +#include + +#define pr_info printf +#define pr_err printf +#define copy_from_user(a, b, c) soc_copy_data(a, b, c) +#define copy_to_user(a, b, c) soc_copy_data(a, b, c) +#define __user +#define __iomem + +void soc_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); +} + +#else // __KERNEL__ +#include /* Module support */ +#include + +#endif + +#include "soc_ioctl.h" +#include "vivsoc_hub.h" + + +long soc_priv_ioctl(struct vvcam_soc_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + struct soc_control_context soc_ctrl; + if (!dev) { + return ret; + } + + switch (cmd) { + /* ISP part */ + adfasf + case VVSOC_IOC_S_RESET_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* DWE part */ + case VVSOC_IOC_S_RESET_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* VSE part */ + case VVSOC_IOC_S_RESET_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + + /* CSI part */ + case VVSOC_IOC_S_RESET_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* sensor part */ + case VVSOC_IOC_S_RESET_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + + default: + pr_err("unsupported command %d", cmd); + break; + } + + return ret; +} + +extern struct vvcam_soc_function_s gen6_soc_function; + +int vvnative_soc_init(struct vvcam_soc_dev *dev) +{ + if (dev == NULL) + { + pr_err("[%s] dev is NULL\n", __func__); + return -1; + } + + vivsoc_register_hardware(dev, &gen6_soc_function); + return 0; +} + +int vvnative_soc_deinit(struct vvcam_soc_dev *dev) +{ + return 0; +} + + diff --git a/vvcam/soc/soc_ioctl.h b/vvcam/soc/soc_ioctl.h new file mode 100755 index 0000000..6d01f40 --- /dev/null +++ b/vvcam/soc/soc_ioctl.h @@ -0,0 +1,158 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _SOC_IOC_H_ +#define _SOC_IOC_H_ + +#ifndef __KERNEL__ +#include +#endif + +#include + +enum { + VVSOC_IOC_S_RESET_ISP = _IO('r', 0), + VVSOC_IOC_S_POWER_ISP, + VVSOC_IOC_G_POWER_ISP, + VVSOC_IOC_S_CLOCK_ISP, + VVSOC_IOC_G_CLOCK_ISP, + + VVSOC_IOC_S_RESET_DWE, + VVSOC_IOC_S_POWER_DWE, + VVSOC_IOC_G_POWER_DWE, + VVSOC_IOC_S_CLOCK_DWE, + VVSOC_IOC_G_CLOCK_DWE, + + VVSOC_IOC_S_RESET_VSE, + VVSOC_IOC_S_POWER_VSE, + VVSOC_IOC_G_POWER_VSE, + VVSOC_IOC_S_CLOCK_VSE, + VVSOC_IOC_G_CLOCK_VSE, + + VVSOC_IOC_S_RESET_CSI, + VVSOC_IOC_S_POWER_CSI, + VVSOC_IOC_G_POWER_CSI, + VVSOC_IOC_S_CLOCK_CSI, + VVSOC_IOC_G_CLOCK_CSI, + + VVSOC_IOC_S_RESET_SENSOR, + VVSOC_IOC_S_POWER_SENSOR, + VVSOC_IOC_G_POWER_SENSOR, + VVSOC_IOC_S_CLOCK_SENSOR, + VVSOC_IOC_G_CLOCK_SENSOR, + + VVSOC_IOC_S_RESET_ISP_RY, + VVSOC_IOC_S_POWER_ISP_RY, + VVSOC_IOC_G_POWER_ISP_RY, + VVSOC_IOC_S_CLOCK_ISP_RY, + VVSOC_IOC_G_CLOCK_ISP_RY, + + VVSOC_IOC_MAX, +}; + +struct soc_control_context { + uint32_t device_idx; + uint32_t control_value; +}; + +struct vvcam_soc_func_s +{ + int (*set_power)(void*,unsigned int,unsigned int); + int (*get_power)(void*,unsigned int,unsigned int *); + int (*set_reset)(void*,unsigned int,unsigned int); + int (*set_clk)(void*,unsigned int,unsigned int); + int (*get_clk)(void*,unsigned int,unsigned int *); +}; + +struct vvcam_soc_function_s +{ + struct vvcam_soc_func_s isp_func; + struct vvcam_soc_func_s dwe_func; + struct vvcam_soc_func_s vse_func; + struct vvcam_soc_func_s csi_func; + struct vvcam_soc_func_s sensor_func; +}; + +struct vvcam_soc_access_s +{ + int (*write)(void * ctx, uint32_t address, uint32_t data); + int (*read)(void * ctx, uint32_t address, uint32_t *data); +}; + + +#ifdef __KERNEL__ + +struct vvcam_soc_dev { + void __iomem *base; + struct soc_control_context isp0; + struct soc_control_context isp1; + struct soc_control_context dwe; + struct soc_control_context vse; + struct vvcam_soc_function_s soc_func; + struct vvcam_soc_access_s soc_access; + void * csi_private; +}; +// internal functions + +long soc_priv_ioctl(struct vvcam_soc_dev *dev, unsigned int cmd, void *args); +int vvnative_soc_init(struct vvcam_soc_dev *dev); +int vvnative_soc_deinit(struct vvcam_soc_dev *dev); + + + +#else +//User space connections + + +#endif + +#endif // _SOC_IOC_H_ diff --git a/vvcam/soc/vivsoc_hub.c b/vvcam/soc/vivsoc_hub.c new file mode 100755 index 0000000..12c2c26 --- /dev/null +++ b/vvcam/soc/vivsoc_hub.c @@ -0,0 +1,586 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include + +#include "soc_ioctl.h" +#include "vivsoc_hub.h" +#include "vsi_core_gen6.h" + + +int vivsoc_hub_isp_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_dwe_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_vse_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_csi_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +unsigned int vivsoc_register_hardware(struct vvcam_soc_dev *dev, struct vvcam_soc_function_s *func) +{ + if (func == NULL) + { + return -1; + } + + memcpy(&dev->soc_func,func,sizeof(struct vvcam_soc_function_s)); + + dev->soc_access.write = gen6_write_reg; + dev->soc_access.read = gen6_read_reg; + + return 0; +} + + + + diff --git a/vvcam/soc/vivsoc_hub.h b/vvcam/soc/vivsoc_hub.h new file mode 100755 index 0000000..3c99805 --- /dev/null +++ b/vvcam/soc/vivsoc_hub.h @@ -0,0 +1,88 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VIVSOC_HUB_H_ +#define _VIVSOC_HUB_H_ + +int vivsoc_hub_isp_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_dwe_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_vse_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_csi_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_sensor_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +unsigned int vivsoc_register_hardware(struct vvcam_soc_dev *dev, struct vvcam_soc_function_s *func); + +#endif /* _VIVSOC_HUB_H_ */ diff --git a/vvcam/soc/vsi/soc_i2c.c b/vvcam/soc/vsi/soc_i2c.c new file mode 100755 index 0000000..51d7345 --- /dev/null +++ b/vvcam/soc/vsi/soc_i2c.c @@ -0,0 +1,372 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct soc_gpio_i2c{ + struct i2c_adapter adap; + unsigned long phy_base_addr; + unsigned long size; + void __iomem * virt_base_addr; + spinlock_t lock; +}; + + +static void i2c_gpio_setsda_val(void *source, int state) +{ + struct soc_gpio_i2c *i2c = source; + int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~0x1)) | (0x10 | (state & 0x01)); + + writel(reg_data, i2c->virt_base_addr); + return ; +} + +static void i2c_gpio_setscl_val(void *source, int state) +{ + struct soc_gpio_i2c *i2c = source; + int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~(0x1 << 8))) | ((0x10 | (state & 0x01)) << 8); + + writel(reg_data, i2c->virt_base_addr); + return ; +} + +static int i2c_gpio_getsda(void *source) +{ + struct soc_gpio_i2c *i2c = source; + unsigned int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~0x10)); + writel(reg_data, i2c->virt_base_addr); + + return (readl(i2c->virt_base_addr) & 0x01); +} +// Start :When SCL is High ,SDA Change to low +static void i2c_gpio_start(void *source) +{ + i2c_gpio_setscl_val(source, 1); + i2c_gpio_setsda_val(source, 1); + udelay(5); + i2c_gpio_setsda_val(source, 0); + udelay(1); + return; +} +//Send Bit : When SCL is LOW, sda change;When SCL is HIgh,SDA hold; +static void i2c_gpio_send_byte(void *source, unsigned char val) +{ + int bit_idx; + for (bit_idx=7; bit_idx >= 0; bit_idx--) + { + i2c_gpio_setscl_val(source, 0); + i2c_gpio_setsda_val(source, (val >> bit_idx) & 0x01); + udelay(1); + i2c_gpio_setscl_val(source, 1); + udelay(1); + } + i2c_gpio_setscl_val(source, 0); + i2c_gpio_setsda_val(source, 1); + return; +} +//Read Bit: When SCL is High read data; +static unsigned char i2c_gpio_read_byte(void *source) +{ + int bit_idx; + unsigned char data = 0; + + i2c_gpio_getsda(source);//SDA change to read + + for(bit_idx=7; bit_idx>=0; bit_idx--) + { + + i2c_gpio_setscl_val(source, 1); + udelay(1); + data = (data << 1) | i2c_gpio_getsda(source); + i2c_gpio_setscl_val(source, 0); + udelay(1); + } + return data; +} + +static int i2c_gpio_wait_ack(void *source) +{ + unsigned int i2c_retry_ack_cnt = 0; + + i2c_gpio_getsda(source);//SDA change to read + udelay(1); + i2c_gpio_setscl_val(source, 1); + + while(i2c_gpio_getsda(source) == 1) + { + udelay(1); + if (i2c_retry_ack_cnt++ > 20) + { + return 0; + } + } + i2c_gpio_setscl_val(source, 0); + return 1; +} + +static void i2c_gpio_stop(void *source) +{ + i2c_gpio_setsda_val(source, 0); + udelay(1); + i2c_gpio_setscl_val(source, 1); + udelay(1); + i2c_gpio_setsda_val(source, 1); + return; +} + +static int i2c_gpio_write(void *source,struct i2c_msg *msg) +{ + + unsigned char slave_address; + unsigned char *buf; + int i; + slave_address = (msg->addr) << 1; + buf = msg->buf; + + i2c_gpio_start(source); + i2c_gpio_send_byte(source, slave_address); + if (i2c_gpio_wait_ack(source) == 0) return -1; + + for (i = 0; i < msg->len; i++) + { + i2c_gpio_send_byte(source, buf[i]); + i2c_gpio_wait_ack(source); + } + + i2c_gpio_stop(source); + return 0; +} + +static int i2c_gpio_read(void *source,struct i2c_msg *msg) +{ + unsigned char slave_address; + unsigned char *buf; + int i; + slave_address = ((msg->addr) << 1) | 0x01; + buf = msg->buf; + + i2c_gpio_start(source); + i2c_gpio_send_byte(source, slave_address); + if (i2c_gpio_wait_ack(source) == 0) return -1; + + for (i = 0; i < msg->len; i++) + { + buf[i] = i2c_gpio_read_byte(source); + i2c_gpio_wait_ack(source); + } + + return 0; +} + +static int i2c_gpio_xfer(struct i2c_adapter *adapter, + struct i2c_msg *msgs, int num) +{ + int result; + int i; + struct soc_gpio_i2c *i2c; + void *source; + + source = i2c_get_adapdata(adapter); + i2c = source; + + for (i=0; idev, sizeof(struct soc_gpio_i2c), GFP_KERNEL); + if (!i2c) + { + return -ENOMEM; + } + memset(i2c, 0, sizeof(struct soc_gpio_i2c)); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + i2c->phy_base_addr = mem->start; + i2c->size = mem->end - mem->start + 1; + //i2c->virt_base_addr = devm_ioremap_resource(&pdev->dev, mem); + //if (IS_ERR(i2c->virt_base_addr)) + // return PTR_ERR(i2c->virt_base_addr); + i2c->virt_base_addr = (void __iomem *)mem->name; + + spin_lock_init(&(i2c->lock)); + + adap = &i2c->adap; + platform_set_drvdata(pdev, adap); + + i2c_set_adapdata(adap, i2c); + adap->owner = THIS_MODULE; + snprintf(adap->name, sizeof(adap->name), "soc_gpio_i2c"); + adap->timeout = 2 * HZ; + adap->retries = 0; + adap->algo = &gpio_i2c_algo; + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + adap->dev.parent = &pdev->dev; + adap->nr = pdev->id; + adap->dev.of_node = pdev->dev.of_node; + + ret = i2c_add_numbered_adapter(adap); + if (ret) + { + pr_info("%s:i2c_add_adapter failed 0x%x\n", __func__, ret); + kfree(i2c); + return ret; + } + + return 0; +} + +static int soc_gpio_i2c_remove(struct platform_device *pdev) +{ + struct i2c_adapter *adap; + + adap = platform_get_drvdata(pdev); + i2c_del_adapter(adap); + + return 0; +} + +static struct platform_driver soc_gpio_i2c_driver = { + .probe = soc_gpio_i2c_probe, + .remove = soc_gpio_i2c_remove, + .driver = { + .name = "soc_gpio_i2c", + .owner = THIS_MODULE, + }, +}; + +static unsigned int i2c_driver_register_flag = 0; + +int soc_gpio_i2c_driver_init(void) +{ + if (i2c_driver_register_flag == 0) + { + platform_driver_register(&soc_gpio_i2c_driver); + } + i2c_driver_register_flag++; + return 0; +} +void soc_gpio_i2c_driver_exit(void) +{ + if (i2c_driver_register_flag == 1) + { + pr_info("enter %s\n", __func__); + platform_driver_unregister(&soc_gpio_i2c_driver); + } + + i2c_driver_register_flag--; + return; +} + + + + + + diff --git a/vvcam/soc/vsi/soc_i2c.h b/vvcam/soc/vsi/soc_i2c.h new file mode 100755 index 0000000..5789029 --- /dev/null +++ b/vvcam/soc/vsi/soc_i2c.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _SOC_I2C_H_ +#define _SOC_I2C_H_ + +//int gen6_i2c_wr(unsigned int dev_address, unsigned int reg_address, unsigned int reg_data); +//unsigned int gen6_i2c_rd(unsigned int dev_address, unsigned int reg_address); + +int soc_gpio_i2c_driver_init(void); +void soc_gpio_i2c_driver_exit(void); +int soc_gpio_i2c_register_bus(unsigned int index,unsigned int bus,unsigned long base_addr, unsigned int size, + void * virt_base); + +void soc_gpio_i2c_unregister_bus(unsigned int index); + + +#endif diff --git a/vvcam/soc/vsi/soc_i2c_dev.c b/vvcam/soc/vsi/soc_i2c_dev.c new file mode 100755 index 0000000..9e2e7e2 --- /dev/null +++ b/vvcam/soc/vsi/soc_i2c_dev.c @@ -0,0 +1,146 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include + + +static void soc_gpio_i2c_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); + return; +} + + +static struct resource soc_gpio_i2c0_resource[] = { + [0] = { + .start = 0x00, + .end = 0x00, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device soc_gpio_i2c0_pdev = { + .name = "soc_gpio_i2c", + .id = -1, + .resource = soc_gpio_i2c0_resource, + .num_resources = 1, + .dev.release = soc_gpio_i2c_release, +}; + +static struct resource soc_gpio_i2c1_resource[] = { + [0] = { + .start = 0x00, + .end = 0x00, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device soc_gpio_i2c1_pdev = { + .name = "soc_gpio_i2c", + .id = -1, + .resource = soc_gpio_i2c1_resource, + .num_resources = 1, + .dev.release = soc_gpio_i2c_release, +}; + +int soc_gpio_i2c_register_bus(unsigned int index,unsigned int bus,unsigned long base_addr, unsigned int size, + void * virt_base) +{ + int ret = 0; + struct platform_device * i2c_pdev; + pr_info("enter %s\n", __func__); + + switch(index) + { + case 0: + i2c_pdev = &soc_gpio_i2c0_pdev; + break; + case 1: + i2c_pdev = &soc_gpio_i2c1_pdev; + break; + default : + return -1; + } + + i2c_pdev->id = bus; + i2c_pdev->resource[0].start = base_addr; + i2c_pdev->resource[0].end = base_addr + size - 1; + i2c_pdev->resource[0].name = virt_base; + + ret = platform_device_register(i2c_pdev); + + pr_info("exit %s\n", __func__); + return ret; +} + +void soc_gpio_i2c_unregister_bus(unsigned int index) +{ + struct platform_device * i2c_pdev; + + switch(index) + { + case 0: + i2c_pdev = &soc_gpio_i2c0_pdev; + break; + case 1: + i2c_pdev = &soc_gpio_i2c1_pdev; + break; + default : + return; + } + + platform_device_unregister(i2c_pdev); + + return ; +} + diff --git a/vvcam/soc/vsi_core_gen6.c b/vvcam/soc/vsi_core_gen6.c new file mode 100755 index 0000000..1751971 --- /dev/null +++ b/vvcam/soc/vsi_core_gen6.c @@ -0,0 +1,353 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "soc_ioctl.h" +#include "vsi_core_gen6.h" + + int gen6_write_reg(void* dev,unsigned int addr,unsigned int val) +{ + struct vvcam_soc_dev *soc_dev; + + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + writel(val,soc_dev->base + addr); + + return 0; +} + + int gen6_read_reg(void* dev,unsigned int addr,unsigned int *val) +{ + struct vvcam_soc_dev *soc_dev; + + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + *val = readl(soc_dev->base + addr); + + return 0; +} + + +static int gen6_set_isp_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_isp_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_isp_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev;; + unsigned int reg_addr; + unsigned int reg_value; + + reg_addr = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + if (id == 0) + { + reg_addr = REG_TPG0; + }else{ + reg_addr = REG_TPG1; + } + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<24); + + }else{ + reg_value |= (1<<24); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + ret |= soc_dev->soc_access.write(dev,REG_TPG0,reg_value); + + return ret; +} + +static int gen6_set_isp_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_isp_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + +static int gen6_set_dwe_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_dwe_power(void* dev, unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_dwe_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev;; + unsigned int reg_addr; + unsigned int reg_value; + + reg_addr = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + reg_addr = REG_DWE_CTRL; + + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<0); + }else{ + reg_value |= (1<<0); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + + return ret; +} + +static int gen6_set_dwe_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_dwe_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +static int gen6_set_vse_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_vse_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_vse_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev;; + unsigned int reg_addr; + unsigned int reg_value; + reg_addr = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + reg_addr = REG_VSE_CTRL; + + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<0); + }else{ + reg_value |= (1<<0); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + + return ret; +} + +static int gen6_set_vse_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_vse_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +static int gen6_set_csi_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_csi_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_csi_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev;; + unsigned int reg_addr; + unsigned int reg_value; + + reg_addr = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + if (id == 0) + { + reg_addr = REG_TPG0; + }else{ + reg_addr = REG_TPG1; + } + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<4 | 1<<28); + }else{ + reg_value |= 0x30000210; + } + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + + return ret; +} + +static int gen6_set_csi_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_csi_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + +static int gen6_set_sensor_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_sensor_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_sensor_reset(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_set_sensor_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_sensor_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +struct vvcam_soc_function_s gen6_soc_function = { + .isp_func.set_power = gen6_set_isp_power, + .isp_func.get_power = gen6_get_isp_power, + .isp_func.set_reset = gen6_set_isp_reset, + .isp_func.set_clk = gen6_set_isp_clk, + .isp_func.get_clk = gen6_get_isp_clk, + + .dwe_func.set_power = gen6_set_dwe_power, + .dwe_func.get_power = gen6_get_dwe_power, + .dwe_func.set_reset = gen6_set_dwe_reset, + .dwe_func.set_clk = gen6_set_dwe_clk, + .dwe_func.get_clk = gen6_get_dwe_clk, + + .vse_func.set_power = gen6_set_vse_power, + .vse_func.get_power = gen6_get_vse_power, + .vse_func.set_reset = gen6_set_vse_reset, + .vse_func.set_clk = gen6_set_vse_clk, + .vse_func.get_clk = gen6_get_vse_clk, + + .csi_func.set_power = gen6_set_csi_power, + .csi_func.get_power = gen6_get_csi_power, + .csi_func.set_reset = gen6_set_csi_reset, + .csi_func.set_clk = gen6_set_csi_clk, + .csi_func.get_clk = gen6_get_csi_clk, + + .sensor_func.set_power = gen6_set_sensor_power, + .sensor_func.get_power = gen6_get_sensor_power, + .sensor_func.set_reset = gen6_set_sensor_reset, + .sensor_func.set_clk = gen6_set_sensor_clk, + .sensor_func.get_clk = gen6_get_sensor_clk, +}; + + + diff --git a/vvcam/soc/vsi_core_gen6.h b/vvcam/soc/vsi_core_gen6.h new file mode 100755 index 0000000..f1b6521 --- /dev/null +++ b/vvcam/soc/vsi_core_gen6.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VSI_CORE_GEN6_H +#define _VSI_CORE_GEN6_H + + +#define REG_TPG0 0x300 +#define REG_TPG1 0x310 +#define REG_DWE_CTRL 0x250 +#define REG_VSE_CTRL 0x254 + + + +extern struct vvcam_soc_function_s gen6_soc_function; +int gen6_write_reg(void* dev,unsigned int addr,unsigned int val); +int gen6_read_reg(void* dev,unsigned int addr,unsigned int *val); + +#endif diff --git a/vvcam/v4l2/Kbuild b/vvcam/v4l2/Kbuild new file mode 100755 index 0000000..ed675a6 --- /dev/null +++ b/vvcam/v4l2/Kbuild @@ -0,0 +1,86 @@ +ifeq ($(BUILD_TYPE), fpga) +INCLUDE_DIR := /usr/src/linux-headers-$(shell uname -r) +KERNEL_SRC := $(INCLUDE_DIR) +endif + +SRC := $(shell pwd) + +ANDROID := no +ifeq ($(ANDROID), yes) +PWD := $(shell pwd) +#PWD := $(ANDROID_BUILD_TOP)/vendor/nxp-opensource/verisilicon_sw_isp_vvcam/vvcam/v4l2 +endif + +EXTRA_CFLAGS += -I$(PWD)/../common/ +EXTRA_CFLAGS += -I$(PWD)/../isp/ +EXTRA_CFLAGS += -I$(PWD)/../v4l2/ + +# Enable interrupt mode for vvcam modules (yes, no) +ENABLE_IRQ := yes + +ifeq ($(ENABLE_IRQ), yes) + EXTRA_CFLAGS += -DENABLE_IRQ +endif + +ifeq ($(ANDROID), no) +EXTRA_CFLAGS += -O2 -Werror +endif + +obj-m += video/ + +include $(PWD)/../version/ISP8000NANO_V1802.mk + +EXTRA_CFLAGS += -DISP_REG_SIZE=0x00010000 +EXTRA_CFLAGS += -DDEC_REG_BASE=0x00600000 +EXTRA_CFLAGS += -DDEC_REG_SIZE=0x2000 +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0xB0000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x10000000 + +vvcam-isp-objs += ../isp/isp_miv1.o +vvcam-isp-objs += ../isp/isp_miv2.o +vvcam-isp-objs += ../isp/isp_wdr3.o +vvcam-isp-objs += ../isp/isp_wdr.o +vvcam-isp-objs += ../isp/isp_3dnr.o +vvcam-isp-objs += ../isp/isp_hdr.o +vvcam-isp-objs += ../isp/isp_dpf.o +vvcam-isp-objs += ../isp/isp_compand.o +vvcam-isp-objs += ../isp/isp_gcmono.o +vvcam-isp-objs += ../isp/isp_ioctl.o +vvcam-isp-objs += ../isp/isp_rgbgamma.o +vvcam-isp-objs += ../isp/isp_rgbir.o +#vvcam-isp-objs += ../isp/isp_dec.o +#vvcam-isp_objs += ../isp/isp_dmsc2.o +vvcam-isp-objs += ../isp/isp_isr.o +ifeq ($(ENABLE_IRQ), yes) + vvcam-isp-objs += isp_driver_of.o +else + vvcam-isp-objs += isp_driver.o +endif +vvcam-isp-objs += video/vvbuf.o +obj-m += vvcam-isp.o + +EXTRA_CFLAGS += -I$(PWD)/../dwe/ +vvcam-dwe-objs += ../dwe/dwe_ioctl.o +vvcam-dwe-objs += ../dwe/dwe_isr.o +ifeq ($(ENABLE_IRQ), yes) + vvcam-dwe-objs += dwe_driver_of.o + vvcam-dwe-objs += dwe_devcore.o +else + vvcam-dwe-objs += dwe_driver.o +endif +vvcam-dwe-objs += video/vvbuf.o +obj-m += vvcam-dwe.o + +#obj-m += csi/ +obj-m += sensor/ + +V := 1 + +all: + @$(MAKE) V=$(V) -C $(KERNEL_DIR) ARCH=$(ARCH_TYPE) M=$(SRC) ENABLE_IRQ=$(ENABLE_IRQ) modules + +clean: + @rm -rf modules.order Module.symvers + @find ../ -name "*.o" | xargs rm -f + @find ../ -name "*.ko" | xargs rm -f + diff --git a/vvcam/v4l2/Makefile b/vvcam/v4l2/Makefile new file mode 100755 index 0000000..4c68259 --- /dev/null +++ b/vvcam/v4l2/Makefile @@ -0,0 +1,81 @@ +ifeq ($(BUILD_TYPE), fpga) +INCLUDE_DIR := /usr/src/linux-headers-$(shell uname -r) +KERNEL_SRC := $(INCLUDE_DIR) +endif + +SRC := $(shell pwd) + +EXTRA_CFLAGS += -I$(PWD)/../common/ +EXTRA_CFLAGS += -I$(PWD)/../isp/ +EXTRA_CFLAGS += -I$(PWD)/../v4l2/ + +# Enable interrupt mode for vvcam modules (yes, no) +ENABLE_IRQ := yes + +ifeq ($(ENABLE_IRQ), yes) + EXTRA_CFLAGS += -DENABLE_IRQ +endif + +EXTRA_CFLAGS += -O2 -Werror + +obj-m += video/ + +include $(PWD)/../version/ISP8000NANO_V1802.mk + +EXTRA_CFLAGS += -DISP_REG_SIZE=0x00010000 +EXTRA_CFLAGS += -DDEC_REG_BASE=0x00600000 +EXTRA_CFLAGS += -DDEC_REG_SIZE=0x2000 +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0xB0000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x10000000 + +vvcam-isp-objs += ../isp/isp_miv1.o +vvcam-isp-objs += ../isp/isp_miv2.o +vvcam-isp-objs += ../isp/isp_wdr3.o +vvcam-isp-objs += ../isp/isp_wdr.o +vvcam-isp-objs += ../isp/isp_3dnr.o +vvcam-isp-objs += ../isp/isp_hdr.o +vvcam-isp-objs += ../isp/isp_dpf.o +vvcam-isp-objs += ../isp/isp_compand.o +vvcam-isp-objs += ../isp/isp_gcmono.o +vvcam-isp-objs += ../isp/isp_ioctl.o +vvcam-isp-objs += ../isp/isp_rgbgamma.o +vvcam-isp-objs += ../isp/isp_rgbir.o +#vvcam-isp-objs += ../isp/isp_dec.o +#vvcam-isp_objs += ../isp/isp_dmsc2.o +vvcam-isp-objs += ../isp/isp_isr.o +ifeq ($(ENABLE_IRQ), yes) + vvcam-isp-objs += isp_driver_of.o +else + vvcam-isp-objs += isp_driver.o +endif +vvcam-isp-objs += video/vvbuf.o +obj-m += vvcam-isp.o + +EXTRA_CFLAGS += -I$(PWD)/../dwe/ +vvcam-dwe-objs += ../dwe/dwe_ioctl.o +vvcam-dwe-objs += ../dwe/dwe_isr.o +ifeq ($(ENABLE_IRQ), yes) + vvcam-dwe-objs += dwe_driver_of.o + vvcam-dwe-objs += dwe_devcore.o +else + vvcam-dwe-objs += dwe_driver.o +endif +vvcam-dwe-objs += video/vvbuf.o +obj-m += vvcam-dwe.o + +#obj-m += csi/ +obj-m += sensor/ + +all: + make -C $(KERNEL_SRC) M=$(SRC) ENABLE_IRQ=$(ENABLE_IRQ) + +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install + +clean: + make -C $(KERNEL_SRC) M=$(SRC) clean + find . -name '*.o' -delete + find . -name '*.ko' -delete + find . -name 'modules.order' -delete + find . -name 'Module.symvers' -delete + find . -name '*.mod.c' -delete diff --git a/vvcam/v4l2/csi/Makefile b/vvcam/v4l2/csi/Makefile new file mode 100755 index 0000000..82bf698 --- /dev/null +++ b/vvcam/v4l2/csi/Makefile @@ -0,0 +1,2 @@ +obj-m += samsung/ + diff --git a/vvcam/v4l2/csi/samsung/Makefile b/vvcam/v4l2/csi/samsung/Makefile new file mode 100755 index 0000000..a5d37ee --- /dev/null +++ b/vvcam/v4l2/csi/samsung/Makefile @@ -0,0 +1,4 @@ +EXTRA_CFLAGS += -I$(PWD)/../common/ +vvcam-csis-objs += mxc-mipi-csi2-sam.o + +obj-m += vvcam-csis.o diff --git a/vvcam/v4l2/csi/samsung/mxc-mipi-csi2-sam.c b/vvcam/v4l2/csi/samsung/mxc-mipi-csi2-sam.c new file mode 100755 index 0000000..4faba97 --- /dev/null +++ b/vvcam/v4l2/csi/samsung/mxc-mipi-csi2-sam.c @@ -0,0 +1,1837 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * Copyright 2019 NXP + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Based on Samsung S5P/EXYNOS SoC series MIPI-CSI receiver driver + * + * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd. + * Author: Sylwester Nawrocki + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vvcsioc.h" + +#include + +#define CSIS_DRIVER_NAME "mxc-mipi-csi2-sam" +#define CSIS_SUBDEV_NAME "mxc-mipi-csi2" +#define CSIS_MAX_ENTITIES 2 +#define CSIS0_MAX_LANES 4 +#define CSIS1_MAX_LANES 2 + +#define MIPI_CSIS_OF_NODE_NAME "csi" + +#define MIPI_CSIS_VC0_PAD_SINK 0 +#define MIPI_CSIS_VC1_PAD_SINK 1 +#define MIPI_CSIS_VC2_PAD_SINK 2 +#define MIPI_CSIS_VC3_PAD_SINK 3 + +#define MIPI_CSIS_VC0_PAD_SOURCE 4 +#define MIPI_CSIS_VC1_PAD_SOURCE 5 +#define MIPI_CSIS_VC2_PAD_SOURCE 6 +#define MIPI_CSIS_VC3_PAD_SOURCE 7 +#define MIPI_CSIS_VCX_PADS_NUM 8 + +#define MIPI_CSIS_DEF_PIX_WIDTH 1920 +#define MIPI_CSIS_DEF_PIX_HEIGHT 1080 + +/* Register map definition */ + +/* CSIS version */ +#define MIPI_CSIS_VERSION 0x00 + +/* CSIS common control */ +#define MIPI_CSIS_CMN_CTRL 0x04 +#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW (1 << 16) +#define MIPI_CSIS_CMN_CTRL_HDR_MODE (1 << 11) +#define MIPI_CSIS_CMN_CTRL_INTER_MODE (1 << 10) +#define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8 +#define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) +#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL (1 << 2) +#define MIPI_CSIS_CMN_CTRL_RESET (1 << 1) +#define MIPI_CSIS_CMN_CTRL_ENABLE (1 << 0) + +/* CSIS clock control */ +#define MIPI_CSIS_CLK_CTRL 0x08 +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) (x << 28) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) (x << 24) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) (x << 20) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) (x << 16) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) +#define MIPI_CSIS_CLK_CTRL_WCLK_SRC (1 << 0) + +/* CSIS Interrupt mask */ +#define MIPI_CSIS_INTMSK 0x10 +#define MIPI_CSIS_INTMSK_EVEN_BEFORE (1 << 31) +#define MIPI_CSIS_INTMSK_EVEN_AFTER (1 << 30) +#define MIPI_CSIS_INTMSK_ODD_BEFORE (1 << 29) +#define MIPI_CSIS_INTMSK_ODD_AFTER (1 << 28) +#define MIPI_CSIS_INTMSK_FRAME_START (1 << 24) +#define MIPI_CSIS_INTMSK_FRAME_END (1 << 20) +#define MIPI_CSIS_INTMSK_ERR_SOT_HS (1 << 16) +#define MIPI_CSIS_INTMSK_ERR_LOST_FS (1 << 12) +#define MIPI_CSIS_INTMSK_ERR_LOST_FE (1 << 8) +#define MIPI_CSIS_INTMSK_ERR_OVER (1 << 4) +#define MIPI_CSIS_INTMSK_ERR_WRONG_CFG (1 << 3) +#define MIPI_CSIS_INTMSK_ERR_ECC (1 << 2) +#define MIPI_CSIS_INTMSK_ERR_CRC (1 << 1) +#define MIPI_CSIS_INTMSK_ERR_UNKNOWN (1 << 0) + +/* CSIS Interrupt source */ +#define MIPI_CSIS_INTSRC 0x14 +#define MIPI_CSIS_INTSRC_EVEN_BEFORE (1 << 31) +#define MIPI_CSIS_INTSRC_EVEN_AFTER (1 << 30) +#define MIPI_CSIS_INTSRC_EVEN (0x3 << 30) +#define MIPI_CSIS_INTSRC_ODD_BEFORE (1 << 29) +#define MIPI_CSIS_INTSRC_ODD_AFTER (1 << 28) +#define MIPI_CSIS_INTSRC_ODD (0x3 << 28) +#define MIPI_CSIS_INTSRC_NON_IMAGE_DATA (0xf << 28) +#define MIPI_CSIS_INTSRC_FRAME_START (1 << 24) +#define MIPI_CSIS_INTSRC_FRAME_END (1 << 20) +#define MIPI_CSIS_INTSRC_ERR_SOT_HS (1 << 16) +#define MIPI_CSIS_INTSRC_ERR_LOST_FS (1 << 12) +#define MIPI_CSIS_INTSRC_ERR_LOST_FE (1 << 8) +#define MIPI_CSIS_INTSRC_ERR_OVER (1 << 4) +#define MIPI_CSIS_INTSRC_ERR_WRONG_CFG (1 << 3) +#define MIPI_CSIS_INTSRC_ERR_ECC (1 << 2) +#define MIPI_CSIS_INTSRC_ERR_CRC (1 << 1) +#define MIPI_CSIS_INTSRC_ERR_UNKNOWN (1 << 0) +#define MIPI_CSIS_INTSRC_ERRORS 0xfffff + +/* D-PHY status control */ +#define MIPI_CSIS_DPHYSTATUS 0x20 +#define MIPI_CSIS_DPHYSTATUS_ULPS_DAT (1 << 8) +#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT (1 << 4) +#define MIPI_CSIS_DPHYSTATUS_ULPS_CLK (1 << 1) +#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK (1 << 0) + +/* D-PHY common control */ +#define MIPI_CSIS_DPHYCTRL 0x24 +#define MIPI_CSIS_DPHYCTRL_HSS_MASK (0xff << 24) +#define MIPI_CSIS_DPHYCTRL_HSS_OFFSET 24 +#define MIPI_CSIS_DPHYCTRL_SCLKS_MASK (0x3 << 22) +#define MIPI_CSIS_DPHYCTRL_SCLKS_OFFSET 22 +#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK (1 << 6) +#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT (1 << 5) +#define MIPI_CSIS_DPHYCTRL_ENABLE_DAT (1 << 1) +#define MIPI_CSIS_DPHYCTRL_ENABLE_CLK (1 << 0) +#define MIPI_CSIS_DPHYCTRL_ENABLE (0x1f << 0) + +/* D-PHY Master and Slave Control register Low */ +#define MIPI_CSIS_DPHYBCTRL_L 0x30 +/* D-PHY Master and Slave Control register High */ +#define MIPI_CSIS_DPHYBCTRL_H 0x34 +/* D-PHY Slave Control register Low */ +#define MIPI_CSIS_DPHYSCTRL_L 0x38 +/* D-PHY Slave Control register High */ +#define MIPI_CSIS_DPHYSCTRL_H 0x3c + +/* ISP Configuration register */ +#define MIPI_CSIS_ISPCONFIG_CH0 0x40 +#define MIPI_CSIS_ISPCONFIG_CH0_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH0_PIXEL_MODE_SHIFT 12 + +#define MIPI_CSIS_ISPCONFIG_CH1 0x50 +#define MIPI_CSIS_ISPCONFIG_CH1_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH1_PIXEL_MODE_SHIFT 12 + +#define MIPI_CSIS_ISPCONFIG_CH2 0x60 +#define MIPI_CSIS_ISPCONFIG_CH2_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH2_PIXEL_MODE_SHIFT 12 + +#define MIPI_CSIS_ISPCONFIG_CH3 0x70 +#define MIPI_CSIS_ISPCONFIG_CH3_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH3_PIXEL_MODE_SHIFT 12 + +#define PIXEL_MODE_SINGLE_PIXEL_MODE 0x0 +#define PIXEL_MODE_DUAL_PIXEL_MODE 0x1 +#define PIXEL_MODE_QUAD_PIXEL_MODE 0x2 +#define PIXEL_MODE_INVALID_PIXEL_MODE 0x3 + +#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) +#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) (x << 24) +#define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT (1 << 12) +#define MIPI_CSIS_ISPCFG_ALIGN_32BIT (1 << 11) +#define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT (0x1e << 2) +#define MIPI_CSIS_ISPCFG_FMT_RAW8 (0x2a << 2) +#define MIPI_CSIS_ISPCFG_FMT_RAW10 (0x2b << 2) +#define MIPI_CSIS_ISPCFG_FMT_RAW12 (0x2c << 2) +#define MIPI_CSIS_ISPCFG_FMT_RGB888 (0x24 << 2) +#define MIPI_CSIS_ISPCFG_FMT_RGB565 (0x22 << 2) +/* User defined formats, x = 1...4 */ +#define MIPI_CSIS_ISPCFG_FMT_USER(x) ((0x30 + x - 1) << 2) +#define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) + +/* ISP Image Resolution register */ +#define MIPI_CSIS_ISPRESOL_CH0 0x44 +#define MIPI_CSIS_ISPRESOL_CH1 0x54 +#define MIPI_CSIS_ISPRESOL_CH2 0x64 +#define MIPI_CSIS_ISPRESOL_CH3 0x74 +#define CSIS_MAX_PIX_WIDTH 0xffff +#define CSIS_MAX_PIX_HEIGHT 0xffff + +/* ISP SYNC register */ +#define MIPI_CSIS_ISPSYNC_CH0 0x48 +#define MIPI_CSIS_ISPSYNC_CH1 0x58 +#define MIPI_CSIS_ISPSYNC_CH2 0x68 +#define MIPI_CSIS_ISPSYNC_CH3 0x78 + +#define MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET 18 +#define MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET 12 +#define MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET 0 + +#define MIPI_CSIS_FRAME_COUNTER_CH0 0x0100 +#define MIPI_CSIS_FRAME_COUNTER_CH1 0x0104 +#define MIPI_CSIS_FRAME_COUNTER_CH2 0x0108 +#define MIPI_CSIS_FRAME_COUNTER_CH3 0x010C + +/* Non-image packet data buffers */ +#define MIPI_CSIS_PKTDATA_ODD 0x2000 +#define MIPI_CSIS_PKTDATA_EVEN 0x3000 +#define MIPI_CSIS_PKTDATA_SIZE SZ_4K + +#define DEFAULT_SCLK_CSIS_FREQ 166000000UL + +/* display_mix_clk_en_csr */ +#define DISP_MIX_GASKET_0_CTRL 0x00 +#define GASKET_0_CTRL_DATA_TYPE(x) (((x) & (0x3F)) << 8) +#define GASKET_0_CTRL_DATA_TYPE_MASK ((0x3FUL) << (8)) + +#define GASKET_0_CTRL_DATA_TYPE_YUV420_8 0x18 +#define GASKET_0_CTRL_DATA_TYPE_YUV420_10 0x19 +#define GASKET_0_CTRL_DATA_TYPE_LE_YUV420_8 0x1a +#define GASKET_0_CTRL_DATA_TYPE_CS_YUV420_8 0x1c +#define GASKET_0_CTRL_DATA_TYPE_CS_YUV420_10 0x1d +#define GASKET_0_CTRL_DATA_TYPE_YUV422_8 0x1e +#define GASKET_0_CTRL_DATA_TYPE_YUV422_10 0x1f +#define GASKET_0_CTRL_DATA_TYPE_RGB565 0x22 +#define GASKET_0_CTRL_DATA_TYPE_RGB666 0x23 +#define GASKET_0_CTRL_DATA_TYPE_RGB888 0x24 +#define GASKET_0_CTRL_DATA_TYPE_RAW6 0x28 +#define GASKET_0_CTRL_DATA_TYPE_RAW7 0x29 +#define GASKET_0_CTRL_DATA_TYPE_RAW8 0x2a +#define GASKET_0_CTRL_DATA_TYPE_RAW10 0x2b +#define GASKET_0_CTRL_DATA_TYPE_RAW12 0x2c +#define GASKET_0_CTRL_DATA_TYPE_RAW14 0x2d + +#define GASKET_0_CTRL_DUAL_COMP_ENABLE BIT(1) +#define GASKET_0_CTRL_ENABLE BIT(0) + +#define DISP_MIX_GASKET_0_HSIZE 0x04 +#define DISP_MIX_GASKET_0_VSIZE 0x08 + +struct mipi_csis_event { + u32 mask; + const char *const name; + unsigned int counter; +}; + +/** + * struct csis_pix_format - CSIS pixel format description + * @pix_width_alignment: horizontal pixel alignment, width will be + * multiple of 2^pix_width_alignment + * @code: corresponding media bus code + * @fmt_reg: MIPI_CSIS_CONFIG register value + * @data_alignment: MIPI-CSI data alignment in bits + */ +struct csis_pix_format { + unsigned int pix_width_alignment; + u32 code; + u32 fmt_reg; + u8 data_alignment; +}; + +struct csis_pktbuf { + u32 *data; + unsigned int len; +}; + +struct csis_hw_reset1 { + struct regmap *src; + u8 req_src; + u8 rst_bit; +}; + +struct csi_state; +typedef int (*mipi_csis_phy_reset_t) (struct csi_state *state); + +static const struct mipi_csis_event mipi_csis_events[] = { + /* Errors */ + {MIPI_CSIS_INTSRC_ERR_SOT_HS, "SOT Error"}, + {MIPI_CSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error"}, + {MIPI_CSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error"}, + {MIPI_CSIS_INTSRC_ERR_OVER, "FIFO Overflow Error"}, + {MIPI_CSIS_INTSRC_ERR_ECC, "ECC Error"}, + {MIPI_CSIS_INTSRC_ERR_CRC, "CRC Error"}, + {MIPI_CSIS_INTSRC_ERR_UNKNOWN, "Unknown Error"}, + /* Non-image data receive events */ + {MIPI_CSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame"}, + {MIPI_CSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame"}, + {MIPI_CSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame"}, + {MIPI_CSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame"}, + /* Frame start/end */ + {MIPI_CSIS_INTSRC_FRAME_START, "Frame Start"}, + {MIPI_CSIS_INTSRC_FRAME_END, "Frame End"}, +}; + +#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) + +/** + * struct csi_state - the driver's internal state data structure + * @lock: mutex serializing the subdev and power management operations, + * protecting @format and @flags members + * @sd: v4l2_subdev associated with CSIS device instance + * @index: the hardware instance index + * @pdev: CSIS platform device + * @phy: pointer to the CSIS generic PHY + * @regs: mmaped I/O registers memory + * @supplies: CSIS regulator supplies + * @clock: CSIS clocks + * @irq: requested s5p-mipi-csis irq number + * @flags: the state variable for power and streaming control + * @clock_frequency: device bus clock frequency + * @hs_settle: HS-RX settle time + * @clk_settle: Clk settle time + * @num_lanes: number of MIPI-CSI data lanes used + * @max_num_lanes: maximum number of MIPI-CSI data lanes supported + * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM + * @csis_fmt: current CSIS pixel format + * @format: common media bus format for the source and sink pad + * @slock: spinlock protecting structure members below + * @pkt_buf: the frame embedded (non-image) data buffer + * @events: MIPI-CSIS event (error) counters + */ +struct csi_state { + struct v4l2_subdev sd; + struct mutex lock; + struct device *dev; + struct v4l2_device *v4l2_dev; + + struct media_pad pads[MIPI_CSIS_VCX_PADS_NUM]; + + u8 index; + struct platform_device *pdev; + struct phy *phy; + void __iomem *regs; + struct clk *mipi_clk; + struct clk *phy_clk; + struct clk *disp_axi; + struct clk *disp_apb; + int irq; + u32 flags; + + u32 clk_frequency; + u32 hs_settle; + u32 clk_settle; + u32 num_lanes; + u32 max_num_lanes; + u8 wclk_ext; + + u8 vchannel; + const struct csis_pix_format *csis_fmt; + struct v4l2_mbus_framefmt format; + + spinlock_t slock; + struct csis_pktbuf pkt_buf; + struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; + + struct v4l2_async_subdev asd; + struct v4l2_async_notifier subdev_notifier; + struct v4l2_async_subdev *async_subdevs[2]; + + struct csis_hw_reset1 hw_reset; + struct regulator *mipi_phy_regulator; + + struct regmap *gasket; + struct regmap *gpr; + struct regmap *mix_gpr; + struct reset_control *soft_resetn; + struct reset_control *clk_enable; + struct reset_control *mipi_reset; + + mipi_csis_phy_reset_t phy_reset_fn; + bool hdr; +}; + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug level (0-2)"); + +static const struct csis_pix_format mipi_csis_formats[] = { + { + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGBRG10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGRBG10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SRGGB10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SBGGR12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGBRG12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGRBG12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SRGGB12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_RGB888_1X24, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RGB888, + .data_alignment = 24, + }, + { + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_VYUY8_2X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SBGGR8_1X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8, + .data_alignment = 8, + } +}; + +typedef int (*mipi_csis_phy_reset_t) (struct csi_state *state); + +#define mipi_csis_write(__csis, __r, __v) writel(__v, __csis->regs + __r) +#define mipi_csis_read(__csis, __r) readl(__csis->regs + __r) + +static void dump_csis_regs(struct csi_state *state, const char *label) +{ + struct { + u32 offset; + const char *const name; + } registers[] = { + { + 0x00, "CSIS_VERSION"}, { + 0x04, "CSIS_CMN_CTRL"}, { + 0x08, "CSIS_CLK_CTRL"}, { + 0x10, "CSIS_INTMSK"}, { + 0x14, "CSIS_INTSRC"}, { + 0x20, "CSIS_DPHYSTATUS"}, { + 0x24, "CSIS_DPHYCTRL"}, { + 0x30, "CSIS_DPHYBCTRL_L"}, { + 0x34, "CSIS_DPHYBCTRL_H"}, { + 0x38, "CSIS_DPHYSCTRL_L"}, { + 0x3C, "CSIS_DPHYSCTRL_H"}, { + 0x40, "CSIS_ISPCONFIG_CH0"}, { + 0x50, "CSIS_ISPCONFIG_CH1"}, { + 0x60, "CSIS_ISPCONFIG_CH2"}, { + 0x70, "CSIS_ISPCONFIG_CH3"}, { + 0x44, "CSIS_ISPRESOL_CH0"}, { + 0x54, "CSIS_ISPRESOL_CH1"}, { + 0x64, "CSIS_ISPRESOL_CH2"}, { + 0x74, "CSIS_ISPRESOL_CH3"}, { + 0x48, "CSIS_ISPSYNC_CH0"}, { + 0x58, "CSIS_ISPSYNC_CH1"}, { + 0x68, "CSIS_ISPSYNC_CH2"}, { + 0x78, "CSIS_ISPSYNC_CH3"},}; + u32 i; + + v4l2_dbg(2, debug, &state->sd, "--- %s ---\n", label); + + for (i = 0; i < ARRAY_SIZE(registers); i++) { + u32 cfg = mipi_csis_read(state, registers[i].offset); + v4l2_dbg(2, debug, &state->sd, "%20s[%x]: 0x%.8x\n", + registers[i].name, registers[i].offset, cfg); + } +} + +static void dump_gasket_regs(struct csi_state *state, const char *label) +{ + struct { + u32 offset; + const char *const name; + } registers[] = { + { + 0x60, "GPR_GASKET_0_CTRL"}, { + 0x64, "GPR_GASKET_0_HSIZE"}, { + 0x68, "GPR_GASKET_0_VSIZE"},}; + u32 i, cfg; + + v4l2_dbg(2, debug, &state->sd, "--- %s ---\n", label); + + for (i = 0; i < ARRAY_SIZE(registers); i++) { + regmap_read(state->gasket, registers[i].offset, &cfg); + v4l2_dbg(2, debug, &state->sd, "%20s[%x]: 0x%.8x\n", + registers[i].name, registers[i].offset, cfg); + } +} + +static inline struct csi_state *mipi_sd_to_csi_state(struct v4l2_subdev *sdev) +{ + return container_of(sdev, struct csi_state, sd); +} + +static inline struct csi_state *notifier_to_mipi_dev( + struct v4l2_async_notifier *n) +{ + return container_of(n, struct csi_state, subdev_notifier); +} + +static struct media_pad *csis_get_remote_sensor_pad(struct csi_state *state) +{ + struct v4l2_subdev *subdev = &state->sd; + struct media_pad *sink_pad, *source_pad; + int i; + + while (1) { + source_pad = NULL; + for (i = 0; i < subdev->entity.num_pads; i++) { + sink_pad = &subdev->entity.pads[i]; + + if (sink_pad->flags & MEDIA_PAD_FL_SINK) { + source_pad = media_entity_remote_pad(sink_pad); + if (source_pad) + break; + } + } + /* return first pad point in the loop */ + return source_pad; + } + + if (i == subdev->entity.num_pads) + v4l2_err(&state->sd, "%s, No remote pad found!\n", __func__); + + return NULL; +} + +static struct v4l2_subdev *csis_get_remote_subdev(struct csi_state *state, + const char *const label) +{ + struct media_pad *source_pad; + struct v4l2_subdev *sen_sd; + + /* Get remote source pad */ + source_pad = csis_get_remote_sensor_pad(state); + if (!source_pad) { + v4l2_err(&state->sd, "%s, No remote pad found!\n", label); + return NULL; + } + + /* Get remote source pad subdev */ + sen_sd = media_entity_to_v4l2_subdev(source_pad->entity); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", label); + return NULL; + } + + return sen_sd; +} + +const struct csis_pix_format *find_csis_format(u32 code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) + if (code == mipi_csis_formats[i].code) + return &mipi_csis_formats[i]; + return NULL; +} + +#ifdef CSI_HW_INTERRUPT +static void mipi_csis_clean_irq(struct csi_state *state) +{ + u32 status; + + status = mipi_csis_read(state, MIPI_CSIS_INTSRC); + mipi_csis_write(state, MIPI_CSIS_INTSRC, status); + + status = mipi_csis_read(state, MIPI_CSIS_INTMSK); + mipi_csis_write(state, MIPI_CSIS_INTMSK, status); +} + +static void mipi_csis_enable_interrupts(struct csi_state *state, bool on) +{ + u32 val; + + mipi_csis_clean_irq(state); + + val = mipi_csis_read(state, MIPI_CSIS_INTMSK); + if (on) + val |= 0x0FFFFF1F; + else + val &= ~0x0FFFFF1F; + mipi_csis_write(state, MIPI_CSIS_INTMSK, val); +} +#endif + +void mipi_csis_sw_reset(struct csi_state *state) +{ + u32 val; + + val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); + val |= MIPI_CSIS_CMN_CTRL_RESET; + mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); + + udelay(20); +} + +static int mipi_csis_phy_init(struct csi_state *state) +{ + state->mipi_phy_regulator = devm_regulator_get(state->dev, "mipi-phy"); + if (IS_ERR(state->mipi_phy_regulator)) { + dev_err(state->dev, "Fail to get mipi-phy regulator\n"); + return PTR_ERR(state->mipi_phy_regulator); + } + + regulator_set_voltage(state->mipi_phy_regulator, 1000000, 1000000); + return 0; +} + +static void mipi_csis_phy_reset_mx8mn(struct csi_state *state) +{ +#if 0 + struct reset_control *reset = state->mipi_reset; + + reset_control_assert(reset); + usleep_range(10, 20); + + reset_control_deassert(reset); + usleep_range(10, 20); +#else + u32 val; + + regmap_read(state->gpr, 0x00, &val); + val |= 0x30000; + if (state->index == 1) + val |= 0x40000000; + regmap_write(state->gpr, 0x00, val); + regmap_write(state->mix_gpr, 0x138, 0x8d8360); + +#endif +} + +static void mipi_csis_system_enable(struct csi_state *state, int on) +{ + u32 val, mask; + + val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); + if (on) + val |= MIPI_CSIS_CMN_CTRL_ENABLE; + else + val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; + mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); + + val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL); + val &= ~MIPI_CSIS_DPHYCTRL_ENABLE; + if (on) { + mask = (1 << (state->num_lanes + 1)) - 1; + val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE); + } + mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val); +} + +/* Called with the state.lock mutex held */ +static void __mipi_csis_set_format(struct csi_state *state) +{ + struct v4l2_mbus_framefmt *mf = &state->format; + u32 val; + + v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n", + mf->code, mf->width, mf->height); + + /* Color format */ + val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0); + val &= ~MIPI_CSIS_ISPCFG_FMT_MASK; + val |= state->csis_fmt->fmt_reg; + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val); + + val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0); + val &= ~MIPI_CSIS_ISPCONFIG_CH0_PIXEL_MODE_MASK; + if (state->csis_fmt->fmt_reg == MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT) + val |= (PIXEL_MODE_DUAL_PIXEL_MODE << + MIPI_CSIS_ISPCONFIG_CH0_PIXEL_MODE_SHIFT); + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val); + + /* Pixel resolution */ + val = mf->width | (mf->height << 16); + mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val); + if (state->hdr) { + mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH1, val); + mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH2, val); + mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH3, val); + val = state->csis_fmt->fmt_reg; + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH1, val | 1); + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH2, val | 2); + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH3, val | 3); + } +} + +static void mipi_csis_set_hsync_settle(struct csi_state *state) +{ + u32 val; + + val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL); + val &= ~MIPI_CSIS_DPHYCTRL_HSS_MASK; + val |= (state->hs_settle << 24) | (state->clk_settle << 22); + mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val); +} + +void mipi_csis_set_params(struct csi_state *state) +{ + u32 val; + val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); + val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; + val |= (state->num_lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; + val |= MIPI_CSIS_CMN_CTRL_HDR_MODE; + mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); + + __mipi_csis_set_format(state); + mipi_csis_set_hsync_settle(state); + + val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0); + if (state->csis_fmt->data_alignment == 32) + val |= MIPI_CSIS_ISPCFG_ALIGN_32BIT; + else /* Normal output */ + val &= ~MIPI_CSIS_ISPCFG_ALIGN_32BIT; + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val); + + val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) | + (0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) | + (0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET); + mipi_csis_write(state, MIPI_CSIS_ISPSYNC_CH0, val); + + val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL); + val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC; + if (state->wclk_ext) + val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; + val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); + val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; + mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val); + + mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_L, 0x1f4); + mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_H, 0); + + /* Update the shadow register. */ + val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); + val |= (MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | + MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); + if (state->hdr) { + val |= MIPI_CSIS_CMN_CTRL_HDR_MODE; + val |= 0xE0000; + } + mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); +} + +static int mipi_csis_clk_enable(struct csi_state *state) +{ + struct device *dev = state->dev; + int ret; + + ret = clk_prepare_enable(state->mipi_clk); + if (ret) { + dev_err(dev, "enable mipi_clk failed!\n"); + return ret; + } +#if 0 + ret = clk_prepare_enable(state->phy_clk); + if (ret) { + dev_err(dev, "enable phy_clk failed!\n"); + return ret; + } + + ret = clk_prepare_enable(state->disp_axi); + if (ret) { + dev_err(dev, "enable disp_axi clk failed!\n"); + return ret; + } + + ret = clk_prepare_enable(state->disp_apb); + if (ret) { + dev_err(dev, "enable disp_apb clk failed!\n"); + return ret; + } +#endif + return 0; +} + +static void mipi_csis_clk_disable(struct csi_state *state) +{ + clk_disable_unprepare(state->mipi_clk); +#if 0 + clk_disable_unprepare(state->phy_clk); + clk_disable_unprepare(state->disp_axi); + clk_disable_unprepare(state->disp_apb); +#endif +} + +static int mipi_csis_clk_get(struct csi_state *state) +{ + struct device *dev = &state->pdev->dev; + int ret = true; + + state->mipi_clk = devm_clk_get(dev, "mipi_clk"); + if (IS_ERR(state->mipi_clk)) { + dev_err(dev, "Could not get mipi csi clock\n"); + return -ENODEV; + } +#if 0 + state->phy_clk = devm_clk_get(dev, "phy_clk"); + if (IS_ERR(state->phy_clk)) { + dev_err(dev, "Could not get mipi phy clock\n"); + return -ENODEV; + } + + state->disp_axi = devm_clk_get(dev, "disp_axi"); + if (IS_ERR(state->disp_axi)) { + dev_warn(dev, "Could not get disp_axi clock\n"); + return -ENODEV; + } + + state->disp_apb = devm_clk_get(dev, "disp_apb"); + if (IS_ERR(state->disp_apb)) { + dev_warn(dev, "Could not get disp apb clock\n"); + return -ENODEV; + } +#endif + /* Set clock rate */ + if (state->clk_frequency) { + ret = clk_set_rate(state->mipi_clk, state->clk_frequency); + if (ret < 0) { + dev_err(dev, "set rate filed, rate=%d\n", + state->clk_frequency); + return -EINVAL; + } + } else { + dev_WARN(dev, "No clock frequency specified!\n"); + } + + return 0; +} + +static int disp_mix_sft_rstn(struct reset_control *reset, bool enable) +{ +#if 0 + int ret; + + ret = enable ? reset_control_assert(reset) : + reset_control_deassert(reset); + return ret; +#else + return 0; +#endif +} + +static int disp_mix_clks_enable(struct reset_control *reset, bool enable) +{ +#if 0 + int ret; + + ret = enable ? reset_control_assert(reset) : + reset_control_deassert(reset); + return ret; +#else + return 0; +#endif +} + +void disp_mix_gasket_config(struct csi_state *state) +{ + struct regmap *gasket = state->gasket; + struct csis_pix_format const *fmt = state->csis_fmt; + struct v4l2_mbus_framefmt *mf = &state->format; + s32 fmt_val = -EINVAL; + u32 val; + + switch (fmt->code) { + case MEDIA_BUS_FMT_RGB888_1X24: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RGB888; + break; + case MEDIA_BUS_FMT_YUYV8_2X8: + case MEDIA_BUS_FMT_YVYU8_2X8: + case MEDIA_BUS_FMT_UYVY8_2X8: + case MEDIA_BUS_FMT_VYUY8_2X8: + fmt_val = GASKET_0_CTRL_DATA_TYPE_YUV422_8; + break; + case MEDIA_BUS_FMT_SBGGR10_1X10: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW10; + break; + case MEDIA_BUS_FMT_SGBRG10_1X10: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW10; + break; + case MEDIA_BUS_FMT_SGRBG10_1X10: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW10; + break; + case MEDIA_BUS_FMT_SRGGB10_1X10: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW10; + break; + case MEDIA_BUS_FMT_SBGGR12_1X12: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW12; + break; + case MEDIA_BUS_FMT_SGBRG12_1X12: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW12; + break; + case MEDIA_BUS_FMT_SGRBG12_1X12: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW12; + break; + case MEDIA_BUS_FMT_SRGGB12_1X12: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW12; + break; + default: + pr_err("gasket not support format %d\n", fmt->code); + return; + } + + regmap_read(gasket, DISP_MIX_GASKET_0_CTRL, &val); + if (fmt_val == GASKET_0_CTRL_DATA_TYPE_YUV422_8) + val |= GASKET_0_CTRL_DUAL_COMP_ENABLE; + val |= GASKET_0_CTRL_DATA_TYPE(fmt_val); + regmap_write(gasket, DISP_MIX_GASKET_0_CTRL, val); + + if (WARN_ON(!mf->width || !mf->height)) + return; + + regmap_write(gasket, DISP_MIX_GASKET_0_HSIZE, mf->width); + regmap_write(gasket, DISP_MIX_GASKET_0_VSIZE, mf->height); +} + +static void disp_mix_gasket_enable(struct csi_state *state, bool enable) +{ + struct regmap *gasket = state->gasket; + + if (enable) + regmap_update_bits(gasket, DISP_MIX_GASKET_0_CTRL, + GASKET_0_CTRL_ENABLE, GASKET_0_CTRL_ENABLE); + else + regmap_update_bits(gasket, DISP_MIX_GASKET_0_CTRL, + GASKET_0_CTRL_ENABLE, 0); +} + +static void mipi_csis_start_stream(struct csi_state *state) +{ + mipi_csis_sw_reset(state); + + disp_mix_gasket_config(state); + mipi_csis_set_params(state); + + mipi_csis_system_enable(state, true); + disp_mix_gasket_enable(state, true); +#ifdef CSI_HW_INTERRUPT + mipi_csis_enable_interrupts(state, true); +#endif + msleep(5); +} + +static void mipi_csis_stop_stream(struct csi_state *state) +{ +#ifdef CSI_HW_INTERRUPT + mipi_csis_enable_interrupts(state, false); +#endif + mipi_csis_system_enable(state, false); + disp_mix_gasket_enable(state, false); +} + +static void mipi_csis_clear_counters(struct csi_state *state) +{ + unsigned long flags; + int i; + + spin_lock_irqsave(&state->slock, flags); + for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) + state->events[i].counter = 0; + spin_unlock_irqrestore(&state->slock, flags); +} + +static void mipi_csis_log_counters(struct csi_state *state, bool non_errors) +{ + int i = non_errors ? MIPI_CSIS_NUM_EVENTS : MIPI_CSIS_NUM_EVENTS - 4; + unsigned long flags; + + spin_lock_irqsave(&state->slock, flags); + + for (i--; i >= 0; i--) { + if (state->events[i].counter > 0 || debug) + v4l2_info(&state->sd, "%s events: %d\n", + state->events[i].name, + state->events[i].counter); + } + spin_unlock_irqrestore(&state->slock, flags); +} + +static int mipi_csi2_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static const struct media_entity_operations mipi_csi2_sd_media_ops = { + .link_setup = mipi_csi2_link_setup, +}; + +/* + * V4L2 subdev operations + */ +int mipi_csis_s_power(struct v4l2_subdev *mipi_sd, int on) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, core, s_power, on); +} + +int mipi_csis_s_stream(struct v4l2_subdev *mipi_sd, int enable) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + + v4l2_dbg(1, debug, mipi_sd, "%s: %d, state: 0x%x\n", + __func__, enable, state->flags); + + if (enable) { + pm_runtime_get_sync(state->dev); + mipi_csis_clear_counters(state); + mipi_csis_start_stream(state); + dump_csis_regs(state, __func__); + dump_gasket_regs(state, __func__); + } else { + mipi_csis_stop_stream(state); + if (debug > 0) + mipi_csis_log_counters(state, true); + pm_runtime_put(state->dev); + } + + return 0; +} + +static int mipi_csis_set_fmt(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_mbus_framefmt *mf = &format->format; + struct csis_pix_format const *csis_fmt; + struct media_pad *source_pad; + struct v4l2_subdev *sen_sd; + int ret; + + /* Get remote source pad */ + source_pad = csis_get_remote_sensor_pad(state); + if (!source_pad) { + v4l2_err(&state->sd, "%s, No remote pad found!\n", __func__); + return -EINVAL; + } + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + format->pad = source_pad->index; + mf->code = MEDIA_BUS_FMT_UYVY8_2X8; + ret = v4l2_subdev_call(sen_sd, pad, set_fmt, NULL, format); + if (ret < 0) { + v4l2_err(&state->sd, "%s, set sensor format fail\n", __func__); + return -EINVAL; + } + + csis_fmt = find_csis_format(mf->code); + if (!csis_fmt) { + csis_fmt = &mipi_csis_formats[0]; + mf->code = csis_fmt->code; + } + + return 0; +} + +static int mipi_csis_get_fmt(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_mbus_framefmt *mf = &state->format; + struct media_pad *source_pad; + struct v4l2_subdev *sen_sd; + int ret; + + /* Get remote source pad */ + source_pad = csis_get_remote_sensor_pad(state); + if (!source_pad) { + v4l2_err(&state->sd, "%s, No remote pad found!\n", __func__); + return -EINVAL; + } + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + format->pad = source_pad->index; + ret = v4l2_subdev_call(sen_sd, pad, get_fmt, NULL, format); + if (ret < 0) { + v4l2_err(&state->sd, "%s, call get_fmt of subdev failed!\n", + __func__); + return ret; + } + + memcpy(mf, &format->format, sizeof(struct v4l2_mbus_framefmt)); + return 0; +} + +static int mipi_csis_s_rx_buffer(struct v4l2_subdev *mipi_sd, void *buf, + unsigned int *size) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + unsigned long flags; + + *size = min_t(unsigned int, *size, MIPI_CSIS_PKTDATA_SIZE); + + spin_lock_irqsave(&state->slock, flags); + state->pkt_buf.data = buf; + state->pkt_buf.len = *size; + spin_unlock_irqrestore(&state->slock, flags); + + return 0; +} + +static int mipi_csis_s_frame_interval(struct v4l2_subdev *mipi_sd, struct v4l2_subdev_frame_interval + *interval) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, video, s_frame_interval, interval); +} + +static int mipi_csis_g_frame_interval(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, video, g_frame_interval, interval); +} + +static int mipi_csis_enum_framesizes(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, pad, enum_frame_size, NULL, fse); +} + +static int mipi_csis_enum_frameintervals(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum + *fie) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, pad, enum_frame_interval, NULL, fie); +} + +static int mipi_csis_log_status(struct v4l2_subdev *mipi_sd) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + + mutex_lock(&state->lock); + mipi_csis_log_counters(state, true); + if (debug) { + dump_csis_regs(state, __func__); + dump_gasket_regs(state, __func__); + } + mutex_unlock(&state->lock); + return 0; +} + + +int csis_s_fmt(struct v4l2_subdev *sd, struct csi_sam_format *fmt) +{ + u32 code; + const struct csis_pix_format *csis_format; + struct csi_state *state = container_of(sd, struct csi_state, sd); + + switch (fmt->format) { + case V4L2_PIX_FMT_SBGGR10: + code = MEDIA_BUS_FMT_SBGGR10_1X10; + break; + case V4L2_PIX_FMT_SGBRG10: + code = MEDIA_BUS_FMT_SGBRG10_1X10; + break; + case V4L2_PIX_FMT_SGRBG10: + code = MEDIA_BUS_FMT_SGRBG10_1X10; + break; + case V4L2_PIX_FMT_SRGGB10: + code = MEDIA_BUS_FMT_SRGGB10_1X10; + break; + case V4L2_PIX_FMT_SBGGR12: + code = MEDIA_BUS_FMT_SBGGR12_1X12; + break; + case V4L2_PIX_FMT_SGBRG12: + code = MEDIA_BUS_FMT_SGBRG12_1X12; + break; + case V4L2_PIX_FMT_SGRBG12: + code = MEDIA_BUS_FMT_SGRBG12_1X12; + break; + case V4L2_PIX_FMT_SRGGB12: + code = MEDIA_BUS_FMT_SRGGB12_1X12; + break; + default: + return -EINVAL; + } + csis_format = find_csis_format(code); + if (csis_format == NULL) + return -EINVAL; + + state->csis_fmt = csis_format; + state->format.width = fmt->width; + state->format.height = fmt->height; + disp_mix_gasket_config(state); + mipi_csis_set_params(state); + return 0; +} + +int csis_s_hdr(struct v4l2_subdev *sd, bool enable) +{ + struct csi_state *state = container_of(sd, struct csi_state, sd); + pr_debug("enter %s: %d\n", __func__, enable); + state->hdr = enable; + return 0; +} + +int csis_ioc_qcap(struct v4l2_subdev *dev, void *args) +{ + struct csi_state *state = mipi_sd_to_csi_state(dev); + struct v4l2_capability *cap = (struct v4l2_capability *)args; + strcpy((char *)cap->driver, "csi_sam_subdev"); + cap->bus_info[0] = state->index; + return 0; +} + +#ifdef CONFIG_HARDENED_USERCOPY +#define USER_TO_KERNEL(TYPE) \ + do {\ + TYPE tmp; \ + arg = (void *)(&tmp); \ + copy_from_user(arg, arg_user, sizeof(TYPE));\ + } while (0) + +#define KERNEL_TO_USER(TYPE) \ + copy_to_user(arg_user, arg, sizeof(TYPE)); +#else +#define USER_TO_KERNEL(TYPE) +#define KERNEL_TO_USER(TYPE) +#endif +long csis_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg_user) +{ + int ret = 1; + struct csi_state *state = container_of(sd, struct csi_state, sd); + void *arg = arg_user; + + pr_debug("enter %s\n", __func__); + switch (cmd) { + case VVCSIOC_RESET: + mipi_csis_sw_reset(state); + ret = 0; + break; + case VVCSIOC_POWERON: + ret = mipi_csis_s_power(sd, 1); + break; + case VVCSIOC_POWEROFF: + ret = mipi_csis_s_power(sd, 0); + break; + case VVCSIOC_STREAMON: + ret = mipi_csis_s_stream(sd, 1); + break; + case VVCSIOC_STREAMOFF: + ret = mipi_csis_s_stream(sd, 0); + break; + case VVCSIOC_S_FMT: { + USER_TO_KERNEL(struct csi_sam_format); + ret = csis_s_fmt(sd, (struct csi_sam_format *)arg); + break; + } + case VVCSIOC_S_HDR: { + USER_TO_KERNEL(bool); + ret = csis_s_hdr(sd, *(bool *) arg); + break; + } + case VIDIOC_QUERYCAP: + ret = csis_ioc_qcap(sd, arg); + break; + default: + pr_err("unsupported csi-sam command %d.", cmd); + break; + } + + return ret; +} + +static struct v4l2_subdev_core_ops mipi_csis_core_ops = { + .s_power = mipi_csis_s_power, + .log_status = mipi_csis_log_status, + .ioctl = csis_priv_ioctl, +}; + +static struct v4l2_subdev_video_ops mipi_csis_video_ops = { + .s_rx_buffer = mipi_csis_s_rx_buffer, + .s_stream = mipi_csis_s_stream, + + .g_frame_interval = mipi_csis_g_frame_interval, + .s_frame_interval = mipi_csis_s_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { + .enum_frame_size = mipi_csis_enum_framesizes, + .enum_frame_interval = mipi_csis_enum_frameintervals, + .get_fmt = mipi_csis_get_fmt, + .set_fmt = mipi_csis_set_fmt, +}; + +static struct v4l2_subdev_ops mipi_csis_subdev_ops = { + .core = &mipi_csis_core_ops, + .video = &mipi_csis_video_ops, + .pad = &mipi_csis_pad_ops, +}; + +#ifdef CSI_HW_INTERRUPT +static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) +{ + struct csi_state *state = dev_id; + struct csis_pktbuf *pktbuf = &state->pkt_buf; + unsigned long flags; + u32 status; + + status = mipi_csis_read(state, MIPI_CSIS_INTSRC); + + spin_lock_irqsave(&state->slock, flags); + if ((status & MIPI_CSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) { + u32 offset; + + if (status & MIPI_CSIS_INTSRC_EVEN) + offset = MIPI_CSIS_PKTDATA_EVEN; + else + offset = MIPI_CSIS_PKTDATA_ODD; + + memcpy(pktbuf->data, state->regs + offset, pktbuf->len); + pktbuf->data = NULL; + rmb(); + } + + /* Update the event/error counters */ + if ((status & MIPI_CSIS_INTSRC_ERRORS) || debug) { + int i; + for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { + if (!(status & state->events[i].mask)) + continue; + state->events[i].counter++; + v4l2_dbg(2, debug, &state->sd, "%s: %d\n", + state->events[i].name, + state->events[i].counter); + } + v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status); + } + spin_unlock_irqrestore(&state->slock, flags); + + mipi_csis_write(state, MIPI_CSIS_INTSRC, status); + return IRQ_HANDLED; +} +#endif + +static int mipi_csis_parse_dt(struct platform_device *pdev, + struct csi_state *state) +{ + struct device_node *node = pdev->dev.of_node; + + state->index = of_alias_get_id(node, "csi"); + + if (of_property_read_u32 + (node, "clock-frequency", &state->clk_frequency)) + state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; + + if (of_property_read_u32(node, "bus-width", &state->max_num_lanes)) + return -EINVAL; + + node = of_graph_get_next_endpoint(node, NULL); + if (!node) { + dev_err(&pdev->dev, "No port node at %s\n", node->full_name); + return -EINVAL; + } + + /* Get MIPI CSI-2 bus configration from the endpoint node. */ + of_property_read_u32(node, "csis-hs-settle", &state->hs_settle); + of_property_read_u32(node, "csis-clk-settle", &state->clk_settle); + of_property_read_u32(node, "data-lanes", &state->num_lanes); + + state->wclk_ext = of_property_read_bool(node, "csis-wclk"); + + of_node_put(node); + return 0; +} + +static const struct of_device_id mipi_csis_of_match[]; + +/* init subdev */ +static int mipi_csis_subdev_init(struct v4l2_subdev *mipi_sd, + struct platform_device *pdev, + const struct v4l2_subdev_ops *ops) +{ + struct csi_state *state = platform_get_drvdata(pdev); + int ret = 0; + + v4l2_subdev_init(mipi_sd, ops); + mipi_sd->owner = THIS_MODULE; + snprintf(mipi_sd->name, sizeof(mipi_sd->name), "%s.%d", + CSIS_SUBDEV_NAME, state->index); + mipi_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + mipi_sd->entity.function = MEDIA_ENT_F_IO_V4L; + mipi_sd->dev = &pdev->dev; + + state->csis_fmt = &mipi_csis_formats[0]; + state->format.code = mipi_csis_formats[0].code; + state->format.width = MIPI_CSIS_DEF_PIX_WIDTH; + state->format.height = MIPI_CSIS_DEF_PIX_HEIGHT; + + /* This allows to retrieve the platform device id by the host driver */ + v4l2_set_subdevdata(mipi_sd, state); + + state->v4l2_dev = kzalloc(sizeof(*state->v4l2_dev), GFP_KERNEL); + if (WARN_ON(!state->v4l2_dev)) { + ret = -ENOMEM; + goto end; + } + + ret = v4l2_device_register(&(pdev->dev), state->v4l2_dev); + if (WARN_ON(ret < 0)) + goto end; + + ret = v4l2_device_register_subdev(state->v4l2_dev, mipi_sd); + + if (ret) { + pr_err("failed to register csis-subdev %d\n", ret); + goto end; + } + + ret = v4l2_device_register_subdev_nodes(state->v4l2_dev); +end: + return ret; +} + +static int mipi_csis_of_parse_resets(struct csi_state *state) +{ +#if 0 + int ret; + struct device *dev = state->dev; + struct device_node *np = dev->of_node; + struct device_node *parent, *child; + struct of_phandle_args args; + struct reset_control *rstc; + const char *compat; + uint32_t len, rstc_num = 0; + + ret = of_parse_phandle_with_args(np, "resets", "#reset-cells", + 0, &args); + if (ret) + return ret; + + parent = args.np; + for_each_child_of_node(parent, child) { + compat = of_get_property(child, "compatible", NULL); + if (!compat) + continue; + + rstc = of_reset_control_array_get(child, false, false, true); + if (IS_ERR(rstc)) + continue; + + len = strlen(compat); + if (!of_compat_cmp("csi,soft-resetn", compat, len)) { + state->soft_resetn = rstc; + rstc_num++; + } else if (!of_compat_cmp("csi,clk-enable", compat, len)) { + state->clk_enable = rstc; + rstc_num++; + } else if (!of_compat_cmp("csi,mipi-reset", compat, len)) { + state->mipi_reset = rstc; + rstc_num++; + } else { + dev_warn(dev, "invalid csis reset node: %s\n", compat); + } + } + + if (!rstc_num) { + dev_err(dev, "no invalid reset control exists\n"); + return -EINVAL; + } + of_node_put(parent); + +#else + return 0; +#endif +} + +static int mipi_csis_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct v4l2_subdev *mipi_sd; + struct resource *mem_res; + struct csi_state *state; + struct device_node *media_mix_gpr; + const struct of_device_id *of_id; + mipi_csis_phy_reset_t phy_reset_fn; + int ret = -ENOMEM; + + state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); + if (!state) + return -ENOMEM; + + mutex_init(&state->lock); + spin_lock_init(&state->slock); + + /* WA on VSI platform, need insmod dynamically for debug */ + pdev->dev.of_node = + of_find_compatible_node(NULL, NULL, "fsl,imx8mp-mipi-csi"); + media_mix_gpr = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-ldb"); + + state->pdev = pdev; + mipi_sd = &state->sd; + state->dev = dev; + + ret = mipi_csis_parse_dt(pdev, state); + if (ret < 0) + return ret; + + /* Hardcode here */ + state->num_lanes = 4; + state->hs_settle = 0x10; + + if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) { + dev_err(dev, "Unsupported number of data lanes: %d (max. %d)\n", + state->num_lanes, state->max_num_lanes); + return -EINVAL; + } + + ret = mipi_csis_phy_init(state); + if (ret < 0) + return ret; + + of_id = of_match_node(mipi_csis_of_match, dev->of_node); + if (!of_id || !of_id->data) { + dev_err(dev, "No match data for %s\n", dev_name(dev)); + return -EINVAL; + } + phy_reset_fn = of_id->data; + state->phy_reset_fn = phy_reset_fn; + + state->gasket = + syscon_regmap_lookup_by_phandle(dev->of_node, "csi-gpr"); + if (IS_ERR(state->gasket)) { + dev_err(dev, "failed to get csi gasket\n"); + return PTR_ERR(state->gasket); + } + + state->gpr = syscon_regmap_lookup_by_phandle(dev->of_node, "csi-gpr2"); + if (IS_ERR(state->gpr)) { + dev_err(dev, "failed to get csi gpr\n"); + return PTR_ERR(state->gpr); + } + + state->mix_gpr = syscon_regmap_lookup_by_phandle(media_mix_gpr, "gpr"); + if (IS_ERR(state->mix_gpr)) { + dev_err(dev, "failed to get mix gpr\n"); + return PTR_ERR(state->mix_gpr); + } + + ret = of_clk_set_defaults(dev->of_node, false); + if (ret < 0) { + pr_err("clk: couldn't set desired clock for CSI\n"); + return ret; + } + + ret = mipi_csis_of_parse_resets(state); + if (ret < 0) { + dev_err(dev, "Can not parse reset control\n"); + return ret; + } + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + //state->regs = devm_ioremap_resource(dev, mem_res); + state->regs = ioremap(0x32e40000, 0x00001000); + if (IS_ERR(state->regs)) + return PTR_ERR(state->regs); +#ifdef CSI_HW_INTERRUPT + state->irq = platform_get_irq(pdev, 0); + if (state->irq < 0) { + dev_err(dev, "Failed to get irq\n"); + return state->irq; + } +#endif + ret = mipi_csis_clk_get(state); + if (ret < 0) + return ret; + + ret = mipi_csis_clk_enable(state); + if (ret < 0) + return ret; + + disp_mix_clks_enable(state->clk_enable, true); + disp_mix_sft_rstn(state->soft_resetn, false); + phy_reset_fn(state); + + /* mipi_csis_clk_disable(state); */ +#ifdef CSI_HW_INTERRUPT + ret = devm_request_irq(dev, state->irq, mipi_csis_irq_handler, 0, + dev_name(dev), state); + if (ret) { + dev_err(dev, "Interrupt request failed\n"); + return ret; + } +#endif + + platform_set_drvdata(pdev, state); + ret = mipi_csis_subdev_init(&state->sd, pdev, &mipi_csis_subdev_ops); + if (ret < 0) { + dev_err(dev, "mipi csi subdev init failed\n"); + return ret; + } + + state->pads[MIPI_CSIS_VC0_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC1_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC2_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC3_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC0_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + state->pads[MIPI_CSIS_VC1_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + state->pads[MIPI_CSIS_VC2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + state->pads[MIPI_CSIS_VC3_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + ret = + media_entity_pads_init(&state->sd.entity, MIPI_CSIS_VCX_PADS_NUM, + state->pads); + if (ret < 0) { + dev_err(dev, "mipi csi entity pad init failed\n"); + return ret; + } + + memcpy(state->events, mipi_csis_events, sizeof(state->events)); + state->sd.entity.ops = &mipi_csi2_sd_media_ops; + + pm_runtime_enable(dev); + /* mipi_csis_s_stream(&state->sd, 1); */ + + dev_info(&pdev->dev, + "lanes: %d, hs_settle: %d, clk_settle: %d, wclk: %d, freq: %u\n", + state->num_lanes, state->hs_settle, state->clk_settle, + state->wclk_ext, state->clk_frequency); + return 0; +} + +static int mipi_csis_system_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev);; +} + +static int mipi_csis_system_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + + return 0; +} + +static int mipi_csis_runtime_suspend(struct device *dev) +{ + struct csi_state *state = dev_get_drvdata(dev); + int ret; + + ret = regulator_disable(state->mipi_phy_regulator); + if (ret < 0) + return ret; + + disp_mix_clks_enable(state->clk_enable, false); + mipi_csis_clk_disable(state); + return 0; +} + +static int mipi_csis_runtime_resume(struct device *dev) +{ + struct csi_state *state = dev_get_drvdata(dev); + int ret; + + ret = regulator_enable(state->mipi_phy_regulator); + if (ret < 0) + return ret; + + ret = mipi_csis_clk_enable(state); + if (ret < 0) + return ret; + + disp_mix_clks_enable(state->clk_enable, true); + disp_mix_sft_rstn(state->soft_resetn, false); + + if (state->phy_reset_fn) + state->phy_reset_fn(state); + + return 0; +} + +static int mipi_csis_remove(struct platform_device *pdev) +{ + struct csi_state *state = platform_get_drvdata(pdev); + + media_entity_cleanup(&state->sd.entity); + + v4l2_device_unregister_subdev(&state->sd); + v4l2_device_disconnect(state->v4l2_dev); + v4l2_device_put(state->v4l2_dev); + + return 0; +} + +static const struct dev_pm_ops mipi_csis_pm_ops = { + SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, + NULL) + SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_system_suspend, + mipi_csis_system_resume) +}; + +static const struct of_device_id mipi_csis_of_match[] = { + {.compatible = "fsl,imx8mn-mipi-csi", + .data = (void *)&mipi_csis_phy_reset_mx8mn, + }, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, mipi_csis_of_match); + +static struct platform_driver mipi_csis_driver = { + .driver = { + .name = CSIS_DRIVER_NAME, + .owner = THIS_MODULE, + .pm = &mipi_csis_pm_ops, + .of_match_table = mipi_csis_of_match, + }, + .probe = mipi_csis_probe, + .remove = mipi_csis_remove, +}; + +static int __init csi_init_module(void) +{ + int ret = 0; + pr_debug("enter %s\n", __func__); + + ret = platform_driver_register(&mipi_csis_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + return ret; +} + +static void __exit csi_exit_module(void) +{ + pr_debug("enter %s\n", __func__); + platform_driver_unregister(&mipi_csis_driver); +} + +module_init(csi_init_module); +module_exit(csi_exit_module); + +MODULE_DESCRIPTION("Freescale MIPI-CSI2 receiver driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("CSI Capture"); +MODULE_VERSION("1.0"); diff --git a/vvcam/v4l2/dw200_driver.c b/vvcam/v4l2/dw200_driver.c new file mode 100755 index 0000000..e2545c7 --- /dev/null +++ b/vvcam/v4l2/dw200_driver.c @@ -0,0 +1,256 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dw200_driver.h" +#include "dw200_ioctl.h" + +#define DEVICE_NAME "vvcam-dw200" + +int dw200_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, 2, NULL); +} + +int dw200_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +#ifdef CONFIG_COMPAT +static long dw200_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct dw200_device *dw200_dev = v4l2_get_subdevdata(sd); + + return dw200_priv_ioctl(&dw200_dev->ic_dev, cmd, arg); +} + +long dw200_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return dw200_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long dw200_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct dw200_device *dw200_dev = v4l2_get_subdevdata(sd); + + return dw200_priv_ioctl(&^dw200_dev->ic_dev, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +int dw200_set_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static struct v4l2_subdev_core_ops dw200_v4l2_subdev_core_ops = { + .ioctl = dw200_ioctl, + .subscribe_event = dw200_subscribe_event, + .unsubscribe_event = dw200_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops dw200_v4l2_subdev_video_ops = { + .s_stream = dw200_set_stream, +}; + +static struct v4l2_subdev_ops dw200_v4l2_subdev_ops = { + .core = &dw200_v4l2_subdev_core_ops, + .video = &dw200_v4l2_subdev_video_ops, +}; + +int dw200_hw_probe(struct platform_device *pdev) +{ + struct dw200_device *dw200_dev; + int rc = 0; + + pr_info("enter %s\n", __func__); + dw200_dev = kzalloc(sizeof(struct dw200_device), GFP_KERNEL); + if (!dw200_dev) { + rc = -ENOMEM; + goto end; + } + + v4l2_subdev_init(&dw200_dev->sd, &dw200_v4l2_subdev_ops); + snprintf(dw200_dev->sd.name, sizeof(dw200_dev->sd.name), DEVICE_NAME); + dw200_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dw200_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + dw200_dev->sd.owner = THIS_MODULE; + v4l2_set_subdevdata(&dw200_dev->sd, dw200_dev); + dw200_dev->vd = kzalloc(sizeof(*dw200_dev->vd), GFP_KERNEL); + if (WARN_ON(!dw200_dev->vd)) { + rc = -ENOMEM; + goto end; + } + + rc = v4l2_device_register(&(pdev->dev), dw200_dev->vd); + if (WARN_ON(rc < 0)) + goto end; + + rc = v4l2_device_register_subdev(dw200_dev->vd, &dw200_dev->sd); + if (rc) { + pr_err("failed to register subdev %d\n", rc); + goto end; + } + dw200_dev->ic_dev.dwe_base = ioremap(DWE_REG_BASE, DWE_REG_SIZE); + dw200_dev->ic_dev.vse_base = ioremap(VSE_REG_BASE, VSE_REG_SIZE); +#ifdef DWE_REG_RESET + dw200_dev->ic_dev.dwe_reset = ioremap(DWE_REG_RESET, 4); +#endif +#ifdef VSE_REG_RESET + dw200_dev->ic_dev.vse_reset = ioremap(VSE_REG_RESET, 4); +#endif + pr_info("dw200 ioremap addr: 0x%08x 0x%08x %px", DWE_REG_BASE, + DWE_REG_SIZE, dw200_dev->ic_dev.dwe_base); + platform_set_drvdata(pdev, dw200_dev); + rc = v4l2_device_register_subdev_nodes(dw200_dev->vd); + return 0; +end: + return rc; +} + +int dw200_hw_remove(struct platform_device *pdev) +{ + struct dw200_device *dw200 = platform_get_drvdata(pdev); + + pr_info("enter %s\n", __func__); + if (!dw200) + return -EINVAL; + + v4l2_device_unregister_subdev(&dw200->sd); + v4l2_device_disconnect(dw200->vd); + v4l2_device_put(dw200->vd); + + iounmap(dw200->ic_dev.dwe_base); + iounmap(dw200->ic_dev.vse_base); +#ifdef DWE_REG_RESET + iounmap(dw200->ic_dev.dwe_reset); +#endif +#ifdef VSE_REG_RESET + iounmap(dw200->ic_dev.vse_reset); +#endif + kzfree(dw200); + + return 0; +} + +static struct platform_driver viv_dw200_driver = { + .probe = dw200_hw_probe, + .remove = dw200_hw_remove, + .driver = { + .name = DEVICE_NAME, + .owner = THIS_MODULE, + } +}; + +static void dw200_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +static struct platform_device viv_dw200_pdev = { + .name = DEVICE_NAME, + .dev.release = dw200_pdev_release, +}; + +static int __init viv_dw200_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + ret = platform_device_register(&viv_dw200_pdev); + if (ret) { + pr_err("register platform device failed.\n"); + return ret; + } + + ret = platform_driver_register(&viv_dw200_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + platform_device_unregister(&viv_dw200_pdev); + return ret; + } + return ret; +} + +static void __exit viv_dw200_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_dw200_driver); + platform_device_unregister(&viv_dw200_pdev); +} + +module_init(viv_dw200_init_module); +module_exit(viv_dw200_exit_module); + +MODULE_AUTHOR("zhiye.yin@verisilicon.com"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Dewarp200"); +MODULE_VERSION("1.0"); diff --git a/vvcam/v4l2/dw200_driver.h b/vvcam/v4l2/dw200_driver.h new file mode 100755 index 0000000..6384908 --- /dev/null +++ b/vvcam/v4l2/dw200_driver.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DW200_DRIVER_H_ +#define _DW200_DRIVER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dw200_subdev.h" + +struct dw200_device { + /* Driver private data */ + struct v4l2_subdev sd; + struct v4l2_device *vd; + struct dw200_subdev ic_dev; +}; + +#endif // _DW200_DRIVER_H_ diff --git a/vvcam/v4l2/dwe_devcore.c b/vvcam/v4l2/dwe_devcore.c new file mode 100755 index 0000000..93e2046 --- /dev/null +++ b/vvcam/v4l2/dwe_devcore.c @@ -0,0 +1,228 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include "dwe_driver.h" +#include "dwe_ioctl.h" + +LIST_HEAD(devcore_list); +static DEFINE_SPINLOCK(devcore_list_lock); + +long dwe_devcore_ioctl(struct dwe_device *dwe, unsigned int cmd, void *args) +{ + struct dwe_ic_dev *dev = &dwe->core->ic_dev; + int which; + long ret = 0; + + switch (cmd) { + case DWEIOC_RESET: + break; + case DWEIOC_S_PARAMS: + which = dev->which[dwe->id]; /*just set the current one*/ + viv_check_retval(copy_from_user(&dev->info[dwe->id][which], + args, sizeof(dev->info[dwe->id][which]))); + break; + case DWEIOC_START: + if (dwe->state & STATE_DRIVER_STARTED) + break; + mutex_lock(&dwe->core->mutex); + if (dwe->core->state == 0) { + ret = dwe_priv_ioctl(&dwe->core->ic_dev, + DWEIOC_RESET, NULL); + ret |= dwe_priv_ioctl(&dwe->core->ic_dev, cmd, args); + } + dwe->core->state++; + mutex_unlock(&dwe->core->mutex); + dwe->state |= STATE_DRIVER_STARTED; + break; + case DWEIOC_STOP: + if (!(dwe->state & STATE_DRIVER_STARTED)) + break; + dwe->state &= ~STATE_DRIVER_STARTED; + mutex_lock(&dwe->core->mutex); + dwe->core->state--; + if (dwe->core->state == 0) + ret = dwe_priv_ioctl(&dwe->core->ic_dev, cmd, args); + mutex_unlock(&dwe->core->mutex); + break; + case DWEIOC_SET_LUT: { + struct lut_info info; + + viv_check_retval(copy_from_user(&info, args, sizeof(info))); + if (info.port < MAX_CFG_NUM) + dev->dist_map[dwe->id][info.port] = info.addr; + else + pr_err("map num exceeds the max cfg num.\n"); + break; + } + case VIDIOC_QUERYCAP: { + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "viv_dewarp100"); + cap->bus_info[0] = (__u8)dwe->id; + break; + } + default: + return dwe_priv_ioctl(&dwe->core->ic_dev, cmd, args); + } + return ret; +} + +static int dwe_core_match(struct dwe_devcore *core, struct resource *res) +{ + return core && res && core->start == res->start && + core->end == res->end; +} + +static int dwe_core_get_index(struct dwe_ic_dev *dev, struct vb2_dc_buf *buf) +{ + struct dwe_devcore *core = + container_of(dev, struct dwe_devcore, ic_dev); + int i; + + for (i = 0; i < MAX_DWE_NUM; ++i) + if (core->src_pads[i] == buf->pad) + return i; + return -1; +} + +struct dwe_devcore *dwe_devcore_init(struct dwe_device *dwe, + struct resource *res) +{ + struct dwe_devcore *core, *found = NULL; + unsigned long flags; + int rc; + + spin_lock_irqsave(&devcore_list_lock, flags); + if (!list_empty(&devcore_list)) { + list_for_each_entry(core, &devcore_list, entry) { + if (core->match && core->match(core, res)) { + found = core; + break; + } + } + } + spin_unlock_irqrestore(&devcore_list_lock, flags); + + if (found) { + found->src_pads[dwe->id] = &dwe->pads[DWE_PAD_SINK]; + found->ic_dev.src_bctx[dwe->id] = &dwe->bctx[DWE_PAD_SOURCE]; + found->ic_dev.state[dwe->id] = &dwe->state; + refcount_inc(&found->refcount); + return found; + } + + core = kzalloc(sizeof(struct dwe_devcore), GFP_KERNEL); + + if (!core) + return NULL; + + core->ic_dev.base = devm_ioremap_resource(dwe->sd.dev, res); + if (IS_ERR(core->ic_dev.base)) { + pr_err("failed to get ioremap resource.\n"); + goto end; + } + core->start = res->start; + core->end = res->end; + +#ifdef DWE_REG_RESET + core->ic_dev.reset = ioremap(DWE_REG_RESET, 4); +#endif + pr_debug("dwe ioremap addr: %llx\n", (u64)core->ic_dev.base); + + vvbuf_ctx_init(&core->bctx[DWE_PAD_SINK]); + core->ic_dev.sink_bctx = &core->bctx[DWE_PAD_SINK]; + + core->irq = dwe->irq; + pr_debug("request_irq num:%d, rc:%d\n", dwe->irq, rc); + + spin_lock_init(&core->ic_dev.irqlock); + + core->match = dwe_core_match; + core->src_pads[dwe->id] = &dwe->pads[DWE_PAD_SINK]; + core->ic_dev.src_bctx[dwe->id] = &dwe->bctx[DWE_PAD_SOURCE]; + core->ic_dev.state[dwe->id] = &dwe->state; + core->ic_dev.get_index = dwe_core_get_index; + + mutex_init(&core->mutex); + refcount_set(&core->refcount, 1); + + spin_lock_irqsave(&devcore_list_lock, flags); + list_add_tail(&core->entry, &devcore_list); + spin_unlock_irqrestore(&devcore_list_lock, flags); + + return core; +end: + kfree(core); + return NULL; +} + +void dwe_devcore_deinit(struct dwe_device *dwe) +{ + struct dwe_devcore *core = dwe->core; + unsigned long flags; + + if (!core) + return; + + if (refcount_dec_and_test(&core->refcount)) { + spin_lock_irqsave(&devcore_list_lock, flags); + list_del(&core->entry); + spin_unlock_irqrestore(&devcore_list_lock, flags); + vvbuf_ctx_deinit(&core->bctx[DWE_PAD_SINK]); + +#ifdef DWE_REG_RESET + iounmap(core->ic_dev.reset); +#endif + mutex_destroy(&core->mutex); + kfree(core); + } +} diff --git a/vvcam/v4l2/dwe_driver.c b/vvcam/v4l2/dwe_driver.c new file mode 100755 index 0000000..b5a3889 --- /dev/null +++ b/vvcam/v4l2/dwe_driver.c @@ -0,0 +1,363 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dwe_driver.h" +#include "dwe_ioctl.h" +#define DEVICE_NAME "vvcam-dwe" + +int dwe_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, 2, NULL); +} + +int dwe_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +#ifdef CONFIG_COMPAT +static long dwe_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd); + + return dwe_priv_ioctl(&dwe_dev->ic_dev, cmd, arg); +} + +long dwe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return dwe_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long dwe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd); + + return dwe_priv_ioctl(&dwe_dev->ic_dev, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +static int dwe_enable_clocks(struct dwe_device *dwe_dev) +{ + int ret; + + ret = clk_prepare_enable(dwe_dev->clk_core); + if (ret) + return ret; + + ret = clk_prepare_enable(dwe_dev->clk_axi); + if (ret) + goto disable_clk_core; + + ret = clk_prepare_enable(dwe_dev->clk_ahb); + if (ret) + goto disable_clk_axi; + + return 0; + +disable_clk_axi: + clk_disable_unprepare(dwe_dev->clk_axi); +disable_clk_core: + clk_disable_unprepare(dwe_dev->clk_core); + + return ret; +} + +static void dwe_disable_clocks(struct dwe_device *dwe_dev) +{ + clk_disable_unprepare(dwe_dev->clk_ahb); + clk_disable_unprepare(dwe_dev->clk_axi); + clk_disable_unprepare(dwe_dev->clk_core); +} + + +int dwe_set_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static struct v4l2_subdev_core_ops dwe_v4l2_subdev_core_ops = { + .ioctl = dwe_ioctl, + .subscribe_event = dwe_subscribe_event, + .unsubscribe_event = dwe_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops dwe_v4l2_subdev_video_ops = { + .s_stream = dwe_set_stream, +}; + +static struct v4l2_subdev_ops dwe_v4l2_subdev_ops = { + .core = &dwe_v4l2_subdev_core_ops, + .video = &dwe_v4l2_subdev_video_ops, +}; + +static int dwe_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pm_runtime_get_sync(sd->dev); + return 0; +} + +static int dwe_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pm_runtime_put_sync(sd->dev); + return 0; +} + +static struct v4l2_subdev_internal_ops dwe_internal_ops = { + .open = dwe_open, + .close = dwe_close, +}; + +int dwe_hw_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dwe_device *dwe_dev; + struct resource *mem_res; + int rc = 0; + + pr_info("enter %s\n", __func__); + dwe_dev = kzalloc(sizeof(struct dwe_device), GFP_KERNEL); + if (!dwe_dev) { + rc = -ENOMEM; + goto end; + } + + dwe_dev->clk_core = devm_clk_get(dev, "core"); + if (IS_ERR(dwe_dev->clk_core)) { + rc = PTR_ERR(dwe_dev->clk_core); + dev_err(dev, "can't get core clock: %d\n", rc); + return rc; + } + + dwe_dev->clk_axi = devm_clk_get(dev, "axi"); + if (IS_ERR(dwe_dev->clk_axi)) { + rc = PTR_ERR(dwe_dev->clk_axi); + dev_err(dev, "can't get axi clock: %d\n", rc); + return rc; + } + + dwe_dev->clk_ahb = devm_clk_get(dev, "ahb"); + if (IS_ERR(dwe_dev->clk_ahb)) { + rc = PTR_ERR(dwe_dev->clk_ahb); + dev_err(dev, "can't get ahb clock: %d\n", rc); + return rc; + } + + dwe_dev->sd.internal_ops = &dwe_internal_ops; + + v4l2_subdev_init(&dwe_dev->sd, &dwe_v4l2_subdev_ops); + snprintf(dwe_dev->sd.name, sizeof(dwe_dev->sd.name), DEVICE_NAME); + dwe_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dwe_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + dwe_dev->sd.owner = THIS_MODULE; + dwe_dev->sd.dev = &pdev->dev; + v4l2_set_subdevdata(&dwe_dev->sd, dwe_dev); + dwe_dev->vd = kzalloc(sizeof(*dwe_dev->vd), GFP_KERNEL); + if (WARN_ON(!dwe_dev->vd)) { + rc = -ENOMEM; + goto end; + } + + rc = v4l2_device_register(&(pdev->dev), dwe_dev->vd); + if (WARN_ON(rc < 0)) + goto end; + + rc = v4l2_device_register_subdev(dwe_dev->vd, &dwe_dev->sd); + if (rc) { + pr_err("failed to register subdev %d\n", rc); + goto end; + } + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dwe_dev->ic_dev.base = devm_ioremap_resource(&pdev->dev, mem_res); + if (IS_ERR(dwe_dev->ic_dev.base)) { + pr_err("failed to get ioremap resource.\n"); + goto end; + } + +#ifdef DWE_REG_RESET + dwe_dev->ic_dev.reset = ioremap(DWE_REG_RESET, 4); +#endif + platform_set_drvdata(pdev, dwe_dev); + rc = v4l2_device_register_subdev_nodes(dwe_dev->vd); + pm_runtime_enable(&pdev->dev); + pr_info("vvcam dewarp driver probed\n"); + return 0; +end: + return rc; +} + +int dwe_hw_remove(struct platform_device *pdev) +{ + struct dwe_device *dwe = platform_get_drvdata(pdev); + + pr_info("enter %s\n", __func__); + + if (!dwe) + return -1; + pm_runtime_disable(&pdev->dev); + v4l2_device_unregister_subdev(&dwe->sd); + v4l2_device_disconnect(dwe->vd); + v4l2_device_put(dwe->vd); + +#ifdef DWE_REG_RESET + iounmap(dwe->ic_dev.reset); +#endif + kfree(dwe); + pr_info("vvcam dewarp driver removed\n"); + return 0; +} + +static int dwe_system_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev); +} + +static int dwe_system_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + + return 0; +} + +static int dwe_runtime_suspend(struct device *dev) +{ + struct dwe_device *dwe_dev = dev_get_drvdata(dev); + + dwe_disable_clocks(dwe_dev); + + return 0; +} + +static int dwe_runtime_resume(struct device *dev) +{ + struct dwe_device *dwe_dev = dev_get_drvdata(dev); + + dwe_enable_clocks(dwe_dev); + + return 0; +} + +static const struct dev_pm_ops dwe_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(dwe_system_suspend, dwe_system_resume) + SET_RUNTIME_PM_OPS(dwe_runtime_suspend, dwe_runtime_resume, NULL) +}; + +static const struct of_device_id dwe_of_match[] = { + {.compatible = DWE_COMPAT_NAME,}, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, dwe_of_match); + +static struct platform_driver viv_dwe_driver = { + .probe = dwe_hw_probe, + .remove = dwe_hw_remove, + .driver = { + .name = DWE_DEVICE_NAME, + .owner = THIS_MODULE, + .of_match_table = dwe_of_match, + .pm = &dwe_pm_ops, + } +}; + +static int __init viv_dwe_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + ret = platform_driver_register(&viv_dwe_driver); + if (ret) + pr_err("register platform driver failed.\n"); + + return ret; +} + +static void __exit viv_dwe_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_dwe_driver); +} + +module_init(viv_dwe_init_module); +module_exit(viv_dwe_exit_module); + +MODULE_AUTHOR("zhiye.yin@verisilicon.com"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Dewarp"); +MODULE_VERSION("1.0"); diff --git a/vvcam/v4l2/dwe_driver.h b/vvcam/v4l2/dwe_driver.h new file mode 100755 index 0000000..6927b80 --- /dev/null +++ b/vvcam/v4l2/dwe_driver.h @@ -0,0 +1,101 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_DRIVER_H_ +#define _DWE_DRIVER_H_ + +#include "dwe_dev.h" +#include "video/vvbuf.h" + +#ifdef ENABLE_IRQ +struct dwe_devcore { + struct vvbuf_ctx bctx[DWE_PADS_NUM]; + struct dwe_ic_dev ic_dev; + struct media_pad *src_pads[MAX_DWE_NUM]; + struct mutex mutex; + int state; + refcount_t refcount; + resource_size_t start; + resource_size_t end; + int (*match)(struct dwe_devcore *core, struct resource *res); + int irq; + struct list_head entry; +}; +#endif + +struct dwe_device { + struct vvbuf_ctx bctx[DWE_PADS_NUM]; + /* Driver private data */ + struct v4l2_subdev sd; +#ifdef ENABLE_IRQ + struct dwe_devcore *core; + struct media_pad pads[DWE_PADS_NUM]; + int state; + int id; + int irq; +#else + struct v4l2_device *vd; + struct dwe_ic_dev ic_dev; +#endif + struct clk *clk_core; + struct clk *clk_axi; + struct clk *clk_ahb; + int refcnt; +}; + +#ifdef ENABLE_IRQ +struct dwe_devcore *dwe_devcore_init(struct dwe_device *dwe, + struct resource *res); +void dwe_devcore_deinit(struct dwe_device *dwe); +long dwe_devcore_ioctl(struct dwe_device *dwe, unsigned int cmd, void *args); +#endif +#endif /* _DWE_DRIVER_H_ */ diff --git a/vvcam/v4l2/dwe_driver_of.c b/vvcam/v4l2/dwe_driver_of.c new file mode 100755 index 0000000..066d105 --- /dev/null +++ b/vvcam/v4l2/dwe_driver_of.c @@ -0,0 +1,582 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include + +#include "dwe_driver.h" +#include "dwe_ioctl.h" + +#define DEWARP_NODE_NUM (2) + +static struct dwe_device *pdwe_dev[DEWARP_NODE_NUM] = {NULL}; + +int dwe_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, 2, NULL); +} + +int dwe_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +#ifdef CONFIG_COMPAT +static long dwe_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + return dwe_devcore_ioctl(v4l2_get_subdevdata(sd), cmd, arg); +} + +long dwe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return dwe_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long dwe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return dwe_devcore_ioctl(v4l2_get_subdevdata(sd), cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +static int dwe_enable_clocks(struct dwe_device *dwe_dev) +{ + int ret; + ret = clk_prepare_enable(dwe_dev->clk_core); + if (ret) + return ret; + + ret = clk_prepare_enable(dwe_dev->clk_axi); + if (ret) + goto disable_clk_core; + + ret = clk_prepare_enable(dwe_dev->clk_ahb); + if (ret) + goto disable_clk_axi; + + return 0; + +disable_clk_axi: + clk_disable_unprepare(dwe_dev->clk_axi); +disable_clk_core: + clk_disable_unprepare(dwe_dev->clk_core); + + return ret; +} + +static void dwe_disable_clocks(struct dwe_device *dwe_dev) +{ + clk_disable_unprepare(dwe_dev->clk_ahb); + clk_disable_unprepare(dwe_dev->clk_axi); + clk_disable_unprepare(dwe_dev->clk_core); +} + +int dwe_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd); + struct vvbuf_ctx *ctx; + struct media_pad *pad; + unsigned long flags; + int state; + struct vb2_dc_buf *src_buf = NULL; + + if (!enable) + dwe_dev->state &= ~STATE_STREAM_STARTED; + else + dwe_dev->state |= STATE_STREAM_STARTED; + + pad = &dwe_dev->pads[DWE_PAD_SINK]; + pad = media_entity_remote_pad(pad); + + if (pad && is_media_entity_v4l2_subdev(pad->entity)) { + sd = media_entity_to_v4l2_subdev(pad->entity); + v4l2_subdev_call(sd, video, s_stream, enable); + } + + if (!enable) { + mutex_lock(&dwe_dev->core->mutex); + state = dwe_dev->core->state; + mutex_unlock(&dwe_dev->core->mutex); + if (state <= 0) { + ctx = &dwe_dev->core->bctx[DWE_PAD_SINK]; + spin_lock_irqsave(&ctx->irqlock, flags); + while (!list_empty(&ctx->dmaqueue)){ + src_buf = list_first_entry(&ctx->dmaqueue, + struct vb2_dc_buf, irqlist); + if (src_buf != NULL){ + list_del(&src_buf->irqlist); + vvbuf_ready(ctx , src_buf->pad, src_buf); + } + } + spin_unlock_irqrestore(&ctx->irqlock, flags); + } + + ctx = &dwe_dev->bctx[DWE_PAD_SOURCE]; + spin_lock_irqsave(&ctx->irqlock, flags); + if (!list_empty(&ctx->dmaqueue)) + list_del_init(&ctx->dmaqueue); + spin_unlock_irqrestore(&ctx->irqlock, flags); + } + return 0; +} + +static struct v4l2_subdev_core_ops dwe_v4l2_subdev_core_ops = { + .ioctl = dwe_ioctl, + .subscribe_event = dwe_subscribe_event, + .unsubscribe_event = dwe_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops dwe_v4l2_subdev_video_ops = { + .s_stream = dwe_set_stream, +}; + +static struct v4l2_subdev_ops dwe_v4l2_subdev_ops = { + .core = &dwe_v4l2_subdev_core_ops, + .video = &dwe_v4l2_subdev_video_ops, +}; + +static int dwe_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static const struct media_entity_operations dwe_media_ops = { + .link_setup = dwe_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +static void dwe_src_buf_notify(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf) +{ + struct v4l2_subdev *sd; + struct dwe_device *dwe; + unsigned long flags; + + if (unlikely(!ctx || !buf)) + return; + + sd = media_entity_to_v4l2_subdev(buf->pad->entity); + dwe = container_of(sd, struct dwe_device, sd); + + if (!dwe || !(dwe->state & STATE_STREAM_STARTED)) { + vvbuf_ready(ctx, buf->pad, buf); + return; + } + + ctx = &dwe->core->bctx[DWE_PAD_SINK]; + + spin_lock_irqsave(&ctx->irqlock, flags); + list_add_tail(&buf->irqlist, &ctx->dmaqueue); + spin_unlock_irqrestore(&ctx->irqlock, flags); + + dwe_on_buf_update(&dwe->core->ic_dev); +} + +static const struct vvbuf_ops dwe_src_buf_ops = { + .notify = dwe_src_buf_notify, +}; + +static void dwe_dst_buf_notify(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf) +{ + struct v4l2_subdev *sd; + struct dwe_device *dwe; + unsigned long flags; + + if (unlikely(!ctx || !buf)) + return; + + sd = media_entity_to_v4l2_subdev(buf->pad->entity); + dwe = container_of(sd, struct dwe_device, sd); + + spin_lock_irqsave(&ctx->irqlock, flags); + list_add_tail(&buf->irqlist, &ctx->dmaqueue); + spin_unlock_irqrestore(&ctx->irqlock, flags); + + if (dwe) + dwe_on_buf_update(&dwe->core->ic_dev); +} + +static const struct vvbuf_ops dwe_dst_buf_ops = { + .notify = dwe_dst_buf_notify, +}; + +static void fake_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +static struct platform_device fake_pdev = { + .name = "fsl,fake-imx8mp-dwe", + .id = 1, + .dev.release = fake_pdev_release, +}; + +static int dwe_fake_pdev_creat(void) +{ + return platform_device_register(&fake_pdev); +} + +static void dwe_fake_pdev_destory(void) +{ + platform_device_unregister(&fake_pdev); +} + +static int dwe_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd); + pm_runtime_get_sync(pdwe_dev[0]->sd.dev); + + dwe_dev->refcnt++; + if ((pdwe_dev[0]->refcnt + pdwe_dev[1]->refcnt) == 1){ + msleep(1); + dwe_clear_interrupts(&pdwe_dev[0]->core->ic_dev); + if (devm_request_irq(pdwe_dev[0]->sd.dev, pdwe_dev[0]->irq, dwe_hw_isr, IRQF_SHARED, + dev_name(pdwe_dev[0]->sd.dev), &pdwe_dev[0]->core->ic_dev) != 0) { + pr_err("failed to request irq.\n"); + pdwe_dev[0]->refcnt = 0; + pm_runtime_put_sync(pdwe_dev[0]->sd.dev); + return -1; + } + } + return 0; +} + +static int dwe_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd); + struct vvbuf_ctx *ctx; + struct vb2_dc_buf *src_buf = NULL; + unsigned long flags; + + dwe_dev->refcnt--; + if (dwe_dev->refcnt < 0) { + dwe_dev->refcnt = 0; + return 0; + } + if (dwe_dev->refcnt == 0) + dwe_dev->state = 0; + + if ((pdwe_dev[0]->refcnt + pdwe_dev[1]->refcnt) == 0) { + devm_free_irq(pdwe_dev[0]->sd.dev, pdwe_dev[0]->irq, &pdwe_dev[0]->core->ic_dev); + dwe_clear_interrupts(&pdwe_dev[0]->core->ic_dev); + mutex_lock(&dwe_dev->core->mutex); + pdwe_dev[0]->core->state = 0; + mutex_unlock(&dwe_dev->core->mutex); + + ctx = &dwe_dev->core->bctx[DWE_PAD_SINK]; + spin_lock_irqsave(&ctx->irqlock, flags); + while (!list_empty(&ctx->dmaqueue)){ + src_buf = list_first_entry(&ctx->dmaqueue, + struct vb2_dc_buf, irqlist); + if (src_buf != NULL){ + list_del(&src_buf->irqlist); + vvbuf_ready(ctx , src_buf->pad, src_buf); + } + } + spin_unlock_irqrestore(&ctx->irqlock, flags); + msleep(5); + } + pm_runtime_put(pdwe_dev[0]->sd.dev); + return 0; +} + +static struct v4l2_subdev_internal_ops dwe_internal_ops = { + .open = dwe_open, + .close = dwe_close, +}; + +int dwe_hw_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dwe_device *dwe_dev; + struct resource *mem_res; + int irq; + int rc, i, index; + int dev_id; + + pr_info("enter %s\n", __func__); + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem_res) { + pr_err("can't fetch device resource info\n"); + return -ENODEV; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + pr_err("failed to get irq number.\n"); + return -ENODEV; + } + + rc = dwe_fake_pdev_creat(); + if (rc < 0) { + pr_err("failed to creat fake pdev for dwe1.\n"); + goto dewarp_destory_fake_pdev; + } + + for (dev_id = 0; dev_id < DEWARP_NODE_NUM; dev_id++) { + pdwe_dev[dev_id] = + kzalloc(sizeof(struct dwe_device), GFP_KERNEL); + if (!pdwe_dev[dev_id]) { + if (dev_id == 0) + goto dewarp_destory_fake_pdev; + else { + dev_id = dev_id - 1; + goto dewarp_entity_pads_deinit; + } + + } + + dwe_dev = pdwe_dev[dev_id]; + dwe_dev->id = dev_id; + if (dev_id == 0){ + dwe_dev->clk_core = devm_clk_get(dev, "core"); + if (IS_ERR(dwe_dev->clk_core)) { + rc = PTR_ERR(dwe_dev->clk_core); + dev_err(dev, "can't get core clock: %d\n", rc); + return rc; + } + + dwe_dev->clk_axi = devm_clk_get(dev, "axi"); + if (IS_ERR(dwe_dev->clk_axi)) { + rc = PTR_ERR(dwe_dev->clk_axi); + dev_err(dev, "can't get axi clock: %d\n", rc); + return rc; + } + + dwe_dev->clk_ahb = devm_clk_get(dev, "ahb"); + if (IS_ERR(dwe_dev->clk_ahb)) { + rc = PTR_ERR(dwe_dev->clk_ahb); + dev_err(dev, "can't get ahb clock: %d\n", rc); + return rc; + } + } + dwe_dev->sd.internal_ops = &dwe_internal_ops; + v4l2_subdev_init(&dwe_dev->sd, &dwe_v4l2_subdev_ops); + snprintf(dwe_dev->sd.name, sizeof(dwe_dev->sd.name), + "%s.%d", DWE_DEVICE_NAME, dwe_dev->id); + dwe_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dwe_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + dwe_dev->sd.owner = THIS_MODULE; + + v4l2_set_subdevdata(&dwe_dev->sd, dwe_dev); + + if (dev_id == 0) + dwe_dev->sd.dev = &pdev->dev; + else + dwe_dev->sd.dev = &fake_pdev.dev; + dwe_dev->sd.entity.name = dwe_dev->sd.name; + dwe_dev->sd.entity.obj_type = MEDIA_ENTITY_TYPE_V4L2_SUBDEV; + dwe_dev->sd.entity.function = MEDIA_ENT_F_IO_V4L; + dwe_dev->sd.entity.ops = &dwe_media_ops; + dwe_dev->pads[DWE_PAD_SINK].flags = + MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT; + dwe_dev->pads[DWE_PAD_SOURCE].flags = + MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT; + rc = media_entity_pads_init(&dwe_dev->sd.entity, + DWE_PADS_NUM, dwe_dev->pads); + if (rc < 0) + goto dewarp_entity_pads_deinit; + } + + for (dev_id = 0; dev_id < DEWARP_NODE_NUM; dev_id++) { + dwe_dev = pdwe_dev[dev_id]; + for (i = 0; i < DWE_PADS_NUM; ++i) + vvbuf_ctx_init(&dwe_dev->bctx[i]); + + dwe_dev->bctx[DWE_PAD_SINK].ops = &dwe_src_buf_ops; + dwe_dev->bctx[DWE_PAD_SOURCE].ops = &dwe_dst_buf_ops; + dwe_dev->irq = irq; + + dwe_dev->core = dwe_devcore_init(dwe_dev, mem_res); + dwe_dev->sd.fwnode = of_fwnode_handle(pdev->dev.of_node); + + rc = v4l2_async_register_subdev(&dwe_dev->sd); + if (rc < 0) + goto dewarp_core_deinit; + } + pm_runtime_enable(&pdev->dev); + pr_info("vvcam dewarp driver probed\n"); + return 0; + +dewarp_core_deinit: + dwe_devcore_deinit(pdwe_dev[0]); + for (index = 0; index <= dev_id; index++) { + dwe_dev = pdwe_dev[index]; + for (i = 0; i < DWE_PADS_NUM; i++) + vvbuf_ctx_deinit(&dwe_dev->bctx[i]); + } + dev_id = DEWARP_NODE_NUM - 1; + +dewarp_entity_pads_deinit: + for (index = 0; index <= dev_id; index++) { + dwe_dev = pdwe_dev[index]; + media_entity_cleanup(&dwe_dev->sd.entity); + kfree(dwe_dev); + } +dewarp_destory_fake_pdev: + dwe_fake_pdev_destory(); + return rc; +} + +int dwe_hw_remove(struct platform_device *pdev) +{ + struct dwe_device *dwe_dev; + int dev_id; + int i; + + pr_info("enter %s\n", __func__); + pm_runtime_disable(&pdev->dev); + dwe_devcore_deinit(pdwe_dev[0]); + + for (dev_id = 0; dev_id < DEWARP_NODE_NUM; dev_id++) { + dwe_dev = pdwe_dev[dev_id]; + for (i = 0; i < DWE_PADS_NUM; i++) + vvbuf_ctx_deinit(&dwe_dev->bctx[i]); + media_entity_cleanup(&dwe_dev->sd.entity); + v4l2_async_unregister_subdev(&dwe_dev->sd); + kfree(dwe_dev); + } + dwe_fake_pdev_destory(); + pr_info("vvcam dewarp driver removed\n"); + return 0; +} + +static int dwe_system_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev); +} + +static int dwe_system_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + + return 0; +} + +static int dwe_runtime_suspend(struct device *dev) +{ + struct dwe_device *dwe_dev = pdwe_dev[0]; + + dwe_disable_clocks(dwe_dev); + + return 0; +} + +static int dwe_runtime_resume(struct device *dev) +{ + struct dwe_device *dwe_dev = pdwe_dev[0]; + + dwe_enable_clocks(dwe_dev); + + return 0; +} + +static const struct dev_pm_ops dwe_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(dwe_system_suspend, dwe_system_resume) + SET_RUNTIME_PM_OPS(dwe_runtime_suspend, dwe_runtime_resume, NULL) +}; + +static const struct of_device_id dwe_of_match[] = { + {.compatible = DWE_COMPAT_NAME,}, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, dwe_of_match); + +static struct platform_driver viv_dwe_driver = { + .probe = dwe_hw_probe, + .remove = dwe_hw_remove, + .driver = { + .name = DWE_DEVICE_NAME, + .owner = THIS_MODULE, + .of_match_table = dwe_of_match, + .pm = &dwe_pm_ops, + } +}; + +static int __init viv_dwe_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + ret = platform_driver_register(&viv_dwe_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + return ret; +} + +static void __exit viv_dwe_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_dwe_driver); +} + +module_init(viv_dwe_init_module); +module_exit(viv_dwe_exit_module); + +MODULE_AUTHOR("zhiye.yin@verisilicon.com"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Dewarp"); +MODULE_VERSION("1.0"); diff --git a/vvcam/v4l2/isp_driver.c b/vvcam/v4l2/isp_driver.c new file mode 100755 index 0000000..c50b227 --- /dev/null +++ b/vvcam/v4l2/isp_driver.c @@ -0,0 +1,508 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "isp_driver.h" +#include "isp_ioctl.h" +#include "mrv_all_bits.h" +#include "viv_video_kevent.h" + +struct clk *clk_isp; + +extern MrvAllRegister_t *all_regs; + +#ifdef CONFIG_COMPAT +static long isp_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + return isp_priv_ioctl(&isp_dev->ic_dev, cmd, arg); +} + +long isp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return isp_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long isp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + return isp_priv_ioctl(&isp_dev->ic_dev, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +static int isp_enable_clocks(struct isp_device *isp_dev) +{ + int ret; + + ret = clk_prepare_enable(isp_dev->clk_core); + if (ret) + return ret; + + ret = clk_prepare_enable(isp_dev->clk_axi); + if (ret) + goto disable_clk_core; + + ret = clk_prepare_enable(isp_dev->clk_ahb); + if (ret) + goto disable_clk_axi; + + return 0; + +disable_clk_axi: + clk_disable_unprepare(isp_dev->clk_axi); +disable_clk_core: + clk_disable_unprepare(isp_dev->clk_core); + + return ret; +} + +static void isp_disable_clocks(struct isp_device *isp_dev) +{ + clk_disable_unprepare(isp_dev->clk_ahb); + clk_disable_unprepare(isp_dev->clk_axi); + clk_disable_unprepare(isp_dev->clk_core); +} + +int isp_set_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static void isp_post_event(struct isp_ic_dev *dev, void *data, size_t size) +{ + struct isp_device *isp_dev; + struct video_device *vdev; + struct v4l2_event event; + + if (!dev || !data || !size) + return; + + isp_dev = container_of(dev, struct isp_device, ic_dev); + vdev = isp_dev->sd.devnode; + if (!vdev) + return; + + memset(&event, 0, sizeof(event)); + memcpy(event.u.data, data, min_t(size_t, size, 64)); + event.type = VIV_VIDEO_ISPIRQ_TYPE; + v4l2_event_queue(vdev, &event); +} + +static int isp_subdev_subscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, struct v4l2_event_subscription *sub) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + if (sub->type != VIV_VIDEO_ISPIRQ_TYPE) + return -EINVAL; + + if (!isp_dev->ic_dev.post_event) + isp_dev->ic_dev.post_event = isp_post_event; + + return v4l2_event_subscribe(fh, sub, 8, NULL); +} + +static int isp_subdev_unsubscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, struct v4l2_event_subscription *sub) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + if (sub->type != VIV_VIDEO_ISPIRQ_TYPE) + return -EINVAL; + + if (isp_dev->ic_dev.post_event) + isp_dev->ic_dev.post_event = NULL; + + return v4l2_event_unsubscribe(fh, sub); +} + +static struct v4l2_subdev_core_ops isp_v4l2_subdev_core_ops = { + .ioctl = isp_ioctl, + .subscribe_event = isp_subdev_subscribe_event, + .unsubscribe_event = isp_subdev_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops isp_v4l2_subdev_video_ops = { + .s_stream = isp_set_stream, +}; + + +irqreturn_t isp_hw_isr_reg_update(int irq, void *data) +{ + u32 isp_mis, isp_ctrl; + + struct isp_irq_data irq_data; + struct isp_ic_dev *dev = (struct isp_ic_dev *)data; + + if (!dev) + return IRQ_HANDLED; + + isp_mis = isp_read_reg(dev, REG_ADDR(isp_mis)); + isp_write_reg(dev, REG_ADDR(isp_icr), isp_mis); + + + if (isp_mis) { + if (isp_mis & MRV_ISP_MIS_FRAME_MASK) { + if (dev->isp_update_flag & ISP_FLT_UPDATE) { + isp_s_flt(dev); + dev->isp_update_flag &= (~ISP_FLT_UPDATE); + } + + if (dev->gamma_out.changed) { + isp_s_gamma_out(dev); + } + + if(dev->update_gamma_en) { + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, + dev->gamma_out.enableGamma); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + dev->update_gamma_en = false; + } + + } + + memset(&irq_data, 0, sizeof(irq_data)); + irq_data.val = isp_mis; + if (dev->post_event) + dev->post_event(dev, &irq_data, sizeof(irq_data)); + } + return IRQ_HANDLED; +} + +struct v4l2_subdev_ops isp_v4l2_subdev_ops = { + .core = &isp_v4l2_subdev_core_ops, + .video = &isp_v4l2_subdev_video_ops, +}; + +static int isp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pm_runtime_get_sync(sd->dev); + return 0; +} + +static int isp_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pm_runtime_put_sync(sd->dev); + return 0; +} + +static struct v4l2_subdev_internal_ops isp_internal_ops = { + .open = isp_open, + .close = isp_close, +}; + +int isp_hw_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct isp_device *isp_dev; + struct resource *mem_res; + int irq; + int rc; + struct device_node *mem_node; + + pr_info("enter %s\n", __func__); + isp_dev = kzalloc(sizeof(struct isp_device), GFP_KERNEL); + if (!isp_dev) { + goto end; + } + + rc = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node), + "id", &isp_dev->id); + if (rc) { + pr_info("isp device id not found, use the default.\n"); + isp_dev->id = 0; + } + isp_dev->ic_dev.id = isp_dev->id; + + isp_dev->clk_core = devm_clk_get(dev, "core"); + if (IS_ERR(isp_dev->clk_core)) { + rc = PTR_ERR(isp_dev->clk_core); + dev_err(dev, "can't get core clock: %d\n", rc); + return rc; + } + + isp_dev->clk_axi = devm_clk_get(dev, "axi"); + if (IS_ERR(isp_dev->clk_axi)) { + rc = PTR_ERR(isp_dev->clk_axi); + dev_err(dev, "can't get axi clock: %d\n", rc); + return rc; + } + + isp_dev->clk_ahb = devm_clk_get(dev, "ahb"); + if (IS_ERR(isp_dev->clk_ahb)) { + rc = PTR_ERR(isp_dev->clk_ahb); + dev_err(dev, "can't get ahb clock: %d\n", rc); + return rc; + } + + isp_dev->sd.internal_ops = &isp_internal_ops; + +#ifdef ISP8000NANO_V1802 + isp_dev->ic_dev.mix_gpr = syscon_regmap_lookup_by_phandle( + pdev->dev.of_node, "gpr"); + if (IS_ERR(isp_dev->ic_dev.mix_gpr)) { + pr_warn("failed to get mix gpr\n"); + isp_dev->ic_dev.mix_gpr = NULL; + return -ENOMEM; + } +#endif + mem_node = of_parse_phandle(pdev->dev.of_node, "memory-region", 0); + if (!mem_node) { + pr_err("No memory-region found\n"); + return -ENODEV; + } + + isp_dev->ic_dev.rmem = of_reserved_mem_lookup(mem_node); + if (!isp_dev->ic_dev.rmem) { + pr_err("of_reserved_mem_lookup() returned NULL\n"); + return -ENODEV; + } + + v4l2_subdev_init(&isp_dev->sd, &isp_v4l2_subdev_ops); + snprintf(isp_dev->sd.name, sizeof(isp_dev->sd.name), + "vvcam-isp.%d", isp_dev->ic_dev.id); + isp_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + isp_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + isp_dev->sd.owner = THIS_MODULE; + isp_dev->sd.dev = &pdev->dev; + v4l2_set_subdevdata(&isp_dev->sd, isp_dev); + isp_dev->vd = kzalloc(sizeof(*isp_dev->vd), GFP_KERNEL); + if (WARN_ON(!isp_dev->vd)) { + rc = -ENOMEM; + goto end; + } + + rc = v4l2_device_register(&(pdev->dev), isp_dev->vd); + if (WARN_ON(rc < 0)) + goto end; + + rc = v4l2_device_register_subdev(isp_dev->vd, &isp_dev->sd); + if (rc) { + pr_err("failed to register subdev %d\n", rc); + goto end; + } + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + isp_dev->ic_dev.base = devm_ioremap_resource(&pdev->dev, mem_res); + if (IS_ERR(isp_dev->ic_dev.base)) { + pr_err("failed to get ioremap resource.\n"); + goto end; + } + +#ifdef ISP_REG_RESET + isp_dev->ic_dev.reset = ioremap(ISP_REG_RESET, 4); +#endif + pr_debug("ioremap addr: %px", isp_dev->ic_dev.base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + pr_err("failed to get irq number.\n"); + goto end; + } + + rc = devm_request_irq(&pdev->dev, irq, isp_hw_isr_reg_update, IRQF_SHARED, + dev_name(&pdev->dev), &isp_dev->ic_dev); + if (rc) { + pr_err("failed to request irq.\n"); + irq = -1; + goto end; + } + isp_dev->irq = irq; + pr_debug("request_irq num:%d, rc:%d", irq, rc); + + platform_set_drvdata(pdev, isp_dev); + rc = v4l2_device_register_subdev_nodes(isp_dev->vd); + + pm_runtime_enable(&pdev->dev); + pr_info("vvcam isp driver registered\n"); + return 0; +end: + if (irq >= 0) + devm_free_irq(&pdev->dev, irq, &isp_dev->ic_dev); + kfree(isp_dev); + return 1; +} + +int isp_hw_remove(struct platform_device *pdev) +{ + struct isp_device *isp = platform_get_drvdata(pdev); + + pr_info("enter %s\n", __func__); + if (!isp) + return -1; + devm_free_irq(&pdev->dev, isp->irq, &isp->ic_dev); + v4l2_device_unregister_subdev(&isp->sd); + if (isp->vd) { + v4l2_device_disconnect(isp->vd); + v4l2_device_put(isp->vd); + } + + kfree(isp); + pm_runtime_disable(&pdev->dev); + return 0; +} + +static int isp_system_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev);; +} + +static int isp_system_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + + return 0; +} + +static int isp_runtime_suspend(struct device *dev) +{ + struct isp_device *isp_dev = dev_get_drvdata(dev); + + isp_disable_clocks(isp_dev); + + return 0; +} + +static int isp_runtime_resume(struct device *dev) +{ + struct isp_device *isp_dev = dev_get_drvdata(dev); + + isp_enable_clocks(isp_dev); + + return 0; +} + +static const struct dev_pm_ops isp_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(isp_system_suspend, isp_system_resume) + SET_RUNTIME_PM_OPS(isp_runtime_suspend, isp_runtime_resume, NULL) +}; + +static const struct of_device_id isp_of_match[] = { + {.compatible = "fsl,imx8mp-isp",}, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, isp_of_match); + +static struct platform_driver viv_isp_driver = { + .probe = isp_hw_probe, + .remove = isp_hw_remove, + .driver = { + .name = "vvcam-isp", + .owner = THIS_MODULE, + .of_match_table = isp_of_match, + .pm = &isp_pm_ops, + } +}; + +static int __init viv_isp_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&viv_isp_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit viv_isp_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_isp_driver); +} + +module_init(viv_isp_init_module); +module_exit(viv_isp_exit_module); + +MODULE_AUTHOR("Verisilicon ISP SW Team"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Verisilicon-ISP"); +MODULE_VERSION("1.0"); diff --git a/vvcam/v4l2/isp_driver.h b/vvcam/v4l2/isp_driver.h new file mode 100755 index 0000000..571fffd --- /dev/null +++ b/vvcam/v4l2/isp_driver.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_DRIVER_H_ +#define _ISP_DRIVER_H_ + +#include "ic_dev.h" +#include "video/vvbuf.h" + +struct isp_device { + struct vvbuf_ctx bctx; + /* Driver private data */ + struct v4l2_subdev sd; +#ifndef ENABLE_IRQ + struct v4l2_device *vd; +#endif + struct isp_ic_dev ic_dev; + struct clk *clk_core; + struct clk *clk_axi; + struct clk *clk_ahb; + int refcnt; +#ifdef ENABLE_IRQ + struct media_pad pads[ISP_PADS_NUM]; + int state; +#endif + int irq; + + int id; +}; + +#endif /* _ISP_DRIVER_H_ */ diff --git a/vvcam/v4l2/isp_driver_of.c b/vvcam/v4l2/isp_driver_of.c new file mode 100755 index 0000000..8477171 --- /dev/null +++ b/vvcam/v4l2/isp_driver_of.c @@ -0,0 +1,619 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include + +#include "isp_driver.h" +#include "isp_ioctl.h" +#include "mrv_all_bits.h" +#include "viv_video_kevent.h" + +struct clk *clk_isp; + +extern MrvAllRegister_t *all_regs; + +#ifdef CONFIG_COMPAT +static long isp_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + return isp_priv_ioctl(&isp_dev->ic_dev, cmd, arg); +} + +long isp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return isp_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long isp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + return isp_priv_ioctl(&isp_dev->ic_dev, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +static int isp_enable_clocks(struct isp_device *isp_dev) +{ + int ret; + + ret = clk_prepare_enable(isp_dev->clk_core); + if (ret) + return ret; + + ret = clk_prepare_enable(isp_dev->clk_axi); + if (ret) + goto disable_clk_core; + + ret = clk_prepare_enable(isp_dev->clk_ahb); + if (ret) + goto disable_clk_axi; + + return 0; + +disable_clk_axi: + clk_disable_unprepare(isp_dev->clk_axi); +disable_clk_core: + clk_disable_unprepare(isp_dev->clk_core); + + return ret; +} + +static void isp_disable_clocks(struct isp_device *isp_dev) +{ + clk_disable_unprepare(isp_dev->clk_ahb); + clk_disable_unprepare(isp_dev->clk_axi); + clk_disable_unprepare(isp_dev->clk_core); +} + +int isp_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + struct vvbuf_ctx *ctx = &isp_dev->bctx; + struct vb2_dc_buf *buf; + + if (!enable) { + isp_dev->state &= ~STATE_STREAM_STARTED; + buf = vvbuf_try_dqbuf(ctx); + if (!buf) + return 0; + + do { + vvbuf_try_dqbuf_done(ctx, buf); + if (buf->flags) + kfree(buf); + } while ((buf = vvbuf_try_dqbuf(ctx))); + } else + isp_dev->state |= STATE_STREAM_STARTED; + return 0; +} + +static void isp_post_event(struct isp_ic_dev *dev, void *data, size_t size) +{ + struct isp_device *isp_dev; + struct video_device *vdev; + struct v4l2_event event; + + if (!dev || !data || !size) + return; + + isp_dev = container_of(dev, struct isp_device, ic_dev); + vdev = isp_dev->sd.devnode; + if (!vdev) + return; + + memset(&event, 0, sizeof(event)); + memcpy(event.u.data, data, min_t(size_t, size, 64)); + event.type = VIV_VIDEO_ISPIRQ_TYPE; + v4l2_event_queue(vdev, &event); +} + +static int isp_subdev_subscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, struct v4l2_event_subscription *sub) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + if (sub->type != VIV_VIDEO_ISPIRQ_TYPE) + return -EINVAL; + + if (!isp_dev->ic_dev.post_event) + isp_dev->ic_dev.post_event = isp_post_event; + + return v4l2_event_subscribe(fh, sub, 8, NULL); +} + +static int isp_subdev_unsubscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, struct v4l2_event_subscription *sub) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + if (sub->type != VIV_VIDEO_ISPIRQ_TYPE) + return -EINVAL; + + if (isp_dev->ic_dev.post_event) + isp_dev->ic_dev.post_event = NULL; + + return v4l2_event_unsubscribe(fh, sub); +} + +static struct v4l2_subdev_core_ops isp_v4l2_subdev_core_ops = { + .ioctl = isp_ioctl, + .subscribe_event = isp_subdev_subscribe_event, + .unsubscribe_event = isp_subdev_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops isp_v4l2_subdev_video_ops = { + .s_stream = isp_set_stream, +}; + +struct v4l2_subdev_ops isp_v4l2_subdev_ops = { + .core = &isp_v4l2_subdev_core_ops, + .video = &isp_v4l2_subdev_video_ops, +}; + +static int isp_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static const struct media_entity_operations isp_media_ops = { + .link_setup = isp_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +static void isp_buf_notify(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf) +{ + struct v4l2_subdev *sd; + struct isp_device *isp; + unsigned long flags; + + if (unlikely(!ctx || !buf)) + return; + + sd = media_entity_to_v4l2_subdev(buf->pad->entity); + isp = container_of(sd, struct isp_device, sd); + if (!(isp->state & STATE_STREAM_STARTED)) { + if (buf->flags) { + kfree(buf); + return; + } + } + + spin_lock_irqsave(&ctx->irqlock, flags); + list_add_tail(&buf->irqlist, &ctx->dmaqueue); + spin_unlock_irqrestore(&ctx->irqlock, flags); +} + +static const struct vvbuf_ops isp_buf_ops = { + .notify = isp_buf_notify, +}; + +static int isp_buf_alloc(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + struct isp_device *isp_dev; + struct vb2_dc_buf *buff, *b; + unsigned long flags; + + if (!dev || !buf) + return -EINVAL; + + isp_dev = container_of(dev, struct isp_device, ic_dev); + + buff = kzalloc(sizeof(struct vb2_dc_buf), GFP_KERNEL); + if (!buff) + return -ENOMEM; + + buff->pad = &isp_dev->pads[ISP_PAD_SOURCE]; + /*single plane*/ +#ifdef ISP_MP_34BIT + buff->dma = buf->addr_y << 2; +#else + buff->dma = buf->addr_y; +#endif + buff->flags = 1; + + spin_lock_irqsave(&isp_dev->bctx.irqlock, flags); + list_for_each_entry(b, &isp_dev->bctx.dmaqueue, irqlist) { + if (b->dma == buff->dma) { + list_del(&b->irqlist); + if (b->flags) + kfree(b); + break; + } + } + list_add_tail(&buff->irqlist, &isp_dev->bctx.dmaqueue); + spin_unlock_irqrestore(&isp_dev->bctx.irqlock, flags); + return 0; +} + +static int isp_buf_free(struct isp_ic_dev *dev, struct vb2_dc_buf *buf) +{ + struct isp_device *isp_dev; + struct vvbuf_ctx *ctx; + + if (buf && buf->flags) + kfree(buf); + + if (!dev) + return -EINVAL; + + isp_dev = container_of(dev, struct isp_device, ic_dev); + ctx = &isp_dev->bctx; + + buf = vvbuf_try_dqbuf(ctx); + if (!buf || !buf->flags) + return 0; + + do { + vvbuf_try_dqbuf_done(ctx, buf); + kfree(buf); + } while ((buf = vvbuf_try_dqbuf(ctx))); + return 0; +} + +static int isp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + pm_runtime_get_sync(sd->dev); + + isp_dev->refcnt++; + if (isp_dev->refcnt == 1) { + msleep(1); + isp_clear_interrupts(&isp_dev->ic_dev); + if (devm_request_irq(sd->dev, isp_dev->irq, isp_hw_isr, IRQF_SHARED, + dev_name(sd->dev), &isp_dev->ic_dev) != 0) { + pr_err("failed to request irq.\n"); + isp_dev->refcnt = 0; + pm_runtime_put_sync(sd->dev); + return -1; + } + } + return 0; +} + +static int isp_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + isp_dev->refcnt--; + if (isp_dev->refcnt < 0) { + isp_dev->refcnt = 0; + return 0; + } + + if (isp_dev->refcnt == 0){ + devm_free_irq(sd->dev, isp_dev->irq, &isp_dev->ic_dev); + isp_priv_ioctl(&isp_dev->ic_dev, ISPIOC_RESET, NULL); + isp_clear_interrupts(&isp_dev->ic_dev); + msleep(5); + } + + pm_runtime_put(sd->dev); + return 0; +} + +static struct v4l2_subdev_internal_ops isp_internal_ops = { + .open = isp_open, + .close = isp_close, +}; + +int isp_hw_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct isp_device *isp_dev; + struct resource *mem_res; + int irq; + int rc; + struct device_node *mem_node; + + pr_info("enter %s\n", __func__); + isp_dev = kzalloc(sizeof(struct isp_device), GFP_KERNEL); + if (!isp_dev) + return -ENOMEM; + + rc = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node), + "id", &isp_dev->id); + if (rc) { + pr_info("isp device id not found, use the default.\n"); + isp_dev->id = 0; + } + isp_dev->ic_dev.id = isp_dev->id; + + isp_dev->clk_core = devm_clk_get(dev, "core"); + if (IS_ERR(isp_dev->clk_core)) { + rc = PTR_ERR(isp_dev->clk_core); + dev_err(dev, "can't get core clock: %d\n", rc); + return rc; + } + + isp_dev->clk_axi = devm_clk_get(dev, "axi"); + if (IS_ERR(isp_dev->clk_axi)) { + rc = PTR_ERR(isp_dev->clk_axi); + dev_err(dev, "can't get axi clock: %d\n", rc); + return rc; + } + + isp_dev->clk_ahb = devm_clk_get(dev, "ahb"); + if (IS_ERR(isp_dev->clk_ahb)) { + rc = PTR_ERR(isp_dev->clk_ahb); + dev_err(dev, "can't get ahb clock: %d\n", rc); + return rc; + } + + isp_dev->sd.internal_ops = &isp_internal_ops; + +#ifdef ISP8000NANO_V1802 + isp_dev->ic_dev.mix_gpr = syscon_regmap_lookup_by_phandle( + pdev->dev.of_node, "gpr"); + if (IS_ERR(isp_dev->ic_dev.mix_gpr)) { + pr_warn("failed to get mix gpr\n"); + isp_dev->ic_dev.mix_gpr = NULL; + return -ENOMEM; + } +#endif + mem_node = of_parse_phandle(pdev->dev.of_node, "memory-region", 0); + if (!mem_node) { + pr_err("No memory-region found\n"); + return -ENODEV; + } + + isp_dev->ic_dev.rmem = of_reserved_mem_lookup(mem_node); + if (!isp_dev->ic_dev.rmem) { + pr_err("of_reserved_mem_lookup() returned NULL\n"); + return -ENODEV; + } + + v4l2_subdev_init(&isp_dev->sd, &isp_v4l2_subdev_ops); + snprintf(isp_dev->sd.name, sizeof(isp_dev->sd.name), + "%s.%d", ISP_DEVICE_NAME, isp_dev->id); + isp_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + isp_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + isp_dev->sd.owner = THIS_MODULE; + v4l2_set_subdevdata(&isp_dev->sd, isp_dev); + isp_dev->sd.dev = &pdev->dev; + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + isp_dev->ic_dev.base = devm_ioremap_resource(&pdev->dev, mem_res); + if (IS_ERR(isp_dev->ic_dev.base)) { + pr_err("failed to get ioremap resource.\n"); + goto end; + } + +#ifdef ISP_REG_RESET + isp_dev->ic_dev.reset = ioremap(ISP_REG_RESET, 4); +#endif + pr_debug("ioremap addr: %px", isp_dev->ic_dev.base); + isp_dev->ic_dev.state = &isp_dev->state; + + vvbuf_ctx_init(&isp_dev->bctx); + isp_dev->bctx.ops = &isp_buf_ops; + isp_dev->ic_dev.bctx = &isp_dev->bctx; + + isp_dev->ic_dev.alloc = isp_buf_alloc; + isp_dev->ic_dev.free = isp_buf_free; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + pr_err("failed to get irq number.\n"); + goto end; + } + + isp_dev->irq = irq; + pr_debug("request_irq num:%d, rc:%d", irq, rc); + + platform_set_drvdata(pdev, isp_dev); + + isp_dev->sd.entity.name = isp_dev->sd.name; + isp_dev->sd.entity.obj_type = MEDIA_ENTITY_TYPE_V4L2_SUBDEV; + isp_dev->sd.entity.function = MEDIA_ENT_F_IO_V4L; + isp_dev->sd.entity.ops = &isp_media_ops; + isp_dev->pads[ISP_PAD_SOURCE].flags = + MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT; + rc = media_entity_pads_init(&isp_dev->sd.entity, + ISP_PADS_NUM, isp_dev->pads); + if (rc) + goto end; + + isp_dev->sd.fwnode = of_fwnode_handle(pdev->dev.of_node); + rc = v4l2_async_register_subdev(&isp_dev->sd); + if (rc) + goto end; + + pm_runtime_enable(&pdev->dev); + + pr_info("vvcam isp driver registered\n"); + return 0; +end: + vvbuf_ctx_deinit(&isp_dev->bctx); + kfree(isp_dev); + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + return rc; +} + +int isp_hw_remove(struct platform_device *pdev) +{ + struct isp_device *isp = platform_get_drvdata(pdev); + + pr_info("enter %s\n", __func__); + if (!isp) + return -1; + + + vvbuf_ctx_deinit(&isp->bctx); + media_entity_cleanup(&isp->sd.entity); + v4l2_async_unregister_subdev(&isp->sd); + + kfree(isp); + pm_runtime_disable(&pdev->dev); + pr_info("vvcam isp driver removed\n"); + return 0; +} + +static int isp_system_suspend(struct device *dev) +{ + struct platform_device *pdev; + struct isp_device *isp = NULL; + pdev = container_of(dev, struct platform_device, dev); + isp = platform_get_drvdata(pdev); + if(!isp){ + dev_err(dev, "isp suspend failed!\n"); + return -1; + } + + if(isp->ic_dev.streaming == true) { + isp_stop_stream(&isp->ic_dev); + } + + return pm_runtime_force_suspend(dev); +} + +static int isp_system_resume(struct device *dev) +{ + int ret; + struct platform_device *pdev; + struct isp_device *isp = NULL; + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + pdev = container_of(dev, struct platform_device, dev); + isp = platform_get_drvdata(pdev); + if(!isp){ + dev_err(dev, "isp resume failed!\n"); + return -1; + } + + if(isp->ic_dev.streaming == true) { + isp_start_stream(&isp->ic_dev, 1); + } + return 0; +} + +static int isp_runtime_suspend(struct device *dev) +{ + struct isp_device *isp_dev = dev_get_drvdata(dev); + + isp_disable_clocks(isp_dev); + + return 0; +} + +static int isp_runtime_resume(struct device *dev) +{ + struct isp_device *isp_dev = dev_get_drvdata(dev); + + isp_enable_clocks(isp_dev); + + return 0; +} + +static const struct dev_pm_ops isp_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(isp_system_suspend, isp_system_resume) + SET_RUNTIME_PM_OPS(isp_runtime_suspend, isp_runtime_resume, NULL) +}; + +static const struct of_device_id isp_of_match[] = { + {.compatible = ISP_COMPAT_NAME,}, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, isp_of_match); + +static struct platform_driver viv_isp_driver = { + .probe = isp_hw_probe, + .remove = isp_hw_remove, + .driver = { + .name = ISP_DEVICE_NAME, + .owner = THIS_MODULE, + .of_match_table = isp_of_match, + .pm = &isp_pm_ops, + } +}; + +static int __init viv_isp_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&viv_isp_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit viv_isp_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_isp_driver); +} + +module_init(viv_isp_init_module); +module_exit(viv_isp_exit_module); + +MODULE_AUTHOR("Verisilicon ISP SW Team"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Verisilicon-ISP"); +MODULE_VERSION("1.0"); diff --git a/vvcam/v4l2/sensor/Makefile b/vvcam/v4l2/sensor/Makefile new file mode 100755 index 0000000..9e569bc --- /dev/null +++ b/vvcam/v4l2/sensor/Makefile @@ -0,0 +1,5 @@ +obj-m += ov2775/ +obj-m += os08a20/ +obj-m += camera-proxy-driver/ + + diff --git a/vvcam/v4l2/sensor/camera-proxy-driver/COPYING b/vvcam/v4l2/sensor/camera-proxy-driver/COPYING new file mode 100755 index 0000000..29676c9 --- /dev/null +++ b/vvcam/v4l2/sensor/camera-proxy-driver/COPYING @@ -0,0 +1,132 @@ + +GNU GENERAL PUBLIC LICENSE + +Version 2, June 1991 + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. +Preamble + +The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation`s software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. + +To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. + +For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. + +We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. + +Also, for each author`s protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors` reputations. + +Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone`s free use or not licensed at all. + +The precise terms and conditions for copying, distribution and modification follow. + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + +0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. + +1. You may copy and distribute verbatim copies of the Program`s source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. + +You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. + +2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: + +a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. +b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. +c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) +These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. + +3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: + +a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, +b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, +c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) +The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. + +If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. + +4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. + +5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. + +6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients` exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. + +7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. + +This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. + +8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. + +9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. + +10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. + +NO WARRANTY + +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs + +If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. + +one line to give the program`s name and an idea of what it does. +Copyright (C) yyyy name of author + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this when it starts in an interactive mode: + +Gnomovision version 69, Copyright (C) year name of author +Gnomovision comes with ABSOLUTELY NO WARRANTY; for details +type `show w`. This is free software, and you are welcome +to redistribute it under certain conditions; type `show c` +for details. +The hypothetical commands `show w` and `show c` should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w` and `show c`; they could even be mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: + +Yoyodyne, Inc., hereby disclaims all copyright +interest in the program `Gnomovision` +(which makes passes at compilers) written +by James Hacker. + +signature of Ty Coon, 1 April 1989 +Ty Coon, President of Vice +This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. + diff --git a/vvcam/v4l2/sensor/camera-proxy-driver/Makefile b/vvcam/v4l2/sensor/camera-proxy-driver/Makefile new file mode 100755 index 0000000..a1dccb6 --- /dev/null +++ b/vvcam/v4l2/sensor/camera-proxy-driver/Makefile @@ -0,0 +1,3 @@ +EXTRA_CFLAGS += -I$(PWD)/../common/ -DISP8000NANO_V1802 -O2 -Werror +basler-camera-driver-vvcam-objs += basler-camera-driver-vvcam/basler-camera-driver-vvcam.o +obj-m += basler-camera-driver-vvcam.o diff --git a/vvcam/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.c b/vvcam/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.c new file mode 100755 index 0000000..8e25f9e --- /dev/null +++ b/vvcam/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.c @@ -0,0 +1,1080 @@ +/* + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2018 NXP + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + */ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "basler-camera-driver-vvcam.h" +#include "vvsensor.h" + +/*global variable*/ +static struct register_access ra_tmp; + + +/* compact name as v4l2_capability->driver is limited to 16 characters */ +#ifdef CONFIG_BASLER_CAMERA_VVCAM +#define SENSOR_NAME "basler-vvcam" +#else +#define SENSOR_NAME "basler-camera" +#endif + + +/* + * ABRM register offsets + * + */ +#define ABRM_GENCP_VERSION 0x0 +#define ABRM_MANUFACTURER_NAME 0x4 +#define ABRM_MODEL_NAME 0x44 +#define ABRM_FAMILY_NAME 0x84 +#define ABRM_DEVICE_VERSION 0xC4 +#define ABRM_MANUFACTURER_INFO 0x104 +#define ABRM_SERIAL_NUMBER 0x144 +#define ABRM_USER_DEFINED_NAME 0x184 +#define ABRM_DEVICE_CAPABILITIES 0x1C4 + +/* + * ABRM register bits + * + */ +#define ABRM_DEVICE_CAPABILITIES_USER_DEFINED_NAMES_SUPPORT 0x1 +#define ABRM_DEVICE_CAPABILITIES_STRING_ENCODING 0x0f +#define ABRM_DEVICE_CAPABILITIES_FAMILY_NAME 0x100 + + +/* + * Maximum read i2c burst + * + * TODO: To be replace by a register call of SBRM + * + */ +#define I2C_MAXIMUM_READ_BURST 8 + + + +static int basler_read_register_chunk(struct i2c_client* client, __u8* buffer, __u8 buffer_size, __u16 register_address); + +static int basler_camera_s_ctrl(struct v4l2_ctrl *ctrl); +static int basler_camera_g_volatile_ctrl(struct v4l2_ctrl *ctrl); +static int basler_camera_validate(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr); +static void basler_camera_init(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr); +static bool basler_camera_equal(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr1, union v4l2_ctrl_ptr ptr2); + +struct basler_camera_dev { + struct i2c_client *i2c_client; + struct v4l2_device *v4l2_dev; + struct v4l2_subdev sd; + struct media_pad pad; + + /* lock to protect all members below */ + struct mutex lock; + + int power_count; + struct v4l2_ctrl_handler ctrl_handler; + + struct basler_device_information device_information; + + int csi; +}; + +/** + * basler_write_burst - issue a burst I2C message in master transmit mode + * @client: Handle to slave device + * @ra_p: Data structure that hold the register address and data that will be written to the slave + * + * Returns negative errno, or else the number of bytes written. + */ +static int basler_write_burst(struct i2c_client *client, + struct register_access *ra_p) +{ + int ret; + __u16 old_address; + + if (ra_p->data_size > sizeof(ra_p->data)){ + dev_err(&client->dev, "i2c burst array too big, max allowed %lu, got %d\n", sizeof(ra_p->data), ra_p->data_size); + return -EINVAL; + } + + old_address = ra_p->address; + ra_p->address = cpu_to_be16(ra_p->address); + + if (I2CREAD == (ra_p->command | I2CREAD)){ + ra_tmp.address = ra_p->address; + ra_tmp.data_size = ra_p->data_size; + old_address = ra_p->address; + return ra_p->data_size; + } + else if(I2CWRITE == (ra_p->command | I2CWRITE)){ + ret = i2c_master_send(client, (char *)ra_p, ra_p->data_size + sizeof(ra_p->address)); + + if(ret) + ra_p->data_size = ret; + + old_address = ra_p->address; + return ret; + } + else + return -EPERM; +} + +/** + * basler_read_burst - issue a burst I2C message in master transmit mode + * @client: Handle to slave device + * @ra_p: Data structure store the data read from slave + * + * Note: Before data can read use basler_write_burst with read command + * to send the register address + * + * Returns negative errno, or else the number of bytes written. + */ +static int basler_read_burst(struct i2c_client *client, + struct register_access *ra_p) +{ + int ret; + + ret = basler_read_register_chunk(client, ra_p->data, ra_tmp.data_size, + ra_tmp.address); + if (ret < 0) + ra_p->data_size = 0; + else + ra_p->data_size = ret; + + return ret; +} + + +static int basler_read_register_chunk(struct i2c_client* client, __u8* buffer, __u8 buffer_size, __u16 register_address) +{ + struct i2c_msg msgs[2] = {}; + int ret = 0; + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].buf = (__u8 *)®ister_address; + msgs[0].len = sizeof(register_address); + + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].buf = buffer; + msgs[1].len = buffer_size; + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret < 0) { + pr_err("i2c_transfer() failed: %d\n", ret); + return ret; + } + + if (ret != 2) { + pr_err("i2c_transfer() incomplete"); + return -EIO; + } + + return msgs[1].len; +} + +static int basler_read_register(struct i2c_client* client, __u8* buffer, __u8 buffer_size, __u16 register_address) +{ + int ret = 0; + __u8 l_read_bytes = 0; + + do { + __be16 l_register_address = cpu_to_be16(register_address + l_read_bytes); + + ret = basler_read_register_chunk(client, (__u8*) buffer + l_read_bytes, (__u8) min(I2C_MAXIMUM_READ_BURST, ((int)buffer_size - l_read_bytes)), l_register_address); + if (ret < 0) + { + pr_err("basler_read_register_chunk() failed: %d\n", ret); + return ret; + } + else if (ret == 0) + { + pr_err("basler_read_register_chunk() read 0 bytes.\n"); + return -EIO; + } + + l_read_bytes = l_read_bytes + ret; + } while (l_read_bytes < buffer_size); + + return l_read_bytes; +} + + +static int basler_retrieve_device_information(struct i2c_client* client, struct basler_device_information* bdi) +{ + int ret = 0; + __u64 deviceCapabilities = 0; + __be64 deviceCapabilitiesBe = 0; + __u32 gencpVersionBe = 0; + + bdi->_magic = BDI_MAGIC; + + ret = basler_read_register(client, (__u8*) &deviceCapabilitiesBe, sizeof(deviceCapabilitiesBe), ABRM_DEVICE_CAPABILITIES); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == sizeof(deviceCapabilitiesBe)) + { + deviceCapabilities = be64_to_cpu(deviceCapabilitiesBe); + pr_debug("deviceCapabilities = 0x%llx\n", deviceCapabilities); + pr_debug("String Encoding = 0x%llx\n", (deviceCapabilities & ABRM_DEVICE_CAPABILITIES_STRING_ENCODING) >> 4); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + ret = basler_read_register(client, (__u8*) &gencpVersionBe, sizeof(gencpVersionBe), ABRM_GENCP_VERSION); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == sizeof(gencpVersionBe)) + { + bdi->gencpVersion = be32_to_cpu(gencpVersionBe); + pr_debug("l_gencpVersion = %d.%d\n", (bdi->gencpVersion & 0xffff0000) >> 16, bdi->gencpVersion & 0xffff); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + ret = basler_read_register(client, bdi->deviceVersion, GENCP_STRING_BUFFER_SIZE, ABRM_DEVICE_VERSION); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->deviceVersion = %s\n", bdi->deviceVersion); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + ret = basler_read_register(client, bdi->serialNumber, GENCP_STRING_BUFFER_SIZE, ABRM_SERIAL_NUMBER); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->serialNumber = %s\n", bdi->serialNumber); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + ret = basler_read_register(client, bdi->manufacturerName, GENCP_STRING_BUFFER_SIZE, ABRM_MANUFACTURER_NAME); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->manufacturerName = %s\n", bdi->manufacturerName); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + ret = basler_read_register(client, bdi->modelName, GENCP_STRING_BUFFER_SIZE, ABRM_MODEL_NAME); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->modelName = %s\n", bdi->modelName); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + if (deviceCapabilities & ABRM_DEVICE_CAPABILITIES_FAMILY_NAME) + { + ret = basler_read_register(client, bdi->familyName, GENCP_STRING_BUFFER_SIZE, ABRM_FAMILY_NAME); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->familyName = %s\n", bdi->familyName); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + } + else + pr_notice("ABRM FamilyName not supported\n"); + + if (deviceCapabilities & ABRM_DEVICE_CAPABILITIES_USER_DEFINED_NAMES_SUPPORT) + { + ret = basler_read_register(client, bdi->userDefinedName, GENCP_STRING_BUFFER_SIZE, ABRM_USER_DEFINED_NAME); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->userDefinedName = %s\n", bdi->userDefinedName); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + } + else + pr_notice("ABRM UserDefinedName not supported\n"); + + ret = basler_read_register(client, bdi->manufacturerInfo, GENCP_STRING_BUFFER_SIZE, ABRM_MANUFACTURER_INFO); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->manufacturerInfo = %s\n", bdi->manufacturerInfo); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + /* + * If the strings are in ASCII - print it. + */ + if (((deviceCapabilities & ABRM_DEVICE_CAPABILITIES_STRING_ENCODING) >> 4) == 0) + { + pr_info("ABRM: Manufacturer: %s, Model: %s, Device: %s, Serial: %s\n", bdi->manufacturerName, bdi->modelName, bdi->deviceVersion, bdi->serialNumber); + } + + return 0; +} + +static int basler_retrieve_csi_information(struct basler_camera_dev *sensor, + struct basler_csi_information* bci) +{ + struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = V4L2_MBUS_CSI2_DPHY }; + struct device *dev = &sensor->i2c_client->dev; + struct device_node *ep; + int ret; + + /* We need a function that searches for the device that holds + * the csi-2 bus information. For now we put the bus information + * also into the sensor endpoint itself. + */ + ep = of_graph_get_next_endpoint(dev->of_node, NULL); + if (!ep) { + dev_err(dev, "missing endpoint node\n"); + return -ENODEV; + } + + ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &bus_cfg); + of_node_put(ep); + if (ret) { + dev_err(dev, "failed to parse endpoint\n"); + return ret; + } + + if (bus_cfg.bus_type != V4L2_MBUS_CSI2_DPHY || + bus_cfg.bus.mipi_csi2.num_data_lanes == 0 || + bus_cfg.nr_of_link_frequencies == 0) { + dev_err(dev, "missing CSI-2 properties in endpoint\n"); + ret = -ENODATA; + } else { + int i; + bci->max_lane_frequency = bus_cfg.link_frequencies[0]; + bci->lane_count = bus_cfg.bus.mipi_csi2.num_data_lanes; + for (i = 0; i < bus_cfg.bus.mipi_csi2.num_data_lanes; ++i) { + bci->lane_assignment[i] = bus_cfg.bus.mipi_csi2.data_lanes[i]; + } + ret = 0; + } + return ret; +} + +static int basler_retrieve_capture_properties(struct basler_camera_dev *sensor, + struct basler_capture_properties* bcp) +{ + struct device *dev = &sensor->i2c_client->dev; + __u64 mlf = 0; + __u64 mpf = 0; + __u64 mdr = 0; + struct device_node *ep; + + int ret; + + /* Collecting the information about limits of capture path + * has been centralized to the sensor + * also into the sensor endpoint itself. + */ + ep = of_graph_get_next_endpoint(dev->of_node, NULL); + if (!ep) { + dev_err(dev, "missing endpoint node\n"); + return -ENODEV; + } + + ret = fwnode_property_read_u64(of_fwnode_handle(ep), + "max-lane-frequency", &mlf); + if (ret || mlf == 0) { + dev_dbg(dev, "no limit for max-lane-frequency\n"); + } + + ret = fwnode_property_read_u64(of_fwnode_handle(ep), + "max-pixel-frequency", &mpf); + if (ret || mpf == 0) { + dev_dbg(dev, "no limit for max-pixel-frequency\n"); + } + + ret = fwnode_property_read_u64(of_fwnode_handle(ep), + "max-data-rate", &mdr); + if (ret || mdr == 0) { + dev_dbg(dev, "no limit for max-data_rate\n"); + } + + bcp->max_lane_frequency = mlf; + bcp->max_pixel_frequency = mpf; + bcp->max_data_rate = mdr; + + return ret; +} + + +static inline struct basler_camera_dev *to_basler_camera_dev(struct v4l2_subdev *sd) +{ + return container_of(sd, struct basler_camera_dev, sd); +} + +static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) +{ + return &container_of(ctrl->handler, struct basler_camera_dev, + ctrl_handler)->sd; +} + +/** + * basler_camera_set_fmt - set format of the camera + * + * Note: Will be done in user space + * + * Returns always zero + */ +static int basler_camera_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + return 0; +} + +/** + * basler_camera_s_stream - start camera streaming + * + * Note: Will be done in user space + * + * Returns always zero + */ +static int basler_camera_s_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static int basler_camera_s_power(struct v4l2_subdev *sd, int on) +{ + struct basler_camera_dev *sensor = to_basler_camera_dev(sd); + + mutex_lock(&sensor->lock); + + /* Update the power count. */ + sensor->power_count += on ? 1 : -1; + WARN_ON(sensor->power_count < 0); + + mutex_unlock(&sensor->lock); + + return 0; +} + +static int basler_ioc_qcap(struct basler_camera_dev *sensor, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + strcpy((char *)cap->driver, SENSOR_NAME); + + sprintf((char *)cap->bus_info, "csi%d",sensor->csi); //bus_info[0:7]-csi number + if(sensor->i2c_client->adapter) + { + //bus_info[8]-i2c bus dev number + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = (__u8)sensor->i2c_client->adapter->nr; + } + else + { + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = 0xFF; + } + + + + + return 0; +} + +/* +Use USER_TO_KERNEL/KERNEL_TO_USER to fix "uaccess" exception on run time. +Also, use "copy_ret" to fix the build issue as below. +error: ignoring return value of function declared with 'warn_unused_result' attribute. +*/ + +#ifdef CONFIG_HARDENED_USERCOPY +#define USER_TO_KERNEL(TYPE) \ + do {\ + TYPE tmp; \ + unsigned long copy_ret; \ + arg = (void *)(&tmp); \ + copy_ret = copy_from_user(arg, arg_user, sizeof(TYPE));\ + } while (0) + +#define KERNEL_TO_USER(TYPE) \ + do {\ + unsigned long copy_ret; \ + copy_ret = copy_to_user(arg_user, arg, sizeof(TYPE));\ + } while (0) +#else +#define USER_TO_KERNEL(TYPE) +#define KERNEL_TO_USER(TYPE) +#endif + + +static long basler_camera_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg_user) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct basler_camera_dev * sensor = to_basler_camera_dev(sd); + void *arg = arg_user; + + int ret = -1; + + switch (cmd) { + case VIDIOC_QUERYCAP: + ret = basler_ioc_qcap(sensor, arg); + break; + + case BASLER_IOC_G_INTERFACE_VERSION: + { + USER_TO_KERNEL(__u32); + *((__u32*)arg) = (((__u32)BASLER_INTERFACE_VERSION_MAJOR) << 16) | BASLER_INTERFACE_VERSION_MINOR; + KERNEL_TO_USER(__u32); + ret = 0; + break; + } + + case BASLER_IOC_READ_REGISTER: + { + struct register_access *ra_p; + USER_TO_KERNEL(struct register_access); + ra_p = (struct register_access *)arg; + ret = basler_read_register(client, + ra_p->data, + ra_p->data_size, + ra_p->address); + if (ret < 0) + ra_p->data_size = 0; + else + ra_p->data_size = ret; + KERNEL_TO_USER(struct register_access); + } + break; + + case BASLER_IOC_WRITE_REGISTER: + { + struct register_access ra; + struct register_access * ra_p; + USER_TO_KERNEL(struct register_access); + ra_p = (struct register_access *)arg; + + memcpy (&ra, ra_p, sizeof(ra)); + ra.address = cpu_to_be16(ra_p->address); + + ret = i2c_master_send(client, (char *)&ra, ra.data_size + sizeof(ra.address)); + if(ret) { + ra_p->data_size = ret; + ret = 0; + } + else + ret = -EIO; + } + break; + + case BASLER_IOC_G_DEVICE_INFORMATION: + { + USER_TO_KERNEL(struct basler_device_information); + memcpy((struct basler_device_information *)arg, &sensor->device_information, sizeof(struct basler_device_information)); + KERNEL_TO_USER(struct basler_device_information); + ret = 0; + break; + } + + case BASLER_IOC_G_CSI_INFORMATION: + { + USER_TO_KERNEL(struct basler_csi_information); + ret = basler_retrieve_csi_information(sensor, (struct basler_csi_information*)arg); + KERNEL_TO_USER(struct basler_csi_information); + break; + } + case BASLER_IOC_G_CAPTURE_PROPERTIES: + { + USER_TO_KERNEL(struct basler_capture_properties); + ret = basler_retrieve_capture_properties(sensor, (struct basler_capture_properties*)arg); + KERNEL_TO_USER(struct basler_capture_properties); + break; + } + + default: + break; + } + return ret; +} + +static const struct v4l2_subdev_core_ops basler_camera_core_ops = { + .s_power = basler_camera_s_power, + .ioctl = basler_camera_priv_ioctl, +}; + +static const struct v4l2_subdev_video_ops basler_camera_video_ops = { + .s_stream = basler_camera_s_stream, +}; + +static const struct v4l2_subdev_pad_ops basler_camera_pad_ops = { + .set_fmt = basler_camera_set_fmt, +}; + +static const struct v4l2_subdev_ops basler_camera_subdev_ops = { + .core = &basler_camera_core_ops, + .video = &basler_camera_video_ops, + .pad = &basler_camera_pad_ops, +}; + +static const struct v4l2_ctrl_ops basler_camera_ctrl_ops = { + .g_volatile_ctrl = basler_camera_g_volatile_ctrl, + .s_ctrl = basler_camera_s_ctrl, +}; + +static const struct v4l2_ctrl_type_ops basler_camera_ctrl_type_ops = { + .validate = basler_camera_validate, + .init = basler_camera_init, + .equal = basler_camera_equal, +}; + +/** + * basler_camera_validate + * + * Note: Not needed by access-register control + * + * Returns always zero + */ +static int basler_camera_validate(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr ) +{ + return 0; +} + +/** + * basler_camera_init + * + * Note: Not needed by access-register control + * + */ +static void basler_camera_init(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr ) +{ +} + +/** + * basler_camera_equal + * + * Note: Not needed by access-register control + * + * Returns always zero + */ +static bool basler_camera_equal(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr1, union v4l2_ctrl_ptr ptr2 ) +{ + return 0; +} + +static const struct v4l2_ctrl_config ctrl_access_register = { + .ops = &basler_camera_ctrl_ops, + .type_ops = &basler_camera_ctrl_type_ops, + .id = V4L2_CID_BASLER_ACCESS_REGISTER, + .name = "basler-access-register", + .type = V4L2_CTRL_TYPE_U32+1, + .flags = V4L2_CTRL_FLAG_EXECUTE_ON_WRITE | V4L2_CTRL_FLAG_VOLATILE, + .step = 1, + .dims = {1}, + .elem_size = sizeof(struct register_access), +}; + +static const struct v4l2_ctrl_config ctrl_basler_device_information = { + .ops = &basler_camera_ctrl_ops, + .type_ops = &basler_camera_ctrl_type_ops, + .id = V4L2_CID_BASLER_DEVICE_INFORMATION, + .name = "basler-device-information", + .type = V4L2_CTRL_TYPE_U32+1, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + .step = 1, + .dims = {1}, + .elem_size = sizeof(struct basler_device_information), +}; + +static const struct v4l2_ctrl_config ctrl_basler_interface_version = { + .ops = &basler_camera_ctrl_ops, + .type_ops = &basler_camera_ctrl_type_ops, + .id = V4L2_CID_BASLER_INTERFACE_VERSION, + .name = "basler-interface-version", + .type = V4L2_CTRL_TYPE_INTEGER, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + .min = 0x0, + .max = 0xffffffff, + .def = (BASLER_INTERFACE_VERSION_MAJOR << 16) | BASLER_INTERFACE_VERSION_MINOR, + .step = 1, +}; + +static const struct v4l2_ctrl_config ctrl_basler_csi_information = { + .ops = &basler_camera_ctrl_ops, + .type_ops = &basler_camera_ctrl_type_ops, + .id = V4L2_CID_BASLER_CSI_INFORMATION, + .name = "basler-csi-information", + .type = V4L2_CTRL_TYPE_U32+1, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + .step = 1, + .dims = {1}, + .elem_size = sizeof(struct basler_csi_information), +}; + +static int basler_camera_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct v4l2_subdev *sd = ctrl_to_sd(ctrl); + struct basler_camera_dev *sensor = to_basler_camera_dev(sd); + struct i2c_client *client = sensor->i2c_client; + int ret; + struct register_access *fp_ra_new; + + switch (ctrl->id) { + case V4L2_CID_BASLER_ACCESS_REGISTER: + + if (ctrl->elem_size != sizeof(struct register_access)) + return -ENOMEM; + + fp_ra_new = (struct register_access*) ctrl->p_new.p; + if(basler_write_burst(client, fp_ra_new)) + ret = 0; + else + ret = -EIO; + + break; + + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int basler_camera_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct v4l2_subdev *sd = ctrl_to_sd(ctrl); + struct basler_camera_dev *sensor = to_basler_camera_dev(sd); + struct i2c_client *client = sensor->i2c_client; + int ret; + struct register_access *fp_ra_new = NULL; + struct basler_device_information* l_bdi = NULL; + + switch (ctrl->id) { + case V4L2_CID_BASLER_ACCESS_REGISTER: + + fp_ra_new = (struct register_access*) ctrl->p_new.p; + + if (ctrl->elem_size == sizeof(struct register_access)) + { + if(basler_read_burst(client, fp_ra_new)) + ret = 0; + else + ret = -EIO; + } + else { + ret = -ENOMEM; + } + break; + + case V4L2_CID_BASLER_DEVICE_INFORMATION: + + l_bdi = (struct basler_device_information*) ctrl->p_new.p; + + if (ctrl->elem_size == sizeof(struct basler_device_information)) + { + memcpy(l_bdi, &sensor->device_information, sizeof(struct basler_device_information)); + ret = 0; + } + else + { + ret = -ENOMEM; + } + break; + + case V4L2_CID_BASLER_CSI_INFORMATION: + if (ctrl->elem_size == sizeof(struct basler_csi_information)) + { + struct basler_csi_information* l_bci = NULL; + l_bci = (struct basler_csi_information*) ctrl->p_new.p; + ret = basler_retrieve_csi_information(sensor, l_bci); + } + else + { + ret = -ENOMEM; + } + break; + case V4L2_CID_BASLER_CAPTURE_PROPERTIES: + if (ctrl->elem_size == sizeof(struct basler_capture_properties)) + { + struct basler_capture_properties* l_bcp = NULL; + l_bcp = (struct basler_capture_properties*) ctrl->p_new.p; + ret = basler_retrieve_capture_properties(sensor, l_bcp); + } + else + { + ret = -ENOMEM; + } + break; + + default: + ret = -EINVAL; + break; + } + + return ret; +} + + +/** + * basler_camera_link_setup + * + * Note: Function is needed by imx8qm + * + * Returns always zero + */ +static int basler_camera_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static const struct media_entity_operations basler_camera_sd_media_ops = { + .link_setup = basler_camera_link_setup, +}; + + +static int basler_camera_init_controls(struct basler_camera_dev *sensor) +{ + struct v4l2_ctrl_handler *hdl = &sensor->ctrl_handler; + int ret; + + v4l2_ctrl_handler_init(hdl, 32); + + /* we can use our own mutex for the ctrl lock */ + hdl->lock = &sensor->lock; + + v4l2_ctrl_new_custom(hdl, &ctrl_access_register, NULL); + if (hdl->error) + { + dev_err(&sensor->i2c_client->dev, "Register ctrl access_register failed: %d\n", hdl->error); + ret = hdl->error; + goto free_ctrls; + } + + v4l2_ctrl_new_custom(hdl, &ctrl_basler_device_information, NULL); + if (hdl->error) + { + dev_err(&sensor->i2c_client->dev, "Register ctrl device_information failed: %d\n", hdl->error); + ret = hdl->error; + goto free_ctrls; + } + + v4l2_ctrl_new_custom(hdl, &ctrl_basler_interface_version, NULL); + if (hdl->error) + { + dev_err(&sensor->i2c_client->dev, "Register ctrl interface_version failed: %d\n", hdl->error); + ret = hdl->error; + goto free_ctrls; + } + + v4l2_ctrl_new_custom(hdl, &ctrl_basler_csi_information, NULL); + if (hdl->error) + { + dev_err(&sensor->i2c_client->dev, "Register ctrl csi_information failed: %d\n", hdl->error); + ret = hdl->error; + goto free_ctrls; + } + + sensor->sd.ctrl_handler = hdl; + return 0; + +free_ctrls: + v4l2_ctrl_handler_free(hdl); + dev_dbg(sensor->sd.v4l2_dev->dev, "%s: ctrl handler error.\n", __func__); + return ret; +} + +static int basler_camera_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct basler_camera_dev *sensor; + int ret; + + dev_dbg(dev, " %s driver start probing\n", SENSOR_NAME); + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + dev_err(dev, "I2C_FUNC_I2C not supported\n"); + return -ENODEV; + } + + sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + + sensor->i2c_client = client; + + ret = of_property_read_u32(dev->of_node, "csi_id", &(sensor->csi)); + if (ret) { + dev_err(dev, "csi id missing or invalid\n"); + return ret; + } + + v4l2_i2c_subdev_init(&sensor->sd, client, &basler_camera_subdev_ops); + + ret = basler_retrieve_device_information(client, &sensor->device_information); + if (ret) + return ret; + + sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + sensor->pad.flags = MEDIA_PAD_FL_SOURCE; + + sensor->sd.entity.ops = &basler_camera_sd_media_ops; + ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad); + if (ret) + return ret; + + mutex_init(&sensor->lock); + + ret = basler_camera_init_controls(sensor); + if (ret) + goto entity_cleanup; + + ret = v4l2_async_register_subdev_sensor_common(&sensor->sd); + if (ret) + goto entity_cleanup; + + dev_dbg(dev, " %s driver probed\n", SENSOR_NAME); + return 0; + +entity_cleanup: + mutex_destroy(&sensor->lock); + media_entity_cleanup(&sensor->sd.entity); + return ret; +} + +static int basler_camera_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct basler_camera_dev *sensor = to_basler_camera_dev(sd); + + v4l2_async_unregister_subdev(&sensor->sd); + sensor->sd.ctrl_handler = NULL; + v4l2_ctrl_handler_free(&sensor->ctrl_handler); + mutex_destroy(&sensor->lock); + media_entity_cleanup(&sensor->sd.entity); + + return 0; +} + +static const struct i2c_device_id basler_camera_id[] = { + { "basler-camera-vvcam", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, basler_camera_id); + +static const struct of_device_id basler_camera_dt_ids[] = { +#ifdef CONFIG_BASLER_CAMERA_VVCAM + { .compatible = "basler,basler-camera-vvcam" }, +#else + { .compatible = "basler,basler-camera" }, +#endif + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, basler_camera_dt_ids); + +static struct +#ifdef CONFIG_BASLER_CAMERA_VVCAM + i2c_driver basler_camera_i2c_driver_vvcam +#else + i2c_driver basler_camera_i2c_driver +#endif + = { + .driver = { + .owner = THIS_MODULE, +#ifdef CONFIG_BASLER_CAMERA_VVCAM + .name = "basler-camera-vvcam", +#else + .name = "basler-camera", +#endif + .of_match_table = basler_camera_dt_ids, + }, + .id_table = basler_camera_id, + .probe = basler_camera_probe, + .remove = basler_camera_remove, +}; + +#ifdef CONFIG_BASLER_CAMERA_VVCAM +module_i2c_driver(basler_camera_i2c_driver_vvcam); +#else +module_i2c_driver(basler_camera_i2c_driver); +#endif + +MODULE_DESCRIPTION("Basler camera subdev driver for vvcam"); +MODULE_AUTHOR("Sebastian Suesens "); +MODULE_LICENSE("GPL"); diff --git a/vvcam/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.h b/vvcam/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.h new file mode 100755 index 0000000..5e80d3e --- /dev/null +++ b/vvcam/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2018 NXP + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + */ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef BASLER_CAMERA_DRIVER_VVCAM_H +#define BASLER_CAMERA_DRIVER_VVCAM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __KERNEL__ + +#include +#include + +#endif /* __KERNEL__ */ + +#define V4L2_CID_PROXY_BASE (V4L2_CTRL_CLASS_USER | 0x1000) +#define V4L2_CID_BASLER_INTERFACE_VERSION (V4L2_CID_PROXY_BASE+1) +#define V4L2_CID_BASLER_ACCESS_REGISTER (V4L2_CID_PROXY_BASE+2) +#define V4L2_CID_BASLER_DEVICE_INFORMATION (V4L2_CID_PROXY_BASE+3) +#define V4L2_CID_BASLER_CSI_INFORMATION (V4L2_CID_PROXY_BASE+4) +#define V4L2_CID_BASLER_CAPTURE_PROPERTIES (V4L2_CID_PROXY_BASE+5) +#define I2CREAD (1) +#define I2CWRITE (2) + +#define GENCP_STRING_BUFFER_SIZE (64) +#define STRING_TERMINATION (1) +#define BDI_MAGIC (84513200) + +/* + * Basler interface Version + */ +#define BASLER_INTERFACE_VERSION_MAJOR ((__u16) 1) +#define BASLER_INTERFACE_VERSION_MINOR ((__u16) 1) + +/* + Write register: + IOCTL VIDIOC_S_EXT_CTRLS with command == I2CWRITE + address, size and value + + Read register: + IOCTL VIDIOC_S_EXT_CTRLS with command == I2CREAD + address and size + then IOCTL VIDIOC_G_EXT_CTRLS returns value + + For the maximum buffer size to use in a read or write command please consider the values + "Maximum Write Transfer Length" and "Maximum Read Transfer Length" as described in the MCM Interface Specification. + These values can differ on the different sensor modules. +*/ +struct register_access { + __u16 address; /* Register address; host endianness*/ + __u8 data[256]; /* Read/Write register value - target endianness */ + __u16 data_size; /* Host endianness */ + __u8 command; /* On a VIDIOC_S_EXT_CTRLS identifies to store the register address */ +}; + +struct basler_device_information { + __u32 _magic; + __u32 gencpVersion; + __u8 manufacturerName[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 modelName[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 familyName[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 deviceVersion[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 manufacturerInfo[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 serialNumber[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 userDefinedName[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; +}; + +/** + * struct basler_csi_information - sensor specific csi2 bus configuration. + * The cid to query this structure is V4L2_CID_BASLER_CSI_INFORMATION. + * The ioctl to query this structure is BASLER_IOC_G_CAPTURE_PROPERTIES + * + * @max_lanefrequency Max theoretical CSI frequency per lane in hertz. + * @lanecount Available CSI lane count. + * @laneassignment describes the physical CSI-2 connection between host and camera module. + * The index starts with 0 as CSI lane 1 of the host. + * The value starts with 1 as the CSI lane 1 of the sensor. + */ +struct basler_csi_information { + __u64 max_lane_frequency; + __u8 lane_count; + __u8 lane_assignment[4]; +}; + +/** +* struct basler_capture_properties - sensor specific capture path properties +* The cid to query this structure is V4L2_CID_BASLER_CAPTURE_PROPERTIES +* The ioctl to query this structure is BASLER_IOC_G_CAPTURE_PROPERTIES +* +* @max_lane_frequency Max supported CSI frequency per lane in hertz. +* @max_pixel_frequency Max supported Pixel frequency for the video capture. +* @max_data_rate Max supported data rate in bytes/second +*/ +struct basler_capture_properties { + __u64 max_lane_frequency; + __u64 max_pixel_frequency; + __u64 max_data_rate; +}; + +enum { + BASLER_IOC_G_INTERFACE_VERSION = 0x100, + BASLER_IOC_READ_REGISTER, + BASLER_IOC_WRITE_REGISTER, + BASLER_IOC_G_DEVICE_INFORMATION, + BASLER_IOC_G_CSI_INFORMATION, + BASLER_IOC_G_CAPTURE_PROPERTIES + +}; + + +#ifdef ISP8000NANO_V1802 +#define CONFIG_BASLER_CAMERA_VVCAM +#endif + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* BASLER_CAMERA_DRIVER_VVCAM_H */ diff --git a/vvcam/v4l2/sensor/os08a20/Makefile b/vvcam/v4l2/sensor/os08a20/Makefile new file mode 100755 index 0000000..f9ccd3f --- /dev/null +++ b/vvcam/v4l2/sensor/os08a20/Makefile @@ -0,0 +1,3 @@ +EXTRA_CFLAGS += -I$(PWD)/../common/ -O2 -Werror +os08a20-objs += os08a20_mipi_v3.o +obj-m += os08a20.o diff --git a/vvcam/v4l2/sensor/os08a20/os08a20_mipi_v3.c b/vvcam/v4l2/sensor/os08a20/os08a20_mipi_v3.c new file mode 100755 index 0000000..5d857eb --- /dev/null +++ b/vvcam/v4l2/sensor/os08a20/os08a20_mipi_v3.c @@ -0,0 +1,1637 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vvsensor.h" + +#include "os08a20_regs_1080p.h" +#include "os08a20_regs_1080p_hdr.h" +#include "os08a20_regs_4k.h" +#include "os08a20_regs_4k_hdr.h" +#include "os08a20_regs_1080p_hdr.h" + +#define OS08a20_VOLTAGE_ANALOG 2800000 +#define OS08a20_VOLTAGE_DIGITAL_CORE 1500000 +#define OS08a20_VOLTAGE_DIGITAL_IO 1800000 + +#define MIN_FPS 15 +#define MAX_FPS 30 +#define DEFAULT_FPS 30 + +#define OS08a20_XCLK_MIN 6000000 +#define OS08a20_XCLK_MAX 24000000 + +#define OS08a20_CHIP_ID_HIGH_BYTE 0x300A +#define OS08a20_CHIP_ID_LOW_BYTE 0x300B + +#define OS08a20_SENS_PAD_SOURCE 0 +#define OS08a20_SENS_PADS_NUM 1 + +enum os08a20_mode { + os08a20_mode_MIN = 0, + os08a20_mode_4K_3840_2160 = 0, + os08a20_mode_1080P_1920_1080 = 0, + os08a20_mode_720P_1280_720 = 1, + os08a20_mode_NTSC_720_480 = 2, + os08a20_mode_VGA_640_480 = 3, + os08a20_mode_QVGA_320_240 = 4, + os08a20_mode_QSXGA_2592_1944 = 5, + os08a20_mode_MAX, + os08a20_mode_INIT = 0xff, /* only for sensor init */ +}; + +enum os08a20_frame_rate { + os08a20_15_fps, + os08a20_30_fps +}; + +struct os08a20_datafmt { + u32 code; + enum v4l2_colorspace colorspace; +}; + +/* image size under 1280 * 960 are SUBSAMPLING + * image size upper 1280 * 960 are SCALING + */ +enum os08a20_downsize_mode { + SUBSAMPLING, + SCALING, +}; + +struct os08a20_mode_info { + enum os08a20_mode mode; + enum os08a20_downsize_mode dn_mode; + u32 width; + u32 height; + struct vvsensor_reg_value_t *init_data_ptr; + u32 init_data_size; + u32 bit_width; + u32 fps; + bool is_default; + u32 stitching_mode; +}; + +struct os08a20_pll_info { + enum os08a20_mode mode; + struct vvsensor_reg_value_t *init_data_ptr; + u32 init_data_size; +}; + +struct os08a20_hs_info { + u32 width; + u32 height; + u32 frame_rate; + u32 val; +}; + +struct os08a20 { + struct regulator *io_regulator; + struct regulator *core_regulator; + struct regulator *analog_regulator; + struct v4l2_subdev subdev; + struct v4l2_device *v4l2_dev; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + const struct os08a20_datafmt *fmt; + struct v4l2_captureparm streamcap; + struct media_pad pads[OS08a20_SENS_PADS_NUM]; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + u32 mclk; + u8 mclk_source; + struct clk *sensor_clk; + int csi; + + void (*io_init) (struct os08a20 *); + int pwn_gpio, rst_gpio; + bool hdr; + int fps; + + vvcam_mode_info_t cur_mode; + struct mutex lock; +}; + +#define client_to_os08a20(client)\ + container_of(i2c_get_clientdata(client), struct os08a20, subdev) + +long os08a20_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg); +static void os08a20_stop(struct os08a20 *sensor); +s32 os08a20_write_reg(struct os08a20 *sensor, u16 reg, u8 val); + +static struct vvcam_mode_info pos08a20_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x492, + .one_line_exp_time_ns = 14250, + .max_integration_time = 0x492 - 8, + .min_integration_time = 8, + .gain_accuracy = 1024, + .max_gain = 62 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = os08a20_init_setting_1080p, + .reg_data_count = ARRAY_SIZE(os08a20_init_setting_1080p), + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_DUAL_DCG, + .bit_width = 10, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x492, + .one_line_exp_time_ns = 14250, + .max_integration_time = 0x492 - 8, + .min_integration_time = 8, + .gain_accuracy = 1024, + .max_gain = 62 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = os08a20_init_setting_1080p_hdr, + .reg_data_count = ARRAY_SIZE(os08a20_init_setting_1080p_hdr), + }, + { + .index = 2, + .width = 3840, + .height = 2160, + .fps = 20, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 12, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0xDB4, + .one_line_exp_time_ns = 14250, + .max_integration_time = 0xDB4 - 64 - 4, + .min_integration_time = 8, + .gain_accuracy = 1024, + .max_gain = 62 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = os08a20_init_setting_4k, + .reg_data_count = ARRAY_SIZE(os08a20_init_setting_4k), + }, + { + .index = 3, + .width = 3840, + .height = 2160, + .fps = 15, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_L_AND_S, + .bit_width = 10, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x960, + .one_line_exp_time_ns = 13889, + .max_integration_time = 0x960 - 64 - 4,//T_long + Tshort < VTS - 4 + .min_integration_time = 8, + .gain_accuracy = 1024, + .max_gain = 62 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = os08a20_init_setting_4k_hdr, + .reg_data_count = ARRAY_SIZE(os08a20_init_setting_4k_hdr), + }, +}; + + +static struct os08a20_hs_info hs_setting[] = { + {1920, 1080, 30, 0x0B}, + {1920, 1080, 15, 0x10}, + {3840, 2160, 30, 0x0B}, + {3840, 2160, 20, 0x10}, +}; + +static int os08a20_probe(struct i2c_client *adapter, + const struct i2c_device_id *device_id); +static int os08a20_remove(struct i2c_client *client); + +static void os08a20_stop(struct os08a20 *sensor); + +static const struct i2c_device_id os08a20_id[] = { + {"ov2775", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, os08a20_id); + +static int __maybe_unused os08a20_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct os08a20 *sensor = client_to_os08a20(client); + + if (sensor->on) { + os08a20_stop(sensor); + } + + return 0; +} + +static int __maybe_unused os08a20_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct os08a20 *sensor = client_to_os08a20(client); + + if (sensor->on) { + os08a20_write_reg(sensor, 0x0100, 0x01); + } + return 0; +} + + +static const struct dev_pm_ops os08a20_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(os08a20_suspend, os08a20_resume) +}; +static const struct of_device_id os08a20_dt_ids[] = { + { .compatible = "ovti,ov2775" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, os08a20_dt_ids); + +static struct i2c_driver os08a20_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov2775", + .pm = &os08a20_pm_ops, + .of_match_table = os08a20_dt_ids, + }, + .probe = os08a20_probe, + .remove = os08a20_remove, + .id_table = os08a20_id, +}; + +#if 0 +static const struct os08a20_datafmt os08a20_colour_fmts[] = { + {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG}, + {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG}, +}; +#else +static const struct os08a20_datafmt os08a20_colour_fmts[] = { + {MEDIA_BUS_FMT_SBGGR12_1X12, V4L2_COLORSPACE_JPEG}, +}; +#endif + +#if 0 +static enum os08a20_frame_rate to_os08a20_frame_rate(struct v4l2_fract + *timeperframe) +{ + enum os08a20_frame_rate rate; + u32 tgt_fps; /* target frames per secound */ + + pr_info("enter %s\n", __func__); + tgt_fps = timeperframe->denominator / timeperframe->numerator; + + if (tgt_fps == 30) + rate = os08a20_30_fps; + else if (tgt_fps == 15) + rate = os08a20_15_fps; + else + rate = -EINVAL; + + return rate; +} +#endif + +static __u16 find_hs_configure(struct os08a20 *sensor) +{ + struct device *dev = &sensor->i2c_client->dev; + struct v4l2_fract *timeperframe = &sensor->streamcap.timeperframe; + struct v4l2_pix_format *pix = &sensor->pix; + u32 frame_rate = timeperframe->denominator / timeperframe->numerator; + int i; + + pr_info("enter %s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(hs_setting); i++) { + if (hs_setting[i].width == pix->width && + hs_setting[i].height == pix->height && + hs_setting[i].frame_rate == frame_rate) + return hs_setting[i].val; + } + + if (i == ARRAY_SIZE(hs_setting)) + dev_err(dev, "%s can not find hs configure\n", __func__); + + return -EINVAL; +} + +/* Find a data format by a pixel code in an array */ +static const struct os08a20_datafmt +*os08a20_find_datafmt(u32 code) +{ + int i; + + pr_debug("enter %s\n", __func__); + for (i = 0; i < ARRAY_SIZE(os08a20_colour_fmts); i++) + if (os08a20_colour_fmts[i].code == code) + return os08a20_colour_fmts + i; + + return NULL; +} + +static inline void os08a20_power_up(struct os08a20 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (gpio_is_valid(sensor->pwn_gpio)) { + gpio_set_value_cansleep(sensor->pwn_gpio, 1); + } +} + +static inline void os08a20_power_down(struct os08a20 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (gpio_is_valid(sensor->pwn_gpio)) { + gpio_set_value_cansleep(sensor->pwn_gpio, 0); + } +} + +static inline void os08a20_reset(struct os08a20 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (!gpio_is_valid(sensor->rst_gpio)) + return; + + gpio_set_value_cansleep(sensor->rst_gpio, 0); + msleep(20); + + gpio_set_value_cansleep(sensor->rst_gpio, 1); + msleep(20); +} + +static int os08a20_regulator_enable(struct os08a20 *sensor) +{ + int ret = 0; + struct device *dev = &(sensor->i2c_client->dev); + + pr_debug("enter %s\n", __func__); + if (sensor->io_regulator) + { + regulator_set_voltage(sensor->io_regulator, + OS08a20_VOLTAGE_DIGITAL_IO, + OS08a20_VOLTAGE_DIGITAL_IO); + ret = regulator_enable(sensor->io_regulator); + if (ret) + { + dev_err(dev, "set io voltage failed\n"); + return ret; + } + } + + if (sensor->analog_regulator) + { + regulator_set_voltage(sensor->analog_regulator, + OS08a20_VOLTAGE_ANALOG, + OS08a20_VOLTAGE_ANALOG); + ret = regulator_enable(sensor->analog_regulator); + if (ret) + { + dev_err(dev, "set analog voltage failed\n"); + goto err_disable_io; + } + } + + if (sensor->core_regulator) + { + regulator_set_voltage(sensor->core_regulator, + OS08a20_VOLTAGE_DIGITAL_CORE, + OS08a20_VOLTAGE_DIGITAL_CORE); + ret = regulator_enable(sensor->core_regulator); + if (ret) { + dev_err(dev, "set core voltage failed\n"); + goto err_disable_analog; + } + } + + return 0; + +err_disable_analog: + regulator_disable(sensor->analog_regulator); +err_disable_io: + regulator_disable(sensor->io_regulator); + return ret; +} + +static void os08a20_regulator_disable(struct os08a20 *sensor) +{ + int ret = 0; + struct device *dev = &(sensor->i2c_client->dev); + + if (sensor->core_regulator) + { + ret = regulator_disable(sensor->core_regulator); + if (ret < 0) + dev_err(dev, "core regulator disable failed\n"); + } + + if (sensor->analog_regulator) + { + ret = regulator_disable(sensor->analog_regulator); + if (ret < 0) + dev_err(dev, "analog regulator disable failed\n"); + } + + if (sensor->io_regulator) + { + ret = regulator_disable(sensor->io_regulator); + if (ret < 0) + dev_err(dev, "io regulator disable failed\n"); + } + return ; +} + + +s32 os08a20_write_reg(struct os08a20 *sensor, u16 reg, u8 val) +{ + u8 au8Buf[3] = { 0 }; + + au8Buf[0] = reg >> 8; + au8Buf[1] = reg & 0xff; + au8Buf[2] = val; + if (i2c_master_send(sensor->i2c_client, au8Buf, 3) < 0) { + pr_err("Write reg error: reg=%x, val=%x\n", reg, val); + return -1; + } + + return 0; +} + +s32 os08a20_read_reg(struct os08a20 *sensor, u16 reg, u8 *val) +{ + struct device *dev = &sensor->i2c_client->dev; + u8 au8RegBuf[2] = { 0 }; + u8 u8RdVal = 0; + + au8RegBuf[0] = reg >> 8; + au8RegBuf[1] = reg & 0xff; + + if (i2c_master_send(sensor->i2c_client, au8RegBuf, 2) != 2) { + dev_err(dev, "Read reg error: reg=%x\n", reg); + return -1; + } + + if (i2c_master_recv(sensor->i2c_client, &u8RdVal, 1) != 1) { + dev_err(dev, "Read reg error: reg=%x, val=%x\n", reg, u8RdVal); + return -1; + } + + *val = u8RdVal; + return u8RdVal; +} + +static int os08a20_set_clk_rate(struct os08a20 *sensor) +{ + u32 tgt_xclk; /* target xclk */ + int ret; + + /* mclk */ + tgt_xclk = sensor->mclk; + tgt_xclk = min_t(u32, tgt_xclk, (u32) OS08a20_XCLK_MAX); + tgt_xclk = max_t(u32, tgt_xclk, (u32) OS08a20_XCLK_MIN); + sensor->mclk = tgt_xclk; + + pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); + ret = clk_set_rate(sensor->sensor_clk, sensor->mclk); + if (ret < 0) + pr_debug("set rate filed, rate=%d\n", sensor->mclk); + return ret; +} + +/* download os08a20 settings to sensor through i2c */ +static int os08a20_download_firmware(struct os08a20 *sensor, + struct vvsensor_reg_value_t *mode_setting, + s32 size) +{ + register u32 delay_ms = 0; + register u16 reg_addr = 0; + register u8 mask = 0; + register u8 val = 0; + u8 reg_val = 0; + int i, retval = 0; + + pr_err("enter %s\n", __func__); + for (i = 0; i < size; ++i, ++mode_setting) { + delay_ms = mode_setting->delay; + reg_addr = mode_setting->addr; + val = mode_setting->val; + mask = mode_setting->mask; + + if (mask) { + retval = os08a20_read_reg(sensor, reg_addr, ®_val); + if (retval < 0) + break; + + reg_val &= ~(u8)mask; + val &= mask; + val |= reg_val; + } + + retval = os08a20_write_reg(sensor, reg_addr, val); + os08a20_read_reg(sensor, reg_addr, ®_val); + + if (retval < 0) + break; + + if (delay_ms) + msleep(delay_ms); + } + + return retval; +} + +static void os08a20_start(struct os08a20 *sensor) +{ + pr_err("enter %s\n", __func__); + os08a20_write_reg(sensor, 0x0100, 0x01); + msleep(100); +} + +static void os08a20_stop(struct os08a20 *sensor) +{ + pr_err("enter %s\n", __func__); + os08a20_write_reg(sensor, 0x0100, 0x00); +} + +/*! + * os08a20_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl + * @s: pointer to standard V4L2 device structure + * @on: indicates power mode (on or off) + * + * Turns the power on or off, depending on the value of on and returns the + * appropriate error code. + */ +static int os08a20_s_power(struct v4l2_subdev *sd, int on) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + + pr_debug("enter %s\n", __func__); + if (on) + clk_prepare_enable(sensor->sensor_clk); + else + clk_disable_unprepare(sensor->sensor_clk); + + sensor->on = on; + return 0; +} + +/*! + * os08a20_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 sub device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int os08a20_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + pr_debug("enter %s\n", __func__); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ov5460_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 sub device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int os08a20_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; + u32 tgt_fps; /* target frames per secound */ + enum os08a20_mode mode = a->parm.capture.capturemode; + int ret = 0; + + pr_debug("enter %s\n", __func__); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + /* Check that the new frame rate is allowed. */ + if ((timeperframe->numerator == 0) || + (timeperframe->denominator == 0)) { + timeperframe->denominator = DEFAULT_FPS; + timeperframe->numerator = 1; + } + + tgt_fps = timeperframe->denominator / timeperframe->numerator; + + if (tgt_fps > MAX_FPS) { + timeperframe->denominator = MAX_FPS; + timeperframe->numerator = 1; + } else if (tgt_fps < MIN_FPS) { + timeperframe->denominator = MIN_FPS; + timeperframe->numerator = 1; + } + + if (mode > os08a20_mode_MAX || mode < os08a20_mode_MIN) { + pr_err("The camera mode[%d] is not supported!\n", mode); + return -EINVAL; + } + + sensor->streamcap.capturemode = mode; + sensor->streamcap.timeperframe = *timeperframe; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_debug(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +static int os08a20_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + + pr_debug("enter %s\n", __func__); + if (enable) + os08a20_start(sensor); + else + os08a20_stop(sensor); + + sensor->on = enable; + return 0; +} + +#if 0 +static struct os08a20_mode_info *get_max_resolution(enum os08a20_frame_rate rate) +{ + u32 max_width; + enum os08a20_mode mode; + int i; + + pr_debug("enter %s\n", __func__); + mode = 0; + max_width = os08a20_mode_info_data[rate][0].width; + + for (i = 0; i < (os08a20_mode_MAX + 1); i++) { + if (os08a20_mode_info_data[rate][i].width > max_width) { + max_width = os08a20_mode_info_data[rate][i].width; + mode = i; + } + } + return &os08a20_mode_info_data[rate][mode]; +} + +static struct os08a20_mode_info *match(struct v4l2_mbus_framefmt *fmt, + enum os08a20_frame_rate rate) +{ + struct os08a20_mode_info *info; + int i; + + pr_debug("enter %s\n", __func__); + for (i = 0; i < (os08a20_mode_MAX + 1); i++) { + if (fmt->width == os08a20_mode_info_data[rate][i].width && + fmt->height == os08a20_mode_info_data[rate][i].height) { + info = &os08a20_mode_info_data[rate][i]; + break; + } + } + if (i == os08a20_mode_MAX + 1) + info = NULL; + + return info; +} + +static void try_to_find_resolution(struct os08a20 *sensor, + struct v4l2_mbus_framefmt *mf) +{ + enum os08a20_mode mode = sensor->streamcap.capturemode; + struct v4l2_fract *timeperframe = &sensor->streamcap.timeperframe; + enum os08a20_frame_rate frame_rate = to_os08a20_frame_rate(timeperframe); + struct device *dev = &sensor->i2c_client->dev; + struct os08a20_mode_info *info; + bool found = false; + + pr_debug("enter %s\n", __func__); + if ((mf->width == os08a20_mode_info_data[frame_rate][mode].width) && + (mf->height == os08a20_mode_info_data[frame_rate][mode].height)) { + info = &os08a20_mode_info_data[frame_rate][mode]; + found = true; + } else { + /* get mode info according to frame user's width and height */ + info = match(mf, frame_rate); + if (info == NULL) { + frame_rate ^= 0x1; + info = match(mf, frame_rate); + if (info) { + sensor->streamcap.capturemode = -1; + dev_err(dev, "%s %dx%d only support %s(fps)\n", + __func__, info->width, info->height, + (frame_rate == 0) ? "15fps" : "30fps"); + return; + } + goto max_resolution; + } + found = true; + } + + /* get max resolution to resize */ +max_resolution: + if (!found) { + frame_rate ^= 0x1; + info = get_max_resolution(frame_rate); + } + + sensor->streamcap.capturemode = info->mode; + sensor->streamcap.timeperframe.denominator = (frame_rate) ? 30 : 15; + sensor->pix.width = info->width; + sensor->pix.height = info->height; +} +#endif + +static int os08a20_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *mf = &format->format; + const struct os08a20_datafmt *fmt = os08a20_find_datafmt(mf->code); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + unsigned int i; + struct vvsensor_reg_value_t *mode_setting = NULL; + int array_size = 0; + + pr_debug("enter %s\n", __func__); + if (format->pad) { + return -EINVAL; + } + + if (!fmt) { + mf->code = os08a20_colour_fmts[0].code; + mf->colorspace = os08a20_colour_fmts[0].colorspace; + } + + mf->field = V4L2_FIELD_NONE; + /* old search method, vsi need change to + search resolution by width/height */ + /* try_to_find_resolution(sensor, mf); */ + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + return 0; + + for (i=0; ihdr) + { + if (mf->width == pos08a20_mode_info[i].width && + mf->height == pos08a20_mode_info[i].height && + pos08a20_mode_info[i].hdr_mode != SENSOR_MODE_LINEAR) + { + memcpy(&(sensor->cur_mode), &pos08a20_mode_info[i], sizeof(struct vvcam_mode_info)); + mode_setting = pos08a20_mode_info[i].preg_data; + array_size = pos08a20_mode_info[i].reg_data_count; + return os08a20_download_firmware(sensor, mode_setting, array_size); + } + }else + { + if (mf->width == pos08a20_mode_info[i].width && + mf->height == pos08a20_mode_info[i].height && + pos08a20_mode_info[i].hdr_mode == SENSOR_MODE_LINEAR) + { + memcpy(&(sensor->cur_mode), &pos08a20_mode_info[i], sizeof(struct vvcam_mode_info)); + mode_setting = pos08a20_mode_info[i].preg_data; + array_size = pos08a20_mode_info[i].reg_data_count; + return os08a20_download_firmware(sensor, mode_setting, array_size); + } + } + } + + pr_err("%s search error: %d %d\n", __func__, mf->width, mf->height); + return -EINVAL;; +} + +static int os08a20_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *mf = &format->format; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + + pr_debug("enter %s\n", __func__); + if (format->pad) + return -EINVAL; + + memset(mf, 0, sizeof(struct v4l2_mbus_framefmt)); + + mf->code = os08a20_colour_fmts[0].code; + mf->colorspace = os08a20_colour_fmts[0].colorspace; + mf->width = sensor->pix.width; + mf->height = sensor->pix.height; + mf->field = V4L2_FIELD_NONE; + mf->reserved[1] = find_hs_configure(sensor); + + dev_dbg(&client->dev, + "%s code=0x%x, w/h=(%d,%d), colorspace=%d, field=%d\n", + __func__, mf->code, mf->width, mf->height, mf->colorspace, + mf->field); + + return 0; +} + +static int os08a20_enum_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + pr_debug("enter %s\n", __func__); + if (code->pad || code->index >= ARRAY_SIZE(os08a20_colour_fmts)) + return -EINVAL; + + code->code = os08a20_colour_fmts[code->index].code; + return 0; +} + +/*! + * os08a20_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int os08a20_enum_framesizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + pr_debug("enter %s\n", __func__); + if (fse->index > ARRAY_SIZE(pos08a20_mode_info)) + return -EINVAL; + + fse->min_width = pos08a20_mode_info[fse->index].width; + fse->max_width = fse->min_width; + fse->min_height = pos08a20_mode_info[fse->index].height; + fse->max_height = fse->min_height; + + return 0; +} + +/*! + * os08a20_enum_frameintervals - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMEINTERVALS ioctl + * @s: pointer to standard V4L2 device structure + * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int os08a20_enum_frameintervals(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum + *fie) +{ + + pr_debug("enter %s\n", __func__); + if (fie->index < 0 || fie->index > os08a20_mode_MAX) + return -EINVAL; + + if (fie->width == 0 || fie->height == 0 || fie->code == 0) { + pr_warn("Please assign pixel format, width and height.\n"); + return -EINVAL; + } + + fie->interval.numerator = 1; + fie->interval.denominator = pos08a20_mode_info[fie->index].fps; + + return 0; +} + +static int os08a20_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static struct v4l2_subdev_video_ops os08a20_subdev_video_ops = { + .g_parm = os08a20_g_parm, + .s_parm = os08a20_s_parm, + .s_stream = os08a20_s_stream, +}; + +static const struct v4l2_subdev_pad_ops os08a20_subdev_pad_ops = { + .enum_frame_size = os08a20_enum_framesizes, + .enum_frame_interval = os08a20_enum_frameintervals, + .enum_mbus_code = os08a20_enum_code, + .set_fmt = os08a20_set_fmt, + .get_fmt = os08a20_get_fmt, +}; + +static struct v4l2_subdev_core_ops os08a20_subdev_core_ops = { + .s_power = os08a20_s_power, + .ioctl = os08a20_priv_ioctl, +}; + +static struct v4l2_subdev_ops os08a20_subdev_ops = { + .core = &os08a20_subdev_core_ops, + .video = &os08a20_subdev_video_ops, + .pad = &os08a20_subdev_pad_ops, +}; + +static const struct media_entity_operations os08a20_sd_media_ops = { + .link_setup = os08a20_link_setup, +}; + +/*! + * os08a20 I2C probe function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ + +static int os08a20_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct pinctrl *pinctrl; + struct device *dev = &client->dev; + struct v4l2_subdev *sd; + int retval; + u8 reg_val = 0; + u16 chip_id = 0; + struct os08a20 *sensor; + + pr_debug("enter %s\n", __func__); + sensor = devm_kmalloc(dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + /* Set initial values for the sensor struct. */ + memset(sensor, 0, sizeof(*sensor)); + sensor->i2c_client = client; + + /* os08a20 pinctrl */ + pinctrl = devm_pinctrl_get_select_default(dev); + if (IS_ERR(pinctrl)) { + dev_err(dev, "setup pinctrl failed\n"); + return PTR_ERR(pinctrl); + } + + /* request power down pin */ + sensor->pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); + if (!gpio_is_valid(sensor->pwn_gpio)) + dev_warn(dev, "No sensor pwdn pin available"); + else { + retval = devm_gpio_request_one(dev, sensor->pwn_gpio, + GPIOF_OUT_INIT_HIGH, + "os08a20_mipi_pwdn"); + if (retval < 0) { + dev_warn(dev, "Failed to set power pin\n"); + dev_warn(dev, "retval=%d\n", retval); + return retval; + } + } + + /* request reset pin */ + sensor->rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); + if (!gpio_is_valid(sensor->rst_gpio)) + dev_warn(dev, "No sensor reset pin available"); + else { + retval = devm_gpio_request_one(dev, sensor->rst_gpio, + GPIOF_OUT_INIT_HIGH, + "os08a20_mipi_reset"); + if (retval < 0) { + dev_warn(dev, "Failed to set reset pin\n"); + return retval; + } + } + + /* Set initial values for the sensor struct. */ + sensor->sensor_clk = devm_clk_get(dev, "csi_mclk"); + if (IS_ERR(sensor->sensor_clk)) { + /* assuming clock enabled by default */ + sensor->sensor_clk = NULL; + dev_err(dev, "clock-frequency missing or invalid\n"); + return PTR_ERR(sensor->sensor_clk); + } + + retval = of_property_read_u32(dev->of_node, "mclk", &(sensor->mclk)); + if (retval) { + dev_err(dev, "mclk missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "mclk_source", + (u32 *)&(sensor->mclk_source)); + if (retval) { + dev_err(dev, "mclk_source missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "csi_id", &(sensor->csi)); + if (retval) { + dev_err(dev, "csi id missing or invalid\n"); + return retval; + } + sensor->io_regulator = devm_regulator_get(dev, "DOVDD"); + if (IS_ERR(sensor->io_regulator)) + { + dev_err(dev, "cannot get io regulator\n"); + return PTR_ERR(sensor->io_regulator); + } + + sensor->core_regulator = devm_regulator_get(dev, "DVDD"); + if (IS_ERR(sensor->core_regulator)) + { + dev_err(dev, "cannot get core regulator\n"); + return PTR_ERR(sensor->core_regulator); + } + + sensor->analog_regulator = devm_regulator_get(dev, "AVDD"); + if (IS_ERR(sensor->analog_regulator)) + { + dev_err(dev, "cannot get analog regulator\n"); + return PTR_ERR(sensor->analog_regulator); + } + + retval = os08a20_regulator_enable(sensor); + if (retval) { + dev_err(dev, "regulator enable failed\n"); + return retval; + } + + /* Set mclk rate before clk on */ + os08a20_set_clk_rate(sensor); + + retval = clk_prepare_enable(sensor->sensor_clk); + if (retval < 0) { + dev_err(dev, "%s: enable sensor clk fail\n", __func__); + goto probe_err_regulator_disable; + } + os08a20_power_up(sensor); + os08a20_reset(sensor); + + sensor->io_init = os08a20_reset; + + sensor->pix.pixelformat = V4L2_PIX_FMT_UYVY; + sensor->pix.width =pos08a20_mode_info[0].width; + sensor->pix.height = pos08a20_mode_info[0].height; + sensor->streamcap.capability = V4L2_MODE_HIGHQUALITY | + V4L2_CAP_TIMEPERFRAME; + sensor->streamcap.capturemode = 0; + sensor->streamcap.timeperframe.denominator = pos08a20_mode_info[0].fps; + sensor->streamcap.timeperframe.numerator = 1; + + chip_id = 0; + os08a20_read_reg(sensor, OS08a20_CHIP_ID_HIGH_BYTE,®_val); + chip_id |= reg_val << 8; + os08a20_read_reg(sensor, OS08a20_CHIP_ID_LOW_BYTE, ®_val); + chip_id |= reg_val; + if (chip_id != 0x5308) { + pr_warn("camera os08a20 is not found\n"); + goto probe_err_power_down; + } + + sd = &sensor->subdev; + v4l2_i2c_subdev_init(sd, client, &os08a20_subdev_ops); + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + sensor->pads[OS08a20_SENS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + + retval = media_entity_pads_init(&sd->entity, OS08a20_SENS_PADS_NUM, + sensor->pads); + sd->entity.ops = &os08a20_sd_media_ops; + if (retval < 0) + goto probe_err_power_down; + + retval = v4l2_async_register_subdev_sensor_common(sd); + if (retval < 0) { + dev_err(&client->dev,"%s--Async register failed, ret=%d\n", __func__,retval); + goto probe_err_entity_cleanup; + } + mutex_init(&sensor->lock); + + pr_info("%s camera mipi os08a20, is found\n", __func__); + return 0; + +probe_err_entity_cleanup: + media_entity_cleanup(&sd->entity); +probe_err_power_down: + os08a20_power_down(sensor); + clk_disable_unprepare(sensor->sensor_clk); +probe_err_regulator_disable: + os08a20_regulator_disable(sensor); + return retval; +} + +/*! + * os08a20 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int os08a20_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct os08a20 *sensor = client_to_os08a20(client); + + pr_info("enter %s\n", __func__); + + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + os08a20_power_down(sensor); + clk_disable_unprepare(sensor->sensor_clk); + os08a20_regulator_disable(sensor); + mutex_destroy(&sensor->lock); + + return 0; +} + +module_i2c_driver(os08a20_i2c_driver); +MODULE_DESCRIPTION("OS08a20 MIPI Camera Subdev Driver"); +MODULE_LICENSE("GPL"); + +int sensor_calc_gain(__u32 total_gain, __u32 *pagain, __u32 *pdgain) +{ + if (total_gain < 1024) + { + total_gain = 1024; + } + + if(total_gain < (0x7c0 << 3)) + { + *pdgain = 0x400; + *pagain = (total_gain << 7) / *pdgain;//(128 * 1024)/1024 = 128 + + }else + { + *pagain = 0x7c0; + *pdgain = (total_gain << 7) / 0x7c0; + } + return 0; +} + +int os08a20_s_long_gain(struct os08a20 *sensor, __u32 new_gain) +{ + __u32 again = 0; + __u32 dgain = 0; + int ret = 0; + + sensor_calc_gain(new_gain, &again, &dgain); + + ret |= os08a20_write_reg(sensor, 0x3508, (again >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x3509, again & 0xff); + + ret |= os08a20_write_reg(sensor, 0x350a, (dgain >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x350b, dgain & 0x00FF); + + return ret; +} + +int os08a20_s_short_gain(struct os08a20 *sensor, __u32 new_gain) +{ + __u32 again = 0; + __u32 dgain = 0; + int ret = 0; + + sensor_calc_gain(new_gain, &again, &dgain); + + ret |= os08a20_write_reg(sensor, 0x350c, (again >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x350d, again & 0xff); + + ret |= os08a20_write_reg(sensor, 0x350e, (dgain >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x350f, dgain & 0x00FF); + + return ret; +} + +int os08a20_s_long_exp(struct os08a20 *sensor, __u32 exp) +{ + int ret = 0; + ret |= os08a20_write_reg(sensor, 0x3501, (exp >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x3502, exp & 0xff); + + return ret; +} + +int os08a20_s_short_exp(struct os08a20 *sensor, __u32 exp) +{ + int ret = 0; + ret |= os08a20_write_reg(sensor, 0x3511, (exp >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x3512, exp & 0xff); + + return ret; +} + +int os08a20_g_gain(struct os08a20 *sensor, struct vvsensor_gain_context *gain) +{ + return 0; +} + +int os08a20_g_version(struct os08a20 *sensor, __u32 *version) +{ + __u8 val = 0; + + os08a20_read_reg(sensor, 0x300a, &val); + *version = val << 8; + os08a20_read_reg(sensor, 0x300b, &val); + *version |= val; + return 0; +} + + +int os08a20_s_hdr(struct os08a20 *sensor, bool enable) +{ + pr_debug("%s: %d\n", __func__, enable); + sensor->hdr = enable; + return 0; +} + +int os08a20_s_clk(struct os08a20 *sensor, __u32 clk) +{ + pr_debug("%s: %d\n", __func__, clk); + os08a20_write_reg(sensor, 0x3005, clk); + return 0; +} + +int os08a20_g_clk(struct os08a20 *sensor, __u32 *clk) +{ + u8 val; + os08a20_read_reg(sensor, 0x3005, &val); + *clk = val; + return 0; +} + +int os08a20_s_fps(struct os08a20 *sensor, __u32 fps) +{ + u32 vts; + pr_debug("%s: %d\n", __func__, fps); + if (fps < 5) { + fps = 5; + } + if (fps > sensor->cur_mode.fps){ + fps = sensor->cur_mode.fps; + } + sensor->fps = fps; + + vts = sensor->cur_mode.fps * sensor->cur_mode.ae_info.DefaultFrameLengthLines / sensor->fps; + + os08a20_write_reg(sensor, 0x380e, (vts >> 8)&0xff); + os08a20_write_reg(sensor, 0x380f, vts&0xff); + + if (sensor->hdr) + { + sensor->cur_mode.ae_info.cur_fps = sensor->fps; + sensor->cur_mode.ae_info.CurFrameLengthLines = vts; + sensor->cur_mode.ae_info.max_integration_time = vts - 64 - 4; + }else + { + sensor->cur_mode.ae_info.cur_fps = sensor->fps; + sensor->cur_mode.ae_info.CurFrameLengthLines = vts; + sensor->cur_mode.ae_info.max_integration_time = vts - 8; + } + + return 0; +} + +int os08a20_g_fps(struct os08a20 *sensor, __u32 *fps) +{ + *fps = sensor->fps; + return 0; +} + +int os08a20_g_chipid(struct os08a20 *sensor, __u32 *chip_id) +{ + int ret = 0; + __u8 chip_id_high = 0; + __u8 chip_id_low = 0; + ret = os08a20_read_reg(sensor, 0x300a, &chip_id_high); + ret |= os08a20_read_reg(sensor, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + return ret; +} + +int os08a20_ioc_qcap(struct os08a20 *sensor, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "os08a20"); + sprintf((char *)cap->bus_info, "csi%d",sensor->csi); + if(sensor->i2c_client->adapter) + {//bus_info[8]-i2c bus dev number + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = (__u8)sensor->i2c_client->adapter->nr; + } + else + { + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = 0xFF; + } + + return 0; +} + +int os08a20_ioc_query_mode(struct os08a20 *sensor, struct vvcam_mode_info_array *array) +{ + array->count = ARRAY_SIZE(pos08a20_mode_info); +#ifdef CONFIG_HARDENED_USERCOPY + unsigned long copy_ret = 0; + pr_debug("sensor %p\n", sensor); + copy_ret = copy_to_user(&array->modes,pos08a20_mode_info,sizeof(pos08a20_mode_info)); +#else + memcpy(&array->modes,pos08a20_mode_info,sizeof(pos08a20_mode_info)); +#endif + return 0; +} + +int os08a20_g_mode(struct os08a20 *sensor, struct vvcam_mode_info *pmode) +{ + int i = 0; + struct vvcam_mode_info *pcur_mode = NULL; + + if (sensor->cur_mode.index == pmode->index && + sensor->cur_mode.width != 0 && + sensor->cur_mode.height != 0) + { + pcur_mode = &(sensor->cur_mode); + memcpy(pmode,pcur_mode,sizeof(struct vvcam_mode_info)); + return 0; + } + + for(i=0; i < ARRAY_SIZE(pos08a20_mode_info); i++) + { + if (pmode->index == pos08a20_mode_info[i].index) + { + pcur_mode = &pos08a20_mode_info[i]; + break; + } + } + + if (pcur_mode == NULL) + { + return -1; + } + + memcpy(pmode,pcur_mode,sizeof(struct vvcam_mode_info)); + return 0; +} + + +/* +Use USER_TO_KERNEL/KERNEL_TO_USER to fix "uaccess" exception on run time. +Also, use "copy_ret" to fix the build issue as below. +error: ignoring return value of function declared with 'warn_unused_result' attribute. +*/ + +#ifdef CONFIG_HARDENED_USERCOPY +#define USER_TO_KERNEL(TYPE) \ + do {\ + TYPE tmp; \ + unsigned long copy_ret; \ + arg = (void *)(&tmp); \ + copy_ret = copy_from_user(arg, arg_user, sizeof(TYPE));\ + } while (0) + +#define KERNEL_TO_USER(TYPE) \ + do {\ + unsigned long copy_ret; \ + copy_ret = copy_to_user(arg_user, arg, sizeof(TYPE));\ + } while (0) +#else +#define USER_TO_KERNEL(TYPE) +#define KERNEL_TO_USER(TYPE) +#endif + +long os08a20_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg_user) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + struct vvcam_sccb_data reg; + int ret = 0; + void *arg = arg_user; + + /* pr_info("enter %s\n", __func__); */ + mutex_lock(&sensor->lock); + switch (cmd) { + case VVSENSORIOC_WRITE_REG: { + USER_TO_KERNEL(struct vvcam_sccb_data); + reg = *(struct vvcam_sccb_data *)arg; + ret = os08a20_write_reg(sensor, reg.addr, (u8)reg.data) < 0; + break; + } + case VVSENSORIOC_READ_REG: { + struct vvcam_sccb_data *preg; + u8 val; + USER_TO_KERNEL(struct vvcam_sccb_data); + preg = (struct vvcam_sccb_data *)arg; + ret = os08a20_read_reg(sensor, (u16) preg->addr, &val) < 0; + preg->data = val; + KERNEL_TO_USER(struct vvcam_sccb_data); + break; + } + case VVSENSORIOC_S_STREAM: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_stream(sd, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_EXP: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_long_exp(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_VSEXP: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_short_exp(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_GAIN: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_long_gain(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_VSGAIN: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_short_gain(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_FPS: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_fps(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_G_FPS: { + USER_TO_KERNEL(__u32); + ret = os08a20_g_fps(sensor, (__u32 *)arg); + KERNEL_TO_USER(__u32); + break; + } + case VVSENSORIOC_S_CLK: { + USER_TO_KERNEL(__u32); + //ret = os08a20_s_clk(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_G_CLK: { + USER_TO_KERNEL(__u32); + ret = os08a20_g_clk(sensor, (__u32 *)arg); + KERNEL_TO_USER(__u32); + break; + } + case VIDIOC_QUERYCAP: + ret = os08a20_ioc_qcap(sensor, arg); + break; + case VVSENSORIOC_G_CHIP_ID: { + USER_TO_KERNEL(__u32); + ret = os08a20_g_chipid(sensor, (__u32 *)arg); + ret = (ret < 0) ? -1 : 0; + KERNEL_TO_USER(__u32); + break; + } + case VVSENSORIOC_G_RESERVE_ID: { + __u32 correct_id = 0x5308; + ret = copy_to_user(arg_user, &correct_id, sizeof(__u32)); + ret = ret? -1 : 0; + break; + } + case VVSENSORIOC_S_HDR_MODE: { + USER_TO_KERNEL(bool); + ret = os08a20_s_hdr(sensor, *(bool *)arg); + break; + } + case VVSENSORIOC_QUERY: { + //USER_TO_KERNEL(struct vvcam_mode_info_array); + os08a20_ioc_query_mode(sensor, arg); + //KERNEL_TO_USER(struct vvcam_mode_info_array); + break; + } + case VVSENSORIOC_G_SENSOR_MODE: { + USER_TO_KERNEL(struct vvcam_mode_info); + os08a20_g_mode(sensor, arg); + KERNEL_TO_USER(struct vvcam_mode_info); + break; + } + default: + /* pr_err("unsupported os08a20 command %d.", cmd); */ + break; + } + mutex_unlock(&sensor->lock); + + return ret; +} diff --git a/vvcam/v4l2/sensor/os08a20/os08a20_regs_1080p.h b/vvcam/v4l2/sensor/os08a20/os08a20_regs_1080p.h new file mode 100755 index 0000000..4588ba8 --- /dev/null +++ b/vvcam/v4l2/sensor/os08a20/os08a20_regs_1080p.h @@ -0,0 +1,246 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVCAM_OS08a20_REGS_1080P_H_ +#define _VVCAM_OS08a20_REGS_1080P_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t os08a20_init_setting_1080p[] = { + {0x0100, 0x00, 0, 0}, + {0x0103, 0x01, 0, 0}, + {0x0303, 0x01, 0, 0}, + {0x0305, 0x32, 0, 0}, + {0x0306, 0x00, 0, 0}, + {0x0308, 0x03, 0, 0}, + {0x0309, 0x04, 0, 0}, + {0x032a, 0x00, 0, 0}, + {0x300f, 0x11, 0, 0}, + {0x3010, 0x01, 0, 0}, + {0x3011, 0x04, 0, 0}, + {0x3012, 0x41, 0, 0}, + {0x3016, 0xf0, 0, 0}, + {0x301e, 0x98, 0, 0}, + {0x3031, 0xa9, 0, 0}, + {0x3103, 0x92, 0, 0}, + {0x3104, 0x01, 0, 0}, + {0x3106, 0x10, 0, 0}, + {0x3400, 0x04, 0, 0}, + {0x3025, 0x03, 0, 0}, + {0x3425, 0x01, 0, 0}, + {0x3428, 0x01, 0, 0}, + {0x3406, 0x08, 0, 0}, + {0x3408, 0x03, 0, 0}, + {0x340c, 0xff, 0, 0}, + {0x340d, 0xff, 0, 0}, + {0x031e, 0x09, 0, 0}, + {0x3501, 0x04, 0, 0}, + {0x3502, 0x62, 0, 0}, + {0x3505, 0x83, 0, 0}, + {0x3508, 0x00, 0, 0}, + {0x3509, 0x80, 0, 0}, + {0x350a, 0x04, 0, 0}, + {0x350b, 0x00, 0, 0}, + {0x350c, 0x00, 0, 0}, + {0x350d, 0x80, 0, 0}, + {0x350e, 0x04, 0, 0}, + {0x350f, 0x00, 0, 0}, + {0x3600, 0x09, 0, 0}, + {0x3603, 0x2c, 0, 0}, + {0x3605, 0x50, 0, 0}, + {0x3609, 0xb5, 0, 0}, + {0x3610, 0x39, 0, 0}, + {0x360c, 0x01, 0, 0}, + {0x3628, 0xa4, 0, 0}, + {0x362d, 0x10, 0, 0}, + {0x3660, 0x43, 0, 0}, + {0x3661, 0x06, 0, 0}, + {0x3662, 0x00, 0, 0}, + {0x3663, 0x28, 0, 0}, + {0x3664, 0x0d, 0, 0}, + {0x366a, 0x38, 0, 0}, + {0x366b, 0xa0, 0, 0}, + {0x366d, 0x00, 0, 0}, + {0x366e, 0x00, 0, 0}, + {0x3680, 0x00, 0, 0}, + {0x36c0, 0x00, 0, 0}, + {0x3701, 0x02, 0, 0}, + {0x373b, 0x02, 0, 0}, + {0x373c, 0x02, 0, 0}, + {0x3736, 0x02, 0, 0}, + {0x3737, 0x02, 0, 0}, + {0x3705, 0x00, 0, 0}, + {0x3706, 0x39, 0, 0}, + {0x370a, 0x00, 0, 0}, + {0x370b, 0x98, 0, 0}, + {0x3709, 0x49, 0, 0}, + {0x3714, 0x22, 0, 0}, + {0x371c, 0x00, 0, 0}, + {0x371d, 0x08, 0, 0}, + {0x3740, 0x1b, 0, 0}, + {0x3741, 0x04, 0, 0}, + {0x375e, 0x0b, 0, 0}, + {0x3760, 0x10, 0, 0}, + {0x3776, 0x10, 0, 0}, + {0x3781, 0x02, 0, 0}, + {0x3782, 0x04, 0, 0}, + {0x3783, 0x02, 0, 0}, + {0x3784, 0x08, 0, 0}, + {0x3785, 0x08, 0, 0}, + {0x3788, 0x01, 0, 0}, + {0x3789, 0x01, 0, 0}, + {0x3797, 0x04, 0, 0}, + {0x3762, 0x11, 0, 0}, + {0x3800, 0x00, 0, 0}, + {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, + {0x3803, 0x0c, 0, 0}, + {0x3804, 0x0e, 0, 0}, + {0x3805, 0xff, 0, 0}, + {0x3806, 0x08, 0, 0}, + {0x3807, 0x6f, 0, 0}, + {0x3808, 0x07, 0, 0}, + {0x3809, 0x80, 0, 0}, + {0x380a, 0x04, 0, 0}, + {0x380b, 0x38, 0, 0}, + {0x380c, 0x08, 0, 0}, + {0x380d, 0x04, 0, 0}, + {0x380e, 0x04, 0, 0}, + {0x380f, 0x92, 0, 0}, + {0x3813, 0x08, 0, 0}, + {0x3814, 0x03, 0, 0}, + {0x3815, 0x01, 0, 0}, + {0x3816, 0x03, 0, 0}, + {0x3817, 0x01, 0, 0}, + {0x381c, 0x00, 0, 0}, + {0x3820, 0x05, 0, 0}, + {0x3821, 0x01, 0, 0}, + {0x3823, 0x08, 0, 0}, + {0x3826, 0x00, 0, 0}, + {0x3827, 0x08, 0, 0}, + {0x382d, 0x08, 0, 0}, + {0x3832, 0x02, 0, 0}, + {0x3833, 0x00, 0, 0}, + {0x383c, 0x48, 0, 0}, + {0x383d, 0xff, 0, 0}, + {0x3d85, 0x0b, 0, 0}, + {0x3d84, 0x40, 0, 0}, + {0x3d8c, 0x63, 0, 0}, + {0x3d8d, 0xd7, 0, 0}, + {0x4000, 0xf8, 0, 0}, + {0x4001, 0x2b, 0, 0}, + {0x4004, 0x00, 0, 0}, + {0x4005, 0x40, 0, 0}, + {0x400a, 0x01, 0, 0}, + {0x400f, 0xa0, 0, 0}, + {0x4010, 0x12, 0, 0}, + {0x4018, 0x00, 0, 0}, + {0x4008, 0x02, 0, 0}, + {0x4009, 0x05, 0, 0}, + {0x401a, 0x58, 0, 0}, + {0x4050, 0x00, 0, 0}, + {0x4051, 0x01, 0, 0}, + {0x4028, 0x2f, 0, 0}, + {0x4052, 0x00, 0, 0}, + {0x4053, 0x80, 0, 0}, + {0x4054, 0x00, 0, 0}, + {0x4055, 0x80, 0, 0}, + {0x4056, 0x00, 0, 0}, + {0x4057, 0x80, 0, 0}, + {0x4058, 0x00, 0, 0}, + {0x4059, 0x80, 0, 0}, + {0x430b, 0xff, 0, 0}, + {0x430c, 0xff, 0, 0}, + {0x430d, 0x00, 0, 0}, + {0x430e, 0x00, 0, 0}, + {0x4501, 0x98, 0, 0}, + {0x4502, 0x00, 0, 0}, + {0x4643, 0x00, 0, 0}, + {0x4640, 0x01, 0, 0}, + {0x4641, 0x04, 0, 0}, + {0x4800, 0x64, 0, 0}, + {0x4809, 0x2b, 0, 0}, + {0x4813, 0x90, 0, 0}, + {0x4817, 0x04, 0, 0}, + {0x4833, 0x18, 0, 0}, + {0x4837, 0x14, 0, 0}, + {0x483b, 0x00, 0, 0}, + {0x484b, 0x03, 0, 0}, + {0x4850, 0x7c, 0, 0}, + {0x4852, 0x06, 0, 0}, + {0x4856, 0x58, 0, 0}, + {0x4857, 0xaa, 0, 0}, + {0x4862, 0x0a, 0, 0}, + {0x4869, 0x18, 0, 0}, + {0x486a, 0xaa, 0, 0}, + {0x486e, 0x03, 0, 0}, + {0x486f, 0x55, 0, 0}, + {0x4875, 0xf0, 0, 0}, + {0x5000, 0x89, 0, 0}, + {0x5001, 0x42, 0, 0}, + {0x5004, 0x40, 0, 0}, + {0x5005, 0x00, 0, 0}, + {0x5180, 0x00, 0, 0}, + {0x5181, 0x10, 0, 0}, + {0x580b, 0x03, 0, 0}, + {0x4d00, 0x03, 0, 0}, + {0x4d01, 0xc9, 0, 0}, + {0x4d02, 0xbc, 0, 0}, + {0x4d03, 0xc6, 0, 0}, + {0x4d04, 0x4a, 0, 0}, + {0x4d05, 0x25, 0, 0}, + {0x4700, 0x2b, 0, 0}, + {0x4e00, 0x2b, 0, 0}, + }; + +#endif diff --git a/vvcam/v4l2/sensor/os08a20/os08a20_regs_1080p_hdr.h b/vvcam/v4l2/sensor/os08a20/os08a20_regs_1080p_hdr.h new file mode 100755 index 0000000..796f9e2 --- /dev/null +++ b/vvcam/v4l2/sensor/os08a20/os08a20_regs_1080p_hdr.h @@ -0,0 +1,248 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OS08a20_REGS_1080PHDR_H_ +#define _VVCAM_OS08a20_REGS_1080PHDR_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t os08a20_init_setting_1080p_hdr[] = { + {0x0100, 0x00, 0, 0}, + {0x0103, 0x01, 0, 0}, + {0x0303, 0x01, 0, 0}, + {0x0305, 0x32, 0, 0}, + {0x0306, 0x00, 0, 0}, + {0x0308, 0x03, 0, 0}, + {0x0309, 0x04, 0, 0}, + {0x032a, 0x00, 0, 0}, + {0x300f, 0x11, 0, 0}, + {0x3010, 0x01, 0, 0}, + {0x3011, 0x04, 0, 0}, + {0x3012, 0x41, 0, 0}, + {0x3016, 0xf0, 0, 0}, + {0x301e, 0x98, 0, 0}, + {0x3031, 0xa9, 0, 0}, + {0x3103, 0x92, 0, 0}, + {0x3104, 0x01, 0, 0}, + {0x3106, 0x10, 0, 0}, + {0x340c, 0xff, 0, 0}, + {0x340d, 0xff, 0, 0}, + {0x031e, 0x09, 0, 0}, + {0x3501, 0x04, 0, 0}, + {0x3502, 0x62, 0, 0}, + {0x3505, 0x83, 0, 0}, + {0x3508, 0x00, 0, 0}, + {0x3509, 0x80, 0, 0}, + {0x350a, 0x04, 0, 0}, + {0x350b, 0x00, 0, 0}, + {0x350c, 0x00, 0, 0}, + {0x350d, 0x80, 0, 0}, + {0x3511, 0x04, 0, 0}, + {0x3512, 0x64, 0, 0}, + {0x350e, 0x04, 0, 0}, + {0x350f, 0x00, 0, 0}, + {0x3600, 0x09, 0, 0}, + {0x3603, 0x2c, 0, 0}, + {0x3605, 0x50, 0, 0}, + {0x3609, 0xb5, 0, 0}, + {0x3610, 0x39, 0, 0}, + {0x360c, 0x01, 0, 0}, + {0x3628, 0xa4, 0, 0}, + {0x362d, 0x10, 0, 0}, + {0x3660, 0x42, 0, 0}, + {0x3661, 0x07, 0, 0}, + {0x3662, 0x00, 0, 0}, + {0x3663, 0x28, 0, 0}, + {0x3664, 0x0d, 0, 0}, + {0x366a, 0x38, 0, 0}, + {0x366b, 0xa0, 0, 0}, + {0x366d, 0x00, 0, 0}, + {0x366e, 0x00, 0, 0}, + {0x3680, 0x00, 0, 0}, + {0x36c0, 0x00, 0, 0}, + {0x3701, 0x02, 0, 0}, + {0x373b, 0x02, 0, 0}, + {0x373c, 0x02, 0, 0}, + {0x3736, 0x02, 0, 0}, + {0x3737, 0x02, 0, 0}, + {0x3705, 0x00, 0, 0}, + {0x3706, 0x39, 0, 0}, + {0x370a, 0x00, 0, 0}, + {0x370b, 0x98, 0, 0}, + {0x3709, 0x49, 0, 0}, + {0x3714, 0x22, 0, 0}, + {0x371c, 0x00, 0, 0}, + {0x371d, 0x08, 0, 0}, + {0x3740, 0x1b, 0, 0}, + {0x3741, 0x04, 0, 0}, + {0x375e, 0x0b, 0, 0}, + {0x3760, 0x10, 0, 0}, + {0x3776, 0x10, 0, 0}, + {0x3781, 0x02, 0, 0}, + {0x3782, 0x04, 0, 0}, + {0x3783, 0x02, 0, 0}, + {0x3784, 0x08, 0, 0}, + {0x3785, 0x08, 0, 0}, + {0x3788, 0x01, 0, 0}, + {0x3789, 0x01, 0, 0}, + {0x3797, 0x04, 0, 0}, + {0x3762, 0x11, 0, 0}, + {0x3800, 0x00, 0, 0}, + {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, + {0x3803, 0x0c, 0, 0}, + {0x3804, 0x0e, 0, 0}, + {0x3805, 0xff, 0, 0}, + {0x3806, 0x08, 0, 0}, + {0x3807, 0x6f, 0, 0}, + {0x3808, 0x07, 0, 0}, + {0x3809, 0x80, 0, 0}, + {0x380a, 0x04, 0, 0}, + {0x380b, 0x38, 0, 0}, + {0x380c, 0x08, 0, 0}, + {0x380d, 0x04, 0, 0}, + {0x380e, 0x04, 0, 0}, + {0x380f, 0x92, 0, 0}, + {0x3813, 0x08, 0, 0}, + {0x3814, 0x03, 0, 0}, + {0x3815, 0x01, 0, 0}, + {0x3816, 0x03, 0, 0}, + {0x3817, 0x01, 0, 0}, + {0x381c, 0x08, 0, 0}, + {0x3820, 0x05, 0, 0}, + {0x3821, 0x21, 0, 0}, + {0x3823, 0x08, 0, 0}, + {0x3826, 0x00, 0, 0}, + {0x3827, 0x08, 0, 0}, + {0x382d, 0x08, 0, 0}, + {0x3832, 0x02, 0, 0}, + {0x3833, 0x01, 0, 0}, + {0x383c, 0x48, 0, 0}, + {0x383d, 0xff, 0, 0}, + {0x3d85, 0x0b, 0, 0}, + {0x3d84, 0x40, 0, 0}, + {0x3d8c, 0x63, 0, 0}, + {0x3d8d, 0xd7, 0, 0}, + {0x4000, 0xf8, 0, 0}, + {0x4001, 0x2b, 0, 0}, + {0x4004, 0x00, 0, 0}, + {0x4005, 0x40, 0, 0}, + {0x400a, 0x01, 0, 0}, + {0x400f, 0xa0, 0, 0}, + {0x4010, 0x12, 0, 0}, + {0x4018, 0x00, 0, 0}, + {0x4008, 0x02, 0, 0}, + {0x4009, 0x05, 0, 0}, + {0x401a, 0x58, 0, 0}, + {0x4050, 0x00, 0, 0}, + {0x4051, 0x01, 0, 0}, + {0x4028, 0x2f, 0, 0}, + {0x4052, 0x00, 0, 0}, + {0x4053, 0x80, 0, 0}, + {0x4054, 0x00, 0, 0}, + {0x4055, 0x80, 0, 0}, + {0x4056, 0x00, 0, 0}, + {0x4057, 0x80, 0, 0}, + {0x4058, 0x00, 0, 0}, + {0x4059, 0x80, 0, 0}, + {0x430b, 0xff, 0, 0}, + {0x430c, 0xff, 0, 0}, + {0x430d, 0x00, 0, 0}, + {0x430e, 0x00, 0, 0}, + {0x4501, 0x98, 0, 0}, + {0x4502, 0x00, 0, 0}, + {0x4643, 0x00, 0, 0}, + {0x4640, 0x01, 0, 0}, + {0x4641, 0x04, 0, 0}, + {0x4800, 0x64, 0, 0}, + {0x4809, 0x2b, 0, 0}, + {0x4813, 0x98, 0, 0}, + {0x4817, 0x04, 0, 0}, + {0x4833, 0x18, 0, 0}, + {0x4837, 0x14, 0, 0}, + {0x483b, 0x00, 0, 0}, + {0x484b, 0x03, 0, 0}, + {0x4850, 0x7c, 0, 0}, + {0x4852, 0x06, 0, 0}, + {0x4856, 0x58, 0, 0}, + {0x4857, 0xaa, 0, 0}, + {0x4862, 0x0a, 0, 0}, + {0x4869, 0x18, 0, 0}, + {0x486a, 0xaa, 0, 0}, + {0x486e, 0x07, 0, 0}, + {0x486f, 0x55, 0, 0}, + {0x4875, 0xf0, 0, 0}, + {0x5000, 0x89, 0, 0}, + {0x5001, 0x42, 0, 0}, + {0x5004, 0x40, 0, 0}, + {0x5005, 0x00, 0, 0}, + {0x5180, 0x00, 0, 0}, + {0x5181, 0x10, 0, 0}, + {0x580b, 0x03, 0, 0}, + {0x4d00, 0x03, 0, 0}, + {0x4d01, 0xc9, 0, 0}, + {0x4d02, 0xbc, 0, 0}, + {0x4d03, 0xc6, 0, 0}, + {0x4d04, 0x4a, 0, 0}, + {0x4d05, 0x25, 0, 0}, + {0x4700, 0x2b, 0, 0}, + {0x4e00, 0x2b, 0, 0}, + {0x3501, 0x04, 0, 0}, + {0x3502, 0x5d, 0, 0}, + {0x3511, 0x00, 0, 0}, + {0x3512, 0x20, 0, 0}, + {0x3833, 0x01, 0, 0}, +}; + +#endif diff --git a/vvcam/v4l2/sensor/os08a20/os08a20_regs_4k.h b/vvcam/v4l2/sensor/os08a20/os08a20_regs_4k.h new file mode 100755 index 0000000..555ea6a --- /dev/null +++ b/vvcam/v4l2/sensor/os08a20/os08a20_regs_4k.h @@ -0,0 +1,255 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OS08a20_REGS_4K_H_ +#define _VVCAM_OS08a20_REGS_4K_H_ + +#include "vvsensor.h" + +/* 4K RAW12 */ +static struct vvsensor_reg_value_t os08a20_init_setting_4k[] = { + {0x0100, 0x00, 0, 0}, + {0x0001, 0xf2, 0, 0}, + {0x0103, 0x01, 0, 0}, + {0x0303, 0x01, 0, 0}, + {0x0305, 0x36, 0, 0}, + {0x0306, 0x00, 0, 0}, + {0x0308, 0x03, 0, 0}, + {0x0309, 0x04, 0, 0}, + {0x032a, 0x00, 0, 0}, + {0x300f, 0x11, 0, 0}, + {0x3010, 0x01, 0, 0}, + {0x3011, 0x04, 0, 0}, + {0x3012, 0x41, 0, 0}, + {0x3016, 0xf0, 0, 0}, + {0x301e, 0x98, 0, 0}, + {0x3031, 0xa9, 0, 0}, + {0x3103, 0x92, 0, 0}, + {0x3104, 0x01, 0, 0}, + {0x3106, 0x10, 0, 0}, + {0x3400, 0x04, 0, 0}, + {0x3025, 0x03, 0, 0}, + {0x3425, 0x01, 0, 0}, + {0x3428, 0x01, 0, 0}, + {0x3406, 0x08, 0, 0}, + {0x3408, 0x03, 0, 0}, + {0x340c, 0xff, 0, 0}, + {0x340d, 0xff, 0, 0}, + {0x031e, 0x0a, 0, 0}, + {0x3501, 0x08, 0, 0}, + {0x3502, 0xe5, 0, 0}, + {0x3505, 0x83, 0, 0}, + {0x3508, 0x00, 0, 0}, + {0x3509, 0x80, 0, 0}, + {0x350a, 0x04, 0, 0}, + {0x350b, 0x00, 0, 0}, + {0x350c, 0x00, 0, 0}, + {0x350d, 0x80, 0, 0}, + {0x350e, 0x04, 0, 0}, + {0x350f, 0x00, 0, 0}, + {0x3600, 0x00, 0, 0}, + {0x3603, 0x2c, 0, 0}, + {0x3605, 0x50, 0, 0}, + {0x3609, 0xdb, 0, 0}, + {0x3610, 0x39, 0, 0}, + {0x360c, 0x01, 0, 0}, + {0x3628, 0xa4, 0, 0}, + {0x362d, 0x10, 0, 0}, + {0x3660, 0xd3, 0, 0}, + {0x3661, 0x06, 0, 0}, + {0x3662, 0x00, 0, 0}, + {0x3663, 0x28, 0, 0}, + {0x3664, 0x0d, 0, 0}, + {0x366a, 0x38, 0, 0}, + {0x366b, 0xa0, 0, 0}, + {0x366d, 0x00, 0, 0}, + {0x366e, 0x00, 0, 0}, + {0x3680, 0x00, 0, 0}, + {0x36c0, 0x00, 0, 0}, + {0x3701, 0x02, 0, 0}, + {0x373b, 0x02, 0, 0}, + {0x373c, 0x02, 0, 0}, + {0x3736, 0x02, 0, 0}, + {0x3737, 0x02, 0, 0}, + {0x3705, 0x00, 0, 0}, + {0x3706, 0x72, 0, 0}, + {0x370a, 0x01, 0, 0}, + {0x370b, 0x30, 0, 0}, + {0x3709, 0x48, 0, 0}, + {0x3714, 0x21, 0, 0}, + {0x371c, 0x00, 0, 0}, + {0x371d, 0x08, 0, 0}, + {0x3740, 0x1b, 0, 0}, + {0x3741, 0x04, 0, 0}, + {0x375e, 0x0b, 0, 0}, + {0x3760, 0x10, 0, 0}, + {0x3776, 0x10, 0, 0}, + {0x3781, 0x02, 0, 0}, + {0x3782, 0x04, 0, 0}, + {0x3783, 0x02, 0, 0}, + {0x3784, 0x08, 0, 0}, + {0x3785, 0x08, 0, 0}, + {0x3788, 0x01, 0, 0}, + {0x3789, 0x01, 0, 0}, + {0x3797, 0x04, 0, 0}, + {0x3762, 0x11, 0, 0}, + {0x3800, 0x00, 0, 0}, + {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, + {0x3803, 0x0c, 0, 0}, + {0x3804, 0x0e, 0, 0}, + {0x3805, 0xff, 0, 0}, + {0x3806, 0x08, 0, 0}, + {0x3807, 0x6f, 0, 0}, + {0x3808, 0x0f, 0, 0}, + {0x3809, 0x00, 0, 0}, + {0x380a, 0x08, 0, 0}, + {0x380b, 0x70, 0, 0}, + {0x380c, 0x08, 0, 0}, /* hts_h */ + {0x380d, 0x04, 0, 0}, /* hts_l */ + {0x380e, 0x0D, 0, 0}, /* vts_h */ + {0x380f, 0xB4, 0, 0}, /* vts_l */ + {0x3813, 0x10, 0, 0}, + {0x3814, 0x01, 0, 0}, + {0x3815, 0x01, 0, 0}, + {0x3816, 0x01, 0, 0}, + {0x3817, 0x01, 0, 0}, + {0x381c, 0x00, 0, 0}, + {0x3820, 0x04, 0, 0}, + {0x3821, 0x00, 0, 0}, + {0x3823, 0x08, 0, 0}, + {0x3826, 0x00, 0, 0}, + {0x3827, 0x08, 0, 0}, + {0x382d, 0x08, 0, 0}, + {0x3832, 0x02, 0, 0}, + {0x3833, 0x00, 0, 0}, + {0x383c, 0x48, 0, 0}, + {0x383d, 0xff, 0, 0}, + {0x3d85, 0x0b, 0, 0}, + {0x3d84, 0x40, 0, 0}, + {0x3d8c, 0x63, 0, 0}, + {0x3d8d, 0xd7, 0, 0}, + {0x4000, 0xf8, 0, 0}, + {0x4001, 0x2b, 0, 0}, + {0x4004, 0x00, 0, 0}, + {0x4005, 0x40, 0, 0}, + {0x400a, 0x01, 0, 0}, + {0x400f, 0xa0, 0, 0}, + {0x4010, 0x12, 0, 0}, + {0x4018, 0x00, 0, 0}, + {0x4008, 0x02, 0, 0}, + {0x4009, 0x0d, 0, 0}, + {0x401a, 0x58, 0, 0}, + {0x4050, 0x00, 0, 0}, + {0x4051, 0x01, 0, 0}, + {0x4028, 0x2f, 0, 0}, + {0x4052, 0x00, 0, 0}, + {0x4053, 0x80, 0, 0}, + {0x4054, 0x00, 0, 0}, + {0x4055, 0x80, 0, 0}, + {0x4056, 0x00, 0, 0}, + {0x4057, 0x80, 0, 0}, + {0x4058, 0x00, 0, 0}, + {0x4059, 0x80, 0, 0}, + {0x430b, 0xff, 0, 0}, + {0x430c, 0xff, 0, 0}, + {0x430d, 0x00, 0, 0}, + {0x430e, 0x00, 0, 0}, + {0x4501, 0x18, 0, 0}, + {0x4502, 0x00, 0, 0}, + {0x4600, 0x00, 0, 0}, + {0x4601, 0x20, 0, 0}, + {0x4603, 0x01, 0, 0}, + {0x4643, 0x00, 0, 0}, + {0x4640, 0x01, 0, 0}, + {0x4641, 0x04, 0, 0}, + {0x4800, 0x64, 0, 0}, + {0x4809, 0x2b, 0, 0}, + {0x4813, 0x90, 0, 0}, + {0x4817, 0x04, 0, 0}, + {0x4833, 0x18, 0, 0}, + {0x4837, 0x12, 0, 0}, + {0x483b, 0x00, 0, 0}, + {0x484b, 0x03, 0, 0}, + {0x4850, 0x7c, 0, 0}, + {0x4852, 0x06, 0, 0}, + {0x4856, 0x58, 0, 0}, + {0x4857, 0xaa, 0, 0}, + {0x4862, 0x0a, 0, 0}, + {0x4869, 0x18, 0, 0}, + {0x486a, 0xaa, 0, 0}, + {0x486e, 0x03, 0, 0}, + {0x486f, 0x55, 0, 0}, + {0x4875, 0xf0, 0, 0}, + {0x5000, 0x89, 0, 0}, + {0x5001, 0x42, 0, 0}, + {0x5004, 0x40, 0, 0}, + {0x5005, 0x00, 0, 0}, + {0x5180, 0x00, 0, 0}, + {0x5181, 0x10, 0, 0}, + {0x580b, 0x03, 0, 0}, + {0x4d00, 0x03, 0, 0}, + {0x4d01, 0xc9, 0, 0}, + {0x4d02, 0xbc, 0, 0}, + {0x4d03, 0xc6, 0, 0}, + {0x4d04, 0x4a, 0, 0}, + {0x4d05, 0x25, 0, 0}, + {0x4700, 0x2b, 0, 0}, + {0x4e00, 0x2b, 0, 0}, + {0x3501, 0x09, 0, 0}, + {0x3502, 0x01, 0, 0}, + {0x0100, 0x01, 0, 0}, +}; + +#endif + diff --git a/vvcam/v4l2/sensor/os08a20/os08a20_regs_4k_hdr.h b/vvcam/v4l2/sensor/os08a20/os08a20_regs_4k_hdr.h new file mode 100755 index 0000000..79073d7 --- /dev/null +++ b/vvcam/v4l2/sensor/os08a20/os08a20_regs_4k_hdr.h @@ -0,0 +1,258 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OS08a20_REGS_4kPHDR_H_ +#define _VVCAM_OS08a20_REGS_4kPHDR_H_ + +#include "vvsensor.h" + +/* 4K HDR RAW10 */ +static struct vvsensor_reg_value_t os08a20_init_setting_4k_hdr[] = { + {0x0100, 0x00, 0, 0}, + {0x0103, 0x01, 0, 0}, + + {0x030c, 0x00, 0, 0}, + {0x0303, 0x01, 0, 0}, + {0x0304, 0x00, 0, 0}, + {0x0305, 0x36, 0, 0}, + {0x0306, 0x00, 0, 0}, + {0x0307, 0x00, 0, 0}, + {0x0308, 0x03, 0, 0}, + {0x0309, 0x04, 0, 0}, + {0x301e, 0x98, 0, 0}, + + {0x032a, 0x00, 0, 0}, + {0x300f, 0x11, 0, 0}, + {0x3010, 0x01, 0, 0}, + {0x3011, 0x04, 0, 0}, + {0x3012, 0x41, 0, 0}, + {0x3016, 0xf0, 0, 0}, + {0x3031, 0xa9, 0, 0}, + {0x3103, 0x92, 0, 0}, + {0x3104, 0x01, 0, 0}, + {0x3106, 0x10, 0, 0}, + {0x340c, 0xff, 0, 0}, + {0x340d, 0xff, 0, 0}, + {0x031e, 0x09, 0, 0}, + {0x3501, 0x08, 0, 0}, + {0x3502, 0xe5, 0, 0}, + {0x3505, 0x83, 0, 0}, + {0x3508, 0x00, 0, 0}, + {0x3509, 0x80, 0, 0}, + {0x350a, 0x04, 0, 0}, + {0x350b, 0x00, 0, 0}, + {0x350c, 0x00, 0, 0}, + {0x350d, 0x80, 0, 0}, + {0x350e, 0x04, 0, 0}, + {0x350f, 0x00, 0, 0}, + {0x3600, 0x00, 0, 0}, + {0x3603, 0x2c, 0, 0}, + {0x3605, 0x50, 0, 0}, + {0x3609, 0xb5, 0, 0}, + {0x3610, 0x39, 0, 0}, + {0x360c, 0x01, 0, 0}, + {0x3628, 0xa4, 0, 0}, + {0x362d, 0x10, 0, 0}, + {0x3660, 0x42, 0, 0}, + {0x3661, 0x07, 0, 0}, + {0x3662, 0x00, 0, 0}, + {0x3663, 0x28, 0, 0}, + {0x3664, 0x0d, 0, 0}, + {0x366a, 0x38, 0, 0}, + {0x366b, 0xa0, 0, 0}, + {0x366d, 0x00, 0, 0}, + {0x366e, 0x00, 0, 0}, + {0x3680, 0x00, 0, 0}, + {0x36c0, 0x00, 0, 0}, + {0x3701, 0x02, 0, 0}, + {0x373b, 0x02, 0, 0}, + {0x373c, 0x02, 0, 0}, + {0x3736, 0x02, 0, 0}, + {0x3737, 0x02, 0, 0}, + {0x3705, 0x00, 0, 0}, + {0x3706, 0x39, 0, 0}, + {0x370a, 0x00, 0, 0}, + {0x370b, 0x98, 0, 0}, + {0x3709, 0x49, 0, 0}, + {0x3714, 0x21, 0, 0}, + {0x371c, 0x00, 0, 0}, + {0x371d, 0x08, 0, 0}, + {0x3740, 0x1b, 0, 0}, + {0x3741, 0x04, 0, 0}, + {0x375e, 0x0b, 0, 0}, + {0x3760, 0x10, 0, 0}, + {0x3776, 0x10, 0, 0}, + {0x3781, 0x02, 0, 0}, + {0x3782, 0x04, 0, 0}, + {0x3783, 0x02, 0, 0}, + {0x3784, 0x08, 0, 0}, + {0x3785, 0x08, 0, 0}, + {0x3788, 0x01, 0, 0}, + {0x3789, 0x01, 0, 0}, + {0x3797, 0x04, 0, 0}, + {0x3762, 0x11, 0, 0}, + {0x3800, 0x00, 0, 0}, + {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, + {0x3803, 0x0c, 0, 0}, + {0x3804, 0x0e, 0, 0}, + {0x3805, 0xff, 0, 0}, + {0x3806, 0x08, 0, 0}, + {0x3807, 0x6f, 0, 0}, + {0x3808, 0x0f, 0, 0}, + {0x3809, 0x00, 0, 0}, + {0x380a, 0x08, 0, 0}, + {0x380b, 0x70, 0, 0}, + {0x380c, 0x07, 0, 0}, + {0x380d, 0xd0, 0, 0}, + {0x380e, 0x09, 0, 0}, + {0x380f, 0x60, 0, 0}, + {0x3813, 0x10, 0, 0}, + {0x3814, 0x01, 0, 0}, + {0x3815, 0x01, 0, 0}, + {0x3816, 0x01, 0, 0}, + {0x3817, 0x01, 0, 0}, + {0x381c, 0x08, 0, 0}, + {0x3820, 0x04, 0, 0}, + {0x3821, 0x20, 0, 0}, + {0x3823, 0x08, 0, 0}, + {0x3826, 0x00, 0, 0}, + {0x3827, 0x08, 0, 0}, + {0x382d, 0x08, 0, 0}, + {0x3832, 0x02, 0, 0}, + {0x3833, 0x00, 0, 0}, + {0x383c, 0x48, 0, 0}, + {0x383d, 0xff, 0, 0}, + {0x3d85, 0x0b, 0, 0}, + {0x3d84, 0x40, 0, 0}, + {0x3d8c, 0x63, 0, 0}, + {0x3d8d, 0xd7, 0, 0}, + {0x4000, 0xf8, 0, 0}, + {0x4001, 0x2b, 0, 0}, + {0x4004, 0x00, 0, 0}, + {0x4005, 0x40, 0, 0}, + {0x400a, 0x01, 0, 0}, + {0x400f, 0xa0, 0, 0}, + {0x4010, 0x12, 0, 0}, + {0x4018, 0x00, 0, 0}, + {0x4008, 0x02, 0, 0}, + {0x4009, 0x0d, 0, 0}, + {0x401a, 0x58, 0, 0}, + {0x4050, 0x00, 0, 0}, + {0x4051, 0x01, 0, 0}, + {0x4028, 0x2f, 0, 0}, + {0x4052, 0x00, 0, 0}, + {0x4053, 0x80, 0, 0}, + {0x4054, 0x00, 0, 0}, + {0x4055, 0x80, 0, 0}, + {0x4056, 0x00, 0, 0}, + {0x4057, 0x80, 0, 0}, + {0x4058, 0x00, 0, 0}, + {0x4059, 0x80, 0, 0}, + {0x430b, 0xff, 0, 0}, + {0x430c, 0xff, 0, 0}, + {0x430d, 0x00, 0, 0}, + {0x430e, 0x00, 0, 0}, + {0x4501, 0x18, 0, 0}, + {0x4502, 0x00, 0, 0}, + {0x4643, 0x00, 0, 0}, + {0x4640, 0x01, 0, 0}, + {0x4641, 0x04, 0, 0}, + {0x4800, 0x64, 0, 0}, + {0x4809, 0x2b, 0, 0}, + {0x4813, 0x98, 0, 0}, + {0x4817, 0x04, 0, 0}, + {0x4833, 0x18, 0, 0}, + {0x4837, 0x12, 0, 0}, + {0x483b, 0x00, 0, 0}, + {0x484b, 0x03, 0, 0}, + {0x4850, 0x7c, 0, 0}, + {0x4852, 0x06, 0, 0}, + {0x4856, 0x58, 0, 0}, + {0x4857, 0xaa, 0, 0}, + {0x4862, 0x0a, 0, 0}, + {0x4869, 0x18, 0, 0}, + {0x486a, 0xaa, 0, 0}, + {0x486e, 0x07, 0, 0}, + {0x486f, 0x55, 0, 0}, + {0x4875, 0xf0, 0, 0}, + {0x5000, 0x09, 0, 0}, + {0x5001, 0x42, 0, 0}, + {0x5004, 0x40, 0, 0}, + {0x5005, 0x00, 0, 0}, + {0x5180, 0x00, 0, 0}, + {0x5181, 0x10, 0, 0}, + {0x580b, 0x03, 0, 0}, + {0x4d00, 0x03, 0, 0}, + {0x4d01, 0xc9, 0, 0}, + {0x4d02, 0xbc, 0, 0}, + {0x4d03, 0xc6, 0, 0}, + {0x4d04, 0x4a, 0, 0}, + {0x4d05, 0x25, 0, 0}, + {0x4700, 0x2b, 0, 0}, + {0x4e00, 0x2b, 0, 0}, + {0x3501, 0x04, 0, 0}, + {0x3502, 0xb0, 0, 0}, + {0x3508, 0x00, 0, 0}, + {0x3509, 0x80, 0, 0}, + {0x350a, 0x00, 0, 0}, + {0x350b, 0x80, 0, 0}, + {0x3511, 0x00, 0, 0}, + {0x3512, 0x3c, 0, 0}, + {0x350c, 0x06, 0, 0}, + {0x350d, 0x00, 0, 0}, + {0x350e, 0x00, 0, 0}, + {0x350f, 0x80, 0, 0}, +}; + +#endif diff --git a/vvcam/v4l2/sensor/ov2775/Makefile b/vvcam/v4l2/sensor/ov2775/Makefile new file mode 100755 index 0000000..16505cb --- /dev/null +++ b/vvcam/v4l2/sensor/ov2775/Makefile @@ -0,0 +1,3 @@ +EXTRA_CFLAGS += -I$(PWD)/../common/ -O2 -Werror +ov2775-objs += ov2775_mipi_v3.o +obj-m += ov2775.o diff --git a/vvcam/v4l2/sensor/ov2775/ov2775_mipi_v3.c b/vvcam/v4l2/sensor/ov2775/ov2775_mipi_v3.c new file mode 100755 index 0000000..8d005af --- /dev/null +++ b/vvcam/v4l2/sensor/ov2775/ov2775_mipi_v3.c @@ -0,0 +1,1972 @@ +/* + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2018 NXP + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vvsensor.h" + +#include "ov2775_regs_1080p.h" +#include "ov2775_regs_1080p_hdr.h" +#include "ov2775_regs_1080p_hdr_low_freq.h" +#include "ov2775_regs_1080p_native_hdr.h" + +#define OV2775_VOLTAGE_ANALOG 2800000 +#define OV2775_VOLTAGE_DIGITAL_CORE 1500000 +#define OV2775_VOLTAGE_DIGITAL_IO 1800000 + +#define OV2775_XCLK_MIN 6000000 +#define OV2775_XCLK_MAX 24000000 + +#define OV2775_CHIP_ID_HIGH_BYTE 0x300A +#define OV2775_CHIP_ID_LOW_BYTE 0x300B + +#define OV2775_SENS_PAD_SOURCE 0 +#define OV2775_SENS_PADS_NUM 1 + +struct ov2775_datafmt { + u32 code; + enum v4l2_colorspace colorspace; +}; +struct ov2775_capture_properties { + __u64 max_lane_frequency; + __u64 max_pixel_frequency; + __u64 max_data_rate; + +}; + +struct ov2775 { + struct regulator *io_regulator; + struct regulator *core_regulator; + struct regulator *analog_regulator; + struct v4l2_subdev subdev; + struct v4l2_device *v4l2_dev; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + const struct ov2775_datafmt *fmt; + struct v4l2_captureparm streamcap; + struct media_pad pads[OV2775_SENS_PADS_NUM]; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + u32 mclk; + u8 mclk_source; + u32 sclk; + struct clk *sensor_clk; + int csi; + + void (*io_init) (struct ov2775 *); + int pwn_gpio, rst_gpio; + int hdr; + int fps; + vvcam_mode_info_t cur_mode; + sensor_blc_t blc; + sensor_white_balance_t wb; + struct mutex lock; + struct ov2775_capture_properties ocp; +}; + +#define client_to_ov2775(client)\ + container_of(i2c_get_clientdata(client), struct ov2775, subdev) + +long ov2775_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg); +static void ov2775_stop(struct ov2775 *sensor); +s32 ov2775_write_reg(struct ov2775 *sensor, u16 reg, u8 val); + +static struct vvcam_mode_info pov2775_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 12, + .data_compress.enable = 0, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x466, + .one_line_exp_time_ns = 29625, + .max_integration_time = 0x466 - 2, + .min_integration_time = 1, + .gain_accuracy = 1024, + .max_gain = 21 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = ov2775_init_setting_1080p, + .reg_data_count = ARRAY_SIZE(ov2775_init_setting_1080p), + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_DUAL_DCG, + .bit_width = 12, + .data_compress.enable = 0, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x466, + .one_line_exp_time_ns = 59167, + .max_integration_time = 0x466 - 64 - 2, + .min_integration_time = 1, + .gain_accuracy = 1024, + .max_gain = 21 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = ov2775_init_setting_1080p_hdr, + .reg_data_count = ARRAY_SIZE(ov2775_init_setting_1080p_hdr), + }, + { + .index = 2, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_NATIVE, + .bit_width = 12, + .data_compress.enable = 1, + .data_compress.x_bit = 16, + .data_compress.y_bit = 12, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x466, + .one_line_exp_time_ns = 59167, + .max_integration_time = 0x466 - 2, + .min_integration_time = 1, + .gain_accuracy = 1024, + .max_gain = 21 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = ov2775_1080p_native_hdr_regs, + .reg_data_count = ARRAY_SIZE(ov2775_1080p_native_hdr_regs), + }, +}; + +static int ov2775_probe(struct i2c_client *adapter, + const struct i2c_device_id *device_id); +static int ov2775_remove(struct i2c_client *client); +static void ov2775_stop(struct ov2775 *sensor); + +static const struct i2c_device_id ov2775_id[] = { + {"ov2775", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov2775_id); + +static int ov2775_retrieve_capture_properties(struct ov2775 *sensor,struct ov2775_capture_properties* ocp) +{ + struct device *dev = &sensor->i2c_client->dev; + __u64 mlf = 0; + __u64 mpf = 0; + __u64 mdr = 0; + + struct device_node *ep; + int ret; + /*Collecting the information about limits of capture path + * has been centralized to the sensor + * * also into the sensor endpoint itself. + */ + + ep = of_graph_get_next_endpoint(dev->of_node, NULL); + if (!ep) { + dev_err(dev, "missing endpoint node\n"); + return -ENODEV; + + } + + ret = fwnode_property_read_u64(of_fwnode_handle(ep), + "max-lane-frequency", &mlf); + if (ret || mlf == 0) { + dev_dbg(dev, "no limit for max-lane-frequency\n"); + + } + ret = fwnode_property_read_u64(of_fwnode_handle(ep), + "max-pixel-frequency", &mpf); + if (ret || mpf == 0) { + dev_dbg(dev, "no limit for max-pixel-frequency\n"); + } + + ret = fwnode_property_read_u64(of_fwnode_handle(ep), + "max-data-rate", &mdr); + if (ret || mdr == 0) { + dev_dbg(dev, "no limit for max-data_rate\n"); + } + + ocp->max_lane_frequency = mlf; + ocp->max_pixel_frequency = mpf; + ocp->max_data_rate = mdr; + + return ret; +} + +static int __maybe_unused ov2775_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct ov2775 *sensor = client_to_ov2775(client); + + if (sensor->on) { + ov2775_stop(sensor); + } + + return 0; +} + +static int __maybe_unused ov2775_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct ov2775 *sensor = client_to_ov2775(client); + + if (sensor->on) { + ov2775_write_reg(sensor, 0x3012, 0x01); + } + return 0; +} + + +static const struct dev_pm_ops ov2775_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(ov2775_suspend, ov2775_resume) +}; + +static const struct of_device_id ov2775_dt_ids[] = { + { .compatible = "ovti,ov2775" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ov2775_dt_ids); + +static struct i2c_driver ov2775_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov2775", + .pm = &ov2775_pm_ops, + .of_match_table = ov2775_dt_ids, + }, + .probe = ov2775_probe, + .remove = ov2775_remove, + .id_table = ov2775_id, +}; + +#if 0 +static const struct ov2775_datafmt ov2775_colour_fmts[] = { + {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG}, + {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG}, +}; +#else +static const struct ov2775_datafmt ov2775_colour_fmts[] = { + {MEDIA_BUS_FMT_SBGGR12_1X12, V4L2_COLORSPACE_JPEG}, +}; +#endif + +#if 0 +static enum ov2775_frame_rate to_ov2775_frame_rate(struct v4l2_fract + *timeperframe) +{ + enum ov2775_frame_rate rate; + u32 tgt_fps; /* target frames per secound */ + + pr_info("enter %s\n", __func__); + tgt_fps = timeperframe->denominator / timeperframe->numerator; + + if (tgt_fps == 30) + rate = ov2775_30_fps; + else if (tgt_fps == 15) + rate = ov2775_15_fps; + else + rate = -EINVAL; + + return rate; +} +#endif + +/* Find a data format by a pixel code in an array */ +static const struct ov2775_datafmt +*ov2775_find_datafmt(u32 code) +{ + int i; + + pr_debug("enter %s\n", __func__); + for (i = 0; i < ARRAY_SIZE(ov2775_colour_fmts); i++) + if (ov2775_colour_fmts[i].code == code) + return ov2775_colour_fmts + i; + + return NULL; +} + +static inline void ov2775_power_up(struct ov2775 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (!gpio_is_valid(sensor->pwn_gpio)) + return; + + gpio_set_value_cansleep(sensor->pwn_gpio, 1); +} + +static inline void ov2775_power_down(struct ov2775 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (!gpio_is_valid(sensor->pwn_gpio)) + return; + + gpio_set_value_cansleep(sensor->pwn_gpio, 0); +} + +static inline void ov2775_reset(struct ov2775 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (!gpio_is_valid(sensor->rst_gpio)) + return; + + gpio_set_value_cansleep(sensor->rst_gpio, 0); + msleep(20); + + gpio_set_value_cansleep(sensor->rst_gpio, 1); + msleep(20); +} + +static int ov2775_regulator_enable(struct ov2775 *sensor) +{ + int ret = 0; + struct device *dev = &(sensor->i2c_client->dev); + + pr_debug("enter %s\n", __func__); + + if (sensor->io_regulator) + { + regulator_set_voltage(sensor->io_regulator, + OV2775_VOLTAGE_DIGITAL_IO, + OV2775_VOLTAGE_DIGITAL_IO); + ret = regulator_enable(sensor->io_regulator); + if (ret < 0) { + dev_err(dev, "set io voltage failed\n"); + return ret; + } + } + + if (sensor->analog_regulator) + { + regulator_set_voltage(sensor->analog_regulator, + OV2775_VOLTAGE_ANALOG, + OV2775_VOLTAGE_ANALOG); + ret = regulator_enable(sensor->analog_regulator); + if (ret) + { + dev_err(dev, "set analog voltage failed\n"); + goto err_disable_io; + } + + } + + if (sensor->core_regulator) + { + regulator_set_voltage(sensor->core_regulator, + OV2775_VOLTAGE_DIGITAL_CORE, + OV2775_VOLTAGE_DIGITAL_CORE); + ret = regulator_enable(sensor->core_regulator); + if (ret) { + dev_err(dev, "set core voltage failed\n"); + goto err_disable_analog; + } + } + + return 0; + +err_disable_analog: + regulator_disable(sensor->analog_regulator); +err_disable_io: + regulator_disable(sensor->io_regulator); + return ret; +} + +static void ov2775_regulator_disable(struct ov2775 *sensor) +{ + int ret = 0; + struct device *dev = &(sensor->i2c_client->dev); + + if (sensor->core_regulator) + { + ret = regulator_disable(sensor->core_regulator); + if (ret < 0) + dev_err(dev, "core regulator disable failed\n"); + } + + if (sensor->analog_regulator) + { + ret = regulator_disable(sensor->analog_regulator); + if (ret < 0) + dev_err(dev, "analog regulator disable failed\n"); + } + + if (sensor->io_regulator) + { + ret = regulator_disable(sensor->io_regulator); + if (ret < 0) + dev_err(dev, "io regulator disable failed\n"); + } + return ; +} + +s32 ov2775_write_reg(struct ov2775 *sensor, u16 reg, u8 val) +{ + struct device *dev = &sensor->i2c_client->dev; + u8 au8Buf[3] = { 0 }; + + au8Buf[0] = reg >> 8; + au8Buf[1] = reg & 0xff; + au8Buf[2] = val; + + if (i2c_master_send(sensor->i2c_client, au8Buf, 3) < 0) { + dev_err(dev, "Write reg error: reg=%x, val=%x\n", reg, val); + return -1; + } + + return 0; +} + +s32 ov2775_read_reg(struct ov2775 *sensor, u16 reg, u8 *val) +{ + struct device *dev = &sensor->i2c_client->dev; + u8 au8RegBuf[2] = { 0 }; + u8 u8RdVal = 0; + + au8RegBuf[0] = reg >> 8; + au8RegBuf[1] = reg & 0xff; + + if (i2c_master_send(sensor->i2c_client, au8RegBuf, 2) != 2) { + dev_err(dev, "Read reg error: reg=%x\n", reg); + return -1; + } + + if (i2c_master_recv(sensor->i2c_client, &u8RdVal, 1) != 1) { + dev_err(dev, "Read reg error: reg=%x, val=%x\n", reg, u8RdVal); + return -1; + } + + *val = u8RdVal; + + return u8RdVal; +} + +static int ov2775_set_clk_rate(struct ov2775 *sensor) +{ + u32 tgt_xclk; /* target xclk */ + int ret; + + /* mclk */ + tgt_xclk = sensor->mclk; + tgt_xclk = min_t(u32, tgt_xclk, (u32) OV2775_XCLK_MAX); + tgt_xclk = max_t(u32, tgt_xclk, (u32) OV2775_XCLK_MIN); + sensor->mclk = tgt_xclk; + + pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); + ret = clk_set_rate(sensor->sensor_clk, sensor->mclk); + if (ret < 0) + pr_debug("set rate filed, rate=%d\n", sensor->mclk); + return ret; +} + +/* download ov2775 settings to sensor through i2c */ +static int ov2775_download_firmware(struct ov2775 *sensor, + struct vvsensor_reg_value_t *mode_setting, + s32 size) +{ + register u32 delay_ms = 0; + register u16 reg_addr = 0; + register u8 mask = 0; + register u8 val = 0; + u8 reg_val = 0; + int i, retval = 0; + + struct i2c_msg msg; + u16 reg_len; + u8 *reg_buf; + struct vvsensor_reg_value_t *mode_setting_next; + struct i2c_client *i2c_client = sensor->i2c_client; + //sensor soft rest + ov2775_write_reg(sensor, 0x3013, 0x1); + msleep(10); + + reg_buf = (u8 *)kmalloc(size + 2, GFP_KERNEL); + if (!reg_buf) + return -ENOMEM; + + pr_debug("enter %s\n", __func__); + for (i = 0; i < size; ++i, ++mode_setting) { + delay_ms = mode_setting->delay; + reg_addr = mode_setting->addr; + val = mode_setting->val; + mask = mode_setting->mask; + + if(unlikely(mask || delay_ms)) { + if (mask) { + retval = ov2775_read_reg(sensor, reg_addr, ®_val); + if (retval < 0) + break; + + reg_val &= ~(u8)mask; + val &= mask; + val |= reg_val; + } + + retval = ov2775_write_reg(sensor, reg_addr, val); + if (retval < 0) + break; + + if (delay_ms) + msleep(delay_ms); + } else { + mode_setting_next = mode_setting + 1; + reg_buf[0] = reg_addr >> 8; + reg_buf[1] = reg_addr & 0xff; + reg_buf[2] = val; + reg_len = 3; + + while(i + 1 < size && + !mode_setting_next->mask && !mode_setting_next->delay && + mode_setting_next->addr == reg_addr + 1) { + reg_buf[reg_len++] = mode_setting_next->val; + i++; + mode_setting++; + mode_setting_next++; + reg_addr++; + } + msg.addr = i2c_client->addr; + msg.flags = i2c_client->flags; + msg.len = reg_len; + msg.buf = reg_buf; + pr_debug("start reg_addr=0x%02x%02x reg_num=%d\n", + reg_buf[0], reg_buf[1], reg_len-2); + retval = i2c_transfer(i2c_client->adapter, &msg, 1); + if (retval < 0) { + dev_err(&i2c_client->dev, "i2c transfer error\n"); + break; + } + } + } + + kfree(reg_buf); + return retval; +} + +static void ov2775_start(struct ov2775 *sensor) +{ + pr_debug("enter %s\n", __func__); +#if 1 + ov2775_write_reg(sensor, 0x3012, 0x01); +#else + ov2775_write_reg(sensor, 0x3008, 0x02); + ov2775_write_reg(sensor, 0x4202, 0x00); +#endif + /* Color bar control */ + /* ov2775_write_reg(sensor, 0x503d, 0x80); */ + + /* skip the first three frame for 30fps */ + msleep(100); +} + +#if 0 +static int ov2775_change_mode(struct ov2775 *sensor) +{ + struct reg_value *mode_setting = NULL; + enum ov2775_mode mode = sensor->streamcap.capturemode; + enum ov2775_frame_rate frame_rate = + to_ov2775_frame_rate(&sensor->streamcap.timeperframe); + int ArySize = 0, retval = 0; + + pr_debug("enter %s\n", __func__); + if (mode > ov2775_mode_MAX || mode < ov2775_mode_MIN) { + pr_err("Wrong ov2775 mode detected!\n"); + return -1; + } + + mode_setting = ov2775_mode_info_data[frame_rate][mode].init_data_ptr; + ArySize = ov2775_mode_info_data[frame_rate][mode].init_data_size; + + sensor->pix.width = ov2775_mode_info_data[frame_rate][mode].width; + sensor->pix.height = ov2775_mode_info_data[frame_rate][mode].height; + + if (sensor->pix.width == 0 || sensor->pix.height == 0 || + mode_setting == NULL || ArySize == 0) { + pr_err("Not support mode=%d %s\n", mode, + (frame_rate == 0) ? "15(fps)" : "30(fps)"); + return -EINVAL; + } + + retval = ov2775_download_firmware(sensor, mode_setting, ArySize); + + return retval; +} +#endif + +static void ov2775_stop(struct ov2775 *sensor) +{ + int i, size, retval = 0; + struct vvsensor_reg_value_t *mode_setting, *mode_setting_next; + struct i2c_msg msg; + register u16 reg_addr = 0; + u16 reg_len; + u8 *reg_buf; + struct i2c_client *i2c_client = sensor->i2c_client; + pr_debug("enter %s\n", __func__); + + ov2775_write_reg(sensor, 0x3012, 0x00); + /* if the sensor re-enter streaming from standby mode + * all registers starting with 0x7000 must be resent + * before setting 0x3012[0]=1. + */ + mode_setting = + (struct vvsensor_reg_value_t *)sensor->cur_mode.preg_data; + size = sensor->cur_mode.reg_data_count; + reg_buf = (u8 *)kmalloc(size + 2, GFP_KERNEL); + if (!reg_buf) + return; + for(i = 0; i < size; i++, mode_setting++) { + reg_addr = mode_setting->addr; + mode_setting_next = mode_setting + 1; + if(reg_addr >= 0x7000) { + reg_buf[0] = reg_addr >> 8; + reg_buf[1] = reg_addr & 0xff; + reg_buf[2] = mode_setting->val; + reg_len = 3; + while(i + 1 < size && reg_addr >= 0x7000 && + mode_setting_next->addr == reg_addr + 1) { + reg_buf[reg_len++] = mode_setting_next->val; + i++; + mode_setting++; + mode_setting_next++; + reg_addr++; + } + msg.addr = i2c_client->addr; + msg.flags = i2c_client->flags; + msg.len = reg_len; + msg.buf = reg_buf; + pr_debug("start reg_addr=0x%02x%02x reg_num=%d\n", + reg_buf[0], reg_buf[1], reg_len-2); + retval = i2c_transfer(i2c_client->adapter, &msg, 1); + if (retval < 0) { + dev_err(&i2c_client->dev, "i2c transfer error\n"); + break; + } + } + } + kfree(reg_buf); + +} + +/*! + * ov2775_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl + * @s: pointer to standard V4L2 device structure + * @on: indicates power mode (on or off) + * + * Turns the power on or off, depending on the value of on and returns the + * appropriate error code. + */ +static int ov2775_s_power(struct v4l2_subdev *sd, int on) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + + pr_debug("enter %s\n", __func__); + if (on) + clk_prepare_enable(sensor->sensor_clk); + else + clk_disable_unprepare(sensor->sensor_clk); + + sensor->on = on; + return 0; +} + +/*! + * ov2775_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 sub device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ov2775_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + pr_debug("enter %s\n", __func__); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ov5460_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 sub device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ov2775_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a) +{ + int ret = 0; + + pr_debug("enter %s\n", __func__); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_debug(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +static int ov2775_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + + pr_debug("enter %s\n", __func__); + if (enable) + ov2775_start(sensor); + else + ov2775_stop(sensor); + + sensor->on = enable; + return 0; +} + +static int ov2775_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *mf = &format->format; + const struct ov2775_datafmt *fmt = ov2775_find_datafmt(mf->code); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + unsigned int i; + struct vvsensor_reg_value_t *mode_setting = NULL; + int array_size = 0; + + pr_debug("enter %s\n", __func__); + if(sensor->ocp.max_pixel_frequency == 266000000) { + pov2775_mode_info[1].preg_data = ov2775_init_setting_1080p_hdr_low_freq; + pov2775_mode_info[1].reg_data_count = ARRAY_SIZE(ov2775_init_setting_1080p_hdr_low_freq); + pov2775_mode_info[1].ae_info.one_line_exp_time_ns = 60784; + } else { + pov2775_mode_info[1].preg_data = ov2775_init_setting_1080p_hdr; + pov2775_mode_info[1].reg_data_count = ARRAY_SIZE(ov2775_init_setting_1080p_hdr); + pov2775_mode_info[1].ae_info.one_line_exp_time_ns = 59167; + } + if (format->pad) { + return -EINVAL; + } + + if (!fmt) { + mf->code = ov2775_colour_fmts[0].code; + mf->colorspace = ov2775_colour_fmts[0].colorspace; + } + + mf->field = V4L2_FIELD_NONE; + /* old search method, vsi need change to + search resolution by width/height */ + /* try_to_find_resolution(sensor, mf); */ + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + return 0; + + for (i=0; iwidth == pov2775_mode_info[i].width && + mf->height == pov2775_mode_info[i].height && + pov2775_mode_info[i].index == sensor->cur_mode.index) + { + memcpy(&(sensor->cur_mode), &pov2775_mode_info[i], sizeof(struct vvcam_mode_info)); + mode_setting = pov2775_mode_info[i].preg_data; + array_size = pov2775_mode_info[i].reg_data_count; + + return ov2775_download_firmware(sensor, mode_setting, array_size); + } + } + + pr_err("%s search error: %d %d\n", __func__, mf->width, mf->height); + return -EINVAL; +} + +static int ov2775_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *mf = &format->format; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + + pr_debug("enter %s\n", __func__); + if (format->pad) + return -EINVAL; + + memset(mf, 0, sizeof(struct v4l2_mbus_framefmt)); + + mf->code = ov2775_colour_fmts[0].code; + mf->colorspace = ov2775_colour_fmts[0].colorspace; + mf->width = sensor->pix.width; + mf->height = sensor->pix.height; + mf->field = V4L2_FIELD_NONE; + + dev_dbg(&client->dev, + "%s code=0x%x, w/h=(%d,%d), colorspace=%d, field=%d\n", + __func__, mf->code, mf->width, mf->height, mf->colorspace, + mf->field); + + return 0; +} + +static int ov2775_enum_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + pr_debug("enter %s\n", __func__); + if (code->pad || code->index >= ARRAY_SIZE(ov2775_colour_fmts)) + return -EINVAL; + + code->code = ov2775_colour_fmts[code->index].code; + return 0; +} + +/*! + * ov2775_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ov2775_enum_framesizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + pr_debug("enter %s\n", __func__); + + if (fse->index > ARRAY_SIZE(pov2775_mode_info)) + return -EINVAL; + + fse->min_width = pov2775_mode_info[fse->index].width; + fse->max_width = fse->min_width; + fse->min_height = pov2775_mode_info[fse->index].height; + fse->max_height = fse->min_height; + + return 0; +} + +/*! + * ov2775_enum_frameintervals - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMEINTERVALS ioctl + * @s: pointer to standard V4L2 device structure + * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ov2775_enum_frameintervals(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum + *fie) +{ + pr_debug("enter %s\n", __func__); + if (fie->index < 0 || fie->index > ARRAY_SIZE(pov2775_mode_info)) + return -EINVAL; + + if (fie->width == 0 || fie->height == 0 || fie->code == 0) { + pr_warn("Please assign pixel format, width and height.\n"); + return -EINVAL; + } + + fie->interval.numerator = 1; + fie->interval.denominator = pov2775_mode_info[fie->index].fps; + + return 0; +} + +static int ov2775_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static struct v4l2_subdev_video_ops ov2775_subdev_video_ops = { + .g_parm = ov2775_g_parm, + .s_parm = ov2775_s_parm, + .s_stream = ov2775_s_stream, +}; + +static const struct v4l2_subdev_pad_ops ov2775_subdev_pad_ops = { + .enum_frame_size = ov2775_enum_framesizes, + .enum_frame_interval = ov2775_enum_frameintervals, + .enum_mbus_code = ov2775_enum_code, + .set_fmt = ov2775_set_fmt, + .get_fmt = ov2775_get_fmt, +}; + +static struct v4l2_subdev_core_ops ov2775_subdev_core_ops = { + .s_power = ov2775_s_power, + .ioctl = ov2775_priv_ioctl, +}; + +static struct v4l2_subdev_ops ov2775_subdev_ops = { + .core = &ov2775_subdev_core_ops, + .video = &ov2775_subdev_video_ops, + .pad = &ov2775_subdev_pad_ops, +}; + +static const struct media_entity_operations ov2775_sd_media_ops = { + .link_setup = ov2775_link_setup, +}; + +/*! + * ov2775 I2C probe function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ + +static int ov2775_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct v4l2_subdev *sd; + int retval; + struct ov2775 *sensor; + u8 reg_val = 0; + u16 chip_id = 0; + + pr_info("enter %s\n", __func__); + + sensor = devm_kmalloc(dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + memset(sensor, 0, sizeof(*sensor)); + sensor->i2c_client = client; + + /* request power down pin */ + sensor->pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); + if (!gpio_is_valid(sensor->pwn_gpio)) + dev_warn(dev, "No sensor pwdn pin available"); + else { + retval = devm_gpio_request_one(dev, sensor->pwn_gpio, + GPIOF_OUT_INIT_HIGH, + "ov2775_mipi_pwdn"); + if (retval < 0) { + dev_warn(dev, "Failed to set power pin\n"); + dev_warn(dev, "retval=%d\n", retval); + return retval; + } + } + + /* request reset pin */ + sensor->rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); + if (!gpio_is_valid(sensor->rst_gpio)) + dev_warn(dev, "No sensor reset pin available"); + else { + retval = devm_gpio_request_one(dev, sensor->rst_gpio, + GPIOF_OUT_INIT_HIGH, + "ov2775_mipi_reset"); + if (retval < 0) { + dev_warn(dev, "Failed to set reset pin\n"); + return retval; + } + } + + /* Set initial values for the sensor struct. */ + sensor->sensor_clk = devm_clk_get(dev, "csi_mclk"); + if (IS_ERR(sensor->sensor_clk)) { + /* assuming clock enabled by default */ + sensor->sensor_clk = NULL; + dev_err(dev, "clock-frequency missing or invalid\n"); + return PTR_ERR(sensor->sensor_clk); + } + + retval = of_property_read_u32(dev->of_node, "mclk", &(sensor->mclk)); + if (retval) { + dev_err(dev, "mclk missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "mclk_source", + (u32 *)&(sensor->mclk_source)); + if (retval) { + dev_err(dev, "mclk_source missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "csi_id", &(sensor->csi)); + if (retval) { + dev_err(dev, "csi id missing or invalid\n"); + return retval; + } + + sensor->io_regulator = devm_regulator_get(dev, "DOVDD"); + if (IS_ERR(sensor->io_regulator)) + { + dev_err(dev, "cannot get io regulator\n"); + return PTR_ERR(sensor->io_regulator); + } + + sensor->core_regulator = devm_regulator_get(dev, "DVDD"); + if (IS_ERR(sensor->core_regulator)) + { + dev_err(dev, "cannot get core regulator\n"); + return PTR_ERR(sensor->core_regulator); + } + + sensor->analog_regulator = devm_regulator_get(dev, "AVDD"); + if (IS_ERR(sensor->analog_regulator)) + { + dev_err(dev, "cannot get analog regulator\n"); + return PTR_ERR(sensor->analog_regulator); + } + + retval = ov2775_regulator_enable(sensor); + if (retval) { + dev_err(dev, "regulator enable failed\n"); + return retval; + } + + /* Set mclk rate before clk on */ + ov2775_set_clk_rate(sensor); + retval = clk_prepare_enable(sensor->sensor_clk); + if (retval < 0) { + dev_err(dev, "%s: enable sensor clk fail\n", __func__); + goto probe_err_regulator_disable; + } + + ov2775_power_up(sensor); + ov2775_reset(sensor); + + sensor->io_init = ov2775_reset; + sensor->pix.pixelformat = V4L2_PIX_FMT_UYVY; + sensor->pix.width = pov2775_mode_info[0].width; + sensor->pix.height = pov2775_mode_info[0].height; + sensor->streamcap.capability = V4L2_MODE_HIGHQUALITY | + V4L2_CAP_TIMEPERFRAME; + sensor->streamcap.capturemode = 0; + sensor->streamcap.timeperframe.denominator = pov2775_mode_info[0].fps; + sensor->streamcap.timeperframe.numerator = 1; + + sensor->blc.blue = 64; + sensor->blc.gb = 64; + sensor->blc.gr = 64; + sensor->blc.red = 64; + sensor->wb.r_gain = 0x1f9; + sensor->wb.gr_gain = 0x104; + sensor->wb.gb_gain = 0x104; + sensor->wb.b_gain = 0x23e; + + chip_id = 0; + ov2775_read_reg(sensor, OV2775_CHIP_ID_HIGH_BYTE,®_val); + chip_id |= reg_val << 8; + ov2775_read_reg(sensor, OV2775_CHIP_ID_LOW_BYTE, ®_val); + chip_id |= reg_val; + if (chip_id != 0x2770) { + pr_warn("camera ov2775 is not found\n"); + goto probe_err_power_down; + } + + sd = &sensor->subdev; + v4l2_i2c_subdev_init(sd, client, &ov2775_subdev_ops); + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + sensor->pads[OV2775_SENS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + + retval = media_entity_pads_init(&sd->entity, OV2775_SENS_PADS_NUM, + sensor->pads); + sd->entity.ops = &ov2775_sd_media_ops; + if (retval < 0) + goto probe_err_power_down; + + retval = v4l2_async_register_subdev_sensor_common(sd); + if (retval < 0) { + dev_err(&client->dev,"%s--Async register failed, ret=%d\n", __func__,retval); + goto probe_err_entity_cleanup; + } + + mutex_init(&sensor->lock); + ov2775_retrieve_capture_properties(sensor,&sensor->ocp); + pr_info("%s camera mipi ov2775, is found\n", __func__); + + return 0; + +probe_err_entity_cleanup: + media_entity_cleanup(&sd->entity); +probe_err_power_down: + ov2775_power_down(sensor); + clk_disable_unprepare(sensor->sensor_clk); +probe_err_regulator_disable: + ov2775_regulator_disable(sensor); + return retval; + +} + +/*! + * ov2775 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int ov2775_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2775 *sensor = client_to_ov2775(client); + + pr_info("enter %s\n", __func__); + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + ov2775_power_down(sensor); + clk_disable_unprepare(sensor->sensor_clk); + ov2775_regulator_disable(sensor); + mutex_destroy(&sensor->lock); + return 0; +} + +module_i2c_driver(ov2775_i2c_driver); +MODULE_DESCRIPTION("OV2775 MIPI Camera Subdev Driver"); +MODULE_LICENSE("GPL"); + +int sensor_calc_gain(__u32 total_gain, __u32 *pagain, __u32 *pdgain, __u32 *phcg) +{ + if (total_gain <= 3072) + total_gain = 3072; + else if ((total_gain >= 22528) && (total_gain < 23552)) + total_gain = 22528; + + if (total_gain < 4480) { + *pagain = 1; + *phcg = 1; + } else if (total_gain < 8960) { + *pagain = 2; + *phcg = 1; + } else if (total_gain < 22528) { + *pagain = 3; + *phcg = 1; + } else if (total_gain < 44990) { + *pagain = 0; + *phcg = 11; + } else if (total_gain < 89320) { + *pagain = 1; + *phcg = 11; + } else if (total_gain < 179498) { + *pagain = 2; + *phcg = 11; + } else { + *pagain = 3; + *phcg = 11; + } + + *pdgain = ((total_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; +} + +int ov2775_s_long_gain(struct ov2775 *sensor, __u32 new_gain) +{ + int ret = 0; + __u8 reg_val; + __u32 hcg; + __u32 hcg_gain; + __u32 hcg_again = 0; + __u32 hcg_dgain = 0; + + hcg_gain = new_gain/10; + + sensor_calc_gain(hcg_gain, &hcg_again, &hcg_dgain, &hcg); + + ret = ov2775_read_reg(sensor, 0x30bb, ®_val); + reg_val &= ~0x03; + reg_val |= hcg_again & 0x03; + + ret = ov2775_write_reg(sensor, 0x3467, 0x00); + ret |= ov2775_write_reg(sensor, 0x3464, 0x04); + + ret |= ov2775_write_reg(sensor, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x315b, hcg_dgain & 0xff); + + ret |= ov2775_write_reg(sensor, 0x30bb, reg_val); + ret |= ov2775_write_reg(sensor, 0x3464, 0x14); + ret |= ov2775_write_reg(sensor, 0x3467, 0x01); + + return ret; +} + +int ov2775_s_gain(struct ov2775 *sensor, __u32 new_gain) +{ + int ret = 0; + __u8 reg_val; + __u32 hcg = 0; + __u32 again, dgain; + + __u32 lcg_gain; + __u32 lcg_again = 0; + __u32 lcg_dgain = 0; + + if (sensor->hdr == SENSOR_MODE_LINEAR) { + sensor_calc_gain(new_gain, &again, &dgain, &hcg); + ret = ov2775_read_reg(sensor, 0x30bb, ®_val); + if (hcg == 1) { + reg_val &= ~(1 << 6); + } else { + reg_val |= (1 << 6); + } + reg_val &= ~0x03; + reg_val |= again; + ret = ov2775_write_reg(sensor, 0x3467, 0x00); + ret |= ov2775_write_reg(sensor, 0x3464, 0x04); + ret |= ov2775_write_reg(sensor, 0x315a, (dgain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x315b, dgain & 0xff); + ret |= ov2775_write_reg(sensor, 0x30bb, reg_val); + ret |= ov2775_write_reg(sensor, 0x3464, 0x14); + ret |= ov2775_write_reg(sensor, 0x3467, 0x01); + }else { + lcg_gain = new_gain; + sensor_calc_gain(lcg_gain, &lcg_again, &lcg_dgain, &hcg); + + ret = ov2775_read_reg(sensor, 0x30bb, ®_val); + reg_val &= ~(0x03 << 2); + reg_val |= (lcg_again & 0x03) << 2; + + ret = ov2775_write_reg(sensor, 0x3467, 0x00); + ret |= ov2775_write_reg(sensor, 0x3464, 0x04); + + ret |= ov2775_write_reg(sensor, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x315d, lcg_dgain & 0xff); + + ret |= ov2775_write_reg(sensor, 0x30bb, reg_val); + ret |= ov2775_write_reg(sensor, 0x3464, 0x14); + ret |= ov2775_write_reg(sensor, 0x3467, 0x01); + } + return ret; +} + +int ov2775_s_vsgain(struct ov2775 *sensor, __u32 new_gain) +{ + __u32 again = 0; + __u32 dgain, hcg; + __u8 reg_val; + + sensor_calc_gain(new_gain, &again, &dgain, &hcg); + + ov2775_read_reg(sensor, 0x30bb, ®_val); + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + + ov2775_write_reg(sensor, 0x3467, 0x00); + ov2775_write_reg(sensor, 0x3464, 0x04); + + ov2775_write_reg(sensor, 0x315e, (dgain & 0xFF00) >> 8); + ov2775_write_reg(sensor, 0x315f, dgain & (0x00FF)); + ov2775_write_reg(sensor, 0x30bb, reg_val); + + ov2775_write_reg(sensor, 0x3464, 0x14); + ov2775_write_reg(sensor, 0x3467, 0x01); + return 0; +} + +int ov2775_s_long_exp(struct ov2775 *sensor, __u32 exp) +{ + return 0; +} + +int ov2775_s_exp(struct ov2775 *sensor, __u32 exp) +{ + /* pr_info("enter %s 0x%08x\n", __func__, exp); */ + ov2775_write_reg(sensor, 0x3467, 0x00); + ov2775_write_reg(sensor, 0x3464, 0x04); + + ov2775_write_reg(sensor, 0x30b6, (exp & 0xFF00) >> 8); + ov2775_write_reg(sensor, 0x30b7, exp & 0x00FF); + + ov2775_write_reg(sensor, 0x3464, 0x14); + ov2775_write_reg(sensor, 0x3467, 0x01); + return 0; +} + +int ov2775_s_vsexp(struct ov2775 *sensor, __u32 exp) +{ + /* pr_info("enter %s 0x%08x\n", __func__, exp); */ + ov2775_write_reg(sensor, 0x3467, 0x00); + ov2775_write_reg(sensor, 0x3464, 0x04); + + if (exp == 0x16) + exp = 0x17; + if (sensor->hdr == SENSOR_MODE_HDR_STITCH) { + if (exp >0x2c) + exp = 0x2c; + } + + ov2775_write_reg(sensor, 0x30b8, (exp & 0xFF00) >> 8); + ov2775_write_reg(sensor, 0x30b9, exp & 0x00FF); + + ov2775_write_reg(sensor, 0x3464, 0x14); + ov2775_write_reg(sensor, 0x3467, 0x01); + return 0; +} + +int ov2775_g_gain(struct ov2775 *sensor, struct vvsensor_gain_context *gain) +{ + __u8 val = 0; + + ov2775_read_reg(sensor, 0x315a, &val); + gain->dgain = val << 8; + ov2775_read_reg(sensor, 0x315b, &val); + gain->dgain |= val << 0; + ov2775_read_reg(sensor, 0x315c, &val); + gain->dgain |= val << 24; + ov2775_read_reg(sensor, 0x315d, &val); + gain->dgain |= val << 16; + ov2775_read_reg(sensor, 0x30bb, &val); + gain->again = val; + return 0; +} + +int ov2775_g_version(struct ov2775 *sensor, __u32 *version) +{ + __u8 val = 0; + + ov2775_read_reg(sensor, 0x300a, &val); + *version = val << 8; + ov2775_read_reg(sensor, 0x300b, &val); + *version |= val; + return 0; +} + + +int ov2775_s_hdr(struct ov2775 *sensor, int hdr_mode) +{ + pr_debug("%s: %d\n", __func__, hdr_mode); + sensor->hdr = hdr_mode; + return 0; +} + +int ov2775_s_sensor_mode(struct ov2775 *sensor, struct vvcam_mode_info *sensor_mode) +{ + + if(sensor_mode->index < ARRAY_SIZE(pov2775_mode_info) && sensor_mode->index >= 0){ + sensor->cur_mode.index = sensor_mode->index; + }else{ + pr_err("%s Set ov2775 mode index error",__func__); + return -1; + } + + return 0; +} + + +int ov2775_s_clk(struct ov2775 *sensor, __u32 clk) +{ + pr_debug("%s: %d\n", __func__, clk); + ov2775_write_reg(sensor, 0x3005, clk); + return 0; +} + +int ov2775_g_clk(struct ov2775 *sensor, __u32 *clk) +{ + u8 val; + ov2775_read_reg(sensor, 0x3005, &val); + *clk = val; + return 0; +} + +int ov2775_g_sclk(struct ov2775 *sensor, __u32 *sclk_hz) +{ + int ret = 0; + u8 pclk_pll_pre;//0x3004[2:0] + u8 pclk_pll_pdiv;//0x3005[7:0] + u8 pclk_pll_sdiv;//0x3006[0] + u8 pclk_pll_post;//0x3007[3:0] + u32 pclk_pll_m; + u8 pclk_pll_pre_num, pclk_pll_pre_deno; + ret = ov2775_read_reg(sensor, 0x3004, &pclk_pll_pre); + ret |= ov2775_read_reg(sensor, 0x3005, &pclk_pll_pdiv); + ret |= ov2775_read_reg(sensor, 0x3006, &pclk_pll_sdiv); + ret |= ov2775_read_reg(sensor, 0x3007, &pclk_pll_post); + switch(pclk_pll_pre&0x07)//0x3004[2:0] + { + case 0: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 1; break; + case 1: pclk_pll_pre_num = 2; pclk_pll_pre_deno = 3; break; + case 2: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 2; break; + case 3: pclk_pll_pre_num = 2; pclk_pll_pre_deno = 5; break; + case 4: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 3; break; + case 5: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 4; break; + case 6: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 6; break; + default: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 8; break; + } + pclk_pll_post = (pclk_pll_post&0x0F) + 1; + pclk_pll_m = 2*pclk_pll_pdiv + (pclk_pll_sdiv&0x01) + 4; + *sclk_hz = (sensor->mclk/1000*pclk_pll_m*pclk_pll_pre_num/(pclk_pll_pre_deno*pclk_pll_post))*1000; + sensor->sclk = *sclk_hz; + return ret; +} + +int ov2775_s_fps(struct ov2775 *sensor, __u32 fps) +{ + u32 vts; + + if (fps < 5) { + fps = 5; + } + if (fps > sensor->cur_mode.fps){ + fps = sensor->cur_mode.fps; + } + sensor->fps = fps; + + vts = sensor->cur_mode.fps * sensor->cur_mode.ae_info.DefaultFrameLengthLines / sensor->fps; + + ov2775_write_reg(sensor, 0x30B2, (u8)(vts >> 8)); + ov2775_write_reg(sensor, 0x30B3, (u8)(vts & 0xff)); + + if (sensor->cur_mode.hdr_mode != SENSOR_MODE_LINEAR) + { + sensor->cur_mode.ae_info.cur_fps = sensor->fps; + sensor->cur_mode.ae_info.CurFrameLengthLines = vts; + sensor->cur_mode.ae_info.max_integration_time = vts - 64 - 2; + }else + { + sensor->cur_mode.ae_info.cur_fps = sensor->fps; + sensor->cur_mode.ae_info.CurFrameLengthLines = vts; + sensor->cur_mode.ae_info.max_integration_time = vts - 2; + } + return 0; +} + +int ov2775_g_fps(struct ov2775 *sensor, __u32 *fps) +{ + *fps = sensor->fps; + return 0; +} + +int ov2775_g_chipid(struct ov2775 *sensor, __u32 *chip_id) +{ + int ret = 0; + __u8 chip_id_high = 0; + __u8 chip_id_low = 0; + ret = ov2775_read_reg(sensor, 0x300a, &chip_id_high); + ret |= ov2775_read_reg(sensor, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + return ret; +} + +int ov2775_ioc_qcap(struct ov2775 *sensor, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "ov2775"); + sprintf((char *)cap->bus_info, "csi%d",sensor->csi);//bus_info[0:7]-csi number + if(sensor->i2c_client->adapter) + {//bus_info[8]-i2c bus dev number + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = (__u8)sensor->i2c_client->adapter->nr; + } + else + { + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = 0xFF; + } + + return 0; +} + +int ov2775_ioc_query_mode(struct ov2775 *sensor, struct vvcam_mode_info_array *array) +{ + array->count = ARRAY_SIZE(pov2775_mode_info); +#ifdef CONFIG_HARDENED_USERCOPY + unsigned long copy_ret = 0; + pr_debug("sensor %px\n", sensor); + copy_ret = copy_to_user(&array->modes,pov2775_mode_info,sizeof(pov2775_mode_info)); +#else + memcpy(&array->modes,pov2775_mode_info,sizeof(pov2775_mode_info)); +#endif + + return 0; +} + +int ov2775_g_mode(struct ov2775 *sensor, struct vvcam_mode_info *pmode) +{ + int i = 0; + struct vvcam_mode_info *pcur_mode = NULL; + + if (sensor->cur_mode.index == pmode->index && + sensor->cur_mode.width != 0 && + sensor->cur_mode.height != 0) + { + pcur_mode = &(sensor->cur_mode); + memcpy(pmode,pcur_mode,sizeof(struct vvcam_mode_info)); + return 0; + } + for(i=0; i < ARRAY_SIZE(pov2775_mode_info); i++) + { + if (pmode->index == pov2775_mode_info[i].index) + { + pcur_mode = &pov2775_mode_info[i]; + sensor->fps = pov2775_mode_info[i].fps; + break; + } + } + if (pcur_mode == NULL) + { + return -1; + } + + memcpy(pmode,pcur_mode,sizeof(struct vvcam_mode_info)); + return 0; +} + +int ov2775_s_blc(struct ov2775 *sensor, sensor_blc_t *pblc) +{ + int ret = 0; + int r_offset,gr_offset,gb_offset,b_offset; + unsigned int r_gain,gr_gain,gb_gain,b_gain; + + r_gain = sensor->wb.r_gain; + gr_gain = sensor->wb.gr_gain; + gb_gain = sensor->wb.gb_gain; + b_gain = sensor->wb.b_gain; + + if (r_gain < 0x100) + r_gain = 0x100; + if (gr_gain < 0x100) + gr_gain = 0x100; + if (gb_gain < 0x100) + gb_gain = 0x100; + if (b_gain < 0x100) + b_gain = 0x100; + + r_offset = (r_gain - 0x100) * pblc->red; + gr_offset = (gr_gain - 0x100) * pblc->gr; + gb_offset = (gb_gain - 0X100) * pblc->gb; + b_offset = (b_gain - 0X100) * pblc->blue; + + //R,Gr,Gb,B HCG Offset + ret |= ov2775_write_reg(sensor, 0x3378, (r_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3379, (r_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x337a, r_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x337b, (gr_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x337c, (gr_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x337d, gr_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x337e, (gb_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x337f, (gb_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3380, gb_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x3381, (b_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3382, (b_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3383, b_offset & 0xff); + + //R,Gr,Gb,B LCG Offset + ret |= ov2775_write_reg(sensor, 0x3384, (r_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3385, (r_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3386, r_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x3387, (gr_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3388, (gr_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3389, gr_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x338a, (gb_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x338b, (gb_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x338c, gb_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x338d, (b_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x338e, (b_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x338f, b_offset & 0xff); + + //R,Gr,Gb,B VS Offset + ret |= ov2775_write_reg(sensor, 0x3390, (r_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3391, (r_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3392, r_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x3393, (gr_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3394, (gr_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3395, gr_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x3396, (gb_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3397, (gb_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3398, gb_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x3399, (b_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x339a, (b_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x339b, b_offset & 0xff); + + memcpy(&sensor->blc,pblc,sizeof(sensor_blc_t)); + + return ret; +} + + +int ov2775_s_wb(struct ov2775 *sensor, sensor_white_balance_t *wb) +{ + unsigned int r_gain,gr_gain,gb_gain,b_gain; + int ret = 0; + + r_gain = wb->r_gain; // wb->r_gain =256 means gain 1.0 + gr_gain = wb->gr_gain;// wb->gr_gain =256 means gain 1.0 + gb_gain = wb->gb_gain;// wb->gb_gain =256 means gain 1.0 + b_gain = wb->b_gain; // wb->b_gain =256 means gain 1.0 + + //Red,Gr,Gb,Blue HCG Channel + if(sensor->wb.r_gain != wb->r_gain){ + + ret = ov2775_write_reg(sensor, 0x3360, (r_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3361, r_gain & 0xff); + } + if(sensor->wb.gr_gain != wb->gr_gain){ + + ret = ov2775_write_reg(sensor, 0x3362, (gr_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3363, gr_gain & 0xff); + } + if(sensor->wb.gb_gain != wb->gb_gain){ + + ret = ov2775_write_reg(sensor, 0x3364, (gb_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3365, gb_gain & 0xff); + } + if(sensor->wb.b_gain != wb->b_gain){ + + ret = ov2775_write_reg(sensor, 0x3366, (b_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3367, b_gain & 0xff); + } + + //Red,Gr,Gb,Blue LCG Channel + if(sensor->wb.r_gain != wb->r_gain){ + + ret = ov2775_write_reg(sensor, 0x3368, (r_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3369, r_gain & 0xff); + } + if(sensor->wb.gr_gain != wb->gr_gain){ + + ret = ov2775_write_reg(sensor, 0x336a, (gr_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x336b, gr_gain & 0xff); + } + if(sensor->wb.gb_gain != wb->gb_gain){ + + ret = ov2775_write_reg(sensor, 0x336c, (gb_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x336d, gb_gain & 0xff); + } + if(sensor->wb.b_gain != wb->b_gain){ + + ret = ov2775_write_reg(sensor, 0x336e, (b_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x336f, b_gain & 0xff); + } + + //Red,Gr,Gb,Blue VS Channel + if(sensor->wb.r_gain != wb->r_gain){ + + ret = ov2775_write_reg(sensor, 0x3370, (r_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3371, r_gain & 0xff); + } + if(sensor->wb.gr_gain != wb->gr_gain){ + + ret = ov2775_write_reg(sensor, 0x3372, (gr_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3373, gr_gain & 0xff); + } + if(sensor->wb.gb_gain != wb->gb_gain){ + + ret = ov2775_write_reg(sensor, 0x3374, (gb_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3375, gb_gain & 0xff); + } + if(sensor->wb.b_gain != wb->b_gain){ + + ret = ov2775_write_reg(sensor, 0x3376, (b_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3377, b_gain & 0xff); + } + + if((sensor->wb.gr_gain != wb->gr_gain) || + (sensor->wb.r_gain != wb->r_gain) || + (sensor->wb.b_gain != wb->b_gain) || + (sensor->wb.gb_gain != wb->gb_gain)){ + + ov2775_s_blc(sensor,&sensor->blc); + } + + memcpy(&sensor->wb,wb,sizeof(sensor_white_balance_t)); + + return ret; +} + +int ov2775_get_expand_curve(struct ov2775 *sensor, sensor_expand_curve_t* pexpand_curve) +{ + int i; + if ((pexpand_curve->x_bit) == 12 && (pexpand_curve->y_bit == 16)) + { + uint8_t expand_px[64] = {6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, + 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, + 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, + 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6}; + + memcpy(pexpand_curve->expand_px,expand_px,sizeof(expand_px)); + + pexpand_curve->expand_x_data[0] = 0; + pexpand_curve->expand_y_data[0] = 0; + for(i = 1; i<65; i++) + { + pexpand_curve->expand_x_data[i] = (1 << pexpand_curve->expand_px[i-1]) + pexpand_curve->expand_x_data[i-1]; + + if (pexpand_curve->expand_x_data[i] < 512) + { + pexpand_curve->expand_y_data[i] = pexpand_curve->expand_x_data[i] << 1; + + }else if (pexpand_curve->expand_x_data[i] < 768) + { + pexpand_curve->expand_y_data[i] = (pexpand_curve->expand_x_data[i] - 256) << 2 ; + + }else if (pexpand_curve->expand_x_data[i] < 2560) + { + pexpand_curve->expand_y_data[i] = (pexpand_curve->expand_x_data[i] - 512) << 3 ; + + }else + { + pexpand_curve->expand_y_data[i] = (pexpand_curve->expand_x_data[i] - 2048) << 5; + } + } + return 0; + } + return -1; +} + +/* +Use USER_TO_KERNEL/KERNEL_TO_USER to fix "uaccess" exception on run time. +Also, use "copy_ret" to fix the build issue as below. +error: ignoring return value of function declared with 'warn_unused_result' attribute. +*/ + +#ifdef CONFIG_HARDENED_USERCOPY +#define USER_TO_KERNEL(TYPE) \ + do {\ + TYPE tmp; \ + unsigned long copy_ret; \ + arg = (void *)(&tmp); \ + copy_ret = copy_from_user(arg, arg_user, sizeof(TYPE));\ + } while (0) + +#define KERNEL_TO_USER(TYPE) \ + do {\ + unsigned long copy_ret; \ + copy_ret = copy_to_user(arg_user, arg, sizeof(TYPE));\ + } while (0) +#else +#define USER_TO_KERNEL(TYPE) +#define KERNEL_TO_USER(TYPE) +#endif + +long ov2775_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg_user) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + struct vvcam_sccb_data reg; + int ret = 0; + void *arg = arg_user; + + /* pr_info("enter %s\n", __func__); */ + mutex_lock(&sensor->lock); + switch (cmd) { + case VVSENSORIOC_WRITE_REG: { + USER_TO_KERNEL(struct vvcam_sccb_data); + reg = *(struct vvcam_sccb_data *)arg; + ret = ov2775_write_reg(sensor, reg.addr, (u8)reg.data) < 0; + break; + } + case VVSENSORIOC_READ_REG: { + struct vvcam_sccb_data *preg; + u8 val; + USER_TO_KERNEL(struct vvcam_sccb_data); + preg = (struct vvcam_sccb_data *)arg; + ret = ov2775_read_reg(sensor, (u16) preg->addr, &val) < 0; + preg->data = val; + KERNEL_TO_USER(struct vvcam_sccb_data); + break; + } + case VVSENSORIOC_S_STREAM: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_stream(sd, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_LONG_EXP: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_long_exp(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_EXP: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_exp(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_VSEXP: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_vsexp(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_LONG_GAIN:{ + USER_TO_KERNEL(__u32); + ret = ov2775_s_long_gain(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_GAIN: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_gain(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_VSGAIN: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_vsgain(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_FPS: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_fps(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_G_FPS: { + USER_TO_KERNEL(__u32); + ret = ov2775_g_fps(sensor, (__u32 *)arg); + KERNEL_TO_USER(__u32); + break; + } + case VVSENSORIOC_S_CLK: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_clk(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_G_CLK: { + USER_TO_KERNEL(__u32); + ret = ov2775_g_clk(sensor, (__u32 *)arg); + KERNEL_TO_USER(__u32); + break; + } + case VIDIOC_QUERYCAP: + ret = ov2775_ioc_qcap(sensor, arg); + break; + + case VVSENSORIOC_G_CHIP_ID: { + USER_TO_KERNEL(__u32); + ret = ov2775_g_chipid(sensor, (__u32 *)arg); + ret = (ret < 0) ? -1 : 0; + KERNEL_TO_USER(__u32); + break; + } + case VVSENSORIOC_G_RESERVE_ID: { + __u32 correct_id = 0x2770; + ret = copy_to_user(arg_user, &correct_id, sizeof(__u32)); + ret = ret ? -1 : 0; + break; + } + case VVSENSORIOC_S_HDR_MODE: { + USER_TO_KERNEL(int); + ret = ov2775_s_hdr(sensor, *(int *)arg); + break; + } + case VVSENSORIOC_QUERY: { + //USER_TO_KERNEL(struct vvcam_mode_info_array); + ret = ov2775_ioc_query_mode(sensor, arg); + //KERNEL_TO_USER(struct vvcam_mode_info_array); + break; + } + case VVSENSORIOC_G_SENSOR_MODE:{ + USER_TO_KERNEL(struct vvcam_mode_info); + ret = ov2775_g_mode(sensor, arg); + KERNEL_TO_USER(struct vvcam_mode_info); + break; + } + case VVSENSORIOC_S_WB: { + USER_TO_KERNEL(sensor_white_balance_t); + ret = ov2775_s_wb(sensor,arg); + break; + } + case VVSENSORIOC_S_BLC: { + USER_TO_KERNEL(sensor_blc_t); + ret = ov2775_s_blc(sensor,arg); + break; + } + case VVSENSORIOC_G_EXPAND_CURVE:{ + //USER_TO_KERNEL(sensor_expand_curve_t); + ret = ov2775_get_expand_curve(sensor, arg); + //KERNEL_TO_USER(sensor_expand_curve_t); + break; + } + case VVSENSORIOC_S_SENSOR_MODE: { + USER_TO_KERNEL(struct vvcam_mode_info); + ret = ov2775_s_sensor_mode(sensor, arg); + KERNEL_TO_USER(struct vvcam_mode_info); + break; + } + default: + pr_err("unsupported ov2775 command %d.", cmd); + ret = -1; + break; + } + mutex_unlock(&sensor->lock); + + return ret; +} diff --git a/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p.h b/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p.h new file mode 100755 index 0000000..853f999 --- /dev/null +++ b/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p.h @@ -0,0 +1,1879 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OV2775_REGS_1080P_H_ +#define _VVCAM_OV2775_REGS_1080P_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t ov2775_init_setting_1080p[] = { + {0x3000, 0x02, 0, 0}, + {0x3001, 0x28, 0, 0}, + {0x3002, 0x03, 0, 0}, + {0x3003, 0x01, 0, 0}, + {0x3004, 0x02, 0, 0}, + {0x3005, 0x1e, 0, 0},//768Mbps //{0x3005, 0x26, 0, 0},//960Mbps + {0x3006, 0x00, 0, 0}, + {0x3007, 0x07, 0, 0},//96MHz + {0x3008, 0x01, 0, 0}, + {0x3009, 0x00, 0, 0}, + {0x300c, 0x6c, 0, 0}, + {0x300e, 0x80, 0, 0}, + {0x300f, 0x00, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3013, 0x00, 0, 0}, + {0x3014, 0xc4, 0, 0}, + {0x3015, 0x00, 0, 0}, + {0x3017, 0x00, 0, 0}, + {0x3018, 0x00, 0, 0}, + {0x3019, 0x00, 0, 0}, + {0x301a, 0x00, 0, 0}, + {0x301b, 0x0e, 0, 0}, + {0x301e, 0x17, 0, 0}, + {0x301f, 0xe1, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x3031, 0x62, 0, 0}, + {0x3032, 0xf0, 0, 0}, + {0x3033, 0x30, 0, 0}, + {0x3034, 0x3f, 0, 0}, + {0x3035, 0x5f, 0, 0}, + {0x3036, 0x02, 0, 0}, + {0x3037, 0x9f, 0, 0}, + {0x3038, 0x04, 0, 0}, + {0x3039, 0xb7, 0, 0}, + {0x303a, 0x04, 0, 0}, + {0x303b, 0x07, 0, 0}, + {0x303c, 0xf0, 0, 0}, + {0x303d, 0x00, 0, 0}, + {0x303e, 0x0b, 0, 0}, + {0x303f, 0xe3, 0, 0}, + {0x3040, 0xf3, 0, 0}, + {0x3041, 0x29, 0, 0}, + {0x3042, 0xf6, 0, 0}, + {0x3043, 0x65, 0, 0}, + {0x3044, 0x06, 0, 0}, + {0x3045, 0x0f, 0, 0}, + {0x3046, 0x59, 0, 0}, + {0x3047, 0x07, 0, 0}, + {0x3048, 0x82, 0, 0}, + {0x3049, 0xcf, 0, 0}, + {0x304a, 0x12, 0, 0}, + {0x304b, 0x40, 0, 0}, + {0x304c, 0x33, 0, 0}, + {0x304d, 0xa4, 0, 0}, + {0x304e, 0x0b, 0, 0}, + {0x304f, 0x3d, 0, 0}, + {0x3050, 0x10, 0, 0}, + {0x3060, 0x00, 0, 0}, + {0x3061, 0x64, 0, 0}, + {0x3062, 0x00, 0, 0}, + {0x3063, 0xe4, 0, 0}, + {0x3066, 0x80, 0, 0}, + {0x3080, 0x00, 0, 0}, + {0x3081, 0x00, 0, 0}, + {0x3082, 0x01, 0, 0}, + {0x3083, 0xe3, 0, 0}, + {0x3084, 0x06, 0, 0}, + {0x3085, 0x00, 0, 0}, + {0x3086, 0x10, 0, 0}, + {0x3087, 0x10, 0, 0}, + {0x3089, 0x00, 0, 0}, + {0x308a, 0x01, 0, 0}, + {0x3093, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x00, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x00, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x90, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x48, 0, 0}, + {0x30b0, 0x04, 0, 0}, + {0x30b1, 0x7e, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x65, 0, 0}, + {0x30b4, 0x00, 0, 0}, + {0x30b5, 0x00, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x10, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x02, 0, 0}, + {0x30ba, 0x10, 0, 0}, + {0x30bb, 0x00, 0, 0}, + {0x30bc, 0x00, 0, 0}, + {0x30bd, 0x03, 0, 0}, + {0x30be, 0x5c, 0, 0}, + {0x30bf, 0x00, 0, 0}, + {0x30c0, 0x05, 0, 0}, + {0x30c1, 0x00, 0, 0}, + {0x30c2, 0x20, 0, 0}, + {0x30c3, 0x00, 0, 0}, + {0x30c4, 0x4a, 0, 0}, + {0x30c5, 0x00, 0, 0}, + {0x30c7, 0x00, 0, 0}, + {0x30c8, 0x00, 0, 0}, + {0x30d1, 0x00, 0, 0}, + {0x30d2, 0x00, 0, 0}, + {0x30d3, 0x80, 0, 0}, + {0x30d4, 0x00, 0, 0}, + {0x30d9, 0x09, 0, 0}, + {0x30da, 0x64, 0, 0}, + {0x30dd, 0x00, 0, 0}, + {0x30de, 0x16, 0, 0}, + {0x30df, 0x00, 0, 0}, + {0x30e0, 0x17, 0, 0}, + {0x30e1, 0x00, 0, 0}, + {0x30e2, 0x18, 0, 0}, + {0x30e3, 0x10, 0, 0}, + {0x30e4, 0x04, 0, 0}, + {0x30e5, 0x00, 0, 0}, + {0x30e6, 0x00, 0, 0}, + {0x30e7, 0x00, 0, 0}, + {0x30e8, 0x00, 0, 0}, + {0x30e9, 0x00, 0, 0}, + {0x30ea, 0x00, 0, 0}, + {0x30eb, 0x00, 0, 0}, + {0x30ec, 0x00, 0, 0}, + {0x30ed, 0x00, 0, 0}, + {0x3101, 0x00, 0, 0}, + {0x3102, 0x00, 0, 0}, + {0x3103, 0x00, 0, 0}, + {0x3104, 0x00, 0, 0}, + {0x3105, 0x8c, 0, 0}, + {0x3106, 0x87, 0, 0}, + {0x3107, 0xc0, 0, 0}, + {0x3108, 0x9d, 0, 0}, + {0x3109, 0x8d, 0, 0}, + {0x310a, 0x8d, 0, 0}, + {0x310b, 0x6a, 0, 0}, + {0x310c, 0x3a, 0, 0}, + {0x310d, 0x5a, 0, 0}, + {0x310e, 0x00, 0, 0}, + {0x3120, 0x00, 0, 0}, + {0x3121, 0x00, 0, 0}, + {0x3122, 0x00, 0, 0}, + {0x3123, 0xf0, 0, 0}, + {0x3124, 0x00, 0, 0}, + {0x3125, 0x70, 0, 0}, + {0x3126, 0x1f, 0, 0}, + {0x3127, 0x0f, 0, 0}, + {0x3128, 0x00, 0, 0}, + {0x3129, 0x3a, 0, 0}, + {0x312a, 0x02, 0, 0}, + {0x312b, 0x0f, 0, 0}, + {0x312c, 0x00, 0, 0}, + {0x312d, 0x0f, 0, 0}, + {0x312e, 0x1d, 0, 0}, + {0x312f, 0x00, 0, 0}, + {0x3130, 0x00, 0, 0}, + {0x3131, 0x00, 0, 0}, + {0x3132, 0x00, 0, 0}, + {0x3140, 0x0a, 0, 0}, + {0x3141, 0x03, 0, 0}, + {0x3142, 0x00, 0, 0}, + {0x3143, 0x00, 0, 0}, + {0x3144, 0x00, 0, 0}, + {0x3145, 0x00, 0, 0}, + {0x3146, 0x00, 0, 0}, + {0x3147, 0x00, 0, 0}, + {0x3148, 0x00, 0, 0}, + {0x3149, 0x00, 0, 0}, + {0x314a, 0x00, 0, 0}, + {0x314b, 0x00, 0, 0}, + {0x314c, 0x00, 0, 0}, + {0x314d, 0x00, 0, 0}, + {0x314e, 0x1c, 0, 0}, + {0x314f, 0xff, 0, 0}, + {0x3150, 0xff, 0, 0}, + {0x3151, 0xff, 0, 0}, + {0x3152, 0x10, 0, 0}, + {0x3153, 0x10, 0, 0}, + {0x3154, 0x10, 0, 0}, + {0x3155, 0x00, 0, 0}, + {0x3156, 0x03, 0, 0}, + {0x3157, 0x00, 0, 0}, + {0x3158, 0x0f, 0, 0}, + {0x3159, 0xff, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x00, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x00, 0, 0}, + {0x3160, 0x00, 0, 0}, + {0x3161, 0x40, 0, 0}, + {0x3162, 0x00, 0, 0}, + {0x3163, 0x40, 0, 0}, + {0x3164, 0x00, 0, 0}, + {0x3165, 0x40, 0, 0}, + {0x3190, 0x08, 0, 0}, + {0x3191, 0x99, 0, 0}, + {0x3193, 0x08, 0, 0}, + {0x3194, 0x13, 0, 0}, + {0x3195, 0x33, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x10, 0, 0}, + {0x3198, 0x00, 0, 0}, + {0x3199, 0x7f, 0, 0}, + {0x319a, 0x80, 0, 0}, + {0x319b, 0xff, 0, 0}, + {0x319c, 0x80, 0, 0}, + {0x319d, 0xbf, 0, 0}, + {0x319e, 0xc0, 0, 0}, + {0x319f, 0xff, 0, 0}, + {0x31a0, 0x24, 0, 0}, + {0x31a1, 0x55, 0, 0}, + {0x31a2, 0x00, 0, 0}, + {0x31a3, 0x00, 0, 0}, + {0x31a6, 0x00, 0, 0}, + {0x31a7, 0x00, 0, 0}, + {0x31b0, 0x00, 0, 0}, + {0x31b1, 0x00, 0, 0}, + {0x31b2, 0x02, 0, 0}, + {0x31b3, 0x00, 0, 0}, + {0x31b4, 0x00, 0, 0}, + {0x31b5, 0x01, 0, 0}, + {0x31b6, 0x00, 0, 0}, + {0x31b7, 0x00, 0, 0}, + {0x31b8, 0x00, 0, 0}, + {0x31b9, 0x00, 0, 0}, + {0x31ba, 0x00, 0, 0}, + {0x31d0, 0x3c, 0, 0}, + {0x31d1, 0x34, 0, 0}, + {0x31d2, 0x3c, 0, 0}, + {0x31d3, 0x00, 0, 0}, + {0x31d4, 0x2d, 0, 0}, + {0x31d5, 0x00, 0, 0}, + {0x31d6, 0x01, 0, 0}, + {0x31d7, 0x06, 0, 0}, + {0x31d8, 0x00, 0, 0}, + {0x31d9, 0x64, 0, 0}, + {0x31da, 0x00, 0, 0}, + {0x31db, 0x30, 0, 0}, + {0x31dc, 0x04, 0, 0}, + {0x31dd, 0x69, 0, 0}, + {0x31de, 0x0a, 0, 0}, + {0x31df, 0x3c, 0, 0}, + {0x31e0, 0x04, 0, 0}, + {0x31e1, 0x32, 0, 0}, + {0x31e2, 0x00, 0, 0}, + {0x31e3, 0x00, 0, 0}, + {0x31e4, 0x08, 0, 0}, + {0x31e5, 0x80, 0, 0}, + {0x31e6, 0x00, 0, 0}, + {0x31e7, 0x2c, 0, 0}, + {0x31e8, 0x6c, 0, 0}, + {0x31e9, 0xac, 0, 0}, + {0x31ea, 0xec, 0, 0}, + {0x31eb, 0x3f, 0, 0}, + {0x31ec, 0x07, 0, 0}, + {0x31ed, 0x80, 0, 0}, + {0x31ee, 0x04, 0, 0}, + {0x31ef, 0x38, 0, 0}, + {0x31f0, 0x07, 0, 0}, + {0x31f1, 0x80, 0, 0}, + {0x31f2, 0x04, 0, 0}, + {0x31f3, 0x38, 0, 0}, + {0x31f4, 0x07, 0, 0}, + {0x31f5, 0x80, 0, 0}, + {0x31f6, 0x04, 0, 0}, + {0x31f7, 0x38, 0, 0}, + {0x31f8, 0x07, 0, 0}, + {0x31f9, 0x80, 0, 0}, + {0x31fa, 0x04, 0, 0}, + {0x31fb, 0x38, 0, 0}, + {0x31fd, 0xcb, 0, 0}, + {0x31fe, 0x0f, 0, 0}, + {0x31ff, 0x03, 0, 0}, + {0x3200, 0x00, 0, 0}, + {0x3201, 0xff, 0, 0}, + {0x3202, 0x00, 0, 0}, + {0x3203, 0xff, 0, 0}, + {0x3204, 0xff, 0, 0}, + {0x3205, 0xff, 0, 0}, + {0x3206, 0xff, 0, 0}, + {0x3207, 0xff, 0, 0}, + {0x3208, 0xff, 0, 0}, + {0x3209, 0xff, 0, 0}, + {0x320a, 0xff, 0, 0}, + {0x320b, 0x1b, 0, 0}, + {0x320c, 0x1f, 0, 0}, + {0x320d, 0x1e, 0, 0}, + {0x320e, 0x30, 0, 0}, + {0x320f, 0x2d, 0, 0}, + {0x3210, 0x2c, 0, 0}, + {0x3211, 0x2b, 0, 0}, + {0x3212, 0x2a, 0, 0}, + {0x3213, 0x24, 0, 0}, + {0x3214, 0x22, 0, 0}, + {0x3215, 0x00, 0, 0}, + {0x3216, 0x04, 0, 0}, + {0x3217, 0x2c, 0, 0}, + {0x3218, 0x6c, 0, 0}, + {0x3219, 0xac, 0, 0}, + {0x321a, 0xec, 0, 0}, + {0x321b, 0x00, 0, 0}, + {0x3230, 0x3a, 0, 0}, + {0x3231, 0x00, 0, 0}, + {0x3232, 0x80, 0, 0}, + {0x3233, 0x00, 0, 0}, + {0x3234, 0x10, 0, 0}, + {0x3235, 0xaa, 0, 0}, + {0x3236, 0x55, 0, 0}, + {0x3237, 0x99, 0, 0}, + {0x3238, 0x66, 0, 0}, + {0x3239, 0x08, 0, 0}, + {0x323a, 0x88, 0, 0}, + {0x323b, 0x00, 0, 0}, + {0x323c, 0x00, 0, 0}, + {0x323d, 0x03, 0, 0}, + {0x3250, 0x33, 0, 0}, + {0x3251, 0x00, 0, 0}, + {0x3252, 0x20, 0, 0}, + {0x3253, 0x00, 0, 3}, + {0x3254, 0x00, 0, 0}, + {0x3255, 0x01, 0, 0}, + {0x3256, 0x00, 0, 0}, + {0x3257, 0x00, 0, 0}, + {0x3258, 0x00, 0, 0}, + {0x3270, 0x01, 0, 0}, + {0x3271, 0x60, 0, 0}, + {0x3272, 0xc0, 0, 0}, + {0x3273, 0x00, 0, 0}, + {0x3274, 0x80, 0, 0}, + {0x3275, 0x40, 0, 0}, + {0x3276, 0x02, 0, 0}, + {0x3277, 0x08, 0, 0}, + {0x3278, 0x10, 0, 0}, + {0x3279, 0x04, 0, 0}, + {0x327a, 0x00, 0, 0}, + {0x327b, 0x03, 0, 0}, + {0x327c, 0x10, 0, 0}, + {0x327d, 0x60, 0, 0}, + {0x327e, 0xc0, 0, 0}, + {0x327f, 0x06, 0, 0}, + {0x3288, 0x10, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x08, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x04, 0, 0}, + {0x328d, 0x00, 0, 0}, + {0x328e, 0x02, 0, 0}, + {0x328f, 0x00, 0, 0}, + {0x3290, 0x20, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x10, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x08, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x04, 0, 0}, + {0x3297, 0x00, 0, 0}, + {0x3298, 0x40, 0, 0}, + {0x3299, 0x00, 0, 0}, + {0x329a, 0x20, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x10, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x08, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x40, 0, 0}, + {0x32a3, 0x00, 0, 0}, + {0x32a4, 0x20, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x10, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32a8, 0x00, 0, 0}, + {0x32a9, 0x00, 0, 0}, + {0x32aa, 0x00, 0, 0}, + {0x32ab, 0x00, 0, 0}, + {0x32ac, 0x00, 0, 0}, + {0x32ad, 0x00, 0, 0}, + {0x32ae, 0x00, 0, 0}, + {0x32af, 0x00, 0, 0}, + {0x32b0, 0x00, 0, 0}, + {0x32b1, 0x00, 0, 0}, + {0x32b2, 0x00, 0, 0}, + {0x32b3, 0x00, 0, 0}, + {0x32b4, 0x00, 0, 0}, + {0x32b5, 0x00, 0, 0}, + {0x32b6, 0x00, 0, 0}, + {0x32b7, 0x00, 0, 0}, + {0x32b8, 0x00, 0, 0}, + {0x32b9, 0x00, 0, 0}, + {0x32ba, 0x00, 0, 0}, + {0x32bb, 0x00, 0, 0}, + {0x32bc, 0x00, 0, 0}, + {0x32bd, 0x00, 0, 0}, + {0x32be, 0x00, 0, 0}, + {0x32bf, 0x00, 0, 0}, + {0x32c0, 0x00, 0, 0}, + {0x32c1, 0x00, 0, 0}, + {0x32c2, 0x00, 0, 0}, + {0x32c3, 0x00, 0, 0}, + {0x32c4, 0x00, 0, 0}, + {0x32c5, 0x00, 0, 0}, + {0x32c6, 0x00, 0, 0}, + {0x32c7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x32c9, 0x00, 0, 0}, + {0x3330, 0x03, 0, 0}, + {0x3331, 0xc8, 0, 0}, + {0x3332, 0x02, 0, 0}, + {0x3333, 0x24, 0, 0}, + {0x3334, 0x00, 0, 0}, + {0x3335, 0x00, 0, 0}, + {0x3336, 0x00, 0, 0}, + {0x3337, 0x00, 0, 0}, + {0x3338, 0x03, 0, 0}, + {0x3339, 0xc8, 0, 0}, + {0x333a, 0x02, 0, 0}, + {0x333b, 0x24, 0, 0}, + {0x333c, 0x00, 0, 0}, + {0x333d, 0x00, 0, 0}, + {0x333e, 0x00, 0, 0}, + {0x333f, 0x00, 0, 0}, + {0x3340, 0x03, 0, 0}, + {0x3341, 0xc8, 0, 0}, + {0x3342, 0x02, 0, 0}, + {0x3343, 0x24, 0, 0}, + {0x3344, 0x00, 0, 0}, + {0x3345, 0x00, 0, 0}, + {0x3346, 0x00, 0, 0}, + {0x3347, 0x00, 0, 0}, + {0x3348, 0x40, 0, 0}, + {0x3349, 0x00, 0, 0}, + {0x334a, 0x00, 0, 0}, + {0x334b, 0x00, 0, 0}, + {0x334c, 0x00, 0, 0}, + {0x334d, 0x00, 0, 0}, + {0x334e, 0x80, 0, 0}, + {0x3360, 0x01, 0, 0}, + {0x3361, 0x00, 0, 0}, + {0x3362, 0x01, 0, 0}, + {0x3363, 0x00, 0, 0}, + {0x3364, 0x01, 0, 0}, + {0x3365, 0x00, 0, 0}, + {0x3366, 0x01, 0, 0}, + {0x3367, 0x00, 0, 0}, + {0x3368, 0x01, 0, 0}, + {0x3369, 0x00, 0, 0}, + {0x336a, 0x01, 0, 0}, + {0x336b, 0x00, 0, 0}, + {0x336c, 0x01, 0, 0}, + {0x336d, 0x00, 0, 0}, + {0x336e, 0x01, 0, 0}, + {0x336f, 0x00, 0, 0}, + {0x3370, 0x01, 0, 0}, + {0x3371, 0x00, 0, 0}, + {0x3372, 0x01, 0, 0}, + {0x3373, 0x00, 0, 0}, + {0x3374, 0x01, 0, 0}, + {0x3375, 0x00, 0, 0}, + {0x3376, 0x01, 0, 0}, + {0x3377, 0x00, 0, 0}, + {0x3378, 0x00, 0, 0}, + {0x3379, 0x00, 0, 0}, + {0x337a, 0x00, 0, 0}, + {0x337b, 0x00, 0, 0}, + {0x337c, 0x00, 0, 0}, + {0x337d, 0x00, 0, 0}, + {0x337e, 0x00, 0, 0}, + {0x337f, 0x00, 0, 0}, + {0x3380, 0x00, 0, 0}, + {0x3381, 0x00, 0, 0}, + {0x3382, 0x00, 0, 0}, + {0x3383, 0x00, 0, 0}, + {0x3384, 0x00, 0, 0}, + {0x3385, 0x00, 0, 0}, + {0x3386, 0x00, 0, 0}, + {0x3387, 0x00, 0, 0}, + {0x3388, 0x00, 0, 0}, + {0x3389, 0x00, 0, 0}, + {0x338a, 0x00, 0, 0}, + {0x338b, 0x00, 0, 0}, + {0x338c, 0x00, 0, 0}, + {0x338d, 0x00, 0, 0}, + {0x338e, 0x00, 0, 0}, + {0x338f, 0x00, 0, 0}, + {0x3390, 0x00, 0, 0}, + {0x3391, 0x00, 0, 0}, + {0x3392, 0x00, 0, 0}, + {0x3393, 0x00, 0, 0}, + {0x3394, 0x00, 0, 0}, + {0x3395, 0x00, 0, 0}, + {0x3396, 0x00, 0, 0}, + {0x3397, 0x00, 0, 0}, + {0x3398, 0x00, 0, 0}, + {0x3399, 0x00, 0, 0}, + {0x339a, 0x00, 0, 0}, + {0x339b, 0x00, 0, 0}, + {0x33b0, 0x00, 0, 0}, + {0x33b1, 0x50, 0, 0}, + {0x33b2, 0x01, 0, 0}, + {0x33b3, 0xff, 0, 0}, + {0x33b4, 0xe0, 0, 0}, + {0x33b5, 0x6b, 0, 0}, + {0x33b6, 0x00, 0, 0}, + {0x33b7, 0x00, 0, 0}, + {0x33b8, 0x00, 0, 0}, + {0x33b9, 0x00, 0, 0}, + {0x33ba, 0x00, 0, 0}, + {0x33bb, 0x1f, 0, 0}, + {0x33bc, 0x01, 0, 0}, + {0x33bd, 0x01, 0, 0}, + {0x33be, 0x01, 0, 0}, + {0x33bf, 0x01, 0, 0}, + {0x33c0, 0x00, 0, 0}, + {0x33c1, 0x00, 0, 0}, + {0x33c2, 0x00, 0, 0}, + {0x33c3, 0x00, 0, 0}, + {0x33e0, 0x14, 0, 0}, + {0x33e1, 0x0f, 0, 0}, + {0x33e2, 0x02, 0, 0}, + {0x33e3, 0x01, 0, 0}, + {0x33e4, 0x01, 0, 0}, + {0x33e5, 0x01, 0, 0}, + {0x33e6, 0x00, 0, 0}, + {0x33e7, 0x04, 0, 0}, + {0x33e8, 0x0c, 0, 0}, + {0x33e9, 0x02, 0, 0}, + {0x33ea, 0x02, 0, 0}, + {0x33eb, 0x02, 0, 0}, + {0x33ec, 0x03, 0, 0}, + {0x33ed, 0x01, 0, 0}, + {0x33ee, 0x02, 0, 0}, + {0x33ef, 0x08, 0, 0}, + {0x33f0, 0x08, 0, 0}, + {0x33f1, 0x04, 0, 0}, + {0x33f2, 0x04, 0, 0}, + {0x33f3, 0x00, 0, 0}, + {0x33f4, 0x03, 0, 0}, + {0x33f5, 0x14, 0, 0}, + {0x33f6, 0x0f, 0, 0}, + {0x33f7, 0x02, 0, 0}, + {0x33f8, 0x01, 0, 0}, + {0x33f9, 0x01, 0, 0}, + {0x33fa, 0x01, 0, 0}, + {0x33fb, 0x00, 0, 0}, + {0x33fc, 0x04, 0, 0}, + {0x33fd, 0x0c, 0, 0}, + {0x33fe, 0x02, 0, 0}, + {0x33ff, 0x02, 0, 0}, + {0x3400, 0x02, 0, 0}, + {0x3401, 0x03, 0, 0}, + {0x3402, 0x01, 0, 0}, + {0x3403, 0x02, 0, 0}, + {0x3404, 0x08, 0, 0}, + {0x3405, 0x08, 0, 0}, + {0x3406, 0x04, 0, 0}, + {0x3407, 0x04, 0, 0}, + {0x3408, 0x00, 0, 0}, + {0x3409, 0x03, 0, 0}, + {0x340a, 0x14, 0, 0}, + {0x340b, 0x0f, 0, 0}, + {0x340c, 0x04, 0, 0}, + {0x340d, 0x02, 0, 0}, + {0x340e, 0x01, 0, 0}, + {0x340f, 0x01, 0, 0}, + {0x3410, 0x00, 0, 0}, + {0x3411, 0x04, 0, 0}, + {0x3412, 0x0c, 0, 0}, + {0x3413, 0x02, 0, 0}, + {0x3414, 0x02, 0, 0}, + {0x3415, 0x02, 0, 0}, + {0x3416, 0x03, 0, 0}, + {0x3417, 0x02, 0, 0}, + {0x3418, 0x05, 0, 0}, + {0x3419, 0x0a, 0, 0}, + {0x341a, 0x08, 0, 0}, + {0x341b, 0x04, 0, 0}, + {0x341c, 0x04, 0, 0}, + {0x341d, 0x00, 0, 0}, + {0x341e, 0x03, 0, 0}, + {0x3440, 0x00, 0, 0}, + {0x3441, 0x00, 0, 0}, + {0x3442, 0x00, 0, 0}, + {0x3443, 0x00, 0, 0}, + {0x3444, 0x02, 0, 0}, + {0x3445, 0xf0, 0, 0}, + {0x3446, 0x02, 0, 0}, + {0x3447, 0x08, 0, 0}, + {0x3448, 0x00, 0, 0}, + {0x3460, 0x40, 0, 0}, + {0x3461, 0x40, 0, 0}, + {0x3462, 0x40, 0, 0}, + {0x3463, 0x40, 0, 0}, + {0x3464, 0x03, 0, 0}, + {0x3465, 0x01, 0, 0}, + {0x3466, 0x01, 0, 0}, + {0x3467, 0x02, 0, 0}, + {0x3468, 0x30, 0, 0}, + {0x3469, 0x00, 0, 0}, + {0x346a, 0x33, 0, 0}, + {0x346b, 0xbf, 0, 0}, + {0x3480, 0x40, 0, 0}, + {0x3481, 0x00, 0, 0}, + {0x3482, 0x00, 0, 0}, + {0x3483, 0x00, 0, 0}, + {0x3484, 0x0d, 0, 0}, + {0x3485, 0x00, 0, 0}, + {0x3486, 0x00, 0, 0}, + {0x3487, 0x00, 0, 0}, + {0x3488, 0x00, 0, 0}, + {0x3489, 0x00, 0, 0}, + {0x348a, 0x00, 0, 0}, + {0x348b, 0x04, 0, 0}, + {0x348c, 0x00, 0, 0}, + {0x348d, 0x01, 0, 0}, + {0x348f, 0x01, 0, 0}, + {0x3030, 0x0a, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x7000, 0x58, 0, 0}, + {0x7001, 0x7a, 0, 0}, + {0x7002, 0x1a, 0, 0}, + {0x7003, 0xc1, 0, 0}, + {0x7004, 0x03, 0, 0}, + {0x7005, 0xda, 0, 0}, + {0x7006, 0xbd, 0, 0}, + {0x7007, 0x03, 0, 0}, + {0x7008, 0xbd, 0, 0}, + {0x7009, 0x06, 0, 0}, + {0x700a, 0xe6, 0, 0}, + {0x700b, 0xec, 0, 0}, + {0x700c, 0xbc, 0, 0}, + {0x700d, 0xff, 0, 0}, + {0x700e, 0xbc, 0, 0}, + {0x700f, 0x73, 0, 0}, + {0x7010, 0xda, 0, 0}, + {0x7011, 0x72, 0, 0}, + {0x7012, 0x76, 0, 0}, + {0x7013, 0xb6, 0, 0}, + {0x7014, 0xee, 0, 0}, + {0x7015, 0xcf, 0, 0}, + {0x7016, 0xac, 0, 0}, + {0x7017, 0xd0, 0, 0}, + {0x7018, 0xac, 0, 0}, + {0x7019, 0xd1, 0, 0}, + {0x701a, 0x50, 0, 0}, + {0x701b, 0xac, 0, 0}, + {0x701c, 0xd2, 0, 0}, + {0x701d, 0xbc, 0, 0}, + {0x701e, 0x2e, 0, 0}, + {0x701f, 0xb4, 0, 0}, + {0x7020, 0x00, 0, 0}, + {0x7021, 0xdc, 0, 0}, + {0x7022, 0xdf, 0, 0}, + {0x7023, 0xb0, 0, 0}, + {0x7024, 0x6e, 0, 0}, + {0x7025, 0xbd, 0, 0}, + {0x7026, 0x01, 0, 0}, + {0x7027, 0xd7, 0, 0}, + {0x7028, 0xed, 0, 0}, + {0x7029, 0xe1, 0, 0}, + {0x702a, 0x36, 0, 0}, + {0x702b, 0x30, 0, 0}, + {0x702c, 0xd3, 0, 0}, + {0x702d, 0x2e, 0, 0}, + {0x702e, 0x54, 0, 0}, + {0x702f, 0x46, 0, 0}, + {0x7030, 0xbc, 0, 0}, + {0x7031, 0x22, 0, 0}, + {0x7032, 0x66, 0, 0}, + {0x7033, 0xbc, 0, 0}, + {0x7034, 0x24, 0, 0}, + {0x7035, 0x2c, 0, 0}, + {0x7036, 0x28, 0, 0}, + {0x7037, 0xbc, 0, 0}, + {0x7038, 0x3c, 0, 0}, + {0x7039, 0xa1, 0, 0}, + {0x703a, 0xac, 0, 0}, + {0x703b, 0xd8, 0, 0}, + {0x703c, 0xd6, 0, 0}, + {0x703d, 0xb4, 0, 0}, + {0x703e, 0x04, 0, 0}, + {0x703f, 0x46, 0, 0}, + {0x7040, 0xb7, 0, 0}, + {0x7041, 0x04, 0, 0}, + {0x7042, 0xbe, 0, 0}, + {0x7043, 0x08, 0, 0}, + {0x7044, 0xc3, 0, 0}, + {0x7045, 0xd9, 0, 0}, + {0x7046, 0xad, 0, 0}, + {0x7047, 0xc3, 0, 0}, + {0x7048, 0xbc, 0, 0}, + {0x7049, 0x19, 0, 0}, + {0x704a, 0xc1, 0, 0}, + {0x704b, 0x27, 0, 0}, + {0x704c, 0xe7, 0, 0}, + {0x704d, 0x00, 0, 0}, + {0x704e, 0x50, 0, 0}, + {0x704f, 0x20, 0, 0}, + {0x7050, 0xb8, 0, 0}, + {0x7051, 0x02, 0, 0}, + {0x7052, 0xbc, 0, 0}, + {0x7053, 0x17, 0, 0}, + {0x7054, 0xdb, 0, 0}, + {0x7055, 0xc7, 0, 0}, + {0x7056, 0xb8, 0, 0}, + {0x7057, 0x00, 0, 0}, + {0x7058, 0x28, 0, 0}, + {0x7059, 0x54, 0, 0}, + {0x705a, 0xb4, 0, 0}, + {0x705b, 0x14, 0, 0}, + {0x705c, 0xab, 0, 0}, + {0x705d, 0xbe, 0, 0}, + {0x705e, 0x06, 0, 0}, + {0x705f, 0xd8, 0, 0}, + {0x7060, 0xd6, 0, 0}, + {0x7061, 0x00, 0, 0}, + {0x7062, 0xb4, 0, 0}, + {0x7063, 0xc7, 0, 0}, + {0x7064, 0x07, 0, 0}, + {0x7065, 0xb9, 0, 0}, + {0x7066, 0x05, 0, 0}, + {0x7067, 0xee, 0, 0}, + {0x7068, 0xe6, 0, 0}, + {0x7069, 0xad, 0, 0}, + {0x706a, 0xb4, 0, 0}, + {0x706b, 0x26, 0, 0}, + {0x706c, 0x19, 0, 0}, + {0x706d, 0xc1, 0, 0}, + {0x706e, 0x3a, 0, 0}, + {0x706f, 0xc3, 0, 0}, + {0x7070, 0xaf, 0, 0}, + {0x7071, 0x00, 0, 0}, + {0x7072, 0xc0, 0, 0}, + {0x7073, 0x3c, 0, 0}, + {0x7074, 0xc3, 0, 0}, + {0x7075, 0xbe, 0, 0}, + {0x7076, 0xe7, 0, 0}, + {0x7077, 0x00, 0, 0}, + {0x7078, 0x15, 0, 0}, + {0x7079, 0xc2, 0, 0}, + {0x707a, 0x40, 0, 0}, + {0x707b, 0xc3, 0, 0}, + {0x707c, 0xa4, 0, 0}, + {0x707d, 0xc0, 0, 0}, + {0x707e, 0x3c, 0, 0}, + {0x707f, 0x00, 0, 0}, + {0x7080, 0xb9, 0, 0}, + {0x7081, 0x64, 0, 0}, + {0x7082, 0x29, 0, 0}, + {0x7083, 0x00, 0, 0}, + {0x7084, 0xb8, 0, 0}, + {0x7085, 0x12, 0, 0}, + {0x7086, 0xbe, 0, 0}, + {0x7087, 0x01, 0, 0}, + {0x7088, 0xd0, 0, 0}, + {0x7089, 0xbc, 0, 0}, + {0x708a, 0x01, 0, 0}, + {0x708b, 0xac, 0, 0}, + {0x708c, 0x37, 0, 0}, + {0x708d, 0xd2, 0, 0}, + {0x708e, 0xac, 0, 0}, + {0x708f, 0x45, 0, 0}, + {0x7090, 0xad, 0, 0}, + {0x7091, 0x28, 0, 0}, + {0x7092, 0x00, 0, 0}, + {0x7093, 0xb8, 0, 0}, + {0x7094, 0x00, 0, 0}, + {0x7095, 0xbc, 0, 0}, + {0x7096, 0x01, 0, 0}, + {0x7097, 0x36, 0, 0}, + {0x7098, 0xd3, 0, 0}, + {0x7099, 0x30, 0, 0}, + {0x709a, 0x04, 0, 0}, + {0x709b, 0xe0, 0, 0}, + {0x709c, 0xd8, 0, 0}, + {0x709d, 0xb4, 0, 0}, + {0x709e, 0xe9, 0, 0}, + {0x709f, 0x00, 0, 0}, + {0x70a0, 0xbe, 0, 0}, + {0x70a1, 0x05, 0, 0}, + {0x70a2, 0x62, 0, 0}, + {0x70a3, 0x07, 0, 0}, + {0x70a4, 0xb9, 0, 0}, + {0x70a5, 0x05, 0, 0}, + {0x70a6, 0xad, 0, 0}, + {0x70a7, 0xc3, 0, 0}, + {0x70a8, 0xcf, 0, 0}, + {0x70a9, 0x00, 0, 0}, + {0x70aa, 0x15, 0, 0}, + {0x70ab, 0xc2, 0, 0}, + {0x70ac, 0x59, 0, 0}, + {0x70ad, 0xc3, 0, 0}, + {0x70ae, 0xc9, 0, 0}, + {0x70af, 0xc0, 0, 0}, + {0x70b0, 0x55, 0, 0}, + {0x70b1, 0x00, 0, 0}, + {0x70b2, 0x46, 0, 0}, + {0x70b3, 0xa1, 0, 0}, + {0x70b4, 0xb9, 0, 0}, + {0x70b5, 0x64, 0, 0}, + {0x70b6, 0x29, 0, 0}, + {0x70b7, 0x00, 0, 0}, + {0x70b8, 0xb8, 0, 0}, + {0x70b9, 0x02, 0, 0}, + {0x70ba, 0xbe, 0, 0}, + {0x70bb, 0x02, 0, 0}, + {0x70bc, 0xd0, 0, 0}, + {0x70bd, 0xdc, 0, 0}, + {0x70be, 0xac, 0, 0}, + {0x70bf, 0xbc, 0, 0}, + {0x70c0, 0x01, 0, 0}, + {0x70c1, 0x37, 0, 0}, + {0x70c2, 0xac, 0, 0}, + {0x70c3, 0xd2, 0, 0}, + {0x70c4, 0x45, 0, 0}, + {0x70c5, 0xad, 0, 0}, + {0x70c6, 0x28, 0, 0}, + {0x70c7, 0x00, 0, 0}, + {0x70c8, 0xb8, 0, 0}, + {0x70c9, 0x00, 0, 0}, + {0x70ca, 0xbc, 0, 0}, + {0x70cb, 0x01, 0, 0}, + {0x70cc, 0x36, 0, 0}, + {0x70cd, 0x30, 0, 0}, + {0x70ce, 0xe0, 0, 0}, + {0x70cf, 0xd8, 0, 0}, + {0x70d0, 0xb5, 0, 0}, + {0x70d1, 0x0b, 0, 0}, + {0x70d2, 0xd6, 0, 0}, + {0x70d3, 0xbe, 0, 0}, + {0x70d4, 0x07, 0, 0}, + {0x70d5, 0x00, 0, 0}, + {0x70d6, 0x62, 0, 0}, + {0x70d7, 0x07, 0, 0}, + {0x70d8, 0xb9, 0, 0}, + {0x70d9, 0x05, 0, 0}, + {0x70da, 0xad, 0, 0}, + {0x70db, 0xc3, 0, 0}, + {0x70dc, 0xcf, 0, 0}, + {0x70dd, 0x46, 0, 0}, + {0x70de, 0xcd, 0, 0}, + {0x70df, 0x07, 0, 0}, + {0x70e0, 0xcd, 0, 0}, + {0x70e1, 0x00, 0, 0}, + {0x70e2, 0xe3, 0, 0}, + {0x70e3, 0x18, 0, 0}, + {0x70e4, 0xc2, 0, 0}, + {0x70e5, 0xa2, 0, 0}, + {0x70e6, 0xb9, 0, 0}, + {0x70e7, 0x64, 0, 0}, + {0x70e8, 0xd1, 0, 0}, + {0x70e9, 0xdd, 0, 0}, + {0x70ea, 0xac, 0, 0}, + {0x70eb, 0xcf, 0, 0}, + {0x70ec, 0xdf, 0, 0}, + {0x70ed, 0xb5, 0, 0}, + {0x70ee, 0x19, 0, 0}, + {0x70ef, 0x46, 0, 0}, + {0x70f0, 0x50, 0, 0}, + {0x70f1, 0xb6, 0, 0}, + {0x70f2, 0xee, 0, 0}, + {0x70f3, 0xe8, 0, 0}, + {0x70f4, 0xe6, 0, 0}, + {0x70f5, 0xbc, 0, 0}, + {0x70f6, 0x31, 0, 0}, + {0x70f7, 0xe1, 0, 0}, + {0x70f8, 0x36, 0, 0}, + {0x70f9, 0x30, 0, 0}, + {0x70fa, 0xd3, 0, 0}, + {0x70fb, 0x2e, 0, 0}, + {0x70fc, 0x54, 0, 0}, + {0x70fd, 0xbd, 0, 0}, + {0x70fe, 0x03, 0, 0}, + {0x70ff, 0xec, 0, 0}, + {0x7100, 0x2c, 0, 0}, + {0x7101, 0x50, 0, 0}, + {0x7102, 0x20, 0, 0}, + {0x7103, 0x04, 0, 0}, + {0x7104, 0xb8, 0, 0}, + {0x7105, 0x02, 0, 0}, + {0x7106, 0xbc, 0, 0}, + {0x7107, 0x18, 0, 0}, + {0x7108, 0xc7, 0, 0}, + {0x7109, 0xb8, 0, 0}, + {0x710a, 0x00, 0, 0}, + {0x710b, 0x28, 0, 0}, + {0x710c, 0x54, 0, 0}, + {0x710d, 0xbc, 0, 0}, + {0x710e, 0x02, 0, 0}, + {0x710f, 0xb4, 0, 0}, + {0x7110, 0xda, 0, 0}, + {0x7111, 0xbe, 0, 0}, + {0x7112, 0x04, 0, 0}, + {0x7113, 0xd6, 0, 0}, + {0x7114, 0xd8, 0, 0}, + {0x7115, 0xab, 0, 0}, + {0x7116, 0x00, 0, 0}, + {0x7117, 0x62, 0, 0}, + {0x7118, 0x07, 0, 0}, + {0x7119, 0xb9, 0, 0}, + {0x711a, 0x05, 0, 0}, + {0x711b, 0xad, 0, 0}, + {0x711c, 0xc3, 0, 0}, + {0x711d, 0xbc, 0, 0}, + {0x711e, 0xe7, 0, 0}, + {0x711f, 0xb9, 0, 0}, + {0x7120, 0x64, 0, 0}, + {0x7121, 0x29, 0, 0}, + {0x7122, 0x00, 0, 0}, + {0x7123, 0xb8, 0, 0}, + {0x7124, 0x02, 0, 0}, + {0x7125, 0xbe, 0, 0}, + {0x7126, 0x00, 0, 0}, + {0x7127, 0x45, 0, 0}, + {0x7128, 0xad, 0, 0}, + {0x7129, 0xe2, 0, 0}, + {0x712a, 0x28, 0, 0}, + {0x712b, 0x00, 0, 0}, + {0x712c, 0xb8, 0, 0}, + {0x712d, 0x00, 0, 0}, + {0x712e, 0xe0, 0, 0}, + {0x712f, 0xd8, 0, 0}, + {0x7130, 0xb4, 0, 0}, + {0x7131, 0xe9, 0, 0}, + {0x7132, 0xbe, 0, 0}, + {0x7133, 0x03, 0, 0}, + {0x7134, 0x00, 0, 0}, + {0x7135, 0x30, 0, 0}, + {0x7136, 0x62, 0, 0}, + {0x7137, 0x07, 0, 0}, + {0x7138, 0xb9, 0, 0}, + {0x7139, 0x05, 0, 0}, + {0x713a, 0xad, 0, 0}, + {0x713b, 0xc3, 0, 0}, + {0x713c, 0xcf, 0, 0}, + {0x713d, 0x42, 0, 0}, + {0x713e, 0xe4, 0, 0}, + {0x713f, 0xcd, 0, 0}, + {0x7140, 0x07, 0, 0}, + {0x7141, 0xcd, 0, 0}, + {0x7142, 0x00, 0, 0}, + {0x7143, 0x00, 0, 0}, + {0x7144, 0x17, 0, 0}, + {0x7145, 0xc2, 0, 0}, + {0x7146, 0xbb, 0, 0}, + {0x7147, 0xde, 0, 0}, + {0x7148, 0xcf, 0, 0}, + {0x7149, 0xdf, 0, 0}, + {0x714a, 0xac, 0, 0}, + {0x714b, 0xd1, 0, 0}, + {0x714c, 0x44, 0, 0}, + {0x714d, 0xac, 0, 0}, + {0x714e, 0xb9, 0, 0}, + {0x714f, 0x76, 0, 0}, + {0x7150, 0xb8, 0, 0}, + {0x7151, 0x08, 0, 0}, + {0x7152, 0xb6, 0, 0}, + {0x7153, 0xfe, 0, 0}, + {0x7154, 0xb4, 0, 0}, + {0x7155, 0xca, 0, 0}, + {0x7156, 0xd6, 0, 0}, + {0x7157, 0xd8, 0, 0}, + {0x7158, 0xab, 0, 0}, + {0x7159, 0x00, 0, 0}, + {0x715a, 0xe1, 0, 0}, + {0x715b, 0x36, 0, 0}, + {0x715c, 0x30, 0, 0}, + {0x715d, 0xd3, 0, 0}, + {0x715e, 0xbc, 0, 0}, + {0x715f, 0x29, 0, 0}, + {0x7160, 0xb4, 0, 0}, + {0x7161, 0x1f, 0, 0}, + {0x7162, 0xaa, 0, 0}, + {0x7163, 0xbd, 0, 0}, + {0x7164, 0x01, 0, 0}, + {0x7165, 0xb8, 0, 0}, + {0x7166, 0x0c, 0, 0}, + {0x7167, 0x45, 0, 0}, + {0x7168, 0xa4, 0, 0}, + {0x7169, 0xbd, 0, 0}, + {0x716a, 0x03, 0, 0}, + {0x716b, 0xec, 0, 0}, + {0x716c, 0xbc, 0, 0}, + {0x716d, 0x3d, 0, 0}, + {0x716e, 0xc3, 0, 0}, + {0x716f, 0xcf, 0, 0}, + {0x7170, 0x42, 0, 0}, + {0x7171, 0xb8, 0, 0}, + {0x7172, 0x00, 0, 0}, + {0x7173, 0xe4, 0, 0}, + {0x7174, 0xd5, 0, 0}, + {0x7175, 0x00, 0, 0}, + {0x7176, 0xb6, 0, 0}, + {0x7177, 0x00, 0, 0}, + {0x7178, 0x74, 0, 0}, + {0x7179, 0xbd, 0, 0}, + {0x717a, 0x03, 0, 0}, + {0x717b, 0xb5, 0, 0}, + {0x717c, 0x39, 0, 0}, + {0x717d, 0x40, 0, 0}, + {0x717e, 0x58, 0, 0}, + {0x717f, 0xdd, 0, 0}, + {0x7180, 0x19, 0, 0}, + {0x7181, 0xc1, 0, 0}, + {0x7182, 0xc8, 0, 0}, + {0x7183, 0xbd, 0, 0}, + {0x7184, 0x06, 0, 0}, + {0x7185, 0x17, 0, 0}, + {0x7186, 0xc1, 0, 0}, + {0x7187, 0xc6, 0, 0}, + {0x7188, 0xe8, 0, 0}, + {0x7189, 0x00, 0, 0}, + {0x718a, 0xc0, 0, 0}, + {0x718b, 0xc8, 0, 0}, + {0x718c, 0xe6, 0, 0}, + {0x718d, 0x95, 0, 0}, + {0x718e, 0x15, 0, 0}, + {0x718f, 0x00, 0, 0}, + {0x7190, 0xbc, 0, 0}, + {0x7191, 0x19, 0, 0}, + {0x7192, 0xb9, 0, 0}, + {0x7193, 0xf6, 0, 0}, + {0x7194, 0x14, 0, 0}, + {0x7195, 0xc1, 0, 0}, + {0x7196, 0xd0, 0, 0}, + {0x7197, 0xd1, 0, 0}, + {0x7198, 0xac, 0, 0}, + {0x7199, 0x37, 0, 0}, + {0x719a, 0xbc, 0, 0}, + {0x719b, 0x35, 0, 0}, + {0x719c, 0x36, 0, 0}, + {0x719d, 0x30, 0, 0}, + {0x719e, 0xe1, 0, 0}, + {0x719f, 0xd3, 0, 0}, + {0x71a0, 0x7a, 0, 0}, + {0x71a1, 0xb6, 0, 0}, + {0x71a2, 0x0c, 0, 0}, + {0x71a3, 0xff, 0, 0}, + {0x71a4, 0xb4, 0, 0}, + {0x71a5, 0xc7, 0, 0}, + {0x71a6, 0xd9, 0, 0}, + {0x71a7, 0x00, 0, 0}, + {0x71a8, 0xbd, 0, 0}, + {0x71a9, 0x01, 0, 0}, + {0x71aa, 0x56, 0, 0}, + {0x71ab, 0xc0, 0, 0}, + {0x71ac, 0xda, 0, 0}, + {0x71ad, 0xb4, 0, 0}, + {0x71ae, 0x1f, 0, 0}, + {0x71af, 0x56, 0, 0}, + {0x71b0, 0xaa, 0, 0}, + {0x71b1, 0xbc, 0, 0}, + {0x71b2, 0x08, 0, 0}, + {0x71b3, 0x00, 0, 0}, + {0x71b4, 0x57, 0, 0}, + {0x71b5, 0xe8, 0, 0}, + {0x71b6, 0xb5, 0, 0}, + {0x71b7, 0x36, 0, 0}, + {0x71b8, 0x00, 0, 0}, + {0x71b9, 0x54, 0, 0}, + {0x71ba, 0xe7, 0, 0}, + {0x71bb, 0xc8, 0, 0}, + {0x71bc, 0xb4, 0, 0}, + {0x71bd, 0x1f, 0, 0}, + {0x71be, 0x56, 0, 0}, + {0x71bf, 0xaa, 0, 0}, + {0x71c0, 0xbc, 0, 0}, + {0x71c1, 0x08, 0, 0}, + {0x71c2, 0x57, 0, 0}, + {0x71c3, 0x00, 0, 0}, + {0x71c4, 0xb5, 0, 0}, + {0x71c5, 0x36, 0, 0}, + {0x71c6, 0x00, 0, 0}, + {0x71c7, 0x54, 0, 0}, + {0x71c8, 0xc8, 0, 0}, + {0x71c9, 0xb5, 0, 0}, + {0x71ca, 0x18, 0, 0}, + {0x71cb, 0xd9, 0, 0}, + {0x71cc, 0x00, 0, 0}, + {0x71cd, 0xbd, 0, 0}, + {0x71ce, 0x01, 0, 0}, + {0x71cf, 0x56, 0, 0}, + {0x71d0, 0x08, 0, 0}, + {0x71d1, 0x57, 0, 0}, + {0x71d2, 0xe8, 0, 0}, + {0x71d3, 0xb4, 0, 0}, + {0x71d4, 0x42, 0, 0}, + {0x71d5, 0x00, 0, 0}, + {0x71d6, 0x54, 0, 0}, + {0x71d7, 0xe7, 0, 0}, + {0x71d8, 0xc8, 0, 0}, + {0x71d9, 0xab, 0, 0}, + {0x71da, 0x00, 0, 0}, + {0x71db, 0x66, 0, 0}, + {0x71dc, 0x62, 0, 0}, + {0x71dd, 0x06, 0, 0}, + {0x71de, 0x74, 0, 0}, + {0x71df, 0xb9, 0, 0}, + {0x71e0, 0x05, 0, 0}, + {0x71e1, 0xb7, 0, 0}, + {0x71e2, 0x14, 0, 0}, + {0x71e3, 0x0e, 0, 0}, + {0x71e4, 0xb7, 0, 0}, + {0x71e5, 0x04, 0, 0}, + {0x71e6, 0xc8, 0, 0}, + {0x7600, 0x04, 0, 0}, + {0x7601, 0x80, 0, 0}, + {0x7602, 0x07, 0, 0}, + {0x7603, 0x44, 0, 0}, + {0x7604, 0x05, 0, 0}, + {0x7605, 0x33, 0, 0}, + {0x7606, 0x0f, 0, 0}, + {0x7607, 0x00, 0, 0}, + {0x7608, 0x07, 0, 0}, + {0x7609, 0x40, 0, 0}, + {0x760a, 0x04, 0, 0}, + {0x760b, 0xe5, 0, 0}, + {0x760c, 0x06, 0, 0}, + {0x760d, 0x50, 0, 0}, + {0x760e, 0x04, 0, 0}, + {0x760f, 0xe4, 0, 0}, + {0x7610, 0x00, 0, 0}, + {0x7611, 0x00, 0, 0}, + {0x7612, 0x06, 0, 0}, + {0x7613, 0x5c, 0, 0}, + {0x7614, 0x00, 0, 0}, + {0x7615, 0x0f, 0, 0}, + {0x7616, 0x06, 0, 0}, + {0x7617, 0x1c, 0, 0}, + {0x7618, 0x00, 0, 0}, + {0x7619, 0x02, 0, 0}, + {0x761a, 0x06, 0, 0}, + {0x761b, 0xa2, 0, 0}, + {0x761c, 0x00, 0, 0}, + {0x761d, 0x01, 0, 0}, + {0x761e, 0x06, 0, 0}, + {0x761f, 0xae, 0, 0}, + {0x7620, 0x00, 0, 0}, + {0x7621, 0x0e, 0, 0}, + {0x7622, 0x05, 0, 0}, + {0x7623, 0x30, 0, 0}, + {0x7624, 0x07, 0, 0}, + {0x7625, 0x00, 0, 0}, + {0x7626, 0x0f, 0, 0}, + {0x7627, 0x00, 0, 0}, + {0x7628, 0x04, 0, 0}, + {0x7629, 0xe5, 0, 0}, + {0x762a, 0x05, 0, 0}, + {0x762b, 0x33, 0, 0}, + {0x762c, 0x06, 0, 0}, + {0x762d, 0x12, 0, 0}, + {0x762e, 0x00, 0, 0}, + {0x762f, 0x01, 0, 0}, + {0x7630, 0x06, 0, 0}, + {0x7631, 0x52, 0, 0}, + {0x7632, 0x00, 0, 0}, + {0x7633, 0x01, 0, 0}, + {0x7634, 0x06, 0, 0}, + {0x7635, 0x5e, 0, 0}, + {0x7636, 0x04, 0, 0}, + {0x7637, 0xe4, 0, 0}, + {0x7638, 0x00, 0, 0}, + {0x7639, 0x01, 0, 0}, + {0x763a, 0x05, 0, 0}, + {0x763b, 0x30, 0, 0}, + {0x763c, 0x0f, 0, 0}, + {0x763d, 0x00, 0, 0}, + {0x763e, 0x06, 0, 0}, + {0x763f, 0xa6, 0, 0}, + {0x7640, 0x00, 0, 0}, + {0x7641, 0x02, 0, 0}, + {0x7642, 0x06, 0, 0}, + {0x7643, 0x26, 0, 0}, + {0x7644, 0x00, 0, 0}, + {0x7645, 0x02, 0, 0}, + {0x7646, 0x05, 0, 0}, + {0x7647, 0x33, 0, 0}, + {0x7648, 0x06, 0, 0}, + {0x7649, 0x20, 0, 0}, + {0x764a, 0x0f, 0, 0}, + {0x764b, 0x00, 0, 0}, + {0x764c, 0x06, 0, 0}, + {0x764d, 0x56, 0, 0}, + {0x764e, 0x00, 0, 0}, + {0x764f, 0x02, 0, 0}, + {0x7650, 0x06, 0, 0}, + {0x7651, 0x16, 0, 0}, + {0x7652, 0x05, 0, 0}, + {0x7653, 0x33, 0, 0}, + {0x7654, 0x06, 0, 0}, + {0x7655, 0x10, 0, 0}, + {0x7656, 0x0f, 0, 0}, + {0x7657, 0x00, 0, 0}, + {0x7658, 0x06, 0, 0}, + {0x7659, 0x10, 0, 0}, + {0x765a, 0x0f, 0, 0}, + {0x765b, 0x00, 0, 0}, + {0x765c, 0x06, 0, 0}, + {0x765d, 0x20, 0, 0}, + {0x765e, 0x0f, 0, 0}, + {0x765f, 0x00, 0, 0}, + {0x7660, 0x00, 0, 0}, + {0x7661, 0x00, 0, 0}, + {0x7662, 0x00, 0, 0}, + {0x7663, 0x02, 0, 0}, + {0x7664, 0x04, 0, 0}, + {0x7665, 0xe5, 0, 0}, + {0x7666, 0x04, 0, 0}, + {0x7667, 0xe4, 0, 0}, + {0x7668, 0x0f, 0, 0}, + {0x7669, 0x00, 0, 0}, + {0x766a, 0x00, 0, 0}, + {0x766b, 0x00, 0, 0}, + {0x766c, 0x00, 0, 0}, + {0x766d, 0x01, 0, 0}, + {0x766e, 0x04, 0, 0}, + {0x766f, 0xe5, 0, 0}, + {0x7670, 0x04, 0, 0}, + {0x7671, 0xe4, 0, 0}, + {0x7672, 0x0f, 0, 0}, + {0x7673, 0x00, 0, 0}, + {0x7674, 0x00, 0, 0}, + {0x7675, 0x02, 0, 0}, + {0x7676, 0x04, 0, 0}, + {0x7677, 0xe4, 0, 0}, + {0x7678, 0x00, 0, 0}, + {0x7679, 0x02, 0, 0}, + {0x767a, 0x04, 0, 0}, + {0x767b, 0xc4, 0, 0}, + {0x767c, 0x00, 0, 0}, + {0x767d, 0x02, 0, 0}, + {0x767e, 0x04, 0, 0}, + {0x767f, 0xc4, 0, 0}, + {0x7680, 0x05, 0, 0}, + {0x7681, 0x83, 0, 0}, + {0x7682, 0x0f, 0, 0}, + {0x7683, 0x00, 0, 0}, + {0x7684, 0x00, 0, 0}, + {0x7685, 0x02, 0, 0}, + {0x7686, 0x04, 0, 0}, + {0x7687, 0xe4, 0, 0}, + {0x7688, 0x00, 0, 0}, + {0x7689, 0x02, 0, 0}, + {0x768a, 0x04, 0, 0}, + {0x768b, 0xc4, 0, 0}, + {0x768c, 0x00, 0, 0}, + {0x768d, 0x02, 0, 0}, + {0x768e, 0x04, 0, 0}, + {0x768f, 0xc4, 0, 0}, + {0x7690, 0x05, 0, 0}, + {0x7691, 0x83, 0, 0}, + {0x7692, 0x03, 0, 0}, + {0x7693, 0x0b, 0, 0}, + {0x7694, 0x05, 0, 0}, + {0x7695, 0x83, 0, 0}, + {0x7696, 0x00, 0, 0}, + {0x7697, 0x07, 0, 0}, + {0x7698, 0x05, 0, 0}, + {0x7699, 0x03, 0, 0}, + {0x769a, 0x00, 0, 0}, + {0x769b, 0x05, 0, 0}, + {0x769c, 0x05, 0, 0}, + {0x769d, 0x32, 0, 0}, + {0x769e, 0x05, 0, 0}, + {0x769f, 0x30, 0, 0}, + {0x76a0, 0x00, 0, 0}, + {0x76a1, 0x02, 0, 0}, + {0x76a2, 0x05, 0, 0}, + {0x76a3, 0x78, 0, 0}, + {0x76a4, 0x00, 0, 0}, + {0x76a5, 0x01, 0, 0}, + {0x76a6, 0x05, 0, 0}, + {0x76a7, 0x7c, 0, 0}, + {0x76a8, 0x03, 0, 0}, + {0x76a9, 0x9a, 0, 0}, + {0x76aa, 0x05, 0, 0}, + {0x76ab, 0x83, 0, 0}, + {0x76ac, 0x00, 0, 0}, + {0x76ad, 0x04, 0, 0}, + {0x76ae, 0x05, 0, 0}, + {0x76af, 0x03, 0, 0}, + {0x76b0, 0x00, 0, 0}, + {0x76b1, 0x03, 0, 0}, + {0x76b2, 0x05, 0, 0}, + {0x76b3, 0x32, 0, 0}, + {0x76b4, 0x05, 0, 0}, + {0x76b5, 0x30, 0, 0}, + {0x76b6, 0x00, 0, 0}, + {0x76b7, 0x02, 0, 0}, + {0x76b8, 0x05, 0, 0}, + {0x76b9, 0x78, 0, 0}, + {0x76ba, 0x00, 0, 0}, + {0x76bb, 0x01, 0, 0}, + {0x76bc, 0x05, 0, 0}, + {0x76bd, 0x7c, 0, 0}, + {0x76be, 0x03, 0, 0}, + {0x76bf, 0x99, 0, 0}, + {0x76c0, 0x05, 0, 0}, + {0x76c1, 0x83, 0, 0}, + {0x76c2, 0x00, 0, 0}, + {0x76c3, 0x03, 0, 0}, + {0x76c4, 0x05, 0, 0}, + {0x76c5, 0x03, 0, 0}, + {0x76c6, 0x00, 0, 0}, + {0x76c7, 0x01, 0, 0}, + {0x76c8, 0x05, 0, 0}, + {0x76c9, 0x32, 0, 0}, + {0x76ca, 0x05, 0, 0}, + {0x76cb, 0x30, 0, 0}, + {0x76cc, 0x00, 0, 0}, + {0x76cd, 0x02, 0, 0}, + {0x76ce, 0x05, 0, 0}, + {0x76cf, 0x78, 0, 0}, + {0x76d0, 0x00, 0, 0}, + {0x76d1, 0x01, 0, 0}, + {0x76d2, 0x05, 0, 0}, + {0x76d3, 0x7c, 0, 0}, + {0x76d4, 0x03, 0, 0}, + {0x76d5, 0x98, 0, 0}, + {0x76d6, 0x05, 0, 0}, + {0x76d7, 0x83, 0, 0}, + {0x76d8, 0x00, 0, 0}, + {0x76d9, 0x00, 0, 0}, + {0x76da, 0x05, 0, 0}, + {0x76db, 0x03, 0, 0}, + {0x76dc, 0x00, 0, 0}, + {0x76dd, 0x01, 0, 0}, + {0x76de, 0x05, 0, 0}, + {0x76df, 0x32, 0, 0}, + {0x76e0, 0x05, 0, 0}, + {0x76e1, 0x30, 0, 0}, + {0x76e2, 0x00, 0, 0}, + {0x76e3, 0x02, 0, 0}, + {0x76e4, 0x05, 0, 0}, + {0x76e5, 0x78, 0, 0}, + {0x76e6, 0x00, 0, 0}, + {0x76e7, 0x01, 0, 0}, + {0x76e8, 0x05, 0, 0}, + {0x76e9, 0x7c, 0, 0}, + {0x76ea, 0x03, 0, 0}, + {0x76eb, 0x97, 0, 0}, + {0x76ec, 0x05, 0, 0}, + {0x76ed, 0x83, 0, 0}, + {0x76ee, 0x00, 0, 0}, + {0x76ef, 0x00, 0, 0}, + {0x76f0, 0x05, 0, 0}, + {0x76f1, 0x03, 0, 0}, + {0x76f2, 0x05, 0, 0}, + {0x76f3, 0x32, 0, 0}, + {0x76f4, 0x05, 0, 0}, + {0x76f5, 0x30, 0, 0}, + {0x76f6, 0x00, 0, 0}, + {0x76f7, 0x02, 0, 0}, + {0x76f8, 0x05, 0, 0}, + {0x76f9, 0x78, 0, 0}, + {0x76fa, 0x00, 0, 0}, + {0x76fb, 0x01, 0, 0}, + {0x76fc, 0x05, 0, 0}, + {0x76fd, 0x7c, 0, 0}, + {0x76fe, 0x03, 0, 0}, + {0x76ff, 0x96, 0, 0}, + {0x7700, 0x05, 0, 0}, + {0x7701, 0x83, 0, 0}, + {0x7702, 0x05, 0, 0}, + {0x7703, 0x03, 0, 0}, + {0x7704, 0x05, 0, 0}, + {0x7705, 0x32, 0, 0}, + {0x7706, 0x05, 0, 0}, + {0x7707, 0x30, 0, 0}, + {0x7708, 0x00, 0, 0}, + {0x7709, 0x02, 0, 0}, + {0x770a, 0x05, 0, 0}, + {0x770b, 0x78, 0, 0}, + {0x770c, 0x00, 0, 0}, + {0x770d, 0x01, 0, 0}, + {0x770e, 0x05, 0, 0}, + {0x770f, 0x7c, 0, 0}, + {0x7710, 0x03, 0, 0}, + {0x7711, 0x95, 0, 0}, + {0x7712, 0x05, 0, 0}, + {0x7713, 0x83, 0, 0}, + {0x7714, 0x05, 0, 0}, + {0x7715, 0x03, 0, 0}, + {0x7716, 0x05, 0, 0}, + {0x7717, 0x32, 0, 0}, + {0x7718, 0x05, 0, 0}, + {0x7719, 0x30, 0, 0}, + {0x771a, 0x00, 0, 0}, + {0x771b, 0x02, 0, 0}, + {0x771c, 0x05, 0, 0}, + {0x771d, 0x78, 0, 0}, + {0x771e, 0x00, 0, 0}, + {0x771f, 0x01, 0, 0}, + {0x7720, 0x05, 0, 0}, + {0x7721, 0x7c, 0, 0}, + {0x7722, 0x03, 0, 0}, + {0x7723, 0x94, 0, 0}, + {0x7724, 0x05, 0, 0}, + {0x7725, 0x83, 0, 0}, + {0x7726, 0x00, 0, 0}, + {0x7727, 0x01, 0, 0}, + {0x7728, 0x05, 0, 0}, + {0x7729, 0x03, 0, 0}, + {0x772a, 0x00, 0, 0}, + {0x772b, 0x01, 0, 0}, + {0x772c, 0x05, 0, 0}, + {0x772d, 0x32, 0, 0}, + {0x772e, 0x05, 0, 0}, + {0x772f, 0x30, 0, 0}, + {0x7730, 0x00, 0, 0}, + {0x7731, 0x02, 0, 0}, + {0x7732, 0x05, 0, 0}, + {0x7733, 0x78, 0, 0}, + {0x7734, 0x00, 0, 0}, + {0x7735, 0x01, 0, 0}, + {0x7736, 0x05, 0, 0}, + {0x7737, 0x7c, 0, 0}, + {0x7738, 0x03, 0, 0}, + {0x7739, 0x93, 0, 0}, + {0x773a, 0x05, 0, 0}, + {0x773b, 0x83, 0, 0}, + {0x773c, 0x00, 0, 0}, + {0x773d, 0x00, 0, 0}, + {0x773e, 0x05, 0, 0}, + {0x773f, 0x03, 0, 0}, + {0x7740, 0x00, 0, 0}, + {0x7741, 0x00, 0, 0}, + {0x7742, 0x05, 0, 0}, + {0x7743, 0x32, 0, 0}, + {0x7744, 0x05, 0, 0}, + {0x7745, 0x30, 0, 0}, + {0x7746, 0x00, 0, 0}, + {0x7747, 0x02, 0, 0}, + {0x7748, 0x05, 0, 0}, + {0x7749, 0x78, 0, 0}, + {0x774a, 0x00, 0, 0}, + {0x774b, 0x01, 0, 0}, + {0x774c, 0x05, 0, 0}, + {0x774d, 0x7c, 0, 0}, + {0x774e, 0x03, 0, 0}, + {0x774f, 0x92, 0, 0}, + {0x7750, 0x05, 0, 0}, + {0x7751, 0x83, 0, 0}, + {0x7752, 0x05, 0, 0}, + {0x7753, 0x03, 0, 0}, + {0x7754, 0x00, 0, 0}, + {0x7755, 0x00, 0, 0}, + {0x7756, 0x05, 0, 0}, + {0x7757, 0x32, 0, 0}, + {0x7758, 0x05, 0, 0}, + {0x7759, 0x30, 0, 0}, + {0x775a, 0x00, 0, 0}, + {0x775b, 0x02, 0, 0}, + {0x775c, 0x05, 0, 0}, + {0x775d, 0x78, 0, 0}, + {0x775e, 0x00, 0, 0}, + {0x775f, 0x01, 0, 0}, + {0x7760, 0x05, 0, 0}, + {0x7761, 0x7c, 0, 0}, + {0x7762, 0x03, 0, 0}, + {0x7763, 0x91, 0, 0}, + {0x7764, 0x05, 0, 0}, + {0x7765, 0x83, 0, 0}, + {0x7766, 0x05, 0, 0}, + {0x7767, 0x03, 0, 0}, + {0x7768, 0x05, 0, 0}, + {0x7769, 0x32, 0, 0}, + {0x776a, 0x05, 0, 0}, + {0x776b, 0x30, 0, 0}, + {0x776c, 0x00, 0, 0}, + {0x776d, 0x02, 0, 0}, + {0x776e, 0x05, 0, 0}, + {0x776f, 0x78, 0, 0}, + {0x7770, 0x00, 0, 0}, + {0x7771, 0x01, 0, 0}, + {0x7772, 0x05, 0, 0}, + {0x7773, 0x7c, 0, 0}, + {0x7774, 0x03, 0, 0}, + {0x7775, 0x90, 0, 0}, + {0x7776, 0x05, 0, 0}, + {0x7777, 0x83, 0, 0}, + {0x7778, 0x05, 0, 0}, + {0x7779, 0x03, 0, 0}, + {0x777a, 0x05, 0, 0}, + {0x777b, 0x32, 0, 0}, + {0x777c, 0x05, 0, 0}, + {0x777d, 0x30, 0, 0}, + {0x777e, 0x00, 0, 0}, + {0x777f, 0x02, 0, 0}, + {0x7780, 0x05, 0, 0}, + {0x7781, 0x78, 0, 0}, + {0x7782, 0x00, 0, 0}, + {0x7783, 0x01, 0, 0}, + {0x7784, 0x05, 0, 0}, + {0x7785, 0x7c, 0, 0}, + {0x7786, 0x02, 0, 0}, + {0x7787, 0x90, 0, 0}, + {0x7788, 0x05, 0, 0}, + {0x7789, 0x03, 0, 0}, + {0x778a, 0x07, 0, 0}, + {0x778b, 0x00, 0, 0}, + {0x778c, 0x0f, 0, 0}, + {0x778d, 0x00, 0, 0}, + {0x778e, 0x08, 0, 0}, + {0x778f, 0x30, 0, 0}, + {0x7790, 0x08, 0, 0}, + {0x7791, 0xee, 0, 0}, + {0x7792, 0x0f, 0, 0}, + {0x7793, 0x00, 0, 0}, + {0x7794, 0x05, 0, 0}, + {0x7795, 0x33, 0, 0}, + {0x7796, 0x04, 0, 0}, + {0x7797, 0xe5, 0, 0}, + {0x7798, 0x06, 0, 0}, + {0x7799, 0x52, 0, 0}, + {0x779a, 0x04, 0, 0}, + {0x779b, 0xe4, 0, 0}, + {0x779c, 0x00, 0, 0}, + {0x779d, 0x00, 0, 0}, + {0x779e, 0x06, 0, 0}, + {0x779f, 0x5e, 0, 0}, + {0x77a0, 0x00, 0, 0}, + {0x77a1, 0x0f, 0, 0}, + {0x77a2, 0x06, 0, 0}, + {0x77a3, 0x1e, 0, 0}, + {0x77a4, 0x00, 0, 0}, + {0x77a5, 0x02, 0, 0}, + {0x77a6, 0x06, 0, 0}, + {0x77a7, 0xa2, 0, 0}, + {0x77a8, 0x00, 0, 0}, + {0x77a9, 0x01, 0, 0}, + {0x77aa, 0x06, 0, 0}, + {0x77ab, 0xae, 0, 0}, + {0x77ac, 0x00, 0, 0}, + {0x77ad, 0x03, 0, 0}, + {0x77ae, 0x05, 0, 0}, + {0x77af, 0x30, 0, 0}, + {0x77b0, 0x09, 0, 0}, + {0x77b1, 0x19, 0, 0}, + {0x77b2, 0x0f, 0, 0}, + {0x77b3, 0x00, 0, 0}, + {0x77b4, 0x05, 0, 0}, + {0x77b5, 0x33, 0, 0}, + {0x77b6, 0x04, 0, 0}, + {0x77b7, 0xe5, 0, 0}, + {0x77b8, 0x06, 0, 0}, + {0x77b9, 0x52, 0, 0}, + {0x77ba, 0x04, 0, 0}, + {0x77bb, 0xe4, 0, 0}, + {0x77bc, 0x00, 0, 0}, + {0x77bd, 0x00, 0, 0}, + {0x77be, 0x06, 0, 0}, + {0x77bf, 0x5e, 0, 0}, + {0x77c0, 0x00, 0, 0}, + {0x77c1, 0x0f, 0, 0}, + {0x77c2, 0x06, 0, 0}, + {0x77c3, 0x1e, 0, 0}, + {0x77c4, 0x00, 0, 0}, + {0x77c5, 0x02, 0, 0}, + {0x77c6, 0x06, 0, 0}, + {0x77c7, 0xa2, 0, 0}, + {0x77c8, 0x00, 0, 0}, + {0x77c9, 0x01, 0, 0}, + {0x77ca, 0x06, 0, 0}, + {0x77cb, 0xae, 0, 0}, + {0x77cc, 0x00, 0, 0}, + {0x77cd, 0x03, 0, 0}, + {0x77ce, 0x05, 0, 0}, + {0x77cf, 0x30, 0, 0}, + {0x77d0, 0x0f, 0, 0}, + {0x77d1, 0x00, 0, 0}, + {0x77d2, 0x00, 0, 0}, + {0x77d3, 0x00, 0, 0}, + {0x77d4, 0x00, 0, 0}, + {0x77d5, 0x02, 0, 0}, + {0x77d6, 0x04, 0, 0}, + {0x77d7, 0xe5, 0, 0}, + {0x77d8, 0x04, 0, 0}, + {0x77d9, 0xe4, 0, 0}, + {0x77da, 0x05, 0, 0}, + {0x77db, 0x33, 0, 0}, + {0x77dc, 0x07, 0, 0}, + {0x77dd, 0x10, 0, 0}, + {0x77de, 0x00, 0, 0}, + {0x77df, 0x00, 0, 0}, + {0x77e0, 0x01, 0, 0}, + {0x77e1, 0xbb, 0, 0}, + {0x77e2, 0x00, 0, 0}, + {0x77e3, 0x00, 0, 0}, + {0x77e4, 0x01, 0, 0}, + {0x77e5, 0xaa, 0, 0}, + {0x77e6, 0x00, 0, 0}, + {0x77e7, 0x00, 0, 0}, + {0x77e8, 0x01, 0, 0}, + {0x77e9, 0x99, 0, 0}, + {0x77ea, 0x00, 0, 0}, + {0x77eb, 0x00, 0, 0}, + {0x77ec, 0x01, 0, 0}, + {0x77ed, 0x88, 0, 0}, + {0x77ee, 0x00, 0, 0}, + {0x77ef, 0x00, 0, 0}, + {0x77f0, 0x01, 0, 0}, + {0x77f1, 0x77, 0, 0}, + {0x77f2, 0x00, 0, 0}, + {0x77f3, 0x00, 0, 0}, + {0x77f4, 0x01, 0, 0}, + {0x77f5, 0x66, 0, 0}, + {0x77f6, 0x00, 0, 0}, + {0x77f7, 0x00, 0, 0}, + {0x77f8, 0x01, 0, 0}, + {0x77f9, 0x55, 0, 0}, + {0x77fa, 0x00, 0, 0}, + {0x77fb, 0x00, 0, 0}, + {0x77fc, 0x01, 0, 0}, + {0x77fd, 0x44, 0, 0}, + {0x77fe, 0x00, 0, 0}, + {0x77ff, 0x00, 0, 0}, + {0x7800, 0x01, 0, 0}, + {0x7801, 0x33, 0, 0}, + {0x7802, 0x00, 0, 0}, + {0x7803, 0x00, 0, 0}, + {0x7804, 0x01, 0, 0}, + {0x7805, 0x22, 0, 0}, + {0x7806, 0x00, 0, 0}, + {0x7807, 0x00, 0, 0}, + {0x7808, 0x01, 0, 0}, + {0x7809, 0x11, 0, 0}, + {0x780a, 0x00, 0, 0}, + {0x780b, 0x00, 0, 0}, + {0x780c, 0x01, 0, 0}, + {0x780d, 0x00, 0, 0}, + {0x780e, 0x01, 0, 0}, + {0x780f, 0xff, 0, 0}, + {0x7810, 0x07, 0, 0}, + {0x7811, 0x00, 0, 0}, + {0x7812, 0x02, 0, 0}, + {0x7813, 0xa0, 0, 0}, + {0x7814, 0x0f, 0, 0}, + {0x7815, 0x00, 0, 0}, + {0x7816, 0x08, 0, 0}, + {0x7817, 0x35, 0, 0}, + {0x7818, 0x06, 0, 0}, + {0x7819, 0x52, 0, 0}, + {0x781a, 0x04, 0, 0}, + {0x781b, 0xe4, 0, 0}, + {0x781c, 0x00, 0, 0}, + {0x781d, 0x00, 0, 0}, + {0x781e, 0x06, 0, 0}, + {0x781f, 0x5e, 0, 0}, + {0x7820, 0x05, 0, 0}, + {0x7821, 0x33, 0, 0}, + {0x7822, 0x09, 0, 0}, + {0x7823, 0x19, 0, 0}, + {0x7824, 0x06, 0, 0}, + {0x7825, 0x1e, 0, 0}, + {0x7826, 0x05, 0, 0}, + {0x7827, 0x33, 0, 0}, + {0x7828, 0x00, 0, 0}, + {0x7829, 0x01, 0, 0}, + {0x782a, 0x06, 0, 0}, + {0x782b, 0x24, 0, 0}, + {0x782c, 0x06, 0, 0}, + {0x782d, 0x20, 0, 0}, + {0x782e, 0x0f, 0, 0}, + {0x782f, 0x00, 0, 0}, + {0x7830, 0x08, 0, 0}, + {0x7831, 0x35, 0, 0}, + {0x7832, 0x07, 0, 0}, + {0x7833, 0x10, 0, 0}, + {0x7834, 0x00, 0, 0}, + {0x7835, 0x00, 0, 0}, + {0x7836, 0x01, 0, 0}, + {0x7837, 0xbb, 0, 0}, + {0x7838, 0x00, 0, 0}, + {0x7839, 0x00, 0, 0}, + {0x783a, 0x01, 0, 0}, + {0x783b, 0xaa, 0, 0}, + {0x783c, 0x00, 0, 0}, + {0x783d, 0x00, 0, 0}, + {0x783e, 0x01, 0, 0}, + {0x783f, 0x99, 0, 0}, + {0x7840, 0x00, 0, 0}, + {0x7841, 0x00, 0, 0}, + {0x7842, 0x01, 0, 0}, + {0x7843, 0x88, 0, 0}, + {0x7844, 0x00, 0, 0}, + {0x7845, 0x00, 0, 0}, + {0x7846, 0x01, 0, 0}, + {0x7847, 0x77, 0, 0}, + {0x7848, 0x00, 0, 0}, + {0x7849, 0x00, 0, 0}, + {0x784a, 0x01, 0, 0}, + {0x784b, 0x66, 0, 0}, + {0x784c, 0x00, 0, 0}, + {0x784d, 0x00, 0, 0}, + {0x784e, 0x01, 0, 0}, + {0x784f, 0x55, 0, 0}, + {0x7850, 0x00, 0, 0}, + {0x7851, 0x00, 0, 0}, + {0x7852, 0x01, 0, 0}, + {0x7853, 0x44, 0, 0}, + {0x7854, 0x00, 0, 0}, + {0x7855, 0x00, 0, 0}, + {0x7856, 0x01, 0, 0}, + {0x7857, 0x33, 0, 0}, + {0x7858, 0x00, 0, 0}, + {0x7859, 0x00, 0, 0}, + {0x785a, 0x01, 0, 0}, + {0x785b, 0x22, 0, 0}, + {0x785c, 0x00, 0, 0}, + {0x785d, 0x00, 0, 0}, + {0x785e, 0x01, 0, 0}, + {0x785f, 0x11, 0, 0}, + {0x7860, 0x00, 0, 0}, + {0x7861, 0x00, 0, 0}, + {0x7862, 0x01, 0, 0}, + {0x7863, 0x00, 0, 0}, + {0x7864, 0x07, 0, 0}, + {0x7865, 0x00, 0, 0}, + {0x7866, 0x01, 0, 0}, + {0x7867, 0xff, 0, 0}, + {0x7868, 0x02, 0, 0}, + {0x7869, 0xa0, 0, 0}, + {0x786a, 0x0f, 0, 0}, + {0x786b, 0x00, 0, 0}, + {0x786c, 0x08, 0, 0}, + {0x786d, 0x3a, 0, 0}, + {0x786e, 0x08, 0, 0}, + {0x786f, 0x6a, 0, 0}, + {0x7870, 0x0f, 0, 0}, + {0x7871, 0x00, 0, 0}, + {0x7872, 0x04, 0, 0}, + {0x7873, 0xc0, 0, 0}, + {0x7874, 0x09, 0, 0}, + {0x7875, 0x19, 0, 0}, + {0x7876, 0x04, 0, 0}, + {0x7877, 0x99, 0, 0}, + {0x7878, 0x07, 0, 0}, + {0x7879, 0x14, 0, 0}, + {0x787a, 0x00, 0, 0}, + {0x787b, 0x01, 0, 0}, + {0x787c, 0x04, 0, 0}, + {0x787d, 0xa4, 0, 0}, + {0x787e, 0x00, 0, 0}, + {0x787f, 0x07, 0, 0}, + {0x7880, 0x04, 0, 0}, + {0x7881, 0xa6, 0, 0}, + {0x7882, 0x00, 0, 0}, + {0x7883, 0x00, 0, 0}, + {0x7884, 0x04, 0, 0}, + {0x7885, 0xa0, 0, 0}, + {0x7886, 0x04, 0, 0}, + {0x7887, 0x80, 0, 0}, + {0x7888, 0x04, 0, 0}, + {0x7889, 0x00, 0, 0}, + {0x788a, 0x05, 0, 0}, + {0x788b, 0x03, 0, 0}, + {0x788c, 0x06, 0, 0}, + {0x788d, 0x00, 0, 0}, + {0x788e, 0x0f, 0, 0}, + {0x788f, 0x00, 0, 0}, + {0x7890, 0x0f, 0, 0}, + {0x7891, 0x00, 0, 0}, + {0x7892, 0x0f, 0, 0}, + {0x7893, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x05, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x04, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x80, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x38, 0, 0}, + {0x30b0, 0x0b, 0, 0},//HTS_H 0x0d + {0x30b1, 0x1c, 0, 0},//HTS_L 0xde + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x66, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x80, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x0a, 0, 0}, + {0x3195, 0x29, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x80, 0, 0}, + {0x30bb, 0x01, 0, 0}, + {0x3250, 0xf7, 0, 0}, + + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x08, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x08, 0, 0}, + + + {0x30c0, 0x08, 0, 0}, + {0x3252, 0x20, 0, 0}, +}; + +#endif diff --git a/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr.h b/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr.h new file mode 100755 index 0000000..22bffae --- /dev/null +++ b/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr.h @@ -0,0 +1,1885 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OV2775_REGS_1080PHDR_H_ +#define _VVCAM_OV2775_REGS_1080PHDR_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t ov2775_init_setting_1080p_hdr[] = { + {0x3000, 0x02, 0, 0}, + {0x3001, 0x28, 0, 0}, + {0x3002, 0x03, 0, 0}, + {0x3003, 0x01, 0, 0}, + {0x3004, 0x02, 0, 0}, + {0x3005, 0x26, 0, 0}, + {0x3006, 0x00, 0, 0}, + {0x3007, 0x07, 0, 0}, + {0x3008, 0x01, 0, 0}, + {0x3009, 0x00, 0, 0}, + {0x300c, 0x6c, 0, 0}, + {0x300e, 0x80, 0, 0}, + {0x300f, 0x00, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3013, 0x00, 0, 0}, + {0x3014, 0xc4, 0, 0}, + {0x3015, 0x00, 0, 0}, + {0x3017, 0x00, 0, 0}, + {0x3018, 0x00, 0, 0}, + {0x3019, 0x00, 0, 0}, + {0x301a, 0x00, 0, 0}, + {0x301b, 0x0e, 0, 0}, + {0x301e, 0x17, 0, 0}, + {0x301f, 0xe1, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x3031, 0x62, 0, 0}, + {0x3032, 0xf0, 0, 0}, + {0x3033, 0x30, 0, 0}, + {0x3034, 0x3f, 0, 0}, + {0x3035, 0x5f, 0, 0}, + {0x3036, 0x02, 0, 0}, + {0x3037, 0x9f, 0, 0}, + {0x3038, 0x04, 0, 0}, + {0x3039, 0xb7, 0, 0}, + {0x303a, 0x04, 0, 0}, + {0x303b, 0x07, 0, 0}, + {0x303c, 0xf0, 0, 0}, + {0x303d, 0x00, 0, 0}, + {0x303e, 0x0b, 0, 0}, + {0x303f, 0xe3, 0, 0}, + {0x3040, 0xf3, 0, 0}, + {0x3041, 0x29, 0, 0}, + {0x3042, 0xf6, 0, 0}, + {0x3043, 0x65, 0, 0}, + {0x3044, 0x06, 0, 0}, + {0x3045, 0x0f, 0, 0}, + {0x3046, 0x59, 0, 0}, + {0x3047, 0x07, 0, 0}, + {0x3048, 0x82, 0, 0}, + {0x3049, 0xcf, 0, 0}, + {0x304a, 0x12, 0, 0}, + {0x304b, 0x40, 0, 0}, + {0x304c, 0x33, 0, 0}, + {0x304d, 0xa4, 0, 0}, + {0x304e, 0x0b, 0, 0}, + {0x304f, 0x3d, 0, 0}, + {0x3050, 0x10, 0, 0}, + {0x3060, 0x00, 0, 0}, + {0x3061, 0x64, 0, 0}, + {0x3062, 0x00, 0, 0}, + {0x3063, 0xe4, 0, 0}, + {0x3066, 0x80, 0, 0}, + {0x3080, 0x00, 0, 0}, + {0x3081, 0x00, 0, 0}, + {0x3082, 0x01, 0, 0}, + {0x3083, 0xe3, 0, 0}, + {0x3084, 0x06, 0, 0}, + {0x3085, 0x00, 0, 0}, + {0x3086, 0x10, 0, 0}, + {0x3087, 0x10, 0, 0}, + {0x3089, 0x00, 0, 0}, + {0x308a, 0x01, 0, 0}, + {0x3093, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x00, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x00, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x90, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x48, 0, 0}, + {0x30b0, 0x08, 0, 0}, + {0x30b1, 0xae, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x65, 0, 0}, + {0x30b4, 0x00, 0, 0}, + {0x30b5, 0x00, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x10, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x02, 0, 0}, + {0x30ba, 0x10, 0, 0}, + {0x30bb, 0x00, 0, 0}, + {0x30bc, 0x00, 0, 0}, + {0x30bd, 0x03, 0, 0}, + {0x30be, 0x5c, 0, 0}, + {0x30bf, 0x00, 0, 0}, + {0x30c0, 0x05, 0, 0}, + {0x30c1, 0x00, 0, 0}, + {0x30c2, 0x20, 0, 0}, + {0x30c3, 0x00, 0, 0}, + {0x30c4, 0x4a, 0, 0}, + {0x30c5, 0x00, 0, 0}, + {0x30c7, 0x00, 0, 0}, + {0x30c8, 0x00, 0, 0}, + {0x30d1, 0x00, 0, 0}, + {0x30d2, 0x00, 0, 0}, + {0x30d3, 0x80, 0, 0}, + {0x30d4, 0x00, 0, 0}, + {0x30d9, 0x09, 0, 0}, + {0x30da, 0x64, 0, 0}, + {0x30dd, 0x00, 0, 0}, + {0x30de, 0x16, 0, 0}, + {0x30df, 0x00, 0, 0}, + {0x30e0, 0x17, 0, 0}, + {0x30e1, 0x00, 0, 0}, + {0x30e2, 0x18, 0, 0}, + {0x30e3, 0x10, 0, 0}, + {0x30e4, 0x04, 0, 0}, + {0x30e5, 0x00, 0, 0}, + {0x30e6, 0x00, 0, 0}, + {0x30e7, 0x00, 0, 0}, + {0x30e8, 0x00, 0, 0}, + {0x30e9, 0x00, 0, 0}, + {0x30ea, 0x00, 0, 0}, + {0x30eb, 0x00, 0, 0}, + {0x30ec, 0x00, 0, 0}, + {0x30ed, 0x00, 0, 0}, + {0x3101, 0x00, 0, 0}, + {0x3102, 0x00, 0, 0}, + {0x3103, 0x00, 0, 0}, + {0x3104, 0x00, 0, 0}, + {0x3105, 0x8c, 0, 0}, + {0x3106, 0x87, 0, 0}, + {0x3107, 0xc0, 0, 0}, + {0x3108, 0x9d, 0, 0}, + {0x3109, 0x8d, 0, 0}, + {0x310a, 0x8d, 0, 0}, + {0x310b, 0x6a, 0, 0}, + {0x310c, 0x3a, 0, 0}, + {0x310d, 0x5a, 0, 0}, + {0x310e, 0x00, 0, 0}, + {0x3120, 0x00, 0, 0}, + {0x3121, 0x00, 0, 0}, + {0x3122, 0x00, 0, 0}, + {0x3123, 0x00, 0, 0}, + {0x3124, 0x00, 0, 0}, + {0x3125, 0x70, 0, 0}, + {0x3126, 0x1f, 0, 0}, + {0x3127, 0x0f, 0, 0}, + {0x3128, 0x00, 0, 0}, + {0x3129, 0x3a, 0, 0}, + {0x312a, 0x02, 0, 0}, + {0x312b, 0x0f, 0, 0}, + {0x312c, 0x00, 0, 0}, + {0x312d, 0x0f, 0, 0}, + {0x312e, 0x1d, 0, 0}, + {0x312f, 0x00, 0, 0}, + {0x3130, 0x00, 0, 0}, + {0x3131, 0x00, 0, 0}, + {0x3132, 0x00, 0, 0}, + {0x3140, 0x0a, 0, 0}, + {0x3141, 0x03, 0, 0}, + {0x3142, 0x00, 0, 0}, + {0x3143, 0x00, 0, 0}, + {0x3144, 0x00, 0, 0}, + {0x3145, 0x00, 0, 0}, + {0x3146, 0x00, 0, 0}, + {0x3147, 0x00, 0, 0}, + {0x3148, 0x00, 0, 0}, + {0x3149, 0x00, 0, 0}, + {0x314a, 0x00, 0, 0}, + {0x314b, 0x00, 0, 0}, + {0x314c, 0x00, 0, 0}, + {0x314d, 0x00, 0, 0}, + {0x314e, 0x1c, 0, 0}, + {0x314f, 0xff, 0, 0}, + {0x3150, 0xff, 0, 0}, + {0x3151, 0xff, 0, 0}, + {0x3152, 0x10, 0, 0}, + {0x3153, 0x10, 0, 0}, + {0x3154, 0x10, 0, 0}, + {0x3155, 0x00, 0, 0}, + {0x3156, 0x03, 0, 0}, + {0x3157, 0x00, 0, 0}, + {0x3158, 0x0f, 0, 0}, + {0x3159, 0xff, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x00, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x00, 0, 0}, + {0x3160, 0x00, 0, 0}, + {0x3161, 0x40, 0, 0}, + {0x3162, 0x00, 0, 0}, + {0x3163, 0x40, 0, 0}, + {0x3164, 0x00, 0, 0}, + {0x3165, 0x40, 0, 0}, + {0x3190, 0x05, 0, 0}, + {0x3191, 0x99, 0, 0}, + {0x3193, 0x08, 0, 0}, + {0x3194, 0x13, 0, 0}, + {0x3195, 0x33, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x10, 0, 0}, + {0x3198, 0x00, 0, 0}, + {0x3199, 0x3f, 0, 0}, + {0x319a, 0x40, 0, 0}, + {0x319b, 0x7f, 0, 0}, + {0x319c, 0x80, 0, 0}, + {0x319d, 0xbf, 0, 0}, + {0x319e, 0xc0, 0, 0}, + {0x319f, 0xff, 0, 0}, + {0x31a0, 0x24, 0, 0}, + {0x31a1, 0x55, 0, 0}, + {0x31a2, 0x00, 0, 0}, + {0x31a3, 0x00, 0, 0}, + {0x31a6, 0x00, 0, 0}, + {0x31a7, 0x00, 0, 0}, + {0x31b0, 0x00, 0, 0}, + {0x31b1, 0x00, 0, 0}, + {0x31b2, 0x02, 0, 0}, + {0x31b3, 0x00, 0, 0}, + {0x31b4, 0x00, 0, 0}, + {0x31b5, 0x01, 0, 0}, + {0x31b6, 0x00, 0, 0}, + {0x31b7, 0x00, 0, 0}, + {0x31b8, 0x00, 0, 0}, + {0x31b9, 0x00, 0, 0}, + {0x31ba, 0x00, 0, 0}, + {0x31d0, 0x3c, 0, 0}, + {0x31d1, 0x34, 0, 0}, + {0x31d2, 0x3c, 0, 0}, + {0x31d3, 0x00, 0, 0}, + {0x31d4, 0x2d, 0, 0}, + {0x31d5, 0x00, 0, 0}, + {0x31d6, 0x01, 0, 0}, + {0x31d7, 0x06, 0, 0}, + {0x31d8, 0x00, 0, 0}, + {0x31d9, 0x64, 0, 0}, + {0x31da, 0x00, 0, 0}, + {0x31db, 0x30, 0, 0}, + {0x31dc, 0x04, 0, 0}, + {0x31dd, 0x69, 0, 0}, + {0x31de, 0x0a, 0, 0}, + {0x31df, 0x3c, 0, 0}, + {0x31e0, 0x04, 0, 0}, + {0x31e1, 0x32, 0, 0}, + {0x31e2, 0x00, 0, 0}, + {0x31e3, 0x00, 0, 0}, + {0x31e4, 0x08, 0, 0}, + {0x31e5, 0x80, 0, 0}, + {0x31e6, 0x00, 0, 0}, + {0x31e7, 0x2c, 0, 0}, + {0x31e8, 0x6c, 0, 0}, + {0x31e9, 0xac, 0, 0}, + {0x31ea, 0xec, 0, 0}, + {0x31eb, 0x3f, 0, 0}, + {0x31ec, 0x07, 0, 0}, + {0x31ed, 0x80, 0, 0}, + {0x31ee, 0x04, 0, 0}, + {0x31ef, 0x38, 0, 0}, + {0x31f0, 0x07, 0, 0}, + {0x31f1, 0x80, 0, 0}, + {0x31f2, 0x04, 0, 0}, + {0x31f3, 0x38, 0, 0}, + {0x31f4, 0x07, 0, 0}, + {0x31f5, 0x80, 0, 0}, + {0x31f6, 0x04, 0, 0}, + {0x31f7, 0x38, 0, 0}, + {0x31f8, 0x07, 0, 0}, + {0x31f9, 0x80, 0, 0}, + {0x31fa, 0x04, 0, 0}, + {0x31fb, 0x38, 0, 0}, + {0x31fd, 0xcb, 0, 0}, + {0x31fe, 0x0f, 0, 0}, + {0x31ff, 0x03, 0, 0}, + {0x3200, 0x00, 0, 0}, + {0x3201, 0xff, 0, 0}, + {0x3202, 0x00, 0, 0}, + {0x3203, 0xff, 0, 0}, + {0x3204, 0xff, 0, 0}, + {0x3205, 0xff, 0, 0}, + {0x3206, 0xff, 0, 0}, + {0x3207, 0xff, 0, 0}, + {0x3208, 0xff, 0, 0}, + {0x3209, 0xff, 0, 0}, + {0x320a, 0xff, 0, 0}, + {0x320b, 0x1b, 0, 0}, + {0x320c, 0x1f, 0, 0}, + {0x320d, 0x1e, 0, 0}, + {0x320e, 0x30, 0, 0}, + {0x320f, 0x2d, 0, 0}, + {0x3210, 0x2c, 0, 0}, + {0x3211, 0x2b, 0, 0}, + {0x3212, 0x2a, 0, 0}, + {0x3213, 0x24, 0, 0}, + {0x3214, 0x22, 0, 0}, + {0x3215, 0x00, 0, 0}, + {0x3216, 0x04, 0, 0}, + {0x3217, 0x2c, 0, 0}, + {0x3218, 0x6c, 0, 0}, + {0x3219, 0xac, 0, 0}, + {0x321a, 0xec, 0, 0}, + {0x321b, 0x00, 0, 0}, + {0x3230, 0x3a, 0, 0}, + {0x3231, 0x00, 0, 0}, + {0x3232, 0x80, 0, 0}, + {0x3233, 0x00, 0, 0}, + {0x3234, 0x10, 0, 0}, + {0x3235, 0xaa, 0, 0}, + {0x3236, 0x55, 0, 0}, + {0x3237, 0x99, 0, 0}, + {0x3238, 0x66, 0, 0}, + {0x3239, 0x08, 0, 0}, + {0x323a, 0x88, 0, 0}, + {0x323b, 0x00, 0, 0}, + {0x323c, 0x00, 0, 0}, + {0x323d, 0x03, 0, 0}, + {0x3250, 0x33, 0, 0}, + {0x3251, 0x00, 0, 0}, + {0x3252, 0x20, 0, 0}, + {0x3253, 0x00, 0, 0}, + {0x3254, 0x11, 0, 0}, + {0x3255, 0x01, 0, 0}, + {0x3256, 0x00, 0, 0}, + {0x3257, 0x00, 0, 0}, + {0x3258, 0x00, 0, 0}, + {0x3270, 0x01, 0, 0}, + {0x3271, 0x60, 0, 0}, + {0x3272, 0xc0, 0, 0}, + {0x3273, 0x00, 0, 0}, + {0x3274, 0x80, 0, 0}, + {0x3275, 0x40, 0, 0}, + {0x3276, 0x02, 0, 0}, + {0x3277, 0x08, 0, 0}, + {0x3278, 0x10, 0, 0}, + {0x3279, 0x04, 0, 0}, + {0x327a, 0x00, 0, 0}, + {0x327b, 0x03, 0, 0}, + {0x327c, 0x10, 0, 0}, + {0x327d, 0x60, 0, 0}, + {0x327e, 0xc0, 0, 0}, + {0x327f, 0x06, 0, 0}, + {0x3288, 0x10, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x08, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x04, 0, 0}, + {0x328d, 0x00, 0, 0}, + {0x328e, 0x02, 0, 0}, + {0x328f, 0x00, 0, 0}, + {0x3290, 0x20, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x10, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x08, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x04, 0, 0}, + {0x3297, 0x00, 0, 0}, + {0x3298, 0x40, 0, 0}, + {0x3299, 0x00, 0, 0}, + {0x329a, 0x20, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x10, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x08, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x40, 0, 0}, + {0x32a3, 0x00, 0, 0}, + {0x32a4, 0x20, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x10, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32a8, 0x00, 0, 0}, + {0x32a9, 0x00, 0, 0}, + {0x32aa, 0x00, 0, 0}, + {0x32ab, 0x00, 0, 0}, + {0x32ac, 0x00, 0, 0}, + {0x32ad, 0x00, 0, 0}, + {0x32ae, 0x00, 0, 0}, + {0x32af, 0x00, 0, 0}, + {0x32b0, 0x00, 0, 0}, + {0x32b1, 0x00, 0, 0}, + {0x32b2, 0x00, 0, 0}, + {0x32b3, 0x00, 0, 0}, + {0x32b4, 0x00, 0, 0}, + {0x32b5, 0x00, 0, 0}, + {0x32b6, 0x00, 0, 0}, + {0x32b7, 0x00, 0, 0}, + {0x32b8, 0x00, 0, 0}, + {0x32b9, 0x00, 0, 0}, + {0x32ba, 0x00, 0, 0}, + {0x32bb, 0x00, 0, 0}, + {0x32bc, 0x00, 0, 0}, + {0x32bd, 0x00, 0, 0}, + {0x32be, 0x00, 0, 0}, + {0x32bf, 0x00, 0, 0}, + {0x32c0, 0x00, 0, 0}, + {0x32c1, 0x00, 0, 0}, + {0x32c2, 0x00, 0, 0}, + {0x32c3, 0x00, 0, 0}, + {0x32c4, 0x00, 0, 0}, + {0x32c5, 0x00, 0, 0}, + {0x32c6, 0x00, 0, 0}, + {0x32c7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x32c9, 0x00, 0, 0}, + {0x3330, 0x03, 0, 0}, + {0x3331, 0xc8, 0, 0}, + {0x3332, 0x02, 0, 0}, + {0x3333, 0x24, 0, 0}, + {0x3334, 0x00, 0, 0}, + {0x3335, 0x00, 0, 0}, + {0x3336, 0x00, 0, 0}, + {0x3337, 0x00, 0, 0}, + {0x3338, 0x03, 0, 0}, + {0x3339, 0xc8, 0, 0}, + {0x333a, 0x02, 0, 0}, + {0x333b, 0x24, 0, 0}, + {0x333c, 0x00, 0, 0}, + {0x333d, 0x00, 0, 0}, + {0x333e, 0x00, 0, 0}, + {0x333f, 0x00, 0, 0}, + {0x3340, 0x03, 0, 0}, + {0x3341, 0xc8, 0, 0}, + {0x3342, 0x02, 0, 0}, + {0x3343, 0x24, 0, 0}, + {0x3344, 0x00, 0, 0}, + {0x3345, 0x00, 0, 0}, + {0x3346, 0x00, 0, 0}, + {0x3347, 0x00, 0, 0}, + {0x3348, 0x40, 0, 0}, + {0x3349, 0x00, 0, 0}, + {0x334a, 0x00, 0, 0}, + {0x334b, 0x00, 0, 0}, + {0x334c, 0x00, 0, 0}, + {0x334d, 0x00, 0, 0}, + {0x334e, 0x80, 0, 0}, + {0x3360, 0x01, 0, 0}, + {0x3361, 0x00, 0, 0}, + {0x3362, 0x01, 0, 0}, + {0x3363, 0x00, 0, 0}, + {0x3364, 0x01, 0, 0}, + {0x3365, 0x00, 0, 0}, + {0x3366, 0x01, 0, 0}, + {0x3367, 0x00, 0, 0}, + {0x3368, 0x01, 0, 0}, + {0x3369, 0x00, 0, 0}, + {0x336a, 0x01, 0, 0}, + {0x336b, 0x00, 0, 0}, + {0x336c, 0x01, 0, 0}, + {0x336d, 0x00, 0, 0}, + {0x336e, 0x01, 0, 0}, + {0x336f, 0x00, 0, 0}, + {0x3370, 0x01, 0, 0}, + {0x3371, 0x00, 0, 0}, + {0x3372, 0x01, 0, 0}, + {0x3373, 0x00, 0, 0}, + {0x3374, 0x01, 0, 0}, + {0x3375, 0x00, 0, 0}, + {0x3376, 0x01, 0, 0}, + {0x3377, 0x00, 0, 0}, + {0x3378, 0x00, 0, 0}, + {0x3379, 0x00, 0, 0}, + {0x337a, 0x00, 0, 0}, + {0x337b, 0x00, 0, 0}, + {0x337c, 0x00, 0, 0}, + {0x337d, 0x00, 0, 0}, + {0x337e, 0x00, 0, 0}, + {0x337f, 0x00, 0, 0}, + {0x3380, 0x00, 0, 0}, + {0x3381, 0x00, 0, 0}, + {0x3382, 0x00, 0, 0}, + {0x3383, 0x00, 0, 0}, + {0x3384, 0x00, 0, 0}, + {0x3385, 0x00, 0, 0}, + {0x3386, 0x00, 0, 0}, + {0x3387, 0x00, 0, 0}, + {0x3388, 0x00, 0, 0}, + {0x3389, 0x00, 0, 0}, + {0x338a, 0x00, 0, 0}, + {0x338b, 0x00, 0, 0}, + {0x338c, 0x00, 0, 0}, + {0x338d, 0x00, 0, 0}, + {0x338e, 0x00, 0, 0}, + {0x338f, 0x00, 0, 0}, + {0x3390, 0x00, 0, 0}, + {0x3391, 0x00, 0, 0}, + {0x3392, 0x00, 0, 0}, + {0x3393, 0x00, 0, 0}, + {0x3394, 0x00, 0, 0}, + {0x3395, 0x00, 0, 0}, + {0x3396, 0x00, 0, 0}, + {0x3397, 0x00, 0, 0}, + {0x3398, 0x00, 0, 0}, + {0x3399, 0x00, 0, 0}, + {0x339a, 0x00, 0, 0}, + {0x339b, 0x00, 0, 0}, + {0x33b0, 0x00, 0, 0}, + {0x33b1, 0x50, 0, 0}, + {0x33b2, 0x01, 0, 0}, + {0x33b3, 0xff, 0, 0}, + {0x33b4, 0xe0, 0, 0}, + {0x33b5, 0x6b, 0, 0}, + {0x33b6, 0x00, 0, 0}, + {0x33b7, 0x00, 0, 0}, + {0x33b8, 0x00, 0, 0}, + {0x33b9, 0x00, 0, 0}, + {0x33ba, 0x00, 0, 0}, + {0x33bb, 0x1f, 0, 0}, + {0x33bc, 0x01, 0, 0}, + {0x33bd, 0x01, 0, 0}, + {0x33be, 0x01, 0, 0}, + {0x33bf, 0x01, 0, 0}, + {0x33c0, 0x00, 0, 0}, + {0x33c1, 0x00, 0, 0}, + {0x33c2, 0x00, 0, 0}, + {0x33c3, 0x00, 0, 0}, + {0x33e0, 0x14, 0, 0}, + {0x33e1, 0x0f, 0, 0}, + {0x33e2, 0x04, 0, 0}, + {0x33e3, 0x02, 0, 0}, + {0x33e4, 0x01, 0, 0}, + {0x33e5, 0x01, 0, 0}, + {0x33e6, 0x00, 0, 0}, + {0x33e7, 0x04, 0, 0}, + {0x33e8, 0x0c, 0, 0}, + {0x33e9, 0x02, 0, 0}, + {0x33ea, 0x02, 0, 0}, + {0x33eb, 0x02, 0, 0}, + {0x33ec, 0x03, 0, 0}, + {0x33ed, 0x02, 0, 0}, + {0x33ee, 0x05, 0, 0}, + {0x33ef, 0x0a, 0, 0}, + {0x33f0, 0x08, 0, 0}, + {0x33f1, 0x04, 0, 0}, + {0x33f2, 0x04, 0, 0}, + {0x33f3, 0x00, 0, 0}, + {0x33f4, 0x03, 0, 0}, + {0x33f5, 0x14, 0, 0}, + {0x33f6, 0x0f, 0, 0}, + {0x33f7, 0x02, 0, 0}, + {0x33f8, 0x01, 0, 0}, + {0x33f9, 0x01, 0, 0}, + {0x33fa, 0x01, 0, 0}, + {0x33fb, 0x00, 0, 0}, + {0x33fc, 0x04, 0, 0}, + {0x33fd, 0x0c, 0, 0}, + {0x33fe, 0x02, 0, 0}, + {0x33ff, 0x02, 0, 0}, + {0x3400, 0x02, 0, 0}, + {0x3401, 0x03, 0, 0}, + {0x3402, 0x01, 0, 0}, + {0x3403, 0x02, 0, 0}, + {0x3404, 0x08, 0, 0}, + {0x3405, 0x08, 0, 0}, + {0x3406, 0x04, 0, 0}, + {0x3407, 0x04, 0, 0}, + {0x3408, 0x00, 0, 0}, + {0x3409, 0x03, 0, 0}, + {0x340a, 0x14, 0, 0}, + {0x340b, 0x0f, 0, 0}, + {0x340c, 0x04, 0, 0}, + {0x340d, 0x02, 0, 0}, + {0x340e, 0x01, 0, 0}, + {0x340f, 0x01, 0, 0}, + {0x3410, 0x00, 0, 0}, + {0x3411, 0x04, 0, 0}, + {0x3412, 0x0c, 0, 0}, + {0x3413, 0x02, 0, 0}, + {0x3414, 0x02, 0, 0}, + {0x3415, 0x02, 0, 0}, + {0x3416, 0x03, 0, 0}, + {0x3417, 0x02, 0, 0}, + {0x3418, 0x05, 0, 0}, + {0x3419, 0x0a, 0, 0}, + {0x341a, 0x08, 0, 0}, + {0x341b, 0x04, 0, 0}, + {0x341c, 0x04, 0, 0}, + {0x341d, 0x00, 0, 0}, + {0x341e, 0x03, 0, 0}, + {0x3440, 0x00, 0, 0}, + {0x3441, 0x00, 0, 0}, + {0x3442, 0x00, 0, 0}, + {0x3443, 0x00, 0, 0}, + {0x3444, 0x02, 0, 0}, + {0x3445, 0xf0, 0, 0}, + {0x3446, 0x02, 0, 0}, + {0x3447, 0x08, 0, 0}, + {0x3448, 0x00, 0, 0}, + {0x3460, 0x40, 0, 0}, + {0x3461, 0x40, 0, 0}, + {0x3462, 0x40, 0, 0}, + {0x3463, 0x40, 0, 0}, + {0x3464, 0x03, 0, 0}, + {0x3465, 0x01, 0, 0}, + {0x3466, 0x01, 0, 0}, + {0x3467, 0x02, 0, 0}, + {0x3468, 0x30, 0, 0}, + {0x3469, 0x00, 0, 0}, + {0x346a, 0x35, 0, 0}, + {0x346b, 0x00, 0, 0}, + {0x3480, 0x40, 0, 0}, + {0x3481, 0x00, 0, 0}, + {0x3482, 0x00, 0, 0}, + {0x3483, 0x00, 0, 0}, + {0x3484, 0x0d, 0, 0}, + {0x3485, 0x00, 0, 0}, + {0x3486, 0x00, 0, 0}, + {0x3487, 0x00, 0, 0}, + {0x3488, 0x00, 0, 0}, + {0x3489, 0x00, 0, 0}, + {0x348a, 0x00, 0, 0}, + {0x348b, 0x04, 0, 0}, + {0x348c, 0x00, 0, 0}, + {0x348d, 0x01, 0, 0}, + {0x348f, 0x01, 0, 0}, + {0x3030, 0x0a, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x7000, 0x58, 0, 0}, + {0x7001, 0x7a, 0, 0}, + {0x7002, 0x1a, 0, 0}, + {0x7003, 0xc1, 0, 0}, + {0x7004, 0x03, 0, 0}, + {0x7005, 0xda, 0, 0}, + {0x7006, 0xbd, 0, 0}, + {0x7007, 0x03, 0, 0}, + {0x7008, 0xbd, 0, 0}, + {0x7009, 0x06, 0, 0}, + {0x700a, 0xe6, 0, 0}, + {0x700b, 0xec, 0, 0}, + {0x700c, 0xbc, 0, 0}, + {0x700d, 0xff, 0, 0}, + {0x700e, 0xbc, 0, 0}, + {0x700f, 0x73, 0, 0}, + {0x7010, 0xda, 0, 0}, + {0x7011, 0x72, 0, 0}, + {0x7012, 0x76, 0, 0}, + {0x7013, 0xb6, 0, 0}, + {0x7014, 0xee, 0, 0}, + {0x7015, 0xcf, 0, 0}, + {0x7016, 0xac, 0, 0}, + {0x7017, 0xd0, 0, 0}, + {0x7018, 0xac, 0, 0}, + {0x7019, 0xd1, 0, 0}, + {0x701a, 0x50, 0, 0}, + {0x701b, 0xac, 0, 0}, + {0x701c, 0xd2, 0, 0}, + {0x701d, 0xbc, 0, 0}, + {0x701e, 0x2e, 0, 0}, + {0x701f, 0xb4, 0, 0}, + {0x7020, 0x00, 0, 0}, + {0x7021, 0xdc, 0, 0}, + {0x7022, 0xdf, 0, 0}, + {0x7023, 0xb0, 0, 0}, + {0x7024, 0x6e, 0, 0}, + {0x7025, 0xbd, 0, 0}, + {0x7026, 0x01, 0, 0}, + {0x7027, 0xd7, 0, 0}, + {0x7028, 0xed, 0, 0}, + {0x7029, 0xe1, 0, 0}, + {0x702a, 0x36, 0, 0}, + {0x702b, 0x30, 0, 0}, + {0x702c, 0xd3, 0, 0}, + {0x702d, 0x2e, 0, 0}, + {0x702e, 0x54, 0, 0}, + {0x702f, 0x46, 0, 0}, + {0x7030, 0xbc, 0, 0}, + {0x7031, 0x22, 0, 0}, + {0x7032, 0x66, 0, 0}, + {0x7033, 0xbc, 0, 0}, + {0x7034, 0x24, 0, 0}, + {0x7035, 0x2c, 0, 0}, + {0x7036, 0x28, 0, 0}, + {0x7037, 0xbc, 0, 0}, + {0x7038, 0x3c, 0, 0}, + {0x7039, 0xa1, 0, 0}, + {0x703a, 0xac, 0, 0}, + {0x703b, 0xd8, 0, 0}, + {0x703c, 0xd6, 0, 0}, + {0x703d, 0xb4, 0, 0}, + {0x703e, 0x04, 0, 0}, + {0x703f, 0x46, 0, 0}, + {0x7040, 0xb7, 0, 0}, + {0x7041, 0x04, 0, 0}, + {0x7042, 0xbe, 0, 0}, + {0x7043, 0x08, 0, 0}, + {0x7044, 0xc3, 0, 0}, + {0x7045, 0xd9, 0, 0}, + {0x7046, 0xad, 0, 0}, + {0x7047, 0xc3, 0, 0}, + {0x7048, 0xbc, 0, 0}, + {0x7049, 0x19, 0, 0}, + {0x704a, 0xc1, 0, 0}, + {0x704b, 0x27, 0, 0}, + {0x704c, 0xe7, 0, 0}, + {0x704d, 0x00, 0, 0}, + {0x704e, 0x50, 0, 0}, + {0x704f, 0x20, 0, 0}, + {0x7050, 0xb8, 0, 0}, + {0x7051, 0x02, 0, 0}, + {0x7052, 0xbc, 0, 0}, + {0x7053, 0x17, 0, 0}, + {0x7054, 0xdb, 0, 0}, + {0x7055, 0xc7, 0, 0}, + {0x7056, 0xb8, 0, 0}, + {0x7057, 0x00, 0, 0}, + {0x7058, 0x28, 0, 0}, + {0x7059, 0x54, 0, 0}, + {0x705a, 0xb4, 0, 0}, + {0x705b, 0x14, 0, 0}, + {0x705c, 0xab, 0, 0}, + {0x705d, 0xbe, 0, 0}, + {0x705e, 0x06, 0, 0}, + {0x705f, 0xd8, 0, 0}, + {0x7060, 0xd6, 0, 0}, + {0x7061, 0x00, 0, 0}, + {0x7062, 0xb4, 0, 0}, + {0x7063, 0xc7, 0, 0}, + {0x7064, 0x07, 0, 0}, + {0x7065, 0xb9, 0, 0}, + {0x7066, 0x05, 0, 0}, + {0x7067, 0xee, 0, 0}, + {0x7068, 0xe6, 0, 0}, + {0x7069, 0xad, 0, 0}, + {0x706a, 0xb4, 0, 0}, + {0x706b, 0x26, 0, 0}, + {0x706c, 0x19, 0, 0}, + {0x706d, 0xc1, 0, 0}, + {0x706e, 0x3a, 0, 0}, + {0x706f, 0xc3, 0, 0}, + {0x7070, 0xaf, 0, 0}, + {0x7071, 0x00, 0, 0}, + {0x7072, 0xc0, 0, 0}, + {0x7073, 0x3c, 0, 0}, + {0x7074, 0xc3, 0, 0}, + {0x7075, 0xbe, 0, 0}, + {0x7076, 0xe7, 0, 0}, + {0x7077, 0x00, 0, 0}, + {0x7078, 0x15, 0, 0}, + {0x7079, 0xc2, 0, 0}, + {0x707a, 0x40, 0, 0}, + {0x707b, 0xc3, 0, 0}, + {0x707c, 0xa4, 0, 0}, + {0x707d, 0xc0, 0, 0}, + {0x707e, 0x3c, 0, 0}, + {0x707f, 0x00, 0, 0}, + {0x7080, 0xb9, 0, 0}, + {0x7081, 0x64, 0, 0}, + {0x7082, 0x29, 0, 0}, + {0x7083, 0x00, 0, 0}, + {0x7084, 0xb8, 0, 0}, + {0x7085, 0x12, 0, 0}, + {0x7086, 0xbe, 0, 0}, + {0x7087, 0x01, 0, 0}, + {0x7088, 0xd0, 0, 0}, + {0x7089, 0xbc, 0, 0}, + {0x708a, 0x01, 0, 0}, + {0x708b, 0xac, 0, 0}, + {0x708c, 0x37, 0, 0}, + {0x708d, 0xd2, 0, 0}, + {0x708e, 0xac, 0, 0}, + {0x708f, 0x45, 0, 0}, + {0x7090, 0xad, 0, 0}, + {0x7091, 0x28, 0, 0}, + {0x7092, 0x00, 0, 0}, + {0x7093, 0xb8, 0, 0}, + {0x7094, 0x00, 0, 0}, + {0x7095, 0xbc, 0, 0}, + {0x7096, 0x01, 0, 0}, + {0x7097, 0x36, 0, 0}, + {0x7098, 0xd3, 0, 0}, + {0x7099, 0x30, 0, 0}, + {0x709a, 0x04, 0, 0}, + {0x709b, 0xe0, 0, 0}, + {0x709c, 0xd8, 0, 0}, + {0x709d, 0xb4, 0, 0}, + {0x709e, 0xe9, 0, 0}, + {0x709f, 0x00, 0, 0}, + {0x70a0, 0xbe, 0, 0}, + {0x70a1, 0x05, 0, 0}, + {0x70a2, 0x62, 0, 0}, + {0x70a3, 0x07, 0, 0}, + {0x70a4, 0xb9, 0, 0}, + {0x70a5, 0x05, 0, 0}, + {0x70a6, 0xad, 0, 0}, + {0x70a7, 0xc3, 0, 0}, + {0x70a8, 0xcf, 0, 0}, + {0x70a9, 0x00, 0, 0}, + {0x70aa, 0x15, 0, 0}, + {0x70ab, 0xc2, 0, 0}, + {0x70ac, 0x59, 0, 0}, + {0x70ad, 0xc3, 0, 0}, + {0x70ae, 0xc9, 0, 0}, + {0x70af, 0xc0, 0, 0}, + {0x70b0, 0x55, 0, 0}, + {0x70b1, 0x00, 0, 0}, + {0x70b2, 0x46, 0, 0}, + {0x70b3, 0xa1, 0, 0}, + {0x70b4, 0xb9, 0, 0}, + {0x70b5, 0x64, 0, 0}, + {0x70b6, 0x29, 0, 0}, + {0x70b7, 0x00, 0, 0}, + {0x70b8, 0xb8, 0, 0}, + {0x70b9, 0x02, 0, 0}, + {0x70ba, 0xbe, 0, 0}, + {0x70bb, 0x02, 0, 0}, + {0x70bc, 0xd0, 0, 0}, + {0x70bd, 0xdc, 0, 0}, + {0x70be, 0xac, 0, 0}, + {0x70bf, 0xbc, 0, 0}, + {0x70c0, 0x01, 0, 0}, + {0x70c1, 0x37, 0, 0}, + {0x70c2, 0xac, 0, 0}, + {0x70c3, 0xd2, 0, 0}, + {0x70c4, 0x45, 0, 0}, + {0x70c5, 0xad, 0, 0}, + {0x70c6, 0x28, 0, 0}, + {0x70c7, 0x00, 0, 0}, + {0x70c8, 0xb8, 0, 0}, + {0x70c9, 0x00, 0, 0}, + {0x70ca, 0xbc, 0, 0}, + {0x70cb, 0x01, 0, 0}, + {0x70cc, 0x36, 0, 0}, + {0x70cd, 0x30, 0, 0}, + {0x70ce, 0xe0, 0, 0}, + {0x70cf, 0xd8, 0, 0}, + {0x70d0, 0xb5, 0, 0}, + {0x70d1, 0x0b, 0, 0}, + {0x70d2, 0xd6, 0, 0}, + {0x70d3, 0xbe, 0, 0}, + {0x70d4, 0x07, 0, 0}, + {0x70d5, 0x00, 0, 0}, + {0x70d6, 0x62, 0, 0}, + {0x70d7, 0x07, 0, 0}, + {0x70d8, 0xb9, 0, 0}, + {0x70d9, 0x05, 0, 0}, + {0x70da, 0xad, 0, 0}, + {0x70db, 0xc3, 0, 0}, + {0x70dc, 0xcf, 0, 0}, + {0x70dd, 0x46, 0, 0}, + {0x70de, 0xcd, 0, 0}, + {0x70df, 0x07, 0, 0}, + {0x70e0, 0xcd, 0, 0}, + {0x70e1, 0x00, 0, 0}, + {0x70e2, 0xe3, 0, 0}, + {0x70e3, 0x18, 0, 0}, + {0x70e4, 0xc2, 0, 0}, + {0x70e5, 0xa2, 0, 0}, + {0x70e6, 0xb9, 0, 0}, + {0x70e7, 0x64, 0, 0}, + {0x70e8, 0xd1, 0, 0}, + {0x70e9, 0xdd, 0, 0}, + {0x70ea, 0xac, 0, 0}, + {0x70eb, 0xcf, 0, 0}, + {0x70ec, 0xdf, 0, 0}, + {0x70ed, 0xb5, 0, 0}, + {0x70ee, 0x19, 0, 0}, + {0x70ef, 0x46, 0, 0}, + {0x70f0, 0x50, 0, 0}, + {0x70f1, 0xb6, 0, 0}, + {0x70f2, 0xee, 0, 0}, + {0x70f3, 0xe8, 0, 0}, + {0x70f4, 0xe6, 0, 0}, + {0x70f5, 0xbc, 0, 0}, + {0x70f6, 0x31, 0, 0}, + {0x70f7, 0xe1, 0, 0}, + {0x70f8, 0x36, 0, 0}, + {0x70f9, 0x30, 0, 0}, + {0x70fa, 0xd3, 0, 0}, + {0x70fb, 0x2e, 0, 0}, + {0x70fc, 0x54, 0, 0}, + {0x70fd, 0xbd, 0, 0}, + {0x70fe, 0x03, 0, 0}, + {0x70ff, 0xec, 0, 0}, + {0x7100, 0x2c, 0, 0}, + {0x7101, 0x50, 0, 0}, + {0x7102, 0x20, 0, 0}, + {0x7103, 0x04, 0, 0}, + {0x7104, 0xb8, 0, 0}, + {0x7105, 0x02, 0, 0}, + {0x7106, 0xbc, 0, 0}, + {0x7107, 0x18, 0, 0}, + {0x7108, 0xc7, 0, 0}, + {0x7109, 0xb8, 0, 0}, + {0x710a, 0x00, 0, 0}, + {0x710b, 0x28, 0, 0}, + {0x710c, 0x54, 0, 0}, + {0x710d, 0xbc, 0, 0}, + {0x710e, 0x02, 0, 0}, + {0x710f, 0xb4, 0, 0}, + {0x7110, 0xda, 0, 0}, + {0x7111, 0xbe, 0, 0}, + {0x7112, 0x04, 0, 0}, + {0x7113, 0xd6, 0, 0}, + {0x7114, 0xd8, 0, 0}, + {0x7115, 0xab, 0, 0}, + {0x7116, 0x00, 0, 0}, + {0x7117, 0x62, 0, 0}, + {0x7118, 0x07, 0, 0}, + {0x7119, 0xb9, 0, 0}, + {0x711a, 0x05, 0, 0}, + {0x711b, 0xad, 0, 0}, + {0x711c, 0xc3, 0, 0}, + {0x711d, 0xbc, 0, 0}, + {0x711e, 0xe7, 0, 0}, + {0x711f, 0xb9, 0, 0}, + {0x7120, 0x64, 0, 0}, + {0x7121, 0x29, 0, 0}, + {0x7122, 0x00, 0, 0}, + {0x7123, 0xb8, 0, 0}, + {0x7124, 0x02, 0, 0}, + {0x7125, 0xbe, 0, 0}, + {0x7126, 0x00, 0, 0}, + {0x7127, 0x45, 0, 0}, + {0x7128, 0xad, 0, 0}, + {0x7129, 0xe2, 0, 0}, + {0x712a, 0x28, 0, 0}, + {0x712b, 0x00, 0, 0}, + {0x712c, 0xb8, 0, 0}, + {0x712d, 0x00, 0, 0}, + {0x712e, 0xe0, 0, 0}, + {0x712f, 0xd8, 0, 0}, + {0x7130, 0xb4, 0, 0}, + {0x7131, 0xe9, 0, 0}, + {0x7132, 0xbe, 0, 0}, + {0x7133, 0x03, 0, 0}, + {0x7134, 0x00, 0, 0}, + {0x7135, 0x30, 0, 0}, + {0x7136, 0x62, 0, 0}, + {0x7137, 0x07, 0, 0}, + {0x7138, 0xb9, 0, 0}, + {0x7139, 0x05, 0, 0}, + {0x713a, 0xad, 0, 0}, + {0x713b, 0xc3, 0, 0}, + {0x713c, 0xcf, 0, 0}, + {0x713d, 0x42, 0, 0}, + {0x713e, 0xe4, 0, 0}, + {0x713f, 0xcd, 0, 0}, + {0x7140, 0x07, 0, 0}, + {0x7141, 0xcd, 0, 0}, + {0x7142, 0x00, 0, 0}, + {0x7143, 0x00, 0, 0}, + {0x7144, 0x17, 0, 0}, + {0x7145, 0xc2, 0, 0}, + {0x7146, 0xbb, 0, 0}, + {0x7147, 0xde, 0, 0}, + {0x7148, 0xcf, 0, 0}, + {0x7149, 0xdf, 0, 0}, + {0x714a, 0xac, 0, 0}, + {0x714b, 0xd1, 0, 0}, + {0x714c, 0x44, 0, 0}, + {0x714d, 0xac, 0, 0}, + {0x714e, 0xb9, 0, 0}, + {0x714f, 0x76, 0, 0}, + {0x7150, 0xb8, 0, 0}, + {0x7151, 0x08, 0, 0}, + {0x7152, 0xb6, 0, 0}, + {0x7153, 0xfe, 0, 0}, + {0x7154, 0xb4, 0, 0}, + {0x7155, 0xca, 0, 0}, + {0x7156, 0xd6, 0, 0}, + {0x7157, 0xd8, 0, 0}, + {0x7158, 0xab, 0, 0}, + {0x7159, 0x00, 0, 0}, + {0x715a, 0xe1, 0, 0}, + {0x715b, 0x36, 0, 0}, + {0x715c, 0x30, 0, 0}, + {0x715d, 0xd3, 0, 0}, + {0x715e, 0xbc, 0, 0}, + {0x715f, 0x29, 0, 0}, + {0x7160, 0xb4, 0, 0}, + {0x7161, 0x1f, 0, 0}, + {0x7162, 0xaa, 0, 0}, + {0x7163, 0xbd, 0, 0}, + {0x7164, 0x01, 0, 0}, + {0x7165, 0xb8, 0, 0}, + {0x7166, 0x0c, 0, 0}, + {0x7167, 0x45, 0, 0}, + {0x7168, 0xa4, 0, 0}, + {0x7169, 0xbd, 0, 0}, + {0x716a, 0x03, 0, 0}, + {0x716b, 0xec, 0, 0}, + {0x716c, 0xbc, 0, 0}, + {0x716d, 0x3d, 0, 0}, + {0x716e, 0xc3, 0, 0}, + {0x716f, 0xcf, 0, 0}, + {0x7170, 0x42, 0, 0}, + {0x7171, 0xb8, 0, 0}, + {0x7172, 0x00, 0, 0}, + {0x7173, 0xe4, 0, 0}, + {0x7174, 0xd5, 0, 0}, + {0x7175, 0x00, 0, 0}, + {0x7176, 0xb6, 0, 0}, + {0x7177, 0x00, 0, 0}, + {0x7178, 0x74, 0, 0}, + {0x7179, 0xbd, 0, 0}, + {0x717a, 0x03, 0, 0}, + {0x717b, 0xb5, 0, 0}, + {0x717c, 0x39, 0, 0}, + {0x717d, 0x40, 0, 0}, + {0x717e, 0x58, 0, 0}, + {0x717f, 0xdd, 0, 0}, + {0x7180, 0x19, 0, 0}, + {0x7181, 0xc1, 0, 0}, + {0x7182, 0xc8, 0, 0}, + {0x7183, 0xbd, 0, 0}, + {0x7184, 0x06, 0, 0}, + {0x7185, 0x17, 0, 0}, + {0x7186, 0xc1, 0, 0}, + {0x7187, 0xc6, 0, 0}, + {0x7188, 0xe8, 0, 0}, + {0x7189, 0x00, 0, 0}, + {0x718a, 0xc0, 0, 0}, + {0x718b, 0xc8, 0, 0}, + {0x718c, 0xe6, 0, 0}, + {0x718d, 0x95, 0, 0}, + {0x718e, 0x15, 0, 0}, + {0x718f, 0x00, 0, 0}, + {0x7190, 0xbc, 0, 0}, + {0x7191, 0x19, 0, 0}, + {0x7192, 0xb9, 0, 0}, + {0x7193, 0xf6, 0, 0}, + {0x7194, 0x14, 0, 0}, + {0x7195, 0xc1, 0, 0}, + {0x7196, 0xd0, 0, 0}, + {0x7197, 0xd1, 0, 0}, + {0x7198, 0xac, 0, 0}, + {0x7199, 0x37, 0, 0}, + {0x719a, 0xbc, 0, 0}, + {0x719b, 0x35, 0, 0}, + {0x719c, 0x36, 0, 0}, + {0x719d, 0x30, 0, 0}, + {0x719e, 0xe1, 0, 0}, + {0x719f, 0xd3, 0, 0}, + {0x71a0, 0x7a, 0, 0}, + {0x71a1, 0xb6, 0, 0}, + {0x71a2, 0x0c, 0, 0}, + {0x71a3, 0xff, 0, 0}, + {0x71a4, 0xb4, 0, 0}, + {0x71a5, 0xc7, 0, 0}, + {0x71a6, 0xd9, 0, 0}, + {0x71a7, 0x00, 0, 0}, + {0x71a8, 0xbd, 0, 0}, + {0x71a9, 0x01, 0, 0}, + {0x71aa, 0x56, 0, 0}, + {0x71ab, 0xc0, 0, 0}, + {0x71ac, 0xda, 0, 0}, + {0x71ad, 0xb4, 0, 0}, + {0x71ae, 0x1f, 0, 0}, + {0x71af, 0x56, 0, 0}, + {0x71b0, 0xaa, 0, 0}, + {0x71b1, 0xbc, 0, 0}, + {0x71b2, 0x08, 0, 0}, + {0x71b3, 0x00, 0, 0}, + {0x71b4, 0x57, 0, 0}, + {0x71b5, 0xe8, 0, 0}, + {0x71b6, 0xb5, 0, 0}, + {0x71b7, 0x36, 0, 0}, + {0x71b8, 0x00, 0, 0}, + {0x71b9, 0x54, 0, 0}, + {0x71ba, 0xe7, 0, 0}, + {0x71bb, 0xc8, 0, 0}, + {0x71bc, 0xb4, 0, 0}, + {0x71bd, 0x1f, 0, 0}, + {0x71be, 0x56, 0, 0}, + {0x71bf, 0xaa, 0, 0}, + {0x71c0, 0xbc, 0, 0}, + {0x71c1, 0x08, 0, 0}, + {0x71c2, 0x57, 0, 0}, + {0x71c3, 0x00, 0, 0}, + {0x71c4, 0xb5, 0, 0}, + {0x71c5, 0x36, 0, 0}, + {0x71c6, 0x00, 0, 0}, + {0x71c7, 0x54, 0, 0}, + {0x71c8, 0xc8, 0, 0}, + {0x71c9, 0xb5, 0, 0}, + {0x71ca, 0x18, 0, 0}, + {0x71cb, 0xd9, 0, 0}, + {0x71cc, 0x00, 0, 0}, + {0x71cd, 0xbd, 0, 0}, + {0x71ce, 0x01, 0, 0}, + {0x71cf, 0x56, 0, 0}, + {0x71d0, 0x08, 0, 0}, + {0x71d1, 0x57, 0, 0}, + {0x71d2, 0xe8, 0, 0}, + {0x71d3, 0xb4, 0, 0}, + {0x71d4, 0x42, 0, 0}, + {0x71d5, 0x00, 0, 0}, + {0x71d6, 0x54, 0, 0}, + {0x71d7, 0xe7, 0, 0}, + {0x71d8, 0xc8, 0, 0}, + {0x71d9, 0xab, 0, 0}, + {0x71da, 0x00, 0, 0}, + {0x71db, 0x66, 0, 0}, + {0x71dc, 0x62, 0, 0}, + {0x71dd, 0x06, 0, 0}, + {0x71de, 0x74, 0, 0}, + {0x71df, 0xb9, 0, 0}, + {0x71e0, 0x05, 0, 0}, + {0x71e1, 0xb7, 0, 0}, + {0x71e2, 0x14, 0, 0}, + {0x71e3, 0x0e, 0, 0}, + {0x71e4, 0xb7, 0, 0}, + {0x71e5, 0x04, 0, 0}, + {0x71e6, 0xc8, 0, 0}, + {0x7600, 0x04, 0, 0}, + {0x7601, 0x80, 0, 0}, + {0x7602, 0x07, 0, 0}, + {0x7603, 0x44, 0, 0}, + {0x7604, 0x05, 0, 0}, + {0x7605, 0x33, 0, 0}, + {0x7606, 0x0f, 0, 0}, + {0x7607, 0x00, 0, 0}, + {0x7608, 0x07, 0, 0}, + {0x7609, 0x40, 0, 0}, + {0x760a, 0x04, 0, 0}, + {0x760b, 0xe5, 0, 0}, + {0x760c, 0x06, 0, 0}, + {0x760d, 0x50, 0, 0}, + {0x760e, 0x04, 0, 0}, + {0x760f, 0xe4, 0, 0}, + {0x7610, 0x00, 0, 0}, + {0x7611, 0x00, 0, 0}, + {0x7612, 0x06, 0, 0}, + {0x7613, 0x5c, 0, 0}, + {0x7614, 0x00, 0, 0}, + {0x7615, 0x0f, 0, 0}, + {0x7616, 0x06, 0, 0}, + {0x7617, 0x1c, 0, 0}, + {0x7618, 0x00, 0, 0}, + {0x7619, 0x02, 0, 0}, + {0x761a, 0x06, 0, 0}, + {0x761b, 0xa2, 0, 0}, + {0x761c, 0x00, 0, 0}, + {0x761d, 0x01, 0, 0}, + {0x761e, 0x06, 0, 0}, + {0x761f, 0xae, 0, 0}, + {0x7620, 0x00, 0, 0}, + {0x7621, 0x0e, 0, 0}, + {0x7622, 0x05, 0, 0}, + {0x7623, 0x30, 0, 0}, + {0x7624, 0x07, 0, 0}, + {0x7625, 0x00, 0, 0}, + {0x7626, 0x0f, 0, 0}, + {0x7627, 0x00, 0, 0}, + {0x7628, 0x04, 0, 0}, + {0x7629, 0xe5, 0, 0}, + {0x762a, 0x05, 0, 0}, + {0x762b, 0x33, 0, 0}, + {0x762c, 0x06, 0, 0}, + {0x762d, 0x12, 0, 0}, + {0x762e, 0x00, 0, 0}, + {0x762f, 0x01, 0, 0}, + {0x7630, 0x06, 0, 0}, + {0x7631, 0x52, 0, 0}, + {0x7632, 0x00, 0, 0}, + {0x7633, 0x01, 0, 0}, + {0x7634, 0x06, 0, 0}, + {0x7635, 0x5e, 0, 0}, + {0x7636, 0x04, 0, 0}, + {0x7637, 0xe4, 0, 0}, + {0x7638, 0x00, 0, 0}, + {0x7639, 0x01, 0, 0}, + {0x763a, 0x05, 0, 0}, + {0x763b, 0x30, 0, 0}, + {0x763c, 0x0f, 0, 0}, + {0x763d, 0x00, 0, 0}, + {0x763e, 0x06, 0, 0}, + {0x763f, 0xa6, 0, 0}, + {0x7640, 0x00, 0, 0}, + {0x7641, 0x02, 0, 0}, + {0x7642, 0x06, 0, 0}, + {0x7643, 0x26, 0, 0}, + {0x7644, 0x00, 0, 0}, + {0x7645, 0x02, 0, 0}, + {0x7646, 0x05, 0, 0}, + {0x7647, 0x33, 0, 0}, + {0x7648, 0x06, 0, 0}, + {0x7649, 0x20, 0, 0}, + {0x764a, 0x0f, 0, 0}, + {0x764b, 0x00, 0, 0}, + {0x764c, 0x06, 0, 0}, + {0x764d, 0x56, 0, 0}, + {0x764e, 0x00, 0, 0}, + {0x764f, 0x02, 0, 0}, + {0x7650, 0x06, 0, 0}, + {0x7651, 0x16, 0, 0}, + {0x7652, 0x05, 0, 0}, + {0x7653, 0x33, 0, 0}, + {0x7654, 0x06, 0, 0}, + {0x7655, 0x10, 0, 0}, + {0x7656, 0x0f, 0, 0}, + {0x7657, 0x00, 0, 0}, + {0x7658, 0x06, 0, 0}, + {0x7659, 0x10, 0, 0}, + {0x765a, 0x0f, 0, 0}, + {0x765b, 0x00, 0, 0}, + {0x765c, 0x06, 0, 0}, + {0x765d, 0x20, 0, 0}, + {0x765e, 0x0f, 0, 0}, + {0x765f, 0x00, 0, 0}, + {0x7660, 0x00, 0, 0}, + {0x7661, 0x00, 0, 0}, + {0x7662, 0x00, 0, 0}, + {0x7663, 0x02, 0, 0}, + {0x7664, 0x04, 0, 0}, + {0x7665, 0xe5, 0, 0}, + {0x7666, 0x04, 0, 0}, + {0x7667, 0xe4, 0, 0}, + {0x7668, 0x0f, 0, 0}, + {0x7669, 0x00, 0, 0}, + {0x766a, 0x00, 0, 0}, + {0x766b, 0x00, 0, 0}, + {0x766c, 0x00, 0, 0}, + {0x766d, 0x01, 0, 0}, + {0x766e, 0x04, 0, 0}, + {0x766f, 0xe5, 0, 0}, + {0x7670, 0x04, 0, 0}, + {0x7671, 0xe4, 0, 0}, + {0x7672, 0x0f, 0, 0}, + {0x7673, 0x00, 0, 0}, + {0x7674, 0x00, 0, 0}, + {0x7675, 0x02, 0, 0}, + {0x7676, 0x04, 0, 0}, + {0x7677, 0xe4, 0, 0}, + {0x7678, 0x00, 0, 0}, + {0x7679, 0x02, 0, 0}, + {0x767a, 0x04, 0, 0}, + {0x767b, 0xc4, 0, 0}, + {0x767c, 0x00, 0, 0}, + {0x767d, 0x02, 0, 0}, + {0x767e, 0x04, 0, 0}, + {0x767f, 0xc4, 0, 0}, + {0x7680, 0x05, 0, 0}, + {0x7681, 0x83, 0, 0}, + {0x7682, 0x0f, 0, 0}, + {0x7683, 0x00, 0, 0}, + {0x7684, 0x00, 0, 0}, + {0x7685, 0x02, 0, 0}, + {0x7686, 0x04, 0, 0}, + {0x7687, 0xe4, 0, 0}, + {0x7688, 0x00, 0, 0}, + {0x7689, 0x02, 0, 0}, + {0x768a, 0x04, 0, 0}, + {0x768b, 0xc4, 0, 0}, + {0x768c, 0x00, 0, 0}, + {0x768d, 0x02, 0, 0}, + {0x768e, 0x04, 0, 0}, + {0x768f, 0xc4, 0, 0}, + {0x7690, 0x05, 0, 0}, + {0x7691, 0x83, 0, 0}, + {0x7692, 0x03, 0, 0}, + {0x7693, 0x0b, 0, 0}, + {0x7694, 0x05, 0, 0}, + {0x7695, 0x83, 0, 0}, + {0x7696, 0x00, 0, 0}, + {0x7697, 0x07, 0, 0}, + {0x7698, 0x05, 0, 0}, + {0x7699, 0x03, 0, 0}, + {0x769a, 0x00, 0, 0}, + {0x769b, 0x05, 0, 0}, + {0x769c, 0x05, 0, 0}, + {0x769d, 0x32, 0, 0}, + {0x769e, 0x05, 0, 0}, + {0x769f, 0x30, 0, 0}, + {0x76a0, 0x00, 0, 0}, + {0x76a1, 0x02, 0, 0}, + {0x76a2, 0x05, 0, 0}, + {0x76a3, 0x78, 0, 0}, + {0x76a4, 0x00, 0, 0}, + {0x76a5, 0x01, 0, 0}, + {0x76a6, 0x05, 0, 0}, + {0x76a7, 0x7c, 0, 0}, + {0x76a8, 0x03, 0, 0}, + {0x76a9, 0x9a, 0, 0}, + {0x76aa, 0x05, 0, 0}, + {0x76ab, 0x83, 0, 0}, + {0x76ac, 0x00, 0, 0}, + {0x76ad, 0x04, 0, 0}, + {0x76ae, 0x05, 0, 0}, + {0x76af, 0x03, 0, 0}, + {0x76b0, 0x00, 0, 0}, + {0x76b1, 0x03, 0, 0}, + {0x76b2, 0x05, 0, 0}, + {0x76b3, 0x32, 0, 0}, + {0x76b4, 0x05, 0, 0}, + {0x76b5, 0x30, 0, 0}, + {0x76b6, 0x00, 0, 0}, + {0x76b7, 0x02, 0, 0}, + {0x76b8, 0x05, 0, 0}, + {0x76b9, 0x78, 0, 0}, + {0x76ba, 0x00, 0, 0}, + {0x76bb, 0x01, 0, 0}, + {0x76bc, 0x05, 0, 0}, + {0x76bd, 0x7c, 0, 0}, + {0x76be, 0x03, 0, 0}, + {0x76bf, 0x99, 0, 0}, + {0x76c0, 0x05, 0, 0}, + {0x76c1, 0x83, 0, 0}, + {0x76c2, 0x00, 0, 0}, + {0x76c3, 0x03, 0, 0}, + {0x76c4, 0x05, 0, 0}, + {0x76c5, 0x03, 0, 0}, + {0x76c6, 0x00, 0, 0}, + {0x76c7, 0x01, 0, 0}, + {0x76c8, 0x05, 0, 0}, + {0x76c9, 0x32, 0, 0}, + {0x76ca, 0x05, 0, 0}, + {0x76cb, 0x30, 0, 0}, + {0x76cc, 0x00, 0, 0}, + {0x76cd, 0x02, 0, 0}, + {0x76ce, 0x05, 0, 0}, + {0x76cf, 0x78, 0, 0}, + {0x76d0, 0x00, 0, 0}, + {0x76d1, 0x01, 0, 0}, + {0x76d2, 0x05, 0, 0}, + {0x76d3, 0x7c, 0, 0}, + {0x76d4, 0x03, 0, 0}, + {0x76d5, 0x98, 0, 0}, + {0x76d6, 0x05, 0, 0}, + {0x76d7, 0x83, 0, 0}, + {0x76d8, 0x00, 0, 0}, + {0x76d9, 0x00, 0, 0}, + {0x76da, 0x05, 0, 0}, + {0x76db, 0x03, 0, 0}, + {0x76dc, 0x00, 0, 0}, + {0x76dd, 0x01, 0, 0}, + {0x76de, 0x05, 0, 0}, + {0x76df, 0x32, 0, 0}, + {0x76e0, 0x05, 0, 0}, + {0x76e1, 0x30, 0, 0}, + {0x76e2, 0x00, 0, 0}, + {0x76e3, 0x02, 0, 0}, + {0x76e4, 0x05, 0, 0}, + {0x76e5, 0x78, 0, 0}, + {0x76e6, 0x00, 0, 0}, + {0x76e7, 0x01, 0, 0}, + {0x76e8, 0x05, 0, 0}, + {0x76e9, 0x7c, 0, 0}, + {0x76ea, 0x03, 0, 0}, + {0x76eb, 0x97, 0, 0}, + {0x76ec, 0x05, 0, 0}, + {0x76ed, 0x83, 0, 0}, + {0x76ee, 0x00, 0, 0}, + {0x76ef, 0x00, 0, 0}, + {0x76f0, 0x05, 0, 0}, + {0x76f1, 0x03, 0, 0}, + {0x76f2, 0x05, 0, 0}, + {0x76f3, 0x32, 0, 0}, + {0x76f4, 0x05, 0, 0}, + {0x76f5, 0x30, 0, 0}, + {0x76f6, 0x00, 0, 0}, + {0x76f7, 0x02, 0, 0}, + {0x76f8, 0x05, 0, 0}, + {0x76f9, 0x78, 0, 0}, + {0x76fa, 0x00, 0, 0}, + {0x76fb, 0x01, 0, 0}, + {0x76fc, 0x05, 0, 0}, + {0x76fd, 0x7c, 0, 0}, + {0x76fe, 0x03, 0, 0}, + {0x76ff, 0x96, 0, 0}, + {0x7700, 0x05, 0, 0}, + {0x7701, 0x83, 0, 0}, + {0x7702, 0x05, 0, 0}, + {0x7703, 0x03, 0, 0}, + {0x7704, 0x05, 0, 0}, + {0x7705, 0x32, 0, 0}, + {0x7706, 0x05, 0, 0}, + {0x7707, 0x30, 0, 0}, + {0x7708, 0x00, 0, 0}, + {0x7709, 0x02, 0, 0}, + {0x770a, 0x05, 0, 0}, + {0x770b, 0x78, 0, 0}, + {0x770c, 0x00, 0, 0}, + {0x770d, 0x01, 0, 0}, + {0x770e, 0x05, 0, 0}, + {0x770f, 0x7c, 0, 0}, + {0x7710, 0x03, 0, 0}, + {0x7711, 0x95, 0, 0}, + {0x7712, 0x05, 0, 0}, + {0x7713, 0x83, 0, 0}, + {0x7714, 0x05, 0, 0}, + {0x7715, 0x03, 0, 0}, + {0x7716, 0x05, 0, 0}, + {0x7717, 0x32, 0, 0}, + {0x7718, 0x05, 0, 0}, + {0x7719, 0x30, 0, 0}, + {0x771a, 0x00, 0, 0}, + {0x771b, 0x02, 0, 0}, + {0x771c, 0x05, 0, 0}, + {0x771d, 0x78, 0, 0}, + {0x771e, 0x00, 0, 0}, + {0x771f, 0x01, 0, 0}, + {0x7720, 0x05, 0, 0}, + {0x7721, 0x7c, 0, 0}, + {0x7722, 0x03, 0, 0}, + {0x7723, 0x94, 0, 0}, + {0x7724, 0x05, 0, 0}, + {0x7725, 0x83, 0, 0}, + {0x7726, 0x00, 0, 0}, + {0x7727, 0x01, 0, 0}, + {0x7728, 0x05, 0, 0}, + {0x7729, 0x03, 0, 0}, + {0x772a, 0x00, 0, 0}, + {0x772b, 0x01, 0, 0}, + {0x772c, 0x05, 0, 0}, + {0x772d, 0x32, 0, 0}, + {0x772e, 0x05, 0, 0}, + {0x772f, 0x30, 0, 0}, + {0x7730, 0x00, 0, 0}, + {0x7731, 0x02, 0, 0}, + {0x7732, 0x05, 0, 0}, + {0x7733, 0x78, 0, 0}, + {0x7734, 0x00, 0, 0}, + {0x7735, 0x01, 0, 0}, + {0x7736, 0x05, 0, 0}, + {0x7737, 0x7c, 0, 0}, + {0x7738, 0x03, 0, 0}, + {0x7739, 0x93, 0, 0}, + {0x773a, 0x05, 0, 0}, + {0x773b, 0x83, 0, 0}, + {0x773c, 0x00, 0, 0}, + {0x773d, 0x00, 0, 0}, + {0x773e, 0x05, 0, 0}, + {0x773f, 0x03, 0, 0}, + {0x7740, 0x00, 0, 0}, + {0x7741, 0x00, 0, 0}, + {0x7742, 0x05, 0, 0}, + {0x7743, 0x32, 0, 0}, + {0x7744, 0x05, 0, 0}, + {0x7745, 0x30, 0, 0}, + {0x7746, 0x00, 0, 0}, + {0x7747, 0x02, 0, 0}, + {0x7748, 0x05, 0, 0}, + {0x7749, 0x78, 0, 0}, + {0x774a, 0x00, 0, 0}, + {0x774b, 0x01, 0, 0}, + {0x774c, 0x05, 0, 0}, + {0x774d, 0x7c, 0, 0}, + {0x774e, 0x03, 0, 0}, + {0x774f, 0x92, 0, 0}, + {0x7750, 0x05, 0, 0}, + {0x7751, 0x83, 0, 0}, + {0x7752, 0x05, 0, 0}, + {0x7753, 0x03, 0, 0}, + {0x7754, 0x00, 0, 0}, + {0x7755, 0x00, 0, 0}, + {0x7756, 0x05, 0, 0}, + {0x7757, 0x32, 0, 0}, + {0x7758, 0x05, 0, 0}, + {0x7759, 0x30, 0, 0}, + {0x775a, 0x00, 0, 0}, + {0x775b, 0x02, 0, 0}, + {0x775c, 0x05, 0, 0}, + {0x775d, 0x78, 0, 0}, + {0x775e, 0x00, 0, 0}, + {0x775f, 0x01, 0, 0}, + {0x7760, 0x05, 0, 0}, + {0x7761, 0x7c, 0, 0}, + {0x7762, 0x03, 0, 0}, + {0x7763, 0x91, 0, 0}, + {0x7764, 0x05, 0, 0}, + {0x7765, 0x83, 0, 0}, + {0x7766, 0x05, 0, 0}, + {0x7767, 0x03, 0, 0}, + {0x7768, 0x05, 0, 0}, + {0x7769, 0x32, 0, 0}, + {0x776a, 0x05, 0, 0}, + {0x776b, 0x30, 0, 0}, + {0x776c, 0x00, 0, 0}, + {0x776d, 0x02, 0, 0}, + {0x776e, 0x05, 0, 0}, + {0x776f, 0x78, 0, 0}, + {0x7770, 0x00, 0, 0}, + {0x7771, 0x01, 0, 0}, + {0x7772, 0x05, 0, 0}, + {0x7773, 0x7c, 0, 0}, + {0x7774, 0x03, 0, 0}, + {0x7775, 0x90, 0, 0}, + {0x7776, 0x05, 0, 0}, + {0x7777, 0x83, 0, 0}, + {0x7778, 0x05, 0, 0}, + {0x7779, 0x03, 0, 0}, + {0x777a, 0x05, 0, 0}, + {0x777b, 0x32, 0, 0}, + {0x777c, 0x05, 0, 0}, + {0x777d, 0x30, 0, 0}, + {0x777e, 0x00, 0, 0}, + {0x777f, 0x02, 0, 0}, + {0x7780, 0x05, 0, 0}, + {0x7781, 0x78, 0, 0}, + {0x7782, 0x00, 0, 0}, + {0x7783, 0x01, 0, 0}, + {0x7784, 0x05, 0, 0}, + {0x7785, 0x7c, 0, 0}, + {0x7786, 0x02, 0, 0}, + {0x7787, 0x90, 0, 0}, + {0x7788, 0x05, 0, 0}, + {0x7789, 0x03, 0, 0}, + {0x778a, 0x07, 0, 0}, + {0x778b, 0x00, 0, 0}, + {0x778c, 0x0f, 0, 0}, + {0x778d, 0x00, 0, 0}, + {0x778e, 0x08, 0, 0}, + {0x778f, 0x30, 0, 0}, + {0x7790, 0x08, 0, 0}, + {0x7791, 0xee, 0, 0}, + {0x7792, 0x0f, 0, 0}, + {0x7793, 0x00, 0, 0}, + {0x7794, 0x05, 0, 0}, + {0x7795, 0x33, 0, 0}, + {0x7796, 0x04, 0, 0}, + {0x7797, 0xe5, 0, 0}, + {0x7798, 0x06, 0, 0}, + {0x7799, 0x52, 0, 0}, + {0x779a, 0x04, 0, 0}, + {0x779b, 0xe4, 0, 0}, + {0x779c, 0x00, 0, 0}, + {0x779d, 0x00, 0, 0}, + {0x779e, 0x06, 0, 0}, + {0x779f, 0x5e, 0, 0}, + {0x77a0, 0x00, 0, 0}, + {0x77a1, 0x0f, 0, 0}, + {0x77a2, 0x06, 0, 0}, + {0x77a3, 0x1e, 0, 0}, + {0x77a4, 0x00, 0, 0}, + {0x77a5, 0x02, 0, 0}, + {0x77a6, 0x06, 0, 0}, + {0x77a7, 0xa2, 0, 0}, + {0x77a8, 0x00, 0, 0}, + {0x77a9, 0x01, 0, 0}, + {0x77aa, 0x06, 0, 0}, + {0x77ab, 0xae, 0, 0}, + {0x77ac, 0x00, 0, 0}, + {0x77ad, 0x03, 0, 0}, + {0x77ae, 0x05, 0, 0}, + {0x77af, 0x30, 0, 0}, + {0x77b0, 0x09, 0, 0}, + {0x77b1, 0x19, 0, 0}, + {0x77b2, 0x0f, 0, 0}, + {0x77b3, 0x00, 0, 0}, + {0x77b4, 0x05, 0, 0}, + {0x77b5, 0x33, 0, 0}, + {0x77b6, 0x04, 0, 0}, + {0x77b7, 0xe5, 0, 0}, + {0x77b8, 0x06, 0, 0}, + {0x77b9, 0x52, 0, 0}, + {0x77ba, 0x04, 0, 0}, + {0x77bb, 0xe4, 0, 0}, + {0x77bc, 0x00, 0, 0}, + {0x77bd, 0x00, 0, 0}, + {0x77be, 0x06, 0, 0}, + {0x77bf, 0x5e, 0, 0}, + {0x77c0, 0x00, 0, 0}, + {0x77c1, 0x0f, 0, 0}, + {0x77c2, 0x06, 0, 0}, + {0x77c3, 0x1e, 0, 0}, + {0x77c4, 0x00, 0, 0}, + {0x77c5, 0x02, 0, 0}, + {0x77c6, 0x06, 0, 0}, + {0x77c7, 0xa2, 0, 0}, + {0x77c8, 0x00, 0, 0}, + {0x77c9, 0x01, 0, 0}, + {0x77ca, 0x06, 0, 0}, + {0x77cb, 0xae, 0, 0}, + {0x77cc, 0x00, 0, 0}, + {0x77cd, 0x03, 0, 0}, + {0x77ce, 0x05, 0, 0}, + {0x77cf, 0x30, 0, 0}, + {0x77d0, 0x0f, 0, 0}, + {0x77d1, 0x00, 0, 0}, + {0x77d2, 0x00, 0, 0}, + {0x77d3, 0x00, 0, 0}, + {0x77d4, 0x00, 0, 0}, + {0x77d5, 0x02, 0, 0}, + {0x77d6, 0x04, 0, 0}, + {0x77d7, 0xe5, 0, 0}, + {0x77d8, 0x04, 0, 0}, + {0x77d9, 0xe4, 0, 0}, + {0x77da, 0x05, 0, 0}, + {0x77db, 0x33, 0, 0}, + {0x77dc, 0x07, 0, 0}, + {0x77dd, 0x10, 0, 0}, + {0x77de, 0x00, 0, 0}, + {0x77df, 0x00, 0, 0}, + {0x77e0, 0x01, 0, 0}, + {0x77e1, 0xbb, 0, 0}, + {0x77e2, 0x00, 0, 0}, + {0x77e3, 0x00, 0, 0}, + {0x77e4, 0x01, 0, 0}, + {0x77e5, 0xaa, 0, 0}, + {0x77e6, 0x00, 0, 0}, + {0x77e7, 0x00, 0, 0}, + {0x77e8, 0x01, 0, 0}, + {0x77e9, 0x99, 0, 0}, + {0x77ea, 0x00, 0, 0}, + {0x77eb, 0x00, 0, 0}, + {0x77ec, 0x01, 0, 0}, + {0x77ed, 0x88, 0, 0}, + {0x77ee, 0x00, 0, 0}, + {0x77ef, 0x00, 0, 0}, + {0x77f0, 0x01, 0, 0}, + {0x77f1, 0x77, 0, 0}, + {0x77f2, 0x00, 0, 0}, + {0x77f3, 0x00, 0, 0}, + {0x77f4, 0x01, 0, 0}, + {0x77f5, 0x66, 0, 0}, + {0x77f6, 0x00, 0, 0}, + {0x77f7, 0x00, 0, 0}, + {0x77f8, 0x01, 0, 0}, + {0x77f9, 0x55, 0, 0}, + {0x77fa, 0x00, 0, 0}, + {0x77fb, 0x00, 0, 0}, + {0x77fc, 0x01, 0, 0}, + {0x77fd, 0x44, 0, 0}, + {0x77fe, 0x00, 0, 0}, + {0x77ff, 0x00, 0, 0}, + {0x7800, 0x01, 0, 0}, + {0x7801, 0x33, 0, 0}, + {0x7802, 0x00, 0, 0}, + {0x7803, 0x00, 0, 0}, + {0x7804, 0x01, 0, 0}, + {0x7805, 0x22, 0, 0}, + {0x7806, 0x00, 0, 0}, + {0x7807, 0x00, 0, 0}, + {0x7808, 0x01, 0, 0}, + {0x7809, 0x11, 0, 0}, + {0x780a, 0x00, 0, 0}, + {0x780b, 0x00, 0, 0}, + {0x780c, 0x01, 0, 0}, + {0x780d, 0x00, 0, 0}, + {0x780e, 0x01, 0, 0}, + {0x780f, 0xff, 0, 0}, + {0x7810, 0x07, 0, 0}, + {0x7811, 0x00, 0, 0}, + {0x7812, 0x02, 0, 0}, + {0x7813, 0xa0, 0, 0}, + {0x7814, 0x0f, 0, 0}, + {0x7815, 0x00, 0, 0}, + {0x7816, 0x08, 0, 0}, + {0x7817, 0x35, 0, 0}, + {0x7818, 0x06, 0, 0}, + {0x7819, 0x52, 0, 0}, + {0x781a, 0x04, 0, 0}, + {0x781b, 0xe4, 0, 0}, + {0x781c, 0x00, 0, 0}, + {0x781d, 0x00, 0, 0}, + {0x781e, 0x06, 0, 0}, + {0x781f, 0x5e, 0, 0}, + {0x7820, 0x05, 0, 0}, + {0x7821, 0x33, 0, 0}, + {0x7822, 0x09, 0, 0}, + {0x7823, 0x19, 0, 0}, + {0x7824, 0x06, 0, 0}, + {0x7825, 0x1e, 0, 0}, + {0x7826, 0x05, 0, 0}, + {0x7827, 0x33, 0, 0}, + {0x7828, 0x00, 0, 0}, + {0x7829, 0x01, 0, 0}, + {0x782a, 0x06, 0, 0}, + {0x782b, 0x24, 0, 0}, + {0x782c, 0x06, 0, 0}, + {0x782d, 0x20, 0, 0}, + {0x782e, 0x0f, 0, 0}, + {0x782f, 0x00, 0, 0}, + {0x7830, 0x08, 0, 0}, + {0x7831, 0x35, 0, 0}, + {0x7832, 0x07, 0, 0}, + {0x7833, 0x10, 0, 0}, + {0x7834, 0x00, 0, 0}, + {0x7835, 0x00, 0, 0}, + {0x7836, 0x01, 0, 0}, + {0x7837, 0xbb, 0, 0}, + {0x7838, 0x00, 0, 0}, + {0x7839, 0x00, 0, 0}, + {0x783a, 0x01, 0, 0}, + {0x783b, 0xaa, 0, 0}, + {0x783c, 0x00, 0, 0}, + {0x783d, 0x00, 0, 0}, + {0x783e, 0x01, 0, 0}, + {0x783f, 0x99, 0, 0}, + {0x7840, 0x00, 0, 0}, + {0x7841, 0x00, 0, 0}, + {0x7842, 0x01, 0, 0}, + {0x7843, 0x88, 0, 0}, + {0x7844, 0x00, 0, 0}, + {0x7845, 0x00, 0, 0}, + {0x7846, 0x01, 0, 0}, + {0x7847, 0x77, 0, 0}, + {0x7848, 0x00, 0, 0}, + {0x7849, 0x00, 0, 0}, + {0x784a, 0x01, 0, 0}, + {0x784b, 0x66, 0, 0}, + {0x784c, 0x00, 0, 0}, + {0x784d, 0x00, 0, 0}, + {0x784e, 0x01, 0, 0}, + {0x784f, 0x55, 0, 0}, + {0x7850, 0x00, 0, 0}, + {0x7851, 0x00, 0, 0}, + {0x7852, 0x01, 0, 0}, + {0x7853, 0x44, 0, 0}, + {0x7854, 0x00, 0, 0}, + {0x7855, 0x00, 0, 0}, + {0x7856, 0x01, 0, 0}, + {0x7857, 0x33, 0, 0}, + {0x7858, 0x00, 0, 0}, + {0x7859, 0x00, 0, 0}, + {0x785a, 0x01, 0, 0}, + {0x785b, 0x22, 0, 0}, + {0x785c, 0x00, 0, 0}, + {0x785d, 0x00, 0, 0}, + {0x785e, 0x01, 0, 0}, + {0x785f, 0x11, 0, 0}, + {0x7860, 0x00, 0, 0}, + {0x7861, 0x00, 0, 0}, + {0x7862, 0x01, 0, 0}, + {0x7863, 0x00, 0, 0}, + {0x7864, 0x07, 0, 0}, + {0x7865, 0x00, 0, 0}, + {0x7866, 0x01, 0, 0}, + {0x7867, 0xff, 0, 0}, + {0x7868, 0x02, 0, 0}, + {0x7869, 0xa0, 0, 0}, + {0x786a, 0x0f, 0, 0}, + {0x786b, 0x00, 0, 0}, + {0x786c, 0x08, 0, 0}, + {0x786d, 0x3a, 0, 0}, + {0x786e, 0x08, 0, 0}, + {0x786f, 0x6a, 0, 0}, + {0x7870, 0x0f, 0, 0}, + {0x7871, 0x00, 0, 0}, + {0x7872, 0x04, 0, 0}, + {0x7873, 0xc0, 0, 0}, + {0x7874, 0x09, 0, 0}, + {0x7875, 0x19, 0, 0}, + {0x7876, 0x04, 0, 0}, + {0x7877, 0x99, 0, 0}, + {0x7878, 0x07, 0, 0}, + {0x7879, 0x14, 0, 0}, + {0x787a, 0x00, 0, 0}, + {0x787b, 0x01, 0, 0}, + {0x787c, 0x04, 0, 0}, + {0x787d, 0xa4, 0, 0}, + {0x787e, 0x00, 0, 0}, + {0x787f, 0x07, 0, 0}, + {0x7880, 0x04, 0, 0}, + {0x7881, 0xa6, 0, 0}, + {0x7882, 0x00, 0, 0}, + {0x7883, 0x00, 0, 0}, + {0x7884, 0x04, 0, 0}, + {0x7885, 0xa0, 0, 0}, + {0x7886, 0x04, 0, 0}, + {0x7887, 0x80, 0, 0}, + {0x7888, 0x04, 0, 0}, + {0x7889, 0x00, 0, 0}, + {0x788a, 0x05, 0, 0}, + {0x788b, 0x03, 0, 0}, + {0x788c, 0x06, 0, 0}, + {0x788d, 0x00, 0, 0}, + {0x788e, 0x0f, 0, 0}, + {0x788f, 0x00, 0, 0}, + {0x7890, 0x0f, 0, 0}, + {0x7891, 0x00, 0, 0}, + {0x7892, 0x0f, 0, 0}, + {0x7893, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x05, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x04, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x80, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x38, 0, 0}, + {0x30b0, 0x0d, 0, 0}, + {0x30b1, 0xde, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x66, 0, 0}, + {0x30b6, 0x01, 0, 0}, + {0x30b7, 0x22, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x20, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x0a, 0, 0}, + {0x3195, 0x2e, 0, 0}, + {0x30bb, 0x14, 0, 0}, + {0x315a, 0x02, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x80, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x80, 0, 0}, + {0x3250, 0xf7, 0, 0}, + {0x3012, 0x00, 0, 0}, + + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x08, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x08, 0, 0}, + + {0x30c0, 0x08, 0, 0}, + {0x3252, 0x20, 0, 0}, +}; + +#endif diff --git a/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr_low_freq.h b/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr_low_freq.h new file mode 100755 index 0000000..3ab980b --- /dev/null +++ b/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr_low_freq.h @@ -0,0 +1,1885 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OV2775_REGS_1080P_HDR_LOW_FREQ_H_ +#define _VVCAM_OV2775_REGS_1080P_HDR_LOW_FREQ_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t ov2775_init_setting_1080p_hdr_low_freq[] = { + {0x3000, 0x02, 0, 0}, + {0x3001, 0x28, 0, 0}, + {0x3002, 0x03, 0, 0}, + {0x3003, 0x01, 0, 0}, + {0x3004, 0x04, 0, 0},//0x02 + {0x3005, 0x30, 0, 0},//800Mbps //{0x3005, 0x26, 0, 0},//960Mbps + {0x3006, 0x00, 0, 0}, + {0x3007, 0x07, 0, 0},//100MHz + {0x3008, 0x01, 0, 0}, + {0x3009, 0x00, 0, 0}, + {0x300c, 0x6c, 0, 0}, + {0x300e, 0x80, 0, 0}, + {0x300f, 0x00, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3013, 0x00, 0, 0}, + {0x3014, 0xc4, 0, 0}, + {0x3015, 0x00, 0, 0}, + {0x3017, 0x00, 0, 0}, + {0x3018, 0x00, 0, 0}, + {0x3019, 0x00, 0, 0}, + {0x301a, 0x00, 0, 0}, + {0x301b, 0x0e, 0, 0}, + {0x301e, 0x17, 0, 0}, + {0x301f, 0xe1, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x3031, 0x62, 0, 0}, + {0x3032, 0xf0, 0, 0}, + {0x3033, 0x30, 0, 0}, + {0x3034, 0x3f, 0, 0}, + {0x3035, 0x5f, 0, 0}, + {0x3036, 0x02, 0, 0}, + {0x3037, 0x9f, 0, 0}, + {0x3038, 0x04, 0, 0}, + {0x3039, 0xb7, 0, 0}, + {0x303a, 0x04, 0, 0}, + {0x303b, 0x07, 0, 0}, + {0x303c, 0xf0, 0, 0}, + {0x303d, 0x00, 0, 0}, + {0x303e, 0x0b, 0, 0}, + {0x303f, 0xe3, 0, 0}, + {0x3040, 0xf3, 0, 0}, + {0x3041, 0x29, 0, 0}, + {0x3042, 0xf6, 0, 0}, + {0x3043, 0x65, 0, 0}, + {0x3044, 0x06, 0, 0}, + {0x3045, 0x0f, 0, 0}, + {0x3046, 0x59, 0, 0}, + {0x3047, 0x07, 0, 0}, + {0x3048, 0x82, 0, 0}, + {0x3049, 0xcf, 0, 0}, + {0x304a, 0x12, 0, 0}, + {0x304b, 0x40, 0, 0}, + {0x304c, 0x33, 0, 0}, + {0x304d, 0xa4, 0, 0}, + {0x304e, 0x0b, 0, 0}, + {0x304f, 0x3d, 0, 0}, + {0x3050, 0x10, 0, 0}, + {0x3060, 0x00, 0, 0}, + {0x3061, 0x64, 0, 0}, + {0x3062, 0x00, 0, 0}, + {0x3063, 0xe4, 0, 0}, + {0x3066, 0x80, 0, 0}, + {0x3080, 0x00, 0, 0}, + {0x3081, 0x00, 0, 0}, + {0x3082, 0x01, 0, 0}, + {0x3083, 0xe3, 0, 0}, + {0x3084, 0x06, 0, 0}, + {0x3085, 0x00, 0, 0}, + {0x3086, 0x10, 0, 0}, + {0x3087, 0x10, 0, 0}, + {0x3089, 0x00, 0, 0}, + {0x308a, 0x01, 0, 0}, + {0x3093, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x00, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x00, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x90, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x48, 0, 0}, + {0x30b0, 0x08, 0, 0}, + {0x30b1, 0xae, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x65, 0, 0}, + {0x30b4, 0x00, 0, 0}, + {0x30b5, 0x00, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x10, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x02, 0, 0}, + {0x30ba, 0x10, 0, 0}, + {0x30bb, 0x00, 0, 0}, + {0x30bc, 0x00, 0, 0}, + {0x30bd, 0x03, 0, 0}, + {0x30be, 0x5c, 0, 0}, + {0x30bf, 0x00, 0, 0}, + {0x30c0, 0x05, 0, 0}, + {0x30c1, 0x00, 0, 0}, + {0x30c2, 0x20, 0, 0}, + {0x30c3, 0x00, 0, 0}, + {0x30c4, 0x4a, 0, 0}, + {0x30c5, 0x00, 0, 0}, + {0x30c7, 0x00, 0, 0}, + {0x30c8, 0x00, 0, 0}, + {0x30d1, 0x00, 0, 0}, + {0x30d2, 0x00, 0, 0}, + {0x30d3, 0x80, 0, 0}, + {0x30d4, 0x00, 0, 0}, + {0x30d9, 0x09, 0, 0}, + {0x30da, 0x64, 0, 0}, + {0x30dd, 0x00, 0, 0}, + {0x30de, 0x16, 0, 0}, + {0x30df, 0x00, 0, 0}, + {0x30e0, 0x17, 0, 0}, + {0x30e1, 0x00, 0, 0}, + {0x30e2, 0x18, 0, 0}, + {0x30e3, 0x10, 0, 0}, + {0x30e4, 0x04, 0, 0}, + {0x30e5, 0x00, 0, 0}, + {0x30e6, 0x00, 0, 0}, + {0x30e7, 0x00, 0, 0}, + {0x30e8, 0x00, 0, 0}, + {0x30e9, 0x00, 0, 0}, + {0x30ea, 0x00, 0, 0}, + {0x30eb, 0x00, 0, 0}, + {0x30ec, 0x00, 0, 0}, + {0x30ed, 0x00, 0, 0}, + {0x3101, 0x00, 0, 0}, + {0x3102, 0x00, 0, 0}, + {0x3103, 0x00, 0, 0}, + {0x3104, 0x00, 0, 0}, + {0x3105, 0x8c, 0, 0}, + {0x3106, 0x87, 0, 0}, + {0x3107, 0xc0, 0, 0}, + {0x3108, 0x9d, 0, 0}, + {0x3109, 0x8d, 0, 0}, + {0x310a, 0x8d, 0, 0}, + {0x310b, 0x6a, 0, 0}, + {0x310c, 0x3a, 0, 0}, + {0x310d, 0x5a, 0, 0}, + {0x310e, 0x00, 0, 0}, + {0x3120, 0x00, 0, 0}, + {0x3121, 0x00, 0, 0}, + {0x3122, 0x00, 0, 0}, + {0x3123, 0x00, 0, 0}, + {0x3124, 0x00, 0, 0}, + {0x3125, 0x70, 0, 0}, + {0x3126, 0x1f, 0, 0}, + {0x3127, 0x0f, 0, 0}, + {0x3128, 0x00, 0, 0}, + {0x3129, 0x3a, 0, 0}, + {0x312a, 0x02, 0, 0}, + {0x312b, 0x0f, 0, 0}, + {0x312c, 0x00, 0, 0}, + {0x312d, 0x0f, 0, 0}, + {0x312e, 0x1d, 0, 0}, + {0x312f, 0x00, 0, 0}, + {0x3130, 0x00, 0, 0}, + {0x3131, 0x00, 0, 0}, + {0x3132, 0x00, 0, 0}, + {0x3140, 0x0a, 0, 0}, + {0x3141, 0x03, 0, 0}, + {0x3142, 0x00, 0, 0}, + {0x3143, 0x00, 0, 0}, + {0x3144, 0x00, 0, 0}, + {0x3145, 0x00, 0, 0}, + {0x3146, 0x00, 0, 0}, + {0x3147, 0x00, 0, 0}, + {0x3148, 0x00, 0, 0}, + {0x3149, 0x00, 0, 0}, + {0x314a, 0x00, 0, 0}, + {0x314b, 0x00, 0, 0}, + {0x314c, 0x00, 0, 0}, + {0x314d, 0x00, 0, 0}, + {0x314e, 0x1c, 0, 0}, + {0x314f, 0xff, 0, 0}, + {0x3150, 0xff, 0, 0}, + {0x3151, 0xff, 0, 0}, + {0x3152, 0x10, 0, 0}, + {0x3153, 0x10, 0, 0}, + {0x3154, 0x10, 0, 0}, + {0x3155, 0x00, 0, 0}, + {0x3156, 0x03, 0, 0}, + {0x3157, 0x00, 0, 0}, + {0x3158, 0x0f, 0, 0}, + {0x3159, 0xff, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x00, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x00, 0, 0}, + {0x3160, 0x00, 0, 0}, + {0x3161, 0x40, 0, 0}, + {0x3162, 0x00, 0, 0}, + {0x3163, 0x40, 0, 0}, + {0x3164, 0x00, 0, 0}, + {0x3165, 0x40, 0, 0}, + {0x3190, 0x05, 0, 0}, + {0x3191, 0x99, 0, 0}, + {0x3193, 0x08, 0, 0}, + {0x3194, 0x13, 0, 0}, + {0x3195, 0x33, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x10, 0, 0}, + {0x3198, 0x00, 0, 0}, + {0x3199, 0x3f, 0, 0}, + {0x319a, 0x40, 0, 0}, + {0x319b, 0x7f, 0, 0}, + {0x319c, 0x80, 0, 0}, + {0x319d, 0xbf, 0, 0}, + {0x319e, 0xc0, 0, 0}, + {0x319f, 0xff, 0, 0}, + {0x31a0, 0x24, 0, 0}, + {0x31a1, 0x55, 0, 0}, + {0x31a2, 0x00, 0, 0}, + {0x31a3, 0x00, 0, 0}, + {0x31a6, 0x00, 0, 0}, + {0x31a7, 0x00, 0, 0}, + {0x31b0, 0x00, 0, 0}, + {0x31b1, 0x00, 0, 0}, + {0x31b2, 0x02, 0, 0}, + {0x31b3, 0x00, 0, 0}, + {0x31b4, 0x00, 0, 0}, + {0x31b5, 0x01, 0, 0}, + {0x31b6, 0x00, 0, 0}, + {0x31b7, 0x00, 0, 0}, + {0x31b8, 0x00, 0, 0}, + {0x31b9, 0x00, 0, 0}, + {0x31ba, 0x00, 0, 0}, + {0x31d0, 0x3c, 0, 0}, + {0x31d1, 0x34, 0, 0}, + {0x31d2, 0x3c, 0, 0}, + {0x31d3, 0x00, 0, 0}, + {0x31d4, 0x2d, 0, 0}, + {0x31d5, 0x00, 0, 0}, + {0x31d6, 0x01, 0, 0}, + {0x31d7, 0x06, 0, 0}, + {0x31d8, 0x00, 0, 0}, + {0x31d9, 0x64, 0, 0}, + {0x31da, 0x00, 0, 0}, + {0x31db, 0x30, 0, 0}, + {0x31dc, 0x04, 0, 0}, + {0x31dd, 0x69, 0, 0}, + {0x31de, 0x0a, 0, 0}, + {0x31df, 0x3c, 0, 0}, + {0x31e0, 0x04, 0, 0}, + {0x31e1, 0x32, 0, 0}, + {0x31e2, 0x00, 0, 0}, + {0x31e3, 0x00, 0, 0}, + {0x31e4, 0x08, 0, 0}, + {0x31e5, 0x80, 0, 0}, + {0x31e6, 0x00, 0, 0}, + {0x31e7, 0x2c, 0, 0}, + {0x31e8, 0x6c, 0, 0}, + {0x31e9, 0xac, 0, 0}, + {0x31ea, 0xec, 0, 0}, + {0x31eb, 0x3f, 0, 0}, + {0x31ec, 0x07, 0, 0}, + {0x31ed, 0x80, 0, 0}, + {0x31ee, 0x04, 0, 0}, + {0x31ef, 0x38, 0, 0}, + {0x31f0, 0x07, 0, 0}, + {0x31f1, 0x80, 0, 0}, + {0x31f2, 0x04, 0, 0}, + {0x31f3, 0x38, 0, 0}, + {0x31f4, 0x07, 0, 0}, + {0x31f5, 0x80, 0, 0}, + {0x31f6, 0x04, 0, 0}, + {0x31f7, 0x38, 0, 0}, + {0x31f8, 0x07, 0, 0}, + {0x31f9, 0x80, 0, 0}, + {0x31fa, 0x04, 0, 0}, + {0x31fb, 0x38, 0, 0}, + {0x31fd, 0xcb, 0, 0}, + {0x31fe, 0x0f, 0, 0}, + {0x31ff, 0x03, 0, 0}, + {0x3200, 0x00, 0, 0}, + {0x3201, 0xff, 0, 0}, + {0x3202, 0x00, 0, 0}, + {0x3203, 0xff, 0, 0}, + {0x3204, 0xff, 0, 0}, + {0x3205, 0xff, 0, 0}, + {0x3206, 0xff, 0, 0}, + {0x3207, 0xff, 0, 0}, + {0x3208, 0xff, 0, 0}, + {0x3209, 0xff, 0, 0}, + {0x320a, 0xff, 0, 0}, + {0x320b, 0x1b, 0, 0}, + {0x320c, 0x1f, 0, 0}, + {0x320d, 0x1e, 0, 0}, + {0x320e, 0x30, 0, 0}, + {0x320f, 0x2d, 0, 0}, + {0x3210, 0x2c, 0, 0}, + {0x3211, 0x2b, 0, 0}, + {0x3212, 0x2a, 0, 0}, + {0x3213, 0x24, 0, 0}, + {0x3214, 0x22, 0, 0}, + {0x3215, 0x00, 0, 0}, + {0x3216, 0x04, 0, 0}, + {0x3217, 0x2c, 0, 0}, + {0x3218, 0x6c, 0, 0}, + {0x3219, 0xac, 0, 0}, + {0x321a, 0xec, 0, 0}, + {0x321b, 0x00, 0, 0}, + {0x3230, 0x3a, 0, 0}, + {0x3231, 0x00, 0, 0}, + {0x3232, 0x80, 0, 0}, + {0x3233, 0x00, 0, 0}, + {0x3234, 0x10, 0, 0}, + {0x3235, 0xaa, 0, 0}, + {0x3236, 0x55, 0, 0}, + {0x3237, 0x99, 0, 0}, + {0x3238, 0x66, 0, 0}, + {0x3239, 0x08, 0, 0}, + {0x323a, 0x88, 0, 0}, + {0x323b, 0x00, 0, 0}, + {0x323c, 0x00, 0, 0}, + {0x323d, 0x03, 0, 0}, + {0x3250, 0x33, 0, 0}, + {0x3251, 0x00, 0, 0}, + {0x3252, 0x20, 0, 0}, + {0x3253, 0x00, 0, 0}, + {0x3254, 0x11, 0, 0}, + {0x3255, 0x01, 0, 0}, + {0x3256, 0x00, 0, 0}, + {0x3257, 0x00, 0, 0}, + {0x3258, 0x00, 0, 0}, + {0x3270, 0x01, 0, 0}, + {0x3271, 0x60, 0, 0}, + {0x3272, 0xc0, 0, 0}, + {0x3273, 0x00, 0, 0}, + {0x3274, 0x80, 0, 0}, + {0x3275, 0x40, 0, 0}, + {0x3276, 0x02, 0, 0}, + {0x3277, 0x08, 0, 0}, + {0x3278, 0x10, 0, 0}, + {0x3279, 0x04, 0, 0}, + {0x327a, 0x00, 0, 0}, + {0x327b, 0x03, 0, 0}, + {0x327c, 0x10, 0, 0}, + {0x327d, 0x60, 0, 0}, + {0x327e, 0xc0, 0, 0}, + {0x327f, 0x06, 0, 0}, + {0x3288, 0x10, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x08, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x04, 0, 0}, + {0x328d, 0x00, 0, 0}, + {0x328e, 0x02, 0, 0}, + {0x328f, 0x00, 0, 0}, + {0x3290, 0x20, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x10, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x08, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x04, 0, 0}, + {0x3297, 0x00, 0, 0}, + {0x3298, 0x40, 0, 0}, + {0x3299, 0x00, 0, 0}, + {0x329a, 0x20, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x10, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x08, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x40, 0, 0}, + {0x32a3, 0x00, 0, 0}, + {0x32a4, 0x20, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x10, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32a8, 0x00, 0, 0}, + {0x32a9, 0x00, 0, 0}, + {0x32aa, 0x00, 0, 0}, + {0x32ab, 0x00, 0, 0}, + {0x32ac, 0x00, 0, 0}, + {0x32ad, 0x00, 0, 0}, + {0x32ae, 0x00, 0, 0}, + {0x32af, 0x00, 0, 0}, + {0x32b0, 0x00, 0, 0}, + {0x32b1, 0x00, 0, 0}, + {0x32b2, 0x00, 0, 0}, + {0x32b3, 0x00, 0, 0}, + {0x32b4, 0x00, 0, 0}, + {0x32b5, 0x00, 0, 0}, + {0x32b6, 0x00, 0, 0}, + {0x32b7, 0x00, 0, 0}, + {0x32b8, 0x00, 0, 0}, + {0x32b9, 0x00, 0, 0}, + {0x32ba, 0x00, 0, 0}, + {0x32bb, 0x00, 0, 0}, + {0x32bc, 0x00, 0, 0}, + {0x32bd, 0x00, 0, 0}, + {0x32be, 0x00, 0, 0}, + {0x32bf, 0x00, 0, 0}, + {0x32c0, 0x00, 0, 0}, + {0x32c1, 0x00, 0, 0}, + {0x32c2, 0x00, 0, 0}, + {0x32c3, 0x00, 0, 0}, + {0x32c4, 0x00, 0, 0}, + {0x32c5, 0x00, 0, 0}, + {0x32c6, 0x00, 0, 0}, + {0x32c7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x32c9, 0x00, 0, 0}, + {0x3330, 0x03, 0, 0}, + {0x3331, 0xc8, 0, 0}, + {0x3332, 0x02, 0, 0}, + {0x3333, 0x24, 0, 0}, + {0x3334, 0x00, 0, 0}, + {0x3335, 0x00, 0, 0}, + {0x3336, 0x00, 0, 0}, + {0x3337, 0x00, 0, 0}, + {0x3338, 0x03, 0, 0}, + {0x3339, 0xc8, 0, 0}, + {0x333a, 0x02, 0, 0}, + {0x333b, 0x24, 0, 0}, + {0x333c, 0x00, 0, 0}, + {0x333d, 0x00, 0, 0}, + {0x333e, 0x00, 0, 0}, + {0x333f, 0x00, 0, 0}, + {0x3340, 0x03, 0, 0}, + {0x3341, 0xc8, 0, 0}, + {0x3342, 0x02, 0, 0}, + {0x3343, 0x24, 0, 0}, + {0x3344, 0x00, 0, 0}, + {0x3345, 0x00, 0, 0}, + {0x3346, 0x00, 0, 0}, + {0x3347, 0x00, 0, 0}, + {0x3348, 0x40, 0, 0}, + {0x3349, 0x00, 0, 0}, + {0x334a, 0x00, 0, 0}, + {0x334b, 0x00, 0, 0}, + {0x334c, 0x00, 0, 0}, + {0x334d, 0x00, 0, 0}, + {0x334e, 0x80, 0, 0}, + {0x3360, 0x01, 0, 0}, + {0x3361, 0x00, 0, 0}, + {0x3362, 0x01, 0, 0}, + {0x3363, 0x00, 0, 0}, + {0x3364, 0x01, 0, 0}, + {0x3365, 0x00, 0, 0}, + {0x3366, 0x01, 0, 0}, + {0x3367, 0x00, 0, 0}, + {0x3368, 0x01, 0, 0}, + {0x3369, 0x00, 0, 0}, + {0x336a, 0x01, 0, 0}, + {0x336b, 0x00, 0, 0}, + {0x336c, 0x01, 0, 0}, + {0x336d, 0x00, 0, 0}, + {0x336e, 0x01, 0, 0}, + {0x336f, 0x00, 0, 0}, + {0x3370, 0x01, 0, 0}, + {0x3371, 0x00, 0, 0}, + {0x3372, 0x01, 0, 0}, + {0x3373, 0x00, 0, 0}, + {0x3374, 0x01, 0, 0}, + {0x3375, 0x00, 0, 0}, + {0x3376, 0x01, 0, 0}, + {0x3377, 0x00, 0, 0}, + {0x3378, 0x00, 0, 0}, + {0x3379, 0x00, 0, 0}, + {0x337a, 0x00, 0, 0}, + {0x337b, 0x00, 0, 0}, + {0x337c, 0x00, 0, 0}, + {0x337d, 0x00, 0, 0}, + {0x337e, 0x00, 0, 0}, + {0x337f, 0x00, 0, 0}, + {0x3380, 0x00, 0, 0}, + {0x3381, 0x00, 0, 0}, + {0x3382, 0x00, 0, 0}, + {0x3383, 0x00, 0, 0}, + {0x3384, 0x00, 0, 0}, + {0x3385, 0x00, 0, 0}, + {0x3386, 0x00, 0, 0}, + {0x3387, 0x00, 0, 0}, + {0x3388, 0x00, 0, 0}, + {0x3389, 0x00, 0, 0}, + {0x338a, 0x00, 0, 0}, + {0x338b, 0x00, 0, 0}, + {0x338c, 0x00, 0, 0}, + {0x338d, 0x00, 0, 0}, + {0x338e, 0x00, 0, 0}, + {0x338f, 0x00, 0, 0}, + {0x3390, 0x00, 0, 0}, + {0x3391, 0x00, 0, 0}, + {0x3392, 0x00, 0, 0}, + {0x3393, 0x00, 0, 0}, + {0x3394, 0x00, 0, 0}, + {0x3395, 0x00, 0, 0}, + {0x3396, 0x00, 0, 0}, + {0x3397, 0x00, 0, 0}, + {0x3398, 0x00, 0, 0}, + {0x3399, 0x00, 0, 0}, + {0x339a, 0x00, 0, 0}, + {0x339b, 0x00, 0, 0}, + {0x33b0, 0x00, 0, 0}, + {0x33b1, 0x50, 0, 0}, + {0x33b2, 0x01, 0, 0}, + {0x33b3, 0xff, 0, 0}, + {0x33b4, 0xe0, 0, 0}, + {0x33b5, 0x6b, 0, 0}, + {0x33b6, 0x00, 0, 0}, + {0x33b7, 0x00, 0, 0}, + {0x33b8, 0x00, 0, 0}, + {0x33b9, 0x00, 0, 0}, + {0x33ba, 0x00, 0, 0}, + {0x33bb, 0x1f, 0, 0}, + {0x33bc, 0x01, 0, 0}, + {0x33bd, 0x01, 0, 0}, + {0x33be, 0x01, 0, 0}, + {0x33bf, 0x01, 0, 0}, + {0x33c0, 0x00, 0, 0}, + {0x33c1, 0x00, 0, 0}, + {0x33c2, 0x00, 0, 0}, + {0x33c3, 0x00, 0, 0}, + {0x33e0, 0x14, 0, 0}, + {0x33e1, 0x0f, 0, 0}, + {0x33e2, 0x04, 0, 0}, + {0x33e3, 0x02, 0, 0}, + {0x33e4, 0x01, 0, 0}, + {0x33e5, 0x01, 0, 0}, + {0x33e6, 0x00, 0, 0}, + {0x33e7, 0x04, 0, 0}, + {0x33e8, 0x0c, 0, 0}, + {0x33e9, 0x02, 0, 0}, + {0x33ea, 0x02, 0, 0}, + {0x33eb, 0x02, 0, 0}, + {0x33ec, 0x03, 0, 0}, + {0x33ed, 0x02, 0, 0}, + {0x33ee, 0x05, 0, 0}, + {0x33ef, 0x0a, 0, 0}, + {0x33f0, 0x08, 0, 0}, + {0x33f1, 0x04, 0, 0}, + {0x33f2, 0x04, 0, 0}, + {0x33f3, 0x00, 0, 0}, + {0x33f4, 0x03, 0, 0}, + {0x33f5, 0x14, 0, 0}, + {0x33f6, 0x0f, 0, 0}, + {0x33f7, 0x02, 0, 0}, + {0x33f8, 0x01, 0, 0}, + {0x33f9, 0x01, 0, 0}, + {0x33fa, 0x01, 0, 0}, + {0x33fb, 0x00, 0, 0}, + {0x33fc, 0x04, 0, 0}, + {0x33fd, 0x0c, 0, 0}, + {0x33fe, 0x02, 0, 0}, + {0x33ff, 0x02, 0, 0}, + {0x3400, 0x02, 0, 0}, + {0x3401, 0x03, 0, 0}, + {0x3402, 0x01, 0, 0}, + {0x3403, 0x02, 0, 0}, + {0x3404, 0x08, 0, 0}, + {0x3405, 0x08, 0, 0}, + {0x3406, 0x04, 0, 0}, + {0x3407, 0x04, 0, 0}, + {0x3408, 0x00, 0, 0}, + {0x3409, 0x03, 0, 0}, + {0x340a, 0x14, 0, 0}, + {0x340b, 0x0f, 0, 0}, + {0x340c, 0x04, 0, 0}, + {0x340d, 0x02, 0, 0}, + {0x340e, 0x01, 0, 0}, + {0x340f, 0x01, 0, 0}, + {0x3410, 0x00, 0, 0}, + {0x3411, 0x04, 0, 0}, + {0x3412, 0x0c, 0, 0}, + {0x3413, 0x02, 0, 0}, + {0x3414, 0x02, 0, 0}, + {0x3415, 0x02, 0, 0}, + {0x3416, 0x03, 0, 0}, + {0x3417, 0x02, 0, 0}, + {0x3418, 0x05, 0, 0}, + {0x3419, 0x0a, 0, 0}, + {0x341a, 0x08, 0, 0}, + {0x341b, 0x04, 0, 0}, + {0x341c, 0x04, 0, 0}, + {0x341d, 0x00, 0, 0}, + {0x341e, 0x03, 0, 0}, + {0x3440, 0x00, 0, 0}, + {0x3441, 0x00, 0, 0}, + {0x3442, 0x00, 0, 0}, + {0x3443, 0x00, 0, 0}, + {0x3444, 0x02, 0, 0}, + {0x3445, 0xf0, 0, 0}, + {0x3446, 0x02, 0, 0}, + {0x3447, 0x08, 0, 0}, + {0x3448, 0x00, 0, 0}, + {0x3460, 0x40, 0, 0}, + {0x3461, 0x40, 0, 0}, + {0x3462, 0x40, 0, 0}, + {0x3463, 0x40, 0, 0}, + {0x3464, 0x03, 0, 0}, + {0x3465, 0x01, 0, 0}, + {0x3466, 0x01, 0, 0}, + {0x3467, 0x02, 0, 0}, + {0x3468, 0x30, 0, 0}, + {0x3469, 0x00, 0, 0}, + {0x346a, 0x35, 0, 0}, + {0x346b, 0x00, 0, 0}, + {0x3480, 0x40, 0, 0}, + {0x3481, 0x00, 0, 0}, + {0x3482, 0x00, 0, 0}, + {0x3483, 0x00, 0, 0}, + {0x3484, 0x0d, 0, 0}, + {0x3485, 0x00, 0, 0}, + {0x3486, 0x00, 0, 0}, + {0x3487, 0x00, 0, 0}, + {0x3488, 0x00, 0, 0}, + {0x3489, 0x00, 0, 0}, + {0x348a, 0x00, 0, 0}, + {0x348b, 0x04, 0, 0}, + {0x348c, 0x00, 0, 0}, + {0x348d, 0x01, 0, 0}, + {0x348f, 0x01, 0, 0}, + {0x3030, 0x0a, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x7000, 0x58, 0, 0}, + {0x7001, 0x7a, 0, 0}, + {0x7002, 0x1a, 0, 0}, + {0x7003, 0xc1, 0, 0}, + {0x7004, 0x03, 0, 0}, + {0x7005, 0xda, 0, 0}, + {0x7006, 0xbd, 0, 0}, + {0x7007, 0x03, 0, 0}, + {0x7008, 0xbd, 0, 0}, + {0x7009, 0x06, 0, 0}, + {0x700a, 0xe6, 0, 0}, + {0x700b, 0xec, 0, 0}, + {0x700c, 0xbc, 0, 0}, + {0x700d, 0xff, 0, 0}, + {0x700e, 0xbc, 0, 0}, + {0x700f, 0x73, 0, 0}, + {0x7010, 0xda, 0, 0}, + {0x7011, 0x72, 0, 0}, + {0x7012, 0x76, 0, 0}, + {0x7013, 0xb6, 0, 0}, + {0x7014, 0xee, 0, 0}, + {0x7015, 0xcf, 0, 0}, + {0x7016, 0xac, 0, 0}, + {0x7017, 0xd0, 0, 0}, + {0x7018, 0xac, 0, 0}, + {0x7019, 0xd1, 0, 0}, + {0x701a, 0x50, 0, 0}, + {0x701b, 0xac, 0, 0}, + {0x701c, 0xd2, 0, 0}, + {0x701d, 0xbc, 0, 0}, + {0x701e, 0x2e, 0, 0}, + {0x701f, 0xb4, 0, 0}, + {0x7020, 0x00, 0, 0}, + {0x7021, 0xdc, 0, 0}, + {0x7022, 0xdf, 0, 0}, + {0x7023, 0xb0, 0, 0}, + {0x7024, 0x6e, 0, 0}, + {0x7025, 0xbd, 0, 0}, + {0x7026, 0x01, 0, 0}, + {0x7027, 0xd7, 0, 0}, + {0x7028, 0xed, 0, 0}, + {0x7029, 0xe1, 0, 0}, + {0x702a, 0x36, 0, 0}, + {0x702b, 0x30, 0, 0}, + {0x702c, 0xd3, 0, 0}, + {0x702d, 0x2e, 0, 0}, + {0x702e, 0x54, 0, 0}, + {0x702f, 0x46, 0, 0}, + {0x7030, 0xbc, 0, 0}, + {0x7031, 0x22, 0, 0}, + {0x7032, 0x66, 0, 0}, + {0x7033, 0xbc, 0, 0}, + {0x7034, 0x24, 0, 0}, + {0x7035, 0x2c, 0, 0}, + {0x7036, 0x28, 0, 0}, + {0x7037, 0xbc, 0, 0}, + {0x7038, 0x3c, 0, 0}, + {0x7039, 0xa1, 0, 0}, + {0x703a, 0xac, 0, 0}, + {0x703b, 0xd8, 0, 0}, + {0x703c, 0xd6, 0, 0}, + {0x703d, 0xb4, 0, 0}, + {0x703e, 0x04, 0, 0}, + {0x703f, 0x46, 0, 0}, + {0x7040, 0xb7, 0, 0}, + {0x7041, 0x04, 0, 0}, + {0x7042, 0xbe, 0, 0}, + {0x7043, 0x08, 0, 0}, + {0x7044, 0xc3, 0, 0}, + {0x7045, 0xd9, 0, 0}, + {0x7046, 0xad, 0, 0}, + {0x7047, 0xc3, 0, 0}, + {0x7048, 0xbc, 0, 0}, + {0x7049, 0x19, 0, 0}, + {0x704a, 0xc1, 0, 0}, + {0x704b, 0x27, 0, 0}, + {0x704c, 0xe7, 0, 0}, + {0x704d, 0x00, 0, 0}, + {0x704e, 0x50, 0, 0}, + {0x704f, 0x20, 0, 0}, + {0x7050, 0xb8, 0, 0}, + {0x7051, 0x02, 0, 0}, + {0x7052, 0xbc, 0, 0}, + {0x7053, 0x17, 0, 0}, + {0x7054, 0xdb, 0, 0}, + {0x7055, 0xc7, 0, 0}, + {0x7056, 0xb8, 0, 0}, + {0x7057, 0x00, 0, 0}, + {0x7058, 0x28, 0, 0}, + {0x7059, 0x54, 0, 0}, + {0x705a, 0xb4, 0, 0}, + {0x705b, 0x14, 0, 0}, + {0x705c, 0xab, 0, 0}, + {0x705d, 0xbe, 0, 0}, + {0x705e, 0x06, 0, 0}, + {0x705f, 0xd8, 0, 0}, + {0x7060, 0xd6, 0, 0}, + {0x7061, 0x00, 0, 0}, + {0x7062, 0xb4, 0, 0}, + {0x7063, 0xc7, 0, 0}, + {0x7064, 0x07, 0, 0}, + {0x7065, 0xb9, 0, 0}, + {0x7066, 0x05, 0, 0}, + {0x7067, 0xee, 0, 0}, + {0x7068, 0xe6, 0, 0}, + {0x7069, 0xad, 0, 0}, + {0x706a, 0xb4, 0, 0}, + {0x706b, 0x26, 0, 0}, + {0x706c, 0x19, 0, 0}, + {0x706d, 0xc1, 0, 0}, + {0x706e, 0x3a, 0, 0}, + {0x706f, 0xc3, 0, 0}, + {0x7070, 0xaf, 0, 0}, + {0x7071, 0x00, 0, 0}, + {0x7072, 0xc0, 0, 0}, + {0x7073, 0x3c, 0, 0}, + {0x7074, 0xc3, 0, 0}, + {0x7075, 0xbe, 0, 0}, + {0x7076, 0xe7, 0, 0}, + {0x7077, 0x00, 0, 0}, + {0x7078, 0x15, 0, 0}, + {0x7079, 0xc2, 0, 0}, + {0x707a, 0x40, 0, 0}, + {0x707b, 0xc3, 0, 0}, + {0x707c, 0xa4, 0, 0}, + {0x707d, 0xc0, 0, 0}, + {0x707e, 0x3c, 0, 0}, + {0x707f, 0x00, 0, 0}, + {0x7080, 0xb9, 0, 0}, + {0x7081, 0x64, 0, 0}, + {0x7082, 0x29, 0, 0}, + {0x7083, 0x00, 0, 0}, + {0x7084, 0xb8, 0, 0}, + {0x7085, 0x12, 0, 0}, + {0x7086, 0xbe, 0, 0}, + {0x7087, 0x01, 0, 0}, + {0x7088, 0xd0, 0, 0}, + {0x7089, 0xbc, 0, 0}, + {0x708a, 0x01, 0, 0}, + {0x708b, 0xac, 0, 0}, + {0x708c, 0x37, 0, 0}, + {0x708d, 0xd2, 0, 0}, + {0x708e, 0xac, 0, 0}, + {0x708f, 0x45, 0, 0}, + {0x7090, 0xad, 0, 0}, + {0x7091, 0x28, 0, 0}, + {0x7092, 0x00, 0, 0}, + {0x7093, 0xb8, 0, 0}, + {0x7094, 0x00, 0, 0}, + {0x7095, 0xbc, 0, 0}, + {0x7096, 0x01, 0, 0}, + {0x7097, 0x36, 0, 0}, + {0x7098, 0xd3, 0, 0}, + {0x7099, 0x30, 0, 0}, + {0x709a, 0x04, 0, 0}, + {0x709b, 0xe0, 0, 0}, + {0x709c, 0xd8, 0, 0}, + {0x709d, 0xb4, 0, 0}, + {0x709e, 0xe9, 0, 0}, + {0x709f, 0x00, 0, 0}, + {0x70a0, 0xbe, 0, 0}, + {0x70a1, 0x05, 0, 0}, + {0x70a2, 0x62, 0, 0}, + {0x70a3, 0x07, 0, 0}, + {0x70a4, 0xb9, 0, 0}, + {0x70a5, 0x05, 0, 0}, + {0x70a6, 0xad, 0, 0}, + {0x70a7, 0xc3, 0, 0}, + {0x70a8, 0xcf, 0, 0}, + {0x70a9, 0x00, 0, 0}, + {0x70aa, 0x15, 0, 0}, + {0x70ab, 0xc2, 0, 0}, + {0x70ac, 0x59, 0, 0}, + {0x70ad, 0xc3, 0, 0}, + {0x70ae, 0xc9, 0, 0}, + {0x70af, 0xc0, 0, 0}, + {0x70b0, 0x55, 0, 0}, + {0x70b1, 0x00, 0, 0}, + {0x70b2, 0x46, 0, 0}, + {0x70b3, 0xa1, 0, 0}, + {0x70b4, 0xb9, 0, 0}, + {0x70b5, 0x64, 0, 0}, + {0x70b6, 0x29, 0, 0}, + {0x70b7, 0x00, 0, 0}, + {0x70b8, 0xb8, 0, 0}, + {0x70b9, 0x02, 0, 0}, + {0x70ba, 0xbe, 0, 0}, + {0x70bb, 0x02, 0, 0}, + {0x70bc, 0xd0, 0, 0}, + {0x70bd, 0xdc, 0, 0}, + {0x70be, 0xac, 0, 0}, + {0x70bf, 0xbc, 0, 0}, + {0x70c0, 0x01, 0, 0}, + {0x70c1, 0x37, 0, 0}, + {0x70c2, 0xac, 0, 0}, + {0x70c3, 0xd2, 0, 0}, + {0x70c4, 0x45, 0, 0}, + {0x70c5, 0xad, 0, 0}, + {0x70c6, 0x28, 0, 0}, + {0x70c7, 0x00, 0, 0}, + {0x70c8, 0xb8, 0, 0}, + {0x70c9, 0x00, 0, 0}, + {0x70ca, 0xbc, 0, 0}, + {0x70cb, 0x01, 0, 0}, + {0x70cc, 0x36, 0, 0}, + {0x70cd, 0x30, 0, 0}, + {0x70ce, 0xe0, 0, 0}, + {0x70cf, 0xd8, 0, 0}, + {0x70d0, 0xb5, 0, 0}, + {0x70d1, 0x0b, 0, 0}, + {0x70d2, 0xd6, 0, 0}, + {0x70d3, 0xbe, 0, 0}, + {0x70d4, 0x07, 0, 0}, + {0x70d5, 0x00, 0, 0}, + {0x70d6, 0x62, 0, 0}, + {0x70d7, 0x07, 0, 0}, + {0x70d8, 0xb9, 0, 0}, + {0x70d9, 0x05, 0, 0}, + {0x70da, 0xad, 0, 0}, + {0x70db, 0xc3, 0, 0}, + {0x70dc, 0xcf, 0, 0}, + {0x70dd, 0x46, 0, 0}, + {0x70de, 0xcd, 0, 0}, + {0x70df, 0x07, 0, 0}, + {0x70e0, 0xcd, 0, 0}, + {0x70e1, 0x00, 0, 0}, + {0x70e2, 0xe3, 0, 0}, + {0x70e3, 0x18, 0, 0}, + {0x70e4, 0xc2, 0, 0}, + {0x70e5, 0xa2, 0, 0}, + {0x70e6, 0xb9, 0, 0}, + {0x70e7, 0x64, 0, 0}, + {0x70e8, 0xd1, 0, 0}, + {0x70e9, 0xdd, 0, 0}, + {0x70ea, 0xac, 0, 0}, + {0x70eb, 0xcf, 0, 0}, + {0x70ec, 0xdf, 0, 0}, + {0x70ed, 0xb5, 0, 0}, + {0x70ee, 0x19, 0, 0}, + {0x70ef, 0x46, 0, 0}, + {0x70f0, 0x50, 0, 0}, + {0x70f1, 0xb6, 0, 0}, + {0x70f2, 0xee, 0, 0}, + {0x70f3, 0xe8, 0, 0}, + {0x70f4, 0xe6, 0, 0}, + {0x70f5, 0xbc, 0, 0}, + {0x70f6, 0x31, 0, 0}, + {0x70f7, 0xe1, 0, 0}, + {0x70f8, 0x36, 0, 0}, + {0x70f9, 0x30, 0, 0}, + {0x70fa, 0xd3, 0, 0}, + {0x70fb, 0x2e, 0, 0}, + {0x70fc, 0x54, 0, 0}, + {0x70fd, 0xbd, 0, 0}, + {0x70fe, 0x03, 0, 0}, + {0x70ff, 0xec, 0, 0}, + {0x7100, 0x2c, 0, 0}, + {0x7101, 0x50, 0, 0}, + {0x7102, 0x20, 0, 0}, + {0x7103, 0x04, 0, 0}, + {0x7104, 0xb8, 0, 0}, + {0x7105, 0x02, 0, 0}, + {0x7106, 0xbc, 0, 0}, + {0x7107, 0x18, 0, 0}, + {0x7108, 0xc7, 0, 0}, + {0x7109, 0xb8, 0, 0}, + {0x710a, 0x00, 0, 0}, + {0x710b, 0x28, 0, 0}, + {0x710c, 0x54, 0, 0}, + {0x710d, 0xbc, 0, 0}, + {0x710e, 0x02, 0, 0}, + {0x710f, 0xb4, 0, 0}, + {0x7110, 0xda, 0, 0}, + {0x7111, 0xbe, 0, 0}, + {0x7112, 0x04, 0, 0}, + {0x7113, 0xd6, 0, 0}, + {0x7114, 0xd8, 0, 0}, + {0x7115, 0xab, 0, 0}, + {0x7116, 0x00, 0, 0}, + {0x7117, 0x62, 0, 0}, + {0x7118, 0x07, 0, 0}, + {0x7119, 0xb9, 0, 0}, + {0x711a, 0x05, 0, 0}, + {0x711b, 0xad, 0, 0}, + {0x711c, 0xc3, 0, 0}, + {0x711d, 0xbc, 0, 0}, + {0x711e, 0xe7, 0, 0}, + {0x711f, 0xb9, 0, 0}, + {0x7120, 0x64, 0, 0}, + {0x7121, 0x29, 0, 0}, + {0x7122, 0x00, 0, 0}, + {0x7123, 0xb8, 0, 0}, + {0x7124, 0x02, 0, 0}, + {0x7125, 0xbe, 0, 0}, + {0x7126, 0x00, 0, 0}, + {0x7127, 0x45, 0, 0}, + {0x7128, 0xad, 0, 0}, + {0x7129, 0xe2, 0, 0}, + {0x712a, 0x28, 0, 0}, + {0x712b, 0x00, 0, 0}, + {0x712c, 0xb8, 0, 0}, + {0x712d, 0x00, 0, 0}, + {0x712e, 0xe0, 0, 0}, + {0x712f, 0xd8, 0, 0}, + {0x7130, 0xb4, 0, 0}, + {0x7131, 0xe9, 0, 0}, + {0x7132, 0xbe, 0, 0}, + {0x7133, 0x03, 0, 0}, + {0x7134, 0x00, 0, 0}, + {0x7135, 0x30, 0, 0}, + {0x7136, 0x62, 0, 0}, + {0x7137, 0x07, 0, 0}, + {0x7138, 0xb9, 0, 0}, + {0x7139, 0x05, 0, 0}, + {0x713a, 0xad, 0, 0}, + {0x713b, 0xc3, 0, 0}, + {0x713c, 0xcf, 0, 0}, + {0x713d, 0x42, 0, 0}, + {0x713e, 0xe4, 0, 0}, + {0x713f, 0xcd, 0, 0}, + {0x7140, 0x07, 0, 0}, + {0x7141, 0xcd, 0, 0}, + {0x7142, 0x00, 0, 0}, + {0x7143, 0x00, 0, 0}, + {0x7144, 0x17, 0, 0}, + {0x7145, 0xc2, 0, 0}, + {0x7146, 0xbb, 0, 0}, + {0x7147, 0xde, 0, 0}, + {0x7148, 0xcf, 0, 0}, + {0x7149, 0xdf, 0, 0}, + {0x714a, 0xac, 0, 0}, + {0x714b, 0xd1, 0, 0}, + {0x714c, 0x44, 0, 0}, + {0x714d, 0xac, 0, 0}, + {0x714e, 0xb9, 0, 0}, + {0x714f, 0x76, 0, 0}, + {0x7150, 0xb8, 0, 0}, + {0x7151, 0x08, 0, 0}, + {0x7152, 0xb6, 0, 0}, + {0x7153, 0xfe, 0, 0}, + {0x7154, 0xb4, 0, 0}, + {0x7155, 0xca, 0, 0}, + {0x7156, 0xd6, 0, 0}, + {0x7157, 0xd8, 0, 0}, + {0x7158, 0xab, 0, 0}, + {0x7159, 0x00, 0, 0}, + {0x715a, 0xe1, 0, 0}, + {0x715b, 0x36, 0, 0}, + {0x715c, 0x30, 0, 0}, + {0x715d, 0xd3, 0, 0}, + {0x715e, 0xbc, 0, 0}, + {0x715f, 0x29, 0, 0}, + {0x7160, 0xb4, 0, 0}, + {0x7161, 0x1f, 0, 0}, + {0x7162, 0xaa, 0, 0}, + {0x7163, 0xbd, 0, 0}, + {0x7164, 0x01, 0, 0}, + {0x7165, 0xb8, 0, 0}, + {0x7166, 0x0c, 0, 0}, + {0x7167, 0x45, 0, 0}, + {0x7168, 0xa4, 0, 0}, + {0x7169, 0xbd, 0, 0}, + {0x716a, 0x03, 0, 0}, + {0x716b, 0xec, 0, 0}, + {0x716c, 0xbc, 0, 0}, + {0x716d, 0x3d, 0, 0}, + {0x716e, 0xc3, 0, 0}, + {0x716f, 0xcf, 0, 0}, + {0x7170, 0x42, 0, 0}, + {0x7171, 0xb8, 0, 0}, + {0x7172, 0x00, 0, 0}, + {0x7173, 0xe4, 0, 0}, + {0x7174, 0xd5, 0, 0}, + {0x7175, 0x00, 0, 0}, + {0x7176, 0xb6, 0, 0}, + {0x7177, 0x00, 0, 0}, + {0x7178, 0x74, 0, 0}, + {0x7179, 0xbd, 0, 0}, + {0x717a, 0x03, 0, 0}, + {0x717b, 0xb5, 0, 0}, + {0x717c, 0x39, 0, 0}, + {0x717d, 0x40, 0, 0}, + {0x717e, 0x58, 0, 0}, + {0x717f, 0xdd, 0, 0}, + {0x7180, 0x19, 0, 0}, + {0x7181, 0xc1, 0, 0}, + {0x7182, 0xc8, 0, 0}, + {0x7183, 0xbd, 0, 0}, + {0x7184, 0x06, 0, 0}, + {0x7185, 0x17, 0, 0}, + {0x7186, 0xc1, 0, 0}, + {0x7187, 0xc6, 0, 0}, + {0x7188, 0xe8, 0, 0}, + {0x7189, 0x00, 0, 0}, + {0x718a, 0xc0, 0, 0}, + {0x718b, 0xc8, 0, 0}, + {0x718c, 0xe6, 0, 0}, + {0x718d, 0x95, 0, 0}, + {0x718e, 0x15, 0, 0}, + {0x718f, 0x00, 0, 0}, + {0x7190, 0xbc, 0, 0}, + {0x7191, 0x19, 0, 0}, + {0x7192, 0xb9, 0, 0}, + {0x7193, 0xf6, 0, 0}, + {0x7194, 0x14, 0, 0}, + {0x7195, 0xc1, 0, 0}, + {0x7196, 0xd0, 0, 0}, + {0x7197, 0xd1, 0, 0}, + {0x7198, 0xac, 0, 0}, + {0x7199, 0x37, 0, 0}, + {0x719a, 0xbc, 0, 0}, + {0x719b, 0x35, 0, 0}, + {0x719c, 0x36, 0, 0}, + {0x719d, 0x30, 0, 0}, + {0x719e, 0xe1, 0, 0}, + {0x719f, 0xd3, 0, 0}, + {0x71a0, 0x7a, 0, 0}, + {0x71a1, 0xb6, 0, 0}, + {0x71a2, 0x0c, 0, 0}, + {0x71a3, 0xff, 0, 0}, + {0x71a4, 0xb4, 0, 0}, + {0x71a5, 0xc7, 0, 0}, + {0x71a6, 0xd9, 0, 0}, + {0x71a7, 0x00, 0, 0}, + {0x71a8, 0xbd, 0, 0}, + {0x71a9, 0x01, 0, 0}, + {0x71aa, 0x56, 0, 0}, + {0x71ab, 0xc0, 0, 0}, + {0x71ac, 0xda, 0, 0}, + {0x71ad, 0xb4, 0, 0}, + {0x71ae, 0x1f, 0, 0}, + {0x71af, 0x56, 0, 0}, + {0x71b0, 0xaa, 0, 0}, + {0x71b1, 0xbc, 0, 0}, + {0x71b2, 0x08, 0, 0}, + {0x71b3, 0x00, 0, 0}, + {0x71b4, 0x57, 0, 0}, + {0x71b5, 0xe8, 0, 0}, + {0x71b6, 0xb5, 0, 0}, + {0x71b7, 0x36, 0, 0}, + {0x71b8, 0x00, 0, 0}, + {0x71b9, 0x54, 0, 0}, + {0x71ba, 0xe7, 0, 0}, + {0x71bb, 0xc8, 0, 0}, + {0x71bc, 0xb4, 0, 0}, + {0x71bd, 0x1f, 0, 0}, + {0x71be, 0x56, 0, 0}, + {0x71bf, 0xaa, 0, 0}, + {0x71c0, 0xbc, 0, 0}, + {0x71c1, 0x08, 0, 0}, + {0x71c2, 0x57, 0, 0}, + {0x71c3, 0x00, 0, 0}, + {0x71c4, 0xb5, 0, 0}, + {0x71c5, 0x36, 0, 0}, + {0x71c6, 0x00, 0, 0}, + {0x71c7, 0x54, 0, 0}, + {0x71c8, 0xc8, 0, 0}, + {0x71c9, 0xb5, 0, 0}, + {0x71ca, 0x18, 0, 0}, + {0x71cb, 0xd9, 0, 0}, + {0x71cc, 0x00, 0, 0}, + {0x71cd, 0xbd, 0, 0}, + {0x71ce, 0x01, 0, 0}, + {0x71cf, 0x56, 0, 0}, + {0x71d0, 0x08, 0, 0}, + {0x71d1, 0x57, 0, 0}, + {0x71d2, 0xe8, 0, 0}, + {0x71d3, 0xb4, 0, 0}, + {0x71d4, 0x42, 0, 0}, + {0x71d5, 0x00, 0, 0}, + {0x71d6, 0x54, 0, 0}, + {0x71d7, 0xe7, 0, 0}, + {0x71d8, 0xc8, 0, 0}, + {0x71d9, 0xab, 0, 0}, + {0x71da, 0x00, 0, 0}, + {0x71db, 0x66, 0, 0}, + {0x71dc, 0x62, 0, 0}, + {0x71dd, 0x06, 0, 0}, + {0x71de, 0x74, 0, 0}, + {0x71df, 0xb9, 0, 0}, + {0x71e0, 0x05, 0, 0}, + {0x71e1, 0xb7, 0, 0}, + {0x71e2, 0x14, 0, 0}, + {0x71e3, 0x0e, 0, 0}, + {0x71e4, 0xb7, 0, 0}, + {0x71e5, 0x04, 0, 0}, + {0x71e6, 0xc8, 0, 0}, + {0x7600, 0x04, 0, 0}, + {0x7601, 0x80, 0, 0}, + {0x7602, 0x07, 0, 0}, + {0x7603, 0x44, 0, 0}, + {0x7604, 0x05, 0, 0}, + {0x7605, 0x33, 0, 0}, + {0x7606, 0x0f, 0, 0}, + {0x7607, 0x00, 0, 0}, + {0x7608, 0x07, 0, 0}, + {0x7609, 0x40, 0, 0}, + {0x760a, 0x04, 0, 0}, + {0x760b, 0xe5, 0, 0}, + {0x760c, 0x06, 0, 0}, + {0x760d, 0x50, 0, 0}, + {0x760e, 0x04, 0, 0}, + {0x760f, 0xe4, 0, 0}, + {0x7610, 0x00, 0, 0}, + {0x7611, 0x00, 0, 0}, + {0x7612, 0x06, 0, 0}, + {0x7613, 0x5c, 0, 0}, + {0x7614, 0x00, 0, 0}, + {0x7615, 0x0f, 0, 0}, + {0x7616, 0x06, 0, 0}, + {0x7617, 0x1c, 0, 0}, + {0x7618, 0x00, 0, 0}, + {0x7619, 0x02, 0, 0}, + {0x761a, 0x06, 0, 0}, + {0x761b, 0xa2, 0, 0}, + {0x761c, 0x00, 0, 0}, + {0x761d, 0x01, 0, 0}, + {0x761e, 0x06, 0, 0}, + {0x761f, 0xae, 0, 0}, + {0x7620, 0x00, 0, 0}, + {0x7621, 0x0e, 0, 0}, + {0x7622, 0x05, 0, 0}, + {0x7623, 0x30, 0, 0}, + {0x7624, 0x07, 0, 0}, + {0x7625, 0x00, 0, 0}, + {0x7626, 0x0f, 0, 0}, + {0x7627, 0x00, 0, 0}, + {0x7628, 0x04, 0, 0}, + {0x7629, 0xe5, 0, 0}, + {0x762a, 0x05, 0, 0}, + {0x762b, 0x33, 0, 0}, + {0x762c, 0x06, 0, 0}, + {0x762d, 0x12, 0, 0}, + {0x762e, 0x00, 0, 0}, + {0x762f, 0x01, 0, 0}, + {0x7630, 0x06, 0, 0}, + {0x7631, 0x52, 0, 0}, + {0x7632, 0x00, 0, 0}, + {0x7633, 0x01, 0, 0}, + {0x7634, 0x06, 0, 0}, + {0x7635, 0x5e, 0, 0}, + {0x7636, 0x04, 0, 0}, + {0x7637, 0xe4, 0, 0}, + {0x7638, 0x00, 0, 0}, + {0x7639, 0x01, 0, 0}, + {0x763a, 0x05, 0, 0}, + {0x763b, 0x30, 0, 0}, + {0x763c, 0x0f, 0, 0}, + {0x763d, 0x00, 0, 0}, + {0x763e, 0x06, 0, 0}, + {0x763f, 0xa6, 0, 0}, + {0x7640, 0x00, 0, 0}, + {0x7641, 0x02, 0, 0}, + {0x7642, 0x06, 0, 0}, + {0x7643, 0x26, 0, 0}, + {0x7644, 0x00, 0, 0}, + {0x7645, 0x02, 0, 0}, + {0x7646, 0x05, 0, 0}, + {0x7647, 0x33, 0, 0}, + {0x7648, 0x06, 0, 0}, + {0x7649, 0x20, 0, 0}, + {0x764a, 0x0f, 0, 0}, + {0x764b, 0x00, 0, 0}, + {0x764c, 0x06, 0, 0}, + {0x764d, 0x56, 0, 0}, + {0x764e, 0x00, 0, 0}, + {0x764f, 0x02, 0, 0}, + {0x7650, 0x06, 0, 0}, + {0x7651, 0x16, 0, 0}, + {0x7652, 0x05, 0, 0}, + {0x7653, 0x33, 0, 0}, + {0x7654, 0x06, 0, 0}, + {0x7655, 0x10, 0, 0}, + {0x7656, 0x0f, 0, 0}, + {0x7657, 0x00, 0, 0}, + {0x7658, 0x06, 0, 0}, + {0x7659, 0x10, 0, 0}, + {0x765a, 0x0f, 0, 0}, + {0x765b, 0x00, 0, 0}, + {0x765c, 0x06, 0, 0}, + {0x765d, 0x20, 0, 0}, + {0x765e, 0x0f, 0, 0}, + {0x765f, 0x00, 0, 0}, + {0x7660, 0x00, 0, 0}, + {0x7661, 0x00, 0, 0}, + {0x7662, 0x00, 0, 0}, + {0x7663, 0x02, 0, 0}, + {0x7664, 0x04, 0, 0}, + {0x7665, 0xe5, 0, 0}, + {0x7666, 0x04, 0, 0}, + {0x7667, 0xe4, 0, 0}, + {0x7668, 0x0f, 0, 0}, + {0x7669, 0x00, 0, 0}, + {0x766a, 0x00, 0, 0}, + {0x766b, 0x00, 0, 0}, + {0x766c, 0x00, 0, 0}, + {0x766d, 0x01, 0, 0}, + {0x766e, 0x04, 0, 0}, + {0x766f, 0xe5, 0, 0}, + {0x7670, 0x04, 0, 0}, + {0x7671, 0xe4, 0, 0}, + {0x7672, 0x0f, 0, 0}, + {0x7673, 0x00, 0, 0}, + {0x7674, 0x00, 0, 0}, + {0x7675, 0x02, 0, 0}, + {0x7676, 0x04, 0, 0}, + {0x7677, 0xe4, 0, 0}, + {0x7678, 0x00, 0, 0}, + {0x7679, 0x02, 0, 0}, + {0x767a, 0x04, 0, 0}, + {0x767b, 0xc4, 0, 0}, + {0x767c, 0x00, 0, 0}, + {0x767d, 0x02, 0, 0}, + {0x767e, 0x04, 0, 0}, + {0x767f, 0xc4, 0, 0}, + {0x7680, 0x05, 0, 0}, + {0x7681, 0x83, 0, 0}, + {0x7682, 0x0f, 0, 0}, + {0x7683, 0x00, 0, 0}, + {0x7684, 0x00, 0, 0}, + {0x7685, 0x02, 0, 0}, + {0x7686, 0x04, 0, 0}, + {0x7687, 0xe4, 0, 0}, + {0x7688, 0x00, 0, 0}, + {0x7689, 0x02, 0, 0}, + {0x768a, 0x04, 0, 0}, + {0x768b, 0xc4, 0, 0}, + {0x768c, 0x00, 0, 0}, + {0x768d, 0x02, 0, 0}, + {0x768e, 0x04, 0, 0}, + {0x768f, 0xc4, 0, 0}, + {0x7690, 0x05, 0, 0}, + {0x7691, 0x83, 0, 0}, + {0x7692, 0x03, 0, 0}, + {0x7693, 0x0b, 0, 0}, + {0x7694, 0x05, 0, 0}, + {0x7695, 0x83, 0, 0}, + {0x7696, 0x00, 0, 0}, + {0x7697, 0x07, 0, 0}, + {0x7698, 0x05, 0, 0}, + {0x7699, 0x03, 0, 0}, + {0x769a, 0x00, 0, 0}, + {0x769b, 0x05, 0, 0}, + {0x769c, 0x05, 0, 0}, + {0x769d, 0x32, 0, 0}, + {0x769e, 0x05, 0, 0}, + {0x769f, 0x30, 0, 0}, + {0x76a0, 0x00, 0, 0}, + {0x76a1, 0x02, 0, 0}, + {0x76a2, 0x05, 0, 0}, + {0x76a3, 0x78, 0, 0}, + {0x76a4, 0x00, 0, 0}, + {0x76a5, 0x01, 0, 0}, + {0x76a6, 0x05, 0, 0}, + {0x76a7, 0x7c, 0, 0}, + {0x76a8, 0x03, 0, 0}, + {0x76a9, 0x9a, 0, 0}, + {0x76aa, 0x05, 0, 0}, + {0x76ab, 0x83, 0, 0}, + {0x76ac, 0x00, 0, 0}, + {0x76ad, 0x04, 0, 0}, + {0x76ae, 0x05, 0, 0}, + {0x76af, 0x03, 0, 0}, + {0x76b0, 0x00, 0, 0}, + {0x76b1, 0x03, 0, 0}, + {0x76b2, 0x05, 0, 0}, + {0x76b3, 0x32, 0, 0}, + {0x76b4, 0x05, 0, 0}, + {0x76b5, 0x30, 0, 0}, + {0x76b6, 0x00, 0, 0}, + {0x76b7, 0x02, 0, 0}, + {0x76b8, 0x05, 0, 0}, + {0x76b9, 0x78, 0, 0}, + {0x76ba, 0x00, 0, 0}, + {0x76bb, 0x01, 0, 0}, + {0x76bc, 0x05, 0, 0}, + {0x76bd, 0x7c, 0, 0}, + {0x76be, 0x03, 0, 0}, + {0x76bf, 0x99, 0, 0}, + {0x76c0, 0x05, 0, 0}, + {0x76c1, 0x83, 0, 0}, + {0x76c2, 0x00, 0, 0}, + {0x76c3, 0x03, 0, 0}, + {0x76c4, 0x05, 0, 0}, + {0x76c5, 0x03, 0, 0}, + {0x76c6, 0x00, 0, 0}, + {0x76c7, 0x01, 0, 0}, + {0x76c8, 0x05, 0, 0}, + {0x76c9, 0x32, 0, 0}, + {0x76ca, 0x05, 0, 0}, + {0x76cb, 0x30, 0, 0}, + {0x76cc, 0x00, 0, 0}, + {0x76cd, 0x02, 0, 0}, + {0x76ce, 0x05, 0, 0}, + {0x76cf, 0x78, 0, 0}, + {0x76d0, 0x00, 0, 0}, + {0x76d1, 0x01, 0, 0}, + {0x76d2, 0x05, 0, 0}, + {0x76d3, 0x7c, 0, 0}, + {0x76d4, 0x03, 0, 0}, + {0x76d5, 0x98, 0, 0}, + {0x76d6, 0x05, 0, 0}, + {0x76d7, 0x83, 0, 0}, + {0x76d8, 0x00, 0, 0}, + {0x76d9, 0x00, 0, 0}, + {0x76da, 0x05, 0, 0}, + {0x76db, 0x03, 0, 0}, + {0x76dc, 0x00, 0, 0}, + {0x76dd, 0x01, 0, 0}, + {0x76de, 0x05, 0, 0}, + {0x76df, 0x32, 0, 0}, + {0x76e0, 0x05, 0, 0}, + {0x76e1, 0x30, 0, 0}, + {0x76e2, 0x00, 0, 0}, + {0x76e3, 0x02, 0, 0}, + {0x76e4, 0x05, 0, 0}, + {0x76e5, 0x78, 0, 0}, + {0x76e6, 0x00, 0, 0}, + {0x76e7, 0x01, 0, 0}, + {0x76e8, 0x05, 0, 0}, + {0x76e9, 0x7c, 0, 0}, + {0x76ea, 0x03, 0, 0}, + {0x76eb, 0x97, 0, 0}, + {0x76ec, 0x05, 0, 0}, + {0x76ed, 0x83, 0, 0}, + {0x76ee, 0x00, 0, 0}, + {0x76ef, 0x00, 0, 0}, + {0x76f0, 0x05, 0, 0}, + {0x76f1, 0x03, 0, 0}, + {0x76f2, 0x05, 0, 0}, + {0x76f3, 0x32, 0, 0}, + {0x76f4, 0x05, 0, 0}, + {0x76f5, 0x30, 0, 0}, + {0x76f6, 0x00, 0, 0}, + {0x76f7, 0x02, 0, 0}, + {0x76f8, 0x05, 0, 0}, + {0x76f9, 0x78, 0, 0}, + {0x76fa, 0x00, 0, 0}, + {0x76fb, 0x01, 0, 0}, + {0x76fc, 0x05, 0, 0}, + {0x76fd, 0x7c, 0, 0}, + {0x76fe, 0x03, 0, 0}, + {0x76ff, 0x96, 0, 0}, + {0x7700, 0x05, 0, 0}, + {0x7701, 0x83, 0, 0}, + {0x7702, 0x05, 0, 0}, + {0x7703, 0x03, 0, 0}, + {0x7704, 0x05, 0, 0}, + {0x7705, 0x32, 0, 0}, + {0x7706, 0x05, 0, 0}, + {0x7707, 0x30, 0, 0}, + {0x7708, 0x00, 0, 0}, + {0x7709, 0x02, 0, 0}, + {0x770a, 0x05, 0, 0}, + {0x770b, 0x78, 0, 0}, + {0x770c, 0x00, 0, 0}, + {0x770d, 0x01, 0, 0}, + {0x770e, 0x05, 0, 0}, + {0x770f, 0x7c, 0, 0}, + {0x7710, 0x03, 0, 0}, + {0x7711, 0x95, 0, 0}, + {0x7712, 0x05, 0, 0}, + {0x7713, 0x83, 0, 0}, + {0x7714, 0x05, 0, 0}, + {0x7715, 0x03, 0, 0}, + {0x7716, 0x05, 0, 0}, + {0x7717, 0x32, 0, 0}, + {0x7718, 0x05, 0, 0}, + {0x7719, 0x30, 0, 0}, + {0x771a, 0x00, 0, 0}, + {0x771b, 0x02, 0, 0}, + {0x771c, 0x05, 0, 0}, + {0x771d, 0x78, 0, 0}, + {0x771e, 0x00, 0, 0}, + {0x771f, 0x01, 0, 0}, + {0x7720, 0x05, 0, 0}, + {0x7721, 0x7c, 0, 0}, + {0x7722, 0x03, 0, 0}, + {0x7723, 0x94, 0, 0}, + {0x7724, 0x05, 0, 0}, + {0x7725, 0x83, 0, 0}, + {0x7726, 0x00, 0, 0}, + {0x7727, 0x01, 0, 0}, + {0x7728, 0x05, 0, 0}, + {0x7729, 0x03, 0, 0}, + {0x772a, 0x00, 0, 0}, + {0x772b, 0x01, 0, 0}, + {0x772c, 0x05, 0, 0}, + {0x772d, 0x32, 0, 0}, + {0x772e, 0x05, 0, 0}, + {0x772f, 0x30, 0, 0}, + {0x7730, 0x00, 0, 0}, + {0x7731, 0x02, 0, 0}, + {0x7732, 0x05, 0, 0}, + {0x7733, 0x78, 0, 0}, + {0x7734, 0x00, 0, 0}, + {0x7735, 0x01, 0, 0}, + {0x7736, 0x05, 0, 0}, + {0x7737, 0x7c, 0, 0}, + {0x7738, 0x03, 0, 0}, + {0x7739, 0x93, 0, 0}, + {0x773a, 0x05, 0, 0}, + {0x773b, 0x83, 0, 0}, + {0x773c, 0x00, 0, 0}, + {0x773d, 0x00, 0, 0}, + {0x773e, 0x05, 0, 0}, + {0x773f, 0x03, 0, 0}, + {0x7740, 0x00, 0, 0}, + {0x7741, 0x00, 0, 0}, + {0x7742, 0x05, 0, 0}, + {0x7743, 0x32, 0, 0}, + {0x7744, 0x05, 0, 0}, + {0x7745, 0x30, 0, 0}, + {0x7746, 0x00, 0, 0}, + {0x7747, 0x02, 0, 0}, + {0x7748, 0x05, 0, 0}, + {0x7749, 0x78, 0, 0}, + {0x774a, 0x00, 0, 0}, + {0x774b, 0x01, 0, 0}, + {0x774c, 0x05, 0, 0}, + {0x774d, 0x7c, 0, 0}, + {0x774e, 0x03, 0, 0}, + {0x774f, 0x92, 0, 0}, + {0x7750, 0x05, 0, 0}, + {0x7751, 0x83, 0, 0}, + {0x7752, 0x05, 0, 0}, + {0x7753, 0x03, 0, 0}, + {0x7754, 0x00, 0, 0}, + {0x7755, 0x00, 0, 0}, + {0x7756, 0x05, 0, 0}, + {0x7757, 0x32, 0, 0}, + {0x7758, 0x05, 0, 0}, + {0x7759, 0x30, 0, 0}, + {0x775a, 0x00, 0, 0}, + {0x775b, 0x02, 0, 0}, + {0x775c, 0x05, 0, 0}, + {0x775d, 0x78, 0, 0}, + {0x775e, 0x00, 0, 0}, + {0x775f, 0x01, 0, 0}, + {0x7760, 0x05, 0, 0}, + {0x7761, 0x7c, 0, 0}, + {0x7762, 0x03, 0, 0}, + {0x7763, 0x91, 0, 0}, + {0x7764, 0x05, 0, 0}, + {0x7765, 0x83, 0, 0}, + {0x7766, 0x05, 0, 0}, + {0x7767, 0x03, 0, 0}, + {0x7768, 0x05, 0, 0}, + {0x7769, 0x32, 0, 0}, + {0x776a, 0x05, 0, 0}, + {0x776b, 0x30, 0, 0}, + {0x776c, 0x00, 0, 0}, + {0x776d, 0x02, 0, 0}, + {0x776e, 0x05, 0, 0}, + {0x776f, 0x78, 0, 0}, + {0x7770, 0x00, 0, 0}, + {0x7771, 0x01, 0, 0}, + {0x7772, 0x05, 0, 0}, + {0x7773, 0x7c, 0, 0}, + {0x7774, 0x03, 0, 0}, + {0x7775, 0x90, 0, 0}, + {0x7776, 0x05, 0, 0}, + {0x7777, 0x83, 0, 0}, + {0x7778, 0x05, 0, 0}, + {0x7779, 0x03, 0, 0}, + {0x777a, 0x05, 0, 0}, + {0x777b, 0x32, 0, 0}, + {0x777c, 0x05, 0, 0}, + {0x777d, 0x30, 0, 0}, + {0x777e, 0x00, 0, 0}, + {0x777f, 0x02, 0, 0}, + {0x7780, 0x05, 0, 0}, + {0x7781, 0x78, 0, 0}, + {0x7782, 0x00, 0, 0}, + {0x7783, 0x01, 0, 0}, + {0x7784, 0x05, 0, 0}, + {0x7785, 0x7c, 0, 0}, + {0x7786, 0x02, 0, 0}, + {0x7787, 0x90, 0, 0}, + {0x7788, 0x05, 0, 0}, + {0x7789, 0x03, 0, 0}, + {0x778a, 0x07, 0, 0}, + {0x778b, 0x00, 0, 0}, + {0x778c, 0x0f, 0, 0}, + {0x778d, 0x00, 0, 0}, + {0x778e, 0x08, 0, 0}, + {0x778f, 0x30, 0, 0}, + {0x7790, 0x08, 0, 0}, + {0x7791, 0xee, 0, 0}, + {0x7792, 0x0f, 0, 0}, + {0x7793, 0x00, 0, 0}, + {0x7794, 0x05, 0, 0}, + {0x7795, 0x33, 0, 0}, + {0x7796, 0x04, 0, 0}, + {0x7797, 0xe5, 0, 0}, + {0x7798, 0x06, 0, 0}, + {0x7799, 0x52, 0, 0}, + {0x779a, 0x04, 0, 0}, + {0x779b, 0xe4, 0, 0}, + {0x779c, 0x00, 0, 0}, + {0x779d, 0x00, 0, 0}, + {0x779e, 0x06, 0, 0}, + {0x779f, 0x5e, 0, 0}, + {0x77a0, 0x00, 0, 0}, + {0x77a1, 0x0f, 0, 0}, + {0x77a2, 0x06, 0, 0}, + {0x77a3, 0x1e, 0, 0}, + {0x77a4, 0x00, 0, 0}, + {0x77a5, 0x02, 0, 0}, + {0x77a6, 0x06, 0, 0}, + {0x77a7, 0xa2, 0, 0}, + {0x77a8, 0x00, 0, 0}, + {0x77a9, 0x01, 0, 0}, + {0x77aa, 0x06, 0, 0}, + {0x77ab, 0xae, 0, 0}, + {0x77ac, 0x00, 0, 0}, + {0x77ad, 0x03, 0, 0}, + {0x77ae, 0x05, 0, 0}, + {0x77af, 0x30, 0, 0}, + {0x77b0, 0x09, 0, 0}, + {0x77b1, 0x19, 0, 0}, + {0x77b2, 0x0f, 0, 0}, + {0x77b3, 0x00, 0, 0}, + {0x77b4, 0x05, 0, 0}, + {0x77b5, 0x33, 0, 0}, + {0x77b6, 0x04, 0, 0}, + {0x77b7, 0xe5, 0, 0}, + {0x77b8, 0x06, 0, 0}, + {0x77b9, 0x52, 0, 0}, + {0x77ba, 0x04, 0, 0}, + {0x77bb, 0xe4, 0, 0}, + {0x77bc, 0x00, 0, 0}, + {0x77bd, 0x00, 0, 0}, + {0x77be, 0x06, 0, 0}, + {0x77bf, 0x5e, 0, 0}, + {0x77c0, 0x00, 0, 0}, + {0x77c1, 0x0f, 0, 0}, + {0x77c2, 0x06, 0, 0}, + {0x77c3, 0x1e, 0, 0}, + {0x77c4, 0x00, 0, 0}, + {0x77c5, 0x02, 0, 0}, + {0x77c6, 0x06, 0, 0}, + {0x77c7, 0xa2, 0, 0}, + {0x77c8, 0x00, 0, 0}, + {0x77c9, 0x01, 0, 0}, + {0x77ca, 0x06, 0, 0}, + {0x77cb, 0xae, 0, 0}, + {0x77cc, 0x00, 0, 0}, + {0x77cd, 0x03, 0, 0}, + {0x77ce, 0x05, 0, 0}, + {0x77cf, 0x30, 0, 0}, + {0x77d0, 0x0f, 0, 0}, + {0x77d1, 0x00, 0, 0}, + {0x77d2, 0x00, 0, 0}, + {0x77d3, 0x00, 0, 0}, + {0x77d4, 0x00, 0, 0}, + {0x77d5, 0x02, 0, 0}, + {0x77d6, 0x04, 0, 0}, + {0x77d7, 0xe5, 0, 0}, + {0x77d8, 0x04, 0, 0}, + {0x77d9, 0xe4, 0, 0}, + {0x77da, 0x05, 0, 0}, + {0x77db, 0x33, 0, 0}, + {0x77dc, 0x07, 0, 0}, + {0x77dd, 0x10, 0, 0}, + {0x77de, 0x00, 0, 0}, + {0x77df, 0x00, 0, 0}, + {0x77e0, 0x01, 0, 0}, + {0x77e1, 0xbb, 0, 0}, + {0x77e2, 0x00, 0, 0}, + {0x77e3, 0x00, 0, 0}, + {0x77e4, 0x01, 0, 0}, + {0x77e5, 0xaa, 0, 0}, + {0x77e6, 0x00, 0, 0}, + {0x77e7, 0x00, 0, 0}, + {0x77e8, 0x01, 0, 0}, + {0x77e9, 0x99, 0, 0}, + {0x77ea, 0x00, 0, 0}, + {0x77eb, 0x00, 0, 0}, + {0x77ec, 0x01, 0, 0}, + {0x77ed, 0x88, 0, 0}, + {0x77ee, 0x00, 0, 0}, + {0x77ef, 0x00, 0, 0}, + {0x77f0, 0x01, 0, 0}, + {0x77f1, 0x77, 0, 0}, + {0x77f2, 0x00, 0, 0}, + {0x77f3, 0x00, 0, 0}, + {0x77f4, 0x01, 0, 0}, + {0x77f5, 0x66, 0, 0}, + {0x77f6, 0x00, 0, 0}, + {0x77f7, 0x00, 0, 0}, + {0x77f8, 0x01, 0, 0}, + {0x77f9, 0x55, 0, 0}, + {0x77fa, 0x00, 0, 0}, + {0x77fb, 0x00, 0, 0}, + {0x77fc, 0x01, 0, 0}, + {0x77fd, 0x44, 0, 0}, + {0x77fe, 0x00, 0, 0}, + {0x77ff, 0x00, 0, 0}, + {0x7800, 0x01, 0, 0}, + {0x7801, 0x33, 0, 0}, + {0x7802, 0x00, 0, 0}, + {0x7803, 0x00, 0, 0}, + {0x7804, 0x01, 0, 0}, + {0x7805, 0x22, 0, 0}, + {0x7806, 0x00, 0, 0}, + {0x7807, 0x00, 0, 0}, + {0x7808, 0x01, 0, 0}, + {0x7809, 0x11, 0, 0}, + {0x780a, 0x00, 0, 0}, + {0x780b, 0x00, 0, 0}, + {0x780c, 0x01, 0, 0}, + {0x780d, 0x00, 0, 0}, + {0x780e, 0x01, 0, 0}, + {0x780f, 0xff, 0, 0}, + {0x7810, 0x07, 0, 0}, + {0x7811, 0x00, 0, 0}, + {0x7812, 0x02, 0, 0}, + {0x7813, 0xa0, 0, 0}, + {0x7814, 0x0f, 0, 0}, + {0x7815, 0x00, 0, 0}, + {0x7816, 0x08, 0, 0}, + {0x7817, 0x35, 0, 0}, + {0x7818, 0x06, 0, 0}, + {0x7819, 0x52, 0, 0}, + {0x781a, 0x04, 0, 0}, + {0x781b, 0xe4, 0, 0}, + {0x781c, 0x00, 0, 0}, + {0x781d, 0x00, 0, 0}, + {0x781e, 0x06, 0, 0}, + {0x781f, 0x5e, 0, 0}, + {0x7820, 0x05, 0, 0}, + {0x7821, 0x33, 0, 0}, + {0x7822, 0x09, 0, 0}, + {0x7823, 0x19, 0, 0}, + {0x7824, 0x06, 0, 0}, + {0x7825, 0x1e, 0, 0}, + {0x7826, 0x05, 0, 0}, + {0x7827, 0x33, 0, 0}, + {0x7828, 0x00, 0, 0}, + {0x7829, 0x01, 0, 0}, + {0x782a, 0x06, 0, 0}, + {0x782b, 0x24, 0, 0}, + {0x782c, 0x06, 0, 0}, + {0x782d, 0x20, 0, 0}, + {0x782e, 0x0f, 0, 0}, + {0x782f, 0x00, 0, 0}, + {0x7830, 0x08, 0, 0}, + {0x7831, 0x35, 0, 0}, + {0x7832, 0x07, 0, 0}, + {0x7833, 0x10, 0, 0}, + {0x7834, 0x00, 0, 0}, + {0x7835, 0x00, 0, 0}, + {0x7836, 0x01, 0, 0}, + {0x7837, 0xbb, 0, 0}, + {0x7838, 0x00, 0, 0}, + {0x7839, 0x00, 0, 0}, + {0x783a, 0x01, 0, 0}, + {0x783b, 0xaa, 0, 0}, + {0x783c, 0x00, 0, 0}, + {0x783d, 0x00, 0, 0}, + {0x783e, 0x01, 0, 0}, + {0x783f, 0x99, 0, 0}, + {0x7840, 0x00, 0, 0}, + {0x7841, 0x00, 0, 0}, + {0x7842, 0x01, 0, 0}, + {0x7843, 0x88, 0, 0}, + {0x7844, 0x00, 0, 0}, + {0x7845, 0x00, 0, 0}, + {0x7846, 0x01, 0, 0}, + {0x7847, 0x77, 0, 0}, + {0x7848, 0x00, 0, 0}, + {0x7849, 0x00, 0, 0}, + {0x784a, 0x01, 0, 0}, + {0x784b, 0x66, 0, 0}, + {0x784c, 0x00, 0, 0}, + {0x784d, 0x00, 0, 0}, + {0x784e, 0x01, 0, 0}, + {0x784f, 0x55, 0, 0}, + {0x7850, 0x00, 0, 0}, + {0x7851, 0x00, 0, 0}, + {0x7852, 0x01, 0, 0}, + {0x7853, 0x44, 0, 0}, + {0x7854, 0x00, 0, 0}, + {0x7855, 0x00, 0, 0}, + {0x7856, 0x01, 0, 0}, + {0x7857, 0x33, 0, 0}, + {0x7858, 0x00, 0, 0}, + {0x7859, 0x00, 0, 0}, + {0x785a, 0x01, 0, 0}, + {0x785b, 0x22, 0, 0}, + {0x785c, 0x00, 0, 0}, + {0x785d, 0x00, 0, 0}, + {0x785e, 0x01, 0, 0}, + {0x785f, 0x11, 0, 0}, + {0x7860, 0x00, 0, 0}, + {0x7861, 0x00, 0, 0}, + {0x7862, 0x01, 0, 0}, + {0x7863, 0x00, 0, 0}, + {0x7864, 0x07, 0, 0}, + {0x7865, 0x00, 0, 0}, + {0x7866, 0x01, 0, 0}, + {0x7867, 0xff, 0, 0}, + {0x7868, 0x02, 0, 0}, + {0x7869, 0xa0, 0, 0}, + {0x786a, 0x0f, 0, 0}, + {0x786b, 0x00, 0, 0}, + {0x786c, 0x08, 0, 0}, + {0x786d, 0x3a, 0, 0}, + {0x786e, 0x08, 0, 0}, + {0x786f, 0x6a, 0, 0}, + {0x7870, 0x0f, 0, 0}, + {0x7871, 0x00, 0, 0}, + {0x7872, 0x04, 0, 0}, + {0x7873, 0xc0, 0, 0}, + {0x7874, 0x09, 0, 0}, + {0x7875, 0x19, 0, 0}, + {0x7876, 0x04, 0, 0}, + {0x7877, 0x99, 0, 0}, + {0x7878, 0x07, 0, 0}, + {0x7879, 0x14, 0, 0}, + {0x787a, 0x00, 0, 0}, + {0x787b, 0x01, 0, 0}, + {0x787c, 0x04, 0, 0}, + {0x787d, 0xa4, 0, 0}, + {0x787e, 0x00, 0, 0}, + {0x787f, 0x07, 0, 0}, + {0x7880, 0x04, 0, 0}, + {0x7881, 0xa6, 0, 0}, + {0x7882, 0x00, 0, 0}, + {0x7883, 0x00, 0, 0}, + {0x7884, 0x04, 0, 0}, + {0x7885, 0xa0, 0, 0}, + {0x7886, 0x04, 0, 0}, + {0x7887, 0x80, 0, 0}, + {0x7888, 0x04, 0, 0}, + {0x7889, 0x00, 0, 0}, + {0x788a, 0x05, 0, 0}, + {0x788b, 0x03, 0, 0}, + {0x788c, 0x06, 0, 0}, + {0x788d, 0x00, 0, 0}, + {0x788e, 0x0f, 0, 0}, + {0x788f, 0x00, 0, 0}, + {0x7890, 0x0f, 0, 0}, + {0x7891, 0x00, 0, 0}, + {0x7892, 0x0f, 0, 0}, + {0x7893, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x05, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x04, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x80, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x38, 0, 0}, + {0x30b0, 0x0c, 0, 0},//dde + {0x30b1, 0x1c, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x66, 0, 0}, + {0x30b6, 0x01, 0, 0}, + {0x30b7, 0x22, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x20, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x0a, 0, 0}, + {0x3195, 0x2e, 0, 0}, + {0x30bb, 0x14, 0, 0}, + {0x315a, 0x02, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x80, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x80, 0, 0}, + {0x3250, 0xf7, 0, 0}, + {0x3012, 0x00, 0, 0}, + + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x08, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x08, 0, 0}, + + {0x30c0, 0x08, 0, 0}, + {0x3252, 0x20, 0, 0}, +}; + +#endif diff --git a/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p_native_hdr.h b/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p_native_hdr.h new file mode 100755 index 0000000..054878c --- /dev/null +++ b/vvcam/v4l2/sensor/ov2775/ov2775_regs_1080p_native_hdr.h @@ -0,0 +1,1915 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OV2775_REGS_1080P_NATIVE_HDR_H_ +#define _VVCAM_OV2775_REGS_1080P_NATIVE_HDR_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t ov2775_1080p_native_hdr_regs[] = { + {0x3000, 0x02, 0, 0}, + {0x3001, 0x28, 0, 0}, + {0x3002, 0x03, 0, 0}, + {0x3003, 0x01, 0, 0}, + {0x3004, 0x02, 0, 0}, + {0x3005, 0x20, 0, 0},//816Mbps //{0x3005, 0x26, 0, 0},//960Mbps + {0x3006, 0x00, 0, 0}, + {0x3007, 0x07, 0, 0},//102MHz + {0x3008, 0x01, 0, 0}, + {0x3009, 0x00, 0, 0}, + {0x300c, 0x6c, 0, 0}, + {0x300e, 0x80, 0, 0}, + {0x300f, 0x00, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3013, 0x00, 0, 0}, + {0x3014, 0xc4, 0, 0}, + {0x3015, 0x00, 0, 0}, + {0x3017, 0x00, 0, 0}, + {0x3018, 0x00, 0, 0}, + {0x3019, 0x00, 0, 0}, + {0x301a, 0x00, 0, 0}, + {0x301b, 0x0e, 0, 0}, + {0x301e, 0x17, 0, 0}, + {0x301f, 0xe1, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x3031, 0x62, 0, 0}, + {0x3032, 0xf0, 0, 0}, + {0x3033, 0x30, 0, 0}, + {0x3034, 0x3f, 0, 0}, + {0x3035, 0x5f, 0, 0}, + {0x3036, 0x02, 0, 0}, + {0x3037, 0x9f, 0, 0}, + {0x3038, 0x04, 0, 0}, + {0x3039, 0xb7, 0, 0}, + {0x303a, 0x04, 0, 0}, + {0x303b, 0x07, 0, 0}, + {0x303c, 0xf0, 0, 0}, + {0x303d, 0x00, 0, 0}, + {0x303e, 0x0b, 0, 0}, + {0x303f, 0xe3, 0, 0}, + {0x3040, 0xf3, 0, 0}, + {0x3041, 0x29, 0, 0}, + {0x3042, 0xf6, 0, 0}, + {0x3043, 0x65, 0, 0}, + {0x3044, 0x06, 0, 0}, + {0x3045, 0x0f, 0, 0}, + {0x3046, 0x59, 0, 0}, + {0x3047, 0x07, 0, 0}, + {0x3048, 0x82, 0, 0}, + {0x3049, 0xcf, 0, 0}, + {0x304a, 0x12, 0, 0}, + {0x304b, 0x40, 0, 0}, + {0x304c, 0x33, 0, 0}, + {0x304d, 0xa4, 0, 0}, + {0x304e, 0x0b, 0, 0}, + {0x304f, 0x3d, 0, 0}, + {0x3050, 0x10, 0, 0}, + {0x3060, 0x00, 0, 0}, + {0x3061, 0x64, 0, 0}, + {0x3062, 0x00, 0, 0}, + {0x3063, 0xe4, 0, 0}, + {0x3066, 0x80, 0, 0}, + {0x3080, 0x00, 0, 0}, + {0x3081, 0x00, 0, 0}, + {0x3082, 0x01, 0, 0}, + {0x3083, 0xe3, 0, 0}, + {0x3084, 0x06, 0, 0}, + {0x3085, 0x00, 0, 0}, + {0x3086, 0x10, 0, 0}, + {0x3087, 0x10, 0, 0}, + {0x3089, 0x00, 0, 0}, + {0x308a, 0x01, 0, 0}, + {0x3093, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x00, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x00, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x90, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x48, 0, 0}, + {0x30b0, 0x08, 0, 0}, + {0x30b1, 0xae, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x65, 0, 0}, + {0x30b4, 0x00, 0, 0}, + {0x30b5, 0x00, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x10, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x02, 0, 0}, + {0x30ba, 0x10, 0, 0}, + {0x30bb, 0x00, 0, 0}, + {0x30bc, 0x00, 0, 0}, + {0x30bd, 0x03, 0, 0}, + {0x30be, 0x5c, 0, 0}, + {0x30bf, 0x00, 0, 0}, + {0x30c0, 0x05, 0, 0}, + {0x30c1, 0x00, 0, 0}, + {0x30c2, 0x20, 0, 0}, + {0x30c3, 0x00, 0, 0}, + {0x30c4, 0x4a, 0, 0}, + {0x30c5, 0x00, 0, 0}, + {0x30c7, 0x00, 0, 0}, + {0x30c8, 0x00, 0, 0}, + {0x30d1, 0x00, 0, 0}, + {0x30d2, 0x00, 0, 0}, + {0x30d3, 0x80, 0, 0}, + {0x30d4, 0x00, 0, 0}, + {0x30d9, 0x09, 0, 0}, + {0x30da, 0x64, 0, 0}, + {0x30dd, 0x00, 0, 0}, + {0x30de, 0x16, 0, 0}, + {0x30df, 0x00, 0, 0}, + {0x30e0, 0x17, 0, 0}, + {0x30e1, 0x00, 0, 0}, + {0x30e2, 0x18, 0, 0}, + {0x30e3, 0x10, 0, 0}, + {0x30e4, 0x04, 0, 0}, + {0x30e5, 0x00, 0, 0}, + {0x30e6, 0x00, 0, 0}, + {0x30e7, 0x00, 0, 0}, + {0x30e8, 0x00, 0, 0}, + {0x30e9, 0x00, 0, 0}, + {0x30ea, 0x00, 0, 0}, + {0x30eb, 0x00, 0, 0}, + {0x30ec, 0x00, 0, 0}, + {0x30ed, 0x00, 0, 0}, + {0x3101, 0x00, 0, 0}, + {0x3102, 0x00, 0, 0}, + {0x3103, 0x00, 0, 0}, + {0x3104, 0x00, 0, 0}, + {0x3105, 0x8c, 0, 0}, + {0x3106, 0x87, 0, 0}, + {0x3107, 0xc0, 0, 0}, + {0x3108, 0x9d, 0, 0}, + {0x3109, 0x8d, 0, 0}, + {0x310a, 0x8d, 0, 0}, + {0x310b, 0x6a, 0, 0}, + {0x310c, 0x3a, 0, 0}, + {0x310d, 0x5a, 0, 0}, + {0x310e, 0x00, 0, 0}, + {0x3120, 0x00, 0, 0}, + {0x3121, 0x00, 0, 0}, + {0x3122, 0x00, 0, 0}, + {0x3123, 0x00, 0, 0}, + {0x3124, 0x00, 0, 0}, + {0x3125, 0x70, 0, 0}, + {0x3126, 0x1f, 0, 0}, + {0x3127, 0x0f, 0, 0}, + {0x3128, 0x00, 0, 0}, + {0x3129, 0x3a, 0, 0}, + {0x312a, 0x02, 0, 0}, + {0x312b, 0x0f, 0, 0}, + {0x312c, 0x00, 0, 0}, + {0x312d, 0x0f, 0, 0}, + {0x312e, 0x1d, 0, 0}, + {0x312f, 0x00, 0, 0}, + {0x3130, 0x00, 0, 0}, + {0x3131, 0x00, 0, 0}, + {0x3132, 0x00, 0, 0}, + {0x3140, 0x0a, 0, 0}, + {0x3141, 0x03, 0, 0}, + {0x3142, 0x00, 0, 0}, + {0x3143, 0x00, 0, 0}, + {0x3144, 0x00, 0, 0}, + {0x3145, 0x00, 0, 0}, + {0x3146, 0x00, 0, 0}, + {0x3147, 0x00, 0, 0}, + {0x3148, 0x00, 0, 0}, + {0x3149, 0x00, 0, 0}, + {0x314a, 0x00, 0, 0}, + {0x314b, 0x00, 0, 0}, + {0x314c, 0x00, 0, 0}, + {0x314d, 0x00, 0, 0}, + {0x314e, 0x1c, 0, 0}, + {0x314f, 0xff, 0, 0}, + {0x3150, 0xff, 0, 0}, + {0x3151, 0xff, 0, 0}, + {0x3152, 0x10, 0, 0}, + {0x3153, 0x10, 0, 0}, + {0x3154, 0x10, 0, 0}, + {0x3155, 0x00, 0, 0}, + {0x3156, 0x03, 0, 0}, + {0x3157, 0x00, 0, 0}, + {0x3158, 0x0f, 0, 0}, + {0x3159, 0xff, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x00, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x00, 0, 0}, + {0x3160, 0x00, 0, 0}, + {0x3161, 0x40, 0, 0}, + {0x3162, 0x00, 0, 0}, + {0x3163, 0x40, 0, 0}, + {0x3164, 0x00, 0, 0}, + {0x3165, 0x40, 0, 0}, + {0x3190, 0x02, 0, 0}, + {0x3191, 0x99, 0, 0}, + {0x3193, 0x08, 0, 0}, + {0x3194, 0x13, 0, 0}, + {0x3195, 0x33, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x10, 0, 0}, + {0x3198, 0x00, 0, 0}, + {0x3199, 0x7f, 0, 0}, + {0x319a, 0x00, 0, 0}, + {0x319b, 0x00, 0, 0}, + {0x319c, 0x80, 0, 0}, + {0x319d, 0xbf, 0, 0}, + {0x319e, 0xc0, 0, 0}, + {0x319f, 0xff, 0, 0}, + {0x31a0, 0x24, 0, 0}, + {0x31a1, 0x55, 0, 0}, + {0x31a2, 0x00, 0, 0}, + {0x31a3, 0x00, 0, 0}, + {0x31a6, 0x00, 0, 0}, + {0x31a7, 0x00, 0, 0}, + {0x31b0, 0x00, 0, 0}, + {0x31b1, 0x00, 0, 0}, + {0x31b2, 0x02, 0, 0}, + {0x31b3, 0x00, 0, 0}, + {0x31b4, 0x00, 0, 0}, + {0x31b5, 0x01, 0, 0}, + {0x31b6, 0x00, 0, 0}, + {0x31b7, 0x00, 0, 0}, + {0x31b8, 0x00, 0, 0}, + {0x31b9, 0x00, 0, 0}, + {0x31ba, 0x00, 0, 0}, + {0x31d0, 0x3c, 0, 0}, + {0x31d1, 0x34, 0, 0}, + {0x31d2, 0x3c, 0, 0}, + {0x31d3, 0x00, 0, 0}, + {0x31d4, 0x2d, 0, 0}, + {0x31d5, 0x00, 0, 0}, + {0x31d6, 0x01, 0, 0}, + {0x31d7, 0x06, 0, 0}, + {0x31d8, 0x00, 0, 0}, + {0x31d9, 0x64, 0, 0}, + {0x31da, 0x00, 0, 0}, + {0x31db, 0x30, 0, 0}, + {0x31dc, 0x04, 0, 0}, + {0x31dd, 0x69, 0, 0}, + {0x31de, 0x0a, 0, 0}, + {0x31df, 0x3c, 0, 0}, + {0x31e0, 0x04, 0, 0}, + {0x31e1, 0x32, 0, 0}, + {0x31e2, 0x00, 0, 0}, + {0x31e3, 0x00, 0, 0}, + {0x31e4, 0x08, 0, 0}, + {0x31e5, 0x80, 0, 0}, + {0x31e6, 0x00, 0, 0}, + {0x31e7, 0x2c, 0, 0}, + {0x31e8, 0x6c, 0, 0}, + {0x31e9, 0xac, 0, 0}, + {0x31ea, 0xec, 0, 0}, + {0x31eb, 0x3f, 0, 0}, + {0x31ec, 0x07, 0, 0}, + {0x31ed, 0x80, 0, 0}, + {0x31ee, 0x04, 0, 0}, + {0x31ef, 0x38, 0, 0}, + {0x31f0, 0x07, 0, 0}, + {0x31f1, 0x80, 0, 0}, + {0x31f2, 0x04, 0, 0}, + {0x31f3, 0x38, 0, 0}, + {0x31f4, 0x07, 0, 0}, + {0x31f5, 0x80, 0, 0}, + {0x31f6, 0x04, 0, 0}, + {0x31f7, 0x38, 0, 0}, + {0x31f8, 0x07, 0, 0}, + {0x31f9, 0x80, 0, 0}, + {0x31fa, 0x04, 0, 0}, + {0x31fb, 0x38, 0, 0}, + {0x31fd, 0xcb, 0, 0}, + {0x31fe, 0x0f, 0, 0}, + {0x31ff, 0x03, 0, 0}, + {0x3200, 0x00, 0, 0}, + {0x3201, 0xff, 0, 0}, + {0x3202, 0x00, 0, 0}, + {0x3203, 0xff, 0, 0}, + {0x3204, 0xff, 0, 0}, + {0x3205, 0xff, 0, 0}, + {0x3206, 0xff, 0, 0}, + {0x3207, 0xff, 0, 0}, + {0x3208, 0xff, 0, 0}, + {0x3209, 0xff, 0, 0}, + {0x320a, 0xff, 0, 0}, + {0x320b, 0x1b, 0, 0}, + {0x320c, 0x1f, 0, 0}, + {0x320d, 0x1e, 0, 0}, + {0x320e, 0x30, 0, 0}, + {0x320f, 0x2d, 0, 0}, + {0x3210, 0x2c, 0, 0}, + {0x3211, 0x2b, 0, 0}, + {0x3212, 0x2a, 0, 0}, + {0x3213, 0x24, 0, 0}, + {0x3214, 0x22, 0, 0}, + {0x3215, 0x00, 0, 0}, + {0x3216, 0x04, 0, 0}, + {0x3217, 0x2c, 0, 0}, + {0x3218, 0x6c, 0, 0}, + {0x3219, 0xac, 0, 0}, + {0x321a, 0xec, 0, 0}, + {0x321b, 0x00, 0, 0}, + {0x3230, 0x3a, 0, 0}, + {0x3231, 0x00, 0, 0}, + {0x3232, 0x80, 0, 0}, + {0x3233, 0x00, 0, 0}, + {0x3234, 0x10, 0, 0}, + {0x3235, 0xaa, 0, 0}, + {0x3236, 0x55, 0, 0}, + {0x3237, 0x99, 0, 0}, + {0x3238, 0x66, 0, 0}, + {0x3239, 0x08, 0, 0}, + {0x323a, 0x88, 0, 0}, + {0x323b, 0x00, 0, 0}, + {0x323c, 0x00, 0, 0}, + {0x323d, 0x03, 0, 0}, + {0x3250, 0x33, 0, 0}, + {0x3251, 0x00, 0, 0}, + {0x3252, 0x20, 0, 0}, + {0x3253, 0x00, 0, 0}, + {0x3254, 0x11, 0, 0}, + {0x3255, 0x01, 0, 0}, + {0x3256, 0x00, 0, 0}, + {0x3257, 0x00, 0, 0}, + {0x3258, 0x00, 0, 0}, + {0x3270, 0x01, 0, 0}, + {0x3271, 0x60, 0, 0}, + {0x3272, 0xc0, 0, 0}, + {0x3273, 0x00, 0, 0}, + {0x3274, 0x80, 0, 0}, + {0x3275, 0x40, 0, 0}, + {0x3276, 0x02, 0, 0}, + {0x3277, 0x08, 0, 0}, + {0x3278, 0x10, 0, 0}, + {0x3279, 0x04, 0, 0}, + {0x327a, 0x00, 0, 0}, + {0x327b, 0x03, 0, 0}, + {0x327c, 0x10, 0, 0}, + {0x327d, 0x60, 0, 0}, + {0x327e, 0xc0, 0, 0}, + {0x327f, 0x06, 0, 0}, + {0x3288, 0x10, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x08, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x04, 0, 0}, + {0x328d, 0x00, 0, 0}, + {0x328e, 0x02, 0, 0}, + {0x328f, 0x00, 0, 0}, + {0x3290, 0x20, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x10, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x08, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x04, 0, 0}, + {0x3297, 0x00, 0, 0}, + {0x3298, 0x40, 0, 0}, + {0x3299, 0x00, 0, 0}, + {0x329a, 0x20, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x10, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x08, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x40, 0, 0}, + {0x32a3, 0x00, 0, 0}, + {0x32a4, 0x20, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x10, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32a8, 0x00, 0, 0}, + {0x32a9, 0x00, 0, 0}, + {0x32aa, 0x00, 0, 0}, + {0x32ab, 0x00, 0, 0}, + {0x32ac, 0x00, 0, 0}, + {0x32ad, 0x00, 0, 0}, + {0x32ae, 0x00, 0, 0}, + {0x32af, 0x00, 0, 0}, + {0x32b0, 0x00, 0, 0}, + {0x32b1, 0x00, 0, 0}, + {0x32b2, 0x00, 0, 0}, + {0x32b3, 0x00, 0, 0}, + {0x32b4, 0x00, 0, 0}, + {0x32b5, 0x00, 0, 0}, + {0x32b6, 0x00, 0, 0}, + {0x32b7, 0x00, 0, 0}, + {0x32b8, 0x00, 0, 0}, + {0x32b9, 0x00, 0, 0}, + {0x32ba, 0x00, 0, 0}, + {0x32bb, 0x00, 0, 0}, + {0x32bc, 0x00, 0, 0}, + {0x32bd, 0x00, 0, 0}, + {0x32be, 0x00, 0, 0}, + {0x32bf, 0x00, 0, 0}, + {0x32c0, 0x00, 0, 0}, + {0x32c1, 0x00, 0, 0}, + {0x32c2, 0x00, 0, 0}, + {0x32c3, 0x00, 0, 0}, + {0x32c4, 0x00, 0, 0}, + {0x32c5, 0x00, 0, 0}, + {0x32c6, 0x00, 0, 0}, + {0x32c7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x32c9, 0x00, 0, 0}, + {0x3330, 0x03, 0, 0}, + {0x3331, 0xc8, 0, 0}, + {0x3332, 0x02, 0, 0}, + {0x3333, 0x24, 0, 0}, + {0x3334, 0x00, 0, 0}, + {0x3335, 0x00, 0, 0}, + {0x3336, 0x00, 0, 0}, + {0x3337, 0x00, 0, 0}, + {0x3338, 0x03, 0, 0}, + {0x3339, 0xc8, 0, 0}, + {0x333a, 0x02, 0, 0}, + {0x333b, 0x24, 0, 0}, + {0x333c, 0x00, 0, 0}, + {0x333d, 0x00, 0, 0}, + {0x333e, 0x00, 0, 0}, + {0x333f, 0x00, 0, 0}, + {0x3340, 0x03, 0, 0}, + {0x3341, 0xc8, 0, 0}, + {0x3342, 0x02, 0, 0}, + {0x3343, 0x24, 0, 0}, + {0x3344, 0x00, 0, 0}, + {0x3345, 0x00, 0, 0}, + {0x3346, 0x00, 0, 0}, + {0x3347, 0x00, 0, 0}, + {0x3348, 0x40, 0, 0}, + {0x3349, 0x00, 0, 0}, + {0x334a, 0x00, 0, 0}, + {0x334b, 0x00, 0, 0}, + {0x334c, 0x00, 0, 0}, + {0x334d, 0x00, 0, 0}, + {0x334e, 0x80, 0, 0}, + {0x3360, 0x01, 0, 0}, + {0x3361, 0xf9, 0, 0}, + {0x3362, 0x01, 0, 0}, + {0x3363, 0x04, 0, 0}, + {0x3364, 0x01, 0, 0}, + {0x3365, 0x04, 0, 0}, + {0x3366, 0x02, 0, 0}, + {0x3367, 0x3e, 0, 0}, + {0x3368, 0x01, 0, 0}, + {0x3369, 0xf9, 0, 0}, + {0x336a, 0x01, 0, 0}, + {0x336b, 0x04, 0, 0}, + {0x336c, 0x01, 0, 0}, + {0x336d, 0x04, 0, 0}, + {0x336e, 0x02, 0, 0}, + {0x336f, 0x3e, 0, 0}, + {0x3370, 0x01, 0, 0}, + {0x3371, 0xf9, 0, 0}, + {0x3372, 0x01, 0, 0}, + {0x3373, 0x04, 0, 0}, + {0x3374, 0x01, 0, 0}, + {0x3375, 0x04, 0, 0}, + {0x3376, 0x02, 0, 0}, + {0x3377, 0x3e, 0, 0}, + {0x3378, 0x00, 0, 0}, + {0x3379, 0x3e, 0, 0}, + {0x337a, 0x54, 0, 0}, + {0x337b, 0x00, 0, 0}, + {0x337c, 0x01, 0, 0}, + {0x337d, 0x00, 0, 0}, + {0x337e, 0x00, 0, 0}, + {0x337f, 0x01, 0, 0}, + {0x3380, 0x00, 0, 0}, + {0x3381, 0x00, 0, 0}, + {0x3382, 0x4f, 0, 0}, + {0x3383, 0x80, 0, 0}, + {0x3384, 0x00, 0, 0}, + {0x3385, 0x3e, 0, 0}, + {0x3386, 0x54, 0, 0}, + {0x3387, 0x00, 0, 0}, + {0x3388, 0x01, 0, 0}, + {0x3389, 0x00, 0, 0}, + {0x338a, 0x00, 0, 0}, + {0x338b, 0x01, 0, 0}, + {0x338c, 0x00, 0, 0}, + {0x338d, 0x00, 0, 0}, + {0x338e, 0x4f, 0, 0}, + {0x338f, 0x80, 0, 0}, + {0x3390, 0x00, 0, 0}, + {0x3391, 0x3e, 0, 0}, + {0x3392, 0x54, 0, 0}, + {0x3393, 0x00, 0, 0}, + {0x3394, 0x01, 0, 0}, + {0x3395, 0x00, 0, 0}, + {0x3396, 0x00, 0, 0}, + {0x3397, 0x01, 0, 0}, + {0x3398, 0x00, 0, 0}, + {0x3399, 0x00, 0, 0}, + {0x339a, 0x4f, 0, 0}, + {0x339b, 0x80, 0, 0}, + {0x33b0, 0x00, 0, 0}, + {0x33b1, 0x50, 0, 0}, + {0x33b2, 0x01, 0, 0}, + {0x33b3, 0xff, 0, 0}, + {0x33b4, 0xe0, 0, 0}, + {0x33b5, 0x6b, 0, 0}, + {0x33b6, 0x00, 0, 0}, + {0x33b7, 0x00, 0, 0}, + {0x33b8, 0x00, 0, 0}, + {0x33b9, 0x00, 0, 0}, + {0x33ba, 0x00, 0, 0}, + {0x33bb, 0x1f, 0, 0}, + {0x33bc, 0x01, 0, 0}, + {0x33bd, 0x01, 0, 0}, + {0x33be, 0x01, 0, 0}, + {0x33bf, 0x01, 0, 0}, + {0x33c0, 0x00, 0, 0}, + {0x33c1, 0x00, 0, 0}, + {0x33c2, 0x00, 0, 0}, + {0x33c3, 0x00, 0, 0}, + {0x33e0, 0x14, 0, 0}, + {0x33e1, 0x0f, 0, 0}, + {0x33e2, 0x04, 0, 0}, + {0x33e3, 0x02, 0, 0}, + {0x33e4, 0x01, 0, 0}, + {0x33e5, 0x01, 0, 0}, + {0x33e6, 0x00, 0, 0}, + {0x33e7, 0x04, 0, 0}, + {0x33e8, 0x0c, 0, 0}, + {0x33e9, 0x02, 0, 0}, + {0x33ea, 0x02, 0, 0}, + {0x33eb, 0x02, 0, 0}, + {0x33ec, 0x03, 0, 0}, + {0x33ed, 0x02, 0, 0}, + {0x33ee, 0x05, 0, 0}, + {0x33ef, 0x0a, 0, 0}, + {0x33f0, 0x08, 0, 0}, + {0x33f1, 0x04, 0, 0}, + {0x33f2, 0x04, 0, 0}, + {0x33f3, 0x00, 0, 0}, + {0x33f4, 0x03, 0, 0}, + {0x33f5, 0x14, 0, 0}, + {0x33f6, 0x0f, 0, 0}, + {0x33f7, 0x02, 0, 0}, + {0x33f8, 0x01, 0, 0}, + {0x33f9, 0x01, 0, 0}, + {0x33fa, 0x01, 0, 0}, + {0x33fb, 0x00, 0, 0}, + {0x33fc, 0x04, 0, 0}, + {0x33fd, 0x0c, 0, 0}, + {0x33fe, 0x02, 0, 0}, + {0x33ff, 0x02, 0, 0}, + {0x3400, 0x02, 0, 0}, + {0x3401, 0x03, 0, 0}, + {0x3402, 0x01, 0, 0}, + {0x3403, 0x02, 0, 0}, + {0x3404, 0x08, 0, 0}, + {0x3405, 0x08, 0, 0}, + {0x3406, 0x04, 0, 0}, + {0x3407, 0x04, 0, 0}, + {0x3408, 0x00, 0, 0}, + {0x3409, 0x03, 0, 0}, + {0x340a, 0x14, 0, 0}, + {0x340b, 0x0f, 0, 0}, + {0x340c, 0x04, 0, 0}, + {0x340d, 0x02, 0, 0}, + {0x340e, 0x01, 0, 0}, + {0x340f, 0x01, 0, 0}, + {0x3410, 0x00, 0, 0}, + {0x3411, 0x04, 0, 0}, + {0x3412, 0x0c, 0, 0}, + {0x3413, 0x02, 0, 0}, + {0x3414, 0x02, 0, 0}, + {0x3415, 0x02, 0, 0}, + {0x3416, 0x03, 0, 0}, + {0x3417, 0x02, 0, 0}, + {0x3418, 0x05, 0, 0}, + {0x3419, 0x0a, 0, 0}, + {0x341a, 0x08, 0, 0}, + {0x341b, 0x04, 0, 0}, + {0x341c, 0x04, 0, 0}, + {0x341d, 0x00, 0, 0}, + {0x341e, 0x03, 0, 0}, + {0x3440, 0x00, 0, 0}, + {0x3441, 0x00, 0, 0}, + {0x3442, 0x00, 0, 0}, + {0x3443, 0x00, 0, 0}, + {0x3444, 0x02, 0, 0}, + {0x3445, 0xf0, 0, 0}, + {0x3446, 0x02, 0, 0}, + {0x3447, 0x08, 0, 0}, + {0x3448, 0x00, 0, 0}, + {0x3460, 0x40, 0, 0}, + {0x3461, 0x40, 0, 0}, + {0x3462, 0x40, 0, 0}, + {0x3463, 0x40, 0, 0}, + {0x3464, 0x03, 0, 0}, + {0x3465, 0x01, 0, 0}, + {0x3466, 0x01, 0, 0}, + {0x3467, 0x02, 0, 0}, + {0x3468, 0x30, 0, 0}, + {0x3469, 0x00, 0, 0}, + {0x346a, 0x35, 0, 0}, + {0x346b, 0x00, 0, 0}, + {0x3480, 0x40, 0, 0}, + {0x3481, 0x00, 0, 0}, + {0x3482, 0x00, 0, 0}, + {0x3483, 0x00, 0, 0}, + {0x3484, 0x0d, 0, 0}, + {0x3485, 0x00, 0, 0}, + {0x3486, 0x00, 0, 0}, + {0x3487, 0x00, 0, 0}, + {0x3488, 0x00, 0, 0}, + {0x3489, 0x00, 0, 0}, + {0x348a, 0x00, 0, 0}, + {0x348b, 0x04, 0, 0}, + {0x348c, 0x00, 0, 0}, + {0x348d, 0x01, 0, 0}, + {0x348f, 0x01, 0, 0}, + {0x3030, 0x0a, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x7000, 0x58, 0, 0}, + {0x7001, 0x7a, 0, 0}, + {0x7002, 0x1a, 0, 0}, + {0x7003, 0xc1, 0, 0}, + {0x7004, 0x03, 0, 0}, + {0x7005, 0xda, 0, 0}, + {0x7006, 0xbd, 0, 0}, + {0x7007, 0x03, 0, 0}, + {0x7008, 0xbd, 0, 0}, + {0x7009, 0x06, 0, 0}, + {0x700a, 0xe6, 0, 0}, + {0x700b, 0xec, 0, 0}, + {0x700c, 0xbc, 0, 0}, + {0x700d, 0xff, 0, 0}, + {0x700e, 0xbc, 0, 0}, + {0x700f, 0x73, 0, 0}, + {0x7010, 0xda, 0, 0}, + {0x7011, 0x72, 0, 0}, + {0x7012, 0x76, 0, 0}, + {0x7013, 0xb6, 0, 0}, + {0x7014, 0xee, 0, 0}, + {0x7015, 0xcf, 0, 0}, + {0x7016, 0xac, 0, 0}, + {0x7017, 0xd0, 0, 0}, + {0x7018, 0xac, 0, 0}, + {0x7019, 0xd1, 0, 0}, + {0x701a, 0x50, 0, 0}, + {0x701b, 0xac, 0, 0}, + {0x701c, 0xd2, 0, 0}, + {0x701d, 0xbc, 0, 0}, + {0x701e, 0x2e, 0, 0}, + {0x701f, 0xb4, 0, 0}, + {0x7020, 0x00, 0, 0}, + {0x7021, 0xdc, 0, 0}, + {0x7022, 0xdf, 0, 0}, + {0x7023, 0xb0, 0, 0}, + {0x7024, 0x6e, 0, 0}, + {0x7025, 0xbd, 0, 0}, + {0x7026, 0x01, 0, 0}, + {0x7027, 0xd7, 0, 0}, + {0x7028, 0xed, 0, 0}, + {0x7029, 0xe1, 0, 0}, + {0x702a, 0x36, 0, 0}, + {0x702b, 0x30, 0, 0}, + {0x702c, 0xd3, 0, 0}, + {0x702d, 0x2e, 0, 0}, + {0x702e, 0x54, 0, 0}, + {0x702f, 0x46, 0, 0}, + {0x7030, 0xbc, 0, 0}, + {0x7031, 0x22, 0, 0}, + {0x7032, 0x66, 0, 0}, + {0x7033, 0xbc, 0, 0}, + {0x7034, 0x24, 0, 0}, + {0x7035, 0x2c, 0, 0}, + {0x7036, 0x28, 0, 0}, + {0x7037, 0xbc, 0, 0}, + {0x7038, 0x3c, 0, 0}, + {0x7039, 0xa1, 0, 0}, + {0x703a, 0xac, 0, 0}, + {0x703b, 0xd8, 0, 0}, + {0x703c, 0xd6, 0, 0}, + {0x703d, 0xb4, 0, 0}, + {0x703e, 0x04, 0, 0}, + {0x703f, 0x46, 0, 0}, + {0x7040, 0xb7, 0, 0}, + {0x7041, 0x04, 0, 0}, + {0x7042, 0xbe, 0, 0}, + {0x7043, 0x08, 0, 0}, + {0x7044, 0xc3, 0, 0}, + {0x7045, 0xd9, 0, 0}, + {0x7046, 0xad, 0, 0}, + {0x7047, 0xc3, 0, 0}, + {0x7048, 0xbc, 0, 0}, + {0x7049, 0x19, 0, 0}, + {0x704a, 0xc1, 0, 0}, + {0x704b, 0x27, 0, 0}, + {0x704c, 0xe7, 0, 0}, + {0x704d, 0x00, 0, 0}, + {0x704e, 0x50, 0, 0}, + {0x704f, 0x20, 0, 0}, + {0x7050, 0xb8, 0, 0}, + {0x7051, 0x02, 0, 0}, + {0x7052, 0xbc, 0, 0}, + {0x7053, 0x17, 0, 0}, + {0x7054, 0xdb, 0, 0}, + {0x7055, 0xc7, 0, 0}, + {0x7056, 0xb8, 0, 0}, + {0x7057, 0x00, 0, 0}, + {0x7058, 0x28, 0, 0}, + {0x7059, 0x54, 0, 0}, + {0x705a, 0xb4, 0, 0}, + {0x705b, 0x14, 0, 0}, + {0x705c, 0xab, 0, 0}, + {0x705d, 0xbe, 0, 0}, + {0x705e, 0x06, 0, 0}, + {0x705f, 0xd8, 0, 0}, + {0x7060, 0xd6, 0, 0}, + {0x7061, 0x00, 0, 0}, + {0x7062, 0xb4, 0, 0}, + {0x7063, 0xc7, 0, 0}, + {0x7064, 0x07, 0, 0}, + {0x7065, 0xb9, 0, 0}, + {0x7066, 0x05, 0, 0}, + {0x7067, 0xee, 0, 0}, + {0x7068, 0xe6, 0, 0}, + {0x7069, 0xad, 0, 0}, + {0x706a, 0xb4, 0, 0}, + {0x706b, 0x26, 0, 0}, + {0x706c, 0x19, 0, 0}, + {0x706d, 0xc1, 0, 0}, + {0x706e, 0x3a, 0, 0}, + {0x706f, 0xc3, 0, 0}, + {0x7070, 0xaf, 0, 0}, + {0x7071, 0x00, 0, 0}, + {0x7072, 0xc0, 0, 0}, + {0x7073, 0x3c, 0, 0}, + {0x7074, 0xc3, 0, 0}, + {0x7075, 0xbe, 0, 0}, + {0x7076, 0xe7, 0, 0}, + {0x7077, 0x00, 0, 0}, + {0x7078, 0x15, 0, 0}, + {0x7079, 0xc2, 0, 0}, + {0x707a, 0x40, 0, 0}, + {0x707b, 0xc3, 0, 0}, + {0x707c, 0xa4, 0, 0}, + {0x707d, 0xc0, 0, 0}, + {0x707e, 0x3c, 0, 0}, + {0x707f, 0x00, 0, 0}, + {0x7080, 0xb9, 0, 0}, + {0x7081, 0x64, 0, 0}, + {0x7082, 0x29, 0, 0}, + {0x7083, 0x00, 0, 0}, + {0x7084, 0xb8, 0, 0}, + {0x7085, 0x12, 0, 0}, + {0x7086, 0xbe, 0, 0}, + {0x7087, 0x01, 0, 0}, + {0x7088, 0xd0, 0, 0}, + {0x7089, 0xbc, 0, 0}, + {0x708a, 0x01, 0, 0}, + {0x708b, 0xac, 0, 0}, + {0x708c, 0x37, 0, 0}, + {0x708d, 0xd2, 0, 0}, + {0x708e, 0xac, 0, 0}, + {0x708f, 0x45, 0, 0}, + {0x7090, 0xad, 0, 0}, + {0x7091, 0x28, 0, 0}, + {0x7092, 0x00, 0, 0}, + {0x7093, 0xb8, 0, 0}, + {0x7094, 0x00, 0, 0}, + {0x7095, 0xbc, 0, 0}, + {0x7096, 0x01, 0, 0}, + {0x7097, 0x36, 0, 0}, + {0x7098, 0xd3, 0, 0}, + {0x7099, 0x30, 0, 0}, + {0x709a, 0x04, 0, 0}, + {0x709b, 0xe0, 0, 0}, + {0x709c, 0xd8, 0, 0}, + {0x709d, 0xb4, 0, 0}, + {0x709e, 0xe9, 0, 0}, + {0x709f, 0x00, 0, 0}, + {0x70a0, 0xbe, 0, 0}, + {0x70a1, 0x05, 0, 0}, + {0x70a2, 0x62, 0, 0}, + {0x70a3, 0x07, 0, 0}, + {0x70a4, 0xb9, 0, 0}, + {0x70a5, 0x05, 0, 0}, + {0x70a6, 0xad, 0, 0}, + {0x70a7, 0xc3, 0, 0}, + {0x70a8, 0xcf, 0, 0}, + {0x70a9, 0x00, 0, 0}, + {0x70aa, 0x15, 0, 0}, + {0x70ab, 0xc2, 0, 0}, + {0x70ac, 0x59, 0, 0}, + {0x70ad, 0xc3, 0, 0}, + {0x70ae, 0xc9, 0, 0}, + {0x70af, 0xc0, 0, 0}, + {0x70b0, 0x55, 0, 0}, + {0x70b1, 0x00, 0, 0}, + {0x70b2, 0x46, 0, 0}, + {0x70b3, 0xa1, 0, 0}, + {0x70b4, 0xb9, 0, 0}, + {0x70b5, 0x64, 0, 0}, + {0x70b6, 0x29, 0, 0}, + {0x70b7, 0x00, 0, 0}, + {0x70b8, 0xb8, 0, 0}, + {0x70b9, 0x02, 0, 0}, + {0x70ba, 0xbe, 0, 0}, + {0x70bb, 0x02, 0, 0}, + {0x70bc, 0xd0, 0, 0}, + {0x70bd, 0xdc, 0, 0}, + {0x70be, 0xac, 0, 0}, + {0x70bf, 0xbc, 0, 0}, + {0x70c0, 0x01, 0, 0}, + {0x70c1, 0x37, 0, 0}, + {0x70c2, 0xac, 0, 0}, + {0x70c3, 0xd2, 0, 0}, + {0x70c4, 0x45, 0, 0}, + {0x70c5, 0xad, 0, 0}, + {0x70c6, 0x28, 0, 0}, + {0x70c7, 0x00, 0, 0}, + {0x70c8, 0xb8, 0, 0}, + {0x70c9, 0x00, 0, 0}, + {0x70ca, 0xbc, 0, 0}, + {0x70cb, 0x01, 0, 0}, + {0x70cc, 0x36, 0, 0}, + {0x70cd, 0x30, 0, 0}, + {0x70ce, 0xe0, 0, 0}, + {0x70cf, 0xd8, 0, 0}, + {0x70d0, 0xb5, 0, 0}, + {0x70d1, 0x0b, 0, 0}, + {0x70d2, 0xd6, 0, 0}, + {0x70d3, 0xbe, 0, 0}, + {0x70d4, 0x07, 0, 0}, + {0x70d5, 0x00, 0, 0}, + {0x70d6, 0x62, 0, 0}, + {0x70d7, 0x07, 0, 0}, + {0x70d8, 0xb9, 0, 0}, + {0x70d9, 0x05, 0, 0}, + {0x70da, 0xad, 0, 0}, + {0x70db, 0xc3, 0, 0}, + {0x70dc, 0xcf, 0, 0}, + {0x70dd, 0x46, 0, 0}, + {0x70de, 0xcd, 0, 0}, + {0x70df, 0x07, 0, 0}, + {0x70e0, 0xcd, 0, 0}, + {0x70e1, 0x00, 0, 0}, + {0x70e2, 0xe3, 0, 0}, + {0x70e3, 0x18, 0, 0}, + {0x70e4, 0xc2, 0, 0}, + {0x70e5, 0xa2, 0, 0}, + {0x70e6, 0xb9, 0, 0}, + {0x70e7, 0x64, 0, 0}, + {0x70e8, 0xd1, 0, 0}, + {0x70e9, 0xdd, 0, 0}, + {0x70ea, 0xac, 0, 0}, + {0x70eb, 0xcf, 0, 0}, + {0x70ec, 0xdf, 0, 0}, + {0x70ed, 0xb5, 0, 0}, + {0x70ee, 0x19, 0, 0}, + {0x70ef, 0x46, 0, 0}, + {0x70f0, 0x50, 0, 0}, + {0x70f1, 0xb6, 0, 0}, + {0x70f2, 0xee, 0, 0}, + {0x70f3, 0xe8, 0, 0}, + {0x70f4, 0xe6, 0, 0}, + {0x70f5, 0xbc, 0, 0}, + {0x70f6, 0x31, 0, 0}, + {0x70f7, 0xe1, 0, 0}, + {0x70f8, 0x36, 0, 0}, + {0x70f9, 0x30, 0, 0}, + {0x70fa, 0xd3, 0, 0}, + {0x70fb, 0x2e, 0, 0}, + {0x70fc, 0x54, 0, 0}, + {0x70fd, 0xbd, 0, 0}, + {0x70fe, 0x03, 0, 0}, + {0x70ff, 0xec, 0, 0}, + {0x7100, 0x2c, 0, 0}, + {0x7101, 0x50, 0, 0}, + {0x7102, 0x20, 0, 0}, + {0x7103, 0x04, 0, 0}, + {0x7104, 0xb8, 0, 0}, + {0x7105, 0x02, 0, 0}, + {0x7106, 0xbc, 0, 0}, + {0x7107, 0x18, 0, 0}, + {0x7108, 0xc7, 0, 0}, + {0x7109, 0xb8, 0, 0}, + {0x710a, 0x00, 0, 0}, + {0x710b, 0x28, 0, 0}, + {0x710c, 0x54, 0, 0}, + {0x710d, 0xbc, 0, 0}, + {0x710e, 0x02, 0, 0}, + {0x710f, 0xb4, 0, 0}, + {0x7110, 0xda, 0, 0}, + {0x7111, 0xbe, 0, 0}, + {0x7112, 0x04, 0, 0}, + {0x7113, 0xd6, 0, 0}, + {0x7114, 0xd8, 0, 0}, + {0x7115, 0xab, 0, 0}, + {0x7116, 0x00, 0, 0}, + {0x7117, 0x62, 0, 0}, + {0x7118, 0x07, 0, 0}, + {0x7119, 0xb9, 0, 0}, + {0x711a, 0x05, 0, 0}, + {0x711b, 0xad, 0, 0}, + {0x711c, 0xc3, 0, 0}, + {0x711d, 0xbc, 0, 0}, + {0x711e, 0xe7, 0, 0}, + {0x711f, 0xb9, 0, 0}, + {0x7120, 0x64, 0, 0}, + {0x7121, 0x29, 0, 0}, + {0x7122, 0x00, 0, 0}, + {0x7123, 0xb8, 0, 0}, + {0x7124, 0x02, 0, 0}, + {0x7125, 0xbe, 0, 0}, + {0x7126, 0x00, 0, 0}, + {0x7127, 0x45, 0, 0}, + {0x7128, 0xad, 0, 0}, + {0x7129, 0xe2, 0, 0}, + {0x712a, 0x28, 0, 0}, + {0x712b, 0x00, 0, 0}, + {0x712c, 0xb8, 0, 0}, + {0x712d, 0x00, 0, 0}, + {0x712e, 0xe0, 0, 0}, + {0x712f, 0xd8, 0, 0}, + {0x7130, 0xb4, 0, 0}, + {0x7131, 0xe9, 0, 0}, + {0x7132, 0xbe, 0, 0}, + {0x7133, 0x03, 0, 0}, + {0x7134, 0x00, 0, 0}, + {0x7135, 0x30, 0, 0}, + {0x7136, 0x62, 0, 0}, + {0x7137, 0x07, 0, 0}, + {0x7138, 0xb9, 0, 0}, + {0x7139, 0x05, 0, 0}, + {0x713a, 0xad, 0, 0}, + {0x713b, 0xc3, 0, 0}, + {0x713c, 0xcf, 0, 0}, + {0x713d, 0x42, 0, 0}, + {0x713e, 0xe4, 0, 0}, + {0x713f, 0xcd, 0, 0}, + {0x7140, 0x07, 0, 0}, + {0x7141, 0xcd, 0, 0}, + {0x7142, 0x00, 0, 0}, + {0x7143, 0x00, 0, 0}, + {0x7144, 0x17, 0, 0}, + {0x7145, 0xc2, 0, 0}, + {0x7146, 0xbb, 0, 0}, + {0x7147, 0xde, 0, 0}, + {0x7148, 0xcf, 0, 0}, + {0x7149, 0xdf, 0, 0}, + {0x714a, 0xac, 0, 0}, + {0x714b, 0xd1, 0, 0}, + {0x714c, 0x44, 0, 0}, + {0x714d, 0xac, 0, 0}, + {0x714e, 0xb9, 0, 0}, + {0x714f, 0x76, 0, 0}, + {0x7150, 0xb8, 0, 0}, + {0x7151, 0x08, 0, 0}, + {0x7152, 0xb6, 0, 0}, + {0x7153, 0xfe, 0, 0}, + {0x7154, 0xb4, 0, 0}, + {0x7155, 0xca, 0, 0}, + {0x7156, 0xd6, 0, 0}, + {0x7157, 0xd8, 0, 0}, + {0x7158, 0xab, 0, 0}, + {0x7159, 0x00, 0, 0}, + {0x715a, 0xe1, 0, 0}, + {0x715b, 0x36, 0, 0}, + {0x715c, 0x30, 0, 0}, + {0x715d, 0xd3, 0, 0}, + {0x715e, 0xbc, 0, 0}, + {0x715f, 0x29, 0, 0}, + {0x7160, 0xb4, 0, 0}, + {0x7161, 0x1f, 0, 0}, + {0x7162, 0xaa, 0, 0}, + {0x7163, 0xbd, 0, 0}, + {0x7164, 0x01, 0, 0}, + {0x7165, 0xb8, 0, 0}, + {0x7166, 0x0c, 0, 0}, + {0x7167, 0x45, 0, 0}, + {0x7168, 0xa4, 0, 0}, + {0x7169, 0xbd, 0, 0}, + {0x716a, 0x03, 0, 0}, + {0x716b, 0xec, 0, 0}, + {0x716c, 0xbc, 0, 0}, + {0x716d, 0x3d, 0, 0}, + {0x716e, 0xc3, 0, 0}, + {0x716f, 0xcf, 0, 0}, + {0x7170, 0x42, 0, 0}, + {0x7171, 0xb8, 0, 0}, + {0x7172, 0x00, 0, 0}, + {0x7173, 0xe4, 0, 0}, + {0x7174, 0xd5, 0, 0}, + {0x7175, 0x00, 0, 0}, + {0x7176, 0xb6, 0, 0}, + {0x7177, 0x00, 0, 0}, + {0x7178, 0x74, 0, 0}, + {0x7179, 0xbd, 0, 0}, + {0x717a, 0x03, 0, 0}, + {0x717b, 0xb5, 0, 0}, + {0x717c, 0x39, 0, 0}, + {0x717d, 0x40, 0, 0}, + {0x717e, 0x58, 0, 0}, + {0x717f, 0xdd, 0, 0}, + {0x7180, 0x19, 0, 0}, + {0x7181, 0xc1, 0, 0}, + {0x7182, 0xc8, 0, 0}, + {0x7183, 0xbd, 0, 0}, + {0x7184, 0x06, 0, 0}, + {0x7185, 0x17, 0, 0}, + {0x7186, 0xc1, 0, 0}, + {0x7187, 0xc6, 0, 0}, + {0x7188, 0xe8, 0, 0}, + {0x7189, 0x00, 0, 0}, + {0x718a, 0xc0, 0, 0}, + {0x718b, 0xc8, 0, 0}, + {0x718c, 0xe6, 0, 0}, + {0x718d, 0x95, 0, 0}, + {0x718e, 0x15, 0, 0}, + {0x718f, 0x00, 0, 0}, + {0x7190, 0xbc, 0, 0}, + {0x7191, 0x19, 0, 0}, + {0x7192, 0xb9, 0, 0}, + {0x7193, 0xf6, 0, 0}, + {0x7194, 0x14, 0, 0}, + {0x7195, 0xc1, 0, 0}, + {0x7196, 0xd0, 0, 0}, + {0x7197, 0xd1, 0, 0}, + {0x7198, 0xac, 0, 0}, + {0x7199, 0x37, 0, 0}, + {0x719a, 0xbc, 0, 0}, + {0x719b, 0x35, 0, 0}, + {0x719c, 0x36, 0, 0}, + {0x719d, 0x30, 0, 0}, + {0x719e, 0xe1, 0, 0}, + {0x719f, 0xd3, 0, 0}, + {0x71a0, 0x7a, 0, 0}, + {0x71a1, 0xb6, 0, 0}, + {0x71a2, 0x0c, 0, 0}, + {0x71a3, 0xff, 0, 0}, + {0x71a4, 0xb4, 0, 0}, + {0x71a5, 0xc7, 0, 0}, + {0x71a6, 0xd9, 0, 0}, + {0x71a7, 0x00, 0, 0}, + {0x71a8, 0xbd, 0, 0}, + {0x71a9, 0x01, 0, 0}, + {0x71aa, 0x56, 0, 0}, + {0x71ab, 0xc0, 0, 0}, + {0x71ac, 0xda, 0, 0}, + {0x71ad, 0xb4, 0, 0}, + {0x71ae, 0x1f, 0, 0}, + {0x71af, 0x56, 0, 0}, + {0x71b0, 0xaa, 0, 0}, + {0x71b1, 0xbc, 0, 0}, + {0x71b2, 0x08, 0, 0}, + {0x71b3, 0x00, 0, 0}, + {0x71b4, 0x57, 0, 0}, + {0x71b5, 0xe8, 0, 0}, + {0x71b6, 0xb5, 0, 0}, + {0x71b7, 0x36, 0, 0}, + {0x71b8, 0x00, 0, 0}, + {0x71b9, 0x54, 0, 0}, + {0x71ba, 0xe7, 0, 0}, + {0x71bb, 0xc8, 0, 0}, + {0x71bc, 0xb4, 0, 0}, + {0x71bd, 0x1f, 0, 0}, + {0x71be, 0x56, 0, 0}, + {0x71bf, 0xaa, 0, 0}, + {0x71c0, 0xbc, 0, 0}, + {0x71c1, 0x08, 0, 0}, + {0x71c2, 0x57, 0, 0}, + {0x71c3, 0x00, 0, 0}, + {0x71c4, 0xb5, 0, 0}, + {0x71c5, 0x36, 0, 0}, + {0x71c6, 0x00, 0, 0}, + {0x71c7, 0x54, 0, 0}, + {0x71c8, 0xc8, 0, 0}, + {0x71c9, 0xb5, 0, 0}, + {0x71ca, 0x18, 0, 0}, + {0x71cb, 0xd9, 0, 0}, + {0x71cc, 0x00, 0, 0}, + {0x71cd, 0xbd, 0, 0}, + {0x71ce, 0x01, 0, 0}, + {0x71cf, 0x56, 0, 0}, + {0x71d0, 0x08, 0, 0}, + {0x71d1, 0x57, 0, 0}, + {0x71d2, 0xe8, 0, 0}, + {0x71d3, 0xb4, 0, 0}, + {0x71d4, 0x42, 0, 0}, + {0x71d5, 0x00, 0, 0}, + {0x71d6, 0x54, 0, 0}, + {0x71d7, 0xe7, 0, 0}, + {0x71d8, 0xc8, 0, 0}, + {0x71d9, 0xab, 0, 0}, + {0x71da, 0x00, 0, 0}, + {0x71db, 0x66, 0, 0}, + {0x71dc, 0x62, 0, 0}, + {0x71dd, 0x06, 0, 0}, + {0x71de, 0x74, 0, 0}, + {0x71df, 0xb9, 0, 0}, + {0x71e0, 0x05, 0, 0}, + {0x71e1, 0xb7, 0, 0}, + {0x71e2, 0x14, 0, 0}, + {0x71e3, 0x0e, 0, 0}, + {0x71e4, 0xb7, 0, 0}, + {0x71e5, 0x04, 0, 0}, + {0x71e6, 0xc8, 0, 0}, + {0x7600, 0x04, 0, 0}, + {0x7601, 0x80, 0, 0}, + {0x7602, 0x07, 0, 0}, + {0x7603, 0x44, 0, 0}, + {0x7604, 0x05, 0, 0}, + {0x7605, 0x33, 0, 0}, + {0x7606, 0x0f, 0, 0}, + {0x7607, 0x00, 0, 0}, + {0x7608, 0x07, 0, 0}, + {0x7609, 0x40, 0, 0}, + {0x760a, 0x04, 0, 0}, + {0x760b, 0xe5, 0, 0}, + {0x760c, 0x06, 0, 0}, + {0x760d, 0x50, 0, 0}, + {0x760e, 0x04, 0, 0}, + {0x760f, 0xe4, 0, 0}, + {0x7610, 0x00, 0, 0}, + {0x7611, 0x00, 0, 0}, + {0x7612, 0x06, 0, 0}, + {0x7613, 0x5c, 0, 0}, + {0x7614, 0x00, 0, 0}, + {0x7615, 0x0f, 0, 0}, + {0x7616, 0x06, 0, 0}, + {0x7617, 0x1c, 0, 0}, + {0x7618, 0x00, 0, 0}, + {0x7619, 0x02, 0, 0}, + {0x761a, 0x06, 0, 0}, + {0x761b, 0xa2, 0, 0}, + {0x761c, 0x00, 0, 0}, + {0x761d, 0x01, 0, 0}, + {0x761e, 0x06, 0, 0}, + {0x761f, 0xae, 0, 0}, + {0x7620, 0x00, 0, 0}, + {0x7621, 0x0e, 0, 0}, + {0x7622, 0x05, 0, 0}, + {0x7623, 0x30, 0, 0}, + {0x7624, 0x07, 0, 0}, + {0x7625, 0x00, 0, 0}, + {0x7626, 0x0f, 0, 0}, + {0x7627, 0x00, 0, 0}, + {0x7628, 0x04, 0, 0}, + {0x7629, 0xe5, 0, 0}, + {0x762a, 0x05, 0, 0}, + {0x762b, 0x33, 0, 0}, + {0x762c, 0x06, 0, 0}, + {0x762d, 0x12, 0, 0}, + {0x762e, 0x00, 0, 0}, + {0x762f, 0x01, 0, 0}, + {0x7630, 0x06, 0, 0}, + {0x7631, 0x52, 0, 0}, + {0x7632, 0x00, 0, 0}, + {0x7633, 0x01, 0, 0}, + {0x7634, 0x06, 0, 0}, + {0x7635, 0x5e, 0, 0}, + {0x7636, 0x04, 0, 0}, + {0x7637, 0xe4, 0, 0}, + {0x7638, 0x00, 0, 0}, + {0x7639, 0x01, 0, 0}, + {0x763a, 0x05, 0, 0}, + {0x763b, 0x30, 0, 0}, + {0x763c, 0x0f, 0, 0}, + {0x763d, 0x00, 0, 0}, + {0x763e, 0x06, 0, 0}, + {0x763f, 0xa6, 0, 0}, + {0x7640, 0x00, 0, 0}, + {0x7641, 0x02, 0, 0}, + {0x7642, 0x06, 0, 0}, + {0x7643, 0x26, 0, 0}, + {0x7644, 0x00, 0, 0}, + {0x7645, 0x02, 0, 0}, + {0x7646, 0x05, 0, 0}, + {0x7647, 0x33, 0, 0}, + {0x7648, 0x06, 0, 0}, + {0x7649, 0x20, 0, 0}, + {0x764a, 0x0f, 0, 0}, + {0x764b, 0x00, 0, 0}, + {0x764c, 0x06, 0, 0}, + {0x764d, 0x56, 0, 0}, + {0x764e, 0x00, 0, 0}, + {0x764f, 0x02, 0, 0}, + {0x7650, 0x06, 0, 0}, + {0x7651, 0x16, 0, 0}, + {0x7652, 0x05, 0, 0}, + {0x7653, 0x33, 0, 0}, + {0x7654, 0x06, 0, 0}, + {0x7655, 0x10, 0, 0}, + {0x7656, 0x0f, 0, 0}, + {0x7657, 0x00, 0, 0}, + {0x7658, 0x06, 0, 0}, + {0x7659, 0x10, 0, 0}, + {0x765a, 0x0f, 0, 0}, + {0x765b, 0x00, 0, 0}, + {0x765c, 0x06, 0, 0}, + {0x765d, 0x20, 0, 0}, + {0x765e, 0x0f, 0, 0}, + {0x765f, 0x00, 0, 0}, + {0x7660, 0x00, 0, 0}, + {0x7661, 0x00, 0, 0}, + {0x7662, 0x00, 0, 0}, + {0x7663, 0x02, 0, 0}, + {0x7664, 0x04, 0, 0}, + {0x7665, 0xe5, 0, 0}, + {0x7666, 0x04, 0, 0}, + {0x7667, 0xe4, 0, 0}, + {0x7668, 0x0f, 0, 0}, + {0x7669, 0x00, 0, 0}, + {0x766a, 0x00, 0, 0}, + {0x766b, 0x00, 0, 0}, + {0x766c, 0x00, 0, 0}, + {0x766d, 0x01, 0, 0}, + {0x766e, 0x04, 0, 0}, + {0x766f, 0xe5, 0, 0}, + {0x7670, 0x04, 0, 0}, + {0x7671, 0xe4, 0, 0}, + {0x7672, 0x0f, 0, 0}, + {0x7673, 0x00, 0, 0}, + {0x7674, 0x00, 0, 0}, + {0x7675, 0x02, 0, 0}, + {0x7676, 0x04, 0, 0}, + {0x7677, 0xe4, 0, 0}, + {0x7678, 0x00, 0, 0}, + {0x7679, 0x02, 0, 0}, + {0x767a, 0x04, 0, 0}, + {0x767b, 0xc4, 0, 0}, + {0x767c, 0x00, 0, 0}, + {0x767d, 0x02, 0, 0}, + {0x767e, 0x04, 0, 0}, + {0x767f, 0xc4, 0, 0}, + {0x7680, 0x05, 0, 0}, + {0x7681, 0x83, 0, 0}, + {0x7682, 0x0f, 0, 0}, + {0x7683, 0x00, 0, 0}, + {0x7684, 0x00, 0, 0}, + {0x7685, 0x02, 0, 0}, + {0x7686, 0x04, 0, 0}, + {0x7687, 0xe4, 0, 0}, + {0x7688, 0x00, 0, 0}, + {0x7689, 0x02, 0, 0}, + {0x768a, 0x04, 0, 0}, + {0x768b, 0xc4, 0, 0}, + {0x768c, 0x00, 0, 0}, + {0x768d, 0x02, 0, 0}, + {0x768e, 0x04, 0, 0}, + {0x768f, 0xc4, 0, 0}, + {0x7690, 0x05, 0, 0}, + {0x7691, 0x83, 0, 0}, + {0x7692, 0x03, 0, 0}, + {0x7693, 0x0b, 0, 0}, + {0x7694, 0x05, 0, 0}, + {0x7695, 0x83, 0, 0}, + {0x7696, 0x00, 0, 0}, + {0x7697, 0x07, 0, 0}, + {0x7698, 0x05, 0, 0}, + {0x7699, 0x03, 0, 0}, + {0x769a, 0x00, 0, 0}, + {0x769b, 0x05, 0, 0}, + {0x769c, 0x05, 0, 0}, + {0x769d, 0x32, 0, 0}, + {0x769e, 0x05, 0, 0}, + {0x769f, 0x30, 0, 0}, + {0x76a0, 0x00, 0, 0}, + {0x76a1, 0x02, 0, 0}, + {0x76a2, 0x05, 0, 0}, + {0x76a3, 0x78, 0, 0}, + {0x76a4, 0x00, 0, 0}, + {0x76a5, 0x01, 0, 0}, + {0x76a6, 0x05, 0, 0}, + {0x76a7, 0x7c, 0, 0}, + {0x76a8, 0x03, 0, 0}, + {0x76a9, 0x9a, 0, 0}, + {0x76aa, 0x05, 0, 0}, + {0x76ab, 0x83, 0, 0}, + {0x76ac, 0x00, 0, 0}, + {0x76ad, 0x04, 0, 0}, + {0x76ae, 0x05, 0, 0}, + {0x76af, 0x03, 0, 0}, + {0x76b0, 0x00, 0, 0}, + {0x76b1, 0x03, 0, 0}, + {0x76b2, 0x05, 0, 0}, + {0x76b3, 0x32, 0, 0}, + {0x76b4, 0x05, 0, 0}, + {0x76b5, 0x30, 0, 0}, + {0x76b6, 0x00, 0, 0}, + {0x76b7, 0x02, 0, 0}, + {0x76b8, 0x05, 0, 0}, + {0x76b9, 0x78, 0, 0}, + {0x76ba, 0x00, 0, 0}, + {0x76bb, 0x01, 0, 0}, + {0x76bc, 0x05, 0, 0}, + {0x76bd, 0x7c, 0, 0}, + {0x76be, 0x03, 0, 0}, + {0x76bf, 0x99, 0, 0}, + {0x76c0, 0x05, 0, 0}, + {0x76c1, 0x83, 0, 0}, + {0x76c2, 0x00, 0, 0}, + {0x76c3, 0x03, 0, 0}, + {0x76c4, 0x05, 0, 0}, + {0x76c5, 0x03, 0, 0}, + {0x76c6, 0x00, 0, 0}, + {0x76c7, 0x01, 0, 0}, + {0x76c8, 0x05, 0, 0}, + {0x76c9, 0x32, 0, 0}, + {0x76ca, 0x05, 0, 0}, + {0x76cb, 0x30, 0, 0}, + {0x76cc, 0x00, 0, 0}, + {0x76cd, 0x02, 0, 0}, + {0x76ce, 0x05, 0, 0}, + {0x76cf, 0x78, 0, 0}, + {0x76d0, 0x00, 0, 0}, + {0x76d1, 0x01, 0, 0}, + {0x76d2, 0x05, 0, 0}, + {0x76d3, 0x7c, 0, 0}, + {0x76d4, 0x03, 0, 0}, + {0x76d5, 0x98, 0, 0}, + {0x76d6, 0x05, 0, 0}, + {0x76d7, 0x83, 0, 0}, + {0x76d8, 0x00, 0, 0}, + {0x76d9, 0x00, 0, 0}, + {0x76da, 0x05, 0, 0}, + {0x76db, 0x03, 0, 0}, + {0x76dc, 0x00, 0, 0}, + {0x76dd, 0x01, 0, 0}, + {0x76de, 0x05, 0, 0}, + {0x76df, 0x32, 0, 0}, + {0x76e0, 0x05, 0, 0}, + {0x76e1, 0x30, 0, 0}, + {0x76e2, 0x00, 0, 0}, + {0x76e3, 0x02, 0, 0}, + {0x76e4, 0x05, 0, 0}, + {0x76e5, 0x78, 0, 0}, + {0x76e6, 0x00, 0, 0}, + {0x76e7, 0x01, 0, 0}, + {0x76e8, 0x05, 0, 0}, + {0x76e9, 0x7c, 0, 0}, + {0x76ea, 0x03, 0, 0}, + {0x76eb, 0x97, 0, 0}, + {0x76ec, 0x05, 0, 0}, + {0x76ed, 0x83, 0, 0}, + {0x76ee, 0x00, 0, 0}, + {0x76ef, 0x00, 0, 0}, + {0x76f0, 0x05, 0, 0}, + {0x76f1, 0x03, 0, 0}, + {0x76f2, 0x05, 0, 0}, + {0x76f3, 0x32, 0, 0}, + {0x76f4, 0x05, 0, 0}, + {0x76f5, 0x30, 0, 0}, + {0x76f6, 0x00, 0, 0}, + {0x76f7, 0x02, 0, 0}, + {0x76f8, 0x05, 0, 0}, + {0x76f9, 0x78, 0, 0}, + {0x76fa, 0x00, 0, 0}, + {0x76fb, 0x01, 0, 0}, + {0x76fc, 0x05, 0, 0}, + {0x76fd, 0x7c, 0, 0}, + {0x76fe, 0x03, 0, 0}, + {0x76ff, 0x96, 0, 0}, + {0x7700, 0x05, 0, 0}, + {0x7701, 0x83, 0, 0}, + {0x7702, 0x05, 0, 0}, + {0x7703, 0x03, 0, 0}, + {0x7704, 0x05, 0, 0}, + {0x7705, 0x32, 0, 0}, + {0x7706, 0x05, 0, 0}, + {0x7707, 0x30, 0, 0}, + {0x7708, 0x00, 0, 0}, + {0x7709, 0x02, 0, 0}, + {0x770a, 0x05, 0, 0}, + {0x770b, 0x78, 0, 0}, + {0x770c, 0x00, 0, 0}, + {0x770d, 0x01, 0, 0}, + {0x770e, 0x05, 0, 0}, + {0x770f, 0x7c, 0, 0}, + {0x7710, 0x03, 0, 0}, + {0x7711, 0x95, 0, 0}, + {0x7712, 0x05, 0, 0}, + {0x7713, 0x83, 0, 0}, + {0x7714, 0x05, 0, 0}, + {0x7715, 0x03, 0, 0}, + {0x7716, 0x05, 0, 0}, + {0x7717, 0x32, 0, 0}, + {0x7718, 0x05, 0, 0}, + {0x7719, 0x30, 0, 0}, + {0x771a, 0x00, 0, 0}, + {0x771b, 0x02, 0, 0}, + {0x771c, 0x05, 0, 0}, + {0x771d, 0x78, 0, 0}, + {0x771e, 0x00, 0, 0}, + {0x771f, 0x01, 0, 0}, + {0x7720, 0x05, 0, 0}, + {0x7721, 0x7c, 0, 0}, + {0x7722, 0x03, 0, 0}, + {0x7723, 0x94, 0, 0}, + {0x7724, 0x05, 0, 0}, + {0x7725, 0x83, 0, 0}, + {0x7726, 0x00, 0, 0}, + {0x7727, 0x01, 0, 0}, + {0x7728, 0x05, 0, 0}, + {0x7729, 0x03, 0, 0}, + {0x772a, 0x00, 0, 0}, + {0x772b, 0x01, 0, 0}, + {0x772c, 0x05, 0, 0}, + {0x772d, 0x32, 0, 0}, + {0x772e, 0x05, 0, 0}, + {0x772f, 0x30, 0, 0}, + {0x7730, 0x00, 0, 0}, + {0x7731, 0x02, 0, 0}, + {0x7732, 0x05, 0, 0}, + {0x7733, 0x78, 0, 0}, + {0x7734, 0x00, 0, 0}, + {0x7735, 0x01, 0, 0}, + {0x7736, 0x05, 0, 0}, + {0x7737, 0x7c, 0, 0}, + {0x7738, 0x03, 0, 0}, + {0x7739, 0x93, 0, 0}, + {0x773a, 0x05, 0, 0}, + {0x773b, 0x83, 0, 0}, + {0x773c, 0x00, 0, 0}, + {0x773d, 0x00, 0, 0}, + {0x773e, 0x05, 0, 0}, + {0x773f, 0x03, 0, 0}, + {0x7740, 0x00, 0, 0}, + {0x7741, 0x00, 0, 0}, + {0x7742, 0x05, 0, 0}, + {0x7743, 0x32, 0, 0}, + {0x7744, 0x05, 0, 0}, + {0x7745, 0x30, 0, 0}, + {0x7746, 0x00, 0, 0}, + {0x7747, 0x02, 0, 0}, + {0x7748, 0x05, 0, 0}, + {0x7749, 0x78, 0, 0}, + {0x774a, 0x00, 0, 0}, + {0x774b, 0x01, 0, 0}, + {0x774c, 0x05, 0, 0}, + {0x774d, 0x7c, 0, 0}, + {0x774e, 0x03, 0, 0}, + {0x774f, 0x92, 0, 0}, + {0x7750, 0x05, 0, 0}, + {0x7751, 0x83, 0, 0}, + {0x7752, 0x05, 0, 0}, + {0x7753, 0x03, 0, 0}, + {0x7754, 0x00, 0, 0}, + {0x7755, 0x00, 0, 0}, + {0x7756, 0x05, 0, 0}, + {0x7757, 0x32, 0, 0}, + {0x7758, 0x05, 0, 0}, + {0x7759, 0x30, 0, 0}, + {0x775a, 0x00, 0, 0}, + {0x775b, 0x02, 0, 0}, + {0x775c, 0x05, 0, 0}, + {0x775d, 0x78, 0, 0}, + {0x775e, 0x00, 0, 0}, + {0x775f, 0x01, 0, 0}, + {0x7760, 0x05, 0, 0}, + {0x7761, 0x7c, 0, 0}, + {0x7762, 0x03, 0, 0}, + {0x7763, 0x91, 0, 0}, + {0x7764, 0x05, 0, 0}, + {0x7765, 0x83, 0, 0}, + {0x7766, 0x05, 0, 0}, + {0x7767, 0x03, 0, 0}, + {0x7768, 0x05, 0, 0}, + {0x7769, 0x32, 0, 0}, + {0x776a, 0x05, 0, 0}, + {0x776b, 0x30, 0, 0}, + {0x776c, 0x00, 0, 0}, + {0x776d, 0x02, 0, 0}, + {0x776e, 0x05, 0, 0}, + {0x776f, 0x78, 0, 0}, + {0x7770, 0x00, 0, 0}, + {0x7771, 0x01, 0, 0}, + {0x7772, 0x05, 0, 0}, + {0x7773, 0x7c, 0, 0}, + {0x7774, 0x03, 0, 0}, + {0x7775, 0x90, 0, 0}, + {0x7776, 0x05, 0, 0}, + {0x7777, 0x83, 0, 0}, + {0x7778, 0x05, 0, 0}, + {0x7779, 0x03, 0, 0}, + {0x777a, 0x05, 0, 0}, + {0x777b, 0x32, 0, 0}, + {0x777c, 0x05, 0, 0}, + {0x777d, 0x30, 0, 0}, + {0x777e, 0x00, 0, 0}, + {0x777f, 0x02, 0, 0}, + {0x7780, 0x05, 0, 0}, + {0x7781, 0x78, 0, 0}, + {0x7782, 0x00, 0, 0}, + {0x7783, 0x01, 0, 0}, + {0x7784, 0x05, 0, 0}, + {0x7785, 0x7c, 0, 0}, + {0x7786, 0x02, 0, 0}, + {0x7787, 0x90, 0, 0}, + {0x7788, 0x05, 0, 0}, + {0x7789, 0x03, 0, 0}, + {0x778a, 0x07, 0, 0}, + {0x778b, 0x00, 0, 0}, + {0x778c, 0x0f, 0, 0}, + {0x778d, 0x00, 0, 0}, + {0x778e, 0x08, 0, 0}, + {0x778f, 0x30, 0, 0}, + {0x7790, 0x08, 0, 0}, + {0x7791, 0xee, 0, 0}, + {0x7792, 0x0f, 0, 0}, + {0x7793, 0x00, 0, 0}, + {0x7794, 0x05, 0, 0}, + {0x7795, 0x33, 0, 0}, + {0x7796, 0x04, 0, 0}, + {0x7797, 0xe5, 0, 0}, + {0x7798, 0x06, 0, 0}, + {0x7799, 0x52, 0, 0}, + {0x779a, 0x04, 0, 0}, + {0x779b, 0xe4, 0, 0}, + {0x779c, 0x00, 0, 0}, + {0x779d, 0x00, 0, 0}, + {0x779e, 0x06, 0, 0}, + {0x779f, 0x5e, 0, 0}, + {0x77a0, 0x00, 0, 0}, + {0x77a1, 0x0f, 0, 0}, + {0x77a2, 0x06, 0, 0}, + {0x77a3, 0x1e, 0, 0}, + {0x77a4, 0x00, 0, 0}, + {0x77a5, 0x02, 0, 0}, + {0x77a6, 0x06, 0, 0}, + {0x77a7, 0xa2, 0, 0}, + {0x77a8, 0x00, 0, 0}, + {0x77a9, 0x01, 0, 0}, + {0x77aa, 0x06, 0, 0}, + {0x77ab, 0xae, 0, 0}, + {0x77ac, 0x00, 0, 0}, + {0x77ad, 0x03, 0, 0}, + {0x77ae, 0x05, 0, 0}, + {0x77af, 0x30, 0, 0}, + {0x77b0, 0x09, 0, 0}, + {0x77b1, 0x19, 0, 0}, + {0x77b2, 0x0f, 0, 0}, + {0x77b3, 0x00, 0, 0}, + {0x77b4, 0x05, 0, 0}, + {0x77b5, 0x33, 0, 0}, + {0x77b6, 0x04, 0, 0}, + {0x77b7, 0xe5, 0, 0}, + {0x77b8, 0x06, 0, 0}, + {0x77b9, 0x52, 0, 0}, + {0x77ba, 0x04, 0, 0}, + {0x77bb, 0xe4, 0, 0}, + {0x77bc, 0x00, 0, 0}, + {0x77bd, 0x00, 0, 0}, + {0x77be, 0x06, 0, 0}, + {0x77bf, 0x5e, 0, 0}, + {0x77c0, 0x00, 0, 0}, + {0x77c1, 0x0f, 0, 0}, + {0x77c2, 0x06, 0, 0}, + {0x77c3, 0x1e, 0, 0}, + {0x77c4, 0x00, 0, 0}, + {0x77c5, 0x02, 0, 0}, + {0x77c6, 0x06, 0, 0}, + {0x77c7, 0xa2, 0, 0}, + {0x77c8, 0x00, 0, 0}, + {0x77c9, 0x01, 0, 0}, + {0x77ca, 0x06, 0, 0}, + {0x77cb, 0xae, 0, 0}, + {0x77cc, 0x00, 0, 0}, + {0x77cd, 0x03, 0, 0}, + {0x77ce, 0x05, 0, 0}, + {0x77cf, 0x30, 0, 0}, + {0x77d0, 0x0f, 0, 0}, + {0x77d1, 0x00, 0, 0}, + {0x77d2, 0x00, 0, 0}, + {0x77d3, 0x00, 0, 0}, + {0x77d4, 0x00, 0, 0}, + {0x77d5, 0x02, 0, 0}, + {0x77d6, 0x04, 0, 0}, + {0x77d7, 0xe5, 0, 0}, + {0x77d8, 0x04, 0, 0}, + {0x77d9, 0xe4, 0, 0}, + {0x77da, 0x05, 0, 0}, + {0x77db, 0x33, 0, 0}, + {0x77dc, 0x07, 0, 0}, + {0x77dd, 0x10, 0, 0}, + {0x77de, 0x00, 0, 0}, + {0x77df, 0x00, 0, 0}, + {0x77e0, 0x01, 0, 0}, + {0x77e1, 0xbb, 0, 0}, + {0x77e2, 0x00, 0, 0}, + {0x77e3, 0x00, 0, 0}, + {0x77e4, 0x01, 0, 0}, + {0x77e5, 0xaa, 0, 0}, + {0x77e6, 0x00, 0, 0}, + {0x77e7, 0x00, 0, 0}, + {0x77e8, 0x01, 0, 0}, + {0x77e9, 0x99, 0, 0}, + {0x77ea, 0x00, 0, 0}, + {0x77eb, 0x00, 0, 0}, + {0x77ec, 0x01, 0, 0}, + {0x77ed, 0x88, 0, 0}, + {0x77ee, 0x00, 0, 0}, + {0x77ef, 0x00, 0, 0}, + {0x77f0, 0x01, 0, 0}, + {0x77f1, 0x77, 0, 0}, + {0x77f2, 0x00, 0, 0}, + {0x77f3, 0x00, 0, 0}, + {0x77f4, 0x01, 0, 0}, + {0x77f5, 0x66, 0, 0}, + {0x77f6, 0x00, 0, 0}, + {0x77f7, 0x00, 0, 0}, + {0x77f8, 0x01, 0, 0}, + {0x77f9, 0x55, 0, 0}, + {0x77fa, 0x00, 0, 0}, + {0x77fb, 0x00, 0, 0}, + {0x77fc, 0x01, 0, 0}, + {0x77fd, 0x44, 0, 0}, + {0x77fe, 0x00, 0, 0}, + {0x77ff, 0x00, 0, 0}, + {0x7800, 0x01, 0, 0}, + {0x7801, 0x33, 0, 0}, + {0x7802, 0x00, 0, 0}, + {0x7803, 0x00, 0, 0}, + {0x7804, 0x01, 0, 0}, + {0x7805, 0x22, 0, 0}, + {0x7806, 0x00, 0, 0}, + {0x7807, 0x00, 0, 0}, + {0x7808, 0x01, 0, 0}, + {0x7809, 0x11, 0, 0}, + {0x780a, 0x00, 0, 0}, + {0x780b, 0x00, 0, 0}, + {0x780c, 0x01, 0, 0}, + {0x780d, 0x00, 0, 0}, + {0x780e, 0x01, 0, 0}, + {0x780f, 0xff, 0, 0}, + {0x7810, 0x07, 0, 0}, + {0x7811, 0x00, 0, 0}, + {0x7812, 0x02, 0, 0}, + {0x7813, 0xa0, 0, 0}, + {0x7814, 0x0f, 0, 0}, + {0x7815, 0x00, 0, 0}, + {0x7816, 0x08, 0, 0}, + {0x7817, 0x35, 0, 0}, + {0x7818, 0x06, 0, 0}, + {0x7819, 0x52, 0, 0}, + {0x781a, 0x04, 0, 0}, + {0x781b, 0xe4, 0, 0}, + {0x781c, 0x00, 0, 0}, + {0x781d, 0x00, 0, 0}, + {0x781e, 0x06, 0, 0}, + {0x781f, 0x5e, 0, 0}, + {0x7820, 0x05, 0, 0}, + {0x7821, 0x33, 0, 0}, + {0x7822, 0x09, 0, 0}, + {0x7823, 0x19, 0, 0}, + {0x7824, 0x06, 0, 0}, + {0x7825, 0x1e, 0, 0}, + {0x7826, 0x05, 0, 0}, + {0x7827, 0x33, 0, 0}, + {0x7828, 0x00, 0, 0}, + {0x7829, 0x01, 0, 0}, + {0x782a, 0x06, 0, 0}, + {0x782b, 0x24, 0, 0}, + {0x782c, 0x06, 0, 0}, + {0x782d, 0x20, 0, 0}, + {0x782e, 0x0f, 0, 0}, + {0x782f, 0x00, 0, 0}, + {0x7830, 0x08, 0, 0}, + {0x7831, 0x35, 0, 0}, + {0x7832, 0x07, 0, 0}, + {0x7833, 0x10, 0, 0}, + {0x7834, 0x00, 0, 0}, + {0x7835, 0x00, 0, 0}, + {0x7836, 0x01, 0, 0}, + {0x7837, 0xbb, 0, 0}, + {0x7838, 0x00, 0, 0}, + {0x7839, 0x00, 0, 0}, + {0x783a, 0x01, 0, 0}, + {0x783b, 0xaa, 0, 0}, + {0x783c, 0x00, 0, 0}, + {0x783d, 0x00, 0, 0}, + {0x783e, 0x01, 0, 0}, + {0x783f, 0x99, 0, 0}, + {0x7840, 0x00, 0, 0}, + {0x7841, 0x00, 0, 0}, + {0x7842, 0x01, 0, 0}, + {0x7843, 0x88, 0, 0}, + {0x7844, 0x00, 0, 0}, + {0x7845, 0x00, 0, 0}, + {0x7846, 0x01, 0, 0}, + {0x7847, 0x77, 0, 0}, + {0x7848, 0x00, 0, 0}, + {0x7849, 0x00, 0, 0}, + {0x784a, 0x01, 0, 0}, + {0x784b, 0x66, 0, 0}, + {0x784c, 0x00, 0, 0}, + {0x784d, 0x00, 0, 0}, + {0x784e, 0x01, 0, 0}, + {0x784f, 0x55, 0, 0}, + {0x7850, 0x00, 0, 0}, + {0x7851, 0x00, 0, 0}, + {0x7852, 0x01, 0, 0}, + {0x7853, 0x44, 0, 0}, + {0x7854, 0x00, 0, 0}, + {0x7855, 0x00, 0, 0}, + {0x7856, 0x01, 0, 0}, + {0x7857, 0x33, 0, 0}, + {0x7858, 0x00, 0, 0}, + {0x7859, 0x00, 0, 0}, + {0x785a, 0x01, 0, 0}, + {0x785b, 0x22, 0, 0}, + {0x785c, 0x00, 0, 0}, + {0x785d, 0x00, 0, 0}, + {0x785e, 0x01, 0, 0}, + {0x785f, 0x11, 0, 0}, + {0x7860, 0x00, 0, 0}, + {0x7861, 0x00, 0, 0}, + {0x7862, 0x01, 0, 0}, + {0x7863, 0x00, 0, 0}, + {0x7864, 0x07, 0, 0}, + {0x7865, 0x00, 0, 0}, + {0x7866, 0x01, 0, 0}, + {0x7867, 0xff, 0, 0}, + {0x7868, 0x02, 0, 0}, + {0x7869, 0xa0, 0, 0}, + {0x786a, 0x0f, 0, 0}, + {0x786b, 0x00, 0, 0}, + {0x786c, 0x08, 0, 0}, + {0x786d, 0x3a, 0, 0}, + {0x786e, 0x08, 0, 0}, + {0x786f, 0x6a, 0, 0}, + {0x7870, 0x0f, 0, 0}, + {0x7871, 0x00, 0, 0}, + {0x7872, 0x04, 0, 0}, + {0x7873, 0xc0, 0, 0}, + {0x7874, 0x09, 0, 0}, + {0x7875, 0x19, 0, 0}, + {0x7876, 0x04, 0, 0}, + {0x7877, 0x99, 0, 0}, + {0x7878, 0x07, 0, 0}, + {0x7879, 0x14, 0, 0}, + {0x787a, 0x00, 0, 0}, + {0x787b, 0x01, 0, 0}, + {0x787c, 0x04, 0, 0}, + {0x787d, 0xa4, 0, 0}, + {0x787e, 0x00, 0, 0}, + {0x787f, 0x07, 0, 0}, + {0x7880, 0x04, 0, 0}, + {0x7881, 0xa6, 0, 0}, + {0x7882, 0x00, 0, 0}, + {0x7883, 0x00, 0, 0}, + {0x7884, 0x04, 0, 0}, + {0x7885, 0xa0, 0, 0}, + {0x7886, 0x04, 0, 0}, + {0x7887, 0x80, 0, 0}, + {0x7888, 0x04, 0, 0}, + {0x7889, 0x00, 0, 0}, + {0x788a, 0x05, 0, 0}, + {0x788b, 0x03, 0, 0}, + {0x788c, 0x06, 0, 0}, + {0x788d, 0x00, 0, 0}, + {0x788e, 0x0f, 0, 0}, + {0x788f, 0x00, 0, 0}, + {0x7890, 0x0f, 0, 0}, + {0x7891, 0x00, 0, 0}, + {0x7892, 0x0f, 0, 0}, + {0x7893, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x05, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x04, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x80, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x38, 0, 0}, + {0x30b0, 0x0b, 0, 0},//dde + {0x30b1, 0xcb, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x66, 0, 0}, + {0x30b6, 0x04, 0, 0}, + {0x30b7, 0x62, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x0a, 0, 0}, + {0x3195, 0x29, 0, 0}, + {0x3288, 0x2a, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x15, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x0a, 0, 0}, + {0x328d, 0x80, 0, 0}, + {0x328e, 0x05, 0, 0}, + {0x328f, 0x40, 0, 0}, + {0x3290, 0x54, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x2a, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x15, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x0a, 0, 0}, + {0x3297, 0x80, 0, 0}, + {0x3298, 0x7f, 0, 0}, + {0x3299, 0xff, 0, 0}, + {0x329a, 0x54, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x2a, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x15, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x7f, 0, 0}, + {0x32a3, 0xff, 0, 0}, + {0x32a4, 0x54, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x2a, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x3250, 0xf7, 0, 0}, + {0x30bb, 0x14, 0, 0}, + {0x315a, 0x02, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x80, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x80, 0, 0}, + + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x08, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x08, 0, 0}, + + {0x30c0, 0x08, 0, 0}, + {0x3252, 0x20, 0, 0}, +}; + +#endif diff --git a/vvcam/v4l2/video/Makefile b/vvcam/v4l2/video/Makefile new file mode 100755 index 0000000..af2ab18 --- /dev/null +++ b/vvcam/v4l2/video/Makefile @@ -0,0 +1,15 @@ +MODULE_NAME = vvcam-video + +obj-m := $(MODULE_NAME).o +$(MODULE_NAME)-objs := \ + video.o \ + vvbuf.o + +EXTRA_CFLAGS += -I$(PWD)/../common/ +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0xB0000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x10000000 + +ifeq ($(ENABLE_IRQ), yes) + EXTRA_CFLAGS += -DENABLE_IRQ +endif +EXTRA_CFLAGS += -O2 -Werror diff --git a/vvcam/v4l2/video/cma.c b/vvcam/v4l2/video/cma.c new file mode 100755 index 0000000..b11cb6c --- /dev/null +++ b/vvcam/v4l2/video/cma.c @@ -0,0 +1,277 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include "cma.h" + +#ifdef __KERNEL__ + +struct block_list { + struct block_list *next; + u64 base_addr; + u64 size; +}; + +struct cma_mem_context { + u64 base; + u64 size; + u64 align; + struct block_list free_blocks; + struct block_list used_blocks; +}; + +static struct cma_mem_context *g_cma_mem_ctx; +static inline void add_free_blocks(struct block_list *free_item); +static inline void add_used_blocks(struct block_list *used_item); +struct mutex viv_cma_mutex; + +int vsi_cma_init(u64 base, u64 size, u64 align) +{ + struct block_list *item = NULL; + + pr_debug("enter %s\n", __func__); + if (!size || (size <= align)) + return -EINVAL; + g_cma_mem_ctx = kzalloc(sizeof(struct cma_mem_context), GFP_KERNEL); + memset(g_cma_mem_ctx, 0, sizeof(*g_cma_mem_ctx)); + + g_cma_mem_ctx->base = (base + align - 1) & ~(align - 1); + g_cma_mem_ctx->size = size - (g_cma_mem_ctx->base - base); + g_cma_mem_ctx->align = align; + + pr_debug("addr:0x%llx, size:0x%llx, alignment:0x%llx.\n", + g_cma_mem_ctx->base, g_cma_mem_ctx->size, + g_cma_mem_ctx->align); + + item = kzalloc(sizeof(struct block_list), GFP_KERNEL); + if (!item) { + kzfree(g_cma_mem_ctx); + g_cma_mem_ctx = NULL; + return -ENOMEM; + } + + item->next = NULL; + item->base_addr = g_cma_mem_ctx->base; + item->size = g_cma_mem_ctx->size; + + g_cma_mem_ctx->free_blocks.next = item; + g_cma_mem_ctx->used_blocks.next = NULL; + + mutex_init(&viv_cma_mutex); + return 0; +} + +int vsi_cma_release(void) +{ + int result = 0; + struct block_list *item, *pFree; + + if (!g_cma_mem_ctx->free_blocks.next + || g_cma_mem_ctx->free_blocks.next->next + || g_cma_mem_ctx->used_blocks.next) { + pr_err("Warning memory is not free.\n"); + } + + item = g_cma_mem_ctx->free_blocks.next; + while (item) { + pFree = item; + item = item->next; + /* kzfree(pFree); */ + } + kzfree(g_cma_mem_ctx); + g_cma_mem_ctx = NULL; + + mutex_destroy(&viv_cma_mutex); + return result; +} + +u64 vsi_cma_alloc(u64 size) +{ + u64 addr = ~0U; + struct block_list *item; + struct block_list *found; + mutex_lock(&viv_cma_mutex); + if (!size || (size > g_cma_mem_ctx->size)) { + mutex_unlock(&viv_cma_mutex); + return ~0U; + } + + pr_debug("enter %s\n", __func__); + pr_debug + ("addr:0x%llx, size:0x%llx, alignment:0x%llx, reqsize:0x%llx.\n", + g_cma_mem_ctx->base, g_cma_mem_ctx->size, g_cma_mem_ctx->align, + size); + + size += g_cma_mem_ctx->align - 1; + size &= ~(g_cma_mem_ctx->align - 1); + /*TODO: need to lock this block */ + item = &g_cma_mem_ctx->free_blocks; + while (item->next && (item->next->size < size)) + item = item->next; + + found = item->next; + if (found) { + item->next = found->next; + if ((found->size - size) >= g_cma_mem_ctx->align) { + item = kzalloc(sizeof(struct block_list), GFP_KERNEL); + if (item) { + item->base_addr = found->base_addr + size; + item->size = found->size - size; + found->size = size; + pr_debug("new free block: base_addr=0x%llx,\n", + item->base_addr); + add_free_blocks(item); + } + } + + pr_debug("new used block: base_addr=0x%llx, size=0x%llx \n", + found->base_addr, found->size); + add_used_blocks(found); + addr = found->base_addr; + } + + pr_debug("block allocated: base_addr=0x%llx\n", addr); + mutex_unlock(&viv_cma_mutex); + return addr; +} + +void vsi_cma_free(u64 addr) +{ + pr_debug("enter %s\n", __func__); + pr_debug("block to free: base_addr=0x%llx\n", addr); + mutex_lock(&viv_cma_mutex); + if (addr) { + /*TODO: need to lock this block */ + struct block_list *item, *free_item; + + item = &g_cma_mem_ctx->used_blocks; + while (item->next && (item->next->base_addr != addr)) + item = item->next; + + free_item = item->next; + item->next = free_item->next; + if (((item->base_addr + item->size) != free_item->base_addr) || + ((free_item->base_addr + item->size) != ((free_item->next) ? + free_item->next->base_addr : + (g_cma_mem_ctx->base + + + g_cma_mem_ctx->size)))) { + struct block_list *loc_item; + struct block_list *pre_item = NULL; + struct block_list *success_item = NULL; + loc_item = &g_cma_mem_ctx->free_blocks; + while (loc_item->next) { + if ((loc_item->next->base_addr + + loc_item->next->size) == + free_item->base_addr) { + pre_item = loc_item; + } + if ((free_item->base_addr + free_item->size) == + loc_item->next->base_addr) { + success_item = loc_item; + } + loc_item = loc_item->next; + } + + if (success_item) { + loc_item = success_item->next; + free_item->size += loc_item->size; + success_item->next = loc_item->next; + kzfree(loc_item); + } + + if (pre_item) { + loc_item = pre_item->next; + free_item->base_addr = loc_item->base_addr; + free_item->size += loc_item->size; + pre_item->next = loc_item->next; + kzfree(loc_item); + } + } else { + pr_err("no adjacent block free\n"); + } + add_free_blocks(free_item); + } + mutex_unlock(&viv_cma_mutex); +} + +static inline void add_free_blocks(struct block_list *free_item) +{ + struct block_list *item; + + item = &g_cma_mem_ctx->free_blocks; + while (item->next && (item->next->size < free_item->size)) + item = item->next; + + free_item->next = item->next; + item->next = free_item; + + item = &g_cma_mem_ctx->free_blocks; + while (item->next) + item = item->next; +} + +static inline void add_used_blocks(struct block_list *used_item) +{ + struct block_list *item; + + item = &g_cma_mem_ctx->used_blocks; + while (item->next && (item->next->base_addr < used_item->base_addr)) + item = item->next; + + used_item->next = item->next; + item->next = used_item; + item = &g_cma_mem_ctx->used_blocks; + while (item->next) + item = item->next; +} + +#endif diff --git a/vvcam/v4l2/video/cma.h b/vvcam/v4l2/video/cma.h new file mode 100755 index 0000000..e133d28 --- /dev/null +++ b/vvcam/v4l2/video/cma.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_CMA_H_ +#define _ISP_CMA_H_ + +#include +#include + +int vsi_cma_init(u64 addr, u64 size, u64 align); +int vsi_cma_release(void); +u64 vsi_cma_alloc(u64 size); +void vsi_cma_free(u64 addr); + +#endif /* _ISP_CMA_H_ */ diff --git a/vvcam/v4l2/video/video.c b/vvcam/v4l2/video/video.c new file mode 100755 index 0000000..d3aae98 --- /dev/null +++ b/vvcam/v4l2/video/video.c @@ -0,0 +1,2387 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG +# include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "video.h" +#include "vvctrl.h" +#include "vvdefs.h" +#include "vvsensor.h" + +#define DEF_PLANE_NO (0) +#define RETRY_TIME_INTERVAL_MS (5) +#define RETRY_TIMES_MAX (10) + +static struct viv_video_device *vvdev[VIDEO_NODE_NUM]; +static struct list_head file_list_head[VIDEO_NODE_NUM]; +static spinlock_t file_list_lock[VIDEO_NODE_NUM]; +#ifdef ENABLE_IRQ +static struct media_device mdev; +#endif + +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG +struct ext_dma_buf { + dma_addr_t addr; + void *vaddr; + size_t size; + struct list_head entry; +}; +#endif + +static struct viv_video_fmt formats[] = { + { + .fourcc = V4L2_PIX_FMT_YUYV, + .depth = 16, + .bpp = 2, + }, + { + .fourcc = V4L2_PIX_FMT_NV12, + .depth = 12, + .bpp = 1, + }, + { + .fourcc = V4L2_PIX_FMT_NV16, + .depth = 16, + .bpp = 1, + }, +}; + +static int bayer_pattern_to_format(unsigned int bayer_pattern, + unsigned int bit_width, struct viv_video_fmt *fmt) +{ + int ret = 0; + + if (bayer_pattern == BAYER_BGGR) + if (bit_width == 8) { + fmt->fourcc = V4L2_PIX_FMT_SBGGR8; + fmt->depth = 8; + fmt->bpp = 1; + } else if (bit_width == 10) { + fmt->fourcc = V4L2_PIX_FMT_SBGGR10; + fmt->depth = 16; + fmt->bpp = 2; + } else if (bit_width == 12) { + fmt->fourcc = V4L2_PIX_FMT_SBGGR12; + fmt->depth = 16; + fmt->bpp = 2; + } else + ret = -EPERM; + else if (bayer_pattern == BAYER_GBRG) + if (bit_width == 8) { + fmt->fourcc = V4L2_PIX_FMT_SGBRG8; + fmt->depth = 8; + fmt->bpp = 1; + } else if (bit_width == 10) { + fmt->fourcc = V4L2_PIX_FMT_SGBRG10; + fmt->depth = 16; + fmt->bpp = 2; + } else if (bit_width == 12) { + fmt->fourcc = V4L2_PIX_FMT_SGBRG12; + fmt->depth = 16; + fmt->bpp = 2; + } else + ret = -EPERM; + else if (bayer_pattern == BAYER_GRBG) + if (bit_width == 8) { + fmt->fourcc = V4L2_PIX_FMT_SGRBG8; + fmt->depth = 8; + fmt->bpp = 1; + } else if (bit_width == 10) { + fmt->fourcc = V4L2_PIX_FMT_SGRBG10; + fmt->depth = 16; + fmt->bpp = 2; + } else if (bit_width == 12) { + fmt->fourcc = V4L2_PIX_FMT_SGRBG12; + fmt->depth = 16; + fmt->bpp = 2; + } else + ret = -EPERM; + else if (bayer_pattern == BAYER_RGGB) + if (bit_width == 8) { + fmt->fourcc = V4L2_PIX_FMT_SRGGB8; + fmt->depth = 8; + fmt->bpp = 1; + } else if (bit_width == 10) { + fmt->fourcc = V4L2_PIX_FMT_SRGGB10; + fmt->depth = 16; + fmt->bpp = 2; + } else if (bit_width == 12) { + fmt->fourcc = V4L2_PIX_FMT_SRGGB12; + fmt->depth = 16; + fmt->bpp = 2; + } else + ret = -EPERM; + else + ret = -EPERM; + return ret; +} + +/* Caller must hold fh->vdev->fh_lock! */ +static struct v4l2_subscribed_event *video_event_fh_subscribed( + struct v4l2_fh *fh, u32 type, u32 id) +{ + struct v4l2_subscribed_event *sev; + + assert_spin_locked(&fh->vdev->fh_lock); + + list_for_each_entry(sev, &fh->subscribed, list) + if (sev->type == type && sev->id == id) { + return sev; + } + + return NULL; +} + +/*0-unsubscribed 1-subscribed*/ +static int video_event_subscribed(struct video_device *vdev, + const struct v4l2_event *ev, u16 retries) +{ + struct v4l2_fh *fh; + unsigned long flags; + int retry; + + if (vdev == NULL || ev == NULL) + return 0; + + /*retry for waitting the daemon to subscribe */ + for(retry = 0; retry < retries; retry++) { + spin_lock_irqsave(&vdev->fh_lock, flags); + /*search the fh_list and check the event subscribed or not*/ + list_for_each_entry(fh, &vdev->fh_list, list) { + if(video_event_fh_subscribed(fh, ev->type, ev->id)) { + spin_unlock_irqrestore(&vdev->fh_lock, flags); + return 1; + } + } + spin_unlock_irqrestore(&vdev->fh_lock, flags); + msleep(RETRY_TIME_INTERVAL_MS); + } + + return 0; +} + +static int viv_post_event(struct v4l2_event *event, void *fh, bool sync) +{ + struct viv_video_file *handle = priv_to_handle(fh); + struct v4l2_fh *video_fh = (struct v4l2_fh *)fh; + + if(!video_fh || !event) { + return -EINVAL; + } + + if(!video_event_subscribed(video_fh->vdev, event, RETRY_TIMES_MAX)) { + pr_err("%s: unsubscribed event id =%d type=0x%08x", + __func__, event->id, event->type); + return -EAGAIN; + } + + if (sync) + reinit_completion(&handle->wait); + + mutex_lock(&handle->event_mutex); + v4l2_event_queue(handle->vdev->video, event); + mutex_unlock(&handle->event_mutex); + + if (sync) { + if (wait_for_completion_timeout(&handle->wait, msecs_to_jiffies( + VIV_VIDEO_EVENT_TIMOUT_MS)) == 0) + return -ETIMEDOUT; + } + return 0; +} + +static int viv_post_simple_event(int id, int streamid, void *fh, bool sync) +{ + struct v4l2_event event; + struct viv_video_event *v_event; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = streamid; + v_event->file = fh; + v_event->sync = sync; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = id; + return viv_post_event(&event, fh, sync); +} + +static int viv_post_control_event(int streamid, void *fh, + struct viv_control_event *control_event) +{ + struct v4l2_event event; + struct viv_video_event *v_event; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = streamid; + v_event->file = fh; + v_event->sync = true; + v_event->addr = control_event->request; + v_event->response = control_event->response; + v_event->buf_index = control_event->id; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_PASS_JSON; + return viv_post_event(&event, fh, true); +} + +static int set_stream(struct viv_video_device *vdev, int enable) +{ + struct v4l2_subdev *sd; + struct media_pad *pad; + + if (!vdev) + return -EINVAL; + + pad = &vdev->video->entity.pads[0]; + if (pad) + pad = media_entity_remote_pad(pad); + + if (pad && is_media_entity_v4l2_subdev(pad->entity)) { + sd = media_entity_to_v4l2_subdev(pad->entity); + v4l2_subdev_call(sd, video, s_stream, enable); + } + return 0; +} + +static int start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct viv_video_file *handle = queue_to_handle(vq); + struct v4l2_fh *fh = &handle->vfh; + + pr_debug("enter %s\n", __func__); + if (handle->streamid >= 0 && handle->state != 2) { + handle->state = 2; + handle->vdev->active = 1; + set_stream(handle->vdev, 1); + viv_post_simple_event(VIV_VIDEO_EVENT_START_STREAM, + handle->streamid, fh, true); + } else { + pr_err("can't start streaming, device busy!\n"); + return -EBUSY; + } + return 0; +} + +static void stop_streaming(struct vb2_queue *vq) +{ + struct viv_video_file *handle = queue_to_handle(vq); + struct vb2_buffer *vb; + + pr_debug("enter %s\n", __func__); + + if (!handle || handle->streamid < 0 || handle->state != 2) + return; + + handle->state = 1; + set_stream(handle->vdev, 0); + viv_post_simple_event(VIV_VIDEO_EVENT_STOP_STREAM, handle->streamid, + &handle->vfh, true); + handle->sequence = 0; + list_for_each_entry(vb, &vq->queued_list, queued_entry) { + if (vb->state == VB2_BUF_STATE_ACTIVE) + vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); + } +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0) +static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], void *alloc_ctxs[]) +{ + struct viv_video_file *handle = queue_to_handle(vq); + unsigned long size = handle->vdev->fmt.fmt.pix.sizeimage; + + pr_debug("enter %s\n", __func__); + if (*nbuffers == 0) + *nbuffers = 1; + while (size * *nbuffers > RESERVED_MEM_SIZE) + (*nbuffers)--; + sizes[0] = size; + return 0; +} +#else +static int queue_setup(struct vb2_queue *q, + unsigned int *num_buffers, unsigned int *num_planes, + unsigned int sizes[], struct device *alloc_devs[]) +{ + struct viv_video_file *handle = queue_to_handle(q); + unsigned long size = handle->vdev->fmt.fmt.pix.sizeimage; + + pr_debug("enter %s\n", __func__); + if (*num_buffers == 0) + *num_buffers = 1; + while (size * *num_buffers > RESERVED_MEM_SIZE) + (*num_buffers)--; + *num_planes = 1; + sizes[0] = size; + return 0; +} +#endif + +static int buffer_init(struct vb2_buffer *vb) +{ + pr_debug("enter %s\n", __func__); + return 0; +} + +static void buffer_queue(struct vb2_buffer *vb) +{ + struct viv_video_file *handle; + struct vb2_v4l2_buffer *vbuf; + struct vb2_dc_buf *buf; +#ifdef ENABLE_IRQ + struct viv_video_device *vdev; + struct media_pad *pad; +#else + struct v4l2_event event; + struct viv_video_event *v_event; +#endif + + if (!vb) + return; + + handle = queue_to_handle(vb->vb2_queue); + vbuf = container_of(vb, struct vb2_v4l2_buffer, vb2_buf); + buf = container_of(vbuf, struct vb2_dc_buf, vb); + if (!buf) + return; + + if (!handle) + return; + +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + buf->dma = vb2_dma_contig_plane_dma_addr(vb, DEF_PLANE_NO); +#endif + +#ifdef ENABLE_IRQ + vdev = handle->vdev; + if (!vdev) + return; + + pad = &vdev->video->entity.pads[0]; + vvbuf_ready(&vdev->bctx, pad, buf); +#endif + +#ifndef ENABLE_IRQ + if (handle->streamid < 0) + return; + + /* pr_debug("buffer_queue %d", vb->index); */ + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = handle->streamid; + v_event->file = &handle->vfh; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + v_event->addr = vb2_dma_contig_plane_dma_addr(vb, DEF_PLANE_NO); +#endif + v_event->buf_index = vb->index; + v_event->sync = false; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_QBUF; + viv_post_event(&event, &handle->vfh, false); +#endif +} + +static struct vb2_ops buffer_ops = { + .queue_setup = queue_setup, + .buf_init = buffer_init, + .buf_queue = buffer_queue, + .start_streaming = start_streaming, + .stop_streaming = stop_streaming, +}; + +static int video_open(struct file *file) +{ + struct viv_video_device *dev = video_drvdata(file); + struct viv_video_file *handle; + unsigned long flags; + int rc; + + pr_debug("enter %s\n", __func__); + handle = kzalloc(sizeof(*handle), GFP_KERNEL); + + v4l2_fh_init(&handle->vfh, dev->video); + v4l2_fh_add(&handle->vfh); + + file->private_data = &handle->vfh; + handle->vdev = dev; + handle->queue.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + handle->queue.drv_priv = handle; + handle->queue.ops = &buffer_ops; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + handle->queue.io_modes = VB2_MMAP | VB2_DMABUF; + handle->queue.mem_ops = &vb2_dma_contig_memops; +#endif + handle->queue.buf_struct_size = sizeof(struct vb2_dc_buf); + handle->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 5, 0) + handle->queue.dev = dev->v4l2_dev->dev; +#endif + rc = vb2_queue_init(&handle->queue); + if (rc) { + pr_err("can't init vb queue\n"); + v4l2_fh_del(&handle->vfh); + v4l2_fh_exit(&handle->vfh); + kfree(handle); + return rc; + } + mutex_init(&handle->event_mutex); + mutex_init(&handle->buffer_mutex); + init_completion(&handle->wait); + +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + INIT_LIST_HEAD(&handle->extdmaqueue); +#endif + + handle->event_buf.va = kmalloc(VIV_EVENT_BUF_SIZE, GFP_KERNEL); + handle->event_buf.pa = __pa(handle->event_buf.va); + + spin_lock_irqsave(&file_list_lock[handle->vdev->id], flags); + list_add_tail(&handle->entry, &file_list_head[handle->vdev->id]); + spin_unlock_irqrestore(&file_list_lock[handle->vdev->id], flags); + return 0; +} + +static int video_close(struct file *file) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct vb2_buffer *vb; + spinlock_t *lock; + unsigned long flags; + + pr_debug("enter %s\n", __func__); + if (handle) { + handle->req = false; + if (handle->streamid >= 0 && handle->state == 2) { + set_stream(handle->vdev, 0); + viv_post_simple_event(VIV_VIDEO_EVENT_STOP_STREAM, + handle->streamid, &handle->vfh, + false); + handle->state = 1; + } + if (handle->streamid >= 0 && handle->state == 1) { + viv_post_simple_event(VIV_VIDEO_EVENT_DEL_STREAM, + handle->streamid, &handle->vfh, + true); + handle->vdev->frame_flag = false; + } + + if (handle->state > 0) + handle->vdev->active = 0; + handle->state = -1; + handle->streamid = 0; + lock = &file_list_lock[handle->vdev->id]; + spin_lock_irqsave(lock, flags); + list_del(&handle->entry); + spin_unlock_irqrestore(lock, flags); + + list_for_each_entry(vb, &handle->queue.queued_list, + queued_entry) { + if (vb->state == VB2_BUF_STATE_ACTIVE) + vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); + } + + v4l2_fh_del(&handle->vfh); + v4l2_fh_exit(&handle->vfh); + +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + { + struct ext_dma_buf *edb = NULL; + + while (!list_empty(&handle->extdmaqueue)) { + edb = list_first_entry(&handle->extdmaqueue, + struct ext_dma_buf, entry); + if (edb) { + dma_free_attrs(handle->queue.dev, + edb->size, edb->vaddr, + edb->addr, + DMA_ATTR_WRITE_COMBINE); + list_del(&edb->entry); + kfree(edb); + } + } + } +#endif + + vb2_queue_release(&handle->queue); + mutex_destroy(&handle->event_mutex); + mutex_destroy(&handle->buffer_mutex); + kfree(handle->event_buf.va); + kfree(handle); + } + return 0; +} + +static int subscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + int ret; + unsigned long flags; + struct viv_video_file *handle = priv_to_handle(fh); + struct viv_video_device *vdev; + + if (!handle || !sub) + return -EINVAL; + if (unlikely(sub->type != VIV_VIDEO_EVENT_TYPE)) + return v4l2_ctrl_subscribe_event(fh, sub); + ret = v4l2_event_subscribe(fh, sub, 10, 0); + vdev = handle->vdev; + if (!ret && vdev && sub->id == VIV_VIDEO_EVENT_GET_CAPS_SUPPORTS) { + spin_lock_irqsave(&file_list_lock[vdev->id], flags); + vdev->subscribed_cnt++; + spin_unlock_irqrestore(&file_list_lock[vdev->id], flags); + complete_all(&vdev->subscribed_wait); + } + return ret; +} + +static int unsubscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + struct viv_video_file *handle = priv_to_handle(fh); + struct viv_video_file *ph; + struct viv_video_device *vdev; + spinlock_t *lock; + unsigned long flags; + + pr_debug("enter %s\n", __func__); + if (!handle || !handle->vdev || !sub) + return 0; + if (unlikely(sub->type != VIV_VIDEO_EVENT_TYPE)) + return v4l2_event_unsubscribe(fh, sub); + + vdev = handle->vdev; + lock = &file_list_lock[vdev->id]; + spin_lock_irqsave(lock, flags); + list_for_each_entry(ph, &file_list_head[vdev->id], entry) { + if (ph == handle && handle->streamid < 0) { + if (sub->id == VIV_VIDEO_EVENT_GET_CAPS_SUPPORTS) { + vdev->subscribed_cnt--; + if (vdev->subscribed_cnt <= 0) { + reinit_completion( + &vdev->subscribed_wait); + vdev->subscribed_cnt = 0; + } + } + spin_unlock_irqrestore(lock, flags); + return v4l2_event_unsubscribe(fh, sub); + } + } + spin_unlock_irqrestore(lock, flags); + return 0; +} + +#ifndef ENABLE_IRQ +static void viv_buffer_done(struct viv_video_file *handle, u64 addr) +{ + struct vb2_buffer *vb; + + mutex_lock(&handle->buffer_mutex); + list_for_each_entry(vb, &handle->queue.queued_list, queued_entry) { + if (!vb) + continue; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + if (vb2_dma_contig_plane_dma_addr(vb, DEF_PLANE_NO) == addr) { + vb->planes[DEF_PLANE_NO].bytesused = + handle->vdev->fmt.fmt.pix.sizeimage; +#endif +#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 0, 0) + vb->timestamp = ktime_get_ns(); +#endif + vb2_buffer_done(vb, VB2_BUF_STATE_DONE); + mutex_unlock(&handle->buffer_mutex); + return; + } + } + mutex_unlock(&handle->buffer_mutex); +} +#endif + +static int set_caps_mode_event(struct file *file) +{ + struct viv_video_device *dev = video_drvdata(file); + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct v4l2_event event; + struct viv_video_event *v_event; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = 0; + v_event->file = &handle->vfh; + v_event->sync = true; + v_event->buf_index = dev->id; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_SET_CAPSMODE; + return viv_post_event(&event, &handle->vfh, true); +} + +static int get_caps_suppots_event(struct file *file) +{ + struct viv_video_device *dev = video_drvdata(file); + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct v4l2_event event; + struct viv_video_event *v_event; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = 0; + v_event->file = &handle->vfh; + v_event->sync = true; + v_event->buf_index = dev->id; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_GET_CAPS_SUPPORTS; + + if (dev->subscribed_cnt == 0 && + wait_for_completion_timeout(&dev->subscribed_wait, + msecs_to_jiffies(VIV_VIDEO_EVENT_TIMOUT_MS)) == 0) + return -ETIMEDOUT; + return viv_post_event(&event, &handle->vfh, true); +} + +#ifdef ENABLE_IRQ +static struct media_entity *viv_find_entity(struct viv_video_device *dev, + const char *name) +{ + struct v4l2_subdev *sd = NULL; + int i; + + for (i = 0; i < dev->sdcount; ++i) { + if (!strncmp(dev->subdevs[i]->name, name, strlen(name))) { + sd = dev->subdevs[i]; + break; + } + } + return sd ? &sd->entity : NULL; +} + +static int viv_create_link(struct media_entity *source, u16 source_pad, + struct media_entity *sink, u16 sink_pad) +{ + int rc = 0; + u32 flags = MEDIA_LNK_FL_ENABLED; + + if (!source || !sink) + return -EINVAL; + rc = media_create_pad_link(source, source_pad, sink, sink_pad, flags); + if (rc) + goto end; + + rc = media_entity_call(sink, link_setup, &sink->pads[sink_pad], + &source->pads[source_pad], flags); + if (rc) + goto end; + + rc = media_entity_call(source, link_setup, &source->pads[source_pad], + &sink->pads[sink_pad], flags); + if (rc) + goto end; +end: + return rc; +} + +static int viv_create_default_links(struct viv_video_device *dev) +{ + struct media_entity *source, *sink; + + source = viv_find_entity(dev, ISP_DEVICE_NAME); + sink = &dev->video->entity; + return viv_create_link(source, ISP_PAD_SOURCE, sink, 0); +} + +static int viv_config_dwe(struct viv_video_file *handle, bool enable) +{ + struct viv_video_device *vdev = handle->vdev; + int rc; + struct media_entity *source, *sink; + + if (!vdev || !vdev->sdcount) + return -EINVAL; + + if (vdev->dweEnabled == enable) + return 0; + + source = viv_find_entity(vdev, DWE_DEVICE_NAME); + if (!source) + return -EINVAL; + sink = &vdev->video->entity; + media_entity_remove_links(source); + media_entity_remove_links(sink); + + if (!enable) { + source = viv_find_entity(vdev, ISP_DEVICE_NAME); + media_entity_remove_links(source); + rc = viv_create_link(source, ISP_PAD_SOURCE, sink, 0); + if (!rc) + vdev->dweEnabled = false; + return rc; + } + + rc = viv_create_link(source, DWE_PAD_SOURCE, sink, 0); + if (rc) + goto end; + + if (vdev->sdcount > 1) { + source = viv_find_entity(vdev, ISP_DEVICE_NAME); + sink = viv_find_entity(vdev, DWE_DEVICE_NAME); + media_entity_remove_links(source); + if (viv_create_link(source, ISP_PAD_SOURCE, sink, DWE_PAD_SINK)) + pr_err("failed to create link between isp and dwe!\n"); + } + + vdev->dweEnabled = true; +end: + return rc; +} +#endif + +static inline void init_v4l2_fmt(struct v4l2_format *f, unsigned int bpp, + unsigned int depth, unsigned int *bytesperline, + unsigned int *sizeimage) +{ + v4l_bound_align_image(&f->fmt.pix.width, 48, 3840, 2, + &f->fmt.pix.height, 32, 2160, 0, 0); + *bytesperline = ALIGN_UP(f->fmt.pix.width * bpp, 16); + *sizeimage = f->fmt.pix.height * ALIGN_UP(f->fmt.pix.width * depth / 8, 16); +} + +static int viv_set_modeinfo(struct viv_video_file *handle, + struct vvcam_constant_modeinfo *modeinfo) +{ + struct viv_video_device *vdev = handle->vdev; + struct viv_video_fmt fmt; + struct viv_video_fmt *pfmt = NULL; + int i; + + if (modeinfo->w == 0 || modeinfo->h == 0 || modeinfo->fps == 0) { + vdev->modeinfocount = 0; + memset(vdev->modeinfo, 0, sizeof(vdev->modeinfo)); + memset(&vdev->crop, 0, sizeof(struct v4l2_rect)); + memset(&vdev->compose, 0, sizeof(struct v4l2_rect)); + return -EINVAL; + } + + for (i = 0; i < vdev->modeinfocount; ++i) { + if (vdev->modeinfo[i].index == modeinfo->index) { + pr_debug("sensor mode info already configured!\n"); + return 0; + } + } + + if (vdev->modeinfocount < ARRAY_SIZE(vdev->modeinfo)) { + memcpy(&vdev->modeinfo[vdev->modeinfocount], + modeinfo, sizeof(*modeinfo)); + vdev->modeinfocount++; + } + + if (!bayer_pattern_to_format(modeinfo->brpat, modeinfo->bitw, &fmt) && + vdev->formatscount < ARRAY_SIZE(vdev->formats)) { + for (i = 0; i < vdev->formatscount; ++i) + if (vdev->formats[i].fourcc == fmt.fourcc) + break; + if (i == vdev->formatscount) { + memcpy(&vdev->formats[vdev->formatscount], + &fmt, sizeof(fmt)); + vdev->formatscount++; + } + } + + if (vdev->fmt.fmt.pix.width == 0 || vdev->fmt.fmt.pix.height == 0) { + if (vdev->formats[0].fourcc == 0 || vdev->formats[0].bpp == 0 || + vdev->formats[0].depth == 0 || + vdev->modeinfo[0].w == 0 || vdev->modeinfo[0].h == 0 || + vdev->modeinfo[0].fps == 0) + pr_err("invalid default format!\n"); + + if (vdev->fmt.fmt.pix.pixelformat == 0) { + vdev->fmt.fmt.pix.pixelformat = vdev->formats[0].fourcc; + } + for (i = 0; i < vdev->formatscount; ++i) { + if (vdev->fmt.fmt.pix.pixelformat == vdev->formats[i].fourcc) { + pfmt = &vdev->formats[i]; + break; + } + } + if (pfmt == NULL) + pfmt = &vdev->formats[0]; + + init_v4l2_fmt(&vdev->fmt, pfmt->bpp, pfmt->depth, + &vdev->fmt.fmt.pix.bytesperline, + &vdev->fmt.fmt.pix.sizeimage); + + vdev->timeperframe.numerator = 1; + vdev->timeperframe.denominator = vdev->modeinfo[0].fps; + } + + if (vdev->crop.width == 0 || vdev->crop.height == 0) { + vdev->crop.width = vdev->modeinfo[0].w; + vdev->crop.height = vdev->modeinfo[0].h; + } + + if (vdev->compose.width == 0 || vdev->compose.height == 0) { + vdev->compose.width = vdev->modeinfo[0].w; + vdev->compose.height = vdev->modeinfo[0].h; + } + return 0; +} + +static long private_ioctl(struct file *file, void *fh, + bool valid_prio, unsigned int cmd, void *arg) +{ + struct viv_video_file *handle; + struct viv_video_file *ph; + struct viv_video_event *v_event; + struct ext_buf_info *ext_buf; + struct viv_control_event *control_event; + struct viv_caps_supports *pcaps_supports; + struct viv_video_device *dev = video_drvdata(file); + unsigned long flags; + int rc = 0; + struct reserved_mem *rmem; + + if (!file || !fh) + return -EINVAL; + + handle = priv_to_handle(file->private_data); + if (!handle || handle->state == -1) { + pr_err("call ioctl after file closed\n"); + return -EINVAL; + } + + switch (cmd) { + case VIV_VIDIOC_EVENT_COMPLETE: + v_event = (struct viv_video_event *)arg; + if (v_event->file) { + handle = priv_to_handle(v_event->file); + spin_lock_irqsave( + &file_list_lock[dev->id], flags); + list_for_each_entry(ph, + &file_list_head[dev->id], entry) { + if (ph == handle) { + complete(&handle->wait); + break; + } + } + spin_unlock_irqrestore( + &file_list_lock[dev->id], flags); + } else { + complete(&dev->ctrls.wait); + } + break; +#ifndef ENABLE_IRQ + case VIV_VIDIOC_BUFDONE: { + /* pr_debug("priv ioctl VIV_VIDIOC_BUFDONE\n"); */ + struct v4l2_user_buffer *user_buffer = + (struct v4l2_user_buffer *)arg; + if (!user_buffer->file) + break; + + handle = priv_to_handle(user_buffer->file); + if (!handle || handle->state != 2) + break; + + /* handle the stream closed unexpected. */ + spin_lock_irqsave(&file_list_lock[dev->id], flags); + list_for_each_entry(ph, &file_list_head[dev->id], entry) { + if (ph == handle) { + viv_buffer_done(handle, user_buffer->addr); + break; + } + } + spin_unlock_irqrestore(&file_list_lock[dev->id], flags); + break; + } +#endif + case VIV_VIDIOC_S_STREAMID: + pr_debug("priv ioctl VIV_VIDIOC_S_STREAMID\n"); + handle->streamid = *((int *)arg); + break; +#ifdef ENABLE_IRQ + case VIV_VIDIOC_S_DWECFG: + viv_config_dwe(handle, !!*((int *)arg)); + break; + case VIV_VIDIOC_G_DWECFG: + *((int *)arg) = handle->vdev->dweEnabled ? 1 : 0; + break; +#endif + case VIV_VIDIOC_BUFFER_ALLOC: { + struct ext_buf_info *ext_buf = (struct ext_buf_info *)arg; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + struct ext_dma_buf *edb = kzalloc(sizeof(*edb), GFP_KERNEL); + + pr_debug("priv ioctl VIV_VIDIOC_BUFFER_ALLOC\n"); + if (!edb) { + rc = -ENOMEM; + break; + } + edb->vaddr = dma_alloc_attrs(handle->queue.dev, + ext_buf->size, &ext_buf->addr, + GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); + if (!edb->vaddr) { + pr_err("failed to alloc dma buffer!\n"); + rc = -ENOMEM; + } else { + edb->addr = ext_buf->addr; + edb->size = ext_buf->size; + list_add_tail(&edb->entry, &handle->extdmaqueue); + } +#endif + break; + } + case VIV_VIDIOC_BUFFER_FREE: { + struct ext_buf_info *ext_buf = (struct ext_buf_info *)arg; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + struct ext_dma_buf *b, *edb = NULL; + + pr_debug("priv ioctl VIV_VIDIOC_BUFFER_FREE\n"); + list_for_each_entry(b, &handle->extdmaqueue, entry) { + if (b->addr == ext_buf->addr) { + edb = b; + break; + } + } + + if (edb) { + dma_free_attrs(handle->queue.dev, edb->size, + edb->vaddr, edb->addr, + DMA_ATTR_WRITE_COMBINE); + list_del(&edb->entry); + kfree(edb); + } +#endif + break; + } + case VIV_VIDIOC_CONTROL_EVENT: + pr_debug("priv ioctl VIV_VIDIOC_CONTROL_EVENT\n"); + control_event = (struct viv_control_event *)arg; + rc = viv_post_control_event(handle->streamid, &handle->vfh, + control_event); + break; + case VIV_VIDIOC_QUERY_EXTMEM: + pr_debug("priv ioctl VIV_VIDIOC_QUERY_EXTMEM\n"); + ext_buf = (struct ext_buf_info *)arg; + rmem = (struct reserved_mem *)dev->rmem; + if (!rmem) { + ext_buf->addr = 0; + ext_buf->size = 0; + } else { + ext_buf->addr = rmem->base; + ext_buf->size = rmem->size; + } + break; + case VIV_VIDIOC_S_MODEINFO: + rc = viv_set_modeinfo(handle, arg); + break; + + case VIV_VIDIOC_S_CAPS_MODE: + memcpy(&(dev->caps_mode), arg, sizeof(dev->caps_mode)); + rc = set_caps_mode_event(file); + if (rc == 0) + rc = dev->event_result; + break; + + case VIV_VIDIOC_G_CAPS_MODE: + memcpy(arg, &(dev->caps_mode), sizeof(dev->caps_mode)); + break; + + case VIV_VIDIOC_EVENT_RESULT: + dev->event_result = *(int *)arg; + break; + + case VIV_VIDIOC_GET_CAPS_SUPPORTS:{ + pcaps_supports = (struct viv_caps_supports *)arg; + rc = get_caps_suppots_event(file); + memcpy(pcaps_supports, &(dev->caps_supports), + sizeof(dev->caps_supports)); + break; + } + + case VIV_VIDIOC_SET_CAPS_SUPPORTS: + pcaps_supports = (struct viv_caps_supports *)arg; + memcpy(&(dev->caps_supports), arg, sizeof(dev->caps_supports)); + break; + } + return rc; +} + +static int video_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct viv_video_device *dev = video_drvdata(file); + + pr_debug("enter %s\n", __func__); + strcpy(cap->driver, "viv_v4l2_device"); + strcpy(cap->card, "VIV"); + cap->bus_info[0] = 0; + if (dev) + snprintf((char *)cap->bus_info, sizeof(cap->bus_info), + "platform:viv%d", dev->id); + + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_STREAMING | V4L2_CAP_DEVICE_CAPS; + cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + return 0; +} + +static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct viv_video_device *dev = video_drvdata(file); + + if (f->index < dev->formatscount) { + f->pixelformat = dev->formats[f->index].fourcc; + return 0; + } + return -EINVAL; +} + +static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + *f = handle->vdev->fmt; + return 0; +} + +static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viv_video_device *dev = video_drvdata(file); + struct viv_video_fmt *format = NULL; + int bytesperline, sizeimage; + int i; + + pr_debug("enter %s\n", __func__); + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + f->fmt.pix.width = ALIGN_UP(f->fmt.pix.width, 16); + f->fmt.pix.height = ALIGN_UP(f->fmt.pix.height, 8); + + for (i = 0; i < dev->formatscount; ++i) { + if (dev->formats[i].fourcc == f->fmt.pix.pixelformat) { + format = &dev->formats[i]; + break; + } + } + if (format == NULL) + return -EINVAL; + + f->fmt.pix.field = dev->fmt.fmt.pix.field; + f->fmt.pix.colorspace = dev->fmt.fmt.pix.colorspace; + init_v4l2_fmt(f, format->bpp, format->depth, &bytesperline, &sizeimage); + if (f->fmt.pix.bytesperline < bytesperline) + f->fmt.pix.bytesperline = bytesperline; + if (f->fmt.pix.sizeimage < sizeimage) + f->fmt.pix.sizeimage = sizeimage; + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct viv_video_device *vdev = handle->vdev; + int ret; + struct v4l2_event event; + struct viv_video_event *v_event; + struct viv_rect *rect = (struct viv_rect *)handle->event_buf.va; + + pr_debug("enter %s\n", __func__); + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + ret = vidioc_try_fmt_vid_cap(file, priv, f); + + if (ret < 0) + return -EINVAL; + + handle->vdev->fmt = *f; + + if (vdev->crop.top == 0 && + vdev->crop.left == 0 && + vdev->crop.width == vdev->compose.width && + vdev->crop.height == vdev->compose.height) { + vdev->compose.width = f->fmt.pix.width; + vdev->compose.height = f->fmt.pix.height; + vdev->crop.width = vdev->compose.width; + vdev->crop.height = vdev->compose.height; + + rect->left = 0; + rect->top = 0; + rect->width = vdev->compose.width; + rect->height = vdev->compose.height; + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = handle->streamid; + v_event->file = &(handle->vfh); + v_event->sync = true; + v_event->addr = handle->event_buf.pa; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_SET_COMPOSE; + viv_post_event(&event, &handle->vfh, true); + + rect->left = 0; + rect->top = 0; + rect->width = 0; + rect->height = 0; + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = handle->streamid; + v_event->file = &(handle->vfh); + v_event->sync = true; + v_event->addr = handle->event_buf.pa; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_SET_CROP; + viv_post_event(&event, &handle->vfh, true); + } + + return ret; +} + +static int vidioc_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *p) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct viv_video_file *ph; + struct viv_video_device *vdev = handle->vdev; + struct v4l2_event event; + struct viv_video_event *v_event; + unsigned long flags; + int ret = 0; + + pr_debug("enter %s %d %d\n", __func__, p->count, p->memory); + if (p->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + spin_lock_irqsave(&file_list_lock[vdev->id], flags); + list_for_each_entry(ph, &file_list_head[vdev->id], entry) { + if (ph->streamid == handle->streamid && + ph != handle && ph->req) { + pr_err("stream is busy %d\n", ph->streamid); + spin_unlock_irqrestore(&file_list_lock[vdev->id], + flags); + return -EBUSY; + } + } + spin_unlock_irqrestore(&file_list_lock[vdev->id], flags); + + if (p->count == 0) + handle->req = false; + else + handle->req = true; + + mutex_lock(&handle->buffer_mutex); + ret = vb2_reqbufs(&handle->queue, p); + mutex_unlock(&handle->buffer_mutex); + + if (p->count == 0) { + memset(p, 0, sizeof(*p)); + return ret; + } + if (ret < 0) + return ret; + + if (handle->streamid < 0 || handle->state > 0) + return ret; + handle->state = 1; + ret = + viv_post_simple_event(VIV_VIDEO_EVENT_NEW_STREAM, handle->streamid, + &handle->vfh, true); + if (ret) + return ret; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = handle->streamid; + v_event->file = &handle->vfh; + v_event->addr = handle->vdev->fmt.fmt.pix.width; + v_event->response = handle->vdev->fmt.fmt.pix.height; + v_event->buf_index = handle->vdev->fmt.fmt.pix.pixelformat; + v_event->sync = true; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_SET_FMT; + ret = viv_post_event(&event, &handle->vfh, true); + + return ret; +} + +static int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int rc = 0; + + pr_debug("enter %s\n", __func__); + + if (p->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + mutex_lock(&handle->buffer_mutex); + rc = vb2_querybuf(&handle->queue, p); + mutex_unlock(&handle->buffer_mutex); + return rc; +} + +static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int rc = 0; + + if (p->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + mutex_lock(&handle->buffer_mutex); +#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 0, 0) + rc = vb2_qbuf(&handle->queue, NULL, p); +#else + rc = vb2_qbuf(&handle->queue, p); +#endif + mutex_unlock(&handle->buffer_mutex); + return rc; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int rc = 0; + + rc = vb2_dqbuf(&handle->queue, p, file->f_flags & O_NONBLOCK); + p->field = V4L2_FIELD_NONE; + p->sequence = handle->sequence++; + return rc; +} + +static int vidioc_expbuf(struct file *file, void *priv, + struct v4l2_exportbuffer *p) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + + pr_debug("enter %s\n", __func__); + return vb2_expbuf(&handle->queue, p); +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + + pr_debug("enter %s\n", __func__); + return vb2_streamon(&handle->queue, i); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int rc; + + pr_debug("enter %s\n", __func__); + + mutex_lock(&handle->buffer_mutex); + rc = vb2_streamoff(&handle->queue, i); + mutex_unlock(&handle->buffer_mutex); + return rc; +} + +static int vidioc_enum_input(struct file *filep, void *fh, + struct v4l2_input *input) +{ + if (input->index > 0) + return -EINVAL; + + strlcpy(input->name, "camera", sizeof(input->name)); + input->type = V4L2_INPUT_TYPE_CAMERA; + + return 0; +} + +static int vidioc_g_input(struct file *filep, void *fh, unsigned int *input) +{ + *input = 0; + return 0; +} + +static int vidioc_s_input(struct file *filep, void *fh, unsigned int input) +{ + return input == 0 ? 0 : -EINVAL; +} + +static int vidioc_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *fsize) +{ + struct viv_video_device *dev = video_drvdata(file); + struct viv_video_file *handle = priv_to_handle(file->private_data); + int i; + + if (dev->modeinfocount == 0) { + viv_post_simple_event(VIV_VIDEO_EVENT_CREATE_PIPELINE, + handle->streamid, &handle->vfh, true); + } + + if (fsize->index >= dev->modeinfocount) + return -EINVAL; + + for (i = 0; i < dev->formatscount; ++i) + if (dev->formats[i].fourcc == fsize->pixel_format) + break; + + if (i == dev->formatscount) + return -EINVAL; + + fsize->stepwise.min_width = 176; + fsize->stepwise.max_width = dev->modeinfo[fsize->index].w; + fsize->stepwise.step_width = 16; + fsize->stepwise.min_height = 144; + fsize->stepwise.max_height = dev->modeinfo[fsize->index].h; + fsize->stepwise.step_height = 8; + + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; + + return 0; +} + +static inline void update_timeperframe(struct file *file) +{ + struct viv_video_device *dev = video_drvdata(file); + int i; + + if (dev->timeperframe.numerator == 0 || + dev->timeperframe.denominator == 0) { + dev->timeperframe.numerator = 1; + dev->timeperframe.denominator = 30; + for (i = 0; i < dev->modeinfocount; ++i) { + if (dev->fmt.fmt.pix.width == dev->modeinfo[i].w && + dev->fmt.fmt.pix.height == dev->modeinfo[i].h) { + dev->timeperframe.denominator = + dev->modeinfo[i].fps; + break; + } + } + } +} + +static int vidioc_g_parm(struct file *file, void *fh, + struct v4l2_streamparm *a) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + + if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + update_timeperframe(file); + + memset(&a->parm, 0, sizeof(a->parm)); + a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + a->parm.capture.timeperframe = handle->vdev->timeperframe; + return 0; +} + +static int vidioc_s_parm(struct file *file, void *fh, + struct v4l2_streamparm *a) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct viv_video_device *vdev = handle->vdev; + struct v4l2_event event; + struct viv_video_event *v_event; + + if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (a->parm.capture.timeperframe.numerator == 0 || + a->parm.capture.timeperframe.denominator == 0) { + update_timeperframe(file); + memset(&a->parm, 0, sizeof(a->parm)); + a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + a->parm.capture.timeperframe = handle->vdev->timeperframe; + return 0; + } + handle->vdev->timeperframe = a->parm.output.timeperframe; + if (vdev->ctrls.buf_va == NULL) + return -EINVAL; + + sprintf(vdev->ctrls.buf_va,"{:;:%d}",handle->vdev->timeperframe.denominator); + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = 0; + v_event->file = &handle->vfh; + v_event->sync = true; + v_event->addr = vdev->ctrls.buf_pa; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_EXTCTRL; + + viv_post_event(&event, &handle->vfh, true); + + return 0; +} + +static int vidioc_enum_frameintervals(struct file *filp, void *priv, + struct v4l2_frmivalenum *fival) +{ + struct viv_video_device *dev = video_drvdata(filp); + struct viv_video_file *handle = priv_to_handle(filp->private_data); + int i; + + if (dev->modeinfocount == 0) { + viv_post_simple_event(VIV_VIDEO_EVENT_CREATE_PIPELINE, + handle->streamid, &handle->vfh, true); + } + + for (i = 0; i < dev->formatscount; ++i) + if (dev->formats[i].fourcc == fival->pixel_format) + break; + + if (i == dev->formatscount) + return -EINVAL; + + if (fival->index >= dev->modeinfo[0].fps) + return -EINVAL; + + if (fival->width % 16 || fival->height % 8 || + fival->width < 176 || fival->height < 144 || + fival->width > dev->modeinfo[0].w || + fival->height > dev->modeinfo[0].h) + return -EINVAL; + + fival->discrete.numerator = 1; + fival->discrete.denominator = dev->modeinfo[0].fps - fival->index; + fival->type = V4L2_FRMSIZE_TYPE_DISCRETE; + + return 0; +} + +static int vidioc_g_pixelaspect(struct file *file, void *fh, + int buf_type, struct v4l2_fract *aspect) +{ + if (buf_type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + pr_debug("%s not implemented\n", __func__); + return 0; +} + +static int vidioc_g_selection(struct file *file, void *fh, + struct v4l2_selection *s) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct viv_video_device *vdev = handle->vdev; + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (vdev->modeinfocount == 0) { + viv_post_simple_event(VIV_VIDEO_EVENT_CREATE_PIPELINE, + handle->streamid, &handle->vfh, true); + } + + switch (s->target) { + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + s->r.left = 0; + s->r.top = 0; + s->r.width = vdev->compose.width; + s->r.height = vdev->compose.height; + break; + case V4L2_SEL_TGT_CROP: + s->r = vdev->crop; + break; + + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + s->r.left = 0; + s->r.top = 0; + s->r.width = 3840; + s->r.height = 2160; + break; + case V4L2_SEL_TGT_COMPOSE: + s->r = vdev->compose; + break; + default: + return -EINVAL; + } + return 0; +} + +static int vidioc_s_selection(struct file *file, void *fh, + struct v4l2_selection *s) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct viv_video_device *vdev = handle->vdev; + struct v4l2_rect *r; + struct v4l2_event event; + struct viv_video_event *v_event; + struct viv_rect *rect = (struct viv_rect *)handle->event_buf.va; + int rc; + int crop_flag = 1; + + if (!rect) + return -ENOMEM; + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (vdev->modeinfocount == 0) { + viv_post_simple_event(VIV_VIDEO_EVENT_CREATE_PIPELINE, + handle->streamid, &handle->vfh, true); + } + + switch (s->target) { + case V4L2_SEL_TGT_CROP: + r = &vdev->crop; + break; + case V4L2_SEL_TGT_COMPOSE: + r = &vdev->compose; + break; + default: + return -EINVAL; + } + + if (s->r.top < 0 || s->r.left < 0) + return -EINVAL; + + if (s->r.width == 0 || s->r.height == 0 || + s->r.width > 3840 || s->r.height > 2160) + return -EINVAL; + + if (s->target == V4L2_SEL_TGT_CROP) { + if (s->r.left + s->r.width > vdev->compose.width || + s->r.top + s->r.height > vdev->compose.height) + return -EINVAL; + } + + if (s->target == V4L2_SEL_TGT_COMPOSE) { + if (vdev->crop.top == 0 && + vdev->crop.left == 0 && + vdev->crop.width == vdev->compose.width && + vdev->crop.height == vdev->compose.height) { + crop_flag = 0; + } + } + + rect->left = s->r.left; + rect->top = s->r.top; + rect->width = s->r.width; + rect->height = s->r.height; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = handle->streamid; + v_event->file = &(handle->vfh); + v_event->sync = true; + v_event->addr = handle->event_buf.pa; + event.type = VIV_VIDEO_EVENT_TYPE; + if (s->target == V4L2_SEL_TGT_CROP) + event.id = VIV_VIDEO_EVENT_SET_CROP; + else + event.id = VIV_VIDEO_EVENT_SET_COMPOSE; + rc = viv_post_event(&event, &handle->vfh, true); + if (rc == 0) { + s->r.left = rect->left; + s->r.top = rect->top; + s->r.width = rect->width; + s->r.height = rect->height; + *r = s->r; + if (s->target == V4L2_SEL_TGT_COMPOSE && crop_flag == 0) { + vdev->crop.width = vdev->compose.width; + vdev->crop.height = vdev->compose.height; + } + } + return rc; +} + +int viv_gen_g_ctrl(struct v4l2_ctrl *ctrl) +{ + struct viv_custom_ctrls *cc = + container_of(ctrl->handler, struct viv_custom_ctrls, handler); + struct viv_video_device *vdev = + container_of(cc, struct viv_video_device, ctrls); + struct v4l2_event event; + struct viv_video_event *v_event; + struct v4l2_ctrl_data *p_data; + struct v4l2_ext_control *p_ctrl; + + pr_debug("%s:ctrl->id=0x%x\n", __func__, ctrl->id); + memset(&event, 0, sizeof(event)); + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->file = NULL; + v_event->sync = true; + v_event->addr = vdev->ctrls.buf_pa; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_EXTCTRL2; + + if(!video_event_subscribed(vdev->video, &event, RETRY_TIMES_MAX)) { + pr_err("%s: unsubscribed event id =%d type=0x%08x", + __func__, event.id, event.type); + return -EINVAL; + } + + p_data = (struct v4l2_ctrl_data *)vdev->ctrls.buf_va; + if (unlikely(!p_data)) + return -ENOMEM; + + memset(p_data, 0, sizeof(*p_data)); + p_data->dir = V4L2_CTRL_GET; + p_data->ctrls.count = 1; + p_ctrl = nextof(p_data, struct v4l2_ext_control *); + p_ctrl->id = ctrl->id; + + reinit_completion(&vdev->ctrls.wait); + + v4l2_event_queue(vdev->video, &event); + + if (wait_for_completion_timeout(&vdev->ctrls.wait, + msecs_to_jiffies(VIV_VIDEO_EVENT_TIMOUT_MS)) == 0) { + pr_err("connecting to server timed out (g)!"); + *ctrl->p_new.p_s32 = *ctrl->p_cur.p_s32; + return 0; + } + + if (p_ctrl->id == ctrl->id && !p_data->ret) { + *ctrl->p_new.p_s32 = p_ctrl->value; + return 0; + } + return -EINVAL; +} + +int viv_gen_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct viv_custom_ctrls *cc = + container_of(ctrl->handler, struct viv_custom_ctrls, handler); + struct viv_video_device *vdev = + container_of(cc, struct viv_video_device, ctrls); + struct v4l2_event event; + struct viv_video_event *v_event; + struct v4l2_ctrl_data *p_data; + struct v4l2_ext_control *p_ctrl; + + pr_debug("%s:ctrl->id=0x%x\n", __func__, ctrl->id); + memset(&event, 0, sizeof(event)); + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->file = NULL; + v_event->sync = true; + v_event->addr = vdev->ctrls.buf_pa; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_EXTCTRL2; + + if(!video_event_subscribed(vdev->video, &event, RETRY_TIMES_MAX)) { + pr_err("%s: unsubscribed event id =%d type=0x%08x", + __func__, event.id, event.type); + return -EINVAL; + } + + p_data = (struct v4l2_ctrl_data *)vdev->ctrls.buf_va; + if (unlikely(!p_data)) + return -ENOMEM; + + memset(p_data, 0, sizeof(*p_data)); + p_data->dir = V4L2_CTRL_SET; + p_data->ctrls.count = 1; + p_ctrl = nextof(p_data, struct v4l2_ext_control *); + p_ctrl->id = ctrl->id; + p_ctrl->value = *ctrl->p_new.p_s32; + + reinit_completion(&vdev->ctrls.wait); + + v4l2_event_queue(vdev->video, &event); + + if (wait_for_completion_timeout(&vdev->ctrls.wait, + msecs_to_jiffies(VIV_VIDEO_EVENT_TIMOUT_MS)) == 0) { + pr_err("connecting to server timed out (s)!"); + return 0; + } + + if (p_ctrl->id == ctrl->id && !p_data->ret) + return 0; + return -EINVAL; +} + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = video_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_expbuf = vidioc_expbuf, + .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_subscribe_event = subscribe_event, + .vidioc_unsubscribe_event = unsubscribe_event, + .vidioc_default = private_ioctl, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_enum_framesizes = vidioc_enum_framesizes, + .vidioc_enum_frameintervals = vidioc_enum_frameintervals, + .vidioc_g_parm = vidioc_g_parm, + .vidioc_s_parm = vidioc_s_parm, + .vidioc_g_pixelaspect = vidioc_g_pixelaspect, + .vidioc_g_selection = vidioc_g_selection, + .vidioc_s_selection = vidioc_s_selection, +}; + +/* sys /dev/mem can't map large memory size */ +static int viv_private_mmap(struct file *file, struct vm_area_struct *vma) +{ + /* Map reserved video memory. */ + if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) + return -EAGAIN; + return 0; +} + +int vidioc_mmap(struct file *file, struct vm_area_struct *vma) +{ + int rc; + struct viv_video_file *handle = priv_to_handle(file->private_data); + +#ifndef ENABLE_IRQ + struct viv_video_device *dev = video_drvdata(file); + struct reserved_mem *rmem = (struct reserved_mem *)dev->rmem; + unsigned long reserved_base_addr = 0; + if (!rmem) + reserved_base_addr = 0; + else + reserved_base_addr = rmem->base; +#endif + +#ifdef ENABLE_IRQ + if (handle->streamid < 0) +#else + if (vma->vm_pgoff >= (reserved_base_addr >> PAGE_SHIFT)) +#endif + rc = viv_private_mmap(file, vma); + else + rc = vb2_mmap(&handle->queue, vma); + return rc; +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int rc = 0; + + if (handle->streamid < 0) { + poll_wait(file, &handle->vfh.wait, wait); + + if (v4l2_event_pending(&handle->vfh)) + rc = POLLIN | POLLRDNORM; + } else { + mutex_lock(&handle->buffer_mutex); + rc = vb2_poll(&handle->queue, file, wait) | + v4l2_ctrl_poll(file, wait); + mutex_unlock(&handle->buffer_mutex); + } + return rc; +} + +static struct v4l2_file_operations video_ops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_close, + .poll = video_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = vidioc_mmap, +}; + +static void pdev_release(struct device *dev) +{ + pr_debug("enter %s\n", __func__); +} + +static struct platform_device viv_pdev = { + .name = "vvcam-video", + .dev.release = pdev_release, +}; + +static int viv_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct v4l2_event event; + struct viv_video_event *v_event; + struct viv_custom_ctrls *cc = + container_of(ctrl->handler, struct viv_custom_ctrls, handler); + struct viv_video_device *vdev = + container_of(cc, struct viv_video_device, ctrls); + int ret = -1; + char *szbuf = NULL; + unsigned long timeout = + msecs_to_jiffies(VIV_VIDEO_EVENT_TIMOUT_MS); + + switch (ctrl->id) { + case V4L2_CID_VIV_STRING: { + ret = 0; + szbuf = (char *)vdev->ctrls.buf_va; + if (!ctrl->p_new.p_char || !szbuf) + return -EINVAL; + strcpy(szbuf, ctrl->p_new.p_char); + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = 0; + v_event->file = NULL; + v_event->sync = true; + v_event->addr = vdev->ctrls.buf_pa; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_EXTCTRL; + + if(!video_event_subscribed(vdev->video, &event, RETRY_TIMES_MAX)) { + pr_err("%s: unsubscribed event id =%d type=0x%08x", + __func__, event.id, event.type); + return -EINVAL; + } + + reinit_completion(&vdev->ctrls.wait); + + v4l2_event_queue(vdev->video, &event); + + if (!wait_for_completion_timeout(&vdev->ctrls.wait, timeout)) + ret = -ETIMEDOUT; + strcpy(ctrl->p_new.p_char, szbuf); + break; + } + } + return ret; +} + +static const struct v4l2_ctrl_ops viv_ctrl_ops = { + .s_ctrl = viv_s_ctrl, +}; + +static const struct v4l2_ctrl_config viv_ext_ctrl = { + .ops = &viv_ctrl_ops, + .id = V4L2_CID_VIV_STRING, + .name = "viv_ext_ctrl", + .type = V4L2_CTRL_TYPE_STRING, + .max = VIV_JSON_BUFFER_SIZE-1, + .step = 1, +}; + +#ifdef ENABLE_IRQ +static int viv_notifier_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *sd, struct v4l2_async_subdev *asd) +{ + int i; + struct viv_video_device *dev = container_of(notifier, + struct viv_video_device, subdev_notifier); + + if (!dev) + return 0; + + for (i = 0; i < dev->asdcount; ++i) { + if (dev->asd[i]->match_type == V4L2_ASYNC_MATCH_FWNODE) { + if (sd->dev && dev->asd[i]->match.fwnode == + of_fwnode_handle(sd->dev->of_node)) { + dev->subdevs[dev->sdcount] = sd; + dev->sdcount++; + break; + } + } else if (dev->asd[i]->match_type == + V4L2_ASYNC_MATCH_DEVNAME) { + if (sd->dev && !strcmp(dev->asd[i]->match.device_name, + dev_name(sd->dev))) { + dev->subdevs[dev->sdcount] = sd; + dev->sdcount++; + break; + } + } + } + return 0; +} + +static int viv_notifier_complete(struct v4l2_async_notifier *notifier) +{ + struct viv_video_device *dev = container_of(notifier, + struct viv_video_device, subdev_notifier); + int rc; + + if (!dev) + return 0; + + if (dev->sdcount > 0) { + mutex_lock(&dev->mdev->graph_mutex); + rc = viv_create_default_links(dev); + mutex_unlock(&dev->mdev->graph_mutex); + + if (rc) { + pr_err("failed to create media links!\n"); + return rc; + } + } + + return v4l2_device_register_subdev_nodes(dev->v4l2_dev); +} + +static const struct v4l2_async_notifier_operations sd_async_notifier_ops = { + .bound = viv_notifier_bound, + .complete = viv_notifier_complete, +}; + +static int viv_mdev_link_notify(struct media_link *link, unsigned int flags, + unsigned int notification) +{ + return 0; +} + +static const struct media_device_ops viv_mdev_ops = { + .link_notify = viv_mdev_link_notify, +}; + +static int viv_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static const struct media_entity_operations viv_media_ops = { + .link_setup = viv_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +static void viv_buf_notify(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf) +{ + struct viv_video_file *fh; + struct viv_video_device *vdev; + u64 cur_ts, interval; + u32 fps; + int i; + + if (!buf || buf->vb.vb2_buf.state != VB2_BUF_STATE_ACTIVE) + return; + + fh = container_of(buf->vb.vb2_buf.vb2_queue, + struct viv_video_file, queue); + vdev = fh->vdev; + if (!vdev->active) + return; + buf->vb.vb2_buf.planes[DEF_PLANE_NO].bytesused = + vdev->fmt.fmt.pix.sizeimage; + cur_ts = ktime_get_ns(); +#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 0, 0) + buf->vb.vb2_buf.timestamp = cur_ts; +#endif + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + /* print fps info for debugging purpose */ + interval = ktime_us_delta(cur_ts,vdev->last_ts); + for (i = 0; i < VIDEO_NODE_NUM; i++) { + if (vdev->id == i) { + if (vdev->duration >= 3 * 1000000/*ms*/) { + vdev->loop_cnt[i]++; + if (vdev->loop_cnt[i] >= 10) { + if (vdev->frame_flag) { + fps = vdev->frameCnt[i] * 100000000 / vdev->duration; + pr_info("###### video%d(%d) %d.%02d fps ######\n", + vdev->video->num, vdev->id, + fps / 100, fps % 100); + } else { + vdev->frame_flag = true; + } + vdev->loop_cnt[i] = 0; + } + vdev->frameCnt[i] = 0; + vdev->duration = 0; + } else if (interval > 0) { + vdev->frameCnt[i]++; + vdev->duration += interval; + } + } + } + vdev->last_ts = cur_ts; +} + +static const struct vvbuf_ops viv_buf_ops = { + .notify = viv_buf_notify, +}; +#endif + +struct dev_node { + enum v4l2_async_match_type match_type; + struct device_node *node; + int id; + const char *name; +}; +static const char * const dwe_dev_compat_name[] = { + "32e30000.dwe", "fsl,fake-imx8mp-dwe.1"}; + +static inline int viv_find_compatible_nodes(struct dev_node *nodes, int size) +{ + static const char * const compat_name[] = { + ISP_COMPAT_NAME}; + struct device_node *node, *avail; + int i, rc, id, cnt = 0; + + for (i = 0; i < ARRAY_SIZE(compat_name) && cnt < size; ++i) { + node = NULL; + for (; cnt < size;) { + node = of_find_compatible_node(node, + NULL, compat_name[i]); + if (!node) + break; + avail = NULL; + id = -1; + rc = fwnode_property_read_u32( + of_fwnode_handle(node), "id", &id); + if (rc) { + if (of_device_is_available(node)) + avail = node; + } else if (of_device_is_available(node)) + avail = node; + + if (avail) { + nodes[cnt].node = avail; + nodes[cnt].id = id; + nodes[cnt].match_type = V4L2_ASYNC_MATCH_FWNODE; + cnt++; + + nodes[cnt].id = id; + nodes[cnt].match_type = V4L2_ASYNC_MATCH_DEVNAME; + nodes[cnt].name = dwe_dev_compat_name[id]; + cnt++; + } + } + } + return cnt; +} + +static struct reserved_mem * viv_find_isp_reserve_mem(int dev_id) +{ + int i,rc; + int id=0; + struct device_node *node = NULL; + struct device_node *mem_node; + + for (i=0; idev; + media_device_init(&mdev); +#endif + + memset(nodes, 0, sizeof(nodes)); + nodecount = viv_find_compatible_nodes(nodes, MAX_SUBDEVS_NUM); + for (i = 0; i < VIDEO_NODE_NUM && i*2 < nodecount; i++) { + if(nodes[i*2].node) { + video_id = nodes[i*2].id ; + if(video_id >= VIDEO_NODE_NUM) { + pr_err("%s: id %d is too large (id > %d) \n", + __func__, video_id, VIDEO_NODE_NUM); + rc = -EINVAL; + goto probe_end; + } + + spin_lock_init(&file_list_lock[video_id]); + INIT_LIST_HEAD(&file_list_head[video_id]); + + vvdev[video_id] = kzalloc(sizeof(*vdev), GFP_KERNEL); + if (WARN_ON(!vvdev[video_id])) { + rc = -ENOMEM; + goto probe_end; + } + vdev = vvdev[video_id]; + vdev->id = video_id; + vdev->rmem = viv_find_isp_reserve_mem(vdev->id); + vdev->v4l2_dev = kzalloc(sizeof(*vdev->v4l2_dev), GFP_KERNEL); + if (WARN_ON(!vdev->v4l2_dev)) { + rc = -ENOMEM; + goto probe_end; + } + init_completion(&vdev->subscribed_wait); + vdev->subscribed_cnt = 0; + vdev->video = video_device_alloc(); + vdev->video->v4l2_dev = vdev->v4l2_dev; + rc = v4l2_device_register(&pdev->dev, vdev->video->v4l2_dev); + if (WARN_ON(rc < 0)) + goto register_fail; + sprintf(vdev->video->name, "viv_v4l2%d", video_id); + v4l2_ctrl_handler_init(&vdev->ctrls.handler, 1); + vdev->ctrls.request = v4l2_ctrl_new_custom(&vdev->ctrls.handler, + &viv_ext_ctrl, NULL); + create_controls(&vdev->ctrls.handler); + + vdev->video->release = video_device_release; + vdev->video->fops = &video_ops; + vdev->video->ioctl_ops = &video_ioctl_ops; + vdev->video->minor = -1; +#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 10, 0) + vdev->video->vfl_type = VFL_TYPE_VIDEO; +#else + vdev->video->vfl_type = VFL_TYPE_GRABBER; +#endif + vdev->video->ctrl_handler = &vdev->ctrls.handler; +#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 0, 0) + vdev->video->device_caps = + V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; +#endif +#ifdef ENABLE_IRQ + video_set_drvdata(vdev->video, vdev); + + vvbuf_ctx_init(&vdev->bctx); + vdev->bctx.ops = &viv_buf_ops; + + vdev->mdev = &mdev; + vdev->v4l2_dev->mdev = &mdev; + + vdev->video->entity.name = vdev->video->name; + vdev->video->entity.obj_type = MEDIA_ENTITY_TYPE_VIDEO_DEVICE; + vdev->video->entity.function = MEDIA_ENT_F_IO_V4L; + vdev->video->entity.ops = &viv_media_ops; + + vdev->pad.flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT; + rc = media_entity_pads_init(&vdev->video->entity, + 1, &vdev->pad); + if (WARN_ON(rc < 0)) + goto register_fail; + + v4l2_async_notifier_init(&vdev->subdev_notifier); + vdev->subdev_notifier.ops = &sd_async_notifier_ops; +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 10, 0) + rc = video_register_device(vdev->video, VFL_TYPE_VIDEO, -1); +#else + rc = video_register_device(vdev->video, VFL_TYPE_GRABBER, -1); +#endif + if (WARN_ON(rc < 0)) + goto register_fail; + +#ifdef ENABLE_IRQ + for (j = 0; j < nodecount; ++j) { + if (nodes[j].id == video_id) { + switch (nodes[j].match_type) { + case V4L2_ASYNC_MATCH_FWNODE: + asd = v4l2_async_notifier_add_fwnode_subdev( + &vdev->subdev_notifier, + of_fwnode_handle(nodes[j].node), + sizeof(struct v4l2_async_subdev)); + break; + case V4L2_ASYNC_MATCH_DEVNAME: + asd = v4l2_async_notifier_add_devname_subdev( + &vdev->subdev_notifier, + nodes[j].name, + sizeof(struct v4l2_async_subdev)); + break; + default: + asd = NULL; + break; + } + if (asd) { + vdev->asd[vdev->asdcount] = asd; + vdev->asdcount++; + } + } + } + + rc = v4l2_async_notifier_register(vdev->v4l2_dev, + &vdev->subdev_notifier); + if (WARN_ON(rc < 0)) + goto register_fail; +#else + video_set_drvdata(vdev->video, vdev); + + rc = v4l2_device_register_subdev_nodes(vdev->v4l2_dev); +#endif + + vdev->ctrls.buf_va = kmalloc(VIV_JSON_BUFFER_SIZE, GFP_KERNEL); + vdev->ctrls.buf_pa = __pa(vdev->ctrls.buf_va); + init_completion(&vdev->ctrls.wait); + + vdev->fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + vdev->fmt.fmt.pix.field = V4L2_FIELD_NONE; + vdev->fmt.fmt.pix.colorspace = V4L2_COLORSPACE_REC709; + + if (sizeof(vdev->formats) >= sizeof(formats)) { + memcpy(vdev->formats, formats, sizeof(formats)); + vdev->formatscount = ARRAY_SIZE(formats); + } + for (m = 0; m < VIDEO_NODE_NUM; m++) { + vdev->loop_cnt[m] = 0; + vdev->frameCnt[m] = 0; + } + vdev->duration = 0; + vdev->last_ts = 0; + + continue; +register_fail: + video_device_release(vdev->video); + } + } +#ifdef ENABLE_IRQ + if (!rc) + rc = media_device_register(&mdev); +#endif +probe_end: + return rc; +} + +static int viv_video_remove(struct platform_device *pdev) +{ + struct viv_video_device *vdev; + int i; + + for (i = VIDEO_NODE_NUM-1; i >= 0; i--) { + vdev = vvdev[i]; + if (!vdev || !vdev->video) + continue; +#ifdef ENABLE_IRQ + media_entity_cleanup(&vdev->video->entity); + v4l2_async_notifier_cleanup(&vdev->subdev_notifier); + v4l2_async_notifier_unregister(&vdev->subdev_notifier); + v4l2_device_unregister(vdev->v4l2_dev); + kfree(vdev->v4l2_dev); +#endif + video_unregister_device(vdev->video); +#ifdef ENABLE_IRQ + vvbuf_ctx_deinit(&vdev->bctx); +#else + v4l2_device_disconnect(vdev->video->v4l2_dev); + v4l2_device_put(vdev->video->v4l2_dev); +#endif + + kfree(vdev->ctrls.buf_va); + v4l2_ctrl_handler_free(&vdev->ctrls.handler); + kfree(vvdev[i]); + vvdev[i] = NULL; + } + +#ifdef ENABLE_IRQ + media_device_unregister(&mdev); + media_device_cleanup(&mdev); +#endif + return 0; +} + +static struct platform_driver viv_video_driver = { + .probe = viv_video_probe, + .remove = viv_video_remove, + .driver = { + .name = "vvcam-video", + .owner = THIS_MODULE, + }, +}; + +static int __init viv_video_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + ret = platform_device_register(&viv_pdev); + if (ret) { + pr_err("register platform device failed.\n"); + return ret; + } + + ret = platform_driver_register(&viv_video_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + platform_device_unregister(&viv_pdev); + return ret; + } + return ret; +} + +static void __exit viv_video_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_video_driver); + msleep(100); + platform_device_unregister(&viv_pdev); +} + +module_init(viv_video_init_module); +module_exit(viv_video_exit_module); + +MODULE_DESCRIPTION("Verisilicon V4L2 video driver"); +MODULE_AUTHOR("Verisilicon ISP SW Team"); +MODULE_LICENSE("GPL v2"); diff --git a/vvcam/v4l2/video/video.h b/vvcam/v4l2/video/video.h new file mode 100755 index 0000000..b0aa6e4 --- /dev/null +++ b/vvcam/v4l2/video/video.h @@ -0,0 +1,141 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_VIDEO_H_ +#define _ISP_VIDEO_H_ + +#include +#include +#include +#include +#include +#include + +#include "viv_video_kevent.h" +#include "vvbuf.h" + +#define MAX_SUBDEVS_NUM (8) +#define VIDEO_NODE_NUM (2) + +struct viv_custom_ctrls { + struct v4l2_ctrl_handler handler; + struct v4l2_ctrl *request; + uint64_t buf_pa; + void __iomem *buf_va; + struct completion wait; +}; + +struct viv_video_fmt { + int fourcc; + int depth; + int bpp; +}; + +struct viv_video_device { + struct vvbuf_ctx bctx; + struct video_device *video; + struct v4l2_device *v4l2_dev; + struct v4l2_async_notifier subdev_notifier; + struct v4l2_subdev *subdevs[MAX_SUBDEVS_NUM]; + int sdcount; + struct v4l2_async_subdev *asd[MAX_SUBDEVS_NUM]; + int asdcount; + struct media_device *mdev; + struct media_pad pad; + struct v4l2_format fmt; + struct v4l2_fract timeperframe; + struct v4l2_rect crop, compose; + struct viv_custom_ctrls ctrls; + struct vvcam_constant_modeinfo modeinfo[20]; + int modeinfocount; + struct viv_video_fmt formats[20]; + int formatscount; + int id; + struct viv_caps_mode_s caps_mode; + int event_result; + bool dweEnabled; + struct viv_caps_supports caps_supports; + u64 duration, last_ts, frameCnt[VIDEO_NODE_NUM]; + u32 loop_cnt[VIDEO_NODE_NUM]; + struct completion subscribed_wait; + int subscribed_cnt; + int active; + void *rmem; + bool frame_flag; +}; + +struct viv_video_file { + struct v4l2_fh vfh; + int streamid; + int state; /* 0-free,1-ready,2-streaming,-1-closed */ + int sequence; + bool req; + bool capsqueried; + struct vb2_queue queue; + struct mutex event_mutex; + struct mutex buffer_mutex; + struct completion wait; + struct list_head entry; + struct viv_video_device *vdev; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + struct list_head extdmaqueue; +#endif + struct { + uint64_t pa; + void *va; + } event_buf; +}; + +#define priv_to_handle(priv) container_of(priv, struct viv_video_file, vfh) +#define queue_to_handle(__q) container_of(__q, struct viv_video_file, queue) + +#endif /* _ISP_VIDEO_H_ */ diff --git a/vvcam/v4l2/video/vvbuf.c b/vvcam/v4l2/video/vvbuf.c new file mode 100755 index 0000000..6c35138 --- /dev/null +++ b/vvcam/v4l2/video/vvbuf.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include + +#include "vvbuf.h" + +#ifdef ENABLE_IRQ + +void vvbuf_ctx_init(struct vvbuf_ctx *ctx) +{ + if (unlikely(!ctx)) + return; + + spin_lock_init(&ctx->irqlock); + INIT_LIST_HEAD(&ctx->dmaqueue); +} + +void vvbuf_ctx_deinit(struct vvbuf_ctx *ctx) +{ + /*nop*/ +} + +struct vb2_dc_buf *vvbuf_try_dqbuf(struct vvbuf_ctx *ctx) +{ + struct vb2_dc_buf *buf; + unsigned long flags; + + if (unlikely(!ctx)) + return NULL; + + spin_lock_irqsave(&ctx->irqlock, flags); + if (list_empty(&ctx->dmaqueue)) { + spin_unlock_irqrestore(&ctx->irqlock, flags); + return NULL; + } + + buf = list_first_entry(&ctx->dmaqueue, struct vb2_dc_buf, irqlist); + spin_unlock_irqrestore(&ctx->irqlock, flags); + return buf; +} + +void vvbuf_try_dqbuf_done(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf) +{ + unsigned long flags; + + if (unlikely(!ctx)) + return; + + spin_lock_irqsave(&ctx->irqlock, flags); + if (list_empty(&ctx->dmaqueue)) { + spin_unlock_irqrestore(&ctx->irqlock, flags); + return; + } + + if (buf == list_first_entry(&ctx->dmaqueue, + struct vb2_dc_buf, irqlist)) + list_del(&buf->irqlist); + spin_unlock_irqrestore(&ctx->irqlock, flags); +} + +void vvbuf_ready(struct vvbuf_ctx *ctx, struct media_pad *pad, + struct vb2_dc_buf *buf) +{ + struct video_device *vdev; + struct v4l2_subdev *subdev; + struct vvbuf_ctx *rctx = NULL; + + if (unlikely(!pad || !buf)) + return; + + pad = media_entity_remote_pad(pad); + if (!pad) + return; + + if (is_media_entity_v4l2_video_device(pad->entity)) { + vdev = media_entity_to_video_device(pad->entity); + if (vdev) + rctx = (struct vvbuf_ctx *)video_get_drvdata(vdev); + } else if (is_media_entity_v4l2_subdev(pad->entity)) { + subdev = media_entity_to_v4l2_subdev(pad->entity); + if (subdev) + rctx = (struct vvbuf_ctx *)v4l2_get_subdevdata(subdev); + } + + rctx += pad->index; + buf->pad = pad; + + if (rctx && rctx->ops && rctx->ops->notify) + rctx->ops->notify(rctx, buf); +} + +#endif diff --git a/vvcam/v4l2/video/vvbuf.h b/vvcam/v4l2/video/vvbuf.h new file mode 100755 index 0000000..cfc6bae --- /dev/null +++ b/vvcam/v4l2/video/vvbuf.h @@ -0,0 +1,89 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVBUF_H_ +#define _VVBUF_H_ + +#include +#include +#include +#include +#include + +struct vb2_dc_buf { + struct vb2_v4l2_buffer vb; + struct media_pad *pad; + struct list_head irqlist; + dma_addr_t dma; + int flags; +}; + +struct vvbuf_ctx; + +struct vvbuf_ops { + void (*notify)(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf); +}; + +struct vvbuf_ctx { + spinlock_t irqlock; + struct list_head dmaqueue; + const struct vvbuf_ops *ops; +}; + +void vvbuf_ctx_init(struct vvbuf_ctx *ctx); +void vvbuf_ctx_deinit(struct vvbuf_ctx *ctx); +struct vb2_dc_buf *vvbuf_try_dqbuf(struct vvbuf_ctx *ctx); +void vvbuf_try_dqbuf_done(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf); +void vvbuf_ready(struct vvbuf_ctx *ctx, struct media_pad *pad, + struct vb2_dc_buf *buf); + +#endif /* _VVBUF_H_ */ diff --git a/vvcam/v4l2/vse_driver.c b/vvcam/v4l2/vse_driver.c new file mode 100755 index 0000000..ad4426b --- /dev/null +++ b/vvcam/v4l2/vse_driver.c @@ -0,0 +1,246 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vse_driver.h" +#include "vse_ioctl.h" +#define DEVICE_NAME "vvcam-vse" + +int vse_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, 2, NULL); +} + +int vse_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +#ifdef CONFIG_COMPAT +static long vse_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct vse_device *vse_dev = v4l2_get_subdevdata(sd); + + return vse_priv_ioctl(&vse_dev->ic_dev, cmd, arg); +} + +long vse_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return vse_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long vse_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct vse_device *vse_dev = v4l2_get_subdevdata(sd); + + return vse_priv_ioctl(&^vse_dev->ic_dev, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +int vse_set_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static struct v4l2_subdev_core_ops vse_v4l2_subdev_core_ops = { + .ioctl = vse_ioctl, + .subscribe_event = vse_subscribe_event, + .unsubscribe_event = vse_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops vse_v4l2_subdev_video_ops = { + .s_stream = vse_set_stream, +}; + +static struct v4l2_subdev_ops vse_v4l2_subdev_ops = { + .core = &vse_v4l2_subdev_core_ops, + .video = &vse_v4l2_subdev_video_ops, +}; + +int vse_hw_probe(struct platform_device *pdev) +{ + struct vse_device *vse_dev; + int rc = 0; + + pr_info("enter %s\n", __func__); + vse_dev = kzalloc(sizeof(struct vse_device), GFP_KERNEL); + if (!vse_dev) { + rc = -ENOMEM; + goto end; + } + + v4l2_subdev_init(&vse_dev->sd, &vse_v4l2_subdev_ops); + + snprintf(vse_dev->sd.name, sizeof(vse_dev->sd.name), DEVICE_NAME); + vse_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + vse_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + vse_dev->sd.owner = THIS_MODULE; + v4l2_set_subdevdata(&vse_dev->sd, vse_dev); + vse_dev->vd = kzalloc(sizeof(*vse_dev->vd), GFP_KERNEL); + if (WARN_ON(!vse_dev->vd)) { + rc = -ENOMEM; + goto end; + } + + rc = v4l2_device_register(&(pdev->dev), vse_dev->vd); + if (WARN_ON(rc < 0)) + goto end; + + rc = v4l2_device_register_subdev(vse_dev->vd, &vse_dev->sd); + if (rc) { + pr_err("failed to register subdev %d\n", rc); + goto end; + } + vse_dev->ic_dev.base = ioremap(VSE_REG_BASE, VSE_REG_SIZE); +#ifdef VSE_REG_RESET + vse_dev->ic_dev.reset = ioremap(VSE_REG_RESET, 4); +#endif + pr_info("vse ioremap addr: 0x%08x 0x%08x %px", VSE_REG_BASE, + VSE_REG_SIZE, vse_dev->ic_dev.base); + platform_set_drvdata(pdev, vse_dev); + rc = v4l2_device_register_subdev_nodes(vse_dev->vd); + return rc; +end: + return rc; +} + +int vse_hw_remove(struct platform_device *pdev) +{ + struct vse_device *vse = platform_get_drvdata(pdev); + + pr_info("enter %s\n", __func__); + + if (!vse) + return -1; + + v4l2_device_unregister_subdev(&vse->sd); + v4l2_device_disconnect(vse->vd); + v4l2_device_put(vse->vd); + + iounmap(vse->ic_dev.base); + kzfree(vse); + return 0; +} + +static struct platform_driver viv_vse_driver = { + .probe = vse_hw_probe, + .remove = vse_hw_remove, + .driver = { + .name = DEVICE_NAME, + .owner = THIS_MODULE, + } +}; + +static void vse_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +static struct platform_device viv_vse_pdev = { + .name = DEVICE_NAME, + .dev.release = vse_pdev_release, +}; + +static int __init viv_vse_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + ret = platform_device_register(&viv_vse_pdev); + if (ret) { + pr_err("register platform device failed.\n"); + return ret; + } + + ret = platform_driver_register(&viv_vse_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + platform_device_unregister(&viv_vse_pdev); + return ret; + } + return ret; +} + +static void __exit viv_vse_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_vse_driver); + platform_device_unregister(&viv_vse_pdev); +} + +module_init(viv_vse_init_module); +module_exit(viv_vse_exit_module); + +MODULE_AUTHOR("zhiye.yin@verisilicon.com"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("VSE"); +MODULE_VERSION("1.0"); diff --git a/vvcam/v4l2/vse_driver.h b/vvcam/v4l2/vse_driver.h new file mode 100755 index 0000000..f2d19ce --- /dev/null +++ b/vvcam/v4l2/vse_driver.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VSE_DRIVER_H_ +#define _VSE_DRIVER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "vse_dev.h" + +struct vse_device { + /* Driver private data */ + struct v4l2_subdev sd; + struct v4l2_device *vd; + struct vse_ic_dev ic_dev; +}; + +#endif /* _VSE_DRIVER_H_ */ diff --git a/vvcam/version/ISP8000L_V2008.mk b/vvcam/version/ISP8000L_V2008.mk new file mode 100755 index 0000000..aa4089a --- /dev/null +++ b/vvcam/version/ISP8000L_V2008.mk @@ -0,0 +1,30 @@ +EXTRA_CFLAGS += -DISP_EE +EXTRA_CFLAGS += -DISP_2DNR +EXTRA_CFLAGS += -DISP_2DNR_V2 +EXTRA_CFLAGS += -DISP_2DNR_V4 +EXTRA_CFLAGS += -DISP_2DNR_V5 +EXTRA_CFLAGS += -DISP_WDR_V4 +EXTRA_CFLAGS += -DISP_WDR_V4_20BIT +EXTRA_CFLAGS += -DISP_MIV2 +EXTRA_CFLAGS += -DISP_AEV2 +EXTRA_CFLAGS += -DISP_AEV2_V2 +EXTRA_CFLAGS += -DISP_AE_SHADOW +EXTRA_CFLAGS += -DISP_COMPAND +EXTRA_CFLAGS += -DISPVI_EXPAND_CHAN +EXTRA_CFLAGS += -DISP_DEMOSAIC2 +EXTRA_CFLAGS += -DISP_GREENEQUILIBRATE +EXTRA_CFLAGS += -DISP_RGBGC +EXTRA_CFLAGS += -DISP_HIST256 +EXTRA_CFLAGS += -DISP_CA +EXTRA_CFLAGS += -DISP_DUMY_HBLANK_CFG +EXTRA_CFLAGS += -DISP_HDR_STITCH +EXTRA_CFLAGS += -DISP_FILTER +EXTRA_CFLAGS += -DISP_3DNR_V3 +EXTRA_CFLAGS += -DISP_CPROC_10BIT +EXTRA_CFLAGS += -DISP_CPROC_SHD +EXTRA_CFLAGS += -DISP_LSC_V2 +EXTRA_CFLAGS += -DISP_HIST64 +EXTRA_CFLAGS += -DISP_MI_HDR +EXTRA_CFLAGS += -DISP_MI_PP_WRITE +EXTRA_CFLAGS += -DISP_RGBIR +EXTRA_CFLAGS += -DISP_MI_MCM_WR diff --git a/vvcam/vse/vse_dev.h b/vvcam/vse/vse_dev.h new file mode 100755 index 0000000..b6b94b1 --- /dev/null +++ b/vvcam/vse/vse_dev.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VSE_DEV_H_ +#define _VSE_DEV_H_ + +#define VSE_OUTPUT_CHANNEL_NUMBER 3 +#define VSE_INPUT_CHANNEL_NUMBER 6 +/* + * NOTICE NOTICE NOTICE: + * First scale output max resolution is 4096*2160 (max size 4096*2160*3 ) + * Second scale output max resolution is 1920*1080 + * Third scale output max resolution is 1280*720 + */ + +#ifndef __KERNEL__ +#define copy_from_user(a, b, c) vse_copy_data(a, b, c) +#define copy_to_user(a, b, c) vse_copy_data(a, b, c) + +typedef bool(*pVseReadBar) (uint32_t bar, uint32_t *data); +typedef bool(*pVseWriteBar) (uint32_t bar, uint32_t data); + +extern void vse_set_func(pVseReadBar read_func, pVseWriteBar write_func); +extern long vse_copy_data(void *dst, void *src, int size); + +#endif + +#include "vvdefs.h" + +struct vse_crop_size { + u32 left; + u32 right; + u32 top; + u32 bottom; +}; + +struct vse_size { + u32 width; + u32 height; +}; + +struct vse_format_conv_settings { + u32 in_format; + u32 out_format; +}; + +struct vse_mi_settings { + bool enable; + u32 out_format; + u32 width; + u32 height; +}; + +struct vse_params { + u32 src_w; + u32 src_h; + u32 in_format; + u32 input_select; + struct vse_crop_size crop_size[3]; + struct vse_size out_size[3]; + struct vse_format_conv_settings format_conv[3]; + bool resize_enable[3]; + struct vse_mi_settings mi_settings[3]; +}; + +struct vse_ic_dev { + struct vse_params params; + void __iomem *base; + void __iomem *reset; +}; + +#endif /* _VSE_DEV_H_ */ diff --git a/vvcam/vse/vse_ioctl.c b/vvcam/vse/vse_ioctl.c new file mode 100755 index 0000000..6f176aa --- /dev/null +++ b/vvcam/vse/vse_ioctl.c @@ -0,0 +1,699 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include "vse_driver.h" +#else +#include +#include +#include +#endif +#include "vse_ioctl.h" +#include "vse_regs.h" + +#ifndef __KERNEL__ +#ifdef HAL_CMODEL +#define VSE_REGISTER_OFFSET 0 +#else +#define VSE_REGISTER_OFFSET 0x500000 +#endif + +#define VSE_REGISTER_CTL 0x308254 + +pVseReadBar g_read_func; +pVseWriteBar g_write_func; + +void vse_set_func(pVseReadBar read_func, pVseWriteBar write_func) +{ + g_read_func = read_func; + g_write_func = write_func; +} + +void vse_write_reg(struct vse_ic_dev *dev, u32 offset, u32 val) +{ + g_write_func(VSE_REGISTER_OFFSET + offset, val); +} + +u32 vse_read_reg(struct vse_ic_dev *dev, u32 offset) +{ + u32 data; + + g_read_func(VSE_REGISTER_OFFSET + offset, &data); + return data; +} + +long vse_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); + return 0; +} +#else + +void vse_write_reg(struct vse_ic_dev *dev, u32 offset, u32 val) +{ + __raw_writel(val, dev->base + offset); +} + +u32 vse_read_reg(struct vse_ic_dev *dev, u32 offset) +{ + return __raw_readl(dev->base + offset); +} + +#endif + +int vse_reset(struct vse_ic_dev *dev) +{ + pr_info("enter %s\n", __func__); + +#ifdef VSE_REG_RESET + __raw_writel(0, dev->reset); + __raw_writel(1, dev->reset); +#endif + vse_write_reg(dev, VSE_REG_CTRL, 0x100); + return 0; +} + +void vse_triger_dma_read(struct vse_ic_dev *dev) +{ + u32 reg = vse_read_reg(dev, VSE_REG_CTRL); + + REG_SET_BIT(reg, VSE_CONTROL_DMA_FRAME_START_BIT, 1); + vse_write_reg(dev, VSE_REG_CTRL, reg); + vse_write_reg(dev, VSE_REG_DMA_CTRL, 5); +} + +void setMIBaseAddress(struct vse_ic_dev *dev, u32 width, u32 height, u32 format, + u64 addr, int channel) +{ + u32 stride = ALIGN_UP(width, 16); + u32 crSize = 0; + u32 yBaseAddr = addr; + u32 regAddress = VSE_MI_BASE(channel); + u32 crBaseAddr = 0; + u32 ysize = stride * height; + u32 cbSize = ysize; + u32 cbBaseAddr = yBaseAddr + ysize; + + if (ysize == 0) + return; + + switch (format) { + case MEDIA_PIX_FMT_YUV420SP: + cbSize /= 2; + crSize = 0; + break; + case MEDIA_PIX_FMT_YUV422SP: + break; + case MEDIA_PIX_FMT_YUV444: + case MEDIA_PIX_FMT_RGB888P: + crSize = ysize; + crBaseAddr = cbBaseAddr + cbSize; + break; + case MEDIA_PIX_FMT_RGB888: /* only supoort RGB interleave format. RGB RGB RGB .. */ + ysize *= 3; + cbSize = 0; + cbBaseAddr = 0; + break; + } + + vse_write_reg(dev, regAddress + VSE_REG_MI_Y_BASE_ADDR_INIT, yBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_Y_SIZE_INIT, ysize); + vse_write_reg(dev, regAddress + VSE_REG_MI_CB_BASE_ADDR_INIT, + cbBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_CB_SIZE_INIT, cbSize); + vse_write_reg(dev, regAddress + VSE_REG_MI_CR_BASE_ADDR_INIT, + crBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_CR_SIZE_INIT, crSize); +} + +int vse_start_dma_read(struct vse_ic_dev *dev, u64 addr) +{ + u32 writeFormat = 0; + u32 writeString = 0; + u32 reg = 0; + u32 address = VSE_REG_DMA_FORMAT; + u32 width = dev->params.src_w; + u32 height = dev->params.src_h; + u32 format = dev->params.in_format; + u32 ysize, cbSize; + u32 yBaseAddr, cbBaseAddr, crBaseAddr; + u32 stride; + + switch (format) { + case MEDIA_PIX_FMT_YUV422SP: + writeFormat = 1; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV422I: + writeFormat = 1; + writeString = 1; + break; + case MEDIA_PIX_FMT_YUV420SP: + writeFormat = 0; + writeString = 0; + break; + } + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_FMT_ALIGNED, 0); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_STR, writeString); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_FMT, writeFormat); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_10BIT, 0); + vse_write_reg(dev, address, reg); + stride = ALIGN_UP(width, 16); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_WIDTH, width); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_HEIGHT, height); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_STRIDE, stride); + ysize = stride * height; + cbSize = ysize; + yBaseAddr = addr; + cbBaseAddr = yBaseAddr + ysize; + crBaseAddr = 0; + + if (format == MEDIA_PIX_FMT_YUV420SP) { + cbSize /= 2; + } else if (format == MEDIA_PIX_FMT_YUV422I) { + cbSize /= 2; + crBaseAddr = cbBaseAddr + cbSize; + } + vse_write_reg(dev, VSE_REG_Y_PIC_START_ADDR, yBaseAddr); + vse_write_reg(dev, VSE_REG_CB_PIC_START_ADDR, cbBaseAddr); + vse_write_reg(dev, VSE_REG_CR_PIC_START_ADDR, crBaseAddr); + vse_triger_dma_read(dev); + return 0; +} + +void setFormatConvPack(struct vse_ic_dev *dev, u32 enable, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_ENABLE_PACK, enable); + vse_write_reg(dev, address, reg); +} + +void setFormatConvFull(struct vse_ic_dev *dev, u32 y_full, u32 cbcr_full, + u32 noco422, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_Y_FULL, y_full); + REG_SET_MASK(reg, VSE_FORMAT_CONV_CBCR_FULL, cbcr_full); + REG_SET_MASK(reg, VSE_FORMAT_CONV_CONFIG_422NOCO, 0); + vse_write_reg(dev, address, reg); +} + +static u32 format_conv_map[] = { 2, 2, 1, 3, 6, 6 }; + +void setFormatConvFormat(struct vse_ic_dev *dev, u32 inputFormat, + u32 outputFormat, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + } else if (inputFormat == MEDIA_PIX_FMT_YUV422SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + inputFormat = MEDIA_PIX_FMT_YUV420SP; + } else if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat != MEDIA_PIX_FMT_YUV420SP) { + inputFormat = MEDIA_PIX_FMT_YUV422SP; + } + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_OUTPUT_FORMAT, + format_conv_map[outputFormat]); + REG_SET_MASK(reg, VSE_FORMAT_CONV_INPUT_FORMAT, + format_conv_map[inputFormat]); + vse_write_reg(dev, address, reg); +} + +void setInputSize(struct vse_ic_dev *dev, u32 width, u32 height) +{ + u32 reg = ((height & 0x1FFF) << 16) | (width & 0x1FFF); + + vse_write_reg(dev, VSE_REG_IN_SIZE, reg); +} + +void setCropSize(struct vse_ic_dev *dev, u32 left, u32 right, u32 top, + u32 bottom, int channel) +{ + u32 hreg = ((right & 0x1FFF) << 16) | (left & 0x1FFF); + u32 vreg = ((bottom & 0x1FFF) << 16) | (top & 0x1FFF); + + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_CROP_XDIR, hreg); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_CROP_YDIR, vreg); +} + +void updateResizeControl(struct vse_ic_dev *dev, u32 reg, int channel) +{ + u32 address = VSE_RSZBASE(channel); + + vse_write_reg(dev, address, reg); +} + +void resizeControlAutoUpdate(struct vse_ic_dev *dev, u32 autoUpdate, + int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_AUTO_UPDATE_BIT, autoUpdate); + vse_write_reg(dev, address, reg); +} + +void resizeControlConfigUpdate(struct vse_ic_dev *dev, u32 configUpdate, + int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT, configUpdate); + vse_write_reg(dev, address, reg); +} + +void resizeControlEnableCrop(struct vse_ic_dev *dev, u32 enable, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_CROP_ENABLE_BIT, enable); + vse_write_reg(dev, address, reg); +} + +void updateVseControl(struct vse_ic_dev *dev, u32 inputChannel, u32 inputFormat, + u32 enbalePath0, u32 enbalePath1, u32 enbalePath2, + u32 autoUpdate, u32 configUpdate) +{ + u32 reg = 0; + + REG_SET_BIT(reg, VSE_CONTROL_AUTO_UPDATE_BIT, autoUpdate); + REG_SET_BIT(reg, VSE_CONTROL_CONFIG_UPDATE_BIT, configUpdate); + REG_SET_BIT(reg, VSE_CONTROL_PATH0_ENABLE_BIT, enbalePath0); + REG_SET_BIT(reg, VSE_CONTROL_PATH1_ENABLE_BIT, enbalePath1); + REG_SET_BIT(reg, VSE_CONTROL_PATH2_ENABLE_BIT, enbalePath2); + + REG_SET_MASK(reg, VSE_CONTROL_INPUT_SELECT, inputChannel); + REG_SET_MASK(reg, VSE_CONTROL_INPUT_FORMAT, inputFormat); + vse_write_reg(dev, VSE_REG_CTRL, reg); + + /* BUS ID and BUS CONFIG, hardcode here, user need adjust it on their hardware. */ + vse_write_reg(dev, VSE_REG_MI0_BUS_ID, 0x01000108); + vse_write_reg(dev, 0x000003e0, 0x001000fa); + vse_write_reg(dev, 0x000003e8, 0x924c5214); + vse_write_reg(dev, 0x000003f0, 0x100000fa); + vse_write_reg(dev, 0x000003f4, 0x01000108); + vse_write_reg(dev, 0x000003f8, 0x924c5214); +} + +void enableMIControl(struct vse_ic_dev *dev, u32 enable, int channel) +{ + u32 reg = vse_read_reg(dev, VSE_REG_MI_CTRL); + + REG_SET_BIT(reg, channel, enable); + REG_SET_BIT(reg, VSE_MI_CONTROL_RDMA_ENABLE_BIT, 1); + vse_write_reg(dev, VSE_REG_MI_CTRL, reg); +} + +void setMIBufferInfo(struct vse_ic_dev *dev, u32 width, u32 height, u32 format, + u32 is10Bit, u32 aligned, int channel) +{ + u32 writeFormat = 0; + u32 writeString = 0; + u32 reg = 0; + u32 address; + + u32 stride = ALIGN_UP(width, 16); + u32 size = stride * height; + + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_LENGTH, stride); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_WIDTH, + width); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_HEIGHT, + height); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_SIZE, size); + + switch (format) { + case MEDIA_PIX_FMT_YUV422SP: + writeFormat = 1; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV422I: + writeFormat = 1; + writeString = 1; + break; + case MEDIA_PIX_FMT_YUV420SP: + writeFormat = 0; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV444: + writeFormat = 2; + writeString = 2; + break; + case MEDIA_PIX_FMT_RGB888: + writeFormat = 2; + writeString = 1; + break; + case MEDIA_PIX_FMT_RGB888P: + writeFormat = 2; + writeString = 2; + break; + } + + address = VSE_MI_BASE(channel) + VSE_REG_MI_FMT; + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_FMT_ALIGNED, aligned); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_STR, writeString); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_FMT, writeFormat); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_10BIT, is10Bit); + vse_write_reg(dev, address, reg); +} + +void setMIControlConfig(struct vse_ic_dev *dev, u32 enableOffset, + u32 enableUpdateBaseAddress, u32 configUpdate, u32 skip, + u32 autoUpdate, u32 enablePingpong, int channel) +{ + u32 reg = 0; + + REG_SET_BIT(reg, VSE_MI_PATH_INIT_OFFSET_EN_BIT, enableOffset); + REG_SET_BIT(reg, VSE_MI_PATH_INIT_BASE_EN_BIT, enableUpdateBaseAddress); + REG_SET_BIT(reg, VSE_MI_PATH_CONFIG_UPDATE_BIT, configUpdate); + REG_SET_BIT(reg, VSE_MI_PATH_ENABLE_SKIP_BIT, skip); + REG_SET_BIT(reg, VSE_MI_PATH_AUTO_UPDATE_BIT, autoUpdate); + REG_SET_BIT(reg, VSE_MI_PATH_ENABLE_PINGPONG_BIT, enablePingpong); + vse_write_reg(dev, VSE_MI_BASE(channel), reg); +} + +u32 vse_get_scale_factor(int src, int dst) +{ + if (dst >= src) { + return ((65536 * (src - 1)) / (dst - 1)); + } else if (dst < src) { + return ((65536 * (dst - 1)) / (src - 1)) + 1; + } + return 0; +} + +void setScaleFactor(struct vse_ic_dev *dev, u32 src_w, u32 src_h, u32 dst_w, + u32 dst_h, u32 inputFormat, u32 outputFormat, int channel) +{ + bool hyup, vyup, hcup, vcup; + u32 scale_factor = vse_get_scale_factor(src_w, dst_w); + u32 address = VSE_RSZBASE(channel); + u32 reg = vse_read_reg(dev, address); + + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HY, + scale_factor); + scale_factor = vse_get_scale_factor(src_h, dst_h); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_VY, + scale_factor); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VY_ENABLE_BIT, + ((src_h != dst_h) & 0x01)); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HY_ENABLE_BIT, + ((src_w != dst_w) & 0x01)); + hyup = src_w < dst_w; + vyup = src_h < dst_h; + + /* Format conv module doesn't support convert other formats to YUV420SP. + doesn't support convert 420SP to other formats too. + so scale down/up cbcr here. + */ + src_w /= 2; + dst_w /= 2; + if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + src_h /= 2; + dst_h /= 2; + } else if (inputFormat == MEDIA_PIX_FMT_YUV422SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + /* scale 422 to 420 */ + dst_h /= 2; + } else if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat != MEDIA_PIX_FMT_YUV420SP) { + /* scale 420 to 422 + cbcr width*2, use input buffer as 422SP */ + src_h /= 2; + } + + hcup = src_w < dst_w; + vcup = src_h < dst_h; + scale_factor = vse_get_scale_factor(src_w, dst_w); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HCB, + scale_factor); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HCR, + scale_factor); + scale_factor = vse_get_scale_factor(src_h, dst_h); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_VC, + scale_factor); + + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VCUP_BIT, vcup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VYUP_BIT, vyup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HCUP_BIT, hcup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HYUP_BIT, hyup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VC_ENABLE_BIT, + (src_h != dst_h)); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HC_ENABLE_BIT, + (src_w != dst_w)); + vse_write_reg(dev, address, reg); +} + +int vse_read_irq(struct vse_ic_dev *dev, u32 *ret) +{ + pr_info("enter %s\n", __func__); + *ret = vse_read_reg(dev, VSE_REG_MI_MSI); + return 0; +} + +int vse_clear_irq(struct vse_ic_dev *dev) +{ + pr_info("enter %s\n", __func__); + vse_write_reg(dev, VSE_REG_MI_MSI, 0); + return 0; +} + +int vse_mask_irq(struct vse_ic_dev *dev, u32 mask) +{ + pr_info("enter %s 0x%08x\n", __func__, mask); + vse_write_reg(dev, VSE_REG_MI_IMSC, mask); + return 0; +} + +int vse_ioc_qcap(struct vse_ic_dev *dev, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "viv_vse"); + return 0; +} + +int vse_update_buffers(struct vse_ic_dev *dev, u64 *addr) +{ + struct vse_params *param = &dev->params; + struct vse_mi_settings *mi = param->mi_settings; + int i = 0; + + pr_info("enter %s\n", __func__); + for (; i < 3; i++) { + if (addr[i] != 0) { + setMIBaseAddress(dev, mi[i].width, mi[i].height, + mi[i].out_format, addr[i], i); + } + } + return 0; +} + +int vse_update_mi_info(struct vse_ic_dev *dev) +{ + struct vse_params *param = &dev->params; + struct vse_mi_settings *mi = param->mi_settings; + int i = 0; + + pr_info("enter %s\n", __func__); + + for (; i < 3; i++) { + if (!mi[i].enable) + continue; + setMIBufferInfo(dev, mi[i].width, mi[i].height, + mi[i].out_format, false, false, i); + enableMIControl(dev, mi[i].enable, i); + setMIControlConfig(dev, true, true, true, false, true, false, + i); + } + return 0; +} + +int vse_s_params(struct vse_ic_dev *dev) +{ + struct vse_params *param = &dev->params; + int i = 0; + int input_select = 0; + int crop_w, crop_h, scale_w, scale_h; + struct vse_crop_size *cropSize; + struct vse_size *outputSize; + + pr_info("enter %s\n", __func__); + setInputSize(dev, param->src_w, param->src_h); + + for (; i < 3; i++) { + if (!param->resize_enable[i]) + continue; + cropSize = ¶m->crop_size[i]; + outputSize = ¶m->out_size[i]; + crop_w = cropSize->right - cropSize->left + 1; + crop_h = cropSize->bottom - cropSize->top + 1; + scale_w = param->src_w; + scale_h = param->src_h; + if (crop_w > 1 && crop_h > 1) { + resizeControlEnableCrop(dev, 1, i); + setCropSize(dev, cropSize->left, cropSize->right, + cropSize->top, cropSize->bottom, i); + scale_w = crop_w; + scale_h = crop_h; + } else { + resizeControlEnableCrop(dev, 0, i); + } + + /* ONLY SUPPORT Semiplanar NOW, all enable pack */ + setFormatConvPack(dev, true, i); + setFormatConvFull(dev, true, true, false, i); + setFormatConvFormat(dev, param->in_format, + param->format_conv[i].out_format, i); + setScaleFactor(dev, scale_w, scale_h, outputSize->width, + outputSize->height, param->in_format, + param->format_conv[i].out_format, i); + resizeControlAutoUpdate(dev, 1, i); + resizeControlConfigUpdate(dev, 1, i); + } + +#ifndef HAL_CMODEL + input_select = param->input_select; +#endif + updateVseControl(dev, input_select, param->in_format, + param->resize_enable[0], + param->resize_enable[1], + param->resize_enable[2], true, true); + return 0; +} + +long vse_priv_ioctl(struct vse_ic_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + switch (cmd) { + case VSEIOC_RESET: + ret = vse_reset(dev); + break; + case VSEIOC_S_PARAMS: + viv_check_retval(copy_from_user + (&dev->params, args, sizeof(dev->params))); + ret = vse_s_params(dev); + break; + case VSEIOC_CLEAR_IRQ: + ret = vse_clear_irq(dev); + break; + case VSEIOC_READ_IRQ:{ + u32 irq = 0; + ret = vse_read_irq(dev, &irq); + viv_check_retval(copy_to_user(args, &irq, sizeof(irq))); + break; + } + case VSEIOC_START_DMA_READ:{ + u64 addr; + viv_check_retval(copy_from_user + (&addr, args, sizeof(addr))); + ret = vse_start_dma_read(dev, addr); + break; + } + case VSEIOC_U_MI_INFO: + ret = vse_update_mi_info(dev); + break; + case VSEIOC_U_BUFFER:{ + u64 addrs[3]; + viv_check_retval(copy_from_user + (addrs, args, sizeof(addrs))); + vse_update_buffers(dev, addrs); + break; + } + case VSEIOC_MASK_IRQ:{ + u32 mask; + viv_check_retval(copy_from_user + (&mask, args, sizeof(mask))); + vse_mask_irq(dev, mask); + break; + } + case VIDIOC_QUERYCAP: + ret = vse_ioc_qcap(dev, args); + break; + default: + pr_err("unsupported vse command %d", cmd); + break; + } + return ret; +} + +int vvnative_vse_init(struct vse_ic_dev *dev) +{ + return 0; +} + +int vvnative_vse_deinit(struct vse_ic_dev *dev) +{ + return 0; +} diff --git a/vvcam/vse/vse_ioctl.h b/vvcam/vse/vse_ioctl.h new file mode 100755 index 0000000..609ee41 --- /dev/null +++ b/vvcam/vse/vse_ioctl.h @@ -0,0 +1,90 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VSE_IOC_H_ +#define _VSE_IOC_H_ +#include "vse_dev.h" + +enum { + VSEIOC_RESET = 0x100, + VSEIOC_S_PARAMS, + VSEIOC_U_BUFFER, + VSEIOC_U_MI_INFO, + VSEIOC_MASK_IRQ, + VSEIOC_READ_IRQ, + VSEIOC_CLEAR_IRQ, + VSEIOC_START_DMA_READ, +}; + +#ifdef __KERNEL__ + +long vse_priv_ioctl(struct vse_ic_dev *dev, unsigned int cmd, void *args); +int vvnative_vse_init(struct vse_ic_dev *dev); +int vvnative_vse_deinit(struct vse_ic_dev *dev); + + + +int vse_reset(struct vse_ic_dev *dev); +int vse_s_params(struct vse_ic_dev *dev); +int vse_update_mi_info(struct vse_ic_dev *dev); +int vse_mask_irq(struct vse_ic_dev *dev, u32 mask); +int vse_clear_irq(struct vse_ic_dev *dev); +int vse_read_irq(struct vse_ic_dev *dev, u32 * ret); + +/* dma input pa */ +int vse_start_dma_read(struct vse_ic_dev *dev, u64 addr); +/* mi output pa */ +int vse_update_buffers(struct vse_ic_dev *dev, u64 * addr); + +#endif + +#endif /* _VSE_IOC_H_ */ diff --git a/vvcam/vse/vse_regs.h b/vvcam/vse/vse_regs.h new file mode 100755 index 0000000..456a547 --- /dev/null +++ b/vvcam/vse/vse_regs.h @@ -0,0 +1,481 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VSE_REGS_H_ +#define _VSE_REGS_H_ + +/* product identification */ +#define VSE_REG_ID 0x00000000 + +/* VSE CTL + 17 regs_enable_ram_clk "clk domain ram clock 1: enable 0: disable" + 16 auto_upd + 15 cfg_upd + 14 dma_frame_start_clk + 13:11 input select + 000 isp0 mp + 001 isp0 sp + 010 isp1 mp + 011 isp1 sp + 100 dewarp + 101 dma + 10:9 input format + 00 YUV422SP + 01 YUV422I + 10 YUV420SP + 8 soft reset + 7:0 path enable + bit:0 path 0 + bit:1 path 1 + bit:2 path 2 + */ +#define VSE_REG_CTRL 0x00000004 + +#define VSE_CONTROL_ENABLE_RAM_CLK 17 +#define VSE_CONTROL_AUTO_UPDATE_BIT 16 +#define VSE_CONTROL_CONFIG_UPDATE_BIT 15 +#define VSE_CONTROL_DMA_FRAME_START_BIT 14 +#define VSE_CONTROL_INPUT_SELECT_SHIFT 11 +#define VSE_CONTROL_INPUT_SELECT (7 << 11) +#define VSE_CONTROL_INPUT_FORMAT_SHIFT 9 +#define VSE_CONTROL_INPUT_FORMAT (3 << 9) +#define VSE_CONTROL_SOFT_RESET_BIT 8 +#define VSE_CONTROL_PATH2_ENABLE_BIT 2 +#define VSE_CONTROL_PATH1_ENABLE_BIT 1 +#define VSE_CONTROL_PATH0_ENABLE_BIT 0 + +/* input size 28:16 height, 12:0 width */ +#define VSE_REG_IN_SIZE 0x00000008 +#define VSE_REG_CTRL_SHD 0x0000000C + +/* RSZ CTL + 10 auto update + 9 config update + 8 crop enable + 7 scale vc up + 6 scale vy up + 5 scale hc up + 4 scale hy up + 3 scale vc enable + 2 scale vy enable + 1 scale hc enable + 0 scale hy enable + */ +#define VSE_REG_RSZ0_CTL 0x00000010 +#define VSE_REG_RSZ1_CTL 0x000000A0 /* repeat */ +#define VSE_REG_RSZ2_CTL 0x00000130 /* repeat */ +#define VSE_RSZBASE(c) ((c) == 0 ? VSE_REG_RSZ0_CTL : ((c) == 1 ? VSE_REG_RSZ1_CTL : VSE_REG_RSZ2_CTL)) + +/* NOTICE: repeat 3 times, using as VSE_REG_RSZX_CTL + VSE_RSZ_SCALE_HY */ + +#define VSE_RSZ_SCALE_HY 0x00000004 +#define VSE_RSZ_SCALE_HCB 0x00000008 +#define VSE_RSZ_SCALE_HCR 0x0000000C +#define VSE_RSZ_SCALE_VY 0x00000010 +#define VSE_RSZ_SCALE_VC 0x00000014 +#define VSE_RSZ_PHASE_HY 0x00000018 +#define VSE_RSZ_PHASE_HC 0x0000001C +#define VSE_RSZ_PHASE_VY 0x00000020 +#define VSE_RSZ_PHASE_VC 0x00000024 +#define VSE_RSZ_SCALE_LUT_ADDR 0x00000028 +#define VSE_RSZ_SCALE_LUT 0x0000002C + +/* RSZ0 CTRL SHD + 8 crop enable + 7 scale vc up + 6 scale vy up + 5 scale hc up + 4 scale hy up + 3 scale vc enable + 2 scale vy enable + 1 scale hc enable + 0 scale hy enable + */ +#define VSE_RSZ_CTRL_SHD 0x00000030 +#define VSE_RSZ_SCALE_HY_SHD 0x00000034 +#define VSE_RSZ_SCALE_HCB_SHD 0x00000038 +#define VSE_RSZ_SCALE_HCR_SHD 0x0000003C +#define VSE_RSZ_SCALE_VY_SHD 0x00000040 +#define VSE_RSZ_SCALE_VC_SHD 0x00000044 +#define VSE_RSZ_PHASE_HY_SHD 0x00000048 +#define VSE_RSZ_PHASE_HC_SHD 0x0000004C +#define VSE_RSZ_PHASE_VY_SHD 0x00000050 +#define VSE_RSZ_PHASE_VC_SHD 0x00000054 + +/* 28:16 h end, 12:0 h start */ +#define VSE_RSZ_CROP_XDIR 0x00000058 + +/* 28:16 v end, 12:0 v start */ +#define VSE_RSZ_CROP_YDIR 0x0000005C +#define VSE_RSZ_CROP_XDIR_SHD 0x00000060 +#define VSE_RSZ_CROP_YDIR_SHD 0x00000064 + +/* 2:0 frame scale */ +#define VSE_RSZ_FRAME_RATE 0x00000068 + +/* frame conv ctrl + 10 rsz_pack_format + 9 expand_8to10_method + 8 expand_8to10_enable + 7 cfg_422nocosited + 6 cfg_cbcr_full + 5 cfg_y_full + 4:2 rsz_output_format + 1:0 rsz_input_format + */ +#define VSE_REG_FORMAT_CONV_CTRL 0x0000006C +/********************************************************/ +/* END OF RSZ REGS */ + +#define VSE_REG_HBLANK_VALUE 0x000001A0 + +#define VSE_REG_VBLANK_VALUE 0x000001A4 + +#define VSE_REG_VSYNC_WIDTH 0x000001A8 + +#define VSE_REG_HSYNC_PREAMBLE 0x000001AC + +/* mi ctrl + 4 mi3_ycbcr_rdma_start + 3 mi3_ycbcr_rdma_path_enable + 2 mi2_ycbcr_path_enable + 1 mi1_ycbcr_path_enable + 0 mi0_ycbcr_path_enable + */ +#define VSE_REG_MI_CTRL 0x000001B0 +#define VSE_REG_MI_CTRL_SHD 0x000001B4 + +/* mi0 ctrl + 5 mi0_init_offset_en : Enables updating of the offset counters shadow registers for mi0 picture to the programmed register init values. + 4 mi0_init_base_en : Enables updating of the base address and buffer size shadow registers for mi0 picture to the programmed register init values + 3 mi0_cfg_upd : Forced configuration update. Leads to an immediate update of the shadow registers. + 2 mi0_mi_skip : Skip of current or next starting mi0 picture + 1 mi0_auto_update : automatic update of configuration registers for mi0 path at frame end. 1: enabled 0: disabled + 0 mi0_pingpong_enable : pingpong mode of configuration registers for mi0 path at frame end. 1: enabled 0: disabled +*/ +/* REPEAT 3 TIMES */ +#define VSE_REG_MI_PATH_0 0x000001C0 +#define VSE_REG_MI_PATH_1 0x00000260 +#define VSE_REG_MI_PATH_2 0x00000310 +#define VSE_MI_BASE(c) ((c) == 0 ? VSE_REG_MI_PATH_0 : ((c) == 1 ? VSE_REG_MI_PATH_1 : VSE_REG_MI_PATH_2)) + +/* mi0 format + 8:7 mi0_wr_yuv_nvy + 6 mi0_wr_yuv_n21 + 5 mi0_wr_fmt_aligned : 0 unaligned, 1 aligned + 4:3 mi0_wr_yuv_str + 2:1 mi0_wr_yuv_fmt + 0 mi0_wr_yuv_bit : 0 8bit, 1 10 bit. + */ +#define VSE_REG_MI_FMT 0x00000004 + +/* Base address of mi0 picture Y component ring buffer. */ +#define VSE_REG_MI_Y_BASE_ADDR_INIT 0x00000014 +/* Size of mi0 picture Y component ring buffer. */ +#define VSE_REG_MI_Y_SIZE_INIT 0x00000018 +/* Offset counter init value of mi0 picture Y component ring buffer. */ +#define VSE_REG_MI_Y_OFFSET_COUNT_INIT 0x0000001C +/* Line length of mi0 picture Y component or RGB picture n pixel, also known as line stride. */ +#define VSE_REG_MI_Y_LENGTH 0x00000020 +/* Image width of the mi0 picture Y component or RGB picture in pixel */ +#define VSE_REG_MI_Y_PIC_WIDTH 0x00000024 +/* Image height of the y component or RGB picture in pixel. */ +#define VSE_REG_MI_Y_PIC_HEIGHT 0x00000028 +/* Image size of the Y component or RGB picture in pixel which has to be the Y line length multiplied by the Y image height */ +#define VSE_REG_MI_Y_PIC_SIZE 0x0000002C + +/* CBCR */ +#define VSE_REG_MI_CB_BASE_ADDR_INIT 0x00000030 +#define VSE_REG_MI_CB_SIZE_INIT 0x00000034 +#define VSE_REG_MI_CB_OFFSET_COUNT_INIT 0x00000038 +#define VSE_REG_MI_CR_BASE_ADDR_INIT 0x0000003C +#define VSE_REG_MI_CR_SIZE_INIT 0x00000040 +#define VSE_REG_MI_CR_OFFSET_COUNT_INIT 0x00000044 + +/* 2nd ping pong base address of main picture Y component buffer. */ +#define VSE_REG_MI_Y_BASE_ADDR_INIT2 0x00000048 +#define VSE_REG_MI_CB_BASE_ADDR_INIT2 0x0000004C +#define VSE_REG_MI_CR_BASE_ADDR_INIT2 0x00000050 + +/* Offset counter value which points to the start address of the previously processed picture. Updated at frame end. */ +#define VSE_REG_MI_Y_OFFS_CNT_START 0x00000054 +#define VSE_REG_MI_CB_OFFS_CNT_START 0x00000058 +#define VSE_REG_MI_CR_OFFS_CNT_START 0x0000005C + +/* MI SHD */ +#define VSE_REG_MI_Y_BASE_ADDR_SHD 0x00000060 +#define VSE_REG_MI_Y_SIZE_SHD 0x00000064 +#define VSE_REG_MI_Y_OFFS_COUNT_SHD 0x00000068 +#define VSE_REG_MI_CB_BASE_ADDR_SHD 0x0000006C +#define VSE_REG_MI_CB_SIZE_SHD 0x00000070 +#define VSE_REG_MI_CB_OFFS_COUNT_SHD 0x00000074 +#define VSE_REG_MI_CR_BASE_ADDR_SHD 0x00000078 +#define VSE_REG_MI_CR_SIZE_SHD 0x0000007C +#define VSE_REG_MI_CR_OFFS_COUNT_SHD 0x00000080 +#define VSE_REG_MI_STATUS_CLR 0x00000084 +#define VSE_REG_MI_CTRL_STATUS 0x00000088 +#define VSE_REG_MI_Y_IRQ_OFFS_INIT 0x0000008C +#define VSE_REG_MI_Y_IRQ_OFFS_SHD 0x00000090 +/********************************************************/ +/* END OF MI0 MI1 MI2 */ + +/* MI3 DMA CTL + 7 regs_enable_ram_clk "clk domain ram clock 1: enable 0: disable" + 6:5 burst_len_chrom + 4:3 burst_len_lum + 2 frame start + 1 soft reset + 0 soft_upd + */ +#define VSE_REG_DMA_CTRL 0x000003A8 + +/* MI3 DMA FORMAT + 8:7 mi3_rd_yuv_nvy + 6 mi3_rd_yuv_n21 + 5 mi3_rd_fmt_aligned + 4:3 mi3_rd_yuv_str + 2:1 mi3_rd_yuv_fmt + 0 mi3_rd_yuv_bit +*/ +#define VSE_REG_DMA_FORMAT 0x000003AC + +#define VSE_REG_DMA_Y_PIC_WIDTH 0x000003B0 +#define VSE_REG_DMA_Y_PIC_HEIGHT 0x000003B4 +#define VSE_REG_DMA_Y_PIC_STRIDE 0x000003B8 +#define VSE_REG_Y_PIC_START_ADDR 0x000003BC +#define VSE_REG_CB_PIC_START_ADDR 0x000003C0 +#define VSE_REG_CR_PIC_START_ADDR 0x000003C4 +#define VSE_REG_Y_START_ADDR_SHD 0x000003C8 +#define VSE_REG_CB_START_ADDR_SHD 0x000003CC +#define VSE_REG_CR_START_ADDR_SHD 0x000003D0 +/* #define VSE_REG_DMA_STATUS 0x000003D4 */ +/********************************************************/ +/* END OF MI3 */ + +/* MI0 bus config + 19:16 mi_m0_wr_swap_v + 15:12 mi_m0_wr_swap_u + 11:8 mi_m0_wr_swap_y + 7:6 mi_m0_rd_issue_cap + 5:4 mi_m0_wr_issue_cap + 3:2 mi_m0_rd_burst_len + 1:0 mi_m0_wr_burst_len + */ +#define VSE_REG_MI0_BUS_CONFIG 0x000003E0 + +/* MI0 bus id + 24 mi_m0_rd_id_en + 23:16 mi_m0_rd_id_cfg + 8 mi_m0_wr_id_en + 7:0 mi_m0_wr_id_cfg + */ +#define VSE_REG_MI0_BUS_ID 0x000003E4 +#define VSE_REG_MI0_BUS_TIME_OUT 0x000003E8 +#define VSE_REG_MI0_AXI_STATUS 0x000003EC + +#define VSE_REG_MI1_BUS_CONFIG 0x000003F0 +#define VSE_REG_MI1_BUS_ID 0x000003F4 +#define VSE_REG_MI1_BUS_TIME_OUT 0x000003F8 +#define VSE_REG_MI1_AXI_STATUS 0x000003FC +/********************************************************/ +/* END OF BUS CONFIG */ + +/* MI IMSC STATUS + 12 mi_dma_ycbcr_ready + 11 wrap_mi2_cr + 10 wrap_mi2_cb + 9 wrap_mi2_y + 8 wrap_mi1_cr + 7 wrap_mi1_cb + 6 wrap_mi1_y + 5 wrap_mi0_cr + 4 wrap_mi0_cb + 3 wrap_mi0_y + 2 mi2_ycbcr_frame_end + 1 mi1_ycbcr_frame_end + 0 mi0_ycbcr_frame_end + */ +#define VSE_REG_MI_IMSC 0x00000400 + +/* MI IMSC ERROR + 5 mi2_bus_buserr + 4 mi2_bus_timeo + 3 mi1_bus_buserr + 2 mi1_bus_timeo + 1 mi0_bus_buserr + 0 mi0_bus_timeo + */ +#define VSE_REG_MI_IMSC1 0x00000404 +#define VSE_REG_MI_ISR 0x00000408 /* same as imsc */ +#define VSE_REG_MI_ISR1 0x0000040C /* same as imsc1 */ +#define VSE_REG_MI_MSI 0x00000410 +#define VSE_REG_MI_MSI1 0x00000414 +#define VSE_REG_MI_ICR 0x00000418 +#define VSE_REG_MI_ICR1 0x0000041C +#define VSE_REG_MI_RIS 0x00000420 +#define VSE_REG_MI_RIS1 0x00000424 + +/* slice of VSE_REG_FORMAT_CONV_CTRL */ +#define VSE_FORMAT_CONV_ENABLE_PACK_SHIFT 10 +#define VSE_FORMAT_CONV_ENABLE_PACK (1 << 10) +#define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD_SHIFT 9 +#define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD (1 << 9) +#define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE_SHIFT 8 +#define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE (1 << 8) +#define VSE_FORMAT_CONV_CONFIG_422NOCO_SHIFT 7 +#define VSE_FORMAT_CONV_CONFIG_422NOCO (1 << 7) +#define VSE_FORMAT_CONV_CBCR_FULL_SHIFT 6 +#define VSE_FORMAT_CONV_CBCR_FULL (1 << 6) +#define VSE_FORMAT_CONV_Y_FULL_SHIFT 5 +#define VSE_FORMAT_CONV_Y_FULL (1 << 5) +#define VSE_FORMAT_CONV_OUTPUT_FORMAT_SHIFT 2 +#define VSE_FORMAT_CONV_OUTPUT_FORMAT (7 << 2) +#define VSE_FORMAT_CONV_INPUT_FORMAT_SHIFT 0 +#define VSE_FORMAT_CONV_INPUT_FORMAT (3) + +/* slice of VSE_REG_RSZ0_CTL */ +#define VSE_RESIZE_CONTROL_AUTO_UPDATE_BIT 10 +#define VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT 9 +#define VSE_RESIZE_CONTROL_CROP_ENABLE_BIT 8 +#define VSE_RESIZE_CONTROL_SCALE_VCUP_BIT 7 +#define VSE_RESIZE_CONTROL_SCALE_VYUP_BIT 6 +#define VSE_RESIZE_CONTROL_SCALE_HCUP_BIT 5 +#define VSE_RESIZE_CONTROL_SCALE_HYUP_BIT 4 +#define VSE_RESIZE_CONTROL_SCALE_VC_ENABLE_BIT 3 +#define VSE_RESIZE_CONTROL_SCALE_VY_ENABLE_BIT 2 +#define VSE_RESIZE_CONTROL_SCALE_HC_ENABLE_BIT 1 +#define VSE_RESIZE_CONTROL_SCALE_HY_ENABLE_BIT 0 + +/* slice of VSE_REG_MI_FMT */ +#define VSE_MI_FORMAT_WR_YUV_NVY_SHIFT 7 +#define VSE_MI_FORMAT_WR_YUV_NVY (3 << 7) +#define VSE_MI_FORMAT_WR_YUV_N21_SHIFT 6 +#define VSE_MI_FORMAT_WR_YUV_N21 (1 << 6) +#define VSE_MI_FORMAT_WR_FMT_ALIGNED_SHIFT 5 +#define VSE_MI_FORMAT_WR_FMT_ALIGNED (1 << 5) +#define VSE_MI_FORMAT_WR_YUV_STR_SHIFT 3 +#define VSE_MI_FORMAT_WR_YUV_STR (3 << 3) +#define VSE_MI_FORMAT_WR_YUV_FMT_SHIFT 1 +#define VSE_MI_FORMAT_WR_YUV_FMT (3 << 1) +#define VSE_MI_FORMAT_WR_YUV_10BIT_SHIFT 0 +#define VSE_MI_FORMAT_WR_YUV_10BIT (1) + +/* slice of VSE_REG_MI_CTRL */ +#define VSE_MI_CONTROL_RDMA_START_BIT 4 +#define VSE_MI_CONTROL_RDMA_ENABLE_BIT 3 +#define VSE_MI_CONTROL_MI2_PATH_ENABLE_BIT 2 +#define VSE_MI_CONTROL_MI1_PATH_ENABLE_BIT 1 +#define VSE_MI_CONTROL_MI0_PATH_ENABLE_BIT 0 + +/* slice of VSE_REG_MI_PATH */ +#define VSE_MI_PATH_INIT_OFFSET_EN_BIT 5 +#define VSE_MI_PATH_INIT_BASE_EN_BIT 4 +#define VSE_MI_PATH_CONFIG_UPDATE_BIT 3 +#define VSE_MI_PATH_ENABLE_SKIP_BIT 2 +#define VSE_MI_PATH_AUTO_UPDATE_BIT 1 +#define VSE_MI_PATH_ENABLE_PINGPONG_BIT 0 + +#define VSE_MI_ISR_STATUS_DMA_YCBCR_READY_BIT 12 +#define VSE_MI_ISR_STATUS_WRAP_MI2_CR_BIT 11 +#define VSE_MI_ISR_STATUS_WRAP_MI2_CB_BIT 10 +#define VSE_MI_ISR_STATUS_WRAP_MI2_Y_BIT 9 +#define VSE_MI_ISR_STATUS_WRAP_MI1_CR_BIT 8 +#define VSE_MI_ISR_STATUS_WRAP_MI1_CB_BIT 7 +#define VSE_MI_ISR_STATUS_WRAP_MI1_Y_BIT 6 +#define VSE_MI_ISR_STATUS_WRAP_MI0_CR_BIT 5 +#define VSE_MI_ISR_STATUS_WRAP_MI0_CB_BIT 4 +#define VSE_MI_ISR_STATUS_WRAP_MI0_Y_BIT 3 +#define VSE_MI_ISR_STATUS_MI2_FRAME_END_BIT 2 +#define VSE_MI_ISR_STATUS_MI1_FRAME_END_BIT 1 +#define VSE_MI_ISR_STATUS_MI0_FRAME_END_BIT 0 + +#define VSE_MI_ISR_ERROR_MI2_BUS_ERROR_BIT 5 +#define VSE_MI_ISR_ERROR_MI2_BUS_TIMEOUT_BIT 4 +#define VSE_MI_ISR_ERROR_MI1_BUS_ERROR_BIT 3 +#define VSE_MI_ISR_ERROR_MI1_BUS_TIMEOUT_BIT 2 +#define VSE_MI_ISR_ERROR_MI0_BUS_ERROR_BIT 1 +#define VSE_MI_ISR_ERROR_MI0_BUS_TIMEOUT_BIT 0 + +#define VSE_MI_BUS_CONFIG_WR_SWAP_V_SHIFT 16 +#define VSE_MI_BUS_CONFIG_WR_SWAP_V (0XF << 16) +#define VSE_MI_BUS_CONFIG_WR_SWAP_U_SHIFT 12 +#define VSE_MI_BUS_CONFIG_WR_SWAP_U (0XF << 12) +#define VSE_MI_BUS_CONFIG_WR_SWAP_Y_SHIFT 8 +#define VSE_MI_BUS_CONFIG_WR_SWAP_Y (0XF << 8) +#define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP_SHIFT 6 +#define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP (0X3 << 6) +#define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP_SHIFT 4 +#define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP (0X3 << 4) +#define VSE_MI_BUS_CONFIG_RD_BURST_LEN_SHIFT 2 +#define VSE_MI_BUS_CONFIG_RD_BURST_LEN (0X3 << 2) +#define VSE_MI_BUS_CONFIG_WR_BURST_LEN_SHIFT 0 +#define VSE_MI_BUS_CONFIG_WR_BURST_LEN (0X3 << 0) + +#ifndef REG_GET_MASK +#define REG_GET_MASK(reg, mask)\ + (((reg) & (mask)) >> (mask##_SHIFT)) + +#define REG_SET_MASK(reg, mask, value)\ + {\ + ((reg) = (((reg) & ~(mask)) | (((value) << (mask##_SHIFT)) & (mask))));\ + } + +#define REG_GET_BIT(reg, shift)\ + (((reg) & 1) >> shift) + +#define REG_SET_BIT(reg, shift, value)\ + {\ + ((reg) = (((reg) & ~(1 << (shift))) | (((value) & 1) << (shift))));\ + } +#endif + +#endif /* _VSE_REGS_H_ */ diff --git a/vvcam/vvcam.mk b/vvcam/vvcam.mk new file mode 100755 index 0000000..650e79d --- /dev/null +++ b/vvcam/vvcam.mk @@ -0,0 +1,36 @@ +#the device/fsl/common/build/kernel.mk should be included before this file + +KERNEL_DIR := $(TARGET_OUT_INTERMEDIATES)/KERNEL_OBJ +TARGET_ARCH := $(TARGET_KERNEL_ARCH) +VVCAM_CROSS_COMPILE := aarch64-linux-gnu- + +VVCAM_SRC_PATH := $(VVCAM_PATH)/vvcam/v4l2 +VVCAM_OUT := $(TARGET_OUT_INTERMEDIATES)/VVCAM_OBJ + +KERNEL_CFLAGS ?= KCFLAGS=-mno-android +ARCH_TYPE ?= $(TARGET_ARCH) + +VVCAM_KERNELENVSH := $(VVCAM_OUT)/kernelenv.sh +$(VVCAM_KERNELENVSH): + mkdir -p $(VVCAM_OUT) + echo 'export KERNEL_DIR=$(KERNEL_DIR)' > $(VVCAM_KERNELENVSH) + echo 'export CROSS_COMPILE=$(VVCAM_CROSS_COMPILE)' >> $(VVCAM_KERNELENVSH) + echo 'export ARCH_TYPE=$(ARCH_TYPE)' >> $(VVCAM_KERNELENVSH) + +vvcam: $(VVCAM_KERNELENVSH) $(VVCAM_SRC_PATH) + $(hide) if [ ${clean_build} = 1 ]; then \ + PATH=$$PATH $(MAKE) -f Kbuild -C $(VVCAM_SRC_PATH) ANDROID=yes clean; \ + fi + @ . $(VVCAM_KERNELENVSH); $(kernel_build_shell_env) \ + $(MAKE) -f Kbuild -C $(VVCAM_SRC_PATH) ANDROID=yes \ + PWD=$(ANDROID_BUILD_TOP)/vendor/nxp-opensource/verisilicon_sw_isp_vvcam/vvcam/v4l2 \ + $(CLANG_TO_COMPILE) \ + $(KERNEL_CFLAGS) \ + ARCH_TYPE=$(ARCH_TYPE) \ + DEBUG=$(DEBUG); \ + cp $(VVCAM_SRC_PATH)/sensor/ov2775/ov2775.ko $(VVCAM_OUT); + cp $(VVCAM_SRC_PATH)/sensor/camera-proxy-driver/basler-camera-driver-vvcam.ko $(VVCAM_OUT); + cp $(VVCAM_SRC_PATH)/sensor/os08a20/os08a20.ko $(VVCAM_OUT); + cp $(VVCAM_SRC_PATH)/video/vvcam-video.ko $(VVCAM_OUT); + cp $(VVCAM_SRC_PATH)/vvcam-isp.ko $(VVCAM_OUT); + cp $(VVCAM_SRC_PATH)/vvcam-dwe.ko $(VVCAM_OUT); diff --git a/vvcam_ry/.gitignore b/vvcam_ry/.gitignore new file mode 100755 index 0000000..cb6169a --- /dev/null +++ b/vvcam_ry/.gitignore @@ -0,0 +1,13 @@ +*.cmd +*.mod +*.o +*.swp +.vscode/* +.tmp_versions/* +Module.symvers +*.ko +modules.order +*mod.c +*cmd.c +*.tmp +.cache.mk diff --git a/vvcam_ry/LICENSE b/vvcam_ry/LICENSE new file mode 100755 index 0000000..efa96c4 --- /dev/null +++ b/vvcam_ry/LICENSE @@ -0,0 +1,114 @@ +/**************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + *****************************************************************************/ + +GNU GENERAL PUBLIC LICENSE +Version 2, June 1991 + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. + +Preamble + +The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. + +To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. + +For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. + +We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. + +Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. + +Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. + +The precise terms and conditions for copying, distribution and modification follow. + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + +0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. + +1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. + +You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. + +2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. + + c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. + +3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. + +If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. + +4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. + +5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. + +6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. + +7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. + +This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. + +8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. + +9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. + +10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. + +NO WARRANTY + +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +END OF TERMS AND CONDITIONS + diff --git a/vvcam_ry/common/viv_video_kevent.h b/vvcam_ry/common/viv_video_kevent.h new file mode 100755 index 0000000..6b1b43d --- /dev/null +++ b/vvcam_ry/common/viv_video_kevent.h @@ -0,0 +1,191 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VIV_VIDEO_KEVENT_H_ +#define _VIV_VIDEO_KEVENT_H_ +#include + +#ifndef __KERNEL__ +#include +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; +#endif + +enum { + VIV_VIDEO_EVENT_MIN = 0, + VIV_VIDEO_EVENT_NEW_STREAM, + VIV_VIDEO_EVENT_DEL_STREAM, + VIV_VIDEO_EVENT_START_STREAM, + VIV_VIDEO_EVENT_STOP_STREAM, + VIV_VIDEO_EVENT_SET_FMT, + VIV_VIDEO_EVENT_SET_CROP, + VIV_VIDEO_EVENT_SET_COMPOSE, + VIV_VIDEO_EVENT_QUERYCAPS, + VIV_VIDEO_EVENT_PASS_JSON, + VIV_VIDEO_EVENT_EXTCTRL, + VIV_VIDEO_EVENT_EXTCTRL2, + VIV_VIDEO_EVENT_SET_CAPSMODE, + VIV_VIDEO_EVENT_GET_CAPS_SUPPORTS, + VIV_VIDEO_EVENT_CREATE_PIPELINE, + VIV_VIDEO_EVENT_QBUF, + VIV_VIDEO_EVENT_MAX, +}; + +enum { + VIV_DWE_EVENT_MIN = VIV_VIDEO_EVENT_MAX + 1, + VIV_DWE_EVENT_FRAMEDONE, + VIV_DWE_EVENT_MAX, +}; + +/* max support to 64 bytes! */ +struct viv_video_event { + u32 stream_id; + void *file; + u64 addr; + int buf_index; + u64 response; + u32 sync; +}; + +struct v4l2_user_buffer { + u64 addr; + int streamid; + void *file; +}; + +struct viv_rect { + __s16 left; + __s16 top; + __u16 width; + __u16 height; +}; + +#define VIV_EVENT_BUF_SIZE (4*1024) + +#define VIV_JSON_BUFFER_SIZE (64*1024) +struct viv_control_event { + /* physical address of json request, fixed size 64K */ + u64 request; + /* physical address of json response fixed size 64K */ + u64 response; + u32 id; +}; + + +struct ext_buf_info { + u64 addr; + u64 size; +}; + +struct vvcam_constant_modeinfo { + unsigned index; + unsigned w; + unsigned h; + unsigned fps; + unsigned brpat; /*bayer pattern*/ + unsigned bitw; /*bit width*/ +}; + +#define CALIBXML_FILE_NAME_SIZE 64 +struct viv_caps_mode_s { + int mode; + char CalibXmlName[CALIBXML_FILE_NAME_SIZE]; +}; + +enum viv_caps_hdr_mode_e +{ + VIV_CAPS_MODE_LINEAR , + VIV_CAPS_MODE_HDR_STITCH, + VIV_CAPS_MODE_HDR_NATIVE, +}; + +struct viv_caps_mode_info_s{ + unsigned int index; + unsigned int width; + unsigned int height; + unsigned int hdr_mode; + unsigned int fps; +}; + +#define VIV_CAPS_MODE_MAX_COUNT 20 +struct viv_caps_supports{ + unsigned int count; + struct viv_caps_mode_info_s mode[VIV_CAPS_MODE_MAX_COUNT]; +}; + +#define VIV_VIDEO_ISPIRQ_TYPE (V4L2_EVENT_PRIVATE_START + 0x0) +#define VIV_VIDEO_MIIRQ_TYPE (V4L2_EVENT_PRIVATE_START + 0x1) +#define VIV_VIDEO_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x2000) +#define VIV_DWE_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x3000) + +#define VIV_VIDEO_EVENT_TIMOUT_MS 5000 + +#define VIV_VIDIOC_EVENT_COMPLETE _IOW('V', BASE_VIDIOC_PRIVATE + 0, struct viv_video_event) // 0x403056c0 +#define VIV_VIDIOC_BUFFER_ALLOC _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct ext_buf_info) +#define VIV_VIDIOC_BUFFER_FREE _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct ext_buf_info) +#define VIV_VIDIOC_CONTROL_EVENT _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct viv_control_event) +#define VIV_VIDIOC_S_STREAMID _IOW('V', BASE_VIDIOC_PRIVATE + 4, int) // 0x403056c4 +#define VIV_VIDIOC_BUFDONE _IOW('V', BASE_VIDIOC_PRIVATE + 5, struct v4l2_user_buffer) // 0x403056c5 +#define VIV_VIDIOC_QUERY_EXTMEM _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct ext_buf_info) +#define VIV_VIDIOC_S_ENDPOINT _IOW('V', BASE_VIDIOC_PRIVATE + 7, int) +#define VIV_VIDIOC_S_MODEINFO _IOW('V', BASE_VIDIOC_PRIVATE + 8, struct vvcam_constant_modeinfo) +#define VIV_VIDIOC_S_CAPS_MODE _IOW('V', BASE_VIDIOC_PRIVATE + 9, struct viv_caps_mode_s) +#define VIV_VIDIOC_G_CAPS_MODE _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct viv_caps_mode_s) +#define VIV_VIDIOC_EVENT_RESULT _IOWR('V', BASE_VIDIOC_PRIVATE + 11,int) +#define VIV_VIDIOC_GET_CAPS_SUPPORTS _IOWR('V', BASE_VIDIOC_PRIVATE + 12,struct viv_caps_supports) +#define VIV_VIDIOC_SET_CAPS_SUPPORTS _IOWR('V', BASE_VIDIOC_PRIVATE + 13,struct viv_caps_supports) +#define VIV_VIDIOC_S_DWECFG _IOW('V', BASE_VIDIOC_PRIVATE + 14, int) +#define VIV_VIDIOC_G_DWECFG _IOR('V', BASE_VIDIOC_PRIVATE + 15, int) + +#endif diff --git a/vvcam_ry/common/vvcsioc.h b/vvcam_ry/common/vvcsioc.h new file mode 100755 index 0000000..9dfe9fa --- /dev/null +++ b/vvcam_ry/common/vvcsioc.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVCAM_CSIOC_H_ +#define _VVCAM_CSIOC_H_ +#ifdef __KERNEL__ +#include +#else +#include +#endif + +enum { + VVCSIOC_RESET = 0x100, + VVCSIOC_POWERON, + VVCSIOC_POWEROFF, + VVCSIOC_STREAMON, + VVCSIOC_STREAMOFF, + VVCSIOC_S_FMT, + VVCSIOC_S_HDR, +}; + +struct csi_sam_format { + int64_t format; + __u32 width; + __u32 height; +}; + +#endif /* _VVCAM_CSIOC_H_ */ diff --git a/vvcam_ry/common/vvctrl.h b/vvcam_ry/common/vvctrl.h new file mode 100755 index 0000000..7a6ca0e --- /dev/null +++ b/vvcam_ry/common/vvctrl.h @@ -0,0 +1,148 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVCTRL_H_ +#define _VVCTRL_H_ + +#include + +#define VIV_CUSTOM_CID_BASE (V4L2_CID_USER_BASE | 0xf000) +#define V4L2_CID_VIV_STRING (VIV_CUSTOM_CID_BASE + 0x01) +#define V4L2_CID_VIV_SENSOR_MODE (VIV_CUSTOM_CID_BASE + 0x02) +#define V4L2_CID_VIV_SENSOR_RES_W (VIV_CUSTOM_CID_BASE + 0x03) +#define V4L2_CID_VIV_SENSOR_RES_H (VIV_CUSTOM_CID_BASE + 0x04) +#define V4L2_CID_VIV_SENSOR_TPG_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x05) +#define V4L2_CID_VIV_DEWARP_MODE (VIV_CUSTOM_CID_BASE + 0x06) +#define V4L2_CID_VIV_DEWARP_BYPASS_STATUS (VIV_CUSTOM_CID_BASE + 0x07) +#define V4L2_CID_VIV_AEC_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x08) +#define V4L2_CID_VIV_AWB_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x09) +#define V4L2_CID_VIV_AWB_DAMPING_STATUS (VIV_CUSTOM_CID_BASE + 0x0A) +#define V4L2_CID_VIV_LSC_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x0B) +#define V4L2_CID_VIV_CPROC_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x0C) +#define V4L2_CID_VIV_GAMMA_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x0D) +#define V4L2_CID_VIV_GAMMA_MODE (VIV_CUSTOM_CID_BASE + 0x0E) +#define V4L2_CID_VIV_DEMOSAIC_MODE (VIV_CUSTOM_CID_BASE + 0x0F) +#define V4L2_CID_VIV_FILTER_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x10) +#define V4L2_CID_VIV_CAC_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x11) +#define V4L2_CID_VIV_DPCC_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x12) +#define V4L2_CID_VIV_CNR_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x13) +#define V4L2_CID_VIV_DPF_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x14) +#define V4L2_CID_VIV_WDR3_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x15) +#define V4L2_CID_VIV_AVS_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x16) +#define V4L2_CID_VIV_2DNR_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x17) +#define V4L2_CID_VIV_3DNR_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x18) +#define V4L2_CID_VIV_HDR_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x19) +#define V4L2_CID_VIV_HDR_MODE (VIV_CUSTOM_CID_BASE + 0x1A) +#define V4L2_CID_VIV_STITCHING_MODE (VIV_CUSTOM_CID_BASE + 0x1B) +#define V4L2_CID_VIV_IS_OUT_RES_W (VIV_CUSTOM_CID_BASE + 0x1C) +#define V4L2_CID_VIV_IS_OUT_RES_H (VIV_CUSTOM_CID_BASE + 0x1D) +#define V4L2_CID_VIV_MP_OUT_RES_W (VIV_CUSTOM_CID_BASE + 0x1E) +#define V4L2_CID_VIV_MP_OUT_RES_H (VIV_CUSTOM_CID_BASE + 0x1F) +#define V4L2_CID_VIV_MP_OUT_FORMAT (VIV_CUSTOM_CID_BASE + 0x20) +#define V4L2_CID_VIV_PIPELINE_SMP_MODE (VIV_CUSTOM_CID_BASE + 0x21) +#define V4L2_CID_VIV_PIPELINE_DWE_ENABLED_STATUS (VIV_CUSTOM_CID_BASE + 0x22) + +enum v4l2_ctrl_direction { + V4L2_CTRL_GET, + V4L2_CTRL_SET, +}; + +struct v4l2_ctrl_data { + struct v4l2_ext_controls ctrls; + enum v4l2_ctrl_direction dir; + int ret; +}; + +#define nextof(ptr, new_type) ((new_type)((ptr) + 1)) + +#ifdef __KERNEL__ +int viv_gen_g_ctrl(struct v4l2_ctrl *ctrl); +int viv_gen_s_ctrl(struct v4l2_ctrl *ctrl); + +static const struct v4l2_ctrl_ops viv_gen_ctrl_ops = { + .g_volatile_ctrl = viv_gen_g_ctrl, + .s_ctrl = viv_gen_s_ctrl, +}; + +static const struct v4l2_ctrl_config viv_ctrl_sensor_resw = { + .ops = &viv_gen_ctrl_ops, + .id = V4L2_CID_VIV_SENSOR_RES_W, + .name = "sensor.resw", + .type = V4L2_CTRL_TYPE_INTEGER, + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, + .min = 0, + .max = 3840, + .def = 1920, + .step = 1, +}; + +static const struct v4l2_ctrl_config viv_ctrl_sensor_resh = { + .ops = &viv_gen_ctrl_ops, + .id = V4L2_CID_VIV_SENSOR_RES_H, + .name = "sensor.resh", + .type = V4L2_CTRL_TYPE_INTEGER, + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, + .min = 0, + .max = 2160, + .def = 1080, + .step = 1, +}; + +#define create_controls(handler) \ +do { \ + v4l2_ctrl_new_custom(handler, &viv_ctrl_sensor_resw, NULL); \ + v4l2_ctrl_new_custom(handler, &viv_ctrl_sensor_resh, NULL); \ +} while (0) + +#endif + +#endif /* _VVCTRL_H_ */ diff --git a/vvcam_ry/common/vvdefs.h b/vvcam_ry/common/vvdefs.h new file mode 100755 index 0000000..e299ef1 --- /dev/null +++ b/vvcam_ry/common/vvdefs.h @@ -0,0 +1,144 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_VVDEFS_H_ +#define _ISP_VVDEFS_H_ + +#define viv_check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +#ifndef VIV_MEDIA_PIX_FMT +#define VIV_MEDIA_PIX_FMT +enum { + MEDIA_PIX_FMT_YUV422SP = 0, + MEDIA_PIX_FMT_YUV422I, + MEDIA_PIX_FMT_YUV420SP, + MEDIA_PIX_FMT_YUV444, + MEDIA_PIX_FMT_RGB888, + MEDIA_PIX_FMT_RGB888P, + MEDIA_PIX_FMT_RAW8, + MEDIA_PIX_FMT_RAW10, + MEDIA_PIX_FMT_RAW12, +}; +#endif + +#ifndef __KERNEL__ +#include +#include +#include +#include +#include + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +#define pr_info(...) printf(__VA_ARGS__) +#define pr_err(...) printf(__VA_ARGS__) +#define pr_debug(...) printf(__VA_ARGS__) +#define __user +#define __iomem +#else /* __KERNEL__ */ + +/* if v4l2 */ +#include +#include +#include +#include +#include +#include +#include +#include + +enum STATE_CODE { + STATE_STOPPED = 0, + STATE_STREAM_STARTED = 1 << 1, + STATE_DRIVER_STARTED = 1 << 2, +}; +#endif + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef ALIGN_UP +#define ALIGN_UP(x, align) (((x) + ((align) - 1)) & ~((align)-1)) +#endif + +#define ISP_COMPAT_NAME "fsl,imx8mp-isp" +#define DWE_COMPAT_NAME "fsl,imx8mp-dwe" + +#define ISP_DEVICE_NAME "vvcam-isp" +#define DWE_DEVICE_NAME "vvcam-dwe" + +#define ISP_PAD_SOURCE (0) +#define ISP_PADS_NUM (1) + +#define DWE_PAD_SOURCE (0) +#define DWE_PAD_SINK (1) +#define DWE_PADS_NUM (2) + +#define RESV_STREAMID_ISP(id) \ + ((id) ? RESV_STREAMID_ISP1 : RESV_STREAMID_ISP0) +#define RESV_STREAMID_ISP0 (-2) +#define RESV_STREAMID_ISP1 (-3) +#define RESV_STREAMID_DWE (-4) + +#endif /* _ISP_VVDEFS_H_ */ diff --git a/vvcam_ry/common/vvnative.c b/vvcam_ry/common/vvnative.c new file mode 100755 index 0000000..2322820 --- /dev/null +++ b/vvcam_ry/common/vvnative.c @@ -0,0 +1,642 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include /* Module support */ +#include /* Kernel version */ +#include /* Charactor device support */ +#include +#include +#include +#include + +#include +#include + + +#include "vvnative.h" +#include "vvnative_cfg.h" +#include "vvnative_combo.h" + +#ifdef SENSOR_USE_GPIO_I2C +#include "soc_i2c.h" +#endif + +#ifndef MODULE_LICENSE +# define MODULE_LICENSE(x) +#endif /* MODULE_LICENSE */ + +#ifndef MODULE_VERSION +# define MODULE_VERSION(x) +#endif /* MODULE_VERSION */ + +#define DRIVER_AUTHOR "VeriSilicon IPD" +#define DRIVER_DESC "Verisilicon ISP driver" +#define DRIVER_LICENSE "GPL" +#define DRIVER_VERSION "1.0" + + +#ifdef MODULE +MODULE_AUTHOR( DRIVER_AUTHOR ); +MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_LICENSE( DRIVER_LICENSE ); +MODULE_INFO( vermagic, VERMAGIC_STRING); +#endif /* MODULE */ + + +/* vvcam_isp_dev_major: device major number */ +unsigned int vvcam_isp_dev_major = 0; +module_param(vvcam_isp_dev_major, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcam_isp_dev_major, "vvcam ISP device major number"); + +/* vvcam_isp_dev_minor: device base(start) minor number */ +unsigned int vvcam_isp_dev_minor = 0; +module_param(vvcam_isp_dev_minor, uint, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(vvcam_isp_dev_minor, "vvcam ISP device base minor number"); + +/* vvcam_isp_dev_count: counts */ +unsigned int vvcam_isp_dev_count = VVCAM_ISP_DEVICES; +module_param(vvcam_isp_dev_count, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcam_isp_dev_count, "vvcam ISP device counts"); + + +struct vvcam_isp_dev *vvcam_isp_drv; +struct vvcam_common *vvcam_drv_common; + +static int vvcam_isp_dev_open(struct inode *inode, struct file *file); +static int vvcam_isp_dev_release(struct inode *inode, struct file *file); +static long vvcam_isp_dev_ioctl(struct file * pFile, unsigned int cmd, unsigned long arg); +static int vvcam_isp_dev_mmap(struct file *pFile, struct vm_area_struct *vma); +static int vvcam_isp_devio_remap(int dev_no); +static int vvcam_isp_devio_unmap(int dev_no); + +long (*vvnative_ioctl[])(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args)= +{ + vvcam_combo_isp_ioctl, /*devid0*/ + vvcam_combo_isp_ioctl, /*devid1*/ + vvcam_combo_csi_ioctl, /*devid2*/ + vvcam_combo_csi_ioctl, /*devid3*/ + vvcam_combo_sensor_ioctl, /*devid4*/ + vvcam_combo_sensor_ioctl, /*devid5*/ + vvcam_combo_dwe_ioctl, /*devid6*/ + vvcam_combo_vse_ioctl, /*devid7*/ + vvcam_combo_soc_ioctl, /*devid8*/ +}; + +int (*vvnative_init[])(struct vvcam_isp_dev *vvcam_isp_drv)= +{ + vvcam_combo_isp_init, /*devid0*/ + vvcam_combo_isp_init, /*devid1*/ + vvcam_combo_csi_init, /*devid2*/ + vvcam_combo_csi_init, /*devid3*/ + vvcam_combo_sensor_init, /*devid4*/ + vvcam_combo_sensor_init, /*devid5*/ + vvcam_combo_dwe_init, /*devid6*/ + vvcam_combo_vse_init, /*devid7*/ + vvcam_combo_soc_init, /*devid8*/ +}; + +int (*vvnative_deinit[])(struct vvcam_isp_dev *vvcam_isp_drv)= +{ + vvcam_combo_isp_deinit, /*devid0*/ + vvcam_combo_isp_deinit, /*devid1*/ + vvcam_combo_csi_deinit, /*devid2*/ + vvcam_combo_csi_deinit, /*devid3*/ + vvcam_combo_sensor_deinit, /*devid4*/ + vvcam_combo_sensor_deinit, /*devid5*/ + vvcam_combo_dwe_deinit, /*devid6*/ + vvcam_combo_vse_deinit, /*devid7*/ + vvcam_combo_soc_deinit, /*devid8*/ +}; + +/*TODO:expand dual camera devs*/ +struct file_operations vvcam_isp_fops = { + .owner = THIS_MODULE, + .open = vvcam_isp_dev_open, + .release = vvcam_isp_dev_release, + .unlocked_ioctl = vvcam_isp_dev_ioctl, + .mmap = vvcam_isp_dev_mmap, +}; + +/*On-the-fly debug opitions*/ +char * on_the_fly_str="VIV ISP local debug buffer"; +static void vivdev_dump_buf(unsigned char *out_buf, unsigned char* dump_data, int len, unsigned char * phy_address) +{ + int m; + int n; + char *buf; + buf = out_buf; + int llength = 0x10; + unsigned int udata; + sprintf (buf, "Phy Addr: 0x%lx, Va Addr:0x%lx, len:%d\n", (unsigned long)phy_address, dump_data, len); + buf += strlen(buf); + + for (m=0; m0;n--) + { + if ((*(dump_data+m+1-n)>31) && (*(dump_data+m+1-n)<127)) + { + sprintf (buf, "%c", *(dump_data+m+1-n)); + buf += strlen(buf); + } + else + { + sprintf (buf, "."); + buf += strlen(buf); + } + } + sprintf (buf, "\n"); + buf += strlen(buf); + } + } + sprintf (buf, "\n"); + buf += strlen(buf); +} + +static ssize_t get_vivdev(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const char * name; + char dev_name_perfix[8]; + int dev_index; + int ret; + if(NULL == vvcam_drv_common) + { + pr_info("-->%s Error, null pointer of vvcam_drv_common\n", __func__); + return 0; + } + + mutex_lock(&vvcam_drv_common->vvmutex); + + name = dev_name(dev); + pr_info("-->%s dev_name name:%s\n", __func__, name); + ret = sscanf(name, "%6s%d", dev_name_perfix, &dev_index); + pr_info("-->%s sscanf ret:%d, name:%s, id:%d\n", __func__, ret, dev_name_perfix, dev_index); + + ret = sprintf(buf, "%s\n", vvcam_drv_common->viv_buf); + mutex_unlock(&vvcam_drv_common->vvmutex); + + return ret; +} + +static ssize_t set_vivdev(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + const char * name; + char dev_name_perfix[8]; + int dev_index; + + unsigned int data; + unsigned int addr; + unsigned int read_cnt; + unsigned char mode; + int ret; + + if(NULL == vvcam_drv_common) + { + pr_info("-->%s Error, null pointer of vvcam_drv_common\n", __func__); + return 0; + } + + mutex_lock(&vvcam_drv_common->vvmutex); + + name = dev_name(dev); + pr_info("-->%s dev_name name:%s\n", __func__, name); + ret = sscanf(name, "%6s%d", dev_name_perfix, &dev_index); + pr_info("-->%s sscanf ret:%d, name:%s, id:%d\n", __func__, ret, dev_name_perfix, dev_index); + + ret = sscanf(buf, "%c, 0x%x, 0x%x, 0x%d", &mode, &addr, &data, &read_cnt); + if(ret < 3) + { + sprintf(vvcam_drv_common->viv_buf, "Error input string %s The parameters number:%d, expect format: 'r/w, 0xAddress, 0xData, 0xReadCnt'", + buf, ret); + pr_info("Error input string %s The parameters number:%d, expect format: 'r/w, 0xAddress, 0xData, 0xReadNumber'",buf, ret); + mutex_unlock(&vvcam_drv_common->vvmutex); + return len; + } + + sprintf(vvcam_drv_common->viv_buf, "init: %s, scanf ret:%d, mode:%c, addr:0x%x, data:0x%x, readcnt:0x%x", buf, ret, mode, addr, data, read_cnt); + pr_info("-->%s init: %s, scanf ret:%d, mode:%c, addr:0x%x, data:0x%x, readcnt:0x%x", __func__, buf, ret, mode, addr, data, read_cnt); + + vivdev_dump_buf((unsigned char*)vvcam_drv_common->viv_buf, on_the_fly_str, strlen(on_the_fly_str), 0xaaaa); + + mutex_unlock(&vvcam_drv_common->vvmutex); + + return len; +} + +static DEVICE_ATTR(vivdevio, S_IWUSR|S_IRUSR|S_IRGRP|S_IWGRP|S_IROTH, get_vivdev, set_vivdev); + +static int vvcam_isp_dev_open(struct inode *inode, struct file *file) +{ + + int minor = iminor(inode); + pr_info("-->%s: ISPdev%d opened\n", __func__, minor); + + mutex_lock(&(vvcam_isp_drv + minor)->vvmutex); + + if((vvcam_isp_drv + minor)->open_cnt >= VVISP_OPEN_LIMITATION) + { + pr_info("-->%s: ISPdev%d cannot open device\n", __func__, minor); + mutex_unlock(&(vvcam_isp_drv + minor)->vvmutex); + return -EBUSY; + } + + if((vvcam_isp_drv + minor)->initialized == 0) + { + pr_info("-->%s: ISPdev%d device not initialized\n", __func__, minor); + mutex_unlock(&(vvcam_isp_drv + minor)->vvmutex); + return -EBUSY; + } + + (vvcam_isp_drv + minor)->open_cnt++; + pr_info("-->%s: ISPdev%d update open_cnt to %d\n", __func__, minor, (vvcam_isp_drv + minor)->open_cnt); + try_module_get(THIS_MODULE); + mutex_unlock(&(vvcam_isp_drv + minor)->vvmutex); + + return 0; +} + + +/* Called when a process closes the device file */ +static int vvcam_isp_dev_release(struct inode *inode, struct file *file) +{ + int minor = iminor(inode); + pr_info("-->%s: ISPdev%d releaseing...\n", __func__, minor); + + mutex_lock(&(vvcam_isp_drv + minor)->vvmutex); + + if((vvcam_isp_drv + minor)->open_cnt <= 0) + { + pr_info("-->%s: ISPdev%d internal error\n", __func__, minor); + mutex_unlock(&(vvcam_isp_drv + minor)->vvmutex); + return -EBUSY; + } + + (vvcam_isp_drv + minor)->open_cnt--; + module_put(THIS_MODULE); + + mutex_unlock(&(vvcam_isp_drv + minor)->vvmutex); + + return 0; +} + +static long vvcam_isp_dev_ioctl(struct file * pFile, unsigned int cmd, unsigned long arg) +{ + long ret; + struct inode *inode =pFile->f_mapping->host; + int minor = iminor(inode); + pr_info("-->%s: ISPdev%d Ioctl runs, cmd:%d, args:%ld...\n", __func__, minor, cmd, arg); + + ret = (*(vvnative_ioctl+minor))(vvcam_isp_drv + minor, cmd, arg); + + return ret; +}; + +static int vvcam_isp_dev_mmap(struct file *pFile, struct vm_area_struct *vma) +{ + struct inode *inode =pFile->f_mapping->host; + int minor = iminor(inode); + ulong img_buf_base = vvnative_get_img_buf_base(); + ulong img_buf_size = vvnative_get_img_buf_size(); + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + unsigned long pfn_start = (img_buf_base >> PAGE_SHIFT) + vma->vm_pgoff; + unsigned long size = vma->vm_end - vma->vm_start; + int ret = 0; + + if(size > img_buf_size) + { + size = img_buf_size; + } + pr_info("-->%s: ISPdev%d mmap runs...\n", __func__, minor); + pr_info("-->%s: mmap parameters: phy start:0x%lx, ph size:0x%lx, vm start: 0x%lx, size: 0x%lx, offset, page start: 0x%lx\n", + __func__, img_buf_base, img_buf_size, vma->vm_start, size, offset, pfn_start); + + /* Map reserved image buffer memory. */ + if (remap_pfn_range(vma, vma->vm_start, + (img_buf_base >> PAGE_SHIFT), + size, vma->vm_page_prot)) + { + pr_err("-->%s: remap_pfn_range error!\n", __func__); + pr_info("-->%s: mmap parameters: phy start:0x%lx, ph size:0x%lx, vm start: 0x%lx, size: 0x%lx, offset\n", + __func__, img_buf_base, img_buf_size, vma->vm_start, size, offset); + return -EIO; + } + + return ret; +}; + +static int vvcam_isp_devio_remap(int dev_no) +{ + void __iomem *addr; + ulong reg_base = vvnative_get_reg_base_by_idx(dev_no); + ulong reg_size = vvnative_get_reg_size_by_idx(dev_no); + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: NULL pointer!\n", __func__); + return -1; + } + + (vvcam_isp_drv + dev_no)->phy_address = reg_base; + (vvcam_isp_drv + dev_no)->size = reg_size; + pr_info("ioremap of dev: %d, phy address:0x%lx, size:0x%lx\n", dev_no, reg_base, reg_size); + if((0 == reg_base) ||(0 == reg_size)) + { + (vvcam_isp_drv + dev_no)->base_address = NULL; + pr_info("ioremap of dev: %d, phy address is 0\n", dev_no); + }else{ + addr = ioremap(reg_base, reg_size); + pr_info("ioremap of dev: %d, address:0x%lx\n", dev_no, (unsigned long)addr); + (vvcam_isp_drv + dev_no)->base_address = addr; + } + + return 0; +} + +static int vvcam_isp_devio_unmap(int dev_no) +{ + if((NULL == vvcam_isp_drv)) + { + pr_err("-->%s: NULL pointer!\n", __func__); + return -1; + } + if(NULL != (vvcam_isp_drv + dev_no)->base_address) + { + iounmap((vvcam_isp_drv + dev_no)->base_address); + } + return 0; +} + +/*! +******************************************************************************* +** First function called by the OS. This function registers the device and +** vendor id that this driver handles. +*/ +int __init vvcam_isp_dev_initialize( void ) +{ + int result = 0; + struct device *dev; + dev_t devt; + int retval; + int dev_idx = 0; + struct class *vvisp_class; + + pr_info("-->%s enter\n", __func__); + pr_info("-->%s : %d, registerMemBase = 0x%lx, dev number:%d\n", __func__, __LINE__, VVISP0_BASE, VVCAM_ISP_DEVICES); + + /********************************************************************** + * register/alloc the device major number and range, if + * major = 0, alloc from kernel to get an available device major number + * major != 0, use the specific value as major number, this value may be invalid + **********************************************************************/ + vvcam_isp_drv = kzalloc(sizeof(struct vvcam_isp_dev) * VVCAM_ISP_DEVICES, GFP_KERNEL); + if (!vvcam_isp_drv) + { + return -ENOMEM; + } + + vvcam_drv_common = kzalloc(sizeof(struct vvcam_common), GFP_KERNEL); + if (!vvcam_drv_common) + { + return -ENOMEM; + } + + if (0 == vvcam_isp_dev_major) + { + result = alloc_chrdev_region(&devt, 0, VVCAM_ISP_DEVICES, DRIVER_NAME); + if (result) + { + goto fail_check; + } + vvcam_isp_dev_major = MAJOR(devt); + vvcam_isp_dev_minor = MINOR(devt); + } + else + { + devt = MKDEV(vvcam_isp_dev_major, vvcam_isp_dev_minor); + result = register_chrdev_region(devt, VVCAM_ISP_DEVICES, DRIVER_NAME); + if (result) + { + result = -EBUSY; + goto fail_check; + } + } + + pr_info("--> vvcam ISP init, major id: %d, minor id: %d\n", MAJOR(devt), MINOR(devt)); + + vvisp_class = class_create(THIS_MODULE, DRIVER_NAME); + if (IS_ERR(vvisp_class)) + { + pr_info("-->%s : %d, class_create error!\n", __func__, __LINE__); + goto fail_check; + } + + dev_idx = 0; + for(dev_idx = 0; dev_idx < VVCAM_ISP_DEVICES; dev_idx++) + { + if(strcmp(vvnative_get_dev_name_by_idx(dev_idx), VVNATIVE_NA) == 0) + { + pr_info("--> subisp%d is absent, id number:%s, skip..\n", dev_idx, vvnative_get_dev_name_by_idx(dev_idx) ); + (vvcam_isp_drv + dev_idx)->initialized = 0; + continue; + } + + (vvcam_isp_drv + dev_idx)->devt = MKDEV(vvcam_isp_dev_major, vvcam_isp_dev_minor + dev_idx); + + pr_info("--> subisp%d reg, major id: %d, minor id: %d, dev_name:%s\n", dev_idx, + MAJOR((vvcam_isp_drv + dev_idx)->devt), MINOR((vvcam_isp_drv + dev_idx)->devt), + vvnative_get_dev_name_by_idx(dev_idx)); + + cdev_init(&(vvcam_isp_drv + dev_idx)->cdev, &vvcam_isp_fops); + (vvcam_isp_drv + dev_idx)->cdev.owner = THIS_MODULE; + + retval = cdev_add(&(vvcam_isp_drv + dev_idx)->cdev, (vvcam_isp_drv + dev_idx)->devt, 1); + if (retval) + { + pr_info("-->%s : %d, cdev_add error!\n", __func__, __LINE__); + goto fail_check; + } + + (vvcam_isp_drv + dev_idx)->class = vvisp_class; + + dev = device_create((vvcam_isp_drv + dev_idx)->class, NULL, (vvcam_isp_drv + dev_idx)->devt, + (vvcam_isp_drv + dev_idx), "%s%d", vvnative_get_dev_name_by_idx(dev_idx), vvnative_get_dev_idx(dev_idx)); + if (IS_ERR(dev)) + { + pr_info("-->%s : %d, device_create error!\n", __func__, __LINE__); + class_destroy(vvcam_isp_drv->class); + goto fail_check; + } + pr_info("-->dev create for subisp %s %d done\n", DRIVER_NAME, dev_idx); + (vvcam_isp_drv + dev_idx)->dev = dev; + + + if(sysfs_create_file(&(dev->kobj), &dev_attr_vivdevio.attr)) { + pr_info("-->%s : %d, sysfs_create_file error!\n", __func__, __LINE__); + goto fail_check; + } + + /* init */ + mutex_init(&(vvcam_isp_drv + dev_idx)->vvmutex); + (vvcam_isp_drv + dev_idx)->open_cnt = 0; + (vvcam_isp_drv + dev_idx)->initialized = 1; + (vvcam_isp_drv + dev_idx)->dev_idx = vvnative_get_dev_idx(dev_idx); + + result = vvcam_isp_devio_remap(dev_idx); + if(result) + { + pr_err("-->%s: vvcam_isp_devio_remap error!\n", __func__); + goto fail_check; + } + + /* submodule initialization */ + result = (*(vvnative_init+dev_idx))(vvcam_isp_drv + dev_idx); + if(result) + { + pr_err("-->%s: vvnative_init error with subdev:%d!\n", __func__, dev_idx); + goto fail_check; + } + } + + /* on-the-fly debug init */ + mutex_init(&vvcam_drv_common->vvmutex); + sprintf(vvcam_drv_common->viv_buf, "vivisp_buf"); + return result; + +fail_check: + /* Unregister char driver */ + pr_info("-->vvcam_isp_dev_initialize error\n"); + unregister_chrdev_region(devt, VVCAM_ISP_DEVICES); + return result; +} + +/*! +******************************************************************************* +** Unload the driver module +*/ +void __exit vvcam_isp_dev_cleanup( void ) +{ + int result = 0; + int dev_idx = 0; + + pr_info("-->%s enter\n", __func__); + if(NULL == vvcam_isp_drv) + { + pr_info("-->%s Internal error, NULL pointer\n", __func__); + return; + } + for(dev_idx = 0; dev_idx < VVCAM_ISP_DEVICES; dev_idx++) + { + if(0 == (vvcam_isp_drv + dev_idx)->initialized) + { + continue; + } + + /* submodule un-initialization */ + result = (*(vvnative_deinit+dev_idx))(vvcam_isp_drv + dev_idx); + if(result) + { + pr_err("-->%s: vvnative_deinit error with subdev:%d!\n", __func__, dev_idx); + } + + result = vvcam_isp_devio_unmap(dev_idx); + if(result) + { + pr_err("-->%s: vvcam_isp_devio_unmap error!\n", __func__); + } + + device_destroy((vvcam_isp_drv + dev_idx)->class, (vvcam_isp_drv + dev_idx)->devt); + + cdev_del(&(vvcam_isp_drv + dev_idx)->cdev); + /* remove the char device structure (has been added) */ + + unregister_chrdev_region((vvcam_isp_drv + dev_idx)->devt, VVCAM_ISP_DEVICES); + (vvcam_isp_drv + dev_idx)->dev = NULL; + (vvcam_isp_drv + dev_idx)->open_cnt = 0; + } + + class_destroy(vvcam_isp_drv->class); + vvcam_isp_drv->class = NULL; + + kfree(vvcam_isp_drv); + vvcam_isp_drv = NULL; + kfree(vvcam_drv_common); + vvcam_drv_common = NULL; + + return; +} + +module_init(vvcam_isp_dev_initialize); +module_exit(vvcam_isp_dev_cleanup); + +MODULE_LICENSE ("GPL"); \ No newline at end of file diff --git a/vvcam_ry/common/vvnative.h b/vvcam_ry/common/vvnative.h new file mode 100755 index 0000000..c6fb967 --- /dev/null +++ b/vvcam_ry/common/vvnative.h @@ -0,0 +1,95 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVNATIVE_H_ +#define _VVNATIVE_H_ + +/* #include for kernel space */ +/* #include for user space */ + +#define VVISP_OPEN_LIMITATION 1 +#define VVISP_DBG_BUFFER 4096 + + +#define IOC_MAGIC 'v' +#define IOCINIT _IO(IOC_MAGIC, 0) + +struct vvcam_isp_dev { + struct device *dev; + struct cdev cdev; + dev_t devt; + int dev_idx; + + struct class *class; + int status; + + long phy_address; + long size; + void __iomem *base_address; + int base_range; + + struct mutex vvmutex; + int open_cnt; + int initialized; + void *private_ctx; +}; + +struct vvcam_common{ + struct mutex vvmutex; + char viv_buf[VVISP_DBG_BUFFER]; +}; + + + + + +#endif // _VVNATIVE_H_ \ No newline at end of file diff --git a/vvcam_ry/common/vvnative_cfg.c b/vvcam_ry/common/vvnative_cfg.c new file mode 100755 index 0000000..e470c25 --- /dev/null +++ b/vvcam_ry/common/vvnative_cfg.c @@ -0,0 +1,264 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include /* Module support */ +#include "vvnative_cfg.h" + +char vvcam_driver_name [][8]= +{ + #ifdef WITH_VVISP /* devid 0 */ + VVNATIVE_ISP, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVISP_DUAL /* devid 1 */ + VVNATIVE_ISP, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVCSI /* devid 2 */ + VVNATIVE_CSI, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVCSI_DUAL /* devid 3 */ + VVNATIVE_CSI, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVCAM /* devid 4 */ + VVNATIVE_SENSOR, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVCAM_DUAL /* devid 5 */ + VVNATIVE_SENSOR, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVDWE /* devid 6 */ + VVNATIVE_DWE, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVVSE /* devid 7 */ + VVNATIVE_VSE, + #else + VVNATIVE_NA, + #endif + #ifdef WITH_VVCTL /* devid 8 */ + VVNATIVE_SOC, + #else + VVNATIVE_NA, + #endif +}; + +char * vvnative_get_dev_name_by_idx(int devidx) +{ + if((devidx > VVCAM_ISP_DEVICES)||(devidx < 0)) + { + return VVNATIVE_NA; + } + return vvcam_driver_name[devidx]; +} + + +/* Parameters that can be set with 'insmod' */ +/* ISP */ +static ulong vvisp0_reg_base = VVISP0_BASE; +module_param(vvisp0_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH ); +MODULE_PARM_DESC(vvisp0_reg_base, "VVISP0 Reg Base address of AHB register"); + +static ulong vvisp1_reg_base = VVISP1_BASE; +module_param(vvisp1_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH ); +MODULE_PARM_DESC(vvisp1_reg_base, "VVISP1 Reg Base address of AHB register"); + +static ulong vvisp_reg_size = VVISP_SIZE; +module_param(vvisp_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvisp_reg_size, "VVISP0/1 Reg address range of AHB register"); + +/* CSI */ +static ulong vvcsi0_reg_base = VVCSI0_BASE; +module_param(vvcsi0_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcsi0_reg_base, "VVCSI0 Reg Base address of AHB register"); + +static ulong vvcsi1_reg_base = VVCSI1_BASE; +module_param(vvcsi1_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcsi1_reg_base, "VVCSI1 Reg Base address of AHB register"); + +static ulong vvcsi_reg_size = VVCSI_SIZE; +module_param(vvcsi_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcsi_reg_size, "VVCSI0/1 Reg address range of AHB register"); + +/* Sensor */ +static ulong vvcam0_reg_base = VVCAM0_BASE; +module_param(vvcam0_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcam0_reg_base, "VVCAM0 Reg Base address of AHB register"); + +static ulong vvcam1_reg_base = VVCAM1_BASE; +module_param(vvcam1_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcam1_reg_base, "VVCAM1 Reg Base address of AHB register"); + +static ulong vvcam_reg_size = VVCAM_SIZE; +module_param(vvcam_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvcam_reg_size, "VVCAM0/1 Reg address range of AHB register"); + +/* Dwe */ +static ulong vvdwe_reg_base = VVDWE_BASE; +module_param(vvdwe_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvdwe_reg_base, "VVDWE Reg Base address of AHB register"); + +static ulong vvdwe_reg_size = VVDWE_SIZE; +module_param(vvdwe_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvdwe_reg_size, "VVDWE Reg address range of AHB register"); + +/* Vse */ +static ulong vvvse_reg_base = VVVSE_BASE; +module_param(vvvse_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvvse_reg_base, "VVVSE Reg Base address of AHB register"); + +static ulong vvvse_reg_size = VVVSE_SIZE; +module_param(vvvse_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvvse_reg_size, "VVVSE Reg address range of AHB register"); + +/* Crtl */ +static ulong vvctl_reg_base = VVCTRL_BASE; +module_param(vvctl_reg_base, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvctl_reg_base, "VVCTRL Reg Base address of AHB register"); + +static ulong vvctl_reg_size = VVCTRL_SIZE; +module_param(vvctl_reg_size, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvctl_reg_size, "VVCTRL Reg address range of AHB register"); + + +static ulong vvImgBufBase = 0x10000000; +module_param(vvImgBufBase, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvImgBufBase, "Base addrss of memory reserved for ISP"); + +static ulong vvImgBufSize = 0x10000000; +module_param(vvImgBufSize, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvImgBufSize, "Size of memory reserved for ISP"); + + +ulong* reg_base_size_array[] = +{ + &vvisp0_reg_base, /* devid 0 */ + &vvisp_reg_size, + &vvisp1_reg_base, /* devid 1 */ + &vvisp_reg_size, + &vvcsi0_reg_base, /* devid 2 */ + &vvcsi_reg_size, + &vvcsi1_reg_base, /* devid 3 */ + &vvcsi_reg_size, + &vvcam0_reg_base, /* devid 4 */ + &vvcam_reg_size, + &vvcam1_reg_base, /* devid 5 */ + &vvcam_reg_size, + &vvdwe_reg_base, /* devid 6 */ + &vvdwe_reg_size, + &vvvse_reg_base, /* devid 7 */ + &vvvse_reg_size, + &vvctl_reg_base, /* devid 8 */ + &vvctl_reg_size, +}; + +ulong vvnative_get_reg_base_by_idx(int devidx) +{ + if((devidx > VVCAM_ISP_DEVICES)||(devidx < 0)) + { + return 0; + } + return *reg_base_size_array[devidx*2]; +} + +ulong vvnative_get_reg_size_by_idx(int devidx) +{ + if((devidx > VVCAM_ISP_DEVICES)||(devidx < 0)) + { + return 0; + } + return *reg_base_size_array[devidx*2 + 1]; +} + +int reg_dev_idx_array[] = +{ + 0, /* devid 0 isp0*/ + 1, /* devid 1 isp1 */ + 0, /* devid 2 csi0*/ + 1, /* devid 3 csi1*/ + 0, /* devid 4 cam0*/ + 1, /* devid 5 cam1*/ + 0, /* devid 6 dwe0*/ + 0, /* devid 7 vse0*/ + 0, /* devid 8 ctrl0*/ +}; + + +int vvnative_get_dev_idx(int devidx) +{ + if((devidx > VVCAM_ISP_DEVICES)||(devidx < 0)) + { + return -1; + } + return reg_dev_idx_array[devidx]; +} + + +ulong vvnative_get_img_buf_base(void) +{ + return vvImgBufBase; +} + +ulong vvnative_get_img_buf_size(void) +{ + return vvImgBufSize; +} diff --git a/vvcam_ry/common/vvnative_cfg.h b/vvcam_ry/common/vvnative_cfg.h new file mode 100755 index 0000000..b1052aa --- /dev/null +++ b/vvcam_ry/common/vvnative_cfg.h @@ -0,0 +1,78 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVNATIVE_CFG_H_ +#define _VVNATIVE_CFG_H_ + + +//#define DRIVER_NAME "" +#define DRIVER_NAME "vivisp_ry" + +#define VVNATIVE_ISP "vivisp_ry" +//#define VVNATIVE_CSI "vivcsi" +#define VVNATIVE_CSI "bm_csi" +#define VVNATIVE_SENSOR "vivcam" +#define VVNATIVE_DWE "vivdwe" +#define VVNATIVE_VSE "vivvse" +#define VVNATIVE_SOC "vivsoc" +#define VVNATIVE_NA "nondev" + +#define VVCAM_ISP_DEVICES (9) + +char * vvnative_get_dev_name_by_idx(int devidx); +ulong vvnative_get_reg_base_by_idx(int devidx); +ulong vvnative_get_reg_size_by_idx(int devidx); +ulong vvnative_get_img_buf_base(void); +ulong vvnative_get_img_buf_size(void); +int vvnative_get_dev_idx(int devidx); + +#endif // _VVNATIVE_CFG_H_ diff --git a/vvcam_ry/common/vvnative_combo.c b/vvcam_ry/common/vvnative_combo.c new file mode 100755 index 0000000..509b925 --- /dev/null +++ b/vvcam_ry/common/vvnative_combo.c @@ -0,0 +1,509 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include /* Charactor device support */ +#include + +#include "isp_ioctl.h" +#include "sensor_ioctl.h" +#include "csi_ioctl.h" +#include "soc_ioctl.h" +#include "dwe_ioctl.h" +#include "vse_ioctl.h" + + + +#include "vvnative.h" +#include "vvnative_combo.h" + +/* IOCTL combos */ +long vvcam_combo_isp_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct isp_ic_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: NULL pointer input!\n", __func__); + return -1; + } + + mutex_lock(&vvcam_isp_drv->vvmutex); + pr_info("-->%s: Ioctl runs, cmd:%d, args:%p...\n", __func__, cmd, args); + + dev = (struct isp_ic_dev *)vvcam_isp_drv->private_ctx; + ret = isp_priv_ioctl(dev, cmd, args); + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + + +long vvcam_combo_csi_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct vvcam_csi_dev *dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: NULL pointer input!\n", __func__); + return -1; + } + + mutex_lock(&vvcam_isp_drv->vvmutex); + + dev = (struct vvcam_csi_dev *)vvcam_isp_drv->private_ctx; + ret = csi_priv_ioctl(dev, cmd, args); + + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + +#if 0 +static struct i2c_board_info sensor_i2c_info = +{ + I2C_BOARD_INFO("sensor_ov2775", 0x00), +}; + +static void *vvcamGetSensorI2cClient(struct vvcam_isp_dev *vvcam_isp_drv) +{ + struct i2c_adapter *i2c_adap; + static struct i2c_client *i2c_client = NULL; + if (i2c_client == NULL) + { + i2c_adap = i2c_get_adapter(0); + i2c_client = i2c_new_device(i2c_adap, &sensor_i2c_info); + i2c_put_adapter(i2c_adap); + } + + return i2c_client; +} +#endif + +long vvcam_combo_sensor_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct vvcam_sensor_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: NULL pointer input!\n", __func__); + return -1; + } + + mutex_lock(&vvcam_isp_drv->vvmutex); + pr_info("-->%s: Ioctl runs, cmd:%d, args:%p...\n", __func__, cmd, args); + + dev = (struct vvcam_sensor_dev *)vvcam_isp_drv->private_ctx; + ret = sensor_priv_ioctl(dev, cmd, args); + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + +long vvcam_combo_dwe_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct dwe_ic_dev *dev; + + mutex_lock(&vvcam_isp_drv->vvmutex); + pr_info("-->%s: Ioctl runs, cmd:%d, args:%p...\n", __func__, cmd, args); + + dev = (struct dwe_ic_dev *)vvcam_isp_drv->private_ctx; + ret = dwe_priv_ioctl(dev, cmd, args); + + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + +long vvcam_combo_vse_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct vse_ic_dev *dev; + + mutex_lock(&vvcam_isp_drv->vvmutex); + pr_info("-->%s: Ioctl runs, cmd:%d, args:%p...\n", __func__, cmd, args); + + dev = (struct vse_ic_dev *)vvcam_isp_drv->private_ctx; + ret = vse_priv_ioctl(dev, cmd, args); + + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + +long vvcam_combo_soc_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args) +{ + long ret; + struct vvcam_soc_dev *dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: NULL pointer input!\n", __func__); + return -1; + } + + mutex_lock(&vvcam_isp_drv->vvmutex); + + dev = (struct vvcam_soc_dev *)vvcam_isp_drv->private_ctx; + ret = soc_priv_ioctl(dev, cmd, args); + + mutex_unlock(&vvcam_isp_drv->vvmutex); + + return ret; +} + +/* Submodule init combos */ +int vvcam_combo_isp_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct isp_ic_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct isp_ic_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct isp_ic_dev *)vvcam_isp_drv->private_ctx; + dev->base = vvcam_isp_drv->base_address; + + dev->reset = NULL; + + return ret; +} + +int vvcam_combo_csi_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_csi_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct vvcam_csi_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct vvcam_csi_dev *)vvcam_isp_drv->private_ctx; + + dev->base = vvcam_isp_drv->base_address; + dev->device_idx = vvcam_isp_drv->dev_idx; + ret = vvnative_csi_init(dev); + if (ret != 0) + { + pr_err("-->%s: vvnative_csi_init error!\n", __func__); + return -1; + } + + return ret; +} + +int vvcam_combo_sensor_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_sensor_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct vvcam_sensor_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct vvcam_sensor_dev *)vvcam_isp_drv->private_ctx; + dev->phy_addr = vvcam_isp_drv->phy_address; + dev->reg_size = vvcam_isp_drv->size; + dev->base = vvcam_isp_drv->base_address; + dev->device_idx = vvcam_isp_drv->dev_idx; + + ret = vvnative_sensor_init(dev); + if (ret != 0) + { + pr_err("-->%s: vvnative_sensor_init error!\n", __func__); + return -1; + } + + return ret; +} + +int vvcam_combo_dwe_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct dwe_ic_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct dwe_ic_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct dwe_ic_dev *)vvcam_isp_drv->private_ctx; + dev->base = vvcam_isp_drv->base_address; + + ret = vvnative_dwe_init(dev); + if (ret != 0) + { + pr_err("-->%s: vvnative_dwe_init error!\n", __func__); + return -1; + } + + return ret; +} + +int vvcam_combo_vse_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vse_ic_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct vse_ic_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct vse_ic_dev *)vvcam_isp_drv->private_ctx; + dev->base = vvcam_isp_drv->base_address; + + ret = vvnative_vse_init(dev); + if (ret != 0) + { + pr_err("-->%s: vvnative_vse_init error!\n", __func__); + return -1; + } + + return ret; +} + +int vvcam_combo_soc_init(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_soc_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + vvcam_isp_drv->private_ctx = kzalloc(sizeof(struct vvcam_soc_dev), GFP_KERNEL); + if(NULL == vvcam_isp_drv->private_ctx) + { + pr_err("-->%s: internal alloc memory error!\n", __func__); + return -1; + } + + dev = (struct vvcam_soc_dev *)vvcam_isp_drv->private_ctx; + dev->base = vvcam_isp_drv->base_address; + vvnative_soc_init(dev); + + return ret; +} + + + +/* Submodule deinit combos */ +int vvcam_combo_isp_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} + +int vvcam_combo_csi_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_csi_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + dev = (struct vvcam_csi_dev *)vvcam_isp_drv->private_ctx; + vvnative_csi_deinit(dev); + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} + +int vvcam_combo_sensor_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_sensor_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + dev = (struct vvcam_sensor_dev *)vvcam_isp_drv->private_ctx; + vvnative_sensor_deinit(dev); + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} + +int vvcam_combo_dwe_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct dwe_ic_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + dev = (struct dwe_ic_dev *)vvcam_isp_drv->private_ctx; + vvnative_dwe_deinit(dev); + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} + +int vvcam_combo_vse_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vse_ic_dev * dev; + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + dev = (struct vse_ic_dev *)vvcam_isp_drv->private_ctx; + vvnative_vse_deinit(dev); + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} + +int vvcam_combo_soc_deinit(struct vvcam_isp_dev *vvcam_isp_drv) +{ + int ret = 0; + struct vvcam_soc_dev * dev; + + if(NULL == vvcam_isp_drv) + { + pr_err("-->%s: input NULL pointer!\n", __func__); + return -1; + } + + if(NULL != vvcam_isp_drv->private_ctx) + { + dev = (struct vvcam_soc_dev *)vvcam_isp_drv->private_ctx; + vvnative_soc_deinit(dev); + kzfree(vvcam_isp_drv->private_ctx); + vvcam_isp_drv->private_ctx = NULL; + } + + return ret; +} diff --git a/vvcam_ry/common/vvnative_combo.h b/vvcam_ry/common/vvnative_combo.h new file mode 100755 index 0000000..46c6ef6 --- /dev/null +++ b/vvcam_ry/common/vvnative_combo.h @@ -0,0 +1,78 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVNATIVE_COMBO_H_ +#define _VVNATIVE_COMBO_H_ + +long vvcam_combo_isp_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); +long vvcam_combo_csi_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); +long vvcam_combo_sensor_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); +long vvcam_combo_dwe_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); +long vvcam_combo_vse_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); +long vvcam_combo_soc_ioctl(struct vvcam_isp_dev *vvcam_isp_drv,unsigned int cmd, void *args); + +int vvcam_combo_isp_init(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_csi_init(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_sensor_init(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_dwe_init(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_vse_init(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_soc_init(struct vvcam_isp_dev *vvcam_isp_drv); + +int vvcam_combo_isp_deinit(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_csi_deinit(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_sensor_deinit(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_dwe_deinit(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_vse_deinit(struct vvcam_isp_dev *vvcam_isp_drv); +int vvcam_combo_soc_deinit(struct vvcam_isp_dev *vvcam_isp_drv); + +#endif + diff --git a/vvcam_ry/common/vvsensor.h b/vvcam_ry/common/vvsensor.h new file mode 100755 index 0000000..f734247 --- /dev/null +++ b/vvcam_ry/common/vvsensor.h @@ -0,0 +1,264 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVSENSOR_PUBLIC_HEADER_H_ +#define _VVSENSOR_PUBLIC_HEADER_H_ + +#ifndef __KERNEL__ +#include +#else +#include +#endif + +#define VVCAM_SUPPORT_MAX_MODE_COUNT 20 +#define VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS 8 + +enum { + VVSENSORIOC_RESET = 0x100, + VVSENSORIOC_S_CLK, + VVSENSORIOC_G_CLK, + VVSENSORIOC_S_POWER, + VVSENSORIOC_G_POWER, + VVSENSORIOC_SENSOR_SCCB_CFG, + VVSENSORIOC_FOCUS_SCCB_CFG, + VVSENSORIOC_READ_REG, + VVSENSORIOC_WRITE_REG, + VVSENSORIOC_READ_ARRAY, + VVSENSORIOC_WRITE_ARRAY, + VVSENSORIOC_AF_READ_REG, + VVSENSORIOC_AF_WRITE_REG, + VVSENSORIOC_G_MIPI, + VVSENSORIOC_G_NAME, + VVSENSORIOC_G_RESERVE_ID, + VVSENSORIOC_G_CHIP_ID, + VVSENSORIOC_S_INIT, + VVSENSORIOC_S_STREAM, + VVSENSORIOC_S_LONG_EXP, + VVSENSORIOC_S_EXP, + VVSENSORIOC_S_VSEXP, + VVSENSORIOC_S_LONG_GAIN, + VVSENSORIOC_S_GAIN, + VVSENSORIOC_S_VSGAIN, + VVSENSORIOC_S_FRAMESIZE, + VVSENSORIOC_ENUM_FRAMESIZES, + VVSENSORIOC_S_HDR_MODE, + VVSENSORIOC_G_HDR_MODE, + VVSENSORIOC_S_FPS, + VVSENSORIOC_G_FPS, + VVSENSORIOC_S_HDR_RADIO, + VVSENSORIOC_G_AE_INFO, + VVSENSORIOC_QUERY, + VVSENSORIOC_G_SENSOR_MODE, + VVSENSORIOC_S_WB, + VVSENSORIOC_S_BLC, + VVSENSORIOC_G_EXPAND_CURVE, + VVSENSORIOC_S_SENSOR_MODE, + VVSENSORIOC_MAX, +}; + +/* W/R registers */ +struct vvcam_sccb_data { + uint32_t addr; + uint32_t data; +}; + +/* init settings */ +struct vvsensor_reg_value_t { + uint16_t addr; + uint8_t val; + uint8_t mask; + uint32_t delay; +}; + +/* priv ioctl */ +struct vvsensor_gain_context { + uint32_t again; + uint32_t dgain; +}; + +/* vsi native usage */ +struct vvcam_sccb_cfg_s { + uint8_t slave_addr; + uint8_t addr_byte; + uint8_t data_byte; +}; + +struct vvcam_sccb_array { + uint32_t count; + struct vvcam_sccb_data *sccb_data; +}; + +typedef struct vvcam_ae_info_s { + uint32_t DefaultFrameLengthLines; + uint32_t CurFrameLengthLines; + uint32_t one_line_exp_time_ns; + uint32_t max_integration_time; + uint32_t min_integration_time; + uint32_t integration_accuracy; + uint32_t max_gain; + uint32_t min_gain; + uint32_t gain_accuracy; + uint32_t cur_fps; + uint32_t hdr_radio; +} vvcam_ae_info_t; + +struct sensor_mipi_info { + uint32_t mipi_lane; + uint32_t sensor_data_bit; +}; + +enum sensor_hdr_mode_e +{ + SENSOR_MODE_LINEAR , + SENSOR_MODE_HDR_STITCH, + SENSOR_MODE_HDR_NATIVE, +}; + +enum SENSOR_BAYER_PATTERN_E +{ + BAYER_RGGB = 0, + BAYER_GRBG = 1, + BAYER_GBRG = 2, + BAYER_BGGR = 3, + BAYER_BUTT +}; + +enum sensor_stitching_mode_e +{ + SENSOR_STITCHING_DUAL_DCG = 0, /**< dual DCG mode 3x12-bit */ + SENSOR_STITCHING_3DOL = 1, /**< dol3 frame 3x12-bit */ + SENSOR_STITCHING_LINEBYLINE = 2, /**< 3x12-bit line by line without waiting */ + SENSOR_STITCHING_16BIT_COMPRESS = 3, /**< 16-bit compressed data + 12-bit RAW */ + SENSOR_STITCHING_DUAL_DCG_NOWAIT = 4, /**< 2x12-bit dual DCG without waiting */ + SENSOR_STITCHING_2DOL = 5, /**< dol2 frame or 1 CG+VS sx12-bit RAW */ + SENSOR_STITCHING_L_AND_S = 6, /**< L+S 2x12-bit RAW */ + SENSOR_STITCHING_MAX + +}; + +typedef struct sensor_expand_curve_s +{ + uint32_t x_bit; + uint32_t y_bit; + uint8_t expand_px[64]; + uint32_t expand_x_data[65]; + uint32_t expand_y_data[65]; +}sensor_expand_curve_t; + +typedef struct sensor_data_compress_s +{ + uint32_t enable; + uint32_t x_bit; + uint32_t y_bit; +}sensor_data_compress_t; + + +typedef struct vvcam_mode_info { + uint32_t index; + uint32_t width; + uint32_t height; + uint32_t fps; + uint32_t hdr_mode; + uint32_t stitching_mode; + uint32_t bit_width; + sensor_data_compress_t data_compress; + uint32_t bayer_pattern; + vvcam_ae_info_t ae_info; + void *preg_data; + uint32_t reg_data_count; + +} vvcam_mode_info_t; + +typedef struct sensor_blc_s +{ + uint32_t red; + uint32_t gr; + uint32_t gb; + uint32_t blue; +}sensor_blc_t; + +typedef struct sensor_white_balance_s +{ + uint32_t r_gain; + uint32_t gr_gain; + uint32_t gb_gain; + uint32_t b_gain; +}sensor_white_balance_t; + +typedef struct vvcam_mode_info_array { + uint32_t count; + struct vvcam_mode_info modes[VVCAM_SUPPORT_MAX_MODE_COUNT]; +} vvcam_mode_info_array_t; + + +#ifdef SENSOR_CROP +/************************************** +*Reserved for sensor crop +***************************************/ +typedef struct sensor_crop_regions_s +{ + uint32_t offs_x; + uint32_t offs_y; + uint32_t width; + uint32_t height; +}sensor_crop_regions_t; + +typedef struct sensor_crop_limits_s +{ + uint32_t mode_index; + sensor_crop_regions_t max_regions; + sensor_crop_regions_t min_regions; +}sensor_crop_limits_t; +#endif + +#endif + diff --git a/vvcam_ry/csi/csi_ioctl.c b/vvcam_ry/csi/csi_ioctl.c new file mode 100755 index 0000000..21d0365 --- /dev/null +++ b/vvcam_ry/csi/csi_ioctl.c @@ -0,0 +1,204 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef __KERNEL__ +#include +#include +#include +#include + +#define pr_info printf +#define pr_err printf +#define copy_from_user(a, b, c) csi_copy_data(a, b, c) +#define copy_to_user(a, b, c) csi_copy_data(a, b, c) +#define __user +#define __iomem + +void csi_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); +} + +#else // __KERNEL__ +#include /* Module support */ +#include + +#endif + +#include "csi_ioctl.h" +#include "vivcsi_hub.h" + + +long csi_priv_ioctl(struct vvcam_csi_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + if (!dev) { + return ret; + } + + switch (cmd) { + case VVCSI_IOC_S_RESET: + ret = vivcsi_hub_reset(dev); + break; + + case VVCSI_IOC_S_POWER: + copy_from_user(&dev->power_status, args, sizeof(dev->power_status)); + ret = vivcsi_hub_set_power(dev); + break; + + case VVCSI_IOC_G_POWER: + ret = vivcsi_hub_get_power(dev); + copy_to_user(args, &dev->power_status, sizeof(dev->power_status)); + break; + + case VVCSI_IOC_S_CLOCK: + copy_from_user(&dev->clock, args, sizeof(dev->clock)); + ret = vivcsi_hub_set_clock(dev); + break; + + case VVCSI_IOC_G_CLOCK: + ret = vivcsi_hub_get_clock(dev); + copy_to_user(args, &dev->clock, sizeof(dev->clock)); + ret = 0; + break; + + case VVCSI_IOC_S_STREAM: + copy_from_user(&dev->streaming_enable, args, sizeof(dev->streaming_enable)); + ret = vivcsi_hub_set_stream_control(dev); + break; + + case VVCSI_IOC_G_STREAM: + ret = vivcsi_hub_get_stream_control(dev); + copy_to_user(args, &dev->streaming_enable, sizeof(dev->streaming_enable)); + break; + + case VVCSI_IOC_S_FMT: + copy_from_user(&dev->csi_format, args, sizeof(dev->csi_format)); + ret = vivcsi_hub_set_fmt(dev); + break; + + case VVCSI_IOC_G_FMT: + ret = vivcsi_hub_get_fmt(dev); + copy_to_user(args, &dev->csi_format, sizeof(dev->csi_format)); + break; + + case VVCSI_IOC_S_VC_SELECT: + copy_from_user(&dev->csi_vc_select, args, sizeof(dev->csi_vc_select)); + ret = vivcsi_hub_set_vc_select(dev); + break; + + case VVCSI_IOC_G_VC_SELECT: + ret = vivcsi_hub_get_vc_select(dev); + copy_to_user(args, &dev->csi_vc_select, sizeof(dev->csi_vc_select)); + break; + case VVCSI_IOC_S_LANE_CFG: + copy_from_user(&dev->csi_lane_cfg, args, sizeof(dev->csi_lane_cfg)); + ret = vivcsi_hub_set_csi_lane_cfg(dev); + break; + default: + pr_err("unsupported command %d", cmd); + break; + } + + return ret; +} + +extern struct vvcam_csi_hardware_function_s nwl_mipi_function; + +int vvnative_csi_init(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if (dev == NULL) + { + pr_err("[%s] dev is NULL\n", __func__); + return -1; + } + + vvcsi_register_hardware(dev,&nwl_mipi_function); + if (dev->csi_hard_func.init) + { + ret = dev->csi_hard_func.init(dev); + if (ret < 0) + { + pr_err("[%s] init failed\n", __func__); + return -1; + } + } + return 0; +} + +int vvnative_csi_deinit(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if (dev == NULL) + { + pr_err("[%s] dev is NULL\n", __func__); + return -1; + } + + if (dev->csi_hard_func.exit) + { + ret = dev->csi_hard_func.exit(dev); + if (ret < 0) + { + pr_err("[%s] exit failed\n", __func__); + return -1; + } + } + + return 0; +} + + diff --git a/vvcam_ry/csi/csi_ioctl.h b/vvcam_ry/csi/csi_ioctl.h new file mode 100755 index 0000000..b3f7dae --- /dev/null +++ b/vvcam_ry/csi/csi_ioctl.h @@ -0,0 +1,153 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _CSI_IOC_H_ +#define _CSI_IOC_H_ + +#ifndef __KERNEL__ +#include +#endif +#include + +enum { + VVCSI_IOC_S_RESET = _IO('r', 0), + VVCSI_IOC_S_POWER, + VVCSI_IOC_G_POWER, + VVCSI_IOC_S_CLOCK, + VVCSI_IOC_G_CLOCK, + VVCSI_IOC_S_STREAM, + VVCSI_IOC_G_STREAM, + VVCSI_IOC_S_FMT, + VVCSI_IOC_G_FMT, + VVCSI_IOC_S_VC_SELECT, + VVCSI_IOC_G_VC_SELECT, + VVCSI_IOC_S_LANE_CFG, + VVCSI_IOC_MAX, +}; + +struct csi_vc_select_context { + uint32_t csi_vc_select_mode; + uint32_t vc_channel; +}; + +struct csi_format_context { + uint32_t format; + uint32_t width; + uint32_t height; +}; + +struct vvcam_csi_hardware_function_s +{ + int (*init)(void* dev); + int (*exit)(void* dev); + int (*reset)(void* dev); + int (*set_power)(void* dev); + int (*get_power)(void* dev); + int (*set_clock)(void* dev); + int (*get_clock)(void* dev); + int (*set_stream_control)(void* dev); + int (*get_stream_control)(void* dev); + int (*set_fmt)(void* dev); + int (*get_fmt)(void* dev); + int (*set_vc_select)(void* dev); + int (*get_vc_select)(void* dev); + int (*set_lane_cfg)(void* dev); +}; + +struct vvcam_csi_lane_cfg +{ + uint32_t mipi_lane_num; +}; + +struct vvcam_csi_access_s +{ + int (*write)(void * ctx, uint32_t address, uint32_t data); + int (*read)(void * ctx, uint32_t address, uint32_t *data); +}; + + +#ifdef __KERNEL__ + +struct vvcam_csi_dev { + void __iomem *base; + char name[16]; + + int present; + int device_idx; + + uint32_t power_status; + uint32_t clock; + + uint32_t streaming_enable; + struct csi_vc_select_context csi_vc_select; + struct csi_format_context csi_format; + struct vvcam_csi_hardware_function_s csi_hard_func; + struct vvcam_csi_access_s csi_access; + struct vvcam_csi_lane_cfg csi_lane_cfg; + void * csi_private; +}; + +// internal functions + +long csi_priv_ioctl(struct vvcam_csi_dev *dev, unsigned int cmd, void *args); +int vvnative_csi_init(struct vvcam_csi_dev *dev); +int vvnative_csi_deinit(struct vvcam_csi_dev *dev); + + + +#else +//User space connections + + +#endif + +#endif // _CSI_IOC_H_ diff --git a/vvcam_ry/csi/nwl/nwl_core.c b/vvcam_ry/csi/nwl/nwl_core.c new file mode 100755 index 0000000..feecbb0 --- /dev/null +++ b/vvcam_ry/csi/nwl/nwl_core.c @@ -0,0 +1,322 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#ifdef ISP8000L_V2008 +#include //Fix thead compile error. +#endif + +#include "nwl_regs.h" +#include "../csi_ioctl.h" + + +int nwl_register_write(void * dev,unsigned int addr, unsigned int data) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + writel(data, base_addr + addr); + + return 0; +} + +int nwl_register_read(void * dev,unsigned int addr, unsigned int *data) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + *data = readl(base_addr + addr); + + return 0; +} + + +static int nwl_init(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + nwl_csi_dev->csi_access.write = nwl_register_write; + nwl_csi_dev->csi_access.read = nwl_register_read; + + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_NUM_LANES, 0x4); + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_LANES_CLK, 0x1); + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_LANES_DATA, 0xF); + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_IGNORE_VC, 0x1); + + if (nwl_csi_dev->device_idx == 0) + { + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI0_CTRL, 0x4); + }else + { + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI1_CTRL, 0x4); + } + + return 0; +} + +static int nwl_exit(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_reset(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_power(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_get_power(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_clock(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_get_clock(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_stream_control(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + u32 clock_status; + u32 data_status; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + if (nwl_csi_dev->streaming_enable) + { + clock_status = 0x01; + data_status = 0xFF; + } + else + { + clock_status = 0x00; + data_status = 0x00; + } + + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_LANES_CLK, clock_status); + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_LANES_DATA, data_status); + return 0; +} + +static int nwl_get_stream_control(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_fmt(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_get_fmt(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_vc_select(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_get_vc_select(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + return 0; +} + +static int nwl_set_lane_cfg(void * dev) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + nwl_csi_dev->csi_access.write(dev,MRV_MIPICSI_NUM_LANES, nwl_csi_dev->csi_lane_cfg.mipi_lane_num); + + return 0; +} + +struct vvcam_csi_hardware_function_s nwl_mipi_function = +{ + .init = nwl_init, + .exit = nwl_exit, + .reset = nwl_reset, + .set_power = nwl_set_power, + .get_power = nwl_get_power, + .set_clock = nwl_set_clock, + .get_clock = nwl_get_clock, + .set_stream_control = nwl_set_stream_control, + .get_stream_control = nwl_get_stream_control, + .set_fmt = nwl_set_fmt, + .get_fmt = nwl_get_fmt, + .set_vc_select = nwl_set_vc_select, + .get_vc_select = nwl_get_vc_select, + .set_lane_cfg = nwl_set_lane_cfg, +}; + + diff --git a/vvcam_ry/csi/nwl/nwl_ioctl.c b/vvcam_ry/csi/nwl/nwl_ioctl.c new file mode 100755 index 0000000..9b168d5 --- /dev/null +++ b/vvcam_ry/csi/nwl/nwl_ioctl.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include "nwl_driver.h" +#endif +#include "nwl_ioctl.h" +#include "nwl_regs.h" + +#ifndef __KERNEL__ +#include +#include "common_dev.h" + +#define NWL_EXTREG_OFFSET 0x308244 +#define NWL_REG_OFFSET 0x300000 + +static HalHandle_t hal_handle; +void nwl_ic_set_hal(HalHandle_t hal) +{ + hal_handle = hal; +} + +void nwl_write_reg(u32 offset, u32 val) +{ + offset += NWL_REG_OFFSET; + HalWriteReg(hal_handle, offset, val); +} + +u32 nwl_read_reg(u32 offset) +{ + offset += NWL_REG_OFFSET; + return HalReadReg(hal_handle, offset); +} + +u32 nwl_write_extreg(u32 offset, u32 val) +{ + offset += NWL_EXTREG_OFFSET; + return HalReadReg(hal_handle, offset); +} + +int nwl_set_stream(void *dev, int enable) +{ + u32 clock_status; + u32 data_status; + + nwl_write_reg(MRV_MIPICSI1_NUM_LANES, 0x4); + + if (enable == true) { + clock_status = 0x1; + data_status = 0xFF; + } else { + clock_status = 0x0; + data_status = 0x0; + } + nwl_write_reg(MRV_MIPICSI1_LANES_CLK, clock_status); + nwl_write_reg(MRV_MIPICSI1_LANES_DATA, data_status); + + return 0; +} + +int nwl_init(void) +{ + nwl_write_reg(MRV_MIPICSI1_NUM_LANES, 0x4); + nwl_write_reg(MRV_MIPICSI1_LANES_CLK, 0x1); + nwl_write_reg(MRV_MIPICSI1_LANES_DATA, 0xF); + nwl_write_reg(MRV_MIPICSI1_IGNORE_VC, 0x1); + nwl_write_extreg(MRV_MIPICSI1_OUT_SHIFT, 0x4); + + return 0; +} +#endif + +int nwl_ioc_init(void) +{ + nwl_init(); + + return 0; +} + +int nwl_ioc_s_stream(void *dev, void *__user args) +{ + int enable; + + copy_from_user(&enable, args, sizeof(enable)); + nwl_set_stream(dev, enable); + return 0; +} + +long nwl_priv_ioctl(void *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + switch (cmd) { + case CSIIOC_INIT: + ret = nwl_ioc_init(); + break; + case CSIIOC_S_STREAM:{ + ret = nwl_ioc_s_stream(dev, args); + } + break; + default: + pr_err("Unsupported csi command %d.\n", cmd); + break; + } + + return ret; +} diff --git a/vvcam_ry/csi/nwl/nwl_ioctl.h b/vvcam_ry/csi/nwl/nwl_ioctl.h new file mode 100755 index 0000000..a561015 --- /dev/null +++ b/vvcam_ry/csi/nwl/nwl_ioctl.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _NWL_IOC_H_ +#define _NWL_IOC_H_ + +enum { + CSIIOC_INIT = 0, + CSIIOC_S_STREAM, +}; + +long nwl_priv_ioctl(void *dev, unsigned int cmd, void *args); + +#endif /* _NWL_IOC_H_ */ diff --git a/vvcam_ry/csi/nwl/nwl_regs.h b/vvcam_ry/csi/nwl/nwl_regs.h new file mode 100755 index 0000000..6ba7749 --- /dev/null +++ b/vvcam_ry/csi/nwl/nwl_regs.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _NWL_REGS_H_ +#define _NWL_REGS_H_ + +/* + * MRV_MIPICSI1_NUM_LANES + * Config num lanes register [3:0] rw + * 0000b - controller off + * 0001b - 1 Lane + * 0010b - 2 Lanes + * 0011b - 3 Lanes + * 0100b - 4 Lanes + */ +#define MRV_MIPICSI_NUM_LANES 0x0 + +/* + * MRV_MIPICSI1_LANES_CLK + * Configure lanes clock [0] + * 0b - disable + * 1b - enable + */ +#define MRV_MIPICSI_LANES_CLK 0x4 + +/* + * MRV_MIPICSI1_LANES_DATA + * enable/disable lanes data [7:0] + * setting bits to a '1' value enable data lane + */ +#define MRV_MIPICSI_LANES_DATA 0x8 + +/* + * MRV_MIPICSI1_IGNORE_VC + * enable/disable lanes clock [0] + * setting bits to a '1' value enable data value + */ +#define MRV_MIPICSI_IGNORE_VC 0x80 + +/* + * MRV_MIPICSI1_OUT_SHIFT + * Configure csi_vid_out register + */ + +#define MRV_MIPICSI0_CTRL 0x108240 //0x308240 +#define MRV_MIPICSI1_CTRL 0x8244 //0x308244 + +#endif /* _NWL_REGS_H_ */ diff --git a/vvcam_ry/csi/vivcsi_hub.c b/vvcam_ry/csi/vivcsi_hub.c new file mode 100755 index 0000000..467fb41 --- /dev/null +++ b/vvcam_ry/csi/vivcsi_hub.c @@ -0,0 +1,335 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include "csi_ioctl.h" +#include "vivcsi_hub.h" + +unsigned int vvcsi_register_hardware(struct vvcam_csi_dev *dev, struct vvcam_csi_hardware_function_s *func) +{ + int ret = 0; + if (func == NULL) + { + return -1; + } + + memcpy(&dev->csi_hard_func,func,sizeof(struct vvcam_csi_hardware_function_s)); + return 0; +} + +int vivcsi_hub_init(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.init == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.init(dev); + + return ret; +} + + +int vivcsi_hub_reset(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.reset == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.reset(dev); + + return ret; +} + + +int vivcsi_hub_set_power(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_power == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_power(dev); + + return ret; +} + +int vivcsi_hub_get_power(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.get_power == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.get_power(dev); + + return ret; +} + +int vivcsi_hub_set_clock(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_clock == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_clock(dev); + + return ret; +} + +int vivcsi_hub_get_clock(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.get_clock == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.get_clock(dev); + + return ret; +} + + +int vivcsi_hub_set_stream_control(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_stream_control == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_stream_control(dev); + + return ret; +} + +int vivcsi_hub_get_stream_control(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.get_stream_control == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.get_stream_control(dev); + + return ret; +} + +int vivcsi_hub_set_fmt(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_fmt == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_fmt(dev); + + return ret; +} + +int vivcsi_hub_get_fmt(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.get_fmt == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.get_fmt(dev); + + return ret; +} + +int vivcsi_hub_set_vc_select(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_vc_select == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_vc_select(dev); + + return ret; +} + + +int vivcsi_hub_get_vc_select(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.get_vc_select == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.get_vc_select(dev); + + return ret; +} + +int vivcsi_hub_set_csi_lane_cfg(struct vvcam_csi_dev *dev) +{ + int ret = 0; + if(NULL == dev) + { + pr_err("%s:dev is null!\n", __func__); + return -1; + } + + if (dev->csi_hard_func.set_lane_cfg == NULL) + { + pr_err("%s:csi_hard_func is NULL!\n", __func__); + return -1; + } + + ret = dev->csi_hard_func.set_lane_cfg(dev); + + return ret; + +} + diff --git a/vvcam_ry/csi/vivcsi_hub.h b/vvcam_ry/csi/vivcsi_hub.h new file mode 100755 index 0000000..6f9368e --- /dev/null +++ b/vvcam_ry/csi/vivcsi_hub.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VIVCSI_HUB_H_ +#define _VIVCSI_HUB_H_ + +unsigned int vvcsi_register_hardware(struct vvcam_csi_dev *dev, struct vvcam_csi_hardware_function_s *func); + +int vivcsi_hub_init(struct vvcam_csi_dev *dev); +int vivcsi_hub_reset(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_power(struct vvcam_csi_dev *dev); +int vivcsi_hub_get_power(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_clock(struct vvcam_csi_dev *dev); +int vivcsi_hub_get_clock(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_stream_control(struct vvcam_csi_dev *dev); +int vivcsi_hub_get_stream_control(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_fmt(struct vvcam_csi_dev *dev); +int vivcsi_hub_get_fmt(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_vc_select(struct vvcam_csi_dev *dev); +int vivcsi_hub_get_vc_select(struct vvcam_csi_dev *dev); +int vivcsi_hub_set_csi_lane_cfg(struct vvcam_csi_dev *dev); + +#endif /* _VIVCSI_HUB_H_ */ diff --git a/vvcam_ry/dw200/dw200_ioctl.c b/vvcam_ry/dw200/dw200_ioctl.c new file mode 100755 index 0000000..3e5d725 --- /dev/null +++ b/vvcam_ry/dw200/dw200_ioctl.c @@ -0,0 +1,1022 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +//#include "dw200_driver.h" +#else +#include +#include +#include +#endif + +#include "dw200_ioctl.h" +#include "dwe_regs.h" +#include "vse_regs.h" +#undef ALIGN_UP +#define ALIGN_UP(x, align) (((x) + ((align) - 1)) & ~((align)-1)) + +#ifndef __KERNEL__ +#ifdef HAL_CMODEL +#define DEWARP_REGISTER_OFFSET 0xc00 +#else +#define DEWARP_REGISTER_OFFSET 0x380000 +#endif + +#define DEWARP_REGISTER_CTL 0x308250 + + +pReadBar g_dw200_read_func; +pWriteBar g_dw200_write_func; + +void dwe_set_func(pReadBar read_func, pWriteBar write_func) +{ + g_dw200_read_func = read_func; + g_dw200_write_func = write_func; +} + + +void dwe_write_reg(struct dw200_subdev *dev, u32 offset, u32 val) +{ + g_dw200_write_func(DEWARP_REGISTER_OFFSET + offset, val); +} + +u32 dwe_read_reg(struct dw200_subdev *dev, u32 offset) +{ + u32 data; + g_dw200_read_func(DEWARP_REGISTER_OFFSET + offset, &data); + return data; +} + +long dw200_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); + return 0; +} + +void vse_set_func(pVseReadBar read_func, pVseWriteBar write_func) +{ + g_dw200_read_func = read_func; + g_dw200_write_func = write_func; +} + +void vse_write_reg(struct dw200_subdev *dev, u32 offset, u32 val) +{ + g_dw200_write_func(offset, val); +} + +u32 vse_read_reg(struct dw200_subdev *dev, u32 offset) +{ + u32 data; + g_dw200_read_func(offset, &data); + return data; +} +#else + +void dwe_write_reg(struct dw200_subdev *dev, u32 offset, u32 val) +{ + pr_info("dwe write addr 0x%08x val 0x%08x\n",offset,val); + __raw_writel(val, dev->dwe_base + offset); +} + +u32 dwe_read_reg(struct dw200_subdev *dev, u32 offset) +{ + u32 val; + val=__raw_readl(dev->dwe_base + offset); + pr_info("dwe read addr 0x%08x val 0x%08x\n",offset,val); + return val; +} + +void vse_write_reg(struct dw200_subdev *dev, u32 offset, u32 val) +{ + pr_info("vse write addr 0x%08x val 0x%08x\n",offset,val); + __raw_writel(val, dev->vse_base + offset); +} + +u32 vse_read_reg(struct dw200_subdev *dev, u32 offset) +{ + u32 val; + return __raw_readl(dev->vse_base + offset); + pr_info("vse read addr 0x%08x val 0x%08x\n",offset,val); + return val; +} + +#endif + +int dwe_reset(struct dw200_subdev *dev) +{ + pr_info("enter %s\n", __func__); +#ifdef DWE_REG_RESET + __raw_writel(0, dev->dwe_reset); + __raw_writel(1, dev->dwe_reset); +#endif + dwe_write_reg(dev, DEWARP_CTRL, 0x0c); + return 0; +} + +int dwe_s_params(struct dw200_subdev *dev) +{ + struct dwe_hw_info *info = &dev->dwe_info; + u32 reg = 0; + u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16); + u32 vUp = (info->split_v1 & ~0x0F) | 0x0C; + u32 vDown = (info->split_v2 & ~0x0F) | 0x0C; + u32 hLine = (info->split_h & ~0x0F) | 0x0C; + u32 dst_img_width_bn = (info->out_yuvbit == 1)? (info->dst_w*2) : info->dst_w; + + pr_info("enter %s\n", __func__); + + dwe_write_reg(dev, MAP_LUT_SIZE, + ((info->map_w & 0x7ff) | ((info->map_h & 0x7ff) << 16))); + dwe_write_reg(dev, SRC_IMG_SIZE, + ((info->src_w & 0x1fff) | + ((info->src_h & 0x1fff) << 16))); + dwe_write_reg(dev, SRC_IMG_STRIDE, info->src_stride); + + dwe_write_reg(dev, DST_IMG_SIZE, + ((info->dst_w & 0x1FFF) | + ((info->dst_h & 0x1FFF) << 16))); + + dwe_write_reg(dev, DST_IMG_WIDTH_BN, + ((dst_img_width_bn & 0x7FFF) | + ((dst_img_width_bn & 0x7FFF) << 16))); + dwe_write_reg(dev, DST_IMG_STRIDE, info->dst_stride); + dwe_write_reg(dev, DST_IMG_Y_SIZE1, reg_y_rbuff_size >> 4); + dwe_write_reg(dev, DST_IMG_UV_SIZE1, info->dst_size_uv >> 4); + dwe_write_reg(dev, VERTICAL_SPLIT_LINE, + (vUp & 0x1fff) | ((vDown & 0x1fff) << 16)); + dwe_write_reg(dev, HORIZON_SPLIT_LINE, (hLine & 0x1fff)); + + reg = 0x4c808009; + reg |= ((info->split_line & 0x1) << 11); + reg |= ((info->in_format & 0x3) << 4); + reg |= ((info->out_format & 0x3) << 6); + reg |= ((info->in_yuvbit & 0x1) << 12); + reg |= ((info->out_yuvbit & 0x1) << 13); + reg |= + ((info->src_auto_shadow & 0x1) << 8) | + ((info->dst_auto_shadow & 0x1) << 10); + reg |= ((info->hand_shake & 0x1) << 9); + dwe_write_reg(dev, DEWARP_CTRL, reg); + + dwe_write_reg(dev, BOUNDRY_PIXEL, + (((info->boundary_y & 0xff) << 16) | + ((info->boundary_u & 0xff) + << 8) | (info->boundary_v & 0xff))); + dwe_write_reg(dev, SCALE_FACTOR, info->scale_factor); + dwe_write_reg(dev, ROI_START, + ((info->roi_x & 0x1fff) | + ((info->roi_y & 0x1fff) << 16))); + return 0; +} + +int dwe_enable_bus(struct dw200_subdev *dev, bool enable) +{ + u32 reg = dwe_read_reg(dev, BUS_CTRL); + + pr_info("enter %s\n", __func__); + + if (enable) { + reg |= DEWRAP_BUS_CTRL_ENABLE_MASK; + reg |= DEWRAP_BUS_CTRL_WR_ID_ENABLE_MASK; + reg |= DEWRAP_BUS_CTRL_RD_ID_ENABLE_MASK; + reg &= ~(0xff << DEWRAP_BUS_CTRL_RD_ID_SHIFT); + reg &= ~(0xff << DEWRAP_BUS_CTRL_WR_ID_SHIFT); + reg |= (0x0 << DEWRAP_BUS_CTRL_RD_ID_SHIFT); //set read id as 1 + reg |= (0x0 << DEWRAP_BUS_CTRL_WR_ID_SHIFT); //set write id as 2 + dwe_write_reg(dev, BUS_CTRL, reg); + } else { + reg &= ~DEWRAP_BUS_CTRL_ENABLE_MASK; + reg &= ~DEWRAP_BUS_CTRL_WR_ID_ENABLE_MASK; + reg &= ~DEWRAP_BUS_CTRL_RD_ID_ENABLE_MASK; + reg &= ~(0xff << DEWRAP_BUS_CTRL_RD_ID_SHIFT); + reg &= ~(0xff << DEWRAP_BUS_CTRL_WR_ID_SHIFT); + dwe_write_reg(dev, BUS_CTRL, reg); + } + return 0; +} + +int dwe_disable_irq(struct dw200_subdev *dev) +{ + pr_info("enter %s\n", __func__); + dwe_write_reg(dev, INTERRUPT_STATUS, INT_RESET_MASK|INT_CLR_MASK); + return 0; +} + +int dwe_clear_irq(struct dw200_subdev *dev, u32 mis) +{ + u32 interrupt_status; + + pr_info("enter %s\n", __func__); + interrupt_status = dwe_read_reg(dev, INTERRUPT_STATUS); + + dwe_write_reg(dev, INTERRUPT_STATUS, mis|interrupt_status);// INT_CLR_MASK); + // dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl | 2); + // dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl); + return 0; +} +int dwe_clear_irq_1(struct dw200_subdev *dev) +{ + u32 reg_dewarp_ctrl; + + pr_info("enter %s\n", __func__); + reg_dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL); + dwe_write_reg(dev, INTERRUPT_STATUS, INT_CLR_MASK); + dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl | 2); + dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl); + return 0; +} +int dwe_read_irq(struct dw200_subdev *dev, u32 * ret) +{ + u32 irq = 0; + + irq = dwe_read_reg(dev, INTERRUPT_STATUS); + *ret = irq; + + return 0; +} + +int dwe_dequeue_irq(struct dw200_subdev *dev, u32 * ret) +{ + vivdw200_mis_t data; + + if (dev == NULL || ret == NULL) { + pr_info("wrong input parameter.\n"); + return -1; + } + if(0 ==vivdw200_read_circle_queue(&data, &dev->dwe_circle_list)){ + *ret = data.val; + } else { + pr_err("failed to dequeue dwe mis.\n"); + *ret = 0; + } + return 0; +} + +int dwe_start_dma_read(struct dw200_subdev *dev, u64 addr) +{ + struct dwe_hw_info *info = &dev->dwe_info; +#ifdef DWE_REG_RESET + u32 regStart = 1 << 4; + u32 reg; +#endif + u32 reg_dst_y_base = (u32) addr; + u32 reg_y_rbuff_size = ALIGN_UP(info->src_stride * info->src_h, 16); + u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size; + + pr_info("enter %s\n", __func__); + + dwe_write_reg(dev, SRC_IMG_Y_BASE, (reg_dst_y_base) >> 4); + dwe_write_reg(dev, SRC_IMG_UV_BASE, (reg_dst_uv_base) >> 4); + +#ifdef DWE_REG_RESET + reg = __raw_readl(dev->dwe_reset); + __raw_writel(reg | regStart, dev->dwe_reset); + __raw_writel(reg & ~regStart, dev->dwe_reset); +#endif + return 0; +} + +int dwe_start(struct dw200_subdev *dev) +{ + pr_info("enter %s\n", __func__); + u32 reg_dewarp_ctrl; + reg_dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL); + dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl | 2); + // dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl); + return 0; +} + +int dwe_set_buffer(struct dw200_subdev *dev, u64 addr) +{ + struct dwe_hw_info *info = &dev->dwe_info; + u32 reg_dst_y_base = (u32) addr; + u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16); + u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size; + + pr_info("enter %s\n", __func__); + dwe_write_reg(dev, DST_IMG_Y_BASE, (reg_dst_y_base) >> 4); + dwe_write_reg(dev, DST_IMG_UV_BASE, (reg_dst_uv_base) >> 4); + + return 0; +} + +int dwe_set_lut(struct dw200_subdev *dev, u64 addr) +{ + dwe_write_reg(dev, MAP_LUT_ADDR, ((u32) addr) >> 4); + return 0; +} + +int dwe_ioc_qcap(struct dw200_subdev *dev, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "viv_dw200"); + return 0; +} + +int vse_reset(struct dw200_subdev *dev) +{ + pr_info("enter %s\n", __func__); + +#ifdef VSE_REG_RESET + __raw_writel(0, dev->vse_reset); + __raw_writel(1, dev->vse_reset); +#endif + vse_write_reg(dev, VSE_REG_CTRL, 0x100); + return 0; +} + +void vse_triger_dma_read(struct dw200_subdev *dev) +{ + u32 reg = vse_read_reg(dev, VSE_REG_CTRL); + REG_SET_BIT(reg, VSE_CONTROL_DMA_FRAME_START_BIT, 1); + vse_write_reg(dev, VSE_REG_CTRL, reg); + vse_write_reg(dev, VSE_REG_DMA_CTRL, 5); +} + +void setMIBaseAddress(struct dw200_subdev *dev, u32 width, u32 height, + u32 format,u32 yuvbit, u64 addr, int channel) +{ + u32 stride = ALIGN_UP(width*(yuvbit+1), 16); + u32 crSize = 0; + u32 yBaseAddr = addr; + u32 regAddress = VSE_MI_BASE(channel); + u32 crBaseAddr = 0; + u32 ysize = stride * height; + u32 cbSize = ysize; + u32 cbBaseAddr = yBaseAddr + ysize; + + if (ysize == 0) + return; + + switch (format) { + case MEDIA_PIX_FMT_YUV420SP: + cbSize /= 2; + crSize = 0; + break; + case MEDIA_PIX_FMT_YUV422SP: + break; + case MEDIA_PIX_FMT_YUV444: + case MEDIA_PIX_FMT_RGB888P: + crSize = ysize; + crBaseAddr = cbBaseAddr + cbSize; + break; + case MEDIA_PIX_FMT_RGB888: /* only supoort RGB interleave format. RGB RGB RGB .. */ + ysize *= 3; + cbSize = 0; + cbBaseAddr = 0; + break; + } + + vse_write_reg(dev, regAddress + VSE_REG_MI_Y_BASE_ADDR_INIT, yBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_Y_SIZE_INIT, ysize); + vse_write_reg(dev, regAddress + VSE_REG_MI_CB_BASE_ADDR_INIT, + cbBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_CB_SIZE_INIT, cbSize); + vse_write_reg(dev, regAddress + VSE_REG_MI_CR_BASE_ADDR_INIT, + crBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_CR_SIZE_INIT, crSize); +} + +int vse_start_dma_read(struct dw200_subdev *dev, u64 addr) +{ + u32 writeFormat = 0; + u32 writeString = 0; + u32 reg = 0; + u32 address = VSE_REG_DMA_FORMAT; + u32 width = dev->vse_info.src_w; + u32 height = dev->vse_info.src_h; + u32 format = dev->vse_info.in_format; + u32 yuvbit = dev->vse_info.in_yuvbit; + u32 ysize, cbSize; + u32 yBaseAddr, cbBaseAddr, crBaseAddr; + u32 stride; + u32 img_width_bn = (yuvbit == 1)? (width*2) : width; + switch (format) { + case MEDIA_PIX_FMT_YUV422SP: + writeFormat = 1; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV422I: + writeFormat = 1; + writeString = 1; + break; + case MEDIA_PIX_FMT_YUV420SP: + writeFormat = 0; + writeString = 0; + break; + } + + reg = vse_read_reg(dev, address); + + pr_info("img_width_bn 0x%08x\n", img_width_bn ); + REG_SET_MASK(reg, VSE_RD_IMG_HSIZE_BN, (img_width_bn & 0x3FFF)); + REG_SET_MASK(reg, VSE_MI_FORMAT_WORD_ALIGNED, yuvbit); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_FMT_ALIGNED, yuvbit); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_STR, writeString); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_FMT, writeFormat); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_10BIT, yuvbit); + pr_info("VSE_REG_DMA_FORMAT reg 0x%08x\n", reg); + vse_write_reg(dev, address, reg); + stride = ALIGN_UP(width*(yuvbit+1), 16); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_WIDTH, width); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_HEIGHT, height); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_STRIDE, stride); + ysize = stride * height; + cbSize = ysize; + yBaseAddr = addr; + cbBaseAddr = yBaseAddr + ysize; + crBaseAddr = 0; + + if (format == MEDIA_PIX_FMT_YUV420SP) { + cbSize /= 2; + } else if (format == MEDIA_PIX_FMT_YUV422I) { + cbSize /= 2; + crBaseAddr = cbBaseAddr + cbSize; + } + vse_write_reg(dev, VSE_REG_Y_PIC_START_ADDR, yBaseAddr); + vse_write_reg(dev, VSE_REG_CB_PIC_START_ADDR, cbBaseAddr); + vse_write_reg(dev, VSE_REG_CR_PIC_START_ADDR, crBaseAddr); + vse_triger_dma_read(dev); + return 0; +} + +void setFormatConvPack(struct dw200_subdev *dev, u32 enable, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_ENABLE_PACK, enable); + vse_write_reg(dev, address, reg); +} + +void setFormatConvFull(struct dw200_subdev *dev, u32 y_full, u32 cbcr_full, + u32 noco422, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_Y_FULL, y_full); + REG_SET_MASK(reg, VSE_FORMAT_CONV_CBCR_FULL, cbcr_full); + REG_SET_MASK(reg, VSE_FORMAT_CONV_CONFIG_422NOCO, 0); + vse_write_reg(dev, address, reg); +} + +static u32 format_conv_map[] = { 2, 2, 1, 3, 6, 6 }; + +void setFormatConvFormat(struct dw200_subdev *dev, u32 inputFormat, + u32 outputFormat,u32 yuvbit, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + } else if (inputFormat == MEDIA_PIX_FMT_YUV422SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + inputFormat = MEDIA_PIX_FMT_YUV420SP; + } else if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat != MEDIA_PIX_FMT_YUV420SP) { + inputFormat = MEDIA_PIX_FMT_YUV422SP; + } + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_OUTPUT_FORMAT, + format_conv_map[outputFormat]); + REG_SET_MASK(reg, VSE_FORMAT_CONV_INPUT_FORMAT, + format_conv_map[inputFormat]); + REG_SET_MASK(reg, VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE, + yuvbit); + vse_write_reg(dev, address, reg); +} + +void setInputSize(struct dw200_subdev *dev, u32 width, u32 height) +{ + u32 reg = ((height & 0x1FFF) << 16) | (width & 0x1FFF); + + vse_write_reg(dev, VSE_REG_IN_SIZE, reg); +} + +void setCropSize(struct dw200_subdev *dev, u32 left, u32 right, u32 top, + u32 bottom, int channel) +{ + u32 hreg = ((right & 0x1FFF) << 16) | (left & 0x1FFF); + u32 vreg = ((bottom & 0x1FFF) << 16) | (top & 0x1FFF); + + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_CROP_XDIR, hreg); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_CROP_YDIR, vreg); +} + +void updateResizeControl(struct dw200_subdev *dev, u32 reg, int channel) +{ + u32 address = VSE_RSZBASE(channel); + + vse_write_reg(dev, address, reg); +} + +void resizeControlAutoUpdate(struct dw200_subdev *dev, u32 autoUpdate, + int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_AUTO_UPDATE_BIT, autoUpdate); + vse_write_reg(dev, address, reg); +} + +void resizeControlConfigUpdate(struct dw200_subdev *dev, u32 configUpdate, + int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT, configUpdate); + vse_write_reg(dev, address, reg); +} + +void resizeControlEnableCrop(struct dw200_subdev *dev, u32 enable, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_CROP_ENABLE_BIT, enable); + vse_write_reg(dev, address, reg); +} + +void updateVseControl(struct dw200_subdev *dev, u32 inputChannel, + u32 inputFormat, u32 enbalePath0, u32 enbalePath1, + u32 enbalePath2, u32 autoUpdate, u32 configUpdate) +{ + u32 reg = 0; + + REG_SET_BIT(reg, VSE_CONTROL_AUTO_UPDATE_BIT, autoUpdate); + REG_SET_BIT(reg, VSE_CONTROL_CONFIG_UPDATE_BIT, configUpdate); + REG_SET_BIT(reg, VSE_CONTROL_PATH0_ENABLE_BIT, enbalePath0); + REG_SET_BIT(reg, VSE_CONTROL_PATH1_ENABLE_BIT, enbalePath1); + REG_SET_BIT(reg, VSE_CONTROL_PATH2_ENABLE_BIT, enbalePath2); + + REG_SET_MASK(reg, VSE_CONTROL_INPUT_SELECT, inputChannel); + REG_SET_MASK(reg, VSE_CONTROL_INPUT_FORMAT, inputFormat); + vse_write_reg(dev, VSE_REG_CTRL, reg); + + /* BUS ID and BUS CONFIG, hardcode here, user need adjust it on their hardware. */ + vse_write_reg(dev, 0xa24, 0x01000100); + vse_write_reg(dev, 0xa20, 0x001000fa); + vse_write_reg(dev, 0xa28, 0x924c5214); + vse_write_reg(dev, 0xa30, 0x100000fa); + vse_write_reg(dev, 0xa34, 0x01000100); + vse_write_reg(dev, 0xa38, 0x924c5214); +} + +void enableMIControl(struct dw200_subdev *dev, u32 enable, int channel) +{ + u32 reg = vse_read_reg(dev, VSE_REG_MI_CTRL); + + REG_SET_BIT(reg, channel, enable); + REG_SET_BIT(reg, VSE_MI_CONTROL_RDMA_ENABLE_BIT, 1); + vse_write_reg(dev, VSE_REG_MI_CTRL, reg); +} + +void setMIBufferInfo(struct dw200_subdev *dev, u32 width, u32 height, + u32 format, u32 is10Bit, u32 aligned, int channel) +{ + u32 writeFormat = 0; + u32 writeString = 0; + u32 reg = 0; + u32 address; + + u32 stride = ALIGN_UP(width*(is10Bit+1), 16); + u32 size = stride * height; + + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_LENGTH, stride); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_WIDTH, + width); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_HEIGHT, + height); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_SIZE, size); + + switch (format) { + case MEDIA_PIX_FMT_YUV422SP: + writeFormat = 1; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV422I: + writeFormat = 1; + writeString = 1; + break; + case MEDIA_PIX_FMT_YUV420SP: + writeFormat = 0; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV444: + writeFormat = 2; + writeString = 2; + break; + case MEDIA_PIX_FMT_RGB888: + writeFormat = 2; + writeString = 1; + break; + case MEDIA_PIX_FMT_RGB888P: + writeFormat = 2; + writeString = 2; + break; + } + + address = VSE_MI_BASE(channel) + VSE_REG_MI_FMT; + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_MI_FORMAT_WORD_ALIGNED, is10Bit); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_FMT_ALIGNED, is10Bit); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_STR, writeString); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_FMT, writeFormat); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_10BIT, is10Bit); + vse_write_reg(dev, address, reg); +} + +void setMIControlConfig(struct dw200_subdev *dev, u32 enableOffset, + u32 enableUpdateBaseAddress, u32 configUpdate, u32 skip, + u32 autoUpdate, u32 enablePingpong, int channel) +{ + u32 reg = 0; + + REG_SET_BIT(reg, VSE_MI_PATH_INIT_OFFSET_EN_BIT, enableOffset); + REG_SET_BIT(reg, VSE_MI_PATH_INIT_BASE_EN_BIT, enableUpdateBaseAddress); + REG_SET_BIT(reg, VSE_MI_PATH_CONFIG_UPDATE_BIT, configUpdate); + REG_SET_BIT(reg, VSE_MI_PATH_ENABLE_SKIP_BIT, skip); + REG_SET_BIT(reg, VSE_MI_PATH_AUTO_UPDATE_BIT, autoUpdate); + REG_SET_BIT(reg, VSE_MI_PATH_ENABLE_PINGPONG_BIT, enablePingpong); + vse_write_reg(dev, VSE_MI_BASE(channel), reg); +} + +u32 vse_get_scale_factor(int src, int dst) +{ + if (dst >= src) { + return ((65536 * (src - 1)) / (dst - 1)); + } else if (dst < src) { + return ((65536 * (dst - 1)) / (src - 1)) + 1; + } + return 0; +} + +void setScaleFactor(struct dw200_subdev *dev, u32 src_w, u32 src_h, u32 dst_w, + u32 dst_h, u32 inputFormat, u32 outputFormat, int channel) +{ + bool hyup, vyup, hcup, vcup; + u32 scale_factor = vse_get_scale_factor(src_w, dst_w); + u32 address = VSE_RSZBASE(channel); + u32 reg = vse_read_reg(dev, address); + + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HY, + scale_factor); + scale_factor = vse_get_scale_factor(src_h, dst_h); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_VY, + scale_factor); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VY_ENABLE_BIT, + ((src_h != dst_h) & 0x01)); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HY_ENABLE_BIT, + ((src_w != dst_w) & 0x01)); + hyup = src_w < dst_w; + vyup = src_h < dst_h; + + /* Format conv module doesn't support convert other formats to YUV420SP. + doesn't support convert 420SP to other formats too. + so scale down/up cbcr here. + */ + src_w /= 2; + dst_w /= 2; + if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + src_h /= 2; + dst_h /= 2; + } else if (inputFormat == MEDIA_PIX_FMT_YUV422SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + /* scale 422 to 420 */ + dst_h /= 2; + } else if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat != MEDIA_PIX_FMT_YUV420SP) { + /* scale 420 to 422 + cbcr width*2, use input buffer as 422SP */ + src_h /= 2; + } + + hcup = src_w < dst_w; + vcup = src_h < dst_h; + scale_factor = vse_get_scale_factor(src_w, dst_w); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HCB, + scale_factor); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HCR, + scale_factor); + scale_factor = vse_get_scale_factor(src_h, dst_h); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_VC, + scale_factor); + + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VCUP_BIT, vcup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VYUP_BIT, vyup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HCUP_BIT, hcup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HYUP_BIT, hyup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VC_ENABLE_BIT, + (src_h != dst_h)); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HC_ENABLE_BIT, + (src_w != dst_w)); + vse_write_reg(dev, address, reg); +} + +int vse_read_irq(struct dw200_subdev *dev, u32 * ret) +{ + // pr_info("enter %s\n", __func__); + *ret = vse_read_reg(dev, VSE_REG_MI_MSI); + return 0; +} + +int vse_dequeue_irq(struct dw200_subdev *dev, u32 * ret) +{ + vivdw200_mis_t data; + + if (dev == NULL || ret == NULL) { + pr_info("wrong input parameter.\n"); + return -1; + } + if(0 == vivdw200_read_circle_queue(&data, &dev->vse_circle_list)) { + *ret = data.val; + } else { + pr_err("failed to dequeue vse mis.\n"); + *ret = 0; + } + return 0; +} + +int vse_clear_irq(struct dw200_subdev *dev, u32 mis) +{ + pr_info("enter %s\n", __func__); + vse_write_reg(dev, VSE_REG_MI_ICR, mis); + return 0; +} + +int vse_mask_irq(struct dw200_subdev *dev, u32 mask) +{ + pr_info("enter %s 0x%08x\n", __func__, mask); + vse_write_reg(dev, VSE_REG_MI_IMSC, mask); + return 0; +} + +int vse_ioc_qcap(struct dw200_subdev *dev, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "viv_vse"); + return 0; +} + +int vse_update_buffers(struct dw200_subdev *dev, u64 * addr) +{ + struct vse_params *param = &dev->vse_info; + struct vse_mi_settings *mi = param->mi_settings; + int i = 0; + + pr_info("enter %s\n", __func__); + for (; i < 3; i++) { + if (addr[i] != 0) { + setMIBaseAddress(dev, mi[i].width, mi[i].height, + mi[i].out_format,mi[i].yuvbit, addr[i], i); + } + } + return 0; +} + +int vse_update_mi_info(struct dw200_subdev *dev) +{ + struct vse_params *param = &dev->vse_info; + struct vse_mi_settings *mi = param->mi_settings; + int i = 0; + + pr_info("enter %s\n", __func__); + + for (; i < 3; i++) { + if (!mi[i].enable) + continue; + setMIBufferInfo(dev, mi[i].width, mi[i].height, + mi[i].out_format, mi[i].yuvbit, true, i); + enableMIControl(dev, mi[i].enable, i); + setMIControlConfig(dev, true, true, true, false, true, false, + i); + } + return 0; +} + +int vse_s_params(struct dw200_subdev *dev) +{ + struct vse_params *param = &dev->vse_info; + int i = 0; + int input_select = 0; + int crop_w, crop_h, scale_w, scale_h; + struct vse_crop_size *cropSize; + struct vse_size *outputSize; + + pr_info("enter %s\n", __func__); + setInputSize(dev, param->src_w, param->src_h); + + for (; i < 3; i++) { + if (!param->resize_enable[i]) + continue; + cropSize = ¶m->crop_size[i]; + outputSize = ¶m->out_size[i]; + crop_w = cropSize->right - cropSize->left + 1; + crop_h = cropSize->bottom - cropSize->top + 1; + scale_w = param->src_w; + scale_h = param->src_h; + if (crop_w > 1 && crop_h > 1) { + resizeControlEnableCrop(dev, 1, i); + setCropSize(dev, cropSize->left, cropSize->right, + cropSize->top, cropSize->bottom, i); + scale_w = crop_w; + scale_h = crop_h; + } else { + resizeControlEnableCrop(dev, 0, i); + } + + /* ONLY SUPPORT Semiplanar NOW, all enable pack */ + setFormatConvPack(dev, true, i); + setFormatConvFull(dev, true, true, false, i); + setFormatConvFormat(dev, param->in_format, + param->format_conv[i].out_format,param->mi_settings[i].yuvbit, i); + + setScaleFactor(dev, scale_w, scale_h, outputSize->width, + outputSize->height, param->in_format, + param->format_conv[i].out_format, i); + resizeControlAutoUpdate(dev, 1, i); + resizeControlConfigUpdate(dev, 1, i); + } + +#ifndef HAL_CMODEL + input_select = param->input_select; +#endif + updateVseControl(dev, input_select, param->in_format, + param->resize_enable[0], + param->resize_enable[1], + param->resize_enable[2], true, true); + return 0; +} + +long dw200_priv_ioctl(struct dw200_subdev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + u64 addr; + switch (cmd) { + case DWEIOC_RESET: + ret = dwe_reset(dev); + break; + case DWEIOC_S_PARAMS: + viv_check_retval(copy_from_user + (&dev->dwe_info, args, sizeof(dev->dwe_info))); + ret = dwe_s_params(dev); + break; + case DWEIOC_ENABLE_BUS: + ret = dwe_enable_bus(dev, 1); + break; + case DWEIOC_DISABLE_BUS: + ret = dwe_enable_bus(dev, 0); + break; + case DWEIOC_DISABLE_IRQ: + ret = dwe_disable_irq(dev); + break; + case DWEIOC_CLEAR_IRQ: + ret = dwe_clear_irq_1(dev); + break; + case DWEIOC_READ_IRQ:{ + u32 irq = 0; +#ifdef HAL_CMODEL + dwe_read_irq((struct dw200_subdev *)dev, &irq); +#else + ret = dwe_dequeue_irq(dev, &irq); +#endif + + viv_check_retval(copy_to_user(args, &irq, sizeof(irq))); + break; + } + case DWEIOC_START_DMA_READ: + viv_check_retval(copy_from_user(&addr, args, sizeof(addr))); + ret = dwe_start_dma_read(dev, addr); + break; + case DWEIOC_SET_BUFFER: + viv_check_retval(copy_from_user(&addr, args, sizeof(addr))); + ret = dwe_set_buffer(dev, addr); + break; + case DWEIOC_SET_LUT: + viv_check_retval(copy_from_user(&addr, args, sizeof(addr))); + ret = dwe_set_lut(dev, addr); + break; + case DWEIOC_START: + ret = dwe_start(dev); + break; +#ifdef __KERNEL__ + case VIDIOC_QUERYCAP: + ret = dwe_ioc_qcap(dev, args); + break; +#endif + case VSEIOC_RESET: + ret = vse_reset(dev); + break; + case VSEIOC_S_PARAMS: + viv_check_retval(copy_from_user + (&dev->vse_info, args, sizeof(dev->vse_info))); + ret = vse_s_params(dev); + break; + case VSEIOC_CLEAR_IRQ: + //ret = vse_clear_irq(dev); + vse_write_reg(dev, VSE_REG_MI_MSI, 0); + break; + case VSEIOC_READ_IRQ:{ + u32 irq = 0; +#ifdef HAL_CMODEL + vse_read_irq((struct dw200_subdev *)dev, &irq); +#else + ret = vse_dequeue_irq(dev, &irq); +#endif + viv_check_retval(copy_to_user(args, &irq, sizeof(irq))); + break; + } + case VSEIOC_START_DMA_READ:{ + u64 addr; + viv_check_retval(copy_from_user + (&addr, args, sizeof(addr))); + ret = vse_start_dma_read(dev, addr); + break; + } + case VSEIOC_U_MI_INFO: + ret = vse_update_mi_info(dev); + break; + case VSEIOC_U_BUFFER:{ + u64 addrs[3]; + viv_check_retval(copy_from_user + (addrs, args, sizeof(addrs))); + vse_update_buffers(dev, addrs); + break; + } + case VSEIOC_MASK_IRQ:{ + u32 mask; + viv_check_retval(copy_from_user + (&mask, args, sizeof(mask))); + vse_mask_irq(dev, mask); + break; + } + default: + pr_err("unsupported dwe command %d", cmd); + break; + } + + return ret; +} diff --git a/vvcam_ry/dw200/dw200_ioctl.h b/vvcam_ry/dw200/dw200_ioctl.h new file mode 100755 index 0000000..87e20b0 --- /dev/null +++ b/vvcam_ry/dw200/dw200_ioctl.h @@ -0,0 +1,107 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_IOC_H_ +#define _DWE_IOC_H_ +#include "dw200_subdev.h" +#include "dwe_regs.h" +#include "vse_regs.h" + +enum { + DWEIOC_RESET = 0x100, + DWEIOC_S_PARAMS, + DWEIOC_ENABLE_BUS, + DWEIOC_DISABLE_BUS, + DWEIOC_DISABLE_IRQ, + DWEIOC_CLEAR_IRQ, + DWEIOC_READ_IRQ, + DWEIOC_START_DMA_READ, + DWEIOC_SET_BUFFER, + DWEIOC_SET_LUT, + DWEIOC_START, + // vse + VSEIOC_RESET, + VSEIOC_S_PARAMS, + VSEIOC_U_BUFFER, + VSEIOC_U_MI_INFO, + VSEIOC_MASK_IRQ, + VSEIOC_READ_IRQ, + VSEIOC_CLEAR_IRQ, + VSEIOC_START_DMA_READ, +}; + +long dw200_priv_ioctl(struct dw200_subdev *dev, unsigned int cmd, void *args); + +int dwe_reset(struct dw200_subdev *dev); +int dwe_s_params(struct dw200_subdev *dev); +int dwe_enable_bus(struct dw200_subdev *dev, bool enable); +int dwe_disable_irq(struct dw200_subdev *dev); +int dwe_clear_irq(struct dw200_subdev *dev, u32 mis); +int dwe_clear_irq_1(struct dw200_subdev *dev); + +int dwe_read_irq(struct dw200_subdev *dev, u32 *ret); +int dwe_start_dma_read(struct dw200_subdev *dev, u64 addr); +int dwe_set_buffer(struct dw200_subdev *dev, u64 addr); +int dwe_set_lut(struct dw200_subdev *dev, u64 addr); + +int vse_reset(struct dw200_subdev *dev); +int vse_s_params(struct dw200_subdev *dev); +int vse_update_mi_info(struct dw200_subdev *dev); +int vse_mask_irq(struct dw200_subdev *dev, u32 mask); +int vse_clear_irq(struct dw200_subdev *dev, u32 mis); +int vse_read_irq(struct dw200_subdev *dev, u32 *ret); +/* dma input pa */ +int vse_start_dma_read(struct dw200_subdev *dev, u64 addr); +/* mi output pa */ +int vse_update_buffers(struct dw200_subdev *dev, u64 *addr); + +#endif // _DWE_IOC_H_ diff --git a/vvcam_ry/dw200/dw200_subdev.h b/vvcam_ry/dw200/dw200_subdev.h new file mode 100755 index 0000000..0e10245 --- /dev/null +++ b/vvcam_ry/dw200/dw200_subdev.h @@ -0,0 +1,153 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DW200_DEV_H +#define _DW200_DEV_H + + +#include +#include "vivdw200_irq_queue.h" + +#ifndef __KERNEL__ +#include +#include +#define copy_from_user(a, b, c) dw200_copy_data(a, b, c) +#define copy_to_user(a, b, c) dw200_copy_data(a, b, c) + + +typedef void(*pReadBar) (uint32_t bar, uint32_t *data); +typedef void(*pWriteBar) (uint32_t bar, uint32_t data); + +extern void dwe_set_func(pReadBar read_func, pWriteBar write_func); +//extern void dw200_set_func(cmDW200* pDW200,pDw200ReadBar read_func, pDw200WriteBar write_func); + + +typedef bool(*pVseReadBar) (uint32_t bar, uint32_t * data); +typedef bool(*pVseWriteBar) (uint32_t bar, uint32_t data); + +extern void vse_set_func(pVseReadBar read_func, pVseWriteBar write_func); +extern long dw200_copy_data(void *dst, void *src, int size); +#endif + + +struct dwe_hw_info { + u32 split_line; + u32 scale_factor; + u32 in_format; + u32 out_format; + u32 in_yuvbit; + u32 out_yuvbit; + u32 hand_shake; + u32 roi_x, roi_y; + u32 boundary_y, boundary_u, boundary_v; + u32 map_w, map_h; + u32 src_auto_shadow, dst_auto_shadow; + u32 src_w, src_stride, src_h; + u32 dst_w, dst_stride, dst_h, dst_size_uv; + u32 split_h, split_v1, split_v2; +}; + +struct vse_crop_size { + u32 left; + u32 right; + u32 top; + u32 bottom; +}; + +struct vse_size { + u32 width; + u32 height; +}; + +struct vse_format_conv_settings { + u32 in_format; + u32 out_format; +}; + +struct vse_mi_settings { + bool enable; + u32 out_format; + u32 width; + u32 height; + u32 yuvbit; +}; + +struct vse_params { + u32 src_w; + u32 src_h; + u32 in_format; + u32 in_yuvbit; + u32 input_select; + struct vse_crop_size crop_size[3]; + struct vse_size out_size[3]; + struct vse_format_conv_settings format_conv[3]; + bool resize_enable[3]; + struct vse_mi_settings mi_settings[3]; +}; + +struct dw200_subdev { + struct dwe_hw_info dwe_info; + struct vse_params vse_info; + void __iomem *dwe_base; + void __iomem *dwe_reset; + void __iomem *vse_base; + void __iomem *vse_reset; + vivdw200_mis_list_t dwe_circle_list; + vivdw200_mis_list_t vse_circle_list; +}; + +void dwe_write_reg(struct dw200_subdev *dev, u32 offset, u32 val); +u32 dwe_read_reg(struct dw200_subdev *dev, u32 offset); +void vse_write_reg(struct dw200_subdev *dev, u32 offset, u32 val); +u32 vse_read_reg(struct dw200_subdev *dev, u32 offset); + +#endif // _DW200_DEV_H diff --git a/vvcam_ry/dw200/dwe_regs.h b/vvcam_ry/dw200/dwe_regs.h new file mode 100755 index 0000000..aed4da2 --- /dev/null +++ b/vvcam_ry/dw200/dwe_regs.h @@ -0,0 +1,116 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_REGS_H_ +#define _DWE_REGS_H_ + +//#define REGISTER_NUM 100 +#define DEWARP_REGISTER_BASE_ADDR 0x00000C00 +#define DEWARP_CTRL 0x00000004 +#define SWAP_CONTROL 0x00000058 +#define VERTICAL_SPLIT_LINE 0x0000005C +#define HORIZON_SPLIT_LINE 0x00000060 +#define SCALE_FACTOR 0x00000064 +#define ROI_START 0x00000068 +#define BOUNDRY_PIXEL 0x0000006C +#define INTERRUPT_STATUS 0x00000070 + +#define INT_FRAME_DONE (1 << 0) +#define INT_ERR_STATUS_MASK 0x000000FE +#define INT_ERR_STATUS_SHIFT 1 +#define INT_MSK_STATUS_MASK 0x0000FF00 +#define INT_MSK_STATUS_SHIFT 8 +#define INT_FRAME_BUSY 0x00010000 +#ifdef HAL_CMODEL +#define INT_CLR_MASK 0x00007F00 +#else +#define INT_CLR_MASK 0x00000100 +#endif +#define INT_RESET_MASK 0x01000000 +#define BUS_CTRL 0x00000074 +#define DEWRAP_BUS_CTRL_ENABLE_MASK (1 << 31) +#define DEWRAP_BUS_CTRL_RD_ID_ENABLE_MASK (1 << 30) +#define DEWRAP_BUS_CTRL_WR_ID_ENABLE_MASK (1 << 29) +#define DEWRAP_BUS_CTRL_RD_ID_SHIFT (8) +#define DEWRAP_BUS_CTRL_WR_ID_SHIFT (16) + + + +#define BUS_CTRL1 0x00000078 +#define BUS_TIME_OUT_CYCLE 0x0000007C +#define MAP_LUT_ADDR 0x00000008 +#define MAP_LUT_SIZE 0x0000000C +#define SRC_IMG_Y_BASE 0x00000010 +#define SRC_IMG_UV_BASE 0x00000014 +#define SRC_IMG_SIZE 0x00000018 +#define SRC_IMG_STRIDE 0x0000001C +#define MAP_LUT_ADDR2 0x00000020 +#define MAP_LUT_SIZE2 0x00000024 +#define SRC_IMG_Y_BASE2 0x00000028 +#define SRC_IMG_UV_BASE2 0x0000002C +#define SRC_IMG_SIZE2 0x00000030 +#define SRC_IMG_STRIDE2 0x00000034 +#define DST_IMG_Y_BASE 0x00000038 +#define DST_IMG_UV_BASE 0x0000003C +#define DST_IMG_SIZE 0x00000040 +#define DST_IMG_STRIDE 0x00000044 +#define DST_IMG_Y_BASE2 0x00000048 +#define DST_IMG_UV_BASE2 0x0000004C +#define DST_IMG_SIZE2 0x00000050 +#define DST_IMG_STRIDE2 0x00000054 +#define DST_IMG_Y_SIZE1 0x00000080 +#define DST_IMG_UV_SIZE1 0x00000084 +#define DST_IMG_Y_SIZE2 0x00000088 +#define DST_IMG_UV_SIZE2 0x0000008C +#define DST_IMG_WIDTH_BN 0x0000009C + +#endif /* _DWE_REGS_H_ */ diff --git a/vvcam_ry/dw200/vivdw200_irq_queue.c b/vvcam_ry/dw200/vivdw200_irq_queue.c new file mode 100755 index 0000000..0206355 --- /dev/null +++ b/vvcam_ry/dw200/vivdw200_irq_queue.c @@ -0,0 +1,185 @@ + +#ifdef __KERNEL__ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#else +#include +#include +#include +#endif +#include "vivdw200_irq_queue.h" + + //enqueue +int vivdw200_enqueue(vivdw200_mis_t *data,vivdw200_mis_t* head) + { +#ifdef __KERNEL__ + vivdw200_mis_t* new_node = (vivdw200_mis_t*)kmalloc(sizeof(vivdw200_mis_t), GFP_KERNEL); //create new node + + + if (data == NULL || head == NULL) { + //printk("%s: input wrong parameter\n", __func__); + return -1; + } + new_node->val = data->val; + + printk("%s: new_node %px", __func__, new_node); + INIT_LIST_HEAD(&new_node->list); + list_add_tail(&new_node->list, &head->list); //append to tail + #endif + return 0; + + } + + //dequeue && release memory +int vivdw200_dequeue(vivdw200_mis_t* data, vivdw200_mis_t* head) + { + +#ifdef __KERNEL__ + vivdw200_mis_t* entry; + if (data == NULL || head == NULL) { + //printk("%s: input wrong parameter\n", __func__); + return -1; + } + if (list_empty(&head->list)) { + //printk("%s: There is no node\n", __func__); + return -1; + } + + entry = list_first_entry(&head->list, vivdw200_mis_t, list); + printk("%s: entry %px", __func__, entry); + data->val = entry->val; + + list_del_init(&entry->list); + + kfree(entry); +#endif + return 0; + } + +bool vivdw200_is_queue_empty( vivdw200_mis_t* head) + { +#ifdef __KERNEL__ + return list_empty(&head->list); +#else + return 0; +#endif + } + +int vivdw200_create_circle_queue(vivdw200_mis_list_t* pCList, int number) +{ +#ifdef __KERNEL__ + int i; + vivdw200_mis_t* pMisNode; + if (pCList == NULL || number <= 0) { + printk("%s: create circle queue failed\n", __func__); + return -1; + } + + if (pCList->pHead == NULL) { + + pCList->pHead = (vivdw200_mis_t*)kmalloc(sizeof(vivdw200_mis_t), GFP_KERNEL); + INIT_LIST_HEAD(&pCList->pHead->list); + pCList->pRead = pCList->pHead; + pCList->pWrite = pCList->pHead; + } + printk("%s:pHead %px\n", __func__, pCList->pHead); + for (i = 0; i < number - 1; i++) { + pMisNode = (vivdw200_mis_t*)kmalloc(sizeof(vivdw200_mis_t), GFP_KERNEL); + INIT_LIST_HEAD(&pMisNode->list); + list_add_tail(&pMisNode->list, &pCList->pHead->list); + printk("%s:pMisNode %px\n", __func__, pMisNode); + } + +#endif + return 0; +} + +int vivdw200_destroy_circle_queue(vivdw200_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + vivdw200_mis_t* pMisNode; + if (pCList == NULL) { + printk("%s: destroy circle queue failed. pClist %px\n", __func__, pCList); + return -1; + } + + while(!list_empty(&pCList->pHead->list)) { + pMisNode = list_first_entry(&pCList->pHead->list, vivdw200_mis_t, list); + printk("%s:pMisNode %px\n", __func__, pMisNode); + list_del(&pMisNode->list); + kfree(pMisNode); + pMisNode = NULL; + } + printk("%s:pHead %px\n", __func__, pCList->pHead); + kfree(pCList->pHead); + pCList->pHead = NULL; + pCList->pRead = NULL; + pCList->pWrite = NULL; +#endif + return 0; +} + +int vivdw200_read_circle_queue(vivdw200_mis_t* data, vivdw200_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + //vivdw200_mis_t* pReadEntry; + if (pCList == NULL) { + printk("%s: can not read circle queue\n", __func__); + return -1; + } + + if (pCList->pRead == pCList->pWrite) { + printk("%s: There is no irq mis data\n", __func__); + return -1; + } + data->val = pCList->pRead->val; + + printk("%s: entry %px, msi %08x\n", __func__, pCList->pRead, data->val); + /*Get the next entry that link with read entry list*/ + /*Update read pointer to next entry*/ + pCList->pRead = list_first_entry(&pCList->pRead->list, vivdw200_mis_t, list); + + //pCList->pRead = pReadEntry; + +#endif + return 0; +} + +int vivdw200_write_circle_queue(vivdw200_mis_t* data, vivdw200_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + vivdw200_mis_t* pWriteEntry; + if (pCList == NULL) { + printk("%s: can not read circle queue\n", __func__); + return -1; + } + + pCList->pWrite->val = data->val; + printk("%s: entry %px, msi %08x\n", __func__, pCList->pWrite, data->val); + /*get the next write entry pointer that link with the write entry list*/ + pWriteEntry = list_first_entry(&pCList->pWrite->list, vivdw200_mis_t, list); + + /*Update write pointer to point next entry*/ + pCList->pWrite = pWriteEntry; + +#endif + return 0; +} \ No newline at end of file diff --git a/vvcam_ry/dw200/vivdw200_irq_queue.h b/vvcam_ry/dw200/vivdw200_irq_queue.h new file mode 100755 index 0000000..38567e1 --- /dev/null +++ b/vvcam_ry/dw200/vivdw200_irq_queue.h @@ -0,0 +1,83 @@ + /**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + #ifndef _VIVDW200_QUEUE_H_ + #define _VIVDW200_QUEUE_H_ +#ifdef __KERNEL__ +#include +#endif + +typedef struct vivdw200_mis_s { + unsigned int val; +#ifdef __KERNEL__ + struct list_head list; +#endif +}vivdw200_mis_t; +typedef struct vivdw200_mis_list_s { + + vivdw200_mis_t* pHead; + vivdw200_mis_t* pRead; + vivdw200_mis_t* pWrite; +}vivdw200_mis_list_t; + +int vivdw200_enqueue(vivdw200_mis_t *data,vivdw200_mis_t* head); +int vivdw200_dequeue(vivdw200_mis_t* data, vivdw200_mis_t* head); +bool vivdw200_is_queue_empty( vivdw200_mis_t* head); + +#define QUEUE_NODE_COUNT 15 +int vivdw200_create_circle_queue(vivdw200_mis_list_t* pCList, int number); +int vivdw200_destroy_circle_queue(vivdw200_mis_list_t* pCList); + +int vivdw200_read_circle_queue(vivdw200_mis_t* data, vivdw200_mis_list_t* pCList); +int vivdw200_write_circle_queue(vivdw200_mis_t* data, vivdw200_mis_list_t* pCList); + +#endif \ No newline at end of file diff --git a/vvcam_ry/dw200/vse_regs.h b/vvcam_ry/dw200/vse_regs.h new file mode 100755 index 0000000..77062ef --- /dev/null +++ b/vvcam_ry/dw200/vse_regs.h @@ -0,0 +1,305 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VSE_REGS_H_ +#define _VSE_REGS_H_ + +/* product identification */ +#define VSE_REG_ID 0x00000000 +#define VSE_REG_CTRL 0x00000004 + +#define VSE_CONTROL_ENABLE_RAM_CLK 17 +#define VSE_CONTROL_AUTO_UPDATE_BIT 16 +#define VSE_CONTROL_CONFIG_UPDATE_BIT 15 +#define VSE_CONTROL_DMA_FRAME_START_BIT 14 +#define VSE_CONTROL_INPUT_SELECT_SHIFT 11 +#define VSE_CONTROL_INPUT_SELECT (7 << 11) +#define VSE_CONTROL_INPUT_FORMAT_SHIFT 9 +#define VSE_CONTROL_INPUT_FORMAT (3 << 9) +#define VSE_CONTROL_SOFT_RESET_BIT 8 +#define VSE_CONTROL_PATH2_ENABLE_BIT 2 +#define VSE_CONTROL_PATH1_ENABLE_BIT 1 +#define VSE_CONTROL_PATH0_ENABLE_BIT 0 + +/* input size 28:16 height, 12:0 width */ +#define VSE_REG_IN_SIZE 0x00000008 +#define VSE_REG_CTRL_SHD 0x0000000C +#define VSE_REG_RSZ0_CTL 0x00000400 +#define VSE_REG_RSZ1_CTL 0x00000500 +#define VSE_REG_RSZ2_CTL 0x00000600 +#define VSE_RSZBASE(c) ((c) == 0 ? VSE_REG_RSZ0_CTL : ((c) == 1 ? VSE_REG_RSZ1_CTL : VSE_REG_RSZ2_CTL)) +#define VSE_RSZ_SCALE_HY 0x00000004 +#define VSE_RSZ_SCALE_HCB 0x00000008 +#define VSE_RSZ_SCALE_HCR 0x0000000C +#define VSE_RSZ_SCALE_VY 0x00000010 +#define VSE_RSZ_SCALE_VC 0x00000014 +#define VSE_RSZ_PHASE_HY 0x00000018 +#define VSE_RSZ_PHASE_HC 0x0000001C +#define VSE_RSZ_PHASE_VY 0x00000020 +#define VSE_RSZ_PHASE_VC 0x00000024 +#define VSE_RSZ_SCALE_LUT_ADDR 0x00000028 +#define VSE_RSZ_SCALE_LUT 0x0000002C +#define VSE_RSZ_CTRL_SHD 0x00000030 +#define VSE_RSZ_SCALE_HY_SHD 0x00000034 +#define VSE_RSZ_SCALE_HCB_SHD 0x00000038 +#define VSE_RSZ_SCALE_HCR_SHD 0x0000003C +#define VSE_RSZ_SCALE_VY_SHD 0x00000040 +#define VSE_RSZ_SCALE_VC_SHD 0x00000044 +#define VSE_RSZ_PHASE_HY_SHD 0x00000048 +#define VSE_RSZ_PHASE_HC_SHD 0x0000004C +#define VSE_RSZ_PHASE_VY_SHD 0x00000050 +#define VSE_RSZ_PHASE_VC_SHD 0x00000054 +#define VSE_RSZ_CROP_XDIR 0x00000058 +#define VSE_RSZ_CROP_YDIR 0x0000005C +#define VSE_RSZ_CROP_XDIR_SHD 0x00000060 +#define VSE_RSZ_CROP_YDIR_SHD 0x00000064 +#define VSE_RSZ_FRAME_RATE 0x00000068 +#define VSE_REG_FORMAT_CONV_CTRL 0x0000006C +#define VSE_REG_HBLANK_VALUE 0x000001A0 + +#define VSE_REG_VBLANK_VALUE 0x000001A4 +#define VSE_REG_VSYNC_WIDTH 0x000001A8 +#define VSE_REG_HSYNC_PREAMBLE 0x000001AC +#define VSE_REG_MI_CTRL 0x00000800 +#define VSE_REG_MI_CTRL_SHD 0x00000804 +#define VSE_REG_MI_PATH_0 0x00000810 +#define VSE_REG_MI_PATH_1 0x000008b0 +#define VSE_REG_MI_PATH_2 0x00000950 +#define VSE_MI_BASE(c) ((c) == 0 ? VSE_REG_MI_PATH_0 : ((c) == 1 ? VSE_REG_MI_PATH_1 : VSE_REG_MI_PATH_2)) +#define VSE_REG_MI_FMT 0x00000004 + +#define VSE_REG_MI_Y_BASE_ADDR_INIT 0x00000014 +#define VSE_REG_MI_Y_SIZE_INIT 0x00000018 +#define VSE_REG_MI_Y_OFFSET_COUNT_INIT 0x0000001C +#define VSE_REG_MI_Y_LENGTH 0x00000020 +#define VSE_REG_MI_Y_PIC_WIDTH 0x00000024 +#define VSE_REG_MI_Y_PIC_HEIGHT 0x00000028 +#define VSE_REG_MI_Y_PIC_SIZE 0x0000002C + +#define VSE_REG_MI_CB_BASE_ADDR_INIT 0x00000030 +#define VSE_REG_MI_CB_SIZE_INIT 0x00000034 +#define VSE_REG_MI_CB_OFFSET_COUNT_INIT 0x00000038 +#define VSE_REG_MI_CR_BASE_ADDR_INIT 0x0000003C +#define VSE_REG_MI_CR_SIZE_INIT 0x00000040 +#define VSE_REG_MI_CR_OFFSET_COUNT_INIT 0x00000044 +#define VSE_REG_MI_Y_BASE_ADDR_INIT2 0x00000048 +#define VSE_REG_MI_CB_BASE_ADDR_INIT2 0x0000004C +#define VSE_REG_MI_CR_BASE_ADDR_INIT2 0x00000050 +#define VSE_REG_MI_Y_OFFS_CNT_START 0x00000054 +#define VSE_REG_MI_CB_OFFS_CNT_START 0x00000058 +#define VSE_REG_MI_CR_OFFS_CNT_START 0x0000005C +#define VSE_REG_MI_Y_BASE_ADDR_SHD 0x00000060 +#define VSE_REG_MI_Y_SIZE_SHD 0x00000064 +#define VSE_REG_MI_Y_OFFS_COUNT_SHD 0x00000068 +#define VSE_REG_MI_CB_BASE_ADDR_SHD 0x0000006C +#define VSE_REG_MI_CB_SIZE_SHD 0x00000070 +#define VSE_REG_MI_CB_OFFS_COUNT_SHD 0x00000074 +#define VSE_REG_MI_CR_BASE_ADDR_SHD 0x00000078 +#define VSE_REG_MI_CR_SIZE_SHD 0x0000007C +#define VSE_REG_MI_CR_OFFS_COUNT_SHD 0x00000080 +#define VSE_REG_MI_STATUS_CLR 0x00000084 +#define VSE_REG_MI_CTRL_STATUS 0x00000088 +#define VSE_REG_MI_Y_IRQ_OFFS_INIT 0x0000008C +#define VSE_REG_MI_Y_IRQ_OFFS_SHD 0x00000090 +#define VSE_REG_DMA_CTRL 0x000009E8 +#define VSE_REG_DMA_FORMAT 0x000009EC +#define VSE_REG_DMA_Y_PIC_WIDTH 0x000009F0 +#define VSE_REG_DMA_Y_PIC_HEIGHT 0x000009F4 +#define VSE_REG_DMA_Y_PIC_STRIDE 0x000009F8 +#define VSE_REG_Y_PIC_START_ADDR 0x000009FC +#define VSE_REG_CB_PIC_START_ADDR 0x00000A00 +#define VSE_REG_CR_PIC_START_ADDR 0x00000A04 +#define VSE_REG_Y_START_ADDR_SHD 0x00000A08 +#define VSE_REG_CB_START_ADDR_SHD 0x00000A0C +#define VSE_REG_CR_START_ADDR_SHD 0x00000A10 +#define VSE_REG_DMA_STATUS 0x00000A14 +#define VSE_REG_MI0_BUS_CONFIG 0x00000A20 +#define VSE_REG_MI0_BUS_ID 0x00000A24 +#define VSE_REG_MI0_BUS_TIME_OUT 0x00000A28 +#define VSE_REG_MI0_AXI_STATUS 0x00000A2C + +#define VSE_REG_MI1_BUS_CONFIG 0x00000A30 +#define VSE_REG_MI1_BUS_ID 0x00000A34 +#define VSE_REG_MI1_BUS_TIME_OUT 0x00000A38 +#define VSE_REG_MI1_AXI_STATUS 0x00000A3C + +#define VSE_REG_MI_IMSC 0x00000A40 +#define VSE_REG_MI_IMSC1 0x00000A44 +#define VSE_REG_MI_ISR 0x00000A48 +#define VSE_REG_MI_ISR1 0x00000A4C +#define VSE_REG_MI_MSI 0x00000A50 +#define VSE_REG_MI_MSI1 0x00000A54 +#define VSE_REG_MI_ICR 0x00000A58 +#define VSE_REG_MI_ICR1 0x00000A5C +#define VSE_REG_MI_RIS 0x00000A60 +#define VSE_REG_MI_RIS1 0x00000A64 + +#define VSE_FORMAT_CONV_ENABLE_PACK_SHIFT 10 +#define VSE_FORMAT_CONV_ENABLE_PACK (1 << 10) +#define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD_SHIFT 9 +#define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD (1 << 9) +#define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE_SHIFT 8 +#define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE (1 << 8) +#define VSE_FORMAT_CONV_CONFIG_422NOCO_SHIFT 7 +#define VSE_FORMAT_CONV_CONFIG_422NOCO (1 << 7) +#define VSE_FORMAT_CONV_CBCR_FULL_SHIFT 6 +#define VSE_FORMAT_CONV_CBCR_FULL (1 << 6) +#define VSE_FORMAT_CONV_Y_FULL_SHIFT 5 +#define VSE_FORMAT_CONV_Y_FULL (1 << 5) +#define VSE_FORMAT_CONV_OUTPUT_FORMAT_SHIFT 2 +#define VSE_FORMAT_CONV_OUTPUT_FORMAT (7 << 2) +#define VSE_FORMAT_CONV_INPUT_FORMAT_SHIFT 0 +#define VSE_FORMAT_CONV_INPUT_FORMAT (3) + +/* slice of VSE_REG_RSZ0_CTL */ +#define VSE_RESIZE_CONTROL_AUTO_UPDATE_BIT 10 +#define VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT 9 +#define VSE_RESIZE_CONTROL_CROP_ENABLE_BIT 8 +#define VSE_RESIZE_CONTROL_SCALE_VCUP_BIT 7 +#define VSE_RESIZE_CONTROL_SCALE_VYUP_BIT 6 +#define VSE_RESIZE_CONTROL_SCALE_HCUP_BIT 5 +#define VSE_RESIZE_CONTROL_SCALE_HYUP_BIT 4 +#define VSE_RESIZE_CONTROL_SCALE_VC_ENABLE_BIT 3 +#define VSE_RESIZE_CONTROL_SCALE_VY_ENABLE_BIT 2 +#define VSE_RESIZE_CONTROL_SCALE_HC_ENABLE_BIT 1 +#define VSE_RESIZE_CONTROL_SCALE_HY_ENABLE_BIT 0 + +/* slice of VSE_REG_MI_FMT */ +#define VSE_RD_IMG_HSIZE_BN_SHIFT 16 +#define VSE_RD_IMG_HSIZE_BN (0x3fff<<16) +#define VSE_MI_FORMAT_WA_MSB_EN_SHIFT 10 +#define VSE_MI_FORMAT_WA_MSB_EN (1<<10) +#define VSE_MI_FORMAT_WORD_ALIGNED_SHIFT 9 +#define VSE_MI_FORMAT_WORD_ALIGNED (1<<9) +#define VSE_MI_FORMAT_WR_YUV_NVY_SHIFT 7 +#define VSE_MI_FORMAT_WR_YUV_NVY (3 << 7) +#define VSE_MI_FORMAT_WR_YUV_N21_SHIFT 6 +#define VSE_MI_FORMAT_WR_YUV_N21 (1 << 6) +#define VSE_MI_FORMAT_WR_FMT_ALIGNED_SHIFT 5 +#define VSE_MI_FORMAT_WR_FMT_ALIGNED (1 << 5) +#define VSE_MI_FORMAT_WR_YUV_STR_SHIFT 3 +#define VSE_MI_FORMAT_WR_YUV_STR (3 << 3) +#define VSE_MI_FORMAT_WR_YUV_FMT_SHIFT 1 +#define VSE_MI_FORMAT_WR_YUV_FMT (3 << 1) +#define VSE_MI_FORMAT_WR_YUV_10BIT_SHIFT 0 +#define VSE_MI_FORMAT_WR_YUV_10BIT (1) + +/* slice of VSE_REG_MI_CTRL */ +#define VSE_MI_CONTROL_RDMA_START_BIT 4 +#define VSE_MI_CONTROL_RDMA_ENABLE_BIT 3 +#define VSE_MI_CONTROL_MI2_PATH_ENABLE_BIT 2 +#define VSE_MI_CONTROL_MI1_PATH_ENABLE_BIT 1 +#define VSE_MI_CONTROL_MI0_PATH_ENABLE_BIT 0 + +/* slice of VSE_REG_MI_PATH */ +#define VSE_MI_PATH_INIT_OFFSET_EN_BIT 5 +#define VSE_MI_PATH_INIT_BASE_EN_BIT 4 +#define VSE_MI_PATH_CONFIG_UPDATE_BIT 3 +#define VSE_MI_PATH_ENABLE_SKIP_BIT 2 +#define VSE_MI_PATH_AUTO_UPDATE_BIT 1 +#define VSE_MI_PATH_ENABLE_PINGPONG_BIT 0 + +#define VSE_MI_ISR_STATUS_DMA_YCBCR_READY_BIT 12 +#define VSE_MI_ISR_STATUS_WRAP_MI2_CR_BIT 11 +#define VSE_MI_ISR_STATUS_WRAP_MI2_CB_BIT 10 +#define VSE_MI_ISR_STATUS_WRAP_MI2_Y_BIT 9 +#define VSE_MI_ISR_STATUS_WRAP_MI1_CR_BIT 8 +#define VSE_MI_ISR_STATUS_WRAP_MI1_CB_BIT 7 +#define VSE_MI_ISR_STATUS_WRAP_MI1_Y_BIT 6 +#define VSE_MI_ISR_STATUS_WRAP_MI0_CR_BIT 5 +#define VSE_MI_ISR_STATUS_WRAP_MI0_CB_BIT 4 +#define VSE_MI_ISR_STATUS_WRAP_MI0_Y_BIT 3 +#define VSE_MI_ISR_STATUS_MI2_FRAME_END_BIT 2 +#define VSE_MI_ISR_STATUS_MI1_FRAME_END_BIT 1 +#define VSE_MI_ISR_STATUS_MI0_FRAME_END_BIT 0 + +#define VSE_MI_ISR_ERROR_MI2_BUS_ERROR_BIT 5 +#define VSE_MI_ISR_ERROR_MI2_BUS_TIMEOUT_BIT 4 +#define VSE_MI_ISR_ERROR_MI1_BUS_ERROR_BIT 3 +#define VSE_MI_ISR_ERROR_MI1_BUS_TIMEOUT_BIT 2 +#define VSE_MI_ISR_ERROR_MI0_BUS_ERROR_BIT 1 +#define VSE_MI_ISR_ERROR_MI0_BUS_TIMEOUT_BIT 0 + +#define VSE_MI_BUS_CONFIG_WR_SWAP_V_SHIFT 16 +#define VSE_MI_BUS_CONFIG_WR_SWAP_V (0XF << 16) +#define VSE_MI_BUS_CONFIG_WR_SWAP_U_SHIFT 12 +#define VSE_MI_BUS_CONFIG_WR_SWAP_U (0XF << 12) +#define VSE_MI_BUS_CONFIG_WR_SWAP_Y_SHIFT 8 +#define VSE_MI_BUS_CONFIG_WR_SWAP_Y (0XF << 8) +#define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP_SHIFT 6 +#define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP (0X3 << 6) +#define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP_SHIFT 4 +#define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP (0X3 << 4) +#define VSE_MI_BUS_CONFIG_RD_BURST_LEN_SHIFT 2 +#define VSE_MI_BUS_CONFIG_RD_BURST_LEN (0X3 << 2) +#define VSE_MI_BUS_CONFIG_WR_BURST_LEN_SHIFT 0 +#define VSE_MI_BUS_CONFIG_WR_BURST_LEN (0X3 << 0) + +#ifndef REG_GET_MASK +#define REG_GET_MASK(reg, mask)\ + (((reg) & (mask)) >> (mask##_SHIFT)) + +#define REG_SET_MASK(reg, mask, value)\ + {\ + ((reg) = (((reg) & ~(mask)) | (((value) << (mask##_SHIFT)) & (mask))));\ + } + +#define REG_GET_BIT(reg, shift)\ + (((reg) & 1) >> shift) + +#define REG_SET_BIT(reg, shift, value)\ + {\ + ((reg) = (((reg) & ~(1 << (shift))) | (((value) & 1) << (shift))));\ + } +#endif + +#endif /* _VSE_REGS_H_ */ diff --git a/vvcam_ry/dwe/dwe_dev.h b/vvcam_ry/dwe/dwe_dev.h new file mode 100755 index 0000000..36a7402 --- /dev/null +++ b/vvcam_ry/dwe/dwe_dev.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_DEV_H +#define _DWE_DEV_H + +#include "vvdefs.h" + +#ifndef __KERNEL__ +#define copy_from_user(a, b, c) dwe_copy_data(a, b, c) +#define copy_to_user(a, b, c) dwe_copy_data(a, b, c) + +typedef bool(*pReadBar) (uint32_t bar, uint32_t *data); +typedef bool(*pWriteBar) (uint32_t bar, uint32_t data); + +extern void dwe_set_func(pReadBar read_func, pWriteBar write_func); +extern long dwe_copy_data(void *dst, void *src, int size); +#endif + +#define MAX_DWE_NUM (2) +#define MAX_CFG_NUM (2) + +struct dwe_hw_info { + u32 split_line; + u32 scale_factor; + u32 in_format; + u32 out_format; + u32 hand_shake; + u32 roi_x, roi_y; + u32 boundary_y, boundary_u, boundary_v; + u32 map_w, map_h; + u32 src_auto_shadow, dst_auto_shadow; + u32 src_w, src_stride, src_h; + u32 dst_w, dst_stride, dst_h, dst_size_uv; + u32 split_h, split_v1, split_v2; +}; + +enum BUF_ERR_TYPE { + BUF_ERR_UNDERFLOW = 1, + BUF_ERR_OVERFLOW0 = 1 << 1, + BUF_ERR_OVERFLOW1 = 1 << 2, + BUF_ERR_NO_DIST_MAP0 = 1 << 2, + BUF_ERR_NO_DIST_MAP1 = 1 << 3, + BUF_ERR_WRONGSTATE = 1 << 4, +}; + +struct dwe_ic_dev { + struct dwe_hw_info info[MAX_DWE_NUM][MAX_CFG_NUM]; + int which[MAX_DWE_NUM]; + void __iomem *base; + void __iomem *reset; +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + struct vvbuf_ctx *sink_bctx; + struct vvbuf_ctx *src_bctx[MAX_DWE_NUM]; + dma_addr_t dist_map[MAX_DWE_NUM][MAX_CFG_NUM]; + int *state[MAX_DWE_NUM]; + int index; + struct vb2_dc_buf *src; + struct vb2_dc_buf *dst; + spinlock_t irqlock; + u32 error; + int (*get_index)(struct dwe_ic_dev *dev, struct vb2_dc_buf *buf); +#endif + +}; + +void dwe_write_reg(struct dwe_ic_dev *dev, u32 offset, u32 val); +u32 dwe_read_reg(struct dwe_ic_dev *dev, u32 offset); + +#endif /* _DWE_DEV_H */ diff --git a/vvcam_ry/dwe/dwe_ioctl.c b/vvcam_ry/dwe/dwe_ioctl.c new file mode 100755 index 0000000..e0dcbf5 --- /dev/null +++ b/vvcam_ry/dwe/dwe_ioctl.c @@ -0,0 +1,381 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include "dwe_ioctl.h" +#include "dwe_regs.h" +#ifndef __KERNEL__ +#include +#include +#include +#ifdef USE_V4L2 +#include +#endif +#endif + +#ifndef __KERNEL__ +#ifdef HAL_CMODEL +#define DEWARP_REGISTER_OFFSET 0 +#else +#define DEWARP_REGISTER_OFFSET 0x380000 +#endif + +#define DEWARP_REGISTER_CTL 0x308250 + +pReadBar g_read_func; +pWriteBar g_write_func; + +void dwe_set_func(pReadBar read_func, pWriteBar write_func) +{ + g_read_func = read_func; + g_write_func = write_func; +} + +void dwe_write_reg(struct dwe_ic_dev *dev, u32 offset, u32 val) +{ + g_write_func(DEWARP_REGISTER_OFFSET + offset, val); +} + +u32 dwe_read_reg(struct dwe_ic_dev *dev, u32 offset) +{ + u32 data; + + g_read_func(DEWARP_REGISTER_OFFSET + offset, &data); + return data; +} + +void dwe_write_extreg(u32 offset, u32 val) +{ + g_write_func(DEWARP_REGISTER_CTL + offset, val); +} + +u32 dwe_read_extreg(u32 offset) +{ + u32 data; + + g_read_func(DEWARP_REGISTER_CTL + offset, &data); + return data; +} + +long dwe_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); + return 0; +} +#else +void dwe_write_reg(struct dwe_ic_dev *dev, u32 offset, u32 val) +{ + __raw_writel(val, dev->base + offset); +} + +u32 dwe_read_reg(struct dwe_ic_dev *dev, u32 offset) +{ + return __raw_readl(dev->base + offset); +} +#endif + +int dwe_reset(struct dwe_ic_dev *dev) +{ + pr_debug("enter %s\n", __func__); +#ifdef DWE_REG_RESET + __raw_writel(0, dev->reset); + __raw_writel(1, dev->reset); +#endif + dwe_write_reg(dev, DEWARP_CTRL, 0x0c); + return 0; +} + +int dwe_s_params(struct dwe_ic_dev *dev, struct dwe_hw_info *info) +{ + u32 reg = 0; + u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16); + u32 vUp = (info->split_v1 & ~0x0F) | 0x0C; + u32 vDown = (info->split_v2 & ~0x0F) | 0x0C; + u32 hLine = (info->split_h & ~0x0F) | 0x0C; + + pr_debug("enter %s\n", __func__); + + dwe_write_reg(dev, MAP_LUT_SIZE, + ((info->map_w & 0x7ff) | ((info->map_h & 0x7ff) << 16))); + dwe_write_reg(dev, SRC_IMG_SIZE, + ((info->src_w & 0x1fff) | + ((info->src_h & 0x1fff) << 16))); + dwe_write_reg(dev, SRC_IMG_STRIDE, info->src_stride); + + dwe_write_reg(dev, DST_IMG_SIZE, + ((info->dst_w & 0x1FFF) | + ((info->dst_h & 0x1FFF) << 16))); + dwe_write_reg(dev, DST_IMG_STRIDE, info->dst_stride); + dwe_write_reg(dev, DST_IMG_Y_SIZE1, reg_y_rbuff_size >> 4); + dwe_write_reg(dev, DST_IMG_UV_SIZE1, info->dst_size_uv >> 4); + dwe_write_reg(dev, VERTICAL_SPLIT_LINE, + (vUp & 0x1fff) | ((vDown & 0x1fff) << 16)); + dwe_write_reg(dev, HORIZON_SPLIT_LINE, (hLine & 0x1fff)); + + reg = 0x4C800001; + reg |= ((info->split_line & 0x1) << 11); + reg |= ((info->in_format & 0x3) << 4); + reg |= ((info->out_format & 0x3) << 6); + reg |= + ((info->src_auto_shadow & 0x1) << 8) | + ((info->dst_auto_shadow & 0x1) << 10); + reg |= ((info->hand_shake & 0x1) << 9); + dwe_write_reg(dev, DEWARP_CTRL, reg); + + dwe_write_reg(dev, BOUNDRY_PIXEL, + (((info->boundary_y & 0xff) << 16) | + ((info->boundary_u & 0xff) + << 8) | (info->boundary_v & 0xff))); + dwe_write_reg(dev, SCALE_FACTOR, info->scale_factor); + dwe_write_reg(dev, ROI_START, + ((info->roi_x & 0x1fff) | + ((info->roi_y & 0x1fff) << 16))); + return 0; +} + +int dwe_enable_bus(struct dwe_ic_dev *dev, bool enable) +{ + u32 reg = dwe_read_reg(dev, BUS_CTRL); + + /* pr_debug("enter %s\n", __func__); */ + + if (enable) { + dwe_write_reg(dev, BUS_CTRL, reg | DEWRAP_BUS_CTRL_ENABLE_MASK); + } else { + dwe_write_reg(dev, BUS_CTRL, + reg & ~DEWRAP_BUS_CTRL_ENABLE_MASK); + } + + return 0; +} + +int dwe_disable_irq(struct dwe_ic_dev *dev) +{ + /* pr_debug("enter %s\n", __func__); */ + dwe_write_reg(dev, INTERRUPT_STATUS, INT_CLR_MASK); + return 0; +} + +int dwe_clear_irq(struct dwe_ic_dev *dev) +{ + u32 reg_dewarp_ctrl; + + /* pr_debug("enter %s\n", __func__); */ + reg_dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL); + dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl | 2); + dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl); + dwe_write_reg(dev, INTERRUPT_STATUS, INT_CLR_MASK | INT_MSK_STATUS_MASK); + + return 0; +} + +int dwe_read_irq(struct dwe_ic_dev *dev, u32 *ret) +{ + u32 irq = 0; + + irq = dwe_read_reg(dev, INTERRUPT_STATUS); + *ret = irq; + + return 0; +} + +int dwe_start(struct dwe_ic_dev *dev) +{ +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + dev->src = NULL; + dev->dst = NULL; + dev->error = BUF_ERR_UNDERFLOW; +#endif + return 0; +} + +int dwe_stop(struct dwe_ic_dev *dev) +{ + dwe_enable_bus(dev, 0); + dwe_disable_irq(dev); + return 0; +} + +int dwe_start_dma_read(struct dwe_ic_dev *dev, + struct dwe_hw_info *info, u64 addr) +{ +#ifdef DWE_REG_RESET + u32 regStart = 1 << 4; + u32 reg; +#endif + u32 reg_dst_y_base = (u32)addr; + u32 reg_y_rbuff_size = ALIGN_UP(info->src_stride * info->src_h, 16); + u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size; + + /* pr_debug("enter %s\n", __func__); */ + + dwe_write_reg(dev, SRC_IMG_Y_BASE, (reg_dst_y_base) >> 4); + dwe_write_reg(dev, SRC_IMG_UV_BASE, (reg_dst_uv_base) >> 4); + +#ifdef DWE_REG_RESET + reg = __raw_readl(dev->reset); + __raw_writel(reg | regStart, dev->reset); + __raw_writel(reg & ~regStart, dev->reset); +#endif + + return 0; +} + +int dwe_set_buffer(struct dwe_ic_dev *dev, struct dwe_hw_info *info, u64 addr) +{ + u32 reg_dst_y_base = (u32) addr; + u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16); + u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size; + + /* pr_debug("enter %s\n", __func__); */ + dwe_write_reg(dev, DST_IMG_Y_BASE, (reg_dst_y_base) >> 4); + dwe_write_reg(dev, DST_IMG_UV_BASE, (reg_dst_uv_base) >> 4); + + return 0; +} + +int dwe_set_lut(struct dwe_ic_dev *dev, u64 addr) +{ + dwe_write_reg(dev, MAP_LUT_ADDR, ((u32) addr) >> 4); + return 0; +} + +int dwe_ioc_qcap(struct dwe_ic_dev *dev, void *args) +{ +#ifdef __KERNEL__ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "viv_dewarp100"); +#endif + return 0; +} + +long dwe_priv_ioctl(struct dwe_ic_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + switch (cmd) { + case DWEIOC_RESET: + ret = dwe_reset(dev); + break; + case DWEIOC_S_PARAMS: + viv_check_retval(copy_from_user + (&dev->info[0][0], args, sizeof(dev->info[0][0]))); + ret = dwe_s_params(dev, &dev->info[0][0]); + break; +#ifndef ENABLE_IRQ + case DWEIOC_ENABLE_BUS: + ret = dwe_enable_bus(dev, 1); + break; + case DWEIOC_DISABLE_BUS: + ret = dwe_enable_bus(dev, 0); + break; + case DWEIOC_DISABLE_IRQ: + ret = dwe_disable_irq(dev); + break; + case DWEIOC_CLEAR_IRQ: + ret = dwe_clear_irq(dev); + break; +#endif + case DWEIOC_READ_IRQ: { + u32 irq = 0; +#ifndef ENABLE_IRQ + ret = dwe_read_irq(dev, &irq); +#endif + viv_check_retval(copy_to_user(args, &irq, sizeof(irq))); + break; + } + case DWEIOC_START: + ret = dwe_start(dev); + break; + case DWEIOC_STOP: + ret = dwe_stop(dev); + break; + case DWEIOC_START_DMA_READ: { +#ifndef ENABLE_IRQ + u64 addr; + + viv_check_retval(copy_from_user(&addr, args, sizeof(addr))); + ret = dwe_start_dma_read(dev, &dev->info[0][0], addr); +#endif + break; + } + case DWEIOC_SET_BUFFER: { +#ifndef ENABLE_IRQ + u64 addr; + + viv_check_retval(copy_from_user(&addr, args, sizeof(addr))); + ret = dwe_set_buffer(dev, &dev->info[0][0], addr); +#endif + break; + } + case DWEIOC_SET_LUT: { + struct lut_info info; + + viv_check_retval(copy_from_user(&info, args, sizeof(info))); +#ifndef ENABLE_IRQ + ret = dwe_set_lut(dev, info.addr); +#endif + break; + } +#ifdef __KERNEL__ + case VIDIOC_QUERYCAP: + ret = dwe_ioc_qcap(dev, args); + break; +#endif + default: + pr_err("unsupported dwe command %d", cmd); + break; + } + + return ret; +} diff --git a/vvcam_ry/dwe/dwe_ioctl.h b/vvcam_ry/dwe/dwe_ioctl.h new file mode 100755 index 0000000..77d3707 --- /dev/null +++ b/vvcam_ry/dwe/dwe_ioctl.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_IOC_H_ +#define _DWE_IOC_H_ +#include "dwe_dev.h" + +enum { + DWEIOC_RESET = 0x100, + DWEIOC_S_PARAMS, + DWEIOC_ENABLE_BUS, + DWEIOC_DISABLE_BUS, + DWEIOC_DISABLE_IRQ, + DWEIOC_CLEAR_IRQ, + DWEIOC_READ_IRQ, + DWEIOC_START, + DWEIOC_STOP, + DWEIOC_START_DMA_READ, + DWEIOC_SET_BUFFER, + DWEIOC_SET_LUT, +}; + +struct lut_info { + u32 port; + u64 addr; +}; + +long dwe_priv_ioctl(struct dwe_ic_dev *dev, unsigned int cmd, void *args); + +int dwe_reset(struct dwe_ic_dev *dev); +int dwe_s_params(struct dwe_ic_dev *dev, struct dwe_hw_info *info); +int dwe_enable_bus(struct dwe_ic_dev *dev, bool enable); +int dwe_disable_irq(struct dwe_ic_dev *dev); +int dwe_clear_irq(struct dwe_ic_dev *dev); +int dwe_read_irq(struct dwe_ic_dev *dev, u32 *ret); +int dwe_start_dma_read(struct dwe_ic_dev *dev, + struct dwe_hw_info *info, u64 addr); +int dwe_set_buffer(struct dwe_ic_dev *dev, struct dwe_hw_info *info, u64 addr); +int dwe_set_lut(struct dwe_ic_dev *dev, u64 addr); +#ifdef __KERNEL__ +int dwe_on_buf_update(struct dwe_ic_dev *dev); +irqreturn_t dwe_hw_isr(int irq, void *data); +void dwe_clear_interrupts(struct dwe_ic_dev *dev); +#endif +#endif /* _DWE_IOC_H_ */ diff --git a/vvcam_ry/dwe/dwe_isr.c b/vvcam_ry/dwe/dwe_isr.c new file mode 100755 index 0000000..44f6965 --- /dev/null +++ b/vvcam_ry/dwe/dwe_isr.c @@ -0,0 +1,183 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +# include "dwe_driver.h" +# include "video/vvbuf.h" +#endif +#include "dwe_ioctl.h" +#include "dwe_regs.h" + +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + +static int update_dma_buffer(struct dwe_ic_dev *dev) +{ + int no_dist_map_err, overflow_err; + int which; + u32 dewarp_ctrl; + + dwe_enable_bus(dev, 0); + if (dev->dst) + return -EBUSY; + if (dev->src) { + vvbuf_ready(dev->sink_bctx, dev->src->pad, dev->src); + dev->src = NULL; + } + dev->src = vvbuf_try_dqbuf(dev->sink_bctx); + if (!dev->src) { + dev->error |= BUF_ERR_UNDERFLOW; + return -ENOMEM; + } + dev->error &= ~BUF_ERR_UNDERFLOW; + if (!dev->get_index) { + dev->error |= BUF_ERR_WRONGSTATE; + dev->src = NULL; + return -ENXIO; + } + dev->index = dev->get_index(dev, dev->src); + if (dev->index < 0 || dev->index >= MAX_DWE_NUM) { + dev->error |= BUF_ERR_WRONGSTATE; + dev->src = NULL; + return -ENXIO; + } + dev->error &= ~BUF_ERR_WRONGSTATE; + if (!(*dev->state[dev->index] & STATE_DRIVER_STARTED)) { + vvbuf_try_dqbuf_done(dev->sink_bctx, dev->src); + vvbuf_ready(dev->sink_bctx, dev->src->pad, dev->src); + dev->error |= BUF_ERR_UNDERFLOW; + dev->src = NULL; + return 0; + } + no_dist_map_err = BUF_ERR_NO_DIST_MAP0 << dev->index; + if (!dev->dist_map[dev->index]) { + dev->error |= no_dist_map_err; + dev->src = NULL; + return -ENOMEM; + } + dev->error &= ~no_dist_map_err; + overflow_err = BUF_ERR_OVERFLOW0 << dev->index; + dev->dst = vvbuf_try_dqbuf(dev->src_bctx[dev->index]); + if (!dev->dst) { + if (!(*dev->state[dev->index] & STATE_STREAM_STARTED)) { + vvbuf_try_dqbuf_done(dev->sink_bctx, dev->src); + vvbuf_ready(dev->sink_bctx, dev->src->pad, dev->src); + } + dev->error |= overflow_err; + dev->src = NULL; + return -ENOMEM; + } + dev->error &= ~overflow_err; + vvbuf_try_dqbuf_done(dev->sink_bctx, dev->src); + vvbuf_try_dqbuf_done(dev->src_bctx[dev->index], dev->dst); + which = dev->which[dev->index]; + dwe_s_params(dev, &dev->info[dev->index][which]); + dwe_set_buffer(dev, &dev->info[dev->index][which], dev->dst->dma); + dwe_set_lut(dev, dev->dist_map[dev->index][which]); + dwe_start_dma_read(dev, &dev->info[dev->index][which], dev->src->dma); + dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL); + dwe_write_reg(dev, DEWARP_CTRL, dewarp_ctrl | 2); + dwe_write_reg(dev, DEWARP_CTRL, dewarp_ctrl); + dwe_write_reg(dev, INTERRUPT_STATUS, INT_MSK_STATUS_MASK); + dwe_enable_bus(dev, 1); + return 0; +} + +int dwe_on_buf_update(struct dwe_ic_dev *dev) +{ + int rc = 0; + unsigned long flags; + + if (dev) { + spin_lock_irqsave(&dev->irqlock, flags); + if (dev->error) + rc = update_dma_buffer(dev); + spin_unlock_irqrestore(&dev->irqlock, flags); + } + return rc; +} + +void dwe_clear_interrupts(struct dwe_ic_dev *dev) +{ + u32 status; + u32 clr; + status = dwe_read_reg(dev, INTERRUPT_STATUS); + clr = (status & 0xFF) << 24; + dwe_write_reg(dev, INTERRUPT_STATUS, clr); +} + +irqreturn_t dwe_hw_isr(int irq, void *data) +{ + struct dwe_ic_dev *dev = (struct dwe_ic_dev *)data; + u32 status; + u32 clr; + unsigned long flags; + + if (!dev) + return IRQ_HANDLED; + + status = dwe_read_reg(dev, INTERRUPT_STATUS); + if (status & INT_FRAME_DONE) { + clr = (status & 0xFF) << 24; + dwe_write_reg(dev, INTERRUPT_STATUS, clr); + spin_lock_irqsave(&dev->irqlock, flags); + if (dev->dst) { + vvbuf_ready(dev->src_bctx[dev->index], + dev->dst->pad, dev->dst); + dev->dst = NULL; + } + update_dma_buffer(dev); + spin_unlock_irqrestore(&dev->irqlock, flags); + } + return IRQ_HANDLED; +} + +#endif diff --git a/vvcam_ry/dwe/dwe_regs.h b/vvcam_ry/dwe/dwe_regs.h new file mode 100755 index 0000000..61d355f --- /dev/null +++ b/vvcam_ry/dwe/dwe_regs.h @@ -0,0 +1,104 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_REGS_H_ +#define _DWE_REGS_H_ + +#define REGISTER_NUM 100 +#define DEWARP_REGISTER_BASE_ADDR 0x00000000 +#define DEWARP_CTRL 0x00000004 +#define SWAP_CONTROL 0x00000058 +#define VERTICAL_SPLIT_LINE 0x0000005C +#define HORIZON_SPLIT_LINE 0x00000060 +#define SCALE_FACTOR 0x00000064 +#define ROI_START 0x00000068 +#define BOUNDRY_PIXEL 0x0000006C +#define INTERRUPT_STATUS 0x00000070 + +#define INT_FRAME_DONE (1 << 0) +#define INT_ERR_STATUS_MASK 0x000000FE +#define INT_ERR_STATUS_SHIFT 1 +#define INT_MSK_STATUS_MASK 0x0000FF00 +#define INT_MSK_STATUS_SHIFT 8 +#define INT_FRAME_BUSY 0x00010000 +#define INT_CLR_MASK 0xFF000000 +#define BUS_CTRL 0x00000074 +#define DEWRAP_BUS_CTRL_ENABLE_MASK (1 << 31) + +#define BUS_CTRL1 0x00000078 +#define BUS_TIME_OUT_CYCLE 0x0000007C +#define MAP_LUT_ADDR 0x00000008 +#define MAP_LUT_SIZE 0x0000000C +#define SRC_IMG_Y_BASE 0x00000010 +#define SRC_IMG_UV_BASE 0x00000014 +#define SRC_IMG_SIZE 0x00000018 +#define SRC_IMG_STRIDE 0x0000001C +#define MAP_LUT_ADDR2 0x00000020 +#define MAP_LUT_SIZE2 0x00000024 +#define SRC_IMG_Y_BASE2 0x00000028 +#define SRC_IMG_UV_BASE2 0x0000002C +#define SRC_IMG_SIZE2 0x00000030 +#define SRC_IMG_STRIDE2 0x00000034 +#define DST_IMG_Y_BASE 0x00000038 +#define DST_IMG_UV_BASE 0x0000003C +#define DST_IMG_SIZE 0x00000040 +#define DST_IMG_STRIDE 0x00000044 +#define DST_IMG_Y_BASE2 0x00000048 +#define DST_IMG_UV_BASE2 0x0000004C +#define DST_IMG_SIZE2 0x00000050 +#define DST_IMG_STRIDE2 0x00000054 +#define DST_IMG_Y_SIZE1 0x00000080 +#define DST_IMG_UV_SIZE1 0x00000084 +#define DST_IMG_Y_SIZE2 0x00000088 +#define DST_IMG_UV_SIZE2 0x0000008C + +#endif /* _DWE_REGS_H_ */ diff --git a/vvcam_ry/isp/cam_device_buf_defs_common.h b/vvcam_ry/isp/cam_device_buf_defs_common.h new file mode 100755 index 0000000..f5b7a88 --- /dev/null +++ b/vvcam_ry/isp/cam_device_buf_defs_common.h @@ -0,0 +1,110 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _CAMERA_DEVICE_BUF_DEFS_COMMON_H_ +#define _CAMERA_DEVICE_BUF_DEFS_COMMON_H_ + +enum { + CAMERA_PIX_FMT_YUV422SP = 0, + CAMERA_PIX_FMT_YUV422I, + CAMERA_PIX_FMT_YUV420SP, + CAMERA_PIX_FMT_YUV444, + CAMERA_PIX_FMT_RGB888, + CAMERA_PIX_FMT_RGB888P, +}; + + +typedef enum _ISPCORE_BUFIO_ID_ { + ISPCORE_BUFIO_MP = 0, + ISPCORE_BUFIO_SP1 = 1, + ISPCORE_BUFIO_SP2 = 2, + ISPCORE_BUFIO_RDI = 3, //RAW dump interface + ISPCORE_BUFIO_META = 4, //meta sw delivery port + ISPCORE_BUFIO_WRITEMAX = 5, + ISPCORE_BUFIO_READ = 6, + ISPCORE_BUFIO_MAX = 7, +} ISPCORE_BUFIO_ID; + +typedef struct __BufIdentity__ { + uint64_t address_usr; //address in V4l2 application space + uint64_t address_daemon; //address in native stack space + uint64_t address_kernel; //address in kernel space + uint32_t address_reg; //address set to ispcore register + uint32_t buffer_idx; //buffer index + uint32_t buff_size; //biffer size + uint32_t filled; + void *ctx; //memory handle + int width; + int height; + int format; +} BufIdentity; + +typedef struct ispcore_meta_kernel_s { + unsigned int data_kernel; +} ispcore_meta_kernel_t; + +typedef struct ispcore_meta_kernel_dma_s { + unsigned int data_kernel_dma; +} ispcore_meta_kernel_dma_t; + +typedef struct ispcore_meta_user_s { + unsigned int data_user; +} ispcore_meta_user_t; + +typedef struct ispcore_meta_s { + ispcore_meta_kernel_t kernel_meta; + ispcore_meta_kernel_dma_t kernel_meta_dma; + ispcore_meta_user_t user_meta; +} ispcore_meta_t; + +#endif // _CAMERA_DEVICE_BUF_DEFS_COMMON_H_ diff --git a/vvcam_ry/isp/ic_dev.h b/vvcam_ry/isp/ic_dev.h new file mode 100755 index 0000000..14ef93c --- /dev/null +++ b/vvcam_ry/isp/ic_dev.h @@ -0,0 +1,1102 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_DEV_H_ +#define _ISP_DEV_H_ + +#ifndef __KERNEL__ +#include +#include +#include +#include + +#define copy_from_user(a, b, c) isp_copy_data(a, b, c) +#define copy_to_user(a, b, c) isp_copy_data(a, b, c) + +#if defined(HAL_CMODEL) || defined(HAL_ALTERA) || defined ( HAL_LIGHT_FPGA ) +#include + +void isp_ic_set_hal(HalHandle_t hal); +#endif +#endif + +#include "isp_irq_queue.h" +#include "isp_version.h" +#include "vvdefs.h" + +#define REG_ADDR(x) ((uint32_t)(uintptr_t)&all_regs->x) + +#ifdef ISP_MIV1 +#define ISP_BUF_GAP (1024) +#elif defined ISP_MIV2_RY +#define ISP_BUF_GAP (0) +#endif + +#ifdef ISP_MI_BP +# define MI_PATH_NUM (3) +#else +# define MI_PATH_NUM (2) +#endif + +struct isp_reg_t { + u32 offset; + u32 val; +}; + +struct ic_window { + u16 x; + u16 y; + u16 width; + u16 height; +}; + +struct isp_context { + u32 mode; + u32 sample_edge; + bool hSyncLowPolarity, vSyncLowPolarity; + u32 bayer_pattern; + u32 sub_sampling; + u32 seq_ccir; + u32 field_selection; + u32 input_selection; + u32 latency_fifo; + struct ic_window acqWindow; /**< acquisition window */ + struct ic_window ofWindow; /**< output formatter window */ + struct ic_window isWindow; /**< image stabilization output window */ + u32 bypass_mode; + u8 demosaic_threshold; + u32 stitching_mode; +}; + +typedef struct isp_wdr_context +{ + bool enabled; + bool changed; //the wdr ctrl && reb shift does not have shandow + //register,need to change after frame end irq. + u16 LumOffset; + u16 RgbOffset; + u16 Ym[33]; + u8 dY[33]; + +} isp_wdr_context_t; + +struct isp_digital_gain_cxt { + /* data */ + bool enable; + u16 gain_r; + u16 gain_b; + u16 gain_gr; + u16 gain_gb; +}; + +struct isp_mi_data_path_context { + bool enable; + u32 out_mode; /**< output format */ + u32 in_mode; /**< input format */ + u32 data_layout; /**< layout of data */ + u32 data_alignMode; /**< align mode of data */ + u32 in_width; + u32 in_height; + u32 out_width; + u32 out_height; + bool hscale; + bool vscale; + int pixelformat; + bool yuv_bit; +}; + +struct isp_dummy_hblank_cxt { + u8 bp, fp, w, in_hsize; +}; +enum MIV2_PATH_ID { + ISP_MI_PATH_MP = 0, + ISP_MI_PATH_SP, + ISP_MI_PATH_SP2_BP, +#ifdef ISP_MI_MCM_WR_RY + ISP_MI_MCM_WR0, + ISP_MI_MCM_WR1, +#endif + ISP_MI_PATH_PP, +#ifdef ISP_MI_HDR_RY + ISP_MI_HDR_L, + ISP_MI_HDR_S, + ISP_MI_HDR_VS, +#endif + ISP_MI_PATH_ID_MAX +}; + +enum DMA_ID { + ISP_MI_DMA_ID_MCM_PP = 0, + ISP_MI_DMA_ID_HDR_L, + ISP_MI_DMA_ID_HDR_S, + ISP_MI_DMA_ID_HDR_VS, + ISP_MI_DMA_ID_MAX +}; +typedef enum start_dma_path_e{ + ISP_MI_DMA_PATH_MCM_PP = 0, + ISP_MI_DMA_PATH_HDR, + ISP_MI_DMA_PATH_MAX, +}start_dma_path_t; +struct isp_mi_context { + struct isp_mi_data_path_context path[ISP_MI_PATH_ID_MAX]; + u32 burst_len; +}; + +struct isp_bls_context { + bool enabled; + u32 mode; + u16 a, b, c, d; +}; + +struct isp_tpg_userdefine_mode { + u16 total, fp, sync, bp, act; +}; + +struct isp_tpg_context { + bool enabled; + u32 image_type; + u32 frame_num; + u32 bayer_pattern; + u32 color_depth; + u32 resolution; + u16 pixleGap; + u16 lineGap; + u16 gapStandard; + u32 randomSeed; + struct isp_tpg_userdefine_mode user_mode_h, user_mode_v; +}; + +typedef enum mcm_fmt_e{ + MCM_FMT_RAW8 = 0, + MCM_FMT_RAW10, + MCM_FMT_RAW12, + MCM_FMT_RAW14, + MCM_FMT_RAW16, + MCM_FMT_RAW20, + MCM_FMT_MAX, +}mcm_fmt_t; + +typedef enum mcm_wr_index_e{ + MCM_INDEX_WR0 = 0, //write channel 0 + MCM_INDEX_WR1, //write channel 1 + MCM_INDEX_G2_WR0, //MCM_G2 writec channel 0 + MCM_INDEX_G2_WR1, //MCM_G2 writec channel 1 + MCM_INDEX_WR_MAX, +}mcm_wr_fmt_t; + +struct isp_mcm_context { + bool sensor_mem_bypass; //0: use sensor latency memory in MCM + mcm_fmt_t wr_fmt[MCM_INDEX_WR_MAX]; + u8 bypass_switch; //Bypass switch 0000: sensor0 bypass 0001:sensor1 bypass .. 1111:sensor15 bypass if any + u16 height[MCM_INDEX_WR_MAX]; + u16 width[MCM_INDEX_WR_MAX]; + mcm_fmt_t rd_fmt; + u32 hsync_rpeample_ext; + + bool bypass_enable; + u32 vsync_blank; + u32 vsync_duration; + u32 hsync_blank; + u32 hsync_preample; +}; + +struct isp_mux_context { + u32 mp_mux; /**< main path muxer (vi_mp_mux) */ + u32 sp_mux; /**< self path muxer (vi_dma_spmux) */ + u32 chan_mode; /**< 1-mp, 2-sp, 4-sp2 */ + u32 ie_mux; /**< image effects muxer (vi_dma_iemux) */ + u32 dma_read_switch; /**< dma read switch (vi_dma_switch) */ + u32 if_select; /**< interface selector (if_select) */ +}; + +struct isp_awb_context { + bool enable; + u8 mode; + u16 gain_r, gain_gr, gain_gb, gain_b; + struct ic_window window; + u16 refcb_max_b; + u16 refcr_max_r; + u16 max_y; + u16 max_c_sum; + u16 min_y_max_g; + u16 min_c; +}; + +struct isp_awb_mean { + u32 r, g, b; + u32 no_white_count; +}; + +struct isp_cnr_context { + bool enable; + u32 line_width; + u32 threshold_1; + u32 threshold_2; +}; + +struct isp_cc_context { + u32 lCoeff[9]; + bool update_curve; + bool conv_range_y_full, conv_range_c_full; +}; + +struct isp_xtalk_context { + u32 lCoeff[9]; + u32 r, g, b; +}; + +struct isp_gamma_out_context { + bool enableWB, enableGamma; + bool changed; + u32 mode; + u32 curve[17]; +}; + +#define CAEMRIC_GRAD_TBL_SIZE 8 +#define CAMERIC_DATA_TBL_SIZE 289 +#define CAMERIC_MAX_LSC_SECTORS 16 +#define CA_CURVE_DATA_TABLE_LEN 65 + +struct isp_lsc_context { + /**< correction values of R color part */ + u16 r[CAMERIC_DATA_TBL_SIZE]; + /**< correction values of G (red lines) color part */ + u16 gr[CAMERIC_DATA_TBL_SIZE]; + /**< correction values of G (blue lines) color part */ + u16 gb[CAMERIC_DATA_TBL_SIZE]; + /**< correction values of B color part */ + u16 b[CAMERIC_DATA_TBL_SIZE]; + /**< multiplication factors of x direction */ + u16 x_grad[CAEMRIC_GRAD_TBL_SIZE]; + /**< multiplication factors of y direction */ + u16 y_grad[CAEMRIC_GRAD_TBL_SIZE]; + /**< sector sizes of x direction */ + u16 x_size[CAEMRIC_GRAD_TBL_SIZE]; + /**< sector sizes of y direction */ + u16 y_size[CAEMRIC_GRAD_TBL_SIZE]; +}; + +struct isp_dmoi_context { + bool enable; + uint8_t demoire_area_thr; + uint8_t demoire_sat_shrink; + uint16_t demoire_r2; + uint16_t demoire_r1; + uint8_t demoire_t2_shift; + uint8_t demoire_t1; + uint16_t demoire_edge_r2; + uint16_t demoire_edge_r1; + uint8_t demoire_edge_t2_shift; + uint16_t demoire_edge_t1; +}; + +struct isp_shap_context { + bool enable; + uint16_t sharpen_factor_black; + uint16_t sharpen_factor_white; + uint16_t sharpen_clip_black; + uint16_t sharpen_clip_white; + uint16_t sharpen_t4_shift; + uint16_t sharpen_t3; + uint8_t sharpen_t2_shift; + uint16_t sharpen_t1; + uint16_t sharpen_r3; + uint16_t sharpen_r2; + uint16_t sharpen_r1; +}; + +struct isp_shap_line_context { + bool enable; + uint8_t sharpen_line_shift2; + uint8_t sharpen_line_shift1; + uint16_t sharpen_line_t1; + uint16_t sharpen_line_strength; + uint16_t sharpen_line_r2; + uint16_t sharpen_line_r1; +}; + +struct isp_gfilter_context { + uint8_t sharpen_size; + uint8_t hf_filt_00; + uint8_t hf_filt_01; + uint8_t hf_filt_02; + uint8_t hf_filt_10; + uint8_t hf_filt_11; + uint8_t hf_filt_12; + uint8_t hf_filt_20; + uint8_t hf_filt_21; + uint8_t hf_filt_22; +}; + +struct isp_skin_context { + bool enable; + uint16_t cb_thr_max_2047; + uint16_t cb_thr_min_2047; + uint16_t cr_thr_max_2047; + uint16_t cr_thr_min_2047; + uint16_t y_thr_max_2047; + uint16_t y_thr_min_2047; +}; + +struct isp_depurple_context { + bool enable; + bool red_sat, blue_sat; + uint8_t depurple_sat_shrink; + uint8_t depurple_thr; +}; + +struct isp_intp_thr_cxt { + u16 intp_dir_thr_min; + u16 intp_dir_thr_max; +}; + +struct isp_dmsc_context { + bool enable; + uint8_t demosaic_thr; + uint8_t denoise_stren; + struct isp_intp_thr_cxt intp; + struct isp_dmoi_context demoire; + struct isp_shap_context sharpen; + struct isp_gfilter_context gFilter; + struct isp_shap_line_context sharpenLine; + struct isp_skin_context skin; + struct isp_depurple_context depurple; +}; + +struct isp_ge_context { + bool enable; + u16 threshold; + u16 h_dummy; +}; + +struct isp_ca_context { + bool enable; + u8 mode; + u16 lut_x[CA_CURVE_DATA_TABLE_LEN]; + u16 lut_luma[CA_CURVE_DATA_TABLE_LEN]; + u16 lut_chroma[CA_CURVE_DATA_TABLE_LEN]; + u16 lut_shift[CA_CURVE_DATA_TABLE_LEN]; +}; + +struct isp_buffer_context { + u32 type; + u32 path; + u32 addr_y, addr_cb, addr_cr; + u32 size_y, size_cb, size_cr; +}; + +struct isp_bp_buffer_context { + u32 addr_r; + u32 addr_gr; + u32 addr_gb; + u32 addr_b; +}; + +struct isp_dma_context { + u32 type; + u32 base; + u32 width; + u32 height; + u32 burst_y; + u32 burst_c; + u8 align; + u8 id; +#ifdef ISP_MI_HDR_RY + u8 rd_wr_str; +#endif +}; + +struct isp_dpf_context { + bool enable; + u32 filter_type; + u32 gain_usage; + u32 strength_r; + u32 strength_g; + u32 strength_b; + u8 weight_g[6]; + u8 weight_rb[6]; + u16 denoise_talbe[17]; + u32 x_scale; + u32 nf_gain_r; + u32 nf_gain_gr; + u32 nf_gain_gb; + u32 nf_gain_b; + bool filter_r_off; + bool filter_gr_off; + bool filter_gb_off; + bool filter_b_off; +}; + +struct isp_is_context { + bool enable; + bool update; + struct ic_window window; + u32 recenter; + u32 max_dx, max_dy; + u32 displace_x, displace_y; +}; + +struct isp_ee_context { + bool enable; + u8 src_strength; + u8 strength; + u8 input_sel; + u32 y_gain, uv_gain, edge_gain; +}; + +struct isp_exp_context { + bool enable; + u32 mode; + struct ic_window window; +}; + +struct isp_hist_context { + bool enable; + u32 mode; + u32 step_size; + struct ic_window window; + u8 weight[25]; +}; + +struct isp_hist64_context { + bool enable; + u8 channel; + u32 mode; + u8 vStepSize; + u32 hStepInc; + u8 r_coeff, g_coeff, b_coeff; + u8 sample_shift; + u16 sample_offset; + u16 forced_upd_start_line; + bool forced_upd; + struct ic_window window; + u8 weight[25]; +}; + +struct isp_dpcc_params { + u32 line_thresh; + u32 line_mad_fac; + u32 pg_fac; + u32 rnd_thresh; + u32 rg_fac; +}; + +struct isp_dpcc_context { + bool enable; + u32 mode; + u32 outmode; + u32 set_use; + u32 methods_set[3]; + struct isp_dpcc_params params[3]; + u32 ro_limits; + u32 rnd_offs; +}; + +struct isp_flt_context { + bool enable; + bool changed; + u32 denoise; + u32 sharpen; +}; + +struct isp_cac_context { + bool enable; + u32 hmode, vmode; + u32 ab, ar, bb, br, cb, cr; + u32 xns, xnf, yns, ynf; + u32 hstart, vstart; +}; + +/* degamma */ +struct isp_deg_context { + bool enable; + u8 segment[16]; + u16 r[17]; + u16 g[17]; + u16 b[17]; +}; + +struct isp_ie_context { + bool enable; + u32 mode; + u32 color_sel; + u32 color_thresh; + u32 sharpen_factor; + u32 sharpen_thresh; + int32_t m[9]; + u32 tint_cr; + u32 tint_cb; + bool full_range; +}; + +struct isp_afm_result { + u32 sum_a, sum_b, sum_c; + u32 lum_a, lum_b, lum_c; +}; + +struct isp_afm_context { + bool enable; + u32 thresh; + struct ic_window window[3]; + u32 pixCnt[3]; + bool enableWinId[3]; + u32 lum_shift; + u32 afm_shift; + u32 max_pix_cnt; +}; + +struct isp_vsm_result { + u32 x, y; +}; + +struct isp_vsm_context { + bool enable; + struct ic_window window; + u32 h_seg, v_seg; +}; + +#ifndef WDR3_BIN +#define WDR3_BIN 14 +#endif +struct isp_wdr3_context { + bool enable; + bool changed; + bool inited; + u32 strength; + u32 max_gain; + u32 global_strength; + u32 histogram[WDR3_BIN]; + u32 shift[WDR3_BIN]; + u32 invert_linear[WDR3_BIN]; + u32 invert_curve[WDR3_BIN]; + u32 gamma_pre[WDR3_BIN]; + u32 gamma_up[WDR3_BIN]; + u32 gamma_down[WDR3_BIN]; + u32 entropy[WDR3_BIN]; + u32 distance_weight[WDR3_BIN]; + u32 difference_weight[WDR3_BIN]; +}; + +#ifdef ISP_WDR_V4 +#ifndef WDR4_BIN +#define WDR4_BIN 20 +#endif + +struct isp_wdr4_context { + bool enable; + bool changed; + bool inited; + u8 ratioLSVS, ratioLS; + u8 drc_bayer_ratio, drc_bayer_ratioLSVS; + u32 strength; + u32 high_strength; + u32 low_strength; + u32 low_gain; + u32 global_strength; + int contrast; + u32 flat_strength; + u32 flat_threshold; + u32 histogram[WDR4_BIN]; + u32 shift[WDR4_BIN]; + u32 shift0[WDR4_BIN]; + u32 invert_linear[WDR4_BIN]; + u32 invert_curve[WDR4_BIN]; + u32 gamma_pre[WDR4_BIN]; + u32 gamma_up[WDR4_BIN]; + u32 gamma_down[WDR4_BIN]; + u32 entropy[WDR4_BIN]; + u32 distance_weight[WDR4_BIN]; + u32 difference_weight[WDR4_BIN]; + u32 smooth_invert[WDR4_BIN]; +}; + +#endif +#ifndef ISP_AEV2_V2_RY +#define AEV2_DMA_SIZE 4096 +#else +#define AEV2_DMA_SIZE (4096 *2) +#endif +struct isp_exp2_context { + bool enable; + struct ic_window window; + /* weight; */ + u8 r, gr, gb, b; + u8 input_select; //00: degamma output, 01: awb_gain output 10: WDR3 output + /* write 4096/8192 EXPV2 mean value to dma by MI MP-JDP path. */ + /* physical address, alloacte by user */ + u64 pa; +}; + +#define ISP_2DNR_SIGMA_BIN 60 +struct isp_2dnr_context { + bool enable; + u32 pre_gamma; + u32 strength; + u16 sigma[ISP_2DNR_SIGMA_BIN]; +#if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4) + u32 sigma_sqr; + u32 weight; +#endif +#ifdef ISP_2DNR_V4 + u16 str_off; + u16 str_max; + u8 str_slope; +#endif +}; + +struct isp_3dnr_compress_context { + u8 weight_up_y[2]; + u8 weight_down[4]; + u8 weight_up[8]; +}; +struct isp_3dnr_context { + bool enable; + bool update_bin; + bool enable_h, enable_v; + bool enable_temperal; + bool enable_dilate; + bool init; + u32 spacial_curve[17]; + u32 temperal_curve[17]; + u32 strength; + u16 motion_factor; + u16 delta_factor; + /* write full denoise3d reference raw image to dma by MI SP2. */ + /* physical address, alloacte by user */ + u64 pa; + u32 size; + struct isp_3dnr_compress_context compress; +}; + +struct isp_3dnr_update { + u32 thr_edge_h_inv; + u32 thr_edge_v_inv; + u32 thr_motion_inv; + u32 thr_range_s_inv; + u32 range_t_h; + u32 range_t_v; + u32 range_d; + u32 thr_range_t_inv; + u32 thr_delta_h_inv; + u32 thr_delta_v_inv; + u32 thr_delta_t_inv; +}; + +#ifdef ISP_3DNR_V3 +#define DENOISE3D_GAMMA_BIN 33 + +struct isp_tdnr_stats { + u32 bg_sum; + u32 motion_sum; + u32 bg_pixel_cnt; + u32 motion_pixel_cnt; + u32 frame_avg; +}; + +struct isp_tdnr_curve { + u16 preGamma_y[DENOISE3D_GAMMA_BIN]; + u16 invGamma_y[DENOISE3D_GAMMA_BIN]; +}; + +struct isp_tdnr_buffer { + /* write full denoise3d reference raw image to dma by MI SP2. */ + /* physical address, alloacte by user */ + u64 pa_refer; + u32 size_refer; + u64 pa_motion; + u32 size_motion; +}; + +struct isp_tdnr_context { + bool enable; + bool enable_inv_gamma; + bool enable_pre_gamma; + bool enable_motion_erosion; + bool enable_motion_converage; + bool enable_motion_dilation; + bool enable_tnr; + bool enable_2dnr; + u8 strength; + u16 noise_level; + u16 noise_mean; + u16 noise_threshold; + u16 motion_mean; + u8 range_h; + u8 range_v; + u8 dilate_range_h; + u8 dilate_range_v; + u32 motion_inv_factor; + u16 update_factor; + u16 motion_update_factor; + u16 pre_motion_weight; + u16 motion_slope; + u16 motion_converage_shift; + u16 motion_converage_max; + u16 tnr_val_shift_bit; + u16 tnr_diff_shift_bit; + u16 sad_weight; + u16 luma_pixel_val_shift; + u16 luma_pixel_slope; + u16 luma_pixel_slope_shift; + u16 luma_pixel_slope_min; + u16 dmy_hblank; + u32 fn; + struct isp_tdnr_curve curve; + struct isp_tdnr_buffer buf; + + u8 frames; //skip the first frame before clear reset. + //keep the 3dnr enable in register to avoid scrolling screen when repeat enable +}; + +#endif + +struct isp_hdr_context { + bool enable; + /* hdr bls */ + u16 width; + u16 height; + u8 l_bit_dep, s_bit_dep, vs_bit_dep, ls_bit_dep; + u8 weight0, weight1, weight2; + u16 start_linear, norm_factor_mul_linear; + u16 start_nonlinear, norm_factor_mul_nonlinear; + u16 dummy_hblank, out_hblank; + u16 out_vblank; + u16 long_exp, short_exp, very_short_exp; + u16 bls[4]; + u16 digal_gain[4]; + u32 reg; + /* hdr awb */ + u32 r, gr, gb, b; + /* hdr exp */ + u32 compress_lut[15]; + /* long short, very short */ + u32 ls0, ls1, vs0, vs1; + u32 ext_bit; + u32 valid_thresh; + u32 offset_val; + u32 sat_thresh; + u32 combine_weight; +}; + +struct isp_simp_context { + bool enable; + u32 x, y; + u32 r, g, b; + u32 transparency_mode; + u32 ref_image; +}; + +struct isp_compand_curve_context { + bool enable; + bool update_curve; + uint8_t in_bit; + uint8_t out_bit; + uint32_t px[64]; + uint32_t x_data[63]; + uint32_t y_data[64]; +}; + +struct isp_compand_bls_context_ry { + uint8_t bit_width; + bool enable; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; +}; + +/* COMPAND */ +struct isp_comp_context { + bool enable; + struct isp_compand_curve_context expand; + struct isp_compand_bls_context_ry bls; + struct isp_compand_curve_context compress; +}; + +struct isp_cproc_context { + bool enable; + bool changed; + u32 contrast; + u32 brightness; + u32 saturation; + u32 hue; + bool y_out_full; + bool c_out_full; + bool y_in_full; +}; + +struct elawb_ellipse_info { + u32 x, y; /* ellipse center */ + u32 a1, a2, a3, a4; /* ellipse axis */ + u32 r_max_sqr; +}; + +struct isp_elawb_context { + bool enable; + u32 id; /* ellipse id, 1-8, 0 means update all. */ + struct elawb_ellipse_info info[8]; + struct ic_window window; + u32 r, gr, gb, b; /* gain */ +}; + +struct isp_gcmono_data { + u8 basePara[1024]; + u32 px[64]; + u32 dataX[63]; + u32 dataY[64]; +}; + +struct isp_gcmono_context { + u32 enable; + u32 mode; +}; + +struct isp_rgbgamma_data { + u32 rgbgc_r_px[64]; + u32 rgbgc_r_datax[63]; + u32 rgbgc_r_datay[64]; + u32 rgbgc_g_px[64]; + u32 rgbgc_g_datax[63]; + u32 rgbgc_g_datay[64]; + u32 rgbgc_b_px[64]; + u32 rgbgc_b_datax[63]; + u32 rgbgc_b_datay[64]; +}; + +struct isp_rgbgamma_context { + bool enable; +}; + +struct isp_irq_data { + uint32_t addr; + uint32_t val; + uint32_t nop[14]; +}; + +struct isp_rgbir_bls_context { + u16 a; + u16 b; + u16 c; + u16 d; +}; + +struct isp_rgbir_rgb_gain_context { + u16 r; + u16 g; + u16 b; +}; + +struct isp_rgbir_dpcc_context { + u16 median_thr[4]; + u16 avg_thr[4]; +}; + +struct isp_rgbir_cc_context { + u16 mtx[3][4]; +}; + +struct isp_rgbir_des_context { + u32 ir_px1, ir_py[16]; + u32 ir_pd[16], l_pd[16]; + u32 l_px1, l_py[16]; +}; + +struct isp_rgbir_sharpen_context { + u8 sharpen_lvl, middle; + u16 thresh_bl0, thresh_bl1; + u16 thresh_sh0, thresh_sh1; + u8 lum_weight_min, lum_weight_kink, lum_weight_gain; +}; + +struct isp_rgbir_ir_dnr_context { + u16 ir_sigmaS; + u8 winweight[6]; + u16 width, height; +}; +struct isp_rgbir_context{ + bool prefilt_enable, green_filt_mode, green_filt_enable; + u8 rgbirPattern, out_rgb_pattern, green_filt_stage1_select; + u8 demosaic_threshold; + bool part1_enable, part2_enable; + bool enable_ir_raw_out; + + struct isp_rgbir_bls_context bls; + struct isp_rgbir_rgb_gain_context rgb_gain; + struct isp_rgbir_dpcc_context dpcc; + struct isp_rgbir_cc_context cc; + struct isp_rgbir_des_context des; + struct isp_rgbir_sharpen_context sharpen; + struct isp_rgbir_ir_dnr_context ir_dnr; +}; + +struct isp_crop_context { + bool enabled; + struct ic_window window; +}; + +#if 1 // def ISP_MI_PP_READ_RY +typedef struct pp_dma_line_entry_s { + u32 width; + u32 height; + u32 stride; + u32 buf_size;/**/ + u32 data_format; + u16 entry_line_num; + u32 buf_line_num; + u64 buf_addr; +} pp_dma_line_entry_t; + +#endif + +typedef struct pp_wr_line_entry_ry_s { + u16 entry_line_num; + u16 buf_line_num; + u32 buf_addr; + u32 buf_size; +} pp_wr_line_entry_ry_t; + +struct isp_ic_dev { + void __iomem *base; + void __iomem *reset; + int id; +#ifdef ISP8000NANO_V1802 + struct regmap *mix_gpr; +#endif +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + struct vvbuf_ctx *bctx; + struct vb2_dc_buf *mi_buf[MI_PATH_NUM]; + struct vb2_dc_buf *mi_buf_shd[MI_PATH_NUM]; + int (*alloc)(struct isp_ic_dev *dev, struct isp_buffer_context *buf); + int (*free)(struct isp_ic_dev *dev, struct vb2_dc_buf *buf); + int *state; +#endif + void (*post_event)(struct isp_ic_dev *dev, void *data, size_t size); + + struct isp_context ctx; + struct isp_digital_gain_cxt dgain; + struct isp_bls_context bls; + struct isp_tpg_context tpg; + struct isp_mcm_context mcm; + struct isp_mux_context mux; + struct isp_awb_context awb; + struct isp_lsc_context lsc; + struct isp_gamma_out_context gamma_out; + struct isp_xtalk_context xtalk; + struct isp_cc_context cc; + struct isp_cnr_context cnr; + struct isp_is_context is; + struct isp_is_context rawis; + struct isp_mi_context mi; + struct isp_dpf_context dpf; + struct isp_ee_context ee; + struct isp_exp_context exp; + struct isp_hist_context hist; +#ifdef ISP_HIST64_RY + struct isp_hist64_context hist64; +#endif + struct isp_dpcc_context dpcc; + struct isp_flt_context flt; + struct isp_cac_context cac; + struct isp_deg_context deg; + struct isp_ie_context ie; + struct isp_vsm_context vsm; + struct isp_afm_context afm; + struct isp_wdr3_context wdr3; + struct isp_exp2_context exp2; + struct isp_hdr_context hdr; + struct isp_exp_context hdrexp; + struct isp_hist_context hdrhist; + struct isp_2dnr_context dnr2; + struct isp_3dnr_context dnr3; + + struct isp_comp_context comp; + struct isp_simp_context simp; + struct isp_cproc_context cproc; + struct isp_elawb_context elawb; + struct isp_gcmono_context gcmono; + struct isp_rgbgamma_context rgbgamma; + struct isp_dmsc_context demosaic; + struct isp_ge_context ge; + struct isp_ca_context ca; + struct isp_dummy_hblank_cxt hblank; + isp_wdr_context_t wdr; + bool streaming; + bool update_lsc_tbl; + bool update_gamma_en; +#ifdef ISP_WDR_V4 + struct isp_wdr4_context wdr4; +#endif +#ifdef ISP_3DNR_V3 + struct isp_tdnr_context tdnr; +#endif + struct isp_rgbir_context rgbir; + u32 isp_mis; +#ifdef ISP_MI_PP_READ_RY + pp_dma_line_entry_t pp_dma_line_entry; +#endif + struct isp_crop_context crop[ISP_MI_PATH_SP2_BP + 1]; + pp_wr_line_entry_ry_t pp_write; + isp_mis_list_t circle_list; //The irq circle list + long long unsigned int ut_phy_addr; //for units test + void *ut_addr; + struct device *device; +}; + +struct isp_extmem_info { + u64 addr; + u64 size; +}; + +void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val); +u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset); + +#endif /* _ISP_DEV_H_ */ diff --git a/vvcam_ry/isp/insmod.sh b/vvcam_ry/isp/insmod.sh new file mode 100755 index 0000000..e7f868a --- /dev/null +++ b/vvcam_ry/isp/insmod.sh @@ -0,0 +1,6 @@ +#!/bin/bash +modprobe vivid +rmmod vivid +rmmod viv_isp_driver.ko +insmod viv_isp_driver.ko + diff --git a/vvcam_ry/isp/isp_3dnr.c b/vvcam_ry/isp/isp_3dnr.c new file mode 100755 index 0000000..a54332d --- /dev/null +++ b/vvcam_ry/isp/isp_3dnr.c @@ -0,0 +1,455 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "isp_ioctl.h" +#include "mrv_all_bits.h" + +#include "isp_types.h" +#ifdef ISP_3DNR +extern MrvAllRegister_t *all_regs; + + +static void dnr3_hw_init(struct isp_ic_dev *dev) +{ + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 regVal = 0; + int i, pos; + /* spacial */ + u32 update_spacial = 900; + u32 strength_curve_spacial = 64; + u32 thr_edge_v_inv = 1024; + u32 thr_edge_h_inv = 1024; + u32 thr_range_s_inv = 1024; + /* temperal */ + u32 update_temperal = 1020; + u32 strength_curve_temperal = 64; + u32 range_t_h = 2; + u32 range_t_v = 2; + u32 thr_range_t_inv = 41943; + u32 thr_motion_inv = 1024; + u32 range_d = 1; + u32 thr_delta_h_inv = 1023; + u32 thr_delta_v_inv = 1023; + u32 thr_delta_t_inv = 1023; + u32 strength = dnr3->strength; + strength = MIN(MAX(strength, 0), 128); + + if (dnr3->init) { //for 3dnr init + u32 isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl)); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_HORIZONTAL_EN, + dnr3->enable_h); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_VERTICAL_EN, + dnr3->enable_v); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_TEMPERAL_EN, + dnr3->enable_temperal); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_DILATE_EN, + dnr3->enable_dilate); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl); + } + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_SPACIAL, + strength_curve_spacial); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, thr_edge_h_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_TEMPERAL, + strength_curve_temperal); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, thr_edge_v_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, thr_range_s_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, range_t_h); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, range_t_v); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, thr_range_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, range_d); + REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, thr_motion_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, thr_delta_h_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, thr_delta_v_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, thr_delta_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal); + /* spacial */ + + for (i = 0; i < 6; i++) { + regVal = 0; + pos = i * 3; + if (i < 5) { + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE0, + dnr3->spacial_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1, + dnr3->spacial_curve[pos + 1]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2, + dnr3->spacial_curve[pos + 2]); + } else { + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1, + dnr3->spacial_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2, + dnr3->spacial_curve[pos + 1]); + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_s[i]), regVal); + regVal = 0; + if (i < 5) { + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE0, + dnr3->temperal_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1, + dnr3->temperal_curve[pos + 1]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2, + dnr3->temperal_curve[pos + 2]); + } else { + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1, + dnr3->temperal_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2, + dnr3->temperal_curve[pos + 1]); + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_t[i]), regVal); + } + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_UPDATE_SPACIAL, update_spacial); + REG_SET_SLICE(regVal, DENOISE3D_UPDATE_TEMPERAL, update_temperal); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_dummy_hblank), 0x80); +} + +int isp_u_3dnr_strength(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR + //pr_err("Not supported 3dnr\n"); + return -1; +#else + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 isp_ctrl; + u32 isp_denoise3d_strength; + + isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + return 0; +#endif +} + +int isp_s_3dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR + //pr_err("Not supported 3dnr\n"); + return -1; +#else + u32 isp_denoise3d_ctrl; + + struct isp_3dnr_context *dnr3 = &dev->dnr3; + + u32 isp_denoise3d_strength, isp_denoise3d_motion, isp_denoise3d_delta_inv; + + pr_info("enter %s\n", __func__); + if (dnr3->update_bin) { + dnr3_hw_init(dev); + } + + isp_denoise3d_motion = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), + isp_denoise3d_motion); + isp_denoise3d_delta_inv = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), + isp_denoise3d_delta_inv); + + isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); +#ifndef NR200 + if (!dnr3->enable) { + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, 0); + } else { + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength); + isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl)); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl); + + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength); +#else + isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl)); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl); + + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); +#endif + return 0; +#endif +} + +int isp_s_3dnr_motion(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR + pr_err("Not supported 3dnr\n"); + return -1; +#else + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 isp_denoise3d_motion; + u32 isp_ctrl; + + isp_denoise3d_motion = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), + isp_denoise3d_motion); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); +#endif + return 0; +} + +int isp_s_3dnr_delta(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR + pr_err("Not supported 3dnr\n"); + return -1; +#else + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 isp_denoise3d_delta_inv; + u32 isp_ctrl; + + isp_denoise3d_delta_inv = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), + isp_denoise3d_delta_inv); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); +#endif + + return 0; +} + +int isp_u_3dnr(struct isp_ic_dev *dev, struct isp_3dnr_update *dnr3_update) +{ +#ifndef ISP_3DNR + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + u32 regVal = 0; + + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH, dev->dnr3.strength); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_h)); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, + dnr3_update->thr_edge_h_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_v)); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, + dnr3_update->thr_edge_v_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_s)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, + dnr3_update->thr_range_s_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_t)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, dnr3_update->range_t_h); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, dnr3_update->range_t_v); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, + dnr3_update->thr_range_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, dnr3_update->range_d); + REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, + dnr3_update->thr_motion_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, + dnr3_update->thr_delta_h_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, + dnr3_update->thr_delta_v_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, + dnr3_update->thr_delta_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal); + +#ifdef NR200 + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); +#endif + return 0; +#endif +} + +int isp_g_3dnr(struct isp_ic_dev *dev, u32 * avg) +{ + if (!dev || !avg) { + return -EINVAL; + } + *avg = isp_read_reg(dev, REG_ADDR(isp_denoise3d_average)); + return 0; +} + +int isp_r_3dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR + return -1; +#else + u32 in_width, in_height; + u32 size, lval; + u32 miv2_sp2_bus_id; + u32 miv2_sp2_fmt; + + u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc)); + u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl)); + + //SP2_RAW_PATH_ENABLE is shadow bit, need set SP2_MI_CFG_UPD to update to shadow. + //So here config before set SP2_MI_CFG_UPD + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW_PATH_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + + +#ifndef NR200 + in_width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size)); + in_height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size)); +#else + in_width = isp_read_reg(dev, REG_ADDR(isp_out_h_size)); + in_height = isp_read_reg(dev, REG_ADDR(isp_out_v_size)); +#endif + lval = (in_width * 12 + 127)/ 128; + + lval <<= 4; + + size = in_height * lval; //raw12 unaligned + //write reference frame config + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_base_ad_init), dev->dnr3.pa); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_size_init), size); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_offs_cnt_init), 0); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_height), in_height); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_size), size); + + miv2_sp2_bus_id = isp_read_reg(dev, REG_ADDR(miv2_sp2_bus_id)); + + REG_SET_SLICE(miv2_sp2_bus_id, SP2_WR_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_BURST_LEN, 2); //sp2 rd burst lenghth 16 + REG_SET_SLICE(miv2_sp2_bus_id, SP2_BUS_SW_EN, 1); + + isp_write_reg(dev, REG_ADDR(miv2_sp2_bus_id), miv2_sp2_bus_id); + + miv2_sp2_fmt = isp_read_reg(dev, REG_ADDR(miv2_sp2_fmt)); + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_ALIGNED, 0); //unaligned + + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_ALIGNED, 0); //unaligned + + isp_write_reg(dev, REG_ADDR(miv2_sp2_fmt), miv2_sp2_fmt); + + //read reference frame config + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), dev->dnr3.pa); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_lval), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_size), size); + + + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1); + + /* we successfully programmed a buffer to marvin, so we need + * to enable updateing of base and offset registers */ + miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK); + isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl); + + miv2_imsc |= SP2_DMA_RAW_READY_MASK; + isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc); + + return 0; +#endif +} +#endif diff --git a/vvcam_ry/isp/isp_3dnr2.c b/vvcam_ry/isp/isp_3dnr2.c new file mode 100755 index 0000000..9721f44 --- /dev/null +++ b/vvcam_ry/isp/isp_3dnr2.c @@ -0,0 +1,433 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +#ifdef ISP_3DNR_V2 + +extern MrvAllRegister_t *all_regs; + +static void dnr3_hw_init(struct isp_ic_dev *dev) +{ + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 regVal = 0; + int i, pos; + /* spacial */ + u32 update_spacial = 900; + u32 strength_curve_spacial = 64; + u32 thr_edge_v_inv = 1024; + u32 thr_edge_h_inv = 1024; + u32 thr_range_s_inv = 1024; + /* temperal */ + u32 update_temperal = 1020; + u32 strength_curve_temperal = 64; + u32 range_t_h = 1; + u32 range_t_v = 1; + u32 thr_range_t_inv = 1024; + u32 thr_motion_inv = 1024; + u32 range_d = 1; + u32 thr_delta_h_inv = 1023; + u32 thr_delta_v_inv = 1023; + u32 thr_delta_t_inv = 1023; + u32 strength = dnr3->strength; + strength = MIN(MAX(strength, 0), 128); + + if (dnr3->init) { //for 3dnr init + u32 isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl)); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_READ_REF_EN, 1); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_WRITE_REF_EN, 1); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_HORIZONTAL_EN, + dnr3->enable_h); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_VERTICAL_EN, + dnr3->enable_v); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_TEMPERAL_EN, + dnr3->enable_temperal); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_DILATE_EN, + dnr3->enable_dilate); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl); + + } + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_SPACIAL, + strength_curve_spacial); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, thr_edge_h_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_TEMPERAL, + strength_curve_temperal); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, thr_edge_v_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, thr_range_s_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, range_t_h); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, range_t_v); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, thr_range_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, range_d); + REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, thr_motion_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, thr_delta_h_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, thr_delta_v_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, thr_delta_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal); + /* spacial */ + + for (i = 0; i < 6; i++) { + regVal = 0; + pos = i * 3; + if (i < 5) { + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE0, + dnr3->spacial_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1, + dnr3->spacial_curve[pos + 1]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2, + dnr3->spacial_curve[pos + 2]); + } else { + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1, + dnr3->spacial_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2, + dnr3->spacial_curve[pos + 1]); + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_s[i]), regVal); + regVal = 0; + if (i < 5) { + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE0, + dnr3->temperal_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1, + dnr3->temperal_curve[pos + 1]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2, + dnr3->temperal_curve[pos + 2]); + } else { + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1, + dnr3->temperal_curve[pos + 0]); + REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2, + dnr3->temperal_curve[pos + 1]); + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_t[i]), regVal); + } + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_UPDATE_SPACIAL, update_spacial); + REG_SET_SLICE(regVal, DENOISE3D_UPDATE_TEMPERAL, update_temperal); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal); +} + +int isp_s_3dnr_cmp(struct isp_ic_dev *dev) { + + struct isp_3dnr_compress_context *compress = &dev->dnr3.compress; + + u32 isp_denoise3d_weight1 = 0; // isp_read_reg(dev, REG_ADDR(isp_denoise3d_weight1)); + u32 isp_denoise3d_weight2 = 0; // isp_read_reg(dev, REG_ADDR(isp_denoise3d_weight2)); + int i = 0; + for (i = 0; i < 4; i++) { + isp_denoise3d_weight1 |= (compress->weight_down[i] & DENOISE3D_WEIGHT_MASK) << (3 - i) * 4; + } + REG_SET_SLICE(isp_denoise3d_weight1, DENOISE3D_WEIGHT_UP_Y0, compress->weight_up_y[0]); + REG_SET_SLICE(isp_denoise3d_weight1, DENOISE3D_WEIGHT_UP_Y1, compress->weight_up_y[1]); + + for (i = 0; i < 8; i++) { + isp_denoise3d_weight2 |= (compress->weight_up[i] & DENOISE3D_WEIGHT_MASK) << (7 - i) * 4; + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_weight1), isp_denoise3d_weight1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_weight2), isp_denoise3d_weight2); + return 0; +} + +int isp_s_3dnr(struct isp_ic_dev *dev) +{ + + struct isp_3dnr_context *dnr3 = &dev->dnr3; + + u32 isp_denoise3d_strength, isp_denoise3d_motion, isp_denoise3d_delta_inv; + u32 isp_denoise3d_ctrl; + + pr_info("enter %s\n", __func__); + if (dnr3->update_bin) { + dnr3_hw_init(dev); + } + + isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); + if (!dnr3->enable) { + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, 0); + } else { + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength); + } + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), + isp_denoise3d_strength); + + isp_denoise3d_motion = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), + isp_denoise3d_motion); + isp_denoise3d_delta_inv = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), + isp_denoise3d_delta_inv); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_dummy_hblank), 0x80); + + + isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl)); + + if (dnr3->enable) { + isp_s_3dnr_cmp(dev); + REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, 1); + } + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl); + + + return 0; +} + + +int isp_s_3dnr_motion(struct isp_ic_dev *dev) +{ + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 isp_denoise3d_motion; + u32 isp_ctrl; + + isp_denoise3d_motion = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), + isp_denoise3d_motion); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + return 0; +} + +int isp_s_3dnr_delta(struct isp_ic_dev *dev) +{ + struct isp_3dnr_context *dnr3 = &dev->dnr3; + u32 isp_denoise3d_delta_inv; + u32 isp_ctrl; + + isp_denoise3d_delta_inv = + isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), + isp_denoise3d_delta_inv); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + return 0; +} + +int isp_u_3dnr(struct isp_ic_dev *dev, struct isp_3dnr_update *dnr3_update) +{ + + u32 regVal = 0; + + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); + REG_SET_SLICE(regVal, DENOISE3D_STRENGTH, dev->dnr3.strength); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_h)); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, + dnr3_update->thr_edge_h_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_v)); + REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, + dnr3_update->thr_edge_v_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_s)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, + dnr3_update->thr_range_s_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_t)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, dnr3_update->range_t_h); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, dnr3_update->range_t_v); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, + dnr3_update->thr_range_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion)); + REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, dnr3_update->range_d); + REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, + dnr3_update->thr_motion_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal); + regVal = 0; + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv)); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, + dnr3_update->thr_delta_h_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, + dnr3_update->thr_delta_v_inv); + REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, + dnr3_update->thr_delta_t_inv); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal); + + return 0; +} + +int isp_g_3dnr(struct isp_ic_dev *dev, u32 * avg) +{ + if (!dev || !avg) { + return -EINVAL; + } + *avg = isp_read_reg(dev, REG_ADDR(isp_denoise3d_average)); + return 0; +} + +int isp_u_3dnr_strength(struct isp_ic_dev *dev) +{ + uint32_t isp_denoise3d_strength; + + isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength)); + REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dev->dnr3.strength); + isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength); + return 0; +} + + +int isp_r_3dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_3DNR_V2_V1 + return -1; +#else + u32 in_width, in_height; + u32 size, lval; + u32 miv2_sp2_bus_id; + u32 miv2_sp2_fmt; + + u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc)); + u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl)); + + //SP2_RAW_PATH_ENABLE is shadow bit, need set SP2_MI_CFG_UPD to update to shadow. + //So here config before set SP2_MI_CFG_UPD + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW_PATH_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + + in_width = isp_read_reg(dev, REG_ADDR(isp_out_h_size)); + in_height = isp_read_reg(dev, REG_ADDR(isp_out_v_size)); + + lval = (in_width * 12 + 127)/ 128; + + lval <<= 4; + + size = in_height * lval; //raw12 unaligned + //write reference frame config + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_base_ad_init), dev->dnr3.pa); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_size_init), size); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_offs_cnt_init), 0); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_height), in_height); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_size), size); + + miv2_sp2_bus_id = isp_read_reg(dev, REG_ADDR(miv2_sp2_bus_id)); + + REG_SET_SLICE(miv2_sp2_bus_id, SP2_WR_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_BURST_LEN, 2); //sp2 rd burst lenghth 16 + REG_SET_SLICE(miv2_sp2_bus_id, SP2_BUS_SW_EN, 1); + + isp_write_reg(dev, REG_ADDR(miv2_sp2_bus_id), miv2_sp2_bus_id); + + miv2_sp2_fmt = isp_read_reg(dev, REG_ADDR(miv2_sp2_fmt)); + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_ALIGNED, 0); //unaligned + + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_ALIGNED, 0); //unaligned + + isp_write_reg(dev, REG_ADDR(miv2_sp2_fmt), miv2_sp2_fmt); + + //read reference frame config + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), dev->dnr3.pa); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_lval), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_size), size); + + + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1); + + /* we successfully programmed a buffer to marvin, so we need + * to enable updateing of base and offset registers */ + miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK); + isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl); + + miv2_imsc |= SP2_DMA_RAW_READY_MASK; + isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc); + + return 0; +#endif +} +#endif diff --git a/vvcam_ry/isp/isp_compand.c b/vvcam_ry/isp/isp_compand.c new file mode 100755 index 0000000..4a9d650 --- /dev/null +++ b/vvcam_ry/isp/isp_compand.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; + +int isp_s_comp(struct isp_ic_dev *dev) +{ +#ifndef ISP_COMPAND + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_comp_context *comp = &dev->comp; + int ri, valr; + uint32_t x_data; + uint32_t y_data; + u32 isp_compand_ctrl = isp_read_reg(dev, REG_ADDR(isp_compand_ctrl)); + + pr_info("enter %s\n", __func__); + if (comp->bls.enable) { + isp_write_reg(dev, REG_ADDR(isp_compand_bls_a_fixed), comp->bls.a << (20 - comp->bls.bit_width)); + isp_write_reg(dev, REG_ADDR(isp_compand_bls_b_fixed), comp->bls.b << (20 - comp->bls.bit_width)); + isp_write_reg(dev, REG_ADDR(isp_compand_bls_c_fixed), comp->bls.c << (20 - comp->bls.bit_width)); + isp_write_reg(dev, REG_ADDR(isp_compand_bls_d_fixed), comp->bls.d << (20 - comp->bls.bit_width)); + } + + if (!comp->enable) { + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_BLS_ENABLE, 0); + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_COMPRESS_ENABLE, 0); + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_EXPAND_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_compand_ctrl), isp_compand_ctrl); + return 0; + } + + if (comp->expand.enable && comp->expand.update_curve) { + for (ri = 0; ri < 10; ri++) { + valr = (comp->expand.px[ri * 6 + 0] + (20-comp->expand.in_bit)) | + ((comp->expand.px[ri * 6 + 1] + (20-comp->expand.in_bit)) << 5) | + ((comp->expand.px[ri * 6 + 2] + (20-comp->expand.in_bit)) << 10) | + ((comp->expand.px[ri * 6 + 3] + (20-comp->expand.in_bit)) << 15) | + ((comp->expand.px[ri * 6 + 4] + (20-comp->expand.in_bit)) << 20) | + ((comp->expand.px[ri * 6 + 5] + (20-comp->expand.in_bit)) << 25); + isp_write_reg(dev, REG_ADDR(isp_compand_expand_px_0) + ri * 4, valr); + } + valr = ( comp->expand.px[60] + (20-comp->expand.in_bit)) | + ((comp->expand.px[61] + (20-comp->expand.in_bit)) << 5) | + ((comp->expand.px[62] + (20-comp->expand.in_bit)) << 10) | + ((comp->expand.px[63] + (20-comp->expand.in_bit)) << 15); + isp_write_reg(dev, REG_ADDR(isp_compand_expand_px_10), valr); + + isp_write_reg(dev, REG_ADDR(isp_compand_expand_x_addr), 0x0); + for (ri = 0; ri < 63; ri++) { + x_data = (comp->expand.x_data[ri] << (20 - comp->expand.in_bit)); + isp_write_reg(dev, REG_ADDR(isp_compand_expand_x_write_data), x_data); + } + + isp_write_reg(dev, REG_ADDR(isp_compand_expand_y_addr), 0x0); + for (ri = 0; ri < 64; ri++) { + y_data = (comp->expand.y_data[ri] << (20 - comp->expand.out_bit)); + isp_write_reg(dev, REG_ADDR(isp_compand_expand_y_write_data), y_data); + } + + } + + if (comp->compress.enable && comp->compress.update_curve) { + for (ri = 0; ri < 10; ri++) { + valr = comp->compress.px[ri * 6 + 0] | + (comp->compress.px[ri * 6 + 1] << 5) | + (comp->compress.px[ri * 6 + 2] << 10) | + (comp->compress.px[ri * 6 + 3] << 15) | + (comp->compress.px[ri * 6 + 4] << 20) | + (comp->compress.px[ri * 6 + 5] << 25); + isp_write_reg(dev, REG_ADDR(isp_compand_compress_px_0) + ri * 4, valr); + } + valr = comp->compress.px[60] | (comp->compress.px[61] << 5) | (comp->compress.px[62] << 10) | (comp->compress.px[63] << 15); + isp_write_reg(dev, REG_ADDR(isp_compand_compress_px_10), valr); + + isp_write_reg(dev, REG_ADDR(isp_compand_compress_x_addr), 0x0); + for (ri = 0; ri < 63; ri++) { + x_data = (comp->compress.x_data[ri] << (20 - comp->compress.in_bit)); + isp_write_reg(dev, REG_ADDR(isp_compand_compress_x_write_data), x_data); + } + + isp_write_reg(dev, REG_ADDR(isp_compand_compress_y_addr), 0x0); + for (ri = 0; ri < 64; ri++) { + y_data = (comp->compress.y_data[ri] << (20 - comp->compress.out_bit)); + isp_write_reg(dev, REG_ADDR(isp_compand_compress_y_write_data), y_data); + } + } + + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_BLS_ENABLE, comp->bls.enable); + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_COMPRESS_ENABLE, comp->compress.enable); + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_EXPAND_ENABLE, comp->expand.enable); + REG_SET_SLICE(isp_compand_ctrl, COMPAND_CTRL_EXPAND_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_compand_ctrl), isp_compand_ctrl); + + return 0; +#endif +} diff --git a/vvcam_ry/isp/isp_dmsc2.c b/vvcam_ry/isp/isp_dmsc2.c new file mode 100755 index 0000000..dd70484 --- /dev/null +++ b/vvcam_ry/isp/isp_dmsc2.c @@ -0,0 +1,432 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; +#ifdef ISP_DEMOSAIC2_RY +int isp_enable_dmsc(struct isp_ic_dev *dev) +{ + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + u32 isp_dmsc_size_ctrl = + isp_read_reg(dev, REG_ADDR(isp_dmsc_size_ctrl)); + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_BYPASS, 0U); + REG_SET_SLICE(isp_dmsc_size_ctrl, ISP_DMSC_IMAGE_H_SIZE, + isp_read_reg(dev, REG_ADDR(isp_acq_h_size))); + REG_SET_SLICE(isp_dmsc_size_ctrl, ISP_DMSC_IMAGE_H_BLANK, 0x039c); + isp_write_reg(dev, REG_ADDR(isp_dmsc_size_ctrl), isp_dmsc_size_ctrl); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl_shd), isp_dmsc_ctrl); + return 0; +} + +int isp_disable_dmsc(struct isp_ic_dev *dev) +{ + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + isp_dmsc_ctrl = 0; //clear fpga default bit 3 and 13 to keep the same value with cmodel. + + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_BYPASS, 1U); + + /*clear the reg default val to keep weith cmodel */ + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_fact), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_clip), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt2), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb), 0); + //isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_a), 0); + //isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_c), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y), 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; +} + +int isp_set_dmsc_intp(struct isp_ic_dev *dev) +{ + u32 isp_dmsc_intp_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_intp_thr)); + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_dmsc_intp_thr, ISP_DMSC_INTERPLATION_DIR_THR_MAX, + dev->demosaic.intp.intp_dir_thr_max); + REG_SET_SLICE(isp_dmsc_intp_thr, ISP_DMSC_INTERPLATION_DIR_THR_MIN, + dev->demosaic.intp.intp_dir_thr_min); + isp_write_reg(dev, REG_ADDR(isp_dmsc_intp_thr), isp_dmsc_intp_thr); + return 0; +} + +int isp_set_dmsc_dmoi(struct isp_ic_dev *dev) +{ + + struct isp_dmoi_context *pDemoire = &dev->demosaic.demoire; + u32 isp_dmsc_dmoi_ctrl = + isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl)); + u32 isp_dmsc_dmoi_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr)); + u32 isp_dmsc_dmoi_patn_thr = + isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_patn_thr)); + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + + pr_info("enter %s\n", __func__); + + if (!pDemoire->enable) { + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEMOIRE_ENABLE, 0U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_dmoi_ctrl, ISP_DMSC_DEMOIRE_AREA_THR, + pDemoire->demoire_area_thr); + REG_SET_SLICE(isp_dmsc_dmoi_ctrl, ISP_DMSC_DEMOIRE_SAT_SHRINK, + pDemoire->demoire_sat_shrink); + REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_R2, + pDemoire->demoire_r2); + REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_R1, + pDemoire->demoire_r1); + REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_T2_SHIFT, + pDemoire->demoire_t2_shift); + REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_T1, + pDemoire->demoire_t1); + REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_R2, + pDemoire->demoire_edge_r2); + REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_R1, + pDemoire->demoire_edge_r1); + REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT, + pDemoire->demoire_edge_t2_shift); + REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_T1, + pDemoire->demoire_edge_t1); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl), isp_dmsc_dmoi_ctrl); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr), isp_dmsc_dmoi_thr); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_patn_thr), + isp_dmsc_dmoi_patn_thr); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEMOIRE_ENABLE, 1U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; +} + +int isp_set_dmsc_sharpen(struct isp_ic_dev *dev) +{ + struct isp_shap_context *pSharpen = &dev->demosaic.sharpen; + u32 isp_dmsc_shap_fact = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_fact)); + u32 isp_dmsc_shap_clip = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_clip)); + u32 isp_dmsc_shap_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_thr)); + u32 isp_dmsc_shap_ratio = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_ratio)); + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + + pr_info("enter %s\n", __func__); + + if (!pSharpen->enable) { + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_ENBALE, 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl_shd), isp_dmsc_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_shap_fact, ISP_DMSC_SHARPEN_FACTOR_BLACK, + pSharpen->sharpen_factor_black); + REG_SET_SLICE(isp_dmsc_shap_fact, ISP_DMSC_SHARPEN_FACTOR_WHITE, + pSharpen->sharpen_factor_white); + REG_SET_SLICE(isp_dmsc_shap_clip, ISP_DMSC_SHARPEN_CLIP_BLACK, + pSharpen->sharpen_clip_black); + REG_SET_SLICE(isp_dmsc_shap_clip, ISP_DMSC_SHARPEN_CLIP_WHITE, + pSharpen->sharpen_clip_white); + REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T4_SHIFT, + pSharpen->sharpen_t4_shift); + REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T3, + pSharpen->sharpen_t3); + REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T2_SHIFT, + pSharpen->sharpen_t2_shift); + REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T1, + pSharpen->sharpen_t1); + REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R3, + pSharpen->sharpen_r3); + REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R2, + pSharpen->sharpen_r2); + REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R1, + pSharpen->sharpen_r1); + + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_fact), isp_dmsc_shap_fact); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_clip), isp_dmsc_shap_clip); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_thr), isp_dmsc_shap_thr); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_ratio), isp_dmsc_shap_ratio); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_ENBALE, 1); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + return 0; +} + +int isp_set_dmsc_gfilter(struct isp_ic_dev *dev) +{ + struct isp_gfilter_context *pgfilter = &dev->demosaic.gFilter; + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + u32 isp_dmsc_shap_filt1 = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_filt1)); + u32 isp_dmsc_shap_filt2 = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_filt2)); + pr_info("enter %s\n", __func__); + + REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_00, + pgfilter->hf_filt_00); + REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_01, + pgfilter->hf_filt_01); + REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_02, + pgfilter->hf_filt_02); + REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_10, + pgfilter->hf_filt_10); + REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_11, + pgfilter->hf_filt_11); + REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_12, + pgfilter->hf_filt_12); + REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_20, + pgfilter->hf_filt_20); + REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_21, + pgfilter->hf_filt_21); + REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_22, + pgfilter->hf_filt_22); + + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt1), isp_dmsc_shap_filt1); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt2), isp_dmsc_shap_filt2); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_SIZE, pgfilter->sharpen_size); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + return 0; +} + +int isp_set_dmsc_sharpen_line(struct isp_ic_dev *dev) +{ + struct isp_shap_line_context *sharpenLine = &dev->demosaic.sharpenLine; + + u32 isp_dmsc_shap_line_ctrl = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_line_ctrl)); + u32 isp_dmsc_shap_line_ratio = + isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_line_ratio)); + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + + pr_info("enter %s\n", __func__); + + if (!sharpenLine->enable) { + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_LINE_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_SHIFT2, + sharpenLine->sharpen_line_shift2); + REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_SHIFT1, + sharpenLine->sharpen_line_shift1); + REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_T1, + sharpenLine->sharpen_line_t1); + REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_STRENGTH, + sharpenLine->sharpen_line_strength); + REG_SET_SLICE(isp_dmsc_shap_line_ratio, ISP_DMSC_SHARPEN_LINE_R2, + sharpenLine->sharpen_line_r2); + REG_SET_SLICE(isp_dmsc_shap_line_ratio, ISP_DMSC_SHARPEN_LINE_R1, + sharpenLine->sharpen_line_r1); + + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_line_ctrl), + isp_dmsc_shap_line_ctrl); + isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_line_ratio), + isp_dmsc_shap_line_ratio); + + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_LINE_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + return 0; +} + +int isp_set_dmsc_cac(struct isp_ic_dev *dev) +{ + struct isp_cac_context *cac = &dev->cac; + u32 val = 0; + u32 isp_dmsc_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl)); + + pr_info("enter %s\n", __func__); + + if (!cac->enable) { + REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_CAC_EN, 0); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl), + isp_dmsc_cac_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode); + REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_count_start), + cac->hstart | (cac->vstart << 16)); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_a), cac->ar | (cac->ab << 16)); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_b), cac->br | (cac->bb << 16)); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_c), cac->cr | (cac->cb << 16)); + + REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns); + REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_x_norm), val); + val = 0; + REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns); + REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_y_norm), val); + REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_CAC_EN, 1); + isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl), isp_dmsc_cac_ctrl); + + return 0; +} + +int isp_set_dmsc_depurple(struct isp_ic_dev *dev) +{ + struct isp_depurple_context *depurple = &dev->demosaic.depurple; + u32 isp_dmsc_dpul_ctrl = + isp_read_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl)); + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + + pr_info("enter %s\n", __func__); + if (!depurple->enable) { + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEPURPLE_ENABLE, 0U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_RED_SAT, depurple->red_sat); + REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_BLUE_SAT, depurple->blue_sat); + REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_SAT_SHRINK, + depurple->depurple_sat_shrink); + REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_THR, + depurple->depurple_thr); + isp_write_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl), isp_dmsc_dpul_ctrl); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEPURPLE_ENABLE, 1U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + return 0; +} + +int isp_set_dmsc_skin(struct isp_ic_dev *dev) +{ + struct isp_skin_context *skin = &dev->demosaic.skin; + u32 isp_dmsc_skin_thr_cb = + isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb)); + u32 isp_dmsc_skin_thr_cr = + isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr)); + u32 isp_dmsc_skin_thr_y = + isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y)); + + u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + + pr_info("enter %s\n", __func__); + if (!skin->enable) { + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SKIN_ENABLE, 0U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + return 0; + } + + REG_SET_SLICE(isp_dmsc_skin_thr_cb, ISP_DMSC_SKIN_CB_THR_MAX_2047, + skin->cb_thr_max_2047); + REG_SET_SLICE(isp_dmsc_skin_thr_cb, ISP_DMSC_SKIN_CB_THR_MIN_2047, + skin->cb_thr_min_2047); + REG_SET_SLICE(isp_dmsc_skin_thr_cr, ISP_DMSC_SKIN_CR_THR_MAX_2047, + skin->cr_thr_max_2047); + REG_SET_SLICE(isp_dmsc_skin_thr_cr, ISP_DMSC_SKIN_CR_THR_MIN_2047, + skin->cr_thr_min_2047); + REG_SET_SLICE(isp_dmsc_skin_thr_y, ISP_DMSC_SKIN_Y_THR_MAX, + skin->y_thr_max_2047); + REG_SET_SLICE(isp_dmsc_skin_thr_y, ISP_DMSC_SKIN_Y_THR_MIN, + skin->y_thr_min_2047); + + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb), + isp_dmsc_skin_thr_cb); + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr), + isp_dmsc_skin_thr_cr); + isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y), isp_dmsc_skin_thr_y); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SKIN_ENABLE, 1U); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + return 0; +} + +int isp_s_dmsc(struct isp_ic_dev *dev) +{ + u32 isp_dmsc_ctrl; + /*Clear the cmodel register default value to match the fpga default value */ + isp_disable_dmsc(dev); + + isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl)); + pr_info("enter %s\n", __func__); + if (!dev->demosaic.enable) { + isp_disable_dmsc(dev); + return 0; + } + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_THR, + dev->demosaic.demosaic_thr); + REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DENOISE_STRENGTH, + dev->demosaic.denoise_stren); + isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl); + + isp_set_dmsc_intp(dev); + isp_set_dmsc_dmoi(dev); + isp_set_dmsc_skin(dev); + isp_enable_dmsc(dev); + isp_set_dmsc_depurple(dev); + isp_set_dmsc_sharpen_line(dev); + isp_set_dmsc_sharpen(dev); + isp_set_dmsc_gfilter(dev); + + return 0; +} + +#endif diff --git a/vvcam_ry/isp/isp_dpf.c b/vvcam_ry/isp/isp_dpf.c new file mode 100755 index 0000000..6cd44a9 --- /dev/null +++ b/vvcam_ry/isp/isp_dpf.c @@ -0,0 +1,193 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#else +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; + +int isp_s_dpf(struct isp_ic_dev *dev) +{ + struct isp_dpf_context *dpf = &dev->dpf; + u32 value; + int i = 0; + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + u32 isp_dpf_mode = isp_read_reg(dev, REG_ADDR(isp_dpf_mode)); + + //pr_info("enter %s\n", __func__); + + if (!dpf->enable) { + isp_write_reg(dev, REG_ADDR(isp_dpf_mode), + isp_dpf_mode & ~MRV_DPF_DPF_ENABLE_MASK); + return 0; + } + + isp_dpf_mode &= + (MRV_DPF_DPF_ENABLE_MASK | MRV_DPF_NLL_SEGMENTATION_MASK); + + switch (dpf->gain_usage) { + case IC_DPF_GAIN_USAGE_DISABLED: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 0); + break; + case IC_DPF_GAIN_USAGE_NF_GAINS: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 1); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1); + break; + case IC_DPF_GAIN_USAGE_LSC_GAINS: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 0); + break; + case IC_DPF_GAIN_USAGE_NF_LSC_GAINS: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 1); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1); + break; + case IC_DPF_GAIN_USAGE_AWB_GAINS: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1); + break; + case IC_DPF_GAIN_USAGE_AWB_LSC_GAINS: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1); + break; + default: + pr_err("%s: unsupported gain usage\n", __func__); + break; + } + + switch (dpf->filter_type) { + case IC_DPF_RB_FILTERSIZE_13x9: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_RB_FILTER_SIZE, 0U); + break; + case IC_DPF_RB_FILTERSIZE_9x9: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_RB_FILTER_SIZE, 1U); + break; + default: + pr_err + ("%s: unsupported filter kernel size for red/blue pixel\n", + __func__); + break; + } + + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_R_FILTER_OFF, dpf->filter_r_off); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_GR_FILTER_OFF, dpf->filter_gr_off); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_GB_FILTER_OFF, dpf->filter_gb_off); + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_B_FILTER_OFF, dpf->filter_b_off); + value = 0; + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G1, dpf->weight_g[0]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G2, dpf->weight_g[1]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G3, dpf->weight_g[2]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G4, dpf->weight_g[3]); + isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_g_1_4), value); + value = 0; + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G5, dpf->weight_g[4]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G6, dpf->weight_g[5]); + isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_g_5_6), value); + value = 0; + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB1, dpf->weight_rb[0]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB2, dpf->weight_rb[1]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB3, dpf->weight_rb[2]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB4, dpf->weight_rb[3]); + isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_rb_1_4), value); + value = 0; + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB5, dpf->weight_rb[4]); + REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB6, dpf->weight_rb[5]); + isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_rb_5_6), value); + isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_r), dpf->nf_gain_r); + isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_gr), dpf->nf_gain_gr); + isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_gb), dpf->nf_gain_gb); + isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_b), dpf->nf_gain_b); + isp_write_reg(dev, REG_ADDR(isp_dpf_strength_r), + (MRV_DPF_INV_WEIGHT_R_MASK & dpf->strength_r)); + isp_write_reg(dev, REG_ADDR(isp_dpf_strength_g), + (MRV_DPF_INV_WEIGHT_G_MASK & dpf->strength_g)); + isp_write_reg(dev, REG_ADDR(isp_dpf_strength_b), + (MRV_DPF_INV_WEIGHT_B_MASK & dpf->strength_b)); + + for (i = 0; i < 17; i++) { + if (dpf->denoise_talbe[i] <= MRV_DPF_NLL_COEFF_N_MASK) { + isp_write_reg(dev, + REG_ADDR(nlf_lookup_table_block_arr[i]), + dpf->denoise_talbe[i]); + } + } + + switch (dpf->x_scale) { + case IC_NLL_SCALE_LINEAR: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_NLL_SEGMENTATION, 0); + break; + case IC_NLL_SCALE_LOGARITHMIC: + REG_SET_SLICE(isp_dpf_mode, MRV_DPF_NLL_SEGMENTATION, 1); + break; + default: + break; + } + + isp_write_reg(dev, REG_ADDR(isp_dpf_mode), isp_dpf_mode); + isp_write_reg(dev, REG_ADDR(isp_dpf_mode), + isp_dpf_mode | MRV_DPF_DPF_ENABLE_MASK); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + return 0; +} diff --git a/vvcam_ry/isp/isp_gcmono.c b/vvcam_ry/isp/isp_gcmono.c new file mode 100755 index 0000000..3ab59cf --- /dev/null +++ b/vvcam_ry/isp/isp_gcmono.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#else +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; + +int isp_enable_gcmono(struct isp_ic_dev *dev) +{ +#ifndef ISP_GCMONO + pr_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_gcmono_ctrl = isp_read_reg(dev, REG_ADDR(isp_gcmono_ctrl)); + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_gcmono_ctrl, ISP_GCMONO_CFG_DONE, 1); + REG_SET_SLICE(isp_gcmono_ctrl, ISP_GCMONO_SWITCH, + ISP_GCMONO_SWITCH_ENABLE); + isp_write_reg(dev, REG_ADDR(isp_gcmono_ctrl), isp_gcmono_ctrl); + REG_SET_SLICE(isp_ctrl, ISP_GCMONO_MODE, dev->gcmono.mode); + REG_SET_SLICE(isp_ctrl, ISP_GCMONO_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + dev->gcmono.enable = true; + return 0; +#endif +} + +int isp_disable_gcmono(struct isp_ic_dev *dev) +{ +#ifndef ISP_GCMONO + pr_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_gcmono_ctrl = isp_read_reg(dev, REG_ADDR(isp_gcmono_ctrl)); + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_gcmono_ctrl, ISP_GCMONO_SWITCH, + ISP_GCMONO_SWITCH_DISABLE); + isp_write_reg(dev, REG_ADDR(isp_gcmono_ctrl), isp_gcmono_ctrl); + REG_SET_SLICE(isp_ctrl, ISP_GCMONO_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + dev->gcmono.enable = false; + return 0; +#endif +} + +#ifdef ISP_GCMONO +static int isp_s_gcmonopx(struct isp_ic_dev *dev, struct isp_gcmono_data *data) +{ + u32 isp_gc_px_reg = REG_ADDR(isp_gcmono_px_0); + u32 *p_table = NULL; + int i; + u32 gc_px_data = 0; + + pr_info("enter %s\n", __func__); + p_table = (u32 *)&data->px; + for (i = 0; i < 64; i++) { + gc_px_data |= (*(p_table + i) << (i % 6 * 5)); + if (i % 6 == 5 || i == 63) { + isp_write_reg(dev, isp_gc_px_reg, gc_px_data); + isp_gc_px_reg += 4; + gc_px_data = 0; + } + } + return 0; +} +#endif + +#ifdef ISP_GCMONO +static int isp_s_gcmonoWriteData(struct isp_ic_dev *dev, u32 *tblX, u32 *tblY) +{ + u32 isp_gc_y_data, isp_gc_x_data; + // u32 *p_table = NULL; + int i; + // u32 gc_px_data = 0; + + pr_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(isp_gcmono_y_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_gcmono_x_addr), 0); + for (i = 0; i < 64; i++) { + isp_gc_y_data = *(tblY + i); + isp_write_reg(dev, REG_ADDR(isp_gcmono_y_write_data), + isp_gc_y_data); + } + for (i = 0; i < 63; i++) { + isp_gc_x_data = *(tblX + i); + isp_write_reg(dev, REG_ADDR(isp_gcmono_x_write_data), + isp_gc_x_data); + } + return 0; +} +#endif + +int isp_s_gcmono(struct isp_ic_dev *dev, struct isp_gcmono_data *data) +{ +#ifndef ISP_GCMONO + pr_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_gcmono_ctrl = isp_read_reg(dev, REG_ADDR(isp_gcmono_ctrl)); + u32 isp_gc_para_base = 0; + u8 *p_table = NULL; + int i; + + pr_info("enter %s\n", __func__); + REG_SET_SLICE(isp_gcmono_ctrl, ISP_GCMONO_SWITCH, + ISP_GCMONO_SWITCH_DISABLE); + REG_SET_SLICE(isp_gcmono_ctrl, ISP_GCMONO_CFG_DONE, + ISP_GCMONO_CFG_DONE_SET_CURVE); + isp_write_reg(dev, REG_ADDR(isp_gcmono_ctrl), isp_gcmono_ctrl); + p_table = (u8 *)&data->basePara; + for (i = 0; i < 1024; i++) { + isp_gc_para_base |= (*(p_table + i) << (i % 4 * 8)); + if (i % 4 == 3) { + isp_write_reg(dev, REG_ADDR(isp_gcmono_para_base), + isp_gc_para_base); + isp_gc_para_base = 0; + } + } + isp_s_gcmonopx(dev, data); + isp_s_gcmonoWriteData(dev, data->dataX, data->dataY); + if (dev->gcmono.enable) { + isp_enable_gcmono(dev); + } + return 0; +#endif +} diff --git a/vvcam_ry/isp/isp_hdr.c b/vvcam_ry/isp/isp_hdr.c new file mode 100755 index 0000000..fd6a733 --- /dev/null +++ b/vvcam_ry/isp/isp_hdr.c @@ -0,0 +1,259 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; + +int isp_s_hdr(struct isp_ic_dev *dev) +{ + struct isp_hdr_context *hdr = &dev->hdr; + u32 isp_stitching_ctrl = + isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl)); + u32 val; + int i; + + pr_info("enter %s\n", __func__); + + val = 0; +#if 0 + REG_SET_SLICE(val, STITCHING_FRAME_WIDTH, hdr->width); + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_FRAME_HEIGHT, hdr->height); + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_L_BIT_DEPTH, hdr->l_bit_dep); + REG_SET_SLICE(val, STITCHING_S_BIT_DEPTH, hdr->s_bit_dep); + REG_SET_SLICE(val, STITCHING_VS_BIT_DEPTH, hdr->vs_bit_dep); + REG_SET_SLICE(val, STITCHING_LS_BIT_DEPTH, hdr->ls_bit_dep); + isp_write_reg(dev, REG_ADDR(isp_stitching_exposure_bit), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_COLOR_WEIGHT_0, hdr->weight0); + REG_SET_SLICE(val, STITCHING_COLOR_WEIGHT_1, hdr->weight1); + REG_SET_SLICE(val, STITCHING_COLOR_WEIGHT_2, hdr->weight2); + isp_write_reg(dev, REG_ADDR(isp_stitching_color_weight), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_TRANS_RANGE_START_LINEAR, + hdr->start_linear); + REG_SET_SLICE(val, STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR, + hdr->norm_factor_mul_linear); + isp_write_reg(dev, REG_ADDR(isp_stitching_trans_range_linear), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_TRANS_RANGE_START_NONLINEAR, + hdr->start_nonlinear); + REG_SET_SLICE(val, STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR, + hdr->norm_factor_mul_nonlinear); + isp_write_reg(dev, REG_ADDR(isp_stitching_trans_range_nonlinear), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_DUMMY_HBLANK, hdr->dummy_hblank); + REG_SET_SLICE(val, STITCHING_OUT_HBLANK, hdr->out_hblank); + isp_write_reg(dev, REG_ADDR(isp_stitching_out_hblank), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_OUT_VBLANK, hdr->out_vblank); + isp_write_reg(dev, REG_ADDR(isp_stitching_out_vblank), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_LONG_EXPOSURE_TIME, hdr->long_exp); + isp_write_reg(dev, REG_ADDR(isp_stitching_long_exposure), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_SHORT_EXPOSURE_TIME, hdr->short_exp); + isp_write_reg(dev, REG_ADDR(isp_stitching_short_exposure), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_VERY_SHORT_EXPOSURE_TIME, + hdr->very_short_exp); + isp_write_reg(dev, REG_ADDR(isp_stitching_very_short_exposure), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_LONG_EXPOSURE_TIME, hdr->long_exp); + isp_write_reg(dev, REG_ADDR(isp_stitching_long_exposure), val); +#endif + val = 0; + REG_SET_SLICE(val, STITCHING_RATIO_LONG_SHORT_1, hdr->ls1); + REG_SET_SLICE(val, STITCHING_RATIO_LONG_SHORT_0, hdr->ls0); + isp_write_reg(dev, REG_ADDR(isp_stitching_ratio_ls), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_RATIO_VERYSHORT_SHORT_1, hdr->vs1); + REG_SET_SLICE(val, STITCHING_RATIO_VERYSHORT_SHORT_0, hdr->vs0); + isp_write_reg(dev, REG_ADDR(isp_stitching_ratio_vs), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_SHORT_EXTEND_BIT, hdr->ext_bit); + REG_SET_SLICE(val, STITCHING_VERYSHORT_VALID_THRESH, hdr->valid_thresh); + REG_SET_SLICE(val, STITCHING_VERYSHORT_OFFSET_VAL, hdr->offset_val); + isp_write_reg(dev, REG_ADDR(isp_stitching_sat_level), val); + + for (i = 0; i < 5; i++) { + val = 0; + REG_SET_SLICE(val, STITCHING_COMPRESS_LUT_2, + hdr->compress_lut[i * 3 + 2]); + REG_SET_SLICE(val, STITCHING_COMPRESS_LUT_1, + hdr->compress_lut[i * 3 + 1]); + REG_SET_SLICE(val, STITCHING_COMPRESS_LUT_0, + hdr->compress_lut[i * 3]); + isp_write_reg(dev, + REG_ADDR(isp_stitching_compress_lut_0) + i * 4, + val); + } + val = 0; + REG_SET_SLICE(val, STITCHING_LONG_SAT_THRESH, hdr->sat_thresh); + REG_SET_SLICE(val, STITCHING_LONG_SAT_COMBINE_WEIGHT, + hdr->combine_weight); + isp_write_reg(dev, REG_ADDR(isp_stitching_long_sat_params), val); + + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINE_ENABLE_BIT, 1); + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_CFG_UPD, 1); + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINATION_MODE, 1); + isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), 0x4c0221); + + return 0; +} + +int isp_s_hdr_wb(struct isp_ic_dev *dev) +{ + struct isp_hdr_context *hdr = &dev->hdr; + u32 val = 0; + u32 isp_stitching_ctrl = + isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl)); + + pr_info("enter %s\n", __func__); + REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_GR, hdr->gr); + REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_GB, hdr->gb); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp0_awb_gain_g), val); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp1_awb_gain_g), val); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp2_awb_gain_g), val); + + val = 0; + REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_R, hdr->r); + REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_B, hdr->b); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp0_awb_gain_rb), val); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp1_awb_gain_rb), val); + isp_write_reg(dev, REG_ADDR(isp_stitching_exp2_awb_gain_rb), val); + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), 0x4c0221); + + return 0; +} + +int isp_s_hdr_bls(struct isp_ic_dev *dev) +{ + struct isp_hdr_context *hdr = &dev->hdr; + u32 isp_stitching_ctrl = + isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl)); + u32 val = 0; + int i; + + pr_info("enter %s\n", __func__); + + for (i = 0; i < 12; i++) { + val = 0; + REG_SET_SLICE(val, STITCHING_BLS_EXP_0_A, hdr->bls[i % 4]); + isp_write_reg(dev, REG_ADDR(isp_stitching_bls_exp_0_a) + i * 4, + val); + } + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), 0x4c0221); + + return 0; +} + +int isp_enable_hdr(struct isp_ic_dev *dev) +{ + u32 addr, isp_stitching_ctrl; + u32 dpcl; + int val = 0; + + pr_info("enter %s\n", __func__); + addr = REG_ADDR(isp_stitching_ctrl); + isp_stitching_ctrl = isp_read_reg(dev, addr); + REG_SET_SLICE(val, STITCHING_FRAME_WIDTH, dev->ctx.acqWindow.width); + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), val); + val = 0; + REG_SET_SLICE(val, STITCHING_FRAME_HEIGHT, dev->ctx.acqWindow.height); + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), val); + + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINE_ENABLE_BIT, 0); + isp_write_reg(dev, addr, isp_stitching_ctrl); + dpcl = isp_read_reg(dev, REG_ADDR(vi_dpcl)); + REG_SET_SLICE(dpcl, MRV_IF_SELECT, MRV_IF_SELECT_HDR); + isp_write_reg(dev, REG_ADDR(vi_dpcl), dpcl); + dev->mux.if_select = MRV_IF_SELECT_HDR; + return 0; +} + +int isp_disable_hdr(struct isp_ic_dev *dev) +{ + u32 addr, isp_stitching_ctrl = 0; + + pr_info("enter %s\n", __func__); + addr = REG_ADDR(isp_stitching_ctrl); + isp_stitching_ctrl = isp_read_reg(dev, addr); + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINE_ENABLE_BIT, 1); + isp_write_reg(dev, addr, isp_stitching_ctrl); + return 0; +} diff --git a/vvcam_ry/isp/isp_ioctl.c b/vvcam_ry/isp/isp_ioctl.c new file mode 100755 index 0000000..ebc935f --- /dev/null +++ b/vvcam_ry/isp/isp_ioctl.c @@ -0,0 +1,3647 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +/* process public and sample isp command. for complex modules, need new files.*/ +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" +#include "isp_wdr.h" +#include +#include + +#ifdef __KERNEL__ +#include +#include +#endif + +#ifdef CONFIG_VSI_ISP_DEBUG +#define isp_info(fmt, ...) pr_info(fmt, ##__VA_ARGS__) +#define isp_debug(fmt, ...) pr_debug(fmt, ##__VA_ARGS__) +#define isp_err(fmt, ...) pr_err(fmt, ##__VA_ARGS__) +#else +#define isp_info(fmt, ...) +#define isp_debug(fmt, ...) +#define isp_err(fmt, ...) pr_err(fmt, ##__VA_ARGS__) +#endif + +volatile MrvAllRegister_t *all_regs = NULL; + +#ifndef __KERNEL__ +#define ISP_REG_SIZE 0x10000 +static HalHandle_t hal_handle; + +void isp_ic_set_hal(HalHandle_t hal) +{ + hal_handle = hal; +} + +void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val) +{ + //pr_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val); + if (offset >= ISP_REG_SIZE) + return; + HalWriteReg(hal_handle, offset, val); +} + +u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset) +{ + if (offset >= ISP_REG_SIZE) + return 0; + return HalReadReg(hal_handle, offset); +} + +long isp_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); + return 0; +} +#else +void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val) +{ +// isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val); + if (offset >= ISP_REG_SIZE) + return; + __raw_writel(val, dev->base + offset); + /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/ +} + +u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset) +{ + u32 val = 0; + + if (offset >= ISP_REG_SIZE) + return 0; + val = __raw_readl(dev->base + offset); + /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/ + return val; +} +#endif + +int isp_reset(struct isp_ic_dev *dev) +{ + isp_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(vi_ircl), 0xFFFFFFBF); +#ifdef __KERNEL__ + mdelay(2); +#endif + isp_write_reg(dev, REG_ADDR(vi_ircl), 0x0); + /*clear mis array*/ + isp_write_reg(dev, REG_ADDR(isp_ctrl), 0x0); //clear isp_ctrl disable_isp_clk + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_enable_tpg(struct isp_ic_dev *dev) +{ + u32 addr, isp_tpg_ctrl; + + isp_info("enter %s\n", __func__); + addr = REG_ADDR(isp_tpg_ctrl); + isp_tpg_ctrl = isp_read_reg(dev, addr); + //REG_SET_SLICE(isp_tpg_ctrl, TPG_FRAME_NUM, 1);//set tpg frame num + REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 1); + isp_write_reg(dev, addr, isp_tpg_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_disable_tpg(struct isp_ic_dev *dev) +{ + u32 addr, isp_tpg_ctrl; + + isp_info("enter %s\n", __func__); + addr = REG_ADDR(isp_tpg_ctrl); + isp_tpg_ctrl = isp_read_reg(dev, addr); + REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 0); + isp_write_reg(dev, addr, isp_tpg_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_enable_bls(struct isp_ic_dev *dev) +{ +#ifndef ISP_BLS + //isp_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE, + MRV_BLS_BLS_ENABLE_PROCESS); + isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl); + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_disable_bls(struct isp_ic_dev *dev) +{ +#ifndef ISP_BLS + //isp_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE, + MRV_BLS_BLS_ENABLE_BYPASS); + isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl); + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_enable(struct isp_ic_dev *dev) +{ + u32 isp_ctrl, isp_imsc; + + isp_info("enter %s\n", __func__); + isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK); + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + /*Set lsc tbl after isp enable*/ + if (dev->update_lsc_tbl) { + isp_s_lsc_tbl(dev); + dev->update_lsc_tbl = false; + } + + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_disable(struct isp_ic_dev *dev) +{ + u32 isp_ctrl; +/* #ifndef ENABLE_IRQ + u32 isp_imsc; + #endif*/ + + isp_info("enter %s\n", __func__); + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); +/* #ifndef ENABLE_IRQ + isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK); + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + #endif*/ + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_write_reg(dev, REG_ADDR(isp_isr), MRV_ISP_ISR_ISP_OFF_MASK); + isp_info("exit %s\n", __func__); + return 0; +} + +bool is_isp_enable(struct isp_ic_dev *dev) +{ +// isp_info("enter %s\n", __func__); + return isp_read_reg(dev, REG_ADDR(isp_ctrl)) & 0x01; +} + +int isp_enable_lsc(struct isp_ic_dev *dev) +{ + + u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl)); + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 1U); + isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl); + + { + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_disable_lsc(struct isp_ic_dev *dev) +{ + u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 0U); + isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl); + + { + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } + isp_info("exit %s\n", __func__); + return 0; +} + +#if defined(__KERNEL__) && defined(ISP8000NANO_V1802) +static int isp_gpr_input_control(struct isp_ic_dev *dev) +{ + struct isp_context isp_ctx = *(&dev->ctx); + unsigned int fmt_offset = 3; + unsigned int isp_dewarp_control_val; + + if (dev->mix_gpr == NULL) + return -ENOMEM; + + if (dev->id == 0) + fmt_offset = 3; + else + fmt_offset = 13; + + regmap_read(dev->mix_gpr, 0x138, &isp_dewarp_control_val); + if (isp_dewarp_control_val == 0) + isp_dewarp_control_val = 0x8d8360; + + switch (isp_ctx.input_selection) { + case MRV_ISP_INPUT_SELECTION_12EXT: + isp_dewarp_control_val &= ~(0x3f << fmt_offset); + isp_dewarp_control_val |= (0x2c << fmt_offset); + break; + case MRV_ISP_INPUT_SELECTION_10ZERO: + case MRV_ISP_INPUT_SELECTION_10MSB: + isp_dewarp_control_val &= ~(0x3f << fmt_offset); + isp_dewarp_control_val |= (0x2b << fmt_offset); + break; + case MRV_ISP_INPUT_SELECTION_8ZERO: + case MRV_ISP_INPUT_SELECTION_8MSB: + isp_dewarp_control_val &= ~(0x3f << fmt_offset); + isp_dewarp_control_val |= (0x2a << fmt_offset); + break; + default: + return 0; + } + regmap_write(dev->mix_gpr, 0x138, isp_dewarp_control_val); + return 0; +} +#endif + +int isp_s_input(struct isp_ic_dev *dev) +{ + struct isp_context isp_ctx = *(&dev->ctx); + u32 isp_ctrl, isp_acq_prop, isp_demosaic; +#ifdef ISP_HDR_STITCH_RY + u32 isp_stitching_ctrl; +#endif //ISP_HDR_STITCH_RY + isp_info("enter %s\n", __func__); + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_MODE, isp_ctx.mode); + isp_acq_prop = isp_read_reg(dev, REG_ADDR(isp_acq_prop)); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_SAMPLE_EDGE, isp_ctx.sample_edge); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_HSYNC_POL, + isp_ctx.hSyncLowPolarity); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_VSYNC_POL, + isp_ctx.vSyncLowPolarity); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_BAYER_PAT, isp_ctx.bayer_pattern); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_CONV_422, isp_ctx.sub_sampling); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_CCIR_SEQ, isp_ctx.seq_ccir); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_FIELD_SELECTION, + isp_ctx.field_selection); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_INPUT_SELECTION, + isp_ctx.input_selection); + REG_SET_SLICE(isp_acq_prop, MRV_ISP_LATENCY_FIFO_SELECTION, + isp_ctx.latency_fifo); + + isp_write_reg(dev, REG_ADDR(isp_acq_prop), isp_acq_prop); + isp_write_reg(dev, REG_ADDR(isp_acq_h_offs), isp_ctx.acqWindow.x); + isp_write_reg(dev, REG_ADDR(isp_acq_v_offs), isp_ctx.acqWindow.y); + isp_write_reg(dev, REG_ADDR(isp_acq_h_size), isp_ctx.acqWindow.width); + isp_write_reg(dev, REG_ADDR(isp_acq_v_size), isp_ctx.acqWindow.height); +#ifdef ISP_MI_HDR_RY + isp_write_reg(dev, REG_ADDR(isp_hdr_interval), 0x113); + isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_blank), 0x30); + isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_blank), 0x30); + isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_size), isp_ctx.acqWindow.width); + isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_size), isp_ctx.acqWindow.height); +#endif + + isp_write_reg(dev, REG_ADDR(isp_out_h_offs), + (isp_ctx.ofWindow.x & MRV_ISP_ISP_OUT_H_OFFS_MASK)); + isp_write_reg(dev, REG_ADDR(isp_out_v_offs), + (isp_ctx.ofWindow.y & MRV_ISP_ISP_OUT_V_OFFS_MASK)); + isp_write_reg(dev, REG_ADDR(isp_out_h_size), + (isp_ctx.ofWindow.width & MRV_ISP_ISP_OUT_H_SIZE_MASK)); + isp_write_reg(dev, REG_ADDR(isp_out_v_size), + (isp_ctx.ofWindow.height & MRV_ISP_ISP_OUT_V_SIZE_MASK)); + + isp_write_reg(dev, REG_ADDR(isp_is_h_offs), + (isp_ctx.isWindow.x & MRV_IS_IS_H_OFFS_MASK)); + isp_write_reg(dev, REG_ADDR(isp_is_v_offs), + (isp_ctx.isWindow.y & MRV_IS_IS_V_OFFS_MASK)); + isp_write_reg(dev, REG_ADDR(isp_is_h_size), + (isp_ctx.isWindow.width & MRV_IS_IS_H_SIZE_MASK)); + isp_write_reg(dev, REG_ADDR(isp_is_v_size), + (isp_ctx.isWindow.height & MRV_IS_IS_V_SIZE_MASK)); + + isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic)); + REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS, + isp_ctx.bypass_mode); + REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH, + isp_ctx.demosaic_threshold); + isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic); + +#ifdef ISP_HDR_STITCH + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), isp_ctx.acqWindow.width); + isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), isp_ctx.acqWindow.height); + isp_write_reg(dev, REG_ADDR(isp_stitching_hdr_mode), isp_ctx.stitching_mode); + isp_stitching_ctrl = isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl)); + REG_SET_SLICE(isp_stitching_ctrl, STITCHING_BAYER_PATTERN, isp_ctx.bayer_pattern); + isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), isp_stitching_ctrl); +#endif + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); +#if defined(__KERNEL__) && defined(ISP8000NANO_V1802) + isp_gpr_input_control(dev); +#endif + + return 0; +} + +int isp_s_digital_gain(struct isp_ic_dev *dev) +{ + struct isp_digital_gain_cxt dgain = *(&dev->dgain); + u32 isp_dgain_rb = isp_read_reg(dev, REG_ADDR(isp_dgain_rb)); + u32 isp_dgain_g = isp_read_reg(dev, REG_ADDR(isp_dgain_g)); + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + if (!dgain.enable) { + isp_err("%s, Disable isp digital gain", __func__); + REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 0U); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + return 0; + } + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_R, dgain.gain_r); + REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_B, dgain.gain_b); + + REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GR, dgain.gain_gr); + REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GB, dgain.gain_gb); + REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 1U); + + isp_write_reg(dev, REG_ADDR(isp_dgain_rb), isp_dgain_rb); + isp_write_reg(dev, REG_ADDR(isp_dgain_g), isp_dgain_g); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_demosaic(struct isp_ic_dev *dev) +{ + struct isp_context isp_ctx = *(&dev->ctx); + u32 isp_demosaic; + isp_info("enter %s\n", __func__); + isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic)); + REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS, + isp_ctx.bypass_mode); + REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH, + isp_ctx.demosaic_threshold); + isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic); + isp_info("exit %s\n", __func__); + return 0;; +} + +int isp_s_tpg(struct isp_ic_dev *dev) +{ + struct isp_tpg_context tpg = *(&dev->tpg); + u32 addr, regVal; + + isp_info("enter %s\n", __func__); + addr = REG_ADDR(isp_tpg_ctrl); + regVal = isp_read_reg(dev, addr); + REG_SET_SLICE(regVal, TPG_IMG_NUM, tpg.image_type); + REG_SET_SLICE(regVal, TPG_CFA_PAT, tpg.bayer_pattern); + REG_SET_SLICE(regVal, TPG_COLOR_DEPTH, tpg.color_depth); + REG_SET_SLICE(regVal, TPG_RESOLUTION, tpg.resolution); + REG_SET_SLICE(regVal, TPG_FRAME_NUM, tpg.frame_num); + isp_write_reg(dev, addr, regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_PIX_GAP_IN, tpg.pixleGap); + REG_SET_SLICE(regVal, TPG_LINE_GAP_IN, tpg.lineGap); + isp_write_reg(dev, REG_ADDR(isp_tpg_gap_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_PIX_GAP_STD_IN, tpg.gapStandard); + isp_write_reg(dev, REG_ADDR(isp_tpg_gap_std_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_RANDOM_SEED, tpg.randomSeed); + isp_write_reg(dev, REG_ADDR(isp_tpg_random_seed), regVal); + REG_SET_SLICE(regVal, TPG_HTOTAL_IN, tpg.user_mode_h.total); + REG_SET_SLICE(regVal, TPG_VTOTAL_IN, tpg.user_mode_v.total); + isp_write_reg(dev, REG_ADDR(isp_tpg_total_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_HACT_IN, tpg.user_mode_h.act); + REG_SET_SLICE(regVal, TPG_VACT_IN, tpg.user_mode_v.act); + isp_write_reg(dev, REG_ADDR(isp_tpg_act_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_FP_H_IN, tpg.user_mode_h.fp); + REG_SET_SLICE(regVal, TPG_FP_V_IN, tpg.user_mode_v.fp); + isp_write_reg(dev, REG_ADDR(isp_tpg_fp_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_BP_H_IN, tpg.user_mode_h.bp); + REG_SET_SLICE(regVal, TPG_BP_V_IN, tpg.user_mode_v.bp); + isp_write_reg(dev, REG_ADDR(isp_tpg_bp_in), regVal); + regVal = 0; + REG_SET_SLICE(regVal, TPG_HS_W_IN, tpg.user_mode_h.sync); + REG_SET_SLICE(regVal, TPG_VS_W_IN, tpg.user_mode_v.sync); + isp_write_reg(dev, REG_ADDR(isp_tpg_w_in), regVal); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_mcm_wr(struct isp_ic_dev *dev) +{ + struct isp_mcm_context *mcm = &dev->mcm; + u32 mcm_ctrl; + u32 mcm_hsync_preample_ext; + u32 mcm_size, mcm_rd_fmt; + int i; + isp_info("enter %s\n", __func__); + + mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl)); + mcm_rd_fmt = isp_read_reg(dev, REG_ADDR(mcm_rd_cfg)); + mcm_hsync_preample_ext = isp_read_reg(dev, REG_ADDR(mcm_hsync_preample_ext)); + + REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_SWITCH, mcm->bypass_switch); + REG_SET_SLICE(mcm_ctrl, MCM_WR0_FMT, mcm->wr_fmt[MCM_INDEX_WR0]); + REG_SET_SLICE(mcm_ctrl, MCM_WR1_FMT, mcm->wr_fmt[MCM_INDEX_WR1]); + REG_SET_SLICE(mcm_ctrl, MCM_G2_WR0_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR0]); + REG_SET_SLICE(mcm_ctrl, MCM_G2_WR1_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR1]); + REG_SET_SLICE(mcm_ctrl, MCM_SENSOR_MEM_BYPASS, mcm->sensor_mem_bypass); + + REG_SET_SLICE(mcm_rd_fmt, MCM_RD_FMT, mcm->rd_fmt); + REG_SET_SLICE(mcm_hsync_preample_ext, MCM_HSYNC_PREAMPLE_EXT, mcm->hsync_rpeample_ext); + + for (i = MCM_INDEX_WR0 ; i < MCM_INDEX_WR_MAX; i++){ + REG_SET_SLICE(mcm_size, MCM_HEIGHT0, mcm->height[i]); + REG_SET_SLICE(mcm_size, MCM_WIDTH0, mcm->width[i]); + isp_write_reg(dev, REG_ADDR(mcm_size0) + i *4, mcm_size); + } + isp_write_reg(dev, REG_ADDR(mcm_hsync_preample_ext), mcm_hsync_preample_ext); + isp_write_reg(dev, REG_ADDR(mcm_rd_cfg), mcm_rd_fmt); + isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} +int isp_bypass_mcm(struct isp_ic_dev *dev) +{ + struct isp_mcm_context *mcm = &dev->mcm; + u32 mcm_ctrl; + u32 mcm_retiming0; + u32 mcm_retiming1; + u32 mcm_wr_retiming0; + u32 mcm_wr_retiming1; + + isp_info("enter %s\n", __func__); + mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl)); + mcm_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_retiming0)); + mcm_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_retiming1)); + + mcm_wr_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming0)); + mcm_wr_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming1)); + + if (mcm->bypass_enable) { + REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 1); + } else { + REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 0); + } + + REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration); + REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank); + REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample); + REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank); + + REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration); + REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank); + REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample); + REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank); + + isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl); + isp_write_reg(dev, REG_ADDR(mcm_retiming0), mcm_retiming0); // 0x01042801);// + isp_write_reg(dev, REG_ADDR(mcm_retiming1), mcm_retiming1); //0x00008478); // + isp_write_reg(dev, REG_ADDR(mcm_wr_retiming0), mcm_wr_retiming0); //0x01042801); // + isp_write_reg(dev, REG_ADDR(mcm_wr_retiming1), mcm_wr_retiming1); //0x000084ec);// + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_mux(struct isp_ic_dev *dev) +{ + struct isp_mux_context mux = *(&dev->mux); + u32 vi_dpcl; + + isp_info("enter %s\n", __func__); + vi_dpcl = isp_read_reg(dev, REG_ADDR(vi_dpcl)); + REG_SET_SLICE(vi_dpcl, MRV_VI_MP_MUX, mux.mp_mux); + REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SPMUX, mux.sp_mux); + REG_SET_SLICE(vi_dpcl, MRV_VI_CHAN_MODE, mux.chan_mode); + REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_IEMUX, mux.ie_mux); + REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SWITCH, mux.dma_read_switch); + REG_SET_SLICE(vi_dpcl, MRV_IF_SELECT, mux.if_select); + isp_write_reg(dev, REG_ADDR(vi_dpcl), vi_dpcl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_bls(struct isp_ic_dev *dev) +{ +#ifndef ISP_BLS + //isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_bls_context bls = *(&dev->bls); + u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_MODE, bls.mode); + isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl); + isp_write_reg(dev, REG_ADDR(isp_bls_a_fixed), bls.a); + isp_write_reg(dev, REG_ADDR(isp_bls_b_fixed), bls.b); + isp_write_reg(dev, REG_ADDR(isp_bls_c_fixed), bls.c); + isp_write_reg(dev, REG_ADDR(isp_bls_d_fixed), bls.d); + return 0; +#endif +} + +int isp_enable_awb(struct isp_ic_dev *dev) +{ + u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_MEAS); + isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_disable_awb(struct isp_ic_dev *dev) +{ + u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_NOMEAS); + isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_awb(struct isp_ic_dev *dev) +{ + struct isp_awb_context awb = *(&dev->awb); + u32 gain_data = 0; + u32 isp_awb_thresh = 0; + u32 isp_awb_ref = 0; + u32 isp_awb_prop = 0; + + /* isp_info("enter %s\n", __func__); */ + isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop)); + + if (awb.mode == MRV_ISP_AWB_MEAS_MODE_YCBCR) { + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE, + MRV_ISP_AWB_MEAS_MODE_YCBCR); + if (awb.max_y == 0) { + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN, + MRV_ISP_AWB_MAX_EN_DISABLE); + } else { + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN, + MRV_ISP_AWB_MAX_EN_ENABLE); + } + } else if (awb.mode == MRV_ISP_AWB_MEAS_MODE_RGB) { + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN, + MRV_ISP_AWB_MAX_EN_DISABLE); + REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE, + MRV_ISP_AWB_MEAS_MODE_RGB); + } + isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop); + + REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_Y, awb.max_y); + REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_Y__MAX_G, + awb.min_y_max_g); + REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_CSUM, awb.max_c_sum); + REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_C, awb.min_c); + isp_write_reg(dev, REG_ADDR(isp_awb_thresh), isp_awb_thresh); + + REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CR__MAX_R, awb.refcr_max_r); + REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CB__MAX_B, awb.refcb_max_b); + isp_write_reg(dev, REG_ADDR(isp_awb_ref), isp_awb_ref); + isp_write_reg(dev, REG_ADDR(isp_awb_frames), 0); + isp_write_reg(dev, REG_ADDR(isp_awb_h_offs), + (MRV_ISP_AWB_H_OFFS_MASK & awb.window.x)); + isp_write_reg(dev, REG_ADDR(isp_awb_v_offs), + (MRV_ISP_AWB_V_OFFS_MASK & awb.window.y)); + isp_write_reg(dev, REG_ADDR(isp_awb_h_size), + (MRV_ISP_AWB_H_SIZE_MASK & awb.window.width)); + isp_write_reg(dev, REG_ADDR(isp_awb_v_size), + (MRV_ISP_AWB_V_SIZE_MASK & awb.window.height)); + + gain_data = 0UL; +#ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r << 2); + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b << 2) ; +#else //This is Gain value component 2 bit int part and 8 bit fractional part + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r); + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b); +#endif + isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), gain_data); + + gain_data = 0UL; +#ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr << 2); + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb << 2); +#else //This is Gain value component 2 bit int part and 8 bit fractional part + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr); + REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb); +#endif + + isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), gain_data); + return 0; +} + +int isp_s_is(struct isp_ic_dev *dev) +{ + struct isp_is_context is = *(&dev->is); + u32 isp_is_ctrl; + u32 isp_is_displace; + u32 isp_ctrl; + + isp_info("enter %s\n", __func__); + + isp_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_is_ctrl)); + + if (!is.enable) { + REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 0); + isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl); + return 0; + } + + REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 1); + isp_write_reg(dev, REG_ADDR(isp_is_h_offs), is.window.x); + isp_write_reg(dev, REG_ADDR(isp_is_v_offs), is.window.y); + isp_write_reg(dev, REG_ADDR(isp_is_h_size), is.window.width); + isp_write_reg(dev, REG_ADDR(isp_is_v_size), is.window.height); + isp_write_reg(dev, REG_ADDR(isp_is_recenter), + is.recenter & MRV_IS_IS_RECENTER_MASK); + isp_write_reg(dev, REG_ADDR(isp_is_max_dx), is.max_dx); + isp_write_reg(dev, REG_ADDR(isp_is_max_dy), is.max_dy); + isp_is_displace = isp_read_reg(dev, REG_ADDR(isp_is_displace)); + REG_SET_SLICE(isp_is_displace, MRV_IS_DX, is.displace_x); + REG_SET_SLICE(isp_is_displace, MRV_IS_DY, is.displace_y); + isp_write_reg(dev, REG_ADDR(isp_is_displace), isp_is_displace); + isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl); + if (is.update) { + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + is.update = false; + } + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_raw_is(struct isp_ic_dev *dev) +{ +#ifndef ISP_RAWIS + //isp_err("unsupported funciton: %s\n", __func__); + return -EINVAL; +#else + struct isp_is_context rawis = *(&dev->rawis); + u32 isp_raw_is_ctrl; + u32 isp_raw_is_displace; + // u32 isp_ctrl; + + isp_info("enter %s\n", __func__); + + isp_raw_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_raw_is_ctrl)); + + if (!rawis.enable) { + isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), + rawis.window.width); + isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), + rawis.window.height); + + REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 0); + isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl); + return 0; + } + + REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 1); + isp_write_reg(dev, REG_ADDR(isp_raw_is_h_offs), rawis.window.x); + isp_write_reg(dev, REG_ADDR(isp_raw_is_v_offs), rawis.window.y); + isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), rawis.window.width); + isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), rawis.window.height); + isp_write_reg(dev, REG_ADDR(isp_raw_is_recenter), + rawis.recenter & MRV_IS_IS_RECENTER_MASK); + isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dx), rawis.max_dx); + isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dy), rawis.max_dy); + isp_raw_is_displace = isp_read_reg(dev, REG_ADDR(isp_raw_is_displace)); + REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DX, rawis.displace_x); + REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DY, rawis.displace_y); + isp_write_reg(dev, REG_ADDR(isp_raw_is_displace), isp_raw_is_displace); + isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl); + /*dont update the configuration at the sub module function*/ +#if 0 + if (rawis.update) { + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + rawis.update = false; + } +#endif + return 0; +#endif +} + +int isp_s_cnr(struct isp_ic_dev *dev) +{ + struct isp_cnr_context *cnr = &dev->cnr; + u32 isp_ctrl; + + isp_info("enter %s\n", __func__); + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + if (!cnr->enable) { + REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + return 0; + } + + REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 1); + isp_write_reg(dev, REG_ADDR(isp_cnr_linesize), cnr->line_width); + isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c1), cnr->threshold_1); + isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c2), cnr->threshold_2); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +static void isp_test_bt(struct isp_ic_dev *dev) +{ + + isp_write_reg(dev, 0x00000010, 0x00019f7b); + isp_write_reg(dev, 0x00000014, 0x00020000); + isp_write_reg(dev, 0x00001200, 0x00000000); + isp_write_reg(dev, 0x00001204, 0x01e00280); + isp_write_reg(dev, 0x00001208, 0x01e00280); + isp_write_reg(dev, 0x00001308, 0x6ce60608); + isp_write_reg(dev, 0x00001314, 0x000008c4); + isp_write_reg(dev, 0x00001318, 0x00000001); + isp_write_reg(dev, 0x0000131c, 0x03a2013b); + isp_write_reg(dev, 0x00001320, 0x00000000); + isp_write_reg(dev, 0x00001324, 0xc0000000); + isp_write_reg(dev, 0x00001328, 0x0004B000); + isp_write_reg(dev, 0x0000132c, 0x00000000); + isp_write_reg(dev, 0x00001330, 0x00000280); + isp_write_reg(dev, 0x00001334, 0x00000280); + isp_write_reg(dev, 0x00001338, 0x000001e0); + isp_write_reg(dev, 0x0000133c, 0x0004B000); + isp_write_reg(dev, 0x00001340, 0xc0040000); + isp_write_reg(dev, 0x00001344, 0x0004B000); + isp_write_reg(dev, 0x000016c0, 0x07ffffff); + isp_write_reg(dev, 0x000005bc, 0x00000003); + isp_write_reg(dev, 0x000016c4, 0x052c4e39); + isp_write_reg(dev, 0x00000404, 0x00d00018); + isp_write_reg(dev, 0x00000410, 0x00000280); + isp_write_reg(dev, 0x00000414, 0x000001e0); + + isp_write_reg(dev, 0x00000538, 0x01000100); + isp_write_reg(dev, 0x0000053c, 0x02270220); + isp_write_reg(dev, 0x0000059c, 0x00000280); + isp_write_reg(dev, 0x000005a0, 0x000001e0); + + isp_write_reg(dev, 0x00002310, 0x00000280); + isp_write_reg(dev, 0x00002314, 0x000001e0); + isp_write_reg(dev, 0x0000295c, 0x00000070); + isp_write_reg(dev, 0x00003e00, 0x040128be); + isp_write_reg(dev, 0x00003e04, 0x00000000); + isp_write_reg(dev, 0x00003e08, 0x00001f08); + isp_write_reg(dev, 0x00003e0c, 0x200003ff); + isp_write_reg(dev, 0x00003e10, 0x0c968628); + isp_write_reg(dev, 0x00003e14, 0x00008008); + isp_write_reg(dev, 0x00003e18, 0x007d07d0); + isp_write_reg(dev, 0x00003e1c, 0x301a3012); + isp_write_reg(dev, 0x00003e20, 0x04010000); + isp_write_reg(dev, 0x00003e24, 0x22018000); + isp_write_reg(dev, 0x00003e28, 0x00020000); + isp_write_reg(dev, 0x00003e2c, 0x0210210a); + isp_write_reg(dev, 0x00003e30, 0x00102102); + isp_write_reg(dev, 0x00003e34, 0x0000388c); + isp_write_reg(dev, 0x00003e38, 0x00000000); + isp_write_reg(dev, 0x00003e3c, 0x00000000); + isp_write_reg(dev, 0x00003e40, 0x00000000); + isp_write_reg(dev, 0x00003e44, 0x00000001); + isp_write_reg(dev, 0x00003e48, 0x10001000); + isp_write_reg(dev, 0x00003e4c, 0x00000000); + isp_write_reg(dev, 0x00003e50, 0x00000000); + isp_write_reg(dev, 0x00003e54, 0x00000000); + isp_write_reg(dev, 0x00003e58, 0x00080010); + isp_write_reg(dev, 0x00003e5c, 0x00080010); + isp_write_reg(dev, 0x00003e60, 0x01300280); + isp_write_reg(dev, 0x00000018, 0x00001000); + isp_write_reg(dev, 0x00001200, 0x00000001); //why + + isp_write_reg(dev, 0x00000418, 0x00000001); + isp_write_reg(dev, 0x00000400, 0x80100686); + isp_write_reg(dev, 0x00000400, 0x80100097); + isp_write_reg(dev, 0x00001300, 0x00000001); + isp_write_reg(dev, 0x00001310, 0x00000038); + isp_write_reg(dev, 0x000014e4, 0x00000238); + isp_write_reg(dev, 0x00001600, 0x0000005c); + isp_write_reg(dev, 0x00000704, 0x00c00222); + isp_write_reg(dev, 0x00000708, 0x00a001e0); + isp_write_reg(dev, 0x0000070c, 0x000a4023); + isp_write_reg(dev, 0x00000710, 0x000a401e); + isp_write_reg(dev, 0x00000714, 0x000b8001); + isp_write_reg(dev, 0x00000718, 0x003540a0); + isp_write_reg(dev, 0x0000071c, 0x00000050); + isp_write_reg(dev, 0x00000720, 0x3aca095b); + isp_write_reg(dev, 0x00000700, 0x00000c42); + isp_info("end %s\n", __func__); +} +int isp_start_stream(struct isp_ic_dev *dev, u32 numFrames) +{ + + u32 isp_imsc, isp_ctrl; + + isp_info("enter %s\n", __func__); +#ifdef ISP_PDAF + isp_write_reg(dev, 0x5d00, 0x1); +#endif + + isp_write_reg(dev, REG_ADDR(isp_sh_ctrl), 0x10); + isp_write_reg(dev, REG_ADDR(isp_acq_nr_frames), + (MRV_ISP_ACQ_NR_FRAMES_MASK & numFrames)); + isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + isp_imsc |= + (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK | + MRV_ISP_IMSC_FRAME_IN_MASK | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK | MRV_ISP_IMSC_FLASH_ON_MASK | MRV_ISP_IMSC_FLASH_OFF_MASK); + /* isp_imsc |= (MRV_ISP_IMSC_FRAME_MASK | MRV_ISP_IMSC_DATA_LOSS_MASK | MRV_ISP_IMSC_FRAME_IN_MASK); */ + isp_write_reg(dev, REG_ADDR(isp_icr), 0xFFFFFFFF); + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + isp_write_reg(dev, 0x00001320, 1); + isp_write_reg(dev, 0x00001610, 1); +#if 0/*add by shenwuyi for live sensor*/ + isp_write_reg(dev, 0x00002200, 0x00000000); //disable lsc + isp_write_reg(dev, 0x000005bc, 0x00000001); //irq_enable + isp_write_reg(dev, 0x00000538, 0x01000100); //awb_gain_gr + isp_write_reg(dev, 0x0000053c, 0x02270220); //awb_gain_gc +#endif + /*isp_test_bt(dev);*/ + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + /*Set lsc tbl after isp enable*/ + if (dev->update_lsc_tbl) { + isp_s_lsc_tbl(dev); + dev->update_lsc_tbl = false; + } + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_stop_stream(struct isp_ic_dev *dev) +{ + isp_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(isp_imsc), 0); + isp_disable(dev); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_cc(struct isp_ic_dev *dev) +{ + struct isp_cc_context *cc = &dev->cc; + u32 isp_ctrl, addr; + int i; + + isp_info("enter %s\n", __func__); + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_Y_RANGE, cc->conv_range_y_full); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_C_RANGE, cc->conv_range_c_full); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + if (cc->update_curve) { + addr = REG_ADDR(isp_cc_coeff_0); + for (i = 0; i < 9; i++) { + isp_write_reg(dev, addr + i * 4, + MRV_ISP_CC_COEFF_0_MASK & cc->lCoeff[i]); + } + } + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_xtalk(struct isp_ic_dev *dev) +{ + struct isp_xtalk_context xtalk = *(&dev->xtalk); + int i; + + /* isp_info("enter %s\n", __func__); */ + + for (i = 0; i < 9; i++) { +#ifdef ISP_CTM_0507 // Coefficient for cross talk matrix.Use bit 11,Values are 12-bit signed fixed-point numbers with 5 bit integer and 7 bit fractional part, ranging from -16 (0x800) to +15.992 (0x7FF). + isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]), + MRV_ISP_CT_COEFF_MASK & (xtalk.lCoeff[i] << 1)); +#else // Coefficient for cross talk matrix.Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF). + isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]), + MRV_ISP_CT_COEFF_MASK & xtalk.lCoeff[i]); +#endif + } + + isp_write_reg(dev, REG_ADDR(isp_ct_offset_r), + (MRV_ISP_CT_OFFSET_R_MASK & xtalk.r)); + isp_write_reg(dev, REG_ADDR(isp_ct_offset_g), + (MRV_ISP_CT_OFFSET_G_MASK & xtalk.g)); + isp_write_reg(dev, REG_ADDR(isp_ct_offset_b), + (MRV_ISP_CT_OFFSET_B_MASK & xtalk.b)); + return 0; +} + +int isp_enable_wb(struct isp_ic_dev *dev, bool bEnable) +{ + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + isp_info("enter %s\n", __func__); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_AWB_ENABLE, bEnable); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_enable_gamma_out(struct isp_ic_dev *dev, bool bEnable) +{ + u32 isp_ctrl; + struct isp_gamma_out_context *gamma = &dev->gamma_out; + isp_info("enter %s\n", __func__); + gamma->enableGamma = bEnable; + if(gamma->changed || !is_isp_enable(dev)) + { + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, bEnable); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + gamma->changed = false; + } else { + gamma->changed = true; + } + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_gamma_out(struct isp_ic_dev *dev) +{ + u32 isp_gamma_out_mode; + int i; + u32 isp_ctrl; + struct isp_gamma_out_context *gamma = &dev->gamma_out; + if(gamma->changed || !is_isp_enable(dev)) { + isp_gamma_out_mode = isp_read_reg(dev, REG_ADDR(isp_gamma_out_mode)); + REG_SET_SLICE(isp_gamma_out_mode, MRV_ISP_EQU_SEGM, gamma->mode); + isp_write_reg(dev, REG_ADDR(isp_gamma_out_mode), isp_gamma_out_mode); + + for (i = 0; i < 17; i++) { + isp_write_reg(dev, REG_ADDR(gamma_out_y_block_arr[i]), + MRV_ISP_ISP_GAMMA_OUT_Y_MASK & gamma->curve[i]); + } + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, gamma->enableGamma); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + gamma->changed = false; + } else { + gamma->changed = true; + } + + return 0; +} + +int isp_s_lsc_tbl(struct isp_ic_dev *dev) +{ + int i, n; + u32 isp_ctrl; + u32 sram_addr; + u32 isp_lsc_status; + struct isp_lsc_context *lsc = (&dev->lsc); + + isp_debug("enter %s\n", __func__); + + /*need to set tbl after isp_ctrl enable In ISP8000NANO_V1802*/ + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + /* Enable isp to enable ram clock for write correct table to ram. */ + if (!(isp_ctrl & 0x01)) { + dev->update_lsc_tbl = true; + return 0; + } + + isp_lsc_status = isp_read_reg(dev, REG_ADDR(isp_lsc_status)); + sram_addr = (isp_lsc_status & 0x2U) ? 0U : 153U; + isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_addr), sram_addr); + isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_addr), sram_addr); + isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_addr), sram_addr); + isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_addr), sram_addr); +#ifdef ISP_LSC_V2 + for (n = 0; n < ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1)); n += CAMERIC_MAX_LSC_SECTORS + 1) { + for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) { + isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + i] & 0xFFF) | ((lsc->r[n + i + 1] & 0xFFF) << 12) | ((lsc->r[n + i] >> 12) << 24) | ((lsc->r[n + i + 1] >> 12) << 28)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + i] & 0xFFF) | ((lsc->gr[n + i + 1] & 0xFFF) << 12) | ((lsc->gr[n + i] >> 12) << 24) | ((lsc->gr[n + i + 1] >> 12) << 28)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + i] & 0xFFF) | ((lsc->gb[n + i + 1] & 0xFFF) << 12) | ((lsc->gb[n + i] >> 12) << 24) | ((lsc->gb[n + i + 1] >> 12) << 28)); + isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + i] & 0xFFF) | ((lsc->b[n + i + 1] & 0xFFF) << 12) | ((lsc->b[n + i] >> 12) << 24) | ((lsc->b[n + i + 1] >> 12) << 28)); + } + isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->r[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24)); + isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->b[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24)); + } +#else + for (n = 0; + n < + ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1)); + n += CAMERIC_MAX_LSC_SECTORS + 1) { + /* 17 sectors with 2 values in one DWORD = 9 DWORDs (8 steps + 1 outside loop) */ + for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) { + isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), + lsc->r[n + + i] | (lsc->r[n + i + 1] << 12)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), + lsc->gr[n + + i] | (lsc->gr[n + i + 1] << 12)); + isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), + lsc->gb[n + + i] | (lsc->gb[n + i + 1] << 12)); + isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), + lsc->b[n + + i] | (lsc->b[n + i + 1] << 12)); + } + isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), + lsc->r[n + CAMERIC_MAX_LSC_SECTORS]); + isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), + lsc->gr[n + CAMERIC_MAX_LSC_SECTORS]); + isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), + lsc->gb[n + CAMERIC_MAX_LSC_SECTORS]); + isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), + lsc->b[n + CAMERIC_MAX_LSC_SECTORS]); + } +#endif + isp_write_reg(dev, REG_ADDR(isp_lsc_table_sel), + (isp_lsc_status & 0x2U) ? 0U : 1U); + isp_info("exit %s\n", __func__); + return 0; +} + + +int isp_s_lsc_sec(struct isp_ic_dev *dev) +{ + int i; + struct isp_lsc_context *lsc = (&dev->lsc); + /* isp_info("enter %s\n", __func__); */ + for (i = 0; i < CAEMRIC_GRAD_TBL_SIZE; i += 2) { + isp_write_reg(dev, REG_ADDR(isp_lsc_xsize_01) + i * 2, + (lsc->x_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) | + ((lsc->x_size[i + 1] + << MRV_LSC_X_SECT_SIZE_1_SHIFT) + & MRV_LSC_X_SECT_SIZE_1_MASK)); + isp_write_reg(dev, REG_ADDR(isp_lsc_ysize_01) + i * 2, + (lsc->y_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) | + ((lsc->y_size[i + 1] + << MRV_LSC_Y_SECT_SIZE_1_SHIFT) + & MRV_LSC_Y_SECT_SIZE_1_MASK)); + isp_write_reg(dev, REG_ADDR(isp_lsc_xgrad_01) + i * 2, + (lsc->x_grad[i] & MRV_LSC_XGRAD_0_MASK) | + ((lsc->x_grad[i + 1] + << MRV_LSC_XGRAD_1_SHIFT) + & MRV_LSC_XGRAD_1_MASK)); + isp_write_reg(dev, REG_ADDR(isp_lsc_ygrad_01) + i * 2, + (lsc->y_grad[i] & MRV_LSC_YGRAD_0_MASK) | + ((lsc->y_grad[i + 1] + << MRV_LSC_YGRAD_1_SHIFT) + & MRV_LSC_YGRAD_1_MASK)); + } + return 0; +} + +int isp_ioc_read_mis(struct isp_ic_dev *dev, void __user *args) +{ + isp_mis_list_t* pCList = &dev->circle_list; + isp_mis_t mis_data; + u32 ary[2]; + int ret = -1; + ret = isp_irq_read_circle_queue(&mis_data, pCList); + if (ret < 0) { + /*isp_info("%s can not dequeue mis data\n", __func__);*/ + return ret; + } + + /*isp_info("%s irq src %d val 0x%08x\n", __func__, mis_data.irq_src, mis_data.val);*/ + ary[0] = mis_data.irq_src; + ary[1] = mis_data.val; + viv_check_retval(copy_to_user(args, ary, sizeof( ary))); + return 0; +} + +static int isp_ioc_read_reg(struct isp_ic_dev *dev, void __user * args) +{ + struct isp_reg_t reg; + + viv_check_retval(copy_from_user(®, args, sizeof(reg))); + reg.val = isp_read_reg(dev, reg.offset); + viv_check_retval(copy_to_user(args, ®, sizeof(reg))); + return 0; +} + +static int isp_ioc_write_reg(struct isp_ic_dev *dev, void __user *args) +{ + struct isp_reg_t reg; + + viv_check_retval((copy_from_user(®, args, sizeof(reg)))); + isp_write_reg(dev, reg.offset, reg.val); + return 0; +} + +int isp_ioc_disable_isp_off(struct isp_ic_dev *dev, void __user *args) +{ + u32 isp_imsc; + + isp_info("enter %s\n", __func__); + isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + isp_imsc &= ~MRV_ISP_IMSC_ISP_OFF_MASK; + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_g_awbmean(struct isp_ic_dev *dev, struct isp_awb_mean *mean) +{ + u32 reg = isp_read_reg(dev, REG_ADDR(isp_awb_mean)); + + /* isp_info("enter %s\n", __func__); */ + mean->g = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_Y__G); + mean->b = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CB__B); + mean->r = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CR__R); + mean->no_white_count = isp_read_reg(dev, REG_ADDR(isp_awb_white_cnt)); + + return 0; +} + +int isp_s_ee(struct isp_ic_dev *dev) +{ +#ifndef ISP_EE_RY + //isp_err("unsupported function: %s\n", __func__); + return -EINVAL; +#else + struct isp_ee_context *ee = &dev->ee; + u32 isp_ee_ctrl = isp_read_reg(dev, REG_ADDR(isp_ee_ctrl)); + u32 gain = 0; + + isp_info("enter %s\n", __func__); + + if (!ee->enable) { + isp_write_reg(dev, REG_ADDR(isp_ee_ctrl), + isp_ee_ctrl & ~EE_CTRL_ENABLE_MASK); + return 0; + } + + REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_INPUT_SEL, ee->input_sel); + REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_SOURCE_STRENGTH, ee->src_strength); + REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_STRENGTH, ee->strength); + REG_SET_SLICE(gain, EE_UV_GAIN, ee->uv_gain); + REG_SET_SLICE(gain, EE_EDGE_GAIN, ee->edge_gain); + isp_write_reg(dev, REG_ADDR(isp_ee_y_gain), ee->y_gain); + isp_write_reg(dev, REG_ADDR(isp_ee_uv_gain), gain); + isp_write_reg(dev, REG_ADDR(isp_ee_ctrl), + isp_ee_ctrl | EE_CTRL_ENABLE_MASK); + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_s_exp(struct isp_ic_dev *dev) +{ + struct isp_exp_context *exp = &dev->exp; + u32 isp_exp_ctrl = isp_read_reg(dev, REG_ADDR(isp_exp_ctrl)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + + isp_info("enter %s\n", __func__); + + if (!exp->enable) { + REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 0); + isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc & ~MRV_ISP_IMSC_EXP_END_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_exp_h_offset), + (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x)); + isp_write_reg(dev, REG_ADDR(isp_exp_v_offset), + (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y)); + isp_write_reg(dev, REG_ADDR(isp_exp_h_size), + (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width)); + isp_write_reg(dev, REG_ADDR(isp_exp_v_size), + (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height)); +#ifdef ISP_AE_SHADOW_RY + isp_write_reg(dev, REG_ADDR(isp_exp_h_offset_shd), + (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x)); + isp_write_reg(dev, REG_ADDR(isp_exp_v_offset_shd), + (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y)); + isp_write_reg(dev, REG_ADDR(isp_exp_h_size_shd), + (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width)); + isp_write_reg(dev, REG_ADDR(isp_exp_v_size_shd), + (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height)); +#endif + REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_MEAS_MODE, exp->mode); + REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 1); + isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_EXP_END_MASK); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_hdrexp(struct isp_ic_dev *dev) +{ + struct isp_exp_context *hdrexp = &dev->hdrexp; + u32 isp_hdr_exp_conf = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_conf)); + u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc)); + + pr_info("enter %s\n", __func__); + if (!dev->hdrexp.enable) { + pr_info("%s, hdr disabled\n",__func__); + REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 0); + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf); + isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc & ~0x38); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_offset), + (MRV_ISP_HDR_EXP_H_OFFSET_MASK & hdrexp->window.x)); + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_offset), + (MRV_ISP_HDR_EXP_V_OFFSET_MASK & hdrexp->window.y)); + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_size), + (MRV_ISP_HDR_EXP_H_SIZE_MASK & hdrexp->window.width)); + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_size), + (MRV_ISP_HDR_EXP_V_SIZE_MASK & hdrexp->window.height)); + + REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_MEAS_MODE, hdrexp->mode); + REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_SRC_SEL, 1); //hardware only support 1 + REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 1); + isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf); + isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x38); + return 0; +} + +int isp_g_expmean(struct isp_ic_dev *dev, u8 *mean) +{ + int i = 0; + + /* isp_info("enter %s\n", __func__); */ + if (!dev || !mean) + return -EINVAL; + for (; i < 25; i++) { + mean[i] = isp_read_reg(dev, REG_ADDR(isp_exp_mean_00) + i * 4); + } + + return 0; +} + +int isp_g_hdrexpmean(struct isp_ic_dev *dev, u8 * mean) +{ + int i = 0; + + pr_info("enter %s\n", __func__); + if (!dev || !mean) + return -EINVAL; + for (; i < 75; i++) { + mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_statistics[i])); + } + + return 0; +} + +#ifdef ISP_HIST256 +#define HIST_BIN_TOTAL 256 +#else +#define HIST_BIN_TOTAL 16 +#endif + +int isp_s_hist(struct isp_ic_dev *dev) +{ + struct isp_hist_context *hist = &dev->hist; + +#ifdef ISP_HIST256_RY + u32 isp_hist256_prop = isp_read_reg(dev, REG_ADDR(isp_hist256_prop)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + int i; + + if (!hist->enable) { + REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE, + MRV_HIST_MODE_NONE); + isp_write_reg(dev, REG_ADDR(isp_hist256_prop), + isp_hist256_prop); + //isp_write_reg(dev, REG_ADDR(isp_imsc), + // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_hist256_h_offs), + (MRV_HIST_H_OFFSET_MASK & hist->window.x)); + isp_write_reg(dev, REG_ADDR(isp_hist256_v_offs), + (MRV_HIST_V_OFFSET_MASK & hist->window.y)); + isp_write_reg(dev, REG_ADDR(isp_hist256_h_size), + (MRV_HIST_H_SIZE_MASK & hist->window.width)); + isp_write_reg(dev, REG_ADDR(isp_hist256_v_size), + (MRV_HIST_V_SIZE_MASK & hist->window.height)); + + for (i = 0; i < 24; i += 4) { + isp_write_reg(dev, REG_ADDR(isp_hist256_weight_00to30) + i, + hist->weight[i + + 0] | (hist->weight[i + + 1] << 8) | + (hist->weight[i + 2] << 16) | (hist->weight[i + + 3] << + 24)); + } + + isp_write_reg(dev, REG_ADDR(isp_hist256_weight_44), hist->weight[24]); + REG_SET_SLICE(isp_hist256_prop, MRV_HIST_STEPSIZE, hist->step_size); + REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE, hist->mode); + isp_write_reg(dev, REG_ADDR(isp_hist256_prop), isp_hist256_prop); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); +#else + u32 isp_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hist_prop)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + int i; + + isp_info("enter %s\n", __func__); + if (!hist->enable) { + REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE); + isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop); + //isp_write_reg(dev, REG_ADDR(isp_imsc), + // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_hist_h_offs), + (MRV_HIST_H_OFFSET_MASK & hist->window.x)); + isp_write_reg(dev, REG_ADDR(isp_hist_v_offs), + (MRV_HIST_V_OFFSET_MASK & hist->window.y)); + isp_write_reg(dev, REG_ADDR(isp_hist_h_size), + (MRV_HIST_H_SIZE_MASK & hist->window.width)); + isp_write_reg(dev, REG_ADDR(isp_hist_v_size), + (MRV_HIST_V_SIZE_MASK & hist->window.height)); + + for (i = 0; i < 24; i += 4) { + isp_write_reg(dev, REG_ADDR(isp_hist_weight_00to30) + i, + hist->weight[i + 0] | + (hist->weight[i + 1] << 8) | + (hist->weight[i + 2] << 16) | + (hist->weight[i + 3] << 24)); + } + + isp_write_reg(dev, REG_ADDR(isp_hist_weight_44), hist->weight[24]); + REG_SET_SLICE(isp_hist_prop, MRV_HIST_STEPSIZE, hist->step_size); + REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, hist->mode); + isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); + isp_info("exit %s\n", __func__); +#endif + return 0; +} + +int isp_s_hdrhist(struct isp_ic_dev *dev) +{ + struct isp_hist_context *hdrhist = &dev->hdrhist; + u32 isp_hdr_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_prop)); + u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc)); + + pr_info("enter %s\n", __func__); + if (!dev->hdrhist.enable) { + pr_info("%s, hdr disable\n", __func__); + REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE); + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop); + isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), + isp_stitching_imsc & ~0x1c0); + return 0; + } + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_offs), + (MRV_HIST_H_OFFSET_MASK & hdrhist->window.x)); + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_offs), + (MRV_HIST_V_OFFSET_MASK & hdrhist->window.y)); + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_size), + (MRV_HIST_H_SIZE_MASK & hdrhist->window.width)); + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_size), + (MRV_HIST_V_SIZE_MASK & hdrhist->window.height)); + + REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_STEPSIZE, hdrhist->step_size); + REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, hdrhist->mode); + isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop); + isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x1c0); + return 0; +} + +int isp_g_histmean(struct isp_ic_dev *dev, u32 *mean) +{ + int i = 0; + + /* isp_info("enter %s\n", __func__); */ + if (!dev || !mean) + return -EINVAL; +#ifdef ISP_HIST256_RY + for (; i < HIST_BIN_TOTAL; i++) { + mean[i] = isp_read_reg(dev, REG_ADDR(isp_hist256_bin_n)); + } +#else + for (; i < HIST_BIN_TOTAL; i++) { + mean[i] = isp_read_reg(dev, + REG_ADDR(histogram_measurement_result_arr[i])); + + } +#endif + return 0; +} + +int isp_g_hdrhistmean(struct isp_ic_dev *dev, u32 * mean) +{ + int i = 0; + + pr_info("enter %s\n", __func__); + if (!dev || !mean) + return -EINVAL; + + // size is fixed 48 now, contain 3 channels + for (; i < 48; i++) { + mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_statistics[i])); + } + return 0; +} + +int isp_s_hist64(struct isp_ic_dev *dev) +{ +#ifndef ISP_HIST64_RY + //pr_err("Not supported hist64 module\n"); + return -1; +#else + struct isp_hist64_context *hist64 = &dev->hist64; + + u32 isp64_hist_prop = isp_read_reg(dev, REG_ADDR(isp64_hist_prop)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + u32 isp64_hist_subsampling = isp_read_reg(dev, REG_ADDR(isp64_hist_subsampling)); + u32 isp64_hist_sample_range = isp_read_reg(dev, REG_ADDR(isp64_hist_sample_range)); + + u32 isp64_hist_coeff_r = 0, isp64_hist_coeff_g = 0, isp64_hist_coeff_b = 0; + int i; + + if (!hist64->enable) { + REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE, + MRV_HIST_MODE_NONE); + isp_write_reg(dev, REG_ADDR(isp64_hist_prop), + isp64_hist_prop); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); + //isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl), + /// hist64->enable & ~MRV_HIST_UPDATE_ENABLE_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp64_hist_h_offs), + (MRV_HIST_H_OFFSET_MASK & hist64->window.x)); + isp_write_reg(dev, REG_ADDR(isp64_hist_v_offs), + (MRV_HIST_V_OFFSET_MASK & hist64->window.y)); + isp_write_reg(dev, REG_ADDR(isp64_hist_h_size), + (MRV_HIST_H_SIZE_MASK & hist64->window.width)); + isp_write_reg(dev, REG_ADDR(isp64_hist_v_size), + (MRV_HIST_V_SIZE_MASK & hist64->window.height)); + + for (i = 0; i < 24; i += 4) { + isp_write_reg(dev, REG_ADDR(isp64_hist_weight_00to30) + i, + hist64->weight[i + + 0] | (hist64->weight[i + + 1] << 8) | + (hist64->weight[i + 2] << 16) | (hist64->weight[i + + 3] << + 24)); + } + + isp_write_reg(dev, REG_ADDR(isp64_hist_weight_44), hist64->weight[24]); + REG_SET_SLICE(isp64_hist_prop, MRV_HIST_CHANNEL_SELECT, hist64->channel); + REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE, hist64->mode); + + REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_V_STEPSIZE, hist64->vStepSize); + REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_H_STEP_INC, hist64->hStepInc); + + REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_OFFSET, hist64->sample_offset); + REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_SHIFT, hist64->sample_shift); + + REG_SET_SLICE(isp64_hist_coeff_r, MRV_HIST_COEFF_R, hist64->r_coeff); + REG_SET_SLICE(isp64_hist_coeff_g, MRV_HIST_COEFF_G, hist64->g_coeff); + REG_SET_SLICE(isp64_hist_coeff_b, MRV_HIST_COEFF_B, hist64->b_coeff); + isp_write_reg(dev, REG_ADDR(isp64_hist_subsampling), isp64_hist_subsampling); + isp_write_reg(dev, REG_ADDR(isp64_hist_sample_range), isp64_hist_sample_range); + isp_write_reg(dev, REG_ADDR(isp64_hist_prop), isp64_hist_prop); + + isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_r), isp64_hist_coeff_r); + isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_g), isp64_hist_coeff_g); + isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_b), isp64_hist_coeff_b); + + isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl), + hist64->enable); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK); + + return 0; +#endif +} + +#define HIST64_BIN_TOTAL 32 +int isp_g_hist64mean(struct isp_ic_dev *dev, u32 *mean) +{ +#ifndef ISP_HIST64_RY + //pr_err("Not supported hist64 module\n"); + return -1; +#else + int i = 0; + + isp_info("enter %s\n", __func__); + if (!dev || !mean) + return -EINVAL; + + for (; i < HIST64_BIN_TOTAL; i++) { + mean[i] = isp_read_reg(dev, + REG_ADDR(isp64_histogram_measurement_result_arr[i])); + + } + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_g_hist64_vstart_status(struct isp_ic_dev *dev, u32 *status) +{ +#ifndef ISP_HIST64_RY + //pr_err("Not supported hist64 module\n"); + return -1; +#else + + /* isp_info("enter %s\n", __func__); */ + if (!dev || !status) + return -EINVAL; + + *status = isp_read_reg(dev, REG_ADDR(isp64_hist_vstart_status)); + + return 0; +#endif +} + +int isp_update_hist64(struct isp_ic_dev *dev) +{ +#ifndef ISP_HIST64_RY + //pr_err("Not supported hist64\n"); + return -1; +#else + struct isp_hist64_context* hist64 =&dev->hist64; + + isp_write_reg(dev, REG_ADDR(isp64_hist_forced_upd_start_line),hist64->forced_upd_start_line); + isp_write_reg(dev, REG_ADDR(isp64_hist_forced_update), hist64->forced_upd); + + return 0; +#endif +} + +int isp_s_ge(struct isp_ic_dev *dev) +{ +#ifndef ISP_GREENEQUILIBRATE + //isp_err("unsupported function %s\n", __func__); + return -1; +#else + struct isp_ge_context *ge = &dev->ge; + u32 green_equilibrate_ctrl = + isp_read_reg(dev, REG_ADDR(green_equilibrate_ctrl)); + u32 green_equilibrate_hcnt_dummy = 0; + + isp_info("enter %s\n", __func__); + + if (!ge->enable) { + REG_SET_SLICE(green_equilibrate_ctrl, + ISP_GREEN_EQUILIBTATE_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl), + green_equilibrate_ctrl); + return 0; + } + + REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_TH, + ge->threshold); + REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_ENABLE, 1); + REG_SET_SLICE(green_equilibrate_hcnt_dummy, + ISP_GREEN_EQUILIBTATE_HCNT_DUMMY, ge->h_dummy); + isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl), + green_equilibrate_ctrl); + isp_write_reg(dev, REG_ADDR(green_equilibrate_hcnt_dummy), + green_equilibrate_hcnt_dummy); + isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl_shd), + green_equilibrate_ctrl); + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_s_ca(struct isp_ic_dev *dev) +{ +#ifndef ISP_CA_RY + //isp_err("unsupported function %s\n", __func__); + return -1; +#else + struct isp_ca_context *ca = &dev->ca; + u32 isp_curve_ctrl = isp_read_reg(dev, REG_ADDR(isp_curve_ctrl)); + // u32 isp_curve_lut_x_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_x_addr)); + // u32 isp_curve_lut_luma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_luma_addr)); + // u32 isp_curve_lut_chroma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr)); + // u32 isp_curve_lut_shift_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_shift_addr)); + + int i = 0; + isp_info("enter %s\n", __func__); + if (!ca->enable) { + REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_addr), 0); + + for (i = 0; i < CA_CURVE_DATA_TABLE_LEN; i++) { + isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_write_data), + dev->ca.lut_x[i]); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_write_data), + dev->ca.lut_luma[i]); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_write_data), + dev->ca.lut_chroma[i]); + isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_write_data), + dev->ca.lut_shift[i]); + } + REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_MODE, dev->ca.mode); + REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl); + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_s_dpcc(struct isp_ic_dev *dev) +{ + struct isp_dpcc_context *dpcc = &dev->dpcc; + const u32 reg_gap = 20; + int i; + u32 isp_dpcc_mode = isp_read_reg(dev, REG_ADDR(isp_dpcc_mode)); + + isp_info("enter %s\n", __func__); + + if (!dpcc->enable) { + REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 0); + } else { + REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 1); + } + + isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), dpcc->mode); + isp_write_reg(dev, REG_ADDR(isp_dpcc_output_mode), dpcc->outmode); + isp_write_reg(dev, REG_ADDR(isp_dpcc_set_use), dpcc->set_use); + + for (i = 0; i < 3; i++) { + isp_write_reg(dev, REG_ADDR(isp_dpcc_methods_set_1) + i * 4, + 0x1FFF & dpcc->methods_set[i]); + isp_write_reg(dev, + REG_ADDR(isp_dpcc_line_thresh_1) + i * reg_gap, + 0xFFFF & dpcc->params[i].line_thresh); + isp_write_reg(dev, + REG_ADDR(isp_dpcc_line_mad_fac_1) + i * reg_gap, + 0x3F3F & dpcc->params[i].line_mad_fac); + isp_write_reg(dev, REG_ADDR(isp_dpcc_pg_fac_1) + i * reg_gap, + 0x3F3F & dpcc->params[i].pg_fac); + isp_write_reg(dev, + REG_ADDR(isp_dpcc_rnd_thresh_1) + i * reg_gap, + 0xFFFF & dpcc->params[i].rnd_thresh); + isp_write_reg(dev, REG_ADDR(isp_dpcc_rg_fac_1) + i * reg_gap, + 0x3F3F & dpcc->params[i].rg_fac); + } + + isp_write_reg(dev, REG_ADDR(isp_dpcc_ro_limits), dpcc->ro_limits); + isp_write_reg(dev, REG_ADDR(isp_dpcc_rnd_offs), dpcc->rnd_offs); + isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), isp_dpcc_mode); + isp_info("exit %s\n", __func__); + return 0; +} + + +int isp_s_flt(struct isp_ic_dev *dev) +{ + struct flt_denoise_type { + u32 thresh_sh0; + u32 thresh_sh1; + u32 thresh_bl0; + u32 thresh_bl1; + u32 stage_select; + u32 vmode; + u32 hmode; + }; + + struct flt_sharpen_type { + u32 fac_sh0; + u32 fac_sh1; + u32 fac_mid; + u32 fac_bl0; + u32 fac_bl1; + }; + + static struct flt_denoise_type denoise_tbl[] = { + {0, 0, 0, 0, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC8, + MRV_FILT_FILT_CHR_H_MODE_BYPASS}, + {18, 33, 8, 2, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {26, 44, 13, 5, 4, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {36, 51, 23, 10, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {41, 67, 26, 15, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {75, 10, 50, 20, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {90, 120, 60, 26, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {120, 150, 80, 51, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {170, 200, 140, 100, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {250, 300, 180, 150, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {1023, 1023, 1023, 1023, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12, + MRV_FILT_FILT_CHR_H_MODE_DYN_2}, + {1023, 1023, 1023, 1023, 0, MRV_FILT_FILT_CHR_V_MODE_BYPASS, + MRV_FILT_FILT_CHR_H_MODE_BYPASS}, + }; + + static struct flt_sharpen_type sharpen_tbl[] = { + {0x4, 0x4, 0x4, 0x2, 0x0}, + {0x7, 0x8, 0x6, 0x2, 0x0}, + {0xA, 0xC, 0x8, 0x4, 0x0}, + {0xC, 0x10, 0xA, 0x6, 0x2}, + {0x16, 0x16, 0xC, 0x8, 0x4}, + {0x14, 0x1B, 0x10, 0xA, 0x4}, + {0x1A, 0x20, 0x13, 0xC, 0x6}, + {0x1E, 0x26, 0x17, 0x10, 0x8}, + {0x24, 0x2C, 0x1D, 0x15, 0x0D}, + {0x2A, 0x30, 0x22, 0x1A, 0x14}, + {0x30, 0x3F, 0x28, 0x24, 0x20}, + }; + + // isp_info("enter %s\n", __func__); + + if(dev->flt.changed || !is_isp_enable(dev)) + { + struct isp_flt_context *flt = &dev->flt; + u32 isp_flt_mode = isp_read_reg(dev, REG_ADDR(isp_filt_mode)); + + if (!flt->enable) { + REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode); + return 0; + } + + if (flt->denoise >= 0) { + isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh0), + denoise_tbl[flt->denoise].thresh_sh0); + isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh1), + denoise_tbl[flt->denoise].thresh_sh1); + isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl0), + denoise_tbl[flt->denoise].thresh_bl0); + isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl1), + denoise_tbl[flt->denoise].thresh_bl1); + REG_SET_SLICE(isp_flt_mode, MRV_FILT_STAGE1_SELECT, + denoise_tbl[flt->denoise].stage_select); + REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_V_MODE, + denoise_tbl[flt->denoise].vmode); + REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_H_MODE, + denoise_tbl[flt->denoise].hmode); + } + + if (flt->sharpen >= 0) { + isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh0), + sharpen_tbl[flt->sharpen].fac_sh0); + isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh1), + sharpen_tbl[flt->sharpen].fac_sh1); + isp_write_reg(dev, REG_ADDR(isp_filt_fac_mid), + sharpen_tbl[flt->sharpen].fac_mid); + isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl0), + sharpen_tbl[flt->sharpen].fac_bl0); + isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl1), + sharpen_tbl[flt->sharpen].fac_bl1); + } + + REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_MODE, + MRV_FILT_FILT_MODE_DYNAMIC); + isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode); + REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode); + isp_write_reg(dev, REG_ADDR(isp_filt_lum_weight), 0x00032040); + + dev->flt.changed = false; + } else { + dev->flt.changed = true; + } + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_cac(struct isp_ic_dev *dev) +{ + struct isp_cac_context *cac = &dev->cac; + u32 val = 0; + u32 isp_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_cac_ctrl)); + + isp_info("enter %s\n", __func__); + + if (!cac->enable) { + REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 0); + isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl); + return 0; + } + + REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode); + REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode); + isp_write_reg(dev, REG_ADDR(isp_cac_count_start), + cac->hstart | (cac->vstart << 16)); + isp_write_reg(dev, REG_ADDR(isp_cac_a), cac->ar | (cac->ab << 16)); + isp_write_reg(dev, REG_ADDR(isp_cac_b), cac->br | (cac->bb << 16)); + isp_write_reg(dev, REG_ADDR(isp_cac_c), cac->cr | (cac->cb << 16)); + + REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns); + REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf); + isp_write_reg(dev, REG_ADDR(isp_cac_x_norm), val); + val = 0; + REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns); + REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf); + isp_write_reg(dev, REG_ADDR(isp_cac_y_norm), val); + REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 1); + isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_deg(struct isp_ic_dev *dev) +{ + struct isp_deg_context *deg = &dev->deg; + int i; + u32 isp_gamma_dx_lo = 0; + u32 isp_gamma_dx_hi = 0; + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + isp_info("enter %s\n", __func__); + + if (!deg->enable) { + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + return 0; + } + + for (i = 0; i < 8; i++) { + isp_gamma_dx_lo |= deg->segment[i] << (i * 4); + isp_gamma_dx_hi |= deg->segment[i + 8] << (i * 4); + } + + isp_write_reg(dev, REG_ADDR(isp_gamma_dx_lo), isp_gamma_dx_lo); + isp_write_reg(dev, REG_ADDR(isp_gamma_dx_hi), isp_gamma_dx_hi); + + for (i = 0; i < 17; i++) { + isp_write_reg(dev, REG_ADDR(degamma_r_y_block_arr[i]), + deg->r[i]); + isp_write_reg(dev, REG_ADDR(degamma_g_y_block_arr[i]), + deg->g[i]); + isp_write_reg(dev, REG_ADDR(degamma_b_y_block_arr[i]), + deg->b[i]); + } + + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +static u32 get_eff_coeff(int decimal) +{ + u32 value = 0; + + if (decimal <= -6) + value = 15; + else if (decimal <= -3) + value = 14; + else if (decimal == -2) + value = 13; + else if (decimal == -1) + value = 12; + else if (decimal == 0) + value = 0; + else if (decimal == 1) + value = 8; + else if (decimal == 2) + value = 9; + else if (decimal < 6) + value = 10; + else + value = 11; + + return value; +} + +int isp_s_ie(struct isp_ic_dev *dev) +{ + struct isp_ie_context *ie = &dev->ie; + u32 img_eff_ctrl = isp_read_reg(dev, REG_ADDR(img_eff_ctrl)); + u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl)); + u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl)); + u32 img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint)); + u32 img_eff_color_sel = isp_read_reg(dev, REG_ADDR(img_eff_color_sel)); + u32 mat[9]; + u32 sharpen = 0; + int i; + + isp_info("enter %s\n", __func__); + + REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 1); + isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + + if (!ie->enable) { + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD, + MRV_IMGEFF_CFG_UPD_UPDATE); + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE, + MRV_IMGEFF_BYPASS_MODE_BYPASS); + REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); + isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl); + return 0; + } + + REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 0); + isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + + REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_EFFECT_MODE, ie->mode); + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_FULL_RANGE, ie->full_range); + + for (i = 0; i < 9; i++) + mat[i] = get_eff_coeff(ie->m[i]); + + if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SEPIA) { + img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint)); + REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CR, ie->tint_cr); + REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CB, ie->tint_cb); + isp_write_reg(dev, REG_ADDR(img_eff_tint), img_eff_tint); + } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_COLOR_SEL) { + REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_SELECTION, + ie->color_sel); + REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_THRESHOLD, + ie->color_thresh); + isp_write_reg(dev, REG_ADDR(img_eff_color_sel), + img_eff_color_sel); + } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_EMBOSS) { + isp_write_reg(dev, REG_ADDR(img_eff_mat_1), + mat[0] | (mat[1] << 4) | (mat[2] << 8) | (mat[3] + << 12)); + isp_write_reg(dev, REG_ADDR(img_eff_mat_2), + mat[4] | (mat[5] << 4) | (mat[6] << 8) | (mat[7] + << 12)); + isp_write_reg(dev, REG_ADDR(img_eff_mat_3), mat[8]); + } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SKETCH || + ie->mode == MRV_IMGEFF_EFFECT_MODE_SHARPEN) { + isp_write_reg(dev, REG_ADDR(img_eff_mat_3), + (mat[0] << 4) | (mat[1] << 8) | (mat[2] << 12)); + isp_write_reg(dev, REG_ADDR(img_eff_mat_4), + mat[3] | (mat[4] << 4) | (mat[5] << 8) | (mat[6] + << 12)); + isp_write_reg(dev, REG_ADDR(img_eff_mat_5), + mat[7] | (mat[8] << 4)); + REG_SET_SLICE(sharpen, MRV_IMGEFF_SHARP_FACTOR, + ie->sharpen_factor); + REG_SET_SLICE(sharpen, MRV_IMGEFF_CORING_THR, + ie->sharpen_thresh); + isp_write_reg(dev, REG_ADDR(img_eff_sharpen), sharpen); + } + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD, + MRV_IMGEFF_CFG_UPD_UPDATE); + REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE, + MRV_IMGEFF_BYPASS_MODE_PROCESS); + isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_vsm(struct isp_ic_dev *dev) +{ + struct isp_vsm_context *vsm = &dev->vsm; + u32 isp_vsm_mode = isp_read_reg(dev, REG_ADDR(isp_vsm_mode)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + + isp_info("enter %s\n", __func__); + + if (!vsm->enable) { + REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 0); + REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc & ~MRV_ISP_IMSC_VSM_END_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(isp_vsm_h_offs), vsm->window.x); + isp_write_reg(dev, REG_ADDR(isp_vsm_v_offs), vsm->window.y); + isp_write_reg(dev, REG_ADDR(isp_vsm_h_size), + vsm->window.width & 0xFFFFE); + isp_write_reg(dev, REG_ADDR(isp_vsm_v_size), + vsm->window.height & 0xFFFFE); + isp_write_reg(dev, REG_ADDR(isp_vsm_h_segments), vsm->h_seg); + isp_write_reg(dev, REG_ADDR(isp_vsm_v_segments), vsm->v_seg); + REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 1); + REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_VSM_END_MASK); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_g_vsm(struct isp_ic_dev *dev, struct isp_vsm_result *vsm) +{ + isp_info("enter %s\n", __func__); + vsm->x = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_h)); + vsm->y = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_v)); + isp_info("exit %s\n", __func__); + return 0; +} + +#if 0 +u32 get_afm_shift(u32 count, u32 thresh) +{ + u32 grad = count; + u32 shift = 0; + + while (grad > (thresh)) { + ++shift; + grad >>= 1; + } + + return shift; +} +#endif + +int isp_s_afm(struct isp_ic_dev *dev) +{ + struct isp_afm_context *afm = &dev->afm; + u32 mask = + (MRV_ISP_IMSC_AFM_FIN_MASK | MRV_ISP_IMSC_AFM_LUM_OF_MASK | + MRV_ISP_IMSC_AFM_SUM_OF_MASK); + + u32 shift = 0; + int i; + + u32 isp_afm_ctrl = isp_read_reg(dev, REG_ADDR(isp_afm_ctrl)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + + isp_info("enter %s\n", __func__); + + if (!afm->enable) { + REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 0); + isp_imsc &= ~mask; + isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl); + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + return 0; + } + + for (i = 0; i < 3; i++) { + isp_write_reg(dev, REG_ADDR(isp_afm_lt_a) + i * 8, + (afm->window[i].x << 16) | afm->window[i].y); + isp_write_reg(dev, REG_ADDR(isp_afm_rb_a) + i * 8, + ((afm->window[i].x + afm->window[i].width - + 1) << 16) | ((afm->window[i].y + + afm->window[i].height - 1))); + } + + REG_SET_SLICE(shift, MRV_AFM_LUM_VAR_SHIFT, afm->lum_shift); + REG_SET_SLICE(shift, MRV_AFM_AFM_VAR_SHIFT, afm->afm_shift); + isp_write_reg(dev, REG_ADDR(isp_afm_var_shift), shift); + isp_write_reg(dev, REG_ADDR(isp_afm_thres), afm->thresh); + REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 1); + isp_imsc |= mask; + isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl); + isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_g_afm(struct isp_ic_dev *dev, struct isp_afm_result *afm) +{ + isp_info("enter %s\n", __func__); + afm->sum_a = isp_read_reg(dev, REG_ADDR(isp_afm_sum_a)); + afm->sum_b = isp_read_reg(dev, REG_ADDR(isp_afm_sum_b)); + afm->sum_c = isp_read_reg(dev, REG_ADDR(isp_afm_sum_c)); + afm->lum_a = isp_read_reg(dev, REG_ADDR(isp_afm_lum_a)); + afm->lum_b = isp_read_reg(dev, REG_ADDR(isp_afm_lum_b)); + afm->lum_c = isp_read_reg(dev, REG_ADDR(isp_afm_lum_c)); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_exp2_inputsel(struct isp_ic_dev *dev) +{ +#ifndef ISP_AEV2_RY + pr_err("unsupported function: %s\n", __func__); + return -EINVAL; +#else + struct isp_exp2_context *exp2 = &dev->exp2; + u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl)); + REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select); + isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl); + return 0; +#endif +} + +int isp_s_exp2_sizeratio(struct isp_ic_dev *dev, u32 h_size) +{ +#ifndef ISP_AEV2_RY + pr_err("unsupported function: %s\n", __func__); + return -EINVAL; +#else + u32 size_inv; + size_inv = isp_read_reg(dev, REG_ADDR(isp_expv2_size_invert)); + REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, h_size); + isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv); + return 0; +#endif +} + +int isp_s_exp2(struct isp_ic_dev *dev) +{ +#ifndef ISP_AEV2_RY + //isp_err("unsupported function: %s\n", __func__); + return -EINVAL; +#else + u32 miv2_ctrl; + struct isp_exp2_context *exp2 = &dev->exp2; + u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl)); + u32 grid_w, grid_h; + u32 size, offset, size_inv, weight; + + isp_info("enter %s\n", __func__); + grid_w = ((exp2->window.width - 1) >> 6) << 1; + grid_h = ((exp2->window.height - 1) >> 6) << 1; + + if (!exp2->enable) { + REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl); + return 0; + } + size = 0; + REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_H, grid_w); + REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_V, grid_h); + offset = 0; + REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_H, exp2->window.x); + REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_V, exp2->window.y); + size_inv = 0; + REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, (65536 + grid_w/2) / grid_w); + REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_V, (65536 + grid_h/2) / grid_h); + weight = 0; + REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_R, exp2->r) + REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR, exp2->gr) + REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB, exp2->gb) + REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_B, exp2->b) + isp_write_reg(dev, REG_ADDR(isp_expv2_offset), offset); + isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv); + isp_write_reg(dev, REG_ADDR(isp_expv2_size), size); +#ifdef ISP_AE_SHADOW_RY + isp_write_reg(dev, REG_ADDR(isp_expv2_offset_shd), offset); + isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert_shd), size_inv); + isp_write_reg(dev, REG_ADDR(isp_expv2_size_shd), size); +#endif + isp_write_reg(dev, REG_ADDR(isp_expv2_pixel_weight), weight); + + miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_base_ad_init), dev->exp2.pa); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_size_init), AEV2_DMA_SIZE); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_offs_cnt_init), 0); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_llength), AEV2_DMA_SIZE); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_width), 1024); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_height), 1); + isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_size), AEV2_DMA_SIZE); + + + REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 1); + REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select); + isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl); + + return 0; +#endif +} + +int isp_s_2dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_2DNR + //isp_err("unsupported function: %s\n", __func__); + return -EINVAL; +#else + struct isp_2dnr_context *dnr2 = &dev->dnr2; + u32 isp_denoise2d_control = + isp_read_reg(dev, REG_ADDR(isp_denoise2d_control)); + u32 value, addr, strength; + u32 isp_ctrl; + int i; + + isp_info("enter %s\n", __func__); + + if (!dnr2->enable) { +#ifndef ISP_2DNR_V4 + REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_control), + isp_denoise2d_control); +#else + value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 0); + if((value & DENOISE3D_V20_TNR_ENABLE_MASK) == 0) + REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), + value); + +#endif + return 0; + } + + strength = isp_read_reg(dev, REG_ADDR(isp_denoise2d_strength)); + REG_SET_SLICE(strength, ISP_2DNR_PRGAMMA_STRENGTH, dnr2->pre_gamma); + REG_SET_SLICE(strength, ISP_2DNR_STRENGTH, dnr2->strength); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength), strength); + + addr = REG_ADDR(isp_denoise2d_sigma_y[0]); + for (i = 0; i < 60; i += 5) { + value = 0; + REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i]); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 1]); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY2A, + dnr2->sigma[i + 2] >> 6); + isp_write_reg(dev, addr, value); + value = 0; + addr += 4; + REG_SET_SLICE(value, ISP_2DNR_SIGMAY2B, + dnr2->sigma[i + 2] & 0x3f); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i + 3]); + REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 4]); + isp_write_reg(dev, addr, value); + addr += 4; + } + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 1); + +#if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4) + isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr), dnr2->sigma_sqr); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr_shd), + dnr2->sigma_sqr); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor), + dnr2->weight); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor_shd), + dnr2->weight); + /* refer to HW spec for HBLANK */ + //isp_write_reg(dev, REG_ADDR(isp_denoise2d_dummy_hblank), 0); + + isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength_shd), strength); + isp_write_reg(dev, REG_ADDR(isp_denoise2d_control_shd), + isp_denoise2d_control); +#endif + +#ifndef ISP_2DNR_V4 + isp_write_reg(dev, REG_ADDR(isp_denoise2d_control), + isp_denoise2d_control); +#else + value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_blending)); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_OFFSET, dnr2->str_off); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_MAX, dnr2->str_max); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_SLOPE, dnr2->str_slope); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_blending), value); + value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 1); + REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), + value); +#endif + isp_info("exit %s\n", __func__); + return 0; +#endif +} + +int isp_s_simp(struct isp_ic_dev *dev) +{ + struct isp_simp_context *simp = &dev->simp; + u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl)); + u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl)); + u32 super_imp_ctrl = isp_read_reg(dev, REG_ADDR(super_imp_ctrl)); + + isp_info("enter %s\n", __func__); + + REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 1); + isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + + if (!simp->enable) { + REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); + return 0; + } + + REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 0); + isp_write_reg(dev, REG_ADDR(super_imp_offset_x), simp->x); + isp_write_reg(dev, REG_ADDR(super_imp_offset_y), simp->y); + isp_write_reg(dev, REG_ADDR(super_imp_color_y), simp->r); + isp_write_reg(dev, REG_ADDR(super_imp_color_cb), simp->g); + isp_write_reg(dev, REG_ADDR(super_imp_color_cr), simp->b); + REG_SET_SLICE(super_imp_ctrl, MRV_SI_TRANSPARENCY_MODE, + simp->transparency_mode); + REG_SET_SLICE(super_imp_ctrl, MRV_SI_REF_IMAGE, simp->ref_image); + isp_write_reg(dev, REG_ADDR(super_imp_ctrl), super_imp_ctrl); + isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_cproc(struct isp_ic_dev *dev) +{ + struct isp_cproc_context *cproc = &dev->cproc; + u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl)); + u32 cproc_ctrl = isp_read_reg(dev, REG_ADDR(cproc_ctrl)); + + //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 1); + //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + + //if there is no shd register. should update cporc register in isp frame end irq. +#ifndef ISP_CPROC_SHD_RY + if(dev->cproc.changed || !is_isp_enable(dev)) + { +#endif + isp_info("enter %s %d\n", __func__, cproc->enable); + if (!cproc->enable) { + REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 0); + /* REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 0); */ + /* isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); */ + isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl); + return 0; + } + + //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 0); + //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl); + isp_write_reg(dev, REG_ADDR(cproc_contrast), cproc->contrast); + isp_write_reg(dev, REG_ADDR(cproc_brightness), cproc->brightness); + isp_write_reg(dev, REG_ADDR(cproc_saturation), cproc->saturation); + isp_write_reg(dev, REG_ADDR(cproc_hue), cproc->hue); + REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 1); + REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_C_OUT_RANGE, + cproc->c_out_full); + REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_OUT_RANGE, + cproc->y_out_full); + REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_IN_RANGE, cproc->y_in_full); + REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); + isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl); + +#ifndef ISP_CPROC_SHD_RY + dev->cproc.changed = false; + } else { + dev->cproc.changed = true; + } +#endif + isp_info("exit %s\n", __func__); + return 0; +} + +int isp_s_elawb(struct isp_ic_dev *dev) +{ + struct isp_elawb_context *elawb = &dev->elawb; + u32 awb_meas_mode = isp_read_reg(dev, REG_ADDR(awb_meas_mode)); + u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc)); + u32 id = elawb->id; + u32 data; + + if (!elawb->enable) { + REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 0); + REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 0); + isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK); + return 0; + } + + isp_write_reg(dev, REG_ADDR(awb_meas_h_offs), elawb->window.x); + isp_write_reg(dev, REG_ADDR(awb_meas_v_offs), elawb->window.y); + isp_write_reg(dev, REG_ADDR(awb_meas_h_size), elawb->window.width); + isp_write_reg(dev, REG_ADDR(awb_meas_v_size), elawb->window.height); + + if (id > 0 && id < 9) { + isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].x), + elawb->info[id - 1].x); + isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].y), + elawb->info[id - 1].y); + isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a1), + elawb->info[id - 1].a1); + isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a2), + elawb->info[id - 1].a2); + isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a3), + elawb->info[id - 1].a3); + isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a4), + elawb->info[id - 1].a4); + isp_write_reg(dev, REG_ADDR(awb_meas_rmax[id - 1]), + elawb->info[id - 1].r_max_sqr); + } + + data = 0; + REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_R, elawb->r); + REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_B, elawb->b); + isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), data); + data = 0; + REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GR, elawb->gr); + REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GB, elawb->gb); + isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), data); + + REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 1); + REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 1); + isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode); + isp_write_reg(dev, REG_ADDR(isp_imsc), + isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK); + + return 0; +} + +int isp_ioc_qcap(struct isp_ic_dev *dev, void __user *args) +{ + + /* use public VIDIOC_QUERYCAP to query the type of v4l-subdevs. */ +#ifdef __KERNEL__ +#ifndef USE_FPGA + struct v4l2_capability *cap = (struct v4l2_capability *)args; + strcpy((char *)cap->driver, "viv_isp_subdev"); + cap->bus_info[0] = (__u8)dev->id;//isp channel id +#else + struct v4l2_capability cap; + strcpy((char *)cap.driver, "viv_isp_subdev"); + cap.bus_info[0] = (__u8)dev->id;//isp channel id + isp_info("enter %s viv_isp_subdev\n", __func__); + viv_check_retval(copy_to_user + ((struct v4l2_capability *)args, &cap, sizeof(cap))); +#endif +#endif + return 0; +} + +int isp_ioc_g_status(struct isp_ic_dev *dev, void __user *args) +{ + u32 val = 0; + /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */ + viv_check_retval(copy_to_user(args, &val, sizeof(val))); + return 0; +} + +static u32 getScaleFactor(u32 src, u32 dst) +{ + if (dst > src) { + return ((65536 * (src - 1)) / (dst - 1)); + } else if (dst < src) { + return ((65536 * (dst - 1)) / (src - 1)) + 1; + } + return 65536; +} + +int isp_set_scaling(int id, struct isp_ic_dev *dev, bool stabilization, bool crop) +{ + u32 addr, ctrl; + u32 iw, ih, ow, oh; + u32 inputWidth, inputHeight, outputWidth, outputHeight; + u32 scale_hy, scale_hcb, scale_hcr, scale_vy, scale_vc; + struct isp_mi_data_path_context *path = &dev->mi.path[id]; + if (crop) { //enabled crop.Do not need to scaler. + isp_info("%s:The crop enabled ,So does not need to do scaler.\n", __func__); + return 0; + } + if (id == IC_MI_PATH_MAIN) { /* mp */ + addr = REG_ADDR(mrsz_ctrl); + } else if (id == IC_MI_PATH_SELF) { /* sp */ + addr = REG_ADDR(srsz_ctrl); + } else if (id == IC_MI_PATH_SELF2) { /* sp2 */ + addr = REG_ADDR(srsz2_ctrl); + } else { + return -EFAULT; + } + + inputWidth = path->in_width; + inputHeight = path->in_height; + outputWidth = path->out_width; + outputHeight = path->out_height; + + if (stabilization) { /* enabled image stabilization. */ + inputWidth = isp_read_reg(dev, REG_ADDR(isp_is_h_size)); + inputHeight = isp_read_reg(dev, REG_ADDR(isp_is_v_size)); + } + + ctrl = isp_read_reg(dev, addr); + iw = inputWidth / 2; + ih = inputHeight; + ow = outputWidth / 2; + oh = outputHeight; + + switch (path->in_mode) { + case IC_MI_DATAMODE_YUV422: + oh = outputHeight; + break; + case IC_MI_DATAMODE_YUV420: + oh = outputHeight / 2; /* scale cbcr */ + break; + case IC_MI_DATAMODE_YUV444: + oh = outputHeight; + break; + case IC_MI_DATAMODE_RGB888: + oh = outputHeight; + break; + default: + return -EFAULT; + } + + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_ENABLE, + inputWidth != outputWidth); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_ENABLE, + inputHeight != outputHeight); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_UP, inputWidth < outputWidth); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_UP, inputHeight < outputHeight); + scale_hy = getScaleFactor(inputWidth, outputWidth); + scale_vy = getScaleFactor(inputHeight, outputHeight); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_ENABLE, iw != ow); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_ENABLE, ih != oh); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_UP, iw < ow); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_UP, ih < oh); + scale_hcr = getScaleFactor(iw, ow); + scale_hcb = getScaleFactor(iw, ow); + scale_vc = getScaleFactor(ih, oh); + + /*Need to update immediately*/ + REG_SET_SLICE(ctrl, MRV_MRSZ_CFG_UPD, 1); + + if (id == IC_MI_PATH_MAIN) { + isp_write_reg(dev, REG_ADDR(mrsz_scale_vc), scale_vc); + isp_write_reg(dev, REG_ADDR(mrsz_scale_vy), scale_vy); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hcr), scale_hcr); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hcb), scale_hcb); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hy), scale_hy); + isp_write_reg(dev, REG_ADDR(mrsz_ctrl), ctrl); + } else if (id == IC_MI_PATH_SELF) { + isp_write_reg(dev, REG_ADDR(srsz_scale_vc), scale_vc); + isp_write_reg(dev, REG_ADDR(srsz_scale_vy), scale_vy); + isp_write_reg(dev, REG_ADDR(srsz_scale_hcr), scale_hcr); + isp_write_reg(dev, REG_ADDR(srsz_scale_hcb), scale_hcb); + isp_write_reg(dev, REG_ADDR(srsz_scale_hy), scale_hy); + isp_write_reg(dev, REG_ADDR(srsz_ctrl), ctrl); + } else if (id == IC_MI_PATH_SELF2) { + isp_write_reg(dev, REG_ADDR(srsz2_scale_vc), scale_vc); + isp_write_reg(dev, REG_ADDR(srsz2_scale_vy), scale_vy); + isp_write_reg(dev, REG_ADDR(srsz2_scale_hcr), scale_hcr); + isp_write_reg(dev, REG_ADDR(srsz2_scale_hcb), scale_hcb); + isp_write_reg(dev, REG_ADDR(srsz2_scale_hy), scale_hy); + isp_write_reg(dev, REG_ADDR(srsz2_ctrl), ctrl); + } + + return 0; +} + +typedef struct isp_crop_reg_s { + u32 crop_ctrl_addr; + u32 crop_x_dir_addr; + u32 crop_y_dir_addr; +} isp_crop_reg_t; + +int isp_set_crop(struct isp_ic_dev *dev) +{ + long ret = 0; + u32 crop_ctrl, crop_x_dir, crop_y_dir; + u8 i; + + isp_crop_reg_t crop_reg[ISP_MI_PATH_SP2_BP + 1] = { + { + REG_ADDR(mrsz_ctrl), + REG_ADDR(mrsz_phase_crop_x), + REG_ADDR(mrsz_phase_crop_y) + }, + { + REG_ADDR(srsz_ctrl), + REG_ADDR(srsz_phase_crop_x), + REG_ADDR(srsz_phase_crop_y) + }, + { + REG_ADDR(srsz2_ctrl), + REG_ADDR(srsz2_phase_crop_x), + REG_ADDR(srsz2_phase_crop_y) + } + }; + + struct isp_crop_context *crop = dev->crop; + for ( i = 0; i <= ISP_MI_PATH_SP2_BP; i++) { + crop_ctrl = isp_read_reg(dev, crop_reg[i].crop_ctrl_addr); + crop_x_dir = isp_read_reg(dev, crop_reg[i].crop_x_dir_addr); + crop_y_dir = isp_read_reg(dev, crop_reg[i].crop_y_dir_addr); + if (!crop[i].enabled) { +#ifndef ISP8000NANO_BASE + REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 0); +#endif + isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl); + continue; + } + REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_START, crop[i].window.x); + REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_START, crop[i].window.y); + REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_END, crop[i].window.width + crop[i].window.x - 1); //x_end = x + width -1 + REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_END, crop[i].window.height + crop[i].window.y - 1); //y_end = y + height -1 + +#ifndef ISP8000NANO_BASE + REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 1); + /*Need to update immediately*/ + REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CFG_UPD, 1); +#endif + + isp_write_reg(dev, crop_reg[i].crop_x_dir_addr, crop_x_dir); + isp_write_reg(dev, crop_reg[i].crop_y_dir_addr, crop_y_dir); + isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl); + + } + return ret; +} + +int isp_ioc_g_feature(struct isp_ic_dev *dev, void __user *args) +{ + u32 val = 0; + +#ifdef ISP_EE_RY + val |= ISP_EE_SUPPORT; +#endif +#ifdef ISP_WDR3 + val |= ISP_WDR3_SUPPORT; +#endif +#ifdef ISP_2DNR + val |= ISP_2DNR_SUPPORT; +#endif +#ifdef ISP_3DNR + val |= ISP_3DNR_SUPPORT; +#endif +#ifdef ISP_WDR_V3 + val |= ISP_WDR3_SUPPORT; +#endif +#ifdef ISP_MIV2_RY + val |= ISP_MIV2_SUPPORT; +#endif +#ifdef ISP_AEV2_RY + val |= ISP_AEV2_SUPPORT; +#endif +#ifdef ISP_HDR_STITCH_RY + val |= ISP_HDR_STITCH_SUPPORT; +#endif + viv_check_retval(copy_to_user(args, &val, sizeof(val))); + + return 0; +} + +int isp_ioc_g_feature_veresion(struct isp_ic_dev *dev, void __user *args) +{ + u32 val = 0; + + /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */ + viv_check_retval(copy_to_user(args, &val, sizeof(val))); + + return 0; +} + +static long isp_get_extmem(struct isp_ic_dev *dev, void __user *args) +{ + #define UT_USED_SIZE 0x01000000 + long ret = 0; + struct isp_extmem_info ext_mem; + dev->ut_addr = dma_alloc_coherent(dev->device, UT_USED_SIZE, &dev->ut_phy_addr, GFP_KERNEL); + if (dev->ut_addr != NULL) { + ext_mem.addr = dev->ut_phy_addr; + ext_mem.size = UT_USED_SIZE; + } else { + return -1; + } + ret = copy_to_user(args, &ext_mem, sizeof(struct isp_extmem_info)); + return ret; +} + +long isp_priv_ioctl(struct isp_ic_dev *dev, unsigned int cmd, void __user *args) +{ + int ret = -1; + if (!dev) { + return ret; + } + /*pr_info("ry [%s:%d]cmd 0x%08x\n", __func__, __LINE__, cmd);*/ + switch (cmd) { + case ISPIOC_RESET: + if((ret = isp_mi_stop(dev)) != 0 ) + { + pr_err("[%s:%d]stop mi error before resetting!\n", __func__, __LINE__); + break; + } + if((ret = isp_stop_stream(dev)) != 0) + { + pr_err("[%s:%d]stop isp stream before resetting!\n", __func__, __LINE__); + break; + } + ret = isp_reset(dev); + break; + + case ISPIOC_WRITE_REG: + ret = isp_ioc_write_reg(dev, args); + break; + case ISPIOC_READ_REG: + ret = isp_ioc_read_reg(dev, args); + break; + case ISPIOC_GET_MIS: + ret = isp_ioc_read_mis(dev, args); + break; + case ISPIOC_ENABLE_TPG: + ret = isp_enable_tpg(dev); + break; + case ISPIOC_DISABLE_TPG: + ret = isp_disable_tpg(dev); + break; + case ISPIOC_ENABLE_BLS: + ret = isp_enable_bls(dev); + break; + case ISPIOC_DISABLE_BLS: + ret = isp_disable_bls(dev); + break; + case ISPIOC_START_DMA_READ: + ret = isp_ioc_start_dma_read(dev, args); + break; + case ISPIOC_CFG_DMA: + ret = isp_ioc_cfg_dma(dev, args); + break; + case ISPIOC_MI_STOP: + ret = isp_mi_stop(dev); + break; + case ISPIOC_DISABLE_ISP_OFF: + ret = isp_ioc_disable_isp_off(dev, args); + break; + case ISPIOC_ISP_STOP: + ret = isp_stop_stream(dev); + if(!ret) { + dev->streaming = false; + } + break; + case ISPIOC_ENABLE: + ret = isp_enable(dev); + break; + case ISPIOC_DISABLE: + ret = isp_disable(dev); + break; + case ISPIOC_ISP_STATUS:{ + bool enable = is_isp_enable(dev); + viv_check_retval(copy_to_user + (args, &enable, sizeof(bool))); + ret = 0; + break; + } + case ISPIOC_ENABLE_LSC: + ret = isp_enable_lsc(dev); + break; + case ISPIOC_DISABLE_LSC: + ret = isp_disable_lsc(dev); + break; + case ISPIOC_S_DIGITAL_GAIN: + viv_check_retval(copy_from_user + (&dev->dgain, args, sizeof(dev->dgain))); + ret = isp_s_digital_gain(dev); + break; +#ifdef ISP_DEMOSAIC2_RY + case ISPIOC_S_DMSC_INTP: + viv_check_retval(copy_from_user + (&dev->demosaic.intp, args, + sizeof(dev->demosaic.intp))); + ret = isp_set_dmsc_intp(dev); + break; + case ISPIOC_S_DMSC_DMOI: + viv_check_retval(copy_from_user + (&dev->demosaic.demoire, args, + sizeof(dev->demosaic.demoire))); + ret = isp_set_dmsc_dmoi(dev); + break; + case ISPIOC_S_DMSC_SKIN: + viv_check_retval(copy_from_user + (&dev->demosaic.skin, args, + sizeof(dev->demosaic.skin))); + ret = isp_set_dmsc_skin(dev); + break; + case ISPIOC_S_DMSC_SHAP: + viv_check_retval(copy_from_user + (&dev->demosaic.sharpen, args, + sizeof(dev->demosaic.sharpen))); + ret = isp_set_dmsc_sharpen(dev); + break; + case ISPIOC_S_DMSC_SHAP_LINE: + viv_check_retval(copy_from_user + (&dev->demosaic.sharpenLine, args, + sizeof(dev->demosaic.sharpenLine))); + ret = isp_set_dmsc_sharpen_line(dev); + break; + case ISPIOC_S_DMSC_CAC: + viv_check_retval(copy_from_user + (&dev->cac, args, sizeof(dev->cac))); + + ret = isp_set_dmsc_cac(dev); + break; + case ISPIOC_S_DMSC_DEPURPLE: + viv_check_retval(copy_from_user + (&dev->demosaic.depurple, args, + sizeof(dev->demosaic.depurple))); + ret = isp_set_dmsc_depurple(dev); + break; + case ISPIOC_S_DMSC_GFILTER: + viv_check_retval(copy_from_user + (&dev->demosaic.gFilter, args, + sizeof(dev->demosaic.gFilter))); + ret = isp_set_dmsc_gfilter(dev); + break; + case ISPIOC_S_DMSC: + viv_check_retval(copy_from_user + (&dev->demosaic, args, sizeof(dev->demosaic))); + ret = isp_s_dmsc(dev); + break; +#endif + case ISPIOC_ENABLE_AWB: + ret = isp_enable_awb(dev); + break; + case ISPIOC_DISABLE_AWB: + ret = isp_disable_awb(dev); + break; + case ISPIOC_ENABLE_WB: + ret = isp_enable_wb(dev, 1); + break; + case ISPIOC_DISABLE_WB: + ret = isp_enable_wb(dev, 0); + break; + case ISPIOC_ENABLE_GAMMA_OUT: + ret = isp_enable_gamma_out(dev, 1); + break; + case ISPIOC_DISABLE_GAMMA_OUT: + ret = isp_enable_gamma_out(dev, 0); + break; +#if defined(ISP_3DNR) || defined(ISP_3DNR_V2_V1) + case ISPIOC_R_3DNR: + viv_check_retval(copy_from_user + (&dev->dnr3, args, sizeof(dev->dnr3))); + ret = isp_r_3dnr(dev); + break; +#endif + case ISPIOC_S_IS: + viv_check_retval(copy_from_user + (&dev->is, args, sizeof(dev->is))); + ret = isp_s_is(dev); + break; + case ISPIOC_S_RAW_IS: + viv_check_retval(copy_from_user + (&dev->rawis, args, sizeof(dev->rawis))); + ret = isp_s_raw_is(dev); + break; + case ISPIOC_S_CC: + viv_check_retval(copy_from_user + (&dev->cc, args, sizeof(dev->cc))); + ret = isp_s_cc(dev); + break; + case ISPIOC_S_EE: + viv_check_retval(copy_from_user + (&dev->ee, args, sizeof(dev->ee))); + ret = isp_s_ee(dev); + break; + case ISPIOC_S_IE: + viv_check_retval(copy_from_user + (&dev->ie, args, sizeof(dev->ie))); + ret = isp_s_ie(dev); + break; + case ISPIOC_S_TPG: + viv_check_retval(copy_from_user + (&dev->tpg, args, sizeof(dev->tpg))); + ret = isp_s_tpg(dev); + break; + case ISPIOC_S_BLS: + viv_check_retval(copy_from_user + (&dev->bls, args, sizeof(dev->bls))); + ret = isp_s_bls(dev); + break; + case ISPIOC_BYPASS_MCM: + viv_check_retval(copy_from_user + (&dev->mcm, args, sizeof(dev->mcm))); + ret = isp_bypass_mcm(dev); + break; + case ISPIOC_S_MCM_WR: + viv_check_retval(copy_from_user + (&dev->mcm, args, sizeof(dev->mcm))); + ret = isp_s_mcm_wr(dev); + break; + case ISPIOC_S_MUX: + viv_check_retval(copy_from_user + (&dev->mux, args, sizeof(dev->mux))); + ret = isp_s_mux(dev); + break; + case ISPIOC_S_AWB: + viv_check_retval(copy_from_user + (&dev->awb, args, sizeof(dev->awb))); + ret = isp_s_awb(dev); + break; + case ISPIOC_S_LSC_TBL: + viv_check_retval(copy_from_user + (&dev->lsc, args, sizeof(dev->lsc))); + ret = isp_s_lsc_tbl(dev); + break; + case ISPIOC_S_LSC_SEC: + viv_check_retval(copy_from_user + (&dev->lsc, args, sizeof(dev->lsc))); + ret = isp_s_lsc_sec(dev); + break; + case ISPIOC_S_DPF: + viv_check_retval(copy_from_user + (&dev->dpf, args, sizeof(dev->dpf))); + ret = isp_s_dpf(dev); + break; + case ISPIOC_S_EXP: + viv_check_retval(copy_from_user + (&dev->exp, args, sizeof(dev->exp))); + ret = isp_s_exp(dev); + break; + case ISPIOC_S_HDREXP: + viv_check_retval(copy_from_user + (&dev->hdrexp, args, sizeof(dev->hdrexp))); + ret = isp_s_hdrexp(dev); + break; + case ISPIOC_S_CNR: + viv_check_retval(copy_from_user + (&dev->cnr, args, sizeof(dev->cnr))); + ret = isp_s_cnr(dev); + break; + case ISPIOC_S_FLT: + { + viv_check_retval(copy_from_user + (&dev->flt, args, sizeof(dev->flt))); + ret = isp_s_flt(dev); + + break; + } + case ISPIOC_S_CAC: + viv_check_retval(copy_from_user + (&dev->cac, args, sizeof(dev->cac))); + ret = isp_s_cac(dev); + break; + case ISPIOC_S_DEG: + viv_check_retval(copy_from_user + (&dev->deg, args, sizeof(dev->deg))); + ret = isp_s_deg(dev); + break; + case ISPIOC_S_VSM: + viv_check_retval(copy_from_user + (&dev->vsm, args, sizeof(dev->vsm))); + ret = isp_s_vsm(dev); + break; + case ISPIOC_S_AFM: + viv_check_retval(copy_from_user + (&dev->afm, args, sizeof(dev->afm))); + ret = isp_s_afm(dev); + break; + case ISPIOC_S_HDR: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + ret = isp_s_hdr(dev); + break; + case ISPIOC_ENABLE_HDR: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + ret = isp_enable_hdr(dev); + break; + case ISPIOC_DISABLE_HDR: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + ret = isp_disable_hdr(dev); + break; + case ISPIOC_S_HIST: + viv_check_retval(copy_from_user + (&dev->hist, args, sizeof(dev->hist))); + ret = isp_s_hist(dev); + break; + case ISPIOC_S_HDRHIST: + viv_check_retval(copy_from_user + (&dev->hdrhist, args, sizeof(dev->hdrhist))); + ret = isp_s_hdrhist(dev); + break; +#ifdef ISP_HIST64_RY + case ISPIOC_S_HIST64: + viv_check_retval(copy_from_user + (&dev->hist64, args, sizeof(dev->hist64))); + ret = isp_s_hist64(dev); + break; + case ISPIOC_U_HIST64: + viv_check_retval(copy_from_user + (&dev->hist64, args, sizeof(dev->hist64))); + ret = isp_update_hist64(dev); + break; +#endif + case ISPIOC_S_DPCC: + viv_check_retval(copy_from_user + (&dev->dpcc, args, sizeof(dev->dpcc))); + ret = isp_s_dpcc(dev); + break; + case ISPIOC_ENABLE_WDR3: + ret = isp_enable_wdr3(dev); + break; + case ISPIOC_DISABLE_WDR3: + ret = isp_disable_wdr3(dev); + break; + case ISPIOC_U_WDR3: + viv_check_retval(copy_from_user + (&dev->wdr3, args, sizeof(dev->wdr3))); + ret = isp_u_wdr3(dev); + break; + case ISPIOC_S_WDR3: + viv_check_retval(copy_from_user + (&dev->wdr3, args, sizeof(dev->wdr3))); + ret = isp_s_wdr3(dev); + break; +#ifdef ISP_WDR_V4 + case ISPIOC_ENABLE_WDR4: + ret = isp_enable_wdr4(dev); + break; + case ISPIOC_DISABLE_WDR4: + ret = isp_disable_wdr4(dev); + break; + case ISPIOC_U_WDR4: + viv_check_retval(copy_from_user + (&dev->wdr4, args, sizeof(dev->wdr4))); + ret = isp_u_wdr4(dev); + break; + case ISPIOC_S_WDR4: + viv_check_retval(copy_from_user + (&dev->wdr4, args, sizeof(dev->wdr4))); + ret = isp_s_wdr4(dev); + break; +#endif + case ISPIOC_S_EXP2: + viv_check_retval(copy_from_user + (&dev->exp2, args, sizeof(dev->exp2))); + ret = isp_s_exp2(dev); + break; + case ISPIOC_S_EXP2_INPUTSEL: + viv_check_retval(copy_from_user + (&dev->exp2.input_select, args, + sizeof(dev->exp2.input_select))); + ret = isp_s_exp2_inputsel(dev); + break; + case ISPIOC_S_EXP2_SIZERATIO: { + u32 ratio; + viv_check_retval(copy_from_user(&ratio, args, sizeof(ratio))); + ret = isp_s_exp2_sizeratio(dev, ratio); + break; + } + case ISPIOC_S_2DNR: + viv_check_retval(copy_from_user + (&dev->dnr2, args, sizeof(dev->dnr2))); + ret = isp_s_2dnr(dev); + break; + case ISPIOC_S_SIMP: + viv_check_retval(copy_from_user + (&dev->simp, args, sizeof(dev->simp))); + ret = isp_s_simp(dev); + break; + case ISPIOC_S_COMP: + viv_check_retval(copy_from_user + (&dev->comp, args, sizeof(dev->comp))); + ret = isp_s_comp(dev); + break; + case ISPIOC_S_CPROC: + viv_check_retval(copy_from_user + (&dev->cproc, args, sizeof(dev->cproc))); + ret = isp_s_cproc(dev); + break; + case ISPIOC_S_XTALK: + viv_check_retval(copy_from_user + (&dev->xtalk, args, sizeof(dev->xtalk))); + ret = isp_s_xtalk(dev); + break; + case ISPIOC_S_ELAWB: + viv_check_retval(copy_from_user + (&dev->elawb, args, sizeof(dev->elawb))); + ret = isp_s_elawb(dev); + break; + case ISPIOC_S_INPUT: + viv_check_retval(copy_from_user + (&dev->ctx, args, sizeof(dev->ctx))); + ret = isp_s_input(dev); + break; + case ISPIOC_S_DEMOSAIC: + viv_check_retval(copy_from_user + (&dev->ctx, args, sizeof(dev->ctx))); + ret = isp_s_demosaic(dev); + break; + case ISPIOC_MI_START: + viv_check_retval(copy_from_user + (&dev->mi, args, sizeof(dev->mi))); + ret = isp_mi_start(dev); + break; + case ISPIOC_S_HDR_WB: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + ret = isp_s_hdr_wb(dev); + break; + case ISPIOC_S_HDR_BLS: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + ret = isp_s_hdr_bls(dev); + break; + case ISPIOC_S_HDR_DIGITAL_GAIN: + viv_check_retval(copy_from_user + (&dev->hdr, args, sizeof(dev->hdr))); + // ret = isp_s_hdr_digal_gain(dev); + break; + case ISPIOC_S_GAMMA_OUT:{ + viv_check_retval(copy_from_user + (&dev->gamma_out, args, + sizeof(dev->gamma_out))); + ret = isp_s_gamma_out(dev); + break; + } + case ISPIOC_SET_BUFFER:{ + struct isp_buffer_context buf; + viv_check_retval(copy_from_user + (&buf, args, sizeof(buf))); +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + if (dev->alloc) + ret = dev->alloc(dev, &buf); +#else + ret = isp_set_buffer(dev, &buf); +#endif + break; + } + case ISPIOC_SET_BP_BUFFER:{ + struct isp_bp_buffer_context buf; + viv_check_retval(copy_from_user + (&buf, args, sizeof(buf))); + ret = isp_set_bp_buffer(dev, &buf); + break; + } + case ISPIOC_START_CAPTURE:{ + u32 num; + viv_check_retval(copy_from_user + (&num, args, sizeof(num))); + ret = isp_start_stream(dev, num); + if(!ret) { + dev->streaming = true; + } + break; + } +#if defined(ISP_3DNR_V2) || defined(ISP_3DNR_V2_V1) + case ISPIOC_S_3DNR_CMP: { + viv_check_retval( + copy_from_user(&dev->dnr3.compress, args, sizeof(dev->dnr3.compress))); + ret = isp_s_3dnr_cmp(dev); + break; + } +#endif +#if defined(ISP_3DNR) || defined(ISP_3DNR_V2) + case ISPIOC_U_3DNR:{ + struct isp_3dnr_update param; + viv_check_retval(copy_from_user + (¶m, args, sizeof(param))); + ret = isp_u_3dnr(dev, ¶m); + break; + } + case ISPIOC_S_3DNR: + viv_check_retval(copy_from_user + (&dev->dnr3, args, sizeof(dev->dnr3))); + ret = isp_s_3dnr(dev); + break; + case ISPIOC_U_3DNR_STRENGTH: { + viv_check_retval( + copy_from_user(&dev->dnr3, args, sizeof(dev->dnr3))); + ret = isp_u_3dnr_strength(dev); + break; + } + case ISPIOC_S_3DNR_MOT:{ + viv_check_retval(copy_from_user + (&dev->dnr3, args, sizeof(dev->dnr3))); + ret = isp_s_3dnr_motion(dev); + break; + } + case ISPIOC_S_3DNR_DLT:{ + viv_check_retval(copy_from_user + (&dev->dnr3, args, sizeof(dev->dnr3))); + + ret = isp_s_3dnr_delta(dev); + break; + } + case ISPIOC_G_3DNR:{ + u32 avg; + ret = isp_g_3dnr(dev, &avg); + viv_check_retval(copy_to_user(args, &avg, sizeof(avg))); + break; + } +#endif + case ISPIOC_G_AWBMEAN:{ + struct isp_awb_mean mean; + ret = isp_g_awbmean(dev, &mean); + viv_check_retval(copy_to_user + (args, &mean, sizeof(mean))); + break; + } + case ISPIOC_G_EXPMEAN:{ + u8 mean[25]; + ret = isp_g_expmean(dev, mean); + viv_check_retval(copy_to_user + (args, mean, sizeof(mean))); + break; + } + case ISPIOC_G_HDREXPMEAN:{ + u8 mean[75]; + ret = isp_g_hdrexpmean(dev, mean); + viv_check_retval(copy_to_user + (args, mean, sizeof(mean))); + break; + } + case ISPIOC_G_HISTMEAN:{ + u32 mean[HIST_BIN_TOTAL]; + ret = isp_g_histmean(dev, mean); + viv_check_retval(copy_to_user + (args, mean, sizeof(mean))); + break; + } + case ISPIOC_G_HDRHISTMEAN:{ + u32 mean[48]; + ret = isp_g_hdrhistmean(dev, mean); + viv_check_retval(copy_to_user + (args, mean, sizeof(mean))); + break; + } +#ifdef ISP_HIST64_RY + case ISPIOC_G_HIST64MEAN:{ + u32 mean[HIST64_BIN_TOTAL]; + ret = isp_g_hist64mean(dev, mean); + viv_check_retval(copy_to_user + (args, mean, sizeof(mean))); + break; + } + case ISPIOC_G_HIST64VSTART_STATUS:{ + u32 status = 0; + ret = isp_g_hist64_vstart_status(dev, &status); + viv_check_retval(copy_to_user + (args, &status, sizeof(status))); + break; + } +#endif + case ISPIOC_G_VSM:{ + struct isp_vsm_result vsm; + ret = isp_g_vsm(dev, &vsm); + viv_check_retval(copy_to_user(args, &vsm, sizeof(vsm))); + break; + } + case ISPIOC_G_AFM:{ + struct isp_afm_result afm; + ret = isp_g_afm(dev, &afm); + viv_check_retval(copy_to_user(args, &afm, sizeof(afm))); + break; + } + case ISPIOC_G_STATUS: + ret = isp_ioc_g_status(dev, args); + break; + case ISPIOC_G_FEATURE: + ret = isp_ioc_g_feature(dev, args); + break; + case ISPIOC_G_FEATURE_VERSION: + ret = isp_ioc_g_feature_veresion(dev, args); + break; + case ISPIOC_WDR_CONFIG: + viv_check_retval(copy_from_user + (&dev->wdr, args, sizeof(dev->wdr))); + ret = isp_s_wdr(dev); + break; + case ISPIOC_S_WDR_CURVE: + viv_check_retval(copy_from_user + (&dev->wdr, args, sizeof(dev->wdr))); + ret = isp_s_wdr_curve(dev); + break; + case ISPIOC_ENABLE_GCMONO: + viv_check_retval(copy_from_user + (&dev->gcmono.mode, args, sizeof(u32))); + ret = isp_enable_gcmono(dev); + break; + case ISPIOC_DISABLE_GCMONO: + ret = isp_disable_gcmono(dev); + break; + case ISPIOC_S_GCMONO:{ + struct isp_gcmono_data *data; +#ifdef __KERNEL__ + data = (struct isp_gcmono_data *) + kmalloc(sizeof(struct isp_gcmono_data), GFP_KERNEL); +#else + data = (struct isp_gcmono_data *) + malloc(sizeof(struct isp_gcmono_data)); +#endif + if (data == NULL) { + isp_err("%s, malloc mem for rgb gamma failed.", __func__); + ret = -1; + } else { + viv_check_retval(copy_from_user + (data, args, + sizeof(struct + isp_gcmono_data))); + ret = isp_s_gcmono(dev, data); +#ifdef __KERNEL__ + kfree(data); +#else + free(data); +#endif + + } + break; + } + case ISPIOC_ENABLE_RGBGAMMA: + ret = isp_enable_rgbgamma(dev); + break; + case ISPIOC_DISABLE_RGBGAMMA: + ret = isp_disable_rgbgamma(dev); + break; + case ISPIOC_S_RGBGAMMA:{ + struct isp_rgbgamma_data *data; +#ifdef __KERNEL__ + data = (struct isp_rgbgamma_data *) + kmalloc(sizeof(struct isp_rgbgamma_data), + GFP_KERNEL); +#else + data = (struct isp_rgbgamma_data *) + malloc(sizeof(struct isp_rgbgamma_data)); +#endif + if (data == NULL) { + isp_err("%s, malloc mem for rgb gamma failed.", __func__); + ret = -1; + } else { + viv_check_retval(copy_from_user + (data, args, + sizeof(struct + isp_rgbgamma_data))); + ret = isp_s_rgbgamma(dev, data); +#ifdef __KERNEL__ + kfree(data); +#else + free(data); +#endif + } + break; + } + case ISPIOC_S_GREENEQUILIBRATE: + viv_check_retval(copy_from_user + (&dev->ge, args, sizeof(dev->ge))); + ret = isp_s_ge(dev); + break; + case ISPIOC_S_COLOR_ADJUST: + viv_check_retval(copy_from_user + (&dev->ca, args, sizeof(dev->ca))); + ret = isp_s_ca(dev); + break; +#ifdef __KERNEL__ + case VIDIOC_QUERYCAP: + ret = isp_ioc_qcap(dev, args); + break; +#endif + case ISPIOC_G_QUERY_EXTMEM: + ret = isp_get_extmem(dev, args); + break; + case ISPIOC_ENABLE_RGBIR: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_enable_rgbir(dev); + break; + case ISPIOC_S_RGBIR: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_s_rgbir(dev); + break; + case ISPIOC_RGBIR_HW_INIT: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_hw_init(dev); + break; + case ISPIOC_RGBIR_S_IR_DNR: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_ir_dnr(dev); + break; + case ISPIOC_RGBIR_S_SHARPEN: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_sharpen(dev); + break; + case ISPIOC_RGBIR_S_DES: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_des(dev); + break; + case ISPIOC_RGBIR_S_CC_MATRIX: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_cc_matrix(dev); + break; + case ISPIOC_RGBIR_S_DPCC: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_dpcc(dev); + break; + case ISPIOC_RGBIR_S_GAIN: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_gain(dev); + break; + case ISPIOC_RGBIR_S_BLS: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_s_bls(dev); + break; + case ISPIOC_RGBIR_S_IR_RAW_OUT: + viv_check_retval(copy_from_user + (&dev->rgbir, args, sizeof(dev->rgbir))); + ret = isp_rgbir_out_ir_raw(dev); + break; + case ISPIOC_S_CROP: + viv_check_retval(copy_from_user + (&dev->crop, args, sizeof(struct isp_crop_context) * 3)); + ret = isp_set_crop(dev); + break; +#ifdef ISP_3DNR_V3 + case ISPIOC_S_TDNR: + viv_check_retval(copy_from_user + (&dev->tdnr, args, sizeof(dev->tdnr))); + ret = isp_s_tdnr(dev); + break; + case ISPIOC_TDNR_ENABLE: + ret = isp_tdnr_enable(dev); + break; + case ISPIOC_TDNR_DISABLE: + ret = isp_tdnr_disable(dev); + break; + case ISPIOC_TDNR_ENABLE_TDNR: + ret = isp_tdnr_enable_tdnr(dev); + break; + case ISPIOC_TDNR_DISABLE_TDNR: + ret = isp_tdnr_disable_tdnr(dev); + break; + case ISPIOC_TDNR_ENABLE_2DNR: + ret = isp_tdnr_enable_2dnr(dev); + break; + case ISPIOC_TDNR_DISABLE_2DNR: + ret = isp_tdnr_disable_2dnr(dev); + break; + case ISPIOC_S_TDNR_CURVE: + viv_check_retval(copy_from_user + (&dev->tdnr.curve, args, sizeof(dev->tdnr.curve))); + ret = isp_tdnr_cfg_gamma(dev); + break; + case ISPIOC_G_TDNR: { + struct isp_tdnr_stats stats; + ret = isp_tdnr_g_stats(dev, &stats); + viv_check_retval(copy_to_user(args, &stats, sizeof(stats))); + } + break; + case ISPIOC_S_TDNR_STRENGTH: + viv_check_retval(copy_from_user + (&dev->tdnr, args, sizeof(dev->tdnr))); + ret = isp_tdnr_set_strength(dev); + break; + case ISPIOC_U_TDNR_NOISE: + viv_check_retval(copy_from_user + (&dev->tdnr, args, sizeof(dev->tdnr))); + ret = isp_tdnr_u_noise(dev); + break; + case ISPIOC_U_TDNR_THR: + viv_check_retval(copy_from_user + (&dev->tdnr, args, sizeof(dev->tdnr))); + ret = isp_tdnr_u_thr(dev); + break; + case ISPIOC_R_TDNR_REFER: + ret = isp_r_tdnr_refer(dev); + break; + case ISPIOC_R_TDNR_MOTION: + ret = isp_r_tdnr_motion(dev); + break; + case ISPIOC_S_TDNR_BUF: + viv_check_retval(copy_from_user + (&dev->tdnr.buf, args, sizeof(dev->tdnr.buf))); + ret = isp_tdnr_s_buf(dev); + break; +#endif +#ifdef ISP_MI_PP_WRITE_RY + case ISPIOC_GET_PPW_LINE_CNT: + { + u16 ppw_pic_cnt; + ret = isp_get_ppw_pic_cnt(dev, &ppw_pic_cnt); + viv_check_retval(copy_to_user + (args, &ppw_pic_cnt, sizeof(ppw_pic_cnt))); + + break; + } + case ISPIOC_SET_PPW_LINE_NUM: + { + viv_check_retval(copy_from_user + (&dev->pp_write, args, sizeof(dev->pp_write))); + ret = isp_set_ppw_line_num(dev); + break; + } +#endif + +#ifdef ISP_MI_PP_READ_RY + case ISPIOC_CFG_DMA_LINE_ENTRY: + viv_check_retval(copy_from_user + (&dev->pp_dma_line_entry, args, sizeof(dev->pp_dma_line_entry))); + ret = isp_cfg_pp_dma_line_entry(dev); + break; +#endif + default: + isp_err("unsupported command %d", cmd); + break; + } + if (cmd != ISPIOC_WRITE_REG) //frame end isp update shd registers. + ISP_GEN_CFG_UPDATE(dev); + return ret; +} diff --git a/vvcam_ry/isp/isp_ioctl.h b/vvcam_ry/isp/isp_ioctl.h new file mode 100755 index 0000000..523ec50 --- /dev/null +++ b/vvcam_ry/isp/isp_ioctl.h @@ -0,0 +1,431 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_IOC_H_ +#define _ISP_IOC_H_ +#include "ic_dev.h" +#include +//#define POST_ISP_SDK_TEST +enum { + ISPIOC_RESET = 0x100, + ISPIOC_WRITE_REG = 0x101, + ISPIOC_READ_REG = 0x102, + ISPIOC_S_INPUT = 0x103, + ISPIOC_ENABLE = 0x104, + ISPIOC_DISABLE = 0x105, + ISPIOC_ISP_STATUS = 0x106, + ISPIOC_ISP_STOP = 0x107, + ISPIOC_START_CAPTURE = 0x108, + ISPIOC_DISABLE_ISP_OFF = 0x109, + ISPIOC_SET_BUFFER = 0x10A, + ISPIOC_SET_BP_BUFFER = 0x10B, + ISPIOC_START_DMA_READ = 0x10C, + ISPIOC_MI_START = 0x10D, + ISPIOC_MI_STOP = 0x10E, + ISPIOC_ENABLE_TPG = 0x10F, + ISPIOC_DISABLE_TPG = 0x110, + ISPIOC_S_TPG = 0x111, + ISPIOC_S_MCM_WR = 0x112, + ISPIOC_ENABLE_BLS = 0x113, + ISPIOC_DISABLE_BLS = 0x114, + ISPIOC_S_BLS = 0x115, + ISPIOC_S_MUX = 0x116, + ISPIOC_ENABLE_AWB = 0x117, + ISPIOC_DISABLE_AWB = 0x118, + ISPIOC_S_AWB = 0x119, + ISPIOC_G_AWBMEAN = 0x11A, + ISPIOC_S_IS = 0x11B, + ISPIOC_S_RAW_IS = 0x11C, + ISPIOC_S_CNR = 0x11D, + ISPIOC_S_CC = 0x11E, + ISPIOC_S_XTALK = 0x11F, + ISPIOC_S_GAMMA_OUT = 0x120, + ISPIOC_ENABLE_LSC = 0x121, + ISPIOC_DISABLE_LSC = 0x122, + ISPIOC_S_LSC_TBL = 0x123, + ISPIOC_S_LSC_SEC = 0x124, + ISPIOC_S_DPF = 0x125, + ISPIOC_S_EE = 0x126, + ISPIOC_S_EXP = 0x127, + ISPIOC_S_HDREXP = 0x128, + ISPIOC_G_EXPMEAN = 0x129, + ISPIOC_G_HDREXPMEAN = 0x12A, + ISPIOC_S_HIST = 0x12B, + ISPIOC_G_HISTMEAN = 0x12C, + ISPIOC_S_HDRHIST = 0x12D, + ISPIOC_G_HDRHISTMEAN = 0x12E, + ISPIOC_S_HIST64 = 0x12F, + ISPIOC_G_HIST64MEAN = 0x130, + ISPIOC_G_HIST64VSTART_STATUS= 0x131, + ISPIOC_U_HIST64 = 0x132, + ISPIOC_S_DPCC = 0x133, + ISPIOC_S_FLT = 0x134, + ISPIOC_S_CAC = 0x135, + ISPIOC_S_DEG = 0x136, + ISPIOC_S_AFM = 0x137, + ISPIOC_G_AFM = 0x138, + ISPIOC_S_VSM = 0x139, + ISPIOC_G_VSM = 0x13A, + ISPIOC_S_IE = 0x13B, + ISPIOC_ENABLE_WDR3 = 0x13C, + ISPIOC_DISABLE_WDR3 = 0x13D, + ISPIOC_U_WDR3 = 0x13E, + ISPIOC_S_WDR3 = 0x13F, + ISPIOC_S_EXP2 = 0x140, + ISPIOC_S_EXP2_INPUTSEL = 0x141, + ISPIOC_S_EXP2_SIZERATIO = 0x142, + ISPIOC_S_2DNR = 0x143, + ISPIOC_S_3DNR = 0x144, + ISPIOC_G_3DNR = 0x145, /* get last avg */ + ISPIOC_U_3DNR = 0x146, /* update */ + ISPIOC_R_3DNR = 0x147, /* read back 3dnr reference image. */ + ISPIOC_S_3DNR_CMP = 0x148, /*config 3dnr compress */ + ISPIOC_U_3DNR_STRENGTH = 0x149, + ISPIOC_S_3DNR_MOT = 0x14A, /*config 3dnr motion*/ + ISPIOC_S_3DNR_DLT = 0x14B,/*config 3dnr delta*/ + ISPIOC_S_HDR = 0x14C, + ISPIOC_S_COMP = 0x14D, + ISPIOC_S_CPROC = 0x14E, + ISPIOC_S_SIMP = 0x14F, + ISPIOC_S_ELAWB = 0x150, + ISPIOC_S_HDR_WB = 0x151, + ISPIOC_S_HDR_BLS = 0x152, + ISPIOC_S_HDR_DIGITAL_GAIN = 0x153, + ISPIOC_ENABLE_WB = 0x154, + ISPIOC_DISABLE_WB = 0x155, + ISPIOC_DISABLE_HDR = 0x156, + ISPIOC_ENABLE_HDR = 0x157, + ISPIOC_ENABLE_GAMMA_OUT = 0x158, + ISPIOC_DISABLE_GAMMA_OUT = 0x159, + ISPIOC_G_STATUS = 0x15A, + ISPIOC_G_FEATURE = 0x15B, + ISPIOC_G_FEATURE_VERSION = 0x15C, + ISPIOC_ENABLE_GCMONO = 0x15D, + ISPIOC_DISABLE_GCMONO = 0x15E, + ISPIOC_S_GCMONO = 0x15F, + ISPIOC_ENABLE_RGBGAMMA = 0x160, + ISPIOC_DISABLE_RGBGAMMA = 0x161, + ISPIOC_S_RGBGAMMA = 0x162, + ISPIOC_S_DEMOSAIC = 0x163, + ISPIOC_S_DMSC_INTP = 0x164, + ISPIOC_S_DMSC_DMOI = 0x165, + ISPIOC_S_DMSC_SKIN = 0x166, + ISPIOC_S_DMSC_CAC = 0x167, + ISPIOC_S_DMSC_SHAP = 0x168, + ISPIOC_S_DMSC_SHAP_LINE = 0x169, + ISPIOC_S_DMSC_DEPURPLE = 0x16A, + ISPIOC_S_DMSC_GFILTER = 0x16B, + ISPIOC_S_DMSC = 0x16C, + ISPIOC_S_GREENEQUILIBRATE = 0x16D, + ISPIOC_S_COLOR_ADJUST = 0x16E, + ISPIOC_S_DIGITAL_GAIN = 0x16F, + ISPIOC_G_QUERY_EXTMEM = 0x170, +#ifdef ISP_WDR_V4 + ISPIOC_ENABLE_WDR4 = 0x171, + ISPIOC_DISABLE_WDR4 = 0x172, + ISPIOC_U_WDR4 = 0x173, + ISPIOC_S_WDR4 = 0x174, +#endif + ISPIOC_WDR_CONFIG = 0x175, + ISPIOC_S_WDR_CURVE = 0x176, + ISPIOC_ENABLE_RGBIR = 0x177, + ISPIOC_S_RGBIR = 0x178, + ISPIOC_RGBIR_HW_INIT = 0x179, + ISPIOC_RGBIR_S_IR_DNR = 0x17A, + ISPIOC_RGBIR_S_SHARPEN = 0x17B, + ISPIOC_RGBIR_S_DES = 0x17C, + ISPIOC_RGBIR_S_CC_MATRIX = 0x17D, + ISPIOC_RGBIR_S_DPCC = 0x17E, + ISPIOC_RGBIR_S_GAIN = 0x17F, + ISPIOC_RGBIR_S_BLS = 0x180, + ISPIOC_RGBIR_S_IR_RAW_OUT = 0x181, + ISPIOC_S_TDNR = 0x182, + ISPIOC_TDNR_ENABLE = 0x183, + ISPIOC_TDNR_DISABLE = 0x184, + ISPIOC_TDNR_ENABLE_TDNR = 0x185, + ISPIOC_TDNR_DISABLE_TDNR = 0x186, + ISPIOC_TDNR_ENABLE_2DNR = 0x187, + ISPIOC_TDNR_DISABLE_2DNR = 0x188, + ISPIOC_S_TDNR_CURVE = 0x189, + ISPIOC_G_TDNR = 0x18A, + ISPIOC_S_TDNR_STRENGTH = 0x18B, + ISPIOC_U_TDNR_NOISE = 0x18C, + ISPIOC_U_TDNR_THR = 0x18D, + ISPIOC_S_TDNR_BUF = 0x18E, // refer and motion + ISPIOC_R_TDNR_REFER = 0x18F, + ISPIOC_R_TDNR_MOTION = 0x190, + ISPIOC_GET_MIS = 0x191, + ISPIOC_CFG_DMA = 0x192, + ISPIOC_BYPASS_MCM = 0x193, + ISPIOC_SET_PPW_LINE_NUM = 0x194, + ISPIOC_GET_PPW_LINE_CNT = 0x195, + ISPIOC_CFG_DMA_LINE_ENTRY = 0x196, + ISPIOC_S_CROP = 0x197, +}; + +#define ISP_GEN_CFG_UPDATE(dev) { \ + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); \ + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); \ + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); \ + } + +#define CONFIG_VSI_ISP_DEBUG 1 +#ifdef CONFIG_VSI_ISP_DEBUG +#define isp_info(fmt, ...) pr_info(fmt, ##__VA_ARGS__) +#define isp_debug(fmt, ...) pr_debug(fmt, ##__VA_ARGS__) +#define isp_err(fmt, ...) pr_err(fmt, ##__VA_ARGS__) +#else +#define isp_info(fmt, ...) +#define isp_debug(fmt, ...) +#define isp_err(fmt, ...) pr_err(fmt, ##__VA_ARGS__) +#endif + +#define ISP_REG_GAP 4 +long isp_priv_ioctl(struct isp_ic_dev *dev, unsigned int cmd, void __user *args); +long isp_copy_data(void *dst, void *src, int size); + +/* internal functions, can called by v4l2 video device and ioctl */ +int isp_reset(struct isp_ic_dev *dev); +int isp_enable_tpg(struct isp_ic_dev *dev); +int isp_disable_tpg(struct isp_ic_dev *dev); +int isp_enable_bls(struct isp_ic_dev *dev); +int isp_disable_bls(struct isp_ic_dev *dev); +int isp_enable(struct isp_ic_dev *dev); +int isp_disable(struct isp_ic_dev *dev); +bool is_isp_enable(struct isp_ic_dev *dev); +int isp_enable_lsc(struct isp_ic_dev *dev); +int isp_disable_lsc(struct isp_ic_dev *dev); +int isp_s_input(struct isp_ic_dev *dev); +int isp_s_digital_gain(struct isp_ic_dev *dev); +int isp_s_demosaic(struct isp_ic_dev *dev); +int isp_s_tpg(struct isp_ic_dev *dev); +int isp_s_mcm_wr(struct isp_ic_dev *dev); +int isp_bypass_mcm(struct isp_ic_dev *dev); +int isp_s_mux(struct isp_ic_dev *dev); +int isp_s_bls(struct isp_ic_dev *dev); +int isp_enable_awb(struct isp_ic_dev *dev); +int isp_disable_awb(struct isp_ic_dev *dev); +int isp_s_awb(struct isp_ic_dev *dev); +int isp_g_awbmean(struct isp_ic_dev *dev, struct isp_awb_mean *mean); +int isp_s_is(struct isp_ic_dev *dev); +int isp_s_raw_is(struct isp_ic_dev *dev); +int isp_s_cnr(struct isp_ic_dev *dev); +int isp_start_stream(struct isp_ic_dev *dev, u32 framenum); +int isp_stop_stream(struct isp_ic_dev *dev); +int isp_s_cc(struct isp_ic_dev *dev); +int isp_s_xtalk(struct isp_ic_dev *dev); +int isp_enable_wb(struct isp_ic_dev *dev, bool bEnable); +int isp_enable_gamma_out(struct isp_ic_dev *dev, bool bEnable); +int isp_s_gamma_out(struct isp_ic_dev *dev); +int isp_s_lsc_sec(struct isp_ic_dev *dev); +int isp_s_lsc_tbl(struct isp_ic_dev *dev); +int isp_ioc_disable_isp_off(struct isp_ic_dev *dev, void __user *args); +int isp_s_dpf(struct isp_ic_dev *dev); +int isp_s_ee(struct isp_ic_dev *dev); +int isp_s_exp(struct isp_ic_dev *dev); +int isp_s_hdrexp(struct isp_ic_dev *dev); +int isp_g_expmean(struct isp_ic_dev *dev, u8 * mean); +int isp_g_hdrexpmean(struct isp_ic_dev *dev, u8 * mean); +int isp_s_hist(struct isp_ic_dev *dev); +int isp_g_histmean(struct isp_ic_dev *dev, u32 * mean); +int isp_s_hdrhist(struct isp_ic_dev *dev); +int isp_g_hdrhistmean(struct isp_ic_dev *dev, u32 * mean); +#ifdef ISP_HIST64_RY +int isp_s_hist64(struct isp_ic_dev *dev); +int isp_g_hist64mean(struct isp_ic_dev *dev, u32 *mean); +int isp_g_hist64_vstart(struct isp_ic_dev *dev, u32 start_line); +int isp_g_hist64_vstart_status(struct isp_ic_dev *dev, u32 *status); +int isp_update_hist64(struct isp_ic_dev *dev); +#endif +int isp_s_dpcc(struct isp_ic_dev *dev); +int isp_s_flt(struct isp_ic_dev *dev); +int isp_s_cac(struct isp_ic_dev *dev); +int isp_s_deg(struct isp_ic_dev *dev); +int isp_s_ie(struct isp_ic_dev *dev); +int isp_s_vsm(struct isp_ic_dev *dev); +int isp_g_vsm(struct isp_ic_dev *dev, struct isp_vsm_result *vsm); +int isp_s_afm(struct isp_ic_dev *dev); +int isp_g_afm(struct isp_ic_dev *dev, struct isp_afm_result *afm); +int isp_enable_wdr3(struct isp_ic_dev *dev); +int isp_disable_wdr3(struct isp_ic_dev *dev); +int isp_u_wdr3(struct isp_ic_dev *dev); +int isp_s_wdr3(struct isp_ic_dev *dev); +#ifdef ISP_WDR_V4 +int isp_enable_wdr4(struct isp_ic_dev *dev); +int isp_disable_wdr4(struct isp_ic_dev *dev); +int isp_u_wdr4(struct isp_ic_dev *dev); +int isp_s_wdr4(struct isp_ic_dev *dev); +#endif +int isp_s_exp2(struct isp_ic_dev *dev); +int isp_s_exp2_inputsel(struct isp_ic_dev *dev); +int isp_s_exp2_sizeratio(struct isp_ic_dev *dev, u32 ratio); +int isp_s_hdr(struct isp_ic_dev *dev); +int isp_s_hdr_wb(struct isp_ic_dev *dev); +int isp_s_hdr_bls(struct isp_ic_dev *dev); +//int isp_s_hdr_digal_gain(struct isp_ic_dev *dev); +int isp_enable_hdr(struct isp_ic_dev *dev); +int isp_disable_hdr(struct isp_ic_dev *dev); +int isp_s_2dnr(struct isp_ic_dev *dev); + +#if defined(ISP_3DNR) || defined(ISP_3DNR_V2) +int isp_s_3dnr(struct isp_ic_dev *dev); +int isp_g_3dnr(struct isp_ic_dev *dev, u32 * avg); +int isp_u_3dnr(struct isp_ic_dev *dev, struct isp_3dnr_update *dnr3_update); +int isp_s_3dnr_motion(struct isp_ic_dev *dev); +int isp_s_3dnr_delta(struct isp_ic_dev *dev); +#endif + +#if defined(ISP_3DNR) || defined(ISP_3DNR_V2_V1) +int isp_r_3dnr(struct isp_ic_dev *dev); +#endif +#ifdef ISP_3DNR_V2 +int isp_s_3dnr_cmp(struct isp_ic_dev *dev); +#endif +int isp_u_3dnr_strength(struct isp_ic_dev *dev); +int isp_s_comp(struct isp_ic_dev *dev); +int isp_s_simp(struct isp_ic_dev *dev); +int isp_s_cproc(struct isp_ic_dev *dev); +int isp_s_elawb(struct isp_ic_dev *dev); +int isp_ioc_qcap(struct isp_ic_dev *dev, void __user *args); +int isp_ioc_g_status(struct isp_ic_dev *dev, void __user *args); + +int isp_enable_gcmono(struct isp_ic_dev *dev); +int isp_disable_gcmono(struct isp_ic_dev *dev); +int isp_s_gcmono(struct isp_ic_dev *dev, struct isp_gcmono_data *data); /* set curve */ +int isp_enable_rgbgamma(struct isp_ic_dev *dev); +int isp_disable_rgbgamma(struct isp_ic_dev *dev); +int isp_s_rgbgamma(struct isp_ic_dev *dev, struct isp_rgbgamma_data *data); + +u32 isp_read_mi_irq(struct isp_ic_dev *dev); +void isp_reset_mi_irq(struct isp_ic_dev *dev, u32 icr); + +int isp_ioc_cfg_dma(struct isp_ic_dev *dev, void __user *args); +int isp_ioc_start_dma_read(struct isp_ic_dev *dev, void __user *args); +int isp_mi_start(struct isp_ic_dev *dev); +int isp_mi_stop(struct isp_ic_dev *dev); +int isp_set_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf); +int isp_set_bp_buffer(struct isp_ic_dev *dev, + struct isp_bp_buffer_context *buf); + +int isp_enable_dmsc(struct isp_ic_dev *dev); +int isp_disable_dmsc(struct isp_ic_dev *dev); +int isp_set_dmsc_intp(struct isp_ic_dev *dev); +int isp_set_dmsc_skin(struct isp_ic_dev *dev); +int isp_set_dmsc_gfilter(struct isp_ic_dev *dev); +int isp_set_dmsc_depurple(struct isp_ic_dev *dev); +int isp_set_dmsc_cac(struct isp_ic_dev *dev); +int isp_set_dmsc_sharpen(struct isp_ic_dev *dev); +int isp_set_dmsc_sharpen_line(struct isp_ic_dev *dev); +int isp_set_dmsc_dmoi(struct isp_ic_dev *dev); +int isp_s_dmsc(struct isp_ic_dev *dev); +int isp_s_ge(struct isp_ic_dev *dev); +int isp_s_ca(struct isp_ic_dev *dev); +int isp_s_color_adjust(struct isp_ic_dev *dev); +int isp_config_dummy_hblank(struct isp_ic_dev *dev); + +int isp_s_rgbir(struct isp_ic_dev *dev); +int isp_enable_rgbir(struct isp_ic_dev *dev); +int isp_rgbir_hw_init(struct isp_ic_dev *dev); +int isp_rgbir_s_ir_dnr(struct isp_ic_dev *dev); +int isp_rgbir_s_sharpen(struct isp_ic_dev *dev); +int isp_rgbir_s_des(struct isp_ic_dev *dev); +int isp_rgbir_s_cc_matrix(struct isp_ic_dev *dev); +int isp_rgbir_s_dpcc(struct isp_ic_dev *dev); +int isp_rgbir_s_gain(struct isp_ic_dev *dev); +int isp_rgbir_s_bls(struct isp_ic_dev *dev); +int isp_rgbir_out_ir_raw(struct isp_ic_dev *dev); + +#ifdef ISP_3DNR_V3 +int isp_tdnr_cfg_gamma(struct isp_ic_dev *dev); +int isp_s_tdnr(struct isp_ic_dev *dev); +int isp_tdnr_set_strength(struct isp_ic_dev *dev); +int isp_tdnr_set_motion(struct isp_ic_dev *dev); +int isp_tdnr_enable(struct isp_ic_dev *dev); +int isp_tdnr_disable(struct isp_ic_dev *dev); +int isp_tdnr_enable_tdnr(struct isp_ic_dev *dev); +int isp_tdnr_disable_tdnr(struct isp_ic_dev *dev); +int isp_tdnr_enable_2dnr(struct isp_ic_dev *dev); +int isp_tdnr_disable_2dnr(struct isp_ic_dev *dev); +int isp_tdnr_g_stats(struct isp_ic_dev *dev, struct isp_tdnr_stats *avg); +int isp_tdnr_u_noise(struct isp_ic_dev *dev); +int isp_r_tdnr_refer(struct isp_ic_dev *dev); +int isp_r_tdnr_motion(struct isp_ic_dev *dev); +int isp_tdnr_u_thr(struct isp_ic_dev *dev); +int isp_tdnr_s_buf(struct isp_ic_dev *dev); +#endif + +#ifdef ISP_MI_PP_WRITE_RY +int isp_set_ppw_line_num(struct isp_ic_dev *dev); +int isp_get_ppw_pic_cnt(struct isp_ic_dev *dev, u16* pic_cnt); +#endif + +#ifdef ISP_MI_PP_READ_RY +int isp_cfg_pp_dma_line_entry(struct isp_ic_dev *dev); +#endif +#ifdef __KERNEL__ +int clean_dma_buffer(struct isp_ic_dev *dev); +irqreturn_t isp_hw_isr(int irq, void *data); +void isp_clear_interrupts(struct isp_ic_dev *dev); +#endif +/*get irq mis value from store array*/ +u32 isp_read_mis(struct isp_ic_dev *dev, u32 irq_src); +int isp_ioc_read_mis(struct isp_ic_dev *dev, void __user *args); + +/*set scaler*/ +int isp_set_scaling(int id, struct isp_ic_dev *dev, bool stabilization, bool crop); +int isp_set_crop(struct isp_ic_dev *dev); + + +int isp_ioc_g_feature(struct isp_ic_dev *dev, void __user *args); +int isp_ioc_g_feature_veresion(struct isp_ic_dev *dev, void __user *args); + +#endif /* _ISP_IOC_H_ */ diff --git a/vvcam_ry/isp/isp_irq_queue.c b/vvcam_ry/isp/isp_irq_queue.c new file mode 100755 index 0000000..3b8b82e --- /dev/null +++ b/vvcam_ry/isp/isp_irq_queue.c @@ -0,0 +1,239 @@ +/**************************************************************************** + + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifdef __KERNEL__ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#else +#include +#include +#include +#endif +#include "isp_irq_queue.h" + + //enqueue +int isp_irq_enqueue(isp_mis_t *new,isp_mis_t* head) + { +#ifdef __KERNEL__ + isp_mis_t* new_node = (isp_mis_t*)kmalloc(sizeof(isp_mis_t), GFP_KERNEL); //create new node + + + if (new == NULL || head == NULL) { + //printk("%s: input wrong parameter\n", __func__); + return -1; + } + new_node->val = new->val; + new_node->irq_src = new->irq_src; + /*printk("%s: new_node %px irq_src %d", __func__, new_node, new->irq_src);*/ + INIT_LIST_HEAD(&new_node->list); + list_add_tail(&new_node->list, &head->list); //append to tail + #endif + return 0; + + } + + //dequeue && release memory +int isp_irq_dequeue(isp_mis_t* data, isp_mis_t* head) + { + +#ifdef __KERNEL__ + isp_mis_t* entry; + if (data == NULL || head == NULL) { + //printk("%s: input wrong parameter\n", __func__); + return -1; + } + if (list_empty(&head->list)) { + //printk("%s: There is no node\n", __func__); + return -1; + } + + entry = list_first_entry(&head->list, isp_mis_t, list); + /*printk("%s: entry %px irq_src %d", __func__, entry, entry->irq_src);*/ + data->val = entry->val; + data->irq_src = entry->irq_src; + list_del_init(&entry->list); + + kfree(entry); +#endif + return 0; + } + +bool isp_irq_is_queue_empty( isp_mis_t* head) + { +#ifdef __KERNEL__ + return list_empty(&head->list); +#endif + return 0; + } + +int isp_irq_create_circle_queue(isp_mis_list_t* pCList, int number) +{ +#ifdef __KERNEL__ + int i; + isp_mis_t* pMisNode; + if (pCList == NULL || number <= 0) { + printk("%s: create circle queue failed\n", __func__); + return -1; + } + + if (pCList->pHead == NULL) { + + pCList->pHead = (isp_mis_t*)kmalloc(sizeof(isp_mis_t), GFP_KERNEL); + INIT_LIST_HEAD(&pCList->pHead->list); + pCList->pRead = pCList->pHead; + pCList->pWrite = pCList->pHead; + } + printk("%s:pHead %px\n", __func__, pCList->pHead); + for (i = 0; i < number - 1; i++) { + pMisNode = (isp_mis_t*)kmalloc(sizeof(isp_mis_t), GFP_KERNEL); + INIT_LIST_HEAD(&pMisNode->list); + list_add_tail(&pMisNode->list, &pCList->pHead->list); + printk("%s:pMisNode %px\n", __func__, pMisNode); + } + +#endif + return 0; +} + +int isp_irq_destroy_circle_queue(isp_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + isp_mis_t* pMisNode; + if ((pCList == NULL) || (pCList->pHead == NULL) ) { + printk("%s: destroy circle queue failed. pClist %px\n", __func__, pCList); + return -1; + } + + while(!list_empty(&pCList->pHead->list)) { + pMisNode = list_first_entry(&pCList->pHead->list, isp_mis_t, list); + printk("%s:pMisNode %px\n", __func__, pMisNode); + list_del(&pMisNode->list); + kfree(pMisNode); + pMisNode = NULL; + } + printk("%s:pHead %px\n", __func__, pCList->pHead); + kfree(pCList->pHead); + pCList->pHead = NULL; + pCList->pRead = NULL; + pCList->pWrite = NULL; +#endif + return 0; +} + +int isp_irq_read_circle_queue(isp_mis_t* data, isp_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + //isp_mis_t* pReadEntry; + if (pCList == NULL) { + printk("%s: can not read circle queue\n", __func__); + return -1; + } + + if (pCList->pRead == pCList->pWrite) { + /*printk("%s: There is no irq mis data\n", __func__);*/ + return -1; + } + data->val = pCList->pRead->val; + data->irq_src = pCList->pRead->irq_src; + /*printk("%s: entry %px irq_src %d, msi %08x\n", __func__, pCList->pRead, data->irq_src, data->val);*/ + /*Get the next entry that link with read entry list*/ + /*Update read pointer to next entry*/ + pCList->pRead = list_first_entry(&pCList->pRead->list, isp_mis_t, list); + + //pCList->pRead = pReadEntry; + +#endif + return 0; +} + +int isp_irq_write_circle_queue(isp_mis_t* data, isp_mis_list_t* pCList) +{ +#ifdef __KERNEL__ + isp_mis_t* pWriteEntry; + if (pCList == NULL) { + printk("%s: can not read circle queue\n", __func__); + return -1; + } + + pCList->pWrite->val = data->val; + pCList->pWrite->irq_src = data->irq_src; + /*printk("%s: entry %px irq_src %d, msi %08x\n", __func__, pCList->pWrite, data->irq_src, data->val);*/ + /*get the next write entry pointer that link with the write entry list*/ + pWriteEntry = list_first_entry(&pCList->pWrite->list, isp_mis_t, list); + + /*Update write pointer to point next entry*/ + pCList->pWrite = pWriteEntry; + +#endif + return 0; +} + diff --git a/vvcam_ry/isp/isp_irq_queue.h b/vvcam_ry/isp/isp_irq_queue.h new file mode 100755 index 0000000..7eecffe --- /dev/null +++ b/vvcam_ry/isp/isp_irq_queue.h @@ -0,0 +1,97 @@ + /**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_IRQ_QUEUE_H_ +#define _ISP_IRQ_QUEUE_H_ +#ifdef __KERNEL__ +#include +#endif + typedef enum isp_src_e +{ + SRC_ISP_IRQ = 0X0000, + SRC_JPE_STATUS_IRQ, + SRC_JPE_ERROR_IRQ, + SRC_MI_IRQ, + SRC_MI1_IRQ, + SRC_MI2_IRQ, + SRC_MIPI_IRQ, + SRC_IRQ_MAX, +} isp_src_t; + +typedef struct isp_mis_s { + unsigned int irq_src; + unsigned int val; +#ifdef __KERNEL__ + struct list_head list; +#endif +}isp_mis_t; + +typedef struct isp_mis_list_s { + + isp_mis_t* pHead; + isp_mis_t* pRead; + isp_mis_t* pWrite; +}isp_mis_list_t; + +#ifdef __KERNEL__ +int isp_irq_enqueue(isp_mis_t *new,isp_mis_t* head); +int isp_irq_dequeue(isp_mis_t* data, isp_mis_t* head); +bool isp_irq_is_queue_empty( isp_mis_t* head); + +#define QUEUE_NODE_COUNT 15 +int isp_irq_create_circle_queue(isp_mis_list_t* pCList, int number); +int isp_irq_destroy_circle_queue(isp_mis_list_t* pCList); +int isp_irq_read_circle_queue(isp_mis_t* data, isp_mis_list_t* pCList); +int isp_irq_write_circle_queue(isp_mis_t* data, isp_mis_list_t* pCList); +#endif + +#endif \ No newline at end of file diff --git a/vvcam_ry/isp/isp_isr.c b/vvcam_ry/isp/isp_isr.c new file mode 100755 index 0000000..d8a3583 --- /dev/null +++ b/vvcam_ry/isp/isp_isr.c @@ -0,0 +1,279 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef ENABLE_IRQ + +#include "isp_ioctl.h" +#include "isp_types.h" +#include "mrv_all_bits.h" +#include "video/vvbuf.h" + +extern MrvAllRegister_t *all_regs; + +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG +static int config_dma_buf(struct isp_mi_data_path_context *path, + dma_addr_t dma, struct isp_buffer_context *buf) +{ + u32 size = path->out_width * path->out_height; + + buf->addr_y = dma; + switch (path->out_mode) { + case IC_MI_DATAMODE_YUV444: + case IC_MI_DATAMODE_YUV422: + case IC_MI_DATAMODE_YUV420: + if (path->data_layout == IC_MI_DATASTORAGE_PLANAR) { + buf->size_y = size + ISP_BUF_GAP; + buf->addr_cb = buf->addr_y + size; + buf->size_cb = size + ISP_BUF_GAP; + buf->addr_cr = buf->addr_cb + size; + buf->size_cr = size + ISP_BUF_GAP; + } else if (path->data_layout == + IC_MI_DATASTORAGE_SEMIPLANAR) { + buf->size_y = size + ISP_BUF_GAP; + buf->addr_cb = buf->addr_y + size; + if (path->out_mode == IC_MI_DATAMODE_YUV420) + buf->size_cb = (size >> 1) + ISP_BUF_GAP; + else + buf->size_cb = size + ISP_BUF_GAP; + } else if (path->data_layout == + IC_MI_DATASTORAGE_INTERLEAVED) { + buf->size_y = (size << 1) + ISP_BUF_GAP; + } else + return -1; + break; + case IC_MI_DATAMODE_RAW8: + buf->size_y = size + ISP_BUF_GAP; + break; + case IC_MI_DATAMODE_RAW10: + case IC_MI_DATAMODE_RAW12: + buf->size_y = (size << 1) + ISP_BUF_GAP; + break; + default: + pr_err("unsupported out mode:%d\n", path->out_mode); + return -1; + } +#ifdef ISP_MP_34BIT + buf->addr_y >>= 2; + buf->addr_cb >>= 2; + buf->addr_cr >>= 2; +#endif + return 0; +} +#endif + +static int update_dma_buffer(struct isp_ic_dev *dev) +{ +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + struct isp_mi_context *mi = &dev->mi; + struct vb2_dc_buf *buf = NULL; + struct isp_buffer_context dmabuf; + int i,dequeued; + + for (i = 0; i < MI_PATH_NUM; ++i) { + if (!mi->path[i].enable) + continue; + if (dev->mi_buf[i]) { + vvbuf_ready(dev->bctx, dev->mi_buf[i]->pad, + dev->mi_buf[i]); + dev->mi_buf[i] = NULL; + } + if (dev->state && !(*dev->state & STATE_DRIVER_STARTED)) + continue; + dequeued = 1; + buf = vvbuf_try_dqbuf(dev->bctx); + if (!buf) { + buf = dev->mi_buf_shd[i]; + if (!buf) + return -ENOMEM; + dev->mi_buf_shd[i] = NULL; + dequeued = 0; + } else if (dev->mi_buf_shd[i]) { + dev->mi_buf[i] = dev->mi_buf_shd[i]; + dev->mi_buf_shd[i] = NULL; + } + + memset(&dmabuf, 0, sizeof(dmabuf)); + dmabuf.path = i; + if (config_dma_buf(&mi->path[i], buf->dma, &dmabuf)) + continue; + isp_set_buffer(dev, &dmabuf); + dev->mi_buf_shd[i] = buf; + if (dequeued) + vvbuf_try_dqbuf_done(dev->bctx, buf); + } +#endif + return 0; +} + +int clean_dma_buffer(struct isp_ic_dev *dev) +{ +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + int i; + + if (!dev->free) + return 0; + + dev->free(dev, NULL); + + for (i = 0; i < MI_PATH_NUM; ++i) { + if (dev->mi_buf[i]) { + dev->free(dev, dev->mi_buf[i]); + dev->mi_buf[i] = NULL; + } + if (dev->mi_buf_shd[i]) { + dev->free(dev, dev->mi_buf_shd[i]); + dev->mi_buf_shd[i] = NULL; + } + } +#endif + return 0; +} + +void isp_clear_interrupts(struct isp_ic_dev *dev) +{ + u32 isp_mis, mi_mis; + + isp_mis = isp_read_reg(dev, REG_ADDR(isp_mis)); + isp_write_reg(dev, REG_ADDR(isp_icr), isp_mis); + +#ifdef ISP_MIV1 + mi_mis = isp_read_reg(dev, REG_ADDR(mi_mis)); + isp_write_reg(dev, REG_ADDR(mi_icr), mi_mis); +#elif defined(ISP_MIV2_RY) + mi_mis = isp_read_reg(dev, REG_ADDR(miv2_mis)); + isp_write_reg(dev, REG_ADDR(miv2_icr), mi_mis); +#else + mi_mis = 0; +#endif +} + +irqreturn_t isp_hw_isr(int irq, void *data) +{ + struct isp_ic_dev *dev = (struct isp_ic_dev *)data; + static const u32 frameendmask = MRV_MI_MP_FRAME_END_MASK | +#ifdef ISP_MI_BP + MRV_MI_BP_FRAME_END_MASK | +#endif + MRV_MI_SP_FRAME_END_MASK; + static const u32 errormask = MRV_MI_WRAP_MP_Y_MASK | + MRV_MI_WRAP_MP_CB_MASK | + MRV_MI_WRAP_MP_CR_MASK | +#ifdef ISP_MI_BP + MRV_MI_BP_WRAP_R_MASK | + MRV_MI_BP_WRAP_GR_MASK | + MRV_MI_BP_WRAP_GB_MASK | + MRV_MI_BP_WRAP_B_MASK | +#endif + MRV_MI_WRAP_SP_Y_MASK | + MRV_MI_WRAP_SP_CB_MASK | + MRV_MI_WRAP_SP_CR_MASK | + MRV_MI_FILL_MP_Y_MASK; + static const u32 fifofullmask = MRV_MI_MP_Y_FIFO_FULL_MASK | + MRV_MI_MP_CB_FIFO_FULL_MASK | + MRV_MI_MP_CR_FIFO_FULL_MASK | + MRV_MI_SP_Y_FIFO_FULL_MASK | + MRV_MI_SP_CB_FIFO_FULL_MASK | + MRV_MI_SP_CR_FIFO_FULL_MASK; + u32 isp_mis, mi_mis, mi_status; + struct isp_irq_data irq_data; + int rc = 0; + + if (!dev) + return IRQ_HANDLED; + + isp_mis = isp_read_reg(dev, REG_ADDR(isp_mis)); + isp_write_reg(dev, REG_ADDR(isp_icr), isp_mis); + +#ifdef ISP_MIV1 + mi_mis = isp_read_reg(dev, REG_ADDR(mi_mis)); + isp_write_reg(dev, REG_ADDR(mi_icr), mi_mis); +#elif defined(ISP_MIV2_RY) + mi_mis = isp_read_reg(dev, REG_ADDR(miv2_mis)); + isp_write_reg(dev, REG_ADDR(miv2_icr), mi_mis); +#else + mi_mis = 0; +#endif + + mi_status = isp_read_reg(dev, REG_ADDR(mi_status)); + if (mi_status & fifofullmask) { + isp_write_reg(dev, REG_ADDR(mi_status), mi_status); + pr_debug("MI FIFO full: 0x%x\n", mi_status); + } + + if (mi_mis & errormask) + pr_debug("MI mis error: 0x%x\n", mi_mis); + + if (mi_mis & frameendmask) + rc = update_dma_buffer(dev); + + if (isp_mis) { + if(isp_mis & MRV_ISP_MIS_FRAME_MASK) { + if (dev->isp_update_flag & ISP_FLT_UPDATE) { + isp_s_flt(dev); + dev->isp_update_flag &= (~ISP_FLT_UPDATE); + } + + if (dev->gamma_out.changed) { + isp_s_gamma_out(dev); + } + + } + + memset(&irq_data, 0, sizeof(irq_data)); + irq_data.val = isp_mis; + if (dev->post_event) + dev->post_event(dev, &irq_data, sizeof(irq_data)); + } + return IRQ_HANDLED; +} + +#endif diff --git a/vvcam_ry/isp/isp_miv1.c b/vvcam_ry/isp/isp_miv1.c new file mode 100755 index 0000000..2a1d317 --- /dev/null +++ b/vvcam_ry/isp/isp_miv1.c @@ -0,0 +1,626 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +#ifdef ISP_MIV1 + +extern MrvAllRegister_t *all_regs; + +static int getRawBit(u32 type, u32 *bit, u32 *len) +{ + *len = 16; + switch (type) { + case ISP_PICBUF_TYPE_RAW8: + *bit = 0; + *len = 8; + break; +#if 0 /* normal process, need pass type from engine. */ + case ISP_PICBUF_TYPE_RAW10: + *bit = 1; + break; + case ISP_PICBUF_TYPE_RAW12: + *bit = 2; + break; + case ISP_PICBUF_TYPE_RAW14: + *bit = 3; + break; + case ISP_PICBUF_TYPE_RAW16: + *bit = 4; + break; +#else /* WA */ + case ISP_PICBUF_TYPE_RAW10: + case ISP_PICBUF_TYPE_RAW12: + case ISP_PICBUF_TYPE_RAW14: + case ISP_PICBUF_TYPE_RAW16: + *bit = 4; + break; +#endif + default: + pr_err("unsupport raw formt: %d\n", type); + return -1; + } + return 0; +} +int isp_ioc_cfg_dma(struct isp_ic_dev *dev, void __user *args) +{ + return 0; +} +int isp_ioc_start_dma_read(struct isp_ic_dev *dev, void __user *args) +{ + struct isp_dma_context dma; + u32 mi_dma_ctrl = isp_read_reg(dev, REG_ADDR(mi_dma_ctrl)); + u32 llength = 0, mcm_rd_fmt_bit = 0; + u32 mi_imsc = 0, mcm_fmt = 0; + + pr_info("enter %s\n", __func__); + viv_check_retval(copy_from_user(&dma, args, sizeof(dma))); + + REG_SET_SLICE(mi_dma_ctrl, MRV_MI_DMA_BURST_LEN_LUM, dma.burst_y); + REG_SET_SLICE(mi_dma_ctrl, MRV_MI_DMA_BURST_LEN_CHROM, dma.burst_c); + + isp_write_reg(dev, REG_ADDR(mi_dma_y_pic_start_ad), + (MRV_MI_DMA_Y_PIC_START_AD_MASK & dma.base)); + getRawBit(dma.type, &mcm_rd_fmt_bit, &llength); + + llength = dma.width * llength / 8; + REG_SET_SLICE(mcm_fmt, MCM_RD_RAW_BIT, mcm_rd_fmt_bit); + isp_write_reg(dev, REG_ADDR(mi_dma_y_pic_width), + (MRV_MI_DMA_Y_PIC_WIDTH_MASK & dma.width)); + isp_write_reg(dev, REG_ADDR(mi_dma_y_llength), + (MRV_MI_DMA_Y_LLENGTH_MASK & llength)); + isp_write_reg(dev, REG_ADDR(mi_dma_y_pic_size), + (MRV_MI_DMA_Y_PIC_SIZE_MASK & (llength * dma.height))); + isp_write_reg(dev, REG_ADDR(mi_dma_cb_pic_start_ad), 0); + isp_write_reg(dev, REG_ADDR(mi_dma_cr_pic_start_ad), 0); + isp_write_reg(dev, REG_ADDR(mi_dma_ctrl), mi_dma_ctrl); + + isp_write_reg(dev, REG_ADDR(mi_dma_status), 0); + isp_write_reg(dev, REG_ADDR(mi_dma_y_raw_fmt), mcm_fmt); + isp_write_reg(dev, REG_ADDR(mi_dma_y_raw_lval), + (MRV_MI_DMA_Y_LLENGTH_MASK & llength)); + + mi_imsc = isp_read_reg(dev, REG_ADDR(mi_imsc)); + mi_imsc |= MRV_MI_DMA_READY_MASK; + + isp_write_reg(dev, REG_ADDR(mi_imsc), mi_imsc); + isp_write_reg(dev, REG_ADDR(mi_dma_start), MRV_MI_DMA_START_MASK); + return 0; +} + +u32 getScaleFactor(u32 src, u32 dst) +{ + if (dst > src) { + return ((65536 * (src - 1)) / (dst - 1)); + } else if (dst < src) { + return ((65536 * (dst - 1)) / (src - 1)) + 1; + } + return 65536; +} + +int set_scaling(int id, struct isp_ic_dev *dev, bool stabilization) +{ + u32 addr, ctrl; + u32 iw, ih, ow, oh; + u32 inputWidth, inputHeight, outputWidth, outputHeight; + u32 scale_hy, scale_hcb, scale_hcr, scale_vy, scale_vc; + struct isp_mi_data_path_context *path = &dev->mi.path[id]; + + if (id == IC_MI_PATH_MAIN) { /* mp */ + addr = REG_ADDR(mrsz_ctrl); + } else if (id == IC_MI_PATH_SELF) { /* sp */ + addr = REG_ADDR(srsz_ctrl); + } else { + return -EINVAL; + } + + inputWidth = path->in_width; + inputHeight = path->in_height; + outputWidth = path->out_width; + outputHeight = path->out_height; + + if (stabilization) { /* enabled image stabilization. */ + inputWidth = isp_read_reg(dev, REG_ADDR(isp_is_h_size)); + inputHeight = isp_read_reg(dev, REG_ADDR(isp_is_v_size)); + } + + ctrl = isp_read_reg(dev, addr); + iw = inputWidth / 2; + ih = inputHeight; + ow = outputWidth / 2; + oh = outputHeight; + + switch (path->in_mode) { + case IC_MI_DATAMODE_YUV422: + oh = outputHeight; + break; + case IC_MI_DATAMODE_YUV420: + oh = outputHeight / 2; /* scale cbcr */ + break; + default: + return -EFAULT; + } + + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_ENABLE, + inputWidth != outputWidth); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_ENABLE, + inputHeight != outputHeight); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_UP, inputWidth < outputWidth); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_UP, inputHeight < outputHeight); + scale_hy = getScaleFactor(inputWidth, outputWidth); + scale_vy = getScaleFactor(inputHeight, outputHeight); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_ENABLE, iw != ow); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_ENABLE, ih != oh); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_UP, iw < ow); + REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_UP, ih < oh); + scale_hcr = getScaleFactor(iw, ow); + scale_hcb = getScaleFactor(iw, ow); + scale_vc = getScaleFactor(ih, oh); + + REG_SET_SLICE(ctrl, MRV_MRSZ_AUTO_UPD, 1); + + if (id == IC_MI_PATH_MAIN) { + isp_write_reg(dev, REG_ADDR(mrsz_scale_vc), scale_vc); + isp_write_reg(dev, REG_ADDR(mrsz_scale_vy), scale_vy); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hcr), scale_hcr); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hcb), scale_hcb); + isp_write_reg(dev, REG_ADDR(mrsz_scale_hy), scale_hy); + isp_write_reg(dev, REG_ADDR(mrsz_ctrl), + ctrl | MRV_MRSZ_CFG_UPD_MASK); + } else if (id == IC_MI_PATH_SELF) { + isp_write_reg(dev, REG_ADDR(srsz_scale_vc), scale_vc); + isp_write_reg(dev, REG_ADDR(srsz_scale_vy), scale_vy); + isp_write_reg(dev, REG_ADDR(srsz_scale_hcr), scale_hcr); + isp_write_reg(dev, REG_ADDR(srsz_scale_hcb), scale_hcb); + isp_write_reg(dev, REG_ADDR(srsz_scale_hy), scale_hy); + isp_write_reg(dev, REG_ADDR(srsz_ctrl), + ctrl | MRV_MRSZ_CFG_UPD_MASK); + } + + return 0; +} + +#ifdef ISP_MI_BP +int isp_bppath_start(struct isp_ic_dev *dev) +{ + struct isp_mi_context mi = *(&dev->mi); + u32 bp_ctrl = 0, lval = 0; + struct isp_mi_data_path_context *path = &mi.path[2]; + u32 mi_imsc = isp_read_reg(dev, REG_ADDR(mi_imsc)); + int i; + + pr_info("enter %s\n", __func__); + bp_ctrl = 0; + lval = path->out_width; + + if (mi.path[2].enable) { + bp_ctrl &= ~MRV_MI_BP_WRITE_RAWBIT_MASK; + + if (path->data_alignMode == ISP_MI_DATA_ALIGN_16BIT_MODE) { + if ((path->out_mode == IC_MI_DATAMODE_RAW10) || + (path->out_mode == IC_MI_DATAMODE_RAW12) || + (path->out_mode == IC_MI_DATAMODE_RAW14)) { + lval = (path->out_width + 3) / 4; + } + } else if (path->data_alignMode == + ISP_MI_DATA_ALIGN_128BIT_MODE) { + if ((path->out_mode == IC_MI_DATAMODE_RAW10) + || (path->out_mode == IC_MI_DATAMODE_RAW12) + || (path->out_mode == IC_MI_DATAMODE_RAW14)) { + lval = (path->out_width * 2 + 126) / 128; + } + } else { + if (path->out_mode == IC_MI_DATAMODE_RAW10) { + lval = (path->out_width * 10 + 63) / 64; + } else if (path->out_mode == IC_MI_DATAMODE_RAW12) { + lval = (path->out_width * 12 + 63) / 64; + } else if (path->out_mode == IC_MI_DATAMODE_RAW14) { + lval = (path->out_width * 14 + 63) / 64; + } else if (path->out_mode == IC_MI_DATAMODE_RAW16) { + lval = (path->out_width * 16 + 63) / 64; + } else { + lval = (path->out_width * 8 + 63) / 64; + } + } + lval <<= 3; + REG_SET_SLICE(bp_ctrl, BP_WR_RAW_ALIGNED, path->data_alignMode); + switch (mi.path[2].out_mode) { + case (IC_MI_DATAMODE_RAW8): + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_RAWBIT, + MRV_MI_BP_WRITE_RAWBIT_RAW_8); + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_FORMAT, + MRV_MI_BP_WRITE_INTERLEAVE_FORMAT); + break; + case (IC_MI_DATAMODE_RAW12): + REG_SET_SLICE(bp_ctrl, BP_WR_BYTE_SWAP, 1); + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_RAWBIT, + MRV_MI_BP_WRITE_RAWBIT_RAW_12); + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_FORMAT, + MRV_MI_BP_WRITE_INTERLEAVE_FORMAT); + break; + case (IC_MI_DATAMODE_RAW10): + REG_SET_SLICE(bp_ctrl, BP_WR_BYTE_SWAP, 1); + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_RAWBIT, + MRV_MI_BP_WRITE_RAWBIT_RAW_10); + REG_SET_SLICE(bp_ctrl, MRV_MI_BP_WRITE_FORMAT, + MRV_MI_BP_WRITE_INTERLEAVE_FORMAT); + break; + default: + break; + } + isp_write_reg(dev, REG_ADDR(mi_bp_wr_size_init), + lval * mi.path[2].out_height); + isp_write_reg(dev, REG_ADDR(mi_bp_pic_width), + mi.path[2].out_width); + isp_write_reg(dev, REG_ADDR(mi_bp_wr_llength), lval); + isp_write_reg(dev, REG_ADDR(mi_bp_pic_height), + mi.path[2].out_height); + isp_write_reg(dev, REG_ADDR(mi_bp_pic_size), + lval * mi.path[2].out_height); + /* enable frame end irq for bp path */ + mi_imsc |= + MRV_MI_BP_FRAME_END_MASK | MRV_MI_BP_WRAP_R_MASK | + MRV_MI_BP_WRAP_GR_MASK | MRV_MI_BP_WRAP_GB_MASK | + MRV_MI_BP_WRAP_B_MASK; + } + if (!dev->rawis.enable) { + isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), + mi.path[2].out_width); + isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), + mi.path[2].out_height); + isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), 0); + } + bp_ctrl |= MRV_MI_BP_PATH_ENABLE_MASK; + isp_write_reg(dev, REG_ADDR(mi_bp_ctrl), bp_ctrl); + + isp_write_reg(dev, REG_ADDR(mi_imsc), mi_imsc); + return 0; +} +#endif +int isp_mi_start(struct isp_ic_dev *dev) +{ + struct isp_mi_context mi = *(&dev->mi); + u32 mi_init, mi_ctrl, mi_imsc; + u32 out_stride; + int i; + u8 retry = 3; + + pr_info("enter %s\n", __func__); + + isp_write_reg(dev, REG_ADDR(mrsz_ctrl), 0); + isp_write_reg(dev, REG_ADDR(mrsz_ctrl_shd), 0); + + for (i = 0; i < 2; i++) { + if (mi.path[i].hscale || mi.path[i].vscale) { + set_scaling(i, dev, dev->is.enable); + } + } + + mi_init = 0; + mi_ctrl = 0; + mi_imsc = 0; + if (mi.path[0].enable) { + /* remove update enable bits for offset and base registers */ + mi_init &= ~MRV_MI_MP_OUTPUT_FORMAT_MASK; + mi_ctrl &= ~MRV_MI_MP_WRITE_FORMAT_MASK; + + /* config mi_init output format for yuv format */ + if (mi.path[0].out_mode <= IC_MI_DATAMODE_YUV400) + REG_SET_SLICE(mi_init, MRV_MI_MP_OUTPUT_FORMAT, + IC_MI_DATAMODE_YUV400 - + mi.path[0].out_mode); + switch (mi.path[0].out_mode) { + case (IC_MI_DATAMODE_RAW8): + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_RAW_8); + REG_SET_SLICE(mi_ctrl, MRV_MI_RAW_ENABLE, 1); + REG_SET_SLICE(mi_init, MRV_MI_MP_OUTPUT_FORMAT, + MRV_MI_MP_OUTPUT_FORMAT_RAW8); + break; + case (IC_MI_DATAMODE_RAW12): + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_RAW_12); + REG_SET_SLICE(mi_ctrl, MRV_MI_RAW_ENABLE, 1); + REG_SET_SLICE(mi_init, MRV_MI_MP_OUTPUT_FORMAT, + MRV_MI_MP_OUTPUT_FORMAT_RAW12); + isp_write_reg(dev, REG_ADDR(mi_output_align_format), 1); + break; + case (IC_MI_DATAMODE_RAW10): + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_RAW_12); + REG_SET_SLICE(mi_ctrl, MRV_MI_RAW_ENABLE, 1); + REG_SET_SLICE(mi_init, MRV_MI_MP_OUTPUT_FORMAT, + MRV_MI_MP_OUTPUT_FORMAT_RAW10); + isp_write_reg(dev, REG_ADDR(mi_output_align_format), 1); + break; + case (IC_MI_DATAMODE_JPEG): + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_PLANAR); + REG_SET_SLICE(mi_ctrl, MRV_MI_JPEG_ENABLE, 1); + break; + case (IC_MI_DATAMODE_YUV444): + case (IC_MI_DATAMODE_YUV422): + case (IC_MI_DATAMODE_YUV420): + case (IC_MI_DATAMODE_YUV400): + if (mi.path[0].data_layout == IC_MI_DATASTORAGE_PLANAR) { + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_PLANAR); + } else if (mi.path[0].data_layout == + IC_MI_DATASTORAGE_SEMIPLANAR) { + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_SEMIPLANAR); + } else if (mi.path[0].data_layout == + IC_MI_DATASTORAGE_INTERLEAVED) { + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_WRITE_FORMAT, + MRV_MI_MP_WRITE_FORMAT_INTERLEAVED); + } else { + break; + } + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_ENABLE, 1); + break; + default: + break; + } + + out_stride = mi.path[0].data_layout == + IC_MI_DATASTORAGE_INTERLEAVED ? + (mi.path[0].out_width * 2) : (mi.path[0].out_width); + isp_write_reg(dev, REG_ADDR(mi_mp_y_pic_width), out_stride); + isp_write_reg(dev, REG_ADDR(mi_mp_y_llength), out_stride); + isp_write_reg(dev, REG_ADDR(mi_mp_y_pic_height), + mi.path[0].out_height); + isp_write_reg(dev, REG_ADDR(mi_mp_y_pic_size), + out_stride * mi.path[0].out_height); + + /* workaround to resolve the problem that the mi_mp_y_pic_width can't be written */ + for(i = 0; i < retry; i++) { + if(isp_read_reg(dev, REG_ADDR(mi_mp_y_pic_width)) != out_stride) { + isp_write_reg(dev, REG_ADDR(mi_mp_y_pic_width), out_stride); + } else { + break; + } + } + if(retry == i) { + pr_info("%s: update mi_mp_y_pic_width error!\n", __func__); + } + + /* enable frame end irq for main path */ + mi_imsc |= + (MRV_MI_MP_FRAME_END_MASK | MRV_MI_WRAP_MP_Y_MASK | + MRV_MI_WRAP_MP_CB_MASK | MRV_MI_WRAP_MP_CR_MASK); + } + + if (mi.path[1].enable) { + /* setup mi for self-path */ + mi_ctrl &= ~(MRV_MI_SP_WRITE_FORMAT_MASK); + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_INPUT_FORMAT, + mi.path[1].in_mode - 1); + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_OUTPUT_FORMAT, + mi.path[1].out_mode - 1); + + switch (mi.path[1].out_mode) { + case (IC_MI_DATAMODE_RGB888): + case (IC_MI_DATAMODE_RGB666): + case (IC_MI_DATAMODE_RGB565): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_RGB_INTERLEAVED); + break; + case (IC_MI_DATAMODE_YUV444): + case (IC_MI_DATAMODE_YUV400): + if (mi.path[1].data_layout == IC_MI_DATASTORAGE_PLANAR) { + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_PLANAR); + } + break; + case (IC_MI_DATAMODE_YUV422): + switch (mi.path[1].data_layout) { + case (IC_MI_DATASTORAGE_PLANAR): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_PLANAR); + break; + case (IC_MI_DATASTORAGE_SEMIPLANAR): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_SEMIPLANAR); + break; + case (IC_MI_DATASTORAGE_INTERLEAVED): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_INTERLEAVED); + break; + default: + break; + } + break; + case (IC_MI_DATAMODE_YUV420): + switch (mi.path[1].data_layout) { + case (IC_MI_DATASTORAGE_PLANAR): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_PLANAR); + break; + case (IC_MI_DATASTORAGE_SEMIPLANAR): + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_WRITE_FORMAT, + MRV_MI_SP_WRITE_FORMAT_SEMIPLANAR); + break; + default: + break; + } + break; + default: + break; + } + + out_stride = mi.path[1].data_layout == + IC_MI_DATASTORAGE_INTERLEAVED ? + mi.path[1].out_width * 2 : mi.path[1].out_width; + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(mi_sp_y_pic_width), out_stride); + isp_write_reg(dev, REG_ADDR(mi_sp_y_llength), out_stride); + isp_write_reg(dev, REG_ADDR(mi_sp_y_pic_height), + mi.path[1].out_height); + isp_write_reg(dev, REG_ADDR(mi_sp_y_pic_size), + out_stride * mi.path[1].out_height); + /* enable frame end interrupt on self path */ + mi_imsc |= + (MRV_MI_SP_FRAME_END_MASK | MRV_MI_WRAP_SP_Y_MASK | + MRV_MI_WRAP_SP_CB_MASK | MRV_MI_WRAP_SP_CR_MASK); + } + +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + for (i = 0; i < MI_PATH_NUM; ++i) { + dev->mi_buf[i] = NULL; + dev->mi_buf_shd[i] = NULL; + } + if (dev->state) + *dev->state |= STATE_DRIVER_STARTED; +#endif + + mi_ctrl |= (MRV_MI_INIT_BASE_EN_MASK | MRV_MI_INIT_OFFSET_EN_MASK); + REG_SET_SLICE(mi_ctrl, MRV_MI_BURST_LEN_CHROM, mi.burst_len); + REG_SET_SLICE(mi_ctrl, MRV_MI_BURST_LEN_LUM, mi.burst_len); + isp_write_reg(dev, REG_ADDR(mi_ctrl), mi_ctrl | 0x2000); + REG_SET_SLICE(mi_init, MRV_MI_MI_CFG_UPD, 1); + + isp_write_reg(dev, REG_ADDR(mi_imsc), mi_imsc); +#ifdef ISP_MI_BP + isp_bppath_start(dev); +#endif + isp_write_reg(dev, REG_ADDR(mi_init), mi_init); + return 0; +} + +int isp_mi_stop(struct isp_ic_dev *dev) +{ + u32 mi_ctrl = 0, mi_init = 0; + pr_info("enter %s\n", __func__); + + isp_write_reg(dev, REG_ADDR(mi_imsc), 0); + + /* disable mi path */ + mi_ctrl = isp_read_reg(dev, REG_ADDR(mi_ctrl)); + REG_SET_SLICE(mi_ctrl, MRV_MI_MP_ENABLE, 0); + REG_SET_SLICE(mi_ctrl, MRV_MI_SP_ENABLE, 0); + REG_SET_SLICE(mi_ctrl, MRV_MI_JPEG_ENABLE, 0); + REG_SET_SLICE(mi_ctrl, MRV_MI_RAW_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(mi_ctrl), mi_ctrl); + + mi_init = isp_read_reg(dev, REG_ADDR(mi_init)); + REG_SET_SLICE(mi_init, MRV_MI_MI_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(mi_init), mi_init); + +#if defined(__KERNEL__) && defined(ENABLE_IRQ) + if (dev->state) + *dev->state &= ~STATE_DRIVER_STARTED; + clean_dma_buffer(dev); +#endif + return 0; +} + +int isp_set_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + u32 addr; + + if (!dev || !buf) { + pr_err("NULL pointer %s\n", __func__); + return -EINVAL; + } + + addr = buf->path == 0 ? + REG_ADDR(mi_mp_y_base_ad_init) : REG_ADDR(mi_sp_y_base_ad_init); + isp_write_reg(dev, addr, (buf->addr_y & MRV_MI_MP_Y_BASE_AD_INIT_MASK)); + isp_write_reg(dev, addr + 1 * 4, + (buf->size_y & MRV_MI_MP_Y_SIZE_INIT_MASK)); + isp_write_reg(dev, addr + 2 * 4, 0); + isp_write_reg(dev, addr + 5 * 4, + (buf->addr_cb & MRV_MI_MP_CB_BASE_AD_INIT_MASK)); + isp_write_reg(dev, addr + 6 * 4, + (buf->size_cb & MRV_MI_MP_CB_SIZE_INIT_MASK)); + isp_write_reg(dev, addr + 7 * 4, 0); + isp_write_reg(dev, addr + 9 * 4, + (buf->addr_cr & MRV_MI_MP_CR_BASE_AD_INIT_MASK)); + isp_write_reg(dev, addr + 10 * 4, + (buf->size_cr & MRV_MI_MP_CR_SIZE_INIT_MASK)); + isp_write_reg(dev, addr + 11 * 4, 0); + + return 0; +} + +int isp_set_bp_buffer(struct isp_ic_dev *dev, struct isp_bp_buffer_context *buf) +{ +#ifndef ISP_MI_BP + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + isp_write_reg(dev, REG_ADDR(mi_bp_r_base_ad_init), + (buf->addr_r & BP_R_BASE_AD_INIT_MASK)); + isp_write_reg(dev, REG_ADDR(mi_bp_gr_base_ad_init), + (buf->addr_gr & BP_GR_BASE_AD_INIT_MASK)); + + isp_write_reg(dev, REG_ADDR(mi_bp_gb_base_ad_init), + (buf->addr_gb & BP_GB_BASE_AD_INIT_MASK)); + isp_write_reg(dev, REG_ADDR(mi_bp_b_base_ad_init), + (buf->addr_b & BP_B_BASE_AD_INIT_MASK)); + return 0; +#endif +} + +u32 isp_read_mi_irq(struct isp_ic_dev * dev) +{ + return isp_read_reg(dev, REG_ADDR(mi_mis)); +} + +void isp_reset_mi_irq(struct isp_ic_dev *dev, u32 icr) +{ + isp_write_reg(dev, REG_ADDR(mi_icr), icr); +} + +#endif diff --git a/vvcam_ry/isp/isp_miv2.c b/vvcam_ry/isp/isp_miv2.c new file mode 100755 index 0000000..2c6ac5a --- /dev/null +++ b/vvcam_ry/isp/isp_miv2.c @@ -0,0 +1,1189 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +#ifdef ISP_MIV2_RY + +static void mi_set_slice(u32* val, u32 mask, u32 slice); +extern MrvAllRegister_t *all_regs; + +static int getRawBit(u32 type, u32 *bit, u32 *len) +{ + *len = 16; + switch (type) { + case ISP_PICBUF_TYPE_RAW8: + *bit = 0; + *len = 8; + break; +#if 0 /* normal process, need pass type from engine. */ + case ISP_PICBUF_TYPE_RAW10: + *bit = 1; + break; + case ISP_PICBUF_TYPE_RAW12: + *bit = 2; + break; + case ISP_PICBUF_TYPE_RAW14: + *bit = 3; + break; + case ISP_PICBUF_TYPE_RAW16: + *bit = 4; + break; +#else /* WA */ + case ISP_PICBUF_TYPE_RAW10: + case ISP_PICBUF_TYPE_RAW12: + case ISP_PICBUF_TYPE_RAW14: + case ISP_PICBUF_TYPE_RAW16: + *bit = 4; + break; +#endif + default: + pr_err("unsupport raw formt: %d\n", type); + return -1; + } + return 0; +} + +static bool isYuv(int type) +{ + return (type == ISP_PICBUF_TYPE_YCbCr444) || + (type == ISP_PICBUF_TYPE_YCbCr422) || + (type == ISP_PICBUF_TYPE_YCbCr420) || + (type == ISP_PICBUF_TYPE_YCbCr400); +} + +static bool isRaw(u32 type) +{ + return (type == ISP_PICBUF_TYPE_RAW8) || + (type == ISP_PICBUF_TYPE_RAW10) || + (type == ISP_PICBUF_TYPE_RAW12) || + (type == ISP_PICBUF_TYPE_RAW14) || (type == ISP_PICBUF_TYPE_RAW16); + +} + +static void set_rgb_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + u32 addr = buf->path == 0 ? REG_ADDR(miv2_mp_y_base_ad_init) : + (buf->path == + 1) ? REG_ADDR(miv2_sp1_y_base_ad_init) : + REG_ADDR(miv2_sp2_y_base_ad_init); + if (buf->type == ISP_PICBUF_TYPE_RGB888) { + isp_write_reg(dev, addr, (buf->addr_y & MP_Y_BASE_AD_MASK)); + isp_write_reg(dev, addr + 1 * 4, + (buf->size_y & MP_Y_SIZE_MASK)); + isp_write_reg(dev, addr + 2 * 4, 0); + isp_write_reg(dev, addr + 7 * 4, + (buf->addr_cb & MP_CB_BASE_AD_MASK)); + isp_write_reg(dev, addr + 8 * 4, + (buf->size_cb & MP_CB_SIZE_MASK)); + isp_write_reg(dev, addr + 9 * 4, 0); + isp_write_reg(dev, addr + 10 * 4, + (buf->addr_cr & MP_CR_BASE_AD_MASK)); + isp_write_reg(dev, addr + 11 * 4, + (buf->size_cr & MP_CR_SIZE_MASK)); + isp_write_reg(dev, addr + 12 * 4, 0); + } +} +/*#define PP_LINE_ENTRY*/ +#define PP_LINE_NUM 80*2 + +static void set_yuv_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + + u32 addr = buf->path == 0 ? REG_ADDR(miv2_mp_y_base_ad_init) : + (buf->path == 1) ? REG_ADDR(miv2_sp1_y_base_ad_init) : + (buf->path == 2) ? REG_ADDR(miv2_sp2_y_base_ad_init) : + REG_ADDR(isp_mi_pp_y_base_ad_init); + + if (isYuv(buf->type)) { + isp_write_reg(dev, addr, (buf->addr_y & MP_Y_BASE_AD_MASK)); + isp_write_reg(dev, addr + 1 * 4, + (buf->size_y & MP_Y_SIZE_MASK)); + isp_write_reg(dev, addr + 2 * 4, 0); + isp_write_reg(dev, addr + 7 * 4, + (buf->addr_cb & MP_CB_BASE_AD_MASK)); + isp_write_reg(dev, addr + 8 * 4, + (buf->size_cb & MP_CB_SIZE_MASK)); + isp_write_reg(dev, addr + 9 * 4, 0); + isp_write_reg(dev, addr + 10 * 4, + (buf->addr_cr & MP_CR_BASE_AD_MASK)); + isp_write_reg(dev, addr + 11 * 4, + (buf->size_cr & MP_CR_SIZE_MASK)); + isp_write_reg(dev, addr + 12 * 4, 0); + + + } +} + +static void set_raw_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + u32 addr = buf->path == ISP_MI_PATH_MP ? REG_ADDR(miv2_mp_raw_base_ad_init) : + (buf->path == ISP_MI_PATH_SP2_BP) ? REG_ADDR(miv2_sp2_raw_base_ad_init) : + (buf->path == ISP_MI_PATH_PP) ?REG_ADDR(isp_mi_pp_y_base_ad_init): +#ifdef ISP_MI_MCM_WR_RY + (buf->path == ISP_MI_MCM_WR0) ?REG_ADDR(miv2_mcm_raw0_base_ad_init): + (buf->path == ISP_MI_MCM_WR1) ?REG_ADDR(miv2_mcm_raw1_base_ad_init): +#endif +#ifdef ISP_MI_HDR_RY + (buf->path == ISP_MI_HDR_L) ?REG_ADDR(isp_mi_hdr_l_base_ad_init): + (buf->path == ISP_MI_HDR_S) ?REG_ADDR(isp_mi_hdr_s_base_ad_init): + (buf->path == ISP_MI_HDR_VS) ?REG_ADDR(isp_mi_hdr_vs_base_ad_init): +#endif + 0; + uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num)); + if ((buf->path == ISP_MI_PATH_PP) && (line_num != 0)) { + buf->addr_y = dev->pp_write.buf_addr; + buf->size_y = dev->pp_write.buf_size; + } + /*pr_info("%s path %d type %d addr %08x line_num = %d buf_addr = 0x%x, buf_size = %d\n", + __func__, buf->path, buf->type, addr, line_num, buf->addr_y, buf->size_y);*/ + if (isRaw(buf->type)) { + if (addr != 0) { + isp_write_reg(dev, addr, + (buf->addr_y & MP_RAW_BASE_AD_MASK)); + isp_write_reg(dev, addr + 4, + (buf->size_y & MP_RAW_SIZE_MASK)); + isp_write_reg(dev, addr + 2 * 4, 0); + } + } + +} + +int isp_set_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + if (!dev || !buf) { + pr_err("NULL pointer %s\n", __func__); + return -1; + } + + set_yuv_buffer(dev, buf); + set_raw_buffer(dev, buf); + set_rgb_buffer(dev, buf); + return 0; +} + +static int calc_raw_lval(int width, int out_mode, int align_mode) +{ + u32 lval = 0; + + if (align_mode == ISP_MI_DATA_ALIGN_16BIT_MODE) { + if ((out_mode == IC_MI_DATAMODE_RAW10) || + (out_mode == IC_MI_DATAMODE_RAW12) || + (out_mode == IC_MI_DATAMODE_RAW14)) { + lval = (width + 7) / 8; + } + } else if (align_mode == ISP_MI_DATA_ALIGN_128BIT_MODE) { + if (out_mode == IC_MI_DATAMODE_RAW10){ + lval = (width + 12 - 1)/12; + }else if(out_mode == IC_MI_DATAMODE_RAW12){ + lval = (width + 10 - 1)/10; + }else if(out_mode == IC_MI_DATAMODE_RAW14){ + lval = (width + 9 - 1)/9; + }else{ + lval = (width + 128 - 1)/128; + } + } else { + if (out_mode == IC_MI_DATAMODE_RAW10) { + lval = (width * 10 + 127) / 128; + } else if (out_mode == IC_MI_DATAMODE_RAW12) { + lval = (width * 12 + 127) / 128; + } else if (out_mode == IC_MI_DATAMODE_RAW14) { + lval = (width * 14 + 127) / 128; + } else if (out_mode == IC_MI_DATAMODE_RAW16) { + lval = (width * 16 + 127) / 128; + } else { + lval = (width * 8 + 127) / 128; + } + } + + return lval; +} + +struct isp_dma_path_context{ + u32 ctrl_addr; + u32 fmt_addr; + u32 bus_cfg_addr; + u32 bus_id_addr; + u32 mi_imsc_addr; + u32 rd_fmt_align; + u32 rd_raw_bit; + u32 rd_cfg_upd; + u32 rd_auto_upd; + u32 pic_start_addr; + u32 pic_width; + u32 pic_height; + u32 pic_llength; + u32 pic_size; + u32 pic_lval; + u32 path_enable_mask; + u32 path_dma_start_mask; +}; + +int isp_ioc_cfg_dma(struct isp_ic_dev *dev, void __user *args) +{ + u32 llength, miv2_imsc, miv2_ctrl,path_ctrl,path_fmt; + struct isp_dma_context dma; + //u32 path_bus_cfg; + u32 bus_id; + u32 path_rd_fmt_bit = 0; + u8 id; + struct isp_dma_path_context dma_path_ctx[] = +#ifndef ISP_MI_PP_READ_RY + {{REG_ADDR(miv2_mcm_ctrl), REG_ADDR(miv2_mcm_fmt), REG_ADDR(miv2_mcm_bus_cfg), REG_ADDR(miv2_mcm_bus_id), + REG_ADDR(miv2_imsc), MCM_RD_FMT_ALIGNED_MASK, MCM_RD_RAW_BIT_MASK, MCM_RD_CFG_UPD_MASK, MCM_RD_AUTO_UPDATE_MASK, \ + REG_ADDR(miv2_mcm_dma_raw_pic_start_ad), REG_ADDR(miv2_mcm_dma_raw_pic_width), 0, \ + REG_ADDR(miv2_mcm_dma_raw_pic_llength), REG_ADDR(miv2_mcm_dma_raw_pic_size), \ + REG_ADDR(miv2_mcm_dma_raw_pic_lval), MCM_RAW_RDMA_PATH_ENABLE_MASK, MCM_RAW_RDMA_START_MASK}, +#ifdef ISP_MI_HDR_RY + {REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(miv2_imsc2), \ + HDR_RD_RAW_ALIGNED_MASK, HDR_RD_L_BIT_MASK, HDR_RD_RAW_CFG_UPDATE_MASK,HDR_RD_RAW_CFG_UPDATE_MASK, \ + REG_ADDR(isp_mi_hdr_dma_l_base_ad_init), REG_ADDR(isp_mi_hdr_dma_pic_width), REG_ADDR(isp_mi_hdr_dma_pic_height), \ + REG_ADDR(isp_mi_hdr_dma_l_llength), REG_ADDR(isp_mi_hdr_dma_l_size_init), \ + REG_ADDR(isp_mi_hdr_dma_l_lval), 0, HDR_DMA_START_MASK}, + + {REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(miv2_imsc2), \ + HDR_RD_RAW_ALIGNED_MASK, HDR_RD_S_BIT_MASK, HDR_RD_RAW_CFG_UPDATE_MASK,HDR_RD_RAW_CFG_UPDATE_MASK, \ + REG_ADDR(isp_mi_hdr_dma_s_base_ad_init), REG_ADDR(isp_mi_hdr_dma_pic_width), REG_ADDR(isp_mi_hdr_dma_pic_height), \ + REG_ADDR(isp_mi_hdr_dma_s_llength), REG_ADDR(isp_mi_hdr_dma_s_size_init), \ + REG_ADDR(isp_mi_hdr_dma_s_lval), 0, HDR_DMA_START_MASK}, + + {REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(miv2_imsc2), \ + HDR_RD_RAW_ALIGNED_MASK, HDR_RD_VS_BIT_MASK, HDR_RD_RAW_CFG_UPDATE_MASK,HDR_RD_RAW_CFG_UPDATE_MASK, \ + REG_ADDR(isp_mi_hdr_dma_vs_base_ad_init), REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_dma_pic_height), \ + REG_ADDR(isp_mi_hdr_dma_vs_llength), REG_ADDR(isp_mi_hdr_dma_vs_size_init), \ + REG_ADDR(isp_mi_hdr_dma_vs_lval), 0, HDR_DMA_START_MASK} +#endif + }; +#else + {{REG_ADDR(isp_mi_pp_ctrl), REG_ADDR(isp_mi_pp_fmt), 0, 0, REG_ADDR(miv2_imsc2), \ + PP_RD_RAW_ALIGNED_MASK, PP_RD_RAW_BIT_MASK, PP_MI_CFG_UPD_MASK, PP_RD_YUV_CFG_UPDATE_MASK, \ + REG_ADDR(isp_mi_pp_dma_y_pic_start_ad), REG_ADDR(isp_mi_pp_dma_y_pic_width), 0, \ + REG_ADDR(isp_mi_pp_dma_y_pic_llength), REG_ADDR(isp_mi_pp_dma_y_pic_size), \ + REG_ADDR(isp_mi_pp_dma_y_pic_lval), 0, PP_DMA_START_MASK}}; +#endif + if (dev == NULL || args == NULL) { + pr_info("input wrong parameter %s\n", __func__); + return -1; + } + + pr_info("enter %s\n", __func__); + + viv_check_retval(copy_from_user(&dma, args, sizeof(dma))); + id = dma.id; + if ( id > ISP_MI_DMA_ID_MAX){ + pr_info("id config wrong %s\n", __func__); + return -1; + } + path_fmt = isp_read_reg(dev, dma_path_ctx[id].fmt_addr); +#ifdef ISP_MI_PP_READ_RY + path_fmt |= 0x80000000; +#endif + miv2_imsc = isp_read_reg(dev, dma_path_ctx[id].mi_imsc_addr); + miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + path_ctrl = isp_read_reg(dev, dma_path_ctx[id].ctrl_addr); + + //if ( dma_path_ctx[id].bus_cfg_addr != 0) { + // path_bus_cfg = isp_read_reg(dev, dma_path_ctx[id].bus_cfg_addr); + //} + if ( dma_path_ctx[id].bus_id_addr != 0) { + bus_id = isp_read_reg(dev, dma_path_ctx[id].bus_id_addr); + } + + if ( dma.align == ISP_MI_DATA_UNALIGN_MODE ) { + + switch(dma.type){ + case ISP_PICBUF_TYPE_RAW10: + llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW10, ISP_MI_DATA_UNALIGN_MODE); + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 1); + break; + case ISP_PICBUF_TYPE_RAW12: + llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW12,ISP_MI_DATA_UNALIGN_MODE); + if (id >= ISP_MI_DMA_ID_HDR_L && id <= ISP_MI_DMA_ID_HDR_VS) { + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 0); //mi dma hdr stitch raw only support raw12 and raw16 + } else { + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 2); + } + break; + case ISP_PICBUF_TYPE_RAW14: + llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW14, ISP_MI_DATA_UNALIGN_MODE); + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 3); + break; + case ISP_PICBUF_TYPE_RAW16: + llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW16, ISP_MI_DATA_UNALIGN_MODE); + if (id >= ISP_MI_DMA_ID_HDR_L && id <= ISP_MI_DMA_ID_HDR_VS) { + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 1); //mi dma hdr stitch raw only support raw12 and raw16 + } else { + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 4); + } + + break; + default: + return -EFAULT; + } + + llength <<= 4; + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_fmt_align, dma.align); + + } else { + getRawBit(dma.type, &path_rd_fmt_bit, &llength); //The old version load all kinds of raw format with raw16 format except raw8 + llength = dma.width * llength / 8; + if (id >= ISP_MI_DMA_ID_HDR_L && id <= ISP_MI_DMA_ID_HDR_VS) { + path_rd_fmt_bit = 1; + } + mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, path_rd_fmt_bit); + } + +/* if (llength != 8) + REG_SET_SLICE(mcm_bus_cfg, MCM_RD_SWAP_RAW, 1);*/ + + //path_ctrl |= PP_RD_YUV_CFG_UPDATE_MASK; //PP_INIT_OFFSET_EN_MASK | PP_INIT_BASE_EN_MASK | +#ifdef POST_ISP_SDK_TEST + isp_write_reg(dev, dma_path_ctx[id].pic_start_addr, (MCM_DMA_RAW_PIC_START_AD_MASK & dma.base)); +#endif + isp_write_reg(dev,dma_path_ctx[id].pic_width, (MCM_DMA_RAW_PIC_WIDTH_MASK & dma.width)); + + if (dma_path_ctx[id].pic_height) { + isp_write_reg(dev,dma_path_ctx[id].pic_height, dma.height); + } + + isp_write_reg(dev, dma_path_ctx[id].pic_llength, (MCM_DMA_RAW_PIC_LLENGTH_MASK & llength)); + isp_write_reg(dev,dma_path_ctx[id].pic_size, (MCM_DMA_RAW_PIC_SIZE_MASK & (llength * dma.height))); + isp_write_reg(dev, dma_path_ctx[id].pic_lval, (MCM_DMA_RAW_PIC_WIDTH_MASK & llength)); + isp_write_reg(dev, dma_path_ctx[id].fmt_addr, path_fmt); + + //isp_write_reg(dev, REG_ADDR(miv2_mcm_bus_cfg), path_bus_cfg); +#ifdef ISP_MI_PP_READ_RY + isp_write_reg(dev, REG_ADDR(mi_pp_dma_y_pic_height), dma.height); + isp_write_reg(dev, REG_ADDR(mi_pp_y_lval_bytes), llength); + + // isp_write_reg(dev, 0x55c0, dma.height); + // isp_write_reg(dev, 0x55c4, dma.height); + // isp_write_reg(dev, 0x55c8, dma.height); + // isp_write_reg(dev, 0x55cc, llength); + + //isp_write_reg(dev, dma_path_ctx[id].mi_imsc_addr, miv2_imsc | PPR_DMA_READY_MASK); /* modify by wuyi for line entry mode enabled pp dma */ +#else + isp_write_reg(dev, dma_path_ctx[id].mi_imsc_addr, miv2_imsc | 0x01800025); /* enabled jdp, sp2_raw, mp_raw, mcm */ +#endif + + if(id == ISP_MI_DMA_ID_MCM_PP) { + miv2_ctrl |= (dma_path_ctx[id].path_enable_mask );//| dma_path_ctx[id].path_dma_start_mask); + //path_ctrl |= 0xfa; + mi_set_slice(&path_ctrl, dma_path_ctx[id].rd_cfg_upd, 1); + mi_set_slice(&path_ctrl, dma_path_ctx[id].rd_auto_upd, 1); + + REG_SET_SLICE(bus_id, MCM_BUS_SW_EN, 1); + REG_SET_SLICE(bus_id, MCM_RD_ID_EN, 1); + if (dma_path_ctx[id].bus_id_addr) { + isp_write_reg(dev, dma_path_ctx[id].bus_id_addr, bus_id); + } + isp_write_reg(dev,dma_path_ctx[id].ctrl_addr, path_ctrl); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); +#ifdef ISP_MI_HDR_RY + } else { + REG_SET_SLICE(path_fmt, HDR_RD_STR, dma.rd_wr_str); + //config wr str, l,s,vs bit and wr raw aligned same with rd str,l,s,vs bit and wr raw aligned + path_fmt |= ((path_fmt >> HDR_RD_STR_SHIFT) &0x3ff) ; + isp_write_reg(dev, dma_path_ctx[id].fmt_addr, path_fmt); + + /*hdr mi dma path enable in mi hdr ctrl register*/ + path_ctrl |= (dma_path_ctx[id].path_enable_mask) ; //| dma_path_ctx[id].path_dma_start_mask); + REG_SET_SLICE(path_ctrl, HDR_INIT_OFFSET_EN, 1); + REG_SET_SLICE(path_ctrl, HDR_INIT_BASE_EN, 1); + + REG_SET_SLICE(bus_id, HDR_BUS_SW_EN, 1); + REG_SET_SLICE(bus_id, HDR_RD_ID_EN, 1); + if (dma_path_ctx[id].bus_id_addr) { + isp_write_reg(dev, dma_path_ctx[id].bus_id_addr, bus_id); + } + isp_write_reg(dev,dma_path_ctx[id].ctrl_addr, path_ctrl); +#endif + } + + + return 0; + +} +/* only support read raw */ +int isp_ioc_start_dma_read(struct isp_ic_dev *dev, void __user *args) +{ + start_dma_path_t dma_path; + u32 mi_hdr_fmt; + u32 mi_path_ctrl; + u32 mi_hdr_ret_ctrl; + u32 rd_wr_str; + if (dev == NULL || args == NULL) { + pr_info("input wrong parameter %s\n", __func__); + return -1; + } + + pr_info("enter %s\n", __func__); + viv_check_retval(copy_from_user(&dma_path, args, sizeof(dma_path))); + if (dma_path == ISP_MI_DMA_PATH_MCM_PP) { +#ifndef ISP_MI_PP_READ_RY + mi_path_ctrl = isp_read_reg(dev,REG_ADDR(miv2_ctrl)); + REG_SET_SLICE(mi_path_ctrl, MCM_RAW_RDMA_START, 1); + isp_write_reg(dev,REG_ADDR(miv2_ctrl), mi_path_ctrl); +#else + mi_path_ctrl = isp_read_reg(dev,REG_ADDR(miv2_ctrl)); +#ifdef POST_ISP_SDK_TEST + REG_SET_SLICE(mi_path_ctrl, PP_DMA_START, 1);/*add by shenwuyi must open for sdk test case*/ +#endif + isp_write_reg(dev,REG_ADDR(miv2_ctrl), mi_path_ctrl); +#endif + } else if (dma_path == ISP_MI_DMA_PATH_HDR) { + + isp_write_reg(dev, REG_ADDR(isp_mi_hdr_ret_bus_timeo), 0x00000001); //disable bus time out interrupt + + mi_hdr_ret_ctrl = isp_read_reg(dev,REG_ADDR(isp_hdr_ret_ctrl)); + REG_SET_SLICE(mi_hdr_ret_ctrl, HDR_RT_VSYNC_POL, 1); + REG_SET_SLICE(mi_hdr_ret_ctrl, HDR_RETIMING_ENABLE, 1); + REG_SET_SLICE(mi_hdr_ret_ctrl, DUMP_MODE_EN, 1); + mi_hdr_fmt = isp_read_reg(dev,REG_ADDR(isp_mi_hdr_fmt)); + rd_wr_str = (mi_hdr_fmt & HDR_RD_STR_MASK)>>HDR_RD_STR_SHIFT; + if (rd_wr_str == 0) { + REG_SET_SLICE(mi_hdr_ret_ctrl, EXPOSURE_COUNT, 1); + } else if (rd_wr_str == 1|| rd_wr_str == 3) { + REG_SET_SLICE(mi_hdr_ret_ctrl, EXPOSURE_COUNT, 2); + if (rd_wr_str == 3) { + REG_SET_SLICE(mi_hdr_ret_ctrl, L_VS_COMBINING_ENABLE, 1); + } + } else if (rd_wr_str == 2) { + REG_SET_SLICE(mi_hdr_ret_ctrl, EXPOSURE_COUNT, 0); + } + isp_write_reg(dev, REG_ADDR(isp_mi_hdr_dma_start_by_lines), 0x360);//0x10); //the written lines count of the last appearing frame after which start dma read + isp_write_reg(dev,REG_ADDR(isp_hdr_ret_ctrl), mi_hdr_ret_ctrl); + mi_path_ctrl = isp_read_reg(dev,REG_ADDR(isp_mi_hdr_ctrl)); + REG_SET_SLICE(mi_path_ctrl, HDR_RD_RAW_CFG_UPDATE, 1); + REG_SET_SLICE(mi_path_ctrl, HDR_RD_RAW_AUTO_UPDATE, 1); + + REG_SET_SLICE(mi_path_ctrl, HDR_DMA_START, 1); + isp_write_reg(dev,REG_ADDR(isp_mi_hdr_ctrl), mi_path_ctrl); + + } + return 0; +} + +#define PATHNUM ISP_MI_PATH_ID_MAX// hw related + +// only config write bits, SP2 read bit at 3dnr.c +// read defined is same as write +struct miv2_format_bit { + u32 nyv, nv12; + u32 raw_aligned, yuv_aligned; + u32 raw_bit, yuv_str; + u32 yuv_fmt, yuv_bit, jdp_fmt; +}; + +static struct miv2_format_bit fmt_bit[PATHNUM] = { + { + .nyv = 3 << 13, .nv12 = 1 << 12, + .raw_aligned = 3 << 10, + .yuv_aligned = 1 << 9, + .raw_bit = 7 << 6, + .yuv_str = 3 << 4, + .yuv_fmt = 3 << 2, + .yuv_bit = 1 << 1, + .jdp_fmt = 1, + }, + { + .nyv = 3 << 7, + .nv12 = 1 << 6, + .yuv_aligned = 1 << 5, + .yuv_str = 3 << 3, + .yuv_fmt = 3 << 1, + .yuv_bit = 1, + }, + { + .nyv = 3 << 12, + .nv12 = 1 << 11, + .raw_aligned = 3 << 9, + .yuv_aligned = 1 << 8, + .raw_bit = 7 << 5, + .yuv_str = 3 << 3, + .yuv_fmt = 3 << 1, + .yuv_bit = 1, + }, +#ifdef ISP_MI_MCM_WR_RY + { + .nyv = 0, + .nv12 = 0, + .raw_aligned = 3 << 14, + .raw_bit = 3 << 4, + .yuv_aligned = 0, + .yuv_str = 0, + .yuv_fmt = 0, + .yuv_bit = 0, + }, + { + .nyv = 0, + .nv12 = 0, + .raw_aligned = 3 << 16, + .raw_bit = 3 << 8, + .yuv_aligned = 0, + .yuv_str = 0, + .yuv_fmt = 0, + .yuv_bit = 0, + }, +#endif +#ifdef ISP_MI_PP_WRITE_RY + { + .nyv = 3 << 7, + .nv12 = 1 << 6, + .raw_aligned = 3 << 14, + .raw_bit = 7 << 11, + .yuv_aligned = 1 << 5, + .yuv_str = 3 << 3, + .yuv_fmt = 3 << 1, + .yuv_bit = 1, + }, +#endif +#ifdef ISP_MI_HDR_RY + { + .nyv = 0, + .nv12 = 0, + .raw_aligned = 3 << 8, + .raw_bit = 3 << 2, + .yuv_aligned = 0, + .yuv_str = 0, + .yuv_fmt = 0, + .yuv_bit = 0, + }, + { + .nyv = 0, + .nv12 = 0, + .raw_aligned = 3 << 8, + .raw_bit = 3 << 4, + .yuv_aligned = 0, + .yuv_str = 0, + .yuv_fmt = 0, + .yuv_bit = 0, + }, + { + .nyv = 0, + .nv12 = 0, + .raw_aligned = 3 << 8, + .raw_bit = 3 << 6, + .yuv_aligned = 0, + .yuv_str = 0, + .yuv_fmt = 0, + .yuv_bit = 0, + }, +#endif +}; + +static u32 bit_shift(u32 i) { + u32 shift = 0; + while(!(i&1)) { + shift++; + i >>= 1; + } + return shift; +} + +void mi_set_slice(u32* val, u32 mask, u32 slice) +{ + // mp, sp1, sp2 mcm postpath have different masks. + if (mask) { + *val &= ~mask; + *val |= (slice << bit_shift(mask)); + } +} + +struct miv2_path_address { + u32 bus_cfg_addr; + u32 bus_id_addr; + u32 bus_timeo_addr; //axi bus time out waiting ctrl register + u32 path_ctrl_addr; + u32 format_addr; + u32 y_length_addr; + u32 raw_llength_addr; + u32 raw_pic_width_addr; + u32 raw_pic_height_addr; + u32 raw_pic_size_addr; + u32 ycbcr_enable_bit; + u32 raw_enable_bit; + u32 format_conv_ctrl; + u32 wr_raw_swap_bit; +}; + +static void disable_bus_timeo_intr(struct isp_ic_dev *dev, u32 bus_addr) +{ + u32 val; + pr_info("%s bus timeo interrupt register addr 0x%08x\n", __func__, bus_addr); + val = isp_read_reg(dev, bus_addr); + REG_SET_SLICE(val, MP_BUS_TIMEO_INTERRUPT_DISABLE, 1); + isp_write_reg(dev, bus_addr, val); +} + +static void set_data_path(int id, struct isp_mi_data_path_context *path, + struct isp_ic_dev *dev) +{ + u32 bus_cfg, bus_id; + u32 format; + u32 miv2_ctrl; + u32 path_ctrl; + u32 lval; + u32 acq_proc; + u32 mcm_bus_cfg = isp_read_reg(dev, REG_ADDR(miv2_mcm_bus_cfg)); + u32 conv_format_ctrl = 0; + u32 y_length_addr; + u32 y_llength = 0; +#ifdef ISP_MI_PP_WRITE_RY + u32 isp_ctrl; +#endif + // please take care the register order +#if 0 + struct miv2_path_address path_list[PATHNUM] = { + { 0x1318, 0x131c, 0x1310, 0x1314, 0x1330, 0x13a0, 0x13a4, 0x13a8, 0x13ac, 1, 0x0c6c }, + { 0x1434, 0x1438, 0x142c, 0x1430, 0x144c, 0, 0, 0, 8, 0x106c }, + { 0x14ec, 0x14f0, 0x14e4, 0x14e8, 0x1504, 0x1574, 0x1578, 0x157c, 0x1580, 0x10, 0x116c }, + }; +#else + //id 0 is mp path;id 1 is sp path;id 2 is sp2 path; + //id 3 is post process path write; + struct miv2_path_address path_list[PATHNUM] = { + { + REG_ADDR(miv2_mp_bus_cfg), REG_ADDR(miv2_mp_bus_id), REG_ADDR(miv2_mp_bus_timeo), REG_ADDR(miv2_mp_ctrl), + REG_ADDR(miv2_mp_fmt), REG_ADDR(miv2_mp_y_llength), REG_ADDR(miv2_mp_raw_llength), + REG_ADDR(miv2_mp_raw_pic_width), REG_ADDR(miv2_mp_raw_pic_height), REG_ADDR(miv2_mp_raw_pic_size), + MP_YCBCR_PATH_ENABLE_MASK, MP_RAW_PATH_ENABLE_MASK, REG_ADDR(mrsz_format_conv_ctrl), MP_WR_SWAP_RAW_MASK + }, + { + REG_ADDR(miv2_sp1_bus_cfg), REG_ADDR(miv2_sp1_bus_id), REG_ADDR(miv2_sp1_bus_timeo), REG_ADDR(miv2_sp1_ctrl), + REG_ADDR(miv2_sp1_fmt), REG_ADDR(miv2_sp1_y_llength), 0, + 0, 0, 0, + SP1_YCBCR_PATH_ENABLE_MASK, 0, REG_ADDR(srsz_phase_format_conv_ctr), 0, + }, + { + REG_ADDR(miv2_sp2_bus_cfg), REG_ADDR(miv2_sp2_bus_id), REG_ADDR(miv2_sp2_bus_timeo), REG_ADDR(miv2_sp2_ctrl), + REG_ADDR(miv2_sp2_fmt), REG_ADDR(miv2_sp2_y_llength), REG_ADDR(miv2_sp2_raw_llength), + REG_ADDR(miv2_sp2_raw_pic_width), REG_ADDR(miv2_sp2_raw_pic_height), REG_ADDR(miv2_sp2_raw_pic_size), + SP2_YCBCR_PATH_ENABLE_MASK, SP2_RAW_PATH_ENABLE_MASK, REG_ADDR(srsz2_phase_format_conv_ctr), + SP2_WR_SWAP_RAW_MASK + }, +#ifdef ISP_MI_MCM_WR_RY + { + REG_ADDR(miv2_mcm_bus_cfg), REG_ADDR(miv2_mcm_bus_id), REG_ADDR(miv2_mcm_bus_timeo), REG_ADDR(miv2_mcm_ctrl), + REG_ADDR(miv2_mcm_fmt), 0, REG_ADDR(miv2_mcm_raw0_llength), + REG_ADDR(miv2_mcm_raw0_pic_width), REG_ADDR(miv2_mcm_raw0_pic_height), REG_ADDR(miv2_mcm_raw0_pic_size), + 0, MCM_RAW0_PATH_ENABLE_MASK, 0, MCM_WR0_SWAP_RAW_MASK + }, + + { + REG_ADDR(miv2_mcm_bus_cfg), REG_ADDR(miv2_mcm_bus_id), REG_ADDR(miv2_mcm_bus_timeo), REG_ADDR(miv2_mcm_ctrl), + REG_ADDR(miv2_mcm_fmt), 0, REG_ADDR(miv2_mcm_raw1_llength), + REG_ADDR(miv2_mcm_raw1_pic_width), REG_ADDR(miv2_mcm_raw1_pic_height), REG_ADDR(miv2_mcm_raw1_pic_size), + 0, MCM_RAW1_PATH_ENABLE_MASK, 0, MCM_WR1_SWAP_RAW_MASK + }, +#endif + { + REG_ADDR(isp_mi_pp_data_swap), REG_ADDR(miv2_sp1_bus_id), REG_ADDR(miv2_sp1_bus_timeo), REG_ADDR(isp_mi_pp_ctrl), + REG_ADDR(isp_mi_pp_fmt), REG_ADDR(isp_mi_pp_y_llength), REG_ADDR(mi_pp_y_lval_bytes), + REG_ADDR(isp_mi_pp_y_pic_width), REG_ADDR(isp_mi_pp_y_pic_height), REG_ADDR(isp_mi_pp_y_pic_size), + PP_WRITE_PATH_ENABLE_MASK, PP_WRITE_PATH_ENABLE_MASK, 0,PP_WR_SWAP_Y_MASK + }, +#ifdef ISP_MI_HDR_RY + { + REG_ADDR(isp_mi_hdr_ret_bus_cfg), REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(isp_mi_hdr_ret_bus_timeo), + REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_l_llength), + REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_pic_height), REG_ADDR(isp_mi_hdr_l_size_init), + 0, HDR_WR_ENABLE_MASK, 0, HDR_WR_SWAP_RAW_MASK + }, + + { + REG_ADDR(isp_mi_hdr_ret_bus_cfg), REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(isp_mi_hdr_ret_bus_timeo), + REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_s_llength), + REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_pic_height), REG_ADDR(isp_mi_hdr_s_size_init), + 0, HDR_WR_ENABLE_MASK, 0, HDR_WR_SWAP_RAW_MASK + }, + { + REG_ADDR(isp_mi_hdr_ret_bus_cfg), REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(isp_mi_hdr_ret_bus_timeo), + REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_vs_llength), + REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_pic_height), REG_ADDR(isp_mi_hdr_vs_size_init), + 0, HDR_WR_ENABLE_MASK, 0, HDR_WR_SWAP_RAW_MASK + }, +#endif + + }; +#endif + + if (!path->enable) { + disable_bus_timeo_intr(dev, path_list[id].bus_timeo_addr); + return; + } + + + if (path->hscale || path->vscale || dev->is.enable) { + if (id <= ISP_MI_PATH_SP2_BP) + isp_set_scaling(id, dev, dev->is.enable, dev->crop[id].enabled); + else + isp_set_scaling(id, dev, dev->is.enable, 0); + + } + + miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + if(path_list[id].bus_cfg_addr) + bus_cfg = isp_read_reg(dev, path_list[id].bus_cfg_addr); + format = isp_read_reg(dev, path_list[id].format_addr); + if (path_list[id].format_conv_ctrl) { + conv_format_ctrl = isp_read_reg(dev, path_list[id].format_conv_ctrl); + } + pr_err("mi %s id %d fmt_bit[id].raw_bit 0x%08x miv2_ctrl 0x%08x ", __func__, id, path_list[id].raw_enable_bit, miv2_ctrl); + + path_ctrl = isp_read_reg(dev, path_list[id].path_ctrl_addr); + switch (path->out_mode) { + case IC_MI_DATAMODE_YUV444: + mi_set_slice(&format, fmt_bit[id].yuv_fmt, 2); + miv2_ctrl |= path_list[id].ycbcr_enable_bit; + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_OUTPUT, 3); + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_INPUT, 2); + break; + case IC_MI_DATAMODE_YUV422: + mi_set_slice(&format, fmt_bit[id].yuv_fmt, 1); + miv2_ctrl |= path_list[id].ycbcr_enable_bit; + break; + case IC_MI_DATAMODE_YUV420: + mi_set_slice(&format, fmt_bit[id].yuv_fmt, 0); + miv2_ctrl |= path_list[id].ycbcr_enable_bit; + break; + case IC_MI_DATAMODE_YUV400: + case IC_MI_DATAMODE_JPEG: + mi_set_slice(&format, fmt_bit[id].jdp_fmt, 1); + REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1); + break; + case IC_MI_DATAMODE_RAW8: + mi_set_slice(&format, fmt_bit[id].raw_bit, 0); + miv2_ctrl |= path_list[id].raw_enable_bit; + break; + case IC_MI_DATAMODE_RAW10: + mi_set_slice(&format, fmt_bit[id].raw_bit, 1); + miv2_ctrl |= path_list[id].raw_enable_bit; + + mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + break; + case IC_MI_DATAMODE_RAW12: +#ifdef ISP_MI_HDR_RY + if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) { + mi_set_slice(&format, fmt_bit[id].raw_bit, 0); + path_ctrl |= path_list[id].raw_enable_bit; + //mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + } +#endif + if (id <= ISP_MI_PATH_PP) { + mi_set_slice(&format, fmt_bit[id].raw_bit, 2); + miv2_ctrl |= path_list[id].raw_enable_bit; + mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + } + break; + case IC_MI_DATAMODE_RAW14: + mi_set_slice(&format, fmt_bit[id].raw_bit, 3); + miv2_ctrl |= path_list[id].raw_enable_bit; + + mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + break; + case IC_MI_DATAMODE_RAW16: +#ifdef ISP_MI_HDR_RY + if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) { + mi_set_slice(&format, fmt_bit[id].raw_bit, 1); + path_ctrl |= path_list[id].raw_enable_bit; + //mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + } +#endif + if (id <= ISP_MI_PATH_PP) { + mi_set_slice(&format, fmt_bit[id].raw_bit, 4); + miv2_ctrl |= path_list[id].raw_enable_bit; + mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); + } + break; + case IC_MI_DATAMODE_RGB888: + mi_set_slice(&format, fmt_bit[id].yuv_fmt, 2); + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_OUTPUT, 6); + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_INPUT, 2); + miv2_ctrl |= path_list[id].ycbcr_enable_bit; + break; + default: + pr_err("mi %s unsupport format: %d", __func__, path->out_mode); + return; + } + + switch (path->data_layout) { + case IC_MI_DATASTORAGE_PLANAR: + mi_set_slice(&format, fmt_bit[id].yuv_str, 2); + break; + case IC_MI_DATASTORAGE_SEMIPLANAR: + mi_set_slice(&format, fmt_bit[id].yuv_str, 0); + break; + case IC_MI_DATASTORAGE_INTERLEAVED: + mi_set_slice(&format, fmt_bit[id].yuv_str, 1); + break; + default: + break; + } + + mi_set_slice(&format, fmt_bit[id].yuv_bit, path->yuv_bit); + if(path->yuv_bit){ + if(path->data_alignMode){ + mi_set_slice(&format, fmt_bit[id].yuv_aligned, 1); + }else{ + mi_set_slice(&format, fmt_bit[id].yuv_aligned, 0); + } + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_10_ENABLE, 1); + REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_10_METHOD, 0); + } + + mi_set_slice(&format, fmt_bit[id].raw_aligned, path->data_alignMode); + if (id == ISP_MI_PATH_MP) + REG_SET_SLICE(bus_cfg, MP_WR_BURST_LEN, dev->mi.burst_len); + REG_SET_SLICE(mcm_bus_cfg, MCM_WR_BURST_LEN, dev->mi.burst_len); + + + if(path->yuv_bit){// + if(path->data_alignMode){//aligned mode + lval = (path->out_width + 12 - 1)/12; + //printf("zw debug lval = 0x%x\n",lval); + }else{ //unaligned mode + lval = (path->out_width * 10 + 127)/128; + } + y_llength =lval<<4; + //printf("zw debug y_llength = 0x%x\n",y_llength); + }else{ //8bit output + y_llength = ALIGN_16BYTE(path->out_width); + } + + y_length_addr = path_list[id].y_length_addr; + if (y_length_addr) { + isp_write_reg(dev, y_length_addr, y_llength); + isp_write_reg(dev, y_length_addr + 4, path->out_width); + isp_write_reg(dev, y_length_addr + 8, path->out_height); + isp_write_reg(dev, y_length_addr + 12, + y_llength * path->out_height); + } + // aev2, 3dnr + if (id == ISP_MI_PATH_MP) { + if (dev->exp2.enable) { + REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1); +#ifdef ISP_AEV2_V2_RY + REG_SET_SLICE(format, MP_WR_JDP_DP_BIT, 1); +#endif + } else { + REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 0); + } + } + + if ((id == ISP_MI_PATH_MP && (miv2_ctrl & MP_RAW_PATH_ENABLE_MASK)) || + (id == ISP_MI_PATH_SP2_BP && (miv2_ctrl & SP2_RAW_PATH_ENABLE_MASK)) +#ifdef ISP_MI_MCM_WR_RY + || (id == ISP_MI_MCM_WR0 && (miv2_ctrl & MCM_RAW0_PATH_ENABLE_MASK)) || + (id == ISP_MI_MCM_WR1 && (miv2_ctrl & MCM_RAW1_PATH_ENABLE_MASK)) +#endif +#ifdef ISP_MI_PP_WRITE_RY + || (id == ISP_MI_PATH_PP && ((path->out_mode == IC_MI_DATAMODE_RAW8) || + (path->out_mode == IC_MI_DATAMODE_RAW10) || (path->out_mode == IC_MI_DATAMODE_RAW12) || + (path->out_mode == IC_MI_DATAMODE_RAW14) || (path->out_mode == IC_MI_DATAMODE_RAW16))) +#endif +#ifdef ISP_MI_HDR_RY + || (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) +#endif + ) { + lval = + calc_raw_lval(path->out_width, path->out_mode, + path->data_alignMode); + y_llength = lval <<4; + isp_write_reg(dev, path_list[id].raw_llength_addr, y_llength); + isp_write_reg(dev, path_list[id].raw_pic_width_addr, path->out_width); + isp_write_reg(dev, path_list[id].raw_pic_height_addr, path->out_height); + isp_write_reg(dev, path_list[id].raw_pic_size_addr, path->out_height * y_llength ); +#ifdef ISP_MI_MCM_WR_RY + if (id == ISP_MI_MCM_WR0 || id == ISP_MI_MCM_WR1) { + isp_write_reg(dev, REG_ADDR(miv2_mcm_raw0_lval_bytes), y_llength); + } +#endif +#ifdef ISP_MI_PP_WRITE_RY + //ppw line entry mode, llength need to align with 256. + //llength is line length, lval is line availble data. +#if 1/*should check by VV, if align with 256 is needed*/ + uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num)); + /*TODO shenweiyi to enable */ + if (line_num != 0) { + y_llength = y_llength & 0xff ? (y_llength & 0xffffff00 + 0x100):y_llength; + } + pr_info("%s:line_num = %d y_llength = 0x%x\n", __func__, line_num, y_llength); + isp_write_reg(dev, REG_ADDR(isp_mi_pp_y_llength), y_llength); + isp_write_reg(dev, path_list[id].raw_pic_size_addr, path->out_height * y_llength ); +#else + if (id == ISP_MI_PATH_PP) { + uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num)); + if (line_num != 0) { + y_llength = (y_llength & 0xff) ? ((y_llength + 0xff) &(~0xff)):y_llength; + } + isp_write_reg(dev, REG_ADDR(isp_mi_pp_y_llength), y_llength); + isp_write_reg(dev, path_list[id].raw_pic_size_addr, path->out_height * y_llength ); + } +#endif +#endif +#if defined(ISP_MI_HDR_RY) + if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) + isp_write_reg(dev, path_list[id].raw_llength_addr+4, y_llength); +#endif + } + +#ifdef ISP_MI_HDR_RY + if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) { + REG_SET_SLICE(path_ctrl, HDR_MI_CFG_UPD, 1); + REG_SET_SLICE(path_ctrl, HDR_AUTO_UPDATE, 1); + path_ctrl |= (HDR_INIT_OFFSET_EN_MASK | HDR_INIT_BASE_EN_MASK); + } +#endif + if (id <= ISP_MI_PATH_PP) { + REG_SET_SLICE(path_ctrl, MP_MI_CFG_UPD, 1); + REG_SET_SLICE(path_ctrl, MP_AUTO_UPDATE, 1); + //path_ctrl |= 0x05; + path_ctrl |= (MP_INIT_BASE_EN_MASK | MP_INIT_OFFSET_EN_MASK); + } +#ifdef ISP_MI_MCM_WR_RY + if (id <= ISP_MI_MCM_WR1 && id >= ISP_MI_MCM_WR0) { + REG_SET_SLICE(path_ctrl, MCM_WR_CFG_UPD, 1); + REG_SET_SLICE(path_ctrl, MCM_WR_AUTO_UPDATE, 1); + //path_ctrl |= 0x05; + path_ctrl |= (MCM_INIT_BASE_EN_MASK | MCM_INIT_OFFSET_EN_MASK); + } +#endif + + pr_info("%s:path_ctrl 0x%08x\n", __func__, path_ctrl); + acq_proc = isp_read_reg(dev, REG_ADDR(isp_acq_prop)); + isp_write_reg(dev, REG_ADDR(isp_acq_prop), + acq_proc & ~MRV_ISP_LATENCY_FIFO_SELECTION_MASK); + + bus_id = isp_read_reg(dev, path_list[id].bus_id_addr); + if (id == ISP_MI_PATH_SP) { + bus_id <<= 4; + } + bus_id |= MP_WR_ID_EN_MASK; + if (id == ISP_MI_PATH_SP2_BP) { + bus_id |= SP2_BUS_SW_EN_MASK; + // REG_SET_SLICE(bus_cfg, SP2_WR_SWAP_Y, 1); +#ifdef ISP_MI_HDR_RY + } else if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS ) { + bus_id |= HDR_BUS_SW_EN_MASK; +#endif + } else { + bus_id |= MP_BUS_SW_EN_MASK; + } + if (path_list[id].bus_id_addr) + isp_write_reg(dev, path_list[id].bus_id_addr, bus_id); + + if (path_list[id].bus_cfg_addr) + isp_write_reg(dev, path_list[id].bus_cfg_addr, bus_cfg); + + isp_write_reg(dev, REG_ADDR(miv2_mcm_bus_cfg), mcm_bus_cfg); +#ifdef ISP_MI_PP_WRITE_RY + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + if (id == ISP_MI_PATH_PP && ((path->out_mode == IC_MI_DATAMODE_RAW8) || + (path->out_mode == IC_MI_DATAMODE_RAW10) || (path->out_mode == IC_MI_DATAMODE_RAW12) || + (path->out_mode == IC_MI_DATAMODE_RAW14) || (path->out_mode == IC_MI_DATAMODE_RAW16))) { //pp path output raw + format |= PP_WR_RAW_SEL_MASK; + REG_SET_SLICE(format, PP_WR_RAW_SEL, 1); + REG_SET_SLICE(isp_ctrl, PP_WRITE_SEL, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + } else { + REG_SET_SLICE(format, PP_WR_RAW_SEL, 0); + REG_SET_SLICE(isp_ctrl, PP_WRITE_SEL, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } +#endif + isp_write_reg(dev, path_list[id].format_addr, format); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + isp_write_reg(dev, path_list[id].path_ctrl_addr, path_ctrl); + + if (path_list[id].format_conv_ctrl) + isp_write_reg(dev, path_list[id].format_conv_ctrl, conv_format_ctrl); + +} + +int isp_mi_start(struct isp_ic_dev *dev) +{ + int i; + struct isp_mi_context mi = *(&dev->mi); + u32 imsc, miv2_mcm_bus_id; + pr_info("enter %s\n", __func__); + + miv2_mcm_bus_id = isp_read_reg(dev, REG_ADDR(miv2_mcm_bus_id)); + miv2_mcm_bus_id |= MCM_BUS_SW_EN_MASK; + isp_write_reg(dev, REG_ADDR(miv2_mcm_bus_id), miv2_mcm_bus_id); + + for (i = 0; i < ISP_MI_PATH_ID_MAX; i++) { + set_data_path(i, &mi.path[i], dev); + } + + imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc)); + isp_write_reg(dev, REG_ADDR(miv2_imsc), + imsc | (MP_YCBCR_FRAME_END_MASK | MP_RAW_FRAME_END_MASK | + WRAP_MP_Y_MASK | WRAP_MP_CB_MASK | WRAP_MP_CR_MASK | + WRAP_MP_RAW_MASK | WRAP_MP_JDP_MASK | MCM_RAW0_FRAME_END_MASK | + SP1_YCBCR_FRAME_END_MASK | WRAP_SP1_Y_MASK |MCM_RAW1_FRAME_END_MASK| + WRAP_SP1_CB_MASK | WRAP_SP1_CR_MASK | + SP2_YCBCR_FRAME_END_MASK | WRAP_SP2_Y_MASK | + WRAP_SP2_CB_MASK | WRAP_SP2_CR_MASK | + SP2_RAW_FRAME_END_MASK | MP_JDP_FRAME_END_MASK)); + + + //isp_write_reg(dev, REG_ADDR(miv2_imsc1), 0x7ffffff); + isp_write_reg(dev, REG_ADDR(miv2_imsc1), 0); +#ifdef ISP_MI_PP_WRITE_RY + imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc2)); + isp_write_reg(dev, REG_ADDR(miv2_imsc2), + imsc | ( PPW_U_BUF_FULL_MASK | PPW_Y_BUF_FULL_MASK | + PPW_V_BUF_FULL_MASK | PPR_Y_BUF_FULL_MASK | SP2_RAW2_W_BUF_FULL_MASK | + SP2_RAW2_R_BUF_FULL_MASK | HDR_W_BUF_FULL_MASK | HDR_R_BUF_FULL_MASK | + WRAP_SP2_RAW_MASK | WRAP_PPW_CR_MASK | WRAP_PPW_CB_MASK | //WRAP_PPW_Y_MASK | + SP2_RAW2_FRAME_END_MASK | PPW_FRAME_END_MASK | HDR_VS_DMA_READY_MASK | + HDR_S_DMA_READY_MASK | HDR_L_DMA_READY_MASK | HDR_L_DMA_READY_MASK | + WRAP_HDR_VS_MASK | WRAP_HDR_S_MASK | WRAP_HDR_L_MASK | HDR_VS_FRAME_END_MASK | + HDR_S_FRAME_END_MASK | HDR_L_FRAME_END_MASK | MI_RT_BUS_BUSERR_MASK | + MI_RT_BUS_TIMEO_MASK)); +#endif + isp_write_reg(dev, REG_ADDR(miv2_imsc3), 0x3f); + /*add by shenwuyi for ppline entry must close for sdk test case*/ +#ifndef POST_ISP_SDK_TEST + isp_write_reg(dev, REG_ADDR(miv2_imsc), 0x19); + isp_write_reg(dev, REG_ADDR(miv2_imsc1), 0); + isp_write_reg(dev, REG_ADDR(miv2_imsc2), 0); +#endif + return 0; +} + +int isp_mi_stop(struct isp_ic_dev *dev) +{ + pr_info("enter %s\n", __func__); +#ifdef ISP_MI_PP_WRITE_RY + isp_write_reg(dev, REG_ADDR(miv2_imsc2), 0); +#endif + isp_write_reg(dev, REG_ADDR(miv2_imsc3), 0); + isp_write_reg(dev, REG_ADDR(miv2_imsc), 0); + isp_write_reg(dev, REG_ADDR(miv2_imsc1), 0); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), 0UL); + return 0; +} + +u32 isp_read_mi_irq(struct isp_ic_dev *dev) +{ + return isp_read_reg(dev, REG_ADDR(miv2_mis)); +} + +void isp_reset_mi_irq(struct isp_ic_dev *dev, u32 icr) +{ + isp_write_reg(dev, REG_ADDR(miv2_icr), icr); +} + +int isp_set_bp_buffer(struct isp_ic_dev *dev, struct isp_bp_buffer_context *buf) +{ + return 0; +} +#ifdef ISP_MI_PP_WRITE_RY + +int isp_set_ppw_line_num(struct isp_ic_dev *dev) +{ + if (dev == NULL) { + pr_err("Wrong input %s\n", __func__); + return -1; + } + pr_info("enter %s\n", __func__); + + isp_write_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num), dev->pp_write.entry_line_num); + pr_info("exit %s\n", __func__); + return 0; +} +int isp_get_ppw_pic_cnt(struct isp_ic_dev *dev, u16* pic_cnt) +{ + + if (dev == NULL) { + pr_err("Wrong input %s\n", __func__); + return -1; + } + pr_info("enter %s\n", __func__); + *pic_cnt = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_pic_cnt)); + pr_info("exit %s\n", __func__); + return 0; +} +#endif + +#ifdef ISP_MI_PP_READ_RY +int isp_cfg_pp_dma_line_entry(struct isp_ic_dev *dev) +{ + pr_info("enter %s\n", __func__); + uint32_t path_ctrl = isp_read_reg(dev, REG_ADDR(isp_mi_pp_ctrl)); + pp_dma_line_entry_t* pp_dam_line_entry = &dev->pp_dma_line_entry; + if (dev == NULL) { + pr_err("Wrong input %s\n", __func__); + return -1; + } + + isp_write_reg(dev, REG_ADDR(mi_pp_dma_y_entry_line_num), pp_dam_line_entry->entry_line_num); + isp_write_reg(dev, REG_ADDR(mi_pp_dma_y_buf_line_num), pp_dam_line_entry->buf_line_num); +#ifndef POST_ISP_SDK_TEST + isp_write_reg(dev, 0x00005598, pp_dam_line_entry->buf_addr);/*add by shenwuyi for line entry mode*/ + mi_set_slice(&path_ctrl, PP_RD_YUV_CFG_UPDATE_MASK, 1); + isp_write_reg(dev, REG_ADDR(isp_mi_pp_ctrl), path_ctrl); +#endif + pr_info("exit %s\n", __func__); + return 0; +} +#endif +#endif diff --git a/vvcam_ry/isp/isp_rgbgamma.c b/vvcam_ry/isp/isp_rgbgamma.c new file mode 100755 index 0000000..91342a0 --- /dev/null +++ b/vvcam_ry/isp/isp_rgbgamma.c @@ -0,0 +1,217 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#else +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; + +int isp_enable_rgbgamma(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBGC_RY + pr_err("unsupported function %s\n", __func__); + return -1; +#else + + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + REG_SET_SLICE(isp_ctrl, ISP_RGBGC_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + dev->rgbgamma.enable = true; + return 0; +#endif +} + +int isp_disable_rgbgamma(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBGC_RY + pr_err("unsupported function %s\n", __func__); + return -1; +#else + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + REG_SET_SLICE(isp_ctrl, ISP_RGBGC_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + dev->rgbgamma.enable = false; + return 0; +#endif +} + +#ifdef ISP_RGBGC_RY +static int isp_s_rgbgammapx(struct isp_ic_dev *dev, struct isp_rgbgamma_data *data) +{ + + u32 isp_gc_px_reg = REG_ADDR(isp_gcrgb_r_px_0); + u32 *p_table = NULL; + int i; + u32 gc_px_data = 0; + + p_table = (u32 *)&data->rgbgc_r_px; + for (i = 0; i < 64; i++) { + gc_px_data |= (*(p_table + i) << (i % 6 * 5)); + if (i % 6 == 5 || i == 63) { + isp_write_reg(dev, isp_gc_px_reg, gc_px_data); + isp_gc_px_reg += 4; + gc_px_data = 0; + } + } + + isp_gc_px_reg = REG_ADDR(isp_gcrgb_g_px_0); + p_table = (u32 *)&data->rgbgc_g_px; + for (i = 0; i < 64; i++) { + gc_px_data |= (*(p_table + i) << (i % 6 * 5)); + if (i % 6 == 5 || i == 63) { + isp_write_reg(dev, isp_gc_px_reg, gc_px_data); + isp_gc_px_reg += 4; + gc_px_data = 0; + } + } + isp_gc_px_reg = REG_ADDR(isp_gcrgb_b_px_0); + p_table = (u32 *)&data->rgbgc_b_px; + for (i = 0; i < 64; i++) { + gc_px_data |= (*(p_table + i) << (i % 6 * 5)); + if (i % 6 == 5 || i == 63) { + isp_write_reg(dev, isp_gc_px_reg, gc_px_data); + isp_gc_px_reg += 4; + gc_px_data = 0; + } + } + + return 0; +} +#endif + +#ifdef ISP_RGBGC_RY +static int isp_s_rgbgammaWriteData(struct isp_ic_dev *dev, + struct isp_rgbgamma_data *data) +{ + u32 isp_gc_y_data, isp_gc_x_data; + int i; + u32 *tblX, *tblY; + + isp_write_reg(dev, REG_ADDR(isp_gcrgb_r_x_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_r_y_addr), 0); + + isp_write_reg(dev, REG_ADDR(isp_gcrgb_g_x_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_g_y_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_b_x_addr), 0); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_b_y_addr), 0); + + tblX = data->rgbgc_r_datax; + tblY = data->rgbgc_r_datay; + for (i = 0; i < 64; i++) { + isp_gc_y_data = *(tblY + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_r_y_write_data), + isp_gc_y_data); + } + for (i = 0; i < 63; i++) { + isp_gc_x_data = *(tblX + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_r_x_write_data), + isp_gc_x_data); + } + + tblX = data->rgbgc_g_datax; + tblY = data->rgbgc_g_datay; + for (i = 0; i < 64; i++) { + isp_gc_y_data = *(tblY + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_g_y_write_data), + isp_gc_y_data); + } + for (i = 0; i < 63; i++) { + isp_gc_x_data = *(tblX + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_g_x_write_data), + isp_gc_x_data); + } + tblX = data->rgbgc_b_datax; + tblY = data->rgbgc_b_datay; + for (i = 0; i < 64; i++) { + isp_gc_y_data = *(tblY + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_b_y_write_data), + isp_gc_y_data); + } + for (i = 0; i < 63; i++) { + isp_gc_x_data = *(tblX + i); + isp_write_reg(dev, REG_ADDR(isp_gcrgb_b_x_write_data), + isp_gc_x_data); + } + return 0; +} +#endif + +int isp_s_rgbgamma(struct isp_ic_dev *dev, struct isp_rgbgamma_data *data) +{ +#ifndef ISP_RGBGC_RY + pr_err("unsupported function %s", __func__); + return -1; +#else + u8 ret; + u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + + REG_SET_SLICE(isp_ctrl, ISP_RGBGC_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + + isp_s_rgbgammapx(dev, data); + isp_s_rgbgammaWriteData(dev, data); + ret = 0; + if (dev->rgbgamma.enable) { + ret = isp_enable_rgbgamma(dev); + } + return ret; +#endif +} diff --git a/vvcam_ry/isp/isp_rgbir.c b/vvcam_ry/isp/isp_rgbir.c new file mode 100755 index 0000000..fdd9607 --- /dev/null +++ b/vvcam_ry/isp/isp_rgbir.c @@ -0,0 +1,401 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +extern MrvAllRegister_t *all_regs; +enum { + ISP_RGBIR_OUT_BAT_RGGB = 0, + ISP_RGBIR_OUT_BAT_GRBG, + ISP_RGBIR_OUT_BAT_GBRG, + ISP_RGBIR_OUT_BAT_BGGR +}; + +enum { + ISP_RGBIR_BAT_BGGIR = 0, + ISP_RGBIR_BAT_GRIRG, + ISP_RGBIR_BAT_RGGIR, + ISP_RGBIR_BAT_GBIRG, + ISP_RGBIR_BAT_GIRRG, + ISP_RGBIR_BAT_IRGGB, + ISP_RGBIR_BAT_GIRBG, + ISP_RGBIR_BAT_IRGGR, + ISP_RGBIR_BAT_RGIRB, + ISP_RGBIR_BAT_GRBIR, + ISP_RGBIR_BAT_IRBRG, + ISP_RGBIR_BAT_BIRGR, + ISP_RGBIR_BAT_BGIRR, + ISP_RGBIR_BAT_GBRIR, + ISP_RGBIR_BAT_IRRBG, + ISP_RGBIR_BAT_RIRGB, +}; + +int isp_rgbir_s_bls(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR_RY + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_context rgbir = *(&dev->rgbir); + struct isp_rgbir_bls_context* bls = &rgbir.bls; + isp_info("enter %s\n", __func__); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_a), bls->a); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_b), bls->b); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_c), bls->c); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_d), bls->d); + return 0; +#endif +} + +int isp_rgbir_s_gain(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR_RY + isp_err("unsupported function %s", __func__); + return -1; +#else + + struct isp_rgbir_context rgbir = *(&dev->rgbir); + struct isp_rgbir_rgb_gain_context* rgb_gain = &rgbir.rgb_gain; + isp_info("enter %s\n", __func__); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_gain_r), rgb_gain->r); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_gain_g), rgb_gain->g); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_gain_b), rgb_gain->b); + + return 0; +#endif +} + +int isp_rgbir_s_dpcc(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR_RY + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_dpcc_context *dpcc = &dev->rgbir.dpcc; + int i; + u32 isp_pre_filt_dpc_th_r; + + isp_info("enter %s\n", __func__); + + for (i = 0; i < 4; i++) { + isp_pre_filt_dpc_th_r = isp_read_reg(dev, REG_ADDR(isp_pre_filt_dpc_th_r) + i * ISP_REG_GAP); + REG_SET_SLICE(isp_pre_filt_dpc_th_r, ISP_PRE_FILT_DPC_TH_MED_R, dpcc->median_thr[i]); + REG_SET_SLICE(isp_pre_filt_dpc_th_r, ISP_PRE_FILT_DPC_TH_AVG_R, dpcc->avg_thr[i]); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_dpc_th_r) + i * ISP_REG_GAP, isp_pre_filt_dpc_th_r); + + } + return 0; +#endif +} + +int isp_rgbir_s_cc_matrix(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR_RY + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_cc_context *cc = &dev->rgbir.cc; //cc color correct + int i; + const u8 reg_gap = 8; + u32 isp_pre_filt_cc_00_01; + isp_info("enter %s\n", __func__); + + for (i = 0; i < 3; i++) { + + isp_pre_filt_cc_00_01 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + i * reg_gap); + REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_00, (u32)(cc->mtx[i][0] )); + REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_01, (u32)(cc->mtx[i][1] )); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + i * reg_gap, isp_pre_filt_cc_00_01); + + isp_pre_filt_cc_00_01 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + i * reg_gap + ISP_REG_GAP); + REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_02, (u32)(cc->mtx[i][2] )); + REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_03, (u32)(cc->mtx[i][3] )); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + (i * reg_gap) + ISP_REG_GAP, isp_pre_filt_cc_00_01); + } + return 0; +#endif +} + +int isp_rgbir_s_des(struct isp_ic_dev *dev) //de-saturation +{ +#ifndef ISP_RGBIR_RY + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_des_context *des = &dev->rgbir.des; //cc color correct + int i; + u32 isp_pre_filt_ir_des_pd1; // isp_pre_filt_ir_des_px1, isp_pre_filt_ir_des_py1; + u32 isp_pre_filt_l_des_pd1; // isp_pre_filt_l_des_px1, isp_pre_filt_l_des_py1; + + isp_info("enter %s\n", __func__); + //register value + for (i = 0 ; i < 4; i++) { + isp_pre_filt_ir_des_pd1 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ir_des_pd1) + i * ISP_REG_GAP); + if (i != 3) { + isp_pre_filt_ir_des_pd1 = des->ir_pd[i *4] | des->ir_pd[i *4 + 1] << 8 | des->ir_pd[i * 4 + 2] << 16 |\ + des->ir_pd[i*4 + 3] << 24; + } else { + isp_pre_filt_ir_des_pd1 = des->ir_pd[i *4] | des->ir_pd[i *4 + 1] << 8 | des->ir_pd[i*4 + 2] << 16; + } + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_des_pd1) + i * ISP_REG_GAP, isp_pre_filt_ir_des_pd1); + } + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_des_px1), (des->ir_px1 & 0xffff)); + for (i = 0; i < 8; i++) + { + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_des_py1) + i * ISP_REG_GAP, des->ir_py[i]); + } + + for (i = 0 ; i < 4; i++) { + isp_pre_filt_l_des_pd1 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_l_des_pd1) + i * ISP_REG_GAP); + if (i != 3) { + isp_pre_filt_l_des_pd1 = des->l_pd[i *4] | des->l_pd[i*4 + 1] << 8 | des->l_pd[i*4 + 2] << 16 |\ + des->l_pd[i*4 + 3] << 24; + } else { + isp_pre_filt_l_des_pd1 = des->l_pd[i *4] | des->l_pd[i*4 + 1] << 8 | des->l_pd[i*4+2] << 16; + } + isp_write_reg(dev, REG_ADDR(isp_pre_filt_l_des_pd1) + i * ISP_REG_GAP, isp_pre_filt_l_des_pd1); + } + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_l_des_px1), (des->l_px1 & 0xffff)); + for ( i = 0; i < 8; i++) + { + isp_write_reg(dev, REG_ADDR(isp_pre_filt_l_des_py1) + i * 4, des->l_py[i]); + } + return 0; +#endif +} + +int isp_rgbir_s_sharpen(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR_RY + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_sharpen_context *sharpen = &dev->rgbir.sharpen; + u8 sharpl = sharpen->sharpen_lvl; + u32 isp_pre_filt_lum_weight; // isp_pre_filt_thresh_sh0, isp_pre_filt_thresh_sh1; + // u32 isp_pre_filt_thresh_bl0, isp_pre_filt_thresh_bl1; + // u32 isp_pre_filt_fac_sh0, isp_pre_filt_fac_sh1, isp_pre_filt_fac_mid; + // u32 isp_pre_filt_fac_bl0, isp_pre_filt_fac_bl1; + const unsigned int sharplevel[5][11] = { + { 0x4, 0x08, 0x0C, 0x10, 0x16, 0x1B, 0x20, 0x26, 0x2C, 0x30, 0x3F }, + { 0x4, 0x07, 0x0A, 0x0C, 0x10, 0x14, 0x1A, 0x1E, 0x24, 0x2A, 0x30 }, + { 0x4, 0x06, 0x08, 0x0A, 0x0C, 0x10, 0x13, 0x17, 0x1D, 0x22, 0x28 }, + { 0x2, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x10, 0x15, 0x1A, 0x24 }, + { 0x0, 0x00, 0x00, 0x02, 0x04, 0x04, 0x06, 0x08, 0x0D, 0x14, 0x20 } }; + + isp_info("enter %s\n", __func__); + + + //filter factor sharp + isp_pre_filt_lum_weight = isp_read_reg(dev, REG_ADDR(isp_pre_filt_lum_weight)); + + REG_SET_SLICE(isp_pre_filt_lum_weight, LUM_WEIGHT_GAIN, sharpen->lum_weight_gain); + REG_SET_SLICE(isp_pre_filt_lum_weight, LUM_WEIGHT_KINK, sharpen->lum_weight_kink); + REG_SET_SLICE(isp_pre_filt_lum_weight, LUM_WEIGHT_MIN, sharpen->lum_weight_min); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_lum_weight), isp_pre_filt_lum_weight); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_mid), sharpen->middle); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_sh0), sharpen->thresh_sh0); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_sh1), sharpen->thresh_sh1); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_bl0), sharpen->thresh_bl0); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_bl1), sharpen->thresh_bl1); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_sh1), (unsigned int)(sharplevel[0][sharpl])); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_sh0), (unsigned int)(sharplevel[1][sharpl])); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_mid), (unsigned int)(sharplevel[2][sharpl])); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_bl0), (unsigned int)(sharplevel[3][sharpl])); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_bl1), (unsigned int)(sharplevel[4][sharpl])); + return 0; +#endif +} + +int isp_rgbir_s_ir_dnr(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR_RY + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_ir_dnr_context* ir_dnr = &dev->rgbir.ir_dnr; + //u16 imgwidth, imgheight; + u32 ir_denoise_reg_03; + u32 ir_denoise_reg_45; + + ir_denoise_reg_03 = (ir_dnr->winweight[0] | (ir_dnr->winweight[1] << 8) | (ir_dnr->winweight[2] << 16) | (ir_dnr->winweight[3] << 24)); + ir_denoise_reg_45 = (ir_dnr->winweight[4] | (ir_dnr->winweight[5] << 8)); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_denoise_sw_03), (unsigned int)(ir_denoise_reg_03)); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_denoise_sw_45), ((unsigned int)(ir_denoise_reg_45) & 0xffff)); + + //imgwidth = isp_read_reg(dev, REG_ADDR(isp_out_h_size)); + //imgheight = isp_read_reg(dev, REG_ADDR(isp_out_v_size)); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_h_size), ir_dnr->width& 0x7fff); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_v_size), ir_dnr->height & 0x3fff); + return 0; +#endif +} + +int isp_rgbir_hw_init(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR_RY + isp_err("unsupported function %s", __func__); + return -1; +#else + u32 isp_pre_filt_ctrl; + struct isp_rgbir_context *rgbir = &dev->rgbir; + isp_info("enter %s\n", __func__); + + isp_rgbir_s_cc_matrix(dev); + isp_rgbir_s_bls(dev); + isp_rgbir_s_dpcc(dev); + isp_rgbir_s_des(dev); + isp_rgbir_s_gain(dev); + isp_rgbir_s_ir_dnr(dev); + isp_rgbir_s_sharpen(dev); + + isp_pre_filt_ctrl = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl));//pre filt ctrl + REG_SET_SLICE(isp_pre_filt_ctrl , ISP_PRE_FILT_ENABLE, rgbir->prefilt_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_MODE, rgbir->green_filt_mode); + REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_ENABLE, rgbir->green_filt_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , RGBIR_BAYER_PATTERN, rgbir->rgbirPattern ); + REG_SET_SLICE(isp_pre_filt_ctrl , OUT_RGB_BAYER_PATTERN, rgbir->out_rgb_pattern); + REG_SET_SLICE(isp_pre_filt_ctrl , STAGE1_SELECT, rgbir->green_filt_stage1_select); + REG_SET_SLICE(isp_pre_filt_ctrl , DEMOSAIC_THRESHOLD, rgbir->demosaic_threshold); + REG_SET_SLICE(isp_pre_filt_ctrl , PART_ONE_ENABLE, rgbir->part1_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , PART_TWO_ENABLE,rgbir->part2_enable); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ctrl), (unsigned int)(isp_pre_filt_ctrl));//pre filt ctrl + return 0; +#endif +} + +int isp_enable_rgbir(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR_RY + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_context *rgbir = &dev->rgbir; + u32 isp_pre_filt_ctrl; + isp_info("enter %s\n", __func__); + + isp_pre_filt_ctrl = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl));//pre filt ctrl + REG_SET_SLICE(isp_pre_filt_ctrl , ISP_PRE_FILT_ENABLE, rgbir->prefilt_enable); + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ctrl), isp_pre_filt_ctrl);//pre filt ctrl + return 0; +#endif +} + +int isp_rgbir_out_ir_raw(struct isp_ic_dev *dev) +{ +#ifndef ISP_RGBIR_RY + isp_err("unsupported function %s", __func__); + return -1; +#else + struct isp_rgbir_context *rgbir = &dev->rgbir; + u32 isp_ctrl; + isp_info("enter %s\n", __func__); + + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));//isp ctrl + REG_SET_SLICE(isp_ctrl , ISP_IR_RAW_OUT, rgbir->enable_ir_raw_out); + REG_SET_SLICE(isp_ctrl , MRV_ISP_ISP_MODE, MRV_ISP_ISP_MODE_RGB); //there need to config rgb mode. + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);//isp_ctrl + return 0; +#endif +} + +int isp_s_rgbir(struct isp_ic_dev *dev) +{ + +#ifndef ISP_WDR_V4 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_rgbir_context *rgbir = &dev->rgbir; + u32 isp_pre_filt_ctrl; + isp_info("enter %s\n", __func__); + isp_rgbir_s_cc_matrix(dev); + isp_rgbir_s_bls(dev); + isp_rgbir_s_dpcc(dev); + isp_rgbir_s_des(dev); + isp_rgbir_s_gain(dev); + isp_rgbir_s_ir_dnr(dev); + isp_rgbir_s_sharpen(dev); + + isp_pre_filt_ctrl = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl));//pre filt ctrl + REG_SET_SLICE(isp_pre_filt_ctrl , ISP_PRE_FILT_ENABLE, rgbir->prefilt_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_MODE, rgbir->green_filt_mode); + REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_ENABLE, rgbir->green_filt_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , RGBIR_BAYER_PATTERN, rgbir->rgbirPattern ); + REG_SET_SLICE(isp_pre_filt_ctrl , OUT_RGB_BAYER_PATTERN, rgbir->out_rgb_pattern); + REG_SET_SLICE(isp_pre_filt_ctrl , STAGE1_SELECT, rgbir->green_filt_stage1_select); + REG_SET_SLICE(isp_pre_filt_ctrl , DEMOSAIC_THRESHOLD, rgbir->demosaic_threshold); + REG_SET_SLICE(isp_pre_filt_ctrl , PART_ONE_ENABLE, rgbir->part1_enable); + REG_SET_SLICE(isp_pre_filt_ctrl , PART_TWO_ENABLE,rgbir->part2_enable); + + isp_write_reg(dev, REG_ADDR(isp_pre_filt_ctrl), (unsigned int)(isp_pre_filt_ctrl));//pre filt ctrl + return 0; +#endif +} + + diff --git a/vvcam_ry/isp/isp_tdnr3.c b/vvcam_ry/isp/isp_tdnr3.c new file mode 100755 index 0000000..5f3bc3a --- /dev/null +++ b/vvcam_ry/isp/isp_tdnr3.c @@ -0,0 +1,558 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "isp_ioctl.h" +#include "mrv_all_bits.h" + +#include "isp_types.h" +#ifdef ISP_3DNR_V3 +extern MrvAllRegister_t *all_regs; + +int isp_tdnr_cfg_gamma(struct isp_ic_dev *dev) +{ + //write to regs + struct isp_tdnr_context *tdnr = &dev->tdnr; + u32 regVal; + u8 bit_width; + u8 i; + u16 val_a, val_b; + + //const u8 tdnrRegGap = 8; + bit_width = 12; + + pr_info("enter %s\n", __func__); + + for (i = 0; i < DENOISE3D_GAMMA_BIN - 3; i += 5) + { + val_a = tdnr->curve.preGamma_y[i + 2] >> 6; val_b = tdnr->curve.preGamma_y[i + 2] & 0x3f; + regVal = (val_a << 24) | ((tdnr->curve.preGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.preGamma_y[i] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_0) + (i / 5) *8 , regVal); + + regVal = (val_b << 24) | ((tdnr->curve.preGamma_y[i + 4] & 0xfff) << bit_width) | (tdnr->curve.preGamma_y[i + 3] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_1) + (i / 5 ) *8, regVal); + } + + val_a = tdnr->curve.preGamma_y[i + 2] >> 6; val_b = tdnr->curve.preGamma_y[i + 2] & 0x3f; + regVal = (val_a << 24) | ((tdnr->curve.preGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.preGamma_y[i] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_12), regVal); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_13), val_b); + + + i = 0; + for (i = 0; i < DENOISE3D_GAMMA_BIN - 3; i += 5) + { + val_a = tdnr->curve.invGamma_y[i + 2] >> 6; val_b = tdnr->curve.invGamma_y[i + 2] & 0x3f; + regVal = (val_a << 24) | ((tdnr->curve.invGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.invGamma_y[i] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_0) + (i / 5) *8 , regVal); + + regVal = (val_b << 24) | ((tdnr->curve.invGamma_y[i + 4] & 0xfff) << bit_width) | (tdnr->curve.invGamma_y[i + 3] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_1) + (i / 5) *8 , regVal); + } + + val_a = tdnr->curve.invGamma_y[i + 2] >> 6; val_b = tdnr->curve.invGamma_y[i + 2] & 0x3f; + regVal = (val_a << 24) | ((tdnr->curve.invGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.invGamma_y[i] & 0xfff); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_12), regVal); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_13), val_b); + return 0; +} + +int isp_s_tdnr(struct isp_ic_dev *dev) +{ + u32 isp_denoise3d2_ctrl; + struct isp_tdnr_context *tdnr = &dev->tdnr; + u32 regVal = 0; + /* spacial */ + u32 strength = tdnr->strength; + + pr_info("enter %s\n", __func__); + strength = MIN(MAX(strength, 0), 128); + + isp_denoise3d2_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); +#if 0 + if (!tdnr->enable) { + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), isp_denoise3d2_ctrl); + return 0; + } +#endif + +#if 1 + if (dev->tdnr.enable_tnr) { + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), strength); + } else { + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), 0); + if (dev->tdnr.frames == 2) + return 0 ; + } +#endif + //isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), strength); + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_level); + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->noise_mean); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_noise), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_threshold); + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->motion_mean); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_RANGE_H, tdnr->range_h); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_RANGE_V, tdnr->range_v); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_DILATE_RANGE_H, tdnr->dilate_range_h); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_DILATE_RANGE_V, tdnr->dilate_range_v); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_range), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_INV, tdnr->motion_inv_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion_inv), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_THR_UPDATE, tdnr->update_factor); + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_THR_UPDATE, tdnr->motion_update_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_update), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_PRE_WEIGHT, tdnr->pre_motion_weight); + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_SLOPE, tdnr->motion_slope); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_tnr), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_CONV_SHIFT, tdnr->motion_converage_shift); + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_CONV_MAX, tdnr->motion_converage_max); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_VAL_SHIFT_BIT, tdnr->tnr_val_shift_bit); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT, tdnr->tnr_diff_shift_bit); + REG_SET_SLICE(regVal, DENOISE3D_V20_SAD_WEIGHT, tdnr->sad_weight); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_shift), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_VAL_SHIFT, tdnr->luma_pixel_val_shift); + REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_SLOP, tdnr->luma_pixel_slope); + REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT, tdnr->luma_pixel_slope_shift); + REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_SLOP_MIN, tdnr->luma_pixel_slope_min); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_luma), regVal); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_dummy_hblank), 0x63); + + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_INVGAMMA_EN, tdnr->enable_inv_gamma); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_PREGAMMA_EN, tdnr->enable_pre_gamma); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_ERODE_EN, tdnr->enable_motion_erosion); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_MOTION_CONV_EN, tdnr->enable_motion_converage); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_INV_DGAIN_EN, 0); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_INV_AWB_GAIN_EN, 1); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_COMP_LUMA_EN, 0); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_MOTION_DILATE_ENABLE, tdnr->enable_motion_dilation); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_NLM_ENABLE, dev->tdnr.enable_2dnr); + //REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_NLM_ENABLE, 1); + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_TNR_ENABLE, dev->tdnr.enable_tnr); + + if (!dev->tdnr.enable_tnr) { + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_REF_RESET, 1); + } + REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_ENABLE, 1); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), isp_denoise3d2_ctrl); + + return 0; +} + +int isp_tdnr_set_strength(struct isp_ic_dev *dev) +{ + u32 isp_denoise3d2_strength; + struct isp_tdnr_context *tdnr = &dev->tdnr; + pr_info("enter %s\n", __func__); + + isp_denoise3d2_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_strength)); + REG_SET_SLICE(isp_denoise3d2_strength, DENOISE3D_V20_TNR_STRENGTH, tdnr->strength); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), isp_denoise3d2_strength); + + return 0; +} + +int isp_tdnr_set_motion(struct isp_ic_dev *dev) +{ + struct isp_tdnr_context *tdnr = &dev->tdnr; + u32 isp_denoise3d2_motion_inv; + pr_info("enter %s\n", __func__); + + isp_denoise3d2_motion_inv = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_motion_inv)); + REG_SET_SLICE(isp_denoise3d2_motion_inv, DENOISE3D_V20_MOTION_INV, tdnr->motion_inv_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion_inv), isp_denoise3d2_motion_inv); + + return 0; +} + +int isp_tdnr_enable(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + u32 strength = dev->tdnr.strength; + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(regVal, DENOISE3D_V20_ENABLE, 1); + // REG_SET_SLICE(regVal, DENOISE3D_V20_REF_RESET, 1); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal); + + strength = MIN(MAX(strength, 0), 128); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), strength); //clear strength + dev->tdnr.enable = true; + + return 0; +} + +int isp_tdnr_disable(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + // REG_SET_SLICE(regVal, DENOISE3D_V20_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), 0); //clear strength + dev->tdnr.enable = false; + + return 0; +} + +int isp_tdnr_enable_tdnr(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal); + + dev->tdnr.enable_tnr= true; + + return 0; +} + +int isp_tdnr_disable_tdnr(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + + pr_info("enter %s\n", __func__); + regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal); + dev->tdnr.enable = false; + + return 0; +} + +int isp_tdnr_enable_2dnr(struct isp_ic_dev *dev) +{ + //u32 regVal = 0; + + pr_info("enter %s\n", __func__); + /*regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(regVal, DENOISE3D_V20_NLM_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal);*/ + + dev->tdnr.enable_tnr= true; + + return 0; +} + +int isp_tdnr_disable_2dnr(struct isp_ic_dev *dev) +{ + //u32 regVal = 0; + + pr_info("enter %s\n", __func__); + /*regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl)); + REG_SET_SLICE(regVal, DENOISE3D_V20_NLM_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal);*/ + dev->tdnr.enable = false; + + return 0; +} + + + +int isp_tdnr_g_stats(struct isp_ic_dev *dev, struct isp_tdnr_stats *stats) +{ + pr_info("enter %s\n", __func__); + if (!dev || !stats) { + return -EINVAL; + } + + stats->bg_sum = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_bg_val_sum)); + stats->motion_sum = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_mo_val_sum)); + stats->bg_pixel_cnt = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_bg_cnt)); + stats->motion_pixel_cnt = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_mo_cnt)); + stats->frame_avg = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_frame_avg)); + return 0; +} + +int isp_tdnr_u_noise(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + struct isp_tdnr_context *tdnr = &dev->tdnr; + pr_info("enter %s\n", __func__); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_level); + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->noise_mean); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_noise), regVal); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_threshold); + REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->motion_mean); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion), regVal); + + return 0; + +} + +int isp_tdnr_u_thr(struct isp_ic_dev *dev) +{ + u32 regVal = 0; + struct isp_tdnr_context *tdnr = &dev->tdnr; + pr_info("enter %s\n", __func__); + + regVal = 0; + REG_SET_SLICE(regVal, DENOISE3D_V20_THR_UPDATE, tdnr->update_factor); + REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_THR_UPDATE, tdnr->motion_update_factor); + isp_write_reg(dev, REG_ADDR(isp_denoise3d2_update), regVal); + + return 0; + +} + +int isp_tdnr_s_buf(struct isp_ic_dev *dev) +{ + struct isp_tdnr_buffer* buf = &dev->tdnr.buf; + u32 in_width, in_height; + u32 size, lval; + u32 miv2_sp2_bus_id ; + u32 miv2_sp2_fmt; + u32 miv2_imsc2; + + u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc)); + u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl)); + u32 isp_mi_sp2_raw2_ctrl = isp_read_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl)); + pr_info("enter %s\n", __func__); + + /* + + ENABLE MIV2 SP2 RAW1 RAW2 WRITE/READ + + */ + + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW_PATH_ENABLE, 1); + miv2_ctrl |= 0x00100000; // sp2_raw2_path_enable + + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + + in_width = isp_read_reg(dev, REG_ADDR(isp_out_h_size)); + in_height = isp_read_reg(dev, REG_ADDR(isp_out_v_size)); + + lval = (in_width * 12 + 127)/ 128; + lval <<= 4; + size = in_height * lval; //raw12 unaligned + //write reference frame config + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_base_ad_init), buf->pa_refer); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_size_init), size); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_offs_cnt_init), 0); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_height), in_height); + isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_size), size); + + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), buf->pa_refer); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_llength), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_lval), lval); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_size), size); + + in_width /= 2; + in_height /= 2; + lval = (in_width); // RAW8 output + size = in_height * lval; + pr_info("%s 0x%08x\n", __func__, REG_ADDR(isp_mi_sp2_raw2_base_ad_init)); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_base_ad_init), buf->pa_motion); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_size_init), size); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_offs_cnt_init), 0); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_llength), lval); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_pic_height), in_height); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_pic_size), size); + + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_start_ad), buf->pa_motion); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_width), in_width); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_llength), lval); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_lval), lval); // align to 128 + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_size), size); + +#if 0 + isp_write_reg(dev, 0x5620, buf->pa_motion); + isp_write_reg(dev, 0x5624, size); + isp_write_reg(dev, 0x5628, 0); + isp_write_reg(dev, 0x562c, lval); + isp_write_reg(dev, 0x5630, in_width); + isp_write_reg(dev, 0x5634, in_height); + isp_write_reg(dev, 0x5638, size); + + isp_write_reg(dev, 0x5660, buf->pa_motion); + isp_write_reg(dev, 0x5664, in_width); + isp_write_reg(dev, 0x5668, lval); + isp_write_reg(dev, 0x5680, lval); // align to 128 + isp_write_reg(dev, 0x566c, size); +#endif + miv2_sp2_bus_id = isp_read_reg(dev, REG_ADDR(miv2_sp2_bus_id)); + + REG_SET_SLICE(miv2_sp2_bus_id, SP2_WR_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_ID_EN, 1); + REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_BURST_LEN, 2); //sp2 rd burst lenghth 16 + REG_SET_SLICE(miv2_sp2_bus_id, SP2_BUS_SW_EN, 1); + + isp_write_reg(dev, REG_ADDR(miv2_sp2_bus_id), miv2_sp2_bus_id); + + miv2_sp2_fmt = isp_read_reg(dev, REG_ADDR(miv2_sp2_fmt)); + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_ALIGNED, 0); //unaligned + + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_BIT, 2); //raw12 + REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_ALIGNED, 0); //unaligned + + isp_write_reg(dev, REG_ADDR(miv2_sp2_fmt), miv2_sp2_fmt); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_fmt), 0); + + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1); + //REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_AUTO_UPDATE, 1); + + miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK); + //miv2_sp2_ctrl |= 0x2fa; + isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl); + + isp_mi_sp2_raw2_ctrl |= 0x23a; + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl), isp_mi_sp2_raw2_ctrl); + miv2_imsc |= SP2_RAW_FRAME_END_MASK|SP2_DMA_RAW_READY_MASK; + + isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc); + miv2_imsc2 = isp_read_reg(dev, REG_ADDR(miv2_imsc2)); + + miv2_imsc2 |= SP2_RAW2_FRAME_END_MASK | SP2_RAW2_DMA_READY_MASK; //0x41000 + isp_write_reg(dev, REG_ADDR(miv2_imsc2), miv2_imsc2); + + isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), 0x480); + +// isp_write_reg(dev, 0x00000730, 0x00001edf); + //isp_write_reg(dev, 0x000014ec, 0x04b30000); + //isp_write_reg(dev, 0x000014f0, 0x0807e521); + return 0; +} + +int isp_r_tdnr_refer(struct isp_ic_dev *dev) +{ + struct isp_tdnr_buffer* buf = &dev->tdnr.buf; + u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc)); + u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl)); + u32 isp_mi_sp2_raw2_ctrl = isp_read_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl)); + pr_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), buf->pa_refer); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_start_ad), buf->pa_motion); + + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1); + REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1); + + miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK); + miv2_sp2_ctrl |= 0xf0; + isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl); + + isp_mi_sp2_raw2_ctrl |= 0x238; + + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl), isp_mi_sp2_raw2_ctrl); + + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_START_CON, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_START, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START_CON, 1); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + + miv2_imsc |= SP2_DMA_RAW_READY_MASK; + isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc); + return 0; +} + +int isp_r_tdnr_motion(struct isp_ic_dev *dev) +{ + struct isp_tdnr_buffer* buf = &dev->tdnr.buf; + u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl)); + u32 isp_mi_sp2_raw2_ctrl = isp_read_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl)); + pr_info("enter %s\n", __func__); + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_start_ad), buf->pa_motion); + + REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START, 1); + REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START_CON, 1); + isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl); + + isp_mi_sp2_raw2_ctrl |= 0x238; + isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl), isp_mi_sp2_raw2_ctrl); + + return 0; +} +#endif diff --git a/vvcam_ry/isp/isp_types.h b/vvcam_ry/isp/isp_types.h new file mode 100755 index 0000000..b9958e4 --- /dev/null +++ b/vvcam_ry/isp/isp_types.h @@ -0,0 +1,176 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_TYPES_H_ +#define _ISP_TYPES_H_ + +enum { + IC_MI_PATH_INVALID = -1, /**< lower border (only for an internal evaluation) */ + IC_MI_PATH_MAIN = 0, /**< main path index */ + IC_MI_PATH_SELF = 1, /**< self path index */ + IC_MI_PATH_SELF2 = 2, /**< self path index */ + IC_MI_PATH_MAX /**< upper border (only for an internal evaluation) */ +}; + +enum { + IC_MI_DATAMODE_INVALID = 0, /**< lower border (only for an internal evaluation) */ + IC_MI_DATAMODE_DISABLED = 1, /**< disables the path */ + IC_MI_DATAMODE_JPEG = 2, /**< data output format is JPEG (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_YUV444 = 3, /**< data output format is YUV444 */ + IC_MI_DATAMODE_YUV422 = 4, /**< data output format is YUV422 */ + IC_MI_DATAMODE_YUV420 = 5, /**< data output format is YUV420 */ + IC_MI_DATAMODE_YUV400 = 6, /**< data output format is YUV400 */ + IC_MI_DATAMODE_RGB888 = 7, /**< data output format is RGB888 (only valid for selpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RGB666 = 8, /**< data output format is RGB666 (only valid for selpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RGB565 = 9, /**< data output format is RGB565 (only valid for selpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RAW8 = 10, /**< data output format is RAW8 (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RAW12 = 11, /**< data output format is RAW12 (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_DPCC = 12, /**< path dumps out the current measured defect pixel table */ + IC_MI_DATAMODE_RAW10 = 13, /**< data output format is RAW10 (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RAW14 = 14, /**< data output format is RAW14 (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_RAW16 = 15, /**< data output format is RAW16 (only valid for mainpath @ref CamerIcMiPath_e) */ + IC_MI_DATAMODE_MAX /**< upper border (only for an internal evaluation) */ +}; + +enum { + IC_MI_DATASTORAGE_INVALID = 0, /**< lower border (only for an internal evaluation) */ + IC_MI_DATASTORAGE_PLANAR = 1, /**< YUV values are packed together as: YYYY......, UVUVUVUV...... */ + IC_MI_DATASTORAGE_SEMIPLANAR = 2, /**< YUV values are packed together as: YUV, YUV, YUV, ...... */ + IC_MI_DATASTORAGE_INTERLEAVED = 3, /**< Y values for all pixels are put together, as well as U and V, + like: YYYYYY......, UUUUUUU......., VVVVVV...... */ + IC_MI_DATASTORAGE_MAX /**< upper border (only for an internal evaluation) */ +}; + +enum { + ISP_PICBUF_TYPE_INVALID = 0x00, + ISP_PICBUF_TYPE_DATA = 0x08, /* just some sequential data */ + ISP_PICBUF_TYPE_RAW8 = 0x10, + ISP_PICBUF_TYPE_RAW16 = 0x11, /* includes: 9..16bits, MSBit aligned, LSByte first! */ + ISP_PICBUF_TYPE_RAW10 = 0x12, /* includes: 10bits, MSBit aligned, LSByte first! */ + ISP_PICBUF_TYPE_RAW12 = 0x13, + ISP_PICBUF_TYPE_RAW14 = 0x14, + ISP_PICBUF_TYPE_JPEG = 0x20, + ISP_PICBUF_TYPE_YCbCr444 = 0x30, + ISP_PICBUF_TYPE_YCbCr422 = 0x31, + ISP_PICBUF_TYPE_YCbCr420 = 0x32, + ISP_PICBUF_TYPE_YCbCr400 = 0x33, + ISP_PICBUF_TYPE_YCbCr32 = 0x3f, + ISP_PICBUF_TYPE_RGB888 = 0x40, + ISP_PICBUF_TYPE_RGB666 = 0x41, /* R, G & B are LSBit aligned! */ + ISP_PICBUF_TYPE_RGB565 = 0x42, /* TODO: don't know the memory layout right now, investigate! */ + ISP_PICBUF_TYPE_RGB32 = 0x4f, + _ISP_PICBUF_TYPE_DUMMY_ +}; + +enum { + ISP_PICBUF_LAYOUT_INVALID = 0, + ISP_PICBUF_LAYOUT_COMBINED = 0x10, /* ISP_PICBUF_TYPE_DATA: Data: D0 D1 D2... */ + /* ISP_PICBUF_TYPE_RAW8: Data: D0 D1 D2... */ + /* ISP_PICBUF_TYPE_RAW16/10: Data: D0L D0H D1L D1H... */ + /* ISP_PICBUF_TYPE_JPEG: Data: J0 J1 J2... */ + /* ISP_PICBUF_TYPE_YCbCr444: Data: Y0 Cb0 Cr0 Y1 Cb1Cr1... */ + /* ISP_PICBUF_TYPE_YCbCr422: Data: Y0 Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1... */ + /* ISP_PICBUF_TYPE_YCbCr32: Data: Cr0 Cb0 Y0 A0 Cr1 Cb1 Y1 A1... */ + /* ISP_PICBUF_TYPE_RGB888: Data: R0 G0 B0 R1 B2 G1... */ + /* ISP_PICBUF_TYPE_RGB666: Data: {00,R0[5:0]} {00,G0[5:0]} {00,B0[5:0]} {00,R1[5:0]} {00,G2[5:0]} {00,B3[5:0]}... */ + /* ISP_PICBUF_TYPE_RGB565: Data: {R0[4:0],G0[5:3]} {G0[2:0],B0[4:0]} {R1[4:0],G1[5:3]} {G1[2:0],B1[4:0]}... (is this correct?) */ + /* ISP_PICBUF_TYPE_RGB32: Data: B0 G0 R0 A0 B1 G1 R1 A1... */ + ISP_PICBUF_LAYOUT_BAYER_RGRGGBGB = 0x11, /* 1st line: RGRG... , 2nd line GBGB... , etc. */ + ISP_PICBUF_LAYOUT_BAYER_GRGRBGBG = 0x12, /* 1st line: GRGR... , 2nd line BGBG... , etc. */ + ISP_PICBUF_LAYOUT_BAYER_GBGBRGRG = 0x13, /* 1st line: GBGB... , 2nd line RGRG... , etc. */ + ISP_PICBUF_LAYOUT_BAYER_BGBGGRGR = 0x14, /* 1st line: BGBG... , 2nd line GRGR... , etc. */ + ISP_PICBUF_LAYOUT_SEMIPLANAR = 0x20, /* ISP_PICBUF_TYPE_YCbCr422: Luma: Y0 Y1 Y2 Y3... ; Chroma: Cb0 Cr0 Cb1 Cr1... */ + /* ISP_PICBUF_TYPE_YCbCr420: Luma: Y0 Y1 Y2 Y3... ; Chroma: Cb0 Cr0 Cb1 Cr1... */ + /* ISP_PICBUF_TYPE_YCbCr400: Luma: Y0 Y1 Y2 Y3... ; Chroma: not used */ + ISP_PICBUF_LAYOUT_PLANAR = 0x30, /* ISP_PICBUF_TYPE_YCbCr444: Y: Y0 Y1 Y2 Y3...; Cb: Cb0 Cb1 Cb2 Cb3...; Cr: Cr0 Cr1 Cr2 Cr3... */ + /* ISP_PICBUF_TYPE_YCbCr422: Y: Y0 Y1 Y2 Y3...; Cb: Cb0 Cb1 Cb2 Cb3...; Cr: Cr0 Cr1 Cr2 Cr3... */ + /* ISP_PICBUF_TYPE_YCbCr420: Y: Y0 Y1 Y2 Y3...; Cb: Cb0 Cb1 Cb2 Cb3...; Cr: Cr0 Cr1 Cr2 Cr3... */ + /* ISP_PICBUF_TYPE_YCbCr400: Y: Y0 Y1 Y2 Y3...; Cb: not used; Cr: not used... */ + /* ISP_PICBUF_TYPE_RGB888: R: R0 R1 R2 R3...; G: G0 G1 G2 G3...; B: B0 B1 B2 B3... */ + /* ISP_PICBUF_TYPE_RGB666: R: {00,R0[5:0]}...; G: {00,G0[5:0]}...; B: {00,B0[5:0]}... */ + _ISP_PICBUF_LAYOUT_DUMMY_ +}; + +enum { + IC_DPF_RB_FILTERSIZE_INVALID = 0, /**< lower border (only for an internal evaluation) */ + IC_DPF_RB_FILTERSIZE_9x9 = 1, /**< red and blue filter kernel size 9x9 (means 5x5 active pixel) */ + IC_DPF_RB_FILTERSIZE_13x9 = 2, /**< red and blue filter kernel size 13x9 (means 7x5 active pixel) */ + IC_DPF_RB_FILTERSIZE_MAX /**< upper border (only for an internal evaluation) */ +}; + +enum { + ISP_MI_DATA_ALIGN_MODE_INVALID = -1, + ISP_MI_DATA_UNALIGN_MODE = 0, /* pixel data not aligned. */ + ISP_MI_DATA_ALIGN_128BIT_MODE = 1, /* pixel data aligned with 128 bit. */ + ISP_MI_DATA_ALIGN_16BIT_MODE = 2, /* pixel data aligned with 16 bit. */ + ISP_MI_DATA_ALIGN_MODE_MAX +}; + +enum { + IC_DPF_GAIN_USAGE_INVALID = 0, /**< lower border (only for an internal evaluation) */ + IC_DPF_GAIN_USAGE_DISABLED = 1, /**< don't use any gains in preprocessing stage */ + IC_DPF_GAIN_USAGE_NF_GAINS = 2, /**< use only the noise function gains from registers DPF_NF_GAIN_R, ... */ + IC_DPF_GAIN_USAGE_LSC_GAINS = 3, /**< use only the gains from LSC module */ + IC_DPF_GAIN_USAGE_NF_LSC_GAINS = 4, /**< use the moise function gains and the gains from LSC module */ + IC_DPF_GAIN_USAGE_AWB_GAINS = 5, /**< use only the gains from AWB module */ + IC_DPF_GAIN_USAGE_AWB_LSC_GAINS = 6, /**< use the gains from AWB and LSC module */ + IC_DPF_GAIN_USAGE_MAX /**< upper border (only for an internal evaluation) */ +}; + +enum { + IC_NLL_SCALE_INVALID = 0, /**< lower border (only for an internal evaluation) */ + IC_NLL_SCALE_LINEAR = 1, /**< use a linear scaling */ + IC_NLL_SCALE_LOGARITHMIC = 2, /**< use a logarithmic scaling */ + IC_NLL_SCALE_MAX /**< upper border (only for an internal evaluation) */ +}; + +#endif /* _ISP_TYPES_H_ */ diff --git a/vvcam_ry/isp/isp_version.h b/vvcam_ry/isp/isp_version.h new file mode 100755 index 0000000..e82d5d4 --- /dev/null +++ b/vvcam_ry/isp/isp_version.h @@ -0,0 +1,189 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_VERSION_H_ +#define _ISP_VERSION_H_ + +#define ISP_EE_SUPPORT 1 +#define ISP_2DNR_SUPPORT (1 << 1) +#define ISP_3DNR_SUPPORT (1 << 2) +#define ISP_WDR3_SUPPORT (1 << 3) +#define ISP_MIV2_SUPPORT (1 << 4) +#define ISP_AEV2_SUPPORT (1 << 5) +#define ISP_COMPAND_SUPPORT (1 << 6) +#define ISP_HDR_STITCH_SUPPORT (1 << 7) + + +/*****************************************************************************/ +/** + * @brief HDR module version type + */ +/*****************************************************************************/ +#define VSI_ISP_HDR_NOTSUPPORT 0 //!< Not support HDR +#define VSI_ISP_HDR_V10 1 //!< Version V10 +#define VSI_ISP_HDR_V11 2 //!< Version V11 +#define VSI_ISP_HDR_V12 3 //!< Version V12 +#define VSI_ISP_HDR_V13 4 //!< Version V13 + + +///////////////////////////////////////// +//add Version defines +///////////////////////////////////////// + +/* add Version defines(Mrv_all_regs.h) +ISP8000L_V2002、ISP8000_V2003、 +ISP8000NANO_V1801、ISP8000NANO_V1802、 +ISP8000_V1901、ISP8000L_V1901、ISP8000L_V1902、 +ISP8000L_V1903、ISP8000L_V1905、ISP8000L_V2001、ISP8000L_V2006 +*/ +#define MRV_IMAGE_EFFECTS_VERSION 1 +#define MRV_SUPER_IMPOSE_VERSION 1 +#define MRV_BLACK_LEVEL_VERSION 1 +#define MRV_AUTO_EXPOSURE_VERSION 1 +#define MRV_AEV2_VERSION 1 +#define MRV_OUTPUT_FORMATTER_VERSION 1 +#define MRV_GAMMA_OUT_VERSION 1 +#define MRV_FLASH_LIGHT_VERSION 1 +#define MRV_SHUTTER_VERSION 1 +#define MRV_MAINPATH_SCALER_VERSION 1 +#define MRV_SELFPATH_SCALER_VERSION 1 +#define MRV_MI_VERSION 1 +//#define MRV_JPE_VERSION 1 +#define MRV_SMIA_VERSION 1 +#define MRV_MIPI_VERSION 1 +#define MRV_AUTOFOCUS_VERSION 1 +#define MRV_LSC_VERSION 1 +#define MRV_IS_VERSION 1 +#define MRV_HISTOGRAM_VERSION 1 +#define MRV_FILTER_VERSION 1 +#define MRV_CAC_VERSION 1 +#define MRV_DPF_VERSION 1 +#define MRV_DPCC_VERSION 1 +#define MRV_WDR_VERSION 1 +#define MRV_CSM_VERSION 1 +#define MRV_AWB_VERSION 1 +#define MRV_ELAWB_VERSION 1 +#define MRV_GAMMA_IN_VERSION 1 +#define MRV_SHUTTER_CTRL_VERSION 1 +#define MRV_CT_VERSION 1 +#define MRV_COLOR_PROCESSING_VERSION 1 +#define MRV_VSM_VERSION 1 +#define MRV_CNR_VERSION 1 + +#define MRV_WDR2_VERSION 1 +#define MRV_WDR3_VERSION 1 +#define MRV_CMPD_VERSION 1 /* compand */ +#define MRV_TPG_VERSION 1 +//#define MRV_STITCHING_VERSION 1 +#define MRV_EE_VERSION 1 +#define MRV_2DNR_VERSION 1 + +#ifdef ISP_3DNR +#define MRV_3DNR_VERSION 1 +#endif + +#ifdef ISP_GCMONO +#define MRV_GCMONO_VERSION 1 +#endif +#ifdef ISP_RGBGC_RY +#define MRV_RGBGAMMA_VERSION 1 +#endif +#ifdef ISP_DEC +#define MRV_DEC_VERSION 1 +#endif +#ifdef ISP_DEMOSAIC2_RY +#define MRV_DEMOSAIC_VERSION 1 +#endif +#ifdef ISP_GREENEQUILIBRATE +#define MRV_GREENEQUILIBRATION_VERSION 1 +#endif +#ifdef ISP_CA_RY +#define MRV_COLOR_ADJUST_VERSION 1 +#endif + +#ifdef ISP_SP2 +#define MRV_SP2_VERSION 1 +#endif +#ifdef ISP_HDR_STITCH_V2_RY +#undef MRV_STITCHING_VERSION +#define MRV_STITCHING_VERSION 2 //1--V11, 2--V12 + +#elif defined(ISP_HDR_STITCH_V3_RY) +#undef MRV_STITCHING_VERSION +#define MRV_STITCHING_VERSION 3 //1--V11, 2--V12 3--V13 +#elif defined(ISP_HDR_STITCH_RY) + +#undef MRV_STITCHING_VERSION +#define MRV_STITCHING_VERSION 1 //1--V11, 2--V12 3--V13 +#endif + +#ifdef ISP_3DNR_V2 +#define MRV_3DNR_VERSION 1 +#endif + +#ifdef ISP_WDR_V4 +#define MRV_WDR4_VERSION 1 +#endif + +#ifdef ISP_3DNR_V3 +#define MRV_TDNR3_VERSION 1 +#endif + +#ifdef ISP_RGBIR_RY +#define MRV_RGBIR_VERSION 1 +#endif + +#ifdef ISP_HIST64_RY + +#define MRV_HISTOGRAM64_VERSION 1 +#endif +#endif /* _ISP_VERSION_H_ */ diff --git a/vvcam_ry/isp/isp_wdr.c b/vvcam_ry/isp/isp_wdr.c new file mode 100755 index 0000000..6bfa562 --- /dev/null +++ b/vvcam_ry/isp/isp_wdr.c @@ -0,0 +1,136 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include "isp_wdr.h" +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" +#include "ic_dev.h" + +extern MrvAllRegister_t *all_regs; + + +int isp_s_wdr(struct isp_ic_dev *dev) +{ + isp_wdr_context_t* wdr = &dev->wdr; + + pr_info(" enter %s\n", __func__); + + /*update wdr configuration after frame end when isp enable*/ + if (!is_isp_enable(dev) || wdr->changed) { + uint32_t isp_wdr_offset, isp_wdr_ctrl; + + isp_wdr_offset = isp_read_reg(dev, REG_ADDR(isp_wdr_offset)); + REG_SET_SLICE( isp_wdr_offset, MRV_WDR_LUM_OFFSET, wdr->LumOffset ); + REG_SET_SLICE( isp_wdr_offset, MRV_WDR_RGB_OFFSET, wdr->RgbOffset ); + isp_write_reg(dev, REG_ADDR(isp_wdr_offset), isp_wdr_offset); + + isp_wdr_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr_ctrl)); + REG_SET_SLICE(isp_wdr_ctrl, MRV_WDR_ENABLE, wdr->enabled); + isp_write_reg(dev, REG_ADDR(isp_wdr_ctrl), isp_wdr_ctrl); + wdr->changed = false; + } else { + wdr->changed = true; + } + pr_info(" %s wdr.changed %d \n", __func__, wdr->changed); + return 0; +} + +int isp_s_wdr_curve(struct isp_ic_dev *dev) +{ + + isp_wdr_context_t* wdr = &dev->wdr; + + int i, j; + uint32_t dYi = 0U; + for ( i=0; i<4; i++ ) + { + for ( j=8; j>0; j-- ) + { + dYi <<= 4; + dYi += wdr->dY[ (i*8 + j) ]; + } + + if (i == 0) + { + + isp_write_reg(dev, REG_ADDR(isp_wdr_tonecurve_1), dYi); + } + else if (i == 1) + { + isp_write_reg(dev, REG_ADDR(isp_wdr_tonecurve_2), dYi); + } + else if (i == 2) + { + isp_write_reg(dev, REG_ADDR(isp_wdr_tonecurve_3), dYi); + } + else /* if (i == 3) */ + { + isp_write_reg(dev, REG_ADDR(isp_wdr_tonecurve_4), dYi); + } + } + + for ( i=0; i<33; i++ ) + { + isp_write_reg(dev, REG_ADDR(wdr_tone_mapping_curve_y_block_arr[i]), wdr->Ym[i]); + } + + dYi = 0x00000000; + + isp_write_reg(dev, REG_ADDR(isp_wdr_offset), dYi); + isp_write_reg(dev, REG_ADDR(isp_wdr_deltamin), 0x00100000); + + return 0; + +} + + diff --git a/vvcam_ry/isp/isp_wdr.h b/vvcam_ry/isp/isp_wdr.h new file mode 100755 index 0000000..6f6f5e1 --- /dev/null +++ b/vvcam_ry/isp/isp_wdr.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_WDR_H +#define _ISP_WDR_H + +#include "isp_version.h" +#include "vvdefs.h" +#include "ic_dev.h" + + +int isp_s_wdr(struct isp_ic_dev *dev); +int isp_s_wdr_curve(struct isp_ic_dev *dev); + + +#endif + diff --git a/vvcam_ry/isp/isp_wdr3.c b/vvcam_ry/isp/isp_wdr3.c new file mode 100755 index 0000000..90bb772 --- /dev/null +++ b/vvcam_ry/isp/isp_wdr3.c @@ -0,0 +1,502 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +#define WDR3_WW (32) +#define WDR3_HH (32) +#define WDR3_MAX_VALUE (1023) +#define WDR3_GAIN_SHIFT (2) +#define WDR3_NORMALIZE (1024) +#define WDR3_NORMALIZE_SHIFT (10) +#ifdef ISP_WDR_V3_20BIT +#define MODULE_INPUT_BIT_DEPTH (20) +#else +#define MODULE_INPUT_BIT_DEPTH (12) +#endif +#define MODULE_OUTPUT_BIT_DEPTH (12) + +extern MrvAllRegister_t *all_regs; + +#ifdef ISP_WDR_V3 +static void wdr3_hw_init(struct isp_ic_dev *dev) +{ + + struct isp_wdr3_context *wdr3 = &dev->wdr3; + u32 isp_wdr3_shift_0; + u32 isp_wdr3_shift_1; + + u32 width, height; + u32 slice_block_area_factor; + u32 slice_value_weight[4]; + u32 slice_pixel_slope_merge; + u32 slice_pixel_base_merge; + u32 slice_pixel_slope_adjust; + u32 slice_pixel_base_adjust; + u32 slice_pixel_slope_entropy; + u32 slice_pixel_base_entropy; + u32 slice_sigma_height; + u32 slice_sigma_width; + u32 slice_sigma_value; + u32 slice_block_width; + u32 slice_block_height; + u32 isp_wdr3_block_size; + u32 isp_wdr3_block_area_factor; + u32 isp_wdr3_value_weight; + u32 isp_wdr3_pixel_slope; + u32 isp_wdr3_entropy_slope; + u32 isp_wdr3_sigma_width; + u32 isp_wdr3_sigma_height; + u32 isp_wdr3_sigma_value; + u32 isp_wdr3_block_flag_width; + u32 isp_wdr3_block_flag_height; + u32 isp_wdr3_strength; + u32 width_left; + u32 width_count = 0; + u32 height_left; + u32 height_count = 0; + u32 val; + bool reg_flag = false; + int i, pos; + + pr_info("enter %s\n", __func__); + + width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size)); + height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size)); + + pr_info("wdr3 res: %d %d \n", width, height); + /* firware initilization */ + slice_pixel_slope_merge = 128; + slice_pixel_base_merge = 0; + slice_pixel_slope_adjust = 128; + slice_pixel_base_adjust = 0; + slice_pixel_slope_entropy = 204; + slice_pixel_base_entropy = 716; + + slice_value_weight[0] = 6; + slice_value_weight[1] = 5; + slice_value_weight[2] = 5; + slice_value_weight[3] = 16; + + slice_block_width = width / WDR3_WW; + slice_block_height = height / WDR3_HH; + slice_block_area_factor = + WDR3_NORMALIZE * WDR3_NORMALIZE / (slice_block_width * + slice_block_height); + slice_sigma_height = + WDR3_NORMALIZE * WDR3_NORMALIZE / slice_block_height; + slice_sigma_width = WDR3_NORMALIZE * WDR3_NORMALIZE / slice_block_width; + slice_sigma_value = WDR3_NORMALIZE * WDR3_NORMALIZE / WDR3_MAX_VALUE; + + /* block flag configuration */ + width_left = width - slice_block_width * WDR3_WW; + height_left = height - slice_block_height * WDR3_HH; + isp_wdr3_block_flag_width = 0; + isp_wdr3_block_flag_height = 0; + + for (i = 0, width_count = 0; + (i < WDR3_WW) && (width_count < width_left); i++, width_count++) { + isp_wdr3_block_flag_width |= (1 << i); + } + + for (i = 0, height_count = 0; + (i < WDR3_HH) && (height_count < height_left); + i++, height_count++) { + isp_wdr3_block_flag_height |= (1 << i); + } + + slice_pixel_base_adjust += 255; + slice_pixel_base_merge += 255; + +#ifndef __KERNEL__ + //NOTE: register isp_wdr3_shift is read-only register on fpga, can not write + //NOTE: it is used by cmodel, So it should be config. + u32 slice_pixel_shift; + u32 slice_output_shift; + u32 isp_wdr3_shift; + + slice_pixel_shift = MODULE_INPUT_BIT_DEPTH - 5; + slice_output_shift = MODULE_INPUT_BIT_DEPTH - MODULE_OUTPUT_BIT_DEPTH; + + isp_wdr3_shift = isp_read_reg(dev, REG_ADDR(isp_wdr3_shift)); + REG_SET_SLICE(isp_wdr3_shift, WDR3_PIXEL_SHIFT_BIT, slice_pixel_shift); + REG_SET_SLICE(isp_wdr3_shift, WDR3_OUTPUT_SHIFT_BIT, + slice_output_shift); + isp_write_reg(dev, REG_ADDR(isp_wdr3_shift), isp_wdr3_shift); +#endif + + isp_wdr3_block_size = isp_read_reg(dev, REG_ADDR(isp_wdr3_block_size)); + REG_SET_SLICE(isp_wdr3_block_size, WDR3_BLOCK_WIDTH, slice_block_width); + REG_SET_SLICE(isp_wdr3_block_size, WDR3_BLOCK_HEIGHT, + slice_block_height); + isp_write_reg(dev, REG_ADDR(isp_wdr3_block_size), isp_wdr3_block_size); + + isp_wdr3_block_area_factor = + isp_read_reg(dev, REG_ADDR(isp_wdr3_block_area_factor)); + REG_SET_SLICE(isp_wdr3_block_area_factor, WDR3_BLOCK_AREA_INVERSE, + slice_block_area_factor); + isp_write_reg(dev, REG_ADDR(isp_wdr3_block_area_factor), + isp_wdr3_block_area_factor); + isp_wdr3_value_weight = + isp_read_reg(dev, REG_ADDR(isp_wdr3_value_weight)); + REG_SET_SLICE(isp_wdr3_value_weight, WDR3_VALUE_WEIGHT_0, + slice_value_weight[0]); + REG_SET_SLICE(isp_wdr3_value_weight, WDR3_VALUE_WEIGHT_1, + slice_value_weight[1]); + REG_SET_SLICE(isp_wdr3_value_weight, WDR3_VALUE_WEIGHT_2, + slice_value_weight[2]); + REG_SET_SLICE(isp_wdr3_value_weight, WDR3_VALUE_WEIGHT_3, + slice_value_weight[3]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_value_weight), + isp_wdr3_value_weight); + + isp_wdr3_strength = isp_read_reg(dev, REG_ADDR(isp_wdr3_strength)); + REG_SET_SLICE(isp_wdr3_strength, WDR3_MAXIMUM_GAIN, wdr3->max_gain); + REG_SET_SLICE(isp_wdr3_strength, WDR3_GLOBAL_STRENGTH, + wdr3->global_strength); + REG_SET_SLICE(isp_wdr3_strength, WDR3_LOCAL_STRENGTH, + 128); + REG_SET_SLICE(isp_wdr3_strength, WDR3_TOTAL_STRENGTH, wdr3->strength); + isp_write_reg(dev, REG_ADDR(isp_wdr3_strength), isp_wdr3_strength); + + isp_wdr3_pixel_slope = + isp_read_reg(dev, REG_ADDR(isp_wdr3_pixel_slope)); + REG_SET_SLICE(isp_wdr3_pixel_slope, WDR3_PIXEL_ADJUST_BASE, + slice_pixel_base_adjust); + REG_SET_SLICE(isp_wdr3_pixel_slope, WDR3_PIXEL_ADJUST_SLOPE, + slice_pixel_slope_adjust); + REG_SET_SLICE(isp_wdr3_pixel_slope, WDR3_PIXEL_MERGE_BASE, + slice_pixel_base_merge); + REG_SET_SLICE(isp_wdr3_pixel_slope, WDR3_PIXEL_MERGE_SLOPE, + slice_pixel_slope_merge); + isp_write_reg(dev, REG_ADDR(isp_wdr3_pixel_slope), + isp_wdr3_pixel_slope); + + isp_wdr3_entropy_slope = + isp_read_reg(dev, REG_ADDR(isp_wdr3_entropy_slope)); + REG_SET_SLICE(isp_wdr3_entropy_slope, WDR3_ENTROPY_BASE, + slice_pixel_base_entropy); + REG_SET_SLICE(isp_wdr3_entropy_slope, WDR3_ENTROPY_SLOPE, + slice_pixel_slope_entropy); + isp_write_reg(dev, REG_ADDR(isp_wdr3_entropy_slope), + isp_wdr3_entropy_slope); + + isp_wdr3_sigma_width = + isp_read_reg(dev, REG_ADDR(isp_wdr3_sigma_width)); + REG_SET_SLICE(isp_wdr3_sigma_width, WDR3_BILITERAL_WIDTH_SIGMA, + slice_sigma_width); + isp_write_reg(dev, REG_ADDR(isp_wdr3_sigma_width), + isp_wdr3_sigma_width); + + isp_wdr3_sigma_height = + isp_read_reg(dev, REG_ADDR(isp_wdr3_sigma_height)); + REG_SET_SLICE(isp_wdr3_sigma_height, WDR3_BILITERAL_HEIGHT_SIGMA, + slice_sigma_height); + isp_write_reg(dev, REG_ADDR(isp_wdr3_sigma_height), + isp_wdr3_sigma_height); + + isp_wdr3_sigma_value = + isp_read_reg(dev, REG_ADDR(isp_wdr3_sigma_value)); + REG_SET_SLICE(isp_wdr3_sigma_value, WDR3_BILITERAL_VALUE_SIGMA, + slice_sigma_value); + isp_write_reg(dev, REG_ADDR(isp_wdr3_sigma_value), + isp_wdr3_sigma_value); + + isp_write_reg(dev, REG_ADDR(isp_wdr3_block_flag_width), + isp_wdr3_block_flag_width); + isp_write_reg(dev, REG_ADDR(isp_wdr3_block_flag_height), + isp_wdr3_block_flag_height); + + for (i = 0; i < 5; i++) { + reg_flag = i < 4; + pos = i * 3; + val = + wdr3->histogram[pos] << (reg_flag ? + WDR3_HISTOGRAM_CURVE0_SHIFT : + WDR3_HISTOGRAM_CURVE1_SHIFT); + val |= + wdr3->histogram[pos + + 1] << (reg_flag ? + WDR3_HISTOGRAM_CURVE1_SHIFT : + WDR3_HISTOGRAM_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_HISTOGRAM_CURVE2, + wdr3->histogram[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_histogram[i]), val); + + val = + wdr3->entropy[pos] << (reg_flag ? + WDR3_ENTROPY_CONVERT0_SHIFT : + WDR3_ENTROPY_CONVERT1_SHIFT); + val |= + wdr3->entropy[pos + + 1] << (reg_flag ? WDR3_ENTROPY_CONVERT1_SHIFT + : WDR3_ENTROPY_CONVERT2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_ENTROPY_CONVERT2, + wdr3->entropy[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_entropy[i]), val); + + val = + wdr3->gamma_pre[pos] << (reg_flag ? + WDR3_GAMMA_PRE_CURVE0_SHIFT : + WDR3_GAMMA_PRE_CURVE1_SHIFT); + val |= + wdr3->gamma_pre[pos + + 1] << (reg_flag ? + WDR3_GAMMA_PRE_CURVE1_SHIFT : + WDR3_GAMMA_PRE_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_GAMMA_PRE_CURVE2, + wdr3->gamma_pre[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_gamma_pre[i]), val); + + val = + wdr3->gamma_up[pos] << (reg_flag ? + WDR3_GAMMA_UP_CURVE0_SHIFT : + WDR3_GAMMA_UP_CURVE1_SHIFT); + val |= + wdr3->gamma_up[pos + + 1] << (reg_flag ? WDR3_GAMMA_UP_CURVE1_SHIFT + : WDR3_GAMMA_UP_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_GAMMA_UP_CURVE2, + wdr3->gamma_up[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_gamma_up[i]), val); + + val = + wdr3->gamma_down[pos] << (reg_flag ? + WDR3_GAMMA_DOWN_CURVE0_SHIFT : + WDR3_GAMMA_DOWN_CURVE1_SHIFT); + val |= + wdr3->gamma_down[pos + + 1] << (reg_flag ? + WDR3_GAMMA_DOWN_CURVE1_SHIFT : + WDR3_GAMMA_DOWN_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_GAMMA_DOWN_CURVE2, + wdr3->gamma_down[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_gamma_down[i]), val); + + val = + wdr3->distance_weight[pos] << (reg_flag ? + WDR3_DISTANCE_WEIGHT_CURVE0_SHIFT + : + WDR3_DISTANCE_WEIGHT_CURVE1_SHIFT); + val |= + wdr3->distance_weight[pos + + 1] << (reg_flag ? + WDR3_DISTANCE_WEIGHT_CURVE1_SHIFT + : + WDR3_DISTANCE_WEIGHT_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_DISTANCE_WEIGHT_CURVE2, + wdr3->distance_weight[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_distance_weight[i]), val); + + val = + wdr3->difference_weight[pos] << (reg_flag ? + WDR3_DIFFERENCE_WEIGHT_CURVE0_SHIFT + : + WDR3_DIFFERENCE_WEIGHT_CURVE1_SHIFT); + val |= + wdr3->difference_weight[pos + + 1] << (reg_flag ? + WDR3_DIFFERENCE_WEIGHT_CURVE1_SHIFT + : + WDR3_DIFFERENCE_WEIGHT_CURVE2_SHIFT); + if (reg_flag) + REG_SET_SLICE(val, WDR3_DIFFERENCE_WEIGHT_CURVE2, + wdr3->difference_weight[pos + 2]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_difference_weight[i]), + val); + } + + for (i = 0; i < 7; i++) { + val = 0; + REG_SET_SLICE(val, WDR3_GLOBAL_CURVE_INVERT0, + wdr3->invert_curve[i * 2]); + REG_SET_SLICE(val, WDR3_GLOBAL_CURVE_INVERT1, + wdr3->invert_curve[i * 2 + 1]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_invert_curve[i]), val); + val = 0; + REG_SET_SLICE(val, WDR3_LINEAR_CURVE_INVERT0, + wdr3->invert_linear[i * 2]); + REG_SET_SLICE(val, WDR3_LINEAR_CURVE_INVERT1, + wdr3->invert_linear[i * 2 + 1]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_invert_linear[i]), val); + } + + isp_wdr3_shift_0 = 0; + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT0, wdr3->shift[0]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT1, wdr3->shift[1]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT2, wdr3->shift[2]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT3, wdr3->shift[3]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT4, wdr3->shift[4]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT5, wdr3->shift[5]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT6, wdr3->shift[6]); + REG_SET_SLICE(isp_wdr3_shift_0, WDR3_HISTOGRAM_SHIFT7, wdr3->shift[7]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_shift_0), isp_wdr3_shift_0); + + isp_wdr3_shift_1 = 0; + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT8, wdr3->shift[8]); + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT9, wdr3->shift[9]); + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT10, + wdr3->shift[10]); + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT11, + wdr3->shift[11]); + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT12, + wdr3->shift[12]); + REG_SET_SLICE(isp_wdr3_shift_1, WDR3_HISTOGRAM_SHIFT13, + wdr3->shift[13]); + isp_write_reg(dev, REG_ADDR(isp_wdr3_shift_1), isp_wdr3_shift_1); + + { + uint32_t isp_wdr3_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr3_ctrl)); + REG_SET_SLICE(isp_wdr3_ctrl, WDR3_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_wdr3_ctrl), isp_wdr3_ctrl); + } +} +#endif + +int isp_enable_wdr3(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V3 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_wdr3_context *wdr3 = &dev->wdr3; + int32_t isp_wdr3_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr3_ctrl)); + wdr3->enable = true; + REG_SET_SLICE(isp_wdr3_ctrl, WDR3_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_wdr3_ctrl), isp_wdr3_ctrl); + + { + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } + return 0; +#endif +} + +int isp_disable_wdr3(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V3 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_wdr3_context *wdr3 = &dev->wdr3; + int32_t isp_wdr3_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr3_ctrl)); + wdr3->enable = false; + REG_SET_SLICE(isp_wdr3_ctrl, WDR3_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_wdr3_ctrl), isp_wdr3_ctrl); + + { + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } + return 0; +#endif +} + +int isp_u_wdr3(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V3 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + wdr3_hw_init(dev); + return 0; +#endif +} + +int isp_s_wdr3(struct isp_ic_dev *dev) +{ + +#ifndef ISP_WDR_V3 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_wdr3_context *wdr3 = &dev->wdr3; + u32 isp_wdr3_strength = isp_read_reg(dev, REG_ADDR(isp_wdr3_strength)); + u32 width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size)); + u32 height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size)); + width /= 32; + height /= 32; + + REG_SET_SLICE(isp_wdr3_strength, WDR3_MAXIMUM_GAIN, wdr3->max_gain); + REG_SET_SLICE(isp_wdr3_strength, WDR3_GLOBAL_STRENGTH, + wdr3->global_strength); + REG_SET_SLICE(isp_wdr3_strength, WDR3_LOCAL_STRENGTH, 128); + REG_SET_SLICE(isp_wdr3_strength, WDR3_TOTAL_STRENGTH, wdr3->strength); + + isp_write_reg(dev, REG_ADDR(isp_wdr3_block_size), + width | (height << 9)); + isp_write_reg(dev, REG_ADDR(isp_wdr3_strength), isp_wdr3_strength); + isp_write_reg(dev, REG_ADDR(isp_wdr3_strength_shd), isp_wdr3_strength); /* cmodel use */ + + { + uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + } + return 0; +#endif +} diff --git a/vvcam_ry/isp/isp_wdr4.c b/vvcam_ry/isp/isp_wdr4.c new file mode 100755 index 0000000..0ffc82c --- /dev/null +++ b/vvcam_ry/isp/isp_wdr4.c @@ -0,0 +1,515 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include +#include +#endif +#include "mrv_all_bits.h" +#include "isp_ioctl.h" +#include "isp_types.h" + +#ifdef ISP_WDR_V4 +#define WDR4_WW (32) +#define WDR4_HH (32) +#define WDR4_MAX_VALUE (1048575) +#define WDR4_GAIN_SHIFT (2) +#define WDR4_NORMALIZE (1024) +#define WDR4_NORMALIZE_SHIFT (10) +#ifdef ISP_WDR_V4_20BIT +#define MODULE_INPUT_BIT_DEPTH (20) +#else +#define MODULE_INPUT_BIT_DEPTH (12) +#endif +#define MODULE_OUTPUT_BIT_DEPTH (12) + +extern MrvAllRegister_t *all_regs; + +static void wdr4_config_curve(struct isp_ic_dev *dev) +{ + struct isp_wdr4_context *wdr4 = &dev->wdr4; + u32 pos, i , val; + //u32 isp_wdr4_shift_0; + //u32 isp_wdr4_shift0_0; + //initialize the histogram && entropy && gamma_pre && gamma_up && gamma_down && invert_linear + for (i = 0; i < 7; i++) { + u32 val_high_bit, val_low_bit; + pos = i * 3; + //get the curve that combined with high && low data + val_high_bit = (wdr4->histogram[pos] >> 10) & (0x3ff); + val_low_bit = wdr4->histogram[pos] & (0x3ff); + + val = val_low_bit << WDR4_HISTOGRAM_CURVE0_0_SHIFT ; + val |= wdr4->histogram[pos +1]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_histogram_0) + i * 2 * ISP_REG_GAP, val); + + val = val_high_bit << WDR4_HISTOGRAM_CURVE0_0_SHIFT ; + + if (pos + 2 < WDR4_BIN) { + val |= wdr4->histogram[pos +2]; + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_histogram_0) + (i *2 + 1) * ISP_REG_GAP, val); + + //get the value that combined with high && low data + val_high_bit = (wdr4->gamma_pre[pos] >> 10) & 0x3ff; + val_low_bit = (wdr4->gamma_pre[pos] & 0x3ff) ; + + val = val_low_bit << WDR4_GAMMA_PRE_CURVE0_1_SHIFT ; + val |= wdr4->gamma_pre[pos +1]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_gamma_pre_0) + (i * 2) * ISP_REG_GAP, val); + + val = val_high_bit << WDR4_GAMMA_PRE_CURVE0_1_SHIFT ; + + if (pos + 2 < WDR4_BIN) + val |= wdr4->gamma_pre[pos +2]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_gamma_pre_0) + (i *2 + 1) * ISP_REG_GAP, val); + + + //get the value that combined with high && low data + val_high_bit = (wdr4->gamma_up[pos] >> 10) & 0x3ff; + val_low_bit = (wdr4->gamma_up[pos] & 0x3ff); + + val = val_low_bit <gamma_up[pos +1]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_gamma_up_0) + (i * 2) * ISP_REG_GAP, val); + val = val_high_bit <gamma_up[pos +2]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_gamma_up_0) + (i *2 + 1) * ISP_REG_GAP, val); + + + //get the value that combined with high && low data + val_high_bit = (wdr4->invert_linear[pos] >> 9) & 0x1ff; + val_low_bit = (wdr4->invert_linear[pos] & 0x1ff); + + val = val_low_bit << WDR4_LINEAR_CURVE_INVERT0_0_SHIFT; + val |= wdr4->invert_linear[pos +1]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_invert_linear_0) + (i * 2) * ISP_REG_GAP, val); + val = val_high_bit << WDR4_LINEAR_CURVE_INVERT0_0_SHIFT; + if (pos + 2 < WDR4_BIN) + val |= wdr4->invert_linear[pos +2]; + isp_write_reg(dev, REG_ADDR(isp_wdr4_invert_linear_0) + (i *2 + 1) * ISP_REG_GAP, val); + + if (pos + 2 < WDR4_BIN) { + val = wdr4->entropy[pos] << WDR4_ENTROPY_CONVERT0_SHIFT ; + val |= wdr4->entropy[pos +1] << WDR4_ENTROPY_CONVERT1_SHIFT; + + val |= wdr4->entropy[pos +2] << WDR4_ENTROPY_CONVERT2_SHIFT; + } else { //the lasw two entropy + val = wdr4->entropy[pos] << WDR4_ENTROPY_CONVERT18_SHIFT ; + val |= wdr4->entropy[pos +1] << WDR4_ENTROPY_CONVERT19_SHIFT; + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_entropy_0) + i * ISP_REG_GAP, val); + + if (pos + 2 < WDR4_BIN) { + val = wdr4->gamma_down[pos] << WDR4_GAMMA_DOWN_CURVE0_SHIFT ; + val |= wdr4->gamma_down[pos +1] << WDR4_GAMMA_DOWN_CURVE1_SHIFT; + + val |= wdr4->gamma_down[pos +2] << WDR4_GAMMA_DOWN_CURVE2_SHIFT; + } else { //the lasw two entropy + val = wdr4->gamma_down[pos] << WDR4_GAMMA_DOWN_CURVE18_SHIFT ; + val |= wdr4->gamma_down[pos +1] << WDR4_GAMMA_DOWN_CURVE19_SHIFT; + + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_gamma_down_0) + i * ISP_REG_GAP, val); + } + + //config the distance weight && different weight && SMOOTH INVERT + for (i = 0 ; i < 5 ; i++) { + pos = i * ISP_REG_GAP; + val = wdr4->distance_weight[pos] << WDR4_DISTANCE_WEIGHT_CURVE0_SHIFT ; + val |= wdr4->distance_weight[pos +1] << WDR4_DISTANCE_WEIGHT_CURVE1_SHIFT; + val |= wdr4->distance_weight[pos +2] << WDR4_DISTANCE_WEIGHT_CURVE2_SHIFT; + val |= wdr4->distance_weight[pos +3] << WDR4_DISTANCE_WEIGHT_CURVE3_SHIFT; + isp_write_reg(dev, REG_ADDR(isp_wdr4_distance_weight_0) + i * ISP_REG_GAP, val); + + val = wdr4->difference_weight[pos] << WDR4_DIFFERENCE_WEIGHT_CURVE0_SHIFT ; + val |= wdr4->difference_weight[pos +1] << WDR4_DIFFERENCE_WEIGHT_CURVE1_SHIFT; + val |= wdr4->difference_weight[pos +2] << WDR4_DIFFERENCE_WEIGHT_CURVE2_SHIFT; + val |= wdr4->difference_weight[pos +3] << WDR4_DIFFERENCE_WEIGHT_CURVE3_SHIFT; + + + isp_write_reg(dev, REG_ADDR(isp_wdr4_difference_weight_0) + i * ISP_REG_GAP, val); + + + val = wdr4->smooth_invert[pos] << WDR4_SMOOTH_INVERT_CURVE0_SHIFT ; + val |= wdr4->smooth_invert[pos +1] << WDR4_SMOOTH_INVERT_CURVE1_SHIFT; + val |= wdr4->smooth_invert[pos +2] << WDR4_SMOOTH_INVERT_CURVE2_SHIFT; + val |= wdr4->smooth_invert[pos +3] << WDR4_SMOOTH_INVERT_CURVE3_SHIFT; + isp_write_reg(dev, REG_ADDR(isp_wdr4_smooth_invert_0) + i * ISP_REG_GAP, val); + + } + for (i = 0; i < 10; i++) { + val = 0; + REG_SET_SLICE(val, WDR4_GLOBAL_CURVE_INVERT0, + wdr4->invert_curve[i * 2]); + REG_SET_SLICE(val, WDR4_GLOBAL_CURVE_INVERT1, + wdr4->invert_curve[i * 2 + 1]); + isp_write_reg(dev, REG_ADDR(isp_wdr4_invert_curve_0) + i * ISP_REG_GAP, val); + + } + + for (i = 0 ; i < 4; i++) { + val = 0 ; + pos = i * 6; + if (pos + 3 > WDR4_BIN) { + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT18, wdr4->shift[ pos +0]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT19, wdr4->shift[ pos +1]); + } else { + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT0, wdr4->shift[ pos +0]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT1, wdr4->shift[ pos +1]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT2, wdr4->shift[ pos +2]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT3, wdr4->shift[ pos +3]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT4, wdr4->shift[ pos +4]); + REG_SET_SLICE(val, WDR4_HISTOGRAM_SHIFT5, wdr4->shift[ pos +5]); + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_shift_0) + i * ISP_REG_GAP, val); + + } + + for (i = 0 ; i < 3; i++) { + val = 0 ; + pos = i * 8; + if (pos + 5 > WDR4_BIN) { + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT16, wdr4->shift0[ pos +0]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT17, wdr4->shift0[ pos +1]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT18, wdr4->shift0[ pos +2]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT19, wdr4->shift0[ pos +3]); + } else { + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT0, wdr4->shift0[ pos +0]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT1, wdr4->shift0[ pos +1]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT2, wdr4->shift0[ pos +2]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT3, wdr4->shift0[ pos +3]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT4, wdr4->shift0[ pos +4]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT5, wdr4->shift0[ pos +5]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT6, wdr4->shift0[ pos +6]); + REG_SET_SLICE(val, WDR4_HISTOGRAM0_SHIFT7, wdr4->shift0[ pos +7]); + } + + isp_write_reg(dev, REG_ADDR(isp_wdr4_shift0_0) + i * ISP_REG_GAP, val); + } + +} +static void wdr4_hw_init(struct isp_ic_dev *dev) +{ + // struct isp_wdr4_context *wdr4 = &dev->wdr4; + u32 width, height; + u32 slice_sigma_height; + u32 slice_sigma_width; + u32 slice_sigma_value; + u32 slice_block_width; + u32 slice_block_height; + u32 isp_wdr4_block_size; + u32 slice_block_area_inverse; + u32 isp_wdr4_value_weight; + u32 isp_wdr4_pixel_slope; + u32 isp_wdr4_entropy_slope; + u32 isp_wdr4_sigma_width; + u32 isp_wdr4_sigma_height; + u32 isp_wdr4_sigma_value; + u32 isp_wdr4_block_flag_width; + u32 isp_wdr4_block_flag_height; + u32 isp_wdr4_strength; + u32 isp_wdr4_block_area_factor; + u32 width_left; + u32 width_count = 0; + u32 height_left; + u32 height_count = 0; + u32 isp_wdr4_strength_0 = 0, isp_wdr4_strength_1 = 0, isp_wdr4_contrast = 0; + int i; + u8 isp_wdr4_low_strength, isp_wdr4_high_strength, isp_wdr4_global_strength; + u8 isp_wdr4_local_strength; + + u32 slice_pixel_shift; + u32 slice_output_shift;// isp_wdr4_normalize_shift; + u32 isp_wdr4_shift;// isp_wdr4_gain_shift_bit; + pr_info("enter %s\n", __func__); + + width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size)); + height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size)); + + pr_info("isp_wdr4 res: %d %d \n", width, height); + /* firware initilization */ + + isp_wdr4_strength = 128; // valid values: [0,128]; isp_wdr4 will merge original and enhanced image + // together based on this value. + // 128: use enhanced image completely; 0: use original image completely + isp_wdr4_low_strength = 16; // Valid values: [0,255]; if hdr off, limit the maximum gain for image enhancement + // if hdr on, control low light area information. Higher:haver more low light information + isp_wdr4_high_strength = 60; //valid values:[0, 128]: control high light area information. Higher:have more high + // light information + isp_wdr4_global_strength = 128; // Valid values: [0,128] + // isp_wdr4 will increase global contrast based on this value. + // 128: use strongest contrast; 0: on contrast increasing. + isp_wdr4_local_strength = 128; // valid values: [0,128] + // wdr4 will increase local contrast based on this value. + // 128: use strongest contrast; 0: on contrast increasing. + + isp_wdr4_strength_0 = isp_read_reg(dev, REG_ADDR(isp_wdr4_strength_0)); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_LOCAL_STRENGTH, isp_wdr4_local_strength); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_GLOBAL_STRENGTH, isp_wdr4_global_strength); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_LOW_STRENGTH, isp_wdr4_low_strength); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_TOTAL_STRENGTH,isp_wdr4_strength); + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_0), isp_wdr4_strength_0); + + isp_wdr4_strength_1 = isp_read_reg(dev, REG_ADDR(isp_wdr4_strength_1)); + REG_SET_SLICE(isp_wdr4_strength_1, WDR4_HIGH_STRENGTH, isp_wdr4_high_strength); + REG_SET_SLICE(isp_wdr4_strength_1, WDR4_DRC_BAYER_RATIO, 14); + REG_SET_SLICE(isp_wdr4_strength_1, WDR4_DRC_BAYER_RATIOLSVS, 14); + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_1), isp_wdr4_strength_1); + + isp_wdr4_contrast = isp_read_reg(dev, REG_ADDR(isp_wdr4_contrast)); + REG_SET_SLICE(isp_wdr4_contrast , WDR4_CONTRAST ,0); //valid values:[-1023~1023]:control contrast of image,.higher:image have stronger contrast + REG_SET_SLICE(isp_wdr4_contrast , WDR4_FLAT_STRENGTH ,8);//valid values:[0, 19]:adjust flat area. Higher:flat area stretched more strong + REG_SET_SLICE(isp_wdr4_contrast , WDR4_FLAT_THR ,1); //valid values:[0, 20]:judge flat region. + + isp_write_reg(dev, REG_ADDR(isp_wdr4_contrast), isp_wdr4_contrast); + + isp_wdr4_pixel_slope = isp_read_reg(dev, REG_ADDR(isp_wdr4_pixel_slope)); + REG_SET_SLICE(isp_wdr4_pixel_slope , WDR4_PIXEL_MERGE_SLOPE , 128); + REG_SET_SLICE(isp_wdr4_pixel_slope , WDR4_PIXEL_MERGE_BASE , 128); + REG_SET_SLICE(isp_wdr4_pixel_slope , WDR4_PIXEL_ADJUST_SLOPE ,128); + REG_SET_SLICE(isp_wdr4_pixel_slope , WDR4_PIXEL_ADJUST_BASE , 128); + + isp_write_reg(dev, REG_ADDR(isp_wdr4_pixel_slope), isp_wdr4_pixel_slope); + + isp_wdr4_entropy_slope = isp_read_reg(dev, REG_ADDR(isp_wdr4_entropy_slope)); + REG_SET_SLICE(isp_wdr4_entropy_slope , WDR4_ENTROPY_SLOPE , 0xc8); + REG_SET_SLICE(isp_wdr4_entropy_slope , WDR4_ENTROPY_BASE ,0x02bc); + isp_write_reg(dev, REG_ADDR(isp_wdr4_entropy_slope), isp_wdr4_entropy_slope); + + isp_wdr4_value_weight = isp_read_reg(dev, REG_ADDR(isp_wdr4_value_weight)); + REG_SET_SLICE(isp_wdr4_value_weight , WDR4_VALUE_WEIGHT_0 , 6); + REG_SET_SLICE(isp_wdr4_value_weight , WDR4_VALUE_WEIGHT_1 , 5); + REG_SET_SLICE(isp_wdr4_value_weight , WDR4_VALUE_WEIGHT_2 , 5); + REG_SET_SLICE(isp_wdr4_value_weight , WDR4_VALUE_WEIGHT_3 , 16); + isp_write_reg(dev, REG_ADDR(isp_wdr4_value_weight), isp_wdr4_value_weight); + + slice_block_width = width / WDR4_WW; + slice_block_height = height / WDR4_HH; + isp_wdr4_block_size = 0; + REG_SET_SLICE(isp_wdr4_block_size, WDR4_BLOCK_WIDTH, slice_block_width); + REG_SET_SLICE(isp_wdr4_block_size, WDR4_BLOCK_HEIGHT, slice_block_height); + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_size), isp_wdr4_block_size); + + slice_block_area_inverse = + WDR4_NORMALIZE * WDR4_NORMALIZE / (slice_block_width * + slice_block_height); + isp_wdr4_block_area_factor = isp_read_reg(dev, REG_ADDR(isp_wdr4_block_area_factor)); + REG_SET_SLICE(isp_wdr4_block_area_factor, WDR4_BLOCK_AREA_INVERSE, slice_block_area_inverse); + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_area_factor), isp_wdr4_block_area_factor); + + slice_sigma_height = + WDR4_NORMALIZE * WDR4_NORMALIZE / slice_block_height; + slice_sigma_width = WDR4_NORMALIZE * WDR4_NORMALIZE / slice_block_width; + slice_sigma_value = WDR4_NORMALIZE * WDR4_NORMALIZE/ WDR4_MAX_VALUE; + + isp_wdr4_sigma_width = + isp_read_reg(dev, REG_ADDR(isp_wdr4_sigma_width)); + REG_SET_SLICE(isp_wdr4_sigma_width, WDR4_BILITERAL_WIDTH_SIGMA, + slice_sigma_width); + isp_write_reg(dev, REG_ADDR(isp_wdr4_sigma_width), + isp_wdr4_sigma_width); + + isp_wdr4_sigma_height = isp_read_reg(dev, REG_ADDR(isp_wdr4_sigma_height)); + REG_SET_SLICE(isp_wdr4_sigma_height, WDR4_BILITERAL_HEIGHT_SIGMA, + slice_sigma_height); + isp_write_reg(dev, REG_ADDR(isp_wdr4_sigma_height), + isp_wdr4_sigma_height); + + isp_wdr4_sigma_value = isp_read_reg(dev, REG_ADDR(isp_wdr4_sigma_value)); + REG_SET_SLICE(isp_wdr4_sigma_value, WDR4_BILITERAL_VALUE_SIGMA, + slice_sigma_value); + isp_write_reg(dev, REG_ADDR(isp_wdr4_sigma_value), + isp_wdr4_sigma_value); + + /* block flag configuration */ + width_left = width - slice_block_width * WDR4_WW; + height_left = height - slice_block_height * WDR4_HH; + + + // isp_wdr4_gain_shift_bit = 8; + // isp_wdr4_normalize_shift = 10; + slice_pixel_shift = MODULE_INPUT_BIT_DEPTH - 15; + slice_output_shift = MODULE_INPUT_BIT_DEPTH - MODULE_OUTPUT_BIT_DEPTH; + + + isp_wdr4_shift = isp_read_reg(dev, REG_ADDR(isp_wdr4_shift)); + REG_SET_SLICE(isp_wdr4_shift, WDR4_PIXEL_SHIFT_BIT, slice_pixel_shift); + REG_SET_SLICE(isp_wdr4_shift, WDR4_OUTPUT_SHIFT_BIT, + slice_output_shift); + isp_write_reg(dev, REG_ADDR(isp_wdr4_shift), isp_wdr4_shift); + + + /* block flag configuration */ + width_left = width - slice_block_width * WDR4_WW; + height_left = height - slice_block_height * WDR4_HH; + + isp_wdr4_block_flag_width = 0; + isp_wdr4_block_flag_height = 0; + + for (i = 0, width_count = 0; + (i < WDR4_WW) && (width_count < width_left); i++, width_count++) { + isp_wdr4_block_flag_width |= (1 << i); + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_flag_width), isp_wdr4_block_flag_width); + + for (i = 0, height_count = 0; + (i < WDR4_HH) && (height_count < height_left); + i++, height_count++) { + isp_wdr4_block_flag_height |= (1 << i); + } + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_flag_height), isp_wdr4_block_flag_height); + + isp_wdr4_block_size = isp_read_reg(dev, REG_ADDR(isp_wdr4_block_size)); + REG_SET_SLICE(isp_wdr4_block_size, WDR4_BLOCK_WIDTH, slice_block_width); + REG_SET_SLICE(isp_wdr4_block_size, WDR4_BLOCK_HEIGHT, + slice_block_height); + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_size), isp_wdr4_block_size); + + wdr4_config_curve(dev); +#if 1 + { + uint32_t isp_wdr4_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr4_ctrl)); + REG_SET_SLICE(isp_wdr4_ctrl, WDR4_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_wdr4_ctrl), isp_wdr4_ctrl); + } +#endif +} + +int isp_enable_wdr4(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V4 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + int32_t isp_wdr4_ctrl; + struct isp_wdr4_context *wdr4 = &dev->wdr4; + isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl)); + isp_read_reg(dev, REG_ADDR(isp_dmsc_cac_y_norm_shd)); + + isp_wdr4_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr4_ctrl)); + wdr4->enable = true; + REG_SET_SLICE(isp_wdr4_ctrl, WDR4_ENABLE, 1); + isp_write_reg(dev, REG_ADDR(isp_wdr4_ctrl), isp_wdr4_ctrl); + + return 0; +#endif +} + +int isp_disable_wdr4(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V4 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_wdr4_context *wdr4 = &dev->wdr4; + int32_t isp_wdr4_ctrl = isp_read_reg(dev, REG_ADDR(isp_wdr4_ctrl)); + wdr4->enable = false; + REG_SET_SLICE(isp_wdr4_ctrl, WDR4_ENABLE, 0); + isp_write_reg(dev, REG_ADDR(isp_wdr4_ctrl), isp_wdr4_ctrl); + + return 0; +#endif +} + +int isp_u_wdr4(struct isp_ic_dev *dev) +{ +#ifndef ISP_WDR_V4 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + wdr4_hw_init(dev); + return 0; +#endif +} + +int isp_s_wdr4(struct isp_ic_dev *dev) +{ + +#ifndef ISP_WDR_V4 + pr_err("unsupported function: %s", __func__); + return -EINVAL; +#else + struct isp_wdr4_context *wdr4 = &dev->wdr4; + u32 isp_wdr4_strength_0 = isp_read_reg(dev, REG_ADDR(isp_wdr4_strength_0)); + u32 isp_wdr4_strength_1 = isp_read_reg(dev, REG_ADDR(isp_wdr4_strength_1)); + u32 isp_wdr4_contrast = isp_read_reg(dev, REG_ADDR(isp_wdr4_contrast)); + u32 width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size)); + u32 height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size)); + width /= 32; + height /= 32; + + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_LOW_STRENGTH, wdr4->low_gain); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_GLOBAL_STRENGTH, + wdr4->global_strength); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_LOCAL_STRENGTH, 128); + REG_SET_SLICE(isp_wdr4_strength_0, WDR4_TOTAL_STRENGTH, wdr4->strength); + REG_SET_SLICE(isp_wdr4_strength_1, WDR4_HIGH_STRENGTH, wdr4->high_strength); + + REG_SET_SLICE(isp_wdr4_contrast , WDR4_CONTRAST, wdr4->contrast); //valid values:[-1023~1023]:control contrast of image,.higher:image have stronger contrast + REG_SET_SLICE(isp_wdr4_contrast , WDR4_FLAT_STRENGTH, wdr4->flat_strength);//valid values:[0, 19]:adjust flat area. Higher:flat area stretched more strong + REG_SET_SLICE(isp_wdr4_contrast , WDR4_FLAT_THR, wdr4->flat_threshold); //valid values:[0, 20]:judge flat region. + isp_write_reg(dev, REG_ADDR(isp_wdr4_contrast), isp_wdr4_contrast); + + isp_write_reg(dev, REG_ADDR(isp_wdr4_block_size), + width | (height << 9)); + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_0), isp_wdr4_strength_0); + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_1), isp_wdr4_strength_1); + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_0_shd), isp_wdr4_strength_0); /* cmodel use */ + isp_write_reg(dev, REG_ADDR(isp_wdr4_strength_1_shd), isp_wdr4_strength_1); /* cmodel use */ + + return 0; +#endif +} +#endif + diff --git a/vvcam_ry/isp/mrv_all_bits.h b/vvcam_ry/isp/mrv_all_bits.h new file mode 100755 index 0000000..3ae3873 --- /dev/null +++ b/vvcam_ry/isp/mrv_all_bits.h @@ -0,0 +1,10445 @@ +/****************************************************************************** + * + * Copyright 2010, Dream Chip Technologies GmbH. All rights reserved. + * + **************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef __MRV_ALL_BITS_H__ +#define __MRV_ALL_BITS_H__ + +/*****************************************************************************/ +/* this includes the registermap generated by SIG-flow */ +/*****************************************************************************/ +#ifndef __KERNEL__ +#include +#else +#include +#endif +#include "mrv_all_regs.h" + +/*****************************************************************************/ +/* this includes the hw version information */ +/*****************************************************************************/ +#include "isp_version.h" + +/*****************************************************************************/ +/* Marvin Main Control Registers */ +/*****************************************************************************/ +#define ALIGN_16BYTE(width) (((width) + (0xF - 1)) & (~(0xF - 1))) + +/*****************************************************************************/ +/** + * register: vi_ccl: Data path control register (0x0000) + * + *****************************************************************************/ +/* Slice: vi_ccl_dis:*/ +/* Clock Control Logic disable */ +/* 0: processing/cfg-clocks for all marvin sub modules enabled */ +/* 1: processing/cfg-clocks for all marvin sub modules disabled w/o access to ID and VI_CCL register */ +#ifdef MRV_VI_CCL_DIS +#define MRV_VI_CCL_ENABLE_CLOCKS 0 +#define MRV_VI_CCL_DISABLE_CLOCKS 1 +#endif /* MRV_VI_CCL_DIS */ + +/*****************************************************************************/ +/** + * register: vi_id: Revision identification register (0x0008) + * + *****************************************************************************/ +/* Slice: rev_id:*/ +/* MARVIN5 revision IDs */ +#ifdef MRV_REV_ID +#endif /* MRV_REV_ID */ + +/*****************************************************************************/ +/** + * register: vi_iccl: Internal clock control register (0x0010) + * + *****************************************************************************/ + /* Slice: vi_mipi_clk_enable: */ + /* MIPI interface clock enable */ + /* 1: processing mode */ + /* 0: power safe */ +#ifdef MRV_VI_MIPI_CLK_ENABLE +#endif /* MRV_VI_MIPI_CLK_ENABLE */ + +/* Slice: vi_smia_clk_enable:*/ +/* SMIA interface clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_SMIA_CLK_ENABLE +#endif /* MRV_VI_SMIA_CLK_ENABLE */ + +/* Slice: vi_simp_clk_enable:*/ +/* Superimpose clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_SIMP_CLK_ENABLE +#endif /* MRV_VI_SIMP_CLK_ENABLE */ + +/* Slice: vi_ie_clk_enable:*/ +/* Image effect clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_IE_CLK_ENABLE +#endif /* MRV_VI_IE_CLK_ENABLE */ + +/* Slice: vi_mi_clk_enable:*/ +/* memory interface clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_MI_CLK_ENABLE +#endif /* MRV_VI_MI_CLK_ENABLE */ + +/* Slice: vi_jpeg_clk_enable:*/ +/* JPEG encoder clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_JPEG_CLK_ENABLE +#endif /* MRV_VI_JPEG_CLK_ENABLE */ + +/* Slice: vi_srsz_clk_enable:*/ +/* main resize clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_SRSZ_CLK_ENABLE +#endif /* MRV_VI_SRSZ_CLK_ENABLE */ + +/* Slice: vi_mrsz_clk_enable:*/ +/* main resize clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_MRSZ_CLK_ENABLE +#endif /* MRV_VI_MRSZ_CLK_ENABLE */ + +/* Slice: vi_cp_clk_enable:*/ +/* color processing clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_CP_CLK_ENABLE +#endif /* MRV_VI_CP_CLK_ENABLE */ + +/* Slice: vi_isp_clk_enable:*/ +/* isp processing clock enable */ +/* 1: processing mode */ +/* 0: power safe */ +#ifdef MRV_VI_ISP_CLK_ENABLE +#endif /* MRV_VI_ISP_CLK_ENABLE */ + +/*****************************************************************************/ +/** + * register: vi_ircl: Internal reset control register (0x0014) + * + *****************************************************************************/ +/* Slice: vi_mipi_soft_rst:*/ +/* MIPI Interface software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_MIPI_SOFT_RST +#endif /* MRV_VI_MIPI_SOFT_RST */ + +/* Slice: vi_smia_soft_rst:*/ +/* SMIA Interface software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_SMIA_SOFT_RST +#endif /* MRV_VI_SMIA_SOFT_RST */ + +/* Slice: vi_simp_soft_rst:*/ +/* Superimpose software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_SIMP_SOFT_RST +#endif /* MRV_VI_SIMP_SOFT_RST */ + +/* Slice: vi_ie_soft_rst:*/ +/* Image effect software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_IE_SOFT_RST +#endif /* MRV_VI_IE_SOFT_RST */ + +/* Slice: vi_marvin_rst:*/ +/* Soft reset of entire marvin */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_MARVIN_RST +#endif /* MRV_VI_MARVIN_RST */ + +/* Slice: vi_mi_soft_rst:*/ +/* memory interface software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_MI_SOFT_RST +#endif /* MRV_VI_MI_SOFT_RST */ + +/* Slice: vi_jpeg_soft_rst:*/ +/* JPEG encoder software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_JPEG_SOFT_RST +#endif /* MRV_VI_JPEG_SOFT_RST */ + +/* Slice: vi_srsz_soft_rst:*/ +/* Self-picture resize software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_SRSZ_SOFT_RST +#endif /* MRV_VI_SRSZ_SOFT_RST */ + +/* Slice: vi_mrsz_soft_rst:*/ +/* Main-picture resize software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_MRSZ_SOFT_RST +#endif /* MRV_VI_MRSZ_SOFT_RST */ + +/* Slice: vi_ycs_soft_rst:*/ +/* y/c splitter software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_YCS_SOFT_RST +#endif /* MRV_VI_YCS_SOFT_RST */ + +/* Slice: vi_cp_soft_rst:*/ +/* color processing software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_CP_SOFT_RST +#endif /* MRV_VI_CP_SOFT_RST */ + +/* Slice: vi_isp_soft_rst:*/ +/* isp software reset */ +/* 0: processing mode */ +/* 1: reset state */ +#ifdef MRV_VI_ISP_SOFT_RST +#endif /* MRV_VI_ISP_SOFT_RST */ + +/*****************************************************************************/ +/** + * register: vi_dpcl: Data path control register (0x0018) + * + *****************************************************************************/ +/* Slice: vi_dma_spmux:*/ +/* 0: data from camera interface to self resize */ +/* 1: data from DMA read port to self resize */ +#ifdef MRV_VI_DMA_SPMUX +#define MRV_VI_DMA_SPMUX_CAM 0 /* 0: data from camera interface to self resize */ +#define MRV_VI_DMA_SPMUX_DMA 1 /* 1: data from DMA read port to self resize */ +#endif /* MRV_VI_DMA_SPMUX */ + +/* Slice: vi_dma_iemux:*/ +/* 0: data from camera interface to image effects */ +/* 1: data from DMA read port to image effects */ +#ifdef MRV_VI_DMA_IEMUX +#define MRV_VI_DMA_IEMUX_CAM 0 /* 0: data from camera interface to image effects */ +#define MRV_VI_DMA_IEMUX_DMA 1 /* 1: data from DMA read port to image effects */ +#endif /* MRV_VI_DMA_IEMUX */ + +/* Slice: if_select:*/ +/* selects input interface */ +/* 0: parallel interface */ +/* 1: SMIA-interface */ +/* 2: MIPI-interface */ +#ifdef MRV_IF_SELECT +#define MRV_IF_SELECT_PAR 0 /* 0: parallel interface */ +#define MRV_IF_SELECT_SMIA 1 /* 1: SMIA-interface */ +#define MRV_IF_SELECT_MIPI 2 /* 2: MIPI-interface */ +#define MRV_IF_SELECT_HDR 3 /* 2: HDR-interface */ +#endif /* MRV_IF_SELECT */ + +/* Slice: vi_dma_switch:*/ +/* DMA read data path selector */ +/* 0: path to SPMUX */ +/* 1: path to Superimpose */ +/* 2: path to Image Effects */ +/* 3: reserved (for path to JPEG)*/ +/* 4..7: reserved */ +#ifdef MRV_VI_DMA_SWITCH +#define MRV_VI_DMA_SWITCH_SELF 0 /* 0: path to SPMUX */ +#define MRV_VI_DMA_SWITCH_SIMP 1 /* 1: path to Superimpose */ +#define MRV_VI_DMA_SWITCH_IE 2 /* 2: path to Image Effects */ +#define MRV_VI_DMA_SWITCH_JPG 3 /* 3: path to JPEG */ +#define MRV_VI_DMA_SWITCH_ISP 4 /* 4: path to ISP */ +#endif /* MRV_VI_DMA_SWITCH */ + +/* Slice: vi_chan_mode:*/ +/* Y/C splitter channel mode */ +/* 0: disabled */ +/* 1: main path and raw data mode */ +/* 2: self path mode */ +/* 3: main and self path mode */ +#ifdef MRV_VI_CHAN_MODE +#define MRV_VI_CHAN_MODE_OFF 0x00 /* 0: disabled */ +#define MRV_VI_CHAN_MODE_Y 0xFF /* not supported */ +#define MRV_VI_CHAN_MODE_MP_RAW 0x01 /* 1: main path and raw data mode */ +#define MRV_VI_CHAN_MODE_MP 0x01 /* 1: main path and raw data mode */ +#define MRV_VI_CHAN_MODE_SP 0x02 /* 2: self path mode */ +#define MRV_VI_CHAN_MODE_MP_SP 0x03 /* 3: main and self path mode */ +#define MRV_VI_CHAN_MODE_SP2 0x04 /* 4: self2 path mode */ +#define MRV_VI_CHAN_MODE_MP_SP2 0x05 /* 5: main and self2 path mode */ +#define MRV_VI_CHAN_MODE_SP_SP2 0x06 /* 6: self and self2 path mode */ +#define MRV_VI_CHAN_MODE_MP_SP_SP2 0x07 /* 7: main self and self2 path mode */ + +#endif /* MRV_VI_CHAN_MODE */ + +/* Slice: vi_mp_mux:*/ +/* data path selector for main path */ +/* 00: reserved (future: data from DMA read port to JPEG encoder)*/ +/* 01: data from main resize to MI, uncompressed */ +/* 10: data from main resize to JPEG encoder */ +/* 11: reserved */ +#ifdef MRV_VI_MP_MUX +#define MRV_VI_MP_MUX_JPGDIRECT 0x00 /* 00: reserved (future: data from DMA read port to JPEG encoder) */ +#define MRV_VI_MP_MUX_MP 0x01 /* 01: data from main resize to MI, uncompressed */ +#define MRV_VI_MP_MUX_RAW 0x01 /* (now also used for RAW data bypass) */ +#define MRV_VI_MP_MUX_JPEG 0x02 /* 10: data from main resize to JPEG encoder */ +#endif /* MRV_VI_MP_MUX */ + +/*****************************************************************************/ +/* Image Effects Registers */ +/*****************************************************************************/ + +/*****************************************************************************/ +/** + * register: img_eff_ctrl: Global control register (0x0000) + * + *****************************************************************************/ +/* Slice: full_range:*/ +/* write 0: pixel value range according to BT.601 */ +/* write 1: YCbCr full range 0...255 */ +#ifdef MRV_IMGEFF_FULL_RANGE +#define MRV_IMGEFF_FULL_RANGE_FULL 1 /* 1: YCbCr full range 0...255 */ +#define MRV_IMGEFF_FULL_RANGE_BT601 0 /* 0: pixel value range according to BT.601 */ +#endif /* MRV_IMGEFF_FULL_RANGE */ + +/* Slice: cfg_upd:*/ +/* write 0: nothing happens */ +/* write 1: update shadow registers */ +/* read: always 0 */ +#ifdef MRV_IMGEFF_CFG_UPD +#define MRV_IMGEFF_CFG_UPD_NOTHING 0 /* 0: nothing happens */ +#define MRV_IMGEFF_CFG_UPD_UPDATE 1 /* 1: update shadow registers */ +#endif /* MRV_IMGEFF_CFG_UPD */ + +/* Slice: effect_mode:*/ +/* effect mode */ +/* 000: black & white effect (grayscale)*/ +/* 001: negative effect */ +/* 010: sepia effect */ +/* 011: color selection effect */ +/* 100: emboss effect */ +/* 101: sketch effect */ +/* 110: sharpen effect */ +/* 111: reserved */ +#ifdef MRV_IMGEFF_EFFECT_MODE +#define MRV_IMGEFF_EFFECT_MODE_GRAY 0 /* 000: black & white effect (grayscale) */ +#define MRV_IMGEFF_EFFECT_MODE_NEGATIVE 1 /* 001: negative effect */ +#define MRV_IMGEFF_EFFECT_MODE_SEPIA 2 /* 010: sepia effect */ +#define MRV_IMGEFF_EFFECT_MODE_COLOR_SEL 3 /* 011: color selection effect */ +#define MRV_IMGEFF_EFFECT_MODE_EMBOSS 4 /* 100: emboss effect */ +#define MRV_IMGEFF_EFFECT_MODE_SKETCH 5 /* 101: sketch effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHARPEN 6 /* 110: sharpen effect */ +#endif /* MRV_IMGEFF_EFFECT_MODE */ + +/* Slice: bypass_mode:*/ +/* bypass mode */ +/* 1: processing is activated */ +/* 0: processing is deactivated, bypass mode is selected */ +#ifdef MRV_IMGEFF_BYPASS_MODE +#define MRV_IMGEFF_BYPASS_MODE_PROCESS 1 /* 1: processing is activated */ +#define MRV_IMGEFF_BYPASS_MODE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */ +#endif /* MRV_IMGEFF_BYPASS_MODE */ + +/*****************************************************************************/ +/** + * register: img_eff_color_sel: Color selection register (for + * color selection effect) (0x0004) + * + *****************************************************************************/ +/* Slice: color_threshold:*/ +/* Threshold value of the RGB colors for the color selection effect.*/ +#ifdef MRV_IMGEFF_COLOR_THRESHOLD +#endif /* MRV_IMGEFF_COLOR_THRESHOLD */ + +/* Slice: color_selection:*/ +/* Defining the maintained color:*/ +/* 000: red green and blue */ +/* 001: blue */ +/* 010: green */ +/* 011: green and blue */ +/* 100: red */ +/* 101: red and blue */ +/* 110: red and green */ +/* 111: red green and blue */ +#ifdef MRV_IMGEFF_COLOR_SELECTION +#define MRV_IMGEFF_COLOR_SELECTION_RGB 0 /* 000: red green and blue */ +#define MRV_IMGEFF_COLOR_SELECTION_B 1 /* 001: blue */ +#define MRV_IMGEFF_COLOR_SELECTION_G 2 /* 010: green */ +#define MRV_IMGEFF_COLOR_SELECTION_BG 3 /* 011: green and blue */ +#define MRV_IMGEFF_COLOR_SELECTION_R 4 /* 100: red */ +#define MRV_IMGEFF_COLOR_SELECTION_RB 5 /* 101: red and blue */ +#define MRV_IMGEFF_COLOR_SELECTION_RG 6 /* 110: red and green */ +#define MRV_IMGEFF_COLOR_SELECTION_BGR 7 /* 111: red green and blue */ +#endif /* MRV_IMGEFF_COLOR_SELECTION */ + +/* Slice: emb_coef_21_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_21_EN +#endif /* MRV_IMGEFF_EMB_COEF_21_EN */ + +/* Slice: emb_coef_21:*/ +/* second line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_21 +#define MRV_IMGEFF_EMB_COEF_21_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_21_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_21_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_21_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_21_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_21_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_21_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_21_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_21 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_21_4 +#define MRV_IMGEFF_EMB_COEF_21_4_MASK 0x0000F000 +#define MRV_IMGEFF_EMB_COEF_21_4_SHIFT 12 + +/* Slice: emb_coef_13_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_13_EN +#endif /* MRV_IMGEFF_EMB_COEF_13_EN */ + +/* Slice: emb_coef_13:*/ +/* first line, right entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_13 +#define MRV_IMGEFF_EMB_COEF_13_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_13_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_13_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_13_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_13_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_13_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_13_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_13_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_13 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_13_4 +#define MRV_IMGEFF_EMB_COEF_13_4_MASK 0x00000F00 +#define MRV_IMGEFF_EMB_COEF_13_4_SHIFT 8 + +/* Slice: emb_coef_12_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_12_EN +#endif /* MRV_IMGEFF_EMB_COEF_12_EN */ + +/* Slice: emb_coef_12:*/ +/* first line, middle entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_12 +#define MRV_IMGEFF_EMB_COEF_12_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_12_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_12_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_12_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_12_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_12_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_12_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_12_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_12 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_12_4 +#define MRV_IMGEFF_EMB_COEF_12_4_MASK 0x000000F0 +#define MRV_IMGEFF_EMB_COEF_12_4_SHIFT 4 + +/* Slice: emb_coef_11_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_11_EN +#define MRV_IMGEFF_EMB_COEF_11_EN_ON 1 +#define MRV_IMGEFF_EMB_COEF_11_EN_OFF 0 +#endif /* MRV_IMGEFF_EMB_COEF_11_EN */ + +/* Slice: emb_coef_11:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_11 +#define MRV_IMGEFF_EMB_COEF_11_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_11_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_11_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_11_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_11_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_11_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_11_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_11_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_11 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_11_4 +#define MRV_IMGEFF_EMB_COEF_11_4_MASK 0x0000000F +#define MRV_IMGEFF_EMB_COEF_11_4_SHIFT 0 + +/* Slice: emb_coef_32_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_32_EN +#endif /* MRV_IMGEFF_EMB_COEF_32_EN */ + +/* Slice: emb_coef_32:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_32 +#define MRV_IMGEFF_EMB_COEF_32_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_32_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_32_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_32_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_32_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_32_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_32_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_32_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_32 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_32_4 +#define MRV_IMGEFF_EMB_COEF_32_4_MASK 0x0000F000 +#define MRV_IMGEFF_EMB_COEF_32_4_SHIFT 12 + +/* Slice: emb_coef_31_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_31_EN +#endif /* MRV_IMGEFF_EMB_COEF_31_EN */ + +/* Slice: emb_coef_31:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_31 +#define MRV_IMGEFF_EMB_COEF_31_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_31_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_31_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_31_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_31_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_31_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_31_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_31_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_31 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_31_4 +#define MRV_IMGEFF_EMB_COEF_31_4_MASK 0x00000F00 +#define MRV_IMGEFF_EMB_COEF_31_4_SHIFT 8 + +/* Slice: emb_coef_23_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_23_EN +#endif /* MRV_IMGEFF_EMB_COEF_23_EN */ + +/* Slice: emb_coef_23:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_23 +#define MRV_IMGEFF_EMB_COEF_23_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_23_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_23_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_23_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_23_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_23_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_23_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_23_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_23 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_23_4 +#define MRV_IMGEFF_EMB_COEF_23_4_MASK 0x000000F0 +#define MRV_IMGEFF_EMB_COEF_23_4_SHIFT 4 + +/* Slice: emb_coef_22_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_22_EN +#endif /* MRV_IMGEFF_EMB_COEF_22_EN */ + +/* Slice: emb_coef_22:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_22 +#define MRV_IMGEFF_EMB_COEF_22_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_22_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_22_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_22_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_22_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_22_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_22_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_22_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_22 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_22_4 +#define MRV_IMGEFF_EMB_COEF_22_4_MASK 0x0000000F +#define MRV_IMGEFF_EMB_COEF_22_4_SHIFT 0 + +/*****************************************************************************/ +/** + * register: img_eff_mat_3: 3x3 matrix coefficients for emboss(3) effect / + * sketch(1) effect (0x0010) + * + *****************************************************************************/ +/* Slice: sket_coef_13_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_13_EN +#endif /* MRV_IMGEFF_SKET_COEF_13_EN */ + +/* Slice: sket_coef_13:*/ +/* first line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_13 +#define MRV_IMGEFF_SKET_COEF_13_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_13_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_13_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_13_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_13_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_13_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_13_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_13_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_13 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_13_4 +#define MRV_IMGEFF_SKET_COEF_13_4_MASK 0x0000F000 +#define MRV_IMGEFF_SKET_COEF_13_4_SHIFT 12 + +/* Slice: sket_coef_12_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_12_EN +#endif /* MRV_IMGEFF_SKET_COEF_13_EN */ + +/* Slice: sket_coef_12:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_12 +#define MRV_IMGEFF_SKET_COEF_12_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_12_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_12_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_12_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_12_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_12_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_12_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_12_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_12 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_12_4 +#define MRV_IMGEFF_SKET_COEF_12_4_MASK 0x00000F00 +#define MRV_IMGEFF_SKET_COEF_12_4_SHIFT 8 + +/* Slice: sket_coef_11_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_11_EN +#endif /* MRV_IMGEFF_SKET_COEF_13_EN */ + +/* Slice: sket_coef_11:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_11 +#define MRV_IMGEFF_SKET_COEF_11_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_11_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_11_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_11_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_11_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_11_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_11_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_11_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_11 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_11_4 +#define MRV_IMGEFF_SKET_COEF_11_4_MASK 0x000000F0 +#define MRV_IMGEFF_SKET_COEF_11_4_SHIFT 4 + +/* Slice: emb_coef_33_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_EMB_COEF_33_EN +#endif /* MRV_IMGEFF_EMB_COEF_33_EN */ + +/* Slice: emb_coef_33:*/ +/* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_EMB_COEF_3 +#define MRV_IMGEFF_EMB_COEF_33_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_EMB_COEF_33_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_EMB_COEF_33_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_EMB_COEF_33_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_EMB_COEF_33_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_EMB_COEF_33_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_EMB_COEF_33_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_EMB_COEF_33_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_EMB_COEF_33 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_EMB_COEF_33_4 +#define MRV_IMGEFF_EMB_COEF_33_4_MASK 0x0000000F +#define MRV_IMGEFF_EMB_COEF_33_4_SHIFT 0 + +/*****************************************************************************/ +/** + * register: img_eff_mat_4: 3x3 matrix coefficients for sketch effect (2) + * (0x0014) + * + *****************************************************************************/ +/* Slice: sket_coef_31_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_31_EN +#endif /* MRV_IMGEFF_SKET_COEF_31_EN */ + +/* Slice: sket_coef_31:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_31 +#define MRV_IMGEFF_SKET_COEF_31_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_31_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_31_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_31_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_31_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_31_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_31_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_31_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_31 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_31_4 +#define MRV_IMGEFF_SKET_COEF_31_4_MASK 0x0000F000 +#define MRV_IMGEFF_SKET_COEF_31_4_SHIFT 12 + +/* Slice: sket_coef_23_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_23_EN +#endif /* MRV_IMGEFF_SKET_COEF_23_EN */ + +/* Slice: sket_coef_23:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_23 +#define MRV_IMGEFF_SKET_COEF_23_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_23_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_23_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_23_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_23_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_23_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_23_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_23_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_23 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_23_4 +#define MRV_IMGEFF_SKET_COEF_23_4_MASK 0x00000F00 +#define MRV_IMGEFF_SKET_COEF_23_4_SHIFT 8 + +/* Slice: sket_coef_22_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_22_EN +#endif /* MRV_IMGEFF_SKET_COEF_22_EN */ + +/* Slice: sket_coef_22:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_22 +#define MRV_IMGEFF_SKET_COEF_22_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_22_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_22_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_22_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_22_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_22_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_22_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_22_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_22 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_22_4 +#define MRV_IMGEFF_SKET_COEF_22_4_MASK 0x000000F0 +#define MRV_IMGEFF_SKET_COEF_22_4_SHIFT 4 + +/* Slice: sket_coef_21_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_21_EN +#endif /* MRV_IMGEFF_SKET_COEF_21_EN */ + +/* Slice: sket_coef_21:*/ +/* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_21 +#define MRV_IMGEFF_SKET_COEF_21_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_21_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_21_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_21_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_21_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_21_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_21_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_21_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_21 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_21_4 +#define MRV_IMGEFF_SKET_COEF_21_4_MASK 0x0000000F +#define MRV_IMGEFF_SKET_COEF_21_4_SHIFT 0 + +/*****************************************************************************/ +/** + * register: img_eff_mat_5: 3x3 matrix coefficients for sketch effect (3) + * (0x0018) + * + *****************************************************************************/ +/* Slice: sket_coef_33_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_33_EN +#endif /* MRV_IMGEFF_SKET_COEF_33_EN */ + +/* Slice: sket_coef_33:*/ +/* third line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_33 +#define MRV_IMGEFF_SKET_COEF_33_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_33_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_33_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_33_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_33_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_33_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_33_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_33_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_33 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_33_4 +#define MRV_IMGEFF_SKET_COEF_33_4_MASK 0x000000F0 +#define MRV_IMGEFF_SKET_COEF_33_4_SHIFT 4 + +/* Slice: sket_coef_32_en:*/ +/* 0: entry not used (coefficient is zero)*/ +/* 1: entry used */ +#ifdef MRV_IMGEFF_SKET_COEF_32_EN +#endif /* MRV_IMGEFF_SKET_COEF_32_EN */ + +/* Slice: sket_coef_32:*/ +/* third line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/ +/* coefficients:*/ +/* 000 (1), 001(2), 010(4), 011(8)*/ +/* 100 (-1), 101(-2), 110(-4), 111(-8)*/ +#ifdef MRV_IMGEFF_SKET_COEF_32 +#define MRV_IMGEFF_SKET_COEF_32_ONE 0 /* 000 (1) */ +#define MRV_IMGEFF_SKET_COEF_32_TWO 1 /* 001 (2) */ +#define MRV_IMGEFF_SKET_COEF_32_FOUR 2 /* 010 (4) */ +#define MRV_IMGEFF_SKET_COEF_32_EIGHT 3 /* 011 (8) */ +#define MRV_IMGEFF_SKET_COEF_32_MIN_ONE 4 /* 100 (-1) */ +#define MRV_IMGEFF_SKET_COEF_32_MIN_TWO 5 /* 101 (-2) */ +#define MRV_IMGEFF_SKET_COEF_32_MIN_FOUR 6 /* 110 (-4) */ +#define MRV_IMGEFF_SKET_COEF_32_MIN_EIGHT 8 /* 111 (-8) */ +#endif /* MRV_IMGEFF_SKET_COEF_32 */ + +/* combination of value and enable bit */ +#define MRV_IMGEFF_SKET_COEF_32_4 +#define MRV_IMGEFF_SKET_COEF_32_4_MASK 0x0000000F +#define MRV_IMGEFF_SKET_COEF_32_4_SHIFT 0 + +/* valid for all coeffiecient definitions */ +#define MRV_IMGEFF_COEF +#define MRV_IMGEFF_COEF_ONE 0U +#define MRV_IMGEFF_COEF_TWO 1U /* 001: (2) */ +#define MRV_IMGEFF_COEF_FOUR 2U /* 010: (4) */ +#define MRV_IMGEFF_COEF_EIGHT 3U /* 011: (8) */ +#define MRV_IMGEFF_COEF_MIN_ONE 4U /* 100: (-1) */ +#define MRV_IMGEFF_COEF_MIN_TWO 5U /* 101: (-2) */ +#define MRV_IMGEFF_COEF_MIN_FOUR 6U /* 110: (-4) */ +#define MRV_IMGEFF_COEF_MIN_EIGHT 7U /* 111: (-8) */ + +#define MRV_IMGEFF_COEF_ON 1U /* 1: coefficient enabled */ +#define MRV_IMGEFF_COEF_OFF 0U /* 0: coefficient disabled */ +#define MRV_IMGEFF_COEF_SHIFT 3U /* shift for enable bit */ + +/*****************************************************************************/ +/** + * register: img_eff_tint: Chrominance increment values of a tint + * (used for sepia effect) (0x001c) + * + *****************************************************************************/ +/* Slice: incr_cr:*/ +/* Cr increment value of a tint. 7 bits for value, 1 sign bit.*/ +/* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/ +#ifdef MRV_IMGEFF_INCR_CR +#endif /* MRV_IMGEFF_INCR_CR */ + +/* Slice: incr_cb:*/ +/* Cb increment value of a tint. 7 bits for value, 1 sign bit.*/ +/* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/ +#ifdef MRV_IMGEFF_INCR_CB +#endif /* MRV_IMGEFF_INCR_CB */ + +/*****************************************************************************/ +/** + * register: img_eff_ctrl_shd: Shadow register for control register (0x0020) + * + *****************************************************************************/ +/* Slice: effect_mode_shd:*/ +/* effect mode */ +/* 000: black & white effect (grayscale)*/ +/* 001: negative effect */ +/* 010: sepia effect */ +/* 011: color selection effect */ +/* 100: emboss effect */ +/* 101: sketch effect */ +/* 110-111: not used */ +#ifdef MRV_IMGEFF_EFFECT_MODE_SHD +#define MRV_IMGEFF_EFFECT_MODE_SHD_GRAY 0 /* 000: black & white effect (grayscale) */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_NEGATIVE 1 /* 001: negative effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_SEPIA 2 /* 010: sepia effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_COLOR_SEL 3 /* 011: color selection effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_EMBOSS 4 /* 100: emboss effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_SKETCH 5 /* 101: sketch effect */ +#define MRV_IMGEFF_EFFECT_MODE_SHD_SHARPEN 6 /* 110: sharpen effect */ +#endif /* MRV_IMGEFF_EFFECT_MODE_SHD */ + +/*****************************************************************************/ +/* Super Impose Registers */ +/*****************************************************************************/ + +/*****************************************************************************/ +/** + * register: super_imp_ctrl: Global control register (0x0000) + * + *****************************************************************************/ +/* Slice: transparency_mode:*/ +/* transparency mode */ +/* 1: transparency mode disabled */ +/* 0: transparency mode enabled */ +#ifdef MRV_SI_TRANSPARENCY_MODE +#define MRV_SI_TRANSPARENCY_MODE_DISABLED 1 /* 1: transparency mode disabled */ +#define MRV_SI_TRANSPARENCY_MODE_ENABLED 0 /* 0: transparency mode enabled */ +#endif /* MRV_SI_TRANSPARENCY_MODE */ + +/* Slice: ref_image:*/ +/* Define the reference image */ +/* 1: superimpose bitmap from main memory */ +/* 0: image from the Image Effect module */ +/* Note: the reference image defines the size of the output image */ +#ifdef MRV_SI_REF_IMAGE +#define MRV_SI_REF_IMAGE_MEM 1 /* 1: superimpose bitmap from main memory */ +#define MRV_SI_REF_IMAGE_IE 0 /* 0: image from the Image Effect module */ +#endif /* MRV_SI_REF_IMAGE */ + +/* Slice: bypass_mode:*/ +/* bypass mode */ +/* 1: processing is activated */ +/* 0: processing is deactivated, bypass mode is selected */ +#ifdef MRV_SI_BYPASS_MODE +#define MRV_SI_BYPASS_MODE_PROCESS 1 /* 1: processing is activated */ +#define MRV_SI_BYPASS_MODE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */ +#endif /* MRV_IMGEFF_BYPASS_MODE */ + +/*****************************************************************************/ +/** + * register: super_imp_offset_x: Offset x register (0x0004) + * + *****************************************************************************/ +/* Slice: offset_x:*/ +/* Offset X */ +/* Note: the bit 0 is don't care (write 1 doesn't have any effect, the read access always gives 0)*/ +/* Note: the offset_x is positive and refers to the reference image */ +#ifdef MRV_SI_OFFSET_X +#endif /* MRV_SI_OFFSET_X */ + +/*****************************************************************************/ +/** + * register: super_imp_offset_y: Offset y register (0x0008) + * + *****************************************************************************/ +/* Slice: offset_y:*/ +/* Offset Y */ +/* Note: the offset_y is positive and refers to the reference image */ +#ifdef MRV_SI_OFFSET_Y +#endif /* MRV_SI_OFFSET_Y */ + +/*****************************************************************************/ +/** + * register: super_imp_color_y: Y component of transparent key color (0x000c) + * + *****************************************************************************/ +/* Slice: y_comp:*/ +/* Y component of transparent key color */ +#ifdef MRV_SI_Y_COMP +#endif /* MRV_SI_Y_COMP */ + +/*****************************************************************************/ +/** + * register: super_imp_color_cb: Cb component of transparent key color (0x0010) + * + *****************************************************************************/ +/* Slice: cb_comp:*/ +/* Cb component of transparent key color */ +#ifdef MRV_SI_CB_COMP +#endif /* MRV_SI_CB_COMP */ + +/*****************************************************************************/ +/** + * register: super_imp_color_cr: Cr component of transparent key color (0x0014) + * + *****************************************************************************/ +/* Slice: cr_comp:*/ +/* Cr component of transparent key color */ +#ifdef MRV_SI_CR_COMP +#endif /* MRV_SI_CR_COMP */ + +/*****************************************************************************/ +/* ISP Registers */ +/*****************************************************************************/ + +/*****************************************************************************/ +/** + * register: isp_ctrl: global control register (0x0000) + * + *****************************************************************************/ +/* Slice: ISP_DPF_RAW_OUT */ +/*! Slice MRV_ISP_DPF_RAW_OUT:*/ +/*! 0: DPF RAW OUT is disable */ +/*! 1: DPF RAW OUT is enable */ +#ifdef ISP_DPF_RAW +#ifdef MRV_ISP_DPF_RAW_OUT +#define MRV_ISP_DPF_RAW_OUT_DISABLE 0 /* 0: DPF raw out is disable */ +#define MRV_ISP_DPF_RAW_OUT_ENABLE 1 /* 1: DPF raw out is enable */ +#endif +#endif +/* Slice: ISP_CSM_C_RANGE:*/ +/* Color Space Matrix chrominance clipping range for ISP output */ +/* 0: CbCr range 64..960 (16..240) according to ITU-R BT.601 standard */ +/* 1: full UV range 0..1023 (0..255)*/ +/* Numbers in brackets are for 8 bit resolution.*/ +#ifdef MRV_ISP_ISP_CSM_C_RANGE +#define MRV_ISP_ISP_CSM_C_RANGE_BT601 0 /* 0: CbCr range 64..960 (16..240) according to ITU-R BT.601 standard */ +#define MRV_ISP_ISP_CSM_C_RANGE_FULL 1 /* 1: full UV range 0..1023 (0..255) */ +#endif /* MRV_ISP_ISP_CSM_C_RANGE */ + +/* Slice: ISP_CSM_Y_RANGE:*/ +/* Color Space Matrix luminance clipping range for ISP output */ +/* 0: Y range 64..940 (16..235) according to ITU-R BT.601 standard */ +/* 1: full Y range 0..1023 (0..255)*/ +/* Numbers in brackets are for 8 bit resolution.*/ +#ifdef MRV_ISP_ISP_CSM_Y_RANGE +#define MRV_ISP_ISP_CSM_Y_RANGE_BT601 0 /* 0: Y range 64..940 (16..235) according to ITU-R BT.601 standard */ +#define MRV_ISP_ISP_CSM_Y_RANGE_FULL 1 /* 1: full Y range 0..1023 (0..255) */ +#endif /* MRV_ISP_ISP_CSM_Y_RANGE */ + +/* Slice: ISP_FLASH_MODE:*/ +/* 0: sensor interface works independently from flash control unit */ +/* 1: one frame is captured when signaled by flash control unit */ +#ifdef MRV_ISP_ISP_FLASH_MODE +#define MRV_ISP_ISP_FLASH_MODE_INDEP 0 /* 0: sensor interface works independently from flash control unit */ +#define MRV_ISP_ISP_FLASH_MODE_SYNC 1 /* 1: one frame is captured when signaled by flash control unit */ +#endif /* MRV_ISP_ISP_FLASH_MODE */ + +/* Slice: ISP_GAMMA_OUT_ENABLE:*/ +/* gamma ON/OFF */ +#ifdef MRV_ISP_ISP_GAMMA_OUT_ENABLE +#endif /* MRV_ISP_ISP_GAMMA_OUT_ENABLE */ + +/* Slice: ISP_GEN_CFG_UPD:*/ +/* generate vsynced config shadow signal at the output, write only */ +#ifdef MRV_ISP_ISP_GEN_CFG_UPD +#endif /* MRV_ISP_ISP_GEN_CFG_UPD */ + +/* Slice: ISP_CFG_UPD:*/ +/* immediate configure internal shadow registers, write only */ +#ifdef MRV_ISP_ISP_CFG_UPD +#endif /* MRV_ISP_ISP_CFG_UPD */ + +/* Slice: ISP_AE_ENABLE:*/ +/* auto exposure ON/OFF */ +#ifdef MRV_ISP_ISP_AE_ENABLE +#endif /* MRV_ISP_ISP_AE_ENABLE */ + +/* Slice: ISP_AWB_ENABLE:*/ +/* auto white balance ON/OFF */ +#ifdef MRV_ISP_ISP_AWB_ENABLE +#endif /* MRV_ISP_ISP_AWB_ENABLE */ + +/* Slice: ISP_GAMMA_IN_ENABLE:*/ +/* Sensor De-gamma ON/OFF */ +#ifdef MRV_ISP_ISP_GAMMA_IN_ENABLE +#define MRV_ISP_ISP_GAMMA_IN_ENABLE_ON 1U +#define MRV_ISP_ISP_GAMMA_IN_ENABLE_OFF 0U +#endif /* MRV_ISP_ISP_GAMMA_IN_ENABLE */ + +/* Slice: ISP_INFORM_ENABLE:*/ +/* input block ON/OFF (frame-synced on)*/ +#ifdef MRV_ISP_ISP_INFORM_ENABLE +#endif /* MRV_ISP_ISP_INFORM_ENABLE */ + +/* Slice: ISP_MODE:*/ +/* 000: RAW picture with BT.601 sync (ISP bypass)*/ +/* 001: ITU-R BT.656 (YUV with embedded sync)*/ +/* 010: ITU-R BT.601 (YUV input with H and Vsync signals)*/ +/* 011: Bayer RGB processing with H and Vsync signals */ +/* 100: data mode (ISP bypass, sync signals interpreted as data enable)*/ +/* 101: Bayer RGB processing with BT.656 synchronization */ +/* 110: RAW picture with ITU-R BT.656 synchronization (ISP bypass)*/ +/* 111: reserved */ + /**/ +/* Side effect:*/ +/* If RAW, BT.601, BT.656, or data mode is selected, the clock of the */ +/* ISP SRAMs (ISP line buffer, Lens Shading, Bad Pixel) is switched off.*/ +/* Only in Bayer RGB mode the clock to the SRAMs is enabled. This */ +/* further reduces power consumption.*/ +#ifdef MRV_ISP_ISP_MODE +#define MRV_ISP_ISP_MODE_RAW 0 /* 000 - RAW picture with BT.601 sync (ISP bypass) */ +#define MRV_ISP_ISP_MODE_656 1 /* 001 - ITU-R BT.656 (YUV with embedded sync) */ +#define MRV_ISP_ISP_MODE_601 2 /* 010 - ITU-R BT.601 (YUV input with H and Vsync signals) */ +#define MRV_ISP_ISP_MODE_RGB 3 /* 011 - Bayer RGB processing with H and Vsync signals */ +#define MRV_ISP_ISP_MODE_DATA 4 /* 100 - data mode (ISP bypass, sync signals interpreted as data enable) */ +#define MRV_ISP_ISP_MODE_RGB656 5 /* 101 - Bayer RGB processing with BT.656 synchronization */ +#define MRV_ISP_ISP_MODE_RAW656 6 /* 110 - RAW picture with ITU-R BT.656 synchronization (ISP bypass) */ +#endif /* MRV_ISP_ISP_MODE */ +/* Slice: ISP_ENABLE:*/ +/* MANUAL ON/OFF (controls output formatter, framesynced)*/ +#ifdef MRV_ISP_ISP_ENABLE +#endif /* MRV_ISP_ISP_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_acq_prop: ISP acquisition properties (0x0004) + * + *****************************************************************************/ +#ifdef ISP_DVP_PINMAPPING +/*! Slice: MRV_ISP_DVP_INPUT_PIN_MAPPING */ +/*! Bit Mapping for LSB to MSP for ISPNano.*/ +/*! 3'b000: normal 12-bit external interface */ +/*! 3'b001: mapping low 10 bit to high 10 bits, append 2 zeros as LSBs.*/ +/*! 3'b010: mapping low 8 bit to high 8 bits, append 4 zeros as LSBs.*/ +/*! 3'b011: mapping middle 8 bit to high 8 bits, append 4 zeros as LSBs.*/ +/*! 3'b100..3'b111: rsvd */ +#ifdef MRV_ISP_DVP_INPUT_PIN_MAPPING +#define MRV_ISP_DVP_INPUT_PIN_MAPPING_12TO12 0 +#define MRV_ISP_DVP_INPUT_PIN_MAPPING_L10TOH10 1 +#define MRV_ISP_DVP_INPUT_PIN_MAPPING_L8TOH8 2 +#define MRV_ISP_DVP_INPUT_PIN_MAPPING_M8TOH8 3 +#endif +#endif +/*! Slice: DMA_YUV_SELECTION */ +/*! 0: use align or conversion data for isp_is input */ +/*! 1: use dma yuv read data for isp_is input */ +#ifdef MRV_ISP_DMA_YUV_SELECTION +#define MRV_ISP_DMA_YUV_SELECTION_ALIGNED_CONV 0 +#define MRV_ISP_DMA_YUV_SELECTION_DMA_YUV 1 +#endif +/* Slice: LATENCY_FIFO_SELECTION:*/ +/* 0: use input formatter input for latency fifo.*/ +/* 1: use dma rgb read input for latency fifo.*/ +#ifdef MRV_ISP_LATENCY_FIFO_SELECTION +#define MRV_ISP_LATENCY_FIFO_SELECTION_INPUT_FORMATTER 0 +#define MRV_ISP_LATENCY_FIFO_SELECTION_DMA_READ 1 +#endif /* MRV_ISP_LATENCY_FIFO_SELECTION */ +/* Slice: INPUT_SELECTION:*/ +/* 000: 12Bit external Interface */ +/* 001: 10Bit Interface, append 2 zeroes as LSBs */ +/* 010: 10Bit Interface, append 2 MSBs as LSBs */ +/* 011: 8Bit Interface, append 4 zeroes as LSBs */ +/* 100: 8Bit Interface, append 4 MSBs as LSBs */ +/* 101...111: reserved */ +#ifdef MRV_ISP_INPUT_SELECTION +#define MRV_ISP_INPUT_SELECTION_12EXT 0 /* 000- 12Bit external Interface */ +#define MRV_ISP_INPUT_SELECTION_10ZERO 1 /* 001- 10Bit Interface, append 2 zeroes as LSBs */ +#define MRV_ISP_INPUT_SELECTION_10MSB 2 /* 010- 10Bit Interface, append 2 MSBs as LSBs */ +#define MRV_ISP_INPUT_SELECTION_8ZERO 3 /* 011- 8Bit Interface, append 4 zeroes as LSBs */ +#define MRV_ISP_INPUT_SELECTION_8MSB 4 /* 100- 8Bit Interface, append 4 MSBs as LSBs */ +#endif /* MRV_ISP_INPUT_SELECTION */ +/* Slice: FIELD_SELECTION:*/ +/* 00: sample all fields (don't care about fields)*/ +/* 01: sample only even fields */ +/* 10: sample only odd fields */ +/* 11: reserved */ +#ifdef MRV_ISP_FIELD_SELECTION +#define MRV_ISP_FIELD_SELECTION_BOTH 0 /* 00- sample all fields (don't care about fields) */ +#define MRV_ISP_FIELD_SELECTION_EVEN 1 /* 01- sample only even fields */ +#define MRV_ISP_FIELD_SELECTION_ODD 2 /* 10- sample only odd fields */ +#endif /* MRV_ISP_FIELD_SELECTION */ +/* Slice: CCIR_SEQ:*/ +/* 00: YCbYCr */ +/* 01: YCrYCb */ +/* 10: CbYCrY */ +/* 11: CrYCbY */ +#ifdef MRV_ISP_CCIR_SEQ +#define MRV_ISP_CCIR_SEQ_YCBYCR 0 /* 00 - YCbYCr */ +#define MRV_ISP_CCIR_SEQ_YCRYCB 1 /* 01 - YCrYCb */ +#define MRV_ISP_CCIR_SEQ_CBYCRY 2 /* 10 - CbYCrY */ +#define MRV_ISP_CCIR_SEQ_CRYCBY 3 /* 11 - CrYCbY */ +#endif /* MRV_ISP_CCIR_SEQ */ +/* Slice: CONV_422:*/ +/* 00- co-sited color subsampling Y0Cb0Cr0 - Y1 */ +/* 01- interleaved color subsampling Y0Cb0 - Y1Cr1 (not recommended)*/ +/* 10- non-cosited color subsampling Y0Cb(0+1)/2 - Y1Cr(0+1)/2 */ +/* 11- reserved */ +#ifdef MRV_ISP_CONV_422 +#define MRV_ISP_CONV_422_CO 0 /* 00- co-sited color subsampling Y0Cb0Cr0 - Y1 */ +#define MRV_ISP_CONV_422_INTER 1 /* 01- interleaved color subsampling Y0Cb0 - Y1Cr1 (not recommended) */ +#define MRV_ISP_CONV_422_NONCO 2 /* 10- non-cosited color subsampling Y0Cb(0+1)/2 - Y1Cr(0+1)/2 */ +#endif /* MRV_ISP_CONV_422 */ +/* Slice: BAYER_PAT:*/ +/* color components from sensor, starting with top left position in sampled frame */ +/* (reprogram with ISP_ACQ_H_OFFS, ISP_ACQ_V_OFFS)*/ + /**/ +/* 00: first line: RGRG, second line: GBGB, etc.*/ +/* 01: first line: GRGR, second line: BGBG, etc.*/ +/* 10: first line: GBGB, second line: RGRG, etc.*/ +/* 11: first line: BGBG, second line: GRGR, etc.*/ +/* This configuration applies for the black level area after cropping by the input formatter.*/ +#ifdef MRV_ISP_BAYER_PAT +#define MRV_ISP_BAYER_PAT_RG 0 /* 00 - first line: RGRG, second line: GBGB, etc. */ +#define MRV_ISP_BAYER_PAT_GR 1 /* 01 - first line: GRGR, second line: BGBG, etc. */ +#define MRV_ISP_BAYER_PAT_GB 2 /* 10 - first line: GBGB, second line: RGRG, etc. */ +#define MRV_ISP_BAYER_PAT_BG 3 /* 11 - first line: BGBG, second line: GRGR, etc. */ +#endif /* MRV_ISP_BAYER_PAT */ +/* Slice: VSYNC_POL:*/ +/* vertical sync polarity */ +/* 0: high active */ +/* 1: low active */ +#ifdef MRV_ISP_VSYNC_POL +#endif /* MRV_ISP_VSYNC_POL */ +/* Slice: HSYNC_POL:*/ +/* horizontal sync polarity */ +/* 0: high active */ +/* 1: low active */ +#ifdef MRV_ISP_HSYNC_POL +#endif /* MRV_ISP_HSYNC_POL */ +/* Slice: SAMPLE_EDGE:*/ +/* 0: negative edge sampling */ +/* 1: positive edge sampling */ +#ifdef MRV_ISP_SAMPLE_EDGE +#endif /* MRV_ISP_SAMPLE_EDGE */ +/*****************************************************************************/ +/** + * register: isp_acq_h_offs: horizontal input offset (0x0008) + * + *****************************************************************************/ +/* Slice: ACQ_H_OFFS:*/ +/* horizontal sample offset in 8-bit samples (yuv: 4 samples=2pix)*/ +#ifdef MRV_ISP_ACQ_H_OFFS +#endif /* MRV_ISP_ACQ_H_OFFS */ +/*****************************************************************************/ +/** + * register: isp_acq_v_offs: vertical input offset (0x000c) + * + *****************************************************************************/ +/* Slice: ACQ_V_OFFS:*/ +/* vertical sample offset in lines */ +#ifdef MRV_ISP_ACQ_V_OFFS +#endif /* MRV_ISP_ACQ_V_OFFS */ +/*****************************************************************************/ +/** + * register: isp_acq_h_size: horizontal input size (0x0010) + * + *****************************************************************************/ +/* Slice: ACQ_H_SIZE:*/ +/* horizontal sample size in 12-bit samples */ +/* YUV input: 2 samples = 1 pixel, else 1 sample = 1 pixel; So in YUV mode ACQ_H_SIZE must be twice as large as horizontal image size */ +/* horizontal image size must always be even exept in raw picture mode; if an odd size is programmed the value will be truncated to even size */ +#ifdef MRV_ISP_ACQ_H_SIZE +#endif /* MRV_ISP_ACQ_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_acq_v_size: vertical input size (0x0014) + * + *****************************************************************************/ +/* Slice: ACQ_V_SIZE:*/ +/* vertical sample size in lines */ +#ifdef MRV_ISP_ACQ_V_SIZE +#endif /* MRV_ISP_ACQ_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_acq_nr_frames: Number of frames to be captured (0x0018) + * + *****************************************************************************/ +/* Slice: ACQ_NR_FRAMES:*/ +/* number of input frames to be sampled (0 = continuous)*/ +#ifdef MRV_ISP_ACQ_NR_FRAMES +#endif /* MRV_ISP_ACQ_NR_FRAMES */ +/*****************************************************************************/ +/** + * register: isp_gamma_dx_lo: De-Gamma Curve definition lower x increments + * (sampling points) (0x001c) + * + *****************************************************************************/ +/* Slice: GAMMA_DX_8:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_8 +#endif /* MRV_ISP_GAMMA_DX_8 */ +/* Slice: GAMMA_DX_7:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_7 +#endif /* MRV_ISP_GAMMA_DX_7 */ +/* Slice: GAMMA_DX_6:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_6 +#endif /* MRV_ISP_GAMMA_DX_6 */ +/* Slice: GAMMA_DX_5:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_5 +#endif /* MRV_ISP_GAMMA_DX_5 */ +/* Slice: GAMMA_DX_4:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_4 +#endif /* MRV_ISP_GAMMA_DX_4 */ +/* Slice: GAMMA_DX_3:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_3 +#endif /* MRV_ISP_GAMMA_DX_3 */ +/* Slice: GAMMA_DX_2:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_2 +#endif /* MRV_ISP_GAMMA_DX_2 */ +/* Slice: GAMMA_DX_1:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_1 +#endif /* MRV_ISP_GAMMA_DX_1 */ +/*****************************************************************************/ +/** + * register: isp_gamma_dx_hi: De-Gamma Curve definition higher x increments + * (sampling points) (0x0020) + * + *****************************************************************************/ +/* Slice: GAMMA_DX_16:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_16 +#endif /* MRV_ISP_GAMMA_DX_16 */ +/* Slice: GAMMA_DX_15:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_15 +#endif /* MRV_ISP_GAMMA_DX_15 */ +/* Slice: GAMMA_DX_14:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_14 +#endif /* MRV_ISP_GAMMA_DX_14 */ +/* Slice: GAMMA_DX_13:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_13 +#endif /* MRV_ISP_GAMMA_DX_13 */ +/* Slice: GAMMA_DX_12:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_12 +#endif /* MRV_ISP_GAMMA_DX_12 */ +/* Slice: GAMMA_DX_11:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_11 +#endif /* MRV_ISP_GAMMA_DX_11 */ +/* Slice: GAMMA_DX_10:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_10 +#endif /* MRV_ISP_GAMMA_DX_10 */ +/* Slice: GAMMA_DX_9:*/ +/* gamma curve sample point definition x-axis (input)*/ +#ifdef MRV_ISP_GAMMA_DX_9 +#endif /* MRV_ISP_GAMMA_DX_9 */ +/*****************************************************************************/ +/** + * register array: isp_gamma_r_y: De-Gamma Curve definition y red (0x0024+n (n=0..16)) + * + *****************************************************************************/ +/* Slice: GAMMA_R_Y:*/ +/* gamma curve point definition y-axis (output) for red */ +/* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/ +#ifdef MRV_ISP_GAMMA_R_Y +#endif /* MRV_ISP_GAMMA_R_Y */ +/*****************************************************************************/ +/** + * register array: isp_gamma_g_y: De-Gamma Curve definition y green (0x0068+n (n=0..16)) + * + *****************************************************************************/ +/* Slice: GAMMA_G_Y:*/ +/* gamma curve point definition y-axis (output) for green */ +/* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/ +#ifdef MRV_ISP_GAMMA_G_Y +#endif /* MRV_ISP_GAMMA_G_Y */ +/*****************************************************************************/ +/** + * register array: isp_gamma_b_y: De-Gamma Curve definition y blue (0x00AC+n (n=0..16)) + * + *****************************************************************************/ +/* Slice: GAMMA_B_Y:*/ +/* gamma curve point definition y-axis (output) for blue */ +/* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/ +#ifdef MRV_ISP_GAMMA_B_Y +#endif /* MRV_ISP_GAMMA_B_Y */ +/*****************************************************************************/ +/* ISP Auto White Balance Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_awb_prop: Auto white balance properties (0x0110) + * + *****************************************************************************/ +/* Slice: AWB_MEAS_MODE:*/ +/* 1: RGB based measurement mode */ +/* 0: near white discrimination mode using YCbCr color space */ +#ifdef MRV_ISP_AWB_MEAS_MODE +#define MRV_ISP_AWB_MEAS_MODE_RGB 1U /* 1: RGB based measurement mode */ +#define MRV_ISP_AWB_MEAS_MODE_YCBCR 0U /* 0: near white discrimination mode using YCbCr color space */ +#endif /* MRV_ISP_AWB_MEAS_MODE */ +/* Slice: AWB_MAX_EN:*/ +/* 1: enable Y_MAX compare */ +/* 0: disable Y_MAX compare */ +/* ignored if RGB measurement mode is enabled */ +#ifdef MRV_ISP_AWB_MAX_EN +#define MRV_ISP_AWB_MAX_EN_ENABLE 1U /* 1: enable Y_MAX compare */ +#define MRV_ISP_AWB_MAX_EN_DISABLE 0U /* 0: disable Y_MAX compare */ +#endif /* MRV_ISP_AWB_MAX_EN */ +/* Slice: AWB_MODE:*/ +/* AWB_MODE(1:0):*/ +/* 11: reserved */ +/* 10: white balance measurement of YCbCr means */ +/* 01: reserved */ +/* 00: manual white balance (gain adjust possible), no measurement */ +#ifdef MRV_ISP_AWB_MODE +#define MRV_ISP_AWB_MODE_MEAS 2U /* 10: white balance measurement of YCbCr or RGB means (dependent on MRV_ISP_AWB_MEAS_MODE) */ +#define MRV_ISP_AWB_MODE_NOMEAS 0U /* 00: manual white balance (gain adjust possible), no measurement */ +#endif /* MRV_ISP_AWB_MODE */ +/*****************************************************************************/ +/** + * register: isp_awb_h_offs: Auto white balance horizontal offset of measure + * window (0x0114) + * + *****************************************************************************/ +/* Slice: AWB_H_OFFS:*/ +/* horizontal window offset in pixel */ +#ifdef MRV_ISP_AWB_H_OFFS +#define MRV_ISP_AWB_H_OFFS_MIN 0U +#define MRV_ISP_AWB_H_OFFS_MAX (MRV_ISP_AWB_H_OFFS_MASK >> MRV_ISP_AWB_H_OFFS_SHIFT) +#endif /* MRV_ISP_AWB_H_OFFS */ +/*****************************************************************************/ +/** + * register: isp_awb_v_offs: Auto white balance vertical offset of measure + * window (0x0118) + * + *****************************************************************************/ +/* Slice: AWB_V_OFFS:*/ +/* vertical window offset in lines */ +#ifdef MRV_ISP_AWB_V_OFFS +#define MRV_ISP_AWB_V_OFFS_MIN 0U +#define MRV_ISP_AWB_V_OFFS_MAX (MRV_ISP_AWB_V_OFFS_MASK >> MRV_ISP_AWB_V_OFFS_SHIFT) +#endif /* MRV_ISP_AWB_V_OFFS */ +/*****************************************************************************/ +/** + * register: isp_awb_h_size: Auto white balance horizontal window size (0x011c) + * + *****************************************************************************/ +/* Slice: AWB_H_SIZE:*/ +/* horizontal measurement window size in pixel */ +#ifdef MRV_ISP_AWB_H_SIZE +#define MRV_ISP_AWB_H_SIZE_MIN 0U +#define MRV_ISP_AWB_H_SIZE_MAX (MRV_ISP_AWB_H_SIZE_MASK >> MRV_ISP_AWB_H_SIZE_SHIFT) +#endif /* MRV_ISP_AWB_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_awb_v_size: Auto white balance vertical window size (0x0120) + * + *****************************************************************************/ +/* Slice: AWB_V_SIZE:*/ +/* vertical measurement window size in lines */ +#ifdef MRV_ISP_AWB_V_SIZE +#define MRV_ISP_AWB_V_SIZE_MIN 0U +#define MRV_ISP_AWB_V_SIZE_MAX (MRV_ISP_AWB_V_SIZE_MASK >> MRV_ISP_AWB_V_SIZE_SHIFT) +#endif /* MRV_ISP_AWB_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_awb_frames: Auto white balance mean value over multiple frames (0x0124) + * + *****************************************************************************/ +/* Slice: AWB_FRAMES:*/ +/* number of frames-1 used for mean value calculation (value of 0 means 1 frame, value of 7 means 8 frames)*/ +#ifdef MRV_ISP_AWB_FRAMES +#endif /* MRV_ISP_AWB_FRAMES */ +/*****************************************************************************/ +/** + * register: isp_awb_ref: Auto white balance reference Cb/Cr values (0x0128) + * or maximum red/blue values + * + *****************************************************************************/ +/* Slice: AWB_REF_CR__MAX_R:*/ +/* - reference Cr value for AWB regulation, target for AWB */ +/* - maximum red value, if RGB measurement mode is selected */ +#ifdef MRV_ISP_AWB_REF_CR__MAX_R +#endif /* MRV_ISP_AWB_REF_CR__MAX_R */ +/* Slice: AWB_REF_CB__MAX_B:*/ +/* - reference Cb value for AWB regulation, target for AWB */ +/* - maximum blue value, if RGB measurement mode is selected */ +#ifdef MRV_ISP_AWB_REF_CB__MAX_B +#endif /* MRV_ISP_AWB_REF_CB__MAX_B */ +/*****************************************************************************/ +/** + * register: isp_awb_thresh: Auto white balance threshold values (0x012c) + * + *****************************************************************************/ +/* Slice: AWB_MAX_Y:*/ +/* - Luminance maximum value, only consider pixels with luminance smaller than threshold for the WB measurement (must be enabled by AWB_MODE(2)),*/ +/* - ignored if RGB measurement mode is enabled */ +#ifdef MRV_ISP_AWB_MAX_Y +#endif /* MRV_ISP_AWB_MAX_Y */ +/* Slice: AWB_MIN_Y__MAX_G:*/ +/* - Luminance minimum value, only consider pixels with luminance greater than threshold for the WB measurement */ +/* - maximum green value, if RGB measurement mode is selected */ +#ifdef MRV_ISP_AWB_MIN_Y__MAX_G +#endif /* MRV_ISP_AWB_MIN_Y__MAX_G */ +/* Slice: AWB_MAX_CSUM:*/ +/* - Chrominance sum maximum value, only consider pixels with Cb+Cr smaller than threshold for WB measurements */ +/* - ignored if RGB measurement mode is enabled */ +#ifdef MRV_ISP_AWB_MAX_CSUM +#endif /* MRV_ISP_AWB_MAX_CSUM */ +/* Slice: AWB_MIN_C:*/ +/* - Chrominance minimum value, only consider pixels with Cb/Cr each greater than threshold value for WB measurements */ +/* - ignored if RGB measurement mode is enabled */ +#ifdef MRV_ISP_AWB_MIN_C +#endif /* MRV_ISP_AWB_MIN_C */ +/*****************************************************************************/ +/** + * register: isp_awb_gain_g: Auto white balance gain green (0x0138) + * + *****************************************************************************/ +/* Slice: AWB_GAIN_GR:*/ +/* gain value for green component in red line 100h = 1 */ +#ifdef MRV_ISP_AWB_GAIN_GR +#define MRV_ISP_AWB_GAIN_GR_DEFAULT (0x100U) +#define MRV_ISP_AWB_GAIN_GR_MAX (MRV_ISP_AWB_GAIN_GR_MASK >> MRV_ISP_AWB_GAIN_GR_SHIFT) +#endif /* MRV_ISP_AWB_GAIN_GR */ +/* Slice: AWB_GAIN_GB:*/ +/* gain value for green component in blue line 100h = 1 */ +#ifdef MRV_ISP_AWB_GAIN_GB +#define MRV_ISP_AWB_GAIN_GB_DEFAULT (0x100U) +#define MRV_ISP_AWB_GAIN_GB_MAX (MRV_ISP_AWB_GAIN_GB_MASK >> MRV_ISP_AWB_GAIN_GB_SHIFT) +#endif /* MRV_ISP_AWB_GAIN_GB */ +/*****************************************************************************/ +/** + * register: isp_awb_gain_rb: Auto white balance gain red and blue (0x013c) + * + *****************************************************************************/ +/* Slice: AWB_GAIN_R:*/ +/* gain value for red component 100h = 1 */ +#ifdef MRV_ISP_AWB_GAIN_R +#define MRV_ISP_AWB_GAIN_R_DEFAULT (0x100U) +#define MRV_ISP_AWB_GAIN_R_MAX (MRV_ISP_AWB_GAIN_R_MASK >> MRV_ISP_AWB_GAIN_R_SHIFT) +#endif /* MRV_ISP_AWB_GAIN_R */ +/* Slice: AWB_GAIN_B:*/ +/* gain value for blue component 100h = 1 */ +#ifdef MRV_ISP_AWB_GAIN_B +#define MRV_ISP_AWB_GAIN_B_DEFAULT (0x100U) +#define MRV_ISP_AWB_GAIN_B_MAX (MRV_ISP_AWB_GAIN_B_MASK >> MRV_ISP_AWB_GAIN_B_SHIFT) +#endif /* MRV_ISP_AWB_GAIN_B */ +/*****************************************************************************/ +/** + * register: isp_awb_white_cnt: Auto white balance white pixel count (0x0140) + * + *****************************************************************************/ +/* Slice: AWB_WHITE_CNT:*/ +/* White pixel count, number of "white pixels" found during last measurement, i.e. pixels included in mean value calculation */ +#ifdef MRV_ISP_AWB_WHITE_CNT +#endif /* MRV_ISP_AWB_WHITE_CNT */ +/*****************************************************************************/ +/** + * register: isp_awb_mean: Auto white balance measured mean value (0x0144) + * + *****************************************************************************/ +/* Slice: AWB_MEAN_Y_G:*/ +/* - mean value of Y within window and frames */ +/* - mean value of green within window and frames if RGB measurement is enabled */ +#ifdef MRV_ISP_AWB_MEAN_Y__G +#endif /* MRV_ISP_AWB_MEAN_Y__G */ +/* Slice: AWB_MEAN_CB_B:*/ +/* - mean value of Cb within window and frames */ +/* - mean value of blue within window and frames if RGB measurement is enabled */ +#ifdef MRV_ISP_AWB_MEAN_CB__B +#endif /* MRV_ISP_AWB_MEAN_CB__B */ +/* Slice: AWB_MEAN_CR_R:*/ +/* - mean value of Cr within window and frames */ +/* - mean value of red within window and frames if RGB measurement is enabled */ +#ifdef MRV_ISP_AWB_MEAN_CR__R +#endif /* MRV_ISP_AWB_MEAN_CR__R */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_0: Color conversion coefficient 0 (0x0170) + * + *****************************************************************************/ +/* Slice: cc_coeff_0:*/ +/* coefficient 0 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_0 +#endif /* MRV_ISP_CC_COEFF_0 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_1: Color conversion coefficient 1 (0x0174) + * + *****************************************************************************/ +/* Slice: cc_coeff_1:*/ +/* coefficient 1 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_1 +#endif /* MRV_ISP_CC_COEFF_1 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_2: Color conversion coefficient 2 (0x0178) + * + *****************************************************************************/ +/* Slice: cc_coeff_2:*/ +/* coefficient 2 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_2 +#endif /* MRV_ISP_CC_COEFF_2 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_3: Color conversion coefficient 3 (0x017c) + * + *****************************************************************************/ +/* Slice: cc_coeff_3:*/ +/* coefficient 3 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_3 +#endif /* MRV_ISP_CC_COEFF_3 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_4: Color conversion coefficient 4 (0x0180) + * + *****************************************************************************/ +/* Slice: cc_coeff_4:*/ +/* coefficient 4 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_4 +#endif /* MRV_ISP_CC_COEFF_4 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_5: Color conversion coefficient 5 (0x0184) + * + *****************************************************************************/ +/* Slice: cc_coeff_5:*/ +/* coefficient 5 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_5 +#endif /* MRV_ISP_CC_COEFF_5 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_6: Color conversion coefficient 6 (0x0188) + * + *****************************************************************************/ +/* Slice: cc_coeff_6:*/ +/* coefficient 6 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_6 +#endif /* MRV_ISP_CC_COEFF_6 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_7: Color conversion coefficient 7 (0x018c) + * + *****************************************************************************/ +/* Slice: cc_coeff_7:*/ +/* coefficient 7 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_7 +#endif /* MRV_ISP_CC_COEFF_7 */ +/*****************************************************************************/ +/** + * register: isp_cc_coeff_8: Color conversion coefficient 8 (0x0190) + * + *****************************************************************************/ +/* Slice: cc_coeff_8:*/ +/* coefficient 8 for color space conversion */ +#ifdef MRV_ISP_CC_COEFF_8 +#endif /* MRV_ISP_CC_COEFF_8 */ +/*****************************************************************************/ +/** + * register: isp_out_h_offs: Horizontal offset of output window (0x0194) + * + *****************************************************************************/ +/* Slice: ISP_OUT_H_OFFS:*/ +/* vertical pic offset in lines */ +#ifdef MRV_ISP_ISP_OUT_H_OFFS +#endif /* MRV_ISP_ISP_OUT_H_OFFS */ +/*****************************************************************************/ +/** + * register: isp_out_v_offs: Vertical offset of output window (0x0198) + * + *****************************************************************************/ +/* Slice: ISP_OUT_V_OFFS:*/ +/* vertical pic offset in lines */ +#ifdef MRV_ISP_ISP_OUT_V_OFFS +#endif /* MRV_ISP_ISP_OUT_V_OFFS */ +/*****************************************************************************/ +/** + * register: isp_out_h_size: Output horizontal picture size (0x019c) + * + *****************************************************************************/ +/* Slice: ISP_OUT_H_SIZE:*/ +/* horizontal picture size in pixel */ +/* if ISP_MODE is set to */ +/* 001: (ITU-R BT.656 YUV),*/ +/* 010: (ITU-R BT.601 YUV),*/ +/* 011: (ITU-R BT.601 Bayer RGB),*/ +/* 101: (ITU-R BT.656 Bayer RGB)*/ +/* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr)*/ +/* are needed for the 422 output. (if an odd size is programmed the value will */ +/* be truncated to an even size)*/ +#ifdef MRV_ISP_ISP_OUT_H_SIZE +#define MRV_ISP_ISP_OUT_H_SIZE_IS_EVEN(x) (!(x & 0x01U)) /* check is even value */ +#define MRV_ISP_ISP_OUT_H_SIZE_IS_ODD(x) (x & 0x01U) /* check is odd value */ +#endif /* MRV_ISP_ISP_OUT_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_out_v_size: Output vertical picture size (0x01a0) + * + *****************************************************************************/ +/* Slice: ISP_OUT_V_SIZE:*/ +/* vertical pic size in lines */ +#ifdef MRV_ISP_ISP_OUT_V_SIZE +#endif /* MRV_ISP_ISP_OUT_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_demosaic: Demosaic parameters (0x000001a4) + * + *****************************************************************************/ +/* Slice: DEMOSAIC_BYPASS:*/ +/* 0: normal operation for RGB Bayer Pattern input */ +/* 1: demosaicing bypass for Black&White input data */ +#ifdef MRV_ISP_DEMOSAIC_BYPASS +#define MRV_ISP_DEMOSAIC_MODE_STD 0 /* "0": standard */ +#define MRV_ISP_DEMOSAIC_MODE_ENH 1 /* "1": enhanced mode */ +#endif /* MRV_ISP_DEMOSAIC_BYPASS */ +/* Slice: DEMOSAIC_TH:*/ +/* Threshold for Bayer demosaicing texture detection. This value shifted left */ +/* 4bit is compared with the difference of the vertical and horizontal 12Bit */ +/* wide texture indicators, to decide if the vertical or horizontal texture */ +/* flag must be set.*/ +/* 0xFF: no texture detection */ +/* 0x00: maximum edge sensitivity */ +#ifdef MRV_ISP_DEMOSAIC_TH +#define MRV_ISP_DEMOSAIC_TH_MAX_TEXTURE_DETECTION 0xFFU /* 0xFF: no texture detection */ +#define MRV_ISP_DEMOSAIC_TH_MAX_EDGE_SENSITIVITY 0x00U /* 0x00: maximum edge sensitivity */ +#endif /* MRV_ISP_DEMOSAIC_TH */ +/*****************************************************************************/ +/** + * register: isp_flags_shd: Flags (current status) of certain signals and + * Shadow regs for enable signals (0x000001a8) + * + *****************************************************************************/ +/* Slice: S_HSYNC:*/ +/* state of ISP input port s_hsync, for test purposes */ +#ifdef MRV_ISP_S_HSYNC +#endif /* MRV_ISP_S_HSYNC */ +/* Slice: S_VSYNC:*/ +/* state of ISP input port s_vsync, for test purposes */ +#ifdef MRV_ISP_S_VSYNC +#endif /* MRV_ISP_S_VSYNC */ +/* Slice: S_DATA:*/ +/* state of ISP input port s_data, for test purposes */ +#ifdef MRV_ISP_S_DATA +#endif /* MRV_ISP_S_DATA */ +/* Slice: INFORM_FIELD:*/ +/* current field information */ +/* 0: odd */ +/* 1: even */ +#ifdef MRV_ISP_INFORM_FIELD +#define MRV_ISP_INFORM_FIELD_ODD 0 /* 0: odd field is sampled */ +#define MRV_ISP_INFORM_FIELD_EVEN 1 /* 1: even field is sampled */ +#endif /* MRV_ISP_INFORM_FIELD */ +/* Slice: INFORM_EN_SHD:*/ +/* Input formatter enable shadow register */ +#ifdef MRV_ISP_INFORM_EN_SHD +#endif /* MRV_ISP_INFORM_EN_SHD */ +/* Slice: ISP_ENABLE_SHD:*/ +/* ISP enable shadow register */ +/* shows, if ISP currently outputs data (1) or not (0)*/ +#ifdef MRV_ISP_ISP_ENABLE_SHD +#endif /* MRV_ISP_ISP_ENABLE_SHD */ +/*****************************************************************************/ +/** + * register: isp_out_h_offs_shd: current horizontal offset of output window + * (shadow register) (0x000001ac) + * + *****************************************************************************/ +/* Slice: ISP_OUT_H_OFFS_SHD:*/ +/* current vertical pic offset in lines */ +#ifdef MRV_ISP_ISP_OUT_H_OFFS_SHD +#endif /* MRV_ISP_ISP_OUT_H_OFFS_SHD */ +/*****************************************************************************/ +/** + * register: isp_out_v_offs_shd: current vertical offset of output window + * (shadow register) (0x000001b0) + * + *****************************************************************************/ +/* Slice: ISP_OUT_V_OFFS_SHD:*/ +/* current vertical pic offset in lines */ +#ifdef MRV_ISP_ISP_OUT_V_OFFS_SHD +#endif /* MRV_ISP_ISP_OUT_V_OFFS_SHD */ +/*****************************************************************************/ +/** + * register: isp_out_h_size_shd: current output horizontal picture size + * (shadow register) (0x000001b4) + * + *****************************************************************************/ +/* Slice: ISP_OUT_H_SIZE_SHD:*/ +/* current horizontal pic size in pixel */ +#ifdef MRV_ISP_ISP_OUT_H_SIZE_SHD +#endif /* MRV_ISP_ISP_OUT_H_SIZE_SHD */ +/*****************************************************************************/ +/** + * register: isp_out_v_size_shd: current output vertical picture size + * (shadow register) (0x000001b8) + * + *****************************************************************************/ +/* Slice: ISP_OUT_V_SIZE_SHD:*/ +/* vertical pic size in lines */ +#ifdef MRV_ISP_ISP_OUT_V_SIZE_SHD +#endif /* MRV_ISP_ISP_OUT_V_SIZE_SHD */ +/*****************************************************************************/ +/** + * register: isp_imsc: Interrupt mask (0x000001bc) + * + *****************************************************************************/ +/*! Slice: IMSC_VSM_END:*/ +/*! enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_VSM_END +#define MRV_ISP_IMSC_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_VSM_END */ +/* Slice: IMSC_EXP_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_EXP_END +#define MRV_ISP_IMSC_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_EXP_END */ +/* Slice: IMSC_FLASH_CAP:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_FLASH_CAP +#define MRV_ISP_IMSC_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_FLASH_CAP */ +/* Slice: IMSC_BP_DET:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_BP_DET +#define MRV_ISP_IMSC_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_BP_DET */ +/* Slice: IMSC_HIST_MEASURE_RDY:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_HIST_MEASURE_RDY +#define MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_HIST_MEASURE_RDY */ +/* Slice: IMSC_AFM_FIN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_AFM_FIN +#define MRV_ISP_IMSC_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !IMSC_AFM_FIN */ +/* Slice: IMSC_AFM_LUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_AFM_LUM_OF +#define MRV_ISP_IMSC_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_AFM_LUM_OF */ +/* Slice: IMSC_AFM_SUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_AFM_SUM_OF +#define MRV_ISP_IMSC_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_AFM_SUM_OF */ +/* Slice: IMSC_SHUTTER_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_SHUTTER_OFF +#define MRV_ISP_IMSC_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_SHUTTER_OFF */ +/* Slice: IMSC_SHUTTER_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_SHUTTER_ON +#define MRV_ISP_IMSC_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_SHUTTER_ON */ +/* Slice: IMSC_FLASH_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_FLASH_OFF +#define MRV_ISP_IMSC_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_FLASH_OFF */ +/* Slice: IMSC_FLASH_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_FLASH_ON +#define MRV_ISP_IMSC_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_FLASH_ON */ +/* Slice: IMSC_H_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_H_START +#define MRV_ISP_IMSC_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_H_START */ +/* Slice: IMSC_V_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_V_START +#define MRV_ISP_IMSC_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_V_START */ +/* Slice: IMSC_FRAME_IN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_FRAME_IN +#define MRV_ISP_IMSC_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_FRAME_IN */ +/* Slice: IMSC_AWB_DONE:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_AWB_DONE +#define MRV_ISP_IMSC_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_AWB_DONE */ +/* Slice: IMSC_PIC_SIZE_ERR:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_PIC_SIZE_ERR +#define MRV_ISP_IMSC_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_PIC_SIZE_ERR */ +/* Slice: IMSC_DATA_LOSS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_DATA_LOSS +#define MRV_ISP_IMSC_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_DATA_LOSS */ +/* Slice: IMSC_FRAME:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_FRAME +#define MRV_ISP_IMSC_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_FRAME */ +/* Slice: IMSC_ISP_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_IMSC_ISP_OFF +#define MRV_ISP_IMSC_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_IMSC_ISP_OFF */ +/* combination of all interrupt lines */ +#define MRV_ISP_IMSC_ALL_IRQS +#define MRV_ISP_IMSC_ALL_IRQS_MASK \ +(0 \ + | MRV_ISP_IMSC_VSM_END_MASK \ + | MRV_ISP_IMSC_EXP_END_MASK \ + | MRV_ISP_IMSC_FLASH_CAP_MASK \ + | MRV_ISP_IMSC_BP_DET_MASK \ + | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK \ + | MRV_ISP_IMSC_AFM_FIN_MASK \ + | MRV_ISP_IMSC_AFM_LUM_OF_MASK \ + | MRV_ISP_IMSC_AFM_SUM_OF_MASK \ + | MRV_ISP_IMSC_SHUTTER_OFF_MASK \ + | MRV_ISP_IMSC_SHUTTER_ON_MASK \ + | MRV_ISP_IMSC_FLASH_OFF_MASK \ + | MRV_ISP_IMSC_FLASH_ON_MASK \ + | MRV_ISP_IMSC_H_START_MASK \ + | MRV_ISP_IMSC_V_START_MASK \ + | MRV_ISP_IMSC_FRAME_IN_MASK \ + | MRV_ISP_IMSC_AWB_DONE_MASK \ + | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK \ + | MRV_ISP_IMSC_DATA_LOSS_MASK \ + | MRV_ISP_IMSC_FRAME_MASK \ + | MRV_ISP_IMSC_ISP_OFF_MASK \ +) +#define MRV_ISP_IMSC_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register: isp_ris: Raw interrupt status (0x000001c0) + * + *****************************************************************************/ +/*! Slice: RIS_VSM_END:*/ +/*! VSM measurement complete */ +#ifndef MRV_ISP_RIS_VSM_END +#define MRV_ISP_RIS_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_VSM_END */ +/* Slice: RIS_EXP_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_EXP_END +#define MRV_ISP_RIS_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_EXP_END */ +/* Slice: RIS_FLASH_CAP:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_FLASH_CAP +#define MRV_ISP_RIS_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_FLASH_CAP */ +/* Slice: RIS_BP_DET:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_BP_DET +#define MRV_ISP_RIS_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_BP_DET */ +/* Slice: RIS_HIST_MEASURE_RDY:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_HIST_MEASURE_RDY +#define MRV_ISP_RIS_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_HIST_MEASURE_RDY */ +/* Slice: RIS_AFM_FIN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_AFM_FIN +#define MRV_ISP_RIS_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !RIS_AFM_FIN */ +/* Slice: RIS_AFM_LUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_AFM_LUM_OF +#define MRV_ISP_RIS_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_AFM_LUM_OF */ +/* Slice: RIS_AFM_SUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_AFM_SUM_OF +#define MRV_ISP_RIS_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_AFM_SUM_OF */ +/* Slice: RIS_SHUTTER_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_SHUTTER_OFF +#define MRV_ISP_RIS_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_SHUTTER_OFF */ +/* Slice: RIS_SHUTTER_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_SHUTTER_ON +#define MRV_ISP_RIS_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_SHUTTER_ON */ +/* Slice: RIS_FLASH_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_FLASH_OFF +#define MRV_ISP_RIS_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_FLASH_OFF */ +/* Slice: RIS_FLASH_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_FLASH_ON +#define MRV_ISP_RIS_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_FLASH_ON */ +/* Slice: RIS_H_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_H_START +#define MRV_ISP_RIS_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_H_START */ +/* Slice: RIS_V_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_V_START +#define MRV_ISP_RIS_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_V_START */ +/* Slice: RIS_FRAME_IN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_FRAME_IN +#define MRV_ISP_RIS_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_FRAME_IN */ +/* Slice: RIS_AWB_DONE:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_AWB_DONE +#define MRV_ISP_RIS_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_AWB_DONE */ +/* Slice: RIS_PIC_SIZE_ERR:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_PIC_SIZE_ERR +#define MRV_ISP_RIS_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_PIC_SIZE_ERR */ +/* Slice: RIS_DATA_LOSS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_DATA_LOSS +#define MRV_ISP_RIS_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_DATA_LOSS */ +/* Slice: RIS_FRAME:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_FRAME +#define MRV_ISP_RIS_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_FRAME */ +/* Slice: RIS_ISP_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_RIS_ISP_OFF +#define MRV_ISP_RIS_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_RIS_ISP_OFF */ +/* combination of all interrupt lines */ +#define MRV_ISP_RIS_ALL_IRQS +#define MRV_ISP_RIS_ALL_IRQS_MASK \ +(0 \ + | MRV_ISP_RIS_VSM_END_MASK \ + | MRV_ISP_RIS_EXP_END_MASK \ + | MRV_ISP_RIS_FLASH_CAP_MASK \ + | MRV_ISP_RIS_BP_DET_MASK \ + | MRV_ISP_RIS_HIST_MEASURE_RDY_MASK \ + | MRV_ISP_RIS_AFM_FIN_MASK \ + | MRV_ISP_RIS_AFM_LUM_OF_MASK \ + | MRV_ISP_RIS_AFM_SUM_OF_MASK \ + | MRV_ISP_RIS_SHUTTER_OFF_MASK \ + | MRV_ISP_RIS_SHUTTER_ON_MASK \ + | MRV_ISP_RIS_FLASH_OFF_MASK \ + | MRV_ISP_RIS_FLASH_ON_MASK \ + | MRV_ISP_RIS_H_START_MASK \ + | MRV_ISP_RIS_V_START_MASK \ + | MRV_ISP_RIS_FRAME_IN_MASK \ + | MRV_ISP_RIS_AWB_DONE_MASK \ + | MRV_ISP_RIS_PIC_SIZE_ERR_MASK \ + | MRV_ISP_RIS_DATA_LOSS_MASK \ + | MRV_ISP_RIS_FRAME_MASK \ + | MRV_ISP_RIS_ISP_OFF_MASK \ +) +#define MRV_ISP_RIS_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register: isp_mis: Masked interrupt status (0x000001c4) + * + *****************************************************************************/ +/*! Slice: MIS_VSM_END:*/ +/*! VSM measurement complete */ +#ifndef MRV_ISP_MIS_VSM_END +#define MRV_ISP_MIS_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_VSM_END_MASK */ +/* Slice: MIS_EXP_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_EXP_END +#define MRV_ISP_MIS_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_EXP_END */ +/* Slice: MIS_FLASH_CAP:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_FLASH_CAP +#define MRV_ISP_MIS_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_FLASH_CAP */ +/* Slice: MIS_BP_DET:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_BP_DET +#define MRV_ISP_MIS_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_BP_DET */ +/* Slice: MIS_HIST_MEASURE_RDY:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_HIST_MEASURE_RDY +#define MRV_ISP_MIS_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_HIST_MEASURE_RDY */ +/* Slice: MIS_AFM_FIN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_AFM_FIN +#define MRV_ISP_MIS_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MIS_AFM_FIN */ +/* Slice: MIS_AFM_LUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_AFM_LUM_OF +#define MRV_ISP_MIS_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_AFM_LUM_OF */ +/* Slice: MIS_AFM_SUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_AFM_SUM_OF +#define MRV_ISP_MIS_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_AFM_SUM_OF */ +/* Slice: MIS_SHUTTER_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_SHUTTER_OFF +#define MRV_ISP_MIS_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_SHUTTER_OFF */ +/* Slice: MIS_SHUTTER_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_SHUTTER_ON +#define MRV_ISP_MIS_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_SHUTTER_ON */ +/* Slice: MIS_FLASH_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_FLASH_OFF +#define MRV_ISP_MIS_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_FLASH_OFF */ +/* Slice: MIS_FLASH_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_FLASH_ON +#define MRV_ISP_MIS_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_FLASH_ON */ +/* Slice: MIS_H_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_H_START +#define MRV_ISP_MIS_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_H_START */ +/* Slice: MIS_V_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_V_START +#define MRV_ISP_MIS_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_V_START */ +/* Slice: MIS_FRAME_IN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_FRAME_IN +#define MRV_ISP_MIS_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_FRAME_IN */ +/* Slice: MIS_AWB_DONE:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_AWB_DONE +#define MRV_ISP_MIS_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_AWB_DONE */ +/* Slice: MIS_PIC_SIZE_ERR:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_PIC_SIZE_ERR +#define MRV_ISP_MIS_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_PIC_SIZE_ERR */ +/* Slice: MIS_DATA_LOSS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_DATA_LOSS +#define MRV_ISP_MIS_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_DATA_LOSS */ +/* Slice: MIS_FRAME:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_FRAME +#define MRV_ISP_MIS_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_FRAME */ +/* Slice: MIS_ISP_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_MIS_ISP_OFF +#define MRV_ISP_MIS_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_MIS_ISP_OFF */ +/* combination of all interrupt lines */ +#define MRV_ISP_MIS_ALL_IRQS +#define MRV_ISP_MIS_ALL_IRQS_MASK \ + (0 \ + | MRV_ISP_MIS_VSM_END_MASK \ + | MRV_ISP_MIS_EXP_END_MASK \ + | MRV_ISP_MIS_FLASH_CAP_MASK \ + | MRV_ISP_MIS_BP_DET_MASK \ + | MRV_ISP_MIS_HIST_MEASURE_RDY_MASK \ + | MRV_ISP_MIS_AFM_FIN_MASK \ + | MRV_ISP_MIS_AFM_LUM_OF_MASK \ + | MRV_ISP_MIS_AFM_SUM_OF_MASK \ + | MRV_ISP_MIS_SHUTTER_OFF_MASK \ + | MRV_ISP_MIS_SHUTTER_ON_MASK \ + | MRV_ISP_MIS_FLASH_OFF_MASK \ + | MRV_ISP_MIS_FLASH_ON_MASK \ + | MRV_ISP_MIS_H_START_MASK \ + | MRV_ISP_MIS_V_START_MASK \ + | MRV_ISP_MIS_FRAME_IN_MASK \ + | MRV_ISP_MIS_AWB_DONE_MASK \ + | MRV_ISP_MIS_PIC_SIZE_ERR_MASK \ + | MRV_ISP_MIS_DATA_LOSS_MASK \ + | MRV_ISP_MIS_FRAME_MASK \ + | MRV_ISP_MIS_ISP_OFF_MASK \ + ) +#define MRV_ISP_MIS_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register: isp_icr: Interrupt clear register (0x000001c8) + * + *****************************************************************************/ +/*! Slice: ICR_VSM_END:*/ +/*! clear interrupt */ +#ifndef MRV_ISP_ICR_VSM_END +#define MRV_ISP_ICR_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_VSM_END */ +/* Slice: ICR_EXP_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_EXP_END +#define MRV_ISP_ICR_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_EXP_END */ +/* Slice: ICR_FLASH_CAP:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_FLASH_CAP +#define MRV_ISP_ICR_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_FLASH_CAP */ +/* Slice: ICR_BP_DET:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_BP_DET +#define MRV_ISP_ICR_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_BP_DET */ +/* Slice: ICR_HIST_MEASURE_RDY:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_HIST_MEASURE_RDY +#define MRV_ISP_ICR_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_HIST_MEASURE_RDY */ +/* Slice: ICR_AFM_FIN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_AFM_FIN +#define MRV_ISP_ICR_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !ICR_AFM_FIN */ +/* Slice: ICR_AFM_LUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_AFM_LUM_OF +#define MRV_ISP_ICR_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_AFM_LUM_OF */ +/* Slice: ICR_AFM_SUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_AFM_SUM_OF +#define MRV_ISP_ICR_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_AFM_SUM_OF */ +/* Slice: ICR_SHUTTER_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_SHUTTER_OFF +#define MRV_ISP_ICR_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_SHUTTER_OFF */ +/* Slice: ICR_SHUTTER_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_SHUTTER_ON +#define MRV_ISP_ICR_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_SHUTTER_ON */ +/* Slice: ICR_FLASH_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_FLASH_OFF +#define MRV_ISP_ICR_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_FLASH_OFF */ +/* Slice: ICR_FLASH_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_FLASH_ON +#define MRV_ISP_ICR_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_FLASH_ON */ +/* Slice: ICR_H_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_H_START +#define MRV_ISP_ICR_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_H_START */ +/* Slice: ICR_V_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_V_START +#define MRV_ISP_ICR_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_V_START */ +/* Slice: ICR_FRAME_IN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_FRAME_IN +#define MRV_ISP_ICR_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_FRAME_IN */ +/* Slice: ICR_AWB_DONE:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_AWB_DONE +#define MRV_ISP_ICR_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_AWB_DONE */ +/* Slice: ICR_PIC_SIZE_ERR:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_PIC_SIZE_ERR +#define MRV_ISP_ICR_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_PIC_SIZE_ERR */ +/* Slice: ICR_DATA_LOSS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_DATA_LOSS +#define MRV_ISP_ICR_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_DATA_LOSS */ +/* Slice: ICR_FRAME:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_FRAME +#define MRV_ISP_ICR_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_FRAME */ +/* Slice: ICR_ISP_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ICR_ISP_OFF +#define MRV_ISP_ICR_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ICR_ISP_OFF */ +/* combination of all interrupt lines */ +#define MRV_ISP_ICR_ALL_IRQS +#define MRV_ISP_ICR_ALL_IRQS_MASK \ +(0 \ + | MRV_ISP_ICR_VSM_END_MASK \ + | MRV_ISP_ICR_EXP_END_MASK \ + | MRV_ISP_ICR_FLASH_CAP_MASK \ + | MRV_ISP_ICR_BP_DET_MASK \ + | MRV_ISP_ICR_HIST_MEASURE_RDY_MASK \ + | MRV_ISP_ICR_AFM_FIN_MASK \ + | MRV_ISP_ICR_AFM_LUM_OF_MASK \ + | MRV_ISP_ICR_AFM_SUM_OF_MASK \ + | MRV_ISP_ICR_SHUTTER_OFF_MASK \ + | MRV_ISP_ICR_SHUTTER_ON_MASK \ + | MRV_ISP_ICR_FLASH_OFF_MASK \ + | MRV_ISP_ICR_FLASH_ON_MASK \ + | MRV_ISP_ICR_H_START_MASK \ + | MRV_ISP_ICR_V_START_MASK \ + | MRV_ISP_ICR_FRAME_IN_MASK \ + | MRV_ISP_ICR_AWB_DONE_MASK \ + | MRV_ISP_ICR_PIC_SIZE_ERR_MASK \ + | MRV_ISP_ICR_DATA_LOSS_MASK \ + | MRV_ISP_ICR_FRAME_MASK \ + | MRV_ISP_ICR_ISP_OFF_MASK \ +) +#define MRV_ISP_ICR_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register: isp_isr: Interrupt set register (0x000001cc) + * + *****************************************************************************/ +/*! Register: isp_isr: Interrupt set register (0x000001cc)*/ +/*! Slice: ISR_VSM_END:*/ +/*! set interrupt */ +#ifndef MRV_ISP_ISR_VSM_END +#define MRV_ISP_ISR_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_VSM_END */ +/* Slice: ISR_EXP_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_EXP_END +#define MRV_ISP_ISR_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_EXP_END */ +/* Slice: ISR_FLASH_CAP:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_FLASH_CAP +#define MRV_ISP_ISR_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_FLASH_CAP */ +/* Slice: ISR_BP_DET:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_BP_DET +#define MRV_ISP_ISR_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_BP_DET */ +/* Slice: ISR_HIST_MEASURE_RDY:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_HIST_MEASURE_RDY +#define MRV_ISP_ISR_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_HIST_MEASURE_RDY */ +/* Slice: ISR_AFM_FIN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_AFM_FIN +#define MRV_ISP_ISR_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !ISR_AFM_FIN */ +/* Slice: ISR_AFM_LUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_AFM_LUM_OF +#define MRV_ISP_ISR_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_AFM_LUM_OF */ +/* Slice: ISR_AFM_SUM_OF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_AFM_SUM_OF +#define MRV_ISP_ISR_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_AFM_SUM_OF */ +/* Slice: ISR_SHUTTER_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_SHUTTER_OFF +#define MRV_ISP_ISR_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_SHUTTER_OFF */ +/* Slice: ISR_SHUTTER_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_SHUTTER_ON +#define MRV_ISP_ISR_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_SHUTTER_ON */ +/* Slice: ISR_FLASH_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_FLASH_OFF +#define MRV_ISP_ISR_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_FLASH_OFF */ +/* Slice: ISR_FLASH_ON:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_FLASH_ON +#define MRV_ISP_ISR_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_FLASH_ON */ +/* Slice: ISR_H_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_H_START +#define MRV_ISP_ISR_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_H_START */ +/* Slice: ISR_V_START:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_V_START +#define MRV_ISP_ISR_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_V_START */ +/* Slice: ISR_FRAME_IN:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_FRAME_IN +#define MRV_ISP_ISR_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_FRAME_IN */ +/* Slice: ISR_AWB_DONE:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_AWB_DONE +#define MRV_ISP_ISR_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_AWB_DONE */ +/* Slice: ISR_PIC_SIZE_ERR:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_PIC_SIZE_ERR +#define MRV_ISP_ISR_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_PIC_SIZE_ERR */ +/* Slice: ISR_DATA_LOSS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_DATA_LOSS +#define MRV_ISP_ISR_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_DATA_LOSS */ +/* Slice: ISR_FRAME:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_FRAME +#define MRV_ISP_ISR_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_FRAME */ +/* Slice: ISR_ISP_OFF:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_ISP_ISR_ISP_OFF +#define MRV_ISP_ISR_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */ +#endif /* !MRV_ISP_ISR_ISP_OFF */ +/* combination of all interrupt lines */ +#define MRV_ISP_ISR_ALL_IRQS +#define MRV_ISP_ISR_ALL_IRQS_MASK \ +(0 \ + | MRV_ISP_ISR_VSM_END_MASK \ + | MRV_ISP_ISR_EXP_END_MASK \ + | MRV_ISP_ISR_FLASH_CAP_MASK \ + | MRV_ISP_ISR_BP_DET_MASK \ + | MRV_ISP_ISR_HIST_MEASURE_RDY_MASK \ + | MRV_ISP_ISR_AFM_FIN_MASK \ + | MRV_ISP_ISR_AFM_LUM_OF_MASK \ + | MRV_ISP_ISR_AFM_SUM_OF_MASK \ + | MRV_ISP_ISR_SHUTTER_OFF_MASK \ + | MRV_ISP_ISR_SHUTTER_ON_MASK \ + | MRV_ISP_ISR_FLASH_OFF_MASK \ + | MRV_ISP_ISR_FLASH_ON_MASK \ + | MRV_ISP_ISR_H_START_MASK \ + | MRV_ISP_ISR_V_START_MASK \ + | MRV_ISP_ISR_FRAME_IN_MASK \ + | MRV_ISP_ISR_AWB_DONE_MASK \ + | MRV_ISP_ISR_PIC_SIZE_ERR_MASK \ + | MRV_ISP_ISR_DATA_LOSS_MASK \ + | MRV_ISP_ISR_FRAME_MASK \ + | MRV_ISP_ISR_ISP_OFF_MASK \ +) +#define MRV_ISP_ISR_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register array: isp_ct_coeff: cross-talk configuration register (color + * correction matrix) (0x03A0 + n*0x4 (n=0..8)) + * + *****************************************************************************/ +/* Slice: ct_coeff:*/ +/* Coefficient n for cross talk matrix.*/ + /**/ +/* Values are 11-bit signed fixed-point numbers with 4 bit integer and */ +/* 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF).*/ +/* 0 is reprsented by 0x000 and a coefficient value of 1 as 0x080.*/ +#ifdef MRV_ISP_CT_COEFF +#define MRV_ISP_CT_COEFF_DEFAULT 0x080U /* default value */ +#endif /* MRV_ISP_CT_COEFF */ +/*****************************************************************************/ +/** + * register: isp_gamma_out_mode: gamma segmentation mode register for output + * gamma (0x000001f4) + * + *****************************************************************************/ +/* Slice: equ_segm:*/ +/* 0: logarithmic like segmentation of gamma curve (default after reset)*/ +/* segmentation from 0 to 4095: 64 64 64 64 128 128 128 128 256 256 256 512 512 512 512 512 */ +/* 1: equidistant segmentation (all 16 segments are 256)*/ +#ifdef MRV_ISP_EQU_SEGM +#define MRV_ISP_EQU_SEGM_LOG 0 /* 0: logarithmic like segmentation of gamma curve (default after reset) */ +#define MRV_ISP_EQU_SEGM_EQU 1 /* 1: equidistant segmentation (all 16 segments are 256) */ +#endif /* MRV_ISP_EQU_SEGM */ +/*****************************************************************************/ +/** + * register array: isp_gamma_out_y: Gamma Out Curve definition y (0x03F0 + n*0x4 (n=0..16)) + * + *****************************************************************************/ +/* Slice: isp_gamma_out_y:*/ +/* Gamma_out curve point definition y-axis (output) for all color */ +/* components (red, green, blue)*/ +/* RESTRICTION: each Y_n must be in the +511/-512 range compared */ +/* to its predecessor (so that dy is 10-bit signed !)*/ +#ifdef MRV_ISP_ISP_GAMMA_OUT_Y +#endif /* MRV_ISP_ISP_GAMMA_OUT_Y */ +/*****************************************************************************/ +/** + * register: isp_err: ISP error register (0x0000023c) + * + *****************************************************************************/ +/* Slice: outform_size_err:*/ +/* size error is generated in outmux submodule */ +#ifdef MRV_ISP_OUTFORM_SIZE_ERR +#endif /* MRV_ISP_OUTFORM_SIZE_ERR */ +/* Slice: is_size_err:*/ +/* size error is generated in image stabilization submodule */ +#ifdef MRV_ISP_IS_SIZE_ERR +#endif /* MRV_ISP_IS_SIZE_ERR */ +/* Slice: inform_size_err:*/ +/* size error is generated in inform submodule */ +#ifdef MRV_ISP_INFORM_SIZE_ERR +#endif /* MRV_ISP_INFORM_SIZE_ERR */ +/*****************************************************************************/ +/** + * register: isp_err_clr: ISP error clear register (0x00000240) + * + *****************************************************************************/ +/* Slice: outform_size_err_clr:*/ +/* size error is cleared */ +#ifdef MRV_ISP_OUTFORM_SIZE_ERR_CLR +#endif /* MRV_ISP_OUTFORM_SIZE_ERR_CLR */ +/* Slice: is_size_err_clr:*/ +/* size error is cleared */ +#ifdef MRV_ISP_IS_SIZE_ERR_CLR +#endif /* MRV_ISP_IS_SIZE_ERR_CLR */ +/* Slice: inform_size_err_clr:*/ +/* size error is cleared */ +#ifdef MRV_ISP_INFORM_SIZE_ERR_CLR +#endif /* MRV_ISP_INFORM_SIZE_ERR_CLR */ +/*****************************************************************************/ +/** + * register: isp_frame_count: Frame counter (0x00000244) + * + *****************************************************************************/ +/* Slice: frame_counter:*/ +/* Current frame count of processing */ +#ifdef MRV_ISP_FRAME_COUNTER +#endif /* MRV_ISP_FRAME_COUNTER */ +/*****************************************************************************/ +/** + * register: isp_ct_offset_r: cross-talk offset red (0x00000248) + * + *****************************************************************************/ +/* Slice: ct_offset_r:*/ +/* Offset red for cross talk matrix. Two's complement integer number ranging */ +/* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/ +#ifdef MRV_ISP_CT_OFFSET_R +#define MRV_ISP_CT_OFFSET_R_DEFAULT 0x000U /* default value */ +#endif /* MRV_ISP_CT_OFFSET_R */ +/*****************************************************************************/ +/** + * register: isp_ct_offset_g: cross-talk offset green (0x0000024c) + * + *****************************************************************************/ +/* Slice: ct_offset_g:*/ +/* Offset green for cross talk matrix. Two's complement integer number ranging */ +/* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/ +#ifdef MRV_ISP_CT_OFFSET_G +#define MRV_ISP_CT_OFFSET_G_DEFAULT 0x000U /* default value */ +#endif /* MRV_ISP_CT_OFFSET_G */ +/*****************************************************************************/ +/** + * register: isp_ct_offset_b: cross-talk offset blue (0x00000250) + * + *****************************************************************************/ +/* Slice: ct_offset_b:*/ +/* Offset blue for cross talk matrix. Two's complement integer number ranging */ +/* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/ +#ifdef MRV_ISP_CT_OFFSET_B +#define MRV_ISP_CT_OFFSET_B_DEFAULT 0x000U /* default value */ +#endif /* MRV_ISP_CT_OFFSET_B */ +/*****************************************************************************/ +/* ISP Flash Module Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_flash_cmd: Flash command (0x0000) + * + *****************************************************************************/ +/* Slice: preflash_on:*/ +/* preflash on */ +/* 0: no effect */ +/* 1: flash delay counter is started at next trigger event */ +/* No capture event is signaled to the sensor interface block.*/ +#ifdef MRV_FLASH_PREFLASH_ON +#endif /* MRV_FLASH_PREFLASH_ON */ +/* Slice: flash_on:*/ +/* flash on */ +/* 0: no effect */ +/* 1: flash delay counter is started at next trigger event */ +/* A capture event is signaled to the sensor interface block.*/ +#ifdef MRV_FLASH_FLASH_ON +#endif /* MRV_FLASH_FLASH_ON */ +/* Slice: prelight_on:*/ +/* prelight on */ +/* 0: prelight is switched off at next trigger event */ +/* 1: prelight is switched on at next trigger event */ +#ifdef MRV_FLASH_PRELIGHT_ON +#endif /* MRV_FLASH_PRELIGHT_ON */ +/*****************************************************************************/ +/** + * register: isp_flash_config: Flash config (0x0004) + * + *****************************************************************************/ +/* Slice: fl_cap_del:*/ +/* capture delay */ +/* frame number (0 to 15) to be captured after trigger event */ +#ifdef MRV_FLASH_FL_CAP_DEL +#endif /* MRV_FLASH_FL_CAP_DEL */ +/* Slice: fl_trig_src:*/ +/* trigger source for flash and prelight */ +/* 0: use "vds_vsync" for trigger event (with evaluation of vs_in_edge)*/ +/* 1: use "fl_trig" for trigger event (positive edge)*/ +#ifdef MRV_FLASH_FL_TRIG_SRC +#define MRV_FLASH_FL_TRIG_SRC_VDS 0 /* 0: use "vds_vsync" for trigger event (with evaluation of vs_in_edge) */ +#define MRV_FLASH_FL_TRIG_SRC_FL 1 /* 1: use "fl_trig" for trigger event (positive edge) */ +#endif /* MRV_FLASH_FL_TRIG_SRC */ +/* Slice: fl_pol:*/ +/* polarity of flash related signals */ +/* 0: flash_trig, prelight_trig are high active */ +/* 1: flash_trig, prelight_trig are low active */ +#ifdef MRV_FLASH_FL_POL +#define MRV_FLASH_FL_POL_HIGH 0 /* 0: flash_trig, prelight_trig are high active */ +#define MRV_FLASH_FL_POL_LOW 1 /* 1: flash_trig, prelight_trig are low active */ +#endif /* MRV_FLASH_FL_POL */ +/* Slice: vs_in_edge:*/ +/* VSYNC edge */ +/* 0: use negative edge of "vds_vsync" if generating a trigger event */ +/* 1: use positive edge of "vds_vsync" if generating a trigger event */ +#ifdef MRV_FLASH_VS_IN_EDGE +#define MRV_FLASH_VS_IN_EDGE_NEG 0 /* 0: use negative edge of "vds_vsync" if generating a trigger event */ +#define MRV_FLASH_VS_IN_EDGE_POS 1 /* 1: use positive edge of "vds_vsync" if generating a trigger event */ +#endif /* MRV_FLASH_VS_IN_EDGE */ +/* Slice: prelight_mode:*/ +/* prelight mode */ +/* 0: prelight is switched off at begin of flash */ +/* 1: prelight is switched off at end of flash */ +#ifdef MRV_FLASH_PRELIGHT_MODE +#define MRV_FLASH_PRELIGHT_MODE_OASF 0 /* 0: prelight is switched off at begin of flash */ +#define MRV_FLASH_PRELIGHT_MODE_OAEF 1 /* 1: prelight is switched off at end of flash */ +#endif /* MRV_FLASH_PRELIGHT_MODE */ +/*****************************************************************************/ +/** + * register: isp_flash_prediv: Flash Counter Pre-Divider (0x00000008) + * + *****************************************************************************/ +/* Slice: fl_pre_div:*/ +/* pre-divider for flush/preflash counter */ +#ifdef MRV_FLASH_FL_PRE_DIV +#endif /* MRV_FLASH_FL_PRE_DIV */ +/*****************************************************************************/ +/** + * register: isp_flash_delay: Flash Delay (0x000c) + * + *****************************************************************************/ +/* Slice: fl_delay:*/ +/* counter value for flash/preflash delay */ +/* open_delay = (fl_delay + 1) * (fl_pre_div+1) / clk_isp */ +/* fl_delay = (open_delay * clk_isp) / (fl_pre_div+1) - 1 */ +#ifdef MRV_FLASH_FL_DELAY +#endif /* MRV_FLASH_FL_DELAY */ +/*****************************************************************************/ +/** + * register: isp_flash_time: Flash time (0x00000010) + * + *****************************************************************************/ +/* Slice: fl_time:*/ +/* counter value for flash/preflash time */ +/* open_time = (fl_time + 1) * (fl_pre_div+1) / clk_isp */ +/* fl_time = (open_time * clk_isp) / (fl_pre_div+1) - 1 */ +#ifdef MRV_FLASH_FL_TIME +#endif /* MRV_FLASH_FL_TIME */ +/*****************************************************************************/ +/** + * register: isp_flash_maxp: Maximum value for flash or preflash (0x00000014) + * + *****************************************************************************/ +/* Slice: fl_maxp:*/ +/* maximum period value for flash or preflash */ +/* max. flash/preflash period = 214 * (fl_maxp + 1) / clk_isp */ +/* fl_maxp = (max_period * clk_isp) / 214 - 1 */ +#ifdef MRV_FLASH_FL_MAXP +#endif /* MRV_FLASH_FL_MAXP */ +/*****************************************************************************/ +/* ISP Shutter Module Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_sh_ctrl: mechanical shutter control (0x0000) + * + *****************************************************************************/ +/* Slice: sh_open_pol:*/ +/* shutter_open polarity */ +/* 0: shutter_open is high active */ +/* 1: shutter_open is low active */ +#ifdef MRV_SHUT_SH_OPEN_POL +#define MRV_SHUT_SH_OPEN_POL_HIGH 0 /* 0: shutter_open is high active */ +#define MRV_SHUT_SH_OPEN_POL_LOW 1 /* 1: shutter_open is low active */ +#endif /* MRV_SHUT_SH_OPEN_POL */ +/* Slice: sh_trig_en:*/ +/* mechanical shutter trigger edge */ +/* 0: use negative edge of trigger signal */ +/* 1: use positive edge of trigger signal */ +#ifdef MRV_SHUT_SH_TRIG_EN +#define MRV_SHUT_SH_TRIG_EN_NEG 0 /* 0: use negative edge of trigger signal */ +#define MRV_SHUT_SH_TRIG_EN_POS 1 /* 1: use positive edge of trigger signal */ +#endif /* MRV_SHUT_SH_TRIG_EN */ +/* Slice: sh_trig_src:*/ +/* mechanical shutter trigger source */ +/* 0: use "vds_vsync" for trigger event */ +/* 1: use "shutter_trig" for trigger event */ +#ifdef MRV_SHUT_SH_TRIG_SRC +#define MRV_SHUT_SH_TRIG_SRC_VDS 0 /* 0: use "vds_vsync" for trigger event */ +#define MRV_SHUT_SH_TRIG_SRC_SHUT 1 /* 1: use "shutter_trig" for trigger event */ +#endif /* MRV_SHUT_SH_TRIG_SRC */ +/* Slice: sh_rep_en:*/ +/* mechanical shutter repetition enable */ +/* 0: shutter is opened only once */ +/* 1: shutter is opened with the repetition rate of the trigger signal */ +#ifdef MRV_SHUT_SH_REP_EN +#define MRV_SHUT_SH_REP_EN_ONCE 0 /* 0: shutter is opened only once */ +#define MRV_SHUT_SH_REP_EN_REP 1 /* 1: shutter is opened with the repetition rate of the trigger signal */ +#endif /* MRV_SHUT_SH_REP_EN */ +/* Slice: sh_en:*/ +/* mechanical shutter enable */ +/* 0: mechanical shutter function is disabled */ +/* 1: mechanical shutter function is enabled */ +#ifdef MRV_SHUT_SH_EN +#endif /* MRV_SHUT_SH_EN */ +/*****************************************************************************/ +/** + * register: isp_sh_prediv: Mech. Shutter Counter Pre-Divider (0x0004) + * + *****************************************************************************/ +/* Slice: sh_pre_div:*/ +/* pre-divider for mechanical shutter open_delay and open_time counter */ +#ifdef MRV_SHUT_SH_PRE_DIV +#endif /* MRV_SHUT_SH_PRE_DIV */ +/*****************************************************************************/ +/** + * register: isp_sh_delay: Delay register (0x00000008) + * + *****************************************************************************/ +/* Slice: sh_delay:*/ +/* counter value for delay */ +/* open_delay = (sh_delay + 1) * (fl_pre_div+1) / clk_isp */ +/* sh_delay = (open_delay * clk_isp) / (sh_pre_div+1) – 1 */ +#ifdef MRV_SHUT_SH_DELAY +#endif /* MRV_SHUT_SH_DELAY */ +/*****************************************************************************/ +/** + * register: isp_sh_time: Time register (0x0000000c) + * + *****************************************************************************/ +/* Slice: sh_time:*/ +/* counter value for time */ +/* open_time = (sh_time + 1) * (fl_pre_div+1) / clk_isp */ +/* sh_time = (open_time * clk_isp) / (sh_pre_div+1) - 1 */ +#ifndef MRV_SHUT_SH_TIME +#endif /* MRV_SHUT_SH_TIME */ +/*****************************************************************************/ +/* Color Processing Module Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: c_proc_ctrl: Global control register (0x0000) + * + *****************************************************************************/ +/* Slice: cproc_c_out_range:*/ +/* Color processing chrominance pixel clipping range at output */ +/* 0: CbCr_out clipping range 16..240 according to ITU-R BT.601 standard */ +/* 1: full UV_out clipping range 0..255 */ +#ifdef MRV_CPROC_CPROC_C_OUT_RANGE +#define MRV_CPROC_CPROC_C_OUT_RANGE_BT601 0 /* 0: CbCr_out clipping range 16..240 according to ITU-R BT.601 standard */ +#define MRV_CPROC_CPROC_C_OUT_RANGE_FULL 1 /* 1: full UV_out clipping range 0..255 */ +#endif /* MRV_CPROC_CPROC_C_OUT_RANGE */ +/* Slice: cproc_y_in_range:*/ +/* Color processing luminance input range (offset processing)*/ +/* 0: Y_in range 64..940 according to ITU-R BT.601 standard;*/ +/* offset of 64 will be subtracted from Y_in */ +/* 1: Y_in full range 0..1023; no offset will be subtracted from Y_in */ +#ifdef MRV_CPROC_CPROC_Y_IN_RANGE +#define MRV_CPROC_CPROC_Y_IN_RANGE_BT601 0 /* 0: Y_in range 64..940 according to ITU-R BT.601 standard */ +#define MRV_CPROC_CPROC_Y_IN_RANGE_FULL 1 /* 1: Y_in full range 0..1023 */ +#endif /* MRV_CPROC_CPROC_Y_IN_RANGE */ +/* Slice: cproc_y_out_range:*/ +/* Color processing luminance output clipping range */ +/* 0: Y_out clipping range 16..235; offset of 16 is added to Y_out according to ITU-R BT.601 standard */ +/* 1: Y_out clipping range 0..255; no offset is added to Y_out */ +#ifdef MRV_CPROC_CPROC_Y_OUT_RANGE +#define MRV_CPROC_CPROC_Y_OUT_RANGE_BT601 0 /* 0: Y_out clipping range 16..235; offset of 16 is added to Y_out according to ITU-R BT.601 standard */ +#define MRV_CPROC_CPROC_Y_OUT_RANGE_FULL 1 /* 1: Y_out clipping range 0..255; no offset is added to Y_out */ +#endif /* MRV_CPROC_CPROC_Y_OUT_RANGE */ +/* Slice: cproc_enable:*/ +/* color processing enable */ +/* 0: color processing is bypassed */ +/* 2 * 10 Bit input data are truncated to 2 * 8Bit output data */ +/* 1: color processing is active */ +/* output data are rounded to 2 * 8Bit and clipping is active */ +#ifdef MRV_CPROC_CPROC_ENABLE +#define MRV_CPROC_CPROC_ENABLE_PROCESS 1 /* 1: processing is activated */ +#define MRV_CPROC_CPROC_ENABLE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */ +#endif /* MRV_CPROC_CPROC_ENABLE */ +/*****************************************************************************/ +/** + * register: c_proc_contrast: Color Processing contrast register (0x0004) + * + *****************************************************************************/ +/* Slice: cproc_contrast:*/ +/* contrast adjustment value */ +/* 00H equals x 0.0 */ +/* ...*/ +/* 80H equals x 1.0 */ +/* ...*/ +/* FFH equals x 1.992 */ +#ifdef MRV_CPROC_CPROC_CONTRAST +#endif /* MRV_CPROC_CPROC_CONTRAST */ +/*****************************************************************************/ +/** + * register: c_proc_brightness: Color Processing brightness register (0x0008) + * + *****************************************************************************/ +/* Slice: cproc_brightness:*/ +/* brightness adjustment value */ +/* 80H equals -128 */ +/* ...*/ +/* 00H equals +0 */ +/* ...*/ +/* 7FH equals +127 */ +#ifdef MRV_CPROC_CPROC_BRIGHTNESS +#endif /* MRV_CPROC_CPROC_BRIGHTNESS */ +/*****************************************************************************/ +/** + * register: c_proc_saturation: Color Processing saturation register (0x000c) + * + *****************************************************************************/ +/* Slice: cproc_saturation:*/ +/* saturation adjustment value */ +/* 00H equals x 0.0 */ +/* ...*/ +/* 80H equals x 1.0 */ +/* ...*/ +/* FFH equals x 1.992 */ +#ifdef MRV_CPROC_CPROC_SATURATION +#endif /* MRV_CPROC_CPROC_SATURATION */ +/*****************************************************************************/ +/** + * register: c_proc_hue: Color Processing hue register (0x0010) + * + *****************************************************************************/ +/* Slice: cproc_hue:*/ +/* hue adjustment value */ +/* 80H equals -90 deg */ +/* ...*/ +/* 00H equals 0 deg */ +/* ...*/ +/* 7FH equals +87.188 deg */ +#ifdef MRV_CPROC_CPROC_HUE +#endif /* MRV_CPROC_CPROC_HUE */ +/*****************************************************************************/ +/* Main Resizer/Scaler Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: mrsz_ctrl: global control register (0x00000000) + * + *****************************************************************************/ +/* Slice: cfg_upd:*/ +/* write 0: nothing happens */ +/* write 1: update shadow registers */ +/* read: always 0 */ +#ifdef MRV_MRSZ_CFG_UPD +#endif /* MRV_MRSZ_CFG_UPD */ +/* Slice: scale_vc_up:*/ +/* 1: vertical chrominance upscaling selected */ +/* 0: vertical chrominance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_VC_UP +#define MRV_MRSZ_SCALE_VC_UP_UPSCALE 1 /* 1: vertical chrominance upscaling selected */ +#define MRV_MRSZ_SCALE_VC_UP_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_VC_UP */ +/* Slice: scale_vy_up:*/ +/* 1: vertical luminance upscaling selected */ +/* 0: vertical luminance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_VY_UP +#define MRV_MRSZ_SCALE_VY_UP_UPSCALE 1 /* 1: vertical luminance upscaling selected */ +#define MRV_MRSZ_SCALE_VY_UP_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_VY_UP */ +/* Slice: scale_hc_up:*/ +/* 1: horizontal chrominance upscaling selected */ +/* 0: horizontal chrominance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_HC_UP +#define MRV_MRSZ_SCALE_HC_UP_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */ +#define MRV_MRSZ_SCALE_HC_UP_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_HC_UP */ +/* Slice: scale_hy_up:*/ +/* 1: horizontal luminance upscaling selected */ +/* 0: horizontal luminance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_HY_UP +#define MRV_MRSZ_SCALE_HY_UP_UPSCALE 1 /* 1: horizontal luminance upscaling selected */ +#define MRV_MRSZ_SCALE_HY_UP_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_HY_UP */ +/* Slice: scale_vc_enable:*/ +/* 0: bypass vertical chrominance scaling unit */ +/* 1: enable vertical chrominance scaling unit */ +#ifdef MRV_MRSZ_SCALE_VC_ENABLE +#define MRV_MRSZ_SCALE_VC_ENABLE_PROCESS 1 /* 1: enable vertical chrominance scaling unit */ +#define MRV_MRSZ_SCALE_VC_ENABLE_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */ +#endif /* MRV_MRSZ_SCALE_VC_ENABLE */ +/* Slice: scale_vy_enable:*/ +/* 0: bypass vertical luminance scaling unit */ +/* 1: enable vertical luminance scaling unit */ +#ifdef MRV_MRSZ_SCALE_VY_ENABLE +#define MRV_MRSZ_SCALE_VY_ENABLE_PROCESS 1 /* 1: enable vertical luminance scaling unit */ +#define MRV_MRSZ_SCALE_VY_ENABLE_BYPASS 0 /* 0: bypass vertical luminance scaling unit */ +#endif /* MRV_MRSZ_SCALE_VY_ENABLE */ +/* Slice: scale_hc_enable:*/ +/* 0: bypass horizontal chrominance scaling unit */ +/* 1: enable horizontal chrominance scaling unit */ +#ifdef MRV_MRSZ_SCALE_HC_ENABLE +#define MRV_MRSZ_SCALE_HC_ENABLE_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */ +#define MRV_MRSZ_SCALE_HC_ENABLE_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */ +#endif /* MRV_MRSZ_SCALE_HC_ENABLE */ +/* Slice: scale_hy_enable:*/ +/* 0: bypass horizontal luminance scaling unit */ +/* 1: enable horizontal luminance scaling unit */ +#ifdef MRV_MRSZ_SCALE_HY_ENABLE +#define MRV_MRSZ_SCALE_HY_ENABLE_PROCESS 1 /* 1: enable horizontal luminance scaling unit */ +#define MRV_MRSZ_SCALE_HY_ENABLE_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */ +#endif /* MRV_MRSZ_SCALE_HY_ENABLE */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hy: horizontal luminance scale factor register + * (0x00000004) + * + *****************************************************************************/ +/* Slice: scale_hy:*/ +/* This register is set to the horizontal luminance downscale factor or to */ +/* the reciprocal of the horizontal luminance upscale factor */ +#ifdef MRV_MRSZ_SCALE_HY +#endif /* MRV_MRSZ_SCALE_HY */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hcb: horizontal Cb scale factor register (0x00000008) + * + *****************************************************************************/ +/* Slice: scale_hcb:*/ +/* This register is set to the horizontal Cb downscale factor or to the */ +/* reciprocal of the horizontal Cb upscale factor */ +#ifdef MRV_MRSZ_SCALE_HCB +#endif /* MRV_MRSZ_SCALE_HCB */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hcr: horizontal Cr scale factor register (0x0000000c) + * + *****************************************************************************/ +/* Slice: scale_hcr:*/ +/* This register is set to the horizontal Cr downscale factor or to the */ +/* reciprocal of the horizontal Cr upscale factor */ +#ifdef MRV_MRSZ_SCALE_HCR +#endif /* MRV_MRSZ_SCALE_HCR */ +/*****************************************************************************/ +/** + * register: mrsz_scale_vy: vertical luminance scale factor register (0x00000010) + * + *****************************************************************************/ +/* Slice: scale_vy:*/ +/* This register is set to the vertical luminance downscale factor or to the */ +/* reciprocal of the vertical luminance upscale factor */ +#ifdef MRV_MRSZ_SCALE_VY +#endif /* MRV_MRSZ_SCALE_VY */ +/*****************************************************************************/ +/** + * register: mrsz_scale_vc: vertical chrominance scale factor register (0x00000014) + * + *****************************************************************************/ +/* Slice: scale_vc:*/ +/* This register is set to the vertical chrominance downscale factor or to the */ +/* reciprocal of the vertical chrominance upscale factor */ +#ifdef MRV_MRSZ_SCALE_VC +#endif /* MRV_MRSZ_SCALE_VC */ +/*****************************************************************************/ +/** + * register: mrsz_phase_hy: horizontal luminance phase register (0x00000018) + * + *****************************************************************************/ +/* Slice: phase_hy:*/ +/* This register is set to the horizontal luminance phase offset */ +#ifdef MRV_MRSZ_PHASE_HY +#endif /* MRV_MRSZ_PHASE_HY */ +/*****************************************************************************/ +/** + * register: mrsz_phase_hc: horizontal chrominance phase register (0x0000001c) + * + *****************************************************************************/ +/* Slice: phase_hc:*/ +/* This register is set to the horizontal chrominance phase offset */ +#ifdef MRV_MRSZ_PHASE_HC +#endif /* MRV_MRSZ_PHASE_HC */ +/*****************************************************************************/ +/** + * register: mrsz_phase_vy: vertical luminance phase register (0x00000020) + * + *****************************************************************************/ +/* Slice: phase_vy:*/ +/* This register is set to the vertical luminance phase offset */ +#ifdef MRV_MRSZ_PHASE_VY +#endif /* MRV_MRSZ_PHASE_VY */ +/*****************************************************************************/ +/** + * register: mrsz_phase_vc: vertical chrominance phase register (0x00000024) + * + *****************************************************************************/ +/* Slice: phase_vc:*/ +/* This register is set to the vertical chrominance phase offset */ +#ifdef MRV_MRSZ_PHASE_VC +#endif /* MRV_MRSZ_PHASE_VC */ +/*****************************************************************************/ +/** + * register: mrsz_scale_lut_addr: Address pointer of up-scaling look up table + * (0x00000028) + * + *****************************************************************************/ +/* Slice: scale_lut_addr:*/ +/* Pointer to entry of lookup table */ +#ifdef MRV_MRSZ_SCALE_LUT_ADDR +#endif /* MRV_MRSZ_SCALE_LUT_ADDR */ +/*****************************************************************************/ +/** + * register: mrsz_scale_lut: Entry of up-scaling look up table (0x0000002c) + * + *****************************************************************************/ +/* Slice: scale_lut:*/ +/* Entry of lookup table at position scale_lut_addr. The lookup table must be */ +/* filled with appropriate values before the up-scaling functionality can be */ +/* used.*/ +#ifdef MRV_MRSZ_SCALE_LUT +#endif /* MRV_MRSZ_SCALE_LUT */ +/*****************************************************************************/ +/** + * register: mrsz_ctrl_shd: global control shadow register (0x0030) + * + *****************************************************************************/ +/* Slice: scale_vc_up_shd:*/ +/* 1: vertical chrominance upscaling selected */ +/* 0: vertical chrominance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_VC_UP_SHD +#define MRV_MRSZ_SCALE_VC_UP_SHD_UPSCALE 1 /* 1: vertical chrominance upscaling selected */ +#define MRV_MRSZ_SCALE_VC_UP_SHD_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_VC_UP_SHD */ +/* Slice: scale_vy_up_shd:*/ +/* 1: vertical luminance upscaling selected */ +/* 0: vertical luminance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_VY_UP_SHD +#define MRV_MRSZ_SCALE_VY_UP_SHD_UPSCALE 1 /* 1: vertical luminance upscaling selected */ +#define MRV_MRSZ_SCALE_VY_UP_SHD_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_VY_UP_SHD */ +/* Slice: scale_hc_up_shd:*/ +/* 1: horizontal chrominance upscaling selected */ +/* 0: horizontal chrominance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_HC_UP_SHD +#define MRV_MRSZ_SCALE_HC_UP_SHD_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */ +#define MRV_MRSZ_SCALE_HC_UP_SHD_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_HC_UP_SHD */ +/* Slice: scale_hy_up_shd:*/ +/* 1: horizontal luminance upscaling selected */ +/* 0: horizontal luminance downscaling selected */ +#ifdef MRV_MRSZ_SCALE_HY_UP_SHD +#define MRV_MRSZ_SCALE_HY_UP_SHD_UPSCALE 1 /* 1: horizontal luminance upscaling selected */ +#define MRV_MRSZ_SCALE_HY_UP_SHD_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */ +#endif /* MRV_MRSZ_SCALE_HY_UP_SHD */ +/* Slice: scale_vc_enable_shd:*/ +/* 0: bypass vertical chrominance scaling unit */ +/* 1: enable vertical chrominance scaling unit */ +#ifdef MRV_MRSZ_SCALE_VC_ENABLE_SHD +#define MRV_MRSZ_SCALE_VC_ENABLE_SHD_PROCESS 1 /* 1: enable vertical chrominance scaling unit */ +#define MRV_MRSZ_SCALE_VC_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */ +#endif /* MRV_MRSZ_SCALE_VC_ENABLE_SHD */ +/* Slice: scale_vy_enable_shd:*/ +/* 0: bypass vertical luminance scaling unit */ +/* 1: enable vertical luminance scaling unit */ +#ifdef MRV_MRSZ_SCALE_VY_ENABLE_SHD +#define MRV_MRSZ_SCALE_VY_ENABLE_SHD_PROCESS 1 /* 1: enable vertical luminance scaling unit */ +#define MRV_MRSZ_SCALE_VY_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical luminance scaling unit */ +#endif /* MRV_MRSZ_SCALE_VY_ENABLE_SHD */ +/* Slice: scale_hc_enable_shd:*/ +/* 0: bypass horizontal chrominance scaling unit */ +/* 1: enable horizontal chrominance scaling unit */ +#ifdef MRV_MRSZ_SCALE_HC_ENABLE_SHD +#define MRV_MRSZ_SCALE_HC_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */ +#define MRV_MRSZ_SCALE_HC_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */ +#endif /* MRV_MRSZ_SCALE_HC_ENABLE_SHD */ +/* Slice: scale_hy_enable_shd:*/ +/* 0: bypass horizontal luminance scaling unit */ +/* 1: enable horizontal luminance scaling unit */ +#ifdef MRV_MRSZ_SCALE_HY_ENABLE_SHD +#define MRV_MRSZ_SCALE_HY_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal luminance scaling unit */ +#define MRV_MRSZ_SCALE_HY_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */ +#endif /* MRV_MRSZ_SCALE_HY_ENABLE_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hy_shd: horizontal luminance scale factor shadow + * register (0x00000034) + * + *****************************************************************************/ +/* Slice: scale_hy_shd:*/ +/* This register is set to the horizontal luminance downscale factor or to the */ +/* reciprocal of the horizontal luminance upscale factor */ +#ifdef MRV_MRSZ_SCALE_HY_SHD +#endif /* MRV_MRSZ_SCALE_HY_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hcb_shd: horizontal Cb scale factor shadow register + * (0x00000038) + * + *****************************************************************************/ +/* Slice: scale_hcb_shd:*/ +/* This register is set to the horizontal Cb downscale factor or to the */ +/* reciprocal of the horizontal Cb upscale factor */ +#ifdef MRV_MRSZ_SCALE_HCB_SHD +#endif /* MRV_MRSZ_SCALE_HCB_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_scale_hcr_shd: horizontal Cr scale factor shadow register + * (0x0000003c) + * + *****************************************************************************/ +/* Slice: scale_hcr_shd:*/ +/* This register is set to the horizontal Cr downscale factor or to the */ +/* reciprocal of the horizontal Cr upscale factor */ +#ifdef MRV_MRSZ_SCALE_HCR_SHD +#endif /* MRV_MRSZ_SCALE_HCR_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_scale_vy_shd: vertical luminance scale factor shadow register + * (0x00000040) + * + *****************************************************************************/ +/* Slice: scale_vy_shd:*/ +/* This register is set to the vertical luminance downscale factor or to the */ +/* reciprocal of the vertical luminance upscale factor */ +#ifdef MRV_MRSZ_SCALE_VY_SHD +#endif /* MRV_MRSZ_SCALE_VY_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_scale_vc_shd: vertical chrominance scale factor shadow + * register (0x00000044) + * + *****************************************************************************/ +/* Slice: scale_vc_shd:*/ +/* This register is set to the vertical chrominance downscale factor or to */ +/* the reciprocal of the vertical chrominance upscale factor */ +#ifdef MRV_MRSZ_SCALE_VC_SHD +#endif /* MRV_MRSZ_SCALE_VC_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_phase_hy_shd: horizontal luminance phase shadow register + * (0x00000048) + * + *****************************************************************************/ +/* Slice: phase_hy_shd:*/ +/* This register is set to the horizontal luminance phase offset */ +#ifdef MRV_MRSZ_PHASE_HY_SHD +#endif /* MRV_MRSZ_PHASE_HY_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_phase_hc_shd: horizontal chrominance phase shadow register + * (0x0000004c) + * + *****************************************************************************/ +/* Slice: phase_hc_shd:*/ +/* This register is set to the horizontal chrominance phase offset */ +#ifdef MRV_MRSZ_PHASE_HC_SHD +#endif /* MRV_MRSZ_PHASE_HC_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_phase_vy_shd: vertical luminance phase shadow register + * (0x00000050) + * + *****************************************************************************/ +/* Slice: phase_vy_shd:*/ +/* This register is set to the vertical luminance phase offset */ +#ifdef MRV_MRSZ_PHASE_VY_SHD +#endif /* MRV_MRSZ_PHASE_VY_SHD */ +/*****************************************************************************/ +/** + * register: mrsz_phase_vc_shd: vertical chrominance phase shadow register + * (0x00000054) + * + *****************************************************************************/ +/* Slice: phase_vc_shd:*/ +/* This register is set to the vertical chrominance phase offset */ +#ifdef MRV_MRSZ_PHASE_VC_SHD +#endif /* MRV_MRSZ_PHASE_VC_SHD */ +/*****************************************************************************/ +/* Self Resizer/Scaler Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: srsz_ctrl: global control register (0x00000000) + * + *****************************************************************************/ +/* Slice: cfg_upd:*/ +/* write 0: nothing happens */ +/* write 1: update shadow registers */ +/* read: always 0 */ +#ifdef MRV_SRSZ_CFG_UPD +#endif /* MRV_SRSZ_CFG_UPD */ +/* Slice: scale_vc_up:*/ +/* 1: vertical chrominance upscaling selected */ +/* 0: vertical chrominance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_VC_UP +#define MRV_SRSZ_SCALE_VC_UP_UPSCALE 1 /* 1: vertical chrominance upscaling selected */ +#define MRV_SRSZ_SCALE_VC_UP_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_VC_UP */ +/* Slice: scale_vy_up:*/ +/* 1: vertical luminance upscaling selected */ +/* 0: vertical luminance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_VY_UP +#define MRV_SRSZ_SCALE_VY_UP_UPSCALE 1 /* 1: vertical luminance upscaling selected */ +#define MRV_SRSZ_SCALE_VY_UP_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_VY_UP */ +/* Slice: scale_hc_up:*/ +/* 1: horizontal chrominance upscaling selected */ +/* 0: horizontal chrominance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_HC_UP +#define MRV_SRSZ_SCALE_HC_UP_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */ +#define MRV_SRSZ_SCALE_HC_UP_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_HC_UP */ +/* Slice: scale_hy_up:*/ +/* 1: horizontal luminance upscaling selected */ +/* 0: horizontal luminance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_HY_UP +#define MRV_SRSZ_SCALE_HY_UP_UPSCALE 1 /* 1: horizontal luminance upscaling selected */ +#define MRV_SRSZ_SCALE_HY_UP_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_HY_UP */ +/* Slice: scale_vc_enable:*/ +/* 0: bypass vertical chrominance scaling unit */ +/* 1: enable vertical chrominance scaling unit */ +#ifdef MRV_SRSZ_SCALE_VC_ENABLE +#define MRV_SRSZ_SCALE_VC_ENABLE_PROCESS 1 /* 1: enable vertical chrominance scaling unit */ +#define MRV_SRSZ_SCALE_VC_ENABLE_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */ +#endif /* MRV_SRSZ_SCALE_VC_ENABLE */ +/* Slice: scale_vy_enable:*/ +/* 0: bypass vertical luminance scaling unit */ +/* 1: enable vertical luminance scaling unit */ +#ifdef MRV_SRSZ_SCALE_VY_ENABLE +#define MRV_SRSZ_SCALE_VY_ENABLE_PROCESS 1 /* 1: enable vertical luminance scaling unit */ +#define MRV_SRSZ_SCALE_VY_ENABLE_BYPASS 0 /* 0: bypass vertical luminance scaling unit */ +#endif /* MRV_SRSZ_SCALE_VY_ENABLE */ +/* Slice: scale_hc_enable:*/ +/* 0: bypass horizontal chrominance scaling unit */ +/* 1: enable horizontal chrominance scaling unit */ +#ifdef MRV_SRSZ_SCALE_HC_ENABLE +#define MRV_SRSZ_SCALE_HC_ENABLE_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */ +#define MRV_SRSZ_SCALE_HC_ENABLE_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */ +#endif /* MRV_SRSZ_SCALE_HC_ENABLE */ +/* Slice: scale_hy_enable:*/ +/* 0: bypass horizontal luminance scaling unit */ +/* 1: enable horizontal luminance scaling unit */ +#ifdef MRV_SRSZ_SCALE_HY_ENABLE +#define MRV_SRSZ_SCALE_HY_ENABLE_PROCESS 1 /* 1: enable horizontal luminance scaling unit */ +#define MRV_SRSZ_SCALE_HY_ENABLE_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */ +#endif /* MRV_SRSZ_SCALE_HY_ENABLE */ +/*****************************************************************************/ +/** + * register: srsz_scale_hy: horizontal luminance scale factor register + * (0x00000004) + * + *****************************************************************************/ +/* Slice: scale_hy:*/ +/* This register is set to the horizontal luminance downscale factor or to */ +/* the reciprocal of the horizontal luminance upscale factor */ +#ifdef MRV_SRSZ_SCALE_HY +#endif /* MRV_SRSZ_SCALE_HY */ +/*****************************************************************************/ +/** + * register: srsz_scale_hcb: horizontal Cb scale factor register (0x00000008) + * + *****************************************************************************/ +/* Slice: scale_hcb:*/ +/* This register is set to the horizontal Cb downscale factor or to the */ +/* reciprocal of the horizontal Cb upscale factor */ +#ifdef MRV_SRSZ_SCALE_HCB +#endif /* MRV_SRSZ_SCALE_HCB */ +/*****************************************************************************/ +/** + * register: srsz_scale_hcr: horizontal Cr scale factor register (0x0000000c) + * + *****************************************************************************/ +/* Slice: scale_hcr:*/ +/* This register is set to the horizontal Cr downscale factor or to the */ +/* reciprocal of the horizontal Cr upscale factor */ +#ifdef MRV_SRSZ_SCALE_HCR +#endif /* MRV_SRSZ_SCALE_HCR */ +/*****************************************************************************/ +/** + * register: srsz_scale_vy: vertical luminance scale factor register (0x00000010) + * + *****************************************************************************/ +/* Slice: scale_vy:*/ +/* This register is set to the vertical luminance downscale factor or to the */ +/* reciprocal of the vertical luminance upscale factor */ +#ifdef MRV_SRSZ_SCALE_VY +#endif /* MRV_SRSZ_SCALE_VY */ +/*****************************************************************************/ +/** + * register: srsz_scale_vc: vertical chrominance scale factor register (0x00000014) + * + *****************************************************************************/ +/* Slice: scale_vc:*/ +/* This register is set to the vertical chrominance downscale factor or to the */ +/* reciprocal of the vertical chrominance upscale factor */ +#ifdef MRV_SRSZ_SCALE_VC +#endif /* MRV_SRSZ_SCALE_VC */ +/*****************************************************************************/ +/** + * register: srsz_phase_hy: horizontal luminance phase register (0x00000018) + * + *****************************************************************************/ +/* Slice: phase_hy:*/ +/* This register is set to the horizontal luminance phase offset */ +#ifdef MRV_SRSZ_PHASE_HY +#endif /* MRV_SRSZ_PHASE_HY */ +/*****************************************************************************/ +/** + * register: srsz_phase_hc: horizontal chrominance phase register (0x0000001c) + * + *****************************************************************************/ +/* Slice: phase_hc:*/ +/* This register is set to the horizontal chrominance phase offset */ +#ifdef MRV_SRSZ_PHASE_HC +#endif /* MRV_SRSZ_PHASE_HC */ +/*****************************************************************************/ +/** + * register: srsz_phase_vy: vertical luminance phase register (0x00000020) + * + *****************************************************************************/ +/* Slice: phase_vy:*/ +/* This register is set to the vertical luminance phase offset */ +#ifdef MRV_SRSZ_PHASE_VY +#endif /* MRV_SRSZ_PHASE_VY */ +/*****************************************************************************/ +/** + * register: srsz_phase_vc: vertical chrominance phase register (0x00000024) + * + *****************************************************************************/ +/* Slice: phase_vc:*/ +/* This register is set to the vertical chrominance phase offset */ +#ifdef MRV_SRSZ_PHASE_VC +#endif /* MRV_SRSZ_PHASE_VC */ +/*****************************************************************************/ +/** + * register: srsz_scale_lut_addr: Address pointer of up-scaling look up table + * (0x00000028) + * + *****************************************************************************/ +/* Slice: scale_lut_addr:*/ +/* Pointer to entry of lookup table */ +#ifdef MRV_SRSZ_SCALE_LUT_ADDR +#endif /* MRV_SRSZ_SCALE_LUT_ADDR */ +/*****************************************************************************/ +/** + * register: srsz_scale_lut: Entry of up-scaling look up table (0x0000002c) + * + *****************************************************************************/ +/* Slice: scale_lut:*/ +/* Entry of lookup table at position scale_lut_addr. The lookup table must be */ +/* filled with appropriate values before the up-scaling functionality can be */ +/* used.*/ +#ifdef MRV_SRSZ_SCALE_LUT +#endif /* MRV_SRSZ_SCALE_LUT */ +/*****************************************************************************/ +/** + * register: srsz_ctrl_shd: global control shadow register (0x0030) + * + *****************************************************************************/ +/* Slice: scale_vc_up_shd:*/ +/* 1: vertical chrominance upscaling selected */ +/* 0: vertical chrominance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_VC_UP_SHD +#define MRV_SRSZ_SCALE_VC_UP_SHD_UPSCALE 1 /* 1: vertical chrominance upscaling selected */ +#define MRV_SRSZ_SCALE_VC_UP_SHD_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_VC_UP_SHD */ +/* Slice: scale_vy_up_shd:*/ +/* 1: vertical luminance upscaling selected */ +/* 0: vertical luminance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_VY_UP_SHD +#define MRV_SRSZ_SCALE_VY_UP_SHD_UPSCALE 1 /* 1: vertical luminance upscaling selected */ +#define MRV_SRSZ_SCALE_VY_UP_SHD_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_VY_UP_SHD */ +/* Slice: scale_hc_up_shd:*/ +/* 1: horizontal chrominance upscaling selected */ +/* 0: horizontal chrominance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_HC_UP_SHD +#define MRV_SRSZ_SCALE_HC_UP_SHD_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */ +#define MRV_SRSZ_SCALE_HC_UP_SHD_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_HC_UP_SHD */ +/* Slice: scale_hy_up_shd:*/ +/* 1: horizontal luminance upscaling selected */ +/* 0: horizontal luminance downscaling selected */ +#ifdef MRV_SRSZ_SCALE_HY_UP_SHD +#define MRV_SRSZ_SCALE_HY_UP_SHD_UPSCALE 1 /* 1: horizontal luminance upscaling selected */ +#define MRV_SRSZ_SCALE_HY_UP_SHD_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */ +#endif /* MRV_SRSZ_SCALE_HY_UP_SHD */ +/* Slice: scale_vc_enable_shd:*/ +/* 0: bypass vertical chrominance scaling unit */ +/* 1: enable vertical chrominance scaling unit */ +#ifdef MRV_SRSZ_SCALE_VC_ENABLE_SHD +#define MRV_SRSZ_SCALE_VC_ENABLE_SHD_PROCESS 1 /* 1: enable vertical chrominance scaling unit */ +#define MRV_SRSZ_SCALE_VC_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */ +#endif /* MRV_SRSZ_SCALE_VC_ENABLE_SHD */ +/* Slice: scale_vy_enable_shd:*/ +/* 0: bypass vertical luminance scaling unit */ +/* 1: enable vertical luminance scaling unit */ +#ifdef MRV_SRSZ_SCALE_VY_ENABLE_SHD +#define MRV_SRSZ_SCALE_VY_ENABLE_SHD_PROCESS 1 /* 1: enable vertical luminance scaling unit */ +#define MRV_SRSZ_SCALE_VY_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical luminance scaling unit */ +#endif /* MRV_SRSZ_SCALE_VY_ENABLE_SHD */ +/* Slice: scale_hc_enable_shd:*/ +/* 0: bypass horizontal chrominance scaling unit */ +/* 1: enable horizontal chrominance scaling unit */ +#ifdef MRV_SRSZ_SCALE_HC_ENABLE_SHD +#define MRV_SRSZ_SCALE_HC_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */ +#define MRV_SRSZ_SCALE_HC_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */ +#endif /* MRV_SRSZ_SCALE_HC_ENABLE_SHD */ +/* Slice: scale_hy_enable_shd:*/ +/* 0: bypass horizontal luminance scaling unit */ +/* 1: enable horizontal luminance scaling unit */ +#ifdef MRV_SRSZ_SCALE_HY_ENABLE_SHD +#define MRV_SRSZ_SCALE_HY_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal luminance scaling unit */ +#define MRV_SRSZ_SCALE_HY_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */ +#endif /* MRV_SRSZ_SCALE_HY_ENABLE_SHD */ +/*****************************************************************************/ +/** + * register: srsz_scale_hy_shd: horizontal luminance scale factor shadow + * register (0x00000034) + * + *****************************************************************************/ +/* Slice: scale_hy_shd:*/ +/* This register is set to the horizontal luminance downscale factor or to the */ +/* reciprocal of the horizontal luminance upscale factor */ +#ifdef MRV_SRSZ_SCALE_HY_SHD +#endif /* MRV_SRSZ_SCALE_HY_SHD */ +/*****************************************************************************/ +/** + * register: srsz_scale_hcb_shd: horizontal Cb scale factor shadow register + * (0x00000038) + * + *****************************************************************************/ +/* Slice: scale_hcb_shd:*/ +/* This register is set to the horizontal Cb downscale factor or to the */ +/* reciprocal of the horizontal Cb upscale factor */ +#ifdef MRV_SRSZ_SCALE_HCB_SHD +#endif /* MRV_SRSZ_SCALE_HCB_SHD */ +/*****************************************************************************/ +/** + * register: srsz_scale_hcr_shd: horizontal Cr scale factor shadow register + * (0x0000003c) + * + *****************************************************************************/ +/* Slice: scale_hcr_shd:*/ +/* This register is set to the horizontal Cr downscale factor or to the */ +/* reciprocal of the horizontal Cr upscale factor */ +#ifdef MRV_SRSZ_SCALE_HCR_SHD +#endif /* MRV_SRSZ_SCALE_HCR_SHD */ +/*****************************************************************************/ +/** + * register: srsz_scale_vy_shd: vertical luminance scale factor shadow register + * (0x00000040) + * + *****************************************************************************/ +/* Slice: scale_vy_shd:*/ +/* This register is set to the vertical luminance downscale factor or to the */ +/* reciprocal of the vertical luminance upscale factor */ +#ifdef MRV_SRSZ_SCALE_VY_SHD +#endif /* MRV_SRSZ_SCALE_VY_SHD */ +/*****************************************************************************/ +/** + * register: srsz_scale_vc_shd: vertical chrominance scale factor shadow + * register (0x00000044) + * + *****************************************************************************/ +/* Slice: scale_vc_shd:*/ +/* This register is set to the vertical chrominance downscale factor or to */ +/* the reciprocal of the vertical chrominance upscale factor */ +#ifdef MRV_SRSZ_SCALE_VC_SHD +#endif /* MRV_SRSZ_SCALE_VC_SHD */ +/*****************************************************************************/ +/** + * register: srsz_phase_hy_shd: horizontal luminance phase shadow register + * (0x00000048) + * + *****************************************************************************/ +/* Slice: phase_hy_shd:*/ +/* This register is set to the horizontal luminance phase offset */ +#ifdef MRV_SRSZ_PHASE_HY_SHD +#endif /* MRV_SRSZ_PHASE_HY_SHD */ +/*****************************************************************************/ +/** + * register: srsz_phase_hc_shd: horizontal chrominance phase shadow register + * (0x0000004c) + * + *****************************************************************************/ +/* Slice: phase_hc_shd:*/ +/* This register is set to the horizontal chrominance phase offset */ +#ifdef MRV_SRSZ_PHASE_HC_SHD +#endif /* MRV_SRSZ_PHASE_HC_SHD */ +/*****************************************************************************/ +/** + * register: srsz_phase_vy_shd: vertical luminance phase shadow register + * (0x00000050) + * + *****************************************************************************/ +/* Slice: phase_vy_shd:*/ +/* This register is set to the vertical luminance phase offset */ +#ifdef MRV_SRSZ_PHASE_VY_SHD +#endif /* MRV_SRSZ_PHASE_VY_SHD */ +/*****************************************************************************/ +/** + * register: srsz_phase_vc_shd: vertical chrominance phase shadow register + * (0x00000054) + * + *****************************************************************************/ +/* Slice: phase_vc_shd:*/ +/* This register is set to the vertical chrominance phase offset */ +#ifdef MRV_SRSZ_PHASE_VC_SHD +#endif /* MRV_SRSZ_PHASE_VC_SHD */ +/*****************************************************************************/ +/* Memory Interface Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: mi_ctrl: Global control register (0x0000) + * + *****************************************************************************/ +/* Slice: sp_output_format:*/ +/* Selects output format of self picture. For possible restrictions see sub-*/ +/* chapter "Picture Orientation" in chapter "Self Path Output Programming".*/ + /**/ +/* 111: reserved */ +/* 110: RGB 888 */ +/* 101: RGB 666 */ +/* 100: RGB 565 */ + /**/ +/* 011: YCbCr 4:4:4 */ +/* 010: YCbCr 4:2:2 */ +/* 001: YCbCr 4:2:0 */ +/* 000: YCbCr 4:0:0 */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +/* - for RGB output format the SP input format must be YCbCr 4:2:2 */ +#ifdef MRV_MI_SP_OUTPUT_FORMAT +#define MRV_MI_SP_OUTPUT_FORMAT_RGB888 6 /* 110: RGB 888 */ +#define MRV_MI_SP_OUTPUT_FORMAT_RGB666 5 /* 101: RGB 666 */ +#define MRV_MI_SP_OUTPUT_FORMAT_RGB565 4 /* 100: RGB 565 */ +#define MRV_MI_SP_OUTPUT_FORMAT_YUV444 3 /* 011: YCbCr 4:4:4 */ +#define MRV_MI_SP_OUTPUT_FORMAT_YUV422 2 /* 010: YCbCr 4:2:2 */ +#define MRV_MI_SP_OUTPUT_FORMAT_YUV420 1 /* 001: YCbCr 4:2:0 */ +#define MRV_MI_SP_OUTPUT_FORMAT_YUV400 0 /* 000: YCbCr 4:0:0 */ +#endif /* MRV_MI_SP_OUTPUT_FORMAT */ +/* Slice: sp_input_format:*/ +/* Selects input format of self picture. For possible restrictions see sub-*/ +/* chapter "Picture Orientation" in chapter "Self Path Output Programming".*/ + /**/ +/* 11: YCbCr 4:4:4 */ +/* 10: YCbCr 4:2:2 */ +/* 01: YCbCr 4:2:0 */ +/* 00: YCbCr 4:0:0 */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_INPUT_FORMAT +#define MRV_MI_SP_INPUT_FORMAT_YUV444 3 /* 11: YCbCr 4:4:4 */ +#define MRV_MI_SP_INPUT_FORMAT_YUV422 2 /* 10: YCbCr 4:2:2 */ +#define MRV_MI_SP_INPUT_FORMAT_YUV420 1 /* 01: YCbCr 4:2:0 */ +#define MRV_MI_SP_INPUT_FORMAT_YUV400 0 /* 00: YCbCr 4:0:0 */ +#endif /* MRV_MI_SP_INPUT_FORMAT */ +/* Slice: sp_write_format:*/ +/* Defines how YCbCr self picture data is written to memory. Ignored if */ +/* RGB conversion is chosen. With RGB conversion active the output format */ +/* is always interleaved.*/ + /**/ +/* 00: planar */ +/* 01: semi planar, for YCbCr 4:2:x */ +/* 10: interleaved (combined), for YCbCr 4:2:2 only */ +/* 11: reserved */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_WRITE_FORMAT +#define MRV_MI_SP_WRITE_FORMAT_PLANAR 0 /* 00: planar */ +#define MRV_MI_SP_WRITE_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */ +#define MRV_MI_SP_WRITE_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */ +#define MRV_MI_SP_WRITE_FORMAT_RGB_INTERLEAVED 0 /* 00: hw expects a 0 in RGB mode */ +#endif /* MRV_MI_SP_WRITE_FORMAT */ +/* Slice: mp_write_format:*/ +/* Defines how YCbCr main picture data is written to memory.*/ +/* Ignored if JPEG data is chosen.*/ +/* In YCbCr mode the following meaning is applicable */ +/* 00: planar */ +/* 01: semi planar, for YCbCr 4:2:x */ +/* 10: interleaved (combined), for YCbCr 4:2:2 only */ +/* 11: reserved */ +/* In RAW data mode the following meaning is applicable */ +/* 00: RAW 8 bit */ +/* 01: reserved */ +/* 10: RAW 12 bit */ +/* 11: reserved */ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the main path.*/ +#ifdef MRV_MI_MP_WRITE_FORMAT +#define MRV_MI_MP_WRITE_FORMAT_PLANAR 0 /* 00: planar */ +#define MRV_MI_MP_WRITE_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */ +#define MRV_MI_MP_WRITE_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */ +#define MRV_MI_MP_WRITE_FORMAT_RAW_8 0 /* 0x: RAW 8 bit */ +#define MRV_MI_MP_WRITE_FORMAT_RAW_12 2 /* 1x: RAW 12 bit */ +#endif /* MRV_MI_MP_WRITE_FORMAT */ +/* Slice: bp_write_format:*/ +/* In RAW data mode the following meaning is applicable */ +/* 00: RAW 8 bit */ +/* 01: RAW 10 bit */ +/* 10: RAW 12 bit */ +/* 11: reserved */ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the main path.*/ +#ifdef MRV_MI_BP_WRITE_RAWBIT +#define MRV_MI_BP_WRITE_RAWBIT_RAW_8 0 /* 0x: RAW 8 bit */ +#define MRV_MI_BP_WRITE_RAWBIT_RAW_10 1 /* 01x: RAW 10 bit */ +#define MRV_MI_BP_WRITE_RAWBIT_RAW_12 2 /* 10x: RAW 12 bit */ +#endif /* MRV_MI_BP_WRITE_RAWBIT */ +/* Slice: init_offset_en:*/ +/* Enables updating of the offset counters shadow registers for */ +/* main and self picture to the programmed register init values.*/ + /**/ +/* MI_MP/SP_Y/CB/CR_OFFS_CNT_INIT */ +/* -> MI_MP/SP_Y/CB/CR_OFFS_CNT_SHD */ + /**/ +/* The update will be executed either when a forced software */ +/* update occurs (in register MI_INIT bit cfg_upd = 1) or when */ +/* an automatic config update signal arrives at the MI input port.*/ +/* The latter is split into main and self picture. So only the */ +/* corresponding main/self shadow registers are affected.*/ +/* After a picture skip has been performed init_offset_en selects */ +/* between skip restart and skip init mode (see bit skip in */ +/* register MI_INIT).*/ +#ifdef MRV_MI_INIT_OFFSET_EN +#endif /* MRV_MI_INIT_OFFSET_EN */ +/* Slice: init_base_en:*/ +/* Enables updating of the base address and buffer size shadow */ +/* registers for main and self picture to the programmed register */ +/* init values.*/ + /**/ +/* MI_MP/SP_Y/CB/CR_BASE_AD_INIT */ +/* -> MI_MP/SP_Y/CB/CR_BASE_AD_SHD */ + /**/ +/* MI_MP/SP_Y/CB/CR_SIZE_INIT */ +/* -> MI_MP/SP_Y/CB/CR_SIZE_SHD */ + /**/ +/* The update will be executed either when a forced software */ +/* update occurs (in register MI_INIT bit cfg_upd = 1) or when */ +/* an automatic config update signal arrives at the MI input port.*/ +/* The latter is split into main and self picture. So only the */ +/* corresponding main/self shadow registers are affected.*/ +#ifdef MRV_MI_INIT_BASE_EN +#endif /* MRV_MI_INIT_BASE_EN */ +/* Slice: burst_len_chrom:*/ +/* Burst length for Cb or Cr data affecting write port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported. If rotation */ +/* is active, then only 4-beat bursts will be generated in self path,*/ +/* regardless of the setting here.*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the main and self path.*/ +#ifdef MRV_MI_BURST_LEN_CHROM +#define MRV_MI_BURST_LEN_CHROM_4 0 /* 0: 4-beat bursts */ +#define MRV_MI_BURST_LEN_CHROM_8 1 /* 1: 8-beat bursts */ +#define MRV_MI_BURST_LEN_CHROM_16 2 /* 2: 16-beat bursts */ +#endif /* MRV_MI_BURST_LEN_CHROM */ +/* Slice: burst_len_lum:*/ +/* Burst length for Y, JPEG, or raw data affecting write port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ + /**/ +/* Note: Programmed value becomes effective immediately. So write to */ +/* the register only if no picture data is sent to the main and self path.*/ +#ifdef MRV_MI_BURST_LEN_LUM +#define MRV_MI_BURST_LEN_LUM_4 0 /* 0: 4-beat bursts */ +#define MRV_MI_BURST_LEN_LUM_8 1 /* 1: 8-beat bursts */ +#define MRV_MI_BURST_LEN_LUM_16 2 /* 2: 16-beat bursts */ +#endif /* MRV_MI_BURST_LEN_LUM */ +/* Slice: last_pixel_sig_en:*/ +/* enables the last pixel signalization */ +/* 1: enabled */ +/* 0: disabled */ +#ifdef MRV_MI_LAST_PIXEL_SIG_EN +#define MRV_MI_LAST_PIXEL_SIG_EN_ENABLE 1 /* 1: enable last pixel signalization */ +#define MRV_MI_LAST_PIXEL_SIG_EN_DISABLE 0 /* 0: disable last pixel signalization */ +#endif /* MRV_MI_LAST_PIXEL_SIG_EN */ +/* Slice: 422noncosited:*/ +/* Enables self path YCbCr422non-co-sited -> YCbCr444 interpolation */ +/* 1: YCbCr422 data are non_co-sited (Cb and Cr samples */ +/* are centered between Y samples) so modified interpolation */ +/* is activated */ +/* 0: YCbCr422 data are co-sited (Y0 Cb0 and Cr0 are */ +/* sampled at the same position)*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_422NONCOSITED +#endif /* MRV_MI_422NONCOSITED */ +/* Slice: cbcr_full_range:*/ +/* Enables CbCr full range for self path YCbCr -> RGB conversion */ +/* 1: CbCr have full range (0..255)*/ +/* 0: CbCr have compressed range range (16..240)*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_CBCR_FULL_RANGE +#endif /* MRV_MI_CBCR_FULL_RANGE */ +/* Slice: y_full_range:*/ +/* Enables Y full range for self path YCbCr -> RGB conversion */ +/* 1: Y has full range (0..255)*/ +/* 0: Y has compressed range (16..235)*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_Y_FULL_RANGE +#endif /* MRV_MI_Y_FULL_RANGE */ +/* Slice: byte_swap:*/ +/* Enables change of byte order of the 32 bit output word at write port */ +/* 1: byte order is mirrored but the bit order within one byte doesn't */ +/* change */ +/* 0: no byte mirroring */ + /**/ +/* Note: Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the main and self path.*/ +#ifdef MRV_MI_BYTE_SWAP +#endif /* MRV_MI_BYTE_SWAP */ +/* Slice: rot:*/ +/* Rotation 90 degree counter clockwise of self picture, only in RGB */ +/* mode. For picture orientation and operation modes see sub-chapter */ +/* "Picture Orientation" in chapter "Self Path Output Programming".*/ + /**/ +/* For RGB 565 format the line length must be a multiple of 2. There */ +/* are no restrictions for RGB 888/666.*/ +/* 1: enabled */ +/* 0: disabled */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path. In */ +/* rotation mode only 4-beat bursts are supported for self-path.*/ +#ifdef MRV_MI_ROT +#endif /* MRV_MI_ROT */ +/* Slice: v_flip:*/ +/* Vertical flipping of self picture. For picture orientation and */ +/* operation modes see sub-chapter "Picture Orientation" in chapter */ +/* "Self Path Output Programming". For Y component the line length */ +/* in 4:2:x planar mode must be a multiple of 8, for all other component */ +/* modes a multiple of 4 and for RGB 565 a multiple of 2. There are */ +/* no restrictions for RGB 888/666.*/ + /**/ +/* 1: enabled */ +/* 0: disabled */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_V_FLIP +#endif /* MRV_MI_V_FLIP */ +/* Slice: h_flip:*/ +/* Horizontal flipping of self picture. For picture orientation and */ +/* operation modes see sub-chapter "Picture Orientation" in chapter */ +/* "Self Path Output Programming".*/ + /**/ +/* For Y component the line length in 4:2:x planar mode must be a */ +/* multiple of 8, for all other component modes a multiple of 4 and */ +/* for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/ + /**/ +/* 1: enabled */ +/* 0: disabled */ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the */ +/* register only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_H_FLIP +#endif /* MRV_MI_H_FLIP */ +/* Programmed value becomes effective (visible in shadow register)*/ +/* after a soft reset, a forced software update or an automatic */ +/* config update. Affects MI_IN and MI_OUT module.*/ +/* Slice: raw_enable:*/ +/* Enables raw data */ +/* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software update.*/ +/* Affects MI_IN and MI_OUT module.*/ +#ifndef MRV_MI_RAW_ENABLE +#define MRV_MI_RAW_ENABLE +#define MRV_MI_RAW_ENABLE_MASK 0x00000008 +#define MRV_MI_RAW_ENABLE_SHIFT 3 +#endif /* MRV_MI_RAW_ENABLE */ +/* Slice: dpcc_enable:*/ +/* Enables DPCC data */ +/* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software.*/ +/* Affects MI_IN and MI_OUT module.*/ +#ifndef MRV_MI_DPCC_ENABLE +#define MRV_MI_DPCC_ENABLE +#define MRV_MI_DPCC_ENABLE_MASK 0x0000000C +#define MRV_MI_DPCC_ENABLE_SHIFT 2 +#endif /* MRV_MI_JPEG_ENABLE */ +/* Slice: jpeg_enable:*/ +/* Enables JPEG data */ +/* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software.*/ +/* Affects MI_IN and MI_OUT module.*/ +#ifndef MRV_MI_JPEG_ENABLE +#define MRV_MI_JPEG_ENABLE +#define MRV_MI_JPEG_ENABLE_MASK 0x00000004 +#define MRV_MI_JPEG_ENABLE_SHIFT 2 +#endif /* MRV_MI_JPEG_ENABLE */ +/* Slice: sp_enable:*/ +/* Enables self picture data path.*/ +/* Programmed value becomes effective (visible in control shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Affects MI_IN and MI_OUT module.*/ +#ifndef MRV_MI_SP_ENABLE +#define MRV_MI_SP_ENABLE +#define MRV_MI_SP_ENABLE_MASK 0x00000002 +#define MRV_MI_SP_ENABLE_SHIFT 1 +#endif /* MRV_MI_SP_ENABLE */ +/* Slice: mp_enable:*/ +/* Enables main picture data path */ +/* Programmed value becomes effective (visible in control shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Affects MI_IN and MI_OUT module.*/ +#ifndef MRV_MI_MP_ENABLE +#define MRV_MI_MP_ENABLE +#define MRV_MI_MP_ENABLE_MASK 0x00000001 +#define MRV_MI_MP_ENABLE_SHIFT 0 +#endif /* MRV_MI_MP_ENABLE */ +/* Slice: path_enable:*/ +/* Enables data pathes of MI according to the following table:*/ + /**/ +/* 0000: disabled, no data is transferred */ +/* 0001: YUV data output, mainpath only (mp_enable only)*/ +/* 0010: self-path only, output data format depending on other settings (sp_enable only)*/ +/* 0011: YUV data output in mainpath and self-path image data active */ +/* 0100: JPEG data output, mainpath only (jpeg_enable only)*/ +/* 0101: not allowed */ +/* 0110: JPEG data output in mainpath and self-path image data active */ +/* 0111: not allowed */ +/* 1000: RAW data output, mainpath only (raw_enable only)*/ +/* 1001: defect pixel data on self-path, image data on mainpath */ +/* 1010: defect pixel data on mainpath, image data on self-path */ +/* 1011: not allowed */ +/* 1100: defect pixel data on self-path, JPEG data on mainpath */ +/* 1101: defect pixel data on mainpath only */ +/* 1110: defect pixel data on self-path only */ +/* 1111: defect pixel data on self-path, RAW data on mainpath */ +#ifdef MRV_MI_PATH_ENABLE +#endif /* MRV_MI_PATH_ENABLE */ +/*****************************************************************************/ +/** + * register: mi_init: Control register for address init and skip function + * (0x00000004) + * + *****************************************************************************/ +/* Slice: mi_cfg_upd:*/ +/* Forced configuration update. Leads to an immediate update of the shadow registers.*/ +/* Depending on the two init enable bits in the MI_CTRL register (init_offset_en and */ +/* init_base_en) the offset counter, base address and buffer size shadow registers */ +/* are also updated.*/ +#ifdef MRV_MI_MI_CFG_UPD +#endif /* MRV_MI_MI_CFG_UPD */ +/* Slice: mp_output_format:*/ +/* Selects output format of main picture.*/ +/* 1xxx: Reserved */ +/* 0111: RAW10 */ +/* 0110: JPEG */ +/* 0101: RAW8 */ +/* 0100: RAW12 */ + /**/ +/* 0011: YCbCr 4:4:4 */ +/* 0010: YCbCr 4:2:2 */ +/* 0001: YCbCr 4:2:0 */ +/* 0000: YCbCr 4:0:0 */ + /**/ +#ifdef MRV_MI_MP_OUTPUT_FORMAT +#define MRV_MI_MP_OUTPUT_FORMAT_RAW10 7 /* 0111: RAW10 */ +#define MRV_MI_MP_OUTPUT_FORMAT_JPEG 6 /* 0110: JPEG */ +#define MRV_MI_MP_OUTPUT_FORMAT_RAW8 5 /* 0101: RAW8 */ +#define MRV_MI_MP_OUTPUT_FORMAT_RAW12 4 /* 0100: RAW12 */ +#define MRV_MI_MP_OUTPUT_FORMAT_YUV444 3 /* 0011: YCbCr 4:4:4 */ +#define MRV_MI_MP_OUTPUT_FORMAT_YUV422 2 /* 0010: YCbCr 4:2:2 */ +#define MRV_MI_MP_OUTPUT_FORMAT_YUV420 1 /* 0001: YCbCr 4:2:0 */ +#define MRV_MI_MP_OUTPUT_FORMAT_YUV400 0 /* 0000: YCbCr 4:0:0 */ +#endif /* MRV_MI_MP_OUTPUT_FORMAT */ +/* Slice: mi_skip:*/ +/* Skip of current or next starting main picture:*/ +/* Aborts writing of main picture image data of the current frame to RAM (after the */ +/* current burst transmission has been completed). Further main picture data up to */ +/* the end of the current frame are discarded.*/ + /**/ +/* No further makroblock line interrupt (mblk_line), no wrap around interrupt for */ +/* main picture (wrap_mp_y/cb/cr) and no fill level interrupt (fill_mp_y) are generated.*/ + /**/ +/* Skip does not affect the generation of the main path frame end interrupt (mp_frame_end).*/ +/* Skip does not affect the processing of self picture and its corresponding interrupts */ +/* namely the self path frame end interrupt (sp_frame_end).*/ + /**/ +/* The byte counter (register MI_BYTE_CNT) is not affected. It produces the correct */ +/* number of JPEG or RAW data bytes at the end of the current (skipped) frame.*/ + /**/ +/* After a skip has been performed the offset counter for the main picture at the start */ +/* of the following frame are set depending on the bit init_offset_en in register MI_CTRL:*/ + /**/ +/* - Skip restart mode (init_offset_en = 0)*/ +/* The offset counters of the main picture are restarted at the old start values of */ +/* the previous skipped frame.*/ + /**/ +/* - Skip init mode (init_offset_en = 1)*/ +/* The offset counters of the main picture are initialized with the register contents */ +/* of the offset counter init registers without any additional forced software update */ +/* or automatic config update.*/ +#ifdef MRV_MI_MI_SKIP +#endif /* MRV_MI_MI_SKIP */ +/*****************************************************************************/ +/** + * register: mi_mp_y_base_ad_init: Base address for main picture Y component, + * JPEG or raw data (0x00000008) + * + *****************************************************************************/ +/* Slice: mp_y_base_ad_init:*/ +/* Base address of main picture Y component ring buffer, JPEG ring buffer or raw */ +/* data ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_BASE_AD_INIT +#define MRV_MI_MP_Y_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_Y_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_y_size_init: Size of main picture Y component, JPEG or raw + * data (0x0000000c) + * + *****************************************************************************/ +/* Slice: mp_y_size_init:*/ +/* Size of main picture Y component ring buffer, JPEG ring buffer or raw data */ +/* ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_SIZE_INIT +#define MRV_MI_MP_Y_SIZE_INIT_VALID_MASK (MRV_MI_MP_Y_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_y_offs_cnt_init: Offset counter init value for main picture + * Y, JPEG or raw data (0x00000010) + * + *****************************************************************************/ +/* Slice: mp_y_offs_cnt_init:*/ +/* Offset counter init value of main picture Y component ring buffer, JPEG ring */ +/* buffer or raw data ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_OFFS_CNT_INIT +#define MRV_MI_MP_Y_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_y_offs_cnt_start: Offset counter start value for main picture + * Y, JPEG or raw data (0x00000014) + * + *****************************************************************************/ +/* Slice: mp_y_offs_cnt_start:*/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (main picture Y component, JPEG or raw data). Updated at */ +/* frame end.*/ + /**/ +/* Note: A soft reset resets the contents to the reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_OFFS_CNT_START +#define MRV_MI_MP_Y_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_mp_y_irq_offs_init: Fill level interrupt offset value for main + * picture Y, JPEG or raw data (0x00000018) + * + *****************************************************************************/ +/* Slice: mp_y_irq_offs_init:*/ +/* Reaching this programmed value by the current offset counter for addressing */ +/* main picture Y component, JPEG or raw data leads to generation of fill level */ +/* interrupt fill_mp_y.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_IRQ_OFFS_INIT +#define MRV_MI_MP_Y_IRQ_OFFS_INIT_VALID_MASK (MRV_MI_MP_Y_IRQ_OFFS_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_IRQ_OFFS_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_base_ad_init: Base address for main picture Cb component + * ring buffer (0x0000001c) + * + *****************************************************************************/ +/* Slice: mp_cb_base_ad_init:*/ +/* Base address of main picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or */ +/* automatic update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_BASE_AD_INIT +#define MRV_MI_MP_CB_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_CB_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CB_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_size_init: Size of main picture Cb component ring buffer + * (0x00000020) + * + *****************************************************************************/ +/* Slice: mp_cb_size_init:*/ +/* Size of main picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or */ +/* automatic update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_SIZE_INIT +#define MRV_MI_MP_CB_SIZE_INIT_VALID_MASK (MRV_MI_MP_CB_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CB_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_offs_cnt_init: Offset counter init value for main picture + * Cb component ring buffer (0x00000024) + * + *****************************************************************************/ +/* Slice: mp_cb_offs_cnt_init:*/ +/* Offset counter init value of main picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect. Check exceptional handling in skip modes.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_OFFS_CNT_INIT +#define MRV_MI_MP_CB_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_CB_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CB_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_offs_cnt_start: Offset counter start value for main + * picture Cb component ring buffer (0x00000028) + * + *****************************************************************************/ +/* Slice: mp_cb_offs_cnt_start:*/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (main picture Cb component). Updated at frame end.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_OFFS_CNT_START +#define MRV_MI_MP_CB_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_CB_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CB_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_base_ad_init: Base address for main picture Cr component + * ring buffer (0x0000002c) + * + *****************************************************************************/ +/* Slice: mp_cr_base_ad_init:*/ +/* Base address of main picture Cr component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_BASE_AD_INIT +#define MRV_MI_MP_CR_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_CR_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CR_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_size_init: Size of main picture Cr component ring buffer + * (0x00000030) + * + *****************************************************************************/ +/* Slice: mp_cr_size_init:*/ +/* Size of main picture Cr component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_SIZE_INIT +#define MRV_MI_MP_CR_SIZE_INIT_VALID_MASK (MRV_MI_MP_CR_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CR_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_offs_cnt_init: Offset counter init value for main + * picture Cr component ring buffer (0x00000034) + * + *****************************************************************************/ +/* Slice: mp_cr_offs_cnt_init:*/ +/* Offset counter init value of main picture Cr component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect. Check exceptional handling in skip modes.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_OFFS_CNT_INIT +#define MRV_MI_MP_CR_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_CR_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CR_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_offs_cnt_start: Offset counter start value for main + * picture Cr component ring buffer (0x00000038) + * + *****************************************************************************/ +/* Slice: mp_cr_offs_cnt_start:*/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (main picture Cr component). Updated at frame end.*/ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_OFFS_CNT_START +#define MRV_MI_MP_CR_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_CR_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_MP_CR_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_sp_y_base_ad_init: Base address for self picture Y component + * ring buffer (0x0000003c) + * + *****************************************************************************/ +/* Slice: sp_y_base_ad_init:*/ +/* Base address of self picture Y component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_BASE_AD_INIT +#define MRV_MI_SP_Y_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_Y_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_Y_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_y_size_init: Size of self picture Y component ring buffer + * (0x00000040) + * + *****************************************************************************/ +/* Slice: sp_y_size_init:*/ +/* Size of self picture Y component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or */ +/* automatic update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_SIZE_INIT +#define MRV_MI_SP_Y_SIZE_INIT_VALID_MASK (MRV_MI_SP_Y_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_Y_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_y_offs_cnt_init: Offset counter init value for self + * picture Y component ring buffer (0x00000044) + * + *****************************************************************************/ +/* Slice: sp_y_offs_cnt_init:*/ +/* Offset counter init value of self picture Y component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or */ +/* automatic update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_OFFS_CNT_INIT +#define MRV_MI_SP_Y_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_Y_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_Y_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_y_offs_cnt_start: Offset counter start value for self + * picture Y component ring buffer (0x00000048) + * + *****************************************************************************/ +/* Slice: sp_y_offs_cnt_start:*/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (self picture Y component). Updated at frame end.*/ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_OFFS_CNT_START +#define MRV_MI_SP_Y_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_Y_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_SP_Y_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_sp_y_llength: Line length of self picture Y component (0x0000004c) + * + *****************************************************************************/ +/* Slice: sp_y_llength:*/ +/* Line length of self picture Y component or RGB picture in pixel, also */ +/* known as line stride.*/ + /**/ +/* If no line stride is used, line length must match image width.*/ + /**/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8,*/ +/* for all other component modes a multiple of 4 and for RGB 565 a multiple of 2.*/ +/* There are no restrictions for RGB 888/666.*/ + /**/ +/* In planar mode the line length of the Cb and Cr component is assumed according */ +/* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi */ +/* planar 4:2:x mode the line length of the Cb and Cr component is assumed the */ +/* same size.*/ + /**/ +/* Note:*/ +/* - Line length always refers to the line length of the output image. This */ +/* is particularly important when rotating.*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the register */ +/* only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_Y_LLENGTH +#define MRV_MI_SP_Y_LLENGTH_VALID_MASK (MRV_MI_SP_Y_LLENGTH_MASK & ~0x00000000) +#endif /* MRV_MI_SP_Y_LLENGTH */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_base_ad_init: Base address for self picture Cb component + * ring buffer (0x00000050) + * + *****************************************************************************/ +/* Slice: sp_cb_base_ad_init:*/ +/* Base address of self picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note: Set control bit init_base_en before updating so that a forced or */ +/* automatic update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_BASE_AD_INIT +#define MRV_MI_SP_CB_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_CB_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CB_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_size_init: Size of self picture Cb component ring buffer + * (0x00000054) + * + *****************************************************************************/ +/* Slice: sp_cb_size_init:*/ +/* Size of self picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_SIZE_INIT +#define MRV_MI_SP_CB_SIZE_INIT_VALID_MASK (MRV_MI_SP_CB_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CB_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_offs_cnt_init: Offset counter init value for self picture + * Cb component ring buffer (0x00000058) + * + *****************************************************************************/ +/* Slice: sp_cb_offs_cnt_init:*/ +/* Offset counter init value of self picture Cb component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_OFFS_CNT_INIT +#define MRV_MI_SP_CB_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_CB_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CB_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_offs_cnt_start: Offset counter start value for self + * picture Cb component ring buffer (0x0000005c) + * + *****************************************************************************/ +/* Slice: sp_cb_offs_cnt_start:*/ + /**/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (self picture Cb component). Updated at frame end.*/ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_OFFS_CNT_START +#define MRV_MI_SP_CB_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_CB_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CB_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_base_ad_init: Base address for self picture Cr component + * ring buffer (0x00000060) + * + *****************************************************************************/ +/* Slice: sp_cr_base_ad_init:*/ +/* Base address of self picture Cr component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_BASE_AD_INIT +#define MRV_MI_SP_CR_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_CR_BASE_AD_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CR_BASE_AD_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_size_init: Size of self picture Cr component ring buffer + * (0x00000064) + * + *****************************************************************************/ +/* Slice: sp_cr_size_init:*/ +/* Size of self picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_SIZE_INIT +#define MRV_MI_SP_CR_SIZE_INIT_VALID_MASK (MRV_MI_SP_CR_SIZE_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CR_SIZE_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_offs_cnt_init: Offset counter init value for self + * picture Cr component ring buffer (0x00000068) + * + *****************************************************************************/ +/* Slice: sp_cr_offs_cnt_init:*/ +/* Offset counter init value of self picture Cr component ring buffer.*/ + /**/ +/* Programmed value becomes effective (visible in corresponding shadow register)*/ +/* after a soft reset, a forced software update or an automatic config update.*/ + /**/ +/* Note:*/ +/* - Set control bit init_base_en before updating so that a forced or automatic */ +/* update can take effect.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_OFFS_CNT_INIT +#define MRV_MI_SP_CR_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_CR_OFFS_CNT_INIT_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CR_OFFS_CNT_INIT */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_offs_cnt_start: Offset counter start value for self + * picture Cr component ring buffer (0x0000006c) + * + *****************************************************************************/ +/* Slice: sp_cr_offs_cnt_start:*/ +/* Offset counter value which points to the start address of the previously */ +/* processed picture (self picture Cr component). Updated at frame end.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_OFFS_CNT_START +#define MRV_MI_SP_CR_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_CR_OFFS_CNT_START_MASK & ~0x00000007) +#endif /* MRV_MI_SP_CR_OFFS_CNT_START */ +/*****************************************************************************/ +/** + * register: mi_byte_cnt: Counter value of JPEG or RAW data bytes (0x00000070) + * + *****************************************************************************/ +/* Slice: byte_cnt:*/ +/* Counter value specifies the number of JPEG or RAW data bytes of the last */ +/* transmitted frame. Updated at frame end.*/ + /**/ +/* A soft reset will set the byte counter to zero.*/ +#ifdef MRV_MI_BYTE_CNT +#endif /* MRV_MI_BYTE_CNT */ +/*****************************************************************************/ +/** + * register: mi_ctrl_shd: global control internal shadow register (0x00000074) + * + *****************************************************************************/ +/* Slice: path_enable_out:*/ +/* path_enable shadow register for module MI_OUT (former raw_enable_out,*/ +/* jpeg_enable_out, sp_enable_out, mp_enable_out)*/ +#ifdef MRV_MI_PATH_ENABLE_OUT +#endif /* MRV_MI_PATH_ENABLE_OUT */ +/* Slice: path_enable_in:*/ +/* path_enable shadow register for module MI_IN (former raw_enable_in,*/ +/* jpeg_enable_in, sp_enable_in, mp_enable_in)*/ +#ifdef MRV_MI_PATH_ENABLE_IN +#endif /* MRV_MI_PATH_ENABLE_IN */ +/*****************************************************************************/ +/** + * register: mi_mp_y_base_ad_shd: Base address shadow register for main + * picture Y component, JPEG or raw data ring buffer (0x00000078) + * + *****************************************************************************/ +/* Slice: mp_y_base_ad:*/ +/* Base address of main picture Y component ring buffer, JPEG ring buffer or */ +/* raw data ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_BASE_AD +#define MRV_MI_MP_Y_BASE_AD_VALID_MASK (MRV_MI_MP_Y_BASE_AD_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_mp_y_size_shd: Size shadow register of main picture Y component, + * JPEG or raw data (0x0000007c) + * + *****************************************************************************/ +/* Slice: mp_y_size:*/ +/* Size of main picture Y component ring buffer, JPEG ring buffer or raw data */ +/* ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_SIZE +#define MRV_MI_MP_Y_SIZE_VALID_MASK (MRV_MI_MP_Y_SIZE_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_SIZE */ +/*****************************************************************************/ +/** + * register: mi_mp_y_offs_cnt_shd: Current offset counter of main picture Y + * component, JPEG or raw data ring buffer (0x00000080) + * + *****************************************************************************/ +/* Slice: mp_y_offs_cnt:*/ +/* Current offset counter of main picture Y component, JPEG or raw data ring */ +/* buffer for address generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_OFFS_CNT +#define MRV_MI_MP_Y_OFFS_CNT_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_MASK & ~0x00000007) +#endif /* MRV_MI_MP_Y_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_mp_y_irq_offs_shd: Shadow register of fill level interrupt + * offset value for main picture Y component, JPEG or raw data + * (0x00000084) + * + *****************************************************************************/ +/* Slice: mp_y_irq_offs:*/ +/* Reaching this offset value by the current offset counter for addressing */ +/* main picture Y component, JPEG or raw data leads to generation of fill */ +/* level interrupt fill_mp_y.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_Y_IRQ_OFFS +#endif /* MRV_MI_MP_Y_IRQ_OFFS */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_base_ad_shd: Base address shadow register for main + * picture Cb component ring buffer (0x00000088) + * + *****************************************************************************/ +/* Slice: mp_cb_base_ad:*/ +/* Base address of main picture Cb component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_BASE_AD +#endif /* MRV_MI_MP_CB_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_size_shd: Size shadow register of main picture Cb + * component ring buffer (0x0000008c) + * + *****************************************************************************/ +/* Slice: mp_cb_size:*/ +/* Size of main picture Cb component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_SIZE +#endif /* MRV_MI_MP_CB_SIZE */ +/*****************************************************************************/ +/** + * register: mi_mp_cb_offs_cnt_shd: Current offset counter of main picture Cb + * component ring buffer (0x00000090) + * + *****************************************************************************/ +/* Slice: mp_cb_offs_cnt:*/ +/* Current offset counter of main picture Cb component ring buffer for address */ +/* generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CB_OFFS_CNT +#endif /* MRV_MI_MP_CB_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_base_ad_shd: Base address shadow register for main + * picture Cr component ring buffer (0x00000094) + * + *****************************************************************************/ +/* Slice: mp_cr_base_ad:*/ +/* Base address of main picture Cr component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_BASE_AD +#endif /* MRV_MI_MP_CR_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_size_shd: Size shadow register of main picture Cr + * component ring buffer (0x00000098) + * + *****************************************************************************/ +/* Slice: mp_cr_size:*/ +/* Size of main picture Cr component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_SIZE +#endif /* MRV_MI_MP_CR_SIZE */ +/*****************************************************************************/ +/** + * register: mi_mp_cr_offs_cnt_shd: Current offset counter of main picture Cr + * component ring buffer (0x0000009c) + * + *****************************************************************************/ +/* Slice: mp_cr_offs_cnt:*/ +/* Current offset counter of main picture Cr component ring buffer for */ +/* address generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_MP_CR_OFFS_CNT +#endif /* MRV_MI_MP_CR_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_sp_y_base_ad_shd: Base address shadow register for self + * picture Y component ring buffer (0x000000a0) + * + *****************************************************************************/ +/* Slice: sp_y_base_ad:*/ +/* Base address of self picture Y component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_BASE_AD +#endif /* MRV_MI_SP_Y_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_sp_y_size_shd: Size shadow register of self picture Y + * component ring buffer (0x000000a4) + * + *****************************************************************************/ +/* Slice: sp_y_size:*/ +/* Size of self picture Y component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_SIZE +#endif /* MRV_MI_SP_Y_SIZE */ +/*****************************************************************************/ +/** + * register: mi_sp_y_offs_cnt_shd: Current offset counter of self picture Y + * component ring buffer (0x000000a8) + * + *****************************************************************************/ +/* Slice: sp_y_offs_cnt:*/ +/* Current offset counter of self picture Y component ring buffer for address generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_Y_OFFS_CNT +#endif /* MRV_MI_SP_Y_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_base_ad_shd: Base address shadow register for self + * picture Cb component ring buffer (0x000000b0) + * + *****************************************************************************/ +/* Slice: sp_cb_base_ad:*/ +/* Base address of self picture Cb component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_BASE_AD +#endif /* MRV_MI_SP_CB_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_size_shd: Size shadow register of self picture Cb + * component ring buffer (0x000000b4) + * + *****************************************************************************/ +/* Slice: sp_cb_size:*/ +/* Size of self picture Cb component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_SIZE +#endif /* MRV_MI_SP_CB_SIZE */ +/*****************************************************************************/ +/** + * register: mi_sp_cb_offs_cnt_shd: Current offset counter of self picture + * Cb component ring buffer (0x000000b8) + * + *****************************************************************************/ +/* Slice: sp_cb_offs_cnt:*/ +/* Current offset counter of self picture Cb component ring buffer for */ +/* address generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CB_OFFS_CNT +#endif /* MRV_MI_SP_CB_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_base_ad_shd: Base address shadow register for self + * picture Cr component ring buffer (0x000000bc) + * + *****************************************************************************/ +/* Slice: sp_cr_base_ad:*/ +/* Base address of self picture Cr component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_BASE_AD +#endif /* MRV_MI_SP_CR_BASE_AD */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_size_shd: Size shadow register of self picture Cr + * component ring buffer (0x000000c0) + * + *****************************************************************************/ +/* Slice: sp_cr_size:*/ +/* Size of self picture Cr component ring buffer.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_SIZE +#endif /* MRV_MI_SP_CR_SIZE */ +/*****************************************************************************/ +/** + * register: mi_sp_cr_offs_cnt_shd: Current offset counter of self picture Cr + * component ring buffer (0x000000c4) + * + *****************************************************************************/ +/* Slice: sp_cr_offs_cnt:*/ +/* Current offset counter of self picture Cr component ring buffer for */ +/* address generation */ + /**/ +/* Note:*/ +/* - Soft reset will reset the contents to reset value.*/ + /**/ +/* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/ +#ifdef MRV_MI_SP_CR_OFFS_CNT +#endif /* MRV_MI_SP_CR_OFFS_CNT */ +/*****************************************************************************/ +/** + * register: mi_dma_y_pic_start_ad: Y component image start address (0x000000c8) + * + *****************************************************************************/ +/* Slice: dma_y_pic_start_ad:*/ +/* Image start address of the y component */ + /**/ +/* Note:*/ +/* - Must be multiple of 4 in interleaved mode.*/ +#ifdef MRV_MI_DMA_Y_PIC_START_AD +#endif /* MRV_MI_DMA_Y_PIC_START_AD */ +/*****************************************************************************/ +/** + * register: mi_dma_y_pic_width: Y component image width (0x000000cc) + * + *****************************************************************************/ +/* Slice: dma_y_pic_width:*/ +/* Image width of the Y component in pixel.*/ + /**/ +/* For YCbCr 4:2:x the image width must be a multiple of 2.*/ + /**/ +/* In planar mode the image width of the Cb and Cr component is assumed */ +/* according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/ + /**/ +/* In semi planar 4:2:x mode the image width of the Cb component (which includes Cr)*/ +/* is assumed the same size.*/ + /**/ +/* In interleave mode no Cb/Cr image width is used.*/ +#ifdef MRV_MI_DMA_Y_PIC_WIDTH +#endif /* MRV_MI_DMA_Y_PIC_WIDTH */ +/*****************************************************************************/ +/** + * register: mi_dma_y_llength: Y component original line length (0x000000d0) + * + *****************************************************************************/ +/* Slice: dma_y_llength:*/ +/* Line length of the Y component of the original image in memory */ + /**/ +/* For an uncropped image, where lines follow each other without offset */ +/* (no line stride), line length must match image width.*/ + /**/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8,*/ +/* for all other component modes a multiple of 4.*/ + /**/ +/* In planar mode the line length of the Cb and Cr component is assumed according */ +/* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/ + /**/ +/* In semi planar 4:2:x mode the line length of the Cb component (which includes Cr)*/ +/* is assumed the same size.*/ + /**/ +/* In interleave mode no Cb/Cr line length is used.*/ +#ifdef MRV_MI_DMA_Y_LLENGTH +#endif /* MRV_MI_DMA_Y_LLENGTH */ +/*****************************************************************************/ +/** + * register: mi_dma_y_pic_size: Y component image size (0x000000d4) + * + *****************************************************************************/ +/* Slice: dma_y_pic_size:*/ +/* Image size of the Y component in pixel which has to be the Y line length */ +/* multiplied by the Y image height (dma_y_llength * dma_y_pic_height).*/ + /**/ +/* In planar mode the image size of the Cb and Cr component is assumed according */ +/* to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same */ +/* for 4:4:4.*/ + /**/ +/* In semi planar mode the image size of the Cb component (which includes Cr)*/ +/* is assumed half for 4:2:0 and the same size for 4:2:2.*/ + /**/ +/* In interleave mode no Cb/Cr image size is used.*/ +#ifdef MRV_MI_DMA_Y_PIC_SIZE +#endif /* MRV_MI_DMA_Y_PIC_SIZE */ +/*****************************************************************************/ +/** + * register: mi_dma_cb_pic_start_ad: Cb component image start address (0x000000d8) + * + *****************************************************************************/ +/* Slice: dma_cb_pic_start_ad:*/ +/* Image start address of the Cb component */ + /**/ +/* Note:*/ +/* - Must be multiple of 2 in semi-planar mode.*/ +#ifdef MRV_MI_DMA_CB_PIC_START_AD +#endif /* MRV_MI_DMA_CB_PIC_START_AD */ +/*****************************************************************************/ +/** + * register: mi_dma_cr_pic_start_ad: Cr component image start address (0x000000e8) + * + *****************************************************************************/ +/* Slice: dma_cr_pic_start_ad:*/ +/* Image start address of the Cr component */ +#ifdef MRV_MI_DMA_CR_PIC_START_AD +#endif /* MRV_MI_DMA_CR_PIC_START_AD */ +/*****************************************************************************/ +/** + * register: mi_imsc: Interrupt Mask Register (0x000000f8) + * mi_ris : Raw Interrupt Status Register (0x000000fc) + * mi_mis : Masked Interrupt Status Register (0x00000100) + * mi_icr : Interrupt Clear Register (0x00000104) + * mi_isr : Interrupt Set Register (0x00000108) + * + * ('1': interrupt active, '0': interrupt masked) + * + *****************************************************************************/ +/* Slice: dma_ready:*/ +/* Mask bit for dma ready interrupt */ +#ifndef MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0 +#endif /* MRV_MI_DMA_READY */ +/* Slice: wrap_sp_cr:*/ +/* Mask bit for self picture Cr address wrap interrupt */ +#ifndef MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0 +#endif /* MRV_MI_WRAP_SP_CR */ +/* Slice: wrap_sp_cb:*/ +/* Mask bit for self picture Cb address wrap interrupt */ +#ifndef MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0 +#endif /* MRV_MI_WRAP_SP_CB */ +/* Slice: wrap_sp_y:*/ +/* Mask bit for self picture Y address wrap interrupt */ +#ifndef MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0 +#endif /* MRV_MI_WRAP_SP_Y */ +/* Slice: wrap_mp_cr:*/ +/* Mask bit for main picture Cr address wrap interrupt */ +#ifndef MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0 +#endif /* MRV_MI_WRAP_MP_CR */ +/* Slice: wrap_mp_cb:*/ +/* Mask bit for main picture Cb address wrap interrupt */ +#ifndef MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0 +#endif /* MRV_MI_WRAP_MP_CB */ +/* Slice: wrap_mp_y:*/ +/* Mask bit for main picture Y address wrap interrupt */ +#ifndef MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0 +#endif /* MRV_MI_WRAP_MP_Y */ +/* Slice: fill_mp_y:*/ +/* Mask bit for fill level interrupt of main picture Y,*/ +/* JPEG or raw data */ +#ifndef MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0 +#endif /* MRV_MI_FILL_MP_Y */ +/* Slice: mblk_line:*/ +/* Mask bit for makroblock line interrupt of main picture */ +/* (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written */ +/* into RAM)*/ +#ifndef MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0 +#endif /* MRV_MI_MBLK_LINE */ +/* Slice: sp_frame_end:*/ +/* Mask self picture end of frame interrupt */ +#ifndef MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0 +#endif /* MRV_MI_SP_FRAME_END */ +/* Slice: mp_frame_end:*/ +/* Mask main picture end of frame interrupt */ +#ifndef MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0 +#endif /* MRV_MI_MP_FRAME_END */ +/* combination of all interrupt lines */ +#define MRV_MI_ALL_IRQS +#define MRV_MI_ALL_IRQS_MASK \ +(0 \ + | MRV_MI_DMA_READY_MASK \ + | MRV_MI_AHB_ERROR_MASK \ + | MRV_MI_WRAP_SP_CR_MASK \ + | MRV_MI_WRAP_SP_CB_MASK \ + | MRV_MI_WRAP_SP_Y_MASK \ + | MRV_MI_WRAP_MP_CR_MASK \ + | MRV_MI_WRAP_MP_CB_MASK \ + | MRV_MI_WRAP_MP_Y_MASK \ + | MRV_MI_FILL_MP_Y_MASK \ + | MRV_MI_MBLK_LINE_MASK \ + | MRV_MI_SP_FRAME_END_MASK \ + | MRV_MI_DMA_FRAME_END_MASK \ + | MRV_MI_MP_FRAME_END_MASK \ +) +#define MRV_MI_ALL_IRQS_SHIFT 0U +/*****************************************************************************/ +/** + * register: mi_status : MI Status Register (0x0000010c) + * mi_status_clr: MI Status Clear Register (0x00000110) + * + *****************************************************************************/ +/* Slice: sp_cr_fifo_full:*/ +/* FIFO full flag of Cr FIFO in self path asserted since last clear */ +#ifndef MRV_MI_SP_CR_FIFO_FULL +#define MRV_MI_SP_CR_FIFO_FULL_MASK 0U +#endif /* MRV_MI_SP_CR_FIFO_FULL */ +/* Slice: sp_cb_fifo_full:*/ +/* FIFO full flag of Cb FIFO in self path asserted since last clear */ +#ifndef MRV_MI_SP_CB_FIFO_FULL +#define MRV_MI_SP_CB_FIFO_FULL_MASK 0U +#endif /* MRV_MI_SP_CB_FIFO_FULL */ +/* Slice: sp_y_fifo_full:*/ +/* FIFO full flag of Y FIFO in self path asserted since last clear */ +#ifndef MRV_MI_SP_Y_FIFO_FULL +#define MRV_MI_SP_Y_FIFO_FULL_MASK 0U +#endif /* MRV_MI_SP_Y_FIFO_FULL */ +/* Slice: mp_cr_fifo_full:*/ +/* FIFO full flag of Cr FIFO in main path asserted since last clear */ +#ifndef MRV_MI_MP_CR_FIFO_FULL +#define MRV_MI_MP_CR_FIFO_FULL_MASK 0U +#endif /* MRV_MI_MP_CR_FIFO_FULL */ +/* Slice: mp_cb_fifo_full:*/ +/* FIFO full flag of Cb FIFO in main path asserted since last clear */ +#ifndef MRV_MI_MP_CB_FIFO_FULL +#define MRV_MI_MP_CB_FIFO_FULL_MASK 0U +#endif /* MRV_MI_MP_CB_FIFO_FULL */ +/* Slice: mp_y_fifo_full:*/ +/* FIFO full flag of Y FIFO in main path asserted since last clear */ +#ifndef MRV_MI_MP_Y_FIFO_FULL +#define MRV_MI_MP_Y_FIFO_FULL_MASK 0U +#endif /* MRV_MI_MP_Y_FIFO_FULL */ +/* combination of all MI status lines */ +#define MRV_MI_ALL_STAT +#define MRV_MI_ALL_STAT_MASK \ +(0 \ + | MRV_MI_SP_CR_FIFO_FULL_MASK \ + | MRV_MI_SP_CB_FIFO_FULL_MASK \ + | MRV_MI_SP_Y_FIFO_FULL_MASK \ + | MRV_MI_MP_CR_FIFO_FULL_MASK \ + | MRV_MI_MP_CB_FIFO_FULL_MASK \ + | MRV_MI_MP_Y_FIFO_FULL_MASK \ +) +#define MRV_MI_ALL_STAT_SHIFT 0U +/*****************************************************************************/ +/** + * register: mi_sp_y_pic_width: Y component image width (0x00000114) + * + *****************************************************************************/ +/* Slice: sp_y_pic_width:*/ +/* Image width of the self picture Y component or RGB picture in pixel.*/ + /**/ +/* For YCbCr 4:2:x and RGB 565 the image width must be a multiple of 2.*/ +/* If no line stride is used but flipping required, the image width must be */ +/* a multiple of 8 for 4:2:x planar or 4 for 4:4:4 planar/4:2:x semi planar.*/ + /**/ +/* There are no restrictions for RGB 888/666.*/ + /**/ +/* In planar mode the image width of the Cb and Cr component is assumed according */ +/* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/ + /**/ +/* In semi planar 4:2:x mode the image width of the Cb component (which includes Cr)*/ +/* is assumed the same size.*/ + /**/ +/* In interleave mode no Cb/Cr image width is used.*/ +/* Note:*/ +/* - Image width always refers to the picture width of the output image. This is */ +/* particularly important when rotating.*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the register */ +/* only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_Y_PIC_WIDTH +#endif /* MRV_MI_SP_Y_PIC_WIDTH */ +/*****************************************************************************/ +/** + * register: mi_sp_y_pic_height: Y component image height (0x00000118) + * + *****************************************************************************/ +/* Slice: sp_y_pic_height:*/ +/* Image height of the y component or RGB picture in pixel.*/ + /**/ +/* In planar and semi planar mode the image width of the cb and cr component */ +/* is assumed according to the YCbCr format, i.e. half for 4:2:0 and the same */ +/* for 4:2:2 and 4:4:4.*/ + /**/ +/* Note:*/ +/* - Image height always refers to the picture height of the output image.*/ +/* This is particularly important when rotating.*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the register */ +/* only if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_Y_PIC_HEIGHT +#endif /* MRV_MI_SP_Y_PIC_HEIGHT */ +/*****************************************************************************/ +/** + * register: mi_sp_y_pic_size: Y component image size (0x0000011c) + * + *****************************************************************************/ +/* Slice: sp_y_pic_size:*/ +/* Image size of the Y component or RGB picture in pixel which has to be the */ +/* Y line length multiplied by the Y image height (sp_y_llength * sp_y_pic_height).*/ + /**/ +/* In planar mode the image size of the Cb and Cr component is assumed according */ +/* to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for */ +/* 4:4:4.*/ + /**/ +/* In semi planar mode the image size of the Cb and Cr component is assumed half */ +/* for 4:2:0 and the same size for 4:2:2.*/ + /**/ +/* Note:*/ +/* - Programmed value becomes effective immediately. So write to the register only */ +/* if no picture data is sent to the self path.*/ +#ifdef MRV_MI_SP_Y_PIC_SIZE +#endif /* MRV_MI_SP_Y_PIC_SIZE */ +/*****************************************************************************/ +/** + * register: mi_dma_ctrl: DMA control register (0x00000120) + * + *****************************************************************************/ +/* Slice: dma_rgb_format:*/ +/* Selects RGB Bayer data of read DMA picture */ + /**/ +/* 00: no DMA RGB Bayer data */ +/* 01: 8 bit RGB Bayer data */ +/* 10: 16 bit RGB Bayer data (12 bit used)*/ + /**/ +/* bytes are organized MSB first and 4 lower bits of LSB remain unused:*/ +/* byte_even -> bayer[11:4], byte_odd[7:4] -> bayer[3:0]*/ + /**/ +/* 11: reserved.*/ +#ifdef MRV_MI_DMA_RGB_FORMAT +#define MRV_MI_DMA_RGB_FORMAT_NO_DATA 0 +#define MRV_MI_DMA_RGB_FORMAT_8BIT_BAYER 1 +#define MRV_MI_DMA_RGB_FORMAT_16BIT_BAYER 2 +#endif /* MRV_MI_DMA_RGB_FORMAT */ +/* Slice: dma_frame_end_disable:*/ +/* Suppresses v_end so that no frame end can be detected by following */ +/* instances. Note: The dma_ready interrupt is raised as usual, but the */ +/* dma_frame_end interrupt will not be generated until v_end has been */ +/* enabled again.*/ +#ifdef MRV_MI_DMA_FRAME_END_DISABLE +#endif /* MRV_MI_DMA_FRAME_END_DISABLE */ +/* Slice: dma_continuous_en:*/ +/* Enables continuous mode. If set the same frame is read back over and */ +/* over. A start pulse on dma_start is needed only for the first time.*/ +/* To stop continuous mode reset this bit (takes effect after the next */ +/* frame end) or execute a soft reset. This bit is intended to be used */ +/* in conjunction with the Superimpose feature.*/ +#ifdef MRV_MI_DMA_CONTINUOUS_EN +#endif /* MRV_MI_DMA_CONTINUOUS_EN */ +/* Slice: dma_byte_swap:*/ +/* Enables change of DMA byte order of the 32 bit input word at read port */ +/* 1: byte order is mirrored but the bit order within one byte doesn’t change */ +/* 0: no byte mirroring */ +#ifdef MRV_MI_DMA_BYTE_SWAP +#endif /* MRV_MI_DMA_BYTE_SWAP */ +/* Slice: dma_inout_format:*/ +/* Selects input/output format of DMA picture.*/ +/* 11: YCbCr 4:4:4 */ +/* 10: YCbCr 4:2:2 */ +/* 01: YCbCr 4:2:0 */ +/* 00: YCbCr 4:0:0 */ +#ifdef MRV_MI_DMA_INOUT_FORMAT +#define MRV_MI_DMA_INOUT_FORMAT_YUV444 3 /* 11: YCbCr 4:4:4 */ +#define MRV_MI_DMA_INOUT_FORMAT_YUV422 2 /* 10: YCbCr 4:2:2 */ +#define MRV_MI_DMA_INOUT_FORMAT_YUV420 1 /* 01: YCbCr 4:2:0 */ +#define MRV_MI_DMA_INOUT_FORMAT_YUV400 0 /* 00: YCbCr 4:0:0 */ +#endif /* MRV_MI_DMA_INOUT_FORMAT */ +/* Slice: dma_read_format:*/ +/* Defines how YCbCr picture data is read from memory.*/ +/* 00: planar */ +/* 01: semi planar, for YCbCr 4:2:x */ +/* 10: interleaved (combined), for YCbCr 4:2:2 and RGB only */ +/* 11: reserved */ +#ifdef MRV_MI_DMA_READ_FORMAT +#define MRV_MI_DMA_READ_FORMAT_PLANAR 0 /* 00: planar */ +#define MRV_MI_DMA_READ_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */ +#define MRV_MI_DMA_READ_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */ +#endif /* MRV_MI_DMA_READ_FORMAT */ +/* Slice: dma_burst_len_chrom:*/ +/* Burst length for Cb or Cr data affecting DMA read port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ +#ifdef MRV_MI_DMA_BURST_LEN_CHROM +#define MRV_MI_DMA_BURST_LEN_CHROM_4 0 /* 0: 4-beat bursts */ +#define MRV_MI_DMA_BURST_LEN_CHROM_8 1 /* 1: 8-beat bursts */ +#define MRV_MI_DMA_BURST_LEN_CHROM_16 2 /* 2: 16-beat bursts */ +#endif /* MRV_MI_DMA_BURST_LEN_CHROM */ +/* Slice: dma_burst_len_lum:*/ +/* Burst length for Y data affecting DMA read port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ +#ifdef MRV_MI_DMA_BURST_LEN_LUM +#define MRV_MI_DMA_BURST_LEN_LUM_4 0 /* 0: 4-beat bursts */ +#define MRV_MI_DMA_BURST_LEN_LUM_8 1 /* 1: 8-beat bursts */ +#define MRV_MI_DMA_BURST_LEN_LUM_16 2 /* 2: 16-beat bursts */ +#endif /* MRV_MI_DMA_BURST_LEN_LUM */ +/*****************************************************************************/ +/** + * register: mi_dma_start: DMA start register (0x00000124) + * + *****************************************************************************/ +/* Slice: dma_start:*/ +/* Enables DMA access. Additionally main or self path has to be enabled separately.*/ +#ifdef MRV_MI_DMA_START +#endif /* MRV_MI_DMA_START */ +/*****************************************************************************/ +/** + * register: mi_dma_status: DMA status register (0x00000128) + * + *****************************************************************************/ +/* Slice: dma_active:*/ +/* If set DMA access is active.*/ +#ifdef MRV_MI_DMA_ACTIVE +#endif /* MRV_MI_DMA_ACTIVE */ +/*****************************************************************************/ +/** + * register: mi_pixel_cnt: Counter value for defect pixel list (0x0000012c) + * + *****************************************************************************/ +/* Slice: pix_cnt:*/ +/* Counter value specifies the number of pixels of the defect pixel list */ +/* generated by DPCC of the last transmitted frame. Updated at frame end.*/ + /**/ +/* A soft reset will set the counter to zero.*/ +#ifdef MRV_MI_PIX_CNT +#endif /* MRV_MI_PIX_CNT */ +#ifdef ISP_MI_HANDSHAKE_NANO +/* Nano handshake */ +/*****************************************************************************/ +/** + * register: isp_handshake_ctrl_0: Nano handshake functions (0x0000014C) + * + *****************************************************************************/ + /*! Slice: mp_handshake_en: */ +/*! Enable mp handshake function for MI MP */ +#ifdef MRV_MI_MP_HANDSHK_EN +#define MRV_MI_MP_HANDSHK_EN_DISABLE 0 /* HANDSHAKE disable */ +#define MRV_MI_MP_HANDSHK_EN_ENABLE 1 /* HANDSHAKE enable, active high */ +#endif +/*! Slice: mp_handshk_storage_format */ +/*! Define how YCbCr picture data is stored in memory */ +/*! 00: Planar */ +/*! 01: Semi planar, for YCbCr4:2:x */ +/*! 10: Interleaved(combiled), for YCbCr 4:2:2 only or RAW format.*/ +/*! 11: not support */ +#ifdef MRV_MI_MP_HANDSHK_STORAGE_FORMAT +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_PLANAR 0 /* 00: Planar */ +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_SEMIPLANAR 1 /* 01: Semi-Planar */ +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_INTERLEAVED 2 /* 10: Interleaved */ +#endif +/*! Slice: mp_handshk_data_format */ +/*! Defines the video format */ +/*! 00: RAW format */ +/*! 01: reserved */ +/*! 10: YUV 422 */ +/*! 11: YUV 420 */ +#ifdef MRV_MI_MP_HANDSHK_DATA_FORMAT +#define MRV_MI_MP_HANDSHK_DATA_FORMAT_RAW 0 /* 00: raw format */ +#define MRV_MI_MP_HANDSHK_DATA_FORMAT_YUV422 2 /* 10: YUV422 */ +#define MRV_MI_MP_HANDSHK_DATA_FORMAT_YUV420 3 /* 11: YUV420 */ +#endif +/*! Slice: mp_handshk_slice_size */ +/*! Defines the slice size to generate handshake signals, minus 1 is used */ +#ifdef MRV_MI_MP_HANDSHK_SLICE_SIZE +#endif +/*! Slice: mp_handshk_slice_buf_size */ +/*! Defines the circular buffer size in number of defined slices per buffer, minus 1 is used */ +#ifdef MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE +#endif +/*! Slice: mp_handshk_ack_count */ +/*! Defines the acknowledage is not received in the defined cycles, it will generate handshake interrupt.*/ +#ifdef MRV_MI_MP_HANDSHK_ACK_COUNT +#endif +#endif +#ifdef ISP_MI_ALIGN_NANO +/* MI output Alignment */ +/*****************************************************************************/ +/** + * register: mi_output_alignment: Nano MI output alignment (0x0000015C) + * + *****************************************************************************/ +/* Slice: mp_lsb_alignment:*/ +/*! msb/lsb align for raw 10 and raw 12 formats control */ +/*! 0: MSB aligned for RAW10 and RAW12 formats */ +/*! 1: LSB aligned for RAW10 and RAW12 formats */ +#ifdef MRV_MI_LSB_ALIGNMENT +#define MRV_MI_LSB_ALIGNMENT_MSB 0 /* MSB aligned for raw 10 and raw 12 formats */ +#define MRV_MI_LSB_ALIGNMENT_LSB 1 /* LSB aligned for raw 10 and raw 12 formats */ +#endif +#endif +#ifdef ISP_MI_BYTESWAP +/*! Slice mp_byte_swap:*/ +/*! swap bytes for ISP Nano */ +/*! bit 0 to swap bytes */ +/*! bit 1 to swap words */ +/*! bit 2 to swap dwords */ +/*! 3'b001: ABCDEFGH => BADCFEHG */ +/*! 3'b000: ABCDEFGH => ABCDEFGH */ +/*! 3'b010: ABCDEFGH => CDABGHEF */ +/*! 3'b011: ABCDEFGH => DCBAHGFE */ +/*! 3'b100: ABCDEFGH => EFGHABCD */ +/*! 3'b101: ABCDEFGH => FEHGBADC */ +/*! 3'b110: ABCDEFGH => GHEFCDAB */ +/*! 3'b111: ABCDEFGH => HGFEDCBA */ +#ifdef MRV_MI_MP_BYTE_SWAP +#define MRV_MI_MP_BYTE_SWAP_NORMAL 0x0 /* normal mode */ +#define MRV_MI_MP_BYTE_SWAP_BYTE 0x1 /* bit 0 to swap bytes */ +#define MRV_MI_MP_BYTE_SWAP_WORD 0x2 /* bit 1 to swap words */ +#define MRV_MI_MP_BYTE_SWAP_DWORD 0x4 /* bit 2 to swap dwords */ +#endif +#endif +#ifdef ISP_MI_FIFO_DEPTH_NANO +/*****************************************************************************/ +/** + * register: mi_mp_output_fifo_size: Nano MI fifo control (0x00000160) + * + *****************************************************************************/ +/*! Slice output_fifo_depth:*/ +/*! Select output FIFO depth setting */ +/*! 00: FULL(2KBytes)*/ +/*! 01: HALF(1KBytes)*/ +/*! 10: 1/4(512Bytes)*/ +/*! 11: 1/8(256Bytes)*/ +#ifdef MRV_MI_OUTOUT_FIFO_DEPTH +#define MRV_MI_OUTOUT_FIFO_DEPTH_FULL 0 /* FULL(2KBytes) */ +#define MRV_MI_OUTOUT_FIFO_DEPTH_HALF 1 /* HALF(1KBytes) */ +#define MRV_MI_OUTOUT_FIFO_DEPTH_1_4 2 /* 1/4(512Bytes) */ +#define MRV_MI_OUTOUT_FIFO_DEPTH_1_8 3 /* 1/8(256Bytes) */ +#endif +#endif +/*****************************************************************************/ +/* JPEG Encoder Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: jpe_gen_header: command to start stream header generation (0x0000) + * + *****************************************************************************/ +/* Slice: gen_header:*/ +/* "1" = Start command to generate stream header */ +/* auto reset to zero after one clock cycle */ +#ifdef MRV_JPE_GEN_HEADER +#endif /* MRV_JPE_GEN_HEADER */ +/*****************************************************************************/ +/** + * register: jpe_encode: Start command to start JFIF stream encoding (0x0004) + * + *****************************************************************************/ +/* Slice: encode:*/ +/* "1" = Start command to start JFIF stream encoding;*/ +/* auto reset to zero after one clock cycle.*/ +/* This bit is write-only: reading result is always zero!*/ +#ifdef MRV_JPE_ENCODE +#endif /* MRV_JPE_ENCODE */ +/*****************************************************************************/ +/** + * register: jpe_init: Automatic configuration update (INIT) (0x0008) + * + *****************************************************************************/ +/* Slice: JP_INIT:*/ +/* "1" = Immediate start of JPEG encoder.*/ + /**/ +/* This bit has to be set after "Encode" to start the JPEG encoder. The "Encode"*/ +/* command becomes active either with JP_INIT or with the input signal "CFG_UPD".*/ +/* auto reset to zero after one clock cycle !!!*/ +#ifdef MRV_JPE_JP_INIT +#endif /* MRV_JPE_JP_INIT */ +/*****************************************************************************/ +/** + * register: jpe_y_scale_en: Y value scaling control register (0x0000000c) + * + *****************************************************************************/ +/* Slice: y_scale_en:*/ +/* Y scale flag */ +/* 1: scaling Y input from [16..235] to [0..255]*/ +/* 0: no Y input scaling */ +#ifdef MRV_JPE_Y_SCALE_EN +#endif /* MRV_JPE_Y_SCALE_EN */ +/*****************************************************************************/ +/** + * register: jpe_cbcr_scale_en: Cb/Cr value scaling control register (0x00000010) + * + *****************************************************************************/ +/* Slice: cbcr_scale_en:*/ +/* Cb/Cr scale flag */ +/* 1: scaling Cb/Cr input from [16..240] to [0..255]*/ +/* 0: no Cb/Cr input scaling */ +#ifdef MRV_JPE_CBCR_SCALE_EN +#endif /* MRV_JPE_CBCR_SCALE_EN */ +/*****************************************************************************/ +/** + * register: jpe_table_flush: header generation debug register (0x00000014) + * + *****************************************************************************/ +/* Slice: table_flush:*/ +/* header generation debug control flag */ +/* (controls transmission of last header bytes if the 64 bit output buffer */ +/* is not completely filled)*/ +/* 1: immediately transmit last header bytes */ +/* 0: wait for encoded image data to fill output buffer */ +#ifdef MRV_JPE_TABLE_FLUSH +#endif /* MRV_JPE_TABLE_FLUSH */ +/*****************************************************************************/ +/** + * register: jpe_enc_hsize: JPEG codec horizontal image size for encoding + * (0x00000018) + * + *****************************************************************************/ +/* Slice: enc_hsize:*/ +/* JPEG codec horizontal image size for R2B and SGEN blocks */ +#ifdef MRV_JPE_ENC_HSIZE +#endif /* MRV_JPE_ENC_HSIZE */ +/*****************************************************************************/ +/** + * register: jpe_enc_vsize: JPEG codec vertical image size for encoding + * (0x0000001c) + * + *****************************************************************************/ +/* Slice: enc_vsize:*/ +/* JPEG codec vertical image size for R2B and SGEN blocks */ +#ifdef MRV_JPE_ENC_VSIZE +#endif /* MRV_JPE_ENC_VSIZE */ +/*****************************************************************************/ +/** + * register: jpe_pic_format: JPEG picture encoding format (0x00000020) + * + *****************************************************************************/ +/* Slice: enc_pic_format:*/ +/* "0:0:1" = 4:2:2 format */ +/* "1:x:x" = 4:0:0 format */ +#ifdef MRV_JPE_ENC_PIC_FORMAT +#define MRV_JPE_ENC_PIC_FORMAT_422 1 /* "0:0:1" = 4:2:2 format */ +#define MRV_JPE_ENC_PIC_FORMAT_400 4 /* "1:x:x" = 4:0:0 format */ +#endif /* MRV_JPE_ENC_PIC_FORMAT */ +/*****************************************************************************/ +/** + * register: jpe_restart_interval: restart marker insertion register (0x0024) + * + *****************************************************************************/ +/* Slice: restart_interval:*/ +/* No of MCU in reset interval via host */ +#ifdef MRV_JPE_RESTART_INTERVAL +#endif /* MRV_JPE_RESTART_INTERVAL */ +/*****************************************************************************/ +/** + * register: jpe_tq_y_select: Q- table selector 0, quant. table for Y + * component (0x00000028) + * + *****************************************************************************/ +/* Slice: tq0_select:*/ +/* "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#ifdef MRV_JPE_TQ0_SELECT +#endif /* MRV_JPE_TQ0_SELECT */ +/*****************************************************************************/ +/** + * register: jpe_tq_u_select: Q- table selector 1, quant. table for U + * component (0x0000002c) + * + *****************************************************************************/ +/* Slice: tq1_select:*/ +/* "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#ifdef MRV_JPE_TQ1_SELECT +#endif /* MRV_JPE_TQ1_SELECT */ +/*****************************************************************************/ +/** + * register: jpe_tq_v_select: Q- table selector 2, quant. table for V + * component (0x00000030) + * + *****************************************************************************/ +/* Slice: tq2_select:*/ +/* "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#ifdef MRV_JPE_TQ2_SELECT +#endif /* MRV_JPE_TQ2_SELECT */ +#define MRV_JPE_TQ_SELECT_TAB3 3 /* "11": qtable 3 */ +#define MRV_JPE_TQ_SELECT_TAB2 2 /* "10": qtable 2 */ +#define MRV_JPE_TQ_SELECT_TAB1 1 /* "01": qtable 1 */ +#define MRV_JPE_TQ_SELECT_TAB0 0 /* "00": qtable 0 */ +/*****************************************************************************/ +/** + * register: jpe_dc_table_select: Huffman table selector for DC values + * (0x00000034) + * + *****************************************************************************/ +/* Slice: dc_table_select_v:*/ +/* "0" = dc table 0; color component 2 (V)*/ +/* "1" = dc table 1; color component 2 (V)*/ +#ifdef MRV_JPE_DC_TABLE_SELECT_V +#endif /* MRV_JPE_DC_TABLE_SELECT_V */ +/* Slice: dc_table_select_u:*/ +/* "0" = dc table 0; color component 1 (U)*/ +/* "1" = dc table 1; color component 1 (U)*/ +#ifdef MRV_JPE_DC_TABLE_SELECT_U +#endif /* MRV_JPE_DC_TABLE_SELECT_U */ +/* Slice: dc_table_select_y:*/ +/* "0" = dc table 0; color component 0 (Y)*/ +/* "1" = dc table 1; color component 0 (Y)*/ +#ifdef MRV_JPE_DC_TABLE_SELECT_Y +#endif /* MRV_JPE_DC_TABLE_SELECT_Y */ +/*****************************************************************************/ +/** + * register: jpe_ac_table_select: Huffman table selector for AC values + * (0x00000038) + * + *****************************************************************************/ +/* Slice: ac_table_select_v:*/ +/* "0" = ac table 0; component 2 (V)*/ +/* "1" = ac table 1; component 2 (V)*/ +#ifdef MRV_JPE_AC_TABLE_SELECT_V +#endif /* MRV_JPE_AC_TABLE_SELECT_V */ +/* Slice: ac_table_select_u:*/ +/* "0" = ac table 0; component 1 (U)*/ +/* "1" = ac table 1; component 1 (U)*/ +#ifdef MRV_JPE_AC_TABLE_SELECT_U +#endif /* MRV_JPE_AC_TABLE_SELECT_U */ +/* Slice: ac_table_select_y:*/ +/* "0" = ac table 0; component 0 (Y)*/ +/* "1" = ac table 1; component 0 (Y)*/ +#ifdef MRV_JPE_AC_TABLE_SELECT_Y +#endif /* MRV_JPE_AC_TABLE_SELECT_Y */ +/*****************************************************************************/ +/** + * register: jpe_table_data: table programming register (0x0000003c) + * + *****************************************************************************/ +/* Slice: table_wdata_h:*/ +/* Table data MSB */ +#ifdef MRV_JPE_TABLE_WDATA_H +#endif /* MRV_JPE_TABLE_WDATA_H */ +/* Slice: table_wdata_l:*/ +/* Table data LSB */ +#ifdef MRV_JPE_TABLE_WDATA_L +#endif /* MRV_JPE_TABLE_WDATA_L */ +/*****************************************************************************/ +/** + * register: jpe_table_id: table programming select register (0x00000040) + * + *****************************************************************************/ +/* Slice: table_id:*/ +/* select table */ +/* "0000" : Q-table 0 */ +/* "0001" : Q-table 1 */ +/* "0010" : Q-table 2 */ +/* "0011" : Q-table 3 */ +/* "0100" : VLC DC-table 0 */ +/* "0101" : VLC AC-table 0 */ +/* "0110" : VLC DC-table 1 */ +/* "0111" : VLC AC-table 1 */ +/* "1xxx" : reserved for debug */ +#ifdef MRV_JPE_TABLE_ID +#define MRV_JPE_TABLE_ID_QUANT0 0 /* "0000" : Q-table 0 */ +#define MRV_JPE_TABLE_ID_QUANT1 1 /* "0001" : Q-table 1 */ +#define MRV_JPE_TABLE_ID_QUANT2 2 /* "0010" : Q-table 2 */ +#define MRV_JPE_TABLE_ID_QUANT3 3 /* "0011" : Q-table 3 */ +#define MRV_JPE_TABLE_ID_VLC_DC0 4 /* "0100" : VLC DC-table 0 */ +#define MRV_JPE_TABLE_ID_VLC_AC0 5 /* "0101" : VLC AC-table 0 */ +#define MRV_JPE_TABLE_ID_VLC_DC1 6 /* "0110" : VLC DC-table 1 */ +#define MRV_JPE_TABLE_ID_VLC_AC1 7 /* "0111" : VLC AC-table 1 */ +#endif /* MRV_JPE_TABLE_ID */ +/*****************************************************************************/ +/** + * register: jpe_tac0_len: Huffman AC table 0 length (0x0044) + * + *****************************************************************************/ +/* Slice: tac0_len:*/ +/* Huffman table length for ac0 table */ +#ifdef MRV_JPE_TAC0_LEN +#endif /* MRV_JPE_TAC0_LEN */ +/*****************************************************************************/ +/** + * register: jpe_tdc0_len: Huffman DC table 0 length (0x00000048) + * + *****************************************************************************/ +/* Slice: tdc0_len:*/ +/* Huffman table length for dc0 table */ +#ifdef MRV_JPE_TDC0_LEN +#endif /* MRV_JPE_TDC0_LEN */ +/*****************************************************************************/ +/** + * register: jpe_tac1_len: Huffman AC table 1 length (0x0000004c) + * + *****************************************************************************/ +/* Slice: tac1_len:*/ +/* Huffman table length for ac1 table */ +#ifdef MRV_JPE_TAC1_LEN +#endif /* MRV_JPE_TAC1_LEN */ +/*****************************************************************************/ +/** + * register: jpe_tdc1_len: Huffman DC table 1 length (0x00000050) + * + *****************************************************************************/ +/* Slice: tdc1_len:*/ +/* Huffman table length for dc1 table */ +#ifdef MRV_JPE_TDC1_LEN +#endif /* MRV_JPE_TDC1_LEN */ +/*****************************************************************************/ +/** + * register: jpe_encoder_busy: encoder status flag (0x00000058) + * + *****************************************************************************/ +/* Slice: codec_busy:*/ +/* Bit 0 = "1" : JPEG codec in process */ +#ifdef MRV_JPE_CODEC_BUSY +#endif /* MRV_JPE_CODEC_BUSY */ +/*****************************************************************************/ +/** + * register: jpe_header_mode: header mode definition (0x0000005c) + * + *****************************************************************************/ +/* Slice: header_mode:*/ +/* "00" = no header */ +/* "01" = reserved */ +/* "10" = JFIF 1.02 header */ +/* "11" = reserved */ +#ifdef MRV_JPE_HEADER_MODE +#define MRV_JPE_HEADER_MODE_NONE 0 /* "00" = no APPn header */ +#define MRV_JPE_HEADER_MODE_JFIF 2 /* "10" = JFIF header */ +#endif /* MRV_JPE_HEADER_MODE */ +/*****************************************************************************/ +/** + * register: jpe_encode_mode: encode mode (0x00000060) + * + *****************************************************************************/ +/* Slice: encode_mode:*/ +/* Always "1", because this is the encoder only edition */ +#ifdef MRV_JPE_ENCODE_MODE +#endif /* MRV_JPE_ENCODE_MODE */ +/*****************************************************************************/ +/** + * register: jpe_debug: debug information register (0x00000064) + * + *****************************************************************************/ +/* Slice: deb_bad_table_access:*/ +/* Debug signal only (set if an access to the TABLE_DATA or to the TABLE_ID */ +/* register is performed, when the JPEG_ENCODER is busy. In this case a default */ +/* PVCI Acknowledge is generated. Thus the configuration bus is not blocked)*/ +#ifdef MRV_JPE_DEB_BAD_TABLE_ACCESS +#endif /* MRV_JPE_DEB_BAD_TABLE_ACCESS */ +/* Slice: deb_vlc_table_busy:*/ +/* Debug signal only (vlc access to huff-tables)*/ +#ifdef MRV_JPE_DEB_VLC_TABLE_BUSY +#endif /* MRV_JPE_DEB_VLC_TABLE_BUSY */ +/* Slice: deb_r2b_memory_full:*/ +/* Debug signal only (line memory status of r2b)*/ +#ifdef MRV_JPE_DEB_R2B_MEMORY_FULL +#endif /* MRV_JPE_DEB_R2B_MEMORY_FULL */ +/* Slice: deb_vlc_encode_busy:*/ +/* Debug signal only (vlc encode processing active)*/ +#ifdef MRV_JPE_DEB_VLC_ENCODE_BUSY +#endif /* MRV_JPE_DEB_VLC_ENCODE_BUSY */ +/* Slice: deb_qiq_table_acc:*/ +/* Debug signal only (QIQ table access)*/ +#ifdef MRV_JPE_DEB_QIQ_TABLE_ACC +#endif /* MRV_JPE_DEB_QIQ_TABLE_ACC */ +/*****************************************************************************/ +/** + * register: jpe_error_imr: JPEG error interrupt mask register (0x00000068) + * jpe_error_ris: JPEG error raw interrupt status register (0x0000006c) + * jpe_error_mis: JPEG error masked interrupt status register (0x00000070) + * jpe_error_icr: JPEG error interrupt set register (0x00000074) + * jpe_error_isr: JPEG error interrupt clear register (0x00000078) + * + *****************************************************************************/ +/* Slice: vlc_table_err:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_VLC_TABLE_ERR +#endif /* MRV_JPE_VLC_TABLE_ERR */ +/* Slice: r2b_IMG_size_err:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_R2B_IMG_SIZE_ERR +#endif /* MRV_JPE_R2B_IMG_SIZE_ERR */ +/* Slice: DCT_ERR:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_DCT_ERR +#endif /* MRV_JPE_DCT_ERR */ +/* Slice: vlc_symbol_err:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_VLC_SYMBOL_ERR +#endif /* MRV_JPE_VLC_SYMBOL_ERR */ +/*****************************************************************************/ +/** + * register: jpe_status_imr: JPEG status interrupt mask register (0x0000007c) + * jpe_status_ris: JPEG status raw interrupt status register (0x00000080) + * jpe_status_mis: JPEG status masked interrupt status register (0x00000084) + * jpe_status_icr: JPEG status interrupt clear register (0x00000088) + * jpe_status_isr: JPEG status interrupt set register (0x0000008c) + * + *****************************************************************************/ +/* Slice: gen_header_done:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_GEN_HEADER_DONE +#endif /* MRV_JPE_GEN_HEADER_DONE */ +/* Slice: encode_done:*/ +/* "1" = interrupt is activated (masked in)*/ +#ifdef MRV_JPE_ENCODE_DONE +#endif /* MRV_JPE_ENCODE_DONE */ +/*****************************************************************************/ +/** + * register: jpe_config: JPEG configuration register (0x00000090) + * + *****************************************************************************/ +/* Slice: speedview_en:*/ +/* 1: speed view enabled */ +/* 0: speed view disabled */ +#ifdef MRV_JPE_SPEEDVIEW_EN +#define MRV_JPE_SPEEDVIEW_EN_DISABLE 0 /* "0": JPEG Stream Encoding according to JPEG standard */ +#define MRV_JPE_SPEEDVIEW_EN_ENABLE 1 /* "1": SpeedView JPEG Stream Encoding enabled */ +#endif /* MRV_JPE_SPEEDVIEW_EN */ +/* Slice: cont_mode:*/ +/* Encoder continous mode */ +/* "00": encoder stops at frame end (corresponds to former behavior)*/ +/* "01": encoder starts automatically to encode the next frame */ +/* "10": unused */ +/* "11": encoder first generates next header and then encodes automatically the next frame */ +/* These settings are checked after encoding one frame. They are not auto-reset by hardware.*/ +#ifdef MRV_JPE_CONT_MODE +#define MRV_JPE_CONT_MODE_STOP 0 /* "00": encoder stops at frame end (corresponds to former behavior) */ +#define MRV_JPE_CONT_MODE_NEXT 1 /* "01": encoder starts automatically to encode the next frame */ +#define MRV_JPE_CONT_MODE_HEADER 3 /* "11": encoder first generates next header and then encodes automatically the next frame */ +#endif /* MRV_JPE_CONT_MODE */ +/*****************************************************************************/ +/* MIPI Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: mipi_ctrl: global control register (0x0000) + * + *****************************************************************************/ +/* Slice: S_ENABLE_CLK */ +/* 1: enable sensor clock lane (DEFAULT)*/ +/* 0: disable sensor clock lane */ +#ifdef MRV_MIPI_S_ENABLE_CLK +#endif /* MRV_MIPI_S_ENABLE_CLK */ +/* Slice: ERR_SOT_SYNC_HS_SKIP:*/ +/* 1: data within the current transmission is skipped if ErrSotSyncHS is detected (default)*/ +/* 0: ErrSotSyncHS does not affect transmission */ +#ifdef MRV_MIPI_ERR_SOT_SYNC_HS_SKIP +#endif /* MRV_MIPI_ERR_SOT_SYNC_HS_SKIP */ +/* Slice: ERR_SOT_HS_SKIP:*/ +/* 1: data within the current transmission is skipped if ErrSotHS is detected */ +/* 0: ErrSotHS does not affect transmission (default)*/ +#ifdef MRV_MIPI_ERR_SOT_HS_SKIP +#endif /* MRV_MIPI_ERR_SOT_HS_SKIP */ +/* Slice: NUM_LANES:*/ +/* 00: Lane 1 is used;*/ +/* 01: Lanes 1 and 2 are used;*/ +/* 10: Lanes 1...3 are used;*/ +/* 11: Lanes 1...4 are used */ +#ifdef MRV_MIPI_NUM_LANES +#define MRV_MIPI_NUM_LANES_1 0 /* 00: Lane 1 is used */ +#define MRV_MIPI_NUM_LANES_2 1 /* 01: Lanes 1 and 2 are used */ +#define MRV_MIPI_NUM_LANES_3 2 /* 10: Lanes 1...3 are used */ +#define MRV_MIPI_NUM_LANES_4 3 /* 11: Lanes 1...4 are used */ +#endif /* MRV_MIPI_NUM_LANES */ +/* Slice: SHUTDOWN_LANE:*/ +/* Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown[n-1:0]*/ +#ifdef MRV_MIPI_SHUTDOWN_LANE +#define MRV_MIPI_SHUTDOWN_LANE_1 1 /* 0001: shutdown lane 1 */ +#define MRV_MIPI_SHUTDOWN_LANE_2 2 /* 0010: shutdown lane 1 */ +#define MRV_MIPI_SHUTDOWN_LANE_3 4 /* 0100: shutdown lane 1 */ +#define MRV_MIPI_SHUTDOWN_LANE_4 8 /* 1000: shutdown lane 1 */ +#endif /* MRV_MIPI_SHUTDOWN_LANE */ +/* Slice: FLUSH_FIFO:*/ +/* writing '1' resets the write- and read pointers of the additional data fifo.*/ +#ifdef MRV_MIPI_FLUSH_FIFO +#endif /* MRV_MIPI_FLUSH_FIFO */ +/* Slice: OUTPUT_ENA:*/ +/* 1: output to add data fifo and to output interface is enabled */ +#ifdef MRV_MIPI_OUTPUT_ENA +#endif /* MRV_MIPI_OUTPUT_ENA */ +/*****************************************************************************/ +/** + * register: mipi_status: global status register (0x0004) + * + *****************************************************************************/ +/* Slice: S_ULP_ACTIVE_NOT_CLK:*/ +/* sensor clock lane is in ULP state. This register is directly connected to the synchronized input signal "s_ulpsactivenotclk"*/ +#ifdef MRV_MIPI_S_ULP_ACTIVE_NOT_CLK +#endif /* MRV_MIPI_S_ULP_ACTIVE_NOT_CLK */ +/* Slice: S_STOPSTATE_CLK:*/ +/* sensor clock lane is in stopstate. This register is directly connected to the synchronized input signal "s_stopstateclk"*/ +#ifdef MRV_MIPI_S_STOPSTATE_CLK +#endif /* MRV_MIPI_S_STOPSTATE_CLK */ +/* Slice: STOPSTATE:*/ +/* Lane is in stopstate. This register is directly connected to the synchronized input signal stopstate[n-1:0]*/ +#ifdef MRV_MIPI_STOPSTATE +#endif /* MRV_MIPI_STOPSTATE */ +/* Slice: ADD_DATA_AVAIL:*/ +/* 1: additional data fifo contains data */ +/* 0: additional data fifo is empty */ +#ifdef MRV_MIPI_ADD_DATA_AVAIL +#endif /* MRV_MIPI_ADD_DATA_AVAIL */ +/*****************************************************************************/ +/** + * register: mipi_imsc: Interrupt mask (0x00000008) + * + *****************************************************************************/ +/* Slice: IMSC_GEN_SHORT_PACK:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_GEN_SHORT_PACK +#define MRV_MIPI_IMSC_GEN_SHORT_PACK_MASK 0 +#endif /* MRV_MIPI_IMSC_GEN_SHORT_PACK */ +/* Slice: IMSC_ADD_DATA_FILL_LEVEL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK 0 +#endif /* MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL */ +/* Slice: IMSC_ADD_DATA_OVFLW:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ADD_DATA_OVFLW +#endif /* MRV_MIPI_IMSC_ADD_DATA_OVFLW */ +/* Slice: IMSC_FRAME_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_FRAME_END +#define MRV_MIPI_IMSC_FRAME_END_MASK 0 +#endif /* MRV_MIPI_IMSC_ADD_DATA_OVFLW */ +/* Slice: IMSC_ERR_CS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ERR_CS +#define MRV_MIPI_IMSC_ERR_CS_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_CS */ +/* Slice: IMSC_ERR_ECC1:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ERR_ECC1 +#define MRV_MIPI_IMSC_ERR_ECC1_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_ECC1 */ +/* Slice: IMSC_ERR_ECC2:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ERR_ECC2 +#define MRV_MIPI_IMSC_ERR_ECC2_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_ECC2 */ +/* Slice: IMSC_ERR_PROTOCOL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_IMSC_ERR_PROTOCOL +#define MRV_MIPI_IMSC_ERR_PROTOCOL_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_PROTOCOL */ +/* Slice: IMSC_ERR_CONTROL:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_IMSC_ERR_CONTROL +#define MRV_MIPI_IMSC_ERR_CONTROL_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_CONTROL */ +/* Slice: IMSC_ERR_EOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_IMSC_ERR_EOT_SYNC +#define MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_EOT_SYNC */ +/* Slice: IMSC_ERR_SOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_IMSC_ERR_SOT_SYNC +#define MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_SOT_SYNC */ +/* Slice: IMSC_ERR_SOT:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_IMSC_ERR_SOT +#define MRV_MIPI_IMSC_ERR_SOT_MASK 0 +#endif /* MRV_MIPI_IMSC_ERR_SOT */ +/* Slice: IMSC_SYNC_FIFO_OVFLW:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_IMSC_SYNC_FIFO_OVFLW +#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK 0 +#endif /* MRV_MIPI_IMSC_SYNC_FIFO_OVFLW */ +/* combination of all interrupt lines */ +#define MRV_MIPI_IMSC_ALL_IRQS +#define MRV_MIPI_IMSC_ALL_IRQS_MASK \ +(MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK \ + | MRV_MIPI_IMSC_ADD_DATA_OVFLW_MASK \ + | MRV_MIPI_IMSC_FRAME_END_MASK \ + | MRV_MIPI_IMSC_ERR_CS_MASK \ + | MRV_MIPI_IMSC_ERR_ECC1_MASK \ + | MRV_MIPI_IMSC_ERR_ECC2_MASK \ + | MRV_MIPI_IMSC_ERR_PROTOCOL_MASK \ + | MRV_MIPI_IMSC_ERR_CONTROL_MASK \ + | MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK \ + | MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK \ + | MRV_MIPI_IMSC_ERR_SOT_MASK \ + | MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK \ +) +#define MRV_MIPI_IMSC_ALL_IRQS_SHIFT 0 +/*****************************************************************************/ +/** + * register: mipi_ris: Raw interrupt status (0x0000000c) + * + *****************************************************************************/ +/* Slice: RIS_GEN_SHORT_PACK:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_GEN_SHORT_PACK +#define MRV_MIPI_RIS_GEN_SHORT_PACK_MASK 0 +#endif /* MRV_MIPI_RIS_GEN_SHORT_PACK */ +/* Slice: RIS_ADD_DATA_FILL_LEVEL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK 0 +#endif /* MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL */ +/* Slice: RIS_ADD_DATA_OVFLW:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ADD_DATA_OVFLW +#endif /* MRV_MIPI_RIS_ADD_DATA_OVFLW */ +/* Slice: RIS_FRAME_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_FRAME_END +#define MRV_MIPI_RIS_FRAME_END_MASK 0 +#endif /* MRV_MIPI_RIS_ADD_DATA_OVFLW */ +/* Slice: RIS_ERR_CS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ERR_CS +#define MRV_MIPI_RIS_ERR_CS_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_CS */ +/* Slice: RIS_ERR_ECC1:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ERR_ECC1 +#define MRV_MIPI_RIS_ERR_ECC1_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_ECC1 */ +/* Slice: RIS_ERR_ECC2:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ERR_ECC2 +#define MRV_MIPI_RIS_ERR_ECC2_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_ECC2 */ +/* Slice: RIS_ERR_PROTOCOL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_RIS_ERR_PROTOCOL +#define MRV_MIPI_RIS_ERR_PROTOCOL_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_PROTOCOL */ +/* Slice: RIS_ERR_CONTROL:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_RIS_ERR_CONTROL +#define MRV_MIPI_RIS_ERR_CONTROL_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_CONTROL */ +/* Slice: RIS_ERR_EOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_RIS_ERR_EOT_SYNC +#define MRV_MIPI_RIS_ERR_EOT_SYNC_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_EOT_SYNC */ +/* Slice: RIS_ERR_SOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_RIS_ERR_SOT_SYNC +#define MRV_MIPI_RIS_ERR_SOT_SYNC_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_SOT_SYNC */ +/* Slice: RIS_ERR_SOT:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_RIS_ERR_SOT +#define MRV_MIPI_RIS_ERR_SOT_MASK 0 +#endif /* MRV_MIPI_RIS_ERR_SOT */ +/* Slice: RIS_SYNC_FIFO_OVFLW:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_RIS_SYNC_FIFO_OVFLW +#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK 0 +#endif /* MRV_MIPI_RIS_SYNC_FIFO_OVFLW */ +/* combination of all interrupt lines */ +#define MRV_MIPI_RIS_ALL_IRQS +#define MRV_MIPI_RIS_ALL_IRQS_MASK \ +(MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK \ + | MRV_MIPI_RIS_ADD_DATA_OVFLW_MASK \ + | MRV_MIPI_RIS_FRAME_END_MASK \ + | MRV_MIPI_RIS_ERR_CS_MASK \ + | MRV_MIPI_RIS_ERR_ECC1_MASK \ + | MRV_MIPI_RIS_ERR_ECC2_MASK \ + | MRV_MIPI_RIS_ERR_PROTOCOL_MASK \ + | MRV_MIPI_RIS_ERR_CONTROL_MASK \ + | MRV_MIPI_RIS_ERR_EOT_SYNC_MASK \ + | MRV_MIPI_RIS_ERR_SOT_SYNC_MASK \ + | MRV_MIPI_RIS_ERR_SOT_MASK \ + | MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK \ +) +#define MRV_MIPI_RIS_ALL_IRQS_SHIFT 0 +/*****************************************************************************/ +/** + * register: mipi_mis: Masked interrupt status (0x00000010) + * + *****************************************************************************/ +/* Slice: MIS_GEN_SHORT_PACK:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_GEN_SHORT_PACK +#define MRV_MIPI_MIS_GEN_SHORT_PACK_MASK 0 +#endif /* MRV_MIPI_MIS_GEN_SHORT_PACK */ +/* Slice: MIS_ADD_DATA_FILL_LEVEL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK 0 +#endif /* MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL */ +/* Slice: MIS_ADD_DATA_OVFLW:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ADD_DATA_OVFLW +#endif /* MRV_MIPI_MIS_ADD_DATA_OVFLW */ +/* Slice: MIS_FRAME_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_FRAME_END +#define MRV_MIPI_MIS_FRAME_END_MASK 0 +#endif /* MRV_MIPI_MIS_ADD_DATA_OVFLW */ +/* Slice: MIS_ERR_CS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ERR_CS +#define MRV_MIPI_MIS_ERR_CS_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_CS */ +/* Slice: MIS_ERR_ECC1:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ERR_ECC1 +#define MRV_MIPI_MIS_ERR_ECC1_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_ECC1 */ +/* Slice: MIS_ERR_ECC2:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ERR_ECC2 +#define MRV_MIPI_MIS_ERR_ECC2_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_ECC2 */ +/* Slice: MIS_ERR_PROTOCOL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_MIS_ERR_PROTOCOL +#define MRV_MIPI_MIS_ERR_PROTOCOL_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_PROTOCOL */ +/* Slice: MIS_ERR_CONTROL:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_MIS_ERR_CONTROL +#define MRV_MIPI_MIS_ERR_CONTROL_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_CONTROL */ +/* Slice: MIS_ERR_EOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_MIS_ERR_EOT_SYNC +#define MRV_MIPI_MIS_ERR_EOT_SYNC_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_EOT_SYNC */ +/* Slice: MIS_ERR_SOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_MIS_ERR_SOT_SYNC +#define MRV_MIPI_MIS_ERR_SOT_SYNC_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_SOT_SYNC */ +/* Slice: MIS_ERR_SOT:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_MIS_ERR_SOT +#define MRV_MIPI_MIS_ERR_SOT_MASK 0 +#endif /* MRV_MIPI_MIS_ERR_SOT */ +/* Slice: MIS_SYNC_FIFO_OVFLW:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_MIS_SYNC_FIFO_OVFLW +#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK 0 +#endif /* MRV_MIPI_MIS_SYNC_FIFO_OVFLW */ +/* combination of all interrupt lines */ +#define MRV_MIPI_MIS_ALL_IRQS +#define MRV_MIPI_MIS_ALL_IRQS_MASK \ +(MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK \ + | MRV_MIPI_MIS_ADD_DATA_OVFLW_MASK \ + | MRV_MIPI_MIS_FRAME_END_MASK \ + | MRV_MIPI_MIS_ERR_CS_MASK \ + | MRV_MIPI_MIS_ERR_ECC1_MASK \ + | MRV_MIPI_MIS_ERR_ECC2_MASK \ + | MRV_MIPI_MIS_ERR_PROTOCOL_MASK \ + | MRV_MIPI_MIS_ERR_CONTROL_MASK \ + | MRV_MIPI_MIS_ERR_EOT_SYNC_MASK \ + | MRV_MIPI_MIS_ERR_SOT_SYNC_MASK \ + | MRV_MIPI_MIS_ERR_SOT_MASK \ + | MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK \ +) +#define MRV_MIPI_MIS_ALL_IRQS_SHIFT 0 +/*****************************************************************************/ +/** + * register: mipi_icr: Interrupt clear register (0x00000014) + * + *****************************************************************************/ +/* Slice: ICR_GEN_SHORT_PACK:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_GEN_SHORT_PACK +#define MRV_MIPI_ICR_GEN_SHORT_PACK_MASK 0 +#endif /* MRV_MIPI_ICR_GEN_SHORT_PACK */ +/* Slice: ICR_ADD_DATA_FILL_LEVEL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK 0 +#endif /* MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL */ +/* Slice: ICR_ADD_DATA_OVFLW:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ADD_DATA_OVFLW +#endif /* MRV_MIPI_ICR_ADD_DATA_OVFLW */ +/* Slice: ICR_FRAME_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_FRAME_END +#define MRV_MIPI_ICR_FRAME_END_MASK 0 +#endif /* MRV_MIPI_ICR_ADD_DATA_OVFLW */ +/* Slice: ICR_ERR_CS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ERR_CS +#define MRV_MIPI_ICR_ERR_CS_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_CS */ +/* Slice: ICR_ERR_ECC1:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ERR_ECC1 +#define MRV_MIPI_ICR_ERR_ECC1_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_ECC1 */ +/* Slice: ICR_ERR_ECC2:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ERR_ECC2 +#define MRV_MIPI_ICR_ERR_ECC2_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_ECC2 */ +/* Slice: ICR_ERR_PROTOCOL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ICR_ERR_PROTOCOL +#define MRV_MIPI_ICR_ERR_PROTOCOL_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_PROTOCOL */ +/* Slice: ICR_ERR_CONTROL:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ICR_ERR_CONTROL +#define MRV_MIPI_ICR_ERR_CONTROL_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_CONTROL */ +/* Slice: ICR_ERR_EOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ICR_ERR_EOT_SYNC +#define MRV_MIPI_ICR_ERR_EOT_SYNC_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_EOT_SYNC */ +/* Slice: ICR_ERR_SOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ICR_ERR_SOT_SYNC +#define MRV_MIPI_ICR_ERR_SOT_SYNC_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_SOT_SYNC */ +/* Slice: ICR_ERR_SOT:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ICR_ERR_SOT +#define MRV_MIPI_ICR_ERR_SOT_MASK 0 +#endif /* MRV_MIPI_ICR_ERR_SOT */ +/* Slice: ICR_SYNC_FIFO_OVFLW:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ICR_SYNC_FIFO_OVFLW +#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK 0 +#endif /* MRV_MIPI_ICR_SYNC_FIFO_OVFLW */ +/* combination of all interrupt lines */ +#define MRV_MIPI_ICR_ALL_IRQS +#define MRV_MIPI_ICR_ALL_IRQS_MASK \ +(MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK \ + | MRV_MIPI_ICR_ADD_DATA_OVFLW_MASK \ + | MRV_MIPI_ICR_FRAME_END_MASK \ + | MRV_MIPI_ICR_ERR_CS_MASK \ + | MRV_MIPI_ICR_ERR_ECC1_MASK \ + | MRV_MIPI_ICR_ERR_ECC2_MASK \ + | MRV_MIPI_ICR_ERR_PROTOCOL_MASK \ + | MRV_MIPI_ICR_ERR_CONTROL_MASK \ + | MRV_MIPI_ICR_ERR_EOT_SYNC_MASK \ + | MRV_MIPI_ICR_ERR_SOT_SYNC_MASK \ + | MRV_MIPI_ICR_ERR_SOT_MASK \ + | MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK \ +) +#define MRV_MIPI_ICR_ALL_IRQS_SHIFT 0 +/*****************************************************************************/ +/** + * register: mipi_isr: Interrupt set register (0x00000018) + * + *****************************************************************************/ +/* Slice: ISR_GEN_SHORT_PACK:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_GEN_SHORT_PACK +#define MRV_MIPI_ISR_GEN_SHORT_PACK_MASK 0 +#endif /* MRV_MIPI_ISR_GEN_SHORT_PACK */ +/* Slice: ISR_ADD_DATA_FILL_LEVEL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK 0 +#endif /* MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL */ +/* Slice: ISR_ADD_DATA_OVFLW:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ADD_DATA_OVFLW +#endif /* MRV_MIPI_ISR_ADD_DATA_OVFLW */ +/* Slice: ISR_FRAME_END:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_FRAME_END +#define MRV_MIPI_ISR_FRAME_END_MASK 0 +#endif /* MRV_MIPI_ISR_ADD_DATA_OVFLW */ +/* Slice: ISR_ERR_CS:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ERR_CS +#define MRV_MIPI_ISR_ERR_CS_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_CS */ +/* Slice: ISR_ERR_ECC1:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ERR_ECC1 +#define MRV_MIPI_ISR_ERR_ECC1_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_ECC1 */ +/* Slice: ISR_ERR_ECC2:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ERR_ECC2 +#define MRV_MIPI_ISR_ERR_ECC2_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_ECC2 */ +/* Slice: ISR_ERR_PROTOCOL:*/ +/* enable interrupt (1) or mask out (0)*/ +#ifndef MRV_MIPI_ISR_ERR_PROTOCOL +#define MRV_MIPI_ISR_ERR_PROTOCOL_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_PROTOCOL */ +/* Slice: ISR_ERR_CONTROL:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ISR_ERR_CONTROL +#define MRV_MIPI_ISR_ERR_CONTROL_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_CONTROL */ +/* Slice: ISR_ERR_EOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ISR_ERR_EOT_SYNC +#define MRV_MIPI_ISR_ERR_EOT_SYNC_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_EOT_SYNC */ +/* Slice: ISR_ERR_SOT_SYNC:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ISR_ERR_SOT_SYNC +#define MRV_MIPI_ISR_ERR_SOT_SYNC_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_SOT_SYNC */ +/* Slice: ISR_ERR_SOT:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ISR_ERR_SOT +#define MRV_MIPI_ISR_ERR_SOT_MASK 0 +#endif /* MRV_MIPI_ISR_ERR_SOT */ +/* Slice: ISR_SYNC_FIFO_OVFLW:*/ +/* enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#ifndef MRV_MIPI_ISR_SYNC_FIFO_OVFLW +#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK 0 +#endif /* MRV_MIPI_ISR_SYNC_FIFO_OVFLW */ +/* combination of all interrupt lines */ +#define MRV_MIPI_ISR_ALL_IRQS +#define MRV_MIPI_ISR_ALL_IRQS_MASK \ +(MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK \ + | MRV_MIPI_ISR_ADD_DATA_OVFLW_MASK \ + | MRV_MIPI_ISR_FRAME_END_MASK \ + | MRV_MIPI_ISR_ERR_CS_MASK \ + | MRV_MIPI_ISR_ERR_ECC1_MASK \ + | MRV_MIPI_ISR_ERR_ECC2_MASK \ + | MRV_MIPI_ISR_ERR_PROTOCOL_MASK \ + | MRV_MIPI_ISR_ERR_CONTROL_MASK \ + | MRV_MIPI_ISR_ERR_EOT_SYNC_MASK \ + | MRV_MIPI_ISR_ERR_SOT_SYNC_MASK \ + | MRV_MIPI_ISR_ERR_SOT_MASK \ + | MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK \ +) +#define MRV_MIPI_ISR_ALL_IRQS_SHIFT 0 +/*****************************************************************************/ +/** + * register: mipi_cur_data_id: Current Data Identifier (0x0000001c) + * + *****************************************************************************/ +/* Slice: VIRTUAL_CHANNEL:*/ +/* virtual channel of currently received packet */ +#ifdef MRV_MIPI_VIRTUAL_CHANNEL +#endif /* MRV_MIPI_VIRTUAL_CHANNEL */ +/* Slice: DATA_TYPE:*/ +/* data type of currently received packet */ +#ifdef MRV_MIPI_DATA_TYPE +#endif /* MRV_MIPI_DATA_TYPE */ +/*****************************************************************************/ +/** + * register: mipi_img_data_sel: Image Data Selector (0x00000020) + * + *****************************************************************************/ +/* Slice: VIRTUAL_CHANNEL_SEL:*/ +/* virtual channel selector for image data output */ +#ifdef MRV_MIPI_VIRTUAL_CHANNEL_SEL +#endif /* MRV_MIPI_VIRTUAL_CHANNEL_SEL */ +/* Slice: DATA_TYPE_SEL:*/ +/* data type selector for image data output:*/ +/* 0x08...0x0F: generic short packets */ +/* 0x12: embedded 8-bit data */ +/* 0x18: YUV 420 8-bit */ +/* 0x19: YUV 420 10-bit */ +/* 0x1A: Legacy YUV 420 8-bit */ +/* 0x1C: YUV 420 8-bit (CSPS)*/ +/* 0x1D: YUV 420 10-bit (CSPS)*/ +/* 0x1E: YUV 422 8-bit */ +/* 0x1F: YUV 422 10-bit */ +/* 0x20: RGB 444 */ +/* 0x21: RGB 555 */ +/* 0x22: RGB 565 */ +/* 0x23: RGB 666 */ +/* 0x24: RGB 888 */ +/* 0x28: RAW 6 */ +/* 0x29: RAW 7 */ +/* 0x2A: RAW 8 */ +/* 0x2B: RAW 10 */ +/* 0x2C: RAW 12 */ +/* 0x30...0x37: User Defined Byte-based data */ +#ifdef MRV_MIPI_DATA_TYPE_SEL +#define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT 24 /* 0x18 YUV 420 8-bit */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV420_10BIT 25 /* 0x19 YUV 420 10-bit */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT_LEGACY 26 /* 0x1A Legacy YUV 420 8-bit */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT_CSPS 28 /* 0x1C YUV 420 8-bit (CSPS) */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV420_10BIT_CSPS 29 /* 0x1D YUV 420 10-bit (CSPS) */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV422_8BIT 30 /* 0x1E YUV 422 8-bit */ +#define MRV_MIPI_DATA_TYPE_SEL_YUV422_10BIT 31 /* 0x1F YUV 422 10-bit */ +#define MRV_MIPI_DATA_TYPE_SEL_RGB444 32 /* 0x20 RGB 444 */ +#define MRV_MIPI_DATA_TYPE_SEL_RGB555 33 /* 0x21 RGB 555 */ +#define MRV_MIPI_DATA_TYPE_SEL_RGB565 34 /* 0x22 RGB 565 */ +#define MRV_MIPI_DATA_TYPE_SEL_RGB666 35 /* 0x23 RGB 666 */ +#define MRV_MIPI_DATA_TYPE_SEL_RGB888 36 /* 0x24 RGB 888 */ +#define MRV_MIPI_DATA_TYPE_SEL_RAW6 40 /* 0x28 RAW 6 */ +#define MRV_MIPI_DATA_TYPE_SEL_RAW7 41 /* 0x29 RAW 7 */ +#define MRV_MIPI_DATA_TYPE_SEL_RAW8 42 /* 0x2A RAW 8 */ +#define MRV_MIPI_DATA_TYPE_SEL_RAW10 43 /* 0x2B RAW 10 */ +#define MRV_MIPI_DATA_TYPE_SEL_RAW12 44 /* 0x2C RAW 12 */ +#define MRV_MIPI_DATA_TYPE_SEL_USER1 48 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER2 49 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER3 50 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER4 51 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER5 52 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER6 53 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER7 54 /* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL_USER8 55 /* 0x30...0x37 User Defined Byte-based data */ +#endif /* MRV_MIPI_DATA_TYPE_SEL */ +/*****************************************************************************/ +/** + * register: mipi_add_data_sel_1: Additional Data Selector 1 (0x00000024) + * + *****************************************************************************/ +/* Slice: ADD_DATA_VC_1:*/ +/* virtual channel selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_VC_1 +#endif /* MRV_MIPI_ADD_DATA_VC_1 */ +/* Slice: ADD_DATA_TYPE_1:*/ +/* data type selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_TYPE_1 +#endif /* MRV_MIPI_ADD_DATA_TYPE_1 */ +/*****************************************************************************/ +/** + * register: mipi_add_data_sel_2: Additional Data Selector 2 (0x00000028) + * + *****************************************************************************/ +/* Slice: ADD_DATA_VC_2:*/ +/* virtual channel selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_VC_2 +#endif /* MRV_MIPI_ADD_DATA_VC_2 */ +/* Slice: ADD_DATA_TYPE_2:*/ +/* data type selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_TYPE_2 +#endif /* MRV_MIPI_ADD_DATA_TYPE_2 */ +/*****************************************************************************/ +/** + * register: mipi_add_data_sel_3: Additional Data Selector 3 (0x0000002c) + * + *****************************************************************************/ +/* Slice: ADD_DATA_VC_3:*/ +/* virtual channel selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_VC_3 +#endif /* MRV_MIPI_ADD_DATA_VC_3 */ +/* Slice: ADD_DATA_TYPE_3:*/ +/* data type selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_TYPE_3 +#endif /* MRV_MIPI_ADD_DATA_TYPE_3 */ +/*****************************************************************************/ +/** + * register: mipi_add_data_sel_4: Additional Data Selector 4 (0x00000030) + * + *****************************************************************************/ +/* Slice: ADD_DATA_VC_4:*/ +/* virtual channel selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_VC_4 +#endif /* MRV_MIPI_ADD_DATA_VC_4 */ +/* Slice: ADD_DATA_TYPE_4:*/ +/* data type selector for additional data output */ +#ifdef MRV_MIPI_ADD_DATA_TYPE_4 +#endif /* MRV_MIPI_ADD_DATA_TYPE_4 */ +/*****************************************************************************/ +/** + * register: mipi_add_data_fifo: Additional Data Fifo (0x00000034) + * + *****************************************************************************/ +/* Slice: ADD_DATA_FIFO:*/ +/* lowest 4 bytes in additional data fifo;*/ +/* reading increments fifo read pointer.*/ +/* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/ +#ifdef MRV_MIPI_ADD_DATA_FIFO +#endif /* MRV_MIPI_ADD_DATA_FIFO */ +/*****************************************************************************/ +/** + * register: mipi_add_data_fill_level: additional data fifo fill level + * (0x00000038) + * + *****************************************************************************/ +/* Slice: ADD_DATA_FILL_LEVEL:*/ +/* FIFO level in dwords for triggering the FILL_LEVEL interrupt,*/ +/* must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/ +#ifdef MRV_MIPI_ADD_DATA_FILL_LEVEL +#endif /* MRV_MIPI_ADD_DATA_FILL_LEVEL */ +/*****************************************************************************/ +/** + * register: mipi_compressed_mode: controls processing of compressed raw data + * types (0x0000003c) + * + *****************************************************************************/ +/* Slice: predictor_sel:*/ +/* predictor to be used:*/ +/* 0: predictor 1 */ +/* 1: predictor 2 */ +#ifdef MRV_MIPI_PREDICTOR_SEL +#define MRV_MIPI_PREDICTOR_SEL_1 0 /* 0: predictor 1 */ +#define MRV_MIPI_PREDICTOR_SEL_2 1 /* 1: predictor 2 */ +#endif /* MRV_MIPI_PREDICTOR_SEL */ +/* Slice: MRV_MIPI_COMP_SCHEME:*/ +/* Compressed raw data types */ +/* 000: 12-8-12 */ +/* 001: 12-8-12 */ +/* 010: 12-8-12 */ +/* 011: 10-8-10 */ +/* 100: 10-7-10 */ +/* 101: 10-6-10 */ +#ifdef MRV_MIPI_COMP_SCHEME +#define MRV_MIPI_COMP_SCHEME_12_8_12 0 /* 000: 12-8-12 */ +#define MRV_MIPI_COMP_SCHEME_12_7_12 1 /* 001: 12-8-12 */ +#define MRV_MIPI_COMP_SCHEME_12_6_12 2 /* 010: 12-8-12 */ +#define MRV_MIPI_COMP_SCHEME_10_8_10 3 /* 011: 10-8-10 */ +#define MRV_MIPI_COMP_SCHEME_10_7_10 4 /* 100: 10-7-10 */ +#define MRV_MIPI_COMP_SCHEME_10_6_10 5 /* 101: 10-6-10 */ +#endif /* MRV_MIPI_COMP_SCHEME */ +/* Slice: compress_en:*/ +/* 1: enable compressed mode processing */ +/* 0: disable compressed mode */ +#ifdef MRV_MIPI_COMPRESS_EN +#endif /* MRV_MIPI_COMPRESS_EN */ +/*****************************************************************************/ +/* ISP Image Stabilization Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_is_ctrl: Image Stabilization Control Register (0x00000000) + * + *****************************************************************************/ +/* Slice: is_en:*/ +/* 1: image stabilization switched on */ +/* 0: image stabilization switched off */ +#ifdef MRV_IS_IS_EN +#define MRV_IS_IS_EN_PROCESS 1 +#define MRV_IS_IS_EN_BYPASS 0 +#endif /* MRV_IS_IS_EN */ +/*****************************************************************************/ +/** + * register: isp_is_recenter: Recenter register (0x00000004) + * + *****************************************************************************/ +/* Slice: is_recenter:*/ +/* 000: recenter feature switched off */ +/* 1..7: recentering by (cur_h/v_offs-H/V_OFFS)/2^RECENTER */ +#ifdef MRV_IS_IS_RECENTER +#define MRV_IS_IS_RECENTER_MAX (MRV_IS_IS_RECENTER_MASK >> MRV_IS_IS_RECENTER_SHIFT) +#endif /* MRV_IS_IS_RECENTER */ +/*****************************************************************************/ +/** + * register: isp_is_h_offs: Horizontal offset of output window (0x00000008) + * + *****************************************************************************/ +/* Slice: is_h_offs:*/ +/* horizontal picture offset in pixel */ +#ifdef MRV_IS_IS_H_OFFS +#define MRV_IS_IS_H_OFFS_MAX (MRV_IS_IS_H_OFFS_MASK >> MRV_IS_IS_H_OFFS_SHIFT) +#endif /* MRV_IS_IS_H_OFFS */ +/*****************************************************************************/ +/** + * register: isp_is_v_offs: Vertical offset of output window (0x0000000c) + * + *****************************************************************************/ +/* Slice: is_v_offs:*/ +/* vertical picture offset in lines */ +#ifdef MRV_IS_IS_V_OFFS +#define MRV_IS_IS_V_OFFS_MAX (MRV_IS_IS_V_OFFS_MASK >> MRV_IS_IS_V_OFFS_SHIFT) +#endif /* MRV_IS_IS_V_OFFS */ +/*****************************************************************************/ +/** + * register: isp_is_h_size: Output horizontal picture size (0x00000010) + * + *****************************************************************************/ +/* Slice: is_h_size:*/ +/* horizontal picture size in pixel */ +/* if ISP_MODE is set to */ +/* 001-(ITU-R BT.656 YUV),*/ +/* 010-(ITU-R BT.601 YUV),*/ +/* 011-(ITU-R BT.601 Bayer RGB),*/ +/* 101-(ITU-R BT.656 Bayer RGB)*/ +/* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr)*/ +/* are needed for the following modules. If an odd size is programmed the value */ +/* will be truncated to even size.*/ +#ifdef MRV_IS_IS_H_SIZE +#define MRV_IS_IS_H_SIZE_MAX (MRV_IS_IS_H_SIZE_MASK >> MRV_IS_IS_H_SIZE_SHIFT) +#endif /* MRV_IS_IS_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_is_v_size: Output vertical picture size (0x00000014) + * + *****************************************************************************/ +/* Slice: is_v_size:*/ +/* vertical picture size in lines */ +#ifdef MRV_IS_IS_V_SIZE +#define MRV_IS_IS_V_SIZE_MAX (MRV_IS_IS_V_SIZE_MASK >> MRV_IS_IS_V_SIZE_SHIFT) +#endif /* MRV_IS_IS_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_is_max_dx: Maximum Horizontal Displacement (0x00000018) + * + *****************************************************************************/ +/* Slice: is_max_dx:*/ +/* maximum allowed accumulated horizontal displacement in pixels */ +#ifdef MRV_IS_IS_MAX_DX +#define MRV_IS_IS_MAX_DX_MAX (MRV_IS_IS_MAX_DX_MASK >> MRV_IS_IS_MAX_DX_SHIFT) +#endif /* MRV_IS_IS_MAX_DX */ +/*****************************************************************************/ +/** + * register: isp_is_max_dy: Maximum Vertical Displacement (0x0000001c) + * + *****************************************************************************/ +/* Slice: is_max_dy:*/ +/* maximum allowed accumulated vertical displacement in lines */ +#ifdef MRV_IS_IS_MAX_DY +#define MRV_IS_IS_MAX_DY_MAX (MRV_IS_IS_MAX_DY_MASK >> MRV_IS_IS_MAX_DY_SHIFT) +#endif /* MRV_IS_IS_MAX_DY */ +/*****************************************************************************/ +/** + * register: isp_is_displace: Camera displacement (0x00000020) + * + *****************************************************************************/ +/* Slice: dy:*/ +/* ISP_IS will compensate for vertical camera displacement of DY lines in the next frame */ +#ifdef MRV_IS_DY +#define MRV_IS_DY_MAX 0x000007FF +#define MRV_IS_DY_MIN (~MRV_IS_DY_MAX) +#endif /* MRV_IS_DY */ +/* Slice: dx:*/ +/* ISP_IS will compensate for horizontal camera displacement of DX pixels in the next frame */ +#ifdef MRV_IS_DX +#define MRV_IS_DX_MAX 0x000007FF +#define MRV_IS_DX_MIN (~MRV_IS_DX_MAX) +#endif /* MRV_IS_DX */ +/*****************************************************************************/ +/** + * register: isp_is_h_offs_shd: current horizontal offset of output window + * (shadow register) (0x00000024) + * + *****************************************************************************/ +/* Slice: is_h_offs_shd:*/ +/* current horizonatl picture offset in lines */ +#ifdef MRV_IS_IS_H_OFFS_SHD +#endif /* MRV_IS_IS_H_OFFS_SHD */ +/*****************************************************************************/ +/** + * register: isp_is_v_offs_shd: current vertical offset of output window + * (shadow register) (0x00000028) + * + *****************************************************************************/ +/* Slice: is_v_offs_shd:*/ +/* current vertical picture offset in lines */ +#ifdef MRV_IS_IS_V_OFFS_SHD +#endif /* MRV_IS_IS_V_OFFS_SHD */ +/*****************************************************************************/ +/** + * register: isp_is_h_size_shd: current output horizontal picture size + * (shadow register) (0x0000002c) + * + *****************************************************************************/ +/* Slice: isp_h_size_shd:*/ +/* current horizontal picture size in pixel */ +#ifdef MRV_IS_ISP_H_SIZE_SHD +#endif /* MRV_IS_ISP_H_SIZE_SHD */ +/*****************************************************************************/ +/** + * register: isp_is_v_size_shd: current output vertical picture size + * (shadow register) (0x00000030) + * + *****************************************************************************/ +/* Slice: isp_v_size_shd:*/ +/* vertical picture size in lines */ +#ifdef MRV_IS_ISP_V_SIZE_SHD +#endif /* MRV_IS_ISP_V_SIZE_SHD */ +/*****************************************************************************/ +/* ISP Histogram Module Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_hist_prop: Histogram properties (0x00000000) + * + *****************************************************************************/ +/* Slice: stepsize:*/ +/* histogram predivider, process every (stepsize)th pixel, all other pixels are skipped */ +/* 0,1,2: not allowed */ +/* 3: process every third input pixel */ +/* 4: process every fourth input pixel */ +/* ...*/ +/* 7FH: process every 127th pixel */ +#ifdef MRV_HIST_STEPSIZE +#define MRV_HIST_STEPSIZE_MIN 0x00000003 +#define MRV_HIST_STEPSIZE_MAX 0x0000007F +#endif /* MRV_HIST_STEPSIZE */ +/* Slice: hist_mode:*/ +/* histogram mode, luminance is taken at ISP output before output formatter,*/ +/* RGB is taken at xtalk output */ + /**/ +/* 7, 6: must not be used */ +/* 5: Y (luminance) histogram */ +/* 4: B histogram */ +/* 3: G histogram */ +/* 2: R histogram */ +/* 1: RGB combined histogram */ +/* 0: disable, no measurements */ +#ifdef MRV_HIST_MODE +#define MRV_HIST_MODE_MAX 5 /* because 6 and 7 are reserved */ +#define MRV_HIST_MODE_LUM 5 /* 5: Y (luminance) histogram */ +#define MRV_HIST_MODE_B 4 /* 4: B histogram */ +#define MRV_HIST_MODE_G 3 /* 3: G histogram */ +#define MRV_HIST_MODE_R 2 /* 2: R histogram */ +#define MRV_HIST_MODE_RGB 1 /* 1: RGB combined histogram */ +#define MRV_HIST_MODE_NONE 0 /* 0: disable, no measurements */ +#endif /* MRV_HIST_MODE */ +/*****************************************************************************/ +/** + * register: isp_hist_h_offs: Histogram window horizontal offset for first + * window of 25 sub-windows (0x00000004) + * + *****************************************************************************/ +/* Slice: hist_h_offset:*/ +/* Horizontal offset of first window in pixels.*/ +#ifdef MRV_HIST_H_OFFSET +#endif /* MRV_HIST_H_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_hist_v_offs: Histogram window vertical offset for first + * window of 25 sub-windows (0x00000008) + * + *****************************************************************************/ +/* Slice: hist_v_offset:*/ +/* Vertical offset of first window in pixels.*/ +#ifdef MRV_HIST_V_OFFSET +#endif /* MRV_HIST_V_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_hist_h_size: Horizontal (sub-)window size (0x0000000c) + * + *****************************************************************************/ +/* Slice: hist_h_size:*/ +/* Horizontal size in pixels of one sub-window, if histogram version 3 is implemented.*/ +#ifdef MRV_HIST_H_SIZE +#endif /* MRV_HIST_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_hist_v_size: Vertical (sub-)window size (0x00000010) + * + *****************************************************************************/ +/* Slice: hist_v_size:*/ +/* Vertical size in lines of one sub-window, if histogram version 3 is implemented.*/ +#ifdef MRV_HIST_V_SIZE +#endif /* MRV_HIST_V_SIZE */ +/*****************************************************************************/ +/** + * register array: isp_hist_bin: histogram measurement result bin + * (0x028 + n*0x4 (n=0..15)) + * + *****************************************************************************/ +/* Slice: hist_bin_n:*/ +/* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */ +#ifdef MRV_HIST_BIN_N +#define MRV_HIST_BIN_N_MAX (MRV_HIST_BIN_N_MASK >> MRV_HIST_BIN_N_SHIFT) +#endif /* MRV_HIST_BIN_N */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_00to30: Weighting factor for sub-windows + * (0x00000054) + * + *****************************************************************************/ +/* Slice: hist_weight_30:*/ +/* weighting factor for sub-window 30 */ +#ifdef MRV_HIST_WEIGHT_30 +#endif /* MRV_HIST_WEIGHT_30 */ +/* Slice: hist_weight_20:*/ +/* weighting factor for sub-window 20 */ +#ifdef MRV_HIST_WEIGHT_20 +#endif /* MRV_HIST_WEIGHT_20 */ +/* Slice: hist_weight_10:*/ +/* weighting factor for sub-window 10 */ +#ifdef MRV_HIST_WEIGHT_10 +#endif /* MRV_HIST_WEIGHT_10 */ +/* Slice: hist_weight_00:*/ +/* weighting factor for sub-window 00 */ +#ifdef MRV_HIST_WEIGHT_00 +#endif /* MRV_HIST_WEIGHT_00 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_40to21: Weighting factor for sub-windows + * (0x00000058) + * + *****************************************************************************/ +/* Slice: hist_weight_21:*/ +/* weighting factor for sub-window 21 */ +#ifdef MRV_HIST_WEIGHT_21 +#endif /* MRV_HIST_WEIGHT_21 */ +/* Slice: hist_weight_11:*/ +/* weighting factor for sub-window 11 */ +#ifdef MRV_HIST_WEIGHT_11 +#endif /* MRV_HIST_WEIGHT_11 */ +/* Slice: hist_weight_01:*/ +/* weighting factor for sub-window 01 */ +#ifdef MRV_HIST_WEIGHT_01 +#endif /* MRV_HIST_WEIGHT_01 */ +/* Slice: hist_weight_40:*/ +/* weighting factor for sub-window 40 */ +#ifdef MRV_HIST_WEIGHT_40 +#endif /* MRV_HIST_WEIGHT_40 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_31to12: Weighting factor for sub-windows + * (0x0000005c) + * + *****************************************************************************/ +/* Slice: hist_weight_12:*/ +/* weighting factor for sub-window 12 */ +#ifdef MRV_HIST_WEIGHT_12 +#endif /* MRV_HIST_WEIGHT_12 */ +/* Slice: hist_weight_02:*/ +/* weighting factor for sub-window 02 */ +#ifdef MRV_HIST_WEIGHT_02 +#endif /* MRV_HIST_WEIGHT_02 */ +/* Slice: hist_weight_41:*/ +/* weighting factor for sub-window 41 */ +#ifdef MRV_HIST_WEIGHT_41 +#endif /* MRV_HIST_WEIGHT_41 */ +/* Slice: hist_weight_31:*/ +/* weighting factor for sub-window 31 */ +#ifdef MRV_HIST_WEIGHT_31 +#endif /* MRV_HIST_WEIGHT_31 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_22to03: Weighting factor for sub-windows + * (0x00000060) + * + *****************************************************************************/ +/* Slice: hist_weight_03:*/ +/* weighting factor for sub-window 03 */ +#ifdef MRV_HIST_WEIGHT_03 +#endif /* MRV_HIST_WEIGHT_03 */ +/* Slice: hist_weight_42:*/ +/* weighting factor for sub-window 42 */ +#ifdef MRV_HIST_WEIGHT_42 +#endif /* MRV_HIST_WEIGHT_42 */ +/* Slice: hist_weight_32:*/ +/* weighting factor for sub-window 32 */ +#ifdef MRV_HIST_WEIGHT_32 +#endif /* MRV_HIST_WEIGHT_32 */ +/* Slice: hist_weight_22:*/ +/* weighting factor for sub-window 22 */ +#ifdef MRV_HIST_WEIGHT_22 +#endif /* MRV_HIST_WEIGHT_22 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_13to43: Weighting factor for sub-windows + * (0x00000064) + * + *****************************************************************************/ +/* Slice: hist_weight_43:*/ +/* weighting factor for sub-window 43 */ +#ifdef MRV_HIST_WEIGHT_43 +#endif /* MRV_HIST_WEIGHT_43 */ +/* Slice: hist_weight_33:*/ +/* weighting factor for sub-window 33 */ +#ifdef MRV_HIST_WEIGHT_33 +#endif /* MRV_HIST_WEIGHT_33 */ +/* Slice: hist_weight_23:*/ +/* weighting factor for sub-window 23 */ +#ifdef MRV_HIST_WEIGHT_23 +#endif /* MRV_HIST_WEIGHT_23 */ +/* Slice: hist_weight_13:*/ +/* weighting factor for sub-window 13 */ +#ifdef MRV_HIST_WEIGHT_13 +#endif /* MRV_HIST_WEIGHT_13 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_04to34: Weighting factor for sub-windows + * (0x00000068) + * + *****************************************************************************/ +/* Slice: hist_weight_34:*/ +/* weighting factor for sub-window 34 */ +#ifdef MRV_HIST_WEIGHT_34 +#endif /* MRV_HIST_WEIGHT_34 */ +/* Slice: hist_weight_24:*/ +/* weighting factor for sub-window 24 */ +#ifdef MRV_HIST_WEIGHT_24 +#endif /* MRV_HIST_WEIGHT_24 */ +/* Slice: hist_weight_14:*/ +/* weighting factor for sub-window 14 */ +#ifdef MRV_HIST_WEIGHT_14 +#endif /* MRV_HIST_WEIGHT_14 */ +/* Slice: hist_weight_04:*/ +/* weighting factor for sub-window 04 */ +#ifdef MRV_HIST_WEIGHT_04 +#endif /* MRV_HIST_WEIGHT_04 */ +/*****************************************************************************/ +/** + * register: isp_hist_weight_44: Weighting factor for sub-windows (0x0000006c) + * + *****************************************************************************/ +/* Slice: hist_weight_44:*/ +/* weighting factor for sub-window 44 */ +#ifdef MRV_HIST_WEIGHT_44 +#endif /* MRV_HIST_WEIGHT_44 */ +#define MRV_HIST_WEIGHT_MAX 0x10 +/*****************************************************************************/ +/* ISP Filter Module Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_filt_mode: mode control register for the filter block + * (0x00000000) + * + *****************************************************************************/ +/* Slice: stage1_select:*/ +/* Green filter stage 1 select (range 0x0...0x8)*/ +/* 0x0 maximum blurring */ +/* 0x4 Default */ +/* 0x7 minimum blurring */ +/* 0x8 filter stage1 bypass */ +/* For a detailed description refer to chapter "ISP Filter Programming" of user manual */ +#ifdef MRV_FILT_STAGE1_SELECT +#define MRV_FILT_STAGE1_SELECT_MAX_BLUR 0U /* 0x0 maximum blurring */ +#define MRV_FILT_STAGE1_SELECT_DEFAULT 4U /* 0x4 Default */ +#define MRV_FILT_STAGE1_SELECT_MIN_BLUR 7U /* 0x7 minimum blurring */ +#define MRV_FILT_STAGE1_SELECT_BYPASS 8U /* 0x8 filter stage1 bypass */ +#endif /* MRV_FILT_STAGE1_SELECT */ +/* Slice: filt_chr_h_mode:*/ +/* Chroma filter horizontal mode */ +/* 00 horizontal chroma filter bypass */ +/* 01 horizontal chroma filter 1 static mask = [10 12 10]*/ +/* 10 horizontal chroma filter 2 (dynamic blur1)*/ +/* 11 horizontal chroma filter 3 (dynamic blur2) Default */ +#ifdef MRV_FILT_FILT_CHR_H_MODE +#define MRV_FILT_FILT_CHR_H_MODE_BYPASS 0U /* 00 horizontal chroma filter bypass */ +#define MRV_FILT_FILT_CHR_H_MODE_STATIC 1U /* 01 horizontal chroma filter 1 static mask = [10 12 10] */ +#define MRV_FILT_FILT_CHR_H_MODE_DYN_1 2U /* 10 horizontal chroma filter 2 (dynamic blur1) */ +#define MRV_FILT_FILT_CHR_H_MODE_DYN_2 3U /* 11 horizontal chroma filter 3 (dynamic blur2) Default */ +#endif /* MRV_FILT_FILT_CHR_H_MODE */ +/* Slice: filt_chr_v_mode:*/ +/* Chroma filter vertical mode */ +/* 00 vertical chroma filter bypass */ +/* 01 vertical chroma filter 1 static [8 16 8]*/ +/* 10 vertical chroma filter 2 static [10 12 10]*/ +/* 11 vertical chroma filter 3 static [12 8 12] Default */ +#ifdef MRV_FILT_FILT_CHR_V_MODE +#define MRV_FILT_FILT_CHR_V_MODE_BYPASS 0U /* 00 vertical chroma filter bypass */ +#define MRV_FILT_FILT_CHR_V_MODE_STATIC8 1U /* 01 vertical chroma filter 1 static [8 16 8] */ +#define MRV_FILT_FILT_CHR_V_MODE_STATIC10 2U /* 10 vertical chroma filter 2 static [10 12 10] */ +#define MRV_FILT_FILT_CHR_V_MODE_STATIC12 3U /* 11 vertical chroma filter 3 static [12 8 12] Default */ +#endif /* MRV_FILT_FILT_CHR_V_MODE */ +/* Slice: filt_mode:*/ +/* 0 green filter static mode (active filter factor = FILT_FAC_MID)*/ +/* 1 dynamic noise reduction/sharpen Default */ +#ifdef MRV_FILT_FILT_MODE +#define MRV_FILT_FILT_MODE_STATIC 0U /* 0 green filter static mode (active filter factor = FILT_FAC_MID) */ +#define MRV_FILT_FILT_MODE_DYNAMIC 1U /* 1 dynamic noise reduction/sharpen Default */ +#endif /* MRV_FILT_FILT_MODE */ +/* Slice: filt_enable:*/ +/* 1 enable filter */ +/* 0 bypass filter Default */ +#ifdef MRV_FILT_FILT_ENABLE +#define MRV_FILT_FILT_ENABLE_PROCESS 1U +#define MRV_FILT_FILT_ENABLE_BYPASS 0U +#endif /* MRV_FILT_FILT_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_filt_thresh_bl0: Blurring threshold 0 (0x00000028) + * + *****************************************************************************/ +/* Slice: filt_thresh_bl0:*/ +/* If filt_thresh_bl1 < sum_grad < filt_thresh_bl0 then filt_fac_bl0 is selected */ +#ifdef MRV_FILT_FILT_THRESH_BL0 +#endif /* MRV_FILT_FILT_THRESH_BL0 */ +/*****************************************************************************/ +/** + * register: isp_filt_thresh_bl1: Blurring threshold 1 (0x0000002c) + * + *****************************************************************************/ +/* Slice: filt_thresh_bl1:*/ +/* If sum_grad < filt_thresh_bl1 then filt_fac_bl1 is selected */ +#ifdef MRV_FILT_FILT_THRESH_BL1 +#endif /* MRV_FILT_FILT_THRESH_BL1 */ +/*****************************************************************************/ +/** + * register: isp_filt_thresh_sh0: Sharpening threshold 0 (0x00000030) + * + *****************************************************************************/ +/* Slice: filt_thresh_sh0:*/ +/* If filt_thresh_sh0 < sum_grad < filt_thresh_sh1 then filt_thresh_sh0 is selected */ +#ifdef MRV_FILT_FILT_THRESH_SH0 +#endif /* MRV_FILT_FILT_THRESH_SH0 */ +/*****************************************************************************/ +/** + * register: isp_filt_thresh_sh1: Sharpening threshold 1 (0x00000034) + * + *****************************************************************************/ +/* Slice: filt_thresh_sh1:*/ +/* If filt_thresh_sh1 < sum_grad then filt_thresh_sh1 is selected */ +#ifdef MRV_FILT_FILT_THRESH_SH1 +#endif /* MRV_FILT_FILT_THRESH_SH1 */ +/*****************************************************************************/ +/** + * register: isp_filt_lum_weight: Parameters for luminance weight function + * (0x00000038) + * + *****************************************************************************/ +/* Slice: lum_weight_gain:*/ +/* Gain select of luminance weight function */ +#ifdef MRV_FILT_LUM_WEIGHT_GAIN +#endif /* MRV_FILT_LUM_WEIGHT_GAIN */ +/* Slice: lum_weight_kink:*/ +/* Kink position of luminance weight function */ +#ifdef MRV_FILT_LUM_WEIGHT_KINK +#endif /* MRV_FILT_LUM_WEIGHT_KINK */ +/* Slice: lum_weight_min:*/ +/* Minimum value of luminance weight function */ +#ifdef MRV_FILT_LUM_WEIGHT_MIN +#endif /* MRV_FILT_LUM_WEIGHT_MIN */ +/*****************************************************************************/ +/** + * register: isp_filt_fac_sh1: filter factor sharp1 (0x0000003c) + * + *****************************************************************************/ +/* Slice: filt_fac_sh1:*/ +/* Filter factor for sharp1 level */ +#ifdef MRV_FILT_FILT_FAC_SH1 +#endif /* MRV_FILT_FILT_FAC_SH1 */ +/*****************************************************************************/ +/** + * register: isp_filt_fac_sh0: filter factor sharp0 (0x00000040) + * + *****************************************************************************/ +/* Slice: filt_fac_sh0:*/ +/* Filter factor for sharp0 level */ +#ifdef MRV_FILT_FILT_FAC_SH0 +#endif /* MRV_FILT_FILT_FAC_SH0 */ +/*****************************************************************************/ +/** + * register: isp_filt_fac_mid: filter factor middle (0x00000044) + * + *****************************************************************************/ +/* Slice: filt_fac_mid:*/ +/* Filter factor for mid level and for static filter mode */ +#ifdef MRV_FILT_FILT_FAC_MID +#endif /* MRV_FILT_FILT_FAC_MID */ +/*****************************************************************************/ +/** + * register: isp_filt_fac_bl0: Parameter for blur 0 filter (0x00000048) + * + *****************************************************************************/ +/* Slice: filt_fac_bl0:*/ +/* Filter factor for blur 0 level */ +#ifdef MRV_FILT_FILT_FAC_BL0 +#endif /* MRV_FILT_FILT_FAC_BL0 */ +/*****************************************************************************/ +/** + * register: isp_filt_fac_bl1: Parameter for blur 1 filter (0x0000004c) + * + *****************************************************************************/ +/* Slice: filt_fac_bl1:*/ +/* Filter factor for blur 1 level (max blur)*/ +#ifdef MRV_FILT_FILT_FAC_BL1 +#endif /* MRV_FILT_FILT_FAC_BL1 */ +/*****************************************************************************/ +/* ISP Auto Focus Measurement Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_afm_ctrl: This is the control register for AF measurement + * unit (0x00000000) + * + *****************************************************************************/ +/* Slice: afm_en:*/ +/* AF measurement enable */ +/* 0: AF measurement is disabled */ +/* 1: AF measurement is enabled */ +/* Writing a 1 to this register starts a new measurement and resets the afm_fin (measurement finished) interrupt to 0.*/ +/* As long as the afm_en is 1, the AFM unit calculates new sharpness values for each frame.*/ +#ifdef MRV_AFM_AFM_EN +#define MRV_AFM_AFM_EN_ENABLE 1 /* 1: enable AF measurment */ +#define MRV_AFM_AFM_EN_DISABLE 0 /* 0: processing is deactivated, bypass mode is selected */ +#endif /* MRV_AFM_AFM_EN */ +/*****************************************************************************/ +/** + * register: isp_afm_lt_a: Top Left corner of measure window A (0x00000004) + * + *****************************************************************************/ +/* Slice: a_h_l:*/ +/* first pixel of window A (horizontal left row), value must be greater or equal 5 */ +#ifdef MRV_AFM_A_H_L +#define MRV_AFM_A_H_L_MIN (5U) +#define MRV_AFM_A_H_L_MAX (MRV_AFM_A_H_L_MASK >> MRV_AFM_A_H_L_SHIFT) +#endif /* MRV_AFM_A_H_L */ +/* Slice: a_v_t:*/ +/* first line of window A (vertical top line), value must be greater or equal 2 */ +#ifdef MRV_AFM_A_V_T +#define MRV_AFM_A_V_T_MIN (2U) +#define MRV_AFM_A_V_T_MAX (MRV_AFM_A_V_T_MASK >> MRV_AFM_A_V_T_SHIFT) +#endif /* MRV_AFM_A_V_T */ +/*****************************************************************************/ +/** + * register: isp_afm_rb_a: Bottom right corner of measure window A (0x00000008) + * + *****************************************************************************/ +/* Slice: a_h_r:*/ +/* last pixel of window A (horizontal right row)*/ +#ifdef MRV_AFM_A_H_R +#define MRV_AFM_A_H_R_MIN (5U) +#define MRV_AFM_A_H_R_MAX (MRV_AFM_A_H_R_MASK >> MRV_AFM_A_H_R_SHIFT) +#endif /* MRV_AFM_A_H_R */ +/* Slice: a_v_b:*/ +/* last line of window A (vertical bottom line), value must be lower than */ +/* (number of lines -2)*/ +#ifdef MRV_AFM_A_V_B +#define MRV_AFM_A_V_B_MIN (2U) +#define MRV_AFM_A_V_B_MAX (MRV_AFM_A_V_B_MASK >> MRV_AFM_A_V_B_SHIFT) +#endif /* MRV_AFM_A_V_B */ +/*****************************************************************************/ +/** + * register: isp_afm_lt_b: Top left corner of measure window B (0x0000000c) + * + *****************************************************************************/ +/* Slice: b_h_l:*/ +/* first pixel of window B (horizontal left row), value must be greater or equal 5 */ +#ifdef MRV_AFM_B_H_L +#define MRV_AFM_B_H_L_MIN (5U) +#define MRV_AFM_B_H_L_MAX (MRV_AFM_B_H_L_MASK >> MRV_AFM_B_H_L_SHIFT) +#endif /* MRV_AFM_B_H_L */ +/* Slice: b_v_t:*/ +/* first line of window B (vertical top line), value must be greater or equal 2 */ +#ifdef MRV_AFM_B_V_T +#define MRV_AFM_B_V_T_MIN (2U) +#define MRV_AFM_B_V_T_MAX (MRV_AFM_B_V_T_MASK >> MRV_AFM_B_V_T_SHIFT) +#endif /* MRV_AFM_B_V_T */ +/*****************************************************************************/ +/** + * register: isp_afm_rb_b: Bottom right corner of measure window B (0x00000010) + * + *****************************************************************************/ +/* Slice: b_h_r:*/ +/* last pixel of window B (horizontal right row)*/ +#ifdef MRV_AFM_B_H_R +#define MRV_AFM_B_H_R_MIN (5U) +#define MRV_AFM_B_H_R_MAX (MRV_AFM_B_H_R_MASK >> MRV_AFM_B_H_R_SHIFT) +#endif /* MRV_AFM_B_H_R */ +/* Slice: b_v_b:*/ +/* last line of window B (vertical bottom line), value must be lower than */ +/* (number of lines -2)*/ +#ifdef MRV_AFM_B_V_B +#define MRV_AFM_B_V_B_MIN (2U) +#define MRV_AFM_B_V_B_MAX (MRV_AFM_B_V_B_MASK >> MRV_AFM_B_V_B_SHIFT) +#endif /* MRV_AFM_B_V_B */ +/*****************************************************************************/ +/** + * register: isp_afm_lt_c: Top left corner of measure window C (0x00000014) + * + *****************************************************************************/ +/* Slice: c_h_l:*/ +/* first pixel of window C (horizontal left row), value must be greater or equal 5 */ +#ifdef MRV_AFM_C_H_L +#define MRV_AFM_C_H_L_MIN (5U) +#define MRV_AFM_C_H_L_MAX (MRV_AFM_C_H_L_MASK >> MRV_AFM_C_H_L_SHIFT) +#endif /* MRV_AFM_C_H_L */ +/* Slice: c_v_t:*/ +/* first line of window C (vertical top line), value must be greater or equal 2 */ +#ifdef MRV_AFM_C_V_T +#define MRV_AFM_C_V_T_MIN (2U) +#define MRV_AFM_C_V_T_MAX (MRV_AFM_C_V_T_MASK >> MRV_AFM_C_V_T_SHIFT) +#endif /* MRV_AFM_C_V_T */ +/*****************************************************************************/ +/** + * register: isp_afm_rb_c: Bottom right corner of measure window C (0x00000018) + * + *****************************************************************************/ +/* Slice: c_h_r:*/ +/* last pixel of window C (horizontal right row)*/ +#ifdef MRV_AFM_C_H_R +#define MRV_AFM_C_H_R_MIN (5U) +#define MRV_AFM_C_H_R_MAX (MRV_AFM_C_H_R_MASK >> MRV_AFM_C_H_R_SHIFT) +#endif /* MRV_AFM_C_H_R */ +/* Slice: c_v_b:*/ +/* last line of window C (vertical bottom line), value must be lower than */ +/* (number of lines -2)*/ +#ifdef MRV_AFM_C_V_B +#define MRV_AFM_C_V_B_MIN (2U) +#define MRV_AFM_C_V_B_MAX (MRV_AFM_C_V_B_MASK >> MRV_AFM_C_V_B_SHIFT) +#endif /* MRV_AFM_C_V_B */ +/*****************************************************************************/ +/** + * register: isp_afm_thres: Threshold register (0x0000001c) + * + *****************************************************************************/ +/* Slice: afm_thres:*/ +/* AF measurement threshold */ +/* This register defines a threshold which can be used for minimizing the */ +/* influence of noise in the measurement result.*/ +#ifdef MRV_AFM_AFM_THRES +#endif /* MRV_AFM_AFM_THRES */ +/*****************************************************************************/ +/** + * register: isp_afm_var_shift: Variable shift register (0x00000020) + * + *****************************************************************************/ +/* Slice: lum_var_shift:*/ +/* variable shift for luminance summation */ +/* The lum_var_shift defines the number of bits for the shift operation of the */ +/* value of the current pixel before summation. The shift operation is used to */ +/* avoid a luminance sum overflow.*/ +#ifdef MRV_AFM_LUM_VAR_SHIFT +#endif /* MRV_AFM_LUM_VAR_SHIFT */ +/* Slice: afm_var_shift:*/ +/* variable shift for AF measurement */ +/* The afm_var_shift defines the number of bits for the shift operation at the */ +/* end of the calculation chain. The shift operation is used to avoid an AF */ +/* measurement sum overflow.*/ +#ifdef MRV_AFM_AFM_VAR_SHIFT +#endif /* MRV_AFM_AFM_VAR_SHIFT */ +/*****************************************************************************/ +/** + * register: isp_afm_sum_a: Sharpness Value Status Register of Window A (0x0024) + * + *****************************************************************************/ +/* Slice: afm_sum_a:*/ +/* sharpness value of window A */ +#ifdef MRV_AFM_AFM_SUM_A +#endif /* MRV_AFM_AFM_SUM_A */ +/*****************************************************************************/ +/** + * register: isp_afm_sum_b: Sharpness Value Status Register of Window B (0x0028) + * + *****************************************************************************/ +/* Slice: afm_sum_b:*/ +/* sharpness value of window B */ +#ifdef MRV_AFM_AFM_SUM_B +#endif /* MRV_AFM_AFM_SUM_B */ +/*****************************************************************************/ +/** + * register: isp_afm_sum_c: Sharpness Value Status Register of Window C (0x002c) + * + *****************************************************************************/ +/* Slice: afm_sum_c:*/ +/* sharpness value of window C */ +#ifdef MRV_AFM_AFM_SUM_C +#endif /* MRV_AFM_AFM_SUM_C */ +/*****************************************************************************/ +/** + * register: isp_afm_lum_a: Luminance Value Status Register of Window A (0x0030) + * + *****************************************************************************/ +/* Slice: afm_lum_a:*/ +/* luminance value of window A */ +#ifdef MRV_AFM_AFM_LUM_A +#endif /* MRV_AFM_AFM_LUM_A */ +/*****************************************************************************/ +/** + * register: isp_afm_lum_b: Luminance Value Status Register of Window B (0x0034) + * + *****************************************************************************/ +/* Slice: afm_lum_b:*/ +/* luminance value of window B */ +#ifdef MRV_AFM_AFM_LUM_B +#endif /* MRV_AFM_AFM_LUM_B */ +/*****************************************************************************/ +/** + * register: isp_afm_lum_c: Luminance Value Status Register of Window C (0x0038) + * + *****************************************************************************/ +/* Slice: afm_lum_c:*/ +/* luminance value of window C */ +#ifdef MRV_AFM_AFM_LUM_C +#endif /* MRV_AFM_AFM_LUM_C */ +/*****************************************************************************/ +/* ISP Lens Shade Correction Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_lsc_ctrl: Lens shade control (0x00000000) + * + *****************************************************************************/ +/* Slice: lsc_en:*/ +/* 0: activation request for lens shading correction */ +/* 1: deactivation reqeust for lens shading correction */ +/* Activation/Deactivation is object of a shadowing mechnism. The current */ +/* status is visible at ISP_LSC_STATUS::lsc_enable_status */ +#ifdef MRV_LSC_LSC_EN +#define MRV_LSC_LSC_EN_ENABLE 1U +#define MRV_LSC_LSC_EN_DISABLE 0U +#endif /* MRV_LSC_LSC_EN */ +/*****************************************************************************/ +/** + * register: isp_lsc_r_table_addr: Table RAM Address for red component (0x00000004) + * + *****************************************************************************/ +/* Slice: r_ram_addr:*/ +/* table address in RAM for samples of the R color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +/* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */ +/* (if available).*/ +#ifdef MRV_LSC_R_RAM_ADDR +#define MRV_LSC_R_RAM_ADDR_MIN_BANK0 (0x00000000U) +#define MRV_LSC_R_RAM_ADDR_MAX_BANK0 (0x00000098U) +#define MRV_LSC_R_RAM_ADDR_MIN_BANK1 (0x00000099U) +#define MRV_LSC_R_RAM_ADDR_MAX_BANK1 (0x00000132U) +#endif /* MRV_LSC_R_RAM_ADDR */ +/*****************************************************************************/ +/** + * register: isp_lsc_gr_table_addr: Table RAM Address for green (red) component + * (0x00000008) + * + *****************************************************************************/ +/* Slice: gr_ram_addr:*/ +/* table address in RAM for samples of the G_R color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +/* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */ +/* (if available).*/ +#ifdef MRV_LSC_GR_RAM_ADDR +#define MRV_LSC_GR_RAM_ADDR_MIN_BANK0 (0x00000000U) +#define MRV_LSC_GR_RAM_ADDR_MAX_BANK0 (0x00000098U) +#define MRV_LSC_GR_RAM_ADDR_MIN_BANK1 (0x00000099U) +#define MRV_LSC_GR_RAM_ADDR_MAX_BANK1 (0x00000131U) +#endif /* MRV_LSC_GR_RAM_ADDR */ +/*****************************************************************************/ +/** + * register: isp_lsc_b_table_addr: Table RAM Address for blue component + * (0x0000000c) + * + *****************************************************************************/ +/* Slice: b_ram_addr:*/ +/* table address in RAM for samples of the B color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +/* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */ +/* (if available).*/ +#ifdef MRV_LSC_B_RAM_ADDR +#define MRV_LSC_B_RAM_ADDR_MIN_BANK0 (0x00000000U) +#define MRV_LSC_B_RAM_ADDR_MAX_BANK0 (0x00000098U) +#define MRV_LSC_B_RAM_ADDR_MIN_BANK1 (0x00000099U) +#define MRV_LSC_B_RAM_ADDR_MAX_BANK1 (0x00000132U) +#endif /* MRV_LSC_B_RAM_ADDR */ +/*****************************************************************************/ +/** + * register: isp_lsc_gb_table_addr: Table RAM Address for green (blue) component + * (0x00000010) + * + *****************************************************************************/ +/* Slice: gb_ram_addr:*/ +/* table address in RAM for samples of the G_B color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +/* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */ +/* (if available).*/ +#ifdef MRV_LSC_GB_RAM_ADDR +#define MRV_LSC_GB_RAM_ADDR_MIN_BANK0 (0x00000000U) +#define MRV_LSC_GB_RAM_ADDR_MAX_BANK0 (0x00000098U) +#define MRV_LSC_GB_RAM_ADDR_MIN_BANK1 (0x00000099U) +#define MRV_LSC_GB_RAM_ADDR_MAX_BANK1 (0x00000132U) +#endif /* MRV_LSC_GB_RAM_ADDR */ +/*****************************************************************************/ +/** + * register: isp_lsc_r_table_data: Sample table red (0x00000014) + * + *****************************************************************************/ +/* Slice: r_sample_1:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_R_SAMPLE_1 +#endif /* MRV_LSC_R_SAMPLE_1 */ +/* Slice: r_sample_0:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_R_SAMPLE_0 +#endif /* MRV_LSC_R_SAMPLE_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_gr_table_data: Sample table green (red) (0x00000018) + * + *****************************************************************************/ +/* Slice: gr_sample_1:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_GR_SAMPLE_1 +#endif /* MRV_LSC_GR_SAMPLE_1 */ +/* Slice: gr_sample_0:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_GR_SAMPLE_0 +#endif /* MRV_LSC_GR_SAMPLE_0 */ +/*****************************************************************************/ +/** + * register: Register: isp_lsc_b_table_data: Sample table blue (0x0000001c) + * + *****************************************************************************/ +/* Slice: b_sample_1:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_B_SAMPLE_1 +#endif /* MRV_LSC_B_SAMPLE_1 */ +/* Slice: b_sample_0:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_B_SAMPLE_0 +#endif /* MRV_LSC_B_SAMPLE_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_gb_table_data: Sample table green (blue) (0x00000020) + * + *****************************************************************************/ +/* Slice: gb_sample_1:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_GB_SAMPLE_1 +#endif /* MRV_LSC_GB_SAMPLE_1 */ +/* Slice: gb_sample_0:*/ +/* correction factor at sample point (fixed point number: 2 bits integer with */ +/* 10-bit fractional part, range 1..3.999)*/ +#ifdef MRV_LSC_GB_SAMPLE_0 +#endif /* MRV_LSC_GB_SAMPLE_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xgrad_01: Gradient table x (0x00000024) + * + *****************************************************************************/ +/* Slice: xgrad_1:*/ +/* factor for x-gradient calculation of sector 1 */ +#ifdef MRV_LSC_XGRAD_1 +#endif /* MRV_LSC_XGRAD_1 */ +/* Slice: xgrad_0:*/ +/* factor for x-gradient calculation of sector 0 */ +#ifdef MRV_LSC_XGRAD_0 +#endif /* MRV_LSC_XGRAD_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xgrad_23: Gradient table x (0x00000028) + * + *****************************************************************************/ +/* Slice: xgrad_3:*/ +/* factor for x-gradient calculation of sector 3 */ +#ifdef MRV_LSC_XGRAD_3 +#endif /* MRV_LSC_XGRAD_3 */ +/* Slice: xgrad_2:*/ +/* factor for x-gradient calculation of sector 2 */ +#ifdef MRV_LSC_XGRAD_2 +#endif /* MRV_LSC_XGRAD_2 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xgrad_45: Gradient table x (0x0000002c) + * + *****************************************************************************/ +/* Slice: xgrad_5:*/ +/* factor for x-gradient calculation of sector 5 */ +#ifdef MRV_LSC_XGRAD_5 +#endif /* MRV_LSC_XGRAD_5 */ +/* Slice: xgrad_4:*/ +/* factor for x-gradient calculation of sector 4 */ +#ifdef MRV_LSC_XGRAD_4 +#endif /* MRV_LSC_XGRAD_4 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xgrad_67: Gradient table x (0x00000030) + * + *****************************************************************************/ +/* Slice: xgrad_7:*/ +/* factor for x-gradient calculation of sector 7 */ +#ifdef MRV_LSC_XGRAD_7 +#endif /* MRV_LSC_XGRAD_7 */ +/* Slice: xgrad_6:*/ +/* factor for x-gradient calculation of sector 6 */ +#ifdef MRV_LSC_XGRAD_6 +#endif /* MRV_LSC_XGRAD_6 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ygrad_01: Gradient table y (0x00000034) + * + *****************************************************************************/ +/* Slice: ygrad_1:*/ +/* factor for y-gradient calculation of sector 1 */ +#ifdef MRV_LSC_YGRAD_1 +#endif /* MRV_LSC_YGRAD_1 */ +/* Slice: ygrad_0:*/ +/* factor for y-gradient calculation of sector 0 */ +#ifdef MRV_LSC_YGRAD_0 +#endif /* MRV_LSC_YGRAD_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ygrad_23: Gradient table y (0x00000038) + * + *****************************************************************************/ +/* Slice: ygrad_3:*/ +/* factor for y-gradient calculation of sector 3 */ +#ifdef MRV_LSC_YGRAD_3 +#endif /* MRV_LSC_YGRAD_3 */ +/* Slice: ygrad_2:*/ +/* factor for y-gradient calculation of sector 2 */ +#ifdef MRV_LSC_YGRAD_2 +#endif /* MRV_LSC_YGRAD_2 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ygrad_45: Gradient table y (0x0000003c) + * + *****************************************************************************/ +/* Slice: ygrad_5:*/ +/* factor for y-gradient calculation of sector 5 */ +#ifdef MRV_LSC_YGRAD_5 +#endif /* MRV_LSC_YGRAD_5 */ +/* Slice: ygrad_4:*/ +/* factor for y-gradient calculation of sector 4 */ +#ifdef MRV_LSC_YGRAD_4 +#endif /* MRV_LSC_YGRAD_4 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ygrad_67: Gradient table y (0x00000040) + * + *****************************************************************************/ +/* Slice: ygrad_7:*/ +/* factor for y-gradient calculation of sector 7 */ +#ifdef MRV_LSC_YGRAD_7 +#endif /* MRV_LSC_YGRAD_7 */ +/* Slice: ygrad_6:*/ +/* factor for y-gradient calculation of sector 6 */ +#ifdef MRV_LSC_YGRAD_6 +#endif /* MRV_LSC_YGRAD_6 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xsize_01: Size table (0x00000044) + * + *****************************************************************************/ +/* Slice: x_sect_size_1:*/ +/* sector size 1 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_1 +#endif /* MRV_LSC_X_SECT_SIZE_1 */ +/* Slice: x_sect_size_0:*/ +/* sector size 0 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_0 +#endif /* MRV_LSC_X_SECT_SIZE_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xsize_23: Size table (0x00000048) + * + *****************************************************************************/ +/* Slice: x_sect_size_3:*/ +/* sector size 3 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_3 +#endif /* MRV_LSC_X_SECT_SIZE_3 */ +/* Slice: x_sect_size_2:*/ +/* sector size 2 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_2 +#endif /* MRV_LSC_X_SECT_SIZE_2 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xsize_45: Size table (0x0000004c) + * + *****************************************************************************/ +/* Slice: x_sect_size_5:*/ +/* sector size 5 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_5 +#endif /* MRV_LSC_X_SECT_SIZE_5 */ +/* Slice: x_sect_size_4:*/ +/* sector size 4in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_4 +#endif /* MRV_LSC_X_SECT_SIZE_4 */ +/*****************************************************************************/ +/** + * register: isp_lsc_xsize_67: Size table (0x00000050) + * + *****************************************************************************/ +/* Slice: x_sect_size_7:*/ +/* sector size 7 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_7 +#endif /* MRV_LSC_X_SECT_SIZE_7 */ +/* Slice: x_sect_size_6:*/ +/* sector size 6 in x-direction */ +#ifdef MRV_LSC_X_SECT_SIZE_6 +#endif /* MRV_LSC_X_SECT_SIZE_6 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ysize_01: Size table (0x00000054) + * + *****************************************************************************/ +/* Slice: y_sect_size_1:*/ +/* sector size 1 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_1 +#endif /* MRV_LSC_Y_SECT_SIZE_1 */ +/* Slice: y_sect_size_0:*/ +/* sector size 0 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_0 +#endif /* MRV_LSC_Y_SECT_SIZE_0 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ysize_23: Size table (0x00000058) + * + *****************************************************************************/ +/* Slice: y_sect_size_3:*/ +/* sector size 3 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_3 +#endif /* MRV_LSC_Y_SECT_SIZE_3 */ +/* Slice: y_sect_size_2:*/ +/* sector size 2 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_2 +#endif /* MRV_LSC_Y_SECT_SIZE_2 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ysize_45: Size table (0x0000005c) + * + *****************************************************************************/ +/* Slice: y_sect_size_5:*/ +/* sector size 5 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_5 +#endif /* MRV_LSC_Y_SECT_SIZE_5 */ +/* Slice: y_sect_size_4:*/ +/* sector size 4 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_4 +#endif /* MRV_LSC_Y_SECT_SIZE_4 */ +/*****************************************************************************/ +/** + * register: isp_lsc_ysize_67: Size table (0x00000060) + * + *****************************************************************************/ +/* Slice: y_sect_size_7:*/ +/* sector size 7 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_7 +#endif /* MRV_LSC_Y_SECT_SIZE_7 */ +/* Slice: y_sect_size_6:*/ +/* sector size 6 in y-direction */ +#ifdef MRV_LSC_Y_SECT_SIZE_6 +#endif /* MRV_LSC_Y_SECT_SIZE_6 */ +/*****************************************************************************/ +/** + * register: isp_lsc_table_sel: Lens shade table set selection (0x00000064) + * + *****************************************************************************/ +/* Slice: table_sel:*/ +/* 0: next active tables set is table set 0.*/ +/* 1: next active tables set is table set 1.*/ +/* Table selection is object of a shadowing mechnism. The current status is */ +/* visible at ISP_LSC_STATUS::active_table.*/ +#ifdef MRV_LSC_TABLE_SEL +#define MRV_LSC_TABLE_SEL_BANK0 (0U) +#define MRV_LSC_TABLE_SEL_BANK1 (1U) +#endif /* MRV_LSC_TABLE_SEL */ +/*****************************************************************************/ +/** + * register: isp_lsc_status: Lens shade status (0x00000068) + * + *****************************************************************************/ +/* Slice: active_table:*/ +/* 0: currently active tables set is table set 0 */ +/* 1: currently active tables set is table set 1 */ +#ifdef MRV_LSC_ACTIVE_TABLE +#define MRV_LSC_ACTIVE_TABLE_BANK0 (0U) +#define MRV_LSC_ACTIVE_TABLE_BANK1 (1U) +#endif /* MRV_LSC_ACTIVE_TABLE */ +/* Slice: lsc_en_status:*/ +/* 0: lens shading correction is currently off */ +/* 1: lens shading correction is currently on */ +#ifdef MRV_LSC_LSC_EN_STATUS +#endif /* MRV_LSC_LSC_EN_STATUS */ +/*****************************************************************************/ +/* ISP Chromatic Aberration Correction Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_cac_ctrl: Control register for chromatic aberration + * correction (0x00000000) + * + *****************************************************************************/ +/* Slice: h_clip_mode:*/ +/* Defines the maximum red/blue pixel shift in horizontal direction at pixel */ +/* positions, that require a larger displacement, the maximum shift value is */ +/* used instead (vector clipping)*/ + /**/ +/* 0: Set horizontal vector clipping to +/-4 pixel displacement (Default)*/ +/* 1: Set horizontal vector clipping to +/-4 or +/-5 pixel displacement */ +/* depending on pixel position inside the Bayer raster (dynamic switching */ +/* between +/-4 and +/-5)*/ +#ifdef MRV_CAC_H_CLIP_MODE +#define MRV_CAC_H_CLIP_MODE_FIX4 0 /* 0: Set horizontal vector clipping */ + /* to +/-4 pixel displacement (Default) */ +#define MRV_CAC_H_CLIP_MODE_DYN5 1 /* 1: Set horizontal vector clipping */ + /* to +/-4 or +/-5 pixel displacement depending on */ + /* pixel position inside the Bayer raster */ + /* (dynamic switching between +/-4 and +/-5) */ +#endif /* MRV_CAC_H_CLIP_MODE */ +/* Slice: v_clip_mode:*/ +/* Defines the maximum red/blue pixel shift in vertical direction */ +/* 00: Set vertical vector clipping to +/-2 pixel ; fix filter_enable (Default)*/ +/* 01: Set vertical vector clipping to +/-3 pixel; dynamic filter_enable for */ +/* chroma low pass filter */ +/* 10: Set vertical vector clipping +/-3 or +/-4 pixel displacement depending */ +/* on pixel position inside the Bayer raster (dynamic switching between +/-3 and +/-4)*/ +/* 11: reserved */ +#ifdef MRV_CAC_V_CLIP_MODE +#define MRV_CAC_V_CLIP_MODE_FIX2 0 /* 00: Set vertical vector clipping to +/-2 pixel; */ + /* fix filter_enable (Default) */ +#define MRV_CAC_V_CLIP_MODE_FIX3 1 /* 01: Set vertical vector clipping to +/-3 pixel; */ + /* dynamic filter_enable for chroma low pass filter */ +#define MRV_CAC_V_CLIP_MODE_DYN4 2 /* 10: Set vertical vector clipping +/-3 or +/-4 pixel */ + /* displacement depending on pixel position inside */ + /* the Bayer raster (dynamic switching between +/-3 and +/-4) */ +#endif /* MRV_CAC_V_CLIP_MODE */ +/* Slice: cac_en:*/ +/* 0: chromatic aberration correction off */ +/* 1: chromatic aberration correction on */ +#ifdef MRV_CAC_CAC_EN +#define MRV_CAC_CAC_EN_PROCESS 1 +#define MRV_CAC_CAC_EN_BYPASS 0 +#endif /* MRV_CAC_CAC_EN */ +/*****************************************************************************/ +/** + * register: isp_cac_count_start: Preload values for CAC pixel and line + * counter (0x00000004) + * + *****************************************************************************/ +/* Slice: v_count_start:*/ +/* 12 bit v_count preload value (range 4095 ... 1) of the vertical CAC line */ +/* counter. Before frame start v_count has to be preloaded with */ +/* (v_size/2 + v_center_offset), with v_size the image height and v_center_offset */ +/* the vertical distance between image center and optical center.*/ + /**/ +/* After frame start the v_count decrements with every line until a value of zero */ +/* is reached for the line in the optical center. Than the v_sign bit toggles and */ +/* the v_counter decrements with every line until end of frame.*/ +#ifdef MRV_CAC_V_COUNT_START +#define MRV_CAC_V_COUNT_START_MIN 1 +#define MRV_CAC_V_COUNT_START_MAX (MRV_CAC_V_COUNT_START_MASK >> MRV_CAC_V_COUNT_START_SHIFT) +#endif /* MRV_CAC_V_COUNT_START */ +/* Slice: h_count_start:*/ +/* 12 bit h_count preload value (range 4095 .. 1) of the horizontal CAC pixel */ +/* counter. Before line start h_count has to be preloaded with (h_size/2 + h_center_offset),*/ +/* with h_size the image width and h_center_offset the horizontal distance between image */ +/* center and optical center.*/ + /**/ +/* After line start the h_count decrements with every pixel until a value of zero is */ +/* reached for the column in the optical center. Than the h_sign bit toggles and the */ +/* h_counter increments with every pixel until end of line.*/ +#ifdef MRV_CAC_H_COUNT_START +#define MRV_CAC_H_COUNT_START_MIN 1 +#define MRV_CAC_H_COUNT_START_MAX (MRV_CAC_H_COUNT_START_MASK >> MRV_CAC_H_COUNT_START_SHIFT) +#endif /* MRV_CAC_H_COUNT_START */ +/*****************************************************************************/ +/** + * register: isp_cac_a: Linear Parameters for radial shift calculation (0x00000008) + * + *****************************************************************************/ +/* Slice: A_Blue:*/ +/* Parameter A_Blue for radial blue shift calculation, according to */ +/* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_A_BLUE +#define MRV_CAC_A_BLUE_MAX (MRV_CAC_A_BLUE_MASK >> (MRV_CAC_A_BLUE_SHIFT)) +#define MRV_CAC_A_BLUE_MIN 0 +#endif /* MRV_CAC_A_BLUE */ +/* Slice: A_Red:*/ +/* Parameter A_Red for radial red shift calculation, according to */ +/* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_A_RED +#define MRV_CAC_A_RED_MAX (MRV_CAC_A_RED_MASK >> (MRV_CAC_A_RED_SHIFT)) +#define MRV_CAC_A_RED_MIN 0 +#endif /* MRV_CAC_A_RED */ +/*****************************************************************************/ +/** + * register: isp_cac_b: Square Parameters for radial shift calculation (0x0000000c) + * + *****************************************************************************/ +/* Slice: B_Blue:*/ +/* Parameter B_Blue for radial blue shift calculation, according to */ +/* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_B_BLUE +#define MRV_CAC_B_BLUE_MAX (MRV_CAC_B_BLUE_MASK >> (MRV_CAC_B_BLUE_SHIFT)) +#define MRV_CAC_B_BLUE_MIN 0 +#endif /* MRV_CAC_B_BLUE */ +/* Slice: B_Red:*/ +/* Parameter B_Red for radial red shift calculation, according to */ +/* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_B_RED +#define MRV_CAC_B_RED_MAX (MRV_CAC_B_RED_MASK >> (MRV_CAC_B_RED_SHIFT)) +#define MRV_CAC_B_RED_MIN 0 +#endif /* MRV_CAC_B_RED */ +/*****************************************************************************/ +/** + * register: isp_cac_c: Cubical Parameters for radial shift calculation (0x00000010) + * + *****************************************************************************/ +/* Slice: C_Blue:*/ +/* Parameter C_Blue for radial blue shift calculation, according to */ +/* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_C_BLUE +#define MRV_CAC_C_BLUE_MAX (MRV_CAC_C_BLUE_MASK >> (MRV_CAC_C_BLUE_SHIFT)) +#define MRV_CAC_C_BLUE_MIN 0 +#endif /* MRV_CAC_C_BLUE */ +/* Slice: C_Red:*/ +/* Parameter C_Red for radial red shift calculation, according to */ +/* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and */ +/* value range from -16 up to 15.9375.*/ +#ifdef MRV_CAC_C_RED +#define MRV_CAC_C_RED_MAX (MRV_CAC_C_RED_MASK >> (MRV_CAC_C_RED_SHIFT)) +#define MRV_CAC_C_RED_MIN 0 +#endif /* MRV_CAC_C_RED */ +/*****************************************************************************/ +/** + * register: isp_cac_x_norm: Normalization parameters for calculation of image + * coordinate x_d relative to optical center (0x00000014) + * + *****************************************************************************/ +/* Slice: x_ns:*/ +/* Horizontal normalization shift parameter x_ns (4 bit unsigned integer)*/ +/* in equation x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */ +#ifdef MRV_CAC_X_NS +#define MRV_CAC_X_NS_MIN 0 +#define MRV_CAC_X_NS_MAX (MRV_CAC_X_NS_MASK >> MRV_CAC_X_NS_SHIFT) +#endif /* MRV_CAC_X_NS */ +/* Slice: x_nf:*/ +/* Horizontal scaling or normalization factor x_nf (5 bit unsigned integer)*/ +/* range 0 .. 31 in equation x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */ +#ifdef MRV_CAC_X_NF +#define MRV_CAC_X_NF_MIN 0 +#define MRV_CAC_X_NF_MAX 31 +#endif /* MRV_CAC_X_NF */ +/*****************************************************************************/ +/** + * register: isp_cac_y_norm: Normalization parameters for calculation of image + * coordinate y_d relative to optical center (0x00000018) + * + *****************************************************************************/ +/* Slice: y_ns:*/ +/* Vertical normalization shift parameter y_ns (4 bit unsigned integer)*/ +/* in equation y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */ +#ifdef MRV_CAC_Y_NS +#define MRV_CAC_Y_NS_MIN 0 +#define MRV_CAC_Y_NS_MAX (MRV_CAC_Y_NS_MASK >> MRV_CAC_Y_NS_SHIFT) +#endif /* MRV_CAC_Y_NS */ +/* Slice: y_nf:*/ +/* Vertical scaling or normalization factor y_nf (5 bit unsigned integer)*/ +/* range 0 .. 31 in equation y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */ +#ifdef MRV_CAC_Y_NF +#define MRV_CAC_Y_NF_MIN 0 +#define MRV_CAC_Y_NF_MAX 31 +#endif /* MRV_CAC_Y_NF */ +/*****************************************************************************/ +/* ISP Exposure Measurement Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_exp_ctrl: Exposure control (0x00000000) + * + *****************************************************************************/ +/* Slice: exp_meas_mode:*/ +/* '1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256)*/ +/* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */ +#ifdef MRV_AE_EXP_MEAS_MODE +#define MRV_AE_EXP_MEAS_MODE_1 1 /* '1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256) */ +#define MRV_AE_EXP_MEAS_MODE_0 0 /* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */ +#endif /* MRV_AE_EXP_MEAS_MODE */ +/* Slice: autostop:*/ +/* '1' stop measuring after a complete frame */ +/* '0' continous measurement */ +#ifdef MRV_AE_AUTOSTOP +#define MRV_AE_AUTOSTOP_STOP_MEASURING 1 /* stop measuring after a complete frame */ +#define MRV_AE_AUTOSTOP_CONTINOUS_MEASURING 0 /* don't stop measurement, continoue with next frame */ +#endif /* MRV_AE_AUTOSTOP */ +/* Slice: exp_start:*/ +/* '1' start measuring a frame. The exp block will reset this bit and halt */ +/* after completing one frame, if bit "autostop" is set to '1'.*/ +#ifdef MRV_AE_EXP_START +#define MRV_AE_EXP_START_PROCESS 1 /* 1: processing is activated */ +#define MRV_AE_EXP_START_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */ +#endif /* MRV_AE_EXP_START */ +/*****************************************************************************/ +/** + * register: isp_exp_h_offset: Horizontal offset for first block (0x00000004) + * + *****************************************************************************/ +/* Slice: isp_exp_h_offset:*/ +/* Horizontal offset of first block in pixels.*/ +/* 0 <= value <= 3920 */ +#ifdef MRV_AE_ISP_EXP_H_OFFSET +#define MRV_AE_ISP_EXP_H_OFFSET_MIN 0x00000000 +#define MRV_AE_ISP_EXP_H_OFFSET_MAX 0x00000F50 /* 4096-176 */ +#endif /* MRV_AE_ISP_EXP_H_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_exp_v_offset: Vertical offset for first block (0x00000008) + * + *****************************************************************************/ +/* Slice: isp_exp_v_offset:*/ +/* Vertical offset of first block in pixels.*/ +/* 0 <= value <= 1806 */ +#ifdef MRV_AE_ISP_EXP_V_OFFSET +#define MRV_AE_ISP_EXP_V_OFFSET_MIN 0x00000000 +#define MRV_AE_ISP_EXP_V_OFFSET_MAX 0x00000B74 /* 3072-140 */ +#endif /* MRV_AE_ISP_EXP_V_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_exp_h_size: Horizontal size of one block (0x0000000c) + * + *****************************************************************************/ +/* Slice: isp_exp_h_size:*/ +/* Horizontal size in pixels of one block.*/ +/* 35 <= value <= 516 */ +#ifdef MRV_AE_ISP_EXP_H_SIZE +#define MRV_AE_ISP_EXP_H_SIZE_MIN 0x00000023 +#define MRV_AE_ISP_EXP_H_SIZE_MAX 0x00000333 +#endif /* MRV_AE_ISP_EXP_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_exp_v_size: Vertical size of one block (0x00000010) + * + *****************************************************************************/ +/* Slice: isp_exp_v_size:*/ +/* Vertical size in pixels of one block.*/ +/* 28 <= value <= 390 */ +#ifdef MRV_AE_ISP_EXP_V_SIZE +#define MRV_AE_ISP_EXP_V_SIZE_VALID_MASK (MRV_AE_ISP_EXP_V_SIZE_MASK & ~0x00000001) +#define MRV_AE_ISP_EXP_V_SIZE_MIN 0x0000001C +#define MRV_AE_ISP_EXP_V_SIZE_MAX 0x00000266 +#endif /* MRV_AE_ISP_EXP_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_00: Mean luminance value of block 00 (0x00000014) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_00:*/ +/* Mean luminance value of block 00 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_00 +#endif /* MRV_AE_ISP_EXP_MEAN_00 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_10: Mean luminance value of block 10 (0x00000018) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_10:*/ +/* Mean luminance value of block 10 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_10 +#endif /* MRV_AE_ISP_EXP_MEAN_10 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_20: Mean luminance value of block 20 (0x0000001c) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_20:*/ +/* Mean luminance value of block 20 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_20 +#endif /* MRV_AE_ISP_EXP_MEAN_20 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_30: Mean luminance value of block 30 (0x00000020) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_30:*/ +/* Mean luminance value of block 30 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_30 +#endif /* MRV_AE_ISP_EXP_MEAN_30 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_40: Mean luminance value of block 40 (0x00000024) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_40:*/ +/* Mean luminance value of block 40 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_40 +#endif /* MRV_AE_ISP_EXP_MEAN_40 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_01: Mean luminance value of block 01 (0x00000028) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_01:*/ +/* Mean luminance value of block 01 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_01 +#endif /* MRV_AE_ISP_EXP_MEAN_01 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c) + * + *****************************************************************************/ +/* Register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c)*/ +/* Slice: isp_exp_mean_11:*/ +/* Mean luminance value of block 11 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_11 +#endif /* MRV_AE_ISP_EXP_MEAN_11 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_21: Mean luminance value of block 21 (0x00000030) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_21:*/ +/* Mean luminance value of block 21 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_21 +#endif /* MRV_AE_ISP_EXP_MEAN_21 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_31: Mean luminance value of block 31 (0x00000034) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_31:*/ +/* Mean luminance value of block 31 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_31 +#endif /* MRV_AE_ISP_EXP_MEAN_31 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_41: Mean luminance value of block 41 (0x00000038) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_41:*/ +/* Mean luminance value of block 41 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_41 +#endif /* MRV_AE_ISP_EXP_MEAN_41 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_02: Mean luminance value of block 02 (0x0000003c) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_02:*/ +/* Mean luminance value of block 02 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_02 +#endif /* MRV_AE_ISP_EXP_MEAN_02 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_12: Mean luminance value of block 12 (0x00000040) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_12:*/ +/* Mean luminance value of block 12 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_12 +#endif /* MRV_AE_ISP_EXP_MEAN_12 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_22: Mean luminance value of block 22 (0x00000044) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_22:*/ +/* Mean luminance value of block 22 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_22 +#endif /* MRV_AE_ISP_EXP_MEAN_22 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_32: Mean luminance value of block 32 (0x00000048) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_32:*/ +/* Mean luminance value of block 32 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_32 +#endif /* MRV_AE_ISP_EXP_MEAN_32 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_42: Mean luminance value of block 42 (0x0000004c) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_42:*/ +/* Mean luminance value of block 42 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_42 +#endif /* MRV_AE_ISP_EXP_MEAN_42 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_03: Mean luminance value of block 03 (0x00000050) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_03:*/ +/* Mean luminance value of block 03 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_03 +#endif /* MRV_AE_ISP_EXP_MEAN_03 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_13: Mean luminance value of block 13 (0x00000054) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_13:*/ +/* Mean luminance value of block 13 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_13 +#endif /* MRV_AE_ISP_EXP_MEAN_13 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_23: Mean luminance value of block 23 (0x00000058) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_23:*/ +/* Mean luminance value of block 23 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_23 +#endif /* MRV_AE_ISP_EXP_MEAN_23 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_33: Mean luminance value of block 33 (0x0000005c) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_33:*/ +/* Mean luminance value of block 33 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_33 +#endif /* MRV_AE_ISP_EXP_MEAN_33 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_43: Mean luminance value of block 43 (0x00000060) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_43:*/ +/* Mean luminance value of block 43 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_43 +#endif /* MRV_AE_ISP_EXP_MEAN_43 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_04: Mean luminance value of block 04 (0x00000064) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_04:*/ +/* Mean luminance value of block 04 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_04 +#endif /* MRV_AE_ISP_EXP_MEAN_04 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_14: Mean luminance value of block 14 (0x00000068) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_14:*/ +/* Mean luminance value of block 14 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_14 +#endif /* MRV_AE_ISP_EXP_MEAN_14 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_24: Mean luminance value of block 24 (0x0000006c) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_24:*/ +/* Mean luminance value of block 24 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_24 +#endif /* MRV_AE_ISP_EXP_MEAN_24 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_34: Mean luminance value of block 34 (0x00000070) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_34:*/ +/* Mean luminance value of block 34 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_34 +#endif /* MRV_AE_ISP_EXP_MEAN_34 */ +/*****************************************************************************/ +/** + * register: isp_exp_mean_44: Mean luminance value of block 44 (0x00000074) + * + *****************************************************************************/ +/* Slice: isp_exp_mean_44:*/ +/* Mean luminance value of block 44 (x,y)*/ +#ifdef MRV_AE_ISP_EXP_MEAN_44 +#endif /* MRV_AE_ISP_EXP_MEAN_44 */ +/*****************************************************************************/ +/* ISP Black Level Subtraction Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_bls_ctrl: global control register (0x00000000) + * + *****************************************************************************/ +/* Slice: WINDOW_ENABLE:*/ +/* 0: no measuring is performed */ +/* 1: only window 1 is measured */ +/* 2: only window 2 is measured */ +/* 3: both windows are measured */ +#ifdef MRV_BLS_WINDOW_ENABLE +#define MRV_BLS_WINDOW_ENABLE_NONE 0U /* 0: no measuring is performed */ +#define MRV_BLS_WINDOW_ENABLE_WND1 1U /* 1: only window 1 is measured */ +#define MRV_BLS_WINDOW_ENABLE_WND2 2U /* 2: only window 2 is measured */ +#define MRV_BLS_WINDOW_ENABLE_BOTH 3U /* 3: both windows are measured */ +#define MRV_BLS_WINDOW_ENABLE_WND1_MASK 0x00000004U +#define MRV_BLS_WINDOW_ENABLE_WND1_SHIFT 2U +#define MRV_BLS_WINDOW_ENABLE_WND2_MASK 0x00000008U +#define MRV_BLS_WINDOW_ENABLE_WND2_SHIFT 3U +#endif /* MRV_BLS_WINDOW_ENABLE */ +/* Slice: BLS_MODE:*/ +/* 1: subtract measured values */ +/* 0: subtract fixed values */ +#ifdef MRV_BLS_BLS_MODE +#define MRV_BLS_BLS_MODE_MEAS 1U /* 1: subtract measured values */ +#define MRV_BLS_BLS_MODE_FIX 0U /* 0: subtract fixed values */ +#endif /* MRV_BLS_BLS_MODE */ +/* Slice: BLS_ENABLE:*/ +/* 1: black level subtraction is enabled */ +/* 0: bypass the black level processing */ +#ifdef MRV_BLS_BLS_ENABLE +#define MRV_BLS_BLS_ENABLE_PROCESS 1U /* 1: black level subtraction is enabled */ +#define MRV_BLS_BLS_ENABLE_BYPASS 0U /* 0: bypass the black level processing */ +#endif /* MRV_BLS_BLS_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_bls_samples: samples register (0x00000004) + * + *****************************************************************************/ +/* Slice: BLS_SAMPLES:*/ +/* This number to the power of two gives the number of measure samples for */ +/* each Bayer position. Range 0x00: 2^0=1 to 0x12: 2^18=262144. This number */ +/* is also the divider for the accumulator for each Bayer position.*/ + /**/ +/* The accumulation will be stopped, if the number of measured pixels for the */ +/* current Bayer position is equal to the number of samples.*/ + /**/ +/* The measure windows must be positioned that way that the number of included */ +/* pixels of each Bayer position included by both windows is equal or greater */ +/* than the number of measure samples calculated by 2^BLS_SAMPLES !*/ + /**/ +/* NOTE:*/ +/* - The number of pixels of one Bayer position is 1/4 of the number of all */ +/* Pixels included by the measure windows.*/ +#ifdef MRV_BLS_BLS_SAMPLES +#define MRV_BLS_BLS_SAMPLES_MAX (0x00000014U) /* maximum is 2^20 = 1048576 */ +#endif /* MRV_BLS_BLS_SAMPLES */ +/*****************************************************************************/ +/** + * register: isp_bls_h1_start: window 1 horizontal start (0x00000008) + * + *****************************************************************************/ +/* Slice: BLS_H1_START:*/ +/* Black pixel window 1 horizontal start position */ +#ifdef MRV_BLS_BLS_H1_START +#define MRV_BLS_BLS_H1_START_MAX (MRV_BLS_BLS_H1_START_MASK >> MRV_BLS_BLS_H1_START_SHIFT) +#endif /* MRV_BLS_BLS_H1_START */ +/*****************************************************************************/ +/** + * register: isp_bls_h1_stop: window 1 horizontal stop (0x0000000c) + * + *****************************************************************************/ +/* Slice: BLS_H1_STOP:*/ +/* Black pixel window 1 horizontal stop position */ +#ifdef MRV_BLS_BLS_H1_STOP +#define MRV_BLS_BLS_H1_STOP_MAX (MRV_BLS_BLS_H1_STOP_MASK >> MRV_BLS_BLS_H1_STOP_SHIFT) +#endif /* MRV_BLS_BLS_H1_STOP */ +/*****************************************************************************/ +/** + * register: isp_bls_v1_start: window 1 vertical start (0x00000010) + * + *****************************************************************************/ +/* Slice: BLS_V1_START:*/ +/* Black pixel window 1 vertical start position */ +#ifdef MRV_BLS_BLS_V1_START +#define MRV_BLS_BLS_V1_START_MAX (MRV_BLS_BLS_V1_START_MASK >> MRV_BLS_BLS_V1_START_SHIFT) +#endif /* MRV_BLS_BLS_V1_START */ +/*****************************************************************************/ +/** + * register: isp_bls_v1_stop: window 1 vertical stop (0x00000014) + * + *****************************************************************************/ +/* Slice: BLS_V1_STOP:*/ +/* Black pixel window 1 vertical stop position */ +#ifdef MRV_BLS_BLS_V1_STOP +#define MRV_BLS_BLS_V1_STOP_MAX (MRV_BLS_BLS_V1_STOP_MASK >> MRV_BLS_BLS_V1_STOP_SHIFT) +#endif /* MRV_BLS_BLS_V1_STOP */ +/*****************************************************************************/ +/** + * register: isp_bls_h2_start: window 2 horizontal start (0x00000018) + * + *****************************************************************************/ +/* Slice: BLS_H2_START:*/ +/* Black pixel window 2 horizontal start position */ +#ifdef MRV_BLS_BLS_H2_START +#define MRV_BLS_BLS_H2_START_MAX (MRV_BLS_BLS_H2_START_MASK >> MRV_BLS_BLS_H2_START_SHIFT) +#endif /* MRV_BLS_BLS_H2_START */ +/*****************************************************************************/ +/** + * register: isp_bls_h2_stop: window 2 horizontal stop (0x0000001c) + * + *****************************************************************************/ +/* Slice: BLS_H2_STOP:*/ +/* Black pixel window 2 horizontal stop position */ +#ifdef MRV_BLS_BLS_H2_STOP +#define MRV_BLS_BLS_H2_STOP_MAX (MRV_BLS_BLS_H2_STOP_MASK >> MRV_BLS_BLS_H2_STOP_SHIFT) +#endif /* MRV_BLS_BLS_H2_STOP */ +/*****************************************************************************/ +/** + * register: isp_bls_v2_start: window 2 vertical start (0x00000020) + * + *****************************************************************************/ +/* Slice: BLS_V2_START:*/ +/* Black pixel window 2 vertical start position */ +#ifdef MRV_BLS_BLS_V2_START +#define MRV_BLS_BLS_V2_START_MAX (MRV_BLS_BLS_V2_START_MASK >> MRV_BLS_BLS_V2_START_SHIFT) +#endif /* MRV_BLS_BLS_V2_START */ +/*****************************************************************************/ +/** + * register: isp_bls_v2_stop: window 2 vertical stop (0x00000024) + * + *****************************************************************************/ +/* Slice: BLS_V2_STOP:*/ +/* Black pixel window 2 vertical stop position */ +#ifdef MRV_BLS_BLS_V2_STOP +#define MRV_BLS_BLS_V2_STOP_MAX (MRV_BLS_BLS_V2_STOP_MASK >> MRV_BLS_BLS_V2_STOP_SHIFT) +#endif /* MRV_BLS_BLS_V2_STOP */ +/*****************************************************************************/ +/** + * register: isp_bls_a_fixed: fixed black level A (0x00000028) + * + *****************************************************************************/ +/* Slice: BLS_A_FIXED:*/ +/* Fixed black level for A pixels – signed */ +/* two's complement, value range from -4096 to +4095,*/ +/* a positive value will be subtracted from the pixel values */ +#ifdef MRV_BLS_BLS_A_FIXED +#endif /* MRV_BLS_BLS_A_FIXED */ +/*****************************************************************************/ +/** + * register: isp_bls_b_fixed: fixed black level B (0x0000002c) + * + *****************************************************************************/ +/* Slice: BLS_B_FIXED:*/ +/* Fixed black level for B pixels – signed */ +/* two's complement, value range from -4096 to +4095 */ +#ifdef MRV_BLS_BLS_B_FIXED +#endif /* MRV_BLS_BLS_B_FIXED */ +/*****************************************************************************/ +/** + * register: isp_bls_c_fixed: fixed black level C (0x00000030) + * + *****************************************************************************/ +/* Slice: BLS_C_FIXED:*/ +/* Fixed black level for C pixels – signed */ +/* two's complement, value range from -4096 to +4095 */ +#ifdef MRV_BLS_BLS_C_FIXED +#endif /* MRV_BLS_BLS_C_FIXED */ +/*****************************************************************************/ +/** + * register: isp_bls_d_fixed: fixed black level D (0x00000034) + * + *****************************************************************************/ +/* Slice: BLS_D_FIXED:*/ +/* Fixed black level for D pixels - signed */ +/* two's complement, value range from -4096 to +4095 */ +#ifdef MRV_BLS_BLS_D_FIXED +#endif /* MRV_BLS_BLS_D_FIXED */ +/*****************************************************************************/ +/** + * register: isp_bls_a_measured: measured black level A (0x00000038) + * + *****************************************************************************/ +/* Slice: BLS_A_MEASURED:*/ +/* Measured black level for A pixels */ +#ifdef MRV_BLS_BLS_A_MEASURED +#endif /* MRV_BLS_BLS_A_MEASURED */ +/*****************************************************************************/ +/** + * register: isp_bls_b_measured: measured black level B (0x0000003c) + * + *****************************************************************************/ +/* Slice: BLS_B_MEASURED:*/ +/* Measured black level for B pixels */ +#ifdef MRV_BLS_BLS_B_MEASURED +#endif /* MRV_BLS_BLS_B_MEASURED */ +/*****************************************************************************/ +/** + * register: isp_bls_c_measured: measured black level C (0x00000040) + * + *****************************************************************************/ +/* Slice: BLS_C_MEASURED:*/ +/* Measured black level for C pixels */ +#ifdef MRV_BLS_BLS_C_MEASURED +#endif /* MRV_BLS_BLS_C_MEASURED */ +/*****************************************************************************/ +/** + * register: isp_bls_d_measured: measured black level D (0x00000044) + * + *****************************************************************************/ +/* Slice: BLS_D_MEASURED:*/ +/* Measured black level for D pixels */ +#ifdef MRV_BLS_BLS_D_MEASURED +#endif /* MRV_BLS_BLS_D_MEASURED */ +/*****************************************************************************/ +/* ISP Denoising Pre-Filter Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_dpf_mode: Mode control for Denoising Pre-Filter block + * (0x00000000) + * + *****************************************************************************/ +/* Slice: USE_NF_GAIN:*/ +/* 1: dpf_nf_gain's will be used */ +/* 0: external AWB gains will be used *Default**/ +#ifdef MRV_DPF_USE_NF_GAIN +#endif /* MRV_DPF_USE_NF_GAIN */ +/* Slice: LSC_GAIN_COMP:*/ +/* 1: LSC gain will be processed */ +/* 0: LSC gain will not be processed *Default**/ +#ifdef MRV_DPF_LSC_GAIN_COMP +#endif /* MRV_DPF_LSC_GAIN_COMP */ +/* Slice: AWB_GAIN_COMP:*/ +/* 1: AWB gain or internal dpf_nf_gain will be processed */ +/* 0: AWB gain or internal dpf_nf_gain will not be processed *Default**/ +#ifdef MRV_DPF_AWB_GAIN_COMP +#endif /* MRV_DPF_AWB_GAIN_COMP */ +/* Slice: NLL_SEGMENTATION:*/ +/* 1: optimized logarithmic like segmentation for Noise Level Lookup (NLL)*/ +/* 0: equidistant segmentation for NLL *Default**/ +#ifdef MRV_DPF_NLL_SEGMENTATION +#endif /* MRV_DPF_NLL_SEGMENTATION */ +/* Slice: RB_FILTER_SIZE:*/ +/* 1: Red and Blue filter kernel size of 9x9 (5x5 active) pixels */ +/* 0: Wide Red and Blue filter kernel size of 13x9 (7x5 active) pixels *Default**/ +#ifdef MRV_DPF_RB_FILTER_SIZE +#endif /* MRV_DPF_RB_FILTER_SIZE */ +/* Slice: R_FILTER_OFF:*/ +/* 1: disable filter processing for red pixels (R)*/ +/* 0: filter R pixels *Default**/ +#ifdef MRV_DPF_R_FILTER_OFF +#endif /* MRV_DPF_R_FILTER_OFF */ +/* Slice: GR_FILTER_OFF:*/ +/* 1: disable filter processing for green pixels in green/red lines (GR)*/ +/* 0: filter GR pixels *Default**/ +#ifdef MRV_DPF_GR_FILTER_OFF +#endif /* MRV_DPF_GR_FILTER_OFF */ +/* Slice: GB_FILTER_OFF:*/ +/* 1: disable filter processing for green pixels in green/blue lines (GB)*/ +/* 0: filter GB pixels *Default**/ +#ifdef MRV_DPF_GB_FILTER_OFF +#endif /* MRV_DPF_GB_FILTER_OFF */ +/* Slice: B_FILTER_OFF:*/ +/* 1: disable filter processing for blue pixels (B)*/ +/* 0: filter B pixels *Default**/ +#ifdef MRV_DPF_B_FILTER_OFF +#endif /* MRV_DPF_B_FILTER_OFF */ +/* Slice: DPF_ENABLE:*/ +/* 1: enable dpf */ +/* 0: bypass dpf *Default**/ +#ifdef MRV_DPF_DPF_ENABLE +#endif /* MRV_DPF_DPF_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_dpf_strength_r: filter strength of the RED filter (0x00000004) + * + *****************************************************************************/ +/* Slice: INV_WEIGHT_R:*/ +/* Filter strength of the filter is determined by weight. Default is a */ +/* weight of 1. A higher weight increases the filter strength. In this */ +/* register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#ifdef MRV_DPF_INV_WEIGHT_R +#endif /* MRV_DPF_INV_WEIGHT_R */ +/*****************************************************************************/ +/** + * register: isp_dpf_strength_g: filter strength of the GREEN filter (0x00000008) + * + *****************************************************************************/ +/* Slice: INV_WEIGHT_G:*/ +/* Filter strength of the filter is determined by weight. Default is a */ +/* weight of 1. A higher weight increases the filter strength. In this */ +/* register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#ifdef MRV_DPF_INV_WEIGHT_G +#endif /* MRV_DPF_INV_WEIGHT_G */ +/*****************************************************************************/ +/** + * register: isp_dpf_strength_b: filter strength of the BLUE filter (0x0000000c) + * + *****************************************************************************/ +/* Slice: INV_WEIGHT_B:*/ +/* Filter strength of the filter is determined by weight. Default is a */ +/* weight of 1. A higher weight increases the filter strength. In this */ +/* register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#ifdef MRV_DPF_INV_WEIGHT_B +#endif /* MRV_DPF_INV_WEIGHT_B */ +/*****************************************************************************/ +/** + * register: isp_dpf_s_weight_g_1_4: Spatial Weights green channel 1 2 3 4 + * (0x00000010) + * + *****************************************************************************/ +/* Slice: S_WEIGHT_G4:*/ +/* Filter Coefficient green channel S_WEIGHT_G4 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G4 +#endif /* MRV_DPF_S_WEIGHT_G4 */ +/* Slice: S_WEIGHT_G3:*/ +/* Filter Coefficient green channel S_WEIGHT_G3 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G3 +#endif /* MRV_DPF_S_WEIGHT_G3 */ +/* Slice: S_WEIGHT_G2:*/ +/* Filter Coefficient green channel S_WEIGHT_G2 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G2 +#endif /* MRV_DPF_S_WEIGHT_G2 */ +/* Slice: S_WEIGHT_G1:*/ +/* Filter Coefficient green channel S_WEIGHT_G1 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G1 +#endif /* MRV_DPF_S_WEIGHT_G1 */ +/*****************************************************************************/ +/** + * register: isp_dpf_s_weight_g_5_6: Spatial Weights green channel 5 6 + * (0x00000014) + * + *****************************************************************************/ +/* Slice: S_WEIGHT_G6:*/ +/* Filter Coefficient green channel S_WEIGHT_G6 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G6 +#endif /* MRV_DPF_S_WEIGHT_G6 */ +/* Slice: S_WEIGHT_G5:*/ +/* Filter Coefficient green channel S_WEIGHT_G5 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_G5 +#endif /* MRV_DPF_S_WEIGHT_G5 */ +/*****************************************************************************/ +/** + * register: isp_dpf_s_weight_rb_1_4: Spatial Weights red/blue channels 1 2 3 4 + * (0x00000018) + * + *****************************************************************************/ +/* Slice: S_WEIGHT_RB4:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB4 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB4 +#endif /* MRV_DPF_S_WEIGHT_RB4 */ +/* Slice: S_WEIGHT_RB3:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB3 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB3 +#endif /* MRV_DPF_S_WEIGHT_RB3 */ +/* Slice: S_WEIGHT_RB2:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB2 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB2 +#endif /* MRV_DPF_S_WEIGHT_RB2 */ +/* Slice: S_WEIGHT_RB1:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB1 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB1 +#endif /* MRV_DPF_S_WEIGHT_RB1 */ +/*****************************************************************************/ +/** + * register: isp_dpf_s_weight_rb_5_6: Spatial Weights red/blue channels 5 6 + * (0x0000001c) + * + *****************************************************************************/ +/* Slice: S_WEIGHT_RB6:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB6 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB6 +#endif /* MRV_DPF_S_WEIGHT_RB6 */ +/* Slice: S_WEIGHT_RB5:*/ +/* Filter Coefficient red/blue channels S_WEIGHT_RB5 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#ifdef MRV_DPF_S_WEIGHT_RB5 +#endif /* MRV_DPF_S_WEIGHT_RB5 */ +/*****************************************************************************/ +/** + * register array: isp_dpf_nll_coeff: Noise Level Lookup Coefficient + * (0x0040 + n*0x4 (n=0..16)) + * + *****************************************************************************/ +/* Slice: nll_coeff_n:*/ +/* Noise Level Lookup Table Coefficient nll_coeff_n */ +/* 10 bit unsigned, value range 1/1024 to 1023/1024 (*Default*)*/ +#ifdef MRV_DPF_NLL_COEFF_N +#endif /* MRV_DPF_NLL_COEFF_N */ +/*****************************************************************************/ +/** + * register: isp_dpf_nf_gain_r: noise function gain for red pixels (0x00000064) + * + *****************************************************************************/ +/* Slice: DPF_NF_GAIN_R:*/ +/* Noise Function (NF) Gain that replaces the AWB gain for red pixels.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#ifdef MRV_DPF_DPF_NF_GAIN_R +#endif /* MRV_DPF_DPF_NF_GAIN_R */ +/*****************************************************************************/ +/** + * register: isp_dpf_nf_gain_gr: noise function gain for green in red pixels + * (0x00000068) + * + *****************************************************************************/ +/* Slice: DPF_NF_GAIN_GR:*/ +/* Noise Function (NF) Gain that replaces the AWB gain for green pixels in a */ +/* red line.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#ifdef MRV_DPF_DPF_NF_GAIN_GR +#endif /* MRV_DPF_DPF_NF_GAIN_GR */ +/*****************************************************************************/ +/** + * register: isp_dpf_nf_gain_gb: noise function gain for green in blue pixels + * (0x0000006c) + * + *****************************************************************************/ +/* Slice: DPF_NF_GAIN_GB:*/ +/* Noise Function (NF) Gain that replaces the AWB gain for green pixels in a */ +/* blue line.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#ifdef MRV_DPF_DPF_NF_GAIN_GB +#endif /* MRV_DPF_DPF_NF_GAIN_GB */ +/*****************************************************************************/ +/** + * register: isp_dpf_nf_gain_b: noise function gain for blue pixels (0x00000070) + * + *****************************************************************************/ +/* Slice: DPF_NF_GAIN_B:*/ +/* Noise Function (NF) Gain that replaces the AWB gain for blue pixels.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#ifdef MRV_DPF_DPF_NF_GAIN_B +#endif /* MRV_DPF_DPF_NF_GAIN_B */ +/*****************************************************************************/ +/* ISP Defect Pixel Cluster Correction Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_dpcc_mode: mode control for DPCC block (0x0000) + * + *****************************************************************************/ +/* Slice: STAGE1_ENABLE:*/ +/* 1: enable stage1 *Default**/ +/* 0: bypass stage1 */ +#ifdef MRV_DPCC_STAGE1_ENABLE +#endif /* MRV_DPCC_STAGE1_ENABLE */ +/* Slice: GRAYSCALE_MODE:*/ +/* 1: enable gray scale data input from black and white sensors (without color filter array)*/ +/* 0: BAYER DATA INPUT *Default**/ +#ifdef MRV_DPCC_GRAYSCALE_MODE +#endif /* MRV_DPCC_GRAYSCALE_MODE */ +/* Slice: ISP_DPCC_enable:*/ +/* 1: enable DPCC */ +/* 0: bypass DPCC *Default**/ +#ifdef MRV_DPCC_ISP_DPCC_ENABLE +#endif /* MRV_DPCC_ISP_DPCC_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_dpcc_output_mode: interpolation mode for correction unit + * (0x00000004) + * + *****************************************************************************/ +/* Slice: STAGE1_RB_3x3:*/ +/* 1: stage1 red/blue 9 pixel (3x3) output median */ +/* 0: stage1 red/blue 4 or 5 pixel output median *Default**/ +#ifdef MRV_DPCC_STAGE1_RB_3X3 +#endif /* MRV_DPCC_STAGE1_RB_3X3 */ +/* Slice: STAGE1_G_3x3:*/ +/* 1: stage1 green 9 pixel (3x3) output median */ +/* 0: stage1 green 4 or 5 pixel output median *Default**/ +#ifdef MRV_DPCC_STAGE1_G_3X3 +#endif /* MRV_DPCC_STAGE1_G_3X3 */ +/* Slice: STAGE1_INCL_RB_CENTER:*/ +/* 1: stage1 include center pixel for red/blue output median 2x2+1 */ +/* *Default* 0: stage1 do not include center pixel for red/blue output median 2x2 */ +#ifdef MRV_DPCC_STAGE1_INCL_RB_CENTER +#endif /* MRV_DPCC_STAGE1_INCL_RB_CENTER */ +/* Slice: STAGE1_INCL_GREEN_CENTER:*/ +/* 1: stage1 include center pixel for green output median 2x2+1 *Default**/ +/* 0: stage1 do not include center pixel for green output median 2x2 */ +#ifdef MRV_DPCC_STAGE1_INCL_GREEN_CENTER +#endif /* MRV_DPCC_STAGE1_INCL_GREEN_CENTER */ +/*****************************************************************************/ +/** + * register: isp_dpcc_set_use: DPCC methods set usage for detection + * (0x00000008) + * + *****************************************************************************/ +/* Slice: STAGE1_USE_FIX_SET:*/ +/* 1: stage1 use hard coded methods set *Default**/ +/* 0: stage1 do not use hard coded methods set */ +#ifdef MRV_DPCC_STAGE1_USE_FIX_SET +#endif /* MRV_DPCC_STAGE1_USE_FIX_SET */ +/* Slice: STAGE1_USE_SET_3:*/ +/* 1: stage1 use methods set 3 */ +/* 0: stage1 do not use methods set 3 *Default**/ +#ifdef MRV_DPCC_STAGE1_USE_SET_3 +#endif /* MRV_DPCC_STAGE1_USE_SET_3 */ +/* Slice: STAGE1_USE_SET_2:*/ +/* 1: stage1 use methods set 2 */ +/* 0: stage1 do not use methods set 2 *Default**/ +#ifdef MRV_DPCC_STAGE1_USE_SET_2 +#endif /* MRV_DPCC_STAGE1_USE_SET_2 */ +/* Slice: STAGE1_USE_SET_1:*/ +/* 1: stage1 use methods set 1 *Default**/ +/* 0: stage1 do not use methods set 1 */ +#ifdef MRV_DPCC_STAGE1_USE_SET_1 +#endif /* MRV_DPCC_STAGE1_USE_SET_1 */ +/*****************************************************************************/ +/** + * register: isp_dpcc_methods_set_1: Methods enable bits for SET_1 + * (0x0000000c) + * + *****************************************************************************/ +/* Slice: RG_RED_BLUE1_ENABLE:*/ +/* 1: enable Rank Gradient check for red_blue *Default**/ +/* 0: bypass Rank Gradient check for red_blue */ +#ifdef MRV_DPCC_RG_RED_BLUE1_ENABLE +#endif /* MRV_DPCC_RG_RED_BLUE1_ENABLE */ +/* Slice: RND_RED_BLUE1_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for red_blue *Default**/ +/* 0: bypass Rank Neighbor Difference check for red_blue */ +#ifdef MRV_DPCC_RND_RED_BLUE1_ENABLE +#endif /* MRV_DPCC_RND_RED_BLUE1_ENABLE */ +/* Slice: RO_RED_BLUE1_ENABLE:*/ +/* 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#ifdef MRV_DPCC_RO_RED_BLUE1_ENABLE +#endif /* MRV_DPCC_RO_RED_BLUE1_ENABLE */ +/* Slice: LC_RED_BLUE1_ENABLE:*/ +/* 1: enable Line check for red_blue *Default**/ +/* 0: bypass Line check for red_blue */ +#ifdef MRV_DPCC_LC_RED_BLUE1_ENABLE +#endif /* MRV_DPCC_LC_RED_BLUE1_ENABLE */ +/* Slice: PG_RED_BLUE1_ENABLE:*/ +/* 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#ifdef MRV_DPCC_PG_RED_BLUE1_ENABLE +#endif /* MRV_DPCC_PG_RED_BLUE1_ENABLE */ +/* Slice: RG_GREEN1_ENABLE:*/ +/* 1: enable Rank Gradient check for green *Default**/ +/* 0: bypass Rank Gradient check for green */ +#ifdef MRV_DPCC_RG_GREEN1_ENABLE +#endif /* MRV_DPCC_RG_GREEN1_ENABLE */ +/* Slice: RND_GREEN1_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for green *Default**/ +/* 0: bypass Rank Neighbor Difference check for green */ +#ifdef MRV_DPCC_RND_GREEN1_ENABLE +#endif /* MRV_DPCC_RND_GREEN1_ENABLE */ +/* Slice: RO_GREEN1_ENABLE:*/ +/* 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#ifdef MRV_DPCC_RO_GREEN1_ENABLE +#endif /* MRV_DPCC_RO_GREEN1_ENABLE */ +/* Slice: LC_GREEN1_ENABLE:*/ +/* 1: enable Line check for green *Default**/ +/* 0: bypass Line check for green */ +#ifdef MRV_DPCC_LC_GREEN1_ENABLE +#endif /* MRV_DPCC_LC_GREEN1_ENABLE */ +/* Slice: PG_GREEN1_ENABLE:*/ +/* 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#ifdef MRV_DPCC_PG_GREEN1_ENABLE +#endif /* MRV_DPCC_PG_GREEN1_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_dpcc_methods_set_2: Methods enable bits for SET_2 + * (0x00000010) + * + *****************************************************************************/ +/* Slice: RG_RED_BLUE2_ENABLE:*/ +/* 1: enable Rank Gradient check for red_blue *Default**/ +/* 0: bypass Rank Gradient check for red_blue */ +#ifdef MRV_DPCC_RG_RED_BLUE2_ENABLE +#endif /* MRV_DPCC_RG_RED_BLUE2_ENABLE */ +/* Slice: RND_RED_BLUE2_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for red_blue *Default**/ +/* 0: bypass Rank Neighbor Difference check for red_blue */ +#ifdef MRV_DPCC_RND_RED_BLUE2_ENABLE +#endif /* MRV_DPCC_RND_RED_BLUE2_ENABLE */ +/* Slice: RO_RED_BLUE2_ENABLE:*/ +/* 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#ifdef MRV_DPCC_RO_RED_BLUE2_ENABLE +#endif /* MRV_DPCC_RO_RED_BLUE2_ENABLE */ +/* Slice: LC_RED_BLUE2_ENABLE:*/ +/* 1: enable Line check for red_blue *Default**/ +/* 0: bypass Line check for red_blue */ +#ifdef MRV_DPCC_LC_RED_BLUE2_ENABLE +#endif /* MRV_DPCC_LC_RED_BLUE2_ENABLE */ +/* Slice: PG_RED_BLUE2_ENABLE:*/ +/* 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#ifdef MRV_DPCC_PG_RED_BLUE2_ENABLE +#endif /* MRV_DPCC_PG_RED_BLUE2_ENABLE */ +/* Slice: RG_GREEN2_ENABLE:*/ +/* 1: enable Rank Gradient check for green *Default**/ +/* 0: bypass Rank Gradient check for green */ +#ifdef MRV_DPCC_RG_GREEN2_ENABLE +#endif /* MRV_DPCC_RG_GREEN2_ENABLE */ +/* Slice: RND_GREEN2_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for green *Default**/ +/* 0: bypass Rank Neighbor Difference check for green */ +#ifdef MRV_DPCC_RND_GREEN2_ENABLE +#endif /* MRV_DPCC_RND_GREEN2_ENABLE */ +/* Slice: RO_GREEN2_ENABLE:*/ +/* 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#ifdef MRV_DPCC_RO_GREEN2_ENABLE +#endif /* MRV_DPCC_RO_GREEN2_ENABLE */ +/* Slice: LC_GREEN2_ENABLE:*/ +/* 1: enable Line check for green *Default**/ +/* 0: bypass Line check for green */ +#ifdef MRV_DPCC_LC_GREEN2_ENABLE +#endif /* MRV_DPCC_LC_GREEN2_ENABLE */ +/* Slice: PG_GREEN2_ENABLE:*/ +/* 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#ifdef MRV_DPCC_PG_GREEN2_ENABLE +#endif /* MRV_DPCC_PG_GREEN2_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_dpcc_methods_set_3: Methods enable bits for SET_3 + * (0x00000014) + * + *****************************************************************************/ +/* Slice: RG_RED_BLUE3_ENABLE:*/ +/* 1: enable Rank Gradient check for red_blue *Default**/ +/* 0: bypass Rank Gradient check for red_blue */ +#ifdef MRV_DPCC_RG_RED_BLUE3_ENABLE +#endif /* MRV_DPCC_RG_RED_BLUE3_ENABLE */ +/* Slice: RND_RED_BLUE3_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for red_blue *Default**/ +/* 0: bypass Rank Neighbor Difference check for red_blue */ +#ifdef MRV_DPCC_RND_RED_BLUE3_ENABLE +#endif /* MRV_DPCC_RND_RED_BLUE3_ENABLE */ +/* Slice: RO_RED_BLUE3_ENABLE:*/ +/* 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#ifdef MRV_DPCC_RO_RED_BLUE3_ENABLE +#endif /* MRV_DPCC_RO_RED_BLUE3_ENABLE */ +/* Slice: LC_RED_BLUE3_ENABLE:*/ +/* 1: enable Line check for red_blue *Default**/ +/* 0: bypass Line check for red_blue */ +#ifdef MRV_DPCC_LC_RED_BLUE3_ENABLE +#endif /* MRV_DPCC_LC_RED_BLUE3_ENABLE */ +/* Slice: PG_RED_BLUE3_ENABLE:*/ +/* 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#ifdef MRV_DPCC_PG_RED_BLUE3_ENABLE +#endif /* MRV_DPCC_PG_RED_BLUE3_ENABLE */ +/* Slice: RG_GREEN3_ENABLE:*/ +/* 1: enable Rank Gradient check for green *Default**/ +/* 0: bypass Rank Gradient check for green */ +#ifdef MRV_DPCC_RG_GREEN3_ENABLE +#endif /* MRV_DPCC_RG_GREEN3_ENABLE */ +/* Slice: RND_GREEN3_ENABLE:*/ +/* 1: enable Rank Neighbor Difference check for green *Default**/ +/* 0: bypass Rank Neighbor Difference check for green */ +#ifdef MRV_DPCC_RND_GREEN3_ENABLE +#endif /* MRV_DPCC_RND_GREEN3_ENABLE */ +/* Slice: RO_GREEN3_ENABLE:*/ +/* 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#ifdef MRV_DPCC_RO_GREEN3_ENABLE +#endif /* MRV_DPCC_RO_GREEN3_ENABLE */ +/* Slice: LC_GREEN3_ENABLE:*/ +/* 1: enable Line check for green *Default**/ +/* 0: bypass Line check for green */ +#ifdef MRV_DPCC_LC_GREEN3_ENABLE +#endif /* MRV_DPCC_LC_GREEN3_ENABLE */ +/* Slice: PG_GREEN3_ENABLE:*/ +/* 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#ifdef MRV_DPCC_PG_GREEN3_ENABLE +#endif /* MRV_DPCC_PG_GREEN3_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_thresh_1: Line threshold SET_1 (0x00000018) + * + *****************************************************************************/ +/* Slice: LINE_THR_1_RB:*/ +/* line threshold for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_THR_1_RB +#endif /* MRV_DPCC_LINE_THR_1_RB */ +/* Slice: LINE_THR_1_G:*/ +/* line threshold for set 1 green */ +#ifdef MRV_DPCC_LINE_THR_1_G +#endif /* MRV_DPCC_LINE_THR_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_mad_fac_1: Mean Absolute Difference (MAD) factor + * for Line check set 1 (0x0000001c) + * + *****************************************************************************/ +/* Slice: LINE_MAD_FAC_1_RB:*/ +/* line MAD factor for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_MAD_FAC_1_RB +#endif /* MRV_DPCC_LINE_MAD_FAC_1_RB */ +/* Slice: LINE_MAD_FAC_1_G:*/ +/* line MAD factor for set 1 green */ +#ifdef MRV_DPCC_LINE_MAD_FAC_1_G +#endif /* MRV_DPCC_LINE_MAD_FAC_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_pg_fac_1: Peak gradient factor for set 1 (0x00000020) + * + *****************************************************************************/ +/* Slice: PG_FAC_1_RB:*/ +/* Peak gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_PG_FAC_1_RB +#endif /* MRV_DPCC_PG_FAC_1_RB */ +/* Slice: PG_FAC_1_G:*/ +/* Peak gradient factor for set 1 green */ +#ifdef MRV_DPCC_PG_FAC_1_G +#endif /* MRV_DPCC_PG_FAC_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rnd_thresh_1: Rank Neighbor Difference threshold for + * set 1 (0x00000024) + * + *****************************************************************************/ +/* Slice: RND_THR_1_RB:*/ +/* Rank Neighbor Difference threshold for set 1 red/blue */ +#ifdef MRV_DPCC_RND_THR_1_RB +#endif /* MRV_DPCC_RND_THR_1_RB */ +/* Slice: RND_THR_1_G:*/ +/* Rank Neighbor Difference threshold for set 1 green */ +#ifdef MRV_DPCC_RND_THR_1_G +#endif /* MRV_DPCC_RND_THR_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rg_fac_1: Rank gradient factor for set 1 (0x00000028) + * + *****************************************************************************/ +/* Slice: RG_FAC_1_RB:*/ +/* Rank gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_RG_FAC_1_RB +#endif /* MRV_DPCC_RG_FAC_1_RB */ +/* Slice: RG_FAC_1_G:*/ +/* Rank gradient factor for set 1 green */ +#ifdef MRV_DPCC_RG_FAC_1_G +#endif /* MRV_DPCC_RG_FAC_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_thresh_2: Line threshold SET_2 (0x0000002C) + * + *****************************************************************************/ +/* Slice: LINE_THR_2_RB:*/ +/* line threshold for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_THR_2_RB +#endif /* MRV_DPCC_LINE_THR_2_RB */ +/* Slice: LINE_THR_2_G:*/ +/* line threshold for set 1 green */ +#ifdef MRV_DPCC_LINE_THR_2_G +#endif /* MRV_DPCC_LINE_THR_2_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_mad_fac_2: Mean Absolute Difference (MAD) factor + * for Line check set 1 (0x00000030) + * + *****************************************************************************/ +/* Slice: LINE_MAD_FAC_2_RB:*/ +/* line MAD factor for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_MAD_FAC_2_RB +#endif /* MRV_DPCC_LINE_MAD_FAC_2_RB */ +/* Slice: LINE_MAD_FAC_2_G:*/ +/* line MAD factor for set 1 green */ +#ifdef MRV_DPCC_LINE_MAD_FAC_2_G +#endif /* MRV_DPCC_LINE_MAD_FAC_2_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_pg_fac_2: Peak gradient factor for set 1 (0x00000034) + * + *****************************************************************************/ +/* Slice: PG_FAC_2_RB:*/ +/* Peak gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_PG_FAC_2_RB +#endif /* MRV_DPCC_PG_FAC_2_RB */ +/* Slice: PG_FAC_2_G:*/ +/* Peak gradient factor for set 1 green */ +#ifdef MRV_DPCC_PG_FAC_2_G +#endif /* MRV_DPCC_PG_FAC_2_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rnd_thresh_2: Rank Neighbor Difference threshold for + * set 1 (0x00000038) + * + *****************************************************************************/ +/* Slice: RND_THR_2_RB:*/ +/* Rank Neighbor Difference threshold for set 1 red/blue */ +#ifdef MRV_DPCC_RND_THR_2_RB +#endif /* MRV_DPCC_RND_THR_2_RB */ +/* Slice: RND_THR_2_G:*/ +/* Rank Neighbor Difference threshold for set 1 green */ +#ifdef MRV_DPCC_RND_THR_2_G +#endif /* MRV_DPCC_RND_THR_2_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rg_fac_2: Rank gradient factor for set 1 (0x0000003C) + * + *****************************************************************************/ +/* Slice: RG_FAC_2_RB:*/ +/* Rank gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_RG_FAC_2_RB +#endif /* MRV_DPCC_RG_FAC_2_RB */ +/* Slice: RG_FAC_2_G:*/ +/* Rank gradient factor for set 1 green */ +#ifdef MRV_DPCC_RG_FAC_2_G +#endif /* MRV_DPCC_RG_FAC_2_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_thresh_3: Line threshold SET_3 (0x00000040) + * + *****************************************************************************/ +/* Slice: LINE_THR_3_RB:*/ +/* line threshold for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_THR_3_RB +#endif /* MRV_DPCC_LINE_THR_3_RB */ +/* Slice: LINE_THR_3_G:*/ +/* line threshold for set 1 green */ +#ifdef MRV_DPCC_LINE_THR_3_G +#endif /* MRV_DPCC_LINE_THR_3_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_line_mad_fac_3: Mean Absolute Difference (MAD) factor + * for Line check set 1 (0x00000044) + * + *****************************************************************************/ +/* Slice: LINE_MAD_FAC_3_RB:*/ +/* line MAD factor for set 1 red/blue */ +#ifdef MRV_DPCC_LINE_MAD_FAC_3_RB +#endif /* MRV_DPCC_LINE_MAD_FAC_3_RB */ +/* Slice: LINE_MAD_FAC_3_G:*/ +/* line MAD factor for set 1 green */ +#ifdef MRV_DPCC_LINE_MAD_FAC_3_G +#endif /* MRV_DPCC_LINE_MAD_FAC_3_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_pg_fac_3: Peak gradient factor for set 1 (0x00000048) + * + *****************************************************************************/ +/* Slice: PG_FAC_3_RB:*/ +/* Peak gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_PG_FAC_3_RB +#endif /* MRV_DPCC_PG_FAC_3_RB */ +/* Slice: PG_FAC_3_G:*/ +/* Peak gradient factor for set 1 green */ +#ifdef MRV_DPCC_PG_FAC_3_G +#endif /* MRV_DPCC_PG_FAC_3_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rnd_thresh_3: Rank Neighbor Difference threshold for + * set 1 (0x0000004C) + * + *****************************************************************************/ +/* Slice: RND_THR_3_RB:*/ +/* Rank Neighbor Difference threshold for set 1 red/blue */ +#ifdef MRV_DPCC_RND_THR_3_RB +#endif /* MRV_DPCC_RND_THR_3_RB */ +/* Slice: RND_THR_3_G:*/ +/* Rank Neighbor Difference threshold for set 1 green */ +#ifdef MRV_DPCC_RND_THR_3_G +#endif /* MRV_DPCC_RND_THR_3_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rg_fac_3: Rank gradient factor for set 1 (0x00000050) + * + *****************************************************************************/ +/* Slice: RG_FAC_3_RB:*/ +/* Rank gradient factor for set 1 red/blue */ +#ifdef MRV_DPCC_RG_FAC_3_RB +#endif /* MRV_DPCC_RG_FAC_3_RB */ +/* Slice: RG_FAC_3_G:*/ +/* Rank gradient factor for set 1 green */ +#ifdef MRV_DPCC_RG_FAC_3_G +#endif /* MRV_DPCC_RG_FAC_3_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_ro_limits: Rank Order Limits (0x00000054) + * + *****************************************************************************/ +/* Slice: RO_LIM_3_RB:*/ +/* Rank order limit for set 3 red/blue */ +#ifdef MRV_DPCC_RO_LIM_3_RB +#endif /* MRV_DPCC_RO_LIM_3_RB */ +/* Slice: RO_LIM_3_G:*/ +/* Rank order limit for set 3 green */ +#ifdef MRV_DPCC_RO_LIM_3_G +#endif /* MRV_DPCC_RO_LIM_3_G */ +/* Slice: RO_LIM_2_RB:*/ +/* Rank order limit for set 2 red/blue */ +#ifdef MRV_DPCC_RO_LIM_2_RB +#endif /* MRV_DPCC_RO_LIM_2_RB */ +/* Slice: RO_LIM_2_G:*/ +/* Rank order limit for set 2 green */ +#ifdef MRV_DPCC_RO_LIM_2_G +#endif /* MRV_DPCC_RO_LIM_2_G */ +/* Slice: RO_LIM_1_RB:*/ +/* Rank order limit for set 1 red/blue */ +#ifdef MRV_DPCC_RO_LIM_1_RB +#endif /* MRV_DPCC_RO_LIM_1_RB */ +/* Slice: RO_LIM_1_G:*/ +/* Rank order limit for set 1 green */ +#ifdef MRV_DPCC_RO_LIM_1_G +#endif /* MRV_DPCC_RO_LIM_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_rnd_offs: Differential Rank Offsets for Rank Neighbor + * Difference (0x00000058) + * + *****************************************************************************/ +/* Slice: RND_OFFS_3_RB:*/ +/* Rank Offset to Neighbor for set 3 red/blue */ +#ifdef MRV_DPCC_RND_OFFS_3_RB +#endif /* MRV_DPCC_RND_OFFS_3_RB */ +/* Slice: RND_OFFS_3_G:*/ +/* Rank Offset to Neighbor for set 3 green */ +#ifdef MRV_DPCC_RND_OFFS_3_G +#endif /* MRV_DPCC_RND_OFFS_3_G */ +/* Slice: RND_OFFS_2_RB:*/ +/* Rank Offset to Neighbor for set 2 red/blue */ +#ifdef MRV_DPCC_RND_OFFS_2_RB +#endif /* MRV_DPCC_RND_OFFS_2_RB */ +/* Slice: RND_OFFS_2_G:*/ +/* Rank Offset to Neighbor for set 2 green */ +#ifdef MRV_DPCC_RND_OFFS_2_G +#endif /* MRV_DPCC_RND_OFFS_2_G */ +/* Slice: RND_OFFS_1_RB:*/ +/* Rank Offset to Neighbor for set 1 red/blue */ +#ifdef MRV_DPCC_RND_OFFS_1_RB +#endif /* MRV_DPCC_RND_OFFS_1_RB */ +/* Slice: RND_OFFS_1_G:*/ +/* Rank Offset to Neighbor for set 1 green */ +#ifdef MRV_DPCC_RND_OFFS_1_G +#endif /* MRV_DPCC_RND_OFFS_1_G */ +/*****************************************************************************/ +/** + * register: isp_dpcc_bpt_ctrl: bad pixel table settings (0x0000005c) + * + *****************************************************************************/ +/* Slice: BPT_RB_3x3:*/ +/* 1: if BPT active red/blue 9 pixel (3x3) output median */ +/* 0: if BPT active red/blue 4 or 5 pixel output median *Default**/ +#ifdef MRV_DPCC_BPT_RB_3X3 +#endif /* MRV_DPCC_BPT_RB_3X3 */ +/* Slice: BPT_G_3x3:*/ +/* 1: if BPT active green 9 pixel (3x3) output median */ +/* 0: if BPT active green 4 or 5 pixel output median *Default**/ +#ifdef MRV_DPCC_BPT_G_3X3 +#endif /* MRV_DPCC_BPT_G_3X3 */ +/* Slice: BPT_INCL_RB_CENTER:*/ +/* 1: if BPT active include center pixel for red/blue output median 2x2+1 */ +/* 0: if BPT active do not include center pixel for red/blue output median 2x2 *Default**/ +#ifdef MRV_DPCC_BPT_INCL_RB_CENTER +#endif /* MRV_DPCC_BPT_INCL_RB_CENTER */ +/* Slice: BPT_INCL_GREEN_CENTER:*/ +/* 1: if BPT active include center pixel for green output median 2x2+1 */ +/* 0: if BPT active do not include center pixel for green output median 2x2 *Default**/ +#ifdef MRV_DPCC_BPT_INCL_GREEN_CENTER +#endif /* MRV_DPCC_BPT_INCL_GREEN_CENTER */ +/* Slice: BPT_USE_FIX_SET:*/ +/* 1: for BPT write use hard coded methods set */ +/* 0: for BPT write do not use hard coded methods set *Default**/ +#ifdef MRV_DPCC_BPT_USE_FIX_SET +#endif /* MRV_DPCC_BPT_USE_FIX_SET */ +/* Slice: BPT_USE_SET_3:*/ +/* 1: for BPT write use methods set 3 */ +/* 0: for BPT write do not use methods set 3 *Default**/ +#ifdef MRV_DPCC_BPT_USE_SET_3 +#endif /* MRV_DPCC_BPT_USE_SET_3 */ +/* Slice: BPT_USE_SET_2:*/ +/* 1: for BPT write use methods set 2 */ +/* 0: for BPT write do not use methods set 2 *Default**/ +#ifdef MRV_DPCC_BPT_USE_SET_2 +#endif /* MRV_DPCC_BPT_USE_SET_2 */ +/* Slice: BPT_USE_SET_1:*/ +/* 1: for BPT write use methods set 1 */ +/* 0: for BPT write do not use methods set 1 *Default**/ +#ifdef MRV_DPCC_BPT_USE_SET_1 +#endif /* MRV_DPCC_BPT_USE_SET_1 */ +/* Slice: bpt_cor_en:*/ +/* table based correction enable */ +/* 1: table based correction is enabled */ +/* 0: table based correction is disabled */ +#ifdef MRV_DPCC_BPT_COR_EN +#endif /* MRV_DPCC_BPT_COR_EN */ +/* Slice: bpt_det_en:*/ +/* Bad pixel detection write enable */ +/* 1: bad pixel detection write to memory is enabled */ +/* 0: bad pixel detection write to memory is disabled */ +#ifdef MRV_DPCC_BPT_DET_EN +#endif /* MRV_DPCC_BPT_DET_EN */ +/*****************************************************************************/ +/** + * register: isp_dpcc_bpt_addr: TABLE Start Address for table-based correction + * algorithm (0x00000064) + * + *****************************************************************************/ +/* Slice: bp_table_addr:*/ +/* Table RAM start address for read or write operations. The address counter */ +/* is incremented at each read or write access to the data register (auto-*/ +/* increment mechanism).*/ +#ifdef MRV_DPCC_BP_TABLE_ADDR +#endif /* MRV_DPCC_BP_TABLE_ADDR */ +/*****************************************************************************/ +/** + * register: isp_dpcc_bpt_data: TABLE DATA register for read and write access + * of table RAM (0x00000068) + * + *****************************************************************************/ +/* Slice: bpt_v_addr:*/ +/* Bad Pixel vertical address (pixel position)*/ +#ifdef MRV_DPCC_BPT_V_ADDR +#endif /* MRV_DPCC_BPT_V_ADDR */ +/* Slice: bpt_h_addr:*/ +/* Bad Pixel horizontal address (pixel position)*/ +#ifdef MRV_DPCC_BPT_H_ADDR +#endif /* MRV_DPCC_BPT_H_ADDR */ +/*****************************************************************************/ +/* ISP Wide Dynamic Range */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: isp_wdr_ctrl: Control Bits for Wide Dynamic Range Unit (0x00000000) + * + *****************************************************************************/ +/* Slice: WDR_RGB_FACTOR:*/ +/* rgb_factor defines how much influence the RGBmax approach has in comparison */ +/* to Y. The illumination reference Iref is calculated according to the following */ +/* formula:*/ + /**/ +/* Iref = (WDR_RGB_FACTOR * RGBYmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */ + /**/ +/* So, rgb_factor = 0 means that the standard approach is used. Use of this */ +/* factor requires that Iref has been selected, see WDR_USE_IREF.*/ + /**/ +/* Value range of rgb_factor: 0...8 */ +#ifdef MRV_WDR_RGB_FACTOR +#endif /* MRV_WDR_RGB_FACTOR */ +/* Slice: WDR_DISABLE_TRANSIENT:*/ +/* 1: disable transient between Y and RGBY_max */ +/* 0: calculate transient between Y and RGBY_max (for noise reduction) *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#ifdef MRV_WDR_DISABLE_TRANSIENT +#endif /* MRV_WDR_DISABLE_TRANSIENT */ +/* Slice: WDR_USE_RGB7_8:*/ +/* 1: decrease RGBmax by 7/8 (for noise reduction)*/ +/* 0: do not modify RGBmax *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#ifdef MRV_WDR_USE_RGB7_8 +#endif /* MRV_WDR_USE_RGB7_8 */ +/* Slice: WDR_USE_Y9_8:*/ +/* 1: use R G B and Y*9/8 for maximum value calculation (for noise reduction)*/ +/* 0: only use R G B for maximum value calculation (RGBYmax approach) *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#ifdef MRV_WDR_USE_Y9_8 +#endif /* MRV_WDR_USE_Y9_8 */ +/* Slice: WDR_USE_IREF:*/ +/* 1: use Iref (Illumination reference) instead of Y for ToneMapping and Gain calculation */ +/* 0: use Y for ToneMapping and Gain calculation *Default**/ +/* Iref is calculated according to the following formula:*/ +/* Iref = (WDR_RGB_FACTOR * RGBmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */ +#ifdef MRV_WDR_USE_IREF +#endif /* MRV_WDR_USE_IREF */ +/* Slice: WDR_CR_MAPPING_DISABLE:*/ +/* 1: disable (bypass) Chrominance Mapping */ +/* 0: enable Chrominance Mapping *Default**/ +/* requires that Luminance/chrominance color space has been selected */ +#ifdef MRV_WDR_CR_MAPPING_DISABLE +#endif /* MRV_WDR_CR_MAPPING_DISABLE */ +/* Slice: WDR_COLOR_SPACE_SELECT:*/ +/* 1: R, G, B color space */ +/* 0: Luminance/Chrominance color space *Default**/ +#ifdef MRV_WDR_COLOR_SPACE_SELECT +#endif /* MRV_WDR_COLOR_SPACE_SELECT */ +/* Slice: WDR_ENABLE:*/ +/* 1: enable WDR */ +/* 0: bypass WDR *Default**/ +#ifdef MRV_WDR_ENABLE +#endif /* MRV_WDR_ENABLE */ +/*****************************************************************************/ +/** + * register: isp_wdr_tonecurve_1: Tone Curve sample points dYn definition + * (part 1) (0x00000004) + * + * isp_wdr_tonecurve_1_shd: Tone Curve sample points dYn definition + * shadow register (part 1) (0x000000a0) + * + *****************************************************************************/ +/* Slice: WDR_dY8:*/ +/* Tone curve sample point definition dY8 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY8 +#endif /* MRV_WDR_DY8 */ +/* Slice: WDR_dY7:*/ +/* Tone curve sample point definition dY7 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY7 +#endif /* MRV_WDR_DY7 */ +/* Slice: WDR_dY6:*/ +/* Tone curve sample point definition dY6 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY6 +#endif /* MRV_WDR_DY6 */ +/* Slice: WDR_dY5:*/ +/* Tone curve sample point definition dY5 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY5 +#endif /* MRV_WDR_DY5 */ +/* Slice: WDR_dY4:*/ +/* Tone curve sample point definition dY4 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY4 +#endif /* MRV_WDR_DY4 */ +/* Slice: WDR_dY3:*/ +/* Tone curve sample point definition dY3 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY3 +#endif /* MRV_WDR_DY3 */ +/* Slice: WDR_dY2:*/ +/* Tone curve sample point definition dY2 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY2 +#endif /* MRV_WDR_DY2 */ +/* Slice: WDR_dY1:*/ +/* Tone curve sample point definition dY1 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY1 +#endif /* MRV_WDR_DY1 */ +/*****************************************************************************/ +/** + * register: isp_wdr_tonecurve_2: Tone Curve sample points dYn definition + * (part 2) (0x00000008) + * + * isp_wdr_tonecurve_2_shd: Tone Curve sample points dYn definition + * shadow register (part 2) (0x000000a4) + * + *****************************************************************************/ +/* Slice: WDR_dY16:*/ +/* Tone curve sample point definition dY16 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY16 +#endif /* MRV_WDR_DY16 */ +/* Slice: WDR_dY15:*/ +/* Tone curve sample point definition dY15 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY15 +#endif /* MRV_WDR_DY15 */ +/* Slice: WDR_dY14:*/ +/* Tone curve sample point definition dY14 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY14 +#endif /* MRV_WDR_DY14 */ +/* Slice: WDR_dY13:*/ +/* Tone curve sample point definition dY13 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY13 +#endif /* MRV_WDR_DY13 */ +/* Slice: WDR_dY12:*/ +/* Tone curve sample point definition dY12 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY12 +#endif /* MRV_WDR_DY12 */ +/* Slice: WDR_dY11:*/ +/* Tone curve sample point definition dY11 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY11 +#endif /* MRV_WDR_DY11 */ +/* Slice: WDR_dY10:*/ +/* Tone curve sample point definition dY10 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY10 +#endif /* MRV_WDR_DY10 */ +/* Slice: WDR_dY9:*/ +/* Tone curve sample point definition dY9 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY9 +#endif /* MRV_WDR_DY9 */ +/*****************************************************************************/ +/** + * register: isp_wdr_tonecurve_3: Tone Curve sample points dYn definition + * (part 3) (0x0000000c) + * + * isp_wdr_tonecurve_3_shd: Tone Curve sample points dYn definition + * shadow register (part 3) (0x000000a8) + * + *****************************************************************************/ +/* Slice: WDR_dY24:*/ +/* Tone curve sample point definition dY24 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY24 +#endif /* MRV_WDR_DY24 */ +/* Slice: WDR_dY23:*/ +/* Tone curve sample point definition dY23 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY23 +#endif /* MRV_WDR_DY23 */ +/* Slice: WDR_dY22:*/ +/* Tone curve sample point definition dY22 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY22 +#endif /* MRV_WDR_DY22 */ +/* Slice: WDR_dY21:*/ +/* Tone curve sample point definition dY21 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY21 +#endif /* MRV_WDR_DY21 */ +/* Slice: WDR_dY20:*/ +/* Tone curve sample point definition dY20 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY20 +#endif /* MRV_WDR_DY20 */ +/* Slice: WDR_dY19:*/ +/* Tone curve sample point definition dY19 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY19 +#endif /* MRV_WDR_DY19 */ +/* Slice: WDR_dY18:*/ +/* Tone curve sample point definition dY18 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY18 +#endif /* MRV_WDR_DY18 */ +/* Slice: WDR_dY17:*/ +/* Tone curve sample point definition dY17 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY17 +#endif /* MRV_WDR_DY17 */ +/*****************************************************************************/ +/** + * register: isp_wdr_tonecurve_4: Tone Curve sample points dYn definition + * (part 4) (0x00000010) + * + * isp_wdr_tonecurve_4_shd: Tone Curve sample points dYn definition + * shadow register(part 4) (0x000000ac) + * + *****************************************************************************/ +/* Slice: WDR_dY32:*/ +/* Tone curve sample point definition dY32 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY32 +#endif /* MRV_WDR_DY32 */ +/* Slice: WDR_dY31:*/ +/* Tone curve sample point definition dY31 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY31 +#endif /* MRV_WDR_DY31 */ +/* Slice: WDR_dY30:*/ +/* Tone curve sample point definition dY30 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY30 +#endif /* MRV_WDR_DY30 */ +/* Slice: WDR_dY29:*/ +/* Tone curve sample point definition dY29 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY29 +#endif /* MRV_WDR_DY29 */ +/* Slice: WDR_dY28:*/ +/* Tone curve sample point definition dY28 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY28 +#endif /* MRV_WDR_DY28 */ +/* Slice: WDR_dY27:*/ +/* Tone curve sample point definition dY27 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY27 +#endif /* MRV_WDR_DY27 */ +/* Slice: WDR_dY26:*/ +/* Tone curve sample point definition dY26 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY26 +#endif /* MRV_WDR_DY26 */ +/* Slice: WDR_dY25:*/ +/* Tone curve sample point definition dY25 on the horizontal axis (input)*/ +#ifdef MRV_WDR_DY25 +#endif /* MRV_WDR_DY25 */ +/*****************************************************************************/ +/** + * register array: isp_wdr_tonecurve_ym: Tonemapping curve coefficient Ym_ + * (0x0028 + n*0x4 (n=0..32)) + * + *****************************************************************************/ +/* Slice: tonecurve_ym_n:*/ +/* Tone curve value definition y-axis (output) of WDR unit */ +#ifdef MRV_WDR_TONECURVE_YM_N +#endif /* MRV_WDR_TONECURVE_YM_N */ +/*****************************************************************************/ +/** + * register: isp_wdr_offset: Offset values for RGB path (0x00000098) + * + *****************************************************************************/ +/* Slice: LUM_OFFSET:*/ +/* Luminance Offset value (a) for RGB operation mode */ +/* unsigned 12 bit value */ +#ifdef MRV_WDR_LUM_OFFSET +#endif /* MRV_WDR_LUM_OFFSET */ +/* Slice: RGB_OFFSET:*/ +/* RGB Offset value (b) for RGB operation mode */ +/* unsigned 12 bit value */ +#ifdef MRV_WDR_RGB_OFFSET +#endif /* MRV_WDR_RGB_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_wdr_deltamin: DeltaMin Threshold and Strength factor (0x0000009c) + * + *****************************************************************************/ +/* Slice: DMIN_STRENGTH:*/ +/* strength factor for DMIN */ +/* unsigned 5 bit value, range 0x00...0x10 */ +#ifdef MRV_WDR_DMIN_STRENGTH +#endif /* MRV_WDR_DMIN_STRENGTH */ +/* Slice: DMIN_THRESH:*/ +/* Lower threshold for deltaMin value */ +/* unsigned 12 bit value */ +#ifdef MRV_WDR_DMIN_THRESH +#endif /* MRV_WDR_DMIN_THRESH */ +/*****************************************************************************/ +/** + * register array: isp_wdr_tonecurve_ym_shd: Tonemapping curve coefficient + * shadow register (0x0160 + n*0x4 (n=0..32)) + * + *****************************************************************************/ +/* Slice: tonecurve_ym_n_shd:*/ +/* Tone curve value definition y-axis (output) of WDR unit */ +/* shadow register.*/ +#ifdef MRV_WDR_TONECURVE_YM_N_SHD +#endif /* MRV_WDR_TONECURVE_YM_N_SHD */ +/*****************************************************************************/ +/* ISP Elliptic Auto White Balance Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: awb_meas_mode: AWB Measure Mode (0x00000000) + * + *****************************************************************************/ +/*! Register: awb_meas_mode: AWB Measure Mode (0x00000000)*/ +/*! Slice: AWB_union_e5_and_e8:*/ +/*! unite ellipse 5 with ellipse 8. Accu and count for ellipse 8.*/ +#ifdef ISP_AWB_UNION_E5_AND_E8 +#define ISP_AWB_UNION_E5_AND_E8_ON 1 /* 1: enable unite ellipse 5 with ellipse 8 */ +#define ISP_AWB_UNION_E5_AND_E8_OFF 0 /* 0: disable unite ellipse 5 with ellipse 8 */ +#endif /* ISP_AWB_UNION_E5_AND_E8 */ +/*! Slice: AWB_union_e5_and_e7:*/ +/*! unite ellipse 5 with ellipse 7. Accu and count for ellipse 7.*/ +#ifdef ISP_AWB_UNION_E5_AND_E7 +#define ISP_AWB_UNION_E5_AND_E7_ON 1 /* 1: enable unite ellipse 5 with ellipse 7 */ +#define ISP_AWB_UNION_E5_AND_E7_OFF 0 /* 0: disable unite ellipse 5 with ellipse 7 */ +#endif /* ISP_AWB_UNION_E5_AND_E7 */ +/*! Slice: AWB_union_e5_and_e6:*/ +/*! unite ellipse 5 with ellipse 6. Accu and count for ellipse 6.*/ +#ifdef ISP_AWB_UNION_E5_AND_E6 +#define ISP_AWB_UNION_E5_AND_E6_ON 1 /* 1: enable unite ellipse 5 with ellipse 6 */ +#define ISP_AWB_UNION_E5_AND_E6_OFF 0 /* 0: disable unite ellipse 5 with ellipse 6 */ +#endif /* ISP_AWB_UNION_E5_AND_E6 */ +/*! Slice: AWB_union_e1_and_e4:*/ +/*! unite ellipse 1 with ellipse 4. Accu and count for ellipse 4.*/ +#ifdef ISP_AWB_UNION_E1_AND_E4 +#define ISP_AWB_UNION_E1_AND_E4_ON 1 /* 1: enable unite ellipse 1 with ellipse 4 */ +#define ISP_AWB_UNION_E1_AND_E4_OFF 0 /* 0: disable unite ellipse 1 with ellipse 4 */ +#endif /* ISP_AWB_UNION_E1_AND_E4 */ +/*! Slice: AWB_union_e1_and_e3:*/ +/*! unite ellipse 1 with ellipse 3. Accu and count for ellipse 3.*/ +#ifdef ISP_AWB_UNION_E1_AND_E3 +#define ISP_AWB_UNION_E1_AND_E3_ON 1 /* 1: enable unite ellipse 1 with ellipse 3 */ +#define ISP_AWB_UNION_E1_AND_E3_OFF 0 /* 0: disable unite ellipse 1 with ellipse 3 */ +#endif /* ISP_AWB_UNION_E1_AND_E3 */ +/*! Slice: AWB_union_e1_and_e2:*/ +/*! unite ellipse 1 with ellipse 2. Accu and count for ellipse 2.*/ +#ifdef ISP_AWB_UNION_E1_AND_E2 +#define ISP_AWB_UNION_E1_AND_E2_ON 1 /* 1: enable unite ellipse 1 with ellipse 2 */ +#define ISP_AWB_UNION_E1_AND_E2_OFF 0 /* 0: disable unite ellipse 1 with ellipse 2 */ +#endif /* ISP_AWB_UNION_E1_AND_E2 */ +/*! Slice: AWB_meas_chrom_switch:*/ +/*! Accumulates Q1 and Q2 chromaticies instead of R, G, B color signals. Results are written on AWB_ACCU registers as well.*/ +#ifdef ISP_AWB_MEAS_CHROM_SWITCH +#define ISP_AWB_MEAS_CHROM_SWITCH_ON 1 /* 1: accumulates Q1 and Q2 chromaticies */ +#define ISP_AWB_MEAS_CHROM_SWITCH_OFF 0 /* 0: accumulates R, G, B color signals */ +#endif /* ISP_AWB_MEAS_CHROM_SWITCH */ +/* Slice: AWB_meas_irq_enable:*/ +/* AWB measure done IRQ enable.*/ +#ifdef ISP_AWB_MEAS_IRQ_ENABLE +#define ISP_AWB_MEAS_IRQ_ENABLE_ON 1 /* 1: enable measuring done irq */ +#define ISP_AWB_MEAS_IRQ_ENABLE_OFF 0 /* 0: enable measuring done irq */ +#endif /* ISP_AWB_MEAS_IRQ_ENABLE */ +/* Slice: AWB_pre_filt_en:*/ +/* median pre filter enable.*/ +#ifdef ISP_AWB_PRE_FILT_EN +#define ISP_AWB_PRE_FILT_EN_ON 1 /* 1: enable median pre filter */ +#define ISP_AWB_PRE_FILT_EN_OFF 0 /* 0: disable median pre filter */ +#endif /* ISP_AWB_PRE_FILT_EN */ +/* Slice: AWB_meas_en:*/ +/* enable measure.*/ +#ifdef ISP_AWB_MEAS_EN +#define ISP_AWB_MEAS_EN_ON 1 /* 1: enable measuring */ +#define ISP_AWB_MEAS_EN_OFF 0 /* 0: disable measuring */ +#endif /* ISP_AWB_MEAS_EN */ +/*****************************************************************************/ +/** + * register: awb_meas_h_offs: AWB window horizontal offset (0x00000004) + * + *****************************************************************************/ +/* Slice: AWB_h_offset:*/ +/* Horizontal offset in pixels.*/ +#ifdef ISP_AWB_H_OFFSET +#define ISP_AWB_H_OFFSET_MIN 0U +#define ISP_AWB_H_OFFSET_MAX (ISP_AWB_H_OFFSET_MASK >> ISP_AWB_H_OFFSET_SHIFT) +#endif /* ISP_AWB_H_OFFSET */ +/*****************************************************************************/ +/** + * register: awb_meas_v_offs: AWB window vertical offset (0x00000008) + * + *****************************************************************************/ +/* Slice: AWB_v_offset:*/ +/* Vertical offset in pixels.*/ +#ifdef ISP_AWB_V_OFFSET +#define ISP_AWB_V_OFFSET_MIN 0U +#define ISP_AWB_V_OFFSET_MAX (ISP_AWB_V_OFFSET_MASK >> ISP_AWB_V_OFFSET_SHIFT) +#endif /* ISP_AWB_V_OFFSET */ +/*****************************************************************************/ +/** + * register: awb_meas_h_size: Horizontal window size (0x0000000c) + * + *****************************************************************************/ +/* Slice: AWB_h_size:*/ +/* Horizontal size in pixels.*/ +#ifdef ISP_AWB_H_SIZE +#define ISP_AWB_H_SIZE_MIN 0U +#define ISP_AWB_H_SIZE_MAX (ISP_AWB_H_SIZE_MASK >> ISP_AWB_H_SIZE_SHIFT) +#endif /* ISP_AWB_H_SIZE */ +/*****************************************************************************/ +/** + * register: awb_meas_v_size: Vertical window size (0x00000010) + * + *****************************************************************************/ +/* Slice: AWB_v_size:*/ +/* Vertical size.*/ +#ifdef ISP_AWB_V_SIZE +#define ISP_AWB_V_SIZE_MIN 0U +#define ISP_AWB_V_SIZE_MAX (ISP_AWB_V_SIZE_MASK >> ISP_AWB_V_SIZE_SHIFT) +#endif /* ISP_AWB_V_SIZE */ +/*****************************************************************************/ +/** + * register: awb_meas_r_min_max: Min Max Compare Red (0x00000014) + * + *****************************************************************************/ +/* Slice: r_max:*/ +/* max red value */ +#ifdef ISP_AWB_R_MAX +#endif /* ISP_AWB_R_MAX */ +/* Slice: r_min:*/ +/* min red value */ +#ifdef ISP_AWB_R_MIN +#endif /* ISP_AWB_R_MIN */ +/*****************************************************************************/ +/** + * register: awb_meas_g_min_max: Min Max Compare Green (0x00000018) + * + *****************************************************************************/ +/* Slice: g_max:*/ +/* max green value */ +#ifdef ISP_AWB_G_MAX +#endif /* ISP_AWB_G_MAX */ +/* Slice: g_min:*/ +/* min green value */ +#ifdef ISP_AWB_G_MIN +#endif /* ISP_AWB_G_MIN */ +/*****************************************************************************/ +/** + * register: awb_meas_b_min_max: Min Max Compare Blue (0x0000001c) + * + *****************************************************************************/ +/* Slice: b_max:*/ +/* max blue value */ +#ifdef ISP_AWB_B_MAX +#endif /* ISP_AWB_B_MAX */ +/*! Slice: b_min:*/ +/*! min blue value */ +#ifdef ISP_AWB_B_MIN +#endif /* ISP_AWB_B_MIN */ +/*****************************************************************************/ +/** + * register: awb_meas_divider_min: Min Compare Divider (0x00000020) + * + *****************************************************************************/ +/* Slice: div_min:*/ +/* min divider value unsigned integer with 10 fractional Bits range 0 to 0.999 */ +#ifdef ISP_AWB_DIV_MIN +#endif /* ISP_AWB_DIV_MIN */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_0: Color conversion coefficient 0 (0x00000024) + * + *****************************************************************************/ +/* Slice: cc_coeff_0:*/ +/* coefficient 0 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_0 +#endif /* ISP_AWB_CC_COEFF_0 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_1: Color conversion coefficient 1 (0x00000028) + * + *****************************************************************************/ +/* Slice: cc_coeff_1:*/ +/* coefficient 1 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_1 +#endif /* ISP_AWB_CC_COEFF_1 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_2: Color conversion coefficient 2 (0x0000002c) + * + *****************************************************************************/ +/* Slice: cc_coeff_2:*/ +/* coefficient 2 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_2 +#endif /* ISP_AWB_CC_COEFF_2 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_3: Color conversion coefficient 3 (0x00000030) + * + *****************************************************************************/ +/* Slice: cc_coeff_3:*/ +/* coefficient 3 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_3 +#endif /* ISP_AWB_CC_COEFF_3 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_4: Color conversion coefficient 4 (0x00000034) + * + *****************************************************************************/ +/* Slice: cc_coeff_4:*/ +/* coefficient 4 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_4 +#endif /* ISP_AWB_CC_COEFF_4 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_5: Color conversion coefficient 5 (0x00000038) + * + *****************************************************************************/ +/* Slice: cc_coeff_5:*/ +/* coefficient 5 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_5 +#endif /* ISP_AWB_CC_COEFF_5 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_6: Color conversion coefficient 6 (0x0000003c) + * + *****************************************************************************/ +/* Slice: cc_coeff_6:*/ +/* coefficient 6 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_6 +#endif /* ISP_AWB_CC_COEFF_6 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_7: Color conversion coefficient 7 (0x00000040) + * + *****************************************************************************/ +/* Slice: cc_coeff_7:*/ +/* coefficient 7 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_7 +#endif /* ISP_AWB_CC_COEFF_7 */ +/*****************************************************************************/ +/** + * register: awb_meas_csc_coeff_8: Color conversion coefficient 8 (0x00000044) + * + *****************************************************************************/ +/* Slice: cc_coeff_8:*/ +/* coefficient 8 for color space conversion */ +#ifdef ISP_AWB_CC_COEFF_8 +#endif /* ISP_AWB_CC_COEFF_8 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_cen_x: Ellipse 1 Center X (0x00000048) + * + *****************************************************************************/ +/* Slice: ellip1_cen_x:*/ +/* Ellipse 1 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP1_CEN_X +#endif /* ISP_AWB_ELLIP1_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_cen_y: Ellipse 1 Center Y (0x0000004c) + * + *****************************************************************************/ +/* Slice: ellip1_cen_y:*/ +/* Ellipse 1 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP1_CEN_Y +#endif /* ISP_AWB_ELLIP1_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_cen_x: Ellipse 2 Center X (0x00000050) + * + *****************************************************************************/ +/* Slice: ellip2_cen_x:*/ +/* Ellipse 2 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP2_CEN_X +#endif /* ISP_AWB_ELLIP2_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_cen_y: Ellipse 2 Center Y (0x00000054) + * + *****************************************************************************/ +/* Slice: ellip2_cen_y:*/ +/* Ellipse 2 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP2_CEN_Y +#endif /* ISP_AWB_ELLIP2_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_cen_x: Ellipse 3 Center X (0x00000058) + * + *****************************************************************************/ +/* Slice: ellip3_cen_x:*/ +/* Ellipse 3 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP3_CEN_X +#endif /* ISP_AWB_ELLIP3_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_cen_y: Ellipse 3 Center Y (0x0000005c) + * + *****************************************************************************/ +/* Slice: ellip3_cen_y:*/ +/* Ellipse 3 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP3_CEN_Y +#endif /* ISP_AWB_ELLIP3_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_cen_x: Ellipse 4 Center X (0x00000060) + * + *****************************************************************************/ +/* Slice: ellip4_cen_x:*/ +/* Ellipse 4 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP4_CEN_X +#endif /* ISP_AWB_ELLIP4_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_cen_y: Ellipse 4 Center Y (0x00000064) + * + *****************************************************************************/ +/* Register: awb_meas_ellip4_cen_y: Ellipse 4 Center Y (0x00000064)*/ +/* Slice: ellip4_cen_y:*/ +/* Ellipse 4 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP4_CEN_Y +#endif /* ISP_AWB_ELLIP4_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_cen_x: Ellipse 5 Center X (0x00000068) + * + *****************************************************************************/ +/* Slice: ellip5_cen_x:*/ +/* Ellipse 5 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP5_CEN_X +#endif /* ISP_AWB_ELLIP5_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_cen_y: Ellipse 5 Center Y (0x0000006c) + * + *****************************************************************************/ +/* Slice: ellip5_cen_y:*/ +/* Ellipse 5 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP5_CEN_Y +#endif /* ISP_AWB_ELLIP5_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_cen_x: Ellipse 6 Center X (0x00000070) + * + *****************************************************************************/ +/* Slice: ellip6_cen_x:*/ +/* Ellipse 6 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP6_CEN_X +#endif /* ISP_AWB_ELLIP6_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_cen_y: Ellipse 6 Center Y (0x00000074) + * + *****************************************************************************/ +/* Slice: ellip6_cen_y:*/ +/* Ellipse 6 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP6_CEN_Y +#endif /* ISP_AWB_ELLIP6_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_cen_x: Ellipse 7 Center X (0x00000078) + * + *****************************************************************************/ +/* Slice: ellip7_cen_x:*/ +/* Ellipse 7 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP7_CEN_X +#endif /* ISP_AWB_ELLIP7_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_cen_y: Ellipse 7 Center Y (0x0000007c) + * + *****************************************************************************/ +/* Slice: ellip7_cen_y:*/ +/* Ellipse 7 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP7_CEN_Y +#endif /* ISP_AWB_ELLIP7_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_cen_x: Ellipse 8 Center X (0x00000080) + * + *****************************************************************************/ +/* Slice: ellip8_cen_x:*/ +/* Ellipse 8 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP8_CEN_X +#endif /* ISP_AWB_ELLIP8_CEN_X */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_cen_y: Ellipse 8 Center Y (0x00000084) + * + *****************************************************************************/ +/* Slice: ellip8_cen_y:*/ +/* Ellipse 8 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#ifdef ISP_AWB_ELLIP8_CEN_Y +#endif /* ISP_AWB_ELLIP8_CEN_Y */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_a1: Ellipse 1 coefficient a1 (0x00000088) + * + *****************************************************************************/ +/* Slice: ellip1_a1:*/ +/* Ellipse 1 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP1_A1 +#endif /* ISP_AWB_ELLIP1_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_a2: Ellipse 1 coefficient a2 (0x0000008c) + * + *****************************************************************************/ +/* Slice: ellip1_a2:*/ +/* Ellipse 1 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP1_A2 +#endif /* ISP_AWB_ELLIP1_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_a3: Ellipse 1 coefficient a3 (0x00000090) + * + *****************************************************************************/ +/* Slice: ellip1_a3:*/ +/* Ellipse 1 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP1_A3 +#endif /* ISP_AWB_ELLIP1_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_a4: Ellipse 1 coefficient a4 (0x00000094) + * + *****************************************************************************/ +/* Slice: ellip1_a4:*/ +/* Ellipse 1 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP1_A4 +#endif /* ISP_AWB_ELLIP1_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_a1: Ellipse 2 coefficient a1 (0x00000098) + * + *****************************************************************************/ +/* Slice: ellip2_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP2_A1 +#endif /* ISP_AWB_ELLIP2_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_a2: Ellipse 2 coefficient a2 (0x0000009c) + * + *****************************************************************************/ +/* Slice: ellip2_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP2_A2 +#endif /* ISP_AWB_ELLIP2_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_a3: Ellipse 2 coefficient a3 (0x000000a0) + * + *****************************************************************************/ +/* Slice: ellip2_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP2_A3 +#endif /* ISP_AWB_ELLIP2_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_a4: Ellipse 2 coefficient a4 (0x000000a4) + * + *****************************************************************************/ +/* Slice: ellip2_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP2_A4 +#endif /* ISP_AWB_ELLIP2_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_a1: Ellipse 3 coefficient a1 (0x000000a8) + * + *****************************************************************************/ +/* Slice: ellip3_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP3_A1 +#endif /* ISP_AWB_ELLIP3_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_a2: Ellipse 3 coefficient a2 (0x000000ac) + * + *****************************************************************************/ +/* Slice: ellip3_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP3_A2 +#endif /* ISP_AWB_ELLIP3_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_a3: Ellipse 3 coefficient a3 (0x000000b0) + * + *****************************************************************************/ +/* Slice: ellip3_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP3_A3 +#endif /* ISP_AWB_ELLIP3_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_a4: Ellipse 3 coefficient a4 (0x000000b4) + * + *****************************************************************************/ +/* Slice: ellip3_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP3_A4 +#endif /* ISP_AWB_ELLIP3_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_a1: Ellipse 4 coefficient a1 (0x000000b8) + * + *****************************************************************************/ +/* Slice: ellip4_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP4_A1 +#endif /* ISP_AWB_ELLIP4_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_a2: Ellipse 4 coefficient a2 (0x000000bc) + * + *****************************************************************************/ +/* Slice: ellip4_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP4_A2 +#endif /* ISP_AWB_ELLIP4_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_a3: Ellipse 4 coefficient a3 (0x000000c0) + * + *****************************************************************************/ +/* Slice: ellip4_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP4_A3 +#endif /* ISP_AWB_ELLIP4_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_a4: Ellipse 4 coefficient a4 (0x000000c4) + * + *****************************************************************************/ +/* Slice: ellip4_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP4_A4 +#endif /* ISP_AWB_ELLIP4_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_a1: Ellipse 5 coefficient a1 (0x000000c8) + * + *****************************************************************************/ +/* Slice: ellip5_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP5_A1 +#endif /* ISP_AWB_ELLIP5_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_a2: Ellipse 5 coefficient a2 (0x000000cc) + * + *****************************************************************************/ +/* Slice: ellip5_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP5_A2 +#endif /* ISP_AWB_ELLIP5_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_a3: Ellipse 5 coefficient a3 (0x000000d0) + * + *****************************************************************************/ +/* Slice: ellip5_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP5_A3 +#endif /* ISP_AWB_ELLIP5_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_a4: Ellipse 5 coefficient a4 (0x000000d4) + * + *****************************************************************************/ +/* Slice: ellip5_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP5_A4 +#endif /* ISP_AWB_ELLIP5_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_a1: Ellipse 6 coefficient a1 (0x000000d8) + * + *****************************************************************************/ +/* Slice: ellip6_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP6_A1 +#endif /* ISP_AWB_ELLIP6_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_a2: Ellipse 6 coefficient a2 (0x000000dc) + * + *****************************************************************************/ +/* Slice: ellip6_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP6_A2 +#endif /* ISP_AWB_ELLIP6_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_a3: Ellipse 6 coefficient a3 (0x000000e0) + * + *****************************************************************************/ +/* Slice: ellip6_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP6_A3 +#endif /* ISP_AWB_ELLIP6_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_a4: Ellipse 6 coefficient a4 (0x000000e4) + * + *****************************************************************************/ +/* Slice: ellip6_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP6_A4 +#endif /* ISP_AWB_ELLIP6_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_a1: Ellipse 7 coefficient a1 (0x000000e8) + * + *****************************************************************************/ +/* Slice: ellip7_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP7_A1 +#endif /* ISP_AWB_ELLIP7_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_a2: Ellipse 7 coefficient a2 (0x000000ec) + * + *****************************************************************************/ +/* Slice: ellip7_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP7_A2 +#endif /* ISP_AWB_ELLIP7_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_a3: Ellipse 7 coefficient a3 (0x000000f0) + * + *****************************************************************************/ +/* Slice: ellip7_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP7_A3 +#endif /* ISP_AWB_ELLIP7_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_a4: Ellipse 7 coefficient a4 (0x000000f4) + * + *****************************************************************************/ +/* Slice: ellip7_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP7_A4 +#endif /* ISP_AWB_ELLIP7_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_a1: Ellipse 8 coefficient a1 (0x000000f8) + * + *****************************************************************************/ +/* Slice: ellip8_a1:*/ +/* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP8_A1 +#endif /* ISP_AWB_ELLIP8_A1 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_a2: Ellipse 8 coefficient a2 (0x000000fc) + * + *****************************************************************************/ +/* Slice: ellip8_a2:*/ +/* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP8_A2 +#endif /* ISP_AWB_ELLIP8_A2 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_a3: Ellipse 8 coefficient a3 (0x00000100) + * + *****************************************************************************/ +/* Slice: ellip8_a3:*/ +/* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#ifdef ISP_AWB_ELLIP8_A3 +#endif /* ISP_AWB_ELLIP8_A3 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_a4: Ellipse 8 coefficient a4 (0x00000104) + * + *****************************************************************************/ +/* Slice: ellip8_a4:*/ +/* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#ifdef ISP_AWB_ELLIP8_A4 +#endif /* ISP_AWB_ELLIP8_A4 */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip1_rmax: Ellipse 1 r_max (0x00000108) + * + *****************************************************************************/ +/* Slice: ellip1_rmax:*/ +/* Ellipse 1 max radius square compare value */ +#ifdef ISP_AWB_ELLIP1_RMAX +#endif /* ISP_AWB_ELLIP1_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip2_rmax: Ellipse 2 r_max (0x0000010c) + * + *****************************************************************************/ +/* Slice: ellip2_rmax:*/ +/* Ellipse 2 max radius square compare value */ +#ifdef ISP_AWB_ELLIP2_RMAX +#endif /* ISP_AWB_ELLIP2_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip3_rmax: Ellipse 3 r_max (0x00000110) + * + *****************************************************************************/ +/* Slice: ellip3_rmax:*/ +/* Ellipse 3 max radius square compare value */ +#ifdef ISP_AWB_ELLIP3_RMAX +#endif /* ISP_AWB_ELLIP3_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip4_rmax: Ellipse 4 r_max (0x00000114) + * + *****************************************************************************/ +/* Slice: ellip4_rmax:*/ +/* Ellipse 4 max radius square compare value */ +#ifdef ISP_AWB_ELLIP4_RMAX +#endif /* ISP_AWB_ELLIP4_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip5_rmax: Ellipse 5 r_max (0x00000118) + * + *****************************************************************************/ +/* Slice: ellip5_rmax:*/ +/* Ellipse 5 max radius square compare value */ +#ifdef ISP_AWB_ELLIP5_RMAX +#endif /* ISP_AWB_ELLIP5_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip6_rmax: Ellipse 6 r_max (0x0000011c) + * + *****************************************************************************/ +/* Slice: ellip6_rmax:*/ +/* Ellipse 6 max radius square compare value */ +#ifdef ISP_AWB_ELLIP6_RMAX +#endif /* ISP_AWB_ELLIP6_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip7_rmax: Ellipse 7 r_max (0x00000120) + * + *****************************************************************************/ +/* Slice: ellip7_rmax:*/ +/* Ellipse 7 max radius square compare value */ +#ifdef ISP_AWB_ELLIP7_RMAX +#endif /* ISP_AWB_ELLIP7_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_ellip8_rmax: Ellipse 8 r_max (0x00000124) + * + *****************************************************************************/ +/* Slice: ellip8_rmax:*/ +/* Ellipse 8 max radius square compare value */ +#ifdef ISP_AWB_ELLIP8_RMAX +#endif /* ISP_AWB_ELLIP8_RMAX */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_1: AWB Counter 1 (0x00000128) + * + *****************************************************************************/ +/* Slice: count_1:*/ +/* counted Pixels of Ellipse 1 */ +#ifdef ISP_AWB_COUNT_1 +#endif /* ISP_AWB_COUNT_1 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_2: AWB Counter 2 (0x0000012c) + * + *****************************************************************************/ +/* Slice: count_2:*/ +/* counted Pixels of Ellipse 2 */ +#ifdef ISP_AWB_COUNT_2 +#endif /* ISP_AWB_COUNT_2 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_3: AWB Counter 3 (0x00000130) + * + *****************************************************************************/ +/* Slice: count_3:*/ +/* counted Pixels of Ellipse 3 */ +#ifdef ISP_AWB_COUNT_3 +#endif /* ISP_AWB_COUNT_3 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_4: AWB Counter 4 (0x00000134) + * + *****************************************************************************/ +/* Slice: count_4:*/ +/* counted Pixels of Ellipse 4 */ +#ifdef ISP_AWB_COUNT_4 +#endif /* ISP_AWB_COUNT_4 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_5: AWB Counter 5 (0x00000138) + * + *****************************************************************************/ +/* Slice: count_5:*/ +/* counted Pixels of Ellipse 5 */ +#ifdef ISP_AWB_COUNT_5 +#endif /* ISP_AWB_COUNT_5 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_6: AWB Counter 6 (0x0000013c) + * + *****************************************************************************/ +/* Slice: count_6:*/ +/* counted Pixels of Ellipse 6 */ +#ifdef ISP_AWB_COUNT_6 +#endif /* ISP_AWB_COUNT_6 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_7: AWB Counter 7 (0x00000140) + * + *****************************************************************************/ +/* Slice: count_7:*/ +/* counted Pixels of Ellipse 7 */ +#ifdef ISP_AWB_COUNT_7 +#endif /* ISP_AWB_COUNT_7 */ +/*****************************************************************************/ +/** + * register: awb_meas_counter_8: AWB Counter 8 (0x00000144) + * + *****************************************************************************/ +/* Slice: count_8:*/ +/* counted Pixels of Ellipse 8 */ +#ifdef ISP_AWB_COUNT_8 +#endif /* ISP_AWB_COUNT_8 */ +/*****************************************************************************/ +/** + * register array: awb_meas_accu: AWB Accu Read (0x298 + n*0x4 (n=0..23)) + * + *****************************************************************************/ +/* Slice: read_accu:*/ +/* measured sum[34:3] of RGB values.*/ +#ifdef ISP_AWB_READ_ACCU +#endif /* ISP_AWB_READ_ACCU */ +#ifdef EE_CTRL_ENABLE +#define EE_CTRL_ENABLE_SET 1 +#define EE_CTRL_ENABLE_CLEAR 0 +#endif +/*****************************************************************************/ +/** + * register array: awb_meas_accu: AWB Accu Read (0x298 + n*0x4 (n=0..23)) + * + *****************************************************************************/ +/* Slice: read_accu:*/ +/* measured sum[34:3] of RGB values.*/ +#ifdef ISP_VSM_DELTA_H +#endif /* ISP_AWB_READ_ACCU */ +/*****************************************************************************/ +/** + * register: isp_vsm_h_offs: VSM window horizontal offset + * + *****************************************************************************/ +/* Slice: vsm_h_offset:*/ +/* Horizontal offset in pixels.*/ +#ifdef ISP_VSM_H_OFFSET +#define ISP_VSM_H_OFFSET_MAX (ISP_VSM_H_OFFSET_MASK >> ISP_VSM_H_OFFSET_SHIFT) +#endif /* ISP_VSM_H_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_vsm_v_offs: VSM window vertical offset + * + *****************************************************************************/ +/* Slice: vsm_v_offset:*/ +/* Vertical offset in pixels.*/ +#ifdef ISP_VSM_V_OFFSET +#define ISP_VSM_V_OFFSET_MAX (ISP_VSM_V_OFFSET_MASK >> ISP_VSM_V_OFFSET_SHIFT) +#endif /* ISP_VSM_V_OFFSET */ +/*****************************************************************************/ +/** + * register: isp_vsm_h_size: Horizontal measure window size + * + *****************************************************************************/ +/* Slice: vsm_h_size:*/ +/* Horizontal size in pixels..*/ +#ifdef ISP_VSM_H_SIZE +/* note: do not apply shift, since bit 0 is only excluded to get even values */ +#define ISP_VSM_H_SIZE_MAX ISP_VSM_H_SIZE_MASK +#endif /* ISP_VSM_H_SIZE */ +/*****************************************************************************/ +/** + * register: isp_vsm_v_size: Vertical measure window size + * + *****************************************************************************/ +/* Slice: vsm_v_size:*/ +/* Vertical size in pixels.*/ +#ifdef ISP_VSM_V_SIZE +/* note: do not apply shift, since bit 0 is only excluded to get even values */ +#define ISP_VSM_V_SIZE_MAX ISP_VSM_V_SIZE_MASK +#endif /* ISP_VSM_V_SIZE */ +/*****************************************************************************/ +/** + * register: isp_vsm_h_segments: Iteration 1 horizontal segments + * + *****************************************************************************/ +/* Slice: vsm_h_segments:*/ +/* number of 16 point wide segments enclosed by the first iteration sample */ +/* points in horizontal direction. Range: 1 ... 128 */ +#ifdef ISP_VSM_H_SEGMENTS +#define ISP_VSM_H_SEGMENTS_MIN 1 +#define ISP_VSM_H_SEGMENTS_MAX 128 +#endif /* ISP_VSM_H_SEGMENTS */ +/*****************************************************************************/ +/** + * register: isp_vsm_v_segments: Iteration 1 vertical segments + * + *****************************************************************************/ +/* Slice: vsm_v_segments:*/ +/* number of 16 point wide segments enclosed by the first iteration sample */ +/* points in vertical direction. Range: 1 ... 128 */ +/* Note: number of 1st iteration sample points = vsm_v_segments + 1.*/ +/* vsm_v_segments must be equal or smaller than vsm_h_segments.*/ +#ifdef ISP_VSM_V_SEGMENTS +#define ISP_VSM_V_SEGMENTS_MIN 1 +#define ISP_VSM_V_SEGMENTS_MAX 128 +#endif /* ISP_VSM_V_SEGMENTS */ +#ifdef ISP_GCMONO +/*****************************************************************************/ +/** + * register: isp_gcmono_ctrl: gcmono enable and lut table cfg + * + *****************************************************************************/ +/*! Slice: mono_gc_enable */ +/*! Control of gamma correction for mono sensor RAW data */ +/*! 1'b0: disable GC and enter bypass mode */ +/*! 1'b1: enable GC mode */ +#ifdef ISP_GCMONO_SWITCH +#define ISP_GCMONO_SWITCH_DISABLE 0 /* 0: disable GC */ +#define ISP_GCMONO_SWITCH_ENABLE 1 /* 1: enable GC */ +#endif +/*! Slice: mono_gc_cfg_done */ +/*! To notify the ISP HW the LUT configuration is done, ready to use, active high.*/ +/*! Writing ZERO reset teh internal read/write pointer and also indicates that the LUT can be configured or read from CPU.*/ +#ifdef ISP_GCMONO_CFG_DONE +#define ISP_GCMONO_CFG_DONE_CURVE_READY 1 /* 1: notify ISP HW LUT configuration is done */ +#define ISP_GCMONO_CFG_DONE_SET_CURVE 0 /* 0: Write ZERO reset the internal pointer and can cfg LUT. */ +#endif +#ifdef ISP_GCMONO_PARA_BASE +#endif +#endif +/*****************************************************************************/ +/* MIV2 Registers */ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * register: miv2_mp_fmt: main path pixel format control register (0x1314) + * + *****************************************************************************/ +// Slice: MP_WR_JDP_FMT +// 1: JPEG +// 0: DPCC +#ifdef MP_WR_JDP_FMT +#define MIV2_MP_WRITE_FORMAT_DPCC 0 //DPCC +#define MIV2_MP_WRITE_FORMAT_JPEG 1 //JPEG +#endif /* MP_WR_JDP_FMT */ +// Slice: MP_WR_YUV_BIT: +// 1: 10bit YUV/RGB +// 0: 8bit YUV/RGB +#ifdef MP_WR_YUV_BIT +#define MIV2_MP_WRITE_FORMAT_8BIT 0 //8bit YUV/RGB +#define MIV2_MP_WRITE_FORMAT_10BIT 1 //10bit YUV/RGB +#endif /* MP_WR_YUV_BIT */ +// Slice: MP_WR_YUV_FMT: +#ifdef MP_WR_YUV_FMT +#define MIV2_MP_WRITE_FORMAT_YUV420 0 // 00: YUV420 +#define MIV2_MP_WRITE_FORMAT_YUV422 1 // 01: YUV422 +#define MIV2_MP_WRITE_FORMAT_YUV444 2 // 10: YUV444 +#endif /* MP_WR_YUV_FMT */ +// Slice: MP_WR_YUV_STR: +#ifdef MP_WR_YUV_STR +#define MIV2_MP_WRITE_STRIDE_SEMIPLANAR 0 // 00: YUV/RGB SemiPlanar +#define MIV2_MP_WRITE_STRIDE_INTERLEAVE 1 // 01: YUV Interleave, RGB Raster +#define MIV2_MP_WRITE_STRIDE_PLANAR 2 // 10: YUV/RGB Planar +#endif /* MP_WR_YUV_STR */ +// Slice: MP_WR_RAW_BIT: +#ifdef MP_WR_RAW_BIT +#define MIV2_MP_WRITE_FORMAT_RAW8 0 // 000: RAW8 +#define MIV2_MP_WRITE_FORMAT_RAW10 1 // 001: RAW10 +#define MIV2_MP_WRITE_FORMAT_RAW12 2 // 010: RAW12 +#define MIV2_MP_WRITE_FORMAT_RAW14 3 // 011: RAW14 +#define MIV2_MP_WRITE_FORMAT_RAW16 4 // 100: RAW16 +#define MIV2_MP_WRITE_FORMAT_RAW20 5 // 101: RAW20 +#endif /* MP_WR_RAW_BIT */ +// Slice: MP_WR_YUV_ALIGNED +// 1: aligned +// 0: unaligned +#ifdef MP_WR_YUV_ALIGNED +#define MIV2_MP_WRITE_YUV_UNALIGNED 0 //unaligned +#define MIV2_MP_WRITE_YUV_ALIGNED 1 //aligned +#endif /* MP_WR_YUV_ALIGNED */ +// Slice: MP_WR_RAW_ALIGNED: +#ifdef MP_WR_RAW_ALIGNED +#define MIV2_MP_WRITE_RAW_UNALIGNED 0 // 00: unaligned +#define MIV2_MP_WRITE_RAW_ALIGNED_MODE1 1 // 01: aligned mode1 +#define MIV2_MP_WRITE_RAW_ALIGNED_MODE2 2 // 10: aligned mode2 +#endif /* MP_WR_RAW_ALIGNED */ +// Slice: MP_WR_YUV_NV21 +// 1: Put U before V +// 0: Put V before U +#ifdef MP_WR_YUV_NV21 +#define MIV2_MP_WRITE_YUV_NV21_UV 0 //Put U before V +#define MIV2_MP_WRITE_YUV_NV21_VU 1 //Put V before U +#endif /* MP_WR_YUV_NV21 */ +// Slice: MP_WR_YUV_NVY: +#ifdef MP_WR_YUV_NVY +#define MIV2_MP_WRITE_YUV_NVY_YC1C2 0 // 00: Put Y first => YC1C2 +#define MIV2_MP_WRITE_YUV_NVY_C1YC2 1 // 01: Put Y second => C1YC2 +#define MIV2_MP_WRITE_YUV_NVY_C1C2Y 2 // 10: Put Y Third => C1C2Y +#endif /* MP_WR_YUV_NVY */ +// ========================================================================================= +#ifdef ISP_DEMOSAIC_DENOISE_STRENGTH +#define ISP_DEMOSAIC_DENOISE_STRENGTH_MIN 0 +#define ISP_DEMOSAIC_DENOISE_STRENGTH_MAX 32 +#endif +#ifdef ISP_DEMOSAIC_SHARPEN_SIZE +#define ISP_DEMOSAIC_SHARPEN_SIZE_MIN 0 +#define ISP_DEMOSAIC_SHARPEN_SIZE_MAX 16 +#endif +#ifdef ISP_DMSC_DEMOIRE_AREA_THR +#define ISP_DMSC_DEMOIRE_AREA_THR_MIN 0 +#define ISP_DMSC_DEMOIRE_AREA_THR_MAX 32 +#endif +#ifdef ISP_DMSC_DEMOIRE_SAT_SHRINK +#define ISP_DMSC_DEMOIRE_SAT_SHRINK_MIN 0 +#define ISP_DMSC_DEMOIRE_SAT_SHRINK_MAX 32 +#endif +#ifdef ISP_DMSC_SHARPEN_T4_SHIFT +#define ISP_DMSC_SHARPEN_SHIFT_MIN 0 +#define ISP_DMSC_SHARPEN_SHIFT_MAX 11 +#endif +#ifdef ISP_DMSC_SHARPEN_LINE_SHIFT1 +#define ISP_DMSC_SHARPEN_LINE_SHIFT1_MIN 0 +#define ISP_DMSC_SHARPEN_LINE_SHIFT1_MAX 10 +#endif +#ifdef ISP_DMSC_HF_FILT_00 +#define ISP_DMSC_HF_FILT_MIN 0 +#define ISP_DMSC_HF_FILT_MAX 34 +#endif +#ifdef ISP_DMSC_CBCR_MODE +#define ISP_DMSC_CBCR_MODE_MIN 0 +#define ISP_DMSC_CBCR_MODE_MAX 3 +#endif +#ifdef ISP_DMSC_DEPURPLE_SAT_SHRINK +#define ISP_DMSC_DEPURPLE_SAT_SHRINK_MIN 0 +#define ISP_DMSC_DEPURPLE_SAT_SHRINK_MAX 8 +#endif +#ifdef ISP_DMSC_X_NF +#define ISP_DMSC_X_NF_MIN 0 +#define ISP_DMSC_X_NF_MAX 31 +#endif +#ifdef ISP_DMSC_X_NS +#define ISP_DMSC_X_NS_MIN 0 +#define ISP_DMSC_X_NS_MAX 15 +#endif +#ifdef ISP_DMSC_Y_NF +#define ISP_DMSC_Y_NF_MIN 0 +#define ISP_DMSC_Y_NF_MAX 31 +#endif +#ifdef ISP_DMSC_Y_NS +#define ISP_DMSC_Y_NS_MIN 0 +#define ISP_DMSC_Y_NS_MAX 15 +#endif +/* =========================================================================================*/ +/*! returns the value of slice \a name from register or variable \a reg + * \note "parameter" \a reg could be a hardware register or a (32bit) variable, but not a pointer! \n + * each slice (specified as "parameter" \a name) requires two \#defines: \n + * - \_MASK : defines the mask to use on register side + * - \_SHIFT : defines the shift value to use (left on write, right on read) + */ +#define REG_GET_SLICE(reg, name) \ + (((reg) & (name##_MASK)) >> (name##_SHIFT)) +/* =========================================================================================*/ +/*! writes the value \a value into slice \a name of register or variable \a reg + * \note "parameter" \a reg could be a hardware register or a (32bit) variable, but not a pointer! \n + * each slice (specified as "parameter" \a name) requires two \#defines: \n + * - \_MASK : defines the mask to use on register side + * - \_SHIFT : defines the shift value to use (left on write, right on read) + */ +#define REG_SET_SLICE(reg, name, value) \ + { \ + ((reg) = (((reg) & ~(name##_MASK)) | (((value) << (name##_SHIFT)) & (name##_MASK))));\ + } +#endif /* __MRV_ALL_BITS_H__ */ diff --git a/vvcam_ry/isp/mrv_all_regs.h b/vvcam_ry/isp/mrv_all_regs.h new file mode 100755 index 0000000..773e98d --- /dev/null +++ b/vvcam_ry/isp/mrv_all_regs.h @@ -0,0 +1,20364 @@ +/***************************************************************************** + * + * Copyright 2013, Dream Chip Technologies GmbH. All rights reserved. + * + **************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +/* +* NOTE: This file is automaticaly generated by sig of theflow Rev.: 1.1_dev_koehler. +* Modifications can be lost. +* +*****************************************************************************/ +/** +*----------------------------------------------------------------------------- +* $HeadURL$ +* $Author$ +* $Rev$ +* $Date$ +*----------------------------------------------------------------------------- +* @file mrv_all_regs.h +* +* 
+*
+* Description:
+*   This header file exports the module register structure and masks.
+*	It should not be included directly by your driver/application, it will be
+*   exported by the _regs_io.h header file.
+*
+*
+*/ +/*****************************************************************************/ + +#ifndef _MRV_ALL_REGS_H +#define _MRV_ALL_REGS_H + +/* Definitions of block register sizes */ +#define DEGAMMA_R_Y_BLOCK_ARR_SIZE 17 +#define DEGAMMA_G_Y_BLOCK_ARR_SIZE 17 +#define DEGAMMA_B_Y_BLOCK_ARR_SIZE 17 +#define CROSS_TALK_COEF_BLOCK_ARR_SIZE 9 +#define GAMMA_OUT_Y_BLOCK_ARR_SIZE 17 +#define HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE 16 +#define NLF_LOOKUP_TABLE_BLOCK_ARR_SIZE 17 +#define WDR_TONE_MAPPING_CURVE_Y_BLOCK_ARR_SIZE 33 +#define WDR_TONE_MAPPING_CURVE_Y_SHD_BLOCK_ARR_SIZE 33 +#define AWB_MEAS_ACCU_ARR_SIZE 24 +#define ISP64_HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE 32 +#define ISP_HDREXP_MEASUREMENT_RESULT_ARR_SIZE 25 + +/*! degamma_r_y_block register layout */ +typedef struct { + uint32_t isp_gamma_r_y; /*!< De-Gamma Curve definition y red (rw) MRV_ISP_BASE + 0x448 + (n*0x4) (n=0..16) */ +} degamma_r_y_block_t; + +/*! degamma_g_y_block register layout */ +typedef struct { + uint32_t isp_gamma_g_y; /*!< De-Gamma Curve definition y green (rw) MRV_ISP_BASE + 0x490 + (n*0x4) (n=0..16) */ +} degamma_g_y_block_t; + +/*! degamma_b_y_block register layout */ +typedef struct { + uint32_t isp_gamma_b_y; /*!< De-Gamma Curve definition y blue (rw) MRV_ISP_BASE + 0x4D8 + (n*0x4) (n=0..16) */ +} degamma_b_y_block_t; + +/*! cross_talk_coef_block register layout */ +typedef struct { + uint32_t isp_ct_coeff; /*!< cross-talk configuration register (color correction matrix) (rw) MRV_ISP_BASE + 0x7A0 + (n*0x4) (n=0..8) */ +} cross_talk_coef_block_t; + +/*! gamma_out_y_block register layout */ +typedef struct { + uint32_t isp_gamma_out_y; /*!< Gamma Out Curve definition y_ (rw) MRV_ISP_BASE + 0x7F0 + (n*0x4) (n=0..16) */ +} gamma_out_y_block_t; + +/*! histogram_measurement_result register layout */ +typedef struct { + uint32_t isp_hist_bin; /*!< histogram measurement result bin (r) MRV_HIST_BASE + 0x2428 + (n*0x4) (n=0..15) */ +} histogram_measurement_result_t; + +/*! nlf_lookup_table_block register layout */ +typedef struct { + uint32_t isp_dpf_nll_coeff; /*!< Noise Level Lookup Coefficient (rw) MRV_DPF_BASE + 0x2840 + (n*0x4) (n=0..16) */ +} nlf_lookup_table_block_t; + +/*! wdr_tone_mapping_curve_y_block register layout */ +typedef struct { + uint32_t isp_wdr_tonecurve_ym; /*!< Tonemapping curve coefficient Ym_ (rw) MRV_WDR_BASE + 0x2A28 + (n*0x4) (n=0..32) */ +} wdr_tone_mapping_curve_y_block_t; + +/*! wdr_tone_mapping_curve_y_shd_block register layout */ +typedef struct { + uint32_t isp_wdr_tonecurve_ym_shd; /*!< Tonemapping curve coefficient shadow register (r) MRV_WDR_BASE + 0x2B60 + (n*0x4) (n=0..32) */ +} wdr_tone_mapping_curve_y_shd_block_t; + +/*! AWB_MEAS_ACCU register layout */ +typedef struct { + uint32_t awb_meas_accu; /*!< AWB Accu Read (r) ISP_AWB_BASE + 0x2E90 + (n*0x4) (n=0..23) */ +} AWB_MEAS_ACCU_t; + +/*! isp64_histogram_measurement_result register layout */ +typedef struct { + uint32_t isp64_hist_bin; /*!< histogram measurement result bin (sh_r) MRV_HIST_BASE + 0x2EA8 + (n*0x4) (n=0..31) */ +} isp64_histogram_measurement_result_t; + +typedef struct { + uint32_t x, y; +} elawb_ellipse_pt; + +typedef struct { + uint32_t a1, a2, a3, a4; +} elawb_ellipse_axis; + +/*! MrvAll Register layout */ +typedef struct { + uint32_t vi_ccl; /*!< Clock control register (rw) MRV_BASE + 0x00000000 */ + uint32_t _notused_0[(0x00000008 - 0x00000004) / 4]; /* gap in address space */ + uint32_t vi_id; /*!< Revision identification register (r) MRV_BASE + 0x00000008 */ + uint32_t _notused_1[(0x00000010 - 0x0000000c) / 4]; /* gap in address space */ + uint32_t vi_iccl; /*!< Internal clock control register (rw) MRV_BASE + 0x00000010 */ + uint32_t vi_ircl; /*!< Internal reset control register (rw) MRV_BASE + 0x00000014 */ + uint32_t vi_dpcl; /*!< Data path control register (rw) MRV_BASE + 0x00000018 */ + uint32_t _notused_2[(0x00000200 - 0x0000001c) / 4]; /* gap in address space */ + uint32_t img_eff_ctrl; /*!< Global control register (rw) MRV_IMGEFF_BASE + 0x00000000 */ + uint32_t img_eff_color_sel; /*!< Color selection register (for color selection effect) (rw) MRV_IMGEFF_BASE + 0x00000004 */ + uint32_t img_eff_mat_1; /*!< 3x3 matrix coefficients for emboss effect (1) (rw) MRV_IMGEFF_BASE + 0x00000008 */ + uint32_t img_eff_mat_2; /*!< 3x3 matrix coefficients for emboss effect (2) (rw) MRV_IMGEFF_BASE + 0x0000000c */ + uint32_t img_eff_mat_3; /*!< 3x3 matrix coefficients for emboss(3) effect / sketch/sharpen(1) effect (rw) MRV_IMGEFF_BASE + 0x00000010 */ + uint32_t img_eff_mat_4; /*!< 3x3 matrix coefficients for sketch/sharpen effect (2) (rw) MRV_IMGEFF_BASE + 0x00000014 */ + uint32_t img_eff_mat_5; /*!< 3x3 matrix coefficients for sketch/sharpen effect (3) (rw) MRV_IMGEFF_BASE + 0x00000018 */ + uint32_t img_eff_tint; /*!< Chrominance increment values of a tint (used for sepia effect) (rw) MRV_IMGEFF_BASE + 0x0000001c */ + uint32_t img_eff_ctrl_shd; /*!< Shadow register for control register (r) MRV_IMGEFF_BASE + 0x00000020 */ + uint32_t img_eff_sharpen; /*!< Factor and threshold for sharpen effect (rw) MRV_IMGEFF_BASE + 0x00000024 */ + uint32_t _notused_3[(0x00000300 - 0x00000228) / 4]; /* gap in address space */ + uint32_t super_imp_ctrl; /*!< Global control register (rw) MRV_SI_BASE + 0x00000000 */ + uint32_t super_imp_offset_x; /*!< Offset x register (rw) MRV_SI_BASE + 0x00000004 */ + uint32_t super_imp_offset_y; /*!< Offset y register (rw) MRV_SI_BASE + 0x00000008 */ + uint32_t super_imp_color_y; /*!< Y component of transparent key color (rw) MRV_SI_BASE + 0x0000000c */ + uint32_t super_imp_color_cb; /*!< Cb component of transparent key color (rw) MRV_SI_BASE + 0x00000010 */ + uint32_t super_imp_color_cr; /*!< Cr component of transparent key color (rw) MRV_SI_BASE + 0x00000014 */ + uint32_t _notused_4[(0x00000400 - 0x00000318) / 4]; /* gap in address space */ + uint32_t isp_ctrl; /*!< global control register (rw) MRV_ISP_BASE + 0x00000000 */ + uint32_t isp_acq_prop; /*!< ISP acquisition properties (rw) MRV_ISP_BASE + 0x00000004 */ + uint32_t isp_acq_h_offs; /*!< horizontal input offset (rw) MRV_ISP_BASE + 0x00000008 */ + uint32_t isp_acq_v_offs; /*!< vertical input offset (rw) MRV_ISP_BASE + 0x0000000c */ + uint32_t isp_acq_h_size; /*!< horizontal input size (rw) MRV_ISP_BASE + 0x00000010 */ + uint32_t isp_acq_v_size; /*!< vertical input size (rw) MRV_ISP_BASE + 0x00000014 */ + uint32_t isp_acq_nr_frames; /*!< Number of frames to be captured (rw) MRV_ISP_BASE + 0x00000018 */ + uint32_t isp_gamma_dx_lo; /*!< De-Gamma Curve definition lower x increments (sampling points) (rw) MRV_ISP_BASE + 0x0000001c */ + uint32_t isp_gamma_dx_hi; /*!< De-Gamma Curve definition higher x increments (sampling points) (rw) MRV_ISP_BASE + 0x00000020 */ + degamma_r_y_block_t degamma_r_y_block_arr[DEGAMMA_R_Y_BLOCK_ARR_SIZE]; /*!< degamma_r_y_block MRV_ISP_BASE + 36 + (n*0x4) (n=0..16) */ + degamma_g_y_block_t degamma_g_y_block_arr[DEGAMMA_G_Y_BLOCK_ARR_SIZE]; /*!< degamma_g_y_block MRV_ISP_BASE + 104 + (n*0x4) (n=0..16) */ + degamma_b_y_block_t degamma_b_y_block_arr[DEGAMMA_B_Y_BLOCK_ARR_SIZE]; /*!< degamma_b_y_block MRV_ISP_BASE + 172 + (n*0x4) (n=0..16) */ + uint32_t isp_dgain_rb; /*!< (rw) MRV_ISP_BASE + 0x000000f0 */ + uint32_t isp_dgain_g; /*!< (rw) MRV_ISP_BASE + 0x000000f4 */ + uint32_t _notused_5[(0x00000510 - 0x000004f8) / 4]; /* gap in address space */ + uint32_t isp_awb_prop; /*!< Auto white balance properties (rw) MRV_ISP_BASE + 0x00000110 */ + uint32_t isp_awb_h_offs; /*!< Auto white balance horizontal offset of measure window (rw) MRV_ISP_BASE + 0x00000114 */ + uint32_t isp_awb_v_offs; /*!< Auto white balance vertical offset of measure window (rw) MRV_ISP_BASE + 0x00000118 */ + uint32_t isp_awb_h_size; /*!< Auto white balance horizontal window size (rw) MRV_ISP_BASE + 0x0000011c */ + uint32_t isp_awb_v_size; /*!< Auto white balance vertical window size (rw) MRV_ISP_BASE + 0x00000120 */ + uint32_t isp_awb_frames; /*!< Auto white balance mean value over multiple frames (rw) MRV_ISP_BASE + 0x00000124 */ + uint32_t isp_awb_ref; /*!< Auto white balance reference Cb/Cr values (rw) MRV_ISP_BASE + 0x00000128 */ + uint32_t isp_awb_thresh; /*!< Auto white balance threshold values (rw) MRV_ISP_BASE + 0x0000012c */ + uint32_t _notused_6[(0x00000538 - 0x00000530) / 4]; /* gap in address space */ + uint32_t isp_awb_gain_g; /*!< Auto white balance gain green (rw) MRV_ISP_BASE + 0x00000138 */ + uint32_t isp_awb_gain_rb; /*!< Auto white balance gain red and blue (rw) MRV_ISP_BASE + 0x0000013c */ + uint32_t isp_awb_white_cnt; /*!< Auto white balance white pixel count (r) MRV_ISP_BASE + 0x00000140 */ + uint32_t isp_awb_mean; /*!< Auto white balance measured mean value (r) MRV_ISP_BASE + 0x00000144 */ + uint32_t _notused_7[(0x00000570 - 0x00000548) / 4]; /* gap in address space */ + uint32_t isp_cc_coeff_0; /*!< Color conversion coefficient 0 (rw) MRV_ISP_BASE + 0x00000170 */ + uint32_t isp_cc_coeff_1; /*!< Color conversion coefficient 1 (rw) MRV_ISP_BASE + 0x00000174 */ + uint32_t isp_cc_coeff_2; /*!< Color conversion coefficient 2 (rw) MRV_ISP_BASE + 0x00000178 */ + uint32_t isp_cc_coeff_3; /*!< Color conversion coefficient 3 (rw) MRV_ISP_BASE + 0x0000017c */ + uint32_t isp_cc_coeff_4; /*!< Color conversion coefficient 4 (rw) MRV_ISP_BASE + 0x00000180 */ + uint32_t isp_cc_coeff_5; /*!< Color conversion coefficient 5 (rw) MRV_ISP_BASE + 0x00000184 */ + uint32_t isp_cc_coeff_6; /*!< Color conversion coefficient 6 (rw) MRV_ISP_BASE + 0x00000188 */ + uint32_t isp_cc_coeff_7; /*!< Color conversion coefficient 7 (rw) MRV_ISP_BASE + 0x0000018c */ + uint32_t isp_cc_coeff_8; /*!< Color conversion coefficient 8 (rw) MRV_ISP_BASE + 0x00000190 */ + uint32_t isp_out_h_offs; /*!< Horizontal offset of output window (rw) MRV_ISP_BASE + 0x00000194 */ + uint32_t isp_out_v_offs; /*!< Vertical offset of output window (rw) MRV_ISP_BASE + 0x00000198 */ + uint32_t isp_out_h_size; /*!< Output horizontal picture size (rw) MRV_ISP_BASE + 0x0000019c */ + uint32_t isp_out_v_size; /*!< Output vertical picture size (rw) MRV_ISP_BASE + 0x000001a0 */ + uint32_t isp_demosaic; /*!< Demosaic parameters (rw) MRV_ISP_BASE + 0x000001a4 */ + uint32_t isp_flags_shd; /*!< Flags (current status) of certain signals and Shadow regs for enable signals (r) MRV_ISP_BASE + 0x000001a8 */ + uint32_t isp_out_h_offs_shd; /*!< current horizontal offset of output window (shadow register) (r) MRV_ISP_BASE + 0x000001ac */ + uint32_t isp_out_v_offs_shd; /*!< current vertical offset of output window (shadow register) (r) MRV_ISP_BASE + 0x000001b0 */ + uint32_t isp_out_h_size_shd; /*!< current output horizontal picture size (shadow register) (r) MRV_ISP_BASE + 0x000001b4 */ + uint32_t isp_out_v_size_shd; /*!< current output vertical picture size (shadow register) (r) MRV_ISP_BASE + 0x000001b8 */ + uint32_t isp_imsc; /*!< Interrupt mask (rw) MRV_ISP_BASE + 0x000001bc */ + uint32_t isp_ris; /*!< Raw interrupt status (r) MRV_ISP_BASE + 0x000001c0 */ + uint32_t isp_mis; /*!< Masked interrupt status (r) MRV_ISP_BASE + 0x000001c4 */ + uint32_t isp_icr; /*!< Interrupt clear register (w) MRV_ISP_BASE + 0x000001c8 */ + uint32_t isp_isr; /*!< Interrupt set register (w) MRV_ISP_BASE + 0x000001cc */ + cross_talk_coef_block_t cross_talk_coef_block_arr[CROSS_TALK_COEF_BLOCK_ARR_SIZE]; /*!< cross_talk_coef_block MRV_ISP_BASE + 464 + (n*0x4) (n=0..8) */ + uint32_t isp_gamma_out_mode; /*!< gamma segmentation mode register for output gamma (rw) MRV_ISP_BASE + 0x000001f4 */ + gamma_out_y_block_t gamma_out_y_block_arr[GAMMA_OUT_Y_BLOCK_ARR_SIZE]; /*!< gamma_out_y_block MRV_ISP_BASE + 504 + (n*0x4) (n=0..16) */ + uint32_t isp_err; /*!< ISP error register (r) MRV_ISP_BASE + 0x0000023c */ + uint32_t isp_err_clr; /*!< ISP error clear register (w) MRV_ISP_BASE + 0x00000240 */ + uint32_t isp_frame_count; /*!< Frame counter (r) MRV_ISP_BASE + 0x00000244 */ + uint32_t isp_ct_offset_r; /*!< cross-talk offset red (rw) MRV_ISP_BASE + 0x00000248 */ + uint32_t isp_ct_offset_g; /*!< cross-talk offset green (rw) MRV_ISP_BASE + 0x0000024c */ + uint32_t isp_ct_offset_b; /*!< cross-talk offset blue (rw) MRV_ISP_BASE + 0x00000250 */ + uint32_t isp_cnr_linesize; /*!< chroma noise reduction line size (rw) MRV_ISP_BASE + 0x00000254 */ + uint32_t isp_cnr_threshold_c1; /*!< chroma noise reduction C1 Threshold (rw) MRV_ISP_BASE + 0x00000258 */ + uint32_t isp_cnr_threshold_c2; /*!< chroma noise reduction C2 Threshold (rw) MRV_ISP_BASE + 0x0000025c */ + uint32_t isp_flash_cmd; /*!< Flash command (w) MRV_FLASH_BASE + 0x00000000 */ + uint32_t isp_flash_config; /*!< Flash config (rw) MRV_FLASH_BASE + 0x00000004 */ + uint32_t isp_flash_prediv; /*!< Flash Counter Pre-Divider (rw) MRV_FLASH_BASE + 0x00000008 */ + uint32_t isp_flash_delay; /*!< Flash Delay (rw) MRV_FLASH_BASE + 0x0000000c */ + uint32_t isp_flash_time; /*!< Flash time (rw) MRV_FLASH_BASE + 0x00000010 */ + uint32_t isp_flash_maxp; /*!< Maximum value for flash or preflash (rw) MRV_FLASH_BASE + 0x00000014 */ + uint32_t _notused_8[(0x00000680 - 0x00000678) / 4]; /* gap in address space */ + uint32_t isp_sh_ctrl; /*!< mechanical shutter control (rw) MRV_SHUT_BASE + 0x00000000 */ + uint32_t isp_sh_prediv; /*!< Mech. Shutter Counter Pre-Divider (rw) MRV_SHUT_BASE + 0x00000004 */ + uint32_t isp_sh_delay; /*!< Delay register (rw) MRV_SHUT_BASE + 0x00000008 */ + uint32_t isp_sh_time; /*!< Time register (rw) MRV_SHUT_BASE + 0x0000000c */ + + /* TPG */ + uint32_t _notused_pre_tpg[(0x00000700 - 0x00000690) / 4]; /* gap in address space */ + + uint32_t isp_tpg_ctrl; /*!<(rw), 0x00000700 */ + uint32_t isp_tpg_total_in; /*!<(rw), 0x00000704 */ + uint32_t isp_tpg_act_in; /*!<(rw), 0x00000708 */ + uint32_t isp_tpg_fp_in; /*!<(rw), 0x0000070C */ + uint32_t isp_tpg_bp_in; /*!<(rw), 0x00000710 */ + uint32_t isp_tpg_w_in; /*!<(rw), 0x00000714 */ + uint32_t isp_tpg_gap_in; /*!<(rw), 0x00000718 */ + uint32_t isp_tpg_gap_std_in; /*!<(rw), 0x0000071C */ + uint32_t isp_tpg_random_seed; /*!<(rw), 0x00000720 */ + uint32_t _notused_mid_tpg1[(0x00000730 - 0x00000724) / 4]; /* gap in address space */ + uint32_t isp_vsync_delay; /*!<(rw), 0x00000730 */ + uint32_t _notused_mid_tpg2[(0x00000750 - 0x00000734) / 4]; /* gap in address space */ + uint32_t green_equilibrate_ctrl; /*!<(rw), 0x00000750 */ + uint32_t green_equilibrate_hcnt_dummy; /*!<(rw), 0x00000754 */ + uint32_t green_equilibrate_ctrl_shd; /*!<(rw), 0x00000758 */ + + uint32_t _notused_after_tpg[(0x00000800 - 0x0000075c) / 4]; /* gap in address space */ + /* uint32_t _notused_9[(0x00000800-0x00000690)/4]; gap in address space */ + + uint32_t cproc_ctrl; /*!< Global control register (rw) MRV_CPROC_BASE + 0x00000000 */ + uint32_t cproc_contrast; /*!< Color Processing contrast register (rw) MRV_CPROC_BASE + 0x00000004 */ + uint32_t cproc_brightness; /*!< Color Processing brightness register (rw) MRV_CPROC_BASE + 0x00000008 */ + uint32_t cproc_saturation; /*!< Color Processing saturation register (rw) MRV_CPROC_BASE + 0x0000000c */ + uint32_t cproc_hue; /*!< Color Processing hue register (rw) MRV_CPROC_BASE + 0x00000010 */ +#ifdef ISP_RGBGC_RY + uint32_t _notused_10_0[(0x00000900 - 0x00000814) / 4]; /* gap in address space */ + uint32_t isp_gcrgb_r_px_0; /*! MI_MP/SP_Y/CB/CR_OFFS_CNT_SHD */ +/* The update will be executed either when a forced software update occurs (in register MI_INIT bit cfg_upd = 1) or when an automatic config update signal arrives at the MI input port. The latter is split into main and self picture. So only the corresponding main/self shadow registers are affected.*/ +/* After a picture skip has been performed init_offset_en selects between skip restart and skip init mode (see bit skip in register MI_INIT).*/ +#define MRV_MI_INIT_OFFSET_EN +#define MRV_MI_INIT_OFFSET_EN_MASK 0x00200000U +#define MRV_MI_INIT_OFFSET_EN_SHIFT 21U +/*! Slice: init_base_en:*/ +/*! Enables updating of the base address and buffer size shadow registers for main and self picture to the programmed register init values.*/ +/* MI_MP/SP_Y/CB/CR_BASE_AD_INIT */ +/* -> MI_MP/SP_Y/CB/CR_BASE_AD_SHD */ +/* MI_MP/SP_Y/CB/CR_SIZE_INIT */ +/* -> MI_MP/SP_Y/CB/CR_SIZE_SHD */ +/* The update will be executed either when a forced software update occurs (in register MI_INIT bit cfg_upd = 1) or when an automatic config update signal arrives at the MI input port. The latter is split into main and self picture. So only the corresponding main/self shadow registers are affected.*/ +#define MRV_MI_INIT_BASE_EN +#define MRV_MI_INIT_BASE_EN_MASK 0x00100000U +#define MRV_MI_INIT_BASE_EN_SHIFT 20U +/*! Slice: burst_len_chrom:*/ +/*! Burst length for Cb or Cr data affecting write port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported. If rotation is active, then only 4-beat bursts will be generated in self path, regardless of the setting here.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/ +#define MRV_MI_BURST_LEN_CHROM +#define MRV_MI_BURST_LEN_CHROM_MASK 0x000C0000U +#define MRV_MI_BURST_LEN_CHROM_SHIFT 18U +/*! Slice: burst_len_lum:*/ +/*! Burst length for Y, JPEG, or raw data affecting write port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/ +#define MRV_MI_BURST_LEN_LUM +#define MRV_MI_BURST_LEN_LUM_MASK 0x00030000U +#define MRV_MI_BURST_LEN_LUM_SHIFT 16U +/*! Slice: last_pixel_sig_en:*/ +/*! enables the last pixel signalization */ +/* 1: enabled */ +/* 0: disabled */ +#define MRV_MI_LAST_PIXEL_SIG_EN +#define MRV_MI_LAST_PIXEL_SIG_EN_MASK 0x00008000U +#define MRV_MI_LAST_PIXEL_SIG_EN_SHIFT 15U +/*! Slice: sp_auto_update:*/ +/*! automatic update of configuration registers for self path at frame end.*/ +/* 1: enabled */ +/* 0: disabled */ +#define MRV_MI_SP_AUTO_UPDATE +#define MRV_MI_SP_AUTO_UPDATE_MASK 0x00004000U +#define MRV_MI_SP_AUTO_UPDATE_SHIFT 14U +/*! Slice: mp_auto_update:*/ +/*! automatic update of configuration registers for main path at frame end.*/ +/* 1: enabled */ +/* 0: disabled */ +#define MRV_MI_MP_AUTO_UPDATE +#define MRV_MI_MP_AUTO_UPDATE_MASK 0x00002000U +#define MRV_MI_MP_AUTO_UPDATE_SHIFT 13U +/*! Slice: sp_pingpong_enable:*/ +/*! pingpong mode of configuration registers for self path at frame end.*/ +/* 1: enabled */ +/* 0: disabled */ +#define MRV_MI_SP_PINGPONG_ENABLE +#define MRV_MI_SP_PINGPONG_ENABLE_MASK 0x00001000U +#define MRV_MI_SP_PINGPONG_ENABLE_SHIFT 12U +/*! Slice: mp_pingpong_enable:*/ +/*! pingpong mode of configuration registers for main path at frame end.*/ +/* 1: enabled */ +/* 0: disabled */ +#define MRV_MI_MP_PINGPONG_ENABLE +#define MRV_MI_MP_PINGPONG_ENABLE_MASK 0x00000800U +#define MRV_MI_MP_PINGPONG_ENABLE_SHIFT 11U +/*! Slice: 422noncosited:*/ +/*! Enables self path YCbCr422non-co-sited -> YCbCr444 interpolation */ +/* (M5_v6, M5_v7 only)*/ +/* 1: YCbCr422 data are non_co-sited (Cb and Cr samples are centered between Y samples) so modified interpolation is activated */ +/* 0: YCbCr422 data are co-sited (Y0 Cb0 and Cr0 are sampled at the same position)*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_422NONCOSITED +#define MRV_MI_422NONCOSITED_MASK 0x00000400U +#define MRV_MI_422NONCOSITED_SHIFT 10U +/*! Slice: cbcr_full_range:*/ +/*! Enables CbCr full range for self path YCbCr -> RGB conversion */ +/* (M5_v6, M5_v7 only)*/ +/* 1: CbCr have full range (0..255)*/ +/* 0: CbCr have compressed range range (16..240)*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_CBCR_FULL_RANGE +#define MRV_MI_CBCR_FULL_RANGE_MASK 0x00000200U +#define MRV_MI_CBCR_FULL_RANGE_SHIFT 9U +/*! Slice: y_full_range:*/ +/*! Enables Y full range for self path YCbCr -> RGB conversion */ +/* (M5_v6, M5_v7 only)*/ +/* 1: Y has full range (0..255)*/ +/* 0: Y has compressed range (16..235)*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_Y_FULL_RANGE +#define MRV_MI_Y_FULL_RANGE_MASK 0x00000100U +#define MRV_MI_Y_FULL_RANGE_SHIFT 8U +/*! Slice: byte_swap:*/ +/*! Enables change of byte order of the 32 bit output word at write port */ +/* 1: byte order is mirrored but the bit order within one byte doesn’t change */ +/* 0: no byte mirroring */ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/ +#define MRV_MI_BYTE_SWAP +#define MRV_MI_BYTE_SWAP_MASK 0x00000080U +#define MRV_MI_BYTE_SWAP_SHIFT 7U +/*! Slice: rot:*/ +/*! Rotation 90 degree counter clockwise of self picture, only in RGB mode. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/ +/* For RGB 565 format the line length must be a multiple of 2. There are no restrictions for RGB 888/666.*/ +/* 1: enabled */ +/* 0: disabled */ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path. In rotation mode only 4-beat bursts are supported for self-path.*/ +#define MRV_MI_ROT +#define MRV_MI_ROT_MASK 0x00000040U +#define MRV_MI_ROT_SHIFT 6U +/*! Slice: v_flip:*/ +/*! Vertical flipping of self picture. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/ +/* 1: enabled */ +/* 0: disabled */ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_V_FLIP +#define MRV_MI_V_FLIP_MASK 0x00000020U +#define MRV_MI_V_FLIP_SHIFT 5U +/*! Slice: h_flip:*/ +/*! Horizontal flipping of self picture. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/ +/* 1: enabled */ +/* 0: disabled */ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_H_FLIP +#define MRV_MI_H_FLIP_MASK 0x00000010U +#define MRV_MI_H_FLIP_SHIFT 4U +/*! Slice: path_enable:*/ +/*! Enables data pathes of MI according to the following table:*/ + /**/ +/* 0000: disabled, no data is transferred */ +/* 0001: YUV data output, mainpath only (mp_enable only)*/ +/* 0010: self-path only, output data format depending on other settings (sp_enable only)*/ +/* 0011: YUV data output in mainpath and self-path image data active */ +/* 0100: JPEG data output, mainpath only (jpeg_enable only)*/ +/* 0101: not allowed */ +/* 0110: JPEG data output in mainpath and self-path image data active */ +/* 0111: not allowed */ +/* 1000: RAW data output, mainpath only (raw_enable only)*/ +/* 1001: defect pixel data on self-path, image data on mainpath */ +/* 1010: defect pixel data on mainpath, image data on self-path */ +/* 1011: not allowed */ +/* 1100: defect pixel data on self-path, JPEG data on mainpath */ +/* 1101: defect pixel data on mainpath only */ +/* 1110: defect pixel data on self-path only */ +/* 1111: defect pixel data on self-path, RAW data on mainpath */ + /**/ +/* Programmed value becomes effective (visible in shadow register) after a soft reset, a forced software update or an automatic config update. Affects MI_IN and MI_OUT module.*/ +#define MRV_MI_PATH_ENABLE +#define MRV_MI_PATH_ENABLE_MASK 0x0000000FU +#define MRV_MI_PATH_ENABLE_SHIFT 0U +/*! Register: mi_init: Control register for address init and skip function (0x00000004)*/ +/*! Slice: mi_output_format */ +#define MRV_MI_MP_OUTPUT_FORMAT +#define MRV_MI_MP_OUTPUT_FORMAT_MASK 0x000001E0U +#define MRV_MI_MP_OUTPUT_FORMAT_SHIFT 5U +/*! Slice: mi_cfg_upd:*/ +/*! Forced configuration update. Leads to an immediate update of the shadow registers.*/ +/* Depending on the two init enable bits in the MI_CTRL register (init_offset_en and init_base_en) the offset counter, base address and buffer size shadow registers are also updated.*/ +#define MRV_MI_MI_CFG_UPD +#define MRV_MI_MI_CFG_UPD_MASK 0x00000010U +#define MRV_MI_MI_CFG_UPD_SHIFT 4U +/*! Slice: mi_skip:*/ +/*! Skip of current or next starting main picture:*/ +/* Aborts writing of main picture image data of the current frame to RAM (after the current burst transmission has been completed). Further main picture data up to the end of the current frame are discarded.*/ + /**/ +/* No further makroblock line interrupt (mblk_line), no wrap around interrupt for main picture (wrap_mp_y/cb/cr) and no fill level interrupt (fill_mp_y) are generated.*/ + /**/ +/* Skip does not affect the generation of the main path frame end interrupt (mp_frame_end).*/ +/* Skip does not affect the processing of self picture and its corresponding interrupts namely the self path frame end interrupt (sp_frame_end).*/ + /**/ +/* The byte counter (register MI_BYTE_CNT) is not affected. It produces the correct number of JPEG or RAW data bytes at the end of the current (skipped) frame.*/ + /**/ +/* After a skip has been performed the offset counter for the main picture at the start of the following frame are set depending on the bit init_offset_en in register MI_CTRL:*/ + /**/ +/* - Skip restart mode (init_offset_en = 0)*/ +/* The offset counters of the main picture are restarted at the old start values of the previous skipped frame.*/ + /**/ +/* - Skip init mode (init_offset_en = 1)*/ +/* The offset counters of the main picture are initialized with the register contents of the offset counter init registers without any additional forced software update or automatic config update.*/ +#define MRV_MI_MI_SKIP +#define MRV_MI_MI_SKIP_MASK 0x00000004U +#define MRV_MI_MI_SKIP_SHIFT 2U +/*! Register: mi_mp_y_base_ad_init: Base address for main picture Y component, JPEG or raw data (0x00000008)*/ +/*! Slice: mp_y_base_ad_init:*/ +/*! Base address of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +#ifdef ISP_MP_34BIT +#define MRV_MI_MP_Y_BASE_AD_INIT +#define MRV_MI_MP_Y_BASE_AD_INIT_MASK 0xFFFFFFFEU +#define MRV_MI_MP_Y_BASE_AD_INIT_SHIFT 1U +#else +#define MRV_MI_MP_Y_BASE_AD_INIT +#define MRV_MI_MP_Y_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_MP_Y_BASE_AD_INIT_SHIFT 3U +#endif +/*! Register: mi_mp_y_size_init: Size of main picture Y component, JPEG or raw data (0x0000000c)*/ +/*! Slice: mp_y_size_init:*/ +/*! Size of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +#define MRV_MI_MP_Y_SIZE_INIT +#define MRV_MI_MP_Y_SIZE_INIT_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_SIZE_INIT_SHIFT 3U +/*! Register: mi_mp_y_offs_cnt_init: Offset counter init value for main picture Y, JPEG or raw data (0x00000010)*/ +/*! Slice: mp_y_offs_cnt_init:*/ +/*! Offset counter init value of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +#define MRV_MI_MP_Y_OFFS_CNT_INIT +#define MRV_MI_MP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_mp_y_offs_cnt_start: Offset counter start value for main picture Y, JPEG or raw data (0x00000014)*/ +/*! Slice: mp_y_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (main picture Y component, JPEG or raw data). Updated at frame end.*/ +/* Note: A soft reset resets the contents to the reset value.*/ +#define MRV_MI_MP_Y_OFFS_CNT_START +#define MRV_MI_MP_Y_OFFS_CNT_START_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_mp_y_irq_offs_init: Fill level interrupt offset value for main picture Y, JPEG or raw data (0x00000018)*/ +/*! Slice: mp_y_irq_offs_init:*/ +/*! Reaching this programmed value by the current offset counter for addressing main picture Y component, JPEG or raw data leads to generation of fill level interrupt fill_mp_y.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +#define MRV_MI_MP_Y_IRQ_OFFS_INIT +#define MRV_MI_MP_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: mi_mp_cb_base_ad_init: Base address for main picture Cb component ring buffer (0x0000001c)*/ +/*! Slice: mp_cb_base_ad_init:*/ +/*! Base address of main picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#ifdef ISP_MP_34BIT +#define MRV_MI_MP_CB_BASE_AD_INIT +#define MRV_MI_MP_CB_BASE_AD_INIT_MASK 0xFFFFFFFEU +#define MRV_MI_MP_CB_BASE_AD_INIT_SHIFT 1U +#else +#define MRV_MI_MP_CB_BASE_AD_INIT +#define MRV_MI_MP_CB_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CB_BASE_AD_INIT_SHIFT 3U +#endif +/*! Register: mi_mp_cb_size_init: Size of main picture Cb component ring buffer (0x00000020)*/ +/*! Slice: mp_cb_size_init:*/ +/*! Size of main picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_MP_CB_SIZE_INIT +#define MRV_MI_MP_CB_SIZE_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CB_SIZE_INIT_SHIFT 3U +/*! Register: mi_mp_cb_offs_cnt_init: Offset counter init value for main picture Cb component ring buffer (0x00000024)*/ +/*! Slice: mp_cb_offs_cnt_init:*/ +/*! Offset counter init value of main picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect. Check exceptional handling in skip modes.*/ +#define MRV_MI_MP_CB_OFFS_CNT_INIT +#define MRV_MI_MP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CB_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_mp_cb_offs_cnt_start: Offset counter start value for main picture Cb component ring buffer (0x00000028)*/ +/*! Slice: mp_cb_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (main picture Cb component). Updated at frame end.*/ +#define MRV_MI_MP_CB_OFFS_CNT_START +#define MRV_MI_MP_CB_OFFS_CNT_START_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CB_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_mp_cr_base_ad_init: Base address for main picture Cr component ring buffer (0x0000002c)*/ +/*! Slice: mp_cr_base_ad_init:*/ +/*! Base address of main picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#ifdef ISP_MP_34BIT +#define MRV_MI_MP_CR_BASE_AD_INIT +#define MRV_MI_MP_CR_BASE_AD_INIT_MASK 0xFFFFFFFEU +#define MRV_MI_MP_CR_BASE_AD_INIT_SHIFT 1U +#else +#define MRV_MI_MP_CR_BASE_AD_INIT +#define MRV_MI_MP_CR_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CR_BASE_AD_INIT_SHIFT 3U +#endif +/*! Register: mi_mp_cr_size_init: Size of main picture Cr component ring buffer (0x00000030)*/ +/*! Slice: mp_cr_size_init:*/ +/*! Size of main picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_MP_CR_SIZE_INIT +#define MRV_MI_MP_CR_SIZE_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CR_SIZE_INIT_SHIFT 3U +/*! Register: mi_mp_cr_offs_cnt_init: Offset counter init value for main picture Cr component ring buffer (0x00000034)*/ +/*! Slice: mp_cr_offs_cnt_init:*/ +/*! Offset counter init value of main picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect. Check exceptional handling in skip modes.*/ +#define MRV_MI_MP_CR_OFFS_CNT_INIT +#define MRV_MI_MP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CR_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_mp_cr_offs_cnt_start: Offset counter start value for main picture Cr component ring buffer (0x00000038)*/ +/*! Slice: mp_cr_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (main picture Cr component). Updated at frame end.*/ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_MP_CR_OFFS_CNT_START +#define MRV_MI_MP_CR_OFFS_CNT_START_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CR_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_sp_y_base_ad_init: Base address for self picture Y component ring buffer (0x0000003c)*/ +/*! Slice: sp_y_base_ad_init:*/ +/*! Base address of self picture Y component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_Y_BASE_AD_INIT +#define MRV_MI_SP_Y_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_SP_Y_BASE_AD_INIT_SHIFT 3U +/*! Register: mi_sp_y_size_init: Size of self picture Y component ring buffer (0x00000040)*/ +/*! Slice: sp_y_size_init:*/ +/*! Size of self picture Y component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_Y_SIZE_INIT +#define MRV_MI_SP_Y_SIZE_INIT_MASK 0x1FFFFFF8U +#define MRV_MI_SP_Y_SIZE_INIT_SHIFT 3U +/*! Register: mi_sp_y_offs_cnt_init: Offset counter init value for self picture Y component ring buffer (0x00000044)*/ +/*! Slice: sp_y_offs_cnt_init:*/ +/*! Offset counter init value of self picture Y component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_Y_OFFS_CNT_INIT +#define MRV_MI_SP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define MRV_MI_SP_Y_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_sp_y_offs_cnt_start: Offset counter start value for self picture Y component ring buffer (0x00000048)*/ +/*! Slice: sp_y_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (self picture Y component). Updated at frame end.*/ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_SP_Y_OFFS_CNT_START +#define MRV_MI_SP_Y_OFFS_CNT_START_MASK 0x1FFFFFF8U +#define MRV_MI_SP_Y_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_sp_y_llength: Line length of self picture Y component (0x0000004c)*/ +/*! Slice: sp_y_llength:*/ +/*! Line length of self picture Y component or RGB picture in pixel, also known as line stride.*/ +/* If no line stride is used, line length must match image width.*/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/ +/* In planar mode the line length of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the line length of the Cb and Cr component is assumed the same size.*/ +/* Note: Line length always refers to the line length of the output image. This is particularly important when rotating.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_SP_Y_LLENGTH +#define MRV_MI_SP_Y_LLENGTH_MASK 0x00007FFFU +#define MRV_MI_SP_Y_LLENGTH_SHIFT 0U +/*! Register: mi_sp_cb_base_ad_init: Base address for self picture Cb component ring buffer (0x00000050)*/ +/*! Slice: sp_cb_base_ad_init:*/ +/*! Base address of self picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CB_BASE_AD_INIT +#define MRV_MI_SP_CB_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CB_BASE_AD_INIT_SHIFT 3U +/*! Register: mi_sp_cb_size_init: Size of self picture Cb component ring buffer (0x00000054)*/ +/*! Slice: sp_cb_size_init:*/ +/*! Size of self picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CB_SIZE_INIT +#define MRV_MI_SP_CB_SIZE_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CB_SIZE_INIT_SHIFT 3U +/*! Register: mi_sp_cb_offs_cnt_init: Offset counter init value for self picture Cb component ring buffer (0x00000058)*/ +/*! Slice: sp_cb_offs_cnt_init:*/ +/*! Offset counter init value of self picture Cb component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CB_OFFS_CNT_INIT +#define MRV_MI_SP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CB_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_sp_cb_offs_cnt_start: Offset counter start value for self picture Cb component ring buffer (0x0000005c)*/ +/*! Slice: sp_cb_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (self picture Cb component). Updated at frame end.*/ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_SP_CB_OFFS_CNT_START +#define MRV_MI_SP_CB_OFFS_CNT_START_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CB_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_sp_cr_base_ad_init: Base address for self picture Cr component ring buffer (0x00000060)*/ +/*! Slice: sp_cr_base_ad_init:*/ +/*! Base address of self picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CR_BASE_AD_INIT +#define MRV_MI_SP_CR_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CR_BASE_AD_INIT_SHIFT 3U +/*! Register: mi_sp_cr_size_init: Size of self picture Cr component ring buffer (0x00000064)*/ +/*! Slice: sp_cr_size_init:*/ +/*! Size of self picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CR_SIZE_INIT +#define MRV_MI_SP_CR_SIZE_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CR_SIZE_INIT_SHIFT 3U +/*! Register: mi_sp_cr_offs_cnt_init: Offset counter init value for self picture Cr component ring buffer (0x00000068)*/ +/*! Slice: sp_cr_offs_cnt_init:*/ +/*! Offset counter init value of self picture Cr component ring buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CR_OFFS_CNT_INIT +#define MRV_MI_SP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CR_OFFS_CNT_INIT_SHIFT 3U +/*! Register: mi_sp_cr_offs_cnt_start: Offset counter start value for self picture Cr component ring buffer (0x0000006c)*/ +/*! Slice: sp_cr_offs_cnt_start:*/ +/*! Offset counter value which points to the start address of the previously processed picture (self picture Cr component). Updated at frame end.*/ +#define MRV_MI_SP_CR_OFFS_CNT_START +#define MRV_MI_SP_CR_OFFS_CNT_START_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CR_OFFS_CNT_START_SHIFT 3U +/*! Register: mi_byte_cnt: Counter value of JPEG or RAW data bytes (0x00000070)*/ +/*! Slice: byte_cnt:*/ +/*! Counter value specifies the number of JPEG or RAW data bytes of the last transmitted frame. Updated at frame end.*/ +/* A soft reset will set the byte counter to zero.*/ +#define MRV_MI_BYTE_CNT +#define MRV_MI_BYTE_CNT_MASK 0x0FFFFFFFU +#define MRV_MI_BYTE_CNT_SHIFT 0U +/*! Register: mi_ctrl_shd: global control internal shadow register (0x00000074)*/ +/*! Slice: path_enable_out:*/ +/*! path_enable shadow register for module MI_OUT (former raw_enable_out, jpeg_enable_out, sp_enable_out, mp_enable_out)*/ +#define MRV_MI_PATH_ENABLE_OUT +#define MRV_MI_PATH_ENABLE_OUT_MASK 0x000F0000U +#define MRV_MI_PATH_ENABLE_OUT_SHIFT 16U +/*! Slice: path_enable_in:*/ +/*! path_enable shadow register for module MI_IN (former raw_enable_in, jpeg_enable_in, sp_enable_in, mp_enable_in)*/ +#define MRV_MI_PATH_ENABLE_IN +#define MRV_MI_PATH_ENABLE_IN_MASK 0x0000000FU +#define MRV_MI_PATH_ENABLE_IN_SHIFT 0U +/*! Register: mi_mp_y_base_ad_shd: Base address shadow register for main picture Y component, JPEG or raw data ring buffer (0x00000078)*/ +/*! Slice: mp_y_base_ad:*/ +/*! Base address of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/ +#define MRV_MI_MP_Y_BASE_AD +#define MRV_MI_MP_Y_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_MP_Y_BASE_AD_SHIFT 3U +/*! Register: mi_mp_y_size_shd: Size shadow register of main picture Y component, JPEG or raw data (0x0000007c)*/ +/*! Slice: mp_y_size:*/ +/*! Size of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/ +#define MRV_MI_MP_Y_SIZE +#define MRV_MI_MP_Y_SIZE_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_SIZE_SHIFT 3U +/*! Register: mi_mp_y_offs_cnt_shd: Current offset counter of main picture Y component, JPEG or raw data ring buffer (0x00000080)*/ +/*! Slice: mp_y_offs_cnt:*/ +/*! Current offset counter of main picture Y component, JPEG or raw data ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_MP_Y_OFFS_CNT +#define MRV_MI_MP_Y_OFFS_CNT_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_OFFS_CNT_SHIFT 3U +/*! Register: mi_mp_y_irq_offs_shd: Shadow register of fill level interrupt offset value for main picture Y component, JPEG or raw data (0x00000084)*/ +/*! Slice: mp_y_irq_offs:*/ +/*! Reaching this offset value by the current offset counter for addressing main picture Y component, JPEG or raw data leads to generation of fill level interrupt fill_mp_y.*/ +#define MRV_MI_MP_Y_IRQ_OFFS +#define MRV_MI_MP_Y_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MRV_MI_MP_Y_IRQ_OFFS_SHIFT 3U +/*! Register: mi_mp_cb_base_ad_shd: Base address shadow register for main picture Cb component ring buffer (0x00000088)*/ +/*! Slice: mp_cb_base_ad:*/ +/*! Base address of main picture Cb component ring buffer.*/ +#define MRV_MI_MP_CB_BASE_AD +#define MRV_MI_MP_CB_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CB_BASE_AD_SHIFT 3U +/*! Register: mi_mp_cb_size_shd: Size shadow register of main picture Cb component ring buffer (0x0000008c)*/ +/*! Slice: mp_cb_size:*/ +/*! Size of main picture Cb component ring buffer.*/ +#define MRV_MI_MP_CB_SIZE +#define MRV_MI_MP_CB_SIZE_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CB_SIZE_SHIFT 3U +/*! Register: mi_mp_cb_offs_cnt_shd: Current offset counter of main picture Cb component ring buffer (0x00000090)*/ +/*! Slice: mp_cb_offs_cnt:*/ +/*! Current offset counter of main picture Cb component ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_MP_CB_OFFS_CNT +#define MRV_MI_MP_CB_OFFS_CNT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CB_OFFS_CNT_SHIFT 3U +/*! Register: mi_mp_cr_base_ad_shd: Base address shadow register for main picture Cr component ring buffer (0x00000094)*/ +/*! Slice: mp_cr_base_ad:*/ +/*! Base address of main picture Cr component ring buffer.*/ +#define MRV_MI_MP_CR_BASE_AD +#define MRV_MI_MP_CR_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CR_BASE_AD_SHIFT 3U +/*! Register: mi_mp_cr_size_shd: Size shadow register of main picture Cr component ring buffer (0x00000098)*/ +/*! Slice: mp_cr_size:*/ +/*! Size of main picture Cr component ring buffer.*/ +#define MRV_MI_MP_CR_SIZE +#define MRV_MI_MP_CR_SIZE_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CR_SIZE_SHIFT 3U +/*! Register: mi_mp_cr_offs_cnt_shd: Current offset counter of main picture Cr component ring buffer (0x0000009c)*/ +/*! Slice: mp_cr_offs_cnt:*/ +/*! Current offset counter of main picture Cr component ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_MP_CR_OFFS_CNT +#define MRV_MI_MP_CR_OFFS_CNT_MASK 0x0FFFFFF8U +#define MRV_MI_MP_CR_OFFS_CNT_SHIFT 3U +/*! Register: mi_sp_y_base_ad_shd: Base address shadow register for self picture Y component ring buffer (0x000000a0)*/ +/*! Slice: sp_y_base_ad:*/ +/*! Base address of self picture Y component ring buffer.*/ +#define MRV_MI_SP_Y_BASE_AD +#define MRV_MI_SP_Y_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_SP_Y_BASE_AD_SHIFT 3U +/*! Register: mi_sp_y_size_shd: Size shadow register of self picture Y component ring buffer (0x000000a4)*/ +/*! Slice: sp_y_size:*/ +/*! Size of self picture Y component ring buffer.*/ +#define MRV_MI_SP_Y_SIZE +#define MRV_MI_SP_Y_SIZE_MASK 0x1FFFFFF8U +#define MRV_MI_SP_Y_SIZE_SHIFT 3U +/*! Register: mi_sp_y_offs_cnt_shd: Current offset counter of self picture Y component ring buffer (0x000000a8)*/ +/*! Slice: sp_y_offs_cnt:*/ +/*! Current offset counter of self picture Y component ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_SP_Y_OFFS_CNT +#define MRV_MI_SP_Y_OFFS_CNT_MASK 0x1FFFFFF8U +#define MRV_MI_SP_Y_OFFS_CNT_SHIFT 3U +/*! Register: mi_sp_cb_base_ad_shd: Base address shadow register for self picture Cb component ring buffer (0x000000b0)*/ +/*! Slice: sp_cb_base_ad:*/ +/*! Base address of self picture Cb component ring buffer.*/ +#define MRV_MI_SP_CB_BASE_AD +#define MRV_MI_SP_CB_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CB_BASE_AD_SHIFT 3U +/*! Register: mi_sp_cb_size_shd: Size shadow register of self picture Cb component ring buffer (0x000000b4)*/ +/*! Slice: sp_cb_size:*/ +/*! Size of self picture Cb component ring buffer.*/ +#define MRV_MI_SP_CB_SIZE +#define MRV_MI_SP_CB_SIZE_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CB_SIZE_SHIFT 3U +/*! Register: mi_sp_cb_offs_cnt_shd: Current offset counter of self picture Cb component ring buffer (0x000000b8)*/ +/*! Slice: sp_cb_offs_cnt:*/ +/*! Current offset counter of self picture Cb component ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_SP_CB_OFFS_CNT +#define MRV_MI_SP_CB_OFFS_CNT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CB_OFFS_CNT_SHIFT 3U +/*! Register: mi_sp_cr_base_ad_shd: Base address shadow register for self picture Cr component ring buffer (0x000000bc)*/ +/*! Slice: sp_cr_base_ad:*/ +/*! Base address of self picture Cr component ring buffer.*/ +#define MRV_MI_SP_CR_BASE_AD +#define MRV_MI_SP_CR_BASE_AD_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CR_BASE_AD_SHIFT 3U +/*! Register: mi_sp_cr_size_shd: Size shadow register of self picture Cr component ring buffer (0x000000c0)*/ +/*! Slice: sp_cr_size:*/ +/*! Size of self picture Cr component ring buffer.*/ +#define MRV_MI_SP_CR_SIZE +#define MRV_MI_SP_CR_SIZE_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CR_SIZE_SHIFT 3U +/*! Register: mi_sp_cr_offs_cnt_shd: Current offset counter of self picture Cr component ring buffer (0x000000c4)*/ +/*! Slice: sp_cr_offs_cnt:*/ +/*! Current offset counter of self picture Cr component ring buffer for address generation */ +/* Note: Soft reset will reset the contents to reset value.*/ +#define MRV_MI_SP_CR_OFFS_CNT +#define MRV_MI_SP_CR_OFFS_CNT_MASK 0x0FFFFFF8U +#define MRV_MI_SP_CR_OFFS_CNT_SHIFT 3U +/*! Register: mi_dma_y_pic_start_ad: Y component image start address (0x000000c8)*/ +/*! Slice: dma_y_pic_start_ad:*/ +/*! Image start address of the y component */ +/* Note: Must be multiple of 4 in interleaved mode.*/ +#define MRV_MI_DMA_Y_PIC_START_AD +#define MRV_MI_DMA_Y_PIC_START_AD_MASK 0xFFFFFFFFU +#define MRV_MI_DMA_Y_PIC_START_AD_SHIFT 0U +/*! Register: mi_dma_y_pic_width: Y component image width (0x000000cc)*/ +/*! Slice: dma_y_pic_width:*/ +/*! Image width of the Y component in pixel.*/ +/* For YCbCr 4:2:x the image width must be a multiple of 2.*/ +/* In planar mode the image width of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the image width of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr image width is used.*/ +#define MRV_MI_DMA_Y_PIC_WIDTH +#define MRV_MI_DMA_Y_PIC_WIDTH_MASK 0x00007FFFU +#define MRV_MI_DMA_Y_PIC_WIDTH_SHIFT 0U +/*! Register: mi_dma_y_llength: Y component original line length (0x000000d0)*/ +/*! Slice: dma_y_llength:*/ +/*! Line length of the Y component of the original image in memory */ +/* For an uncropped image, where lines follow each other without offset (no line stride), line length must match image width.*/ +/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4.*/ +/* In planar mode the line length of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the line length of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr line length is used.*/ +#define MRV_MI_DMA_Y_LLENGTH +#define MRV_MI_DMA_Y_LLENGTH_MASK 0x00007FFFU +#define MRV_MI_DMA_Y_LLENGTH_SHIFT 0U +/*! Register: mi_dma_y_pic_size: Y component image size (0x000000d4)*/ +/*! Slice: dma_y_pic_size:*/ +/*! Image size of the Y component in pixel which has to be the Y line length multiplied by the Y image height (dma_y_llength * dma_y_pic_height).*/ +/* In planar mode the image size of the Cb and Cr component is assumed according to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for 4:4:4. In semi planar mode the image size of the Cb component (which includes Cr) is assumed half for 4:2:0 and the same size for 4:2:2. In interleave mode no Cb/Cr image size is used.*/ +#define MRV_MI_DMA_Y_PIC_SIZE +#define MRV_MI_DMA_Y_PIC_SIZE_MASK 0x0FFFFFFFU +#define MRV_MI_DMA_Y_PIC_SIZE_SHIFT 0U +/*! Register: mi_dma_cb_pic_start_ad: Cb component image start address (0x000000d8)*/ +/*! Slice: dma_cb_pic_start_ad:*/ +/*! Image start address of the Cb component */ +/* Note: Must be multiple of 2 in semi-planar mode.*/ +#define MRV_MI_DMA_CB_PIC_START_AD +#define MRV_MI_DMA_CB_PIC_START_AD_MASK 0xFFFFFFFFU +#define MRV_MI_DMA_CB_PIC_START_AD_SHIFT 0U +/*! Register: mi_dma_cr_pic_start_ad: Cr component image start address (0x000000e8)*/ +/*! Slice: dma_cr_pic_start_ad:*/ +/*! Image start address of the Cr component */ +#define MRV_MI_DMA_CR_PIC_START_AD +#define MRV_MI_DMA_CR_PIC_START_AD_MASK 0xFFFFFFFFU +#define MRV_MI_DMA_CR_PIC_START_AD_SHIFT 0U +/*! Register: mi_imsc: Interrupt Mask (‘1’: interrupt active, ‘0’: interrupt masked) (0x000000f8)*/ +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Slice mp_handshk_int:*/ +/*! Mask bit for mp handshake interrupt */ +#define MRV_MI_MP_HANDSHK_INT +#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U +#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U +#endif +/*! Slice: dma_ready:*/ +/*! Mask bit for dma ready interrupt */ +#define MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0x00000800U +#define MRV_MI_DMA_READY_SHIFT 11U +/*! Slice: wrap_sp_cr:*/ +/*! Mask bit for self picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U +#define MRV_MI_WRAP_SP_CR_SHIFT 9U +/*! Slice: wrap_sp_cb:*/ +/*! Mask bit for self picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U +#define MRV_MI_WRAP_SP_CB_SHIFT 8U +/*! Slice: wrap_sp_y:*/ +/*! Mask bit for self picture Y address wrap interrupt */ +#define MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U +#define MRV_MI_WRAP_SP_Y_SHIFT 7U +/*! Slice: wrap_mp_cr:*/ +/*! Mask bit for main picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U +#define MRV_MI_WRAP_MP_CR_SHIFT 6U +/*! Slice: wrap_mp_cb:*/ +/*! Mask bit for main picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U +#define MRV_MI_WRAP_MP_CB_SHIFT 5U +/*! Slice: wrap_mp_y:*/ +/*! Mask bit for main picture Y address wrap interrupt */ +#define MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U +#define MRV_MI_WRAP_MP_Y_SHIFT 4U +/*! Slice: fill_mp_y:*/ +/*! Mask bit for fill level interrupt of main picture Y, JPEG or raw data */ +#define MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0x00000008U +#define MRV_MI_FILL_MP_Y_SHIFT 3U +/*! Slice: mblk_line:*/ +/*! Mask bit for makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM)*/ +#define MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0x00000004U +#define MRV_MI_MBLK_LINE_SHIFT 2U +/*! Slice: sp_frame_end:*/ +/*! Mask self picture end of frame interrupt */ +#define MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0x00000002U +#define MRV_MI_SP_FRAME_END_SHIFT 1U +/*! Slice: mp_frame_end:*/ +/*! Mask main picture end of frame interrupt */ +#define MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0x00000001U +#define MRV_MI_MP_FRAME_END_SHIFT 0U +/*! Register: mi_ris: Raw Interrupt Status (0x000000fc)*/ +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Slice mp_handshk_int:*/ +/*! Raw status of mp handshake interrupt */ +#define MRV_MI_MP_HANDSHK_INT +#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U +#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U +#endif +/*! Slice: dma_ready:*/ +/*! Raw status of dma ready interrupt */ +#define MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0x00000800U +#define MRV_MI_DMA_READY_SHIFT 11U +/*! Slice: wrap_sp_cr:*/ +/*! Raw status of self picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U +#define MRV_MI_WRAP_SP_CR_SHIFT 9U +/*! Slice: wrap_sp_cb:*/ +/*! Raw status of self picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U +#define MRV_MI_WRAP_SP_CB_SHIFT 8U +/*! Slice: wrap_sp_y:*/ +/*! Raw status of self picture Y address wrap interrupt */ +#define MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U +#define MRV_MI_WRAP_SP_Y_SHIFT 7U +/*! Slice: wrap_mp_cr:*/ +/*! Raw status of main picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U +#define MRV_MI_WRAP_MP_CR_SHIFT 6U +/*! Slice: wrap_mp_cb:*/ +/*! Raw status of main picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U +#define MRV_MI_WRAP_MP_CB_SHIFT 5U +/*! Slice: wrap_mp_y:*/ +/*! Raw status of main picture Y address wrap interrupt */ +#define MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U +#define MRV_MI_WRAP_MP_Y_SHIFT 4U +/*! Slice: fill_mp_y:*/ +/*! Raw status of fill level interrupt of main picture Y, JPEG or raw data */ +#define MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0x00000008U +#define MRV_MI_FILL_MP_Y_SHIFT 3U +/*! Slice: mblk_line:*/ +/*! Raw status of makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM, valid only for planar and semi-planar mode)*/ +#define MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0x00000004U +#define MRV_MI_MBLK_LINE_SHIFT 2U +/*! Slice: sp_frame_end:*/ +/*! Raw status of self picture end of frame interrupt */ +#define MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0x00000002U +#define MRV_MI_SP_FRAME_END_SHIFT 1U +/*! Slice: mp_frame_end:*/ +/*! Raw status of main picture end of frame interrupt */ +#define MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0x00000001U +#define MRV_MI_MP_FRAME_END_SHIFT 0U +#ifdef ISP_MI_BP +/*! Slice: bp_frame_end:*/ +/*! Raw status of bp picture end of frame interrupt */ +#define MRV_MI_BP_FRAME_END +#define MRV_MI_BP_FRAME_END_MASK 0x00004000U +#define MRV_MI_BP_FRAME_END_SHIFT 14U +/*! Slice: bp_wr_raw_aligned:*/ +#define BP_WR_RAW_ALIGNED +#define BP_WR_RAW_ALIGNED_MASK 0x000000c0U +#define BP_WR_RAW_ALIGNED_SHIFT 6U +/*! Slice: bp_wr_byte_swap:*/ +#define BP_WR_BYTE_SWAP +#define BP_WR_BYTE_SWAP_MASK 0x00007000U +#define BP_WR_BYTE_SWAP_SHIFT 12U +/*! Slice: bp_fill_r */ +#define MRV_MI_BP_FILL_R +#define MRV_MI_BP_FILL_R_MASK 0x00008000U +#define MRV_MI_BP_FILL_R_SHIFT 15U +/*! Slice: wrap_bp_r:*/ +#define MRV_MI_BP_WRAP_R +#define MRV_MI_BP_WRAP_R_MASK 0x00010000U +#define MRV_MI_BP_WRAP_R_SHIFT 16U +/*! Slice: wrap_bp_r:*/ +#define MRV_MI_BP_WRAP_R +#define MRV_MI_BP_WRAP_R_MASK 0x00010000U +#define MRV_MI_BP_WRAP_R_SHIFT 16U +/*! Slice: wrap_bp_gr:*/ +#define MRV_MI_BP_WRAP_GR +#define MRV_MI_BP_WRAP_GR_MASK 0x00020000U +#define MRV_MI_BP_WRAP_GR_SHIFT 17U +/*! Slice: wrap_bp_gb:*/ +#define MRV_MI_BP_WRAP_GB +#define MRV_MI_BP_WRAP_GB_MASK 0x00040000U +#define MRV_MI_BP_WRAP_GB_SHIFT 18U +/*! Slice: wrap_bp_b:*/ +#define MRV_MI_BP_WRAP_B +#define MRV_MI_BP_WRAP_B_MASK 0x00080000U +#define MRV_MI_BP_WRAP_B_SHIFT 19U +/*! Register: miv1_bp_r_base_ad_init (0x000015d8)*/ +/*! Slice: bp_r_base_ad_init:*/ +#define BP_R_BASE_AD_INIT +#define BP_R_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define BP_R_BASE_AD_INIT_SHIFT 3U +/*! Register: miv1_bp_gr_base_ad_init (0x000015dc)*/ +/*! Slice: bp_gr_base_ad_init:*/ +#define BP_GR_BASE_AD_INIT +#define BP_GR_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define BP_GR_BASE_AD_INIT_SHIFT 3U +/*! Register: miv1_bp_gb_base_ad_init (0x000015e0)*/ +/*! Slice: bp_gb_base_ad_init:*/ +#define BP_GB_BASE_AD_INIT +#define BP_GB_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define BP_GB_BASE_AD_INIT_SHIFT 3U +/*! Register: miv1_bp_b_base_ad_init (0x000015e4)*/ +/*! Slice: bp_b_base_ad_init:*/ +#define BP_B_BASE_AD_INIT +#define BP_B_BASE_AD_INIT_MASK 0xFFFFFFF8U +#define BP_B_BASE_AD_INIT_SHIFT 3U +/*! Register: miv1_bp_r_offs_cnt_init (0x000015c8)*/ +/*! Slice: bp_r_offs_cnt_init:*/ +#define BP_R_OFFS_CNT_INIT +#define BP_R_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define BP_R_OFFS_CNT_INIT_SHIFT 3U +/*! Register: miv1_bp_gr_offs_cnt_init (0x000015cc)*/ +/*! Slice: bp_gr_offs_cnt_init:*/ +#define BP_GR_OFFS_CNT_INIT +#define BP_GR_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define BP_GR_OFFS_CNT_INIT_SHIFT 3U +/*! Register: miv1_bp_gb_offs_cnt_init (0x000015d0)*/ +/*! Slice: bp_gb_offs_cnt_init:*/ +#define BP_GB_OFFS_CNT_INIT +#define BP_GB_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define BP_GB_OFFS_CNT_INIT_SHIFT 3U +/*! Register: miv1_bp_b_offs_cnt_init (0x000015d4)*/ +/*! Slice: bp_b_offs_cnt_init:*/ +#define BP_B_OFFS_CNT_INIT +#define BP_B_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define BP_B_OFFS_CNT_INIT_SHIFT 3U +/*! Register: miv1_bp_wr_offs_cnt_init (0x000015A4)*/ +/*! Slice: mi_bp_wr_offs_cnt_init:*/ +#define BP_PIC_WR_OFFS_CNT_INIT +#define BP_PIC_WR_OFFS_CNT_INIT_MASK 0x1FFFFFF8U +#define BP_PIC_WR_OFFS_CNT_INIT_SHIFT 3U +/*! Register: miv1_bp_wr_irq_offs_init (0x000015AC)*/ +/*! Slice: mi_bp_wr_irq_offs_init:*/ +#define BP_PIC_IRQ_OFFS_INIT +#define BP_PIC_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define BP_PIC_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv1_bp_wr_size_init (0x000015B4)*/ +/*! Slice: mi_bp_wr_size_init:*/ +#define BP_PIC_WR_SIZE_INIT +#define BP_PIC_WR_SIZE_INIT_MASK 0x1FFFFFF8U +#define BP_PIC_WR_SIZE_INIT_SHIFT 3U +/*! Register: miv1_bp_pic_width (0x000015bc)*/ +/*! Slice: bp_pic_width:*/ +#define BP_PIC_WIDTH +#define BP_PIC_WIDTH_MASK 0x4FFFU +#define BP_PIC_WIDTH_SHIFT 0U +/*! Register: miv1_bp_pic_height (0x000015c0)*/ +/*! Slice: bp_pic_height:*/ +#define BP_PIC_HEIGHT +#define BP_PIC_HEIGHT_MASK 0x4FFFU +#define BP_PIC_HEIGHT_SHIFT 0U +/*! Register: miv1_bp_pic_size (0x000015c4)*/ +/*! Slice: bp_pic_size:*/ +#define BP_PIC_SIZE +#define BP_PIC_SIZE_MASK 0x1FFFFFFU +#define BP_PIC_SIZE_SHIFT 0U +#endif +/*! Register: mi_mis: Masked Interrupt Status (0x00000100)*/ +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Slice mp_handshk_int:*/ +/*! Masked status for mp handshake interrupt */ +#define MRV_MI_MP_HANDSHK_INT +#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U +#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U +#endif +/*! Slice: dma_ready:*/ +/*! Masked status of dma ready interrupt */ +#define MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0x00000800U +#define MRV_MI_DMA_READY_SHIFT 11U +/*! Slice: wrap_sp_cr:*/ +/*! Masked status of self picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U +#define MRV_MI_WRAP_SP_CR_SHIFT 9U +/*! Slice: wrap_sp_cb:*/ +/*! Masked status of self picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U +#define MRV_MI_WRAP_SP_CB_SHIFT 8U +/*! Slice: wrap_sp_y:*/ +/*! Masked status of self picture Y address wrap interrupt */ +#define MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U +#define MRV_MI_WRAP_SP_Y_SHIFT 7U +/*! Slice: wrap_mp_cr:*/ +/*! Masked status of main picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U +#define MRV_MI_WRAP_MP_CR_SHIFT 6U +/*! Slice: wrap_mp_cb:*/ +/*! Masked status of main picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U +#define MRV_MI_WRAP_MP_CB_SHIFT 5U +/*! Slice: wrap_mp_y:*/ +/*! Masked status of main picture Y address wrap interrupt */ +#define MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U +#define MRV_MI_WRAP_MP_Y_SHIFT 4U +/*! Slice: fill_mp_y:*/ +/*! Masked status of fill level interrupt of main picture Y, JPEG or raw data */ +#define MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0x00000008U +#define MRV_MI_FILL_MP_Y_SHIFT 3U +/*! Slice: mblk_line:*/ +/*! Masked status of makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM, valid only for planar and semi-planar mode)*/ +#define MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0x00000004U +#define MRV_MI_MBLK_LINE_SHIFT 2U +/*! Slice: sp_frame_end:*/ +/*! Masked status of self picture end of frame interrupt */ +#define MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0x00000002U +#define MRV_MI_SP_FRAME_END_SHIFT 1U +/*! Slice: mp_frame_end:*/ +/*! Masked status of main picture end of frame interrupt */ +#define MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0x00000001U +#define MRV_MI_MP_FRAME_END_SHIFT 0U +/*! Register: mi_icr: Interrupt Clear Register (0x00000104)*/ +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Slice mp_handshk_int:*/ +/*! clear mp handshake interrupt */ +#define MRV_MI_MP_HANDSHK_INT +#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U +#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U +#endif +/*! Slice: dma_ready:*/ +/*! Clear dma ready interrupt */ +#define MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0x00000800U +#define MRV_MI_DMA_READY_SHIFT 11U +/*! Slice: wrap_sp_cr:*/ +/*! Clear self picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U +#define MRV_MI_WRAP_SP_CR_SHIFT 9U +/*! Slice: wrap_sp_cb:*/ +/*! Clear self picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U +#define MRV_MI_WRAP_SP_CB_SHIFT 8U +/*! Slice: wrap_sp_y:*/ +/*! Clear self picture Y address wrap interrupt */ +#define MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U +#define MRV_MI_WRAP_SP_Y_SHIFT 7U +/*! Slice: wrap_mp_cr:*/ +/*! Clear main picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U +#define MRV_MI_WRAP_MP_CR_SHIFT 6U +/*! Slice: wrap_mp_cb:*/ +/*! Clear main picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U +#define MRV_MI_WRAP_MP_CB_SHIFT 5U +/*! Slice: wrap_mp_y:*/ +/*! Clear main picture Y address wrap interrupt */ +#define MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U +#define MRV_MI_WRAP_MP_Y_SHIFT 4U +/*! Slice: fill_mp_y:*/ +/*! Clear fill level interrupt */ +#define MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0x00000008U +#define MRV_MI_FILL_MP_Y_SHIFT 3U +/*! Slice: mblk_line:*/ +/*! Clear makroblock line interrupt */ +#define MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0x00000004U +#define MRV_MI_MBLK_LINE_SHIFT 2U +/*! Slice: sp_frame_end:*/ +/*! Clear self picture end of frame interrupt */ +#define MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0x00000002U +#define MRV_MI_SP_FRAME_END_SHIFT 1U +/*! Slice: mp_frame_end:*/ +/*! Clear main picture end of frame interrupt */ +#define MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0x00000001U +#define MRV_MI_MP_FRAME_END_SHIFT 0U +/*! Register: mi_isr: Interrupt Set Register (0x00000108)*/ +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Slice mp_handshk_int:*/ +/*! Set mp handshake interrupt */ +#define MRV_MI_MP_HANDSHK_INT +#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U +#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U +#endif +/*! Slice: dma_ready:*/ +/*! Set dma ready interrupt */ +#define MRV_MI_DMA_READY +#define MRV_MI_DMA_READY_MASK 0x00000800U +#define MRV_MI_DMA_READY_SHIFT 11U +/*! Slice: wrap_sp_cr:*/ +/*! Set self picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_SP_CR +#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U +#define MRV_MI_WRAP_SP_CR_SHIFT 9U +/*! Slice: wrap_sp_cb:*/ +/*! Set self picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_SP_CB +#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U +#define MRV_MI_WRAP_SP_CB_SHIFT 8U +/*! Slice: wrap_sp_y:*/ +/*! Set self picture Y address wrap interrupt */ +#define MRV_MI_WRAP_SP_Y +#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U +#define MRV_MI_WRAP_SP_Y_SHIFT 7U +/*! Slice: wrap_mp_cr:*/ +/*! Set main picture Cr address wrap interrupt */ +#define MRV_MI_WRAP_MP_CR +#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U +#define MRV_MI_WRAP_MP_CR_SHIFT 6U +/*! Slice: wrap_mp_cb:*/ +/*! Set main picture Cb address wrap interrupt */ +#define MRV_MI_WRAP_MP_CB +#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U +#define MRV_MI_WRAP_MP_CB_SHIFT 5U +/*! Slice: wrap_mp_y:*/ +/*! Set main picture Y address wrap interrupt */ +#define MRV_MI_WRAP_MP_Y +#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U +#define MRV_MI_WRAP_MP_Y_SHIFT 4U +/*! Slice: fill_mp_y:*/ +/*! Set fill level interrupt */ +#define MRV_MI_FILL_MP_Y +#define MRV_MI_FILL_MP_Y_MASK 0x00000008U +#define MRV_MI_FILL_MP_Y_SHIFT 3U +/*! Slice: mblk_line:*/ +/*! Set makroblock line interrupt */ +#define MRV_MI_MBLK_LINE +#define MRV_MI_MBLK_LINE_MASK 0x00000004U +#define MRV_MI_MBLK_LINE_SHIFT 2U +/*! Slice: sp_frame_end:*/ +/*! Set self picture end of frame interrupt */ +#define MRV_MI_SP_FRAME_END +#define MRV_MI_SP_FRAME_END_MASK 0x00000002U +#define MRV_MI_SP_FRAME_END_SHIFT 1U +/*! Slice: mp_frame_end:*/ +/*! Set main picture end of frame interrupt */ +#define MRV_MI_MP_FRAME_END +#define MRV_MI_MP_FRAME_END_MASK 0x00000001U +#define MRV_MI_MP_FRAME_END_SHIFT 0U +/*! Register: mi_status: MI Status Register (0x0000010c)*/ +/*! Slice: sp_cr_fifo_full:*/ +/*! FIFO full flag of Cr FIFO in self path asserted since last clear */ +#define MRV_MI_SP_CR_FIFO_FULL +#define MRV_MI_SP_CR_FIFO_FULL_MASK 0x00000040U +#define MRV_MI_SP_CR_FIFO_FULL_SHIFT 6U +/*! Slice: sp_cb_fifo_full:*/ +/*! FIFO full flag of Cb FIFO in self path asserted since last clear */ +#define MRV_MI_SP_CB_FIFO_FULL +#define MRV_MI_SP_CB_FIFO_FULL_MASK 0x00000020U +#define MRV_MI_SP_CB_FIFO_FULL_SHIFT 5U +/*! Slice: sp_y_fifo_full:*/ +/*! FIFO full flag of Y FIFO in self path asserted since last clear */ +#define MRV_MI_SP_Y_FIFO_FULL +#define MRV_MI_SP_Y_FIFO_FULL_MASK 0x00000010U +#define MRV_MI_SP_Y_FIFO_FULL_SHIFT 4U +/*! Slice: mp_cr_fifo_full:*/ +/*! FIFO full flag of Cr FIFO in main path asserted since last clear */ +#define MRV_MI_MP_CR_FIFO_FULL +#define MRV_MI_MP_CR_FIFO_FULL_MASK 0x00000004U +#define MRV_MI_MP_CR_FIFO_FULL_SHIFT 2U +/*! Slice: mp_cb_fifo_full:*/ +/*! FIFO full flag of Cb FIFO in main path asserted since last clear */ +#define MRV_MI_MP_CB_FIFO_FULL +#define MRV_MI_MP_CB_FIFO_FULL_MASK 0x00000002U +#define MRV_MI_MP_CB_FIFO_FULL_SHIFT 1U +/*! Slice: mp_y_fifo_full:*/ +/*! FIFO full flag of Y FIFO in main path asserted since last clear */ +#define MRV_MI_MP_Y_FIFO_FULL +#define MRV_MI_MP_Y_FIFO_FULL_MASK 0x00000001U +#define MRV_MI_MP_Y_FIFO_FULL_SHIFT 0U +/*! Register: mi_status_clr: MI Status Clear Register (0x00000110)*/ +/*! Slice: sp_cr_fifo_full:*/ +/*! Clear status of Cr FIFO full flag in self path */ +#define MRV_MI_SP_CR_FIFO_FULL +#define MRV_MI_SP_CR_FIFO_FULL_MASK 0x00000040U +#define MRV_MI_SP_CR_FIFO_FULL_SHIFT 6U +/*! Slice: sp_cb_fifo_full:*/ +/*! Clear status of Cb FIFO full flag in self path */ +#define MRV_MI_SP_CB_FIFO_FULL +#define MRV_MI_SP_CB_FIFO_FULL_MASK 0x00000020U +#define MRV_MI_SP_CB_FIFO_FULL_SHIFT 5U +/*! Slice: sp_y_fifo_full:*/ +/*! Clear status of Y FIFO full flag in self path */ +#define MRV_MI_SP_Y_FIFO_FULL +#define MRV_MI_SP_Y_FIFO_FULL_MASK 0x00000010U +#define MRV_MI_SP_Y_FIFO_FULL_SHIFT 4U +/*! Slice: mp_cr_fifo_full:*/ +/*! Clear status of Cr FIFO full flag in main path */ +#define MRV_MI_MP_CR_FIFO_FULL +#define MRV_MI_MP_CR_FIFO_FULL_MASK 0x00000004U +#define MRV_MI_MP_CR_FIFO_FULL_SHIFT 2U +/*! Slice: mp_cb_fifo_full:*/ +/*! Clear status of Cb FIFO full flag in main path */ +#define MRV_MI_MP_CB_FIFO_FULL +#define MRV_MI_MP_CB_FIFO_FULL_MASK 0x00000002U +#define MRV_MI_MP_CB_FIFO_FULL_SHIFT 1U +/*! Slice: mp_y_fifo_full:*/ +/*! Clear status of Y FIFO full flag in main path */ +#define MRV_MI_MP_Y_FIFO_FULL +#define MRV_MI_MP_Y_FIFO_FULL_MASK 0x00000001U +#define MRV_MI_MP_Y_FIFO_FULL_SHIFT 0U +/*! Register: mi_sp_y_pic_width: Y component image width (0x00000114)*/ +/*! Slice: sp_y_pic_width:*/ +/*! Image width of the self picture Y component or RGB picture in pixel.*/ +/* For YCbCr 4:2:x and RGB 565 the image width must be a multiple of 2. If no line stride is used but flipping required, the image width must be a multiple of 8 for 4:2:x planar or 4 for 4:4:4 planar/4:2:x semi planar. There are no restrictions for RGB 888/666.*/ +/* In planar mode the image width of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the image width of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr image width is used.*/ +/* Note: Image width always refers to the picture width of the output image. This is particularly important when rotating.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_SP_Y_PIC_WIDTH +#define MRV_MI_SP_Y_PIC_WIDTH_MASK 0x00007FFFU +#define MRV_MI_SP_Y_PIC_WIDTH_SHIFT 0U +/*! Register: mi_sp_y_pic_height: Y component image height (0x00000118)*/ +/*! Slice: sp_y_pic_height:*/ +/*! Image height of the y component or RGB picture in pixel.*/ +/* In planar and semi planar mode the image width of the cb and cr component is assumed according to the YCbCr format, i.e. half for 4:2:0 and the same for 4:2:2 and 4:4:4.*/ +/* Note: Image height always refers to the picture height of the output image. This is particularly important when rotating.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_SP_Y_PIC_HEIGHT +#define MRV_MI_SP_Y_PIC_HEIGHT_MASK 0x00007FFFU +#define MRV_MI_SP_Y_PIC_HEIGHT_SHIFT 0U +/*! Register: mi_sp_y_pic_size: Y component image size (0x0000011c)*/ +/*! Slice: sp_y_pic_size:*/ +/*! Image size of the Y component or RGB picture in pixel which has to be the Y line length multiplied by the Y image height (sp_y_llength * sp_y_pic_height).*/ +/* In planar mode the image size of the Cb and Cr component is assumed according to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for 4:4:4. In semi planar mode the image size of the Cb and Cr component is assumed half for 4:2:0 and the same size for 4:2:2.*/ +/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/ +#define MRV_MI_SP_Y_PIC_SIZE +#define MRV_MI_SP_Y_PIC_SIZE_MASK 0x01FFFFFFU +#define MRV_MI_SP_Y_PIC_SIZE_SHIFT 0U +/*! Register: mi_dma_ctrl: DMA control register (0x00000120)*/ +/*! Slice: dma_rgb_format:*/ +/*! Selects RGB Bayer data of read DMA picture */ +/* 00: no DMA RGB Bayer data */ +/* 01: 8 bit RGB Bayer data */ +/* 10: 16 bit RGB Bayer data (12 bit used)*/ +/* bytes are organized MSB first and 4 lower bits of LSB remain unused:*/ +/* byte_even -> bayer[11:4], byte_odd[7:4] -> bayer[3:0]*/ +/* 11: reserved.*/ +#define MRV_MI_DMA_RGB_FORMAT +#define MRV_MI_DMA_RGB_FORMAT_MASK 0x00003000U +#define MRV_MI_DMA_RGB_FORMAT_SHIFT 12U +/*! Slice: dma_frame_end_disable:*/ +/*! Suppresses v_end so that no frame end can be detected by following instances. Note: The dma_ready interrupt is raised as usual, but the dma_frame_end interrupt will not be generated until v_end has been enabled again.*/ +#define MRV_MI_DMA_FRAME_END_DISABLE +#define MRV_MI_DMA_FRAME_END_DISABLE_MASK 0x00000400U +#define MRV_MI_DMA_FRAME_END_DISABLE_SHIFT 10U +/*! Slice: dma_continuous_en:*/ +/*! Enables continuous mode. If set the same frame is read back over and over. A start pulse on dma_start is needed only for the first time. To stop continuous mode reset this bit (takes effect after the next frame end) or execute a soft reset. This bit is intended to be used in conjunction with the Superimpose feature.*/ +#define MRV_MI_DMA_CONTINUOUS_EN +#define MRV_MI_DMA_CONTINUOUS_EN_MASK 0x00000200U +#define MRV_MI_DMA_CONTINUOUS_EN_SHIFT 9U +/*! Slice: dma_byte_swap:*/ +/*! Enables change of DMA byte order of the 32 bit input word at read port */ +/* 1: byte order is mirrored but the bit order within one byte doesn’t change */ +/* 0: no byte mirroring */ +#define MRV_MI_DMA_BYTE_SWAP +#define MRV_MI_DMA_BYTE_SWAP_MASK 0x00000100U +#define MRV_MI_DMA_BYTE_SWAP_SHIFT 8U +/*! Slice: dma_inout_format:*/ +/*! Selects input/output format of DMA picture.*/ +/* 11: YCbCr 4:4:4 */ +/* 10: YCbCr 4:2:2 */ +/* 01: YCbCr 4:2:0 */ +/* 00: YCbCr 4:0:0 */ +#define MRV_MI_DMA_INOUT_FORMAT +#define MRV_MI_DMA_INOUT_FORMAT_MASK 0x000000C0U +#define MRV_MI_DMA_INOUT_FORMAT_SHIFT 6U +/*! Slice: dma_read_format:*/ +/*! Defines how YCbCr picture data is read from memory.*/ +/* 00: planar */ +/* 01: semi planar, for YCbCr 4:2:x */ +/* 10: interleaved (combined), for YCbCr 4:2:2 and RGB only */ +/* 11: reserved */ +#define MRV_MI_DMA_READ_FORMAT +#define MRV_MI_DMA_READ_FORMAT_MASK 0x00000030U +#define MRV_MI_DMA_READ_FORMAT_SHIFT 4U +/*! Slice: dma_burst_len_chrom:*/ +/*! Burst length for Cb or Cr data affecting DMA read port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ +#define MRV_MI_DMA_BURST_LEN_CHROM +#define MRV_MI_DMA_BURST_LEN_CHROM_MASK 0x0000000CU +#define MRV_MI_DMA_BURST_LEN_CHROM_SHIFT 2U +/*! Slice: dma_burst_len_lum:*/ +/*! Burst length for Y data affecting DMA read port.*/ +/* 00: 4-beat bursts */ +/* 01: 8-beat bursts */ +/* 10: 16-beat bursts */ +/* 11: reserved */ +/* Ignored if 8- or 16-beat bursts are not supported.*/ +#define MRV_MI_DMA_BURST_LEN_LUM +#define MRV_MI_DMA_BURST_LEN_LUM_MASK 0x00000003U +#define MRV_MI_DMA_BURST_LEN_LUM_SHIFT 0U +/*! Register: mi_dma_start: DMA start register (0x00000124)*/ +/*! Slice: dma_start:*/ +/*! Enables DMA access. Additionally main or self path has to be enabled separately.*/ +#define MRV_MI_DMA_START +#define MRV_MI_DMA_START_MASK 0x00000001U +#define MRV_MI_DMA_START_SHIFT 0U +/*! Register: mi_dma_status: DMA status register (0x00000128)*/ +/*! Slice: dma_active:*/ +/*! If set DMA access is active.*/ +#define MRV_MI_DMA_ACTIVE +#define MRV_MI_DMA_ACTIVE_MASK 0x00000001U +#define MRV_MI_DMA_ACTIVE_SHIFT 0U +/*! Register: mi_pixel_cnt: Counter value for defect pixel list (0x0000012c)*/ +/*! Slice: pix_cnt:*/ +/*! Counter value specifies the number of pixels of the defect pixel list generated by DPCC of the last transmitted frame. Updated at frame end.*/ +/* A soft reset will set the counter to zero.*/ +#define MRV_MI_PIX_CNT +#define MRV_MI_PIX_CNT_MASK 0x0FFFFFFFU +#define MRV_MI_PIX_CNT_SHIFT 0U +/*! Register: mi_mp_y_base_ad_init2: Base address 2 (ping pong) for main picture Y component, JPEG or raw data (0x00000130)*/ +/*! Slice: mp_y_base_ad_init2:*/ +/*! 2nd ping pong base address of main picture Y component buffer, JPEG buffer or raw data buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_MP_Y_BASE_AD_INIT2 +#define MRV_MI_MP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_MP_Y_BASE_AD_INIT2_SHIFT 3U +/*! Register: mi_mp_cb_base_ad_init2: Base address 2 (pingpong) for main picture Cb component (0x00000134)*/ +/*! Slice: mp_cb_base_ad_init2:*/ +/*! 2nd ping pong base address of main picture Cb component buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_MP_CB_BASE_AD_INIT2 +#define MRV_MI_MP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CB_BASE_AD_INIT2_SHIFT 3U +/*! Register: mi_mp_cr_base_ad_init2: Base address 2 (pingpong) for main picture Cr component ring buffer (0x00000138)*/ +/*! Slice: mp_cr_base_ad_init2:*/ +/*! 2nd ping pong Base address of main picture Cr component buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_MP_CR_BASE_AD_INIT2 +#define MRV_MI_MP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_MP_CR_BASE_AD_INIT2_SHIFT 3U +/*! Register: mi_sp_y_base_ad_init2: Base address 2 (ping pong) for main picture Y component, JPEG or raw data (0x0000013c)*/ +/*! Slice: sp_y_base_ad_init2:*/ +/*! 2nd ping pong base address of main picture Y component buffer, JPEG buffer or raw data buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_Y_BASE_AD_INIT2 +#define MRV_MI_SP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_SP_Y_BASE_AD_INIT2_SHIFT 3U +/*! Register: mi_sp_cb_base_ad_init2: Base address 2 (pingpong) for main picture Cb component (0x00000140)*/ +/*! Slice: sp_cb_base_ad_init2:*/ +/*! 2nd ping pong base address of main picture Cb component buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CB_BASE_AD_INIT2 +#define MRV_MI_SP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CB_BASE_AD_INIT2_SHIFT 3U +/*! Register: mi_sp_cr_base_ad_init2: Base address 2 (pingpong) for main picture Cr component ring buffer (0x00000144)*/ +/*! Slice: sp_cr_base_ad_init2:*/ +/*! 2nd ping pong Base address of main picture Cr component buffer.*/ +/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/ +/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/ +#define MRV_MI_SP_CR_BASE_AD_INIT2 +#define MRV_MI_SP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF8U +#define MRV_MI_SP_CR_BASE_AD_INIT2_SHIFT 3U +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Nano handshake */ +/*! Register: isp_handshake_ctrl_0: IspNano handshake functions (0x0000014C)*/ +/*! Slice: mp_handshake_en:*/ +/*! Enable mp handshake function for MI MP */ +#define MRV_MI_MP_HANDSHK_EN +#define MRV_MI_MP_HANDSHK_EN_MASK 0x00000001U +#define MRV_MI_MP_HANDSHK_EN_SHIFT 0U +/*! Slice: mp_handshk_storage_format */ +/*! Define how YCbCr picture data is stored in memory */ +/*! 00: Planar */ +/*! 01: Semi planar, for YCbCr4:2:x */ +/*! 10: Interleaved(combiled), for YCbCr 4:2:2 only or RAW format.*/ +/*! 11: not support */ +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_MASK 0x00000006U +#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_SHIFT 1U +/*! Slice: mp_handshk_data_format */ +/*! Defines the video format */ +/*! 00: RAW format */ +/*! 01: reserved */ +/*! 10: YUV 422 */ +/*! 11: YUV 420 */ +#define MRV_MI_MP_HANDSHK_DATA_FORMAT +#define MRV_MI_MP_HANDSHK_DATA_FORMAT_MASK 0x00000018U +#define MRV_MI_MP_HANDSHK_DATA_FORMAT_SHIFT 3U +/*! Slice: mp_handshk_slice_size */ +/*! Defines the slice size to generate handshake signals, minus 1 is used */ +#define MRV_MI_MP_HANDSHK_SLICE_SIZE +#define MRV_MI_MP_HANDSHK_SLICE_SIZE_MASK 0x00001FE0U +#define MRV_MI_MP_HANDSHK_SLICE_SIZE_SHIFT 5U +/*! Slice: mp_handshk_slice_buf_size */ +/*! Defines the circular buffer size in number of defined slices per buffer, minus 1 is used */ +#define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE +#define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE_MASK 0x001FE000U +#define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE_SHIFT 13U +/*! Slice: mp_handshk_ack_count */ +/*! Defines the acknowledage is not received in the defined cycles, it will generate handshake interrupt.*/ +#define MRV_MI_MP_HANDSHK_ACK_COUNT +#define MRV_MI_MP_HANDSHK_ACK_COUNT_MASK 0x1FE00000U +#define MRV_MI_MP_HANDSHK_ACK_COUNT_SHIFT 21U +/*! Register: isp_handshake_mp_y_llength: IspNano handshake y_llength (0x00000150)*/ +/*! Slice: mp_y_llength, line length of main picture Y component or RGB picture in pixel.*/ +/*! Also knows as line stride, if no line stride is used, the line length must match image width.*/ +#define MRV_MI_MP_HANDSHK_Y_LLENGTH +#define MRV_MI_MP_HANDSHK_Y_LLENGTH_MASK 0x00007FFFU +#define MRV_MI_MP_HANDSHK_Y_LLENGTH_SHIFT 0U +/*! Register: isp_handshake_y_slice_offset: IspNano handshake y slice offset (0x00000154)*/ +/*! Slice: mp_y_slice_offset defines the offset bewteen two successive Y slice input buffers in bytes.*/ +#define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET +#define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET_MASK 0xFFFFFFF8U +#define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET_SHIFT 0U +/*! Register: isp_handshake_c_slice_offset: ISPNano handshake c slice offset (ox00000158)*/ +/*! Slice: mp_c_slice_offset defines the offset between two successive Cb/Cr slice input buffers in bytes.*/ +#define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET +#define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET_MASK 0xFFFFFFF8U +#define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET_SHIFT 0U +#endif +#ifdef ISP_MI_ALIGN_NANO +/*! Register mi_output_align_format for isp nano: (0x0000015C)*/ +/*! Slice mp_lsb_alignment:*/ +/*! msb/lsb align for raw 10 and raw 12 formats control */ +/*! 0: MSB aligned for RAW10 and RAW12 formats */ +/*! 1: LSB aligned for RAW10 and RAW12 formats */ +#define MRV_MI_LSB_ALIGNMENT +#define MRV_MI_LSB_ALIGNMENT_MASK 0x00000001U +#define MRV_MI_LSB_ALIGNMENT_SHIFT 0U +#endif +#ifdef ISP_MI_BYTESWAP +/*! Slice mp_byte_swap:*/ +/*! swap bytes for ISP Nano */ +/*! bit 0 to swap bytes */ +/*! bit 1 to swap words */ +/*! bit 2 to swap dwords */ +/*! 3'b001: ABCDEFGH => BADCFEHG */ +/*! 3'b000: ABCDEFGH => ABCDEFGH */ +/*! 3'b010: ABCDEFGH => CDABGHEF */ +/*! 3'b011: ABCDEFGH => DCBAHGFE */ +/*! 3'b100: ABCDEFGH => EFGHABCD */ +/*! 3'b101: ABCDEFGH => FEHGBADC */ +/*! 3'b110: ABCDEFGH => GHEFCDAB */ +/*! 3'b111: ABCDEFGH => HGFEDCBA */ +#define MRV_MI_MP_BYTE_SWAP +#define MRV_MI_MP_BYTE_SWAP_MASK 0x0000000EU +#define MRV_MI_MP_BYTE_SWAP_SHIFT 1U +#endif +#ifdef ISP_MI_FIFO_DEPTH_NANO +/*! Register mi_mp_output_fifo_size for isp nano: (0x00000160)*/ +/*! Slice output_fifo_depth:*/ +/*! Select output FIFO depth setting */ +/*! 00: FULL(2KBytes)*/ +/*! 01: HALF(1KBytes)*/ +/*! 10: 1/4(512Bytes)*/ +/*! 11: 1/8(256Bytes)*/ +#define MRV_MI_OUTOUT_FIFO_DEPTH +#define MRV_MI_OUTOUT_FIFO_DEPTH_MASK 0x00000003U +#define MRV_MI_OUTOUT_FIFO_DEPTH_SHIFT 0U +#endif +#ifdef ISP_MI_HANDSHAKE_NANO +/*! Register mi_mp_y_pic_width: IspNano handshake mp_y_pic_width (0x00000164)*/ +/*! Slice mi_mp_y_pic_width:*/ +/*! Image width of the main picture Y component in pixel.*/ +#define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH +#define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH_SHIFT 0U +/*! Register mi_mp_y_pic_height: IspNano handshake mp_y_pic_height (0x00000168)*/ +/*! Slice mi_mp_y_pic_height:*/ +/*! Image height of the main picture Y component in pixel.*/ +#define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT +#define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT_SHIFT 0U +/*! Register mi_mp_y_pic_size: IspNano handshake mp_y_pic_size (0x0000016C)*/ +/*! Slice mi_mp_y_pic_size */ +/*! Image size of the Y component in pixel which has to be the Y line length multipled by */ +/*! the Y image height(mp_y_llength*mp_y_pic_height)*/ +#define MRV_MI_MP_HANDSHK_Y_PIC_ZISE +#define MRV_MI_MP_HANDSHK_Y_PIC_ZISE_MASK 0xFFFFFFFFU +#define MRV_MI_MP_HANDSHK_Y_PIC_ZISE_SHIFT 0U +#endif +/*! Register: jpe_gen_header: command to start stream header generation (0x00000000)*/ +/*! Slice: gen_header:*/ +/*! "1" = Start command to generate stream header;*/ +/* auto reset to zero after one clock cycle */ +#define MRV_JPE_GEN_HEADER +#define MRV_JPE_GEN_HEADER_MASK 0x00000001U +#define MRV_JPE_GEN_HEADER_SHIFT 0U +/*! Register: jpe_encode: Start command to start JFIF stream encoding (0x00000004)*/ +/*! Slice: encode:*/ +/*! "1" = Start command to start JFIF stream encoding;*/ +/* auto reset to zero after one clock cycle.*/ +/* This bit is write-only: reading result is always zero!*/ +#define MRV_JPE_ENCODE +#define MRV_JPE_ENCODE_MASK 0x00000001U +#define MRV_JPE_ENCODE_SHIFT 0U +/*! Register: jpe_init: Automatic configuration update (INIT) (0x00000008)*/ +/*! Slice: JP_INIT:*/ +/*! "1" = Immediate start of JPEG encoder.*/ +/* This bit has to be set after "Encode" to start the JPEG encoder. The "Encode" command becomes active either with JP_INIT or with the input signal "CFG_UPD".*/ +/* auto reset to zero after one clock cycle !!!*/ +#define MRV_JPE_JP_INIT +#define MRV_JPE_JP_INIT_MASK 0x00000001U +#define MRV_JPE_JP_INIT_SHIFT 0U +/*! Register: jpe_y_scale_en: Y value scaling control register (0x0000000c)*/ +/*! Slice: y_scale_en:*/ +/*! Y scale flag */ +/* 1: scaling Y input from[16..235] to[0..255]*/ +/* 0: no Y input scaling */ +#define MRV_JPE_Y_SCALE_EN +#define MRV_JPE_Y_SCALE_EN_MASK 0x00000001U +#define MRV_JPE_Y_SCALE_EN_SHIFT 0U +/*! Register: jpe_cbcr_scale_en: Cb/Cr value scaling control register (0x00000010)*/ +/*! Slice: cbcr_scale_en:*/ +/*! Cb/Cr scale flag */ +/* 1: scaling Cb/Cr input from[16..240] to[0..255]*/ +/* 0: no Cb/Cr input scaling */ +#define MRV_JPE_CBCR_SCALE_EN +#define MRV_JPE_CBCR_SCALE_EN_MASK 0x00000001U +#define MRV_JPE_CBCR_SCALE_EN_SHIFT 0U +/*! Register: jpe_table_flush: header generation debug register (0x00000014)*/ +/*! Slice: table_flush:*/ +/*! header generation debug control flag */ +/* (controls transmission of last header bytes if the 64 bit output buffer is not completely filled)*/ +/* 1: immediately transmit last header bytes */ +/* 0: wait for encoded image data to fill output buffer */ +#define MRV_JPE_TABLE_FLUSH +#define MRV_JPE_TABLE_FLUSH_MASK 0x00000001U +#define MRV_JPE_TABLE_FLUSH_SHIFT 0U +/*! Register: jpe_enc_hsize: JPEG codec horizontal image size for encoding (0x00000018)*/ +/*! Slice: enc_hsize:*/ +/*! JPEG codec horizontal image size for R2B and SGEN blocks.*/ +/* Note: If the active camerIC version does not support 64 megapixel only those bits will be used which are required and the respective most significant bits will be ignored. Example: 5MP camerIC uses only bits[12:0] and ignores bits[14:13].*/ +#define MRV_JPE_ENC_HSIZE +#define MRV_JPE_ENC_HSIZE_MASK 0x00007FFFU +#define MRV_JPE_ENC_HSIZE_SHIFT 0U +/*! Register: jpe_enc_vsize: JPEG codec vertical image size for encoding (0x0000001c)*/ +/*! Slice: enc_vsize:*/ +/*! JPEG codec vertical image size for R2B and SGEN blocks */ +#define MRV_JPE_ENC_VSIZE +#define MRV_JPE_ENC_VSIZE_MASK 0x00003FFFU +#define MRV_JPE_ENC_VSIZE_SHIFT 0U +/*! Register: jpe_pic_format: JPEG picture encoding format (0x00000020)*/ +/*! Slice: enc_pic_format:*/ +/*! "0:0:1" = 4:2:2 format */ +/* "1:x:x" = 4:0:0 format */ +#define MRV_JPE_ENC_PIC_FORMAT +#define MRV_JPE_ENC_PIC_FORMAT_MASK 0x00000007U +#define MRV_JPE_ENC_PIC_FORMAT_SHIFT 0U +/*! Register: jpe_restart_interval: restart marker insertion register (0x00000024)*/ +/*! Slice: restart_interval:*/ +/*! No of MCU in reset interval via host */ +#define MRV_JPE_RESTART_INTERVAL +#define MRV_JPE_RESTART_INTERVAL_MASK 0x0000FFFFU +#define MRV_JPE_RESTART_INTERVAL_SHIFT 0U +/*! Register: jpe_tq_y_select: Q- table selector 0, quant. table for Y component (0x00000028)*/ +/*! Slice: tq0_select:*/ +/*! "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#define MRV_JPE_TQ0_SELECT +#define MRV_JPE_TQ0_SELECT_MASK 0x00000003U +#define MRV_JPE_TQ0_SELECT_SHIFT 0U +/*! Register: jpe_tq_u_select: Q- table selector 1, quant. table for U component (0x0000002c)*/ +/*! Slice: tq1_select:*/ +/*! "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#define MRV_JPE_TQ1_SELECT +#define MRV_JPE_TQ1_SELECT_MASK 0x00000003U +#define MRV_JPE_TQ1_SELECT_SHIFT 0U +/*! Register: jpe_tq_v_select: Q- table selector 2, quant. table for V component (0x00000030)*/ +/*! Slice: tq2_select:*/ +/*! "00" = qtable 0 */ +/* "01" = qtable 1 */ +/* "10" = qtable 2 */ +/* "11" = qtable 3 */ +#define MRV_JPE_TQ2_SELECT +#define MRV_JPE_TQ2_SELECT_MASK 0x00000003U +#define MRV_JPE_TQ2_SELECT_SHIFT 0U +/*! Register: jpe_dc_table_select: Huffman table selector for DC values (0x00000034)*/ +/*! Slice: dc_table_select_v:*/ +/*! "0" = dc table 0; color component 2 (V)*/ +/* "1" = dc table 1; color component 2 (V)*/ +#define MRV_JPE_DC_TABLE_SELECT_V +#define MRV_JPE_DC_TABLE_SELECT_V_MASK 0x00000004U +#define MRV_JPE_DC_TABLE_SELECT_V_SHIFT 2U +/*! Slice: dc_table_select_u:*/ +/*! "0" = dc table 0; color component 1 (U)*/ +/* "1" = dc table 1; color component 1 (U)*/ +#define MRV_JPE_DC_TABLE_SELECT_U +#define MRV_JPE_DC_TABLE_SELECT_U_MASK 0x00000002U +#define MRV_JPE_DC_TABLE_SELECT_U_SHIFT 1U +/*! Slice: dc_table_select_y:*/ +/*! "0" = dc table 0; color component 0 (Y)*/ +/* "1" = dc table 1; color component 0 (Y)*/ +#define MRV_JPE_DC_TABLE_SELECT_Y +#define MRV_JPE_DC_TABLE_SELECT_Y_MASK 0x00000001U +#define MRV_JPE_DC_TABLE_SELECT_Y_SHIFT 0U +/*! Register: jpe_ac_table_select: Huffman table selector for AC values (0x00000038)*/ +/*! Slice: ac_table_select_v:*/ +/*! "0" = ac table 0; component 2 (V)*/ +/* "1" = ac table 1; component 2 (V)*/ +#define MRV_JPE_AC_TABLE_SELECT_V +#define MRV_JPE_AC_TABLE_SELECT_V_MASK 0x00000004U +#define MRV_JPE_AC_TABLE_SELECT_V_SHIFT 2U +/*! Slice: ac_table_select_u:*/ +/*! "0" = ac table 0; component 1 (U)*/ +/* "1" = ac table 1; component 1 (U)*/ +#define MRV_JPE_AC_TABLE_SELECT_U +#define MRV_JPE_AC_TABLE_SELECT_U_MASK 0x00000002U +#define MRV_JPE_AC_TABLE_SELECT_U_SHIFT 1U +/*! Slice: ac_table_select_y:*/ +/*! "0" = ac table 0; component 0 (Y)*/ +/* "1" = ac table 1; component 0 (Y)*/ +#define MRV_JPE_AC_TABLE_SELECT_Y +#define MRV_JPE_AC_TABLE_SELECT_Y_MASK 0x00000001U +#define MRV_JPE_AC_TABLE_SELECT_Y_SHIFT 0U +/*! Register: jpe_table_data: table programming register (0x0000003c)*/ +/*! Slice: table_wdata_h:*/ +/*! Table data MSB */ +#define MRV_JPE_TABLE_WDATA_H +#define MRV_JPE_TABLE_WDATA_H_MASK 0x0000FF00U +#define MRV_JPE_TABLE_WDATA_H_SHIFT 8U +/*! Slice: table_wdata_l:*/ +/*! Table data LSB */ +#define MRV_JPE_TABLE_WDATA_L +#define MRV_JPE_TABLE_WDATA_L_MASK 0x000000FFU +#define MRV_JPE_TABLE_WDATA_L_SHIFT 0U +/*! Register: jpe_table_id: table programming select register (0x00000040)*/ +/*! Slice: table_id:*/ +/*! select table */ +/* "0000" : Q-table 0 */ +/* "0001" : Q-table 1 */ +/* "0010" : Q-table 2 */ +/* "0011" : Q-table 3 */ +/* "0100" : VLC DC-table 0 */ +/* "0101" : VLC AC-table 0 */ +/* "0110" : VLC DC-table 1 */ +/* "0111" : VLC AC-table 1 */ +/* "1xxx" : reserved for debug */ +#define MRV_JPE_TABLE_ID +#define MRV_JPE_TABLE_ID_MASK 0x0000000FU +#define MRV_JPE_TABLE_ID_SHIFT 0U +/*! Register: jpe_tac0_len: Huffman AC table 0 length (0x00000044)*/ +/*! Slice: tac0_len:*/ +/*! Huffman table length for ac0 table */ +#define MRV_JPE_TAC0_LEN +#define MRV_JPE_TAC0_LEN_MASK 0x000000FFU +#define MRV_JPE_TAC0_LEN_SHIFT 0U +/*! Register: jpe_tdc0_len: Huffman DC table 0 length (0x00000048)*/ +/*! Slice: tdc0_len:*/ +/*! Huffman table length for dc0 table */ +#define MRV_JPE_TDC0_LEN +#define MRV_JPE_TDC0_LEN_MASK 0x000000FFU +#define MRV_JPE_TDC0_LEN_SHIFT 0U +/*! Register: jpe_tac1_len: Huffman AC table 1 length (0x0000004c)*/ +/*! Slice: tac1_len:*/ +/*! Huffman table length for ac1 table */ +#define MRV_JPE_TAC1_LEN +#define MRV_JPE_TAC1_LEN_MASK 0x000000FFU +#define MRV_JPE_TAC1_LEN_SHIFT 0U +/*! Register: jpe_tdc1_len: Huffman DC table 1 length (0x00000050)*/ +/*! Slice: tdc1_len:*/ +/*! Huffman table length for dc1 table */ +#define MRV_JPE_TDC1_LEN +#define MRV_JPE_TDC1_LEN_MASK 0x000000FFU +#define MRV_JPE_TDC1_LEN_SHIFT 0U +/*! Register: jpe_encoder_busy: encoder status flag (0x00000058)*/ +/*! Slice: codec_busy:*/ +/*! Bit 0 = "1" : JPEG codec in process */ +#define MRV_JPE_CODEC_BUSY +#define MRV_JPE_CODEC_BUSY_MASK 0x00000001U +#define MRV_JPE_CODEC_BUSY_SHIFT 0U +/*! Register: jpe_header_mode: header mode definition (0x0000005c)*/ +/*! Slice: header_mode:*/ +/*! "00" = no header */ +/* "01" = reserved */ +/* "10" = JFIF 1.02 header */ +/* "11" = reserved */ +#define MRV_JPE_HEADER_MODE +#define MRV_JPE_HEADER_MODE_MASK 0x00000003U +#define MRV_JPE_HEADER_MODE_SHIFT 0U +/*! Register: jpe_encode_mode: encode mode (0x00000060)*/ +/*! Slice: encode_mode:*/ +/*! Always "1", because this is the encoder only edition */ +#define MRV_JPE_ENCODE_MODE +#define MRV_JPE_ENCODE_MODE_MASK 0x00000001U +#define MRV_JPE_ENCODE_MODE_SHIFT 0U +/*! Register: jpe_debug: debug information register (0x00000064)*/ +/*! Slice: deb_bad_table_access:*/ +/*! Debug signal only (set if an access to the TABLE_DATA or to the TABLE_ID register is performed, when the JPEG_ENCODER is busy. In this case a default PVCI Acknowledge is generated. Thus the configuration bus is not blocked)*/ +#define MRV_JPE_DEB_BAD_TABLE_ACCESS +#define MRV_JPE_DEB_BAD_TABLE_ACCESS_MASK 0x00000100U +#define MRV_JPE_DEB_BAD_TABLE_ACCESS_SHIFT 8U +/*! Slice: deb_vlc_table_busy:*/ +/*! Debug signal only (vlc access to huff-tables)*/ +#define MRV_JPE_DEB_VLC_TABLE_BUSY +#define MRV_JPE_DEB_VLC_TABLE_BUSY_MASK 0x00000020U +#define MRV_JPE_DEB_VLC_TABLE_BUSY_SHIFT 5U +/*! Slice: deb_r2b_memory_full:*/ +/*! Debug signal only (line memory status of r2b)*/ +#define MRV_JPE_DEB_R2B_MEMORY_FULL +#define MRV_JPE_DEB_R2B_MEMORY_FULL_MASK 0x00000010U +#define MRV_JPE_DEB_R2B_MEMORY_FULL_SHIFT 4U +/*! Slice: deb_vlc_encode_busy:*/ +/*! Debug signal only (vlc encode processing active)*/ +#define MRV_JPE_DEB_VLC_ENCODE_BUSY +#define MRV_JPE_DEB_VLC_ENCODE_BUSY_MASK 0x00000008U +#define MRV_JPE_DEB_VLC_ENCODE_BUSY_SHIFT 3U +/*! Slice: deb_qiq_table_acc:*/ +/*! Debug signal only (QIQ table access)*/ +#define MRV_JPE_DEB_QIQ_TABLE_ACC +#define MRV_JPE_DEB_QIQ_TABLE_ACC_MASK 0x00000004U +#define MRV_JPE_DEB_QIQ_TABLE_ACC_SHIFT 2U +/*! Register: jpe_error_imr: JPEG error interrupt mask register (0x00000068)*/ +/*! Slice: vlc_table_err:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_VLC_TABLE_ERR +#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U +#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U +/*! Slice: r2b_IMG_size_err:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_R2B_IMG_SIZE_ERR +#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U +#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U +/*! Slice: DCT_ERR:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_DCT_ERR +#define MRV_JPE_DCT_ERR_MASK 0x00000080U +#define MRV_JPE_DCT_ERR_SHIFT 7U +/*! Slice: vlc_symbol_err:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_VLC_SYMBOL_ERR +#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U +#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U +/*! Register: jpe_error_ris: JPEG error raw interrupt status register (0x0000006c)*/ +/*! Slice: vlc_table_err:*/ +/*! "1" = illegal table detected */ +#define MRV_JPE_VLC_TABLE_ERR +#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U +#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U +/*! Slice: r2b_IMG_size_err:*/ +/*! "1" = mismatch of predefined h_size and v_size values with calculated values (encode mode)*/ +#define MRV_JPE_R2B_IMG_SIZE_ERR +#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U +#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U +/*! Slice: DCT_ERR:*/ +/*! "1" = block start mismatch */ +#define MRV_JPE_DCT_ERR +#define MRV_JPE_DCT_ERR_MASK 0x00000080U +#define MRV_JPE_DCT_ERR_SHIFT 7U +/*! Slice: vlc_symbol_err:*/ +/*! "1" = illegal symbol detected (encoding)*/ +#define MRV_JPE_VLC_SYMBOL_ERR +#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U +#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U +/*! Register: jpe_error_mis: JPEG error masked interrupt status register (0x00000070)*/ +/*! Slice: vlc_table_err:*/ +/*! "1" = illegal table detected */ +#define MRV_JPE_VLC_TABLE_ERR +#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U +#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U +/*! Slice: r2b_IMG_size_err:*/ +/*! "1" = mismatch of predefined h_size and v_size values with calculated values (encode mode)*/ +#define MRV_JPE_R2B_IMG_SIZE_ERR +#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U +#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U +/*! Slice: DCT_ERR:*/ +/*! "1" = block start mismatch */ +#define MRV_JPE_DCT_ERR +#define MRV_JPE_DCT_ERR_MASK 0x00000080U +#define MRV_JPE_DCT_ERR_SHIFT 7U +/*! Slice: vlc_symbol_err:*/ +/*! "1" = illegal symbol detected (encoding)*/ +#define MRV_JPE_VLC_SYMBOL_ERR +#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U +#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U +/*! Register: jpe_error_icr: JPEG error interrupt set register (0x00000074)*/ +/*! Slice: vlc_table_err:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_VLC_TABLE_ERR +#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U +#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U +/*! Slice: r2b_IMG_size_err:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_R2B_IMG_SIZE_ERR +#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U +#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U +/*! Slice: DCT_ERR:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_DCT_ERR +#define MRV_JPE_DCT_ERR_MASK 0x00000080U +#define MRV_JPE_DCT_ERR_SHIFT 7U +/*! Slice: vlc_symbol_err:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_VLC_SYMBOL_ERR +#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U +#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U +/*! Register: jpe_error_isr: JPEG error interrupt clear register (0x00000078)*/ +/*! Slice: vlc_table_err:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_VLC_TABLE_ERR +#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U +#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U +/*! Slice: r2b_IMG_size_err:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_R2B_IMG_SIZE_ERR +#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U +#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U +/*! Slice: dct_err:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_DCT_ERR +#define MRV_JPE_DCT_ERR_MASK 0x00000080U +#define MRV_JPE_DCT_ERR_SHIFT 7U +/*! Slice: vlc_symbol_err:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_VLC_SYMBOL_ERR +#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U +#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U +/*! Register: jpe_status_imr: JPEG status interrupt mask register (0x0000007c)*/ +/*! Slice: gen_header_done:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_GEN_HEADER_DONE +#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U +#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U +/*! Slice: encode_done:*/ +/*! "1" = interrupt is activated (masked in)*/ +#define MRV_JPE_ENCODE_DONE +#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U +#define MRV_JPE_ENCODE_DONE_SHIFT 4U +/*! Register: jpe_status_ris: JPEG status raw interrupt status register (0x00000080)*/ +/*! Slice: gen_header_done:*/ +/*! "1" = Stream header generation finished */ +#define MRV_JPE_GEN_HEADER_DONE +#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U +#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U +/*! Slice: encode_done:*/ +/*! "1" = Encode processing finished */ +#define MRV_JPE_ENCODE_DONE +#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U +#define MRV_JPE_ENCODE_DONE_SHIFT 4U +/*! Register: jpe_status_mis: JPEG status masked interrupt status register (0x00000084)*/ +/*! Slice: gen_header_done:*/ +/*! "1" = Stream header generation finished */ +#define MRV_JPE_GEN_HEADER_DONE +#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U +#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U +/*! Slice: encode_done:*/ +/*! "1" = Encode processing finished */ +#define MRV_JPE_ENCODE_DONE +#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U +#define MRV_JPE_ENCODE_DONE_SHIFT 4U +/*! Register: jpe_status_icr: JPEG status interrupt clear register (0x00000088)*/ +/*! Slice: gen_header_done:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_GEN_HEADER_DONE +#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U +#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U +/*! Slice: encode_done:*/ +/*! "1" = clear status bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_ENCODE_DONE +#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U +#define MRV_JPE_ENCODE_DONE_SHIFT 4U +/*! Register: jpe_status_isr: JPEG status interrupt set register (0x0000008c)*/ +/*! Slice: gen_header_done:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_GEN_HEADER_DONE +#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U +#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U +/*! Slice: encode_done:*/ +/*! "1" = set error bit, bit is reset to zero after 1 clk */ +#define MRV_JPE_ENCODE_DONE +#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U +#define MRV_JPE_ENCODE_DONE_SHIFT 4U +/*! Register: jpe_config: JPEG configuration register (0x00000090)*/ +/*! Slice: speedview_en:*/ +/*! 1: speed view enabled */ +/* 0: speed view disabled */ +#define MRV_JPE_SPEEDVIEW_EN +#define MRV_JPE_SPEEDVIEW_EN_MASK 0x00000010U +#define MRV_JPE_SPEEDVIEW_EN_SHIFT 4U +/*! Slice: cont_mode:*/ +/*! Encoder continous mode */ +/* "00": encoder stops at frame end (corresponds to former behavior)*/ +/* "01": encoder starts automatically to encode the next frame */ +/* "10": unused */ +/* "11": encoder first generates next header and then encodes automatically the next frame */ +/* These settings are checked after encoding one frame. They are not auto-reset by hardware.*/ +#define MRV_JPE_CONT_MODE +#define MRV_JPE_CONT_MODE_MASK 0x00000003U +#define MRV_JPE_CONT_MODE_SHIFT 0U +/*! Register: smia_ctrl: global control register (0x00000000)*/ +/*! Slice: DMA_CHANNEL_SEL:*/ +/*! DMA channel selector for image data output */ +#define MRV_SMIA_DMA_CHANNEL_SEL +#define MRV_SMIA_DMA_CHANNEL_SEL_MASK 0x00000700U +#define MRV_SMIA_DMA_CHANNEL_SEL_SHIFT 8U +/*! Slice: SHUTDOWN_LANE:*/ +/*! Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown */ +#define MRV_SMIA_SHUTDOWN_LANE +#define MRV_SMIA_SHUTDOWN_LANE_MASK 0x00000008U +#define MRV_SMIA_SHUTDOWN_LANE_SHIFT 3U +/*! Slice: CFG_UPD_ENA:*/ +/*! enables generation of cfg_upd signal at frame end */ +#define MRV_SMIA_CFG_UPD_ENA +#define MRV_SMIA_CFG_UPD_ENA_MASK 0x00000004U +#define MRV_SMIA_CFG_UPD_ENA_SHIFT 2U +/*! Slice: FLUSH_FIFO:*/ +/*! writing '1' resets the write- and read pointers of the embedded data fifo.*/ +#define MRV_SMIA_FLUSH_FIFO +#define MRV_SMIA_FLUSH_FIFO_MASK 0x00000002U +#define MRV_SMIA_FLUSH_FIFO_SHIFT 1U +/*! Slice: OUTPUT_ENA:*/ +/*! '1': transmission to alomics output interface is enabled */ +/* '0': transmission is disabled */ +#define MRV_SMIA_OUTPUT_ENA +#define MRV_SMIA_OUTPUT_ENA_MASK 0x00000001U +#define MRV_SMIA_OUTPUT_ENA_SHIFT 0U +/*! Register: smia_status: global status register (0x00000004)*/ +/*! Slice: DMA_CHANNEL:*/ +/*! DMA channel of currently received packet */ +#define MRV_SMIA_DMA_CHANNEL +#define MRV_SMIA_DMA_CHANNEL_MASK 0x00000700U +#define MRV_SMIA_DMA_CHANNEL_SHIFT 8U +/*! Slice: EMB_DATA_AVAIL:*/ +/*! 1: embedded data fifo not empty */ +#define MRV_SMIA_EMB_DATA_AVAIL +#define MRV_SMIA_EMB_DATA_AVAIL_MASK 0x00000001U +#define MRV_SMIA_EMB_DATA_AVAIL_SHIFT 0U +/*! Register: smia_imsc: Interrupt mask (0x00000008)*/ +/*! Slice: IMSC_FIFO_FILL_LEVEL:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL +#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL_MASK 0x00000020U +#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL_SHIFT 5U +/*! Slice: IMSC_SYNC_FIFO_OVFLW:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW +#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_MASK 0x00000010U +#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_SHIFT 4U +/*! Slice: IMSC_ERR_CS:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_ERR_CS +#define MRV_SMIA_IMSC_ERR_CS_MASK 0x00000008U +#define MRV_SMIA_IMSC_ERR_CS_SHIFT 3U +/*! Slice: IMSC_ERR_PROTOCOL:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_ERR_PROTOCOL +#define MRV_SMIA_IMSC_ERR_PROTOCOL_MASK 0x00000004U +#define MRV_SMIA_IMSC_ERR_PROTOCOL_SHIFT 2U +/*! Slice: IMSC_EMB_DATA_OVFLW:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_EMB_DATA_OVFLW +#define MRV_SMIA_IMSC_EMB_DATA_OVFLW_MASK 0x00000002U +#define MRV_SMIA_IMSC_EMB_DATA_OVFLW_SHIFT 1U +/*! Slice: IMSC_FRAME_END:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_SMIA_IMSC_FRAME_END +#define MRV_SMIA_IMSC_FRAME_END_MASK 0x00000001U +#define MRV_SMIA_IMSC_FRAME_END_SHIFT 0U +/*! Register: smia_ris: Raw interrupt status (0x0000000c)*/ +/*! Slice: RIS_FIFO_FILL_LEVEL:*/ +/*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */ +#define MRV_SMIA_RIS_FIFO_FILL_LEVEL +#define MRV_SMIA_RIS_FIFO_FILL_LEVEL_MASK 0x00000020U +#define MRV_SMIA_RIS_FIFO_FILL_LEVEL_SHIFT 5U +/*! Slice: RIS_SYNC_FIFO_OVFLW:*/ +/*! Sync fifo overflow error */ +#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW +#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW_MASK 0x00000010U +#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW_SHIFT 4U +/*! Slice: RIS_ERR_CS:*/ +/*! Checksum error */ +#define MRV_SMIA_RIS_ERR_CS +#define MRV_SMIA_RIS_ERR_CS_MASK 0x00000008U +#define MRV_SMIA_RIS_ERR_CS_SHIFT 3U +/*! Slice: RIS_ERR_PROTOCOL:*/ +/*! Protocol error */ +#define MRV_SMIA_RIS_ERR_PROTOCOL +#define MRV_SMIA_RIS_ERR_PROTOCOL_MASK 0x00000004U +#define MRV_SMIA_RIS_ERR_PROTOCOL_SHIFT 2U +/*! Slice: RIS_EMB_DATA_OVFLW:*/ +/*! Embedded data fifo overflow error */ +#define MRV_SMIA_RIS_EMB_DATA_OVFLW +#define MRV_SMIA_RIS_EMB_DATA_OVFLW_MASK 0x00000002U +#define MRV_SMIA_RIS_EMB_DATA_OVFLW_SHIFT 1U +/*! Slice: RIS_FRAME_END:*/ +/*! Frame end reached */ +#define MRV_SMIA_RIS_FRAME_END +#define MRV_SMIA_RIS_FRAME_END_MASK 0x00000001U +#define MRV_SMIA_RIS_FRAME_END_SHIFT 0U +/*! Register: smia_mis: Masked interrupt status (0x00000010)*/ +/*! Slice: MIS_FIFO_FILL_LEVEL:*/ +/*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */ +#define MRV_SMIA_MIS_FIFO_FILL_LEVEL +#define MRV_SMIA_MIS_FIFO_FILL_LEVEL_MASK 0x00000020U +#define MRV_SMIA_MIS_FIFO_FILL_LEVEL_SHIFT 5U +/*! Slice: MIS_SYNC_FIFO_OVFLW:*/ +/*! Sync fifo overflow error */ +#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW +#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW_MASK 0x00000010U +#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW_SHIFT 4U +/*! Slice: MIS_ERR_CS:*/ +/*! Checksum error */ +#define MRV_SMIA_MIS_ERR_CS +#define MRV_SMIA_MIS_ERR_CS_MASK 0x00000008U +#define MRV_SMIA_MIS_ERR_CS_SHIFT 3U +/*! Slice: MIS_ERR_PROTOCOL:*/ +/*! Protocol error */ +#define MRV_SMIA_MIS_ERR_PROTOCOL +#define MRV_SMIA_MIS_ERR_PROTOCOL_MASK 0x00000004U +#define MRV_SMIA_MIS_ERR_PROTOCOL_SHIFT 2U +/*! Slice: MIS_EMB_DATA_OVFLW:*/ +/*! Embedded data fifo overflow error */ +#define MRV_SMIA_MIS_EMB_DATA_OVFLW +#define MRV_SMIA_MIS_EMB_DATA_OVFLW_MASK 0x00000002U +#define MRV_SMIA_MIS_EMB_DATA_OVFLW_SHIFT 1U +/*! Slice: MIS_FRAME_END:*/ +/*! Frame end reached */ +#define MRV_SMIA_MIS_FRAME_END +#define MRV_SMIA_MIS_FRAME_END_MASK 0x00000001U +#define MRV_SMIA_MIS_FRAME_END_SHIFT 0U +/*! Register: smia_icr: Interrupt clear register (0x00000014)*/ +/*! Slice: ICR_FIFO_FILL_LEVEL:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_FIFO_FILL_LEVEL +#define MRV_SMIA_ICR_FIFO_FILL_LEVEL_MASK 0x00000020U +#define MRV_SMIA_ICR_FIFO_FILL_LEVEL_SHIFT 5U +/*! Slice: ICR_SYNC_FIFO_OVFLW:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW +#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW_MASK 0x00000010U +#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW_SHIFT 4U +/*! Slice: ICR_ERR_CS:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_ERR_CS +#define MRV_SMIA_ICR_ERR_CS_MASK 0x00000008U +#define MRV_SMIA_ICR_ERR_CS_SHIFT 3U +/*! Slice: ICR_ERR_PROTOCOL:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_ERR_PROTOCOL +#define MRV_SMIA_ICR_ERR_PROTOCOL_MASK 0x00000004U +#define MRV_SMIA_ICR_ERR_PROTOCOL_SHIFT 2U +/*! Slice: ICR_EMB_DATA_OVFLW:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_EMB_DATA_OVFLW +#define MRV_SMIA_ICR_EMB_DATA_OVFLW_MASK 0x00000002U +#define MRV_SMIA_ICR_EMB_DATA_OVFLW_SHIFT 1U +/*! Slice: ICR_FRAME_END:*/ +/*! Write '1': clear interrupt; Write '0': no effect */ +#define MRV_SMIA_ICR_FRAME_END +#define MRV_SMIA_ICR_FRAME_END_MASK 0x00000001U +#define MRV_SMIA_ICR_FRAME_END_SHIFT 0U +/*! Register: smia_isr: Interrupt set register (0x00000018)*/ +/*! Slice: ISR_FIFO_FILL_LEVEL:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_FIFO_FILL_LEVEL +#define MRV_SMIA_ISR_FIFO_FILL_LEVEL_MASK 0x00000020U +#define MRV_SMIA_ISR_FIFO_FILL_LEVEL_SHIFT 5U +/*! Slice: ISR_SYNC_FIFO_OVFLW:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW +#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW_MASK 0x00000010U +#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW_SHIFT 4U +/*! Slice: ISR_ERR_CS:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_ERR_CS +#define MRV_SMIA_ISR_ERR_CS_MASK 0x00000008U +#define MRV_SMIA_ISR_ERR_CS_SHIFT 3U +/*! Slice: ISR_ERR_PROTOCOL:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_ERR_PROTOCOL +#define MRV_SMIA_ISR_ERR_PROTOCOL_MASK 0x00000004U +#define MRV_SMIA_ISR_ERR_PROTOCOL_SHIFT 2U +/*! Slice: ISR_EMB_DATA_OVFLW:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_EMB_DATA_OVFLW +#define MRV_SMIA_ISR_EMB_DATA_OVFLW_MASK 0x00000002U +#define MRV_SMIA_ISR_EMB_DATA_OVFLW_SHIFT 1U +/*! Slice: ISR_FRAME_END:*/ +/*! Write '1': set interrupt; Write '0': no effect */ +#define MRV_SMIA_ISR_FRAME_END +#define MRV_SMIA_ISR_FRAME_END_MASK 0x00000001U +#define MRV_SMIA_ISR_FRAME_END_SHIFT 0U +/*! Register: smia_data_format_sel: data format selector register (0x0000001c)*/ +/*! Slice: DATA_FORMAT_SEL:*/ +/*! data format selector:*/ +/* 0x0: YUV 422 */ +/* 0x1: YUV 420 */ +/* 0x4: RGB 444 */ +/* 0x5: RGB 565 */ +/* 0x6: RGB 888 */ +/* 0x8: RAW 6 */ +/* 0x9: RAW 7 */ +/* 0xA: RAW 8 */ +/* 0xB: RAW 10 */ +/* 0xC: RAW 12 */ +/* 0xD: RAW 8-bit to 10-bit decompression */ +/* 0xF: compressed */ +/* 0x2, 0x3, 0x7, 0xE: reserved, no output */ +#define MRV_SMIA_DATA_FORMAT_SEL +#define MRV_SMIA_DATA_FORMAT_SEL_MASK 0x0000000FU +#define MRV_SMIA_DATA_FORMAT_SEL_SHIFT 0U +/*! Register: smia_sof_emb_data_lines: start of frame embedded data lines register (0x00000020)*/ +/*! Slice: SOF_EMB_DATA_LINES:*/ +/*! number of embedded data lines at frame start */ +#define MRV_SMIA_SOF_EMB_DATA_LINES +#define MRV_SMIA_SOF_EMB_DATA_LINES_MASK 0x00000007U +#define MRV_SMIA_SOF_EMB_DATA_LINES_SHIFT 0U +/*! Register: smia_emb_hstart: embedded data hstart register (0x00000024)*/ +/*! Slice: EMB_HSTART:*/ +/*! horizontal start position of captured embedded data.*/ +/* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/ +#define MRV_SMIA_EMB_HSTART +#define MRV_SMIA_EMB_HSTART_MASK 0x00007FFCU +#define MRV_SMIA_EMB_HSTART_SHIFT 2U +/*! Register: smia_emb_hsize: embedded data hsize register (0x00000028)*/ +/*! Slice: EMB_HSIZE:*/ +/*! number of captured embedded data dwords per line */ +/* '0' means no capturing of embedded data.*/ +/* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/ +#define MRV_SMIA_EMB_HSIZE +#define MRV_SMIA_EMB_HSIZE_MASK 0x00007FFCU +#define MRV_SMIA_EMB_HSIZE_SHIFT 2U +/*! Register: smia_emb_vstart: embedded data vstart register (0x0000002c)*/ +/*! Slice: EMB_VSTART:*/ +/*! start line of embedded data extraction.*/ +/* '0' means no capturing of embedded data */ +#define MRV_SMIA_EMB_VSTART +#define MRV_SMIA_EMB_VSTART_MASK 0x00003FFFU +#define MRV_SMIA_EMB_VSTART_SHIFT 0U +/*! Register: smia_num_lines: image data lines register (0x00000030)*/ +/*! Slice: NUM_LINES:*/ +/*! number of image data lines per frame */ +#define MRV_SMIA_NUM_LINES +#define MRV_SMIA_NUM_LINES_MASK 0x00003FFFU +#define MRV_SMIA_NUM_LINES_SHIFT 0U +/*! Register: smia_emb_data_fifo: Embedded Data Fifo (0x00000034)*/ +/*! Slice: EMB_DATA_FIFO:*/ +/*! lowest 4 bytes in embedded data fifo;*/ +/* reading increments fifo read pointer.*/ +/* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/ +#define MRV_SMIA_EMB_DATA_FIFO +#define MRV_SMIA_EMB_DATA_FIFO_MASK 0xFFFFFFFFU +#define MRV_SMIA_EMB_DATA_FIFO_SHIFT 0U +/*! Register: smia_fifo_fill_level: Embedded Data FIFO Fill Level (0x00000038)*/ +/*! Slice: FIFO_FILL_LEVEL:*/ +/*! FIFO level in dwords for triggering the fill level interrupt.*/ +/* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/ +#define MRV_SMIA_FIFO_FILL_LEVEL +#define MRV_SMIA_FIFO_FILL_LEVEL_MASK 0x000003FFU +#define MRV_SMIA_FIFO_FILL_LEVEL_SHIFT 0U +/*! Register: mipi_ctrl: global control register (0x00000000)*/ +/*! Slice: S_ENABLE_CLK:*/ +/*! Sensor clock lane enable signal. This register is directly connected to the output port "s_enableclk".*/ +/* '1': enable sensor clock lane (DEFAULT)*/ +/* '0': disable sensor clock lane */ +#define MRV_MIPI_S_ENABLE_CLK +#define MRV_MIPI_S_ENABLE_CLK_MASK 0x00040000U +#define MRV_MIPI_S_ENABLE_CLK_SHIFT 18U +/*! Slice: ERR_SOT_SYNC_HS_SKIP:*/ +/*! 1: data within the current transmission is skipped if ErrSotSyncHS is detected (default)*/ +/* 0: ErrSotSyncHS does not affect transmission */ +#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP +#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP_MASK 0x00020000U +#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP_SHIFT 17U +/*! Slice: ERR_SOT_HS_SKIP:*/ +/*! 1: data within the current transmission is skipped if ErrSotHS is detected */ +/* 0: ErrSotHS does not affect transmission (default)*/ +#define MRV_MIPI_ERR_SOT_HS_SKIP +#define MRV_MIPI_ERR_SOT_HS_SKIP_MASK 0x00010000U +#define MRV_MIPI_ERR_SOT_HS_SKIP_SHIFT 16U +/*! Slice: NUM_LANES:*/ +/*! 00: Lane 1 is used */ +/* 01: Lanes 1 and 2 are used */ +/* 10: Lanes 1, 2 and 3 are used */ +/* 11: Lanes 1, 2, 3 and 4 are used (default)*/ +#define MRV_MIPI_NUM_LANES +#define MRV_MIPI_NUM_LANES_MASK 0x00003000U +#define MRV_MIPI_NUM_LANES_SHIFT 12U +/*! Slice: SHUTDOWN_LANE:*/ +/*! Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown[n-1:0] where n denotes the lane number 1..4 */ +#define MRV_MIPI_SHUTDOWN_LANE +#define MRV_MIPI_SHUTDOWN_LANE_MASK 0x00000F00U +#define MRV_MIPI_SHUTDOWN_LANE_SHIFT 8U +/*! Slice: FLUSH_FIFO:*/ +/*! writing '1' resets the write- and read pointers of the additional data fifo, reading returns the status of the flush_fifo bit. This bit must be reset by software.*/ +#define MRV_MIPI_FLUSH_FIFO +#define MRV_MIPI_FLUSH_FIFO_MASK 0x00000002U +#define MRV_MIPI_FLUSH_FIFO_SHIFT 1U +/*! Slice: OUTPUT_ENA:*/ +/*! 1: output to add data fifo and to output interface is enabled */ +/* 0: output is disabled */ +#define MRV_MIPI_OUTPUT_ENA +#define MRV_MIPI_OUTPUT_ENA_MASK 0x00000001U +#define MRV_MIPI_OUTPUT_ENA_SHIFT 0U +/*! Register: mipi_status: global status register (0x00000004)*/ +/*! Slice: S_ULP_ACTIVE_NOT_CLK:*/ +/*! sensor clock lane is in ULP state. This register is directly connected to the synchronized input signal "s_ulpsactivenotclk"*/ +#define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK +#define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK_MASK 0x00002000U +#define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK_SHIFT 13U +/*! Slice: S_STOPSTATE_CLK:*/ +/*! sensor clock lane is in stopstate. This register is directly connected to the synchronized input signal "s_stopstateclk"*/ +#define MRV_MIPI_S_STOPSTATE_CLK +#define MRV_MIPI_S_STOPSTATE_CLK_MASK 0x00001000U +#define MRV_MIPI_S_STOPSTATE_CLK_SHIFT 12U +/*! Slice: STOPSTATE:*/ +/*! Data Lane is in stopstate. This register is directly connected to the synchronized input signal stopstate[n-1:0] where n denotes the lane number 1..4 */ +#define MRV_MIPI_STOPSTATE +#define MRV_MIPI_STOPSTATE_MASK 0x00000F00U +#define MRV_MIPI_STOPSTATE_SHIFT 8U +/*! Slice: ADD_DATA_AVAIL:*/ +/*! 1: additional data fifo contains data */ +/* 0: additional data fifo is empty */ +#define MRV_MIPI_ADD_DATA_AVAIL +#define MRV_MIPI_ADD_DATA_AVAIL_MASK 0x00000001U +#define MRV_MIPI_ADD_DATA_AVAIL_SHIFT 0U +/*! Register: mipi_imsc: Interrupt mask (0x00000008)*/ +/*! Slice: IMSC_GEN_SHORT_PACK:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_GEN_SHORT_PACK +#define MRV_MIPI_IMSC_GEN_SHORT_PACK_MASK 0x08000000U +#define MRV_MIPI_IMSC_GEN_SHORT_PACK_SHIFT 27U +/*! Slice: IMSC_ADD_DATA_FILL_LEVEL:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK 0x04000000U +#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_SHIFT 26U +/*! Slice: IMSC_ADD_DATA_OVFLW:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ADD_DATA_OVFLW +#define MRV_MIPI_IMSC_ADD_DATA_OVFLW_MASK 0x02000000U +#define MRV_MIPI_IMSC_ADD_DATA_OVFLW_SHIFT 25U +/*! Slice: IMSC_FRAME_END:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_FRAME_END +#define MRV_MIPI_IMSC_FRAME_END_MASK 0x01000000U +#define MRV_MIPI_IMSC_FRAME_END_SHIFT 24U +/*! Slice: IMSC_ERR_CS:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ERR_CS +#define MRV_MIPI_IMSC_ERR_CS_MASK 0x00800000U +#define MRV_MIPI_IMSC_ERR_CS_SHIFT 23U +/*! Slice: IMSC_ERR_ECC1:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ERR_ECC1 +#define MRV_MIPI_IMSC_ERR_ECC1_MASK 0x00400000U +#define MRV_MIPI_IMSC_ERR_ECC1_SHIFT 22U +/*! Slice: IMSC_ERR_ECC2:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ERR_ECC2 +#define MRV_MIPI_IMSC_ERR_ECC2_MASK 0x00200000U +#define MRV_MIPI_IMSC_ERR_ECC2_SHIFT 21U +/*! Slice: IMSC_ERR_PROTOCOL:*/ +/*! enable interrupt (1) or mask out (0)*/ +#define MRV_MIPI_IMSC_ERR_PROTOCOL +#define MRV_MIPI_IMSC_ERR_PROTOCOL_MASK 0x00100000U +#define MRV_MIPI_IMSC_ERR_PROTOCOL_SHIFT 20U +/*! Slice: IMSC_ERR_CONTROL:*/ +/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#define MRV_MIPI_IMSC_ERR_CONTROL +#define MRV_MIPI_IMSC_ERR_CONTROL_MASK 0x000F0000U +#define MRV_MIPI_IMSC_ERR_CONTROL_SHIFT 16U +/*! Slice: IMSC_ERR_EOT_SYNC:*/ +/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#define MRV_MIPI_IMSC_ERR_EOT_SYNC +#define MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK 0x0000F000U +#define MRV_MIPI_IMSC_ERR_EOT_SYNC_SHIFT 12U +/*! Slice: IMSC_ERR_SOT_SYNC:*/ +/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#define MRV_MIPI_IMSC_ERR_SOT_SYNC +#define MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK 0x00000F00U +#define MRV_MIPI_IMSC_ERR_SOT_SYNC_SHIFT 8U +/*! Slice: IMSC_ERR_SOT:*/ +/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#define MRV_MIPI_IMSC_ERR_SOT +#define MRV_MIPI_IMSC_ERR_SOT_MASK 0x000000F0U +#define MRV_MIPI_IMSC_ERR_SOT_SHIFT 4U +/*! Slice: IMSC_SYNC_FIFO_OVFLW:*/ +/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/ +#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW +#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK 0x0000000FU +#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_SHIFT 0U +/*! Register: mipi_ris: Raw interrupt status (0x0000000c)*/ +/*! Slice: RIS_GEN_SHORT_PACK:*/ +/*! generic short packet was received (only available in version 2 of MIPI interface)*/ + /**/ +/* When this interrupt is cleared, all the bits of the MIPI_GEN_SHORT_DT status register are cleared as well; Setting of this interrupt via MIPI_ISR register will set all the bits of the MIPI_GEN_SHORT_DT register.*/ +#define MRV_MIPI_RIS_GEN_SHORT_PACK +#define MRV_MIPI_RIS_GEN_SHORT_PACK_MASK 0x08000000U +#define MRV_MIPI_RIS_GEN_SHORT_PACK_SHIFT 27U +/*! Slice: RIS_ADD_DATA_FILL_LEVEL:*/ +/*! Programmed fill level was reached; will be raised as long as the fill level is greater than the programmed value */ +#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK 0x04000000U +#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_SHIFT 26U +/*! Slice: RIS_ADD_DATA_OVFLW:*/ +/*! additional data fifo overflow occurred */ +#define MRV_MIPI_RIS_ADD_DATA_OVFLW +#define MRV_MIPI_RIS_ADD_DATA_OVFLW_MASK 0x02000000U +#define MRV_MIPI_RIS_ADD_DATA_OVFLW_SHIFT 25U +/*! Slice: RIS_FRAME_END:*/ +/*! frame end send to output interface */ +#define MRV_MIPI_RIS_FRAME_END +#define MRV_MIPI_RIS_FRAME_END_MASK 0x01000000U +#define MRV_MIPI_RIS_FRAME_END_SHIFT 24U +/*! Slice: RIS_ERR_CS:*/ +/*! checksum error occurred */ +#define MRV_MIPI_RIS_ERR_CS +#define MRV_MIPI_RIS_ERR_CS_MASK 0x00800000U +#define MRV_MIPI_RIS_ERR_CS_SHIFT 23U +/*! Slice: RIS_ERR_ECC1:*/ +/*! 1-bit ecc error occurred */ +#define MRV_MIPI_RIS_ERR_ECC1 +#define MRV_MIPI_RIS_ERR_ECC1_MASK 0x00400000U +#define MRV_MIPI_RIS_ERR_ECC1_SHIFT 22U +/*! Slice: RIS_ERR_ECC2:*/ +/*! 2-bit ecc error occurred */ +#define MRV_MIPI_RIS_ERR_ECC2 +#define MRV_MIPI_RIS_ERR_ECC2_MASK 0x00200000U +#define MRV_MIPI_RIS_ERR_ECC2_SHIFT 21U +/*! Slice: RIS_ERR_PROTOCOL:*/ +/*! packet start detected within current packet */ +#define MRV_MIPI_RIS_ERR_PROTOCOL +#define MRV_MIPI_RIS_ERR_PROTOCOL_MASK 0x00100000U +#define MRV_MIPI_RIS_ERR_PROTOCOL_SHIFT 20U +/*! Slice: RIS_ERR_CONTROL:*/ +/*! PPI interface control error occured, one bit for each lane */ +#define MRV_MIPI_RIS_ERR_CONTROL +#define MRV_MIPI_RIS_ERR_CONTROL_MASK 0x000F0000U +#define MRV_MIPI_RIS_ERR_CONTROL_SHIFT 16U +/*! Slice: RIS_ERR_EOT_SYNC:*/ +/*! PPI interface eot sync error occured, one bit for each lane */ +#define MRV_MIPI_RIS_ERR_EOT_SYNC +#define MRV_MIPI_RIS_ERR_EOT_SYNC_MASK 0x0000F000U +#define MRV_MIPI_RIS_ERR_EOT_SYNC_SHIFT 12U +/*! Slice: RIS_ERR_SOT_SYNC:*/ +/*! PPI interface sot sync error occured, one bit for each lane */ +#define MRV_MIPI_RIS_ERR_SOT_SYNC +#define MRV_MIPI_RIS_ERR_SOT_SYNC_MASK 0x00000F00U +#define MRV_MIPI_RIS_ERR_SOT_SYNC_SHIFT 8U +/*! Slice: RIS_ERR_SOT:*/ +/*! PPI interface sot error occured, one bit for each lane */ +#define MRV_MIPI_RIS_ERR_SOT +#define MRV_MIPI_RIS_ERR_SOT_MASK 0x000000F0U +#define MRV_MIPI_RIS_ERR_SOT_SHIFT 4U +/*! Slice: RIS_SYNC_FIFO_OVFLW:*/ +/*! synchronization fifo overflow occurred, one bit for each lane */ +#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW +#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK 0x0000000FU +#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_SHIFT 0U +/*! Register: mipi_mis: Masked interrupt status (0x00000010)*/ +/*! Slice: MIS_GEN_SHORT_PACK:*/ +/*! generic short packet was received (only available in version 2 of MIPI interface)*/ +#define MRV_MIPI_MIS_GEN_SHORT_PACK +#define MRV_MIPI_MIS_GEN_SHORT_PACK_MASK 0x08000000U +#define MRV_MIPI_MIS_GEN_SHORT_PACK_SHIFT 27U +/*! Slice: MIS_ADD_DATA_FILL_LEVEL:*/ +/*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */ +#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK 0x04000000U +#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_SHIFT 26U +/*! Slice: MIS_ADD_DATA_OVFLW:*/ +/*! additional data fifo overflow */ +#define MRV_MIPI_MIS_ADD_DATA_OVFLW +#define MRV_MIPI_MIS_ADD_DATA_OVFLW_MASK 0x02000000U +#define MRV_MIPI_MIS_ADD_DATA_OVFLW_SHIFT 25U +/*! Slice: MIS_FRAME_END:*/ +/*! frame end send to output interface */ +#define MRV_MIPI_MIS_FRAME_END +#define MRV_MIPI_MIS_FRAME_END_MASK 0x01000000U +#define MRV_MIPI_MIS_FRAME_END_SHIFT 24U +/*! Slice: MIS_ERR_CS:*/ +/*! checksum error occurred */ +#define MRV_MIPI_MIS_ERR_CS +#define MRV_MIPI_MIS_ERR_CS_MASK 0x00800000U +#define MRV_MIPI_MIS_ERR_CS_SHIFT 23U +/*! Slice: MIS_ERR_ECC1:*/ +/*! 1-bit ecc error occurred */ +#define MRV_MIPI_MIS_ERR_ECC1 +#define MRV_MIPI_MIS_ERR_ECC1_MASK 0x00400000U +#define MRV_MIPI_MIS_ERR_ECC1_SHIFT 22U +/*! Slice: MIS_ERR_ECC2:*/ +/*! 2-bit ecc error occurred */ +#define MRV_MIPI_MIS_ERR_ECC2 +#define MRV_MIPI_MIS_ERR_ECC2_MASK 0x00200000U +#define MRV_MIPI_MIS_ERR_ECC2_SHIFT 21U +/*! Slice: MIS_ERR_PROTOCOL:*/ +/*! packet start detected within current packet */ +#define MRV_MIPI_MIS_ERR_PROTOCOL +#define MRV_MIPI_MIS_ERR_PROTOCOL_MASK 0x00100000U +#define MRV_MIPI_MIS_ERR_PROTOCOL_SHIFT 20U +/*! Slice: MIS_ERR_CONTROL:*/ +/*! PPI interface control error occured, one bit for each lane */ +#define MRV_MIPI_MIS_ERR_CONTROL +#define MRV_MIPI_MIS_ERR_CONTROL_MASK 0x000F0000U +#define MRV_MIPI_MIS_ERR_CONTROL_SHIFT 16U +/*! Slice: MIS_ERR_EOT_SYNC:*/ +/*! PPI interface eot sync error occured, one bit for each lane */ +#define MRV_MIPI_MIS_ERR_EOT_SYNC +#define MRV_MIPI_MIS_ERR_EOT_SYNC_MASK 0x0000F000U +#define MRV_MIPI_MIS_ERR_EOT_SYNC_SHIFT 12U +/*! Slice: MIS_ERR_SOT_SYNC:*/ +/*! PPI interface sot sync error occured, one bit for each lane */ +#define MRV_MIPI_MIS_ERR_SOT_SYNC +#define MRV_MIPI_MIS_ERR_SOT_SYNC_MASK 0x00000F00U +#define MRV_MIPI_MIS_ERR_SOT_SYNC_SHIFT 8U +/*! Slice: MIS_ERR_SOT:*/ +/*! PPI interface sot error occured, one bit for each lane */ +#define MRV_MIPI_MIS_ERR_SOT +#define MRV_MIPI_MIS_ERR_SOT_MASK 0x000000F0U +#define MRV_MIPI_MIS_ERR_SOT_SHIFT 4U +/*! Slice: MIS_SYNC_FIFO_OVFLW:*/ +/*! synchronization fifo overflow occurred, one bit for each lane */ +#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW +#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK 0x0000000FU +#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_SHIFT 0U +/*! Register: mipi_icr: Interrupt clear register (0x00000014)*/ +/*! Slice: ICR_GEN_SHORT_PACK:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_GEN_SHORT_PACK +#define MRV_MIPI_ICR_GEN_SHORT_PACK_MASK 0x08000000U +#define MRV_MIPI_ICR_GEN_SHORT_PACK_SHIFT 27U +/*! Slice: ICR_ADD_DATA_FILL_LEVEL:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK 0x04000000U +#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_SHIFT 26U +/*! Slice: ICR_ADD_DATA_OVFLW:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ADD_DATA_OVFLW +#define MRV_MIPI_ICR_ADD_DATA_OVFLW_MASK 0x02000000U +#define MRV_MIPI_ICR_ADD_DATA_OVFLW_SHIFT 25U +/*! Slice: ICR_FRAME_END:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_FRAME_END +#define MRV_MIPI_ICR_FRAME_END_MASK 0x01000000U +#define MRV_MIPI_ICR_FRAME_END_SHIFT 24U +/*! Slice: ICR_ERR_CS:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ERR_CS +#define MRV_MIPI_ICR_ERR_CS_MASK 0x00800000U +#define MRV_MIPI_ICR_ERR_CS_SHIFT 23U +/*! Slice: ICR_ERR_ECC1:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ERR_ECC1 +#define MRV_MIPI_ICR_ERR_ECC1_MASK 0x00400000U +#define MRV_MIPI_ICR_ERR_ECC1_SHIFT 22U +/*! Slice: ICR_ERR_ECC2:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ERR_ECC2 +#define MRV_MIPI_ICR_ERR_ECC2_MASK 0x00200000U +#define MRV_MIPI_ICR_ERR_ECC2_SHIFT 21U +/*! Slice: ICR_ERR_PROTOCOL:*/ +/*! 1: clear register; 0: nothing happens */ +#define MRV_MIPI_ICR_ERR_PROTOCOL +#define MRV_MIPI_ICR_ERR_PROTOCOL_MASK 0x00100000U +#define MRV_MIPI_ICR_ERR_PROTOCOL_SHIFT 20U +/*! Slice: ICR_ERR_CONTROL:*/ +/*! 1: clear register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ICR_ERR_CONTROL +#define MRV_MIPI_ICR_ERR_CONTROL_MASK 0x000F0000U +#define MRV_MIPI_ICR_ERR_CONTROL_SHIFT 16U +/*! Slice: ICR_ERR_EOT_SYNC:*/ +/*! 1: clear register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ICR_ERR_EOT_SYNC +#define MRV_MIPI_ICR_ERR_EOT_SYNC_MASK 0x0000F000U +#define MRV_MIPI_ICR_ERR_EOT_SYNC_SHIFT 12U +/*! Slice: ICR_ERR_SOT_SYNC:*/ +/*! 1: clear register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ICR_ERR_SOT_SYNC +#define MRV_MIPI_ICR_ERR_SOT_SYNC_MASK 0x00000F00U +#define MRV_MIPI_ICR_ERR_SOT_SYNC_SHIFT 8U +/*! Slice: ICR_ERR_SOT:*/ +/*! 1: clear register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ICR_ERR_SOT +#define MRV_MIPI_ICR_ERR_SOT_MASK 0x000000F0U +#define MRV_MIPI_ICR_ERR_SOT_SHIFT 4U +/*! Slice: ICR_SYNC_FIFO_OVFLW:*/ +/*! 1: clear register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW +#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK 0x0000000FU +#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_SHIFT 0U +/*! Register: mipi_isr: Interrupt set register (0x00000018)*/ +/*! Slice: ISR_GEN_SHORT_PACK:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_GEN_SHORT_PACK +#define MRV_MIPI_ISR_GEN_SHORT_PACK_MASK 0x08000000U +#define MRV_MIPI_ISR_GEN_SHORT_PACK_SHIFT 27U +/*! Slice: ISR_ADD_DATA_FILL_LEVEL:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK 0x04000000U +#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_SHIFT 26U +/*! Slice: ISR_ADD_DATA_OVFLW:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ADD_DATA_OVFLW +#define MRV_MIPI_ISR_ADD_DATA_OVFLW_MASK 0x02000000U +#define MRV_MIPI_ISR_ADD_DATA_OVFLW_SHIFT 25U +/*! Slice: ISR_FRAME_END:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_FRAME_END +#define MRV_MIPI_ISR_FRAME_END_MASK 0x01000000U +#define MRV_MIPI_ISR_FRAME_END_SHIFT 24U +/*! Slice: ISR_ERR_CS:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ERR_CS +#define MRV_MIPI_ISR_ERR_CS_MASK 0x00800000U +#define MRV_MIPI_ISR_ERR_CS_SHIFT 23U +/*! Slice: ISR_ERR_ECC1:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ERR_ECC1 +#define MRV_MIPI_ISR_ERR_ECC1_MASK 0x00400000U +#define MRV_MIPI_ISR_ERR_ECC1_SHIFT 22U +/*! Slice: ISR_ERR_ECC2:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ERR_ECC2 +#define MRV_MIPI_ISR_ERR_ECC2_MASK 0x00200000U +#define MRV_MIPI_ISR_ERR_ECC2_SHIFT 21U +/*! Slice: ISR_ERR_PROTOCOL:*/ +/*! 1: set register; 0: nothing happens */ +#define MRV_MIPI_ISR_ERR_PROTOCOL +#define MRV_MIPI_ISR_ERR_PROTOCOL_MASK 0x00100000U +#define MRV_MIPI_ISR_ERR_PROTOCOL_SHIFT 20U +/*! Slice: ISR_ERR_CONTROL:*/ +/*! 1: set register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ISR_ERR_CONTROL +#define MRV_MIPI_ISR_ERR_CONTROL_MASK 0x000F0000U +#define MRV_MIPI_ISR_ERR_CONTROL_SHIFT 16U +/*! Slice: ISR_ERR_EOT_SYNC:*/ +/*! 1: set register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ISR_ERR_EOT_SYNC +#define MRV_MIPI_ISR_ERR_EOT_SYNC_MASK 0x0000F000U +#define MRV_MIPI_ISR_ERR_EOT_SYNC_SHIFT 12U +/*! Slice: ISR_ERR_SOT_SYNC:*/ +/*! 1: set register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ISR_ERR_SOT_SYNC +#define MRV_MIPI_ISR_ERR_SOT_SYNC_MASK 0x00000F00U +#define MRV_MIPI_ISR_ERR_SOT_SYNC_SHIFT 8U +/*! Slice: ISR_ERR_SOT:*/ +/*! 1: set register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ISR_ERR_SOT +#define MRV_MIPI_ISR_ERR_SOT_MASK 0x000000F0U +#define MRV_MIPI_ISR_ERR_SOT_SHIFT 4U +/*! Slice: ISR_SYNC_FIFO_OVFLW:*/ +/*! 1: set register; 0: nothing happens (one bit for each lane)*/ +#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW +#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK 0x0000000FU +#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_SHIFT 0U +/*! Register: mipi_cur_data_id: Current Data Identifier (0x0000001c)*/ +/*! Slice: VIRTUAL_CHANNEL:*/ +/*! virtual channel of currently received packet */ +#define MRV_MIPI_VIRTUAL_CHANNEL +#define MRV_MIPI_VIRTUAL_CHANNEL_MASK 0x000000C0U +#define MRV_MIPI_VIRTUAL_CHANNEL_SHIFT 6U +/*! Slice: DATA_TYPE:*/ +/*! data type of currently received packet */ +#define MRV_MIPI_DATA_TYPE +#define MRV_MIPI_DATA_TYPE_MASK 0x0000003FU +#define MRV_MIPI_DATA_TYPE_SHIFT 0U +/*! Register: mipi_img_data_sel: Image Data Selector (0x00000020)*/ +/*! Slice: VIRTUAL_CHANNEL_SEL:*/ +/*! virtual channel selector for image data output */ +#define MRV_MIPI_VIRTUAL_CHANNEL_SEL +#define MRV_MIPI_VIRTUAL_CHANNEL_SEL_MASK 0x000000C0U +#define MRV_MIPI_VIRTUAL_CHANNEL_SEL_SHIFT 6U +/*! Slice: DATA_TYPE_SEL:*/ +/*! data type selector for image data output:*/ +/* 0x08...0x0F generic short packets */ +/* 0x12 embedded 8-bit data */ +/* 0x18 YUV 420 8-bit */ +/* 0x19 YUV 420 10-bit */ +/* 0x1A Legacy YUV 420 8-bit */ +/* 0x1C YUV 420 8-bit (CSPS)*/ +/* 0x1D YUV 420 10-bit (CSPS)*/ +/* 0x1E YUV 422 8-bit */ +/* 0x1F YUV 422 10-bit */ +/* 0x20 RGB 444 */ +/* 0x21 RGB 555 */ +/* 0x22 RGB 565 */ +/* 0x23 RGB 666 */ +/* 0x24 RGB 888 */ +/* 0x28 RAW 6 */ +/* 0x29 RAW 7 */ +/* 0x2A RAW 8 */ +/* 0x2B RAW 10 */ +/* 0x2C RAW 12 */ +/* 0x30...0x37 User Defined Byte-based data */ +#define MRV_MIPI_DATA_TYPE_SEL +#define MRV_MIPI_DATA_TYPE_SEL_MASK 0x0000003FU +#define MRV_MIPI_DATA_TYPE_SEL_SHIFT 0U +/*! Register: mipi_add_data_sel_1: Additional Data Selector 1 (0x00000024)*/ +/*! Slice: ADD_DATA_VC_1:*/ +/*! virtual channel selector for additional data output */ +#define MRV_MIPI_ADD_DATA_VC_1 +#define MRV_MIPI_ADD_DATA_VC_1_MASK 0x000000C0U +#define MRV_MIPI_ADD_DATA_VC_1_SHIFT 6U +/*! Slice: ADD_DATA_TYPE_1:*/ +/*! data type selector for additional data output */ +#define MRV_MIPI_ADD_DATA_TYPE_1 +#define MRV_MIPI_ADD_DATA_TYPE_1_MASK 0x0000003FU +#define MRV_MIPI_ADD_DATA_TYPE_1_SHIFT 0U +/*! Register: mipi_add_data_sel_2: Additional Data Selector 2 (0x00000028)*/ +/*! Slice: ADD_DATA_VC_2:*/ +/*! virtual channel selector for additional data output */ +#define MRV_MIPI_ADD_DATA_VC_2 +#define MRV_MIPI_ADD_DATA_VC_2_MASK 0x000000C0U +#define MRV_MIPI_ADD_DATA_VC_2_SHIFT 6U +/*! Slice: ADD_DATA_TYPE_2:*/ +/*! data type selector for additional data output */ +#define MRV_MIPI_ADD_DATA_TYPE_2 +#define MRV_MIPI_ADD_DATA_TYPE_2_MASK 0x0000003FU +#define MRV_MIPI_ADD_DATA_TYPE_2_SHIFT 0U +/*! Register: mipi_add_data_sel_3: Additional Data Selector 3 (0x0000002c)*/ +/*! Slice: ADD_DATA_VC_3:*/ +/*! virtual channel selector for additional data output */ +#define MRV_MIPI_ADD_DATA_VC_3 +#define MRV_MIPI_ADD_DATA_VC_3_MASK 0x000000C0U +#define MRV_MIPI_ADD_DATA_VC_3_SHIFT 6U +/*! Slice: ADD_DATA_TYPE_3:*/ +/*! data type selector for additional data output */ +#define MRV_MIPI_ADD_DATA_TYPE_3 +#define MRV_MIPI_ADD_DATA_TYPE_3_MASK 0x0000003FU +#define MRV_MIPI_ADD_DATA_TYPE_3_SHIFT 0U +/*! Register: mipi_add_data_sel_4: Additional Data Selector 4 (0x00000030)*/ +/*! Slice: ADD_DATA_VC_4:*/ +/*! virtual channel selector for additional data output */ +#define MRV_MIPI_ADD_DATA_VC_4 +#define MRV_MIPI_ADD_DATA_VC_4_MASK 0x000000C0U +#define MRV_MIPI_ADD_DATA_VC_4_SHIFT 6U +/*! Slice: ADD_DATA_TYPE_4:*/ +/*! data type selector for additional data output */ +#define MRV_MIPI_ADD_DATA_TYPE_4 +#define MRV_MIPI_ADD_DATA_TYPE_4_MASK 0x0000003FU +#define MRV_MIPI_ADD_DATA_TYPE_4_SHIFT 0U +/*! Register: mipi_add_data_fifo: Additional Data Fifo (0x00000034)*/ +/*! Slice: ADD_DATA_FIFO:*/ +/*! lowest 4 bytes in additional data fifo;*/ +/* reading increments fifo read pointer.*/ +/* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/ +#define MRV_MIPI_ADD_DATA_FIFO +#define MRV_MIPI_ADD_DATA_FIFO_MASK 0xFFFFFFFFU +#define MRV_MIPI_ADD_DATA_FIFO_SHIFT 0U +/*! Register: mipi_add_data_fill_level: Additional Data FIFO Fill Level (0x00000038)*/ +/*! Slice: ADD_DATA_FILL_LEVEL:*/ +/*! FIFO level in dwords for triggering the FILL_LEVEL interrupt,*/ +/* must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/ +#define MRV_MIPI_ADD_DATA_FILL_LEVEL +#define MRV_MIPI_ADD_DATA_FILL_LEVEL_MASK 0x00001FFFU +#define MRV_MIPI_ADD_DATA_FILL_LEVEL_SHIFT 0U +/*! Register: mipi_compressed_mode: controls processing of compressed raw data types (0x0000003c)*/ +/*! Slice: predictor_sel:*/ +/*! predictor to be used:*/ +/* 0: predictor 1 */ +/* 1: predictor 2 */ +#define MRV_MIPI_PREDICTOR_SEL +#define MRV_MIPI_PREDICTOR_SEL_MASK 0x00000100U +#define MRV_MIPI_PREDICTOR_SEL_SHIFT 8U +/*! Slice: comp_scheme:*/ +/*! data compression scheme:*/ +/* 0: 12–8–12 */ +/* 1: 12–7–12 */ +/* 2: 12–6–12 */ +/* 3: 10–8–10 */ +/* 4: 10–7–10 */ +/* 5: 10–6–10 */ +/* 6..7: reserved */ +#define MRV_MIPI_COMP_SCHEME +#define MRV_MIPI_COMP_SCHEME_MASK 0x00000070U +#define MRV_MIPI_COMP_SCHEME_SHIFT 4U +/*! Slice: compress_en:*/ +/*! 1: enable compressed mode processing */ +/* 0: disable compressed mode */ +#define MRV_MIPI_COMPRESS_EN +#define MRV_MIPI_COMPRESS_EN_MASK 0x00000001U +#define MRV_MIPI_COMPRESS_EN_SHIFT 0U +/*! Register: mipi_frame: frame number from frame start and frame end short packets (0x00000040)*/ +/*! Slice: frame_number_fe:*/ +/*! 16 bit frame number from Frame End (FE) short packet */ +#define MRV_MIPI_FRAME_NUMBER_FE +#define MRV_MIPI_FRAME_NUMBER_FE_MASK 0xFFFF0000U +#define MRV_MIPI_FRAME_NUMBER_FE_SHIFT 16U +/*! Slice: frame_number_fs:*/ +/*! 16 bit frame number from Frame Start (FS) short packet */ +#define MRV_MIPI_FRAME_NUMBER_FS +#define MRV_MIPI_FRAME_NUMBER_FS_MASK 0x0000FFFFU +#define MRV_MIPI_FRAME_NUMBER_FS_SHIFT 0U +/*! Register: mipi_gen_short_dt: data type flags for received generic short packets (0x00000044)*/ +/*! Slice: GEN_SHORT_DT_0xF:*/ +/*! 1: generic short packet of data type 0xF received */ +/* 0: data type 0xF not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XF +#define MRV_MIPI_GEN_SHORT_DT_0XF_MASK 0x00000080U +#define MRV_MIPI_GEN_SHORT_DT_0XF_SHIFT 7U +/*! Slice: GEN_SHORT_DT_0xE:*/ +/*! 1: generic short packet of data type 0xE received */ +/* 0: data type 0xE not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XE +#define MRV_MIPI_GEN_SHORT_DT_0XE_MASK 0x00000040U +#define MRV_MIPI_GEN_SHORT_DT_0XE_SHIFT 6U +/*! Slice: GEN_SHORT_DT_0xD:*/ +/*! 1: generic short packet of data type 0xD received */ +/* 0: data type 0xD not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XD +#define MRV_MIPI_GEN_SHORT_DT_0XD_MASK 0x00000020U +#define MRV_MIPI_GEN_SHORT_DT_0XD_SHIFT 5U +/*! Slice: GEN_SHORT_DT_0xC:*/ +/*! 1: generic short packet of data type 0xC received */ +/* 0: data type 0xC not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XC +#define MRV_MIPI_GEN_SHORT_DT_0XC_MASK 0x00000010U +#define MRV_MIPI_GEN_SHORT_DT_0XC_SHIFT 4U +/*! Slice: GEN_SHORT_DT_0xB:*/ +/*! 1: generic short packet of data type 0xB received */ +/* 0: data type 0xB not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XB +#define MRV_MIPI_GEN_SHORT_DT_0XB_MASK 0x00000008U +#define MRV_MIPI_GEN_SHORT_DT_0XB_SHIFT 3U +/*! Slice: GEN_SHORT_DT_0xA:*/ +/*! 1: generic short packet of data type 0xA received */ +/* 0: data type 0xA not received */ +#define MRV_MIPI_GEN_SHORT_DT_0XA +#define MRV_MIPI_GEN_SHORT_DT_0XA_MASK 0x00000004U +#define MRV_MIPI_GEN_SHORT_DT_0XA_SHIFT 2U +/*! Slice: GEN_SHORT_DT_0x9:*/ +/*! 1: generic short packet of data type 0x9 received */ +/* 0: data type 0x9 not received */ +#define MRV_MIPI_GEN_SHORT_DT_0X9 +#define MRV_MIPI_GEN_SHORT_DT_0X9_MASK 0x00000002U +#define MRV_MIPI_GEN_SHORT_DT_0X9_SHIFT 1U +/*! Slice: GEN_SHORT_DT_0x8:*/ +/*! 1: generic short packet of data type 0x8 received */ +/* 0: data type 0x8 not received */ +#define MRV_MIPI_GEN_SHORT_DT_0X8 +#define MRV_MIPI_GEN_SHORT_DT_0X8_MASK 0x00000001U +#define MRV_MIPI_GEN_SHORT_DT_0X8_SHIFT 0U +/*! Register: mipi_gen_short_8_9: data field for generic short packets of data type 0x8 and 0x9 (0x00000048)*/ +/*! Slice: data_field_9:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0x9 */ +#define MRV_MIPI_DATA_FIELD_9 +#define MRV_MIPI_DATA_FIELD_9_MASK 0xFFFF0000U +#define MRV_MIPI_DATA_FIELD_9_SHIFT 16U +/*! Slice: data_field_8:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0x8 */ +#define MRV_MIPI_DATA_FIELD_8 +#define MRV_MIPI_DATA_FIELD_8_MASK 0x0000FFFFU +#define MRV_MIPI_DATA_FIELD_8_SHIFT 0U +/*! Register: mipi_gen_short_a_b: data field for generic short packets of data type 0xA and 0xB (0x0000004c)*/ +/*! Slice: data_field_B:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xB */ +#define MRV_MIPI_DATA_FIELD_B +#define MRV_MIPI_DATA_FIELD_B_MASK 0xFFFF0000U +#define MRV_MIPI_DATA_FIELD_B_SHIFT 16U +/*! Slice: data_field_A:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xA */ +#define MRV_MIPI_DATA_FIELD_A +#define MRV_MIPI_DATA_FIELD_A_MASK 0x0000FFFFU +#define MRV_MIPI_DATA_FIELD_A_SHIFT 0U +/*! Register: mipi_gen_short_c_d: data field for generic short packets of data type 0xC and 0xD (0x00000050)*/ +/*! Slice: data_field_D:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xD */ +#define MRV_MIPI_DATA_FIELD_D +#define MRV_MIPI_DATA_FIELD_D_MASK 0xFFFF0000U +#define MRV_MIPI_DATA_FIELD_D_SHIFT 16U +/*! Slice: data_field_C:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xC */ +#define MRV_MIPI_DATA_FIELD_C +#define MRV_MIPI_DATA_FIELD_C_MASK 0x0000FFFFU +#define MRV_MIPI_DATA_FIELD_C_SHIFT 0U +/*! Register: mipi_gen_short_e_f: data field for generic short packets of data type 0xE and 0xF (0x00000054)*/ +/*! Slice: data_field_F:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xF */ +#define MRV_MIPI_DATA_FIELD_F +#define MRV_MIPI_DATA_FIELD_F_MASK 0xFFFF0000U +#define MRV_MIPI_DATA_FIELD_F_SHIFT 16U +/*! Slice: data_field_E:*/ +/*! 16 bit user defined data field from last generic short packet of data type 0xE */ +#define MRV_MIPI_DATA_FIELD_E +#define MRV_MIPI_DATA_FIELD_E_MASK 0x0000FFFFU +#define MRV_MIPI_DATA_FIELD_E_SHIFT 0U +/*! Register: isp_afm_ctrl: This is the control register for AF measurement unit (0x00000000)*/ +/*! Slice: afm_en:*/ +/*! AF measurement enable */ +/* 0: AF measurement is disabled */ +/* 1: AF measurement is enabled */ +/* Writing a 1 to this register starts a new measurement and resets the afm_fin (measurement finished) interrupt to 0.*/ +/* As long as the afm_en is 1, the AFM unit calculates new sharpness values for each frame.*/ +#define MRV_AFM_AFM_EN +#define MRV_AFM_AFM_EN_MASK 0x00000001U +#define MRV_AFM_AFM_EN_SHIFT 0U +/*! Register: isp_afm_lt_a: Top Left corner of measure window A (0x00000004)*/ +/*! Slice: a_h_l:*/ +/*! first pixel of window A (horizontal left row), value must be greater or equal 5 */ +#define MRV_AFM_A_H_L +#define MRV_AFM_A_H_L_MASK 0x1FFF0000U +#define MRV_AFM_A_H_L_SHIFT 16U +/*! Slice: a_v_t:*/ +/*! first line of window A (vertical top line), value must be greater or equal 2 */ +#define MRV_AFM_A_V_T +#define MRV_AFM_A_V_T_MASK 0x00001FFFU +#define MRV_AFM_A_V_T_SHIFT 0U +/*! Register: isp_afm_rb_a: Bottom right corner of measure window A (0x00000008)*/ +/*! Slice: a_h_r:*/ +/*! last pixel of window A (horizontal right row)*/ +#define MRV_AFM_A_H_R +#define MRV_AFM_A_H_R_MASK 0x1FFF0000U +#define MRV_AFM_A_H_R_SHIFT 16U +/*! Slice: a_v_b:*/ +/*! last line of window A (vertical bottom line), value must be lower than (number of lines – 2)*/ +#define MRV_AFM_A_V_B +#define MRV_AFM_A_V_B_MASK 0x00001FFFU +#define MRV_AFM_A_V_B_SHIFT 0U +/*! Register: isp_afm_lt_b: Top left corner of measure window B (0x0000000c)*/ +/*! Slice: b_h_l:*/ +/*! first pixel of window B (horizontal left row), value must be greater or equal 5 */ +#define MRV_AFM_B_H_L +#define MRV_AFM_B_H_L_MASK 0x1FFF0000U +#define MRV_AFM_B_H_L_SHIFT 16U +/*! Slice: b_v_t:*/ +/*! first line of window B (vertical top line), value must be greater or equal 2 */ +#define MRV_AFM_B_V_T +#define MRV_AFM_B_V_T_MASK 0x00001FFFU +#define MRV_AFM_B_V_T_SHIFT 0U +/*! Register: isp_afm_rb_b: Bottom right corner of measure window B (0x00000010)*/ +/*! Slice: b_h_r:*/ +/*! last pixel of window B (horizontal right row)*/ +#define MRV_AFM_B_H_R +#define MRV_AFM_B_H_R_MASK 0x1FFF0000U +#define MRV_AFM_B_H_R_SHIFT 16U +/*! Slice: b_v_b:*/ +/*! last line of window B (vertical bottom line), value must be lower than (number of lines – 2)*/ +#define MRV_AFM_B_V_B +#define MRV_AFM_B_V_B_MASK 0x00001FFFU +#define MRV_AFM_B_V_B_SHIFT 0U +/*! Register: isp_afm_lt_c: Top left corner of measure window C (0x00000014)*/ +/*! Slice: c_h_l:*/ +/*! first pixel of window C (horizontal left row), value must be greater or equal 5 */ +#define MRV_AFM_C_H_L +#define MRV_AFM_C_H_L_MASK 0x1FFF0000U +#define MRV_AFM_C_H_L_SHIFT 16U +/*! Slice: c_v_t:*/ +/*! first line of window C (vertical top line), value must be greater or equal 2 */ +#define MRV_AFM_C_V_T +#define MRV_AFM_C_V_T_MASK 0x00001FFFU +#define MRV_AFM_C_V_T_SHIFT 0U +/*! Register: isp_afm_rb_c: Bottom right corner of measure window C (0x00000018)*/ +/*! Slice: c_h_r:*/ +/*! last pixel of window C (horizontal right row)*/ +#define MRV_AFM_C_H_R +#define MRV_AFM_C_H_R_MASK 0x1FFF0000U +#define MRV_AFM_C_H_R_SHIFT 16U +/*! Slice: c_v_b:*/ +/*! last line of window C (vertical bottom line), value must be lower than (number of lines – 2)*/ +#define MRV_AFM_C_V_B +#define MRV_AFM_C_V_B_MASK 0x00001FFFU +#define MRV_AFM_C_V_B_SHIFT 0U +/*! Register: isp_afm_thres: Threshold register (0x0000001c)*/ +/*! Slice: afm_thres:*/ +/*! AF measurement threshold */ +/* This register defines a threshold which can be used for minimizing the influence of noise in the measurement result.*/ +#define MRV_AFM_AFM_THRES +#define MRV_AFM_AFM_THRES_MASK 0x0000FFFFU +#define MRV_AFM_AFM_THRES_SHIFT 0U +/*! Register: isp_afm_var_shift: Variable shift register (0x00000020)*/ +/*! Slice: lum_var_shift:*/ +/*! variable shift for luminance summation */ +/* The lum_var_shift defines the number of bits for the shift operation of the value of the current pixel before summation. The shift operation is used to avoid a luminance sum overflow.*/ +#define MRV_AFM_LUM_VAR_SHIFT +#define MRV_AFM_LUM_VAR_SHIFT_MASK 0x00070000U +#define MRV_AFM_LUM_VAR_SHIFT_SHIFT 16U +/*! Slice: afm_var_shift:*/ +/*! variable shift for AF measurement */ +/* The afm_var_shift defines the number of bits for the shift operation at the end of the calculation chain. The shift operation is used to avoid an AF measurement sum overflow.*/ +#define MRV_AFM_AFM_VAR_SHIFT +#define MRV_AFM_AFM_VAR_SHIFT_MASK 0x00000007U +#define MRV_AFM_AFM_VAR_SHIFT_SHIFT 0U +/*! Register: isp_afm_sum_a: Sharpness Value Status Register of Window A (0x00000024)*/ +/*! Slice: afm_sum_a:*/ +/*! sharpness value of window A */ +#define MRV_AFM_AFM_SUM_A +#define MRV_AFM_AFM_SUM_A_MASK 0xFFFFFFFFU +#define MRV_AFM_AFM_SUM_A_SHIFT 0U +/*! Register: isp_afm_sum_b: Sharpness Value Status Register of Window B (0x00000028)*/ +/*! Slice: afm_sum_b:*/ +/*! sharpness value of window B */ +#define MRV_AFM_AFM_SUM_B +#define MRV_AFM_AFM_SUM_B_MASK 0xFFFFFFFFU +#define MRV_AFM_AFM_SUM_B_SHIFT 0U +/*! Register: isp_afm_sum_c: Sharpness Value Status Register of Window C (0x0000002c)*/ +/*! Slice: afm_sum_c:*/ +/*! sharpness value of window C */ +#define MRV_AFM_AFM_SUM_C +#define MRV_AFM_AFM_SUM_C_MASK 0xFFFFFFFFU +#define MRV_AFM_AFM_SUM_C_SHIFT 0U +/*! Register: isp_afm_lum_a: Luminance Value Status Register of Window A (0x00000030)*/ +/*! Slice: afm_lum_a:*/ +/*! luminance value of window A */ +#define MRV_AFM_AFM_LUM_A +#define MRV_AFM_AFM_LUM_A_MASK 0x00FFFFFFU +#define MRV_AFM_AFM_LUM_A_SHIFT 0U +/*! Register: isp_afm_lum_b: Luminance Value Status Register of Window B (0x00000034)*/ +/*! Slice: afm_lum_b:*/ +/*! luminance value of window B */ +#define MRV_AFM_AFM_LUM_B +#define MRV_AFM_AFM_LUM_B_MASK 0x00FFFFFFU +#define MRV_AFM_AFM_LUM_B_SHIFT 0U +/*! Register: isp_afm_lum_c: Luminance Value Status Register of Window C (0x00000038)*/ +/*! Slice: afm_lum_c:*/ +/*! luminance value of window C */ +#define MRV_AFM_AFM_LUM_C +#define MRV_AFM_AFM_LUM_C_MASK 0x00FFFFFFU +#define MRV_AFM_AFM_LUM_C_SHIFT 0U +/*! Register: isp_lsc_ctrl: Lens shade control (0x00000000)*/ +/*! Slice: lsc_en:*/ +/*! 0: activation request for lens shading correction */ +/* 1: deactivation reqeust for lens shading correction */ +/* Activation/Deactivation is object of a shadowing mechnism. The current status is visible at ISP_LSC_STATUS::lsc_enable_status */ +#define MRV_LSC_LSC_EN +#define MRV_LSC_LSC_EN_MASK 0x00000001U +#define MRV_LSC_LSC_EN_SHIFT 0U +/*! Register: isp_lsc_r_table_addr: Table RAM Address for red component (0x00000004)*/ +/*! Slice: r_ram_addr:*/ +/*! table address in RAM for samples of the R color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +/* Valid addresses are in the range 0 to 152.*/ +#define MRV_LSC_R_RAM_ADDR +#define MRV_LSC_R_RAM_ADDR_MASK 0x000001FFU +#define MRV_LSC_R_RAM_ADDR_SHIFT 0U +/*! Register: isp_lsc_gr_table_addr: Table RAM Address for green (red) component (0x00000008)*/ +/*! Slice: gr_ram_addr:*/ +/*! table address in RAM for samples of the G_R color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +#define MRV_LSC_GR_RAM_ADDR +#define MRV_LSC_GR_RAM_ADDR_MASK 0x000001FFU +#define MRV_LSC_GR_RAM_ADDR_SHIFT 0U +/*! Register: isp_lsc_b_table_addr: Table RAM Address for blue component (0x0000000c)*/ +/*! Slice: b_ram_addr:*/ +/*! table address in RAM for samples of the B color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +#define MRV_LSC_B_RAM_ADDR +#define MRV_LSC_B_RAM_ADDR_MASK 0x000001FFU +#define MRV_LSC_B_RAM_ADDR_SHIFT 0U +/*! Register: isp_lsc_gb_table_addr: Table RAM Address for green (blue) component (0x00000010)*/ +/*! Slice: gb_ram_addr:*/ +/*! table address in RAM for samples of the G_B color component.*/ +/* Will be automatically incremented by each read or write access to the table.*/ +#define MRV_LSC_GB_RAM_ADDR +#define MRV_LSC_GB_RAM_ADDR_MASK 0x000001FFU +#define MRV_LSC_GB_RAM_ADDR_SHIFT 0U +/*! Register: isp_lsc_r_table_data: Sample table red (0x00000014)*/ +/*! Slice: r_sample_1:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_R_SAMPLE_1 +#define MRV_LSC_R_SAMPLE_1_MASK 0x00FFF000U +#define MRV_LSC_R_SAMPLE_1_SHIFT 12U +/*! Slice: r_sample_0:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_R_SAMPLE_0 +#define MRV_LSC_R_SAMPLE_0_MASK 0x00000FFFU +#define MRV_LSC_R_SAMPLE_0_SHIFT 0U +/*! Register: isp_lsc_gr_table_data: Sample table green (red) (0x00000018)*/ +/*! Slice: gr_sample_1:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_GR_SAMPLE_1 +#define MRV_LSC_GR_SAMPLE_1_MASK 0x00FFF000U +#define MRV_LSC_GR_SAMPLE_1_SHIFT 12U +/*! Slice: gr_sample_0:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_GR_SAMPLE_0 +#define MRV_LSC_GR_SAMPLE_0_MASK 0x00000FFFU +#define MRV_LSC_GR_SAMPLE_0_SHIFT 0U +/*! Register: isp_lsc_b_table_data: Sample table blue (0x0000001c)*/ +/*! Slice: b_sample_1:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_B_SAMPLE_1 +#define MRV_LSC_B_SAMPLE_1_MASK 0x00FFF000U +#define MRV_LSC_B_SAMPLE_1_SHIFT 12U +/*! Slice: b_sample_0:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_B_SAMPLE_0 +#define MRV_LSC_B_SAMPLE_0_MASK 0x00000FFFU +#define MRV_LSC_B_SAMPLE_0_SHIFT 0U +/*! Register: isp_lsc_gb_table_data: Sample table green (blue) (0x00000020)*/ +/*! Slice: gb_sample_1:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_GB_SAMPLE_1 +#define MRV_LSC_GB_SAMPLE_1_MASK 0x00FFF000U +#define MRV_LSC_GB_SAMPLE_1_SHIFT 12U +/*! Slice: gb_sample_0:*/ +/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/ +#define MRV_LSC_GB_SAMPLE_0 +#define MRV_LSC_GB_SAMPLE_0_MASK 0x00000FFFU +#define MRV_LSC_GB_SAMPLE_0_SHIFT 0U +/*! Register: isp_lsc_xgrad_01: Gradient table x (0x00000024)*/ +/*! Slice: xgrad_1:*/ +/*! factor for x-gradient calculation of sector 1 */ +#define MRV_LSC_XGRAD_1 +#define MRV_LSC_XGRAD_1_MASK 0x0FFF0000U +#define MRV_LSC_XGRAD_1_SHIFT 16U +/*! Slice: xgrad_0:*/ +/*! factor for x-gradient calculation of sector 0 */ +#define MRV_LSC_XGRAD_0 +#define MRV_LSC_XGRAD_0_MASK 0x00000FFFU +#define MRV_LSC_XGRAD_0_SHIFT 0U +/*! Register: isp_lsc_xgrad_23: Gradient table x (0x00000028)*/ +/*! Slice: xgrad_3:*/ +/*! factor for x-gradient calculation of sector 3 */ +#define MRV_LSC_XGRAD_3 +#define MRV_LSC_XGRAD_3_MASK 0x0FFF0000U +#define MRV_LSC_XGRAD_3_SHIFT 16U +/*! Slice: xgrad_2:*/ +/*! factor for x-gradient calculation of sector 2 */ +#define MRV_LSC_XGRAD_2 +#define MRV_LSC_XGRAD_2_MASK 0x00000FFFU +#define MRV_LSC_XGRAD_2_SHIFT 0U +/*! Register: isp_lsc_xgrad_45: Gradient table x (0x0000002c)*/ +/*! Slice: xgrad_5:*/ +/*! factor for x-gradient calculation of sector 5 */ +#define MRV_LSC_XGRAD_5 +#define MRV_LSC_XGRAD_5_MASK 0x0FFF0000U +#define MRV_LSC_XGRAD_5_SHIFT 16U +/*! Slice: xgrad_4:*/ +/*! factor for x-gradient calculation of sector 4 */ +#define MRV_LSC_XGRAD_4 +#define MRV_LSC_XGRAD_4_MASK 0x00000FFFU +#define MRV_LSC_XGRAD_4_SHIFT 0U +/*! Register: isp_lsc_xgrad_67: Gradient table x (0x00000030)*/ +/*! Slice: xgrad_7:*/ +/*! factor for x-gradient calculation of sector 7 */ +#define MRV_LSC_XGRAD_7 +#define MRV_LSC_XGRAD_7_MASK 0x0FFF0000U +#define MRV_LSC_XGRAD_7_SHIFT 16U +/*! Slice: xgrad_6:*/ +/*! factor for x-gradient calculation of sector 6 */ +#define MRV_LSC_XGRAD_6 +#define MRV_LSC_XGRAD_6_MASK 0x00000FFFU +#define MRV_LSC_XGRAD_6_SHIFT 0U +/*! Register: isp_lsc_ygrad_01: Gradient table y (0x00000034)*/ +/*! Slice: ygrad_1:*/ +/*! factor for y-gradient calculation of sector 1 */ +#define MRV_LSC_YGRAD_1 +#define MRV_LSC_YGRAD_1_MASK 0x0FFF0000U +#define MRV_LSC_YGRAD_1_SHIFT 16U +/*! Slice: ygrad_0:*/ +/*! factor for y-gradient calculation of sector 0 */ +#define MRV_LSC_YGRAD_0 +#define MRV_LSC_YGRAD_0_MASK 0x00000FFFU +#define MRV_LSC_YGRAD_0_SHIFT 0U +/*! Register: isp_lsc_ygrad_23: Gradient table y (0x00000038)*/ +/*! Slice: ygrad_3:*/ +/*! factor for y-gradient calculation of sector 3 */ +#define MRV_LSC_YGRAD_3 +#define MRV_LSC_YGRAD_3_MASK 0x0FFF0000U +#define MRV_LSC_YGRAD_3_SHIFT 16U +/*! Slice: ygrad_2:*/ +/*! factor for y-gradient calculation of sector 2 */ +#define MRV_LSC_YGRAD_2 +#define MRV_LSC_YGRAD_2_MASK 0x00000FFFU +#define MRV_LSC_YGRAD_2_SHIFT 0U +/*! Register: isp_lsc_ygrad_45: Gradient table y (0x0000003c)*/ +/*! Slice: ygrad_5:*/ +/*! factor for y-gradient calculation of sector 5 */ +#define MRV_LSC_YGRAD_5 +#define MRV_LSC_YGRAD_5_MASK 0x0FFF0000U +#define MRV_LSC_YGRAD_5_SHIFT 16U +/*! Slice: ygrad_4:*/ +/*! factor for y-gradient calculation of sector 4 */ +#define MRV_LSC_YGRAD_4 +#define MRV_LSC_YGRAD_4_MASK 0x00000FFFU +#define MRV_LSC_YGRAD_4_SHIFT 0U +/*! Register: isp_lsc_ygrad_67: Gradient table y (0x00000040)*/ +/*! Slice: ygrad_7:*/ +/*! factor for y-gradient calculation of sector 7 */ +#define MRV_LSC_YGRAD_7 +#define MRV_LSC_YGRAD_7_MASK 0x0FFF0000U +#define MRV_LSC_YGRAD_7_SHIFT 16U +/*! Slice: ygrad_6:*/ +/*! factor for y-gradient calculation of sector 6 */ +#define MRV_LSC_YGRAD_6 +#define MRV_LSC_YGRAD_6_MASK 0x00000FFFU +#define MRV_LSC_YGRAD_6_SHIFT 0U +/*! Register: isp_lsc_xsize_01: Size table (0x00000044)*/ +/*! Slice: x_sect_size_1:*/ +/*! sector size 1 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_1 +#define MRV_LSC_X_SECT_SIZE_1_MASK 0x03FF0000U +#define MRV_LSC_X_SECT_SIZE_1_SHIFT 16U +/*! Slice: x_sect_size_0:*/ +/*! sector size 0 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_0 +#define MRV_LSC_X_SECT_SIZE_0_MASK 0x000003FFU +#define MRV_LSC_X_SECT_SIZE_0_SHIFT 0U +/*! Register: isp_lsc_xsize_23: Size table (0x00000048)*/ +/*! Slice: x_sect_size_3:*/ +/*! sector size 3 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_3 +#define MRV_LSC_X_SECT_SIZE_3_MASK 0x03FF0000U +#define MRV_LSC_X_SECT_SIZE_3_SHIFT 16U +/*! Slice: x_sect_size_2:*/ +/*! sector size 2 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_2 +#define MRV_LSC_X_SECT_SIZE_2_MASK 0x000003FFU +#define MRV_LSC_X_SECT_SIZE_2_SHIFT 0U +/*! Register: isp_lsc_xsize_45: Size table (0x0000004c)*/ +/*! Slice: x_sect_size_5:*/ +/*! sector size 5 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_5 +#define MRV_LSC_X_SECT_SIZE_5_MASK 0x03FF0000U +#define MRV_LSC_X_SECT_SIZE_5_SHIFT 16U +/*! Slice: x_sect_size_4:*/ +/*! sector size 4in x-direction */ +#define MRV_LSC_X_SECT_SIZE_4 +#define MRV_LSC_X_SECT_SIZE_4_MASK 0x000003FFU +#define MRV_LSC_X_SECT_SIZE_4_SHIFT 0U +/*! Register: isp_lsc_xsize_67: Size table (0x00000050)*/ +/*! Slice: x_sect_size_7:*/ +/*! sector size 7 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_7 +#define MRV_LSC_X_SECT_SIZE_7_MASK 0x03FF0000U +#define MRV_LSC_X_SECT_SIZE_7_SHIFT 16U +/*! Slice: x_sect_size_6:*/ +/*! sector size 6 in x-direction */ +#define MRV_LSC_X_SECT_SIZE_6 +#define MRV_LSC_X_SECT_SIZE_6_MASK 0x000003FFU +#define MRV_LSC_X_SECT_SIZE_6_SHIFT 0U +/*! Register: isp_lsc_ysize_01: Size table (0x00000054)*/ +/*! Slice: y_sect_size_1:*/ +/*! sector size 1 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_1 +#define MRV_LSC_Y_SECT_SIZE_1_MASK 0x03FF0000U +#define MRV_LSC_Y_SECT_SIZE_1_SHIFT 16U +/*! Slice: y_sect_size_0:*/ +/*! sector size 0 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_0 +#define MRV_LSC_Y_SECT_SIZE_0_MASK 0x000003FFU +#define MRV_LSC_Y_SECT_SIZE_0_SHIFT 0U +/*! Register: isp_lsc_ysize_23: Size table (0x00000058)*/ +/*! Slice: y_sect_size_3:*/ +/*! sector size 3 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_3 +#define MRV_LSC_Y_SECT_SIZE_3_MASK 0x03FF0000U +#define MRV_LSC_Y_SECT_SIZE_3_SHIFT 16U +/*! Slice: y_sect_size_2:*/ +/*! sector size 2 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_2 +#define MRV_LSC_Y_SECT_SIZE_2_MASK 0x000003FFU +#define MRV_LSC_Y_SECT_SIZE_2_SHIFT 0U +/*! Register: isp_lsc_ysize_45: Size table (0x0000005c)*/ +/*! Slice: y_sect_size_5:*/ +/*! sector size 5 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_5 +#define MRV_LSC_Y_SECT_SIZE_5_MASK 0x03FF0000U +#define MRV_LSC_Y_SECT_SIZE_5_SHIFT 16U +/*! Slice: y_sect_size_4:*/ +/*! sector size 4 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_4 +#define MRV_LSC_Y_SECT_SIZE_4_MASK 0x000003FFU +#define MRV_LSC_Y_SECT_SIZE_4_SHIFT 0U +/*! Register: isp_lsc_ysize_67: Size table (0x00000060)*/ +/*! Slice: y_sect_size_7:*/ +/*! sector size 7 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_7 +#define MRV_LSC_Y_SECT_SIZE_7_MASK 0x03FF0000U +#define MRV_LSC_Y_SECT_SIZE_7_SHIFT 16U +/*! Slice: y_sect_size_6:*/ +/*! sector size 6 in y-direction */ +#define MRV_LSC_Y_SECT_SIZE_6 +#define MRV_LSC_Y_SECT_SIZE_6_MASK 0x000003FFU +#define MRV_LSC_Y_SECT_SIZE_6_SHIFT 0U +/*! Register: isp_lsc_table_sel: Lens shade table set selection (0x00000064)*/ +/*! Slice: table_sel:*/ +/*! 0: next active tables set is table set 0.*/ +/* 1: next active tables set is table set 1.*/ +/* Table selection is object of a shadowing mechnism. The current status is visible at ISP_LSC_STATUS::active_table.*/ +#define MRV_LSC_TABLE_SEL +#define MRV_LSC_TABLE_SEL_MASK 0x00000001U +#define MRV_LSC_TABLE_SEL_SHIFT 0U +/*! Register: isp_lsc_status: Lens shade status (0x00000068)*/ +/*! Slice: active_table:*/ +/*! 0: currently active tables set is table set 0 */ +/* 1: currently active tables set is table set 1 */ +#define MRV_LSC_ACTIVE_TABLE +#define MRV_LSC_ACTIVE_TABLE_MASK 0x00000002U +#define MRV_LSC_ACTIVE_TABLE_SHIFT 1U +/*! Slice: lsc_en_status:*/ +/*! 0: lens shading correction is currently off */ +/* 1: lens shading correction is currently on */ +#define MRV_LSC_LSC_EN_STATUS +#define MRV_LSC_LSC_EN_STATUS_MASK 0x00000001U +#define MRV_LSC_LSC_EN_STATUS_SHIFT 0U +/*! Register: isp_is_ctrl: Image Stabilization Control Register (0x00000000)*/ +/*! Slice: is_en:*/ +/*! 1: image stabilization switched on */ +/* 0: image stabilization switched off */ +#define MRV_IS_IS_EN +#define MRV_IS_IS_EN_MASK 0x00000001U +#define MRV_IS_IS_EN_SHIFT 0U +/*! Register: isp_is_recenter: Recenter register (0x00000004)*/ +/*! Slice: is_recenter:*/ +/*! 000: recenter feature switched off */ +/* 1..7: recentering by (cur_h/v_offs-H/V_OFFS)/2^RECENTER */ +#define MRV_IS_IS_RECENTER +#define MRV_IS_IS_RECENTER_MASK 0x00000007U +#define MRV_IS_IS_RECENTER_SHIFT 0U +/*! Register: isp_is_h_offs: Horizontal offset of output window (0x00000008)*/ +/*! Slice: is_h_offs:*/ +/*! horizontal picture offset in pixel */ +#define MRV_IS_IS_H_OFFS +#define MRV_IS_IS_H_OFFS_MASK 0x00003FFFU +#define MRV_IS_IS_H_OFFS_SHIFT 0U +/*! Register: isp_is_v_offs: Vertical offset of output window (0x0000000c)*/ +/*! Slice: is_v_offs:*/ +/*! vertical picture offset in lines */ +#define MRV_IS_IS_V_OFFS +#define MRV_IS_IS_V_OFFS_MASK 0x00003FFFU +#define MRV_IS_IS_V_OFFS_SHIFT 0U +/*! Register: isp_is_h_size: Output horizontal picture size (0x00000010)*/ +/*! Slice: is_h_size:*/ +/*! horizontal picture size in pixel */ +/* if ISP_MODE is set to */ +/* 001-(ITU-R BT.656 YUV),*/ +/* 010-( ITU-R BT.601 YUV),*/ +/* 011-( ITU-R BT.601 Bayer RGB),*/ +/* 101-( ITU-R BT.656 Bayer RGB)*/ +/* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr) are needed for the following modules. If an odd size is programmed the value will be truncated to even size.*/ +#define MRV_IS_IS_H_SIZE +#define MRV_IS_IS_H_SIZE_MASK 0x00003FFFU +#define MRV_IS_IS_H_SIZE_SHIFT 0U +/*! Register: isp_is_v_size: Output vertical picture size (0x00000014)*/ +/*! Slice: is_v_size:*/ +/*! vertical picture size in lines */ +#define MRV_IS_IS_V_SIZE +#define MRV_IS_IS_V_SIZE_MASK 0x00003FFFU +#define MRV_IS_IS_V_SIZE_SHIFT 0U +/*! Register: isp_is_max_dx: Maximum Horizontal Displacement (0x00000018)*/ +/*! Slice: is_max_dx:*/ +/*! maximum allowed accumulated horizontal displacement in pixels */ +#define MRV_IS_IS_MAX_DX +#define MRV_IS_IS_MAX_DX_MASK 0x00001FFFU +#define MRV_IS_IS_MAX_DX_SHIFT 0U +/*! Register: isp_is_max_dy: Maximum Vertical Displacement (0x0000001c)*/ +/*! Slice: is_max_dy:*/ +/*! maximum allowed accumulated vertical displacement in lines */ +#define MRV_IS_IS_MAX_DY +#define MRV_IS_IS_MAX_DY_MASK 0x00001FFFU +#define MRV_IS_IS_MAX_DY_SHIFT 0U +/*! Register: isp_is_displace: Camera displacement (0x00000020)*/ +/*! Slice: dy:*/ +/*! ISP_IS will compensate for vertical camera displacement of DY lines in the next frame */ +#define MRV_IS_DY +#define MRV_IS_DY_MASK 0x1FFF0000U +#define MRV_IS_DY_SHIFT 16U +/*! Slice: dx:*/ +/*! ISP_IS will compensate for horizontal camera displacement of DX pixels in the next frame */ +#define MRV_IS_DX +#define MRV_IS_DX_MASK 0x00001FFFU +#define MRV_IS_DX_SHIFT 0U +/*! Register: isp_is_h_offs_shd: current horizontal offset of output window (shadow register) (0x00000024)*/ +/*! Slice: is_h_offs_shd:*/ +/*! current horizonatl picture offset in lines */ +#define MRV_IS_IS_H_OFFS_SHD +#define MRV_IS_IS_H_OFFS_SHD_MASK 0x00003FFFU +#define MRV_IS_IS_H_OFFS_SHD_SHIFT 0U +/*! Register: isp_is_v_offs_shd: current vertical offset of output window (shadow register) (0x00000028)*/ +/*! Slice: is_v_offs_shd:*/ +/*! current vertical picture offset in lines */ +#define MRV_IS_IS_V_OFFS_SHD +#define MRV_IS_IS_V_OFFS_SHD_MASK 0x00003FFFU +#define MRV_IS_IS_V_OFFS_SHD_SHIFT 0U +/*! Register: isp_is_h_size_shd: current output horizontal picture size (shadow register) (0x0000002c)*/ +/*! Slice: isp_h_size_shd:*/ +/*! current horizontal picture size in pixel */ +#define MRV_IS_ISP_H_SIZE_SHD +#define MRV_IS_ISP_H_SIZE_SHD_MASK 0x00003FFFU +#define MRV_IS_ISP_H_SIZE_SHD_SHIFT 0U +/*! Register: isp_is_v_size_shd: current output vertical picture size (shadow register) (0x00000030)*/ +/*! Slice: isp_v_size_shd:*/ +/*! vertical picture size in lines */ +#define MRV_IS_ISP_V_SIZE_SHD +#define MRV_IS_ISP_V_SIZE_SHD_MASK 0x00003FFFU +#define MRV_IS_ISP_V_SIZE_SHD_SHIFT 0U +/*! Register: isp_hist_prop: Histogram properties (0x00000000)*/ +/*! Slice: stepsize:*/ +/*! histogram predivider, process every (stepsize)th pixel, all other pixels are skipped */ +/* 0,1,2: not allowed */ +/* 3: process every third input pixel */ +/* 4: process every fourth input pixel */ +/* ...*/ +/* 7FH: process every 127th pixel */ +#define MRV_HIST_STEPSIZE +#define MRV_HIST_STEPSIZE_MASK 0x000003F8U +#define MRV_HIST_STEPSIZE_SHIFT 3U +/*! Slice: hist_mode:*/ +/*! histogram mode, luminance is taken at ISP output before output formatter, RGB is taken at xtalk output */ +/* 7, 6: must not be used */ +/* 5: Y (luminance) histogram */ +/* 4: B histogram */ +/* 3: G histogram */ +/* 2: R histogram */ +/* 1: RGB combined histogram */ +/* 0: disable, no measurements */ +#define MRV_HIST_MODE +#define MRV_HIST_MODE_MASK 0x00000007U +#define MRV_HIST_MODE_SHIFT 0U +/*! Register: isp_hist_h_offs: Histogram window horizontal offset for first window of 25 sub-windows (0x00000004)*/ +/*! Slice: hist_h_offset:*/ +/*! Horizontal offset of first window in pixels.*/ +#define MRV_HIST_H_OFFSET +#define MRV_HIST_H_OFFSET_MASK 0x00001FFFU +#define MRV_HIST_H_OFFSET_SHIFT 0U +/*! Register: isp_hist_v_offs: Histogram window vertical offset for first window of 25 sub-windows (0x00000008)*/ +/*! Slice: hist_v_offset:*/ +/*! Vertical offset of first window in pixels.*/ +#define MRV_HIST_V_OFFSET +#define MRV_HIST_V_OFFSET_MASK 0x00001FFFU +#define MRV_HIST_V_OFFSET_SHIFT 0U +/*! Register: isp_hist_h_size: Horizontal (sub-)window size (0x0000000c)*/ +/*! Slice: hist_h_size:*/ +/*! Horizontal size in pixels of one sub-window, if histogram version 3 is implemented.*/ +#define MRV_HIST_H_SIZE +#define MRV_HIST_H_SIZE_MASK 0x000007FFU +#define MRV_HIST_H_SIZE_SHIFT 0U +/*! Register: isp_hist_v_size: Vertical (sub-)window size (0x00000010)*/ +/*! Slice: hist_v_size:*/ +/*! Vertical size in lines of one sub-window, if histogram version 3 is implemented.*/ +#define MRV_HIST_V_SIZE +#define MRV_HIST_V_SIZE_MASK 0x000007FFU +#define MRV_HIST_V_SIZE_SHIFT 0U +#ifndef ISP_HIST256_RY +/*! Register array: isp_hist_bin: histogram measurement result bin (0x028 + n*0x4 (n=0..15))*/ +/*! Slice: hist_bin_n:*/ +/* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */ +#define MRV_HIST_BIN_N +#define MRV_HIST_BIN_N_MASK 0x000FFFFFU +#define MRV_HIST_BIN_N_SHIFT 0U +#else +/*! Register array: isp_hist_bin: histogram measurement result bin (0x028 + n*0x4 (n=0..15))*/ +/*! Slice: hist_bin_n:*/ +/* measured bin count as 26-bit unsigned integer value plus 4 bit fractional part */ +#define MRV_HIST_BIN_N +#define MRV_HIST_BIN_N_MASK 0x3FFFFFFFU +#define MRV_HIST_BIN_N_SHIFT 0U +#endif +/*! Register: isp_hist_weight_00to30: Weighting factor for sub-windows (0x00000054)*/ +/*! Slice: hist_weight_30:*/ +/*! weighting factor for sub-window 30 */ +#define MRV_HIST_WEIGHT_30 +#define MRV_HIST_WEIGHT_30_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_30_SHIFT 24U +/*! Slice: hist_weight_20:*/ +/*! weighting factor for sub-window 20 */ +#define MRV_HIST_WEIGHT_20 +#define MRV_HIST_WEIGHT_20_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_20_SHIFT 16U +/*! Slice: hist_weight_10:*/ +/*! weighting factor for sub-window 10 */ +#define MRV_HIST_WEIGHT_10 +#define MRV_HIST_WEIGHT_10_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_10_SHIFT 8U +/*! Slice: hist_weight_00:*/ +/*! weighting factor for sub-window 00 */ +#define MRV_HIST_WEIGHT_00 +#define MRV_HIST_WEIGHT_00_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_00_SHIFT 0U +/*! Register: isp_hist_weight_40to21: Weighting factor for sub-windows (0x00000058)*/ +/*! Slice: hist_weight_21:*/ +/*! weighting factor for sub-window 21 */ +#define MRV_HIST_WEIGHT_21 +#define MRV_HIST_WEIGHT_21_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_21_SHIFT 24U +/*! Slice: hist_weight_11:*/ +/*! weighting factor for sub-window 11 */ +#define MRV_HIST_WEIGHT_11 +#define MRV_HIST_WEIGHT_11_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_11_SHIFT 16U +/*! Slice: hist_weight_01:*/ +/*! weighting factor for sub-window 01 */ +#define MRV_HIST_WEIGHT_01 +#define MRV_HIST_WEIGHT_01_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_01_SHIFT 8U +/*! Slice: hist_weight_40:*/ +/*! weighting factor for sub-window 40 */ +#define MRV_HIST_WEIGHT_40 +#define MRV_HIST_WEIGHT_40_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_40_SHIFT 0U +/*! Register: isp_hist_weight_31to12: Weighting factor for sub-windows (0x0000005c)*/ +/*! Slice: hist_weight_12:*/ +/*! weighting factor for sub-window 12 */ +#define MRV_HIST_WEIGHT_12 +#define MRV_HIST_WEIGHT_12_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_12_SHIFT 24U +/*! Slice: hist_weight_02:*/ +/*! weighting factor for sub-window 02 */ +#define MRV_HIST_WEIGHT_02 +#define MRV_HIST_WEIGHT_02_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_02_SHIFT 16U +/*! Slice: hist_weight_41:*/ +/*! weighting factor for sub-window 41 */ +#define MRV_HIST_WEIGHT_41 +#define MRV_HIST_WEIGHT_41_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_41_SHIFT 8U +/*! Slice: hist_weight_31:*/ +/*! weighting factor for sub-window 31 */ +#define MRV_HIST_WEIGHT_31 +#define MRV_HIST_WEIGHT_31_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_31_SHIFT 0U +/*! Register: isp_hist_weight_22to03: Weighting factor for sub-windows (0x00000060)*/ +/*! Slice: hist_weight_03:*/ +/*! weighting factor for sub-window 03 */ +#define MRV_HIST_WEIGHT_03 +#define MRV_HIST_WEIGHT_03_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_03_SHIFT 24U +/*! Slice: hist_weight_42:*/ +/*! weighting factor for sub-window 42 */ +#define MRV_HIST_WEIGHT_42 +#define MRV_HIST_WEIGHT_42_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_42_SHIFT 16U +/*! Slice: hist_weight_32:*/ +/*! weighting factor for sub-window 32 */ +#define MRV_HIST_WEIGHT_32 +#define MRV_HIST_WEIGHT_32_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_32_SHIFT 8U +/*! Slice: hist_weight_22:*/ +/*! weighting factor for sub-window 22 */ +#define MRV_HIST_WEIGHT_22 +#define MRV_HIST_WEIGHT_22_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_22_SHIFT 0U +/*! Register: isp_hist_weight_13to43: Weighting factor for sub-windows (0x00000064)*/ +/*! Slice: hist_weight_43:*/ +/*! weighting factor for sub-window 43 */ +#define MRV_HIST_WEIGHT_43 +#define MRV_HIST_WEIGHT_43_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_43_SHIFT 24U +/*! Slice: hist_weight_33:*/ +/*! weighting factor for sub-window 33 */ +#define MRV_HIST_WEIGHT_33 +#define MRV_HIST_WEIGHT_33_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_33_SHIFT 16U +/*! Slice: hist_weight_23:*/ +/*! weighting factor for sub-window 23 */ +#define MRV_HIST_WEIGHT_23 +#define MRV_HIST_WEIGHT_23_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_23_SHIFT 8U +/*! Slice: hist_weight_13:*/ +/*! weighting factor for sub-window 13 */ +#define MRV_HIST_WEIGHT_13 +#define MRV_HIST_WEIGHT_13_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_13_SHIFT 0U +/*! Register: isp_hist_weight_04to34: Weighting factor for sub-windows (0x00000068)*/ +/*! Slice: hist_weight_34:*/ +/*! weighting factor for sub-window 34 */ +#define MRV_HIST_WEIGHT_34 +#define MRV_HIST_WEIGHT_34_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_34_SHIFT 24U +/*! Slice: hist_weight_24:*/ +/*! weighting factor for sub-window 24 */ +#define MRV_HIST_WEIGHT_24 +#define MRV_HIST_WEIGHT_24_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_24_SHIFT 16U +/*! Slice: hist_weight_14:*/ +/*! weighting factor for sub-window 14 */ +#define MRV_HIST_WEIGHT_14 +#define MRV_HIST_WEIGHT_14_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_14_SHIFT 8U +/*! Slice: hist_weight_04:*/ +/*! weighting factor for sub-window 04 */ +#define MRV_HIST_WEIGHT_04 +#define MRV_HIST_WEIGHT_04_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_04_SHIFT 0U +/*! Register: isp_hist_weight_44: Weighting factor for sub-windows (0x0000006c)*/ +/*! Slice: hist_weight_44:*/ +/*! weighting factor for sub-window 44 */ +#define MRV_HIST_WEIGHT_44 +#define MRV_HIST_WEIGHT_44_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_44_SHIFT 0U +/*! Register: isp_filt_mode: mode control register for the filter block (0x00000000)*/ +/*! Slice: stage1_select:*/ +/*! Green filter stage 1 select (range 0x0...0x8)*/ +/* 0x0 maximum blurring */ +/* 0x4 Default */ +/* 0x7 minimum blurring */ +/* 0x8 filter stage1 bypass */ +/* For a detailed description refer to chapter "ISP Filter Programming" of user manual */ +#define MRV_FILT_STAGE1_SELECT +#define MRV_FILT_STAGE1_SELECT_MASK 0x00000F00U +#define MRV_FILT_STAGE1_SELECT_SHIFT 8U +/*! Slice: filt_chr_h_mode:*/ +/*! Chroma filter horizontal mode */ +/* 00 horizontal chroma filter bypass */ +/* 01 horizontal chroma filter 1 static mask =[10 12 10]*/ +/* 10 horizontal chroma filter 2 (dynamic blur1)*/ +/* 11 horizontal chroma filter 3 (dynamic blur2) Default */ +#define MRV_FILT_FILT_CHR_H_MODE +#define MRV_FILT_FILT_CHR_H_MODE_MASK 0x000000C0U +#define MRV_FILT_FILT_CHR_H_MODE_SHIFT 6U +/*! Slice: filt_chr_v_mode:*/ +/*! Chroma filter vertical mode */ +/* 00 vertical chroma filter bypass */ +/* 01 vertical chroma filter 1 static[8 16 8]*/ +/* 10 vertical chroma filter 2 static[10 12 10]*/ +/* 11 vertical chroma filter 3 static[12 8 12] Default */ +#define MRV_FILT_FILT_CHR_V_MODE +#define MRV_FILT_FILT_CHR_V_MODE_MASK 0x00000030U +#define MRV_FILT_FILT_CHR_V_MODE_SHIFT 4U +/*! Slice: filt_mode:*/ +/*! 0 green filter static mode (active filter factor = FILT_FAC_MID)*/ +/* 1 dynamic noise reduction/sharpen Default */ +#define MRV_FILT_FILT_MODE +#define MRV_FILT_FILT_MODE_MASK 0x00000002U +#define MRV_FILT_FILT_MODE_SHIFT 1U +/*! Slice: filt_enable:*/ +/*! 1 enable filter */ +/* 0 bypass filter Default */ +#define MRV_FILT_FILT_ENABLE +#define MRV_FILT_FILT_ENABLE_MASK 0x00000001U +#define MRV_FILT_FILT_ENABLE_SHIFT 0U +/*! Register: isp_filt_thresh_bl0: Blurring threshold 0 (0x00000028)*/ +/*! Slice: filt_thresh_bl0:*/ +/*! If filt_thresh_bl1 < sum_grad < filt_thresh_bl0 then filt_fac_bl0 is selected */ +#define MRV_FILT_FILT_THRESH_BL0 +#define MRV_FILT_FILT_THRESH_BL0_MASK 0x000003FFU +#define MRV_FILT_FILT_THRESH_BL0_SHIFT 0U +/*! Register: isp_filt_thresh_bl1: Blurring threshold 1 (0x0000002c)*/ +/*! Slice: filt_thresh_bl1:*/ +/*! If sum_grad < filt_thresh_bl1 then filt_fac_bl1 is selected */ +#define MRV_FILT_FILT_THRESH_BL1 +#define MRV_FILT_FILT_THRESH_BL1_MASK 0x000003FFU +#define MRV_FILT_FILT_THRESH_BL1_SHIFT 0U +/*! Register: isp_filt_thresh_sh0: Sharpening threshold 0 (0x00000030)*/ +/*! Slice: filt_thresh_sh0:*/ +/*! If filt_thresh_sh0 < sum_grad < filt_thresh_sh1 then filt_thresh_sh0 is selected */ +#define MRV_FILT_FILT_THRESH_SH0 +#define MRV_FILT_FILT_THRESH_SH0_MASK 0x000003FFU +#define MRV_FILT_FILT_THRESH_SH0_SHIFT 0U +/*! Register: isp_filt_thresh_sh1: Sharpening threshold 1 (0x00000034)*/ +/*! Slice: filt_thresh_sh1:*/ +/*! If filt_thresh_sh1 < sum_grad then filt_thresh_sh1 is selected */ +#define MRV_FILT_FILT_THRESH_SH1 +#define MRV_FILT_FILT_THRESH_SH1_MASK 0x000003FFU +#define MRV_FILT_FILT_THRESH_SH1_SHIFT 0U +/*! Register: isp_filt_lum_weight: Parameters for luminance weight function (0x00000038)*/ +/*! Slice: lum_weight_gain:*/ +/*! Gain select of luminance weight function */ +#define MRV_FILT_LUM_WEIGHT_GAIN +#define MRV_FILT_LUM_WEIGHT_GAIN_MASK 0x00070000U +#define MRV_FILT_LUM_WEIGHT_GAIN_SHIFT 16U +/*! Slice: lum_weight_kink:*/ +/*! Kink position of luminance weight function */ +#define MRV_FILT_LUM_WEIGHT_KINK +#define MRV_FILT_LUM_WEIGHT_KINK_MASK 0x0000FF00U +#define MRV_FILT_LUM_WEIGHT_KINK_SHIFT 8U +/*! Slice: lum_weight_min:*/ +/*! Minimum value of luminance weight function */ +#define MRV_FILT_LUM_WEIGHT_MIN +#define MRV_FILT_LUM_WEIGHT_MIN_MASK 0x000000FFU +#define MRV_FILT_LUM_WEIGHT_MIN_SHIFT 0U +/*! Register: isp_filt_fac_sh1: filter factor sharp1 (0x0000003c)*/ +/*! Slice: filt_fac_sh1:*/ +/*! Filter factor for sharp1 level */ +#define MRV_FILT_FILT_FAC_SH1 +#define MRV_FILT_FILT_FAC_SH1_MASK 0x0000003FU +#define MRV_FILT_FILT_FAC_SH1_SHIFT 0U +/*! Register: isp_filt_fac_sh0: filter factor sharp0 (0x00000040)*/ +/*! Slice: filt_fac_sh0:*/ +/*! Filter factor for sharp0 level */ +#define MRV_FILT_FILT_FAC_SH0 +#define MRV_FILT_FILT_FAC_SH0_MASK 0x0000003FU +#define MRV_FILT_FILT_FAC_SH0_SHIFT 0U +/*! Register: isp_filt_fac_mid: filter factor middle (0x00000044)*/ +/*! Slice: filt_fac_mid:*/ +/*! Filter factor for mid level and for static filter mode */ +#define MRV_FILT_FILT_FAC_MID +#define MRV_FILT_FILT_FAC_MID_MASK 0x0000003FU +#define MRV_FILT_FILT_FAC_MID_SHIFT 0U +/*! Register: isp_filt_fac_bl0: Parameter for blur 0 filter (0x00000048)*/ +/*! Slice: filt_fac_bl0:*/ +/*! Filter factor for blur 0 level */ +#define MRV_FILT_FILT_FAC_BL0 +#define MRV_FILT_FILT_FAC_BL0_MASK 0x0000003FU +#define MRV_FILT_FILT_FAC_BL0_SHIFT 0U +/*! Register: isp_filt_fac_bl1: Parameter for blur 1 filter (0x0000004c)*/ +/*! Slice: filt_fac_bl1:*/ +/*! Filter factor for blur 1 level (max blur)*/ +#define MRV_FILT_FILT_FAC_BL1 +#define MRV_FILT_FILT_FAC_BL1_MASK 0x0000003FU +#define MRV_FILT_FILT_FAC_BL1_SHIFT 0U +/*! Register: isp_cac_ctrl: Control register for chromatic aberration correction (0x00000000)*/ +/*! Slice: h_clip_mode:*/ +/*! Defines the maximum red/blue pixel shift in horizontal direction At pixel positions, that require a larger displacement, the maximum shift value is used instead (vector clipping)*/ +/* 0: Set horizontal vector clipping to +/-4 pixel displacement (Default)*/ +/* 1: Set horizontal vector clipping to +/-4 or +/-5 pixel displacement depending on pixel position inside the Bayer raster (dynamic switching between +/-4 and +/-5)*/ +#define MRV_CAC_H_CLIP_MODE +#define MRV_CAC_H_CLIP_MODE_MASK 0x00000008U +#define MRV_CAC_H_CLIP_MODE_SHIFT 3U +/*! Slice: v_clip_mode:*/ +/*! Defines the maximum red/blue pixel shift in vertical direction */ +/* 00: Set vertical vector clipping to +/-2 pixel ; fix filter_enable (Default)*/ +/* 01: Set vertical vector clipping to +/-3 pixel; dynamic filter_enable for chroma low pass filter */ +/* 10: Set vertical vector clipping +/-3 or +/-4 pixel displacement depending on pixel position inside the Bayer raster (dynamic switching between +/-3 and +/-4)*/ +/* 11: reserved */ +#define MRV_CAC_V_CLIP_MODE +#define MRV_CAC_V_CLIP_MODE_MASK 0x00000006U +#define MRV_CAC_V_CLIP_MODE_SHIFT 1U +/*! Slice: cac_en:*/ +/*! 0: chromatic aberration correction off */ +/* 1: chromatic aberration correction on */ +#define MRV_CAC_CAC_EN +#define MRV_CAC_CAC_EN_MASK 0x00000001U +#define MRV_CAC_CAC_EN_SHIFT 0U +/*! Register: isp_cac_count_start: Preload values for CAC pixel and line counter (0x00000004)*/ +/*! Slice: v_count_start:*/ +/*! 13 bit v_count preload value (range 8191 ... 1) of the vertical CAC line counter. Before frame start v_count has to be preloaded with (v_size/2 + v_center_offset), with */ +/* v_size the image height and */ +/* v_center_offset the vertical distance between image center and optical center.*/ + /**/ +/* After frame start the v_count decrements with every line until a value of zero is reached for the line in the optical center. Than the v_sign bit toggles and the v_counter decrements with every line until end of frame.*/ +#define MRV_CAC_V_COUNT_START +#define MRV_CAC_V_COUNT_START_MASK 0x1FFF0000U +#define MRV_CAC_V_COUNT_START_SHIFT 16U +/*! Slice: h_count_start:*/ +/*! 13 bit h_count preload value (range 8191 .. 1) of the horizontal CAC pixel counter. Before line start h_count has to be preloaded with (h_size/2 + h_center_offset), with */ +/* h_size the image width and */ +/* h_center_offset the horizontal distance between image center and optical center.*/ + /**/ +/* After line start the h_count decrements with every pixel until a value of zero is reached for the column in the optical center. Than the h_sign bit toggles and the h_counter increments with every pixel until end of line.*/ +#define MRV_CAC_H_COUNT_START +#define MRV_CAC_H_COUNT_START_MASK 0x00001FFFU +#define MRV_CAC_H_COUNT_START_SHIFT 0U +/*! Register: isp_cac_a: Linear Parameters for radial shift calculation (0x00000008)*/ +/*! Slice: A_Blue:*/ +/*! Parameter A_Blue for radial blue shift calculation, according to */ +/*(A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_A_BLUE +#define MRV_CAC_A_BLUE_MASK 0x01FF0000U +#define MRV_CAC_A_BLUE_SHIFT 16U +/*! Slice: A_Red:*/ +/*! Parameter A_Red for radial red shift calculation, according to */ +/*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_A_RED +#define MRV_CAC_A_RED_MASK 0x000001FFU +#define MRV_CAC_A_RED_SHIFT 0U +/*! Register: isp_cac_b: Square Parameters for radial shift calculation (0x0000000c)*/ +/*! Slice: B_Blue:*/ +/*! Parameter B_Blue for radial blue shift calculation, according to */ +/*(A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_B_BLUE +#define MRV_CAC_B_BLUE_MASK 0x01FF0000U +#define MRV_CAC_B_BLUE_SHIFT 16U +/*! Slice: B_Red:*/ +/*! Parameter B_Red for radial red shift calculation, according to */ +/*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_B_RED +#define MRV_CAC_B_RED_MASK 0x000001FFU +#define MRV_CAC_B_RED_SHIFT 0U +/*! Register: isp_cac_c: Cubical Parameters for radial shift calculation (0x00000010)*/ +/*! Slice: C_Blue:*/ +/*! Parameter C_Blue for radial blue shift calculation, according to */ +/*(A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_C_BLUE +#define MRV_CAC_C_BLUE_MASK 0x01FF0000U +#define MRV_CAC_C_BLUE_SHIFT 16U +/*! Slice: C_Red:*/ +/*! Parameter C_Red for radial red shift calculation, according to */ +/*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/ +/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/ +#define MRV_CAC_C_RED +#define MRV_CAC_C_RED_MASK 0x000001FFU +#define MRV_CAC_C_RED_SHIFT 0U +/*! Register: isp_cac_x_norm: Normalization parameters for calculation of image coordinate x_d relative to optical center (0x00000014)*/ +/*! Slice: x_ns:*/ +/*! Horizontal normalization shift parameter x_ns (4 bit unsigned integer) in equation */ +/* x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */ +#define MRV_CAC_X_NS +#define MRV_CAC_X_NS_MASK 0x000F0000U +#define MRV_CAC_X_NS_SHIFT 16U +/*! Slice: x_nf:*/ +/*! Horizontal scaling or normalization factor x_nf (5 bit unsigned integer) range 0 .. 31 in equation */ +/* x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */ +#define MRV_CAC_X_NF +#define MRV_CAC_X_NF_MASK 0x0000001FU +#define MRV_CAC_X_NF_SHIFT 0U +/*! Register: isp_cac_y_norm: Normalization parameters for calculation of image coordinate y_d relative to optical center (0x00000018)*/ +/*! Slice: y_ns:*/ +/*! Vertical normalization shift parameter y_ns (4 bit unsigned integer) in equation */ +/* y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */ +#define MRV_CAC_Y_NS +#define MRV_CAC_Y_NS_MASK 0x000F0000U +#define MRV_CAC_Y_NS_SHIFT 16U +/*! Slice: y_nf:*/ +/*! Vertical scaling or normalization factor y_nf (5 bit unsigned integer) range 0 .. 31 in equation */ +/* y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */ +#define MRV_CAC_Y_NF +#define MRV_CAC_Y_NF_MASK 0x0000001FU +#define MRV_CAC_Y_NF_SHIFT 0U +/*! Register: isp_exp_ctrl: Exposure control (0x00000000)*/ +/*! Slice: exp_meas_mode:*/ +/*! '1' luminance calculation according to */ +/* Y=(R+G+B) x 0.332 (85/256)*/ +/* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */ +#define MRV_AE_EXP_MEAS_MODE +#define MRV_AE_EXP_MEAS_MODE_MASK 0x80000000U +#define MRV_AE_EXP_MEAS_MODE_SHIFT 31U +/*! Slice: autostop:*/ +/*! '1' stop measuring after a complete frame */ +/* '0' continous measurement */ +#define MRV_AE_AUTOSTOP +#define MRV_AE_AUTOSTOP_MASK 0x00000002U +#define MRV_AE_AUTOSTOP_SHIFT 1U +/*! Slice: exp_start:*/ +/*! '1' start measuring a frame. The exp block will reset this bit and halt after completing one frame, if bit "autostop" is set to '1'.*/ +#define MRV_AE_EXP_START +#define MRV_AE_EXP_START_MASK 0x00000001U +#define MRV_AE_EXP_START_SHIFT 0U +/*! Register: isp_exp_h_offset: Horizontal offset for first block (0x00000004)*/ +/*! Slice: isp_exp_h_offset:*/ +/*! Horizontal offset of first block in pixels.*/ +/* 0 <= value <= 2424 */ +#define MRV_AE_ISP_EXP_H_OFFSET +#define MRV_AE_ISP_EXP_H_OFFSET_MASK 0x00001FFFU +#define MRV_AE_ISP_EXP_H_OFFSET_SHIFT 0U +/*! Register: isp_exp_v_offset: Vertical offset for first block (0x00000008)*/ +/*! Slice: isp_exp_v_offset:*/ +/*! Vertical offset of first block in pixels.*/ +/* 0 <= value <= 1806 */ +#define MRV_AE_ISP_EXP_V_OFFSET +#define MRV_AE_ISP_EXP_V_OFFSET_MASK 0x00001FFFU +#define MRV_AE_ISP_EXP_V_OFFSET_SHIFT 0U +/*! Register: isp_exp_h_size: Horizontal size of one block (0x0000000c)*/ +/*! Slice: isp_exp_h_size:*/ +/*! Horizontal size in pixels of one block.*/ +/* 35 <= value <= 516 */ +#define MRV_AE_ISP_EXP_H_SIZE +#define MRV_AE_ISP_EXP_H_SIZE_MASK 0x000007FFU +#define MRV_AE_ISP_EXP_H_SIZE_SHIFT 0U +/*! Register: isp_exp_v_size: Vertical size of one block (0x00000010)*/ +/*! Slice: isp_exp_v_size:*/ +/*! Vertical size in pixels of one block.*/ +/* 28 <= value <= 390 */ +#define MRV_AE_ISP_EXP_V_SIZE +#define MRV_AE_ISP_EXP_V_SIZE_MASK 0x000007FEU +#define MRV_AE_ISP_EXP_V_SIZE_SHIFT 0U +/*! Register: isp_exp_mean_00: Mean luminance value of block 00 (0x00000014)*/ +/*! Slice: isp_exp_mean_00:*/ +/*! Mean luminance value of block 00 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_00 +#define MRV_AE_ISP_EXP_MEAN_00_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_00_SHIFT 0U +/*! Register: isp_exp_mean_10: Mean luminance value of block 10 (0x00000018)*/ +/*! Slice: isp_exp_mean_10:*/ +/*! Mean luminance value of block 10 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_10 +#define MRV_AE_ISP_EXP_MEAN_10_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_10_SHIFT 0U +/*! Register: isp_exp_mean_20: Mean luminance value of block 20 (0x0000001c)*/ +/*! Slice: isp_exp_mean_20:*/ +/*! Mean luminance value of block 20 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_20 +#define MRV_AE_ISP_EXP_MEAN_20_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_20_SHIFT 0U +/*! Register: isp_exp_mean_30: Mean luminance value of block 30 (0x00000020)*/ +/*! Slice: isp_exp_mean_30:*/ +/*! Mean luminance value of block 30 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_30 +#define MRV_AE_ISP_EXP_MEAN_30_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_30_SHIFT 0U +/*! Register: isp_exp_mean_40: Mean luminance value of block 40 (0x00000024)*/ +/*! Slice: isp_exp_mean_40:*/ +/*! Mean luminance value of block 40 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_40 +#define MRV_AE_ISP_EXP_MEAN_40_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_40_SHIFT 0U +/*! Register: isp_exp_mean_01: Mean luminance value of block 01 (0x00000028)*/ +/*! Slice: isp_exp_mean_01:*/ +/*! Mean luminance value of block 01 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_01 +#define MRV_AE_ISP_EXP_MEAN_01_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_01_SHIFT 0U +/*! Register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c)*/ +/*! Slice: isp_exp_mean_11:*/ +/*! Mean luminance value of block 11 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_11 +#define MRV_AE_ISP_EXP_MEAN_11_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_11_SHIFT 0U +/*! Register: isp_exp_mean_21: Mean luminance value of block 21 (0x00000030)*/ +/*! Slice: isp_exp_mean_21:*/ +/*! Mean luminance value of block 21 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_21 +#define MRV_AE_ISP_EXP_MEAN_21_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_21_SHIFT 0U +/*! Register: isp_exp_mean_31: Mean luminance value of block 31 (0x00000034)*/ +/*! Slice: isp_exp_mean_31:*/ +/*! Mean luminance value of block 31 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_31 +#define MRV_AE_ISP_EXP_MEAN_31_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_31_SHIFT 0U +/*! Register: isp_exp_mean_41: Mean luminance value of block 41 (0x00000038)*/ +/*! Slice: isp_exp_mean_41:*/ +/*! Mean luminance value of block 41 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_41 +#define MRV_AE_ISP_EXP_MEAN_41_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_41_SHIFT 0U +/*! Register: isp_exp_mean_02: Mean luminance value of block 02 (0x0000003c)*/ +/*! Slice: isp_exp_mean_02:*/ +/*! Mean luminance value of block 02 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_02 +#define MRV_AE_ISP_EXP_MEAN_02_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_02_SHIFT 0U +/*! Register: isp_exp_mean_12: Mean luminance value of block 12 (0x00000040)*/ +/*! Slice: isp_exp_mean_12:*/ +/*! Mean luminance value of block 12 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_12 +#define MRV_AE_ISP_EXP_MEAN_12_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_12_SHIFT 0U +/*! Register: isp_exp_mean_22: Mean luminance value of block 22 (0x00000044)*/ +/*! Slice: isp_exp_mean_22:*/ +/*! Mean luminance value of block 22 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_22 +#define MRV_AE_ISP_EXP_MEAN_22_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_22_SHIFT 0U +/*! Register: isp_exp_mean_32: Mean luminance value of block 32 (0x00000048)*/ +/*! Slice: isp_exp_mean_32:*/ +/*! Mean luminance value of block 32 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_32 +#define MRV_AE_ISP_EXP_MEAN_32_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_32_SHIFT 0U +/*! Register: isp_exp_mean_42: Mean luminance value of block 42 (0x0000004c)*/ +/*! Slice: isp_exp_mean_42:*/ +/*! Mean luminance value of block 42 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_42 +#define MRV_AE_ISP_EXP_MEAN_42_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_42_SHIFT 0U +/*! Register: isp_exp_mean_03: Mean luminance value of block 03 (0x00000050)*/ +/*! Slice: isp_exp_mean_03:*/ +/*! Mean luminance value of block 03 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_03 +#define MRV_AE_ISP_EXP_MEAN_03_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_03_SHIFT 0U +/*! Register: isp_exp_mean_13: Mean luminance value of block 13 (0x00000054)*/ +/*! Slice: isp_exp_mean_13:*/ +/*! Mean luminance value of block 13 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_13 +#define MRV_AE_ISP_EXP_MEAN_13_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_13_SHIFT 0U +/*! Register: isp_exp_mean_23: Mean luminance value of block 23 (0x00000058)*/ +/*! Slice: isp_exp_mean_23:*/ +/*! Mean luminance value of block 23 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_23 +#define MRV_AE_ISP_EXP_MEAN_23_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_23_SHIFT 0U +/*! Register: isp_exp_mean_33: Mean luminance value of block 33 (0x0000005c)*/ +/*! Slice: isp_exp_mean_33:*/ +/*! Mean luminance value of block 33 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_33 +#define MRV_AE_ISP_EXP_MEAN_33_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_33_SHIFT 0U +/*! Register: isp_exp_mean_43: Mean luminance value of block 43 (0x00000060)*/ +/*! Slice: isp_exp_mean_43:*/ +/*! Mean luminance value of block 43 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_43 +#define MRV_AE_ISP_EXP_MEAN_43_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_43_SHIFT 0U +/*! Register: isp_exp_mean_04: Mean luminance value of block 04 (0x00000064)*/ +/*! Slice: isp_exp_mean_04:*/ +/*! Mean luminance value of block 04 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_04 +#define MRV_AE_ISP_EXP_MEAN_04_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_04_SHIFT 0U +/*! Register: isp_exp_mean_14: Mean luminance value of block 14 (0x00000068)*/ +/*! Slice: isp_exp_mean_14:*/ +/*! Mean luminance value of block 14 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_14 +#define MRV_AE_ISP_EXP_MEAN_14_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_14_SHIFT 0U +/*! Register: isp_exp_mean_24: Mean luminance value of block 24 (0x0000006c)*/ +/*! Slice: isp_exp_mean_24:*/ +/*! Mean luminance value of block 24 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_24 +#define MRV_AE_ISP_EXP_MEAN_24_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_24_SHIFT 0U +/*! Register: isp_exp_mean_34: Mean luminance value of block 34 (0x00000070)*/ +/*! Slice: isp_exp_mean_34:*/ +/*! Mean luminance value of block 34 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_34 +#define MRV_AE_ISP_EXP_MEAN_34_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_34_SHIFT 0U +/*! Register: isp_exp_mean_44: Mean luminance value of block 44 (0x00000074)*/ +/*! Slice: isp_exp_mean_44:*/ +/*! Mean luminance value of block 44 (x,y)*/ +#define MRV_AE_ISP_EXP_MEAN_44 +#define MRV_AE_ISP_EXP_MEAN_44_MASK 0x000000FFU +#define MRV_AE_ISP_EXP_MEAN_44_SHIFT 0U +/*! Register: isp_expv2_ctrl: (0x00002680)*/ +/*! Slice: isp_expv2_ctrl:*/ +#define MRV_AE_ISP_EXPV2_INPUT_SELECT +#define MRV_AE_ISP_EXPV2_INPUT_SELECT_MASK 0x0000000CU +#define MRV_AE_ISP_EXPV2_INPUT_SELECT_SHIFT 2U +#define MRV_AE_ISP_EXPV2_AUTO_STOP +#define MRV_AE_ISP_EXPV2_AUTO_STOP_MASK 0x00000002U +#define MRV_AE_ISP_EXPV2_AUTO_STOP_SHIFT 1U +#define MRV_AE_ISP_EXPV2_ENABLE +#define MRV_AE_ISP_EXPV2_ENABLE_MASK 0x00000001U +#define MRV_AE_ISP_EXPV2_ENABLE_SHIFT 0U +/*! Register: isp_expv2_offset: (0x00002684)*/ +/*! Slice: isp_expv2_offset:*/ +#define MRV_AE_ISP_EXPV2_OFFSET_V +#define MRV_AE_ISP_EXPV2_OFFSET_V_MASK 0x1FFF0000U +#define MRV_AE_ISP_EXPV2_OFFSET_V_SHIFT 16U +#define MRV_AE_ISP_EXPV2_OFFSET_H +#define MRV_AE_ISP_EXPV2_OFFSET_H_MASK 0x00001FFFU +#define MRV_AE_ISP_EXPV2_OFFSET_H_SHIFT 0 +/*! Register: isp_expv2_size: (0x00002688)*/ +/*! Slice: isp_expv2_size:*/ +#define MRV_AE_ISP_EXPV2_SIZE_V +#define MRV_AE_ISP_EXPV2_SIZE_V_MASK 0x01FF0000U +#define MRV_AE_ISP_EXPV2_SIZE_V_SHIFT 16U +#define MRV_AE_ISP_EXPV2_SIZE_H +#define MRV_AE_ISP_EXPV2_SIZE_H_MASK 0x000001FFU +#define MRV_AE_ISP_EXPV2_SIZE_H_SHIFT 0U +/*! Register: isp_expv2_size_invert: (0x0000268c)*/ +/*! Slice: isp_expv2_size_invert:*/ +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_V +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_V_MASK 0xFFFF0000U +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_V_SHIFT 16U +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_H +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_H_MASK 0x0000FFFFU +#define MRV_AE_ISP_EXPV2_SIZE_INVERT_H_SHIFT 0U +/*! Register: isp_expv2_pixel_weight: (0x00002690)*/ +/*! Slice: isp_expv2_pixel_weight:*/ +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R_MASK 0x3F000000U +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R_SHIFT 24U +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR_MASK 0x003F0000U +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR_SHIFT 16 +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB_MASK 0x00003F00U +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB_SHIFT 8U +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B_MASK 0x0000003FU +#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B_SHIFT 0U +/*! Register: isp_bls_ctrl: global control register (0x00000000)*/ +/*! Slice: WINDOW_ENABLE:*/ +/*! 0: no measuring is performed */ +/* 1: only window 1 is measured */ +/* 2: only window 2 is measured */ +/* 3: both windows are measured */ +#define MRV_BLS_WINDOW_ENABLE +#define MRV_BLS_WINDOW_ENABLE_MASK 0x0000000CU +#define MRV_BLS_WINDOW_ENABLE_SHIFT 2U +/*! Slice: BLS_MODE:*/ +/*! 1: subtract measured values */ +/* 0: subtract fixed values */ +#define MRV_BLS_BLS_MODE +#define MRV_BLS_BLS_MODE_MASK 0x00000002U +#define MRV_BLS_BLS_MODE_SHIFT 1U +/*! Slice: BLS_ENABLE:*/ +/*! 1: black level subtraction is enabled */ +/* 0: bypass the black level processing */ +#define MRV_BLS_BLS_ENABLE +#define MRV_BLS_BLS_ENABLE_MASK 0x00000001U +#define MRV_BLS_BLS_ENABLE_SHIFT 0U +/*! Register: isp_bls_samples: samples register (0x00000004)*/ +/*! Slice: BLS_SAMPLES:*/ +/*! This number to the power of two gives the number of measure samples for each Bayer position. Range 0x00: 2^0=1 to 0x12: 2^18=262144. This number is also the divider for the accumulator for each Bayer position.*/ +/* The accumulation will be stopped, if the number of measured pixels for the current Bayer position is equal to the number of samples.*/ +/* The measure windows must be positioned that way that the number of included pixels of each Bayer position included by both windows is equal or greater than the number of measure samples calculated by 2^BLS_SAMPLES !*/ +/* NOTE: The number of pixels of one Bayer position is 1/4 of the number of all Pixels included by the measure windows.*/ +#define MRV_BLS_BLS_SAMPLES +#define MRV_BLS_BLS_SAMPLES_MASK 0x0000001FU +#define MRV_BLS_BLS_SAMPLES_SHIFT 0U +/*! Register: isp_bls_h1_start: window 1 horizontal start (0x00000008)*/ +/*! Slice: BLS_H1_START:*/ +/*! Black pixel window 1 horizontal start position */ +#define MRV_BLS_BLS_H1_START +#define MRV_BLS_BLS_H1_START_MASK 0x00003FFFU +#define MRV_BLS_BLS_H1_START_SHIFT 0U +/*! Register: isp_bls_h1_stop: window 1 horizontal stop (0x0000000c)*/ +/*! Slice: BLS_H1_STOP:*/ +/*! Black pixel window 1 horizontal stop position */ +#define MRV_BLS_BLS_H1_STOP +#define MRV_BLS_BLS_H1_STOP_MASK 0x00003FFFU +#define MRV_BLS_BLS_H1_STOP_SHIFT 0U +/*! Register: isp_bls_v1_start: window 1 vertical start (0x00000010)*/ +/*! Slice: BLS_V1_START:*/ +/*! Black pixel window 1 vertical start position */ +#define MRV_BLS_BLS_V1_START +#define MRV_BLS_BLS_V1_START_MASK 0x00003FFFU +#define MRV_BLS_BLS_V1_START_SHIFT 0U +/*! Register: isp_bls_v1_stop: window 1 vertical stop (0x00000014)*/ +/*! Slice: BLS_V1_STOP:*/ +/*! Black pixel window 1 vertical stop position */ +#define MRV_BLS_BLS_V1_STOP +#define MRV_BLS_BLS_V1_STOP_MASK 0x00003FFFU +#define MRV_BLS_BLS_V1_STOP_SHIFT 0U +/*! Register: isp_bls_h2_start: window 2 horizontal start (0x00000018)*/ +/*! Slice: BLS_H2_START:*/ +/*! Black pixel window 2 horizontal start position */ +#define MRV_BLS_BLS_H2_START +#define MRV_BLS_BLS_H2_START_MASK 0x00003FFFU +#define MRV_BLS_BLS_H2_START_SHIFT 0U +/*! Register: isp_bls_h2_stop: window 2 horizontal stop (0x0000001c)*/ +/*! Slice: BLS_H2_STOP:*/ +/*! Black pixel window 2 horizontal stop position */ +#define MRV_BLS_BLS_H2_STOP +#define MRV_BLS_BLS_H2_STOP_MASK 0x00003FFFU +#define MRV_BLS_BLS_H2_STOP_SHIFT 0U +/*! Register: isp_bls_v2_start: window 2 vertical start (0x00000020)*/ +/*! Slice: BLS_V2_START:*/ +/*! Black pixel window 2 vertical start position */ +#define MRV_BLS_BLS_V2_START +#define MRV_BLS_BLS_V2_START_MASK 0x00003FFFU +#define MRV_BLS_BLS_V2_START_SHIFT 0U +/*! Register: isp_bls_v2_stop: window 2 vertical stop (0x00000024)*/ +/*! Slice: BLS_V2_STOP:*/ +/*! Black pixel window 2 vertical stop position */ +#define MRV_BLS_BLS_V2_STOP +#define MRV_BLS_BLS_V2_STOP_MASK 0x00003FFFU +#define MRV_BLS_BLS_V2_STOP_SHIFT 0U +/*! Register: isp_bls_a_fixed: fixed black level A (0x00000028)*/ +/*! Slice: BLS_A_FIXED:*/ +/*! Fixed black level for A pixels – signed */ +/* two's complement, value range from -4096 to +4095,*/ +/* a positive value will be subtracted from the pixel values */ +#define MRV_BLS_BLS_A_FIXED +#define MRV_BLS_BLS_A_FIXED_MASK 0x00001FFFU +#define MRV_BLS_BLS_A_FIXED_SHIFT 0U +/*! Register: isp_bls_b_fixed: fixed black level B (0x0000002c)*/ +/*! Slice: BLS_B_FIXED:*/ +/*! Fixed black level for B pixels – signed */ +/* two's complement, value range from -4096 to +4095 */ +#define MRV_BLS_BLS_B_FIXED +#define MRV_BLS_BLS_B_FIXED_MASK 0x00001FFFU +#define MRV_BLS_BLS_B_FIXED_SHIFT 0U +/*! Register: isp_bls_c_fixed: fixed black level C (0x00000030)*/ +/*! Slice: BLS_C_FIXED:*/ +/*! Fixed black level for C pixels – signed */ +/* two's complement, value range from -4096 to +4095 */ +#define MRV_BLS_BLS_C_FIXED +#define MRV_BLS_BLS_C_FIXED_MASK 0x00001FFFU +#define MRV_BLS_BLS_C_FIXED_SHIFT 0U +/*! Register: isp_bls_d_fixed: fixed black level D (0x00000034)*/ +/*! Slice: BLS_D_FIXED:*/ +/*! Fixed black level for D pixels - signed */ +/* two's complement, value range from -4096 to +4095 */ +#define MRV_BLS_BLS_D_FIXED +#define MRV_BLS_BLS_D_FIXED_MASK 0x00001FFFU +#define MRV_BLS_BLS_D_FIXED_SHIFT 0U +/*! Register: isp_bls_a_measured: measured black level A (0x00000038)*/ +/*! Slice: BLS_A_MEASURED:*/ +/*! Measured black level for A pixels */ +#define MRV_BLS_BLS_A_MEASURED +#define MRV_BLS_BLS_A_MEASURED_MASK 0x00000FFFU +#define MRV_BLS_BLS_A_MEASURED_SHIFT 0U +/*! Register: isp_bls_b_measured: measured black level B (0x0000003c)*/ +/*! Slice: BLS_B_MEASURED:*/ +/*! Measured black level for B pixels */ +#define MRV_BLS_BLS_B_MEASURED +#define MRV_BLS_BLS_B_MEASURED_MASK 0x00000FFFU +#define MRV_BLS_BLS_B_MEASURED_SHIFT 0U +/*! Register: isp_bls_c_measured: measured black level C (0x00000040)*/ +/*! Slice: BLS_C_MEASURED:*/ +/*! Measured black level for C pixels */ +#define MRV_BLS_BLS_C_MEASURED +#define MRV_BLS_BLS_C_MEASURED_MASK 0x00000FFFU +#define MRV_BLS_BLS_C_MEASURED_SHIFT 0U +/*! Register: isp_bls_d_measured: measured black level D (0x00000044)*/ +/*! Slice: BLS_D_MEASURED:*/ +/*! Measured black level for D pixels */ +#define MRV_BLS_BLS_D_MEASURED +#define MRV_BLS_BLS_D_MEASURED_MASK 0x00000FFFU +#define MRV_BLS_BLS_D_MEASURED_SHIFT 0U +/*! Register: isp_dpf_mode: Mode control for Denoising Pre-Filter block (0x00000000)*/ +/*! Slice: USE_NF_GAIN:*/ +/*! 1: DPF_NF_GAINs will be used.*/ +/* 0: DPF_NF_GAINs will not be used. *Default**/ +#define MRV_DPF_USE_NF_GAIN +#define MRV_DPF_USE_NF_GAIN_MASK 0x00000200U +#define MRV_DPF_USE_NF_GAIN_SHIFT 9U +/*! Slice: LSC_GAIN_COMP:*/ +/*! 1: LSC gain will be processed */ +/* 0: LSC gain will not be processed. Use LSC gain factor of 1. *Default**/ +#define MRV_DPF_LSC_GAIN_COMP +#define MRV_DPF_LSC_GAIN_COMP_MASK 0x00000100U +#define MRV_DPF_LSC_GAIN_COMP_SHIFT 8U +/*! Slice: AWB_GAIN_COMP:*/ +/*! Only relevant when use_nf_gain == 0 && ISP_CTRL::ISP_AWB_ENABLE ==1 */ +/* 1: ISP_AWB gains will be processed */ +/* 0: ISP_AWB gains will not be processed. Use AWB gain factor of 1. *Default**/ +#define MRV_DPF_AWB_GAIN_COMP +#define MRV_DPF_AWB_GAIN_COMP_MASK 0x00000080U +#define MRV_DPF_AWB_GAIN_COMP_SHIFT 7U +/*! Slice: NLL_SEGMENTATION:*/ +/*! 1: optimized logarithmic like segmentation for Noise Level Lookup (NLL)*/ +/* 0: equidistant segmentation for NLL *Default**/ +#define MRV_DPF_NLL_SEGMENTATION +#define MRV_DPF_NLL_SEGMENTATION_MASK 0x00000040U +#define MRV_DPF_NLL_SEGMENTATION_SHIFT 6U +/*! Slice: RB_FILTER_SIZE:*/ +/*! 1: Red and Blue filter kernel size of 9x9 (5x5 active) pixels */ +/* 0: Wide Red and Blue filter kernel size of 13x9 (7x5 active) pixels *Default**/ +#define MRV_DPF_RB_FILTER_SIZE +#define MRV_DPF_RB_FILTER_SIZE_MASK 0x00000020U +#define MRV_DPF_RB_FILTER_SIZE_SHIFT 5U +/*! Slice: R_FILTER_OFF:*/ +/*! 1: disable filter processing for red pixels (R)*/ +/* 0: filter R pixels *Default**/ +#define MRV_DPF_R_FILTER_OFF +#define MRV_DPF_R_FILTER_OFF_MASK 0x00000010U +#define MRV_DPF_R_FILTER_OFF_SHIFT 4U +/*! Slice: GR_FILTER_OFF:*/ +/*! 1: disable filter processing for green pixels in green/red lines (GR)*/ +/* 0: filter GR pixels *Default**/ +#define MRV_DPF_GR_FILTER_OFF +#define MRV_DPF_GR_FILTER_OFF_MASK 0x00000008U +#define MRV_DPF_GR_FILTER_OFF_SHIFT 3U +/*! Slice: GB_FILTER_OFF:*/ +/*! 1: disable filter processing for green pixels in green/blue lines (GB)*/ +/* 0: filter GB pixels *Default**/ +#define MRV_DPF_GB_FILTER_OFF +#define MRV_DPF_GB_FILTER_OFF_MASK 0x00000004U +#define MRV_DPF_GB_FILTER_OFF_SHIFT 2U +/*! Slice: B_FILTER_OFF:*/ +/*! 1: disable filter processing for blue pixels (B)*/ +/* 0: filter B pixels *Default**/ +#define MRV_DPF_B_FILTER_OFF +#define MRV_DPF_B_FILTER_OFF_MASK 0x00000002U +#define MRV_DPF_B_FILTER_OFF_SHIFT 1U +/*! Slice: DPF_ENABLE:*/ +/*! 1: enable dpf */ +/* 0: bypass dpf *Default**/ +#define MRV_DPF_DPF_ENABLE +#define MRV_DPF_DPF_ENABLE_MASK 0x00000001U +#define MRV_DPF_DPF_ENABLE_SHIFT 0U +/*! Register: isp_dpf_strength_r: filter strength of the RED filter (0x00000004)*/ +/*! Slice: INV_WEIGHT_R:*/ +/*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#define MRV_DPF_INV_WEIGHT_R +#define MRV_DPF_INV_WEIGHT_R_MASK 0x000000FFU +#define MRV_DPF_INV_WEIGHT_R_SHIFT 0U +/*! Register: isp_dpf_strength_g: filter strength of the GREEN filter (0x00000008)*/ +/*! Slice: INV_WEIGHT_G:*/ +/*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#define MRV_DPF_INV_WEIGHT_G +#define MRV_DPF_INV_WEIGHT_G_MASK 0x000000FFU +#define MRV_DPF_INV_WEIGHT_G_SHIFT 0U +/*! Register: isp_dpf_strength_b: filter strength of the BLUE filter (0x0000000c)*/ +/*! Slice: INV_WEIGHT_B:*/ +/*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/ + /**/ +/* The following values show examples:*/ +/* weight=0.251 -> 255, weight=0.5 -> 128,*/ +/* weight=1 -> 64 *default**/ +/* weight=1.25 -> 51, weight=1.5 -> 42,*/ +/* weight=1.75 -> 37, weight=2 -> 32 */ +#define MRV_DPF_INV_WEIGHT_B +#define MRV_DPF_INV_WEIGHT_B_MASK 0x000000FFU +#define MRV_DPF_INV_WEIGHT_B_SHIFT 0U +/*! Register: isp_dpf_s_weight_g_1_4: Spatial Weights green channel 1 2 3 4 (0x00000010)*/ +/*! Slice: S_WEIGHT_G4:*/ +/*! Filter Coefficient green channel S_WEIGHT_G4 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G4 +#define MRV_DPF_S_WEIGHT_G4_MASK 0x1F000000U +#define MRV_DPF_S_WEIGHT_G4_SHIFT 24U +/*! Slice: S_WEIGHT_G3:*/ +/*! Filter Coefficient green channel S_WEIGHT_G3 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G3 +#define MRV_DPF_S_WEIGHT_G3_MASK 0x001F0000U +#define MRV_DPF_S_WEIGHT_G3_SHIFT 16U +/*! Slice: S_WEIGHT_G2:*/ +/*! Filter Coefficient green channel S_WEIGHT_G2 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G2 +#define MRV_DPF_S_WEIGHT_G2_MASK 0x00001F00U +#define MRV_DPF_S_WEIGHT_G2_SHIFT 8U +/*! Slice: S_WEIGHT_G1:*/ +/*! Filter Coefficient green channel S_WEIGHT_G1 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G1 +#define MRV_DPF_S_WEIGHT_G1_MASK 0x0000001FU +#define MRV_DPF_S_WEIGHT_G1_SHIFT 0U +/*! Register: isp_dpf_s_weight_g_5_6: Spatial Weights green channel 5 6 (0x00000014)*/ +/*! Slice: S_WEIGHT_G6:*/ +/*! Filter Coefficient green channel S_WEIGHT_G6 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G6 +#define MRV_DPF_S_WEIGHT_G6_MASK 0x00001F00U +#define MRV_DPF_S_WEIGHT_G6_SHIFT 8U +/*! Slice: S_WEIGHT_G5:*/ +/*! Filter Coefficient green channel S_WEIGHT_G5 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_G5 +#define MRV_DPF_S_WEIGHT_G5_MASK 0x0000001FU +#define MRV_DPF_S_WEIGHT_G5_SHIFT 0U +/*! Register: isp_dpf_s_weight_rb_1_4: Spatial Weights red/blue channels 1 2 3 4 (0x00000018)*/ +/*! Slice: S_WEIGHT_RB4:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB4 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB4 +#define MRV_DPF_S_WEIGHT_RB4_MASK 0x1F000000U +#define MRV_DPF_S_WEIGHT_RB4_SHIFT 24U +/*! Slice: S_WEIGHT_RB3:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB3 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB3 +#define MRV_DPF_S_WEIGHT_RB3_MASK 0x001F0000U +#define MRV_DPF_S_WEIGHT_RB3_SHIFT 16U +/*! Slice: S_WEIGHT_RB2:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB2 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB2 +#define MRV_DPF_S_WEIGHT_RB2_MASK 0x00001F00U +#define MRV_DPF_S_WEIGHT_RB2_SHIFT 8U +/*! Slice: S_WEIGHT_RB1:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB1 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB1 +#define MRV_DPF_S_WEIGHT_RB1_MASK 0x0000001FU +#define MRV_DPF_S_WEIGHT_RB1_SHIFT 0U +/*! Register: isp_dpf_s_weight_rb_5_6: Spatial Weights red/blue channels 5 6 (0x0000001c)*/ +/*! Slice: S_WEIGHT_RB6:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB6 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB6 +#define MRV_DPF_S_WEIGHT_RB6_MASK 0x00001F00U +#define MRV_DPF_S_WEIGHT_RB6_SHIFT 8U +/*! Slice: S_WEIGHT_RB5:*/ +/*! Filter Coefficient red/blue channels S_WEIGHT_RB5 */ +/* 5 bit unsigned, value range 1/16 to 16/16 */ +/* Default value is 16/16 (*Default*)*/ +#define MRV_DPF_S_WEIGHT_RB5 +#define MRV_DPF_S_WEIGHT_RB5_MASK 0x0000001FU +#define MRV_DPF_S_WEIGHT_RB5_SHIFT 0U +/*! Register array: isp_dpf_nll_coeff: Noise Level Lookup Coefficient (0x0040 + n*0x4 (n=0..16))*/ +/*! Slice: nll_coeff_n:*/ +/* Noise Level Lookup Table Coefficient nll_coeff_n */ +/* 10 bit unsigned, value range 1/1024 to 1023/1024 (*Default*)*/ +#define MRV_DPF_NLL_COEFF_N +#define MRV_DPF_NLL_COEFF_N_MASK 0x000003FFU +#define MRV_DPF_NLL_COEFF_N_SHIFT 0U +/*! Register: isp_dpf_nf_gain_r: noise function gain for red pixels (0x00000064)*/ +/*! Slice: DPF_NF_GAIN_R:*/ +/*! Noise Function (NF) Gain that replaces the AWB gain for red pixels.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#define MRV_DPF_DPF_NF_GAIN_R +#define MRV_DPF_DPF_NF_GAIN_R_MASK 0x00000FFFU +#define MRV_DPF_DPF_NF_GAIN_R_SHIFT 0U +/*! Register: isp_dpf_nf_gain_gr: noise function gain for green in red pixels (0x00000068)*/ +/*! Slice: DPF_NF_GAIN_GR:*/ +/*! Noise Function (NF) Gain that replaces the AWB gain for green pixels in a red line.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#define MRV_DPF_DPF_NF_GAIN_GR +#define MRV_DPF_DPF_NF_GAIN_GR_MASK 0x00000FFFU +#define MRV_DPF_DPF_NF_GAIN_GR_SHIFT 0U +/*! Register: isp_dpf_nf_gain_gb: noise function gain for green in blue pixels (0x0000006c)*/ +/*! Slice: DPF_NF_GAIN_GB:*/ +/*! Noise Function (NF) Gain that replaces the AWB gain for green pixels in a blue line.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#define MRV_DPF_DPF_NF_GAIN_GB +#define MRV_DPF_DPF_NF_GAIN_GB_MASK 0x00000FFFU +#define MRV_DPF_DPF_NF_GAIN_GB_SHIFT 0U +/*! Register: isp_dpf_nf_gain_b: noise function gain for blue pixels (0x00000070)*/ +/*! Slice: DPF_NF_GAIN_B:*/ +/*! Noise Function (NF) Gain that replaces the AWB gain for blue pixels.*/ +/* 12 bit unsigned integer format: gain=1 -> 0x100 */ +#define MRV_DPF_DPF_NF_GAIN_B +#define MRV_DPF_DPF_NF_GAIN_B_MASK 0x00000FFFU +#define MRV_DPF_DPF_NF_GAIN_B_SHIFT 0U +/*! Register: isp_dpcc_mode: Mode control for DPCC detection unit (0x00000000)*/ +/*! Slice: STAGE1_ENABLE:*/ +/*! 1: enable stage1 *Default**/ +/* 0: bypass stage1 */ +#define MRV_DPCC_STAGE1_ENABLE +#define MRV_DPCC_STAGE1_ENABLE_MASK 0x00000004U +#define MRV_DPCC_STAGE1_ENABLE_SHIFT 2U +/*! Slice: GRAYSCALE_MODE:*/ +/*! 1: enable gray scale data input from black and white sensors (without color filter array)*/ +/* 0: BAYER DATA INPUT *Default**/ +#define MRV_DPCC_GRAYSCALE_MODE +#define MRV_DPCC_GRAYSCALE_MODE_MASK 0x00000002U +#define MRV_DPCC_GRAYSCALE_MODE_SHIFT 1U +/*! Slice: ISP_DPCC_enable:*/ +/*! 1: enable DPCC */ +/* 0: bypass DPCC *Default**/ +#define MRV_DPCC_ISP_DPCC_ENABLE +#define MRV_DPCC_ISP_DPCC_ENABLE_MASK 0x00000001U +#define MRV_DPCC_ISP_DPCC_ENABLE_SHIFT 0U +/*! Register: isp_dpcc_output_mode: Interpolation mode for correction unit (0x00000004)*/ +/*! Slice: STAGE1_RB_3x3:*/ +/*! 1: stage1 red/blue 9 pixel (3x3) output median */ +/* 0: stage1 red/blue 4 or 5 pixel output median *Default**/ +#define MRV_DPCC_STAGE1_RB_3X3 +#define MRV_DPCC_STAGE1_RB_3X3_MASK 0x00000008U +#define MRV_DPCC_STAGE1_RB_3X3_SHIFT 3U +/*! Slice: STAGE1_G_3x3:*/ +/*! 1: stage1 green 9 pixel (3x3) output median */ +/* 0: stage1 green 4 or 5 pixel output median *Default**/ +#define MRV_DPCC_STAGE1_G_3X3 +#define MRV_DPCC_STAGE1_G_3X3_MASK 0x00000004U +#define MRV_DPCC_STAGE1_G_3X3_SHIFT 2U +/*! Slice: STAGE1_INCL_RB_CENTER:*/ +/*! 1: stage1 include center pixel for red/blue output median 2x2+1 */ +/* *Default* 0: stage1 do not include center pixel for red/blue output median 2x2 */ +#define MRV_DPCC_STAGE1_INCL_RB_CENTER +#define MRV_DPCC_STAGE1_INCL_RB_CENTER_MASK 0x00000002U +#define MRV_DPCC_STAGE1_INCL_RB_CENTER_SHIFT 1U +/*! Slice: STAGE1_INCL_GREEN_CENTER:*/ +/*! 1: stage1 include center pixel for green output median 2x2+1 *Default**/ +/* 0: stage1 do not include center pixel for green output median 2x2 */ +#define MRV_DPCC_STAGE1_INCL_GREEN_CENTER +#define MRV_DPCC_STAGE1_INCL_GREEN_CENTER_MASK 0x00000001U +#define MRV_DPCC_STAGE1_INCL_GREEN_CENTER_SHIFT 0U +/*! Register: isp_dpcc_set_use: DPCC methods set usage for detection (0x00000008)*/ +/*! Slice: STAGE1_USE_FIX_SET:*/ +/*! 1: stage1 use hard coded methods set *Default**/ +/* 0: stage1 do not use hard coded methods set */ +#define MRV_DPCC_STAGE1_USE_FIX_SET +#define MRV_DPCC_STAGE1_USE_FIX_SET_MASK 0x00000008U +#define MRV_DPCC_STAGE1_USE_FIX_SET_SHIFT 3U +/*! Slice: STAGE1_USE_SET_3:*/ +/*! 1: stage1 use methods set 3 */ +/* 0: stage1 do not use methods set 3 *Default**/ +#define MRV_DPCC_STAGE1_USE_SET_3 +#define MRV_DPCC_STAGE1_USE_SET_3_MASK 0x00000004U +#define MRV_DPCC_STAGE1_USE_SET_3_SHIFT 2U +/*! Slice: STAGE1_USE_SET_2:*/ +/*! 1: stage1 use methods set 2 */ +/* 0: stage1 do not use methods set 2 *Default**/ +#define MRV_DPCC_STAGE1_USE_SET_2 +#define MRV_DPCC_STAGE1_USE_SET_2_MASK 0x00000002U +#define MRV_DPCC_STAGE1_USE_SET_2_SHIFT 1U +/*! Slice: STAGE1_USE_SET_1:*/ +/*! 1: stage1 use methods set 1 *Default**/ +/* 0: stage1 do not use methods set 1 */ +#define MRV_DPCC_STAGE1_USE_SET_1 +#define MRV_DPCC_STAGE1_USE_SET_1_MASK 0x00000001U +#define MRV_DPCC_STAGE1_USE_SET_1_SHIFT 0U +/*! Register: isp_dpcc_methods_set_1: Methods enable bits for SET_1 (0x0000000c)*/ +/*! Slice: RG_RED_BLUE1_ENABLE:*/ +/*! 1: enable Rank Gradient check for red_blue *Default**/ +/* 0: bypass Rank Gradient check for red_blue */ +#define MRV_DPCC_RG_RED_BLUE1_ENABLE +#define MRV_DPCC_RG_RED_BLUE1_ENABLE_MASK 0x00001000U +#define MRV_DPCC_RG_RED_BLUE1_ENABLE_SHIFT 12U +/*! Slice: RND_RED_BLUE1_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for red_blue *Default**/ +/* 0: bypass Rank Neighbor Difference check for red_blue */ +#define MRV_DPCC_RND_RED_BLUE1_ENABLE +#define MRV_DPCC_RND_RED_BLUE1_ENABLE_MASK 0x00000800U +#define MRV_DPCC_RND_RED_BLUE1_ENABLE_SHIFT 11U +/*! Slice: RO_RED_BLUE1_ENABLE:*/ +/*! 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#define MRV_DPCC_RO_RED_BLUE1_ENABLE +#define MRV_DPCC_RO_RED_BLUE1_ENABLE_MASK 0x00000400U +#define MRV_DPCC_RO_RED_BLUE1_ENABLE_SHIFT 10U +/*! Slice: LC_RED_BLUE1_ENABLE:*/ +/*! 1: enable Line check for red_blue *Default**/ +/* 0: bypass Line check for red_blue */ +#define MRV_DPCC_LC_RED_BLUE1_ENABLE +#define MRV_DPCC_LC_RED_BLUE1_ENABLE_MASK 0x00000200U +#define MRV_DPCC_LC_RED_BLUE1_ENABLE_SHIFT 9U +/*! Slice: PG_RED_BLUE1_ENABLE:*/ +/*! 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#define MRV_DPCC_PG_RED_BLUE1_ENABLE +#define MRV_DPCC_PG_RED_BLUE1_ENABLE_MASK 0x00000100U +#define MRV_DPCC_PG_RED_BLUE1_ENABLE_SHIFT 8U +/*! Slice: RG_GREEN1_ENABLE:*/ +/*! 1: enable Rank Gradient check for green *Default**/ +/* 0: bypass Rank Gradient check for green */ +#define MRV_DPCC_RG_GREEN1_ENABLE +#define MRV_DPCC_RG_GREEN1_ENABLE_MASK 0x00000010U +#define MRV_DPCC_RG_GREEN1_ENABLE_SHIFT 4U +/*! Slice: RND_GREEN1_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for green *Default**/ +/* 0: bypass Rank Neighbor Difference check for green */ +#define MRV_DPCC_RND_GREEN1_ENABLE +#define MRV_DPCC_RND_GREEN1_ENABLE_MASK 0x00000008U +#define MRV_DPCC_RND_GREEN1_ENABLE_SHIFT 3U +/*! Slice: RO_GREEN1_ENABLE:*/ +/*! 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#define MRV_DPCC_RO_GREEN1_ENABLE +#define MRV_DPCC_RO_GREEN1_ENABLE_MASK 0x00000004U +#define MRV_DPCC_RO_GREEN1_ENABLE_SHIFT 2U +/*! Slice: LC_GREEN1_ENABLE:*/ +/*! 1: enable Line check for green *Default**/ +/* 0: bypass Line check for green */ +#define MRV_DPCC_LC_GREEN1_ENABLE +#define MRV_DPCC_LC_GREEN1_ENABLE_MASK 0x00000002U +#define MRV_DPCC_LC_GREEN1_ENABLE_SHIFT 1U +/*! Slice: PG_GREEN1_ENABLE:*/ +/*! 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#define MRV_DPCC_PG_GREEN1_ENABLE +#define MRV_DPCC_PG_GREEN1_ENABLE_MASK 0x00000001U +#define MRV_DPCC_PG_GREEN1_ENABLE_SHIFT 0U +/*! Register: isp_dpcc_methods_set_2: Methods enable bits for SET_2 (0x00000010)*/ +/*! Slice: RG_RED_BLUE2_ENABLE:*/ +/*! 1: enable Rank Gradient check for red_blue *Default**/ +/* 0: bypass Rank Gradient check for red_blue */ +#define MRV_DPCC_RG_RED_BLUE2_ENABLE +#define MRV_DPCC_RG_RED_BLUE2_ENABLE_MASK 0x00001000U +#define MRV_DPCC_RG_RED_BLUE2_ENABLE_SHIFT 12U +/*! Slice: RND_RED_BLUE2_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for red_blue *Default**/ +/* 0: bypass Rank Neighbor Difference check for red_blue */ +#define MRV_DPCC_RND_RED_BLUE2_ENABLE +#define MRV_DPCC_RND_RED_BLUE2_ENABLE_MASK 0x00000800U +#define MRV_DPCC_RND_RED_BLUE2_ENABLE_SHIFT 11U +/*! Slice: RO_RED_BLUE2_ENABLE:*/ +/*! 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#define MRV_DPCC_RO_RED_BLUE2_ENABLE +#define MRV_DPCC_RO_RED_BLUE2_ENABLE_MASK 0x00000400U +#define MRV_DPCC_RO_RED_BLUE2_ENABLE_SHIFT 10U +/*! Slice: LC_RED_BLUE2_ENABLE:*/ +/*! 1: enable Line check for red_blue */ +/* 0: bypass Line check for red_blue *Default**/ +#define MRV_DPCC_LC_RED_BLUE2_ENABLE +#define MRV_DPCC_LC_RED_BLUE2_ENABLE_MASK 0x00000200U +#define MRV_DPCC_LC_RED_BLUE2_ENABLE_SHIFT 9U +/*! Slice: PG_RED_BLUE2_ENABLE:*/ +/*! 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#define MRV_DPCC_PG_RED_BLUE2_ENABLE +#define MRV_DPCC_PG_RED_BLUE2_ENABLE_MASK 0x00000100U +#define MRV_DPCC_PG_RED_BLUE2_ENABLE_SHIFT 8U +/*! Slice: RG_GREEN2_ENABLE:*/ +/*! 1: enable Rank Gradient check for green *Default**/ +/* 0: bypass Rank Gradient check for green */ +#define MRV_DPCC_RG_GREEN2_ENABLE +#define MRV_DPCC_RG_GREEN2_ENABLE_MASK 0x00000010U +#define MRV_DPCC_RG_GREEN2_ENABLE_SHIFT 4U +/*! Slice: RND_GREEN2_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for green *Default**/ +/* 0: bypass Rank Neighbor Difference check for green */ +#define MRV_DPCC_RND_GREEN2_ENABLE +#define MRV_DPCC_RND_GREEN2_ENABLE_MASK 0x00000008U +#define MRV_DPCC_RND_GREEN2_ENABLE_SHIFT 3U +/*! Slice: RO_GREEN2_ENABLE:*/ +/*! 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#define MRV_DPCC_RO_GREEN2_ENABLE +#define MRV_DPCC_RO_GREEN2_ENABLE_MASK 0x00000004U +#define MRV_DPCC_RO_GREEN2_ENABLE_SHIFT 2U +/*! Slice: LC_GREEN2_ENABLE:*/ +/*! 1: enable Line check for green */ +/* 0: bypass Line check for green *Default**/ +#define MRV_DPCC_LC_GREEN2_ENABLE +#define MRV_DPCC_LC_GREEN2_ENABLE_MASK 0x00000002U +#define MRV_DPCC_LC_GREEN2_ENABLE_SHIFT 1U +/*! Slice: PG_GREEN2_ENABLE:*/ +/*! 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#define MRV_DPCC_PG_GREEN2_ENABLE +#define MRV_DPCC_PG_GREEN2_ENABLE_MASK 0x00000001U +#define MRV_DPCC_PG_GREEN2_ENABLE_SHIFT 0U +/*! Register: isp_dpcc_methods_set_3: Methods enable bits for SET_3 (0x00000014)*/ +/*! Slice: RG_RED_BLUE3_ENABLE:*/ +/*! 1: enable Rank Gradient check for red_blue */ +/* 0: bypass Rank Gradient check for red_blue *Default**/ +#define MRV_DPCC_RG_RED_BLUE3_ENABLE +#define MRV_DPCC_RG_RED_BLUE3_ENABLE_MASK 0x00001000U +#define MRV_DPCC_RG_RED_BLUE3_ENABLE_SHIFT 12U +/*! Slice: RND_RED_BLUE3_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for red_blue */ +/* 0: bypass Rank Neighbor Difference check for red_blue *Default**/ +#define MRV_DPCC_RND_RED_BLUE3_ENABLE +#define MRV_DPCC_RND_RED_BLUE3_ENABLE_MASK 0x00000800U +#define MRV_DPCC_RND_RED_BLUE3_ENABLE_SHIFT 11U +/*! Slice: RO_RED_BLUE3_ENABLE:*/ +/*! 1: enable Rank Order check for red_blue *Default**/ +/* 0: bypass Rank Order check for red_blue */ +#define MRV_DPCC_RO_RED_BLUE3_ENABLE +#define MRV_DPCC_RO_RED_BLUE3_ENABLE_MASK 0x00000400U +#define MRV_DPCC_RO_RED_BLUE3_ENABLE_SHIFT 10U +/*! Slice: LC_RED_BLUE3_ENABLE:*/ +/*! 1: enable Line check for red_blue *Default**/ +/* 0: bypass Line check for red_blue */ +#define MRV_DPCC_LC_RED_BLUE3_ENABLE +#define MRV_DPCC_LC_RED_BLUE3_ENABLE_MASK 0x00000200U +#define MRV_DPCC_LC_RED_BLUE3_ENABLE_SHIFT 9U +/*! Slice: PG_RED_BLUE3_ENABLE:*/ +/*! 1: enable Peak Gradient check for red_blue *Default**/ +/* 0: bypass Peak Gradient check for red_blue */ +#define MRV_DPCC_PG_RED_BLUE3_ENABLE +#define MRV_DPCC_PG_RED_BLUE3_ENABLE_MASK 0x00000100U +#define MRV_DPCC_PG_RED_BLUE3_ENABLE_SHIFT 8U +/*! Slice: RG_GREEN3_ENABLE:*/ +/*! 1: enable Rank Gradient check for green */ +/* 0: bypass Rank Gradient check for green *Default**/ +#define MRV_DPCC_RG_GREEN3_ENABLE +#define MRV_DPCC_RG_GREEN3_ENABLE_MASK 0x00000010U +#define MRV_DPCC_RG_GREEN3_ENABLE_SHIFT 4U +/*! Slice: RND_GREEN3_ENABLE:*/ +/*! 1: enable Rank Neighbor Difference check for green */ +/* 0: bypass Rank Neighbor Difference check for green *Default**/ +#define MRV_DPCC_RND_GREEN3_ENABLE +#define MRV_DPCC_RND_GREEN3_ENABLE_MASK 0x00000008U +#define MRV_DPCC_RND_GREEN3_ENABLE_SHIFT 3U +/*! Slice: RO_GREEN3_ENABLE:*/ +/*! 1: enable Rank Order check for green *Default**/ +/* 0: bypass Rank Order check for green */ +#define MRV_DPCC_RO_GREEN3_ENABLE +#define MRV_DPCC_RO_GREEN3_ENABLE_MASK 0x00000004U +#define MRV_DPCC_RO_GREEN3_ENABLE_SHIFT 2U +/*! Slice: LC_GREEN3_ENABLE:*/ +/*! 1: enable Line check for green *Default**/ +/* 0: bypass Line check for green */ +#define MRV_DPCC_LC_GREEN3_ENABLE +#define MRV_DPCC_LC_GREEN3_ENABLE_MASK 0x00000002U +#define MRV_DPCC_LC_GREEN3_ENABLE_SHIFT 1U +/*! Slice: PG_GREEN3_ENABLE:*/ +/*! 1: enable Peak Gradient check for green *Default**/ +/* 0: bypass Peak Gradient check for green */ +#define MRV_DPCC_PG_GREEN3_ENABLE +#define MRV_DPCC_PG_GREEN3_ENABLE_MASK 0x00000001U +#define MRV_DPCC_PG_GREEN3_ENABLE_SHIFT 0U +/*! Register: isp_dpcc_line_thresh_1: Line threshold SET_1 (0x00000018)*/ +/*! Slice: LINE_THR_1_RB:*/ +/*! line threshold for set 1 red/blue */ +#define MRV_DPCC_LINE_THR_1_RB +#define MRV_DPCC_LINE_THR_1_RB_MASK 0x0000FF00U +#define MRV_DPCC_LINE_THR_1_RB_SHIFT 8U +/*! Slice: LINE_THR_1_G:*/ +/*! line threshold for set 1 green */ +#define MRV_DPCC_LINE_THR_1_G +#define MRV_DPCC_LINE_THR_1_G_MASK 0x000000FFU +#define MRV_DPCC_LINE_THR_1_G_SHIFT 0U +/*! Register: isp_dpcc_line_mad_fac_1: Mean Absolute Difference (MAD) factor for Line check set 1 (0x0000001c)*/ +/*! Slice: LINE_MAD_FAC_1_RB:*/ +/*! line MAD factor for set 1 red/blue */ +#define MRV_DPCC_LINE_MAD_FAC_1_RB +#define MRV_DPCC_LINE_MAD_FAC_1_RB_MASK 0x00003F00U +#define MRV_DPCC_LINE_MAD_FAC_1_RB_SHIFT 8U +/*! Slice: LINE_MAD_FAC_1_G:*/ +/*! line MAD factor for set 1 green */ +#define MRV_DPCC_LINE_MAD_FAC_1_G +#define MRV_DPCC_LINE_MAD_FAC_1_G_MASK 0x0000003FU +#define MRV_DPCC_LINE_MAD_FAC_1_G_SHIFT 0U +/*! Register: isp_dpcc_pg_fac_1: Peak gradient factor for set 1 (0x00000020)*/ +/*! Slice: PG_FAC_1_RB:*/ +/*! Peak gradient factor for set 1 red/blue */ +#define MRV_DPCC_PG_FAC_1_RB +#define MRV_DPCC_PG_FAC_1_RB_MASK 0x00003F00U +#define MRV_DPCC_PG_FAC_1_RB_SHIFT 8U +/*! Slice: PG_FAC_1_G:*/ +/*! Peak gradient factor for set 1 green */ +#define MRV_DPCC_PG_FAC_1_G +#define MRV_DPCC_PG_FAC_1_G_MASK 0x0000003FU +#define MRV_DPCC_PG_FAC_1_G_SHIFT 0U +/*! Register: isp_dpcc_rnd_thresh_1: Rank Neighbor Difference threshold for set 1 (0x00000024)*/ +/*! Slice: RND_THR_1_RB:*/ +/*! Rank Neighbor Difference threshold for set 1 red/blue */ +#define MRV_DPCC_RND_THR_1_RB +#define MRV_DPCC_RND_THR_1_RB_MASK 0x0000FF00U +#define MRV_DPCC_RND_THR_1_RB_SHIFT 8U +/*! Slice: RND_THR_1_G:*/ +/*! Rank Neighbor Difference threshold for set 1 green */ +#define MRV_DPCC_RND_THR_1_G +#define MRV_DPCC_RND_THR_1_G_MASK 0x000000FFU +#define MRV_DPCC_RND_THR_1_G_SHIFT 0U +/*! Register: isp_dpcc_rg_fac_1: Rank gradient factor for set 1 (0x00000028)*/ +/*! Slice: RG_FAC_1_RB:*/ +/*! Rank gradient factor for set 1 red/blue */ +#define MRV_DPCC_RG_FAC_1_RB +#define MRV_DPCC_RG_FAC_1_RB_MASK 0x00003F00U +#define MRV_DPCC_RG_FAC_1_RB_SHIFT 8U +/*! Slice: RG_FAC_1_G:*/ +/*! Rank gradient factor for set 1 green */ +#define MRV_DPCC_RG_FAC_1_G +#define MRV_DPCC_RG_FAC_1_G_MASK 0x0000003FU +#define MRV_DPCC_RG_FAC_1_G_SHIFT 0U +/*! Register: isp_dpcc_line_thresh_2: Line threshold set 2 (0x0000002c)*/ +/*! Slice: LINE_THR_2_RB:*/ +/*! line threshold for set 2 red/blue */ +#define MRV_DPCC_LINE_THR_2_RB +#define MRV_DPCC_LINE_THR_2_RB_MASK 0x0000FF00U +#define MRV_DPCC_LINE_THR_2_RB_SHIFT 8U +/*! Slice: LINE_THR_2_G:*/ +/*! line threshold for set 2 green */ +#define MRV_DPCC_LINE_THR_2_G +#define MRV_DPCC_LINE_THR_2_G_MASK 0x000000FFU +#define MRV_DPCC_LINE_THR_2_G_SHIFT 0U +/*! Register: isp_dpcc_line_mad_fac_2: Mean Absolute Difference (MAD) factor for Line check set 2 (0x00000030)*/ +/*! Slice: LINE_MAD_FAC_2_RB:*/ +/*! line MAD factor for set 2 red/blue */ +#define MRV_DPCC_LINE_MAD_FAC_2_RB +#define MRV_DPCC_LINE_MAD_FAC_2_RB_MASK 0x00003F00U +#define MRV_DPCC_LINE_MAD_FAC_2_RB_SHIFT 8U +/*! Slice: LINE_MAD_FAC_2_G:*/ +/*! line MAD factor for set 2 green */ +#define MRV_DPCC_LINE_MAD_FAC_2_G +#define MRV_DPCC_LINE_MAD_FAC_2_G_MASK 0x0000003FU +#define MRV_DPCC_LINE_MAD_FAC_2_G_SHIFT 0U +/*! Register: isp_dpcc_pg_fac_2: Peak gradient factor for set 2 (0x00000034)*/ +/*! Slice: PG_FAC_2_RB:*/ +/*! Peak gradient factor for set 2 red/blue */ +#define MRV_DPCC_PG_FAC_2_RB +#define MRV_DPCC_PG_FAC_2_RB_MASK 0x00003F00U +#define MRV_DPCC_PG_FAC_2_RB_SHIFT 8U +/*! Slice: PG_FAC_2_G:*/ +/*! Peak gradient factor for set 2 green */ +#define MRV_DPCC_PG_FAC_2_G +#define MRV_DPCC_PG_FAC_2_G_MASK 0x0000003FU +#define MRV_DPCC_PG_FAC_2_G_SHIFT 0U +/*! Register: isp_dpcc_rnd_thresh_2: Rank Neighbor Difference threshold for set 2 (0x00000038)*/ +/*! Slice: RND_THR_2_RB:*/ +/*! Rank Neighbor Difference threshold for set 2 red/blue */ +#define MRV_DPCC_RND_THR_2_RB +#define MRV_DPCC_RND_THR_2_RB_MASK 0x0000FF00U +#define MRV_DPCC_RND_THR_2_RB_SHIFT 8U +/*! Slice: RND_THR_2_G:*/ +/*! Rank Neighbor Difference threshold for set 2 green */ +#define MRV_DPCC_RND_THR_2_G +#define MRV_DPCC_RND_THR_2_G_MASK 0x000000FFU +#define MRV_DPCC_RND_THR_2_G_SHIFT 0U +/*! Register: isp_dpcc_rg_fac_2: Rank gradient factor for set 2 (0x0000003c)*/ +/*! Slice: RG_FAC_2_RB:*/ +/*! Rank gradient factor for set 2 red/blue */ +#define MRV_DPCC_RG_FAC_2_RB +#define MRV_DPCC_RG_FAC_2_RB_MASK 0x00003F00U +#define MRV_DPCC_RG_FAC_2_RB_SHIFT 8U +/*! Slice: RG_FAC_2_G:*/ +/*! Rank gradient factor for set 2 green */ +#define MRV_DPCC_RG_FAC_2_G +#define MRV_DPCC_RG_FAC_2_G_MASK 0x0000003FU +#define MRV_DPCC_RG_FAC_2_G_SHIFT 0U +/*! Register: isp_dpcc_line_thresh_3: Line threshold set 3 (0x00000040)*/ +/*! Slice: LINE_THR_3_RB:*/ +/*! line threshold for set 3 red/blue */ +#define MRV_DPCC_LINE_THR_3_RB +#define MRV_DPCC_LINE_THR_3_RB_MASK 0x0000FF00U +#define MRV_DPCC_LINE_THR_3_RB_SHIFT 8U +/*! Slice: LINE_THR_3_G:*/ +/*! line threshold for set 3 green */ +#define MRV_DPCC_LINE_THR_3_G +#define MRV_DPCC_LINE_THR_3_G_MASK 0x000000FFU +#define MRV_DPCC_LINE_THR_3_G_SHIFT 0U +/*! Register: isp_dpcc_line_mad_fac_3: Mean Absolute Difference (MAD) factor for Line check set 3 (0x00000044)*/ +/*! Slice: LINE_MAD_FAC_3_RB:*/ +/*! line MAD factor for set 3 red/blue */ +#define MRV_DPCC_LINE_MAD_FAC_3_RB +#define MRV_DPCC_LINE_MAD_FAC_3_RB_MASK 0x00003F00U +#define MRV_DPCC_LINE_MAD_FAC_3_RB_SHIFT 8U +/*! Slice: LINE_MAD_FAC_3_G:*/ +/*! line MAD factor for set 3 green */ +#define MRV_DPCC_LINE_MAD_FAC_3_G +#define MRV_DPCC_LINE_MAD_FAC_3_G_MASK 0x0000003FU +#define MRV_DPCC_LINE_MAD_FAC_3_G_SHIFT 0U +/*! Register: isp_dpcc_pg_fac_3: Peak gradient factor for set 3 (0x00000048)*/ +/*! Slice: PG_FAC_3_RB:*/ +/*! Peak gradient factor for set 3 red/blue */ +#define MRV_DPCC_PG_FAC_3_RB +#define MRV_DPCC_PG_FAC_3_RB_MASK 0x00003F00U +#define MRV_DPCC_PG_FAC_3_RB_SHIFT 8U +/*! Slice: PG_FAC_3_G:*/ +/*! Peak gradient factor for set 3 green */ +#define MRV_DPCC_PG_FAC_3_G +#define MRV_DPCC_PG_FAC_3_G_MASK 0x0000003FU +#define MRV_DPCC_PG_FAC_3_G_SHIFT 0U +/*! Register: isp_dpcc_rnd_thresh_3: Rank Neighbor Difference threshold for set 3 (0x0000004c)*/ +/*! Slice: RND_THR_3_RB:*/ +/*! Rank Neighbor Difference threshold for set 3 red/blue */ +#define MRV_DPCC_RND_THR_3_RB +#define MRV_DPCC_RND_THR_3_RB_MASK 0x0000FF00U +#define MRV_DPCC_RND_THR_3_RB_SHIFT 8U +/*! Slice: RND_THR_3_G:*/ +/*! Rank Neighbor Difference threshold for set 3 green */ +#define MRV_DPCC_RND_THR_3_G +#define MRV_DPCC_RND_THR_3_G_MASK 0x000000FFU +#define MRV_DPCC_RND_THR_3_G_SHIFT 0U +/*! Register: isp_dpcc_rg_fac_3: Rank gradient factor for set 3 (0x00000050)*/ +/*! Slice: RG_FAC_3_RB:*/ +/*! Rank gradient factor for set 3 red/blue */ +#define MRV_DPCC_RG_FAC_3_RB +#define MRV_DPCC_RG_FAC_3_RB_MASK 0x00003F00U +#define MRV_DPCC_RG_FAC_3_RB_SHIFT 8U +/*! Slice: RG_FAC_3_G:*/ +/*! Rank gradient factor for set 3 green */ +#define MRV_DPCC_RG_FAC_3_G +#define MRV_DPCC_RG_FAC_3_G_MASK 0x0000003FU +#define MRV_DPCC_RG_FAC_3_G_SHIFT 0U +/*! Register: isp_dpcc_ro_limits: Rank Order Limits (0x00000054)*/ +/*! Slice: RO_LIM_3_RB:*/ +/*! Rank order limit for set 3 red/blue */ +#define MRV_DPCC_RO_LIM_3_RB +#define MRV_DPCC_RO_LIM_3_RB_MASK 0x00000C00U +#define MRV_DPCC_RO_LIM_3_RB_SHIFT 10U +/*! Slice: RO_LIM_3_G:*/ +/*! Rank order limit for set 3 green */ +#define MRV_DPCC_RO_LIM_3_G +#define MRV_DPCC_RO_LIM_3_G_MASK 0x00000300U +#define MRV_DPCC_RO_LIM_3_G_SHIFT 8U +/*! Slice: RO_LIM_2_RB:*/ +/*! Rank order limit for set 2 red/blue */ +#define MRV_DPCC_RO_LIM_2_RB +#define MRV_DPCC_RO_LIM_2_RB_MASK 0x000000C0U +#define MRV_DPCC_RO_LIM_2_RB_SHIFT 6U +/*! Slice: RO_LIM_2_G:*/ +/*! Rank order limit for set 2 green */ +#define MRV_DPCC_RO_LIM_2_G +#define MRV_DPCC_RO_LIM_2_G_MASK 0x00000030U +#define MRV_DPCC_RO_LIM_2_G_SHIFT 4U +/*! Slice: RO_LIM_1_RB:*/ +/*! Rank order limit for set 1 red/blue */ +#define MRV_DPCC_RO_LIM_1_RB +#define MRV_DPCC_RO_LIM_1_RB_MASK 0x0000000CU +#define MRV_DPCC_RO_LIM_1_RB_SHIFT 2U +/*! Slice: RO_LIM_1_G:*/ +/*! Rank order limit for set 1 green */ +#define MRV_DPCC_RO_LIM_1_G +#define MRV_DPCC_RO_LIM_1_G_MASK 0x00000003U +#define MRV_DPCC_RO_LIM_1_G_SHIFT 0U +/*! Register: isp_dpcc_rnd_offs: Differential Rank Offsets for Rank Neighbor Difference (0x00000058)*/ +/*! Slice: RND_OFFS_3_RB:*/ +/*! Rank Offset to Neighbor for set 3 red/blue */ +#define MRV_DPCC_RND_OFFS_3_RB +#define MRV_DPCC_RND_OFFS_3_RB_MASK 0x00000C00U +#define MRV_DPCC_RND_OFFS_3_RB_SHIFT 10U +/*! Slice: RND_OFFS_3_G:*/ +/*! Rank Offset to Neighbor for set 3 green */ +#define MRV_DPCC_RND_OFFS_3_G +#define MRV_DPCC_RND_OFFS_3_G_MASK 0x00000300U +#define MRV_DPCC_RND_OFFS_3_G_SHIFT 8U +/*! Slice: RND_OFFS_2_RB:*/ +/*! Rank Offset to Neighbor for set 2 red/blue */ +#define MRV_DPCC_RND_OFFS_2_RB +#define MRV_DPCC_RND_OFFS_2_RB_MASK 0x000000C0U +#define MRV_DPCC_RND_OFFS_2_RB_SHIFT 6U +/*! Slice: RND_OFFS_2_G:*/ +/*! Rank Offset to Neighbor for set 2 green */ +#define MRV_DPCC_RND_OFFS_2_G +#define MRV_DPCC_RND_OFFS_2_G_MASK 0x00000030U +#define MRV_DPCC_RND_OFFS_2_G_SHIFT 4U +/*! Slice: RND_OFFS_1_RB:*/ +/*! Rank Offset to Neighbor for set 1 red/blue */ +#define MRV_DPCC_RND_OFFS_1_RB +#define MRV_DPCC_RND_OFFS_1_RB_MASK 0x0000000CU +#define MRV_DPCC_RND_OFFS_1_RB_SHIFT 2U +/*! Slice: RND_OFFS_1_G:*/ +/*! Rank Offset to Neighbor for set 1 green */ +#define MRV_DPCC_RND_OFFS_1_G +#define MRV_DPCC_RND_OFFS_1_G_MASK 0x00000003U +#define MRV_DPCC_RND_OFFS_1_G_SHIFT 0U +/*! Register: isp_dpcc_bpt_ctrl: bad pixel table settings (0x0000005c)*/ +/*! Slice: BPT_RB_3x3:*/ +/*! 1: if BPT active red/blue 9 pixel (3x3) output median */ +/* 0: if BPT active red/blue 4 or 5 pixel output median *Default**/ +#define MRV_DPCC_BPT_RB_3X3 +#define MRV_DPCC_BPT_RB_3X3_MASK 0x00000800U +#define MRV_DPCC_BPT_RB_3X3_SHIFT 11U +/*! Slice: BPT_G_3x3:*/ +/*! 1: if BPT active green 9 pixel (3x3) output median */ +/* 0: if BPT active green 4 or 5 pixel output median *Default**/ +#define MRV_DPCC_BPT_G_3X3 +#define MRV_DPCC_BPT_G_3X3_MASK 0x00000400U +#define MRV_DPCC_BPT_G_3X3_SHIFT 10U +/*! Slice: BPT_INCL_RB_CENTER:*/ +/*! 1: if BPT active include center pixel for red/blue output median 2x2+1 */ +/* 0: if BPT active do not include center pixel for red/blue output median 2x2 *Default**/ +#define MRV_DPCC_BPT_INCL_RB_CENTER +#define MRV_DPCC_BPT_INCL_RB_CENTER_MASK 0x00000200U +#define MRV_DPCC_BPT_INCL_RB_CENTER_SHIFT 9U +/*! Slice: BPT_INCL_GREEN_CENTER:*/ +/*! 1: if BPT active include center pixel for green output median 2x2+1 */ +/* 0: if BPT active do not include center pixel for green output median 2x2 *Default**/ +#define MRV_DPCC_BPT_INCL_GREEN_CENTER +#define MRV_DPCC_BPT_INCL_GREEN_CENTER_MASK 0x00000100U +#define MRV_DPCC_BPT_INCL_GREEN_CENTER_SHIFT 8U +/*! Slice: BPT_USE_FIX_SET:*/ +/*! 1: for BPT write use hard coded methods set */ +/* 0: for BPT write do not use hard coded methods set *Default**/ +#define MRV_DPCC_BPT_USE_FIX_SET +#define MRV_DPCC_BPT_USE_FIX_SET_MASK 0x00000080U +#define MRV_DPCC_BPT_USE_FIX_SET_SHIFT 7U +/*! Slice: BPT_USE_SET_3:*/ +/*! 1: for BPT write use methods set 3 */ +/* 0: for BPT write do not use methods set 3 *Default**/ +#define MRV_DPCC_BPT_USE_SET_3 +#define MRV_DPCC_BPT_USE_SET_3_MASK 0x00000040U +#define MRV_DPCC_BPT_USE_SET_3_SHIFT 6U +/*! Slice: BPT_USE_SET_2:*/ +/*! 1: for BPT write use methods set 2 */ +/* 0: for BPT write do not use methods set 2 *Default**/ +#define MRV_DPCC_BPT_USE_SET_2 +#define MRV_DPCC_BPT_USE_SET_2_MASK 0x00000020U +#define MRV_DPCC_BPT_USE_SET_2_SHIFT 5U +/*! Slice: BPT_USE_SET_1:*/ +/*! 1: for BPT write use methods set 1 */ +/* 0: for BPT write do not use methods set 1 *Default**/ +#define MRV_DPCC_BPT_USE_SET_1 +#define MRV_DPCC_BPT_USE_SET_1_MASK 0x00000010U +#define MRV_DPCC_BPT_USE_SET_1_SHIFT 4U +/*! Slice: bpt_cor_en:*/ +/*! table based correction enable */ +/* 1: table based correction is enabled */ +/* 0: table based correction is disabled */ +#define MRV_DPCC_BPT_COR_EN +#define MRV_DPCC_BPT_COR_EN_MASK 0x00000002U +#define MRV_DPCC_BPT_COR_EN_SHIFT 1U +/*! Slice: bpt_det_en:*/ +/*! Bad pixel detection write enable */ +/* 1: bad pixel detection write to memory is enabled */ +/* 0: bad pixel detection write to memory is disabled */ +#define MRV_DPCC_BPT_DET_EN +#define MRV_DPCC_BPT_DET_EN_MASK 0x00000001U +#define MRV_DPCC_BPT_DET_EN_SHIFT 0U +/*! Register: isp_dpcc_bpt_number: Number of entries for bad pixel table (table based correction) (0x00000060)*/ +/*! Slice: bp_number:*/ +/*! Number of current Bad Pixel entries in bad pixel table (BPT)*/ +#define MRV_DPCC_BP_NUMBER +#define MRV_DPCC_BP_NUMBER_MASK 0x00000FFFU +#define MRV_DPCC_BP_NUMBER_SHIFT 0U +/*! Register: isp_dpcc_bpt_addr: TABLE Start Address for table-based correction algorithm (0x00000064)*/ +/*! Slice: bp_table_addr:*/ +/*! Table RAM start address for read or write operations. The address counter is incremented at each read or write access to the data register (auto-increment mechanism).*/ +#define MRV_DPCC_BP_TABLE_ADDR +#define MRV_DPCC_BP_TABLE_ADDR_MASK 0x000007FFU +#define MRV_DPCC_BP_TABLE_ADDR_SHIFT 0U +/*! Register: isp_dpcc_bpt_data: TABLE DATA register for read and write access of table RAM (0x00000068)*/ +/*! Slice: bpt_v_addr:*/ +/*! Bad Pixel vertical address (pixel position)*/ +#define MRV_DPCC_BPT_V_ADDR +#define MRV_DPCC_BPT_V_ADDR_MASK 0x0FFF0000U +#define MRV_DPCC_BPT_V_ADDR_SHIFT 16U +/*! Slice: bpt_h_addr:*/ +/*! Bad Pixel horizontal address (pixel position)*/ +#define MRV_DPCC_BPT_H_ADDR +#define MRV_DPCC_BPT_H_ADDR_MASK 0x00001FFFU +#define MRV_DPCC_BPT_H_ADDR_SHIFT 0U +/*! Register: isp_wdr_ctrl: Control Bits for Wide Dynamic Range Unit (0x00000000)*/ +/*! Slice: WDR_RGB_FACTOR:*/ +/*! rgb_factor defines how much influence the RGBmax approach has in comparison to Y. The illumination reference Iref is calculated according to the following formula:*/ +/* Iref = (WDR_RGB_FACTOR * RGBYmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */ +/* So, rgb_factor = 0 means that the standard approach is used. Use of this factor requires that Iref has been selected, see WDR_USE_IREF.*/ +/* Value range of rgb_factor: 0...8 */ +#define MRV_WDR_RGB_FACTOR +#define MRV_WDR_RGB_FACTOR_MASK 0x00000F00U +#define MRV_WDR_RGB_FACTOR_SHIFT 8U +/*! Slice: WDR_DISABLE_TRANSIENT:*/ +/*! 1: disable transient between Y and RGBY_max */ +/* 0: calculate transient between Y and RGBY_max (for noise reduction) *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#define MRV_WDR_DISABLE_TRANSIENT +#define MRV_WDR_DISABLE_TRANSIENT_MASK 0x00000040U +#define MRV_WDR_DISABLE_TRANSIENT_SHIFT 6U +/*! Slice: WDR_USE_RGB7_8:*/ +/*! 1: decrease RGBmax by 7/8 (for noise reduction)*/ +/* 0: do not modify RGBmax *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#define MRV_WDR_USE_RGB7_8 +#define MRV_WDR_USE_RGB7_8_MASK 0x00000020U +#define MRV_WDR_USE_RGB7_8_SHIFT 5U +/*! Slice: WDR_USE_Y9_8:*/ +/*! 1: use R G B and Y*9/8 for maximum value calculation (for noise reduction)*/ +/* 0: only use R G B for maximum value calculation (RGBYmax approach) *Default**/ +/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/ +#define MRV_WDR_USE_Y9_8 +#define MRV_WDR_USE_Y9_8_MASK 0x00000010U +#define MRV_WDR_USE_Y9_8_SHIFT 4U +/*! Slice: WDR_USE_IREF:*/ +/*! 1: use Iref (Illumination reference) instead of Y for ToneMapping and Gain calculation */ +/* 0: use Y for ToneMapping and Gain calculation *Default**/ +/* Iref is calculated according to the following formula:*/ +/* Iref = (WDR_RGB_FACTOR * RGBmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */ +#define MRV_WDR_USE_IREF +#define MRV_WDR_USE_IREF_MASK 0x00000008U +#define MRV_WDR_USE_IREF_SHIFT 3U +/*! Slice: WDR_CR_MAPPING_DISABLE:*/ +/*! 1: disable (bypass) Chrominance Mapping */ +/* 0: enable Chrominance Mapping *Default**/ +/* requires that Luminance/chrominance color space has been selected */ +#define MRV_WDR_CR_MAPPING_DISABLE +#define MRV_WDR_CR_MAPPING_DISABLE_MASK 0x00000004U +#define MRV_WDR_CR_MAPPING_DISABLE_SHIFT 2U +/*! Slice: WDR_COLOR_SPACE_SELECT:*/ +/*! 1: R, G, B color space */ +/* 0: Luminance/Chrominance color space *Default**/ +#define MRV_WDR_COLOR_SPACE_SELECT +#define MRV_WDR_COLOR_SPACE_SELECT_MASK 0x00000002U +#define MRV_WDR_COLOR_SPACE_SELECT_SHIFT 1U +/*! Slice: WDR_ENABLE:*/ +/*! 1: enable WDR */ +/* 0: bypass WDR *Default**/ +#define MRV_WDR_ENABLE +#define MRV_WDR_ENABLE_MASK 0x00000001U +#define MRV_WDR_ENABLE_SHIFT 0U +/*! Register: isp_wdr_tonecurve_1: Tone Curve sample points dYn definition (part 1) (0x00000004)*/ +/*! Slice: WDR_dY8:*/ +/*! Tone curve sample point definition dY8 on the horizontal axis (input)*/ +#define MRV_WDR_DY8 +#define MRV_WDR_DY8_MASK 0x70000000U +#define MRV_WDR_DY8_SHIFT 28U +/*! Slice: WDR_dY7:*/ +/*! Tone curve sample point definition dY7 on the horizontal axis (input)*/ +#define MRV_WDR_DY7 +#define MRV_WDR_DY7_MASK 0x07000000U +#define MRV_WDR_DY7_SHIFT 24U +/*! Slice: WDR_dY6:*/ +/*! Tone curve sample point definition dY6 on the horizontal axis (input)*/ +#define MRV_WDR_DY6 +#define MRV_WDR_DY6_MASK 0x00700000U +#define MRV_WDR_DY6_SHIFT 20U +/*! Slice: WDR_dY5:*/ +/*! Tone curve sample point definition dY5 on the horizontal axis (input)*/ +#define MRV_WDR_DY5 +#define MRV_WDR_DY5_MASK 0x00070000U +#define MRV_WDR_DY5_SHIFT 16U +/*! Slice: WDR_dY4:*/ +/*! Tone curve sample point definition dY4 on the horizontal axis (input)*/ +#define MRV_WDR_DY4 +#define MRV_WDR_DY4_MASK 0x00007000U +#define MRV_WDR_DY4_SHIFT 12U +/*! Slice: WDR_dY3:*/ +/*! Tone curve sample point definition dY3 on the horizontal axis (input)*/ +#define MRV_WDR_DY3 +#define MRV_WDR_DY3_MASK 0x00000700U +#define MRV_WDR_DY3_SHIFT 8U +/*! Slice: WDR_dY2:*/ +/*! Tone curve sample point definition dY2 on the horizontal axis (input)*/ +#define MRV_WDR_DY2 +#define MRV_WDR_DY2_MASK 0x00000070U +#define MRV_WDR_DY2_SHIFT 4U +/*! Slice: WDR_dY1:*/ +/*! Tone curve sample point definition dY1 on the horizontal axis (input)*/ +#define MRV_WDR_DY1 +#define MRV_WDR_DY1_MASK 0x00000007U +#define MRV_WDR_DY1_SHIFT 0U +/*! Register: isp_wdr_tonecurve_2: Tone Curve sample points dYn definition (part 2) (0x00000008)*/ +/*! Slice: WDR_dY16:*/ +/*! Tone curve sample point definition dY16 on the horizontal axis (input)*/ +#define MRV_WDR_DY16 +#define MRV_WDR_DY16_MASK 0x70000000U +#define MRV_WDR_DY16_SHIFT 28U +/*! Slice: WDR_dY15:*/ +/*! Tone curve sample point definition dY15 on the horizontal axis (input)*/ +#define MRV_WDR_DY15 +#define MRV_WDR_DY15_MASK 0x07000000U +#define MRV_WDR_DY15_SHIFT 24U +/*! Slice: WDR_dY14:*/ +/*! Tone curve sample point definition dY14 on the horizontal axis (input)*/ +#define MRV_WDR_DY14 +#define MRV_WDR_DY14_MASK 0x00700000U +#define MRV_WDR_DY14_SHIFT 20U +/*! Slice: WDR_dY13:*/ +/*! Tone curve sample point definition dY13 on the horizontal axis (input)*/ +#define MRV_WDR_DY13 +#define MRV_WDR_DY13_MASK 0x00070000U +#define MRV_WDR_DY13_SHIFT 16U +/*! Slice: WDR_dY12:*/ +/*! Tone curve sample point definition dY12 on the horizontal axis (input)*/ +#define MRV_WDR_DY12 +#define MRV_WDR_DY12_MASK 0x00007000U +#define MRV_WDR_DY12_SHIFT 12U +/*! Slice: WDR_dY11:*/ +/*! Tone curve sample point definition dY11 on the horizontal axis (input)*/ +#define MRV_WDR_DY11 +#define MRV_WDR_DY11_MASK 0x00000700U +#define MRV_WDR_DY11_SHIFT 8U +/*! Slice: WDR_dY10:*/ +/*! Tone curve sample point definition dY10 on the horizontal axis (input)*/ +#define MRV_WDR_DY10 +#define MRV_WDR_DY10_MASK 0x00000070U +#define MRV_WDR_DY10_SHIFT 4U +/*! Slice: WDR_dY9:*/ +/*! Tone curve sample point definition dY9 on the horizontal axis (input)*/ +#define MRV_WDR_DY9 +#define MRV_WDR_DY9_MASK 0x00000007U +#define MRV_WDR_DY9_SHIFT 0U +/*! Register: isp_wdr_tonecurve_3: Tone Curve sample points dYn definition (part 3) (0x0000000c)*/ +/*! Slice: WDR_dY24:*/ +/*! Tone curve sample point definition dY24 on the horizontal axis (input)*/ +#define MRV_WDR_DY24 +#define MRV_WDR_DY24_MASK 0x70000000U +#define MRV_WDR_DY24_SHIFT 28U +/*! Slice: WDR_dY23:*/ +/*! Tone curve sample point definition dY23 on the horizontal axis (input)*/ +#define MRV_WDR_DY23 +#define MRV_WDR_DY23_MASK 0x07000000U +#define MRV_WDR_DY23_SHIFT 24U +/*! Slice: WDR_dY22:*/ +/*! Tone curve sample point definition dY22 on the horizontal axis (input)*/ +#define MRV_WDR_DY22 +#define MRV_WDR_DY22_MASK 0x00700000U +#define MRV_WDR_DY22_SHIFT 20U +/*! Slice: WDR_dY21:*/ +/*! Tone curve sample point definition dY21 on the horizontal axis (input)*/ +#define MRV_WDR_DY21 +#define MRV_WDR_DY21_MASK 0x00070000U +#define MRV_WDR_DY21_SHIFT 16U +/*! Slice: WDR_dY20:*/ +/*! Tone curve sample point definition dY20 on the horizontal axis (input)*/ +#define MRV_WDR_DY20 +#define MRV_WDR_DY20_MASK 0x00007000U +#define MRV_WDR_DY20_SHIFT 12U +/*! Slice: WDR_dY19:*/ +/*! Tone curve sample point definition dY19 on the horizontal axis (input)*/ +#define MRV_WDR_DY19 +#define MRV_WDR_DY19_MASK 0x00000700U +#define MRV_WDR_DY19_SHIFT 8U +/*! Slice: WDR_dY18:*/ +/*! Tone curve sample point definition dY18 on the horizontal axis (input)*/ +#define MRV_WDR_DY18 +#define MRV_WDR_DY18_MASK 0x00000070U +#define MRV_WDR_DY18_SHIFT 4U +/*! Slice: WDR_dY17:*/ +/*! Tone curve sample point definition dY17 on the horizontal axis (input)*/ +#define MRV_WDR_DY17 +#define MRV_WDR_DY17_MASK 0x00000007U +#define MRV_WDR_DY17_SHIFT 0U +/*! Register: isp_wdr_tonecurve_4: Tone Curve sample points dYn definition (part 4) (0x00000010)*/ +/*! Slice: WDR_dY32:*/ +/*! Tone curve sample point definition dY32 on the horizontal axis (input)*/ +#define MRV_WDR_DY32 +#define MRV_WDR_DY32_MASK 0x70000000U +#define MRV_WDR_DY32_SHIFT 28U +/*! Slice: WDR_dY31:*/ +/*! Tone curve sample point definition dY31 on the horizontal axis (input)*/ +#define MRV_WDR_DY31 +#define MRV_WDR_DY31_MASK 0x07000000U +#define MRV_WDR_DY31_SHIFT 24U +/*! Slice: WDR_dY30:*/ +/*! Tone curve sample point definition dY30 on the horizontal axis (input)*/ +#define MRV_WDR_DY30 +#define MRV_WDR_DY30_MASK 0x00700000U +#define MRV_WDR_DY30_SHIFT 20U +/*! Slice: WDR_dY29:*/ +/*! Tone curve sample point definition dY29 on the horizontal axis (input)*/ +#define MRV_WDR_DY29 +#define MRV_WDR_DY29_MASK 0x00070000U +#define MRV_WDR_DY29_SHIFT 16U +/*! Slice: WDR_dY28:*/ +/*! Tone curve sample point definition dY28 on the horizontal axis (input)*/ +#define MRV_WDR_DY28 +#define MRV_WDR_DY28_MASK 0x00007000U +#define MRV_WDR_DY28_SHIFT 12U +/*! Slice: WDR_dY27:*/ +/*! Tone curve sample point definition dY27 on the horizontal axis (input)*/ +#define MRV_WDR_DY27 +#define MRV_WDR_DY27_MASK 0x00000700U +#define MRV_WDR_DY27_SHIFT 8U +/*! Slice: WDR_dY26:*/ +/*! Tone curve sample point definition dY26 on the horizontal axis (input)*/ +#define MRV_WDR_DY26 +#define MRV_WDR_DY26_MASK 0x00000070U +#define MRV_WDR_DY26_SHIFT 4U +/*! Slice: WDR_dY25:*/ +/*! Tone curve sample point definition dY25 on the horizontal axis (input)*/ +#define MRV_WDR_DY25 +#define MRV_WDR_DY25_MASK 0x00000007U +#define MRV_WDR_DY25_SHIFT 0U +/*! Register array: isp_wdr_tonecurve_ym: Tonemapping curve coefficient Ym_ (0x0028 + n*0x4 (n=0..32))*/ +/*! Slice: tonecurve_ym_n:*/ +/* Tone curve value definition y-axis (output) of WDR unit */ +#define MRV_WDR_TONECURVE_YM_N +#define MRV_WDR_TONECURVE_YM_N_MASK 0x00001FFFU +#define MRV_WDR_TONECURVE_YM_N_SHIFT 0U +/*! Register: isp_wdr_offset: Offset values for RGB path (0x00000098)*/ +/*! Slice: LUM_OFFSET:*/ +/*! Luminance Offset value (a) for RGB operation mode */ +/* unsigned 12 bit value */ +#define MRV_WDR_LUM_OFFSET +#define MRV_WDR_LUM_OFFSET_MASK 0x0FFF0000U +#define MRV_WDR_LUM_OFFSET_SHIFT 16U +/*! Slice: RGB_OFFSET:*/ +/*! RGB Offset value (b) for RGB operation mode */ +/* unsigned 12 bit value */ +#define MRV_WDR_RGB_OFFSET +#define MRV_WDR_RGB_OFFSET_MASK 0x00000FFFU +#define MRV_WDR_RGB_OFFSET_SHIFT 0U +/*! Register: isp_wdr_deltamin: DeltaMin Threshold and Strength factor (0x0000009c)*/ +/*! Slice: DMIN_STRENGTH:*/ +/*! strength factor for DMIN */ +/* unsigned 5 bit value, range 0x00...0x10 */ +#define MRV_WDR_DMIN_STRENGTH +#define MRV_WDR_DMIN_STRENGTH_MASK 0x001F0000U +#define MRV_WDR_DMIN_STRENGTH_SHIFT 16U +/*! Slice: DMIN_THRESH:*/ +/*! Lower threshold for deltaMin value */ +/* unsigned 12 bit value */ +#define MRV_WDR_DMIN_THRESH +#define MRV_WDR_DMIN_THRESH_MASK 0x00000FFFU +#define MRV_WDR_DMIN_THRESH_SHIFT 0U +/*! Register: isp_wdr_tonecurve_1_shd: Tone Curve sample points dYn definition shadow register (part 1) (0x000000a0)*/ +/*! Slice: WDR_dY8:*/ +/*! Tone curve sample point definition dY8 on the horizontal axis (input)*/ +#define MRV_WDR_DY8 +#define MRV_WDR_DY8_MASK 0x70000000U +#define MRV_WDR_DY8_SHIFT 28U +/*! Slice: WDR_dY7:*/ +/*! Tone curve sample point definition dY7 on the horizontal axis (input)*/ +#define MRV_WDR_DY7 +#define MRV_WDR_DY7_MASK 0x07000000U +#define MRV_WDR_DY7_SHIFT 24U +/*! Slice: WDR_dY6:*/ +/*! Tone curve sample point definition dY6 on the horizontal axis (input)*/ +#define MRV_WDR_DY6 +#define MRV_WDR_DY6_MASK 0x00700000U +#define MRV_WDR_DY6_SHIFT 20U +/*! Slice: WDR_dY5:*/ +/*! Tone curve sample point definition dY5 on the horizontal axis (input)*/ +#define MRV_WDR_DY5 +#define MRV_WDR_DY5_MASK 0x00070000U +#define MRV_WDR_DY5_SHIFT 16U +/*! Slice: WDR_dY4:*/ +/*! Tone curve sample point definition dY4 on the horizontal axis (input)*/ +#define MRV_WDR_DY4 +#define MRV_WDR_DY4_MASK 0x00007000U +#define MRV_WDR_DY4_SHIFT 12U +/*! Slice: WDR_dY3:*/ +/*! Tone curve sample point definition dY3 on the horizontal axis (input)*/ +#define MRV_WDR_DY3 +#define MRV_WDR_DY3_MASK 0x00000700U +#define MRV_WDR_DY3_SHIFT 8U +/*! Slice: WDR_dY2:*/ +/*! Tone curve sample point definition dY2 on the horizontal axis (input)*/ +#define MRV_WDR_DY2 +#define MRV_WDR_DY2_MASK 0x00000070U +#define MRV_WDR_DY2_SHIFT 4U +/*! Slice: WDR_dY1:*/ +/*! Tone curve sample point definition dY1 on the horizontal axis (input)*/ +#define MRV_WDR_DY1 +#define MRV_WDR_DY1_MASK 0x00000007U +#define MRV_WDR_DY1_SHIFT 0U +/*! Register: isp_wdr_tonecurve_2_shd: Tone Curve sample points dYn definition shadow register (part 2) (0x000000a4)*/ +/*! Slice: WDR_dY16:*/ +/*! Tone curve sample point definition dY16 on the horizontal axis (input)*/ +#define MRV_WDR_DY16 +#define MRV_WDR_DY16_MASK 0x70000000U +#define MRV_WDR_DY16_SHIFT 28U +/*! Slice: WDR_dY15:*/ +/*! Tone curve sample point definition dY15 on the horizontal axis (input)*/ +#define MRV_WDR_DY15 +#define MRV_WDR_DY15_MASK 0x07000000U +#define MRV_WDR_DY15_SHIFT 24U +/*! Slice: WDR_dY14:*/ +/*! Tone curve sample point definition dY14 on the horizontal axis (input)*/ +#define MRV_WDR_DY14 +#define MRV_WDR_DY14_MASK 0x00700000U +#define MRV_WDR_DY14_SHIFT 20U +/*! Slice: WDR_dY13:*/ +/*! Tone curve sample point definition dY13 on the horizontal axis (input)*/ +#define MRV_WDR_DY13 +#define MRV_WDR_DY13_MASK 0x00070000U +#define MRV_WDR_DY13_SHIFT 16U +/*! Slice: WDR_dY12:*/ +/*! Tone curve sample point definition dY12 on the horizontal axis (input)*/ +#define MRV_WDR_DY12 +#define MRV_WDR_DY12_MASK 0x00007000U +#define MRV_WDR_DY12_SHIFT 12U +/*! Slice: WDR_dY11:*/ +/*! Tone curve sample point definition dY11 on the horizontal axis (input)*/ +#define MRV_WDR_DY11 +#define MRV_WDR_DY11_MASK 0x00000700U +#define MRV_WDR_DY11_SHIFT 8U +/*! Slice: WDR_dY10:*/ +/*! Tone curve sample point definition dY10 on the horizontal axis (input)*/ +#define MRV_WDR_DY10 +#define MRV_WDR_DY10_MASK 0x00000070U +#define MRV_WDR_DY10_SHIFT 4U +/*! Slice: WDR_dY9:*/ +/*! Tone curve sample point definition dY9 on the horizontal axis (input)*/ +#define MRV_WDR_DY9 +#define MRV_WDR_DY9_MASK 0x00000007U +#define MRV_WDR_DY9_SHIFT 0U +/*! Register: isp_wdr_tonecurve_3_shd: Tone Curve sample points dYn definition shadow register (part 3) (0x000000a8)*/ +/*! Slice: WDR_dY24:*/ +/*! Tone curve sample point definition dY24 on the horizontal axis (input)*/ +#define MRV_WDR_DY24 +#define MRV_WDR_DY24_MASK 0x70000000U +#define MRV_WDR_DY24_SHIFT 28U +/*! Slice: WDR_dY23:*/ +/*! Tone curve sample point definition dY23 on the horizontal axis (input)*/ +#define MRV_WDR_DY23 +#define MRV_WDR_DY23_MASK 0x07000000U +#define MRV_WDR_DY23_SHIFT 24U +/*! Slice: WDR_dY22:*/ +/*! Tone curve sample point definition dY22 on the horizontal axis (input)*/ +#define MRV_WDR_DY22 +#define MRV_WDR_DY22_MASK 0x00700000U +#define MRV_WDR_DY22_SHIFT 20U +/*! Slice: WDR_dY21:*/ +/*! Tone curve sample point definition dY21 on the horizontal axis (input)*/ +#define MRV_WDR_DY21 +#define MRV_WDR_DY21_MASK 0x00070000U +#define MRV_WDR_DY21_SHIFT 16U +/*! Slice: WDR_dY20:*/ +/*! Tone curve sample point definition dY20 on the horizontal axis (input)*/ +#define MRV_WDR_DY20 +#define MRV_WDR_DY20_MASK 0x00007000U +#define MRV_WDR_DY20_SHIFT 12U +/*! Slice: WDR_dY19:*/ +/*! Tone curve sample point definition dY19 on the horizontal axis (input)*/ +#define MRV_WDR_DY19 +#define MRV_WDR_DY19_MASK 0x00000700U +#define MRV_WDR_DY19_SHIFT 8U +/*! Slice: WDR_dY18:*/ +/*! Tone curve sample point definition dY18 on the horizontal axis (input)*/ +#define MRV_WDR_DY18 +#define MRV_WDR_DY18_MASK 0x00000070U +#define MRV_WDR_DY18_SHIFT 4U +/*! Slice: WDR_dY17:*/ +/*! Tone curve sample point definition dY17 on the horizontal axis (input)*/ +#define MRV_WDR_DY17 +#define MRV_WDR_DY17_MASK 0x00000007U +#define MRV_WDR_DY17_SHIFT 0U +/*! Register: isp_wdr_tonecurve_4_shd: Tone Curve sample points dYn definition shadow register(part 4) (0x000000ac)*/ +/*! Slice: WDR_dY32:*/ +/*! Tone curve sample point definition dY32 on the horizontal axis (input)*/ +#define MRV_WDR_DY32 +#define MRV_WDR_DY32_MASK 0x70000000U +#define MRV_WDR_DY32_SHIFT 28U +/*! Slice: WDR_dY31:*/ +/*! Tone curve sample point definition dY31 on the horizontal axis (input)*/ +#define MRV_WDR_DY31 +#define MRV_WDR_DY31_MASK 0x07000000U +#define MRV_WDR_DY31_SHIFT 24U +/*! Slice: WDR_dY30:*/ +/*! Tone curve sample point definition dY30 on the horizontal axis (input)*/ +#define MRV_WDR_DY30 +#define MRV_WDR_DY30_MASK 0x00700000U +#define MRV_WDR_DY30_SHIFT 20U +/*! Slice: WDR_dY29:*/ +/*! Tone curve sample point definition dY29 on the horizontal axis (input)*/ +#define MRV_WDR_DY29 +#define MRV_WDR_DY29_MASK 0x00070000U +#define MRV_WDR_DY29_SHIFT 16U +/*! Slice: WDR_dY28:*/ +/*! Tone curve sample point definition dY28 on the horizontal axis (input)*/ +#define MRV_WDR_DY28 +#define MRV_WDR_DY28_MASK 0x00007000U +#define MRV_WDR_DY28_SHIFT 12U +/*! Slice: WDR_dY27:*/ +/*! Tone curve sample point definition dY27 on the horizontal axis (input)*/ +#define MRV_WDR_DY27 +#define MRV_WDR_DY27_MASK 0x00000700U +#define MRV_WDR_DY27_SHIFT 8U +/*! Slice: WDR_dY26:*/ +/*! Tone curve sample point definition dY26 on the horizontal axis (input)*/ +#define MRV_WDR_DY26 +#define MRV_WDR_DY26_MASK 0x00000070U +#define MRV_WDR_DY26_SHIFT 4U +/*! Slice: WDR_dY25:*/ +/*! Tone curve sample point definition dY25 on the horizontal axis (input)*/ +#define MRV_WDR_DY25 +#define MRV_WDR_DY25_MASK 0x00000007U +#define MRV_WDR_DY25_SHIFT 0U +/*! Register array: isp_wdr_tonecurve_ym_shd: Tonemapping curve coefficient shadow register (0x0160 + n*0x4 (n=0..32))*/ +/*! Slice: tonecurve_ym_n_shd:*/ +/* Tone curve value definition y-axis (output) of WDR unit */ +/* shadow register.*/ +#define MRV_WDR_TONECURVE_YM_N_SHD +#define MRV_WDR_TONECURVE_YM_N_SHD_MASK 0x00001FFFU +#define MRV_WDR_TONECURVE_YM_N_SHD_SHIFT 0U +/*! Register: awb_meas_mode: AWB Measure Mode (0x00000000)*/ +/*! Slice: AWB_union_e5_and_e8:*/ +/*! unite ellipse 5 with ellipse 8. Accu and count for ellipse 8.*/ +#define ISP_AWB_UNION_E5_AND_E8 +#define ISP_AWB_UNION_E5_AND_E8_MASK 0x00000200U +#define ISP_AWB_UNION_E5_AND_E8_SHIFT 9U +/*! Slice: AWB_union_e5_and_e7:*/ +/*! unite ellipse 5 with ellipse 7. Accu and count for ellipse 7.*/ +#define ISP_AWB_UNION_E5_AND_E7 +#define ISP_AWB_UNION_E5_AND_E7_MASK 0x00000100U +#define ISP_AWB_UNION_E5_AND_E7_SHIFT 8U +/*! Slice: AWB_union_e5_and_e6:*/ +/*! unite ellipse 5 with ellipse 6. Accu and count for ellipse 6.*/ +#define ISP_AWB_UNION_E5_AND_E6 +#define ISP_AWB_UNION_E5_AND_E6_MASK 0x00000080U +#define ISP_AWB_UNION_E5_AND_E6_SHIFT 7U +/*! Slice: AWB_union_e1_and_e4:*/ +/*! unite ellipse 1 with ellipse 4. Accu and count for ellipse 4.*/ +#define ISP_AWB_UNION_E1_AND_E4 +#define ISP_AWB_UNION_E1_AND_E4_MASK 0x00000040U +#define ISP_AWB_UNION_E1_AND_E4_SHIFT 6U +/*! Slice: AWB_union_e1_and_e3:*/ +/*! unite ellipse 1 with ellipse 3. Accu and count for ellipse 3.*/ +#define ISP_AWB_UNION_E1_AND_E3 +#define ISP_AWB_UNION_E1_AND_E3_MASK 0x00000020U +#define ISP_AWB_UNION_E1_AND_E3_SHIFT 5U +/*! Slice: AWB_union_e1_and_e2:*/ +/*! unite ellipse 1 with ellipse 2. Accu and count for ellipse 2.*/ +#define ISP_AWB_UNION_E1_AND_E2 +#define ISP_AWB_UNION_E1_AND_E2_MASK 0x00000010U +#define ISP_AWB_UNION_E1_AND_E2_SHIFT 4U +/*! Slice: AWB_meas_chrom_switch:*/ +/*! Accumulates Q1 and Q2 chromaticies instead of R, G, B color signals. Results are written on AWB_ACCU registers as well.*/ +#define ISP_AWB_MEAS_CHROM_SWITCH +#define ISP_AWB_MEAS_CHROM_SWITCH_MASK 0x00000008U +#define ISP_AWB_MEAS_CHROM_SWITCH_SHIFT 3U +/*! Slice: AWB_meas_irq_enable:*/ +/*! AWB measure done IRQ enable.*/ +#define ISP_AWB_MEAS_IRQ_ENABLE +#define ISP_AWB_MEAS_IRQ_ENABLE_MASK 0x00000004U +#define ISP_AWB_MEAS_IRQ_ENABLE_SHIFT 2U +/*! Slice: AWB_pre_filt_en:*/ +/*! median pre filter enable.*/ +#define ISP_AWB_PRE_FILT_EN +#define ISP_AWB_PRE_FILT_EN_MASK 0x00000002U +#define ISP_AWB_PRE_FILT_EN_SHIFT 1U +/*! Slice: AWB_meas_en:*/ +/*! enable measure.*/ +#define ISP_AWB_MEAS_EN +#define ISP_AWB_MEAS_EN_MASK 0x00000001U +#define ISP_AWB_MEAS_EN_SHIFT 0U +/*! Register: awb_meas_h_offs: AWB window horizontal offset (0x00000004)*/ +/*! Slice: AWB_h_offset:*/ +/*! Horizontal offset in pixels.*/ +#define ISP_AWB_H_OFFSET +#define ISP_AWB_H_OFFSET_MASK 0x00001FFFU +#define ISP_AWB_H_OFFSET_SHIFT 0U +/*! Register: awb_meas_v_offs: AWB window vertical offset (0x00000008)*/ +/*! Slice: AWB_v_offset:*/ +/*! Vertical offset in pixels.*/ +#define ISP_AWB_V_OFFSET +#define ISP_AWB_V_OFFSET_MASK 0x00001FFFU +#define ISP_AWB_V_OFFSET_SHIFT 0U +/*! Register: awb_meas_h_size: Horizontal window size (0x0000000c)*/ +/*! Slice: AWB_h_size:*/ +/*! Horizontal size in pixels.*/ +#define ISP_AWB_H_SIZE +#define ISP_AWB_H_SIZE_MASK 0x00003FFFU +#define ISP_AWB_H_SIZE_SHIFT 0U +/*! Register: awb_meas_v_size: Vertical window size (0x00000010)*/ +/*! Slice: AWB_v_size:*/ +/*! Vertical size.*/ +#define ISP_AWB_V_SIZE +#define ISP_AWB_V_SIZE_MASK 0x00003FFFU +#define ISP_AWB_V_SIZE_SHIFT 0U +/*! Register: awb_meas_r_min_max: Min Max Compare Red (0x00000014)*/ +/*! Slice: r_max:*/ +/*! max red value */ +#define ISP_AWB_R_MAX +#define ISP_AWB_R_MAX_MASK 0x0000FF00U +#define ISP_AWB_R_MAX_SHIFT 8U +/*! Slice: r_min:*/ +/*! min red value */ +#define ISP_AWB_R_MIN +#define ISP_AWB_R_MIN_MASK 0x000000FFU +#define ISP_AWB_R_MIN_SHIFT 0U +/*! Register: awb_meas_g_min_max: Min Max Compare Green (0x00000018)*/ +/*! Slice: g_max:*/ +/*! max green value */ +#define ISP_AWB_G_MAX +#define ISP_AWB_G_MAX_MASK 0x0000FF00U +#define ISP_AWB_G_MAX_SHIFT 8U +/*! Slice: g_min:*/ +/*! min green value */ +#define ISP_AWB_G_MIN +#define ISP_AWB_G_MIN_MASK 0x000000FFU +#define ISP_AWB_G_MIN_SHIFT 0U +/*! Register: awb_meas_b_min_max: Min Max Compare Blue (0x0000001c)*/ +/*! Slice: b_max:*/ +/*! max blue value */ +#define ISP_AWB_B_MAX +#define ISP_AWB_B_MAX_MASK 0x0000FF00U +#define ISP_AWB_B_MAX_SHIFT 8U +/*! Slice: b_min:*/ +/*! min blue value */ +#define ISP_AWB_B_MIN +#define ISP_AWB_B_MIN_MASK 0x000000FFU +#define ISP_AWB_B_MIN_SHIFT 0U +/*! Register: awb_meas_divider_min: Min Compare Divider (0x00000020)*/ +/*! Slice: div_min:*/ +/*! min divider value unsigned integer with 10 fractional Bits range 0 to 0.999 */ +#define ISP_AWB_DIV_MIN +#define ISP_AWB_DIV_MIN_MASK 0x000003FFU +#define ISP_AWB_DIV_MIN_SHIFT 0U +/*! Register: awb_meas_csc_coeff_0: Color conversion coefficient 0 (0x00000024)*/ +/*! Slice: cc_coeff_0:*/ +/*! coefficient 0 for color space conversion */ +#define ISP_AWB_CC_COEFF_0 +#define ISP_AWB_CC_COEFF_0_MASK 0x000007FFU +#define ISP_AWB_CC_COEFF_0_SHIFT 0U +/*! Register: awb_meas_ellip1_cen_x: Ellipse 1 Center X (0x00000048)*/ +/*! Slice: ellip1_cen_x:*/ +/*! Ellipse 1 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#define ISP_AWB_ELLIP1_CEN_X +#define ISP_AWB_ELLIP1_CEN_X_MASK 0x000003FFU +#define ISP_AWB_ELLIP1_CEN_X_SHIFT 0U +/*! Register: awb_meas_ellip1_cen_y: Ellipse 1 Center Y (0x0000004c)*/ +/*! Slice: ellip1_cen_y:*/ +/*! Ellipse 1 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */ +#define ISP_AWB_ELLIP1_CEN_Y +#define ISP_AWB_ELLIP1_CEN_Y_MASK 0x000003FFU +#define ISP_AWB_ELLIP1_CEN_Y_SHIFT 0U +/*! Register: awb_meas_ellip1_a1: Ellipse 1 coefficient a1 (0x00000088)*/ +/*! Slice: ellip1_a1:*/ +/*! Ellipse 1 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#define ISP_AWB_ELLIP1_A1 +#define ISP_AWB_ELLIP1_A1_MASK 0x00000FFFU +#define ISP_AWB_ELLIP1_A1_SHIFT 0U +/*! Register: awb_meas_ellip1_a2: Ellipse 1 coefficient a2 (0x0000008c)*/ +/*! Slice: ellip1_a2:*/ +/*! Ellipse 1 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#define ISP_AWB_ELLIP1_A2 +#define ISP_AWB_ELLIP1_A2_MASK 0x000001FFU +#define ISP_AWB_ELLIP1_A2_SHIFT 0U +/*! Register: awb_meas_ellip1_a3: Ellipse 1 coefficient a3 (0x00000090)*/ +/*! Slice: ellip1_a3:*/ +/*! Ellipse 1 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */ +#define ISP_AWB_ELLIP1_A3 +#define ISP_AWB_ELLIP1_A3_MASK 0x00000FFFU +#define ISP_AWB_ELLIP1_A3_SHIFT 0U +/*! Register: awb_meas_ellip1_a4: Ellipse 1 coefficient a4 (0x00000094)*/ +/*! Slice: ellip1_a4:*/ +/*! Ellipse 1 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */ +#define ISP_AWB_ELLIP1_A4 +#define ISP_AWB_ELLIP1_A4_MASK 0x000001FFU +#define ISP_AWB_ELLIP1_A4_SHIFT 0U +/*! Register: awb_meas_ellip1_rmax: Ellipse 1 r_max (0x00000108)*/ +/*! Slice: ellip1_rmax:*/ +/*! Ellipse 1 max radius square compare value */ +#define ISP_AWB_ELLIP1_RMAX +#define ISP_AWB_ELLIP1_RMAX_MASK 0x00FFFFFFU +#define ISP_AWB_ELLIP1_RMAX_SHIFT 0U +/*! Register: awb_meas_counter_1: AWB Counter 1 (0x00000128)*/ +/*! Slice: count_1:*/ +/*! counted Pixels of Ellipse 1 */ +#define ISP_AWB_COUNT_1 +#define ISP_AWB_COUNT_1_MASK 0x00FFFFFFU +#define ISP_AWB_COUNT_1_SHIFT 0U +/*! Register array: awb_meas_accu: AWB Accu Read (0x290 + n*0x4 (n=0..23))*/ +/*! Slice: read_accu:*/ +/* measured sum[34:3] of RGB values.*/ +#define ISP_AWB_READ_ACCU +#define ISP_AWB_READ_ACCU_MASK 0xFFFFFFFFU +#define ISP_AWB_READ_ACCU_SHIFT 0U +/*! Register: isp64_hist_ctrl: Histogram control (0x00000000)*/ +/*! Slice: hist_update_enable:*/ +/*! 0: automatic register update at end of measuement ot frame denied */ +/* 1: automatic register update at end of measuement ot frame enabled.*/ +#define MRV_HIST_UPDATE_ENABLE +#define MRV_HIST_UPDATE_ENABLE_MASK 0x00000001U +#define MRV_HIST_UPDATE_ENABLE_SHIFT 0U +/*! Register: isp64_hist_prop: Histogram properties (0x00000004)*/ +/*! Slice: channel_select:*/ +/*! select 1 out of max. 8 input channels */ +/* 7: channel 7 */ +/* 6: channel 6 */ +/* 5: channel 5 */ +/* 4: channel 4 */ +/* 3: channel 3 */ +/* 2: channel 2 */ +/* 1: channel 1 */ +/* 0: channel 0 */ +/* The channels might be RGB or Bayer channels. Each channel provides 3 subchannels for tranfer the RGB component data. However if the channel operates in bayer mode only subchannel 0 is used transferring the interleaved bayer pattern data. Check with top level specification to discover the channel type.*/ +#define MRV_HIST_CHANNEL_SELECT +#define MRV_HIST_CHANNEL_SELECT_MASK 0x00000038U +#define MRV_HIST_CHANNEL_SELECT_SHIFT 3U +/*! Slice: hist_mode:*/ +/*! histogram mode (RGB/Bayer)*/ +/* 7, 6: reserved */ +/* 5: bayer Gb histogram */ +/* 4: bayer B histogram */ +/* 3: bayer Gr histogram */ +/* 2: bayer R histogram */ +/* 1: Y/R/G/B histogram controlled via coefficients coeff_r/g/b */ +/* 0: disable, no measurements */ +/* With histogram mode 1 all three subchannels are used. Modes 2...5 use only th subchannel 0 which transfers the bayer pattern data. Check with top level specification to discover the channel type.*/ +#define MRV_HIST_MODE +#define MRV_HIST_MODE_MASK 0x00000007U +#define MRV_HIST_MODE_SHIFT 0U +/*! Register: isp64_hist_subsampling: Subsampling properties (0x00000008)*/ +/*! Slice: v_stepsize:*/ +/*! histogram veritcal predivider, process every (stepsize)th line, all other lines are skipped */ +/* RGB mode:*/ +/* 0: not allowed */ +/* 1: process every input line */ +/* 2: process every second line */ +/* 3: process every third input line */ +/* 4: process every fourth input line */ +/* ...*/ +/* 7FH: process every 127th line */ +/* Bayer mode:*/ +/* 0: not allowed */ +/* 1: process every second input line */ +/* 2: process every fourth line */ +/* 3: process every sixth input line */ +/* 4: process every eighth input line */ +/* ...*/ +/* 7FH: process every 254th line */ +/* In bayer mode vertical subsampling will start at the 1st input line which contain the bayer component selected in ISP64_HIST_PROP::hist_mode.*/ +#define MRV_HIST_V_STEPSIZE +#define MRV_HIST_V_STEPSIZE_MASK 0x7F000000U +#define MRV_HIST_V_STEPSIZE_SHIFT 24U +/*! Slice: h_step_inc:*/ +/*! horizontal subsampling step counter increment.*/ +/* In RGB mode the subsampling counter cnt is incremented by h_step_inc with every input pixel (cnt %= cnt + h_step_inc). A valid subsampling position is reached when cnt would result in a value %= 2^16. In this case the new counter value is cnt = cnt + h_step_inc - 2^16. For example if every incoming pixel shall be selected configure h_step_inc = 2^16.*/ +/* In Bayer mode the behaviour is similar but for the fact that cnt is only incremented for pixels which belong to the bayer component selected in ISP64_HIST_PROP::hist_mode.*/ +#define MRV_HIST_H_STEP_INC +#define MRV_HIST_H_STEP_INC_MASK 0x0001FFFFU +#define MRV_HIST_H_STEP_INC_SHIFT 0U +/*! Register: isp64_hist_coeff_r: Color conversion coefficient for red (0x0000000c)*/ +/*! Slice: coeff_r:*/ +/*! coefficient for red for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/ +#define MRV_HIST_COEFF_R +#define MRV_HIST_COEFF_R_MASK 0x000000FFU +#define MRV_HIST_COEFF_R_SHIFT 0U +/*! Register: isp64_hist_coeff_g: Color conversion coefficient for green (0x00000010)*/ +/*! Slice: coeff_g:*/ +/*! coefficient for green for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/ +#define MRV_HIST_COEFF_G +#define MRV_HIST_COEFF_G_MASK 0x000000FFU +#define MRV_HIST_COEFF_G_SHIFT 0U +/*! Register: isp64_hist_coeff_b: Color conversion coefficient for blue (0x00000014)*/ +/*! Slice: coeff_b:*/ +/*! coefficient for blue for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/ +#define MRV_HIST_COEFF_B +#define MRV_HIST_COEFF_B_MASK 0x000000FFU +#define MRV_HIST_COEFF_B_SHIFT 0U +/*! Register: isp64_hist_h_offs: Histogram window horizontal offset for first window of 25 sub-windows (0x00000018)*/ +/*! Slice: hist_h_offset:*/ +/*! Horizontal offset of first window in pixels.*/ +#define MRV_HIST_H_OFFSET +#define MRV_HIST_H_OFFSET_MASK 0x00001FFFU +#define MRV_HIST_H_OFFSET_SHIFT 0U +/*! Register: isp64_hist_v_offs: Histogram window vertical offset for first window of 25 sub-windows (0x0000001c)*/ +/*! Slice: hist_v_offset:*/ +/*! Vertical offset of first window in pixels.*/ +#define MRV_HIST_V_OFFSET +#define MRV_HIST_V_OFFSET_MASK 0x00001FFFU +#define MRV_HIST_V_OFFSET_SHIFT 0U +/*! Register: isp64_hist_h_size: Horizontal (sub-)window size (0x00000020)*/ +/*! Slice: hist_h_size:*/ +/*! Horizontal size in pixels of one sub-window.*/ +#define MRV_HIST_H_SIZE +#define MRV_HIST_H_SIZE_MASK 0x000007FFU +#define MRV_HIST_H_SIZE_SHIFT 0U +/*! Register: isp64_hist_v_size: Vertical (sub-)window size (0x00000024)*/ +/*! Slice: hist_v_size:*/ +/*! Vertical size in lines of one sub-window.*/ +#define MRV_HIST_V_SIZE +#define MRV_HIST_V_SIZE_MASK 0x000007FFU +#define MRV_HIST_V_SIZE_SHIFT 0U +/*! Register: isp64_hist_sample_range: Weighting factor for sub-windows (0x00000028)*/ +/*! Slice: sample_shift:*/ +/*! sample (left) shift will be executed after offset subtraction and prior to histogram evaluation */ +#define MRV_HIST_SAMPLE_SHIFT +#define MRV_HIST_SAMPLE_SHIFT_MASK 0x00070000U +#define MRV_HIST_SAMPLE_SHIFT_SHIFT 16U +/*! Slice: sample_offset:*/ +/*! sample offset will be subtracted from input sample prior to shift and histogram evaluation */ +#define MRV_HIST_SAMPLE_OFFSET +#define MRV_HIST_SAMPLE_OFFSET_MASK 0x00000FFFU +#define MRV_HIST_SAMPLE_OFFSET_SHIFT 0U +/*! Register: isp64_hist_weight_00to30: Weighting factor for sub-windows (0x0000002c)*/ +/*! Slice: hist_weight_30:*/ +/*! weighting factor for sub-window 30 */ +#define MRV_HIST_WEIGHT_30 +#define MRV_HIST_WEIGHT_30_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_30_SHIFT 24U +/*! Slice: hist_weight_20:*/ +/*! weighting factor for sub-window 20 */ +#define MRV_HIST_WEIGHT_20 +#define MRV_HIST_WEIGHT_20_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_20_SHIFT 16U +/*! Slice: hist_weight_10:*/ +/*! weighting factor for sub-window 10 */ +#define MRV_HIST_WEIGHT_10 +#define MRV_HIST_WEIGHT_10_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_10_SHIFT 8U +/*! Slice: hist_weight_00:*/ +/*! weighting factor for sub-window 00 */ +#define MRV_HIST_WEIGHT_00 +#define MRV_HIST_WEIGHT_00_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_00_SHIFT 0U +/*! Register: isp64_hist_weight_40to21: Weighting factor for sub-windows (0x00000030)*/ +/*! Slice: hist_weight_21:*/ +/*! weighting factor for sub-window 21 */ +#define MRV_HIST_WEIGHT_21 +#define MRV_HIST_WEIGHT_21_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_21_SHIFT 24U +/*! Slice: hist_weight_11:*/ +/*! weighting factor for sub-window 11 */ +#define MRV_HIST_WEIGHT_11 +#define MRV_HIST_WEIGHT_11_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_11_SHIFT 16U +/*! Slice: hist_weight_01:*/ +/*! weighting factor for sub-window 01 */ +#define MRV_HIST_WEIGHT_01 +#define MRV_HIST_WEIGHT_01_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_01_SHIFT 8U +/*! Slice: hist_weight_40:*/ +/*! weighting factor for sub-window 40 */ +#define MRV_HIST_WEIGHT_40 +#define MRV_HIST_WEIGHT_40_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_40_SHIFT 0U +/*! Register: isp64_hist_weight_31to12: Weighting factor for sub-windows (0x00000034)*/ +/*! Slice: hist_weight_12:*/ +/*! weighting factor for sub-window 12 */ +#define MRV_HIST_WEIGHT_12 +#define MRV_HIST_WEIGHT_12_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_12_SHIFT 24U +/*! Slice: hist_weight_02:*/ +/*! weighting factor for sub-window 02 */ +#define MRV_HIST_WEIGHT_02 +#define MRV_HIST_WEIGHT_02_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_02_SHIFT 16U +/*! Slice: hist_weight_41:*/ +/*! weighting factor for sub-window 41 */ +#define MRV_HIST_WEIGHT_41 +#define MRV_HIST_WEIGHT_41_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_41_SHIFT 8U +/*! Slice: hist_weight_31:*/ +/*! weighting factor for sub-window 31 */ +#define MRV_HIST_WEIGHT_31 +#define MRV_HIST_WEIGHT_31_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_31_SHIFT 0U +/*! Register: isp64_hist_weight_22to03: Weighting factor for sub-windows (0x00000038)*/ +/*! Slice: hist_weight_03:*/ +/*! weighting factor for sub-window 03 */ +#define MRV_HIST_WEIGHT_03 +#define MRV_HIST_WEIGHT_03_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_03_SHIFT 24U +/*! Slice: hist_weight_42:*/ +/*! weighting factor for sub-window 42 */ +#define MRV_HIST_WEIGHT_42 +#define MRV_HIST_WEIGHT_42_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_42_SHIFT 16U +/*! Slice: hist_weight_32:*/ +/*! weighting factor for sub-window 32 */ +#define MRV_HIST_WEIGHT_32 +#define MRV_HIST_WEIGHT_32_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_32_SHIFT 8U +/*! Slice: hist_weight_22:*/ +/*! weighting factor for sub-window 22 */ +#define MRV_HIST_WEIGHT_22 +#define MRV_HIST_WEIGHT_22_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_22_SHIFT 0U +/*! Register: isp64_hist_weight_13to43: Weighting factor for sub-windows (0x0000003c)*/ +/*! Slice: hist_weight_43:*/ +/*! weighting factor for sub-window 43 */ +#define MRV_HIST_WEIGHT_43 +#define MRV_HIST_WEIGHT_43_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_43_SHIFT 24U +/*! Slice: hist_weight_33:*/ +/*! weighting factor for sub-window 33 */ +#define MRV_HIST_WEIGHT_33 +#define MRV_HIST_WEIGHT_33_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_33_SHIFT 16U +/*! Slice: hist_weight_23:*/ +/*! weighting factor for sub-window 23 */ +#define MRV_HIST_WEIGHT_23 +#define MRV_HIST_WEIGHT_23_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_23_SHIFT 8U +/*! Slice: hist_weight_13:*/ +/*! weighting factor for sub-window 13 */ +#define MRV_HIST_WEIGHT_13 +#define MRV_HIST_WEIGHT_13_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_13_SHIFT 0U +/*! Register: isp64_hist_weight_04to34: Weighting factor for sub-windows (0x00000040)*/ +/*! Slice: hist_weight_34:*/ +/*! weighting factor for sub-window 34 */ +#define MRV_HIST_WEIGHT_34 +#define MRV_HIST_WEIGHT_34_MASK 0x1F000000U +#define MRV_HIST_WEIGHT_34_SHIFT 24U +/*! Slice: hist_weight_24:*/ +/*! weighting factor for sub-window 24 */ +#define MRV_HIST_WEIGHT_24 +#define MRV_HIST_WEIGHT_24_MASK 0x001F0000U +#define MRV_HIST_WEIGHT_24_SHIFT 16U +/*! Slice: hist_weight_14:*/ +/*! weighting factor for sub-window 14 */ +#define MRV_HIST_WEIGHT_14 +#define MRV_HIST_WEIGHT_14_MASK 0x00001F00U +#define MRV_HIST_WEIGHT_14_SHIFT 8U +/*! Slice: hist_weight_04:*/ +/*! weighting factor for sub-window 04 */ +#define MRV_HIST_WEIGHT_04 +#define MRV_HIST_WEIGHT_04_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_04_SHIFT 0U +/*! Register: isp64_hist_weight_44: Weighting factor for sub-windows (0x00000044)*/ +/*! Slice: hist_weight_44:*/ +/*! weighting factor for sub-window 44 */ +#define MRV_HIST_WEIGHT_44 +#define MRV_HIST_WEIGHT_44_MASK 0x0000001FU +#define MRV_HIST_WEIGHT_44_SHIFT 0U +/*! Register: isp64_hist_forced_upd_start_line: Forced update start line limit (0x00000048)*/ +/*! Slice: forced_upd_start_line:*/ +/*! start line for histogram calculation in case of forced update. histogram is started as soon as current line < forced_upd_start_line. Used start line will be given in ISP64_HIST_VSTART_STATUS.*/ +#define MRV_HIST_FORCED_UPD_START_LINE +#define MRV_HIST_FORCED_UPD_START_LINE_MASK 0x00001FFFU +#define MRV_HIST_FORCED_UPD_START_LINE_SHIFT 0U +/*! Register: isp64_hist_forced_update: Histogram forced update (0x0000004c)*/ +/*! Slice: forced_upd:*/ +/*! 0: no effect */ +/* 1: forcing register update.*/ +#define MRV_HIST_FORCED_UPD +#define MRV_HIST_FORCED_UPD_MASK 0x00000001U +#define MRV_HIST_FORCED_UPD_SHIFT 0U +/*! Register: isp64_hist_vstart_status: Forced update start line status (0x00000050)*/ +/*! Slice: hist_vstart_status:*/ +/*! start line for histogram. Important in case of backward switching because 1st histogram after switch might not cover the complete image.*/ +#define MRV_HIST_VSTART_STATUS +#define MRV_HIST_VSTART_STATUS_MASK 0x00001FFFU +#define MRV_HIST_VSTART_STATUS_SHIFT 0U +/*! Register array: isp64_hist_bin: histogram measurement result bin (0x0A8 + n*0x4 (n=0..31))*/ +/*! Slice: hist_bin:*/ +/* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */ +#define MRV_HIST_BIN +#define MRV_HIST_BIN_MASK 0x000FFFFFU +#define MRV_HIST_BIN_SHIFT 0U +/*! Register: isp_vsm_mode: VS Measure Mode (0x00000000)*/ +/*! Slice: vsm_meas_irq_enable:*/ +/*! 1: VS measure done IRQ enable.*/ +#define ISP_VSM_MEAS_IRQ_ENABLE +#define ISP_VSM_MEAS_IRQ_ENABLE_MASK 0x00000002U +#define ISP_VSM_MEAS_IRQ_ENABLE_SHIFT 1U +/*! Slice: vsm_meas_en:*/ +/*! 1: enable measure.*/ +#define ISP_VSM_MEAS_EN +#define ISP_VSM_MEAS_EN_MASK 0x00000001U +#define ISP_VSM_MEAS_EN_SHIFT 0U +/*! Register: isp_vsm_h_offs: VSM window horizontal offset (0x00000004)*/ +/*! Slice: vsm_h_offset:*/ +/*! Horizontal offset in pixels.*/ +#define ISP_VSM_H_OFFSET +#define ISP_VSM_H_OFFSET_MASK 0x00001FFFU +#define ISP_VSM_H_OFFSET_SHIFT 0U +/*! Register: isp_vsm_v_offs: VSM window vertical offset (0x00000008)*/ +/*! Slice: vsm_v_offset:*/ +/*! Vertical offset in pixels.*/ +#define ISP_VSM_V_OFFSET +#define ISP_VSM_V_OFFSET_MASK 0x00001FFFU +#define ISP_VSM_V_OFFSET_SHIFT 0U +/*! Register: isp_vsm_h_size: Horizontal measure window size (0x0000000c)*/ +/*! Slice: vsm_h_size:*/ +/*! Horizontal size in pixels. Range 64..1920 */ +#define ISP_VSM_H_SIZE +#define ISP_VSM_H_SIZE_MASK 0x00000780U +#define ISP_VSM_H_SIZE_SHIFT 1U +/*! Register: isp_vsm_v_size: Vertical measure window size (0x00000010)*/ +/*! Slice: vsm_v_size:*/ +/*! Vertical size. Range 64..1088 */ +#define ISP_VSM_V_SIZE +#define ISP_VSM_V_SIZE_MASK 0x00000440U +#define ISP_VSM_V_SIZE_SHIFT 1U +/*! Register: isp_vsm_h_segments: Iteration 1 horizontal segments (0x00000014)*/ +/*! Slice: vsm_h_segments:*/ +/*! number of 16 point wide segments enclosed by the first iteration sample points in horizontal direction. Range: 1 ... 128 */ +#define ISP_VSM_H_SEGMENTS +#define ISP_VSM_H_SEGMENTS_MASK 0x000000FFU +#define ISP_VSM_H_SEGMENTS_SHIFT 0U +/*! Register: isp_vsm_v_segments: Iteration 1 vertical segments (0x00000018)*/ +/*! Slice: vsm_v_segments:*/ +/*! number of 16 point wide segments enclosed by the first iteration sample points in vertical direction. Range: 1 ... 128 */ +#define ISP_VSM_V_SEGMENTS +#define ISP_VSM_V_SEGMENTS_MASK 0x000000FFU +#define ISP_VSM_V_SEGMENTS_SHIFT 0U +/*! Register: isp_vsm_delta_h: estimated horizontal displacement (0x0000001c)*/ +/*! Slice: delta_h:*/ +/*! estimated horizontal displacement 12Bit two's complement. positive values indicate a displacement of the image from right to left (camera turns right)*/ +#define ISP_VSM_DELTA_H +#define ISP_VSM_DELTA_H_MASK 0x00000FFFU +#define ISP_VSM_DELTA_H_SHIFT 0U +/*! Register: isp_vsm_delta_v: estimated vertical displacement (0x00000020)*/ +/*! Slice: delta_v:*/ +/*! estimated vertical displacement 12Bit two's complement. positive values indicate a displacement of the image from bottom to top (camera turns down)*/ +#define ISP_VSM_DELTA_V +#define ISP_VSM_DELTA_V_MASK 0x00000FFFU +#define ISP_VSM_DELTA_V_SHIFT 0U +//#ifdef ISP_RGBGC_RY +/*! Register: isp_ctrl:isp control register (0x00000400)*/ +/*! Slice: rgb_gc_enable */ +/*! Control of rgb gamma correction */ +/*! 1'b0: disable rgb GC bypass mode */ +/*! 1'b1: enable rgb GC mode */ +#define ISP_RGBGC_ENABLE +#define ISP_RGBGC_ENABLE_MASK 0x00000800U +#define ISP_RGBGC_ENABLE_SHIFT 11U +//#endif +#ifdef ISP_GCMONO +/*! Register: isp_ctrl:isp control register (0x00000400)*/ +/*! Slice: mono_gc_enable */ +/*! Control of gamma correction for mono sensor RAW data */ +/*! 1'b0: disable GC bypass mode */ +/*! 1'b1: enable GC mode */ +#define ISP_GCMONO_ENABLE +#define ISP_GCMONO_ENABLE_MASK 0x00080000U +#define ISP_GCMONO_ENABLE_SHIFT 19U +/*! Register: isp_ctrl:isp control register (0x00000400)*/ +/*! Slice: mono_gc_mode */ +/*! Control of gamma correction for mono sensor RAW data mode */ +/*! 1'b0: 0: 10->8 */ +/*! 1'b1: 12->10 */ +#define ISP_GCMONO_MODE +#define ISP_GCMONO_MODE_MASK 0x00100000U +#define ISP_GCMONO_MODE_SHIFT 20 +/*! Register: isp_gcmono_ctrl: GC Mono control register (0x00000000)*/ +/*! Slice: mono_gc_enable */ +/*! Control of gamma correction for mono sensor RAW data */ +/*! 1'b0: disable GC bypass mode */ +/*! 1'b1: enable GC mode */ +#define ISP_GCMONO_SWITCH +#define ISP_GCMONO_SWITCH_MASK 0x00000001U +#define ISP_GCMONO_SWITCH_SHIFT 0U +/*! Slice: mono_gc_cfg_done */ +/*! To notify the ISP HW the LUT configuration is done, ready to use, active high.*/ +/*! Writing ZERO reset teh internal read/write pointer and also indicates that the LUT can be configured or read from CPU.*/ +#define ISP_GCMONO_CFG_DONE +#define ISP_GCMONO_CFG_DONE_MASK 0x00000002U +#define ISP_GCMONO_CFG_DONE_SHIFT 1U +/*! Register: isp_gcmono_para_base: GC Mono Gamma LUT for mono sensor (0x00000004)*/ +/*! Slice: Base address of Gamma LUT for mono sensor, when AHB slave writes/reads this register address continuously, it means it will start to */ +/*! write or read the LUT.*/ +#define ISP_GCMONO_PARA_BASE +#define ISP_GCMONO_PARA_BASE_MASK 0xFFFFFFFFU +#define ISP_GCMONO_PARA_BASE_SHIFT 0U +#endif +/*! Register: isp_wdr2_ctrl (0x00003100)*/ +/*! Slice: wdr2_soft_reset_flag:*/ +#define WDR2_SOFT_RESET_FLAG +#define WDR2_SOFT_RESET_FLAG_MASK 0x00000004U +#define WDR2_SOFT_RESET_FLAG_SHIFT 2U +/*! Slice: wdr2_mono_input:*/ +#define WDR2_MONO_INPUT +#define WDR2_MONO_INPUT_MASK 0x00000002U +#define WDR2_MONO_INPUT_SHIFT 1U +/*! Slice: wdr2_enable:*/ +#define WDR2_ENABLE +#define WDR2_ENABLE_MASK 0x00000001U +#define WDR2_ENABLE_SHIFT 0U +/*! Register: isp_wdr2_blk_siz (0x00003104)*/ +/*! Slice: hist_block_width:*/ +#define HIST_BLOCK_WIDTH +#define HIST_BLOCK_WIDTH_MASK 0x000FFC00U +#define HIST_BLOCK_WIDTH_SHIFT 10U +/*! Slice: hist_block_height:*/ +#define HIST_BLOCK_HEIGHT +#define HIST_BLOCK_HEIGHT_MASK 0x000003FFU +#define HIST_BLOCK_HEIGHT_SHIFT 0U +/*! Register: isp_wdr2_color_weight (0x00003108)*/ +/*! Slice: wdr2_color_weight_2:*/ +#define WDR2_COLOR_WEIGHT_2 +#define WDR2_COLOR_WEIGHT_2_MASK 0x00FF0000U +#define WDR2_COLOR_WEIGHT_2_SHIFT 16U +/*! Slice: wdr2_color_weight_1:*/ +#define WDR2_COLOR_WEIGHT_1 +#define WDR2_COLOR_WEIGHT_1_MASK 0x0000FF00U +#define WDR2_COLOR_WEIGHT_1_SHIFT 8U +/*! Slice: wdr2_color_weight_0:*/ +#define WDR2_COLOR_WEIGHT_0 +#define WDR2_COLOR_WEIGHT_0_MASK 0x000000FFU +#define WDR2_COLOR_WEIGHT_0_SHIFT 0U +/*! Register: isp_wdr2_blt_sigma (0x0000310C)*/ +/*! Slice: wdr2_blt_range_sigma:*/ +#define WDR2_BLT_RANGE_SIGMA +#define WDR2_BLT_RANGE_SIGMA_MASK 0x000FFC00U +#define WDR2_BLT_RANGE_SIGMA_SHIFT 10U +/*! Slice: wdr2_blt_spatial_sigma:*/ +#define WDR2_BLT_SPATIAL_SIGMA +#define WDR2_BLT_SPATIAL_SIGMA_MASK 0x000003FFU +#define WDR2_BLT_SPATIAL_SIGMA_SHIFT 0U +/*! Register: isp_wdr2_blt_kernel_0 (0x00003110)*/ +/*! Slice: wdr2_blt_kernel_c:*/ +#define WDR2_BLT_KERNEL_C +#define WDR2_BLT_KERNEL_C_MASK 0x00FF0000U +#define WDR2_BLT_KERNEL_C_SHIFT 16U +/*! Slice: wdr2_blt_kernel_b:*/ +#define WDR2_BLT_KERNEL_B +#define WDR2_BLT_KERNEL_B_MASK 0x0000FF00U +#define WDR2_BLT_KERNEL_B_SHIFT 8U +/*! Slice: wdr2_blt_kernel_a:*/ +#define WDR2_BLT_KERNEL_A +#define WDR2_BLT_KERNEL_A_MASK 0x000000FFU +#define WDR2_BLT_KERNEL_A_SHIFT 0U +/*! Register: isp_wdr2_blt_kernel_1 (0x00003114)*/ +/*! Slice: wdr2_blt_kernel_f:*/ +#define WDR2_BLT_KERNEL_F +#define WDR2_BLT_KERNEL_F_MASK 0x00FF0000U +#define WDR2_BLT_KERNEL_F_SHIFT 16U +/*! Slice: wdr2_blt_kernel_e:*/ +#define WDR2_BLT_KERNEL_E +#define WDR2_BLT_KERNEL_E_MASK 0x0000FF00U +#define WDR2_BLT_KERNEL_E_SHIFT 8U +/*! Slice: wdr2_blt_kernel_d:*/ +#define WDR2_BLT_KERNEL_D +#define WDR2_BLT_KERNEL_D_MASK 0x000000FFU +#define WDR2_BLT_KERNEL_D_SHIFT 0U +/*! Register: isp_wdr2_vol_shift_bit (0x00003118)*/ +/*! Slice: wdr2_vol_shift_bit:*/ +#define WDR2_VOL_SHIFT_BIT +#define WDR2_VOL_SHIFT_BIT_MASK 0x0000001FU +#define WDR2_VOL_SHIFT_BIT_SHIFT 0U +/*! Register: isp_wdr2_bin_dist_0 (0x0000311C)*/ +/*! Slice: wdr2_bin_dist_1:*/ +#define WDR2_BIN_DIST_1 +#define WDR2_BIN_DIST_1_MASK 0x0FFF0000U +#define WDR2_BIN_DIST_1_SHIFT 16U +/*! Slice: wdr2_bin_dist_0:*/ +#define WDR2_BIN_DIST_0 +#define WDR2_BIN_DIST_0_MASK 0x00000FFFU +#define WDR2_BIN_DIST_0_SHIFT 0U +/*! Register: isp_wdr2_bin_dist_1 (0x00003120)*/ +/*! Slice: wdr2_bin_dist_3:*/ +#define WDR2_BIN_DIST_3 +#define WDR2_BIN_DIST_3_MASK 0x0FFF0000U +#define WDR2_BIN_DIST_3_SHIFT 16U +/*! Slice: wdr2_bin_dist_2:*/ +#define WDR2_BIN_DIST_2 +#define WDR2_BIN_DIST_2_MASK 0x00000FFFU +#define WDR2_BIN_DIST_2_SHIFT 0U +/*! Register: isp_wdr2_bin_dist_2 (0x00003124)*/ +/*! Slice: wdr2_bin_dist_5:*/ +#define WDR2_BIN_DIST_5 +#define WDR2_BIN_DIST_5_MASK 0x0FFF0000U +#define WDR2_BIN_DIST_5_SHIFT 16U +/*! Slice: wdr2_bin_dist_4:*/ +#define WDR2_BIN_DIST_4 +#define WDR2_BIN_DIST_4_MASK 0x00000FFFU +#define WDR2_BIN_DIST_4_SHIFT 0U +/*! Register: isp_wdr2_bin_dist_3 (0x00003128)*/ +/*! Slice: wdr2_bin_dist_7:*/ +#define WDR2_BIN_DIST_7 +#define WDR2_BIN_DIST_7_MASK 0x0FFF0000U +#define WDR2_BIN_DIST_7_SHIFT 16U +/*! Slice: wdr2_bin_dist_6:*/ +#define WDR2_BIN_DIST_6 +#define WDR2_BIN_DIST_6_MASK 0x00000FFFU +#define WDR2_BIN_DIST_6_SHIFT 0U +/*! Register: isp_wdr2_hist_norm_fac (0x0000312C)*/ +/*! Slice: wdr2_hist_norm_shift_bit:*/ +#define WDR2_HIST_NORM_SHIFT_BIT +#define WDR2_HIST_NORM_SHIFT_BIT_MASK 0x0FFF0000U +#define WDR2_HIST_NORM_SHIFT_BIT_SHIFT 16U +/*! Slice: wdr2_hist_norm_mul:*/ +#define WDR2_HIST_NORM_MUL +#define WDR2_HIST_NORM_MUL_MASK 0x00000FFFU +#define WDR2_HIST_NORM_MUL_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_lut (0x00003138)*/ +/*! Slice: wdr2_pre_gamma_lut:*/ +#define WDR2_PRE_GAMMA_LUT +#define WDR2_PRE_GAMMA_LUT_MASK 0xFFFFFFFFU +#define WDR2_PRE_GAMMA_LUT_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_write_data (0x0000313C)*/ +/*! Slice: wdr2_pre_gamma_write_data:*/ +#define WDR2_PRE_GAMMA_WRITE_DATA +#define WDR2_PRE_GAMMA_WRITE_DATA_MASK 0x00000FFFU +#define WDR2_PRE_GAMMA_WRITE_DATA_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_lut (0x00003140)*/ +/*! Slice: wdr2_tone_curve_lut:*/ +#define WDR2_TONE_CURVE_LUT +#define WDR2_TONE_CURVE_LUT_MASK 0xFFFFFFFFU +#define WDR2_TONE_CURVE_LUT_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_write_data (0x00003144)*/ +/*! Slice: wdr2_tone_curve_write_data:*/ +#define WDR2_TONE_CURVE_WRITE_DATA +#define WDR2_TONE_CURVE_WRITE_DATA_MASK 0x00000FFFU +#define WDR2_TONE_CURVE_WRITE_DATA_SHIFT 0U +/*! Register: isp_wdr2_merge_coeff_lut (0x00003148)*/ +/*! Slice: wdr2_merge_coeff_lut:*/ +#define WDR2_MERGE_COEFF_LUT +#define WDR2_MERGE_COEFF_LUT_MASK 0xFFFFFFFFU +#define WDR2_MERGE_COEFF_LUT_SHIFT 0U +/*! Register: isp_wdr2_merge_coeff_write_data (0x0000314C)*/ +/*! Slice: wdr2_merge_coeff_write_data:*/ +#define WDR2_MERGE_COEFF_WRITE_DATA +#define WDR2_MERGE_COEFF_WRITE_DATA_MASK 0x000000FFU +#define WDR2_MERGE_COEFF_WRITE_DATA_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_0 (0x00003150)*/ +/*! Slice: wdr2_pre_gamma_cx_5:*/ +#define WDR2_PRE_GAMMA_CX_5 +#define WDR2_PRE_GAMMA_CX_5_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_5_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_4:*/ +#define WDR2_PRE_GAMMA_CX_4 +#define WDR2_PRE_GAMMA_CX_4_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_4_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_3:*/ +#define WDR2_PRE_GAMMA_CX_3 +#define WDR2_PRE_GAMMA_CX_3_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_3_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_2:*/ +#define WDR2_PRE_GAMMA_CX_2 +#define WDR2_PRE_GAMMA_CX_2_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_2_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_1:*/ +#define WDR2_PRE_GAMMA_CX_1 +#define WDR2_PRE_GAMMA_CX_1_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_1_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_0:*/ +#define WDR2_PRE_GAMMA_CX_0 +#define WDR2_PRE_GAMMA_CX_0_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_0_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_1 (0x00003154)*/ +/*! Slice: wdr2_pre_gamma_cx_11:*/ +#define WDR2_PRE_GAMMA_CX_11 +#define WDR2_PRE_GAMMA_CX_11_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_11_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_10:*/ +#define WDR2_PRE_GAMMA_CX_10 +#define WDR2_PRE_GAMMA_CX_10_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_10_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_9:*/ +#define WDR2_PRE_GAMMA_CX_9 +#define WDR2_PRE_GAMMA_CX_9_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_9_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_8:*/ +#define WDR2_PRE_GAMMA_CX_8 +#define WDR2_PRE_GAMMA_CX_8_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_8_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_7:*/ +#define WDR2_PRE_GAMMA_CX_7 +#define WDR2_PRE_GAMMA_CX_7_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_7_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_6:*/ +#define WDR2_PRE_GAMMA_CX_6 +#define WDR2_PRE_GAMMA_CX_6_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_6_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_2 (0x00003158)*/ +/*! Slice: wdr2_pre_gamma_cx_17:*/ +#define WDR2_PRE_GAMMA_CX_17 +#define WDR2_PRE_GAMMA_CX_17_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_17_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_16:*/ +#define WDR2_PRE_GAMMA_CX_16 +#define WDR2_PRE_GAMMA_CX_16_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_16_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_15:*/ +#define WDR2_PRE_GAMMA_CX_15 +#define WDR2_PRE_GAMMA_CX_15_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_15_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_14:*/ +#define WDR2_PRE_GAMMA_CX_14 +#define WDR2_PRE_GAMMA_CX_14_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_14_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_13:*/ +#define WDR2_PRE_GAMMA_CX_13 +#define WDR2_PRE_GAMMA_CX_13_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_13_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_12:*/ +#define WDR2_PRE_GAMMA_CX_12 +#define WDR2_PRE_GAMMA_CX_12_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_12_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_3 (0x0000315C)*/ +/*! Slice: wdr2_pre_gamma_cx_23:*/ +#define WDR2_PRE_GAMMA_CX_23 +#define WDR2_PRE_GAMMA_CX_23_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_23_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_22:*/ +#define WDR2_PRE_GAMMA_CX_22 +#define WDR2_PRE_GAMMA_CX_22_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_22_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_21:*/ +#define WDR2_PRE_GAMMA_CX_21 +#define WDR2_PRE_GAMMA_CX_21_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_21_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_20:*/ +#define WDR2_PRE_GAMMA_CX_20 +#define WDR2_PRE_GAMMA_CX_20_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_20_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_19:*/ +#define WDR2_PRE_GAMMA_CX_19 +#define WDR2_PRE_GAMMA_CX_19_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_19_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_18:*/ +#define WDR2_PRE_GAMMA_CX_18 +#define WDR2_PRE_GAMMA_CX_18_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_18_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_4 (0x00003160)*/ +/*! Slice: wdr2_pre_gamma_cx_29:*/ +#define WDR2_PRE_GAMMA_CX_29 +#define WDR2_PRE_GAMMA_CX_29_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_29_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_28:*/ +#define WDR2_PRE_GAMMA_CX_28 +#define WDR2_PRE_GAMMA_CX_28_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_28_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_27:*/ +#define WDR2_PRE_GAMMA_CX_27 +#define WDR2_PRE_GAMMA_CX_27_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_27_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_26:*/ +#define WDR2_PRE_GAMMA_CX_26 +#define WDR2_PRE_GAMMA_CX_26_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_26_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_25:*/ +#define WDR2_PRE_GAMMA_CX_25 +#define WDR2_PRE_GAMMA_CX_25_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_25_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_24:*/ +#define WDR2_PRE_GAMMA_CX_24 +#define WDR2_PRE_GAMMA_CX_24_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_24_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_5 (0x00003164)*/ +/*! Slice: wdr2_pre_gamma_cx_35:*/ +#define WDR2_PRE_GAMMA_CX_35 +#define WDR2_PRE_GAMMA_CX_35_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_35_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_34:*/ +#define WDR2_PRE_GAMMA_CX_34 +#define WDR2_PRE_GAMMA_CX_34_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_34_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_33:*/ +#define WDR2_PRE_GAMMA_CX_33 +#define WDR2_PRE_GAMMA_CX_33_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_33_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_32:*/ +#define WDR2_PRE_GAMMA_CX_32 +#define WDR2_PRE_GAMMA_CX_32_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_32_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_31:*/ +#define WDR2_PRE_GAMMA_CX_31 +#define WDR2_PRE_GAMMA_CX_31_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_31_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_30:*/ +#define WDR2_PRE_GAMMA_CX_30 +#define WDR2_PRE_GAMMA_CX_30_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_30_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_6 (0x00003168)*/ +/*! Slice: wdr2_pre_gamma_cx_41:*/ +#define WDR2_PRE_GAMMA_CX_41 +#define WDR2_PRE_GAMMA_CX_41_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_41_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_40:*/ +#define WDR2_PRE_GAMMA_CX_40 +#define WDR2_PRE_GAMMA_CX_40_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_40_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_39:*/ +#define WDR2_PRE_GAMMA_CX_39 +#define WDR2_PRE_GAMMA_CX_39_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_39_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_38:*/ +#define WDR2_PRE_GAMMA_CX_38 +#define WDR2_PRE_GAMMA_CX_38_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_38_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_37:*/ +#define WDR2_PRE_GAMMA_CX_37 +#define WDR2_PRE_GAMMA_CX_37_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_37_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_36:*/ +#define WDR2_PRE_GAMMA_CX_36 +#define WDR2_PRE_GAMMA_CX_36_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_36_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_7 (0x0000316C)*/ +/*! Slice: wdr2_pre_gamma_cx_47:*/ +#define WDR2_PRE_GAMMA_CX_47 +#define WDR2_PRE_GAMMA_CX_47_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_47_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_46:*/ +#define WDR2_PRE_GAMMA_CX_46 +#define WDR2_PRE_GAMMA_CX_46_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_46_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_45:*/ +#define WDR2_PRE_GAMMA_CX_45 +#define WDR2_PRE_GAMMA_CX_45_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_45_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_44:*/ +#define WDR2_PRE_GAMMA_CX_44 +#define WDR2_PRE_GAMMA_CX_44_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_44_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_43:*/ +#define WDR2_PRE_GAMMA_CX_43 +#define WDR2_PRE_GAMMA_CX_43_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_43_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_42:*/ +#define WDR2_PRE_GAMMA_CX_42 +#define WDR2_PRE_GAMMA_CX_42_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_42_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_8 (0x00003170)*/ +/*! Slice: wdr2_pre_gamma_cx_53:*/ +#define WDR2_PRE_GAMMA_CX_53 +#define WDR2_PRE_GAMMA_CX_53_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_53_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_52:*/ +#define WDR2_PRE_GAMMA_CX_52 +#define WDR2_PRE_GAMMA_CX_52_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_52_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_51:*/ +#define WDR2_PRE_GAMMA_CX_51 +#define WDR2_PRE_GAMMA_CX_51_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_51_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_50:*/ +#define WDR2_PRE_GAMMA_CX_50 +#define WDR2_PRE_GAMMA_CX_50_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_50_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_49:*/ +#define WDR2_PRE_GAMMA_CX_49 +#define WDR2_PRE_GAMMA_CX_49_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_49_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_48:*/ +#define WDR2_PRE_GAMMA_CX_48 +#define WDR2_PRE_GAMMA_CX_48_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_48_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_9 (0x00003174)*/ +/*! Slice: wdr2_pre_gamma_cx_59:*/ +#define WDR2_PRE_GAMMA_CX_59 +#define WDR2_PRE_GAMMA_CX_59_MASK 0x3E000000U +#define WDR2_PRE_GAMMA_CX_59_SHIFT 25U +/*! Slice: wdr2_pre_gamma_cx_58:*/ +#define WDR2_PRE_GAMMA_CX_58 +#define WDR2_PRE_GAMMA_CX_58_MASK 0x01F00000U +#define WDR2_PRE_GAMMA_CX_58_SHIFT 20U +/*! Slice: wdr2_pre_gamma_cx_57:*/ +#define WDR2_PRE_GAMMA_CX_57 +#define WDR2_PRE_GAMMA_CX_57_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_57_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_56:*/ +#define WDR2_PRE_GAMMA_CX_56 +#define WDR2_PRE_GAMMA_CX_56_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_56_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_55:*/ +#define WDR2_PRE_GAMMA_CX_55 +#define WDR2_PRE_GAMMA_CX_55_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_55_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_54:*/ +#define WDR2_PRE_GAMMA_CX_54 +#define WDR2_PRE_GAMMA_CX_54_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_54_SHIFT 0U +/*! Register: isp_wdr2_pre_gamma_cx_10 (0x00003178)*/ +/*! Slice: wdr2_pre_gamma_cx_63:*/ +#define WDR2_PRE_GAMMA_CX_63 +#define WDR2_PRE_GAMMA_CX_63_MASK 0x000F8000U +#define WDR2_PRE_GAMMA_CX_63_SHIFT 15U +/*! Slice: wdr2_pre_gamma_cx_62:*/ +#define WDR2_PRE_GAMMA_CX_62 +#define WDR2_PRE_GAMMA_CX_62_MASK 0x00007C00U +#define WDR2_PRE_GAMMA_CX_62_SHIFT 10U +/*! Slice: wdr2_pre_gamma_cx_61:*/ +#define WDR2_PRE_GAMMA_CX_61 +#define WDR2_PRE_GAMMA_CX_61_MASK 0x000003E0U +#define WDR2_PRE_GAMMA_CX_61_SHIFT 5U +/*! Slice: wdr2_pre_gamma_cx_60:*/ +#define WDR2_PRE_GAMMA_CX_60 +#define WDR2_PRE_GAMMA_CX_60_MASK 0x0000001FU +#define WDR2_PRE_GAMMA_CX_60_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_cx_0 (0x0000317C)*/ +/*! Slice: wdr2_tone_curve_cx_7:*/ +#define WDR2_TONE_CURVE_CX_7 +#define WDR2_TONE_CURVE_CX_7_MASK 0xF0000000U +#define WDR2_TONE_CURVE_CX_7_SHIFT 28U +/*! Slice: wdr2_tone_curve_cx_6:*/ +#define WDR2_TONE_CURVE_CX_6 +#define WDR2_TONE_CURVE_CX_6_MASK 0x0F000000U +#define WDR2_TONE_CURVE_CX_6_SHIFT 24U +/*! Slice: wdr2_tone_curve_cx_5:*/ +#define WDR2_TONE_CURVE_CX_5 +#define WDR2_TONE_CURVE_CX_5_MASK 0x00F00000U +#define WDR2_TONE_CURVE_CX_5_SHIFT 20U +/*! Slice: wdr2_tone_curve_cx_4:*/ +#define WDR2_TONE_CURVE_CX_4 +#define WDR2_TONE_CURVE_CX_4_MASK 0x000F0000U +#define WDR2_TONE_CURVE_CX_4_SHIFT 16U +/*! Slice: wdr2_tone_curve_cx_3:*/ +#define WDR2_TONE_CURVE_CX_3 +#define WDR2_TONE_CURVE_CX_3_MASK 0x0000F000U +#define WDR2_TONE_CURVE_CX_3_SHIFT 12U +/*! Slice: wdr2_tone_curve_cx_2:*/ +#define WDR2_TONE_CURVE_CX_2 +#define WDR2_TONE_CURVE_CX_2_MASK 0x00000F00U +#define WDR2_TONE_CURVE_CX_2_SHIFT 8U +/*! Slice: wdr2_tone_curve_cx_1:*/ +#define WDR2_TONE_CURVE_CX_1 +#define WDR2_TONE_CURVE_CX_1_MASK 0x000000F0U +#define WDR2_TONE_CURVE_CX_1_SHIFT 4U +/*! Slice: wdr2_tone_curve_cx_0:*/ +#define WDR2_TONE_CURVE_CX_0 +#define WDR2_TONE_CURVE_CX_0_MASK 0x0000000FU +#define WDR2_TONE_CURVE_CX_0_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_cx_1 (0x00003180)*/ +/*! Slice: wdr2_tone_curve_cx_15:*/ +#define WDR2_TONE_CURVE_CX_15 +#define WDR2_TONE_CURVE_CX_15_MASK 0xF0000000U +#define WDR2_TONE_CURVE_CX_15_SHIFT 28U +/*! Slice: wdr2_tone_curve_cx_14:*/ +#define WDR2_TONE_CURVE_CX_14 +#define WDR2_TONE_CURVE_CX_14_MASK 0x0F000000U +#define WDR2_TONE_CURVE_CX_14_SHIFT 24U +/*! Slice: wdr2_tone_curve_cx_13:*/ +#define WDR2_TONE_CURVE_CX_13 +#define WDR2_TONE_CURVE_CX_13_MASK 0x00F00000U +#define WDR2_TONE_CURVE_CX_13_SHIFT 20U +/*! Slice: wdr2_tone_curve_cx_12:*/ +#define WDR2_TONE_CURVE_CX_12 +#define WDR2_TONE_CURVE_CX_12_MASK 0x000F0000U +#define WDR2_TONE_CURVE_CX_12_SHIFT 16U +/*! Slice: wdr2_tone_curve_cx_11:*/ +#define WDR2_TONE_CURVE_CX_11 +#define WDR2_TONE_CURVE_CX_11_MASK 0x0000F000U +#define WDR2_TONE_CURVE_CX_11_SHIFT 12U +/*! Slice: wdr2_tone_curve_cx_10:*/ +#define WDR2_TONE_CURVE_CX_10 +#define WDR2_TONE_CURVE_CX_10_MASK 0x00000F00U +#define WDR2_TONE_CURVE_CX_10_SHIFT 8U +/*! Slice: wdr2_tone_curve_cx_9:*/ +#define WDR2_TONE_CURVE_CX_9 +#define WDR2_TONE_CURVE_CX_9_MASK 0x000000F0U +#define WDR2_TONE_CURVE_CX_9_SHIFT 4U +/*! Slice: wdr2_tone_curve_cx_8:*/ +#define WDR2_TONE_CURVE_CX_8 +#define WDR2_TONE_CURVE_CX_8_MASK 0x0000000FU +#define WDR2_TONE_CURVE_CX_8_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_cx_2 (0x00003184)*/ +/*! Slice: wdr2_tone_curve_cx_23:*/ +#define WDR2_TONE_CURVE_CX_23 +#define WDR2_TONE_CURVE_CX_23_MASK 0xF0000000U +#define WDR2_TONE_CURVE_CX_23_SHIFT 28U +/*! Slice: wdr2_tone_curve_cx_22:*/ +#define WDR2_TONE_CURVE_CX_22 +#define WDR2_TONE_CURVE_CX_22_MASK 0x0F000000U +#define WDR2_TONE_CURVE_CX_22_SHIFT 24U +/*! Slice: wdr2_tone_curve_cx_21:*/ +#define WDR2_TONE_CURVE_CX_21 +#define WDR2_TONE_CURVE_CX_21_MASK 0x00F00000U +#define WDR2_TONE_CURVE_CX_21_SHIFT 20U +/*! Slice: wdr2_tone_curve_cx_20:*/ +#define WDR2_TONE_CURVE_CX_20 +#define WDR2_TONE_CURVE_CX_20_MASK 0x000F0000U +#define WDR2_TONE_CURVE_CX_20_SHIFT 16U +/*! Slice: wdr2_tone_curve_cx_19:*/ +#define WDR2_TONE_CURVE_CX_19 +#define WDR2_TONE_CURVE_CX_19_MASK 0x0000F000U +#define WDR2_TONE_CURVE_CX_19_SHIFT 12U +/*! Slice: wdr2_tone_curve_cx_18:*/ +#define WDR2_TONE_CURVE_CX_18 +#define WDR2_TONE_CURVE_CX_18_MASK 0x00000F00U +#define WDR2_TONE_CURVE_CX_18_SHIFT 8U +/*! Slice: wdr2_tone_curve_cx_17:*/ +#define WDR2_TONE_CURVE_CX_17 +#define WDR2_TONE_CURVE_CX_17_MASK 0x000000F0U +#define WDR2_TONE_CURVE_CX_17_SHIFT 4U +/*! Slice: wdr2_tone_curve_cx_16:*/ +#define WDR2_TONE_CURVE_CX_16 +#define WDR2_TONE_CURVE_CX_16_MASK 0x0000000FU +#define WDR2_TONE_CURVE_CX_16_SHIFT 0U +/*! Register: isp_wdr2_tone_curve_cx_3 (0x00003188)*/ +/*! Slice: wdr2_tone_curve_cx_31:*/ +#define WDR2_TONE_CURVE_CX_31 +#define WDR2_TONE_CURVE_CX_31_MASK 0xF0000000U +#define WDR2_TONE_CURVE_CX_31_SHIFT 28U +/*! Slice: wdr2_tone_curve_cx_30:*/ +#define WDR2_TONE_CURVE_CX_30 +#define WDR2_TONE_CURVE_CX_30_MASK 0x0F000000U +#define WDR2_TONE_CURVE_CX_30_SHIFT 24U +/*! Slice: wdr2_tone_curve_cx_29:*/ +#define WDR2_TONE_CURVE_CX_29 +#define WDR2_TONE_CURVE_CX_29_MASK 0x00F00000U +#define WDR2_TONE_CURVE_CX_29_SHIFT 20U +/*! Slice: wdr2_tone_curve_cx_28:*/ +#define WDR2_TONE_CURVE_CX_28 +#define WDR2_TONE_CURVE_CX_28_MASK 0x000F0000U +#define WDR2_TONE_CURVE_CX_28_SHIFT 16U +/*! Slice: wdr2_tone_curve_cx_27:*/ +#define WDR2_TONE_CURVE_CX_27 +#define WDR2_TONE_CURVE_CX_27_MASK 0x0000F000U +#define WDR2_TONE_CURVE_CX_27_SHIFT 12U +/*! Slice: wdr2_tone_curve_cx_26:*/ +#define WDR2_TONE_CURVE_CX_26 +#define WDR2_TONE_CURVE_CX_26_MASK 0x00000F00U +#define WDR2_TONE_CURVE_CX_26_SHIFT 8U +/*! Slice: wdr2_tone_curve_cx_25:*/ +#define WDR2_TONE_CURVE_CX_25 +#define WDR2_TONE_CURVE_CX_25_MASK 0x000000F0U +#define WDR2_TONE_CURVE_CX_25_SHIFT 4U +/*! Slice: wdr2_tone_curve_cx_24:*/ +#define WDR2_TONE_CURVE_CX_24 +#define WDR2_TONE_CURVE_CX_24_MASK 0x0000000FU +#define WDR2_TONE_CURVE_CX_24_SHIFT 0U +/*! Register: isp_wdr2_merge_coeff_cx_0 (0x0000318C)*/ +/*! Slice: wdr2_merge_coeff_cx_7:*/ +#define WDR2_MERGE_COEFF_CX_7 +#define WDR2_MERGE_COEFF_CX_7_MASK 0xF0000000U +#define WDR2_MERGE_COEFF_CX_7_SHIFT 28U +/*! Slice: wdr2_merge_coeff_cx_6:*/ +#define WDR2_MERGE_COEFF_CX_6 +#define WDR2_MERGE_COEFF_CX_6_MASK 0x0F000000U +#define WDR2_MERGE_COEFF_CX_6_SHIFT 24U +/*! Slice: wdr2_merge_coeff_cx_5:*/ +#define WDR2_MERGE_COEFF_CX_5 +#define WDR2_MERGE_COEFF_CX_5_MASK 0x00F00000U +#define WDR2_MERGE_COEFF_CX_5_SHIFT 20U +/*! Slice: wdr2_merge_coeff_cx_4:*/ +#define WDR2_MERGE_COEFF_CX_4 +#define WDR2_MERGE_COEFF_CX_4_MASK 0x000F0000U +#define WDR2_MERGE_COEFF_CX_4_SHIFT 16U +/*! Slice: wdr2_merge_coeff_cx_3:*/ +#define WDR2_MERGE_COEFF_CX_3 +#define WDR2_MERGE_COEFF_CX_3_MASK 0x0000F000U +#define WDR2_MERGE_COEFF_CX_3_SHIFT 12U +/*! Slice: wdr2_merge_coeff_cx_2:*/ +#define WDR2_MERGE_COEFF_CX_2 +#define WDR2_MERGE_COEFF_CX_2_MASK 0x00000F00U +#define WDR2_MERGE_COEFF_CX_2_SHIFT 8U +/*! Slice: wdr2_merge_coeff_cx_1:*/ +#define WDR2_MERGE_COEFF_CX_1 +#define WDR2_MERGE_COEFF_CX_1_MASK 0x000000F0U +#define WDR2_MERGE_COEFF_CX_1_SHIFT 4U +/*! Slice: wdr2_merge_coeff_cx_0:*/ +#define WDR2_MERGE_COEFF_CX_0 +#define WDR2_MERGE_COEFF_CX_0_MASK 0x0000000FU +#define WDR2_MERGE_COEFF_CX_0_SHIFT 0U +/*! Register: isp_wdr2_merge_coeff_cx_1 (0x00003190)*/ +/*! Slice: wdr2_merge_coeff_cx_15:*/ +#define WDR2_MERGE_COEFF_CX_15 +#define WDR2_MERGE_COEFF_CX_15_MASK 0xF0000000U +#define WDR2_MERGE_COEFF_CX_15_SHIFT 28U +/*! Slice: wdr2_merge_coeff_cx_14:*/ +#define WDR2_MERGE_COEFF_CX_14 +#define WDR2_MERGE_COEFF_CX_14_MASK 0x0F000000U +#define WDR2_MERGE_COEFF_CX_14_SHIFT 24U +/*! Slice: wdr2_merge_coeff_cx_13:*/ +#define WDR2_MERGE_COEFF_CX_13 +#define WDR2_MERGE_COEFF_CX_13_MASK 0x00F00000U +#define WDR2_MERGE_COEFF_CX_13_SHIFT 20U +/*! Slice: wdr2_merge_coeff_cx_12:*/ +#define WDR2_MERGE_COEFF_CX_12 +#define WDR2_MERGE_COEFF_CX_12_MASK 0x000F0000U +#define WDR2_MERGE_COEFF_CX_12_SHIFT 16U +/*! Slice: wdr2_merge_coeff_cx_11:*/ +#define WDR2_MERGE_COEFF_CX_11 +#define WDR2_MERGE_COEFF_CX_11_MASK 0x0000F000U +#define WDR2_MERGE_COEFF_CX_11_SHIFT 12U +/*! Slice: wdr2_merge_coeff_cx_10:*/ +#define WDR2_MERGE_COEFF_CX_10 +#define WDR2_MERGE_COEFF_CX_10_MASK 0x00000F00U +#define WDR2_MERGE_COEFF_CX_10_SHIFT 8U +/*! Slice: wdr2_merge_coeff_cx_9:*/ +#define WDR2_MERGE_COEFF_CX_9 +#define WDR2_MERGE_COEFF_CX_9_MASK 0x000000F0U +#define WDR2_MERGE_COEFF_CX_9_SHIFT 4U +/*! Slice: wdr2_merge_coeff_cx_8:*/ +#define WDR2_MERGE_COEFF_CX_8 +#define WDR2_MERGE_COEFF_CX_8_MASK 0x0000000FU +#define WDR2_MERGE_COEFF_CX_8_SHIFT 0U +/*! Register: isp_wdr2_max_gain_cx (0x000031A8)*/ +/*! Slice: wdr2_max_gain_cx_4:*/ +#define WDR2_MAX_GAIN_CX_4 +#define WDR2_MAX_GAIN_CX_4_MASK 0xFF000000U +#define WDR2_MAX_GAIN_CX_4_SHIFT 24U +/*! Slice: wdr2_max_gain_cx_3:*/ +#define WDR2_MAX_GAIN_CX_3 +#define WDR2_MAX_GAIN_CX_3_MASK 0x00FF0000U +#define WDR2_MAX_GAIN_CX_3_SHIFT 16U +/*! Slice: wdr2_max_gain_cx_2:*/ +#define WDR2_MAX_GAIN_CX_2 +#define WDR2_MAX_GAIN_CX_2_MASK 0x0000FF00U +#define WDR2_MAX_GAIN_CX_2_SHIFT 8U +/*! Slice: wdr2_max_gain_cx_1:*/ +#define WDR2_MAX_GAIN_CX_1 +#define WDR2_MAX_GAIN_CX_1_MASK 0x000000FFU +#define WDR2_MAX_GAIN_CX_1_SHIFT 0U +/*! Register: isp_wdr2_max_gain_slope_0 (0x000031AC)*/ +/*! Slice: wdr2_max_gain_slope_1:*/ +#define WDR2_MAX_GAIN_SLOPE_1 +#define WDR2_MAX_GAIN_SLOPE_1_MASK 0x0FFF0000U +#define WDR2_MAX_GAIN_SLOPE_1_SHIFT 16U +/*! Slice: wdr2_max_gain_slope_0:*/ +#define WDR2_MAX_GAIN_SLOPE_0 +#define WDR2_MAX_GAIN_SLOPE_0_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_SLOPE_0_SHIFT 0U +/*! Register: isp_wdr2_max_gain_slope_1 (0x000031B0)*/ +/*! Slice: wdr2_max_gain_slope_3:*/ +#define WDR2_MAX_GAIN_SLOPE_3 +#define WDR2_MAX_GAIN_SLOPE_3_MASK 0x0FFF0000U +#define WDR2_MAX_GAIN_SLOPE_3_SHIFT 16U +/*! Slice: wdr2_max_gain_slope_2:*/ +#define WDR2_MAX_GAIN_SLOPE_2 +#define WDR2_MAX_GAIN_SLOPE_2_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_SLOPE_2_SHIFT 0U +/*! Register: isp_wdr2_max_gain_slope_2 (0x000031B4)*/ +/*! Slice: wdr2_max_gain_slope_4:*/ +#define WDR2_MAX_GAIN_SLOPE_4 +#define WDR2_MAX_GAIN_SLOPE_4_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_SLOPE_4_SHIFT 0U +/*! Register: isp_wdr2_max_gain_cy_0 (0x000031B8)*/ +/*! Slice: wdr2_max_gain_cy_1:*/ +#define WDR2_MAX_GAIN_CY_1 +#define WDR2_MAX_GAIN_CY_1_MASK 0x0FFF0000U +#define WDR2_MAX_GAIN_CY_1_SHIFT 16U +/*! Slice: wdr2_max_gain_cy_0:*/ +#define WDR2_MAX_GAIN_CY_0 +#define WDR2_MAX_GAIN_CY_0_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_CY_0_SHIFT 0U +/*! Register: isp_wdr2_max_gain_cy_1 (0x000031BC)*/ +/*! Slice: wdr2_max_gain_cy_3:*/ +#define WDR2_MAX_GAIN_CY_3 +#define WDR2_MAX_GAIN_CY_3_MASK 0x0FFF0000U +#define WDR2_MAX_GAIN_CY_3_SHIFT 16U +/*! Slice: wdr2_max_gain_cy_2:*/ +#define WDR2_MAX_GAIN_CY_2 +#define WDR2_MAX_GAIN_CY_2_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_CY_2_SHIFT 0U +/*! Register: isp_wdr2_max_gain_cy_2 (0x000031C0)*/ +/*! Slice: wdr2_max_gain_cy_5:*/ +#define WDR2_MAX_GAIN_CY_5 +#define WDR2_MAX_GAIN_CY_5_MASK 0x0FFF0000U +#define WDR2_MAX_GAIN_CY_5_SHIFT 16U +/*! Slice: wdr2_max_gain_cy_4:*/ +#define WDR2_MAX_GAIN_CY_4 +#define WDR2_MAX_GAIN_CY_4_MASK 0x00000FFFU +#define WDR2_MAX_GAIN_CY_4_SHIFT 0U +/*! Register: isp_wdr2_norm_factor_mul_0 (0x000031C4)*/ +/*! Slice: wdr2_norm_factor_mul_3:*/ +#define WDR2_NORM_FACTOR_MUL_3 +#define WDR2_NORM_FACTOR_MUL_3_MASK 0xFF000000U +#define WDR2_NORM_FACTOR_MUL_3_SHIFT 24U +/*! Slice: wdr2_norm_factor_mul_2:*/ +#define WDR2_NORM_FACTOR_MUL_2 +#define WDR2_NORM_FACTOR_MUL_2_MASK 0x00FF0000U +#define WDR2_NORM_FACTOR_MUL_2_SHIFT 16U +/*! Slice: wdr2_norm_factor_mul_1:*/ +#define WDR2_NORM_FACTOR_MUL_1 +#define WDR2_NORM_FACTOR_MUL_1_MASK 0x0000FF00U +#define WDR2_NORM_FACTOR_MUL_1_SHIFT 8U +/*! Slice: wdr2_norm_factor_mul_0:*/ +#define WDR2_NORM_FACTOR_MUL_0 +#define WDR2_NORM_FACTOR_MUL_0_MASK 0x000000FFU +#define WDR2_NORM_FACTOR_MUL_0_SHIFT 0U +/*! Register: isp_wdr2_norm_factor_mul_1 (0x000031C8)*/ +/*! Slice: wdr2_norm_factor_mul_7:*/ +#define WDR2_NORM_FACTOR_MUL_7 +#define WDR2_NORM_FACTOR_MUL_7_MASK 0xFF000000U +#define WDR2_NORM_FACTOR_MUL_7_SHIFT 24U +/*! Slice: wdr2_norm_factor_mul_6:*/ +#define WDR2_NORM_FACTOR_MUL_6 +#define WDR2_NORM_FACTOR_MUL_6_MASK 0x00FF0000U +#define WDR2_NORM_FACTOR_MUL_6_SHIFT 16U +/*! Slice: wdr2_norm_factor_mul_5:*/ +#define WDR2_NORM_FACTOR_MUL_5 +#define WDR2_NORM_FACTOR_MUL_5_MASK 0x0000FF00U +#define WDR2_NORM_FACTOR_MUL_5_SHIFT 8U +/*! Slice: wdr2_norm_factor_mul_4:*/ +#define WDR2_NORM_FACTOR_MUL_4 +#define WDR2_NORM_FACTOR_MUL_4_MASK 0x000000FFU +#define WDR2_NORM_FACTOR_MUL_4_SHIFT 0U +/*! Register: isp_wdr2_norm_factor_shift_bit_0 (0x000031CC)*/ +/*! Slice: wdr2_norm_factor_shift_bit_3:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_3 +#define WDR2_NORM_FACTOR_SHIFT_BIT_3_MASK 0xFF000000U +#define WDR2_NORM_FACTOR_SHIFT_BIT_3_SHIFT 24U +/*! Slice: wdr2_norm_factor_shift_bit_2:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_2 +#define WDR2_NORM_FACTOR_SHIFT_BIT_2_MASK 0x00FF0000U +#define WDR2_NORM_FACTOR_SHIFT_BIT_2_SHIFT 16U +/*! Slice: wdr2_norm_factor_shift_bit_1:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_1 +#define WDR2_NORM_FACTOR_SHIFT_BIT_1_MASK 0x0000FF00U +#define WDR2_NORM_FACTOR_SHIFT_BIT_1_SHIFT 8U +/*! Slice: wdr2_norm_factor_shift_bit_0:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_0 +#define WDR2_NORM_FACTOR_SHIFT_BIT_0_MASK 0x000000FFU +#define WDR2_NORM_FACTOR_SHIFT_BIT_0_SHIFT 0U +/*! Register: isp_wdr2_norm_factor_shift_bit_1 (0x000031D0)*/ +/*! Slice: wdr2_norm_factor_shift_bit_7:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_7 +#define WDR2_NORM_FACTOR_SHIFT_BIT_7_MASK 0xFF000000U +#define WDR2_NORM_FACTOR_SHIFT_BIT_7_SHIFT 24U +/*! Slice: wdr2_norm_factor_shift_bit_6:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_6 +#define WDR2_NORM_FACTOR_SHIFT_BIT_6_MASK 0x00FF0000U +#define WDR2_NORM_FACTOR_SHIFT_BIT_6_SHIFT 16U +/*! Slice: wdr2_norm_factor_shift_bit_5:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_5 +#define WDR2_NORM_FACTOR_SHIFT_BIT_5_MASK 0x0000FF00U +#define WDR2_NORM_FACTOR_SHIFT_BIT_5_SHIFT 8U +/*! Slice: wdr2_norm_factor_shift_bit_4:*/ +#define WDR2_NORM_FACTOR_SHIFT_BIT_4 +#define WDR2_NORM_FACTOR_SHIFT_BIT_4_MASK 0x000000FFU +#define WDR2_NORM_FACTOR_SHIFT_BIT_4_SHIFT 0U +/*! Register: isp_wdr2_bin_range_0 (0x000031D4)*/ +/*! Slice: wdr2_bin_range_2:*/ +#define WDR2_BIN_RANGE_2 +#define WDR2_BIN_RANGE_2_MASK 0x0FFF0000U +#define WDR2_BIN_RANGE_2_SHIFT 16U +/*! Slice: wdr2_bin_range_1:*/ +#define WDR2_BIN_RANGE_1 +#define WDR2_BIN_RANGE_1_MASK 0x00000FFFU +#define WDR2_BIN_RANGE_1_SHIFT 0U +/*! Register: isp_wdr2_bin_range_1 (0x000031D8)*/ +/*! Slice: wdr2_bin_range_4:*/ +#define WDR2_BIN_RANGE_4 +#define WDR2_BIN_RANGE_4_MASK 0x0FFF0000U +#define WDR2_BIN_RANGE_4_SHIFT 16U +/*! Slice: wdr2_bin_range_3:*/ +#define WDR2_BIN_RANGE_3 +#define WDR2_BIN_RANGE_3_MASK 0x00000FFFU +#define WDR2_BIN_RANGE_3_SHIFT 0U +/*! Register: isp_wdr2_bin_range_2 (0x000031DC)*/ +/*! Slice: wdr2_bin_range_6:*/ +#define WDR2_BIN_RANGE_6 +#define WDR2_BIN_RANGE_6_MASK 0x0FFF0000U +#define WDR2_BIN_RANGE_6_SHIFT 16U +/*! Slice: wdr2_bin_range_5:*/ +#define WDR2_BIN_RANGE_5 +#define WDR2_BIN_RANGE_5_MASK 0x00000FFFU +#define WDR2_BIN_RANGE_5_SHIFT 0U +/*! Register: isp_wdr2_bin_range_3 (0x000031E0)*/ +/*! Slice: wdr2_bin_range_8:*/ +#define WDR2_BIN_RANGE_8 +#define WDR2_BIN_RANGE_8_MASK 0x0FFF0000U +#define WDR2_BIN_RANGE_8_SHIFT 16U +/*! Slice: wdr2_bin_range_7:*/ +#define WDR2_BIN_RANGE_7 +#define WDR2_BIN_RANGE_7_MASK 0x00000FFFU +#define WDR2_BIN_RANGE_7_SHIFT 0U +/*! Register: isp_wdr2_hist_data_0 (0x000031E4)*/ +/*! Slice: wdr2_hist_data_3:*/ +#define WDR2_HIST_DATA_3 +#define WDR2_HIST_DATA_3_MASK 0xFF000000U +#define WDR2_HIST_DATA_3_SHIFT 24U +/*! Slice: wdr2_hist_data_2:*/ +#define WDR2_HIST_DATA_2 +#define WDR2_HIST_DATA_2_MASK 0x00FF0000U +#define WDR2_HIST_DATA_2_SHIFT 16U +/*! Slice: wdr2_hist_data_1:*/ +#define WDR2_HIST_DATA_1 +#define WDR2_HIST_DATA_1_MASK 0x0000FF00U +#define WDR2_HIST_DATA_1_SHIFT 8U +/*! Slice: wdr2_hist_data_0:*/ +#define WDR2_HIST_DATA_0 +#define WDR2_HIST_DATA_0_MASK 0x000000FFU +#define WDR2_HIST_DATA_0_SHIFT 0U +/*! Register: isp_wdr2_hist_data_1 (0x000031E8)*/ +/*! Slice: wdr2_hist_data_7:*/ +#define WDR2_HIST_DATA_7 +#define WDR2_HIST_DATA_7_MASK 0xFF000000U +#define WDR2_HIST_DATA_7_SHIFT 24U +/*! Slice: wdr2_hist_data_6:*/ +#define WDR2_HIST_DATA_6 +#define WDR2_HIST_DATA_6_MASK 0x00FF0000U +#define WDR2_HIST_DATA_6_SHIFT 16U +/*! Slice: wdr2_hist_data_5:*/ +#define WDR2_HIST_DATA_5 +#define WDR2_HIST_DATA_5_MASK 0x0000FF00U +#define WDR2_HIST_DATA_5_SHIFT 8U +/*! Slice: wdr2_hist_data_4:*/ +#define WDR2_HIST_DATA_4 +#define WDR2_HIST_DATA_4_MASK 0x000000FFU +#define WDR2_HIST_DATA_4_SHIFT 0U +/*! Register: isp_compand_ctrl (0x00003200)*/ +/*! Slice: compand_ctrl_bls_enable:*/ +#define COMPAND_CTRL_BLS_ENABLE +#define COMPAND_CTRL_BLS_ENABLE_MASK 0x00000008U +#define COMPAND_CTRL_BLS_ENABLE_SHIFT 3U +/*! Slice: compand_ctrl_soft_reset_flag:*/ +#define COMPAND_CTRL_SOFT_RESET_FLAG +#define COMPAND_CTRL_SOFT_RESET_FLAG_MASK 0x00000004U +#define COMPAND_CTRL_SOFT_RESET_FLAG_SHIFT 2U +/*! Slice: compand_ctrl_compress_enable:*/ +#define COMPAND_CTRL_COMPRESS_ENABLE +#define COMPAND_CTRL_COMPRESS_ENABLE_MASK 0x00000002U +#define COMPAND_CTRL_COMPRESS_ENABLE_SHIFT 1U +/*! Slice: compand_ctrl_expand_enable:*/ +#define COMPAND_CTRL_EXPAND_ENABLE +#define COMPAND_CTRL_EXPAND_ENABLE_MASK 0x00000001U +#define COMPAND_CTRL_EXPAND_ENABLE_SHIFT 0U +/*! Register: isp_compand_bls_a_fixed (0x00003204)*/ +/*! Slice: compand_bls_a_fixed:*/ +#define COMPAND_BLS_A_FIXED +#define COMPAND_BLS_A_FIXED_MASK 0x001FFFFFU +#define COMPAND_BLS_A_FIXED_SHIFT 0U +/*! Register: isp_compand_bls_b_fixed (0x00003208)*/ +/*! Slice: compand_bls_b_fixed:*/ +#define COMPAND_BLS_B_FIXED +#define COMPAND_BLS_B_FIXED_MASK 0x001FFFFFU +#define COMPAND_BLS_B_FIXED_SHIFT 0U +/*! Register: isp_compand_bls_c_fixed (0x0000320C)*/ +/*! Slice: compand_bls_c_fixed:*/ +#define COMPAND_BLS_C_FIXED +#define COMPAND_BLS_C_FIXED_MASK 0x001FFFFFU +#define COMPAND_BLS_C_FIXED_SHIFT 0U +/*! Register: isp_compand_bls_d_fixed (0x00003210)*/ +/*! Slice: compand_bls_d_fixed:*/ +#define COMPAND_BLS_D_FIXED +#define COMPAND_BLS_D_FIXED_MASK 0x001FFFFFU +#define COMPAND_BLS_D_FIXED_SHIFT 0U +/*! Register: isp_compand_expand_px_0 (0x00003214)*/ +/*! Slice: compand_expand_px_5:*/ +#define COMPAND_EXPAND_PX_5 +#define COMPAND_EXPAND_PX_5_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_5_SHIFT 25U +/*! Slice: compand_expand_px_4:*/ +#define COMPAND_EXPAND_PX_4 +#define COMPAND_EXPAND_PX_4_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_4_SHIFT 20U +/*! Slice: compand_expand_px_3:*/ +#define COMPAND_EXPAND_PX_3 +#define COMPAND_EXPAND_PX_3_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_3_SHIFT 15U +/*! Slice: compand_expand_px_2:*/ +#define COMPAND_EXPAND_PX_2 +#define COMPAND_EXPAND_PX_2_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_2_SHIFT 10U +/*! Slice: compand_expand_px_1:*/ +#define COMPAND_EXPAND_PX_1 +#define COMPAND_EXPAND_PX_1_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_1_SHIFT 5U +/*! Slice: compand_expand_px_0:*/ +#define COMPAND_EXPAND_PX_0 +#define COMPAND_EXPAND_PX_0_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_0_SHIFT 0U +/*! Register: isp_compand_expand_px_1 (0x00003218)*/ +/*! Slice: compand_expand_px_11:*/ +#define COMPAND_EXPAND_PX_11 +#define COMPAND_EXPAND_PX_11_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_11_SHIFT 25U +/*! Slice: compand_expand_px_10:*/ +#define COMPAND_EXPAND_PX_10 +#define COMPAND_EXPAND_PX_10_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_10_SHIFT 20U +/*! Slice: compand_expand_px_9:*/ +#define COMPAND_EXPAND_PX_9 +#define COMPAND_EXPAND_PX_9_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_9_SHIFT 15U +/*! Slice: compand_expand_px_8:*/ +#define COMPAND_EXPAND_PX_8 +#define COMPAND_EXPAND_PX_8_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_8_SHIFT 10U +/*! Slice: compand_expand_px_7:*/ +#define COMPAND_EXPAND_PX_7 +#define COMPAND_EXPAND_PX_7_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_7_SHIFT 5U +/*! Slice: compand_expand_px_6:*/ +#define COMPAND_EXPAND_PX_6 +#define COMPAND_EXPAND_PX_6_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_6_SHIFT 0U +/*! Register: isp_compand_expand_px_2 (0x0000321C)*/ +/*! Slice: compand_expand_px_17:*/ +#define COMPAND_EXPAND_PX_17 +#define COMPAND_EXPAND_PX_17_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_17_SHIFT 25U +/*! Slice: compand_expand_px_16:*/ +#define COMPAND_EXPAND_PX_16 +#define COMPAND_EXPAND_PX_16_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_16_SHIFT 20U +/*! Slice: compand_expand_px_15:*/ +#define COMPAND_EXPAND_PX_15 +#define COMPAND_EXPAND_PX_15_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_15_SHIFT 15U +/*! Slice: compand_expand_px_14:*/ +#define COMPAND_EXPAND_PX_14 +#define COMPAND_EXPAND_PX_14_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_14_SHIFT 10U +/*! Slice: compand_expand_px_13:*/ +#define COMPAND_EXPAND_PX_13 +#define COMPAND_EXPAND_PX_13_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_13_SHIFT 5U +/*! Slice: compand_expand_px_12:*/ +#define COMPAND_EXPAND_PX_12 +#define COMPAND_EXPAND_PX_12_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_12_SHIFT 0U +/*! Register: isp_compand_expand_px_3 (0x00003220)*/ +/*! Slice: compand_expand_px_23:*/ +#define COMPAND_EXPAND_PX_23 +#define COMPAND_EXPAND_PX_23_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_23_SHIFT 25U +/*! Slice: compand_expand_px_22:*/ +#define COMPAND_EXPAND_PX_22 +#define COMPAND_EXPAND_PX_22_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_22_SHIFT 20U +/*! Slice: compand_expand_px_21:*/ +#define COMPAND_EXPAND_PX_21 +#define COMPAND_EXPAND_PX_21_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_21_SHIFT 15U +/*! Slice: compand_expand_px_20:*/ +#define COMPAND_EXPAND_PX_20 +#define COMPAND_EXPAND_PX_20_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_20_SHIFT 10U +/*! Slice: compand_expand_px_19:*/ +#define COMPAND_EXPAND_PX_19 +#define COMPAND_EXPAND_PX_19_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_19_SHIFT 5U +/*! Slice: compand_expand_px_18:*/ +#define COMPAND_EXPAND_PX_18 +#define COMPAND_EXPAND_PX_18_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_18_SHIFT 0U +/*! Register: isp_compand_expand_px_4 (0x00003224)*/ +/*! Slice: compand_expand_px_29:*/ +#define COMPAND_EXPAND_PX_29 +#define COMPAND_EXPAND_PX_29_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_29_SHIFT 25U +/*! Slice: compand_expand_px_28:*/ +#define COMPAND_EXPAND_PX_28 +#define COMPAND_EXPAND_PX_28_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_28_SHIFT 20U +/*! Slice: compand_expand_px_27:*/ +#define COMPAND_EXPAND_PX_27 +#define COMPAND_EXPAND_PX_27_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_27_SHIFT 15U +/*! Slice: compand_expand_px_26:*/ +#define COMPAND_EXPAND_PX_26 +#define COMPAND_EXPAND_PX_26_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_26_SHIFT 10U +/*! Slice: compand_expand_px_25:*/ +#define COMPAND_EXPAND_PX_25 +#define COMPAND_EXPAND_PX_25_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_25_SHIFT 5U +/*! Slice: compand_expand_px_24:*/ +#define COMPAND_EXPAND_PX_24 +#define COMPAND_EXPAND_PX_24_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_24_SHIFT 0U +/*! Register: isp_compand_expand_px_5 (0x00003228)*/ +/*! Slice: compand_expand_px_35:*/ +#define COMPAND_EXPAND_PX_35 +#define COMPAND_EXPAND_PX_35_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_35_SHIFT 25U +/*! Slice: compand_expand_px_34:*/ +#define COMPAND_EXPAND_PX_34 +#define COMPAND_EXPAND_PX_34_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_34_SHIFT 20U +/*! Slice: compand_expand_px_33:*/ +#define COMPAND_EXPAND_PX_33 +#define COMPAND_EXPAND_PX_33_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_33_SHIFT 15U +/*! Slice: compand_expand_px_32:*/ +#define COMPAND_EXPAND_PX_32 +#define COMPAND_EXPAND_PX_32_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_32_SHIFT 10U +/*! Slice: compand_expand_px_31:*/ +#define COMPAND_EXPAND_PX_31 +#define COMPAND_EXPAND_PX_31_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_31_SHIFT 5U +/*! Slice: compand_expand_px_30:*/ +#define COMPAND_EXPAND_PX_30 +#define COMPAND_EXPAND_PX_30_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_30_SHIFT 0U +/*! Register: isp_compand_expand_px_6 (0x0000322C)*/ +/*! Slice: compand_expand_px_41:*/ +#define COMPAND_EXPAND_PX_41 +#define COMPAND_EXPAND_PX_41_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_41_SHIFT 25U +/*! Slice: compand_expand_px_40:*/ +#define COMPAND_EXPAND_PX_40 +#define COMPAND_EXPAND_PX_40_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_40_SHIFT 20U +/*! Slice: compand_expand_px_39:*/ +#define COMPAND_EXPAND_PX_39 +#define COMPAND_EXPAND_PX_39_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_39_SHIFT 15U +/*! Slice: compand_expand_px_38:*/ +#define COMPAND_EXPAND_PX_38 +#define COMPAND_EXPAND_PX_38_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_38_SHIFT 10U +/*! Slice: compand_expand_px_37:*/ +#define COMPAND_EXPAND_PX_37 +#define COMPAND_EXPAND_PX_37_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_37_SHIFT 5U +/*! Slice: compand_expand_px_36:*/ +#define COMPAND_EXPAND_PX_36 +#define COMPAND_EXPAND_PX_36_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_36_SHIFT 0U +/*! Register: isp_compand_expand_px_7 (0x00003230)*/ +/*! Slice: compand_expand_px_47:*/ +#define COMPAND_EXPAND_PX_47 +#define COMPAND_EXPAND_PX_47_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_47_SHIFT 25U +/*! Slice: compand_expand_px_46:*/ +#define COMPAND_EXPAND_PX_46 +#define COMPAND_EXPAND_PX_46_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_46_SHIFT 20U +/*! Slice: compand_expand_px_45:*/ +#define COMPAND_EXPAND_PX_45 +#define COMPAND_EXPAND_PX_45_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_45_SHIFT 15U +/*! Slice: compand_expand_px_44:*/ +#define COMPAND_EXPAND_PX_44 +#define COMPAND_EXPAND_PX_44_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_44_SHIFT 10U +/*! Slice: compand_expand_px_43:*/ +#define COMPAND_EXPAND_PX_43 +#define COMPAND_EXPAND_PX_43_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_43_SHIFT 5U +/*! Slice: compand_expand_px_42:*/ +#define COMPAND_EXPAND_PX_42 +#define COMPAND_EXPAND_PX_42_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_42_SHIFT 0U +/*! Register: isp_compand_expand_px_8 (0x00003234)*/ +/*! Slice: compand_expand_px_53:*/ +#define COMPAND_EXPAND_PX_53 +#define COMPAND_EXPAND_PX_53_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_53_SHIFT 25U +/*! Slice: compand_expand_px_52:*/ +#define COMPAND_EXPAND_PX_52 +#define COMPAND_EXPAND_PX_52_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_52_SHIFT 20U +/*! Slice: compand_expand_px_51:*/ +#define COMPAND_EXPAND_PX_51 +#define COMPAND_EXPAND_PX_51_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_51_SHIFT 15U +/*! Slice: compand_expand_px_50:*/ +#define COMPAND_EXPAND_PX_50 +#define COMPAND_EXPAND_PX_50_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_50_SHIFT 10U +/*! Slice: compand_expand_px_49:*/ +#define COMPAND_EXPAND_PX_49 +#define COMPAND_EXPAND_PX_49_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_49_SHIFT 5U +/*! Slice: compand_expand_px_48:*/ +#define COMPAND_EXPAND_PX_48 +#define COMPAND_EXPAND_PX_48_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_48_SHIFT 0U +/*! Register: isp_compand_expand_px_9 (0x00003238)*/ +/*! Slice: compand_expand_px_59:*/ +#define COMPAND_EXPAND_PX_59 +#define COMPAND_EXPAND_PX_59_MASK 0x3E000000U +#define COMPAND_EXPAND_PX_59_SHIFT 25U +/*! Slice: compand_expand_px_58:*/ +#define COMPAND_EXPAND_PX_58 +#define COMPAND_EXPAND_PX_58_MASK 0x01F00000U +#define COMPAND_EXPAND_PX_58_SHIFT 20U +/*! Slice: compand_expand_px_57:*/ +#define COMPAND_EXPAND_PX_57 +#define COMPAND_EXPAND_PX_57_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_57_SHIFT 15U +/*! Slice: compand_expand_px_56:*/ +#define COMPAND_EXPAND_PX_56 +#define COMPAND_EXPAND_PX_56_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_56_SHIFT 10U +/*! Slice: compand_expand_px_55:*/ +#define COMPAND_EXPAND_PX_55 +#define COMPAND_EXPAND_PX_55_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_55_SHIFT 5U +/*! Slice: compand_expand_px_54:*/ +#define COMPAND_EXPAND_PX_54 +#define COMPAND_EXPAND_PX_54_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_54_SHIFT 0U +/*! Register: isp_compand_expand_px_10 (0x0000323C)*/ +/*! Slice: compand_expand_px_63:*/ +#define COMPAND_EXPAND_PX_63 +#define COMPAND_EXPAND_PX_63_MASK 0x000F8000U +#define COMPAND_EXPAND_PX_63_SHIFT 15U +/*! Slice: compand_expand_px_62:*/ +#define COMPAND_EXPAND_PX_62 +#define COMPAND_EXPAND_PX_62_MASK 0x00007C00U +#define COMPAND_EXPAND_PX_62_SHIFT 10U +/*! Slice: compand_expand_px_61:*/ +#define COMPAND_EXPAND_PX_61 +#define COMPAND_EXPAND_PX_61_MASK 0x000003E0U +#define COMPAND_EXPAND_PX_61_SHIFT 5U +/*! Slice: compand_expand_px_60:*/ +#define COMPAND_EXPAND_PX_60 +#define COMPAND_EXPAND_PX_60_MASK 0x0000001FU +#define COMPAND_EXPAND_PX_60_SHIFT 0U +/*! Register: isp_compand_compress_px_0 (0x00003240)*/ +/*! Slice: compand_compress_px_5:*/ +#define COMPAND_COMPRESS_PX_5 +#define COMPAND_COMPRESS_PX_5_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_5_SHIFT 25U +/*! Slice: compand_compress_px_4:*/ +#define COMPAND_COMPRESS_PX_4 +#define COMPAND_COMPRESS_PX_4_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_4_SHIFT 20U +/*! Slice: compand_compress_px_3:*/ +#define COMPAND_COMPRESS_PX_3 +#define COMPAND_COMPRESS_PX_3_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_3_SHIFT 15U +/*! Slice: compand_compress_px_2:*/ +#define COMPAND_COMPRESS_PX_2 +#define COMPAND_COMPRESS_PX_2_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_2_SHIFT 10U +/*! Slice: compand_compress_px_1:*/ +#define COMPAND_COMPRESS_PX_1 +#define COMPAND_COMPRESS_PX_1_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_1_SHIFT 5U +/*! Slice: compand_compress_px_0:*/ +#define COMPAND_COMPRESS_PX_0 +#define COMPAND_COMPRESS_PX_0_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_0_SHIFT 0U +/*! Register: isp_compand_compress_px_1 (0x00003244)*/ +/*! Slice: compand_compress_px_11:*/ +#define COMPAND_COMPRESS_PX_11 +#define COMPAND_COMPRESS_PX_11_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_11_SHIFT 25U +/*! Slice: compand_compress_px_10:*/ +#define COMPAND_COMPRESS_PX_10 +#define COMPAND_COMPRESS_PX_10_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_10_SHIFT 20U +/*! Slice: compand_compress_px_9:*/ +#define COMPAND_COMPRESS_PX_9 +#define COMPAND_COMPRESS_PX_9_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_9_SHIFT 15U +/*! Slice: compand_compress_px_8:*/ +#define COMPAND_COMPRESS_PX_8 +#define COMPAND_COMPRESS_PX_8_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_8_SHIFT 10U +/*! Slice: compand_compress_px_7:*/ +#define COMPAND_COMPRESS_PX_7 +#define COMPAND_COMPRESS_PX_7_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_7_SHIFT 5U +/*! Slice: compand_compress_px_6:*/ +#define COMPAND_COMPRESS_PX_6 +#define COMPAND_COMPRESS_PX_6_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_6_SHIFT 0U +/*! Register: isp_compand_compress_px_2 (0x00003248)*/ +/*! Slice: compand_compress_px_17:*/ +#define COMPAND_COMPRESS_PX_17 +#define COMPAND_COMPRESS_PX_17_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_17_SHIFT 25U +/*! Slice: compand_compress_px_16:*/ +#define COMPAND_COMPRESS_PX_16 +#define COMPAND_COMPRESS_PX_16_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_16_SHIFT 20U +/*! Slice: compand_compress_px_15:*/ +#define COMPAND_COMPRESS_PX_15 +#define COMPAND_COMPRESS_PX_15_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_15_SHIFT 15U +/*! Slice: compand_compress_px_14:*/ +#define COMPAND_COMPRESS_PX_14 +#define COMPAND_COMPRESS_PX_14_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_14_SHIFT 10U +/*! Slice: compand_compress_px_13:*/ +#define COMPAND_COMPRESS_PX_13 +#define COMPAND_COMPRESS_PX_13_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_13_SHIFT 5U +/*! Slice: compand_compress_px_12:*/ +#define COMPAND_COMPRESS_PX_12 +#define COMPAND_COMPRESS_PX_12_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_12_SHIFT 0U +/*! Register: isp_compand_compress_px_3 (0x0000324C)*/ +/*! Slice: compand_compress_px_23:*/ +#define COMPAND_COMPRESS_PX_23 +#define COMPAND_COMPRESS_PX_23_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_23_SHIFT 25U +/*! Slice: compand_compress_px_22:*/ +#define COMPAND_COMPRESS_PX_22 +#define COMPAND_COMPRESS_PX_22_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_22_SHIFT 20U +/*! Slice: compand_compress_px_21:*/ +#define COMPAND_COMPRESS_PX_21 +#define COMPAND_COMPRESS_PX_21_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_21_SHIFT 15U +/*! Slice: compand_compress_px_20:*/ +#define COMPAND_COMPRESS_PX_20 +#define COMPAND_COMPRESS_PX_20_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_20_SHIFT 10U +/*! Slice: compand_compress_px_19:*/ +#define COMPAND_COMPRESS_PX_19 +#define COMPAND_COMPRESS_PX_19_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_19_SHIFT 5U +/*! Slice: compand_compress_px_18:*/ +#define COMPAND_COMPRESS_PX_18 +#define COMPAND_COMPRESS_PX_18_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_18_SHIFT 0U +/*! Register: isp_compand_compress_px_4 (0x00003250)*/ +/*! Slice: compand_compress_px_29:*/ +#define COMPAND_COMPRESS_PX_29 +#define COMPAND_COMPRESS_PX_29_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_29_SHIFT 25U +/*! Slice: compand_compress_px_28:*/ +#define COMPAND_COMPRESS_PX_28 +#define COMPAND_COMPRESS_PX_28_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_28_SHIFT 20U +/*! Slice: compand_compress_px_27:*/ +#define COMPAND_COMPRESS_PX_27 +#define COMPAND_COMPRESS_PX_27_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_27_SHIFT 15U +/*! Slice: compand_compress_px_26:*/ +#define COMPAND_COMPRESS_PX_26 +#define COMPAND_COMPRESS_PX_26_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_26_SHIFT 10U +/*! Slice: compand_compress_px_25:*/ +#define COMPAND_COMPRESS_PX_25 +#define COMPAND_COMPRESS_PX_25_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_25_SHIFT 5U +/*! Slice: compand_compress_px_24:*/ +#define COMPAND_COMPRESS_PX_24 +#define COMPAND_COMPRESS_PX_24_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_24_SHIFT 0U +/*! Register: isp_compand_compress_px_5 (0x00003254)*/ +/*! Slice: compand_compress_px_35:*/ +#define COMPAND_COMPRESS_PX_35 +#define COMPAND_COMPRESS_PX_35_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_35_SHIFT 25U +/*! Slice: compand_compress_px_34:*/ +#define COMPAND_COMPRESS_PX_34 +#define COMPAND_COMPRESS_PX_34_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_34_SHIFT 20U +/*! Slice: compand_compress_px_33:*/ +#define COMPAND_COMPRESS_PX_33 +#define COMPAND_COMPRESS_PX_33_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_33_SHIFT 15U +/*! Slice: compand_compress_px_32:*/ +#define COMPAND_COMPRESS_PX_32 +#define COMPAND_COMPRESS_PX_32_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_32_SHIFT 10U +/*! Slice: compand_compress_px_31:*/ +#define COMPAND_COMPRESS_PX_31 +#define COMPAND_COMPRESS_PX_31_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_31_SHIFT 5U +/*! Slice: compand_compress_px_30:*/ +#define COMPAND_COMPRESS_PX_30 +#define COMPAND_COMPRESS_PX_30_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_30_SHIFT 0U +/*! Register: isp_compand_compress_px_6 (0x00003258)*/ +/*! Slice: compand_compress_px_41:*/ +#define COMPAND_COMPRESS_PX_41 +#define COMPAND_COMPRESS_PX_41_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_41_SHIFT 25U +/*! Slice: compand_compress_px_40:*/ +#define COMPAND_COMPRESS_PX_40 +#define COMPAND_COMPRESS_PX_40_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_40_SHIFT 20U +/*! Slice: compand_compress_px_39:*/ +#define COMPAND_COMPRESS_PX_39 +#define COMPAND_COMPRESS_PX_39_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_39_SHIFT 15U +/*! Slice: compand_compress_px_38:*/ +#define COMPAND_COMPRESS_PX_38 +#define COMPAND_COMPRESS_PX_38_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_38_SHIFT 10U +/*! Slice: compand_compress_px_37:*/ +#define COMPAND_COMPRESS_PX_37 +#define COMPAND_COMPRESS_PX_37_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_37_SHIFT 5U +/*! Slice: compand_compress_px_36:*/ +#define COMPAND_COMPRESS_PX_36 +#define COMPAND_COMPRESS_PX_36_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_36_SHIFT 0U +/*! Register: isp_compand_compress_px_7 (0x0000325C)*/ +/*! Slice: compand_compress_px_47:*/ +#define COMPAND_COMPRESS_PX_47 +#define COMPAND_COMPRESS_PX_47_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_47_SHIFT 25U +/*! Slice: compand_compress_px_46:*/ +#define COMPAND_COMPRESS_PX_46 +#define COMPAND_COMPRESS_PX_46_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_46_SHIFT 20U +/*! Slice: compand_compress_px_45:*/ +#define COMPAND_COMPRESS_PX_45 +#define COMPAND_COMPRESS_PX_45_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_45_SHIFT 15U +/*! Slice: compand_compress_px_44:*/ +#define COMPAND_COMPRESS_PX_44 +#define COMPAND_COMPRESS_PX_44_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_44_SHIFT 10U +/*! Slice: compand_compress_px_43:*/ +#define COMPAND_COMPRESS_PX_43 +#define COMPAND_COMPRESS_PX_43_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_43_SHIFT 5U +/*! Slice: compand_compress_px_42:*/ +#define COMPAND_COMPRESS_PX_42 +#define COMPAND_COMPRESS_PX_42_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_42_SHIFT 0U +/*! Register: isp_compand_compress_px_8 (0x00003260)*/ +/*! Slice: compand_compress_px_53:*/ +#define COMPAND_COMPRESS_PX_53 +#define COMPAND_COMPRESS_PX_53_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_53_SHIFT 25U +/*! Slice: compand_compress_px_52:*/ +#define COMPAND_COMPRESS_PX_52 +#define COMPAND_COMPRESS_PX_52_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_52_SHIFT 20U +/*! Slice: compand_compress_px_51:*/ +#define COMPAND_COMPRESS_PX_51 +#define COMPAND_COMPRESS_PX_51_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_51_SHIFT 15U +/*! Slice: compand_compress_px_50:*/ +#define COMPAND_COMPRESS_PX_50 +#define COMPAND_COMPRESS_PX_50_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_50_SHIFT 10U +/*! Slice: compand_compress_px_49:*/ +#define COMPAND_COMPRESS_PX_49 +#define COMPAND_COMPRESS_PX_49_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_49_SHIFT 5U +/*! Slice: compand_compress_px_48:*/ +#define COMPAND_COMPRESS_PX_48 +#define COMPAND_COMPRESS_PX_48_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_48_SHIFT 0U +/*! Register: isp_compand_compress_px_9 (0x00003264)*/ +/*! Slice: compand_compress_px_59:*/ +#define COMPAND_COMPRESS_PX_59 +#define COMPAND_COMPRESS_PX_59_MASK 0x3E000000U +#define COMPAND_COMPRESS_PX_59_SHIFT 25U +/*! Slice: compand_compress_px_58:*/ +#define COMPAND_COMPRESS_PX_58 +#define COMPAND_COMPRESS_PX_58_MASK 0x01F00000U +#define COMPAND_COMPRESS_PX_58_SHIFT 20U +/*! Slice: compand_compress_px_57:*/ +#define COMPAND_COMPRESS_PX_57 +#define COMPAND_COMPRESS_PX_57_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_57_SHIFT 15U +/*! Slice: compand_compress_px_56:*/ +#define COMPAND_COMPRESS_PX_56 +#define COMPAND_COMPRESS_PX_56_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_56_SHIFT 10U +/*! Slice: compand_compress_px_55:*/ +#define COMPAND_COMPRESS_PX_55 +#define COMPAND_COMPRESS_PX_55_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_55_SHIFT 5U +/*! Slice: compand_compress_px_54:*/ +#define COMPAND_COMPRESS_PX_54 +#define COMPAND_COMPRESS_PX_54_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_54_SHIFT 0U +/*! Register: isp_compand_compress_px_10 (0x00003268)*/ +/*! Slice: compand_compress_px_63:*/ +#define COMPAND_COMPRESS_PX_63 +#define COMPAND_COMPRESS_PX_63_MASK 0x000F8000U +#define COMPAND_COMPRESS_PX_63_SHIFT 15U +/*! Slice: compand_compress_px_62:*/ +#define COMPAND_COMPRESS_PX_62 +#define COMPAND_COMPRESS_PX_62_MASK 0x00007C00U +#define COMPAND_COMPRESS_PX_62_SHIFT 10U +/*! Slice: compand_compress_px_61:*/ +#define COMPAND_COMPRESS_PX_61 +#define COMPAND_COMPRESS_PX_61_MASK 0x000003E0U +#define COMPAND_COMPRESS_PX_61_SHIFT 5U +/*! Slice: compand_compress_px_60:*/ +#define COMPAND_COMPRESS_PX_60 +#define COMPAND_COMPRESS_PX_60_MASK 0x0000001FU +#define COMPAND_COMPRESS_PX_60_SHIFT 0U +/*! Register: isp_compand_expand_y_addr (0x0000326C)*/ +/*! Slice: compand_expand_y_addr:*/ +#define COMPAND_EXPAND_Y_ADDR +#define COMPAND_EXPAND_Y_ADDR_MASK 0xFFFFFFFFU +#define COMPAND_EXPAND_Y_ADDR_SHIFT 0U +/*! Register: isp_compand_expand_y_write_data (0x00003270)*/ +/*! Slice: compand_expand_y_write_data:*/ +#define COMPAND_EXPAND_Y_WRITE_DATA +#define COMPAND_EXPAND_Y_WRITE_DATA_MASK 0x000FFFFFU +#define COMPAND_EXPAND_Y_WRITE_DATA_SHIFT 0U +/*! Register: isp_compand_compress_y_addr (0x00003274)*/ +/*! Slice: compand_compress_y_addr:*/ +#define COMPAND_COMPRESS_Y_ADDR +#define COMPAND_COMPRESS_Y_ADDR_MASK 0xFFFFFFFFU +#define COMPAND_COMPRESS_Y_ADDR_SHIFT 0U +/*! Register: isp_compand_compress_y_write_data (0x00003278)*/ +/*! Slice: compand_compress_y_write_data:*/ +#define COMPAND_COMPRESS_Y_WRITE_DATA +#define COMPAND_COMPRESS_Y_WRITE_DATA_MASK 0x0000FFFFU +#define COMPAND_COMPRESS_Y_WRITE_DATA_SHIFT 0U +/*! Register: isp_compand_expand_x_addr (0x0000327C)*/ +/*! Slice: compand_expand_x_addr:*/ +#define COMPAND_EXPAND_X_ADDR +#define COMPAND_EXPAND_X_ADDR_MASK 0xFFFFFFFFU +#define COMPAND_EXPAND_X_ADDR_SHIFT 0U +/*! Register: isp_compand_expand_x_write_data (0x00003280)*/ +/*! Slice: compand_expand_x_write_data:*/ +#define COMPAND_EXPAND_X_WRITE_DATA +#define COMPAND_EXPAND_X_WRITE_DATA_MASK 0x000FFFFFU +#define COMPAND_EXPAND_X_WRITE_DATA_SHIFT 0U +/*! Register: isp_compand_compress_x_addr (0x00003284)*/ +/*! Slice: compand_compress_x_addr:*/ +#define COMPAND_COMPRESS_X_ADDR +#define COMPAND_COMPRESS_X_ADDR_MASK 0xFFFFFFFFU +#define COMPAND_COMPRESS_X_ADDR_SHIFT 0U +/*! Register: isp_compand_compress_x_write_data (0x00003288)*/ +/*! Slice: compand_compress_x_write_data:*/ +#define COMPAND_COMPRESS_X_WRITE_DATA +#define COMPAND_COMPRESS_X_WRITE_DATA_MASK 0x000FFFFFU +#define COMPAND_COMPRESS_X_WRITE_DATA_SHIFT 0U +/*! Register: isp_wdr3_ctrl (0x00003500)*/ +/*! Slice: wdr3_dummmy_blk:*/ +#define WDR3_DUMMY_BLK +#define WDR3_DUMMY_BLK_MASK 0xffff0000U +#define WDR3_DUMMY_BLK_SHIFT 16U +/*! Register: isp_wdr3_ctrl (0x00003500)*/ +/*! Slice: wdr3_dummy_blk_en:*/ +#define WDR3_DUMMY_BLK_EN +#define WDR3_DUMMY_BLK_EN_MASK 0x00008000U +#define WDR3_DUMMY_BLK_EN_SHIFT 15U +/*! Register: isp_wdr3_ctrl (0x00003500)*/ +/*! Slice: wdr3_interrupt_en:*/ +#define WDR3_INTERRUPT_EN +#define WDR3_INTERRUPT_EN_MASK 0x00000200U +#define WDR3_INTERRUPT_EN_SHIFT 9U +/*! Slice: wdr3_soft_reset_flag:*/ +#define WDR3_SOFT_RESET_FLAG +#define WDR3_SOFT_RESET_FLAG_MASK 0x00000002U +#define WDR3_SOFT_RESET_FLAG_SHIFT 1U +/*! Slice: wdr3_enable:*/ +#define WDR3_ENABLE +#define WDR3_ENABLE_MASK 0x00000001U +#define WDR3_ENABLE_SHIFT 0U +/*! Register: isp_wdr3_shift (0x00003504)*/ +/*! Slice: wdr3_gain_shift_bit:*/ +#define WDR3_GAIN_SHIFT_BIT +#define WDR3_GAIN_SHIFT_BIT_MASK 0x00FC0000U +#define WDR3_GAIN_SHIFT_BIT_SHIFT 18U +/*! Slice: wdr3_normalize_shift_bit:*/ +#define WDR3_NORMALIZE_SHIFT_BIT +#define WDR3_NORMALIZE_SHIFT_BIT_MASK 0x0003F000U +#define WDR3_NORMALIZE_SHIFT_BIT_SHIFT 12U +/*! Slice: wdr3_output_shift_bit:*/ +#define WDR3_OUTPUT_SHIFT_BIT +#define WDR3_OUTPUT_SHIFT_BIT_MASK 0x00000FC0U +#define WDR3_OUTPUT_SHIFT_BIT_SHIFT 6U +/*! Slice: wdr3_pixel_shift_bit:*/ +#define WDR3_PIXEL_SHIFT_BIT +#define WDR3_PIXEL_SHIFT_BIT_MASK 0x0000003FU +#define WDR3_PIXEL_SHIFT_BIT_SHIFT 0U +/*! Register: isp_wdr3_block_size (0x00003508)*/ +/*! Slice: wdr3_block_height:*/ +#define WDR3_BLOCK_HEIGHT +#define WDR3_BLOCK_HEIGHT_MASK 0x0003FE00U +#define WDR3_BLOCK_HEIGHT_SHIFT 9U +/*! Slice: wdr3_block_width:*/ +#define WDR3_BLOCK_WIDTH +#define WDR3_BLOCK_WIDTH_MASK 0x000001FFU +#define WDR3_BLOCK_WIDTH_SHIFT 0U +/*! Register: isp_wdr3_block_area_factor (0x0000350C)*/ +/*! Slice: wdr3_block_area_inverse:*/ +#define WDR3_BLOCK_AREA_INVERSE +#define WDR3_BLOCK_AREA_INVERSE_MASK 0x000FFFFFU +#define WDR3_BLOCK_AREA_INVERSE_SHIFT 0U +/*! Register: isp_wdr3_value_weight (0x00003510)*/ +/*! Slice: wdr3_value_weight_3:*/ +#define WDR3_VALUE_WEIGHT_3 +#define WDR3_VALUE_WEIGHT_3_MASK 0x000F8000U +#define WDR3_VALUE_WEIGHT_3_SHIFT 15U +/*! Slice: wdr3_value_weight_2:*/ +#define WDR3_VALUE_WEIGHT_2 +#define WDR3_VALUE_WEIGHT_2_MASK 0x00007C00U +#define WDR3_VALUE_WEIGHT_2_SHIFT 10U +/*! Slice: wdr3_value_weight_1:*/ +#define WDR3_VALUE_WEIGHT_1 +#define WDR3_VALUE_WEIGHT_1_MASK 0x000003E0U +#define WDR3_VALUE_WEIGHT_1_SHIFT 5U +/*! Slice: wdr3_value_weight_0:*/ +#define WDR3_VALUE_WEIGHT_0 +#define WDR3_VALUE_WEIGHT_0_MASK 0x0000001FU +#define WDR3_VALUE_WEIGHT_0_SHIFT 0U +/*! Register: isp_wdr3_strength (0x00003514)*/ +/*! Slice: wdr3_total_strength:*/ +#define WDR3_TOTAL_STRENGTH +#define WDR3_TOTAL_STRENGTH_MASK 0xFF000000U +#define WDR3_TOTAL_STRENGTH_SHIFT 24U +/*! Slice: wdr3_local_strength:*/ +#define WDR3_LOCAL_STRENGTH +#define WDR3_LOCAL_STRENGTH_MASK 0x00FF0000U +#define WDR3_LOCAL_STRENGTH_SHIFT 16U +/*! Slice: wdr3_global_strength:*/ +#define WDR3_GLOBAL_STRENGTH +#define WDR3_GLOBAL_STRENGTH_MASK 0x0000FF00U +#define WDR3_GLOBAL_STRENGTH_SHIFT 8U +/*! Slice: wdr3_maximum_gain:*/ +#define WDR3_MAXIMUM_GAIN +#define WDR3_MAXIMUM_GAIN_MASK 0x000000FFU +#define WDR3_MAXIMUM_GAIN_SHIFT 0U +/*! Register: isp_wdr3_pixel_slope (0x00003518)*/ +/*! Slice: wdr3_pixel_merge_slope:*/ +#define WDR3_PIXEL_MERGE_SLOPE +#define WDR3_PIXEL_MERGE_SLOPE_MASK 0xFF000000U +#define WDR3_PIXEL_MERGE_SLOPE_SHIFT 24U +/*! Slice: wdr3_pixel_merge_base:*/ +#define WDR3_PIXEL_MERGE_BASE +#define WDR3_PIXEL_MERGE_BASE_MASK 0x00FF0000U +#define WDR3_PIXEL_MERGE_BASE_SHIFT 16U +/*! Slice: wdr3_pixel_adjust_slope:*/ +#define WDR3_PIXEL_ADJUST_SLOPE +#define WDR3_PIXEL_ADJUST_SLOPE_MASK 0x0000FF00U +#define WDR3_PIXEL_ADJUST_SLOPE_SHIFT 8U +/*! Slice: wdr3_pixel_adjust_base:*/ +#define WDR3_PIXEL_ADJUST_BASE +#define WDR3_PIXEL_ADJUST_BASE_MASK 0x000000FFU +#define WDR3_PIXEL_ADJUST_BASE_SHIFT 0U +/*! Register: isp_wdr3_entropy_slope (0x0000351C)*/ +/*! Slice: wdr3_entropy_slope:*/ +#define WDR3_ENTROPY_SLOPE +#define WDR3_ENTROPY_SLOPE_MASK 0x000FFC00U +#define WDR3_ENTROPY_SLOPE_SHIFT 10U +/*! Slice: wdr3_entropy_base:*/ +#define WDR3_ENTROPY_BASE +#define WDR3_ENTROPY_BASE_MASK 0x000003FFU +#define WDR3_ENTROPY_BASE_SHIFT 0U +/*! Register: isp_wdr3_sigma_width (0x00003520)*/ +/*! Slice: wdr3_biliteral_width_sigma:*/ +#define WDR3_BILITERAL_WIDTH_SIGMA +#define WDR3_BILITERAL_WIDTH_SIGMA_MASK 0x000FFFFFU +#define WDR3_BILITERAL_WIDTH_SIGMA_SHIFT 0U +/*! Register: isp_wdr3_sigma_height (0x00003524)*/ +/*! Slice: wdr3_biliteral_height_sigma:*/ +#define WDR3_BILITERAL_HEIGHT_SIGMA +#define WDR3_BILITERAL_HEIGHT_SIGMA_MASK 0x000FFFFFU +#define WDR3_BILITERAL_HEIGHT_SIGMA_SHIFT 0U +/*! Register: isp_wdr3_sigma_value (0x00003528)*/ +/*! Slice: wdr3_biliteral_value_sigma:*/ +#define WDR3_BILITERAL_VALUE_SIGMA +#define WDR3_BILITERAL_VALUE_SIGMA_MASK 0x000FFFFFU +#define WDR3_BILITERAL_VALUE_SIGMA_SHIFT 0U +/*! Register: isp_wdr3_block_flag_width (0x0000352C)*/ +/*! Slice: wdr3_block_col_flag:*/ +#define WDR3_BLOCK_COL_FLAG +#define WDR3_BLOCK_COL_FLAG_MASK 0xFFFFFFFFU +#define WDR3_BLOCK_COL_FLAG_SHIFT 0U +/*! Register: isp_wdr3_block_flag_height (0x00003530)*/ +/*! Slice: wdr3_block_row_flag:*/ +#define WDR3_BLOCK_ROW_FLAG +#define WDR3_BLOCK_ROW_FLAG_MASK 0xFFFFFFFFU +#define WDR3_BLOCK_ROW_FLAG_SHIFT 0U +/*! Register: isp_wdr3_frame_average (0x00003534)*/ +/*! Slice: wdr3_frame_average:*/ +#define WDR3_FRAME_AVERAGE +#define WDR3_FRAME_AVERAGE_MASK 0xFFFFFFFFU +#define WDR3_FRAME_AVERAGE_SHIFT 0U +/*! Register: isp_wdr3_frame_std (0x00003538)*/ +/*! Slice: wdr3_frame_std:*/ +#define WDR3_FRAME_STD +#define WDR3_FRAME_STD_MASK 0xFFFFFFFFU +#define WDR3_FRAME_STD_SHIFT 0U +/*! Register: isp_wdr3_histogram_0 (0x0000353C)*/ +/*! Slice: wdr3_histogram_curve0:*/ +#define WDR3_HISTOGRAM_CURVE0 +#define WDR3_HISTOGRAM_CURVE0_MASK 0x3FF00000U +#define WDR3_HISTOGRAM_CURVE0_SHIFT 20U +/*! Slice: wdr3_histogram_curve1:*/ +#define WDR3_HISTOGRAM_CURVE1 +#define WDR3_HISTOGRAM_CURVE1_MASK 0x000FFC00U +#define WDR3_HISTOGRAM_CURVE1_SHIFT 10U +/*! Slice: wdr3_histogram_curve2:*/ +#define WDR3_HISTOGRAM_CURVE2 +#define WDR3_HISTOGRAM_CURVE2_MASK 0x000003FFU +#define WDR3_HISTOGRAM_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_entropy_0 (0x00003550)*/ +/*! Slice: wdr3_entropy_convert0:*/ +#define WDR3_ENTROPY_CONVERT0 +#define WDR3_ENTROPY_CONVERT0_MASK 0x07FC0000U +#define WDR3_ENTROPY_CONVERT0_SHIFT 18U +/*! Slice: wdr3_entropy_convert1:*/ +#define WDR3_ENTROPY_CONVERT1 +#define WDR3_ENTROPY_CONVERT1_MASK 0x0003FE00U +#define WDR3_ENTROPY_CONVERT1_SHIFT 9U +/*! Slice: wdr3_entropy_convert2:*/ +#define WDR3_ENTROPY_CONVERT2 +#define WDR3_ENTROPY_CONVERT2_MASK 0x000001FFU +#define WDR3_ENTROPY_CONVERT2_SHIFT 0U +/*! Register: isp_wdr3_gamma_pre_0 (0x00003564)*/ +/*! Slice: wdr3_gamma_pre_curve0:*/ +#define WDR3_GAMMA_PRE_CURVE0 +#define WDR3_GAMMA_PRE_CURVE0_MASK 0x3FF00000U +#define WDR3_GAMMA_PRE_CURVE0_SHIFT 20U +/*! Slice: wdr3_gamma_pre_curve1:*/ +#define WDR3_GAMMA_PRE_CURVE1 +#define WDR3_GAMMA_PRE_CURVE1_MASK 0x000FFC00U +#define WDR3_GAMMA_PRE_CURVE1_SHIFT 10U +/*! Slice: wdr3_gamma_pre_curve2:*/ +#define WDR3_GAMMA_PRE_CURVE2 +#define WDR3_GAMMA_PRE_CURVE2_MASK 0x000003FFU +#define WDR3_GAMMA_PRE_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_gamma_up_0 (0x00003578)*/ +/*! Slice: wdr3_gamma_up_curve0:*/ +#define WDR3_GAMMA_UP_CURVE0 +#define WDR3_GAMMA_UP_CURVE0_MASK 0x3FF00000U +#define WDR3_GAMMA_UP_CURVE0_SHIFT 20U +/*! Slice: wdr3_gamma_up_curve1:*/ +#define WDR3_GAMMA_UP_CURVE1 +#define WDR3_GAMMA_UP_CURVE1_MASK 0x000FFC00U +#define WDR3_GAMMA_UP_CURVE1_SHIFT 10U +/*! Slice: wdr3_gamma_up_curve2:*/ +#define WDR3_GAMMA_UP_CURVE2 +#define WDR3_GAMMA_UP_CURVE2_MASK 0x000003FFU +#define WDR3_GAMMA_UP_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_gamma_down_0 (0x0000358C)*/ +/*! Slice: wdr3_gamma_down_curve0:*/ +#define WDR3_GAMMA_DOWN_CURVE0 +#define WDR3_GAMMA_DOWN_CURVE0_MASK 0x3FF00000U +#define WDR3_GAMMA_DOWN_CURVE0_SHIFT 20U +/*! Slice: wdr3_gamma_down_curve1:*/ +#define WDR3_GAMMA_DOWN_CURVE1 +#define WDR3_GAMMA_DOWN_CURVE1_MASK 0x000FFC00U +#define WDR3_GAMMA_DOWN_CURVE1_SHIFT 10U +/*! Slice: wdr3_gamma_down_curve2:*/ +#define WDR3_GAMMA_DOWN_CURVE2 +#define WDR3_GAMMA_DOWN_CURVE2_MASK 0x000003FFU +#define WDR3_GAMMA_DOWN_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_distance_weight_0 (0x000035A0)*/ +/*! Slice: wdr3_distance_weight_curve0:*/ +#define WDR3_DISTANCE_WEIGHT_CURVE0 +#define WDR3_DISTANCE_WEIGHT_CURVE0_MASK 0x001FC000U +#define WDR3_DISTANCE_WEIGHT_CURVE0_SHIFT 14U +/*! Slice: wdr3_distance_weight_curve1:*/ +#define WDR3_DISTANCE_WEIGHT_CURVE1 +#define WDR3_DISTANCE_WEIGHT_CURVE1_MASK 0x00003F80U +#define WDR3_DISTANCE_WEIGHT_CURVE1_SHIFT 7U +/*! Slice: wdr3_distance_weight_curve2:*/ +#define WDR3_DISTANCE_WEIGHT_CURVE2 +#define WDR3_DISTANCE_WEIGHT_CURVE2_MASK 0x0000007FU +#define WDR3_DISTANCE_WEIGHT_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_difference_weight_0 (0x000035B4)*/ +/*! Slice: wdr3_difference_weight_curve0:*/ +#define WDR3_DIFFERENCE_WEIGHT_CURVE0 +#define WDR3_DIFFERENCE_WEIGHT_CURVE0_MASK 0x001FC000U +#define WDR3_DIFFERENCE_WEIGHT_CURVE0_SHIFT 14U +/*! Slice: wdr3_difference_weight_curve1:*/ +#define WDR3_DIFFERENCE_WEIGHT_CURVE1 +#define WDR3_DIFFERENCE_WEIGHT_CURVE1_MASK 0x00003F80U +#define WDR3_DIFFERENCE_WEIGHT_CURVE1_SHIFT 7U +/*! Slice: wdr3_difference_weight_curve2:*/ +#define WDR3_DIFFERENCE_WEIGHT_CURVE2 +#define WDR3_DIFFERENCE_WEIGHT_CURVE2_MASK 0x0000007FU +#define WDR3_DIFFERENCE_WEIGHT_CURVE2_SHIFT 0U +/*! Register: isp_wdr3_invert_curve_0 (0x000035C8)*/ +/*! Slice: wdr3_global_curve_invert0:*/ +#define WDR3_GLOBAL_CURVE_INVERT0 +#define WDR3_GLOBAL_CURVE_INVERT0_MASK 0x00FFF000U +#define WDR3_GLOBAL_CURVE_INVERT0_SHIFT 12U +/*! Slice: wdr3_global_curve_invert1:*/ +#define WDR3_GLOBAL_CURVE_INVERT1 +#define WDR3_GLOBAL_CURVE_INVERT1_MASK 0x00000FFFU +#define WDR3_GLOBAL_CURVE_INVERT1_SHIFT 0U +/*! Register: isp_wdr3_invert_curve_1 (0x000035CC)*/ +/*! Slice: wdr3_global_curve_invert2:*/ +#define WDR3_GLOBAL_CURVE_INVERT2 +#define WDR3_GLOBAL_CURVE_INVERT2_MASK 0x00FFF000U +#define WDR3_GLOBAL_CURVE_INVERT2_SHIFT 12U +/*! Register: isp_wdr3_invert_linear_0 (0x000035E4)*/ +/*! Slice: wdr3_linear_curve_invert0:*/ +#define WDR3_LINEAR_CURVE_INVERT0 +#define WDR3_LINEAR_CURVE_INVERT0_MASK 0x00FFF000U +#define WDR3_LINEAR_CURVE_INVERT0_SHIFT 12U +/*! Slice: wdr3_linear_curve_invert1:*/ +#define WDR3_LINEAR_CURVE_INVERT1 +#define WDR3_LINEAR_CURVE_INVERT1_MASK 0x00000FFFU +#define WDR3_LINEAR_CURVE_INVERT1_SHIFT 0U +/*! Register: isp_wdr3_invert_linear_1 (0x000035E8)*/ +/*! Slice: wdr3_linear_curve_invert2:*/ +#define WDR3_LINEAR_CURVE_INVERT2 +#define WDR3_LINEAR_CURVE_INVERT2_MASK 0x00FFF000U +#define WDR3_LINEAR_CURVE_INVERT2_SHIFT 12U +/*! Register: isp_wdr3_shift_0 (0x00003600)*/ +/*! Slice: wdr3_histogram_shift0:*/ +#define WDR3_HISTOGRAM_SHIFT0 +#define WDR3_HISTOGRAM_SHIFT0_MASK 0xF0000000U +#define WDR3_HISTOGRAM_SHIFT0_SHIFT 28U +/*! Slice: wdr3_histogram_shift1:*/ +#define WDR3_HISTOGRAM_SHIFT1 +#define WDR3_HISTOGRAM_SHIFT1_MASK 0x0F000000U +#define WDR3_HISTOGRAM_SHIFT1_SHIFT 24U +/*! Slice: wdr3_histogram_shift2:*/ +#define WDR3_HISTOGRAM_SHIFT2 +#define WDR3_HISTOGRAM_SHIFT2_MASK 0x00F00000U +#define WDR3_HISTOGRAM_SHIFT2_SHIFT 20U +/*! Slice: wdr3_histogram_shift3:*/ +#define WDR3_HISTOGRAM_SHIFT3 +#define WDR3_HISTOGRAM_SHIFT3_MASK 0x000F0000U +#define WDR3_HISTOGRAM_SHIFT3_SHIFT 16U +/*! Slice: wdr3_histogram_shift4:*/ +#define WDR3_HISTOGRAM_SHIFT4 +#define WDR3_HISTOGRAM_SHIFT4_MASK 0x0000F000U +#define WDR3_HISTOGRAM_SHIFT4_SHIFT 12U +/*! Slice: wdr3_histogram_shift5:*/ +#define WDR3_HISTOGRAM_SHIFT5 +#define WDR3_HISTOGRAM_SHIFT5_MASK 0x00000F00U +#define WDR3_HISTOGRAM_SHIFT5_SHIFT 8U +/*! Slice: wdr3_histogram_shift6:*/ +#define WDR3_HISTOGRAM_SHIFT6 +#define WDR3_HISTOGRAM_SHIFT6_MASK 0x000000F0U +#define WDR3_HISTOGRAM_SHIFT6_SHIFT 4U +/*! Slice: wdr3_histogram_shift7:*/ +#define WDR3_HISTOGRAM_SHIFT7 +#define WDR3_HISTOGRAM_SHIFT7_MASK 0x0000000FU +#define WDR3_HISTOGRAM_SHIFT7_SHIFT 0U +/*! Register: isp_wdr3_shift_1 (0x00003604)*/ +/*! Slice: wdr3_histogram_shift8:*/ +#define WDR3_HISTOGRAM_SHIFT8 +#define WDR3_HISTOGRAM_SHIFT8_MASK 0x00F00000U +#define WDR3_HISTOGRAM_SHIFT8_SHIFT 20U +/*! Slice: wdr3_histogram_shift9:*/ +#define WDR3_HISTOGRAM_SHIFT9 +#define WDR3_HISTOGRAM_SHIFT9_MASK 0x000F0000U +#define WDR3_HISTOGRAM_SHIFT9_SHIFT 16U +/*! Slice: wdr3_histogram_shift10:*/ +#define WDR3_HISTOGRAM_SHIFT10 +#define WDR3_HISTOGRAM_SHIFT10_MASK 0x0000F000U +#define WDR3_HISTOGRAM_SHIFT10_SHIFT 12U +/*! Slice: wdr3_histogram_shift11:*/ +#define WDR3_HISTOGRAM_SHIFT11 +#define WDR3_HISTOGRAM_SHIFT11_MASK 0x00000F00U +#define WDR3_HISTOGRAM_SHIFT11_SHIFT 8U +/*! Slice: wdr3_histogram_shift12:*/ +#define WDR3_HISTOGRAM_SHIFT12 +#define WDR3_HISTOGRAM_SHIFT12_MASK 0x000000F0U +#define WDR3_HISTOGRAM_SHIFT12_SHIFT 4U +/*! Slice: wdr3_histogram_shift13:*/ +#define WDR3_HISTOGRAM_SHIFT13 +#define WDR3_HISTOGRAM_SHIFT13_MASK 0x0000000FU +#define WDR3_HISTOGRAM_SHIFT13_SHIFT 0U +/*! Register: isp_wdr3_strength_shd (0x00003608)*/ +/*! Slice: wdr3_total_strength_shd:*/ +#define WDR3_TOTAL_STRENGTH_SHD +#define WDR3_TOTAL_STRENGTH_SHD_MASK 0xFF000000U +#define WDR3_TOTAL_STRENGTH_SHD_SHIFT 24U +/*! Slice: wdr3_local_strength_shd:*/ +#define WDR3_LOCAL_STRENGTH_SHD +#define WDR3_LOCAL_STRENGTH_SHD_MASK 0x00FF0000U +#define WDR3_LOCAL_STRENGTH_SHD_SHIFT 16U +/*! Slice: wdr3_global_strength_shd:*/ +#define WDR3_GLOBAL_STRENGTH_SHD +#define WDR3_GLOBAL_STRENGTH_SHD_MASK 0x0000FF00U +#define WDR3_GLOBAL_STRENGTH_SHD_SHIFT 8U +/*! Slice: wdr3_maximum_gain_shd:*/ +#define WDR3_MAXIMUM_GAIN_SHD +#define WDR3_MAXIMUM_GAIN_SHD_MASK 0x000000FFU +#define WDR3_MAXIMUM_GAIN_SHD_SHIFT 0U +/*! Register: isp_wdr3_pixel_slope_shd (0x0000360C)*/ +/*! Slice: wdr3_pixel_merge_slope_shd:*/ +#define WDR3_PIXEL_MERGE_SLOPE_SHD +#define WDR3_PIXEL_MERGE_SLOPE_SHD_MASK 0xFF000000U +#define WDR3_PIXEL_MERGE_SLOPE_SHD_SHIFT 24U +/*! Slice: wdr3_pixel_merge_base_shd:*/ +#define WDR3_PIXEL_MERGE_BASE_SHD +#define WDR3_PIXEL_MERGE_BASE_SHD_MASK 0x00FF0000U +#define WDR3_PIXEL_MERGE_BASE_SHD_SHIFT 16U +/*! Slice: wdr3_pixel_adjust_slope_shd:*/ +#define WDR3_PIXEL_ADJUST_SLOPE_SHD +#define WDR3_PIXEL_ADJUST_SLOPE_SHD_MASK 0x0000FF00U +#define WDR3_PIXEL_ADJUST_SLOPE_SHD_SHIFT 8U +/*! Slice: wdr3_pixel_adjust_base_shd:*/ +#define WDR3_PIXEL_ADJUST_BASE_SHD +#define WDR3_PIXEL_ADJUST_BASE_SHD_MASK 0x000000FFU +#define WDR3_PIXEL_ADJUST_BASE_SHD_SHIFT 0U +/*! Register: isp_wdr3_entropy_slope_shd (0x00003610)*/ +/*! Slice: wdr3_entropy_slope_shd:*/ +#define WDR3_ENTROPY_SLOPE_SHD +#define WDR3_ENTROPY_SLOPE_SHD_MASK 0x000FFC00U +#define WDR3_ENTROPY_SLOPE_SHD_SHIFT 10U +/*! Slice: wdr3_entropy_base_shd:*/ +#define WDR3_ENTROPY_BASE_SHD +#define WDR3_ENTROPY_BASE_SHD_MASK 0x000003FFU +#define WDR3_ENTROPY_BASE_SHD_SHIFT 0U +/* TPG */ +/*! Register: isp_tpg_ctrl (0x00000700)*/ +/*! Slice: tpg_resolution:*/ +#define TPG_RESOLUTION +#define TPG_RESOLUTION_MASK 0x00000C00U +#define TPG_RESOLUTION_SHIFT 10U +/*! Slice: tpg_max_sync:*/ +#define TPG_MAX_SYNC +#define TPG_MAX_SYNC_MASK 0x00000200U +#define TPG_MAX_SYNC_SHIFT 9U +/*! Slice: tpg_def_sync:*/ +#define TPG_DEF_SYNC +#define TPG_DEF_SYNC_MASK 0x00000100U +#define TPG_DEF_SYNC_SHIFT 8U +/*! Slice: tpg_color_depth:*/ +#define TPG_COLOR_DEPTH +#define TPG_COLOR_DEPTH_MASK 0x000000C0U +#define TPG_COLOR_DEPTH_SHIFT 6U +/*! Slice: tpg_cfa_pat:*/ +#define TPG_CFA_PAT +#define TPG_CFA_PAT_MASK 0x00000030U +#define TPG_CFA_PAT_SHIFT 4U +/*! Slice: tpg_img_num:*/ +#define TPG_IMG_NUM +#define TPG_IMG_NUM_MASK 0x0000000EU +#define TPG_IMG_NUM_SHIFT 1U +/*! Slice: tpg_frame_num:*/ +#define TPG_FRAME_NUM +#define TPG_FRAME_NUM_MASK 0xFFFF0000U +#define TPG_FRAME_NUM_SHIFT 16U +/*! Slice: tpg_enable:*/ +#define TPG_ENABLE +#define TPG_ENABLE_MASK 0x00000001U +#define TPG_ENABLE_SHIFT 0U +/*! Register: isp_tpg_total_in (0x00000704)*/ +/*! Slice: tpg_htotal_in:*/ +#define TPG_HTOTAL_IN +#define TPG_HTOTAL_IN_MASK 0x0FFFC000U +#define TPG_HTOTAL_IN_SHIFT 14U +/*! Slice: tpg_vtotal_in:*/ +#define TPG_VTOTAL_IN +#define TPG_VTOTAL_IN_MASK 0x00003FFFU +#define TPG_VTOTAL_IN_SHIFT 0U +/*! Register: isp_tpg_act_in (0x00000708)*/ +/*! Slice: tpg_hact_in:*/ +#define TPG_HACT_IN +#define TPG_HACT_IN_MASK 0x0FFFC000U +#define TPG_HACT_IN_SHIFT 14U +/*! Slice: tpg_vact_in:*/ +#define TPG_VACT_IN +#define TPG_VACT_IN_MASK 0x00003FFFU +#define TPG_VACT_IN_SHIFT 0U +/*! Register: isp_tpg_fp_in (0x0000070C)*/ +/*! Slice: tpg_fp_h_in:*/ +#define TPG_FP_H_IN +#define TPG_FP_H_IN_MASK 0x0FFFC000U +#define TPG_FP_H_IN_SHIFT 14U +/*! Slice: tpg_fp_v_in:*/ +#define TPG_FP_V_IN +#define TPG_FP_V_IN_MASK 0x00003FFFU +#define TPG_FP_V_IN_SHIFT 0U +/*! Register: isp_tpg_bp_in (0x00000710)*/ +/*! Slice: tpg_bp_h_in:*/ +#define TPG_BP_H_IN +#define TPG_BP_H_IN_MASK 0x0FFFC000U +#define TPG_BP_H_IN_SHIFT 14U +/*! Slice: tpg_bp_v_in:*/ +#define TPG_BP_V_IN +#define TPG_BP_V_IN_MASK 0x00003FFFU +#define TPG_BP_V_IN_SHIFT 0U +/*! Register: isp_tpg_w_in (0x00000714)*/ +/*! Slice: tpg_hs_w_in:*/ +#define TPG_HS_W_IN +#define TPG_HS_W_IN_MASK 0x0FFFC000U +#define TPG_HS_W_IN_SHIFT 14U +/*! Slice: tpg_vs_w_in:*/ +#define TPG_VS_W_IN +#define TPG_VS_W_IN_MASK 0x00003FFFU +#define TPG_VS_W_IN_SHIFT 0U +/*! Register: isp_tpg_gap_in (0x00000718)*/ +/*! Slice: tpg_pix_gap_in:*/ +#define TPG_PIX_GAP_IN +#define TPG_PIX_GAP_IN_MASK 0x0FFFC000U +#define TPG_PIX_GAP_IN_SHIFT 14U +/*! Slice: tpg_line_gap_in:*/ +#define TPG_LINE_GAP_IN +#define TPG_LINE_GAP_IN_MASK 0x00003FFFU +#define TPG_LINE_GAP_IN_SHIFT 0U +/*! Register: isp_tpg_gap_std_in (0x0000071C)*/ +/*! Slice: tpg_pix_gap_std_in:*/ +#define TPG_PIX_GAP_STD_IN +#define TPG_PIX_GAP_STD_IN_MASK 0x00003FFFU +#define TPG_PIX_GAP_STD_IN_SHIFT 0U +/*! Register: isp_tpg_random_seed (0x00000720)*/ +/*! Slice: tpg_random_seed:*/ +#define TPG_RANDOM_SEED +#define TPG_RANDOM_SEED_MASK 0xFFFFFFFFU +#define TPG_RANDOM_SEED_SHIFT 0U +/* MCM */ +/*! Register: mcm_ctrl (0x00001200)*/ +/*! Slice: MCM_SENSOR_MEM_BYPASS:*/ +#define MCM_SENSOR_MEM_BYPASS +#define MCM_SENSOR_MEM_BYPASS_MASK 0x00020000U +#define MCM_SENSOR_MEM_BYPASS_SHIFT 17U +/*! Slice: MCM_G2_WR1_FMT:*/ +#define MCM_G2_WR1_FMT +#define MCM_G2_WR1_FMT_MASK 0x0001C000U +#define MCM_G2_WR1_FMT_SHIFT 14U +/*! Slice: MCM_G2_WR0_FMT:*/ +#define MCM_G2_WR0_FMT +#define MCM_G2_WR0_FMT_MASK 0x00003800U +#define MCM_G2_WR0_FMT_SHIFT 11U +/*! Slice: MCM_WR1_FMT:*/ +#define MCM_WR1_FMT +#define MCM_WR1_FMT_MASK 0x00000700U +#define MCM_WR1_FMT_SHIFT 8U +/*! Slice: MCM_WR0_FMT:*/ +#define MCM_WR0_FMT +#define MCM_WR0_FMT_MASK 0x000000E0U +#define MCM_WR0_FMT_SHIFT 5U +/*! Slice: MCM_BYPASS_SWITCH:*/ +#define MCM_BYPASS_SWITCH +#define MCM_BYPASS_SWITCH_MASK 0x0000001EU +#define MCM_BYPASS_SWITCH_SHIFT 1U +/*! Slice: MCM_BYPASS_EN:*/ +#define MCM_BYPASS_EN +#define MCM_BYPASS_EN_MASK 0x00000001U +#define MCM_BYPASS_EN_SHIFT 0U +/*! Register: mcm_size0 (0x00001204)*/ +/*! Slice: MCM_HEIGHT0:*/ +#define MCM_HEIGHT0 +#define MCM_HEIGHT0_MASK 0x3FFF0000U +#define MCM_HEIGHT0_SHIFT 16U +/*! Slice: MCM_WIDTH0:*/ +#define MCM_WIDTH0 +#define MCM_WIDTH0_MASK 0x00003FFFU +#define MCM_WIDTH0_SHIFT 0U +/*! Register: mcm_size1 (0x00001208)*/ +/*! Slice: MCM_HEIGHT1:*/ +#define MCM_HEIGHT1 +#define MCM_HEIGHT1_MASK 0x3FFF0000U +#define MCM_HEIGHT1_SHIFT 16U +/*! Slice: MCM_WIDTH1:*/ +#define MCM_WIDTH1 +#define MCM_WIDTH1_MASK 0x00003FFFU +#define MCM_WIDTH1_SHIFT 0U +/*! Register: mcm_rd_cfg (0x00001280)*/ +/*! Slice: MCM_RD_FMT:*/ +#define MCM_RD_FMT +#define MCM_RD_FMT_MASK 0x00000007U +#define MCM_RD_FMT_SHIFT 0U +/*! Register: mcm_retiming0 (0x00001284)*/ +/*! Slice: MCM_VSYNC_BLANK:*/ +#define MCM_VSYNC_BLANK +#define MCM_VSYNC_BLANK_MASK 0xFFFFFF00U +#define MCM_VSYNC_BLANK_SHIFT 8U +/*! Slice: MCM_VSYNC_DURATION:*/ +#define MCM_VSYNC_DURATION +#define MCM_VSYNC_DURATION_MASK 0x000000FFU +#define MCM_VSYNC_DURATION_SHIFT 0U +/*! Register: mcm_retiming1 (0x00001288)*/ +/*! Slice: MCM_HSYNC_BLANK:*/ +#define MCM_HSYNC_BLANK +#define MCM_HSYNC_BLANK_MASK 0xFFFFFF00U +#define MCM_HSYNC_BLANK_SHIFT 8U +/*! Slice: MCM_HSYNC_PREAMPLE:*/ +#define MCM_HSYNC_PREAMPLE +#define MCM_HSYNC_PREAMPLE_MASK 0x000000FFU +#define MCM_HSYNC_PREAMPLE_SHIFT 0U +/*! Register: mcm_hsync_preample_ext (0x0000128c)*/ +/*! Slice: MCM_HSYNC_PREAMPLE_EXT:*/ +#define MCM_HSYNC_PREAMPLE_EXT +#define MCM_HSYNC_PREAMPLE_EXT_MASK 0x000FFFFFU +#define MCM_HSYNC_PREAMPLE_EXT_SHIFT 0U +/*! Register: mcm_wr_retiming0 (0x00001290)*/ +/*! Slice: MCM_WR_VSYNC_BLANK:*/ +#define MCM_WR_VSYNC_BLANK +#define MCM_WR_VSYNC_BLANK_MASK 0xFFFFFF00U +#define MCM_WR_VSYNC_BLANK_SHIFT 8U +/*! Slice: MCM_WR_VSYNC_DURATION:*/ +#define MCM_WR_VSYNC_DURATION +#define MCM_WR_VSYNC_DURATION_MASK 0x000000FFU +#define MCM_WR_VSYNC_DURATION_SHIFT 0U +/*! Register: mcm_wr_retiming1 (0x00001294)*/ +/*! Slice: MCM_WR_HSYNC_BLANK:*/ +#define MCM_WR_HSYNC_BLANK +#define MCM_WR_HSYNC_BLANK_MASK 0xFFFFFF00U +#define MCM_WR_HSYNC_BLANK_SHIFT 8U +/*! Slice: MCM_WR_HSYNC_PREAMPLE:*/ +#define MCM_WR_HSYNC_PREAMPLE +#define MCM_WR_HSYNC_PREAMPLE_MASK 0x000000FFU +#define MCM_WR_HSYNC_PREAMPLE_SHIFT 0U + +/*Stitching */ +/*!Register: isp_stitching_ctrl (0x00003300) */ +/*!Register: isp_stitching_ctrl (0x00003300) */ +/*!Slice: regs_inform_en */ +#define STITCHING_REGS_INFORM_EN +#define STITCHING_REGS_INFORM_EN_MASK 0x00400000U +#define STITCHING_REGS_INFORM_EN_SHIFT 22U +/*!Slice: vsync_pol */ +#define STITCHING_VSYNC_POL +#define STITCHING_VSYNC_POL_MASK 0x00200000U +#define STITCHING_VSYNC_POL_SHIFT 21U +/*!Slice: hsync_pol */ +#define STITCHING_HSYNC_POL +#define STITCHING_HSYNC_POL_MASK 0x00100000U +#define STITCHING_HSYNC_POL_SHIFT 20U +/*!Slice: awb_gain_enable */ +#define STITCHING_AWB_GAIN_ENABLE +#define STITCHING_AWB_GAIN_ENABLE_MASK 0x00080000U +#define STITCHING_AWB_GAIN_ENABLE_SHIFT 19U +/*!Slice: cfg_upd */ +#define STITCHING_CFG_UPD +#define STITCHING_CFG_UPD_MASK 0x00040000U +#define STITCHING_CFG_UPD_SHIFT 18U +/*!Slice: gen_cfg_upd */ +#define STITCHING_GEN_CFG_UPD +#define STITCHING_GEN_CFG_UPD_MASK 0x00020000U +#define STITCHING_GEN_CFG_UPD_SHIFT 17U +/*!Slice: gen_cfg_upd_fix */ +#define STITCHING_GEN_CFG_UPD_FIX +#define STITCHING_GEN_CFG_UPD_FIX_MASK 0x00010000U +#define STITCHING_GEN_CFG_UPD_FIX_SHIFT 16U +/*!Slice: bypass_select */ +#define STITCHING_BYPASS_SELECT +#define STITCHING_BYPASS_SELECT_MASK 0x00006000U +#define STITCHING_BYPASS_SELECT_SHIFT 13U +/*!Slice: linear_combine_enable */ +#define STITCHING_LINEAR_COMBINE_ENABLE +#define STITCHING_LINEAR_COMBINE_ENABLE_MASK 0x00001000U +#define STITCHING_LINEAR_COMBINE_ENABLE_SHIFT 12U +/*!Slice: base_frame_selection */ +#define STITCHING_BASE_FRAME_SELECTION +#define STITCHING_BASE_FRAME_SELECTION_MASK 0x00000800U +#define STITCHING_BASE_FRAME_SELECTION_SHIFT 11U +/*!Slice: combination_mode */ +#define STITCHING_COMBINATION_MODE +#define STITCHING_COMBINATION_MODE_MASK 0x00000600U +#define STITCHING_COMBINATION_MODE_SHIFT 9U +/*!Slice: channel_config_bit */ +#define STITCHING_CHANNEL_CONFIG_BIT +#define STITCHING_CHANNEL_CONFIG_BIT_MASK 0x00000100U +#define STITCHING_CHANNEL_CONFIG_BIT_SHIFT 8U +/*!Slice: B10_enable_bit */ +#define STITCHING_B10_ENABLE_BIT +#define STITCHING_B10_ENABLE_BIT_MASK 0x00000080U +#define STITCHING_B10_ENABLE_BIT_SHIFT 7U +/*!Slice: lin_enable_bit */ +#define STITCHING_LIN_ENABLE_BIT +#define STITCHING_LIN_ENABLE_BIT_MASK 0x00000040U +#define STITCHING_LIN_ENABLE_BIT_SHIFT 6U +/*!Slice: VS_enable_bit */ +#define STITCHING_VS_ENABLE_BIT +#define STITCHING_VS_ENABLE_BIT_MASK 0x00000020U +#define STITCHING_VS_ENABLE_BIT_SHIFT 5U +/*!Slice: bayer_pattern */ +#define STITCHING_BAYER_PATTERN +#define STITCHING_BAYER_PATTERN_MASK 0x00000018U +#define STITCHING_BAYER_PATTERN_SHIFT 3U +/*!Slice: soft_reset_flag */ +#define STITCHING_SOFT_RESET_FLAG +#define STITCHING_SOFT_RESET_FLAG_MASK 0x00000004U +#define STITCHING_SOFT_RESET_FLAG_SHIFT 2U +/*!Slice: mono_input_flag */ +#define STITCHING_MONO_INPUT_FLAG +#define STITCHING_MONO_INPUT_FLAG_MASK 0x00000002U +#define STITCHING_MONO_INPUT_FLAG_SHIFT 1U +/*!Slice: combine_enable_bit */ +#define STITCHING_COMBINE_ENABLE_BIT +#define STITCHING_COMBINE_ENABLE_BIT_MASK 0x00000001U +#define STITCHING_COMBINE_ENABLE_BIT_SHIFT 0U +/*!Slice: regs_inform_en */ +#define STITCHING_REGS_INFORM_EN +#define STITCHING_REGS_INFORM_EN_MASK 0x00400000U +#define STITCHING_REGS_INFORM_EN_SHIFT 22U +/*!Slice: vsync_pol */ +#define STITCHING_VSYNC_POL +#define STITCHING_VSYNC_POL_MASK 0x00200000U +#define STITCHING_VSYNC_POL_SHIFT 21U +/*!Slice: hsync_pol */ +#define STITCHING_HSYNC_POL +#define STITCHING_HSYNC_POL_MASK 0x00100000U +#define STITCHING_HSYNC_POL_SHIFT 20U +/*!Slice: awb_gain_enable */ +#define STITCHING_AWB_GAIN_ENABLE +#define STITCHING_AWB_GAIN_ENABLE_MASK 0x00080000U +#define STITCHING_AWB_GAIN_ENABLE_SHIFT 19U +/*!Slice: cfg_upd */ +#define STITCHING_CFG_UPD +#define STITCHING_CFG_UPD_MASK 0x00040000U +#define STITCHING_CFG_UPD_SHIFT 18U +/*!Slice: gen_cfg_upd */ +#define STITCHING_GEN_CFG_UPD +#define STITCHING_GEN_CFG_UPD_MASK 0x00020000U +#define STITCHING_GEN_CFG_UPD_SHIFT 17U +/*!Slice: gen_cfg_upd_fix */ +#define STITCHING_GEN_CFG_UPD_FIX +#define STITCHING_GEN_CFG_UPD_FIX_MASK 0x00010000U +#define STITCHING_GEN_CFG_UPD_FIX_SHIFT 16U +/*!Slice: bypass_select */ +#define STITCHING_BYPASS_SELECT +#define STITCHING_BYPASS_SELECT_MASK 0x00006000U +#define STITCHING_BYPASS_SELECT_SHIFT 13U +/*!Slice: linear_combine_enable */ +#define STITCHING_LINEAR_COMBINE_ENABLE +#define STITCHING_LINEAR_COMBINE_ENABLE_MASK 0x00001000U +#define STITCHING_LINEAR_COMBINE_ENABLE_SHIFT 12U +/*!Slice: base_frame_selection */ +#define STITCHING_BASE_FRAME_SELECTION +#define STITCHING_BASE_FRAME_SELECTION_MASK 0x00000800U +#define STITCHING_BASE_FRAME_SELECTION_SHIFT 11U +/*!Slice: combination_mode */ +#define STITCHING_COMBINATION_MODE +#define STITCHING_COMBINATION_MODE_MASK 0x00000600U +#define STITCHING_COMBINATION_MODE_SHIFT 9U +/*!Slice: channel_config_bit */ +#define STITCHING_CHANNEL_CONFIG_BIT +#define STITCHING_CHANNEL_CONFIG_BIT_MASK 0x00000100U +#define STITCHING_CHANNEL_CONFIG_BIT_SHIFT 8U +/*!Slice: B10_enable_bit */ +#define STITCHING_B10_ENABLE_BIT +#define STITCHING_B10_ENABLE_BIT_MASK 0x00000080U +#define STITCHING_B10_ENABLE_BIT_SHIFT 7U +/*!Slice: lin_enable_bit */ +#define STITCHING_LIN_ENABLE_BIT +#define STITCHING_LIN_ENABLE_BIT_MASK 0x00000040U +#define STITCHING_LIN_ENABLE_BIT_SHIFT 6U +/*!Slice: VS_enable_bit */ +#define STITCHING_VS_ENABLE_BIT +#define STITCHING_VS_ENABLE_BIT_MASK 0x00000020U +#define STITCHING_VS_ENABLE_BIT_SHIFT 5U +/*!Slice: bayer_pattern */ +#define STITCHING_BAYER_PATTERN +#define STITCHING_BAYER_PATTERN_MASK 0x00000018U +#define STITCHING_BAYER_PATTERN_SHIFT 3U +/*!Slice: soft_reset_flag */ +#define STITCHING_SOFT_RESET_FLAG +#define STITCHING_SOFT_RESET_FLAG_MASK 0x00000004U +#define STITCHING_SOFT_RESET_FLAG_SHIFT 2U +/*!Slice: mono_input_flag */ +#define STITCHING_MONO_INPUT_FLAG +#define STITCHING_MONO_INPUT_FLAG_MASK 0x00000002U +#define STITCHING_MONO_INPUT_FLAG_SHIFT 1U +/*!Slice: combine_enable_bit */ +#define STITCHING_COMBINE_ENABLE_BIT +#define STITCHING_COMBINE_ENABLE_BIT_MASK 0x00000001U +#define STITCHING_COMBINE_ENABLE_BIT_SHIFT 0U +/*!Register: isp_stitching_frame_width (0x00003304) */ +/*!Slice: stitching_frame_width */ +#define STITCHING_FRAME_WIDTH +#define STITCHING_FRAME_WIDTH_MASK 0x00003FFFU +#define STITCHING_FRAME_WIDTH_SHIFT 0U +/*!Register: isp_stitching_ctrl (0x00003300)*/ +/*!Slice: digital_gain_en_2 */ +#define STITCHING_DIGITAL_GAIN_EN2 +#define STITCHING_DIGITAL_GAIN_EN2_MASK 0x02000000U +#define STITCHING_DIGITAL_GAIN_EN2_SHIFT 25U +/*!Register: isp_stitching_ctrl (0x00003300)*/ +/*!Slice: digital_gain_en_1 */ +#define STITCHING_DIGITAL_GAIN_EN1 +#define STITCHING_DIGITAL_GAIN_EN1_MASK 0x01000000U +#define STITCHING_DIGITAL_GAIN_EN1_SHIFT 24U +/*!Register: isp_stitching_ctrl (0x00003300)*/ +/*!Slice: digital_gain_en_0 */ +#define STITCHING_DIGITAL_GAIN_EN0 +#define STITCHING_DIGITAL_GAIN_EN0_MASK 0x00800000U +#define STITCHING_DIGITAL_GAIN_EN0_SHIFT 23U +/*!Register: isp_stitching_ctrl (0x00003300)*/ +/*!Slice: digital_gain_en */ +#define STITCHING_DIGITAL_GAIN_EN +#define STITCHING_DIGITAL_GAIN_EN_MASK 0x00400000U +#define STITCHING_DIGITAL_GAIN_EN_SHIFT 22U +/*!Register: isp_stitching_frame_height (0x00003308) */ +/*!Slice: stitching_frame_height */ +#define STITCHING_FRAME_HEIGHT +#define STITCHING_FRAME_HEIGHT_MASK 0x00003FFFU +#define STITCHING_FRAME_HEIGHT_SHIFT 0U +/*Register: isp_stitching_exposure_bit (0x0000330C) */ +/*!Slice: stitching_l_bit_depth */ +#define STITCHING_L_BIT_DEPTH +#define STITCHING_L_BIT_DEPTH_MASK 0xFF000000U +#define STITCHING_L_BIT_DEPTH_SHIFT 24U +/*!Slice: stitching_s_bit_depth */ +#define STITCHING_S_BIT_DEPTH +#define STITCHING_S_BIT_DEPTH_MASK 0x00FF0000U +#define STITCHING_S_BIT_DEPTH_SHIFT 16U +/*!Slice: stitching_vs_bit_depth */ +#define STITCHING_VS_BIT_DEPTH +#define STITCHING_VS_BIT_DEPTH_MASK 0x0000FF00U +#define STITCHING_VS_BIT_DEPTH_SHIFT 8U +/*!Slice: stitching_ls_bit_depth */ +#define STITCHING_LS_BIT_DEPTH +#define STITCHING_LS_BIT_DEPTH_MASK 0x000000FFU +#define STITCHING_LS_BIT_DEPTH_SHIFT 0U +/*!Register: isp_stitching_color_weight */ +/*!Slice: stitching_color_weight_2 */ +#define STITCHING_COLOR_WEIGHT_2 +#define STITCHING_COLOR_WEIGHT_2_MASK 0x00FF0000U +#define STITCHING_COLOR_WEIGHT_2_SHIFT 16U +/*!Slice: stitching_color_weight_1 */ +#define STITCHING_COLOR_WEIGHT_1 +#define STITCHING_COLOR_WEIGHT_1_MASK 0x0000FF00U +#define STITCHING_COLOR_WEIGHT_1_SHIFT 8U +/*!Slice: stitching_color_weight_0 */ +#define STITCHING_COLOR_WEIGHT_0 +#define STITCHING_COLOR_WEIGHT_0_MASK 0x000000FFU +#define STITCHING_COLOR_WEIGHT_0_SHIFT 0U +/*!Register: isp_stitching_bls_exp_0_a (0x00003314)*/ +/*!Slice: stitching_digital_gain_exp_0_r */ +#define STITCHING_DIGITAL_GAIN_EXP_0_R +#define STITCHING_DIGITAL_GAIN_EXP_0_R_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_0_R_SHIFT 16U +/*!Register: isp_stitching_bls_exp_0_a (0x00003314)*/ +/*!Slice: stitching_bls_exp_0_a */ +#define STITCHING_BLS_EXP_0_A +#define STITCHING_BLS_EXP_0_A_MASK 0x000000FFFU +#define STITCHING_BLS_EXP_0_A_SHIFT 0U +/*!Register: isp_stitching_bls_exp_0_b (0x00003318)*/ +/*!Slice: stitching_digital_gain_exp_0_g */ +#define STITCHING_DIGITAL_GAIN_EXP_0_G +#define STITCHING_DIGITAL_GAIN_EXP_0_G_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_0_G_SHIFT 16U +/*!Register: isp_stitching_bls_exp_0_b (0x00003318)*/ +/*!Slice: stitching_bls_exp_0_b */ +#define STITCHING_BLS_EXP_0_B +#define STITCHING_BLS_EXP_0_B_MASK 0x000000FFFU +#define STITCHING_BLS_EXP_0_B_SHIFT 0U +/*!Register: isp_stitching_bls_exp_0_c (0x0000331c)*/ +/*!Slice: stitching_digital_gain_exp_0_gr */ +#define STITCHING_DIGITAL_GAIN_EXP_0_GR +#define STITCHING_DIGITAL_GAIN_EXP_0_GR_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_0_GR_SHIFT 16U +/*!Register: isp_stitching_bls_exp_0_c (0x0000331C)*/ +/*!Slice: stitching_bls_exp_0_c */ +#define STITCHING_BLS_EXP_0_C +#define STITCHING_BLS_EXP_0_C_MASK 0x000000FFFU +#define STITCHING_BLS_EXP_0_C_SHIFT 0U +/*!Register: isp_stitching_bls_exp_0_d (0x00003320)*/ +/*!Slice: stitching_digital_gain_exp_0_gb */ +#define STITCHING_DIGITAL_GAIN_EXP_0_GB +#define STITCHING_DIGITAL_GAIN_EXP_0_GB_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_0_GB_SHIFT 16U +/*!Register: isp_stitching_bls_exp_0_d (0x00003320)*/ +/*!Slice: stitching_bls_exp_0_d */ +#define STITCHING_BLS_EXP_0_D +#define STITCHING_BLS_EXP_0_D_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_0_D_SHIFT 0U +/*!Register: isp_stitching_bls_exp_1_a (0x00003324)*/ +/*!Slice: stitching_digital_gain_exp_1_r */ +#define STITCHING_DIGITAL_GAIN_EXP_1_R +#define STITCHING_DIGITAL_GAIN_EXP_1_R_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_1_R_SHIFT 16U +/*!Register: isp_stitching_bls_exp_1_a (0x00003324)*/ +/*!Slice: stitching_bls_exp_1_a */ +#define STITCHING_BLS_EXP_1_A +#define STITCHING_BLS_EXP_1_A_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_1_A_SHIFT 0U +/*!Register: isp_stitching_bls_exp_1_b (0x00003328)*/ +/*!Slice: stitching_digital_gain_exp_1_g */ +#define STITCHING_DIGITAL_GAIN_EXP_1_G +#define STITCHING_DIGITAL_GAIN_EXP_1_G_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_1_G_SHIFT 16U +/*!Register: isp_stitching_bls_exp_1_b (0x00003328)*/ +/*!Slice: stitching_bls_exp_1_b */ +#define STITCHING_BLS_EXP_1_B +#define STITCHING_BLS_EXP_1_B_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_1_B_SHIFT 0U +/*!Register: isp_stitching_bls_exp_1_c (0x0000332c)*/ +/*!Slice: stitching_digital_gain_exp_1_gr */ +#define STITCHING_DIGITAL_GAIN_EXP_1_GR +#define STITCHING_DIGITAL_GAIN_EXP_1_GR_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_1_GR_SHIFT 16U +/*!Register: isp_stitching_bls_exp_1_c (0x0000332C)*/ +/*!Slice: stitching_bls_exp_1_c */ +#define STITCHING_BLS_EXP_1_C +#define STITCHING_BLS_EXP_1_C_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_1_C_SHIFT 0U +/*!Register: isp_stitching_bls_exp_1_d (0x00003330)*/ +/*!Slice: stitching_digital_gain_exp_1_gb */ +#define STITCHING_DIGITAL_GAIN_EXP_1_GB +#define STITCHING_DIGITAL_GAIN_EXP_1_GB_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_1_GB_SHIFT 16U +/*!Register: isp_stitching_bls_exp_1_d (0x00003330)*/ +/*!Slice: stitching_bls_exp_1_d */ +#define STITCHING_BLS_EXP_1_D +#define STITCHING_BLS_EXP_1_D_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_1_D_SHIFT 0U +/*!Register: isp_stitching_bls_exp_2_a (0x00003334)*/ +/*!Slice: stitching_digital_gain_exp_2_r */ +#define STITCHING_DIGITAL_GAIN_EXP_2_R +#define STITCHING_DIGITAL_GAIN_EXP_2_R_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_2_R_SHIFT 16U +/*!Register: isp_stitching_bls_exp_2_a (0x00003334)*/ +/*!Slice: stitching_bls_exp_2_a */ +#define STITCHING_BLS_EXP_2_A +#define STITCHING_BLS_EXP_2_A_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_2_A_SHIFT 0U +/*!Register: isp_stitching_bls_exp_2_b (0x00003338)*/ +/*!Slice: stitching_digital_gain_exp_2_g */ +#define STITCHING_DIGITAL_GAIN_EXP_2_G +#define STITCHING_DIGITAL_GAIN_EXP_2_G_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_2_G_SHIFT 16U +/*!Register: isp_stitching_bls_exp_2_b (0x00003338)*/ +/*!Slice: stitching_bls_exp_2_b */ +#define STITCHING_BLS_EXP_2_B +#define STITCHING_BLS_EXP_2_B_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_2_B_SHIFT 0U +/*!Register: isp_stitching_bls_exp_2_c (0x0000333c)*/ +/*!Slice: stitching_digital_gain_exp_2_gr */ +#define STITCHING_DIGITAL_GAIN_EXP_2_GR +#define STITCHING_DIGITAL_GAIN_EXP_2_GR_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_2_GR_SHIFT 16U +/*!Register: isp_stitching_bls_exp_2_c (0x0000333C)*/ +/*!Slice: stitching_bls_exp_2_c */ +#define STITCHING_BLS_EXP_2_C +#define STITCHING_BLS_EXP_2_C_MASK 0x0000FFFU +#define STITCHING_BLS_EXP_2_C_SHIFT 0U +/*!Register: isp_stitching_bls_exp_2_d (0x00003340)*/ +/*!Slice: stitching_digital_gain_exp_2_gb */ +#define STITCHING_DIGITAL_GAIN_EXP_2_GB +#define STITCHING_DIGITAL_GAIN_EXP_2_GB_MASK 0XFFFFF0000U +#define STITCHING_DIGITAL_GAIN_EXP_2_GB_SHIFT 16U +/*!Register: isp_stitching_bls_exp_2_d (0x00003340)*/ +/*!Slice: stitching_bls_exp_2_d */ +#define STITCHING_BLS_EXP_2_D +#define STITCHING_BLS_EXP_2_D_MASK 0x000000FFFU +#define STITCHING_BLS_EXP_2_D_SHIFT 0U +/*!Reister: isp_stitching_ratio_ls (0x00003344)*/ +/*!Slice: stitching_ratio_long_short_1 */ +#define STITCHING_RATIO_LONG_SHORT_1 +#define STITCHING_RATIO_LONG_SHORT_1_MASK 0x00FFF000U +#define STITCHING_RATIO_LONG_SHORT_1_SHIFT 12U +/*!Slice: stitching_ratio_long_short_0 */ +#define STITCHING_RATIO_LONG_SHORT_0 +#define STITCHING_RATIO_LONG_SHORT_0_MASK 0x00000FFFU +#define STITCHING_RATIO_LONG_SHORT_0_SHIFT 0U +/*!Reister: isp_stitching_ratio_vs (0x00003348) */ +/*!Slice: stitching_ratio_veryshort_short_1 */ +#define STITCHING_RATIO_VERYSHORT_SHORT_1 +#define STITCHING_RATIO_VERYSHORT_SHORT_1_MASK 0x00FFF000U +#define STITCHING_RATIO_VERYSHORT_SHORT_1_SHIFT 12U +/*!Slice: stitching_ratio_veryshort_short_0 */ +#define STITCHING_RATIO_VERYSHORT_SHORT_0 +#define STITCHING_RATIO_VERYSHORT_SHORT_0_MASK 0x00000FFFU +#define STITCHING_RATIO_VERYSHORT_SHORT_0_SHIFT 0U +/*!Reister: isp_stitching_ratio_ls_shd (0x0000334C) */ +/*!Slice: stitching_ratio_long_short_shd_1 */ +#define STITCHING_RATIO_LONG_SHORT_SHD_1 +#define STITCHING_RATIO_LONG_SHORT_SHD_1_MASK 0x00FFF000U +#define STITCHING_RATIO_LONG_SHORT_SHD_1_SHIFT 12U +/*!Slice: stitching_ratio_long_short_shd_0 */ +#define STITCHING_RATIO_LONG_SHORT_SHD_0 +#define STITCHING_RATIO_LONG_SHORT_SHD_0_MASK 0x00000FFFU +#define STITCHING_RATIO_LONG_SHORT_SHD_0_SHIFT 0U +/*!Reister: isp_stitching_ratio_vs_shd (0x00003350) */ +/*!Slice: stitching_ratio_veryshort_short_shd_1 */ +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1 +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1_MASK 0x00FFF000U +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1_SHIFT 12U +/*!Slice: stitching_ratio_veryshort_short_shd_0 */ +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0 +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0_MASK 0x00000FFFU +#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0_SHIFT 0U +/*!Register: isp_sitching_trans_range_linear (0x00003354) */ +/*!Slice: stitching_trans_range_start_linear */ +#define STITCHING_TRANS_RANGE_START_LINEAR +#define STITCHING_TRANS_RANGE_START_LINEAR_MASK 0xFFFF0000U +#define STITCHING_TRANS_RANGE_START_LINEAR_SHIFT 16U +/*!Slice:stitching_trans_range_norm_factor_mul_linear */ +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR_MASK 0x0000FFFFU +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR_SHIFT 0U +/*!Register: isp_sitching_trans_range_nonlinear (0x00003358) */ +/*!Slice: stitching_trans_range_start_nonlinear */ +#define STITCHING_TRANS_RANGE_START_NONLINEAR +#define STITCHING_TRANS_RANGE_START_NONLINEAR_MASK 0xFFFF0000U +#define STITCHING_TRANS_RANGE_START_NONLINEAR_SHIFT 16U +/*!Slice:stitching_trans_range_norm_factor_mul_nonlinear */ +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR_MASK 0x0000FFFFU +#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR_SHIFT 0U +/*!Register: isp_stitching_sat_level (0x0000335C) */ +//Version-11 Stitching only support one type extend bit +//!Slice: stitching_short_vs_extend_bit +#define STITCHING_SHORT_EXTEND_BIT +#define STITCHING_SHORT_EXTEND_BIT_MASK 0xFF000000U +#define STITCHING_SHORT_EXTEND_BIT_SHIFT 24U +//Version-12 Stitching support two type extend bit +//!Slice: stitching_short_ls_extend_bit +#define STITCHING_SHORT_LS_EXTEND_BIT +#define STITCHING_SHORT_LS_EXTEND_BIT_MASK 0xF0000000U +#define STITCHING_SHORT_LS_EXTEND_BIT_SHIFT 28U +//!Slice: stitching_short_vs_extend_bit +#define STITCHING_SHORT_VS_EXTEND_BIT +#define STITCHING_SHORT_VS_EXTEND_BIT_MASK 0x0F000000U +#define STITCHING_SHORT_VS_EXTEND_BIT_SHIFT 24U +/*!Slice: stitching_veryshort_valid_thresh */ +#define STITCHING_VERYSHORT_VALID_THRESH +#define STITCHING_VERYSHORT_VALID_THRESH_MASK 0x00FFF000U +#define STITCHING_VERYSHORT_VALID_THRESH_SHIFT 12U +/*!Slice: stitching_veryshort_offset_val */ +#define STITCHING_VERYSHORT_OFFSET_VAL +#define STITCHING_VERYSHORT_OFFSET_VAL_MASK 0x00000FFFU +#define STITCHING_VERYSHORT_OFFSET_VAL_SHIFT 0U +/*!Register: isp_stitching_long_exposure (0x00003360) */ +/*!Slice: stitching_long_exposure_time */ +#define STITCHING_LONG_EXPOSURE_TIME +#define STITCHING_LONG_EXPOSURE_TIME_MASK 0x00000FFFU +#define STITCHING_LONG_EXPOSURE_TIME_SHIFT 0U +/*!Register: isp_stitching_short_exposure (0x00003364) */ +/*!Slice: stitching_short_exposure_time */ +#define STITCHING_SHORT_EXPOSURE_TIME +#define STITCHING_SHORT_EXPOSURE_TIME_MASK 0x00000FFFU +#define STITCHING_SHORT_EXPOSURE_TIME_SHIFT 0U +/*!Register: isp_stitching_very_short_exposure (0x00003368) */ +/*!Slice: stitching_very_short_exposure_time */ +#define STITCHING_VERY_SHORT_EXPOSURE_TIME +#define STITCHING_VERY_SHORT_EXPOSURE_TIME_MASK 0x00000FFFU +#define STITCHING_VERY_SHORT_EXPOSURE_TIME_SHIFT 0U +/*!Register: isp_stitching_hdr_mode (0x0000336C) */ +/*!Slice: stitching_hdr_mode */ +#define STITCHING_HDR_MODE_BIT +#define STITCHING_HDR_MODE_BIT_MASK 0x0000000FU +#define STITCHING_HDR_MODE_BIT_SHIFT 0U +/*!Register: isp_stitching_out_hblank (0x00003370) */ +/*!Slice: stitching_dummy_s_hblank */ +#define STITCHING_DUMMY_S_HBLANK +#define STITCHING_DUMMY_S_HBLANK_MASK 0xFFFF0000U +#define STITCHING_DUMMY_S_HBLANK_SHIFT 16U +/*!Slice: stitching_out_hblank */ +#define STITCHING_OUT_HBLANK +#define STITCHING_OUT_HBLANK_MASK 0x00003FFFU +#define STITCHING_OUT_HBLANK_SHIFT 0U +/*!Register: isp_stitching_out_vblank (0x00003374) */ +/*!Slice: stitching_dummy_vs_hblank */ +#define STITCHING_DUMMY_VS_HBLANK +#define STITCHING_DUMMY_VS_HBLANK_MASK 0xFFFF0000U +#define STITCHING_DUMMY_VS_HBLANK_SHIFT 16U +/*!Slice: stitching_out_vblank */ +#define STITCHING_OUT_VBLANK +#define STITCHING_OUT_VBLANK_MASK 0x00000FFFU +#define STITCHING_OUT_VBLANK_SHIFT 0U +/*!Register:ISP_STITCHING_OUT_HBLANK (0x00003370)*/ +/* Slice:stiching_dummy_hblank */ +#define STITCHING_DUMMY_HBLANK +#define STITCHING_DUMMY_HBLANK_MASK 0xFFFF0000U +#define STITCHING_DUMMY_HBLANK_SHIFT 16U +/*!Register: isp_stitching_interrupt_status (0x00003378) */ +/*!Slice: stitching_interrupt_status */ +#define STITCHING_INTERRUPT_STATUS +#define STITCHING_INTERRUPT_STATUS_MASK 0x00000007U +#define STITCHING_INTERRUPT_STATUS_SHIFT 0U +/*!Register: isp_stitching_compress_x0 (0x0000337C) */ +/*!Slice: stitching_compress_x0 */ +#define STITCHING_COMPRESS_X0 +#define STITCHING_COMPRESS_X0_MASK 0x000003FFU +#define STITCHING_COMPRESS_X0_SHIFT 0U +/*!Register: isp_stitching_compress_lut_0 (0x000033A0) */ +/*!Slice: stitching_compress_lut_2 */ +#define STITCHING_COMPRESS_LUT_2 +#define STITCHING_COMPRESS_LUT_2_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_2_SHIFT 20U +/*!Slice: stitching_compress_lut_1 */ +#define STITCHING_COMPRESS_LUT_1 +#define STITCHING_COMPRESS_LUT_1_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_1_SHIFT 10U +/*!Slice: stitching_compress_lut_0 */ +#define STITCHING_COMPRESS_LUT_0 +#define STITCHING_COMPRESS_LUT_0_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_0_SHIFT 0U +/*!Register: isp_stitching_compress_lut_1 (0x000033A4) */ +/*!Slice: stitching_compress_lut_5 */ +#define STITCHING_COMPRESS_LUT_5 +#define STITCHING_COMPRESS_LUT_5_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_5_SHIFT 20U +/*!Slice: stitching_compress_lut_4 */ +#define STITCHING_COMPRESS_LUT_4 +#define STITCHING_COMPRESS_LUT_4_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_4_SHIFT 10U +/*!Slice: stitching_compress_lut_3 */ +#define STITCHING_COMPRESS_LUT_3 +#define STITCHING_COMPRESS_LUT_3_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_3_SHIFT 0U +/*!Register: isp_stitching_compress_lut_2 (0x000033A8) */ +/*!Slice: stitching_compress_lut_8 */ +#define STITCHING_COMPRESS_LUT_8 +#define STITCHING_COMPRESS_LUT_8_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_8_SHIFT 20U +/*!Slice: stitching_compress_lut_7 */ +#define STITCHING_COMPRESS_LUT_7 +#define STITCHING_COMPRESS_LUT_7_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_7_SHIFT 10U +/*!Slice: stitching_compress_lut_6 */ +#define STITCHING_COMPRESS_LUT_6 +#define STITCHING_COMPRESS_LUT_6_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_6_SHIFT 0U +/*!Register: isp_stitching_compress_lut_3 (0x000033AC) */ +/*!Slice: stitching_compress_lut_11 */ +#define STITCHING_COMPRESS_LUT_11 +#define STITCHING_COMPRESS_LUT_11_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_11_SHIFT 20U +/*!Slice: stitching_compress_lut_10 */ +#define STITCHING_COMPRESS_LUT_10 +#define STITCHING_COMPRESS_LUT_10_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_10_SHIFT 10U +/*!Slice: stitching_compress_lut_9 */ +#define STITCHING_COMPRESS_LUT_9 +#define STITCHING_COMPRESS_LUT_9_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_9_SHIFT 0U +/*!Register: isp_stitching_compress_lut_4 (0x000033B0) */ +/*!Slice: stitching_compress_lut_14 */ +#define STITCHING_COMPRESS_LUT_14 +#define STITCHING_COMPRESS_LUT_14_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_14_SHIFT 20U +/*!Slice: stitching_compress_lut_13 */ +#define STITCHING_COMPRESS_LUT_13 +#define STITCHING_COMPRESS_LUT_13_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_13_SHIFT 10U +/*!Slice: stitching_compress_lut_12 */ +#define STITCHING_COMPRESS_LUT_12 +#define STITCHING_COMPRESS_LUT_12_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_12_SHIFT 0U +/*/*!Register: isp_stitching_compress_lut_shd_0 (0x000033B4) */ +/*!Slice: stitching_compress_lut_shd_2 */ +#define STITCHING_COMPRESS_LUT_SHD_2 +#define STITCHING_COMPRESS_LUT_SHD_2_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_SHD_2_SHIFT 20U +/*!Slice: stitching_compress_lut_shd_1 */ +#define STITCHING_COMPRESS_LUT_SHD_1 +#define STITCHING_COMPRESS_LUT_SHD_1_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_SHD_1_SHIFT 10U +/*!Slice: stitching_compress_lut_shd_0 */ +#define STITCHING_COMPRESS_LUT_SHD_0 +#define STITCHING_COMPRESS_LUT_SHD_0_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_SHD_0_SHIFT 0U +/*!Register: isp_stitching_compress_lut_shd_1 (0x000033B8) */ +/*!Slice: stitching_compress_lut_shd_5 */ +#define STITCHING_COMPRESS_LUT_SHD_5 +#define STITCHING_COMPRESS_LUT_SHD_5_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_SHD_5_SHIFT 20U +/*!Slice: stitching_compress_lut_shd_4 */ +#define STITCHING_COMPRESS_LUT_SHD_4 +#define STITCHING_COMPRESS_LUT_SHD_4_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_SHD_4_SHIFT 10U +/*!Slice: stitching_compress_lut_shd_3 */ +#define STITCHING_COMPRESS_LUT_SHD_3 +#define STITCHING_COMPRESS_LUT_SHD_3_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_SHD_3_SHIFT 0U +/*!Register: isp_stitching_compress_lut_shd_2 (0x000033BC) */ +/*!Slice: stitching_compress_lut_shd_8 */ +#define STITCHING_COMPRESS_LUT_SHD_8 +#define STITCHING_COMPRESS_LUT_SHD_8_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_SHD_8_SHIFT 20U +/*!Slice: stitching_compress_lut_shd_7 */ +#define STITCHING_COMPRESS_LUT_SHD_7 +#define STITCHING_COMPRESS_LUT_SHD_7_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_SHD_7_SHIFT 10U +/*!Slice: stitching_compress_lut_shd_6 */ +#define STITCHING_COMPRESS_LUT_SHD_6 +#define STITCHING_COMPRESS_LUT_SHD_6_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_SHD_6_SHIFT 0U +/*!Register: isp_stitching_compress_lut_shd_3 (0x000033C0) */ +/*!Slice: stitching_compress_lut_shd_11 */ +#define STITCHING_COMPRESS_LUT_SHD_11 +#define STITCHING_COMPRESS_LUT_SHD_11_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_SHD_11_SHIFT 20U +/*!Slice: stitching_compress_lut_shd_10 */ +#define STITCHING_COMPRESS_LUT_SHD_10 +#define STITCHING_COMPRESS_LUT_SHD_10_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_SHD_10_SHIFT 10U +/*!Slice: stitching_compress_lut_shd_9 */ +#define STITCHING_COMPRESS_LUT_SHD_9 +#define STITCHING_COMPRESS_LUT_SHD_9_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_SHD_9_SHIFT 0U +/*!Register: isp_stitching_compress_lut_shd_4 (0x000033C4) */ +/*!Slice: stitching_compress_lut_shd_14 */ +#define STITCHING_COMPRESS_LUT_SHD_14 +#define STITCHING_COMPRESS_LUT_SHD_14_MASK 0x3FF00000U +#define STITCHING_COMPRESS_LUT_SHD_14_SHIFT 20U +/*!Slice: stitching_compress_lut_shd_13 */ +#define STITCHING_COMPRESS_LUT_SHD_13 +#define STITCHING_COMPRESS_LUT_SHD_13_MASK 0x000FFC00U +#define STITCHING_COMPRESS_LUT_SHD_13_SHIFT 10U +/*!Slice: stitching_compress_lut_shd_12 */ +#define STITCHING_COMPRESS_LUT_SHD_12 +#define STITCHING_COMPRESS_LUT_SHD_12_MASK 0x000003FFU +#define STITCHING_COMPRESS_LUT_SHD_12_SHIFT 0U +/*!Register:isp_stitching_exp0_awb_gain_g (0x000033C8) */ +/*Slice:stiching_exp0_awb_gain_gr */ +#define STITCHING_EXP0_AWB_GAIN_GR +#define STITCHING_EXP0_AWB_GAIN_GR_MASK 0x03FF0000U +#define STITCHING_EXP0_AWB_GAIN_GR_SHIFT 16U +/*Slice:stiching_exp0_awb_gain_gb */ +#define STITCHING_EXP0_AWB_GAIN_GB +#define STITCHING_EXP0_AWB_GAIN_GB_MASK 0x000003FFU +#define STITCHING_EXP0_AWB_GAIN_GB_SHIFT 0U +/*Slice:stiching_exp0_awb_gain_r */ +#define STITCHING_EXP0_AWB_GAIN_R +#define STITCHING_EXP0_AWB_GAIN_R_MASK 0x03FF0000U +#define STITCHING_EXP0_AWB_GAIN_R_SHIFT 16U +/*Slice:stiching_exp0_awb_gain_b */ +#define STITCHING_EXP0_AWB_GAIN_B +#define STITCHING_EXP0_AWB_GAIN_B_MASK 0x000003FFU +#define STITCHING_EXP0_AWB_GAIN_B_SHIFT 0U +/*Slice:stiching_exp1_awb_gain_gr */ +#define STITCHING_EXP1_AWB_GAIN_GR +#define STITCHING_EXP1_AWB_GAIN_GR_MASK 0x03FF0000U +#define STITCHING_EXP1_AWB_GAIN_GR_SHIFT 16U +/*Slice:stiching_exp1_awb_gain_gb */ +#define STITCHING_EXP1_AWB_GAIN_GB +#define STITCHING_EXP1_AWB_GAIN_GB_MASK 0x000003FFU +#define STITCHING_EXP1_AWB_GAIN_GB_SHIFT 0U +/*Slice:stiching_exp1_awb_gain_r */ +#define STITCHING_EXP1_AWB_GAIN_R +#define STITCHING_EXP1_AWB_GAIN_R_MASK 0x03FF0000U +#define STITCHING_EXP1_AWB_GAIN_R_SHIFT 16U +/*Slice:stiching_exp1_awb_gain_b */ +#define STITCHING_EXP1_AWB_GAIN_B +#define STITCHING_EXP1_AWB_GAIN_B_MASK 0x000003FFU +#define STITCHING_EXP1_AWB_GAIN_B_SHIFT 0U +/*Slice:stiching_exp2_awb_gain_gr */ +#define STITCHING_EXP2_AWB_GAIN_GR +#define STITCHING_EXP2_AWB_GAIN_GR_MASK 0x03FF0000U +#define STITCHING_EXP2_AWB_GAIN_GR_SHIFT 16U +/*Slice:stiching_exp2_awb_gain_gb */ +#define STITCHING_EXP2_AWB_GAIN_GB +#define STITCHING_EXP2_AWB_GAIN_GB_MASK 0x000003FFU +#define STITCHING_EXP2_AWB_GAIN_GB_SHIFT 0U +/*Slice:stiching_exp0_awb_gain_r */ +#define STITCHING_EXP2_AWB_GAIN_R +#define STITCHING_EXP2_AWB_GAIN_R_MASK 0x03FF0000U +#define STITCHING_EXP2_AWB_GAIN_R_SHIFT 16U +/*Slice:stiching_exp0_awb_gain_b */ +#define STITCHING_EXP2_AWB_GAIN_B +#define STITCHING_EXP2_AWB_GAIN_B_MASK 0x000003FFU +#define STITCHING_EXP2_AWB_GAIN_B_SHIFT 0U +/*Register: isp_stitching_long_sat_params */ +/*!Slice: stitching_long_sat_thresh */ +#define STITCHING_LONG_SAT_THRESH +#define STITCHING_LONG_SAT_THRESH_MASK 0x00FFF000U +#define STITCHING_LONG_SAT_THRESH_SHIFT 12U +/*!Slice: stitching_long_sat_combine_weight */ +#define STITCHING_LONG_SAT_COMBINE_WEIGHT +#define STITCHING_LONG_SAT_COMBINE_WEIGHT_MASK 0x000001FF +#define STITCHING_LONG_SAT_COMBINE_WEIGHT_SHIFT 0U +//!Register: isp_stitching_bls_exp_out_0 (0x000033F8) +//! Slice: stitching_bls_exp_out_a: +#define STITCHING_BLS_EXP_OUT_A +#define STITCHING_BLS_EXP_OUT_A_MASK 0x0FFF0000U +#define STITCHING_BLS_EXP_OUT_A_SHIFT 16U +//! Slice: stitching_bls_exp_out_b: +#define STITCHING_BLS_EXP_OUT_B +#define STITCHING_BLS_EXP_OUT_B_MASK 0x00000FFFU +#define STITCHING_BLS_EXP_OUT_B_SHIFT 0U +//!Register: isp_stitching_bls_exp_out_1 (0x000033FC) +//! Slice: stitching_bls_exp_out_c: +#define STITCHING_BLS_EXP_OUT_C +#define STITCHING_BLS_EXP_OUT_C_MASK 0x0FFF0000U +#define STITCHING_BLS_EXP_OUT_C_SHIFT 16U +//! Slice: stitching_bls_exp_out_d: +#define STITCHING_BLS_EXP_OUT_D +#define STITCHING_BLS_EXP_OUT_D_MASK 0x00000FFFU +#define STITCHING_BLS_EXP_OUT_D_SHIFT 0U + +/*! Slice: ISP_STITCHING0_EXP_IMSC:*/ +#define STITCHING_MIS_HDR_EXP_COMPLETE_L +#define STITCHING_MIS_HDR_EXP_COMPLETE_L_MASK 0x00000008U +#define STITCHING_MIS_HDR_EXP_COMPLETE_L_SHIFT 3U +#define STITCHING_MIS_HDR_EXP_COMPLETE_S +#define STITCHING_MIS_HDR_EXP_COMPLETE_S_MASK 0x00000010U +#define STITCHING_MIS_HDR_EXP_COMPLETE_S_SHIFT 4U +#define STITCHING_MIS_HDR_EXP_COMPLETE_VS +#define STITCHING_MIS_HDR_EXP_COMPLETE_VS_MASK 0x00000020U +#define STITCHING_MIS_HDR_EXP_COMPLETE_VS_SHIFT 5U + +/*! Slice: ISP_STITCHING0_HIST_MIS:*/ +#define STITCHING_MIS_HDR_HIST_COMPLETE_VS +#define STITCHING_MIS_HDR_HIST_COMPLETE_VS_MASK 0x00000100U +#define STITCHING_MIS_HDR_HIST_COMPLETE_VS_SHIFT 8U +#define STITCHING_MIS_HDR_HIST_COMPLETE_S +#define STITCHING_MIS_HDR_HIST_COMPLETE_S_MASK 0x00000080U +#define STITCHING_MIS_HDR_HIST_COMPLETE_S_SHIFT 7U +#define STITCHING_MIS_HDR_HIST_COMPLETE_L +#define STITCHING_MIS_HDR_HIST_COMPLETE_L_MASK 0x00000040U +#define STITCHING_MIS_HDR_HIST_COMPLETE_L_SHIFT 6U + +/*!Slice: 2DNR ENABLE */ +#define ISP_2DNR_ENABLE +#define ISP_2DNR_ENABLE_MASK 0x00000001 +#define ISP_2DNR_ENABLE_SHIFT 0U +/*!Slice: 2DNR PRGAMMA STRENGTH */ +#define ISP_2DNR_PRGAMMA_STRENGTH +#define ISP_2DNR_PRGAMMA_STRENGTH_MASK 0x00003F80 +#define ISP_2DNR_PRGAMMA_STRENGTH_SHIFT 7U +/*!Slice: 2DNR STRENGTH */ +#define ISP_2DNR_STRENGTH +#define ISP_2DNR_STRENGTH_MASK 0x0000007F +#define ISP_2DNR_STRENGTH_SHIFT 0U +/*!Slice: 2DNR SIGMAY0 */ +#define ISP_2DNR_SIGMAY0 +#define ISP_2DNR_SIGMAY0_MASK 0x00000FFF +#define ISP_2DNR_SIGMAY0_SHIFT 0U +/*!Slice: 2DNR SIGMAY1 */ +#define ISP_2DNR_SIGMAY1 +#define ISP_2DNR_SIGMAY1_MASK 0x00FFF000 +#define ISP_2DNR_SIGMAY1_SHIFT 12U +/*!Slice: 2DNR SIGMAY2A */ +#define ISP_2DNR_SIGMAY2A +#define ISP_2DNR_SIGMAY2A_MASK 0x3F000000 +#define ISP_2DNR_SIGMAY2A_SHIFT 24U +/*!Slice: 2DNR SIGMAY2B */ +#define ISP_2DNR_SIGMAY2B +#define ISP_2DNR_SIGMAY2B_MASK 0x3F000000 +#define ISP_2DNR_SIGMAY2B_SHIFT 24U +/*!Slice: 2DNR SIGMAY3 */ +#define ISP_2DNR_SIGMAY3 +#define ISP_2DNR_SIGMAY3_MASK 0x00000FFF +#define ISP_2DNR_SIGMAY3_SHIFT 0U +/*!Slice: 2DNR SIGMAY4 */ +#define ISP_2DNR_SIGMAY4 +#define ISP_2DNR_SIGMAY4_MASK 0x00FFF000 +#define ISP_2DNR_SIGMAY4_SHIFT 12U +/*!Slice: 2DNR denoise2d_dummy_hblank */ +#define ISP_2DNR_DUMMY_HBLANK +#define ISP_2DNR_DUMMY_HBLANK_MASK 0x0000FFFF +#define ISP_2DNR_DUMMY_HBLANK_SHIFT 0U + +/*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */ +#define DENOISE3D_V20_NLM_STRENGTH_OFFSET +#define DENOISE3D_V20_NLM_STRENGTH_OFFSET_MASK 0X3FF80000 +#define DENOISE3D_V20_NLM_STRENGTH_OFFSET_SHIFT 19U + +/*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */ +#define DENOISE3D_V20_NLM_STRENGTH_MAX +#define DENOISE3D_V20_NLM_STRENGTH_MAX_MASK 0X0007ff00 +#define DENOISE3D_V20_NLM_STRENGTH_MAX_SHIFT 8U + +/*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */ +#define DENOISE3D_V20_NLM_STRENGTH_SLOPE +#define DENOISE3D_V20_NLM_STRENGTH_SLOPE_MASK 0X000000ff +#define DENOISE3D_V20_NLM_STRENGTH_SLOPE_SHIFT 0U + +/* Register: ISP_DENOISE3D_CTRL 0x00003700 */ +/* Slice: 10:10 denoise3d_read_ref_en */ +#define DENOISE3D_READ_REF_EN +#define DENOISE3D_READ_REF_EN_MASK 0x00000400U +#define DENOISE3D_READ_REF_EN_SHIFT 10U + +/* Slice: 9:9 denoise3d_raw_decompress_en */ +#define DENOISE3D_RAW_DECOMPRESS_EN +#define DENOISE3D_RAW_DECOMPRESS_EN_MASK 0x00000200U +#define DENOISE3D_RAW_DECOMPRESS_EN_SHIFT 9U + +/* Slice: 8:8 denoise3d_rew_compress_en */ +#define DENOISE3D_RAW_COMPRESS_EN +#define DENOISE3D_RAW_COMPRESS_EN_MASK 0x00000100U +#define DENOISE3D_RAW_COMPRESS_EN_SHIFT 8U + +/* Slice: 7:7 denoise3d_write_ref_en */ +#define DENOISE3D_WRITE_REF_EN +#define DENOISE3D_WRITE_REF_EN_MASK 0x00000080U +#define DENOISE3D_WRITE_REF_EN_SHIFT 7U +/* Register: ISP_DENOISE3D_CTRL 0x00003700 */ +/* Slice: 5:5 denoise3d_soft_reset */ +#define DENOISE3D_SOFT_RESET +#define DENOISE3D_SOFT_RESET_MASK 0x00000020U +#define DENOISE3D_SOFT_RESET_SHIFT 5U +/* Slice: 4:4 denoise3d_horizontal_en */ +#define DENOISE3D_HORIZONTAL_EN +#define DENOISE3D_HORIZONTAL_EN_MASK 0x00000010U +#define DENOISE3D_HORIZONTAL_EN_SHIFT 4U +/* Slice: 3:3 denoise3d_vertical_en */ +#define DENOISE3D_VERTICAL_EN +#define DENOISE3D_VERTICAL_EN_MASK 0x00000008U +#define DENOISE3D_VERTICAL_EN_SHIFT 3U +/* Slice: 2:2 denoise3d_temperal_en */ +#define DENOISE3D_TEMPERAL_EN +#define DENOISE3D_TEMPERAL_EN_MASK 0x00000004U +#define DENOISE3D_TEMPERAL_EN_SHIFT 2U +/* Slice: 1:1 denoise3d_dilate_en */ +#define DENOISE3D_DILATE_EN +#define DENOISE3D_DILATE_EN_MASK 0x00000002U +#define DENOISE3D_DILATE_EN_SHIFT 1U +/* Slice: 0:0 denoise3d_enable */ +#define DENOISE3D_ENABLE +#define DENOISE3D_ENABLE_MASK 0x00000001U +#define DENOISE3D_ENABLE_SHIFT 0U +/* Register: ISP_DENOISE3D_STRENGTH 0x00003704 */ +/* Slice: 29:19 denoise3d_update_temperal */ +#define DENOISE3D_UPDATE_TEMPERAL +#define DENOISE3D_UPDATE_TEMPERAL_MASK 0x3FF80000U +#define DENOISE3D_UPDATE_TEMPERAL_SHIFT 19U +/* Slice: 18 : 8 denoise3d_update_spacial */ +#define DENOISE3D_UPDATE_SPACIAL +#define DENOISE3D_UPDATE_SPACIAL_MASK 0x0007FF00U +#define DENOISE3D_UPDATE_SPACIAL_SHIFT 8U +/* Slice: 7 : 0 denoise3d_strength */ +#define DENOISE3D_STRENGTH +#define DENOISE3D_STRENGTH_MASK 0x000000FFU +#define DENOISE3D_STRENGTH_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_H 0x00003708 */ +/* Slice: 27:20 denoise3d_strength_curve_spacial */ +#define DENOISE3D_STRENGTH_CURVE_SPACIAL +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_h_inv */ +#define DENOISE3D_THR_EDGE_H_INV +#define DENOISE3D_THR_EDGE_H_INV_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_H_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_V 0x0000370C */ +/* Slice: 27:20 denoise3d_strength_curve_temperal */ +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_v_inv */ +#define DENOISE3D_THR_EDGE_V_INV +#define DENOISE3D_THR_EDGE_V_INV_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_V_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_S 0x00003710 */ +/* Slice: 19:0 denoise3d_range_s_inv */ +#define DENOISE3D_RANGE_S_INV +#define DENOISE3D_RANGE_S_INV_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_S_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_T 0x00003714 */ +/* Slice: 29:25 denoise3d_range_t_h */ +#define DENOISE3D_RANGE_T_H +#define DENOISE3D_RANGE_T_H_MASK 0x3E000000U +#define DENOISE3D_RANGE_T_H_SHIFT 25U +/* Slice: 24:20 denoise3d_range_t_v */ +#define DENOISE3D_RANGE_T_V +#define DENOISE3D_RANGE_T_V_MASK 0x01F00000U +#define DENOISE3D_RANGE_T_V_SHIFT 20U +/* Slice: 19 : 0 denoise3d_range_t_inv */ +#define DENOISE3D_RANGE_T_INV +#define DENOISE3D_RANGE_T_INV_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_T_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_MOTION 0x00003718 */ +/* Slice: 24:20 denoise3d_range_d */ +#define DENOISE3D_RANGE_D +#define DENOISE3D_RANGE_D_MASK 0x01F00000U +#define DENOISE3D_RANGE_D_SHIFT 20U +/* Slice: 19 : 0 denoise3d_motion_inv */ +#define DENOISE3D_MOTION_INV +#define DENOISE3D_MOTION_INV_MASK 0x000FFFFFU +#define DENOISE3D_MOTION_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_DELTA_INV 0x0000371C */ +/* Slice: 29:20 denoise3d_delta_h_inv */ +#define DENOISE3D_DELTA_H_INV +#define DENOISE3D_DELTA_H_INV_MASK 0x3FF00000U +#define DENOISE3D_DELTA_H_INV_SHIFT 20U +/* Slice: 19 : 10 denoise3d_delta_v_inv */ +#define DENOISE3D_DELTA_V_INV +#define DENOISE3D_DELTA_V_INV_MASK 0x000FFC00U +#define DENOISE3D_DELTA_V_INV_SHIFT 10U +/* Slice: 9 : 0 denoise3d_delta_t_inv */ +#define DENOISE3D_DELTA_T_INV +#define DENOISE3D_DELTA_T_INV_MASK 0x000003FFU +#define DENOISE3D_DELTA_T_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_0 0x00003720 */ +/* Slice: 29:20 denoise3d_spacial_curve0 */ +#define DENOISE3D_SPACIAL_CURVE0 +#define DENOISE3D_SPACIAL_CURVE0_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE0_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve1 */ +#define DENOISE3D_SPACIAL_CURVE1 +#define DENOISE3D_SPACIAL_CURVE1_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE1_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve2 */ +#define DENOISE3D_SPACIAL_CURVE2 +#define DENOISE3D_SPACIAL_CURVE2_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE2_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_1 0x00003724 */ +/* Slice: 29 : 20 denoise3d_spacial_curve3 */ +#define DENOISE3D_SPACIAL_CURVE3 +#define DENOISE3D_SPACIAL_CURVE3_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE3_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve4 */ +#define DENOISE3D_SPACIAL_CURVE4 +#define DENOISE3D_SPACIAL_CURVE4_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE4_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve5 */ +#define DENOISE3D_SPACIAL_CURVE5 +#define DENOISE3D_SPACIAL_CURVE5_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE5_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_2 0x00003728 */ +/* Slice: 29 : 20 denoise3d_spacial_curve6 */ +#define DENOISE3D_SPACIAL_CURVE6 +#define DENOISE3D_SPACIAL_CURVE6_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE6_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve7 */ +#define DENOISE3D_SPACIAL_CURVE7 +#define DENOISE3D_SPACIAL_CURVE7_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE7_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve8 */ +#define DENOISE3D_SPACIAL_CURVE8 +#define DENOISE3D_SPACIAL_CURVE8_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE8_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_3 0x0000372C */ +/* Slice: 29 : 20 denoise3d_spacial_curve9 */ +#define DENOISE3D_SPACIAL_CURVE9 +#define DENOISE3D_SPACIAL_CURVE9_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE9_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve10 */ +#define DENOISE3D_SPACIAL_CURVE10 +#define DENOISE3D_SPACIAL_CURVE10_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE10_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve11 */ +#define DENOISE3D_SPACIAL_CURVE11 +#define DENOISE3D_SPACIAL_CURVE11_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE11_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_4 0x00003730 */ +/* Slice: 29 : 20 denoise3d_spacial_curve12 */ +#define DENOISE3D_SPACIAL_CURVE12 +#define DENOISE3D_SPACIAL_CURVE12_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE12_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve13 */ +#define DENOISE3D_SPACIAL_CURVE13 +#define DENOISE3D_SPACIAL_CURVE13_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE13_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve14 */ +#define DENOISE3D_SPACIAL_CURVE14 +#define DENOISE3D_SPACIAL_CURVE14_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE14_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_5 0x00003734 */ +/* Slice: 19 : 10 denoise3d_spacial_curve15 */ +#define DENOISE3D_SPACIAL_CURVE15 +#define DENOISE3D_SPACIAL_CURVE15_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE15_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve16 */ +#define DENOISE3D_SPACIAL_CURVE16 +#define DENOISE3D_SPACIAL_CURVE16_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE16_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_0 0x00003738 */ +/* Slice: 29 : 20 denoise3d_temperal_curve0 */ +#define DENOISE3D_TEMPERAL_CURVE0 +#define DENOISE3D_TEMPERAL_CURVE0_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE0_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve1 */ +#define DENOISE3D_TEMPERAL_CURVE1 +#define DENOISE3D_TEMPERAL_CURVE1_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE1_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve2 */ +#define DENOISE3D_TEMPERAL_CURVE2 +#define DENOISE3D_TEMPERAL_CURVE2_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE2_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_1 0x0000373C */ +/* Slice: 29 : 20 denoise3d_temperal_curve3 */ +#define DENOISE3D_TEMPERAL_CURVE3 +#define DENOISE3D_TEMPERAL_CURVE3_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE3_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve4 */ +#define DENOISE3D_TEMPERAL_CURVE4 +#define DENOISE3D_TEMPERAL_CURVE4_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE4_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve5 */ +#define DENOISE3D_TEMPERAL_CURVE5 +#define DENOISE3D_TEMPERAL_CURVE5_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE5_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_2 0x00003740 */ +/* Slice: 29 : 20 denoise3d_temperal_curve6 */ +#define DENOISE3D_TEMPERAL_CURVE6 +#define DENOISE3D_TEMPERAL_CURVE6_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE6_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve7 */ +#define DENOISE3D_TEMPERAL_CURVE7 +#define DENOISE3D_TEMPERAL_CURVE7_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE7_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve8 */ +#define DENOISE3D_TEMPERAL_CURVE8 +#define DENOISE3D_TEMPERAL_CURVE8_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE8_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_3 0x00003744 */ +/* Slice: 29 : 20 denoise3d_temperal_curve9 */ +#define DENOISE3D_TEMPERAL_CURVE9 +#define DENOISE3D_TEMPERAL_CURVE9_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE9_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve10 */ +#define DENOISE3D_TEMPERAL_CURVE10 +#define DENOISE3D_TEMPERAL_CURVE10_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE10_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve11 */ +#define DENOISE3D_TEMPERAL_CURVE11 +#define DENOISE3D_TEMPERAL_CURVE11_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE11_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_4 0x00003748 */ +/* Slice: 29 : 20 denoise3d_temperal_curve12 */ +#define DENOISE3D_TEMPERAL_CURVE12 +#define DENOISE3D_TEMPERAL_CURVE12_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE12_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve13 */ +#define DENOISE3D_TEMPERAL_CURVE13 +#define DENOISE3D_TEMPERAL_CURVE13_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE13_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve14 */ +#define DENOISE3D_TEMPERAL_CURVE14 +#define DENOISE3D_TEMPERAL_CURVE14_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE14_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_5 0x0000374C */ +/* Slice: 19 : 10 denoise3d_temperal_curve15 */ +#define DENOISE3D_TEMPERAL_CURVE15 +#define DENOISE3D_TEMPERAL_CURVE15_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE15_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve16 */ +#define DENOISE3D_TEMPERAL_CURVE16 +#define DENOISE3D_TEMPERAL_CURVE16_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE16_SHIFT 0U +/* Register: ISP_DENOISE3D_AVERAGE 0x00003750 */ +/* Slice: 31 : 0 denoise3d_frame_average */ +#define DENOISE3D_FRAME_AVERAGE +#define DENOISE3D_FRAME_AVERAGE_MASK 0xFFFFFFFFU +#define DENOISE3D_FRAME_AVERAGE_SHIFT 0U +/* Register: ISP_DENOISE3D_STRENGTH_SHD 0x00003754 */ +/* Slice: 29 : 19 denoise3d_update_temperal_shd */ +#define DENOISE3D_UPDATE_TEMPERAL_SHD +#define DENOISE3D_UPDATE_TEMPERAL_SHD_MASK 0x3FF80000U +#define DENOISE3D_UPDATE_TEMPERAL_SHD_SHIFT 19U +/* Slice: 18 : 8 denoise3d_update_spacial_shd */ +#define DENOISE3D_UPDATE_SPACIAL_SHD +#define DENOISE3D_UPDATE_SPACIAL_SHD_MASK 0x0007FF00U +#define DENOISE3D_UPDATE_SPACIAL_SHD_SHIFT 8U +/* Slice: 7 : 0 denoise3d_strength_shd */ +#define DENOISE3D_STRENGTH_SHD +#define DENOISE3D_STRENGTH_SHD_MASK 0x0000000FU +#define DENOISE3D_STRENGTH_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_H_SHD 0x00003758 */ +/* Slice: 27 : 20 denoise3d_strength_curve_spacial_shd */ +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_h_inv_shd */ +#define DENOISE3D_THR_EDGE_H_INV_SHD +#define DENOISE3D_THR_EDGE_H_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_H_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_V_SHD 0x0000375C */ +/* Slice: 27 : 20 denoise3d_strength_curve_temperal_shd */ +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_v_inv_shd */ +#define DENOISE3D_THR_EDGE_V_INV_SHD +#define DENOISE3D_THR_EDGE_V_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_V_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_S_SHD 0x00003760 */ +/* Slice: 19 : 0 denoise3d_range_s_inv_shd */ +#define DENOISE3D_RANGE_S_INV_SHD +#define DENOISE3D_RANGE_S_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_S_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_T_SHD 0x00003764 */ +/* Slice: 29 : 25 denoise3d_range_t_h_shd */ +#define DENOISE3D_RANGE_T_H_SHD +#define DENOISE3D_RANGE_T_H_SHD_MASK 0x3E000000U +#define DENOISE3D_RANGE_T_H_SHD_SHIFT 25U +/* Slice: 24 : 20 denoise3d_range_t_v_shd */ +#define DENOISE3D_RANGE_T_V_SHD +#define DENOISE3D_RANGE_T_V_SHD_MASK 0x01F00000U +#define DENOISE3D_RANGE_T_V_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_range_t_inv_shd */ +#define DENOISE3D_RANGE_T_INV_SHD +#define DENOISE3D_RANGE_T_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_T_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_MOTION_SHD 0x00003768 */ +/* Slice: 24 : 20 denoise3d_range_d_shd */ +#define DENOISE3D_RANGE_D_SHD +#define DENOISE3D_RANGE_D_SHD_MASK 0x01F00000U +#define DENOISE3D_RANGE_D_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_motion_inv_shd */ +#define DENOISE3D_MOTION_INV_SHD +#define DENOISE3D_MOTION_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_MOTION_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_DELTA_INV_SHD 0x0000376C */ +/* Slice: 29 : 20 denoise3d_delta_h_inv_shd */ +#define DENOISE3D_DELTA_H_INV_SHD +#define DENOISE3D_DELTA_H_INV_SHD_MASK 0x3FF00000U +#define DENOISE3D_DELTA_H_INV_SHD_SHIFT 20U +/* Slice: 19 : 10 denoise3d_delta_v_inv_shd */ +#define DENOISE3D_DELTA_V_INV_SHD +#define DENOISE3D_DELTA_V_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_DELTA_V_INV_SHD_SHIFT 10U +/* Slice: 9 : 0 denoise3d_delta_t_inv_shd */ +#define DENOISE3D_DELTA_T_INV_SHD +#define DENOISE3D_DELTA_T_INV_SHD_MASK 0x000003FFU +#define DENOISE3D_DELTA_T_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_DUMMY_HBLANK 0x00003770 */ +/* Slice: 14 : 0 denoise3d_H_Blank */ +#define DENOISE3D_H_BLANK +#define DENOISE3D_H_BLANK_MASK 0x0000FFFFU +#define DENOISE3D_H_BLANK_SHIFT 0U +/* Register: ISP_DENOISE3D_CTRL 0x00003700 */ +/* Slice: 5:5 denoise3d_soft_reset */ +#define DENOISE3D_SOFT_RESET +#define DENOISE3D_SOFT_RESET_MASK 0x00000020U +#define DENOISE3D_SOFT_RESET_SHIFT 5U +/* Slice: 4:4 denoise3d_horizontal_en */ +#define DENOISE3D_HORIZONTAL_EN +#define DENOISE3D_HORIZONTAL_EN_MASK 0x00000010U +#define DENOISE3D_HORIZONTAL_EN_SHIFT 4U +/* Slice: 3:3 denoise3d_vertical_en */ +#define DENOISE3D_VERTICAL_EN +#define DENOISE3D_VERTICAL_EN_MASK 0x00000008U +#define DENOISE3D_VERTICAL_EN_SHIFT 3U +/* Slice: 2:2 denoise3d_temperal_en */ +#define DENOISE3D_TEMPERAL_EN +#define DENOISE3D_TEMPERAL_EN_MASK 0x00000004U +#define DENOISE3D_TEMPERAL_EN_SHIFT 2U +/* Slice: 1:1 denoise3d_dilate_en */ +#define DENOISE3D_DILATE_EN +#define DENOISE3D_DILATE_EN_MASK 0x00000002U +#define DENOISE3D_DILATE_EN_SHIFT 1U +/* Slice: 0:0 denoise3d_enable */ +#define DENOISE3D_ENABLE +#define DENOISE3D_ENABLE_MASK 0x00000001U +#define DENOISE3D_ENABLE_SHIFT 0U +/* Register: ISP_DENOISE3D_STRENGTH 0x00003704 */ +/* Slice: 29:19 denoise3d_update_temperal */ +#define DENOISE3D_UPDATE_TEMPERAL +#define DENOISE3D_UPDATE_TEMPERAL_MASK 0x3FF80000U +#define DENOISE3D_UPDATE_TEMPERAL_SHIFT 19U +/* Slice: 18 : 8 denoise3d_update_spacial */ +#define DENOISE3D_UPDATE_SPACIAL +#define DENOISE3D_UPDATE_SPACIAL_MASK 0x0007FF00U +#define DENOISE3D_UPDATE_SPACIAL_SHIFT 8U +/* Slice: 7 : 0 denoise3d_strength */ +#define DENOISE3D_STRENGTH +#define DENOISE3D_STRENGTH_MASK 0x000000FFU +#define DENOISE3D_STRENGTH_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_H 0x00003708 */ +/* Slice: 27:20 denoise3d_strength_curve_spacial */ +#define DENOISE3D_STRENGTH_CURVE_SPACIAL +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_h_inv */ +#define DENOISE3D_THR_EDGE_H_INV +#define DENOISE3D_THR_EDGE_H_INV_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_H_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_V 0x0000370C */ +/* Slice: 27:20 denoise3d_strength_curve_temperal */ +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_v_inv */ +#define DENOISE3D_THR_EDGE_V_INV +#define DENOISE3D_THR_EDGE_V_INV_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_V_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_S 0x00003710 */ +/* Slice: 19:0 denoise3d_range_s_inv */ +#define DENOISE3D_RANGE_S_INV +#define DENOISE3D_RANGE_S_INV_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_S_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_T 0x00003714 */ +/* Slice: 29:25 denoise3d_range_t_h */ +#define DENOISE3D_RANGE_T_H +#define DENOISE3D_RANGE_T_H_MASK 0x3E000000U +#define DENOISE3D_RANGE_T_H_SHIFT 25U +/* Slice: 24:20 denoise3d_range_t_v */ +#define DENOISE3D_RANGE_T_V +#define DENOISE3D_RANGE_T_V_MASK 0x01F00000U +#define DENOISE3D_RANGE_T_V_SHIFT 20U +/* Slice: 19 : 0 denoise3d_range_t_inv */ +#define DENOISE3D_RANGE_T_INV +#define DENOISE3D_RANGE_T_INV_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_T_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_MOTION 0x00003718 */ +/* Slice: 24:20 denoise3d_range_d */ +#define DENOISE3D_RANGE_D +#define DENOISE3D_RANGE_D_MASK 0x01F00000U +#define DENOISE3D_RANGE_D_SHIFT 20U +/* Slice: 19 : 0 denoise3d_motion_inv */ +#define DENOISE3D_MOTION_INV +#define DENOISE3D_MOTION_INV_MASK 0x000FFFFFU +#define DENOISE3D_MOTION_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_DELTA_INV 0x0000371C */ +/* Slice: 29:20 denoise3d_delta_h_inv */ +#define DENOISE3D_DELTA_H_INV +#define DENOISE3D_DELTA_H_INV_MASK 0x3FF00000U +#define DENOISE3D_DELTA_H_INV_SHIFT 20U +/* Slice: 19 : 10 denoise3d_delta_v_inv */ +#define DENOISE3D_DELTA_V_INV +#define DENOISE3D_DELTA_V_INV_MASK 0x000FFC00U +#define DENOISE3D_DELTA_V_INV_SHIFT 10U +/* Slice: 9 : 0 denoise3d_delta_t_inv */ +#define DENOISE3D_DELTA_T_INV +#define DENOISE3D_DELTA_T_INV_MASK 0x000003FFU +#define DENOISE3D_DELTA_T_INV_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_S_0 0x00003720 */ +/* Slice: 29:20 denoise3d_spacial_curve0 */ +#define DENOISE3D_SPACIAL_CURVE0 +#define DENOISE3D_SPACIAL_CURVE0_MASK 0x3FF00000U +#define DENOISE3D_SPACIAL_CURVE0_SHIFT 20U +/* Slice: 19 : 10 denoise3d_spacial_curve1 */ +#define DENOISE3D_SPACIAL_CURVE1 +#define DENOISE3D_SPACIAL_CURVE1_MASK 0x000FFC00U +#define DENOISE3D_SPACIAL_CURVE1_SHIFT 10U +/* Slice: 9 : 0 denoise3d_spacial_curve2 */ +#define DENOISE3D_SPACIAL_CURVE2 +#define DENOISE3D_SPACIAL_CURVE2_MASK 0x000003FFU +#define DENOISE3D_SPACIAL_CURVE2_SHIFT 0U +/* Register: ISP_DENOISE3D_CURVE_T_0 0x00003738 */ +/* Slice: 29 : 20 denoise3d_temperal_curve0 */ +#define DENOISE3D_TEMPERAL_CURVE0 +#define DENOISE3D_TEMPERAL_CURVE0_MASK 0x3FF00000U +#define DENOISE3D_TEMPERAL_CURVE0_SHIFT 20U +/* Slice: 19 : 10 denoise3d_temperal_curve1 */ +#define DENOISE3D_TEMPERAL_CURVE1 +#define DENOISE3D_TEMPERAL_CURVE1_MASK 0x000FFC00U +#define DENOISE3D_TEMPERAL_CURVE1_SHIFT 10U +/* Slice: 9 : 0 denoise3d_temperal_curve2 */ +#define DENOISE3D_TEMPERAL_CURVE2 +#define DENOISE3D_TEMPERAL_CURVE2_MASK 0x000003FFU +#define DENOISE3D_TEMPERAL_CURVE2_SHIFT 0U +/* Register: ISP_DENOISE3D_AVERAGE 0x00003750 */ +/* Slice: 31 : 0 denoise3d_frame_average */ +#define DENOISE3D_FRAME_AVERAGE +#define DENOISE3D_FRAME_AVERAGE_MASK 0xFFFFFFFFU +#define DENOISE3D_FRAME_AVERAGE_SHIFT 0U +/* Register: ISP_DENOISE3D_STRENGTH_SHD 0x00003754 */ +/* Slice: 29 : 19 denoise3d_update_temperal_shd */ +#define DENOISE3D_UPDATE_TEMPERAL_SHD +#define DENOISE3D_UPDATE_TEMPERAL_SHD_MASK 0x3FF80000U +#define DENOISE3D_UPDATE_TEMPERAL_SHD_SHIFT 19U +/* Slice: 18 : 8 denoise3d_update_spacial_shd */ +#define DENOISE3D_UPDATE_SPACIAL_SHD +#define DENOISE3D_UPDATE_SPACIAL_SHD_MASK 0x0007FF00U +#define DENOISE3D_UPDATE_SPACIAL_SHD_SHIFT 8U +/* Slice: 7 : 0 denoise3d_strength_shd */ +#define DENOISE3D_STRENGTH_SHD +#define DENOISE3D_STRENGTH_SHD_MASK 0x0000000FU +#define DENOISE3D_STRENGTH_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_H_SHD 0x00003758 */ +/* Slice: 27 : 20 denoise3d_strength_curve_spacial_shd */ +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_h_inv_shd */ +#define DENOISE3D_THR_EDGE_H_INV_SHD +#define DENOISE3D_THR_EDGE_H_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_H_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_EDGE_V_SHD 0x0000375C */ +/* Slice: 27 : 20 denoise3d_strength_curve_temperal_shd */ +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_MASK 0x0FF00000U +#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_thr_edge_v_inv_shd */ +#define DENOISE3D_THR_EDGE_V_INV_SHD +#define DENOISE3D_THR_EDGE_V_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_THR_EDGE_V_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_S_SHD 0x00003760 */ +/* Slice: 19 : 0 denoise3d_range_s_inv_shd */ +#define DENOISE3D_RANGE_S_INV_SHD +#define DENOISE3D_RANGE_S_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_S_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_RANGE_T_SHD 0x00003764 */ +/* Slice: 29 : 25 denoise3d_range_t_h_shd */ +#define DENOISE3D_RANGE_T_H_SHD +#define DENOISE3D_RANGE_T_H_SHD_MASK 0x3E000000U +#define DENOISE3D_RANGE_T_H_SHD_SHIFT 25U +/* Slice: 24 : 20 denoise3d_range_t_v_shd */ +#define DENOISE3D_RANGE_T_V_SHD +#define DENOISE3D_RANGE_T_V_SHD_MASK 0x01F00000U +#define DENOISE3D_RANGE_T_V_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_range_t_inv_shd */ +#define DENOISE3D_RANGE_T_INV_SHD +#define DENOISE3D_RANGE_T_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_RANGE_T_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_MOTION_SHD 0x00003768 */ +/* Slice: 24 : 20 denoise3d_range_d_shd */ +#define DENOISE3D_RANGE_D_SHD +#define DENOISE3D_RANGE_D_SHD_MASK 0x01F00000U +#define DENOISE3D_RANGE_D_SHD_SHIFT 20U +/* Slice: 19 : 0 denoise3d_motion_inv_shd */ +#define DENOISE3D_MOTION_INV_SHD +#define DENOISE3D_MOTION_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_MOTION_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_DELTA_INV_SHD 0x0000376C */ +/* Slice: 29 : 20 denoise3d_delta_h_inv_shd */ +#define DENOISE3D_DELTA_H_INV_SHD +#define DENOISE3D_DELTA_H_INV_SHD_MASK 0x3FF00000U +#define DENOISE3D_DELTA_H_INV_SHD_SHIFT 20U +/* Slice: 19 : 10 denoise3d_delta_v_inv_shd */ +#define DENOISE3D_DELTA_V_INV_SHD +#define DENOISE3D_DELTA_V_INV_SHD_MASK 0x000FFFFFU +#define DENOISE3D_DELTA_V_INV_SHD_SHIFT 10U +/* Slice: 9 : 0 denoise3d_delta_t_inv_shd */ +#define DENOISE3D_DELTA_T_INV_SHD +#define DENOISE3D_DELTA_T_INV_SHD_MASK 0x000003FFU +#define DENOISE3D_DELTA_T_INV_SHD_SHIFT 0U +/* Register: ISP_DENOISE3D_DUMMY_HBLANK 0x00003770 */ +/* Slice: 14 : 0 denoise3d_H_Blank */ +#define DENOISE3D_H_BLANK +#define DENOISE3D_H_BLANK_MASK 0x0000FFFFU +#define DENOISE3D_H_BLANK_SHIFT 0U +/* Register: ISP_DENOISE3D_WEIGHT1 0x00003778 */ +/* Slice: denoise3d_weight_up_y0 */ +#define DENOISE3D_WEIGHT_UP_Y0 +#define DENOISE3D_WEIGHT_UP_Y0_MASK 0x00F00000U +#define DENOISE3D_WEIGHT_UP_Y0_SHIFT 20U +#define DENOISE3D_WEIGHT_UP_Y1 +#define DENOISE3D_WEIGHT_UP_Y1_MASK 0x000F0000U +#define DENOISE3D_WEIGHT_UP_Y1_SHIFT 16U +#define DENOISE3D_WEIGHT +#define DENOISE3D_WEIGHT_MASK 0x0000000FU +#define DENOISE3D_WEIGHT_SHIFT 0U +/*! for miv2 by shenchao */ +/*! Register: miv2_ctrl (0x00001300)*/ +/*! Slice: sp2_raw2_continous:*/ +#define SP2_RAW2_CONTINUOUS +#define SP2_RAW2_CONTINUOUS_MASK 0x1 << 24 +#define SP2_RAW2_CONTINUOUS_SHIFT 24U + +#define SP2_RAW2_START +#define SP2_RAW2_START_MASK 0x1 << 23 +#define SP2_RAW2_START_SHIFT 23U + +#define PP_DMA_CONTINUOUS +#define PP_DMA_CONTINUOUS_MASK 0x1 << 22 +#define PP_DMA_CONTINUOUS_SHIFT 22U + +#define PP_DMA_START +#define PP_DMA_START_MASK 0x1 << 21 +#define PP_DMA_START_SHIFT 21U + +#define SP2_RAW2_WRITE_PATH_ENABLE +#define SP2_RAW2_WRITE_PATH_ENABLE_MASK 0x1 << 20 +#define SP2_RAW2_WRITE_PATH_ENABLE_SHIFT 20U + +#define PP_WRITE_PATH_ENABLE +#define PP_WRITE_PATH_ENABLE_MASK 0x1 << 19 +#define PP_WRITE_PATH_ENABLE_SHIFT 19U + +#define MCM_G2_RAW1_PATH_ENABLE +#define MCM_G2_RAW1_PATH_ENABLE_MASK 0x1 << 18 +#define MCM_G2_RAW1_PATH_ENABLE_SHIFT 18U + +#define MCM_G2_RAW0_PATH_ENABLE +#define MCM_G2_RAW0_PATH_ENABLE_MASK 0x1 << 17 +#define MCM_G2_RAW0_PATH_ENABLE_SHIFT 17U + +//! Register: isp_hdr_exp_conf: Exposure control (0x00000000) +//! Slice: exp_meas_mode: +//! '1' luminance calculation according to +// Y=(R+G+B) x 0.332 (85/256) +// '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B +#define MRV_HDR_EXP_MEAS_MODE +#define MRV_HDR_EXP_MEAS_MODE_MASK 0x80000000U +#define MRV_HDR_EXP_MEAS_MODE_SHIFT 31U +//! Slice: src_select: +#define MRV_HDR_EXP_SRC_SEL +#define MRV_HDR_EXP_SRC_SEL_MASK 0x00000004U +#define MRV_HDR_EXP_SRC_SEL_SHIFT 2U +//! Slice: autostop: +//! '1' stop measuring after a complete frame +// '0' continous measurement +#define MRV_HDR_EXP_AUTOSTOP +#define MRV_HDR_EXP_AUTOSTOP_MASK 0x00000002U +#define MRV_HDR_EXP_AUTOSTOP_SHIFT 1U +//! Slice: exp_start: +//! '1' start measuring a frame. The exp block will reset this bit and halt after completing one frame, if bit "autostop" is set to '1'. +#define MRV_HDR_EXP_START +#define MRV_HDR_EXP_START_MASK 0x00000001U +#define MRV_HDR_EXP_START_SHIFT 0U + +//! Register: isp_hdr_exp_h_offset: Horizontal offset for first block (0x00000004) +#define MRV_ISP_HDR_EXP_H_OFFSET +#define MRV_ISP_HDR_EXP_H_OFFSET_MASK 0x00001FFFU +#define MRV_ISP_HDR_EXP_H_OFFSET_SHIFT 0U + +//! Register: isp_hdr_exp_v_offset: Vertical offset for first block (0x00000008) +#define MRV_ISP_HDR_EXP_V_OFFSET +#define MRV_ISP_HDR_EXP_V_OFFSET_MASK 0x00001FFFU +#define MRV_ISP_HDR_EXP_V_OFFSET_SHIFT 0U + +//! Register: isp_exp_h_size: Horizontal size of one block (0x0000000c) +#define MRV_ISP_HDR_EXP_H_SIZE +#define MRV_ISP_HDR_EXP_H_SIZE_MASK 0x000007FFU +#define MRV_ISP_HDR_EXP_H_SIZE_SHIFT 0U + +//! Register: isp_exp_v_size: Vertical size of one block (0x00000010) +#define MRV_ISP_HDR_EXP_V_SIZE +#define MRV_ISP_HDR_EXP_V_SIZE_MASK 0x000007FEU +#define MRV_ISP_HDR_EXP_V_SIZE_SHIFT 0U +/*! for miv2 by shenchao */ +/*! Register: miv2_ctrl (0x00001300)*/ +/*! Slice: mcm_raw_rdma_start_con:*/ +#define MCM_RAW_RDMA_START_CON +#define MCM_RAW_RDMA_START_CON_MASK 0x00010000U +#define MCM_RAW_RDMA_START_CON_SHIFT 16U +/*! Slice: mcm_raw_rdma_start:*/ +#define MCM_RAW_RDMA_START +#define MCM_RAW_RDMA_START_MASK 0x00008000U +#define MCM_RAW_RDMA_START_SHIFT 15U +/*! Slice: mcm_raw_rdma_path_enable:*/ +#define MCM_RAW_RDMA_PATH_ENABLE +#define MCM_RAW_RDMA_PATH_ENABLE_MASK 0x00004000U +#define MCM_RAW_RDMA_PATH_ENABLE_SHIFT 14U +/*! Slice: sp2_raw2_rdma_start_con:*/ +#define SP2_RAW2_RDMA_START_CON +#define SP2_RAW2_RDMA_START_CON_MASK 0x01000000U +#define SP2_RAW2_RDMA_START_CON_SHIFT 24U +/*! Slice: sp2_raw2_rdma_start:*/ +#define SP2_RAW2_RDMA_START +#define SP2_RAW2_RDMA_START_MASK 0x00800000U +#define SP2_RAW2_RDMA_START_SHIFT 23U +/*! Slice: sp2_raw_rdma_start_con:*/ +#define SP2_RAW_RDMA_START_CON +#define SP2_RAW_RDMA_START_CON_MASK 0x00002000U +#define SP2_RAW_RDMA_START_CON_SHIFT 13U +/*! Slice: sp2_raw_rdma_start:*/ +#define SP2_RAW_RDMA_START +#define SP2_RAW_RDMA_START_MASK 0x00001000U +#define SP2_RAW_RDMA_START_SHIFT 12U +/*! Slice: sp2_raw_rdma_path_enable:*/ +#define SP2_RAW_RDMA_PATH_ENABLE +#define SP2_RAW_RDMA_PATH_ENABLE_MASK 0x00000800U +#define SP2_RAW_RDMA_PATH_ENABLE_SHIFT 11U +/*! Slice: sp2_ycbcr_rdma_start_con:*/ +#define SP2_YCBCR_RDMA_START_CON +#define SP2_YCBCR_RDMA_START_CON_MASK 0x00000400U +#define SP2_YCBCR_RDMA_START_CON_SHIFT 10U +/*! Slice: sp2_ycbcr_rdma_start:*/ +#define SP2_YCBCR_RDMA_START +#define SP2_YCBCR_RDMA_START_MASK 0x00000200U +#define SP2_YCBCR_RDMA_START_SHIFT 9U +/*! Slice: sp2_ycbcr_rdma_path_enable:*/ +#define SP2_YCBCR_RDMA_PATH_ENABLE +#define SP2_YCBCR_RDMA_PATH_ENABLE_MASK 0x00000100U +#define SP2_YCBCR_RDMA_PATH_ENABLE_SHIFT 8U +/*! Slice: mcm_raw1_path_enable:*/ +#define MCM_RAW1_PATH_ENABLE +#define MCM_RAW1_PATH_ENABLE_MASK 0x00000080U +#define MCM_RAW1_PATH_ENABLE_SHIFT 7U +/*! Slice: mcm_raw0_path_enable:*/ +#define MCM_RAW0_PATH_ENABLE +#define MCM_RAW0_PATH_ENABLE_MASK 0x00000040U +#define MCM_RAW0_PATH_ENABLE_SHIFT 6U +/*! Slice: sp2_raw_path_enable:*/ +#define SP2_RAW_PATH_ENABLE +#define SP2_RAW_PATH_ENABLE_MASK 0x00000020U +#define SP2_RAW_PATH_ENABLE_SHIFT 5U +/*! Slice: sp2_ycbcr_path_enable:*/ +#define SP2_YCBCR_PATH_ENABLE +#define SP2_YCBCR_PATH_ENABLE_MASK 0x00000010U +#define SP2_YCBCR_PATH_ENABLE_SHIFT 4U +/*! Slice: sp1_ycbcr_path_enable:*/ +#define SP1_YCBCR_PATH_ENABLE +#define SP1_YCBCR_PATH_ENABLE_MASK 0x00000008U +#define SP1_YCBCR_PATH_ENABLE_SHIFT 3U +/*! Slice: mp_jdp_path_enable:*/ +#define MP_JDP_PATH_ENABLE +#define MP_JDP_PATH_ENABLE_MASK 0x00000004U +#define MP_JDP_PATH_ENABLE_SHIFT 2U +/*! Slice: mp_raw_path_enable:*/ +#define MP_RAW_PATH_ENABLE +#define MP_RAW_PATH_ENABLE_MASK 0x00000002U +#define MP_RAW_PATH_ENABLE_SHIFT 1U +/*! Slice: mp_ycbcr_path_enable:*/ +#define MP_YCBCR_PATH_ENABLE +#define MP_YCBCR_PATH_ENABLE_MASK 0x00000001U +#define MP_YCBCR_PATH_ENABLE_SHIFT 0U +/*! Register: miv2_ctrl_shd (0x00001304)*/ +/*! Slice: mcm_raw_rdma_start_con:*/ +#define MCM_RAW_RDMA_START_CON +#define MCM_RAW_RDMA_START_CON_MASK 0x00010000U +#define MCM_RAW_RDMA_START_CON_SHIFT 16U +/*! Slice: mcm_raw_rdma_start:*/ +#define MCM_RAW_RDMA_START +#define MCM_RAW_RDMA_START_MASK 0x00008000U +#define MCM_RAW_RDMA_START_SHIFT 15U +/*! Slice: mcm_raw_rdma_path_enable:*/ +#define MCM_RAW_RDMA_PATH_ENABLE +#define MCM_RAW_RDMA_PATH_ENABLE_MASK 0x00004000U +#define MCM_RAW_RDMA_PATH_ENABLE_SHIFT 14U +/*! Slice: sp2_raw_rdma_start_con:*/ +#define SP2_RAW_RDMA_START_CON +#define SP2_RAW_RDMA_START_CON_MASK 0x00002000U +#define SP2_RAW_RDMA_START_CON_SHIFT 13U +/*! Slice: sp2_raw_rdma_start:*/ +#define SP2_RAW_RDMA_START +#define SP2_RAW_RDMA_START_MASK 0x00001000U +#define SP2_RAW_RDMA_START_SHIFT 12U +/*! Slice: sp2_raw_rdma_path_enable:*/ +#define SP2_RAW_RDMA_PATH_ENABLE +#define SP2_RAW_RDMA_PATH_ENABLE_MASK 0x00000800U +#define SP2_RAW_RDMA_PATH_ENABLE_SHIFT 11U +/*! Slice: sp2_ycbcr_rdma_start_con:*/ +#define SP2_YCBCR_RDMA_START_CON +#define SP2_YCBCR_RDMA_START_CON_MASK 0x00000400U +#define SP2_YCBCR_RDMA_START_CON_SHIFT 10U +/*! Slice: sp2_ycbcr_rdma_start:*/ +#define SP2_YCBCR_RDMA_START +#define SP2_YCBCR_RDMA_START_MASK 0x00000200U +#define SP2_YCBCR_RDMA_START_SHIFT 9U +/*! Slice: sp2_ycbcr_rdma_path_enable:*/ +#define SP2_YCBCR_RDMA_PATH_ENABLE +#define SP2_YCBCR_RDMA_PATH_ENABLE_MASK 0x00000100U +#define SP2_YCBCR_RDMA_PATH_ENABLE_SHIFT 8U +/*! Slice: mcm_raw1_path_enable:*/ +#define MCM_RAW1_PATH_ENABLE +#define MCM_RAW1_PATH_ENABLE_MASK 0x00000080U +#define MCM_RAW1_PATH_ENABLE_SHIFT 7U +/*! Slice: mcm_raw0_path_enable:*/ +#define MCM_RAW0_PATH_ENABLE +#define MCM_RAW0_PATH_ENABLE_MASK 0x00000040U +#define MCM_RAW0_PATH_ENABLE_SHIFT 6U +/*! Slice: sp2_raw_path_enable:*/ +#define SP2_RAW_PATH_ENABLE +#define SP2_RAW_PATH_ENABLE_MASK 0x00000020U +#define SP2_RAW_PATH_ENABLE_SHIFT 5U +/*! Slice: sp2_ycbcr_path_enable:*/ +#define SP2_YCBCR_PATH_ENABLE +#define SP2_YCBCR_PATH_ENABLE_MASK 0x00000010U +#define SP2_YCBCR_PATH_ENABLE_SHIFT 4U +/*! Slice: sp1_ycbcr_path_enable:*/ +#define SP1_YCBCR_PATH_ENABLE +#define SP1_YCBCR_PATH_ENABLE_MASK 0x00000008U +#define SP1_YCBCR_PATH_ENABLE_SHIFT 3U +/*! Slice: mp_jdp_path_enable:*/ +#define MP_JDP_PATH_ENABLE +#define MP_JDP_PATH_ENABLE_MASK 0x00000004U +#define MP_JDP_PATH_ENABLE_SHIFT 2U +/*! Slice: mp_raw_path_enable:*/ +#define MP_RAW_PATH_ENABLE +#define MP_RAW_PATH_ENABLE_MASK 0x00000002U +#define MP_RAW_PATH_ENABLE_SHIFT 1U +/*! Slice: mp_ycbcr_path_enable:*/ +#define MP_YCBCR_PATH_ENABLE +#define MP_YCBCR_PATH_ENABLE_MASK 0x00000001U +#define MP_YCBCR_PATH_ENABLE_SHIFT 0U +/*! Register: miv2_mp_ctrl (0x00001310)*/ +/*! Slice: mp_init_offset_en:*/ +#define MP_INIT_OFFSET_EN +#define MP_INIT_OFFSET_EN_MASK 0x00000020U +#define MP_INIT_OFFSET_EN_SHIFT 5U +/*! Slice: mp_init_base_en:*/ +#define MP_INIT_BASE_EN +#define MP_INIT_BASE_EN_MASK 0x00000010U +#define MP_INIT_BASE_EN_SHIFT 4U +/*! Slice: mp_miv2_cfg_upd:*/ +#define MP_MI_CFG_UPD +#define MP_MI_CFG_UPD_MASK 0x00000008U +#define MP_MI_CFG_UPD_SHIFT 3U +/*! Slice: mp_miv2_skip:*/ +#define MP_MI_SKIP +#define MP_MI_SKIP_MASK 0x00000004U +#define MP_MI_SKIP_SHIFT 2U +/*! Slice: mp_auto_update:*/ +#define MP_AUTO_UPDATE +#define MP_AUTO_UPDATE_MASK 0x00000002U +#define MP_AUTO_UPDATE_SHIFT 1U +/*! Slice: mp_pingpong_enable:*/ +#define MP_PINGPONG_ENABLE +#define MP_PINGPONG_ENABLE_MASK 0x00000001U +#define MP_PINGPONG_ENABLE_SHIFT 0U +/*! Register: miv2_mp_fmt (0x00001314)*/ +/*! Slice: mp_wr_jdp_dp_bit:*/ +#define MP_WR_JDP_DP_BIT +#define MP_WR_JDP_DP_BIT_MASK 0x000020000U +#define MP_WR_JDP_DP_BIT_SHIFT 17U + +/*! Slice: mp_wr_yuv_nvy:*/ +#define MP_WR_YUV_NVY +#define MP_WR_YUV_NVY_MASK 0x00006000U +#define MP_WR_YUV_NVY_SHIFT 13U +/*! Slice: mp_wr_yuv_nv21:*/ +#define MP_WR_YUV_NV21 +#define MP_WR_YUV_NV21_MASK 0x00001000U +#define MP_WR_YUV_NV21_SHIFT 12U +/*! Slice: mp_wr_raw_aligned:*/ +#define MP_WR_RAW_ALIGNED +#define MP_WR_RAW_ALIGNED_MASK 0x00000C00U +#define MP_WR_RAW_ALIGNED_SHIFT 10U +/*! Slice: mp_wr_yuv_aligned:*/ +#define MP_WR_YUV_ALIGNED +#define MP_WR_YUV_ALIGNED_MASK 0x00000200U +#define MP_WR_YUV_ALIGNED_SHIFT 9U +/*! Slice: mp_wr_raw_bit:*/ +#define MP_WR_RAW_BIT +#define MP_WR_RAW_BIT_MASK 0x000001C0U +#define MP_WR_RAW_BIT_SHIFT 6U +/*! Slice: mp_wr_yuv_str:*/ +#define MP_WR_YUV_STR +#define MP_WR_YUV_STR_MASK 0x00000030U +#define MP_WR_YUV_STR_SHIFT 4U +/*! Slice: mp_wr_yuv_fmt:*/ +#define MP_WR_YUV_FMT +#define MP_WR_YUV_FMT_MASK 0x0000000CU +#define MP_WR_YUV_FMT_SHIFT 2U +/*! Slice: mp_wr_yuv_bit:*/ +#define MP_WR_YUV_BIT +#define MP_WR_YUV_BIT_MASK 0x00000002U +#define MP_WR_YUV_BIT_SHIFT 1U +/*! Slice: mp_wr_jdp_fmt:*/ +#define MP_WR_JDP_FMT +#define MP_WR_JDP_FMT_MASK 0x00000001U +#define MP_WR_JDP_FMT_SHIFT 0U +/*! Register: miv2_mp_bus_cfg (0x00001318)*/ +/*! Slice: mp_wr_swap_jdp:*/ +#define MP_WR_SWAP_JDP +#define MP_WR_SWAP_JDP_MASK 0x0F000000U +#define MP_WR_SWAP_JDP_SHIFT 24U +/*! Slice: mp_wr_swap_raw:*/ +#define MP_WR_SWAP_RAW +#define MP_WR_SWAP_RAW_MASK 0x00F00000U +#define MP_WR_SWAP_RAW_SHIFT 20U +/*! Slice: mp_wr_swap_v:*/ +#define MP_WR_SWAP_V +#define MP_WR_SWAP_V_MASK 0x000F0000U +#define MP_WR_SWAP_V_SHIFT 16U +/*! Slice: mp_wr_swap_u:*/ +#define MP_WR_SWAP_U +#define MP_WR_SWAP_U_MASK 0x0000F000U +#define MP_WR_SWAP_U_SHIFT 12U +/*! Slice: mp_wr_swap_y:*/ +#define MP_WR_SWAP_Y +#define MP_WR_SWAP_Y_MASK 0x00000F00U +#define MP_WR_SWAP_Y_SHIFT 8U +/*! Slice: mp_rd_issue_cap:*/ +#define MP_RD_ISSUE_CAP +#define MP_RD_ISSUE_CAP_MASK 0x000000C0U +#define MP_RD_ISSUE_CAP_SHIFT 6U +/*! Slice: mp_wr_issue_cap:*/ +#define MP_WR_ISSUE_CAP +#define MP_WR_ISSUE_CAP_MASK 0x00000030U +#define MP_WR_ISSUE_CAP_SHIFT 4U +/*! Slice: mp_rd_burst_len:*/ +#define MP_RD_BURST_LEN +#define MP_RD_BURST_LEN_MASK 0x0000000CU +#define MP_RD_BURST_LEN_SHIFT 2U +/*! Slice: mp_wr_burst_len:*/ +#define MP_WR_BURST_LEN +#define MP_WR_BURST_LEN_MASK 0x00000003U +#define MP_WR_BURST_LEN_SHIFT 0U +/*! Register: miv2_mp_bus_id (0x0000131c)*/ +/*! Slice: mp_bus_sw_en:*/ +#define MP_BUS_SW_EN +#define MP_BUS_SW_EN_MASK 0x02000000U +#define MP_BUS_SW_EN_SHIFT 25U +/*! Slice: mp_rd_id_en:*/ +#define MP_RD_ID_EN +#define MP_RD_ID_EN_MASK 0x01000000U +#define MP_RD_ID_EN_SHIFT 24U +/*! Slice: mp_rd_id_cfg:*/ +#define MP_RD_ID_CFG +#define MP_RD_ID_CFG_MASK 0x00FF0000U +#define MP_RD_ID_CFG_SHIFT 16U +/*! Slice: mp_wr_id_en:*/ +#define MP_WR_ID_EN +#define MP_WR_ID_EN_MASK 0x00000100U +#define MP_WR_ID_EN_SHIFT 8U +/*! Slice: mp_wr_id_cfg:*/ +#define MP_WR_ID_CFG +#define MP_WR_ID_CFG_MASK 0x000000FFU +#define MP_WR_ID_CFG_SHIFT 0U +/*! Register: miv2_mp_bus_timeo (0x00001320)*/ +/*! Slice: mp_bus_timeo_en:*/ +#define MP_BUS_TIMEO_EN +#define MP_BUS_TIMEO_EN_MASK 0x80000000U +#define MP_BUS_TIMEO_EN_SHIFT 31U +/*! Slice: mp_bus_timeo:*/ +#define MP_BUS_TIMEO +#define MP_BUS_TIMEO_MASK 0x7FFFFFFEU +#define MP_BUS_TIMEO_SHIFT 1U + +/*! Slice: mp_bus_timeo_interrupt_disable:*/ +/*! 0 enable 1 disable*/ +#define MP_BUS_TIMEO_INTERRUPT_DISABLE +#define MP_BUS_TIMEO_INTERRUPT_DISABLE_MASK 1U +#define MP_BUS_TIMEO_INTERRUPT_DISABLE_SHIFT 0U +/*! Register: miv2_mp_y_base_ad_init (0x00001324)*/ +/*! Slice: mp_y_base_ad_init:*/ +#define MP_Y_BASE_AD_INIT +#define MP_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MP_Y_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mp_y_size_init (0x00001328)*/ +/*! Slice: mp_y_size_init:*/ +#define MP_Y_SIZE_INIT +#define MP_Y_SIZE_INIT_MASK 0x1FFFFFF0U +#define MP_Y_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mp_y_offs_cnt_init (0x0000132c)*/ +/*! Slice: mp_y_offs_cnt_init:*/ +#define MP_Y_OFFS_CNT_INIT +#define MP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define MP_Y_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mp_y_llength (0x00001330)*/ +/*! Slice: mp_y_llengh:*/ +#define MP_Y_LLENGH +#define MP_Y_LLENGH_MASK 0x00007FFFU +#define MP_Y_LLENGH_SHIFT 0U +/*! Register: miv2_mp_y_pic_width (0x00001334)*/ +/*! Slice: mp_y_pic_width:*/ +#define MP_Y_PIC_WIDTH +#define MP_Y_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MP_Y_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mp_y_pic_height (0x00001338)*/ +/*! Slice: mp_y_pic_height:*/ +#define MP_Y_PIC_HEIGHT +#define MP_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MP_Y_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_mp_y_pic_size (0x0000133c)*/ +/*! Slice: mp_y_pic_size:*/ +#define MP_Y_PIC_SIZE +#define MP_Y_PIC_SIZE_MASK 0xFFFFFFFFU +#define MP_Y_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mp_cb_base_ad_init (0x00001340)*/ +/*! Slice: mp_cb_base_ad_init:*/ +#define MP_CB_BASE_AD_INIT +#define MP_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MP_CB_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mp_cb_size_init (0x00001344)*/ +/*! Slice: mp_cb_size_init:*/ +#define MP_CB_SIZE_INIT +#define MP_CB_SIZE_INIT_MASK 0x0FFFFFF0U +#define MP_CB_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mp_cb_offs_cnt_init (0x00001348)*/ +/*! Slice: mp_cb_offs_cnt_init:*/ +#define MP_CB_OFFS_CNT_INIT +#define MP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define MP_CB_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mp_cr_base_ad_init (0x0000134c)*/ +/*! Slice: mp_cr_base_ad_init:*/ +#define MP_CR_BASE_AD_INIT +#define MP_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MP_CR_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mp_cr_size_init (0x00001350)*/ +/*! Slice: mp_cr_size_init:*/ +#define MP_CR_SIZE_INIT +#define MP_CR_SIZE_INIT_MASK 0x0FFFFFF0U +#define MP_CR_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mp_cr_offs_cnt_init (0x00001354)*/ +/*! Slice: mp_cr_offs_cnt_init:*/ +#define MP_CR_OFFS_CNT_INIT +#define MP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define MP_CR_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mp_y_base_ad_init2 (0x00001358)*/ +/*! Slice: mp_y_base_ad_init2:*/ +#define MP_Y_BASE_AD_INIT2 +#define MP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define MP_Y_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_mp_cb_base_ad_init2 (0x0000135c)*/ +/*! Slice: mp_cb_base_ad_init2:*/ +#define MP_CB_BASE_AD_INIT2 +#define MP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define MP_CB_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_mp_cr_base_ad_init2 (0x00001360)*/ +/*! Slice: mp_cr_base_ad_init2:*/ +#define MP_CR_BASE_AD_INIT2 +#define MP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define MP_CR_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_mp_y_offs_cnt_start (0x00001364)*/ +/*! Slice: mp_y_offs_cnt_start:*/ +#define MP_Y_OFFS_CNT_START +#define MP_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define MP_Y_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mp_cb_offs_cnt_start (0x00001368)*/ +/*! Slice: mp_cb_offs_cnt_start:*/ +#define MP_CB_OFFS_CNT_START +#define MP_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define MP_CB_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mp_cr_offs_cnt_start (0x0000136c)*/ +/*! Slice: mp_cr_offs_cnt_start:*/ +#define MP_CR_OFFS_CNT_START +#define MP_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define MP_CR_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mp_y_base_ad_shd (0x00001370)*/ +/*! Slice: mp_y_base_ad:*/ +#define MP_Y_BASE_AD +#define MP_Y_BASE_AD_MASK 0xFFFFFFF0U +#define MP_Y_BASE_AD_SHIFT 4U +/*! Register: miv2_mp_y_size_shd (0x00001374)*/ +/*! Slice: mp_y_size:*/ +#define MP_Y_SIZE +#define MP_Y_SIZE_MASK 0x1FFFFFF0U +#define MP_Y_SIZE_SHIFT 4U +/*! Register: miv2_mp_y_offs_cnt_shd (0x00001378)*/ +/*! Slice: mp_y_offs_cnt:*/ +#define MP_Y_OFFS_CNT +#define MP_Y_OFFS_CNT_MASK 0x1FFFFFF0U +#define MP_Y_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mp_cb_base_ad_shd (0x0000137c)*/ +/*! Slice: mp_cb_base_ad:*/ +#define MP_CB_BASE_AD +#define MP_CB_BASE_AD_MASK 0xFFFFFFF0U +#define MP_CB_BASE_AD_SHIFT 4U +/*! Register: miv2_mp_cb_size_shd (0x00001380)*/ +/*! Slice: mp_cb_size:*/ +#define MP_CB_SIZE +#define MP_CB_SIZE_MASK 0x0FFFFFF0U +#define MP_CB_SIZE_SHIFT 4U +/*! Register: miv2_mp_cb_offs_cnt_shd (0x00001384)*/ +/*! Slice: mp_cb_offs_cnt:*/ +#define MP_CB_OFFS_CNT +#define MP_CB_OFFS_CNT_MASK 0x0FFFFFF0U +#define MP_CB_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mp_cr_base_ad_shd (0x00001388)*/ +/*! Slice: mp_cr_base_ad:*/ +#define MP_CR_BASE_AD +#define MP_CR_BASE_AD_MASK 0xFFFFFFF0U +#define MP_CR_BASE_AD_SHIFT 4U +/*! Register: miv2_mp_cr_size_shd (0x0000138c)*/ +/*! Slice: mp_cr_size:*/ +#define MP_CR_SIZE +#define MP_CR_SIZE_MASK 0x0FFFFFF0U +#define MP_CR_SIZE_SHIFT 4U +/*! Register: miv2_mp_cr_offs_cnt_shd (0x00001390)*/ +/*! Slice: mp_cr_offs_cnt:*/ +#define MP_CR_OFFS_CNT +#define MP_CR_OFFS_CNT_MASK 0x0FFFFFF0U +#define MP_CR_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mp_raw_base_ad_init (0x00001394)*/ +/*! Slice: mp_raw_base_ad_init:*/ +#define MP_RAW_BASE_AD_INIT +#define MP_RAW_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MP_RAW_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mp_raw_size_init (0x00001398)*/ +/*! Slice: mp_raw_size_init:*/ +#define MP_RAW_SIZE_INIT +#define MP_RAW_SIZE_INIT_MASK 0x1FFFFFF0U +#define MP_RAW_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mp_raw_offs_cnt_init (0x0000139c)*/ +/*! Slice: mp_raw_offs_cnt_init:*/ +#define MP_RAW_OFFS_CNT_INIT +#define MP_RAW_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define MP_RAW_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mp_raw_llength (0x000013a0)*/ +/*! Slice: mp_raw_llengh:*/ +#define MP_RAW_LLENGH +#define MP_RAW_LLENGH_MASK 0x00007FFFU +#define MP_RAW_LLENGH_SHIFT 0U +/*! Register: miv2_mp_raw_pic_width (0x000013a4)*/ +/*! Slice: mp_raw_pic_width:*/ +#define MP_RAW_PIC_WIDTH +#define MP_RAW_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MP_RAW_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mp_raw_pic_height (0x000013a8)*/ +/*! Slice: mp_raw_pic_height:*/ +#define MP_RAW_PIC_HEIGHT +#define MP_RAW_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MP_RAW_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_mp_raw_pic_size (0x000013ac)*/ +/*! Slice: mp_raw_pic_size:*/ +#define MP_RAW_PIC_SIZE +#define MP_RAW_PIC_SIZE_MASK 0xFFFFFFFFU +#define MP_RAW_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mp_raw_offs_cnt_start (0x000013b0)*/ +/*! Slice: mp_raw_offs_cnt_start:*/ +#define MP_RAW_OFFS_CNT_START +#define MP_RAW_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define MP_RAW_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mp_raw_base_ad_shd (0x000013b4)*/ +/*! Slice: mp_raw_base_ad:*/ +#define MP_RAW_BASE_AD +#define MP_RAW_BASE_AD_MASK 0xFFFFFFF0U +#define MP_RAW_BASE_AD_SHIFT 4U +/*! Register: miv2_mp_raw_size_shd (0x000013b8)*/ +/*! Slice: mp_raw_size:*/ +#define MP_RAW_SIZE +#define MP_RAW_SIZE_MASK 0x1FFFFFF0U +#define MP_RAW_SIZE_SHIFT 4U +/*! Register: miv2_mp_raw_offs_cnt_shd (0x000013bc)*/ +/*! Slice: mp_raw_offs_cnt:*/ +#define MP_RAW_OFFS_CNT +#define MP_RAW_OFFS_CNT_MASK 0x1FFFFFF0U +#define MP_RAW_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mp_jdp_base_ad_init (0x000013c0)*/ +/*! Slice: mp_jdp_base_ad_init:*/ +#define MP_JDP_BASE_AD_INIT +#define MP_JDP_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MP_JDP_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mp_jdp_size_init (0x000013c4)*/ +/*! Slice: mp_jdp_size_init:*/ +#define MP_JDP_SIZE_INIT +#define MP_JDP_SIZE_INIT_MASK 0x1FFFFFF0U +#define MP_JDP_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mp_jdp_offs_cnt_init (0x000013c8)*/ +/*! Slice: mp_jdp_offs_cnt_init:*/ +#define MP_JDP_OFFS_CNT_INIT +#define MP_JDP_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define MP_JDP_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mp_jdp_llength (0x000013cc)*/ +/*! Slice: mp_jdp_llengh:*/ +#define MP_JDP_LLENGH +#define MP_JDP_LLENGH_MASK 0x00007FFFU +#define MP_JDP_LLENGH_SHIFT 0U +/*! Register: miv2_mp_jdp_pic_width (0x000013d0)*/ +/*! Slice: mp_jdp_pic_width:*/ +#define MP_JDP_PIC_WIDTH +#define MP_JDP_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MP_JDP_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mp_jdp_pic_height (0x000013d4)*/ +/*! Slice: mp_jdp_pic_height:*/ +#define MP_JDP_PIC_HEIGHT +#define MP_JDP_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MP_JDP_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_mp_jdp_pic_size (0x000013d8)*/ +/*! Slice: mp_jdp_pic_size:*/ +#define MP_JDP_PIC_SIZE +#define MP_JDP_PIC_SIZE_MASK 0xFFFFFFFFU +#define MP_JDP_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mp_jdp_offs_cnt_start (0x000013dc)*/ +/*! Slice: mp_jdp_offs_cnt_start:*/ +#define MP_JDP_OFFS_CNT_START +#define MP_JDP_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define MP_JDP_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mp_jdp_base_ad_shd (0x000013e0)*/ +/*! Slice: mp_jdp_base_ad:*/ +#define MP_JDP_BASE_AD +#define MP_JDP_BASE_AD_MASK 0xFFFFFFF0U +#define MP_JDP_BASE_AD_SHIFT 4U +/*! Register: miv2_mp_jdp_size_shd (0x000013e4)*/ +/*! Slice: mp_jdp_size:*/ +#define MP_JDP_SIZE +#define MP_JDP_SIZE_MASK 0x1FFFFFF0U +#define MP_JDP_SIZE_SHIFT 4U +/*! Register: miv2_mp_jdp_offs_cnt_shd (0x000013e8)*/ +/*! Slice: mp_jdp_offs_cnt:*/ +#define MP_JDP_OFFS_CNT +#define MP_JDP_OFFS_CNT_MASK 0x1FFFFFF0U +#define MP_JDP_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mp_status_clr (0x000013ec) */ +/*! Slice: mp_jdp_fifo_full: */ +#define MP_JDP_FIFO_FULL +#define MP_JDP_FIFO_FULL_MASK 0x00000010U +#define MP_JDP_FIFO_FULL_SHIFT 4U +/*! Slice: mp_raw_fifo_full:*/ +#define MP_RAW_FIFO_FULL +#define MP_RAW_FIFO_FULL_MASK 0x00000008U +#define MP_RAW_FIFO_FULL_SHIFT 3U +/*! Slice: mp_cr_fifo_full:*/ +#define MP_CR_FIFO_FULL +#define MP_CR_FIFO_FULL_MASK 0x00000004U +#define MP_CR_FIFO_FULL_SHIFT 2U +/*! Slice: mp_cb_fifo_full:*/ +#define MP_CB_FIFO_FULL +#define MP_CB_FIFO_FULL_MASK 0x00000002U +#define MP_CB_FIFO_FULL_SHIFT 1U +/*! Slice: mp_y_fifo_full:*/ +#define MP_Y_FIFO_FULL +#define MP_Y_FIFO_FULL_MASK 0x00000001U +#define MP_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_mp_ctrl_status (0x000013f0) */ +/*! Slice: mp_jdp_fifo_full: */ +#define MP_JDP_FIFO_FULL +#define MP_JDP_FIFO_FULL_MASK 0x00000010U +#define MP_JDP_FIFO_FULL_SHIFT 4U +/*! Slice: mp_raw_fifo_full: */ +#define MP_RAW_FIFO_FULL +#define MP_RAW_FIFO_FULL_MASK 0x00000008U +#define MP_RAW_FIFO_FULL_SHIFT 3U +/*! Slice: mp_cr_fifo_full: */ +#define MP_CR_FIFO_FULL +#define MP_CR_FIFO_FULL_MASK 0x00000004U +#define MP_CR_FIFO_FULL_SHIFT 2U +/*! Slice: mp_cb_fifo_full: */ +#define MP_CB_FIFO_FULL +#define MP_CB_FIFO_FULL_MASK 0x00000002U +#define MP_CB_FIFO_FULL_SHIFT 1U +/*! Slice: mp_y_fifo_full: */ +#define MP_Y_FIFO_FULL +#define MP_Y_FIFO_FULL_MASK 0x00000001U +#define MP_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_mp_axi_status (0x000013f4) */ +/*! Slice: agsw_enc_pic_rdy: */ +#define AGSW_ENC_PIC_RDY +#define AGSW_ENC_PIC_RDY_MASK 0x00000002U +#define AGSW_ENC_PIC_RDY_SHIFT 1U +/*! Slice: agsw_enc_buf_full:*/ +#define AGSW_ENC_BUF_FULL +#define AGSW_ENC_BUF_FULL_MASK 0x00000001U +#define AGSW_ENC_BUF_FULL_SHIFT 0U +/*! Register: miv2_mp_raw_byte_cnt_status (0x000013f8)*/ +/*! Slice: mp_raw_byte_cnt_status:*/ +#define MP_RAW_BYTE_CNT_STATUS +#define MP_RAW_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU +#define MP_RAW_BYTE_CNT_STATUS_SHIFT 0U +/*! Register: miv2_mp_jdp_byte_cnt_status (0x000013fc)*/ +/*! Slice: mp_jdp_byte_cnt_status:*/ +#define MP_JDP_BYTE_CNT_STATUS +#define MP_JDP_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU +#define MP_JDP_BYTE_CNT_STATUS_SHIFT 0U +/*! Register: miv2_mp_dp_byte_cnt_status (0x00001400)*/ +/*! Slice: mp_dp_byte_cnt_status:*/ +#define MP_DP_BYTE_CNT_STATUS +#define MP_DP_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU +#define MP_DP_BYTE_CNT_STATUS_SHIFT 0U +/*! Register: miv2_sp1_ctrl (0x0000142c)*/ +/*! Slice: sp1_init_offset_en:*/ +#define SP1_INIT_OFFSET_EN +#define SP1_INIT_OFFSET_EN_MASK 0x00000020U +#define SP1_INIT_OFFSET_EN_SHIFT 5U +/*! Slice: sp1_init_base_en:*/ +#define SP1_INIT_BASE_EN +#define SP1_INIT_BASE_EN_MASK 0x00000010U +#define SP1_INIT_BASE_EN_SHIFT 4U +/*! Slice: sp1_miv2_cfg_upd:*/ +#define SP1_MI_CFG_UPD +#define SP1_MI_CFG_UPD_MASK 0x00000008U +#define SP1_MI_CFG_UPD_SHIFT 3U +/*! Slice: sp1_miv2_skip:*/ +#define SP1_MI_SKIP +#define SP1_MI_SKIP_MASK 0x00000004U +#define SP1_MI_SKIP_SHIFT 2U +/*! Slice: sp1_auto_update:*/ +#define SP1_AUTO_UPDATE +#define SP1_AUTO_UPDATE_MASK 0x00000002U +#define SP1_AUTO_UPDATE_SHIFT 1U +/*! Slice: sp1_pingpong_enable:*/ +#define SP1_PINGPONG_ENABLE +#define SP1_PINGPONG_ENABLE_MASK 0x00000001U +#define SP1_PINGPONG_ENABLE_SHIFT 0U +/*! Register: miv2_sp1_fmt (0x00001430)*/ +/*! Slice: sp1_wr_yuv_nvy:*/ +#define SP1_WR_YUV_NVY +#define SP1_WR_YUV_NVY_MASK 0x00000180U +#define SP1_WR_YUV_NVY_SHIFT 7U +/*! Slice: sp1_wr_yuv_nv21:*/ +#define SP1_WR_YUV_NV21 +#define SP1_WR_YUV_NV21_MASK 0x00000040U +#define SP1_WR_YUV_NV21_SHIFT 6U +/*! Slice: sp1_wr_yuv_aligned:*/ +#define SP1_WR_YUV_ALIGNED +#define SP1_WR_YUV_ALIGNED_MASK 0x00000020U +#define SP1_WR_YUV_ALIGNED_SHIFT 5U +/*! Slice: sp1_wr_yuv_str:*/ +#define SP1_WR_YUV_STR +#define SP1_WR_YUV_STR_MASK 0x00000018U +#define SP1_WR_YUV_STR_SHIFT 3U +/*! Slice: sp1_wr_yuv_fmt:*/ +#define SP1_WR_YUV_FMT +#define SP1_WR_YUV_FMT_MASK 0x00000006U +#define SP1_WR_YUV_FMT_SHIFT 1U +/*! Slice: sp1_wr_yuv_bit:*/ +#define SP1_WR_YUV_BIT +#define SP1_WR_YUV_BIT_MASK 0x00000001U +#define SP1_WR_YUV_BIT_SHIFT 0U +/*! Register: miv2_sp1_bus_cfg (0x00001434)*/ +/*! Slice: sp1_wr_swap_v:*/ +#define SP1_WR_SWAP_V +#define SP1_WR_SWAP_V_MASK 0x000F0000U +#define SP1_WR_SWAP_V_SHIFT 16U +/*! Slice: sp1_wr_swap_u:*/ +#define SP1_WR_SWAP_U +#define SP1_WR_SWAP_U_MASK 0x0000F000U +#define SP1_WR_SWAP_U_SHIFT 12U +/*! Slice: sp1_wr_swap_y:*/ +#define SP1_WR_SWAP_Y +#define SP1_WR_SWAP_Y_MASK 0x00000F00U +#define SP1_WR_SWAP_Y_SHIFT 8U +/*! Slice: sp1_rd_issue_cap:*/ +#define SP1_RD_ISSUE_CAP +#define SP1_RD_ISSUE_CAP_MASK 0x000000C0U +#define SP1_RD_ISSUE_CAP_SHIFT 6U +/*! Slice: sp1_wr_issue_cap:*/ +#define SP1_WR_ISSUE_CAP +#define SP1_WR_ISSUE_CAP_MASK 0x00000030U +#define SP1_WR_ISSUE_CAP_SHIFT 4U +/*! Slice: sp1_rd_burst_len:*/ +#define SP1_RD_BURST_LEN +#define SP1_RD_BURST_LEN_MASK 0x0000000CU +#define SP1_RD_BURST_LEN_SHIFT 2U +/*! Slice: sp1_wr_burst_len:*/ +#define SP1_WR_BURST_LEN +#define SP1_WR_BURST_LEN_MASK 0x00000003U +#define SP1_WR_BURST_LEN_SHIFT 0U +/*! Register: miv2_sp1_bus_id (0x00001438)*/ +/*! Slice: sp1_bus_sw_en:*/ +#define SP1_BUS_SW_EN +#define SP1_BUS_SW_EN_MASK 0x02000000U +#define SP1_BUS_SW_EN_SHIFT 25U + +/*! Slice: sp1_rd_id_en:*/ +#define SP1_RD_ID_EN +#define SP1_RD_ID_EN_MASK 0x01000000U +#define SP1_RD_ID_EN_SHIFT 24U +/*! Slice: sp1_rd_id_cfg:*/ +#define SP1_RD_ID_CFG +#define SP1_RD_ID_CFG_MASK 0x00FF0000U +#define SP1_RD_ID_CFG_SHIFT 16U +/*! Slice: sp1_wr_id_en:*/ +#define SP1_WR_ID_EN +#define SP1_WR_ID_EN_MASK 0x00000100U +#define SP1_WR_ID_EN_SHIFT 8U +/*! Slice: sp1_wr_id_cfg:*/ +#define SP1_WR_ID_CFG +#define SP1_WR_ID_CFG_MASK 0x000000FFU +#define SP1_WR_ID_CFG_SHIFT 0U +/*! Register: miv2_sp1_bus_timeo (0x0000143c)*/ +/*! Slice: sp1_bus_timeo_en:*/ +#define SP1_BUS_TIMEO_EN +#define SP1_BUS_TIMEO_EN_MASK 0x80000000U +#define SP1_BUS_TIMEO_EN_SHIFT 31U +/*! Slice: sp1_bus_timeo:*/ +#define SP1_BUS_TIMEO +#define SP1_BUS_TIMEO_MASK 0x7FFFFFFFU +#define SP1_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_sp1_y_base_ad_init (0x00001440)*/ +/*! Slice: sp1_y_base_ad_init:*/ +#define SP1_Y_BASE_AD_INIT +#define SP1_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP1_Y_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp1_y_size_init (0x00001444)*/ +/*! Slice: sp1_y_size_init:*/ +#define SP1_Y_SIZE_INIT +#define SP1_Y_SIZE_INIT_MASK 0x1FFFFFF0U +#define SP1_Y_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp1_y_offs_cnt_init (0x00001448)*/ +/*! Slice: sp1_y_offs_cnt_init:*/ +#define SP1_Y_OFFS_CNT_INIT +#define SP1_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define SP1_Y_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp1_y_llength (0x0000144c)*/ +/*! Slice: sp1_y_llengh:*/ +#define SP1_Y_LLENGH +#define SP1_Y_LLENGH_MASK 0x00007FFFU +#define SP1_Y_LLENGH_SHIFT 0U +/*! Register: miv2_sp1_y_pic_width (0x00001450)*/ +/*! Slice: sp1_y_pic_width:*/ +#define SP1_Y_PIC_WIDTH +#define SP1_Y_PIC_WIDTH_MASK 0xFFFFFFFFU +#define SP1_Y_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_sp1_y_pic_height (0x00001454)*/ +/*! Slice: sp1_y_pic_height:*/ +#define SP1_Y_PIC_HEIGHT +#define SP1_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define SP1_Y_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_sp1_y_pic_size (0x00001458)*/ +/*! Slice: sp1_y_pic_size:*/ +#define SP1_Y_PIC_SIZE +#define SP1_Y_PIC_SIZE_MASK 0xFFFFFFFFU +#define SP1_Y_PIC_SIZE_SHIFT 0U +/*! Register: miv2_sp1_cb_base_ad_init (0x0000145c)*/ +/*! Slice: sp1_cb_base_ad_init:*/ +#define SP1_CB_BASE_AD_INIT +#define SP1_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP1_CB_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp1_cb_size_init (0x00001460)*/ +/*! Slice: sp1_cb_size_init:*/ +#define SP1_CB_SIZE_INIT +#define SP1_CB_SIZE_INIT_MASK 0x0FFFFFF0U +#define SP1_CB_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp1_cb_offs_cnt_init (0x00001464)*/ +/*! Slice: sp1_cb_offs_cnt_init:*/ +#define SP1_CB_OFFS_CNT_INIT +#define SP1_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define SP1_CB_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp1_cr_base_ad_init (0x00001468)*/ +/*! Slice: sp1_cr_base_ad_init:*/ +#define SP1_CR_BASE_AD_INIT +#define SP1_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP1_CR_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp1_cr_size_init (0x0000146c)*/ +/*! Slice: sp1_cr_size_init:*/ +#define SP1_CR_SIZE_INIT +#define SP1_CR_SIZE_INIT_MASK 0x0FFFFFF0U +#define SP1_CR_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp1_cr_offs_cnt_init (0x00001470)*/ +/*! Slice: sp1_cr_offs_cnt_init:*/ +#define SP1_CR_OFFS_CNT_INIT +#define SP1_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define SP1_CR_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp1_y_base_ad_init2 (0x00001474)*/ +/*! Slice: sp1_y_base_ad_init2:*/ +#define SP1_Y_BASE_AD_INIT2 +#define SP1_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP1_Y_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp1_cb_base_ad_init2 (0x00001478)*/ +/*! Slice: sp1_cb_base_ad_init2:*/ +#define SP1_CB_BASE_AD_INIT2 +#define SP1_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP1_CB_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp1_cr_base_ad_init2 (0x0000147c)*/ +/*! Slice: sp1_cr_base_ad_init2:*/ +#define SP1_CR_BASE_AD_INIT2 +#define SP1_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP1_CR_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp1_y_offs_cnt_start (0x00001480)*/ +/*! Slice: sp1_y_offs_cnt_start:*/ +#define SP1_Y_OFFS_CNT_START +#define SP1_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define SP1_Y_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp1_cb_offs_cnt_start (0x00001484)*/ +/*! Slice: sp1_cb_offs_cnt_start:*/ +#define SP1_CB_OFFS_CNT_START +#define SP1_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define SP1_CB_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp1_cr_offs_cnt_start (0x00001488)*/ +/*! Slice: sp1_cr_offs_cnt_start:*/ +#define SP1_CR_OFFS_CNT_START +#define SP1_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define SP1_CR_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp1_y_base_ad_shd (0x0000148c)*/ +/*! Slice: sp1_y_base_ad:*/ +#define SP1_Y_BASE_AD +#define SP1_Y_BASE_AD_MASK 0xFFFFFFF0U +#define SP1_Y_BASE_AD_SHIFT 4U +/*! Register: miv2_sp1_y_size_shd (0x00001490)*/ +/*! Slice: sp1_y_size:*/ +#define SP1_Y_SIZE +#define SP1_Y_SIZE_MASK 0x1FFFFFF0U +#define SP1_Y_SIZE_SHIFT 4U +/*! Register: miv2_sp1_y_offs_cnt_shd (0x00001494)*/ +/*! Slice: sp1_y_offs_cnt:*/ +#define SP1_Y_OFFS_CNT +#define SP1_Y_OFFS_CNT_MASK 0x1FFFFFF0U +#define SP1_Y_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp1_cb_base_ad_shd (0x00001498)*/ +/*! Slice: sp1_cb_base_ad:*/ +#define SP1_CB_BASE_AD +#define SP1_CB_BASE_AD_MASK 0xFFFFFFF0U +#define SP1_CB_BASE_AD_SHIFT 4U +/*! Register: miv2_sp1_cb_size_shd (0x0000149c)*/ +/*! Slice: sp1_cb_size:*/ +#define SP1_CB_SIZE +#define SP1_CB_SIZE_MASK 0x0FFFFFF0U +#define SP1_CB_SIZE_SHIFT 4U +/*! Register: miv2_sp1_cb_offs_cnt_shd (0x000014a0)*/ +/*! Slice: sp1_cb_offs_cnt:*/ +#define SP1_CB_OFFS_CNT +#define SP1_CB_OFFS_CNT_MASK 0x0FFFFFF0U +#define SP1_CB_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp1_cr_base_ad_shd (0x000014a4)*/ +/*! Slice: sp1_cr_base_ad:*/ +#define SP1_CR_BASE_AD +#define SP1_CR_BASE_AD_MASK 0xFFFFFFF0U +#define SP1_CR_BASE_AD_SHIFT 4U +/*! Register: miv2_sp1_cr_size_shd (0x000014a8)*/ +/*! Slice: sp1_cr_size:*/ +#define SP1_CR_SIZE +#define SP1_CR_SIZE_MASK 0x0FFFFFF0U +#define SP1_CR_SIZE_SHIFT 4U +/*! Register: miv2_sp1_cr_offs_cnt_shd (0x000014ac)*/ +/*! Slice: sp1_cr_offs_cnt:*/ +#define SP1_CR_OFFS_CNT +#define SP1_CR_OFFS_CNT_MASK 0x0FFFFFF0U +#define SP1_CR_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp1_status_clr (0x000014b0)*/ +/*! Slice: sp1_cr_fifo_full:*/ +#define SP1_CR_FIFO_FULL +#define SP1_CR_FIFO_FULL_MASK 0x00000004U +#define SP1_CR_FIFO_FULL_SHIFT 2U +/*! Slice: sp1_cb_fifo_full:*/ +#define SP1_CB_FIFO_FULL +#define SP1_CB_FIFO_FULL_MASK 0x00000002U +#define SP1_CB_FIFO_FULL_SHIFT 1U +/*! Slice: sp1_y_fifo_full:*/ +#define SP1_Y_FIFO_FULL +#define SP1_Y_FIFO_FULL_MASK 0x00000001U +#define SP1_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_sp1_ctrl_status (0x000014b4)*/ +/*! Slice: sp1_cr_fifo_full:*/ +#define SP1_CR_FIFO_FULL +#define SP1_CR_FIFO_FULL_MASK 0x00000004U +#define SP1_CR_FIFO_FULL_SHIFT 2U +/*! Slice: sp1_cb_fifo_full:*/ +#define SP1_CB_FIFO_FULL +#define SP1_CB_FIFO_FULL_MASK 0x00000002U +#define SP1_CB_FIFO_FULL_SHIFT 1U +/*! Slice: sp1_y_fifo_full:*/ +#define SP1_Y_FIFO_FULL +#define SP1_Y_FIFO_FULL_MASK 0x00000001U +#define SP1_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_sp1_axi_status (0x000014b8)*/ +/*! Slice: agsw_enc_pic_rdy:*/ +#define AGSW_ENC_PIC_RDY +#define AGSW_ENC_PIC_RDY_MASK 0x00000002U +#define AGSW_ENC_PIC_RDY_SHIFT 1U +/*! Slice: agsw_enc_buf_full:*/ +#define AGSW_ENC_BUF_FULL +#define AGSW_ENC_BUF_FULL_MASK 0x00000001U +#define AGSW_ENC_BUF_FULL_SHIFT 0U +/*! Register: miv2_sp2_ctrl (0x000014e4)*/ +/*! Slice: sp2_rd_raw_cfg_update */ +#define SP2_RD_RAW_CFG_UPDATE +#define SP2_RD_RAW_CFG_UPDATE_MASK 0x00000200U +#define SP2_RD_RAW_CFG_UPDATE_SHIFT 9U +/*! Slice: sp2_rd_raw_auto_update */ +#define SP2_RD_RAW_AUTO_UPDATE +#define SP2_RD_RAW_AUTO_UPDATE_MASK 0x00000100U +#define SP2_RD_RAW_AUTO_UPDATE_SHIFT 8U +/*! Slice: sp2_rd_yuv_cfg_update */ +#define SP2_RD_YUV_CFG_UPDATE +#define SP2_RD_YUV_CFG_UPDATE_MASK 0x00000080U +#define SP2_RD_YUV_CFG_UPDATE_SHIFT 7U +/*! Slice: sp2_rd_yuv_auto_update */ +#define SP2_RD_YUV_AUTO_UPDATE +#define SP2_RD_YUV_AUTO_UPDATE_MASK 0x00000040U +#define SP2_RD_YUV_AUTO_UPDATE_SHIFT 6U +/*! Slice: sp2_init_offset_en:*/ +#define SP2_INIT_OFFSET_EN +#define SP2_INIT_OFFSET_EN_MASK 0x00000020U +#define SP2_INIT_OFFSET_EN_SHIFT 5U +/*! Slice: sp2_init_base_en:*/ +#define SP2_INIT_BASE_EN +#define SP2_INIT_BASE_EN_MASK 0x00000010U +#define SP2_INIT_BASE_EN_SHIFT 4U +/*! Slice: sp2_miv2_cfg_upd:*/ +#define SP2_MI_CFG_UPD +#define SP2_MI_CFG_UPD_MASK 0x00000008U +#define SP2_MI_CFG_UPD_SHIFT 3U +/*! Slice: sp2_miv2_skip:*/ +#define SP2_MI_SKIP +#define SP2_MI_SKIP_MASK 0x00000004U +#define SP2_MI_SKIP_SHIFT 2U +/*! Slice: sp2_auto_update:*/ +#define SP2_AUTO_UPDATE +#define SP2_AUTO_UPDATE_MASK 0x00000002U +#define SP2_AUTO_UPDATE_SHIFT 1U +/*! Slice: sp2_pingpong_enable:*/ +#define SP2_PINGPONG_ENABLE +#define SP2_PINGPONG_ENABLE_MASK 0x00000001U +#define SP2_PINGPONG_ENABLE_SHIFT 0U +/*! Register: miv2_sp2_fmt (0x000014e8)*/ +/*! Slice: sp2_rd_yuv_nvy:*/ +#define SP2_RD_YUV_NVY +#define SP2_RD_YUV_NVY_MASK 0x0C000000U +#define SP2_RD_YUV_NVY_SHIFT 26U +/*! Slice: sp2_rd_yuv_nv21:*/ +#define SP2_RD_YUV_NV21 +#define SP2_RD_YUV_NV21_MASK 0x02000000U +#define SP2_RD_YUV_NV21_SHIFT 25U +/*! Slice: sp2_rd_raw_aligned:*/ +#define SP2_RD_RAW_ALIGNED +#define SP2_RD_RAW_ALIGNED_MASK 0x01800000U +#define SP2_RD_RAW_ALIGNED_SHIFT 23U +/*! Slice: sp2_rd_yuv_aligned:*/ +#define SP2_RD_YUV_ALIGNED +#define SP2_RD_YUV_ALIGNED_MASK 0x00400000U +#define SP2_RD_YUV_ALIGNED_SHIFT 22U +/*! Slice: sp2_rd_raw_bit:*/ +#define SP2_RD_RAW_BIT +#define SP2_RD_RAW_BIT_MASK 0x00380000U +#define SP2_RD_RAW_BIT_SHIFT 19U +/*! Slice: sp2_rd_yuv_str:*/ +#define SP2_RD_YUV_STR +#define SP2_RD_YUV_STR_MASK 0x00060000U +#define SP2_RD_YUV_STR_SHIFT 17U +/*! Slice: sp2_rd_yuv_fmt:*/ +#define SP2_RD_YUV_FMT +#define SP2_RD_YUV_FMT_MASK 0x00018000U +#define SP2_RD_YUV_FMT_SHIFT 15U +/*! Slice: sp2_rd_yuv_bit:*/ +#define SP2_RD_YUV_BIT +#define SP2_RD_YUV_BIT_MASK 0x00004000U +#define SP2_RD_YUV_BIT_SHIFT 14U +/*! Slice: sp2_wr_yuv_nvy:*/ +#define SP2_WR_YUV_NVY +#define SP2_WR_YUV_NVY_MASK 0x00003000U +#define SP2_WR_YUV_NVY_SHIFT 12U +/*! Slice: sp2_wr_yuv_nv21:*/ +#define SP2_WR_YUV_NV21 +#define SP2_WR_YUV_NV21_MASK 0x00000800U +#define SP2_WR_YUV_NV21_SHIFT 11U +/*! Slice: sp2_wr_raw_aligned:*/ +#define SP2_WR_RAW_ALIGNED +#define SP2_WR_RAW_ALIGNED_MASK 0x00000600U +#define SP2_WR_RAW_ALIGNED_SHIFT 9U +/*! Slice: sp2_wr_yuv_aligned:*/ +#define SP2_WR_YUV_ALIGNED +#define SP2_WR_YUV_ALIGNED_MASK 0x00000100U +#define SP2_WR_YUV_ALIGNED_SHIFT 8U +/*! Slice: sp2_wr_raw_bit:*/ +#define SP2_WR_RAW_BIT +#define SP2_WR_RAW_BIT_MASK 0x000000E0U +#define SP2_WR_RAW_BIT_SHIFT 5U +/*! Slice: sp2_wr_yuv_str:*/ +#define SP2_WR_YUV_STR +#define SP2_WR_YUV_STR_MASK 0x00000018U +#define SP2_WR_YUV_STR_SHIFT 3U +/*! Slice: sp2_wr_yuv_fmt:*/ +#define SP2_WR_YUV_FMT +#define SP2_WR_YUV_FMT_MASK 0x00000006U +#define SP2_WR_YUV_FMT_SHIFT 1U +/*! Slice: sp2_wr_yuv_bit:*/ +#define SP2_WR_YUV_BIT +#define SP2_WR_YUV_BIT_MASK 0x00000001U +#define SP2_WR_YUV_BIT_SHIFT 0U +/*! Register: miv2_sp2_bus_cfg (0x000014ec)*/ +/*! Slice: sp2_rd_swap_raw:*/ +#define SP2_RD_SWAP_RAW +#define SP2_RD_SWAP_RAW_MASK 0xF0000000U +#define SP2_RD_SWAP_RAW_SHIFT 28U +/*! Slice: sp2_rd_swap_v:*/ +#define SP2_RD_SWAP_V +#define SP2_RD_SWAP_V_MASK 0x0F000000U +#define SP2_RD_SWAP_V_SHIFT 24U +/*! Slice: sp2_rd_swap_u:*/ +#define SP2_RD_SWAP_U +#define SP2_RD_SWAP_U_MASK 0x00F00000U +#define SP2_RD_SWAP_U_SHIFT 20U +/*! Slice: sp2_rd_swap_y:*/ +#define SP2_RD_SWAP_Y +#define SP2_RD_SWAP_Y_MASK 0x000F0000U +#define SP2_RD_SWAP_Y_SHIFT 16U +/*! Slice: sp2_wr_swap_raw:*/ +#define SP2_WR_SWAP_RAW +#define SP2_WR_SWAP_RAW_MASK 0x0000F000U +#define SP2_WR_SWAP_RAW_SHIFT 12U +/*! Slice: sp2_wr_swap_v:*/ +#define SP2_WR_SWAP_V +#define SP2_WR_SWAP_V_MASK 0x00000F00U +#define SP2_WR_SWAP_V_SHIFT 8U +/*! Slice: sp2_wr_swap_u:*/ +#define SP2_WR_SWAP_U +#define SP2_WR_SWAP_U_MASK 0x000000F0U +#define SP2_WR_SWAP_U_SHIFT 4U +/*! Slice: sp2_wr_swap_y:*/ +#define SP2_WR_SWAP_Y +#define SP2_WR_SWAP_Y_MASK 0x0000000FU +#define SP2_WR_SWAP_Y_SHIFT 0U +/*! Register: miv2_sp2_bus_id (0x000014f0)*/ +/*! Slice: sp2_bus_sw_en:*/ +#define SP2_BUS_SW_EN +#define SP2_BUS_SW_EN_MASK 0x08000000U +#define SP2_BUS_SW_EN_SHIFT 27U +/*! Slice: sp2_rd_issue_cap:*/ +#define SP2_RD_ISSUE_CAP +#define SP2_RD_ISSUE_CAP_MASK 0x06000000U +#define SP2_RD_ISSUE_CAP_SHIFT 25U +/*! Slice: sp2_wr_issue_cap:*/ +#define SP2_WR_ISSUE_CAP +#define SP2_WR_ISSUE_CAP_MASK 0x01800000U +#define SP2_WR_ISSUE_CAP_SHIFT 23U +/*! Slice: sp2_rd_burst_len:*/ +#define SP2_RD_BURST_LEN +#define SP2_RD_BURST_LEN_MASK 0x00600000U +#define SP2_RD_BURST_LEN_SHIFT 21U +/*! Slice: sp2_wr_burst_len:*/ +#define SP2_WR_BURST_LEN +#define SP2_WR_BURST_LEN_MASK 0x00180000U +#define SP2_WR_BURST_LEN_SHIFT 19U +/*! Slice: sp2_rd_id_en:*/ +#define SP2_RD_ID_EN +#define SP2_RD_ID_EN_MASK 0x00040000U +#define SP2_RD_ID_EN_SHIFT 18U +/*! Slice: sp2_rd_id_cfg:*/ +#define SP2_RD_ID_CFG +#define SP2_RD_ID_CFG_MASK 0x0003FC00U +#define SP2_RD_ID_CFG_SHIFT 10U +/*! Slice: sp2_wr_id_en:*/ +#define SP2_WR_ID_EN +#define SP2_WR_ID_EN_MASK 0x00000100U +#define SP2_WR_ID_EN_SHIFT 8U +/*! Slice: sp2_wr_id_cfg:*/ +#define SP2_WR_ID_CFG +#define SP2_WR_ID_CFG_MASK 0x000000FFU +#define SP2_WR_ID_CFG_SHIFT 0U +/*! Register: miv2_sp2_bus_timeo (0x000014f4)*/ +/*! Slice: sp2_bus_timeo_en:*/ +#define SP2_BUS_TIMEO_EN +#define SP2_BUS_TIMEO_EN_MASK 0x80000000U +#define SP2_BUS_TIMEO_EN_SHIFT 31U +/*! Slice: sp2_bus_timeo:*/ +#define SP2_BUS_TIMEO +#define SP2_BUS_TIMEO_MASK 0x7FFFFFFFU +#define SP2_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_sp2_y_base_ad_init (0x000014f8)*/ +/*! Slice: sp2_y_base_ad_init:*/ +#define SP2_Y_BASE_AD_INIT +#define SP2_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP2_Y_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp2_y_size_init (0x000014fc)*/ +/*! Slice: sp2_y_size_init:*/ +#define SP2_Y_SIZE_INIT +#define SP2_Y_SIZE_INIT_MASK 0x1FFFFFF0U +#define SP2_Y_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp2_y_offs_cnt_init (0x00001500)*/ +/*! Slice: sp2_y_offs_cnt_init:*/ +#define SP2_Y_OFFS_CNT_INIT +#define SP2_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define SP2_Y_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp2_y_llength (0x00001504)*/ +/*! Slice: sp2_y_llengh:*/ +#define SP2_Y_LLENGH +#define SP2_Y_LLENGH_MASK 0x00007FFFU +#define SP2_Y_LLENGH_SHIFT 0U +/*! Register: miv2_sp2_y_pic_width (0x00001508)*/ +/*! Slice: sp2_y_pic_width:*/ +#define SP2_Y_PIC_WIDTH +#define SP2_Y_PIC_WIDTH_MASK 0xFFFFFFFFU +#define SP2_Y_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_sp2_y_pic_height (0x0000150c)*/ +/*! Slice: sp2_y_pic_height:*/ +#define SP2_Y_PIC_HEIGHT +#define SP2_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define SP2_Y_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_sp2_y_pic_size (0x00001510)*/ +/*! Slice: sp2_y_pic_size:*/ +#define SP2_Y_PIC_SIZE +#define SP2_Y_PIC_SIZE_MASK 0xFFFFFFFFU +#define SP2_Y_PIC_SIZE_SHIFT 0U +/*! Register: miv2_sp2_cb_base_ad_init (0x00001514)*/ +/*! Slice: sp2_cb_base_ad_init:*/ +#define SP2_CB_BASE_AD_INIT +#define SP2_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP2_CB_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp2_cb_size_init (0x00001518)*/ +/*! Slice: sp2_cb_size_init:*/ +#define SP2_CB_SIZE_INIT +#define SP2_CB_SIZE_INIT_MASK 0x0FFFFFF0U +#define SP2_CB_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp2_cb_offs_cnt_init (0x0000151c)*/ +/*! Slice: sp2_cb_offs_cnt_init:*/ +#define SP2_CB_OFFS_CNT_INIT +#define SP2_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define SP2_CB_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp2_cr_base_ad_init (0x00001520)*/ +/*! Slice: sp2_cr_base_ad_init:*/ +#define SP2_CR_BASE_AD_INIT +#define SP2_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP2_CR_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp2_cr_size_init (0x00001524)*/ +/*! Slice: sp2_cr_size_init:*/ +#define SP2_CR_SIZE_INIT +#define SP2_CR_SIZE_INIT_MASK 0x0FFFFFF0U +#define SP2_CR_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp2_cr_offs_cnt_init (0x00001528)*/ +/*! Slice: sp2_cr_offs_cnt_init:*/ +#define SP2_CR_OFFS_CNT_INIT +#define SP2_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U +#define SP2_CR_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp2_y_base_ad_init2 (0x0000152c)*/ +/*! Slice: sp2_y_base_ad_init2:*/ +#define SP2_Y_BASE_AD_INIT2 +#define SP2_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP2_Y_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp2_cb_base_ad_init2 (0x00001530)*/ +/*! Slice: sp2_cb_base_ad_init2:*/ +#define SP2_CB_BASE_AD_INIT2 +#define SP2_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP2_CB_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp2_cr_base_ad_init2 (0x00001534)*/ +/*! Slice: sp2_cr_base_ad_init2:*/ +#define SP2_CR_BASE_AD_INIT2 +#define SP2_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U +#define SP2_CR_BASE_AD_INIT2_SHIFT 4U +/*! Register: miv2_sp2_y_offs_cnt_start (0x00001538)*/ +/*! Slice: sp2_y_offs_cnt_start:*/ +#define SP2_Y_OFFS_CNT_START +#define SP2_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define SP2_Y_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp2_cb_offs_cnt_start (0x0000153c)*/ +/*! Slice: sp2_cb_offs_cnt_start:*/ +#define SP2_CB_OFFS_CNT_START +#define SP2_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define SP2_CB_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp2_cr_offs_cnt_start (0x00001540)*/ +/*! Slice: sp2_cr_offs_cnt_start:*/ +#define SP2_CR_OFFS_CNT_START +#define SP2_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U +#define SP2_CR_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp2_y_base_ad_shd (0x00001544)*/ +/*! Slice: sp2_y_base_ad:*/ +#define SP2_Y_BASE_AD +#define SP2_Y_BASE_AD_MASK 0xFFFFFFF0U +#define SP2_Y_BASE_AD_SHIFT 4U +/*! Register: miv2_sp2_y_size_shd (0x00001548)*/ +/*! Slice: sp2_y_size:*/ +#define SP2_Y_SIZE +#define SP2_Y_SIZE_MASK 0x1FFFFFF0U +#define SP2_Y_SIZE_SHIFT 4U +/*! Register: miv2_sp2_y_offs_cnt_shd (0x0000154c)*/ +/*! Slice: sp2_y_offs_cnt:*/ +#define SP2_Y_OFFS_CNT +#define SP2_Y_OFFS_CNT_MASK 0x1FFFFFF0U +#define SP2_Y_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp2_cb_base_ad_shd (0x00001550)*/ +/*! Slice: sp2_cb_base_ad:*/ +#define SP2_CB_BASE_AD +#define SP2_CB_BASE_AD_MASK 0xFFFFFFF0U +#define SP2_CB_BASE_AD_SHIFT 4U +/*! Register: miv2_sp2_cb_size_shd (0x00001554)*/ +/*! Slice: sp2_cb_size:*/ +#define SP2_CB_SIZE +#define SP2_CB_SIZE_MASK 0x0FFFFFF0U +#define SP2_CB_SIZE_SHIFT 4U +/*! Register: miv2_sp2_cb_offs_cnt_shd (0x00001558)*/ +/*! Slice: sp2_cb_offs_cnt:*/ +#define SP2_CB_OFFS_CNT +#define SP2_CB_OFFS_CNT_MASK 0x0FFFFFF0U +#define SP2_CB_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp2_cr_base_ad_shd (0x0000155c)*/ +/*! Slice: sp2_cr_base_ad:*/ +#define SP2_CR_BASE_AD +#define SP2_CR_BASE_AD_MASK 0xFFFFFFF0U +#define SP2_CR_BASE_AD_SHIFT 4U +/*! Register: miv2_sp2_cr_size_shd (0x00001560)*/ +/*! Slice: sp2_cr_size:*/ +#define SP2_CR_SIZE +#define SP2_CR_SIZE_MASK 0x0FFFFFF0U +#define SP2_CR_SIZE_SHIFT 4U +/*! Register: miv2_sp2_cr_offs_cnt_shd (0x00001564)*/ +/*! Slice: sp2_cr_offs_cnt:*/ +#define SP2_CR_OFFS_CNT +#define SP2_CR_OFFS_CNT_MASK 0x0FFFFFF0U +#define SP2_CR_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp2_raw_base_ad_init (0x00001568)*/ +/*! Slice: sp2_raw_base_ad_init:*/ +#define SP2_RAW_BASE_AD_INIT +#define SP2_RAW_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define SP2_RAW_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_sp2_raw_size_init (0x0000156c)*/ +/*! Slice: sp2_raw_size_init:*/ +#define SP2_RAW_SIZE_INIT +#define SP2_RAW_SIZE_INIT_MASK 0x1FFFFFF0U +#define SP2_RAW_SIZE_INIT_SHIFT 4U +/*! Register: miv2_sp2_raw_offs_cnt_init (0x00001570)*/ +/*! Slice: sp2_raw_offs_cnt_init:*/ +#define SP2_RAW_OFFS_CNT_INIT +#define SP2_RAW_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define SP2_RAW_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_sp2_raw_llength (0x00001574)*/ +/*! Slice: sp2_raw_llengh:*/ +#define SP2_RAW_LLENGH +#define SP2_RAW_LLENGH_MASK 0x00007FFFU +#define SP2_RAW_LLENGH_SHIFT 0U +/*! Register: miv2_sp2_raw_pic_width (0x00001578)*/ +/*! Slice: sp2_raw_pic_width:*/ +#define SP2_RAW_PIC_WIDTH +#define SP2_RAW_PIC_WIDTH_MASK 0xFFFFFFFFU +#define SP2_RAW_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_sp2_raw_pic_height (0x0000157c)*/ +/*! Slice: sp2_raw_pic_height:*/ +#define SP2_RAW_PIC_HEIGHT +#define SP2_RAW_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define SP2_RAW_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_sp2_raw_pic_size (0x00001580)*/ +/*! Slice: sp2_raw_pic_size:*/ +#define SP2_RAW_PIC_SIZE +#define SP2_RAW_PIC_SIZE_MASK 0xFFFFFFFFU +#define SP2_RAW_PIC_SIZE_SHIFT 0U +/*! Register: miv2_sp2_raw_offs_cnt_start (0x00001584)*/ +/*! Slice: sp2_raw_offs_cnt_start:*/ +#define SP2_RAW_OFFS_CNT_START +#define SP2_RAW_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define SP2_RAW_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_sp2_raw_base_ad_shd (0x0000158c)*/ +/*! Slice: sp2_raw_base_ad:*/ +#define SP2_RAW_BASE_AD +#define SP2_RAW_BASE_AD_MASK 0xFFFFFFF0U +#define SP2_RAW_BASE_AD_SHIFT 4U +/*! Register: miv2_sp2_raw_size_shd (0x00001590)*/ +/*! Slice: sp2_raw_size:*/ +#define SP2_RAW_SIZE +#define SP2_RAW_SIZE_MASK 0x1FFFFFF0U +#define SP2_RAW_SIZE_SHIFT 4U +/*! Register: miv2_sp2_raw_offs_cnt_shd (0x00001594)*/ +/*! Slice: sp2_raw_offs_cnt:*/ +#define SP2_RAW_OFFS_CNT +#define SP2_RAW_OFFS_CNT_MASK 0x1FFFFFF0U +#define SP2_RAW_OFFS_CNT_SHIFT 4U +/*! Register: miv2_sp2_dma_y_pic_start_ad (0x00001598)*/ +/*! Slice: sp2_dma_y_pic_start_ad:*/ +#define SP2_DMA_Y_PIC_START_AD +#define SP2_DMA_Y_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_Y_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_y_pic_width (0x0000159c)*/ +/*! Slice: sp2_dma_y_pic_width:*/ +#define SP2_DMA_Y_PIC_WIDTH +#define SP2_DMA_Y_PIC_WIDTH_MASK 0x00007FFFU +#define SP2_DMA_Y_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_sp2_dma_y_pic_llength (0x000015a0)*/ +/*! Slice: sp2_dma_y_pic_llength:*/ +#define SP2_DMA_Y_PIC_LLENGTH +#define SP2_DMA_Y_PIC_LLENGTH_MASK 0x00007FFFU +#define SP2_DMA_Y_PIC_LLENGTH_SHIFT 0U +/*! Register: miv2_sp2_dma_y_pic_size (0x000015a4)*/ +/*! Slice: sp2_dma_y_pic_size:*/ +#define SP2_DMA_Y_PIC_SIZE +#define SP2_DMA_Y_PIC_SIZE_MASK 0x0FFFFFFFU +#define SP2_DMA_Y_PIC_SIZE_SHIFT 0U +/*! Register: miv2_sp2_dma_cb_pic_start_ad (0x000015a8)*/ +/*! Slice: sp2_dma_cb_pic_start_ad:*/ +#define SP2_DMA_CB_PIC_START_AD +#define SP2_DMA_CB_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_CB_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_cr_pic_start_ad (0x000015ac)*/ +/*! Slice: sp2_dma_cr_pic_start_ad:*/ +#define SP2_DMA_CR_PIC_START_AD +#define SP2_DMA_CR_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_CR_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_y_pic_start_ad_shd (0x000015b0)*/ +/*! Slice: sp2_dma_y_pic_start_ad:*/ +#define SP2_DMA_Y_PIC_START_AD +#define SP2_DMA_Y_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_Y_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_cb_pic_start_ad_shd (0x000015b4)*/ +/*! Slice: sp2_dma_cb_pic_start_ad:*/ +#define SP2_DMA_CB_PIC_START_AD +#define SP2_DMA_CB_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_CB_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_cr_pic_start_ad_shd (0x000015b8)*/ +/*! Slice: sp2_dma_cr_pic_start_ad:*/ +#define SP2_DMA_CR_PIC_START_AD +#define SP2_DMA_CR_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_CR_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_raw_pic_start_ad (0x000015bc)*/ +/*! Slice: sp2_dma_raw_pic_start_ad:*/ +#define SP2_DMA_RAW_PIC_START_AD +#define SP2_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_RAW_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_dma_raw_pic_width (0x000015c0)*/ +/*! Slice: sp2_dma_raw_pic_width:*/ +#define SP2_DMA_RAW_PIC_WIDTH +#define SP2_DMA_RAW_PIC_WIDTH_MASK 0x00007FFFU +#define SP2_DMA_RAW_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_sp2_dma_raw_pic_llength (0x000015c4)*/ +/*! Slice: sp2_dma_raw_pic_llength:*/ +#define SP2_DMA_RAW_PIC_LLENGTH +#define SP2_DMA_RAW_PIC_LLENGTH_MASK 0x00007FFFU +#define SP2_DMA_RAW_PIC_LLENGTH_SHIFT 0U +/*! Register: miv2_sp2_dma_raw_pic_size (0x000015c8)*/ +/*! Slice: sp2_dma_raw_pic_size:*/ +#define SP2_DMA_RAW_PIC_SIZE +#define SP2_DMA_RAW_PIC_SIZE_MASK 0x0FFFFFFFU +#define SP2_DMA_RAW_PIC_SIZE_SHIFT 0U +/*! Register: miv2_sp2_dma_raw_pic_start_ad_shd (0x000015cc)*/ +/*! Slice: sp2_dma_raw_pic_start_ad:*/ +#define SP2_DMA_RAW_PIC_START_AD +#define SP2_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U +#define SP2_DMA_RAW_PIC_START_AD_SHIFT 4U +/*! Register: miv2_sp2_status_clr (0x000015d0)*/ +/*! Slice: sp2_jdp_fifo_full:*/ +#define SP2_JDP_FIFO_FULL +#define SP2_JDP_FIFO_FULL_MASK 0x00000010U +#define SP2_JDP_FIFO_FULL_SHIFT 4U +/*! Slice: sp2_raw_fifo_full:*/ +#define SP2_RAW_FIFO_FULL +#define SP2_RAW_FIFO_FULL_MASK 0x00000008U +#define SP2_RAW_FIFO_FULL_SHIFT 3U +/*! Slice: sp2_cr_fifo_full:*/ +#define SP2_CR_FIFO_FULL +#define SP2_CR_FIFO_FULL_MASK 0x00000004U +#define SP2_CR_FIFO_FULL_SHIFT 2U +/*! Slice: sp2_cb_fifo_full:*/ +#define SP2_CB_FIFO_FULL +#define SP2_CB_FIFO_FULL_MASK 0x00000002U +#define SP2_CB_FIFO_FULL_SHIFT 1U +/*! Slice: sp2_y_fifo_full:*/ +#define SP2_Y_FIFO_FULL +#define SP2_Y_FIFO_FULL_MASK 0x00000001U +#define SP2_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_sp2_ctrl_status (0x000015d4)*/ +/*! Slice: sp2_jdp_fifo_full:*/ +#define SP2_JDP_FIFO_FULL +#define SP2_JDP_FIFO_FULL_MASK 0x00000010U +#define SP2_JDP_FIFO_FULL_SHIFT 4U +/*! Slice: sp2_raw_fifo_full:*/ +#define SP2_RAW_FIFO_FULL +#define SP2_RAW_FIFO_FULL_MASK 0x00000008U +#define SP2_RAW_FIFO_FULL_SHIFT 3U +/*! Slice: sp2_cr_fifo_full:*/ +#define SP2_CR_FIFO_FULL +#define SP2_CR_FIFO_FULL_MASK 0x00000004U +#define SP2_CR_FIFO_FULL_SHIFT 2U +/*! Slice: sp2_cb_fifo_full:*/ +#define SP2_CB_FIFO_FULL +#define SP2_CB_FIFO_FULL_MASK 0x00000002U +#define SP2_CB_FIFO_FULL_SHIFT 1U +/*! Slice: sp2_y_fifo_full:*/ +#define SP2_Y_FIFO_FULL +#define SP2_Y_FIFO_FULL_MASK 0x00000001U +#define SP2_Y_FIFO_FULL_SHIFT 0U +/*! Register: miv2_sp2_axi_status (0x000015d8)*/ +/*! Slice: agsw_enc_pic_rdy:*/ +#define AGSW_ENC_PIC_RDY +#define AGSW_ENC_PIC_RDY_MASK 0x00000002U +#define AGSW_ENC_PIC_RDY_SHIFT 1U +/*! Slice: agsw_enc_buf_full:*/ +#define AGSW_ENC_BUF_FULL +#define AGSW_ENC_BUF_FULL_MASK 0x00000001U +#define AGSW_ENC_BUF_FULL_SHIFT 0U +/*! Register: miv2_sp2_dma_yuv_status (0x000015dc)*/ +/*! Slice: sp2_dma_yuv_active:*/ +#define SP2_DMA_YUV_ACTIVE +#define SP2_DMA_YUV_ACTIVE_MASK 0x00000001U +#define SP2_DMA_YUV_ACTIVE_SHIFT 0U +/*! Register: miv2_sp2_dma_raw_status (0x000015e0)*/ +/*! Slice: sp2_dma_raw_active:*/ +#define SP2_DMA_RAW_ACTIVE +#define SP2_DMA_RAW_ACTIVE_MASK 0x00000001U +#define SP2_DMA_RAW_ACTIVE_SHIFT 0U +/*! Register: miv2_mcm_ctrl (0x00001600)*/ +/*! Slice: mcm_init_offset_en:*/ +#define MCM_RD_CFG_UPD +#define MCM_RD_CFG_UPD_MASK 0x00000040U +#define MCM_RD_CFG_UPD_SHIFT 6U +/*! Slice: mcm_init_offset_en:*/ +#define MCM_RD_AUTO_UPDATE +#define MCM_RD_AUTO_UPDATE_MASK 0x00000020U +#define MCM_RD_AUTO_UPDATE_SHIFT 5U +#define MCM_INIT_OFFSET_EN +#define MCM_INIT_OFFSET_EN_MASK 0x00000010U +#define MCM_INIT_OFFSET_EN_SHIFT 4U +/*! Slice: mcm_init_base_en:*/ +#define MCM_INIT_BASE_EN +#define MCM_INIT_BASE_EN_MASK 0x00000008U +#define MCM_INIT_BASE_EN_SHIFT 3U +/*! Slice: mcm_miv2_cfg_upd:*/ +#define MCM_WR_CFG_UPD +#define MCM_WR_CFG_UPD_MASK 0x00000004U +#define MCM_WR_CFG_UPD_SHIFT 2U +/*! Slice: mcm_miv2_skip:*/ +#define MCM_MI_SKIP +#define MCM_MI_SKIP_MASK 0x00000002U +#define MCM_MI_SKIP_SHIFT 1U +/*! Slice: mcm_auto_update:*/ +#define MCM_WR_AUTO_UPDATE +#define MCM_WR_AUTO_UPDATE_MASK 0x00000001U +#define MCM_WR_AUTO_UPDATE_SHIFT 0U +/*! Register: miv2_mcm_fmt (0x00001604)*/ +/*! Slice: mcm_wr1_fmt_aligned:*/ +#define MCM_WR1_FMT_ALIGNED +#define MCM_WR1_FMT_ALIGNED_MASK 0x00030000U +#define MCM_WR1_FMT_ALIGNED_SHIFT 16U +/*! Slice: mcm_wr0_fmt_aligned:*/ +#define MCM_WR0_FMT_ALIGNED +#define MCM_WR0_FMT_ALIGNED_MASK 0x0000C000U +#define MCM_WR0_FMT_ALIGNED_SHIFT 14U +/*! Slice: mcm_rd_fmt_aligned:*/ +#define MCM_RD_FMT_ALIGNED +#define MCM_RD_FMT_ALIGNED_MASK 0x00003000U +#define MCM_RD_FMT_ALIGNED_SHIFT 12U +/*! Slice: mcm_wr1_raw_bit:*/ +#define MCM_WR1_RAW_BIT +#define MCM_WR1_RAW_BIT_MASK 0x00000F00U +#define MCM_WR1_RAW_BIT_SHIFT 8U +/*! Slice: mcm_wr0_raw_bit:*/ +#define MCM_WR0_RAW_BIT +#define MCM_WR0_RAW_BIT_MASK 0x000000F0U +#define MCM_WR0_RAW_BIT_SHIFT 4U +/*! Slice: mcm_rd_raw_bit:*/ +#define MCM_RD_RAW_BIT +#define MCM_RD_RAW_BIT_MASK 0x0000000FU +#define MCM_RD_RAW_BIT_SHIFT 0U +/*! Register: miv2_mcm_bus_cfg (0x00001608)*/ +/*! Slice: mcm_rd_swap_raw:*/ +#define MCM_RD_SWAP_RAW +#define MCM_RD_SWAP_RAW_MASK 0x000F0000U +#define MCM_RD_SWAP_RAW_SHIFT 16U +/*! Slice: mcm_wr0_swap_raw:*/ +#define MCM_WR0_SWAP_RAW +#define MCM_WR0_SWAP_RAW_MASK 0x0000F000U +#define MCM_WR0_SWAP_RAW_SHIFT 12U +/*! Slice: mcm_wr1_swap_raw:*/ +#define MCM_WR1_SWAP_RAW +#define MCM_WR1_SWAP_RAW_MASK 0x00000F00U +#define MCM_WR1_SWAP_RAW_SHIFT 8U +/*! Slice: mcm_rd_issue_cap:*/ +#define MCM_RD_ISSUE_CAP +#define MCM_RD_ISSUE_CAP_MASK 0x000000C0U +#define MCM_RD_ISSUE_CAP_SHIFT 6U +/*! Slice: mcm_wr_issue_cap:*/ +#define MCM_WR_ISSUE_CAP +#define MCM_WR_ISSUE_CAP_MASK 0x00000030U +#define MCM_WR_ISSUE_CAP_SHIFT 4U +/*! Slice: mcm_rd_burst_len:*/ +#define MCM_RD_BURST_LEN +#define MCM_RD_BURST_LEN_MASK 0x0000000CU +#define MCM_RD_BURST_LEN_SHIFT 2U +/*! Slice: mcm_wr_burst_len:*/ +#define MCM_WR_BURST_LEN +#define MCM_WR_BURST_LEN_MASK 0x00000003U +#define MCM_WR_BURST_LEN_SHIFT 0U +/*! Register: miv2_mcm_bus_id (0x0000160c)*/ +/*! Slice: mcm_bus_sw_en:*/ +#define MCM_BUS_SW_EN +#define MCM_BUS_SW_EN_MASK 0x08000000U +#define MCM_BUS_SW_EN_SHIFT 27U +/*! Slice: mcm_rd_id_en:*/ +#define MCM_RD_ID_EN +#define MCM_RD_ID_EN_MASK 0x04000000U +#define MCM_RD_ID_EN_SHIFT 26U +/*! Slice: mcm_rd_id_cfg:*/ +#define MCM_RD_ID_CFG +#define MCM_RD_ID_CFG_MASK 0x03FC0000U +#define MCM_RD_ID_CFG_SHIFT 18U +/*! Slice: mcm_wr0_id_en:*/ +#define MCM_WR0_ID_EN +#define MCM_WR0_ID_EN_MASK 0x00020000U +#define MCM_WR0_ID_EN_SHIFT 17U +/*! Slice: mcm_wr0_id_cfg:*/ +#define MCM_WR0_ID_CFG +#define MCM_WR0_ID_CFG_MASK 0x0001FE00U +#define MCM_WR0_ID_CFG_SHIFT 9U +/*! Slice: mcm_wr1_id_en:*/ +#define MCM_WR1_ID_EN +#define MCM_WR1_ID_EN_MASK 0x00000100U +#define MCM_WR1_ID_EN_SHIFT 8U +/*! Slice: mcm_wr1_id_cfg:*/ +#define MCM_WR1_ID_CFG +#define MCM_WR1_ID_CFG_MASK 0x000000FFU +#define MCM_WR1_ID_CFG_SHIFT 0U +/*! Register: miv2_mcm_bus_timeo (0x00001610)*/ +/*! Slice: mcm_bus_timeo_en:*/ +#define MCM_BUS_TIMEO_EN +#define MCM_BUS_TIMEO_EN_MASK 0x80000000U +#define MCM_BUS_TIMEO_EN_SHIFT 31U +/*! Slice: mcm_bus_timeo:*/ +#define MCM_BUS_TIMEO +#define MCM_BUS_TIMEO_MASK 0x7FFFFFFFU +#define MCM_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_mcm_raw0_base_ad_init (0x00001614)*/ +/*! Slice: mcm_raw0_base_ad_init:*/ +#define MCM_RAW0_BASE_AD_INIT +#define MCM_RAW0_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MCM_RAW0_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw0_size_init (0x00001618)*/ +/*! Slice: mcm_raw0_size_init:*/ +#define MCM_RAW0_SIZE_INIT +#define MCM_RAW0_SIZE_INIT_MASK 0x1FFFFFF0U +#define MCM_RAW0_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw0_offs_cnt_init (0x0000161c)*/ +/*! Slice: mcm_raw0_offs_cnt_init:*/ +#define MCM_RAW0_OFFS_CNT_INIT +#define MCM_RAW0_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define MCM_RAW0_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw0_llength (0x00001620)*/ +/*! Slice: mcm_raw0_llengh:*/ +#define MCM_RAW0_LLENGH +#define MCM_RAW0_LLENGH_MASK 0x00007FFFU +#define MCM_RAW0_LLENGH_SHIFT 0U +/*! Register: miv2_mcm_raw0_pic_width (0x00001624)*/ +/*! Slice: mcm_raw0_pic_width:*/ +#define MCM_RAW0_PIC_WIDTH +#define MCM_RAW0_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MCM_RAW0_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mcm_raw0_pic_height (0x00001628)*/ +/*! Slice: mcm_raw0_pic_height:*/ +#define MCM_RAW0_PIC_HEIGHT +#define MCM_RAW0_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MCM_RAW0_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_mcm_raw0_pic_size (0x0000162c)*/ +/*! Slice: mcm_raw0_pic_size:*/ +#define MCM_RAW0_PIC_SIZE +#define MCM_RAW0_PIC_SIZE_MASK 0xFFFFFFFFU +#define MCM_RAW0_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mcm_raw0_offs_cnt_start (0x00001630)*/ +/*! Slice: mcm_raw0_offs_cnt_start:*/ +#define MCM_RAW0_OFFS_CNT_START +#define MCM_RAW0_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define MCM_RAW0_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mcm_raw0_base_ad_shd (0x00001634)*/ +/*! Slice: mcm_raw0_base_ad:*/ +#define MCM_RAW0_BASE_AD +#define MCM_RAW0_BASE_AD_MASK 0xFFFFFFF0U +#define MCM_RAW0_BASE_AD_SHIFT 4U +/*! Register: miv2_mcm_raw0_size_shd (0x00001638)*/ +/*! Slice: mcm_raw0_size:*/ +#define MCM_RAW0_SIZE +#define MCM_RAW0_SIZE_MASK 0x1FFFFFF0U +#define MCM_RAW0_SIZE_SHIFT 4U +/*! Register: miv2_mcm_raw0_offs_cnt_shd (0x0000163c)*/ +/*! Slice: mcm_raw0_offs_cnt:*/ +#define MCM_RAW0_OFFS_CNT +#define MCM_RAW0_OFFS_CNT_MASK 0x1FFFFFF0U +#define MCM_RAW0_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mcm_raw1_base_ad_init (0x00001640)*/ +/*! Slice: mcm_raw1_base_ad_init:*/ +#define MCM_RAW1_BASE_AD_INIT +#define MCM_RAW1_BASE_AD_INIT_MASK 0xFFFFFFF0U +#define MCM_RAW1_BASE_AD_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw1_size_init (0x00001644)*/ +/*! Slice: mcm_raw1_size_init:*/ +#define MCM_RAW1_SIZE_INIT +#define MCM_RAW1_SIZE_INIT_MASK 0x1FFFFFF0U +#define MCM_RAW1_SIZE_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw1_offs_cnt_init (0x00001648)*/ +/*! Slice: mcm_raw1_offs_cnt_init:*/ +#define MCM_RAW1_OFFS_CNT_INIT +#define MCM_RAW1_OFFS_CNT_INIT_MASK 0x1FFFFFF0U +#define MCM_RAW1_OFFS_CNT_INIT_SHIFT 4U +/*! Register: miv2_mcm_raw1_llength (0x0000164c)*/ +/*! Slice: mcm_raw1_llengh:*/ +#define MCM_RAW1_LLENGH +#define MCM_RAW1_LLENGH_MASK 0x00007FFFU +#define MCM_RAW1_LLENGH_SHIFT 0U +/*! Register: miv2_mcm_raw1_pic_width (0x00001650)*/ +/*! Slice: mcm_raw1_pic_width:*/ +#define MCM_RAW1_PIC_WIDTH +#define MCM_RAW1_PIC_WIDTH_MASK 0xFFFFFFFFU +#define MCM_RAW1_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mcm_raw1_pic_height (0x00001654)*/ +/*! Slice: mcm_raw1_pic_height:*/ +#define MCM_RAW1_PIC_HEIGHT +#define MCM_RAW1_PIC_HEIGHT_MASK 0xFFFFFFFFU +#define MCM_RAW1_PIC_HEIGHT_SHIFT 0U +/*! Register: miv2_mcm_raw1_pic_size (0x00001658)*/ +/*! Slice: mcm_raw1_pic_size:*/ +#define MCM_RAW1_PIC_SIZE +#define MCM_RAW1_PIC_SIZE_MASK 0xFFFFFFFFU +#define MCM_RAW1_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mcm_raw1_offs_cnt_start (0x0000165c)*/ +/*! Slice: mcm_raw1_offs_cnt_start:*/ +#define MCM_RAW1_OFFS_CNT_START +#define MCM_RAW1_OFFS_CNT_START_MASK 0x1FFFFFF0U +#define MCM_RAW1_OFFS_CNT_START_SHIFT 4U +/*! Register: miv2_mcm_raw1_base_ad_shd (0x00001660)*/ +/*! Slice: mcm_raw1_base_ad:*/ +#define MCM_RAW1_BASE_AD +#define MCM_RAW1_BASE_AD_MASK 0xFFFFFFF0U +#define MCM_RAW1_BASE_AD_SHIFT 4U +/*! Register: miv2_mcm_raw1_size_shd (0x00001664)*/ +/*! Slice: mcm_raw1_size:*/ +#define MCM_RAW1_SIZE +#define MCM_RAW1_SIZE_MASK 0x1FFFFFF0U +#define MCM_RAW1_SIZE_SHIFT 4U +/*! Register: miv2_mcm_raw1_offs_cnt_shd (0x00001668)*/ +/*! Slice: mcm_raw1_offs_cnt:*/ +#define MCM_RAW1_OFFS_CNT +#define MCM_RAW1_OFFS_CNT_MASK 0x1FFFFFF0U +#define MCM_RAW1_OFFS_CNT_SHIFT 4U +/*! Register: miv2_mcm_dma_raw_pic_start_ad (0x0000166c)*/ +/*! Slice: mcm_dma_raw_pic_start_ad:*/ +#define MCM_DMA_RAW_PIC_START_AD +#define MCM_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U +#define MCM_DMA_RAW_PIC_START_AD_SHIFT 4U +/*! Register: miv2_mcm_dma_raw_pic_width (0x00001670)*/ +/*! Slice: mcm_dma_raw_pic_width:*/ +#define MCM_DMA_RAW_PIC_WIDTH +#define MCM_DMA_RAW_PIC_WIDTH_MASK 0x00007FFFU +#define MCM_DMA_RAW_PIC_WIDTH_SHIFT 0U +/*! Register: miv2_mcm_dma_raw_pic_llength (0x00001674)*/ +/*! Slice: mcm_dma_raw_pic_llength:*/ +#define MCM_DMA_RAW_PIC_LLENGTH +#define MCM_DMA_RAW_PIC_LLENGTH_MASK 0x00007FFFU +#define MCM_DMA_RAW_PIC_LLENGTH_SHIFT 0U +/*! Register: miv2_mcm_dma_raw_pic_size (0x00001678)*/ +/*! Slice: mcm_dma_raw_pic_size:*/ +#define MCM_DMA_RAW_PIC_SIZE +#define MCM_DMA_RAW_PIC_SIZE_MASK 0x0FFFFFFFU +#define MCM_DMA_RAW_PIC_SIZE_SHIFT 0U +/*! Register: miv2_mcm_dma_raw_pic_start_ad_shd (0x0000167c)*/ +/*! Slice: mcm_dma_raw_pic_start_ad:*/ +#define MCM_DMA_RAW_PIC_START_AD +#define MCM_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U +#define MCM_DMA_RAW_PIC_START_AD_SHIFT 4U +/*! Register: miv2_mcm_status_clr (0x00001680)*/ +/*! Slice: mcm_raw1_fifo_full:*/ +#define MCM_RAW1_FIFO_FULL +#define MCM_RAW1_FIFO_FULL_MASK 0x00000002U +#define MCM_RAW1_FIFO_FULL_SHIFT 1U +/*! Slice: mcm_raw0_fifo_full:*/ +#define MCM_RAW0_FIFO_FULL +#define MCM_RAW0_FIFO_FULL_MASK 0x00000001U +#define MCM_RAW0_FIFO_FULL_SHIFT 0U +/*! Register: miv2_mcm_ctrl_status (0x00001684)*/ +/*! Slice: mcm_raw1_fifo_full:*/ +#define MCM_RAW1_FIFO_FULL +#define MCM_RAW1_FIFO_FULL_MASK 0x00000002U +#define MCM_RAW1_FIFO_FULL_SHIFT 1U +/*! Slice: mcm_raw0_fifo_full:*/ +#define MCM_RAW0_FIFO_FULL +#define MCM_RAW0_FIFO_FULL_MASK 0x00000001U +#define MCM_RAW0_FIFO_FULL_SHIFT 0U +/*! Register: miv2_mcm_axi_status (0x00001688)*/ +/*! Slice: agsw_enc_pic_rdy:*/ +#define AGSW_ENC_PIC_RDY +#define AGSW_ENC_PIC_RDY_MASK 0x00000002U +#define AGSW_ENC_PIC_RDY_SHIFT 1U +/*! Slice: agsw_enc_buf_full:*/ +#define AGSW_ENC_BUF_FULL +#define AGSW_ENC_BUF_FULL_MASK 0x00000001U +#define AGSW_ENC_BUF_FULL_SHIFT 0U +/*! Register: miv2_mcm_dma_status (0x0000168c)*/ +/*! Slice: mcm_dma_active:*/ +#define MCM_DMA_ACTIVE +#define MCM_DMA_ACTIVE_MASK 0x00000001U +#define MCM_DMA_ACTIVE_SHIFT 0U +/*! Register: miv2_imsc (0x000016c0)*/ +/*! Slice: fill_mp_y:*/ +#define FILL_MP_Y +#define FILL_MP_Y_MASK 0x08000000U +#define FILL_MP_Y_SHIFT 27U +/*! Slice: mblk_line:*/ +#define MBLK_LINE +#define MBLK_LINE_MASK 0x04000000U +#define MBLK_LINE_SHIFT 26U +/*! Slice: mp_handshk_int:*/ +#define MP_HANDSHK_INT +#define MP_HANDSHK_INT_MASK 0x02000000U +#define MP_HANDSHK_INT_SHIFT 25U +/*! Slice: mcm_dma_raw_ready:*/ +#define MCM_DMA_RAW_READY +#define MCM_DMA_RAW_READY_MASK 0x01000000U +#define MCM_DMA_RAW_READY_SHIFT 24U +/*! Slice: sp2_dma_raw_ready:*/ +#define SP2_DMA_RAW_READY +#define SP2_DMA_RAW_READY_MASK 0x00800000U +#define SP2_DMA_RAW_READY_SHIFT 23U +/*! Slice: sp2_dma_ycbcr_ready:*/ +#define SP2_DMA_YCBCR_READY +#define SP2_DMA_YCBCR_READY_MASK 0x00400000U +#define SP2_DMA_YCBCR_READY_SHIFT 22U +/*! Slice: wrap_mcm_raw1:*/ +#define WRAP_MCM_RAW1 +#define WRAP_MCM_RAW1_MASK 0x00200000U +#define WRAP_MCM_RAW1_SHIFT 21U +/*! Slice: wrap_mcm_raw0:*/ +#define WRAP_MCM_RAW0 +#define WRAP_MCM_RAW0_MASK 0x00100000U +#define WRAP_MCM_RAW0_SHIFT 20U +/*! Slice: wrap_sp2_cr:*/ +#define WRAP_SP2_CR +#define WRAP_SP2_CR_MASK 0x00040000U +#define WRAP_SP2_CR_SHIFT 18U +/*! Slice: wrap_sp2_cb:*/ +#define WRAP_SP2_CB +#define WRAP_SP2_CB_MASK 0x00020000U +#define WRAP_SP2_CB_SHIFT 17U +/*! Slice: wrap_sp2_y:*/ +#define WRAP_SP2_Y +#define WRAP_SP2_Y_MASK 0x00010000U +#define WRAP_SP2_Y_SHIFT 16U +/*! Slice: wrap_sp1_cr:*/ +#define WRAP_SP1_CR +#define WRAP_SP1_CR_MASK 0x00008000U +#define WRAP_SP1_CR_SHIFT 15U +/*! Slice: wrap_sp1_cb:*/ +#define WRAP_SP1_CB +#define WRAP_SP1_CB_MASK 0x00004000U +#define WRAP_SP1_CB_SHIFT 14U +/*! Slice: wrap_sp1_y:*/ +#define WRAP_SP1_Y +#define WRAP_SP1_Y_MASK 0x00002000U +#define WRAP_SP1_Y_SHIFT 13U +/*! Slice: wrap_mp_jdp:*/ +#define WRAP_MP_JDP +#define WRAP_MP_JDP_MASK 0x00001000U +#define WRAP_MP_JDP_SHIFT 12U +/*! Slice: wrap_mp_raw:*/ +#define WRAP_MP_RAW +#define WRAP_MP_RAW_MASK 0x00000800U +#define WRAP_MP_RAW_SHIFT 11U +/*! Slice: wrap_mp_cr:*/ +#define WRAP_MP_CR +#define WRAP_MP_CR_MASK 0x00000400U +#define WRAP_MP_CR_SHIFT 10U +/*! Slice: wrap_mp_cb:*/ +#define WRAP_MP_CB +#define WRAP_MP_CB_MASK 0x00000200U +#define WRAP_MP_CB_SHIFT 9U +/*! Slice: wrap_mp_y:*/ +#define WRAP_MP_Y +#define WRAP_MP_Y_MASK 0x00000100U +#define WRAP_MP_Y_SHIFT 8U +/*! Slice: mcm_raw1_frame_end:*/ +#define MCM_RAW1_FRAME_END +#define MCM_RAW1_FRAME_END_MASK 0x00000080U +#define MCM_RAW1_FRAME_END_SHIFT 7U +/*! Slice: mcm_raw0_frame_end:*/ +#define MCM_RAW0_FRAME_END +#define MCM_RAW0_FRAME_END_MASK 0x00000040U +#define MCM_RAW0_FRAME_END_SHIFT 6U +/*! Slice: sp2_raw_frame_end:*/ +#define SP2_RAW_FRAME_END +#define SP2_RAW_FRAME_END_MASK 0x00000020U +#define SP2_RAW_FRAME_END_SHIFT 5U +/*! Slice: sp2_ycbcr_frame_end:*/ +#define SP2_YCBCR_FRAME_END +#define SP2_YCBCR_FRAME_END_MASK 0x00000010U +#define SP2_YCBCR_FRAME_END_SHIFT 4U +/*! Slice: sp1_ycbcr_frame_end:*/ +#define SP1_YCBCR_FRAME_END +#define SP1_YCBCR_FRAME_END_MASK 0x00000008U +#define SP1_YCBCR_FRAME_END_SHIFT 3U +/*! Slice: mp_jdp_frame_end:*/ +#define MP_JDP_FRAME_END +#define MP_JDP_FRAME_END_MASK 0x00000004U +#define MP_JDP_FRAME_END_SHIFT 2U +/*! Slice: mp_raw_frame_end:*/ +#define MP_RAW_FRAME_END +#define MP_RAW_FRAME_END_MASK 0x00000002U +#define MP_RAW_FRAME_END_SHIFT 1U +/*! Slice: mp_ycbcr_frame_end:*/ +#define MP_YCBCR_FRAME_END +#define MP_YCBCR_FRAME_END_MASK 0x00000001U +#define MP_YCBCR_FRAME_END_SHIFT 0U +/*! Register: miv2_imsc1 (0x000016c4)*/ +/*! Slice: miv2_mcm_bus_buserr:*/ +#define MI_MCM_BUS_BUSERR +#define MI_MCM_BUS_BUSERR_MASK 0x00000080U +#define MI_MCM_BUS_BUSERR_SHIFT 7U +/*! Slice: miv2_mcm_bus_timeo:*/ +#define MI_MCM_BUS_TIMEO +#define MI_MCM_BUS_TIMEO_MASK 0x00000040U +#define MI_MCM_BUS_TIMEO_SHIFT 6U +/*! Slice: miv2_sp2_bus_buserr:*/ +#define MI_SP2_BUS_BUSERR +#define MI_SP2_BUS_BUSERR_MASK 0x00000020U +#define MI_SP2_BUS_BUSERR_SHIFT 5U +/*! Slice: miv2_sp2_bus_timeo:*/ +#define MI_SP2_BUS_TIMEO +#define MI_SP2_BUS_TIMEO_MASK 0x00000010U +#define MI_SP2_BUS_TIMEO_SHIFT 4U +/*! Slice: miv2_sp1_bus_buserr:*/ +#define MI_SP1_BUS_BUSERR +#define MI_SP1_BUS_BUSERR_MASK 0x00000008U +#define MI_SP1_BUS_BUSERR_SHIFT 3U +/*! Slice: miv2_sp1_bus_timeo:*/ +#define MI_SP1_BUS_TIMEO +#define MI_SP1_BUS_TIMEO_MASK 0x00000004U +#define MI_SP1_BUS_TIMEO_SHIFT 2U +/*! Slice: miv2_mp_bus_buserr:*/ +#define MI_MP_BUS_BUSERR +#define MI_MP_BUS_BUSERR_MASK 0x00000002U +#define MI_MP_BUS_BUSERR_SHIFT 1U +/*! Slice: miv2_mp_bus_timeo:*/ +#define MI_MP_BUS_TIMEO +#define MI_MP_BUS_TIMEO_MASK 0x00000001U +#define MI_MP_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_isr (0x000016c8)*/ +/*! Slice: fill_mp_y:*/ +#define FILL_MP_Y +#define FILL_MP_Y_MASK 0x08000000U +#define FILL_MP_Y_SHIFT 27U +/*! Slice: mblk_line:*/ +#define MBLK_LINE +#define MBLK_LINE_MASK 0x04000000U +#define MBLK_LINE_SHIFT 26U +/*! Slice: mp_handshk_int:*/ +#define MP_HANDSHK_INT +#define MP_HANDSHK_INT_MASK 0x02000000U +#define MP_HANDSHK_INT_SHIFT 25U +/*! Slice: mcm_dma_raw_ready:*/ +#define MCM_DMA_RAW_READY +#define MCM_DMA_RAW_READY_MASK 0x01000000U +#define MCM_DMA_RAW_READY_SHIFT 24U +/*! Slice: sp2_dma_raw_ready:*/ +#define SP2_DMA_RAW_READY +#define SP2_DMA_RAW_READY_MASK 0x00800000U +#define SP2_DMA_RAW_READY_SHIFT 23U +/*! Slice: sp2_dma_ycbcr_ready:*/ +#define SP2_DMA_YCBCR_READY +#define SP2_DMA_YCBCR_READY_MASK 0x00400000U +#define SP2_DMA_YCBCR_READY_SHIFT 22U +/*! Slice: wrap_mcm_raw1:*/ +#define WRAP_MCM_RAW1 +#define WRAP_MCM_RAW1_MASK 0x00200000U +#define WRAP_MCM_RAW1_SHIFT 21U +/*! Slice: wrap_mcm_raw0:*/ +#define WRAP_MCM_RAW0 +#define WRAP_MCM_RAW0_MASK 0x00100000U +#define WRAP_MCM_RAW0_SHIFT 20U +/*! Slice: wrap_sp2_cr:*/ +#define WRAP_SP2_CR +#define WRAP_SP2_CR_MASK 0x00040000U +#define WRAP_SP2_CR_SHIFT 18U +/*! Slice: wrap_sp2_cb:*/ +#define WRAP_SP2_CB +#define WRAP_SP2_CB_MASK 0x00020000U +#define WRAP_SP2_CB_SHIFT 17U +/*! Slice: wrap_sp2_y:*/ +#define WRAP_SP2_Y +#define WRAP_SP2_Y_MASK 0x00010000U +#define WRAP_SP2_Y_SHIFT 16U +/*! Slice: wrap_sp1_cr:*/ +#define WRAP_SP1_CR +#define WRAP_SP1_CR_MASK 0x00008000U +#define WRAP_SP1_CR_SHIFT 15U +/*! Slice: wrap_sp1_cb:*/ +#define WRAP_SP1_CB +#define WRAP_SP1_CB_MASK 0x00004000U +#define WRAP_SP1_CB_SHIFT 14U +/*! Slice: wrap_sp1_y:*/ +#define WRAP_SP1_Y +#define WRAP_SP1_Y_MASK 0x00002000U +#define WRAP_SP1_Y_SHIFT 13U +/*! Slice: wrap_mp_jdp:*/ +#define WRAP_MP_JDP +#define WRAP_MP_JDP_MASK 0x00001000U +#define WRAP_MP_JDP_SHIFT 12U +/*! Slice: wrap_mp_raw:*/ +#define WRAP_MP_RAW +#define WRAP_MP_RAW_MASK 0x00000800U +#define WRAP_MP_RAW_SHIFT 11U +/*! Slice: wrap_mp_cr:*/ +#define WRAP_MP_CR +#define WRAP_MP_CR_MASK 0x00000400U +#define WRAP_MP_CR_SHIFT 10U +/*! Slice: wrap_mp_cb:*/ +#define WRAP_MP_CB +#define WRAP_MP_CB_MASK 0x00000200U +#define WRAP_MP_CB_SHIFT 9U +/*! Slice: wrap_mp_y:*/ +#define WRAP_MP_Y +#define WRAP_MP_Y_MASK 0x00000100U +#define WRAP_MP_Y_SHIFT 8U +/*! Slice: mcm_raw1_frame_end:*/ +#define MCM_RAW1_FRAME_END +#define MCM_RAW1_FRAME_END_MASK 0x00000080U +#define MCM_RAW1_FRAME_END_SHIFT 7U +/*! Slice: mcm_raw0_frame_end:*/ +#define MCM_RAW0_FRAME_END +#define MCM_RAW0_FRAME_END_MASK 0x00000040U +#define MCM_RAW0_FRAME_END_SHIFT 6U +/*! Slice: sp2_raw_frame_end:*/ +#define SP2_RAW_FRAME_END +#define SP2_RAW_FRAME_END_MASK 0x00000020U +#define SP2_RAW_FRAME_END_SHIFT 5U +/*! Slice: sp2_ycbcr_frame_end:*/ +#define SP2_YCBCR_FRAME_END +#define SP2_YCBCR_FRAME_END_MASK 0x00000010U +#define SP2_YCBCR_FRAME_END_SHIFT 4U +/*! Slice: sp1_ycbcr_frame_end:*/ +#define SP1_YCBCR_FRAME_END +#define SP1_YCBCR_FRAME_END_MASK 0x00000008U +#define SP1_YCBCR_FRAME_END_SHIFT 3U +/*! Slice: mp_jdp_frame_end:*/ +#define MP_JDP_FRAME_END +#define MP_JDP_FRAME_END_MASK 0x00000004U +#define MP_JDP_FRAME_END_SHIFT 2U +/*! Slice: mp_raw_frame_end:*/ +#define MP_RAW_FRAME_END +#define MP_RAW_FRAME_END_MASK 0x00000002U +#define MP_RAW_FRAME_END_SHIFT 1U +/*! Slice: mp_ycbcr_frame_end:*/ +#define MP_YCBCR_FRAME_END +#define MP_YCBCR_FRAME_END_MASK 0x00000001U +#define MP_YCBCR_FRAME_END_SHIFT 0U +/*! Register: miv2_isr1 (0x000016cc)*/ +/*! Slice: miv2_mcm_bus_buserr:*/ +#define MI_MCM_BUS_BUSERR +#define MI_MCM_BUS_BUSERR_MASK 0x00000080U +#define MI_MCM_BUS_BUSERR_SHIFT 7U +/*! Slice: miv2_mcm_bus_timeo:*/ +#define MI_MCM_BUS_TIMEO +#define MI_MCM_BUS_TIMEO_MASK 0x00000040U +#define MI_MCM_BUS_TIMEO_SHIFT 6U +/*! Slice: miv2_sp2_bus_buserr:*/ +#define MI_SP2_BUS_BUSERR +#define MI_SP2_BUS_BUSERR_MASK 0x00000020U +#define MI_SP2_BUS_BUSERR_SHIFT 5U +/*! Slice: miv2_sp2_bus_timeo:*/ +#define MI_SP2_BUS_TIMEO +#define MI_SP2_BUS_TIMEO_MASK 0x00000010U +#define MI_SP2_BUS_TIMEO_SHIFT 4U +/*! Slice: miv2_sp1_bus_buserr:*/ +#define MI_SP1_BUS_BUSERR +#define MI_SP1_BUS_BUSERR_MASK 0x00000008U +#define MI_SP1_BUS_BUSERR_SHIFT 3U +/*! Slice: miv2_sp1_bus_timeo:*/ +#define MI_SP1_BUS_TIMEO +#define MI_SP1_BUS_TIMEO_MASK 0x00000004U +#define MI_SP1_BUS_TIMEO_SHIFT 2U +#define MRV_MI_BP_PATH_ENABLE +#define MRV_MI_BP_PATH_ENABLE_MASK 0x00000001U +#define MRV_MI_BP_PATH_ENABLE_SHIFT 0U +/*! Register: bp_ctrl: Control register */ +/*! Slice: bp_output_format */ +/* 000 raw8 + 001 raw10 + 010 raw12 +*/ +#define MRV_MI_BP_WRITE_RAWBIT +#define MRV_MI_BP_WRITE_RAWBIT_MASK 0x0000001cU +#define MRV_MI_BP_WRITE_RAWBIT_SHIFT 2U +#define MRV_MI_BP_WRITE_FORMAT +#define MRV_MI_BP_WRITE_FORMAT_MASK 0x00000300U +#define MRV_MI_BP_WRITE_FORMAT_SHIFT 8U +#define MRV_MI_BP_WRITE_PLANAR_FORMAT 1 +#define MRV_MI_BP_WRITE_INTERLEAVE_FORMAT 2 +/*! Slice: miv2_mp_bus_buserr:*/ +#define MI_MP_BUS_BUSERR +#define MI_MP_BUS_BUSERR_MASK 0x00000002U +#define MI_MP_BUS_BUSERR_SHIFT 1U +/*! Slice: miv2_mp_bus_timeo:*/ +#define MI_MP_BUS_TIMEO +#define MI_MP_BUS_TIMEO_MASK 0x00000001U +#define MI_MP_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_mis (0x000016d0) */ +/*! Slice: fill_mp_y: */ +#define FILL_MP_Y +#define FILL_MP_Y_MASK 0x08000000U +#define FILL_MP_Y_SHIFT 27U +/*! Slice: mblk_line: */ +#define MBLK_LINE +#define MBLK_LINE_MASK 0x04000000U +#define MBLK_LINE_SHIFT 26U +/*! Slice: mp_handshk_int: */ +#define MP_HANDSHK_INT +#define MP_HANDSHK_INT_MASK 0x02000000U +#define MP_HANDSHK_INT_SHIFT 25U +/*! Slice: mcm_dma_raw_ready: */ +#define MCM_DMA_RAW_READY +#define MCM_DMA_RAW_READY_MASK 0x01000000U +#define MCM_DMA_RAW_READY_SHIFT 24U +/*! Slice: sp2_dma_raw_ready: */ +#define SP2_DMA_RAW_READY +#define SP2_DMA_RAW_READY_MASK 0x00800000U +#define SP2_DMA_RAW_READY_SHIFT 23U +/*! Slice: sp2_dma_ycbcr_ready: */ +#define SP2_DMA_YCBCR_READY +#define SP2_DMA_YCBCR_READY_MASK 0x00400000U +#define SP2_DMA_YCBCR_READY_SHIFT 22U +/*! Slice: wrap_mcm_raw1: */ +#define WRAP_MCM_RAW1 +#define WRAP_MCM_RAW1_MASK 0x00200000U +#define WRAP_MCM_RAW1_SHIFT 21U +/*! Slice: wrap_mcm_raw0: */ +#define WRAP_MCM_RAW0 +#define WRAP_MCM_RAW0_MASK 0x00100000U +#define WRAP_MCM_RAW0_SHIFT 20U +/*! Slice: wrap_sp2_cr: */ +#define WRAP_SP2_CR +#define WRAP_SP2_CR_MASK 0x00040000U +#define WRAP_SP2_CR_SHIFT 18U +/*! Slice: wrap_sp2_cb: */ +#define WRAP_SP2_CB +#define WRAP_SP2_CB_MASK 0x00020000U +#define WRAP_SP2_CB_SHIFT 17U +/*! Slice: wrap_sp2_y: */ +#define WRAP_SP2_Y +#define WRAP_SP2_Y_MASK 0x00010000U +#define WRAP_SP2_Y_SHIFT 16U +/*! Slice: wrap_sp1_cr: */ +#define WRAP_SP1_CR +#define WRAP_SP1_CR_MASK 0x00008000U +#define WRAP_SP1_CR_SHIFT 15U +/*! Slice: wrap_sp1_cb: */ +#define WRAP_SP1_CB +#define WRAP_SP1_CB_MASK 0x00004000U +#define WRAP_SP1_CB_SHIFT 14U +/*! Slice: wrap_sp1_y: */ +#define WRAP_SP1_Y +#define WRAP_SP1_Y_MASK 0x00002000U +#define WRAP_SP1_Y_SHIFT 13U +/*! Slice: wrap_mp_jdp: */ +#define WRAP_MP_JDP +#define WRAP_MP_JDP_MASK 0x00001000U +#define WRAP_MP_JDP_SHIFT 12U +/*! Slice: wrap_mp_raw: */ +#define WRAP_MP_RAW +#define WRAP_MP_RAW_MASK 0x00000800U +#define WRAP_MP_RAW_SHIFT 11U +/*! Slice: wrap_mp_cr: */ +#define WRAP_MP_CR +#define WRAP_MP_CR_MASK 0x00000400U +#define WRAP_MP_CR_SHIFT 10U +/*! Slice: wrap_mp_cb: */ +#define WRAP_MP_CB +#define WRAP_MP_CB_MASK 0x00000200U +#define WRAP_MP_CB_SHIFT 9U +/*! Slice: wrap_mp_y: */ +#define WRAP_MP_Y +#define WRAP_MP_Y_MASK 0x00000100U +#define WRAP_MP_Y_SHIFT 8U +/*! Slice: mcm_raw1_frame_end: */ +#define MCM_RAW1_FRAME_END +#define MCM_RAW1_FRAME_END_MASK 0x00000080U +#define MCM_RAW1_FRAME_END_SHIFT 7U +/*! Slice: mcm_raw0_frame_end: */ +#define MCM_RAW0_FRAME_END +#define MCM_RAW0_FRAME_END_MASK 0x00000040U +#define MCM_RAW0_FRAME_END_SHIFT 6U +/*! Slice: sp2_raw_frame_end: */ +#define SP2_RAW_FRAME_END +#define SP2_RAW_FRAME_END_MASK 0x00000020U +#define SP2_RAW_FRAME_END_SHIFT 5U +/*! Slice: sp2_ycbcr_frame_end: */ +#define SP2_YCBCR_FRAME_END +#define SP2_YCBCR_FRAME_END_MASK 0x00000010U +#define SP2_YCBCR_FRAME_END_SHIFT 4U +/*! Slice: sp1_ycbcr_frame_end: */ +#define SP1_YCBCR_FRAME_END +#define SP1_YCBCR_FRAME_END_MASK 0x00000008U +#define SP1_YCBCR_FRAME_END_SHIFT 3U +/*! Slice: mp_jdp_frame_end: */ +#define MP_JDP_FRAME_END +#define MP_JDP_FRAME_END_MASK 0x00000004U +#define MP_JDP_FRAME_END_SHIFT 2U +/*! Slice: mp_raw_frame_end: */ +#define MP_RAW_FRAME_END +#define MP_RAW_FRAME_END_MASK 0x00000002U +#define MP_RAW_FRAME_END_SHIFT 1U +/*! Slice: mp_ycbcr_frame_end: */ +#define MP_YCBCR_FRAME_END +#define MP_YCBCR_FRAME_END_MASK 0x00000001U +#define MP_YCBCR_FRAME_END_SHIFT 0U +/*! Register: miv2_mis1 (0x000016d4) */ +/*! Slice: miv2_mcm_bus_buserr: */ +#define MI_MCM_BUS_BUSERR +#define MI_MCM_BUS_BUSERR_MASK 0x00000080U +#define MI_MCM_BUS_BUSERR_SHIFT 7U +/*! Slice: miv2_mcm_bus_timeo: */ +#define MI_MCM_BUS_TIMEO +#define MI_MCM_BUS_TIMEO_MASK 0x00000040U +#define MI_MCM_BUS_TIMEO_SHIFT 6U +/*! Slice: miv2_sp2_bus_buserr: */ +#define MI_SP2_BUS_BUSERR +#define MI_SP2_BUS_BUSERR_MASK 0x00000020U +#define MI_SP2_BUS_BUSERR_SHIFT 5U +/*! Slice: miv2_sp2_bus_timeo: */ +#define MI_SP2_BUS_TIMEO +#define MI_SP2_BUS_TIMEO_MASK 0x00000010U +#define MI_SP2_BUS_TIMEO_SHIFT 4U +/*! Slice: miv2_sp1_bus_buserr: */ +#define MI_SP1_BUS_BUSERR +#define MI_SP1_BUS_BUSERR_MASK 0x00000008U +#define MI_SP1_BUS_BUSERR_SHIFT 3U +/*! Slice: miv2_sp1_bus_timeo: */ +#define MI_SP1_BUS_TIMEO +#define MI_SP1_BUS_TIMEO_MASK 0x00000004U +#define MI_SP1_BUS_TIMEO_SHIFT 2U +/*! Slice: miv2_mp_bus_buserr: */ +#define MI_MP_BUS_BUSERR +#define MI_MP_BUS_BUSERR_MASK 0x00000002U +#define MI_MP_BUS_BUSERR_SHIFT 1U +/*! Slice: miv2_mp_bus_timeo: */ +#define MI_MP_BUS_TIMEO +#define MI_MP_BUS_TIMEO_MASK 0x00000001U +#define MI_MP_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_icr (0x000016d8) */ +/*! Slice: fill_mp_y: */ +#define FILL_MP_Y +#define FILL_MP_Y_MASK 0x08000000U +#define FILL_MP_Y_SHIFT 27U +/*! Slice: mblk_line: */ +#define MBLK_LINE +#define MBLK_LINE_MASK 0x04000000U +#define MBLK_LINE_SHIFT 26U +/*! Slice: mp_handshk_int: */ +#define MP_HANDSHK_INT +#define MP_HANDSHK_INT_MASK 0x02000000U +#define MP_HANDSHK_INT_SHIFT 25U +/*! Slice: mcm_dma_raw_ready: */ +#define MCM_DMA_RAW_READY +#define MCM_DMA_RAW_READY_MASK 0x01000000U +#define MCM_DMA_RAW_READY_SHIFT 24U +/*! Slice: sp2_dma_raw_ready: */ +#define SP2_DMA_RAW_READY +#define SP2_DMA_RAW_READY_MASK 0x00800000U +#define SP2_DMA_RAW_READY_SHIFT 23U +/*! Slice: sp2_dma_ycbcr_ready: */ +#define SP2_DMA_YCBCR_READY +#define SP2_DMA_YCBCR_READY_MASK 0x00400000U +#define SP2_DMA_YCBCR_READY_SHIFT 22U +/*! Slice: wrap_mcm_raw1: */ +#define WRAP_MCM_RAW1 +#define WRAP_MCM_RAW1_MASK 0x00200000U +#define WRAP_MCM_RAW1_SHIFT 21U +/*! Slice: wrap_mcm_raw0: */ +#define WRAP_MCM_RAW0 +#define WRAP_MCM_RAW0_MASK 0x00100000U +#define WRAP_MCM_RAW0_SHIFT 20U +/*! Slice: wrap_sp2_cr: */ +#define WRAP_SP2_CR +#define WRAP_SP2_CR_MASK 0x00040000U +#define WRAP_SP2_CR_SHIFT 18U +/*! Slice: wrap_sp2_cb: */ +#define WRAP_SP2_CB +#define WRAP_SP2_CB_MASK 0x00020000U +#define WRAP_SP2_CB_SHIFT 17U +/*! Slice: wrap_sp2_y: */ +#define WRAP_SP2_Y +#define WRAP_SP2_Y_MASK 0x00010000U +#define WRAP_SP2_Y_SHIFT 16U +/*! Slice: wrap_sp1_cr: */ +#define WRAP_SP1_CR +#define WRAP_SP1_CR_MASK 0x00008000U +#define WRAP_SP1_CR_SHIFT 15U +/*! Slice: wrap_sp1_cb: */ +#define WRAP_SP1_CB +#define WRAP_SP1_CB_MASK 0x00004000U +#define WRAP_SP1_CB_SHIFT 14U +/*! Slice: wrap_sp1_y: */ +#define WRAP_SP1_Y +#define WRAP_SP1_Y_MASK 0x00002000U +#define WRAP_SP1_Y_SHIFT 13U +/*! Slice: wrap_mp_jdp: */ +#define WRAP_MP_JDP +#define WRAP_MP_JDP_MASK 0x00001000U +#define WRAP_MP_JDP_SHIFT 12U +/*! Slice: wrap_mp_raw: */ +#define WRAP_MP_RAW +#define WRAP_MP_RAW_MASK 0x00000800U +#define WRAP_MP_RAW_SHIFT 11U +/*! Slice: wrap_mp_cr: */ +#define WRAP_MP_CR +#define WRAP_MP_CR_MASK 0x00000400U +#define WRAP_MP_CR_SHIFT 10U +/*! Slice: wrap_mp_cb: */ +#define WRAP_MP_CB +#define WRAP_MP_CB_MASK 0x00000200U +#define WRAP_MP_CB_SHIFT 9U +/*! Slice: wrap_mp_y: */ +#define WRAP_MP_Y +#define WRAP_MP_Y_MASK 0x00000100U +#define WRAP_MP_Y_SHIFT 8U +/*! Slice: mcm_raw1_frame_end: */ +#define MCM_RAW1_FRAME_END +#define MCM_RAW1_FRAME_END_MASK 0x00000080U +#define MCM_RAW1_FRAME_END_SHIFT 7U +/*! Slice: mcm_raw0_frame_end: */ +#define MCM_RAW0_FRAME_END +#define MCM_RAW0_FRAME_END_MASK 0x00000040U +#define MCM_RAW0_FRAME_END_SHIFT 6U +/*! Slice: sp2_raw_frame_end: */ +#define SP2_RAW_FRAME_END +#define SP2_RAW_FRAME_END_MASK 0x00000020U +#define SP2_RAW_FRAME_END_SHIFT 5U +/*! Slice: sp2_ycbcr_frame_end: */ +#define SP2_YCBCR_FRAME_END +#define SP2_YCBCR_FRAME_END_MASK 0x00000010U +#define SP2_YCBCR_FRAME_END_SHIFT 4U +/*! Slice: sp1_ycbcr_frame_end: */ +#define SP1_YCBCR_FRAME_END +#define SP1_YCBCR_FRAME_END_MASK 0x00000008U +#define SP1_YCBCR_FRAME_END_SHIFT 3U +/*! Slice: mp_jdp_frame_end: */ +#define MP_JDP_FRAME_END +#define MP_JDP_FRAME_END_MASK 0x00000004U +#define MP_JDP_FRAME_END_SHIFT 2U +/*! Slice: mp_raw_frame_end: */ +#define MP_RAW_FRAME_END +#define MP_RAW_FRAME_END_MASK 0x00000002U +#define MP_RAW_FRAME_END_SHIFT 1U +/*! Slice: mp_ycbcr_frame_end: */ +#define MP_YCBCR_FRAME_END +#define MP_YCBCR_FRAME_END_MASK 0x00000001U +#define MP_YCBCR_FRAME_END_SHIFT 0U +/*! Register: miv2_icr1 (0x000016dc) */ +/*! Slice: miv2_mcm_bus_buserr: */ +#define MI_MCM_BUS_BUSERR +#define MI_MCM_BUS_BUSERR_MASK 0x00000080U +#define MI_MCM_BUS_BUSERR_SHIFT 7U +/*! Slice: miv2_mcm_bus_timeo: */ +#define MI_MCM_BUS_TIMEO +#define MI_MCM_BUS_TIMEO_MASK 0x00000040U +#define MI_MCM_BUS_TIMEO_SHIFT 6U +/*! Slice: miv2_sp2_bus_buserr: */ +#define MI_SP2_BUS_BUSERR +#define MI_SP2_BUS_BUSERR_MASK 0x00000020U +#define MI_SP2_BUS_BUSERR_SHIFT 5U +/*! Slice: miv2_sp2_bus_timeo: */ +#define MI_SP2_BUS_TIMEO +#define MI_SP2_BUS_TIMEO_MASK 0x00000010U +#define MI_SP2_BUS_TIMEO_SHIFT 4U +/*! Slice: miv2_sp1_bus_buserr: */ +#define MI_SP1_BUS_BUSERR +#define MI_SP1_BUS_BUSERR_MASK 0x00000008U +#define MI_SP1_BUS_BUSERR_SHIFT 3U +/*! Slice: miv2_sp1_bus_timeo: */ +#define MI_SP1_BUS_TIMEO +#define MI_SP1_BUS_TIMEO_MASK 0x00000004U +#define MI_SP1_BUS_TIMEO_SHIFT 2U +/*! Slice: miv2_mp_bus_buserr: */ +#define MI_MP_BUS_BUSERR +#define MI_MP_BUS_BUSERR_MASK 0x00000002U +#define MI_MP_BUS_BUSERR_SHIFT 1U +/*! Slice: miv2_mp_bus_timeo: */ +#define MI_MP_BUS_TIMEO +#define MI_MP_BUS_TIMEO_MASK 0x00000001U +#define MI_MP_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_ris (0x000016e0) */ +/*! Slice: fill_mp_y: */ +#define FILL_MP_Y +#define FILL_MP_Y_MASK 0x08000000U +#define FILL_MP_Y_SHIFT 27U +/*! Slice: mblk_line: */ +#define MBLK_LINE +#define MBLK_LINE_MASK 0x04000000U +#define MBLK_LINE_SHIFT 26U +/*! Slice: mp_handshk_int: */ +#define MP_HANDSHK_INT +#define MP_HANDSHK_INT_MASK 0x02000000U +#define MP_HANDSHK_INT_SHIFT 25U +/*! Slice: mcm_dma_raw_ready: */ +#define MCM_DMA_RAW_READY +#define MCM_DMA_RAW_READY_MASK 0x01000000U +#define MCM_DMA_RAW_READY_SHIFT 24U +/*! Slice: sp2_dma_raw_ready: */ +#define SP2_DMA_RAW_READY +#define SP2_DMA_RAW_READY_MASK 0x00800000U +#define SP2_DMA_RAW_READY_SHIFT 23U +/*! Slice: sp2_dma_ycbcr_ready: */ +#define SP2_DMA_YCBCR_READY +#define SP2_DMA_YCBCR_READY_MASK 0x00400000U +#define SP2_DMA_YCBCR_READY_SHIFT 22U +/*! Slice: wrap_mcm_raw1: */ +#define WRAP_MCM_RAW1 +#define WRAP_MCM_RAW1_MASK 0x00200000U +#define WRAP_MCM_RAW1_SHIFT 21U +/*! Slice: wrap_mcm_raw0: */ +#define WRAP_MCM_RAW0 +#define WRAP_MCM_RAW0_MASK 0x00100000U +#define WRAP_MCM_RAW0_SHIFT 20U +/*! Slice: wrap_sp2_raw: */ +#define WRAP_SP2_RAW +#define WRAP_SP2_RAW_MASK (0x1 << 16) +#define WRAP_SP2_RAW_SHIFT 16U +/*! Slice: wrap_sp2_cr: */ +#define WRAP_SP2_CR +#define WRAP_SP2_CR_MASK 0x00040000U +#define WRAP_SP2_CR_SHIFT 18U +/*! Slice: wrap_sp2_cb: */ +#define WRAP_SP2_CB +#define WRAP_SP2_CB_MASK 0x00020000U +#define WRAP_SP2_CB_SHIFT 17U +/*! Slice: wrap_sp2_y: */ +#define WRAP_SP2_Y +#define WRAP_SP2_Y_MASK 0x00010000U +#define WRAP_SP2_Y_SHIFT 16U +/*! Slice: wrap_sp1_cr: */ +#define WRAP_SP1_CR +#define WRAP_SP1_CR_MASK 0x00008000U +#define WRAP_SP1_CR_SHIFT 15U +/*! Slice: wrap_sp1_cb: */ +#define WRAP_SP1_CB +#define WRAP_SP1_CB_MASK 0x00004000U +#define WRAP_SP1_CB_SHIFT 14U +/*! Slice: wrap_sp1_y: */ +#define WRAP_SP1_Y +#define WRAP_SP1_Y_MASK 0x00002000U +#define WRAP_SP1_Y_SHIFT 13U +/*! Slice: wrap_mp_jdp: */ +#define WRAP_MP_JDP +#define WRAP_MP_JDP_MASK 0x00001000U +#define WRAP_MP_JDP_SHIFT 12U +/*! Slice: wrap_mp_raw: */ +#define WRAP_MP_RAW +#define WRAP_MP_RAW_MASK 0x00000800U +#define WRAP_MP_RAW_SHIFT 11U +/*! Slice: wrap_mp_cr: */ +#define WRAP_MP_CR +#define WRAP_MP_CR_MASK 0x00000400U +#define WRAP_MP_CR_SHIFT 10U +/*! Slice: wrap_mp_cb: */ +#define WRAP_MP_CB +#define WRAP_MP_CB_MASK 0x00000200U +#define WRAP_MP_CB_SHIFT 9U +/*! Slice: wrap_mp_y: */ +#define WRAP_MP_Y +#define WRAP_MP_Y_MASK 0x00000100U +#define WRAP_MP_Y_SHIFT 8U +/*! Slice: mcm_raw1_frame_end: */ +#define MCM_RAW1_FRAME_END +#define MCM_RAW1_FRAME_END_MASK 0x00000080U +#define MCM_RAW1_FRAME_END_SHIFT 7U +/*! Slice: mcm_raw0_frame_end: */ +#define MCM_RAW0_FRAME_END +#define MCM_RAW0_FRAME_END_MASK 0x00000040U +#define MCM_RAW0_FRAME_END_SHIFT 6U +/*! Slice: sp2_raw_frame_end: */ +#define SP2_RAW_FRAME_END +#define SP2_RAW_FRAME_END_MASK 0x00000020U +#define SP2_RAW_FRAME_END_SHIFT 5U +/*! Slice: sp2_ycbcr_frame_end: */ +#define SP2_YCBCR_FRAME_END +#define SP2_YCBCR_FRAME_END_MASK 0x00000010U +#define SP2_YCBCR_FRAME_END_SHIFT 4U +/*! Slice: sp1_ycbcr_frame_end: */ +#define SP1_YCBCR_FRAME_END +#define SP1_YCBCR_FRAME_END_MASK 0x00000008U +#define SP1_YCBCR_FRAME_END_SHIFT 3U +/*! Slice: mp_jdp_frame_end: */ +#define MP_JDP_FRAME_END +#define MP_JDP_FRAME_END_MASK 0x00000004U +#define MP_JDP_FRAME_END_SHIFT 2U +/*! Slice: mp_raw_frame_end: */ +#define MP_RAW_FRAME_END +#define MP_RAW_FRAME_END_MASK 0x00000002U +#define MP_RAW_FRAME_END_SHIFT 1U +/*! Slice: mp_ycbcr_frame_end: */ +#define MP_YCBCR_FRAME_END +#define MP_YCBCR_FRAME_END_MASK 0x00000001U +#define MP_YCBCR_FRAME_END_SHIFT 0U +/*! Register: miv2_ris1 (0x000016e4)*/ +/*! Slice: miv2_mcm_bus_buserr:*/ +#define MI_MCM_BUS_BUSERR +#define MI_MCM_BUS_BUSERR_MASK 0x00000080U +#define MI_MCM_BUS_BUSERR_SHIFT 7U +/*! Slice: miv2_mcm_bus_timeo:*/ +#define MI_MCM_BUS_TIMEO +#define MI_MCM_BUS_TIMEO_MASK 0x00000040U +#define MI_MCM_BUS_TIMEO_SHIFT 6U +/*! Slice: miv2_sp2_bus_buserr:*/ +#define MI_SP2_BUS_BUSERR +#define MI_SP2_BUS_BUSERR_MASK 0x00000020U +#define MI_SP2_BUS_BUSERR_SHIFT 5U +/*! Slice: miv2_sp2_bus_timeo:*/ +#define MI_SP2_BUS_TIMEO +#define MI_SP2_BUS_TIMEO_MASK 0x00000010U +#define MI_SP2_BUS_TIMEO_SHIFT 4U +/*! Slice: miv2_sp1_bus_buserr:*/ +#define MI_SP1_BUS_BUSERR +#define MI_SP1_BUS_BUSERR_MASK 0x00000008U +#define MI_SP1_BUS_BUSERR_SHIFT 3U +/*! Slice: miv2_sp1_bus_timeo:*/ +#define MI_SP1_BUS_TIMEO +#define MI_SP1_BUS_TIMEO_MASK 0x00000004U +#define MI_SP1_BUS_TIMEO_SHIFT 2U +/*! Slice: miv2_mp_bus_buserr:*/ +#define MI_MP_BUS_BUSERR +#define MI_MP_BUS_BUSERR_MASK 0x00000002U +#define MI_MP_BUS_BUSERR_SHIFT 1U +/*! Slice: miv2_mp_bus_timeo:*/ +#define MI_MP_BUS_TIMEO +#define MI_MP_BUS_TIMEO_MASK 0x00000001U +#define MI_MP_BUS_TIMEO_SHIFT 0U +/*! Register: miv2_mp_y_irq_offs_init (0x00001700)*/ +/*! Slice: mp_y_irq_offs_init:*/ +#define MP_Y_IRQ_OFFS_INIT +#define MP_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MP_Y_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_mp_jdp_irq_offs_init (0x00001704)*/ +/*! Slice: mp_jdp_irq_offs_init:*/ +#define MP_JDP_IRQ_OFFS_INIT +#define MP_JDP_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MP_JDP_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_mp_raw_irq_offs_init (0x00001708)*/ +/*! Slice: mp_raw_irq_offs_init:*/ +#define MP_RAW_IRQ_OFFS_INIT +#define MP_RAW_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MP_RAW_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_sp1_y_irq_offs_init (0x0000170c)*/ +/*! Slice: sp1_y_irq_offs_init:*/ +#define SP1_Y_IRQ_OFFS_INIT +#define SP1_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define SP1_Y_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_sp2_y_irq_offs_init (0x00001710)*/ +/*! Slice: sp2_y_irq_offs_init:*/ +#define SP2_Y_IRQ_OFFS_INIT +#define SP2_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define SP2_Y_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_sp2_raw_irq_offs_init (0x00001714)*/ +/*! Slice: sp2_raw_irq_offs_init:*/ +#define SP2_RAW_IRQ_OFFS_INIT +#define SP2_RAW_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define SP2_RAW_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_mcm_raw0_irq_offs_init (0x00001718)*/ +/*! Slice: mcm_raw0_irq_offs_init:*/ +#define MCM_RAW0_IRQ_OFFS_INIT +#define MCM_RAW0_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MCM_RAW0_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_mcm_raw1_irq_offs_init (0x0000171c)*/ +/*! Slice: mcm_raw1_irq_offs_init:*/ +#define MCM_RAW1_IRQ_OFFS_INIT +#define MCM_RAW1_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U +#define MCM_RAW1_IRQ_OFFS_INIT_SHIFT 3U +/*! Register: miv2_mp_y_irq_offs_shd (0x00001720)*/ +/*! Slice: mp_y_irq_offs:*/ +#define MP_Y_IRQ_OFFS +#define MP_Y_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MP_Y_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_mp_jdp_irq_offs_shd (0x00001724)*/ +/*! Slice: mp_jdp_irq_offs:*/ +#define MP_JDP_IRQ_OFFS +#define MP_JDP_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MP_JDP_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_mp_raw_irq_offs_shd (0x00001728)*/ +/*! Slice: mp_raw_irq_offs:*/ +#define MP_RAW_IRQ_OFFS +#define MP_RAW_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MP_RAW_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_sp1_y_irq_offs_shd (0x0000172c)*/ +/*! Slice: sp1_y_irq_offs:*/ +#define SP1_Y_IRQ_OFFS +#define SP1_Y_IRQ_OFFS_MASK 0x1FFFFFF8U +#define SP1_Y_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_sp2_y_irq_offs_shd (0x00001730)*/ +/*! Slice: sp2_y_irq_offs:*/ +#define SP2_Y_IRQ_OFFS +#define SP2_Y_IRQ_OFFS_MASK 0x1FFFFFF8U +#define SP2_Y_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_sp2_raw_irq_offs_shd (0x00001734)*/ +/*! Slice: sp2_raw_irq_offs:*/ +#define SP2_RAW_IRQ_OFFS +#define SP2_RAW_IRQ_OFFS_MASK 0x1FFFFFF8U +#define SP2_RAW_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_mcm_raw0_irq_offs_shd (0x00001738)*/ +/*! Slice: mcm_raw0_irq_offs:*/ +#define MCM_RAW0_IRQ_OFFS +#define MCM_RAW0_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MCM_RAW0_IRQ_OFFS_SHIFT 3U +/*! Register: miv2_mcm_raw1_irq_offs_shd (0x0000173c)*/ +/*! Slice: mcm_raw1_irq_offs:*/ +#define MCM_RAW1_IRQ_OFFS +#define MCM_RAW1_IRQ_OFFS_MASK 0x1FFFFFF8U +#define MCM_RAW1_IRQ_OFFS_SHIFT 3U +/*! Register: isp_ee_ctrl (0x00003900)*/ +/*! Slice: isp_ee_ctrl enable:*/ +#define EE_CTRL_ENABLE +#define EE_CTRL_ENABLE_MASK 0x00000001U +#define EE_CTRL_ENABLE_SHIFT 0U +/*! Slice: isp_ee_ctrl_input_sel_flag:*/ +#define EE_CTRL_INPUT_SEL +#define EE_CTRL_INPUT_SEL_MASK 0x00000002U +#define EE_CTRL_INPUT_SEL_SHIFT 1U +/*! Slice: isp_ee_ctrl_soft_reset_flag:*/ +#define EE_CTRL_SOFT_RESET_FLAG +#define EE_CTRL_SOFT_RESET_FLAG_MASK 0x00000004U +#define EE_CTRL_SOFT_RESET_FLAG_SHIFT 2U +/*! Slice: isp_ee_ctrl_strength:*/ +#define EE_CTRL_STRENGTH +#define EE_CTRL_STRENGTH_MASK 0x000007F8U +#define EE_CTRL_STRENGTH_SHIFT 3U +/*! Slice: isp_ee_ctrl_source_strength:*/ +#define EE_CTRL_SOURCE_STRENGTH +#define EE_CTRL_SOURCE_STRENGTH_MASK 0x0007F800U +#define EE_CTRL_SOURCE_STRENGTH_SHIFT 11U +/*! Register: isp_ee_y_gain (0x00003904)*/ +/*! Slice: ee_y_down_gain: */ +#define EE_Y_DOWN_GAIN +#define EE_Y_DOWN_GAIN_MASK 0xFFFF0000U +#define EE_Y_DOWN_GAIN_SHIFT 16U +/*! Slice: ee_y_up_gain: */ +#define EE_Y_UP_GAIN +#define EE_Y_UP_GAIN_MASK 0x0000FFFFU +#define EE_Y_UP_GAIN_SHIFT 0U +/*! Slice: ee_y_gain:*/ +#define EE_Y_GAIN +#define EE_Y_GAIN_MASK 0xFFFFFFFFU +#define EE_Y_GAIN_SHIFT 0U +/*! Register: isp_ee_edge_gain (0x00003908)*/ +/*! Slice: isp_ee_edge_gain:*/ +#define EE_EDGE_GAIN +#define EE_EDGE_GAIN_MASK 0xFFFF0000U +#define EE_EDGE_GAIN_SHIFT 16U +/*! Register: isp_ee_uv_gain (0x00003908)*/ +/*! Slice: isp_ee_uv_gain:*/ +#define EE_UV_GAIN +#define EE_UV_GAIN_MASK 0x0000FFFFU +#define EE_UV_GAIN_SHIFT 0U +/*! Register: isp_ee_dummy_hblank (0x00003918)*/ +/*! Slice: isp_ee_dummy_hblank:*/ +#define ISP_EE_DUMMY_HBLANK +#define ISP_EE_DUMMY_HBLANK_MASK 0x0000FFFFU +#define ISP_EE_DUMMY_HBLANK_SHIFT 0U +/*! Register: isp_ee_ctrl_shd (0x0000390c)*/ +/*! Slice: isp_ee_ctrl_shd enable:*/ +#define EE_CTRL_ENABLE_SHD +#define EE_CTRL_ENABLE_SHD_MASK 0x00000001U +#define EE_CTRL_ENABLE_SHD_SHIFT 0U +/*! Slice: isp_ee_ctrl_input_sel_shd:*/ +#define EE_CTRL_INPUT_SEL_SHD +#define EE_CTRL_INPUT_SEL_SHD_MASK 0x00000002U +#define EE_CTRL_INPUT_SEL_SHD_SHIFT 1U +/*! Slice: isp_ee_ctrl_soft_reset_flag_shd:*/ +#define EE_CTRL_SOFT_RESET_FLAG_SHD +#define EE_CTRL_SOFT_RESET_FLAG_SHD_MASK 0x00000004U +#define EE_CTRL_SOFT_RESET_FLAG_SHD_SHIFT 2U +/*! Slice: isp_ee_ctrl_strength_shd:*/ +#define EE_CTRL_STRENGTH_SHD +#define EE_CTRL_STRENGTH_SHD_MASK 0x000007F8U +#define EE_CTRL_STRENGTH_SHD_SHIFT 3U +/*! Slice: isp_ee_ctrl_source_strength_shd:*/ +#define EE_CTRL_SOURCE_STRENGTH_SHD +#define EE_CTRL_SOURCE_STRENGTH_SHD_MASK 0xFF000000U +#define EE_CTRL_SOURCE_STRENGTH_SHD_SHIFT 24U +/*! Register: isp_ee_y_gain_shd (0x00003910)*/ +/*! Slice: isp_ee_y_gain_shd:*/ +#define EE_Y_GAIN_SHD +#define EE_Y_GAIN_SHD_MASK 0xFFFFFFFFU +#define EE_Y_GAIN_SHD_SHIFT 0U +/*! Register: isp_ee_edge_gain_shd (0x00003908)*/ +/*! Slice: isp_ee_edge_gain_shd:*/ +#define EE_EDGE_GAIN_SHD +#define EE_EDGE_GAIN_SHD_MASK 0xFFFF0000U +#define EE_EDGE_GAIN_SHD_SHIFT 16U +/*! Register: isp_ee_uv_gain_shd (0x00003914)*/ +/*! Slice: isp_ee_uv_gain_shd:*/ +#define EE_UV_GAIN_SHD +#define EE_UV_GAIN_SHD_MASK 0x0000FFFFU +#define EE_UV_GAIN_SHD_SHIFT 0U +#define ISP_DEMOSAIC_THR +#define ISP_DEMOSAIC_THR_MASK 0xff000000U +#define ISP_DEMOSAIC_THR_SHIFT 24U +#define ISP_DEMOSAIC_DENOISE_STRENGTH +#define ISP_DEMOSAIC_DENOISE_STRENGTH_MASK 0x003f0000U +#define ISP_DEMOSAIC_DENOISE_STRENGTH_SHIFT 16U +#define ISP_DEMOSAIC_SHARPEN_SIZE +#define ISP_DEMOSAIC_SHARPEN_SIZE_MASK 0x00001f00U +#define ISP_DEMOSAIC_SHARPEN_SIZE_SHIFT 8U +#define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE +#define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE_MASK 0x00000020U +#define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE_SHIFT 5U +#define ISP_DEMOSAIC_SKIN_ENABLE +#define ISP_DEMOSAIC_SKIN_ENABLE_MASK 0x00000010U +#define ISP_DEMOSAIC_SKIN_ENABLE_SHIFT 4U +#define ISP_DEMOSAIC_DEPURPLE_ENABLE +#define ISP_DEMOSAIC_DEPURPLE_ENABLE_MASK 0x00000008U +#define ISP_DEMOSAIC_DEPURPLE_ENABLE_SHIFT 3U +#define ISP_DEMOSAIC_DEMOIRE_ENABLE +#define ISP_DEMOSAIC_DEMOIRE_ENABLE_MASK 0x00000004U +#define ISP_DEMOSAIC_DEMOIRE_ENABLE_SHIFT 2U +#define ISP_DEMOSAIC_SHARPEN_ENBALE +#define ISP_DEMOSAIC_SHARPEN_ENBALE_MASK 0x00000002U +#define ISP_DEMOSAIC_SHARPEN_ENBALE_SHIFT 1U +#define ISP_DEMOSAIC_BYPASS +#define ISP_DEMOSAIC_BYPASS_MASK 0x00000001U +#define ISP_DEMOSAIC_BYPASS_SHIFT 0U +#define ISP_DMSC_INTERPLATION_DIR_THR_MIN +#define ISP_DMSC_INTERPLATION_DIR_THR_MIN_MASK 0x00fff000U +#define ISP_DMSC_INTERPLATION_DIR_THR_MIN_SHIFT 12U +#define ISP_DMSC_INTERPLATION_DIR_THR_MAX +#define ISP_DMSC_INTERPLATION_DIR_THR_MAX_MASK 0x00000fffU +#define ISP_DMSC_INTERPLATION_DIR_THR_MAX_SHIFT 0U +#define ISP_DMSC_DEMOIRE_AREA_THR +#define ISP_DMSC_DEMOIRE_AREA_THR_MASK 0x00003f00U +#define ISP_DMSC_DEMOIRE_AREA_THR_SHIFT 8U +#define ISP_DMSC_DEMOIRE_SAT_SHRINK +#define ISP_DMSC_DEMOIRE_SAT_SHRINK_MASK 0x0000003fU +#define ISP_DMSC_DEMOIRE_SAT_SHRINK_SHIFT 0U +#define ISP_DMSC_DEMOIRE_R2 +#define ISP_DMSC_DEMOIRE_R2_MASK 0x3FE00000U +#define ISP_DMSC_DEMOIRE_R2_SHIFT 21U +#define ISP_DMSC_DEMOIRE_R1 +#define ISP_DMSC_DEMOIRE_R1_MASK 0x001ff000U +#define ISP_DMSC_DEMOIRE_R1_SHIFT 12U +#define ISP_DMSC_DEMOIRE_T2_SHIFT +#define ISP_DMSC_DEMOIRE_T2_SHIFT_MASK 0x00000f00U +#define ISP_DMSC_DEMOIRE_T2_SHIFT_SHIFT 8U +#define ISP_DMSC_DEMOIRE_T1 +#define ISP_DMSC_DEMOIRE_T1_MASK 0x000000FFU +#define ISP_DMSC_DEMOIRE_T1_SHIFT 0U +#define ISP_DMSC_DEMOIRE_EDGE_R2 +#define ISP_DMSC_DEMOIRE_EDGE_R2_MASK 0x7fc00000U +#define ISP_DMSC_DEMOIRE_EDGE_R2_SHIFT 22U +#define ISP_DMSC_DEMOIRE_EDGE_R1 +#define ISP_DMSC_DEMOIRE_EDGE_R1_MASK 0x003fe000U +#define ISP_DMSC_DEMOIRE_EDGE_R1_SHIFT 13U +#define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT +#define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT_MASK 0x00001e00U +#define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT_SHIFT 9U +#define ISP_DMSC_DEMOIRE_EDGE_T1 +#define ISP_DMSC_DEMOIRE_EDGE_T1_MASK 0x000001ffU +#define ISP_DMSC_DEMOIRE_EDGE_T1_SHIFT 0U +#define ISP_DMSC_SHARPEN_FACTOR_BLACK +#define ISP_DMSC_SHARPEN_FACTOR_BLACK_MASK 0x001ff000U +#define ISP_DMSC_SHARPEN_FACTOR_BLACK_SHIFT 12U +#define ISP_DMSC_SHARPEN_FACTOR_WHITE +#define ISP_DMSC_SHARPEN_FACTOR_WHITE_MASK 0x000001ffU +#define ISP_DMSC_SHARPEN_FACTOR_WHITE_SHIFT 0U +#define ISP_DMSC_SHARPEN_CLIP_BLACK +#define ISP_DMSC_SHARPEN_CLIP_BLACK_MASK 0x007ff000U +#define ISP_DMSC_SHARPEN_CLIP_BLACK_SHIFT 12U +#define ISP_DMSC_SHARPEN_CLIP_WHITE +#define ISP_DMSC_SHARPEN_CLIP_WHITE_MASK 0x000007ffU +#define ISP_DMSC_SHARPEN_CLIP_WHITE_SHIFT 0U +#define ISP_DMSC_SHARPEN_T4_SHIFT +#define ISP_DMSC_SHARPEN_T4_SHIFT_MASK 0xf0000000U +#define ISP_DMSC_SHARPEN_T4_SHIFT_SHIFT 28U +#define ISP_DMSC_SHARPEN_T3 +#define ISP_DMSC_SHARPEN_T3_MASK 0x07ff0000U +#define ISP_DMSC_SHARPEN_T3_SHIFT 16U +#define ISP_DMSC_SHARPEN_T2_SHIFT +#define ISP_DMSC_SHARPEN_T2_SHIFT_MASK 0x0000f000U +#define ISP_DMSC_SHARPEN_T2_SHIFT_SHIFT 12U +#define ISP_DMSC_SHARPEN_T1 +#define ISP_DMSC_SHARPEN_T1_MASK 0x000003ffU +#define ISP_DMSC_SHARPEN_T1_SHIFT 0U +#define ISP_DMSC_SHARPEN_R3 +#define ISP_DMSC_SHARPEN_R3_MASK 0x07fc0000 +#define ISP_DMSC_SHARPEN_R3_SHIFT 18U +#define ISP_DMSC_SHARPEN_R2 +#define ISP_DMSC_SHARPEN_R2_MASK 0x0003fe00 +#define ISP_DMSC_SHARPEN_R2_SHIFT 9U +#define ISP_DMSC_SHARPEN_R1 +#define ISP_DMSC_SHARPEN_R1_MASK 0x000001ffU +#define ISP_DMSC_SHARPEN_R1_SHIFT 0U +#define ISP_DMSC_SHARPEN_LINE_SHIFT2 +#define ISP_DMSC_SHARPEN_LINE_SHIFT2_MASK 0xf0000000U +#define ISP_DMSC_SHARPEN_LINE_SHIFT2_SHIFT 28U +#define ISP_DMSC_SHARPEN_LINE_SHIFT1 +#define ISP_DMSC_SHARPEN_LINE_SHIFT1_MASK 0x0f000000U +#define ISP_DMSC_SHARPEN_LINE_SHIFT1_SHIFT 24U +#define ISP_DMSC_SHARPEN_LINE_T1 +#define ISP_DMSC_SHARPEN_LINE_T1_MASK 0x007ff000U +#define ISP_DMSC_SHARPEN_LINE_T1_SHIFT 12U +#define ISP_DMSC_SHARPEN_LINE_STRENGTH +#define ISP_DMSC_SHARPEN_LINE_STRENGTH_MASK 0x00000fffU +#define ISP_DMSC_SHARPEN_LINE_STRENGTH_SHIFT 0U +#define ISP_DMSC_SHARPEN_LINE_R2 +#define ISP_DMSC_SHARPEN_LINE_R2_MASK 0x0003fe00 +#define ISP_DMSC_SHARPEN_LINE_R2_SHIFT 9U +#define ISP_DMSC_SHARPEN_LINE_R1 +#define ISP_DMSC_SHARPEN_LINE_R1_MASK 0x000001ffU +#define ISP_DMSC_SHARPEN_LINE_R1_SHIFT 0U +#define ISP_DMSC_HF_FILT_00 +#define ISP_DMSC_HF_FILT_00_MASK 0x3f000000U +#define ISP_DMSC_HF_FILT_00_SHIFT 24U +#define ISP_DMSC_HF_FILT_01 +#define ISP_DMSC_HF_FILT_01_MASK 0x00fc0000U +#define ISP_DMSC_HF_FILT_01_SHIFT 18U +#define ISP_DMSC_HF_FILT_02 +#define ISP_DMSC_HF_FILT_02_MASK 0x0003f000U +#define ISP_DMSC_HF_FILT_02_SHIFT 12U +#define ISP_DMSC_HF_FILT_10 +#define ISP_DMSC_HF_FILT_10_MASK 0x00000fc0U +#define ISP_DMSC_HF_FILT_10_SHIFT 6U +#define ISP_DMSC_HF_FILT_11 +#define ISP_DMSC_HF_FILT_11_MASK 0x0000003fU +#define ISP_DMSC_HF_FILT_11_SHIFT 0U +#define ISP_DMSC_HF_FILT_12 +#define ISP_DMSC_HF_FILT_12_MASK 0x00fc0000U +#define ISP_DMSC_HF_FILT_12_SHIFT 18U +#define ISP_DMSC_HF_FILT_20 +#define ISP_DMSC_HF_FILT_20_MASK 0x0003f000U +#define ISP_DMSC_HF_FILT_20_SHIFT 12U +#define ISP_DMSC_HF_FILT_21 +#define ISP_DMSC_HF_FILT_21_MASK 0x00000fc0U +#define ISP_DMSC_HF_FILT_21_SHIFT 6U +#define ISP_DMSC_HF_FILT_22 +#define ISP_DMSC_HF_FILT_22_MASK 0x0000003fU +#define ISP_DMSC_HF_FILT_22_SHIFT 0U +#define ISP_DMSC_DEPURPLE_RED_SAT +#define ISP_DMSC_DEPURPLE_RED_SAT_MASK 0x00001000U +#define ISP_DMSC_DEPURPLE_RED_SAT_SHIFT 12U +#define ISP_DMSC_DEPURPLE_BLUE_SAT +#define ISP_DMSC_DEPURPLE_BLUE_SAT_MASK 0x00002000U +#define ISP_DMSC_DEPURPLE_BLUE_SAT_SHIFT 13U +#define ISP_DMSC_DEPURPLE_SAT_SHRINK +#define ISP_DMSC_DEPURPLE_SAT_SHRINK_MASK 0x00000f00U +#define ISP_DMSC_DEPURPLE_SAT_SHRINK_SHIFT 8U +#define ISP_DMSC_DEPURPLE_THR +#define ISP_DMSC_DEPURPLE_THR_MASK 0x000000ffU +#define ISP_DMSC_DEPURPLE_THR_SHIFT 0U +#define ISP_DMSC_SKIN_CB_THR_MAX_2047 +#define ISP_DMSC_SKIN_CB_THR_MAX_2047_MASK 0x00FFF000U +#define ISP_DMSC_SKIN_CB_THR_MAX_2047_SHIFT 12U +#define ISP_DMSC_SKIN_CB_THR_MIN_2047 +#define ISP_DMSC_SKIN_CB_THR_MIN_2047_MASK 0x00000fffU +#define ISP_DMSC_SKIN_CB_THR_MIN_2047_SHIFT 0U +#define ISP_DMSC_SKIN_CR_THR_MAX_2047 +#define ISP_DMSC_SKIN_CR_THR_MAX_2047_MASK 0x00FFF000U +#define ISP_DMSC_SKIN_CR_THR_MAX_2047_SHIFT 12U +#define ISP_DMSC_SKIN_CR_THR_MIN_2047 +#define ISP_DMSC_SKIN_CR_THR_MIN_2047_MASK 0x00000fffU +#define ISP_DMSC_SKIN_CR_THR_MIN_2047_SHIFT 0U +#define ISP_DMSC_SKIN_Y_THR_MAX +#define ISP_DMSC_SKIN_Y_THR_MAX_MASK 0x00FFF000U +#define ISP_DMSC_SKIN_Y_THR_MAX_SHIFT 12U +#define ISP_DMSC_SKIN_Y_THR_MIN +#define ISP_DMSC_SKIN_Y_THR_MIN_MASK 0x00000fffU +#define ISP_DMSC_SKIN_Y_THR_MIN_SHIFT 0U +#define ISP_DMSC_CAC_ENABLE +#define ISP_DMSC_CAC_ENABLE_MASK 0x00000001U +#define ISP_DMSC_CAC_ENABLE_SHIFT 0U +#define ISP_DMSC_V_COUNT_START +#define ISP_DMSC_V_COUNT_START_MASK 0xffff0000U +#define ISP_DMSC_V_COUNT_START_SHIFT 16U +#define ISP_DMSC_H_COUNT_START +#define ISP_DMSC_H_COUNT_START_MASK 0x0000ffffU +#define ISP_DMSC_H_COUNT_START_SHIFT 0U +#define ISP_DMSC_A_RED +#define ISP_DMSC_A_RED_MASK 0x01ff0000U +#define ISP_DMSC_A_RED_SHIFT 16U +#define ISP_DMSC_A_BLUE +#define ISP_DMSC_A_BLUE_MASK 0x000001ffU +#define ISP_DMSC_A_BLUE_SHIFT 0U +#define ISP_DMSC_B_RED +#define ISP_DMSC_B_RED_MASK 0x01ff0000U +#define ISP_DMSC_B_RED_SHIFT 16U +#define ISP_DMSC_B_BLUE +#define ISP_DMSC_B_BLUE_MASK 0x000001ffU +#define ISP_DMSC_B_BLUE_SHIFT 0U +#define ISP_DMSC_C_RED +#define ISP_DMSC_C_RED_MASK 0x01ff0000U +#define ISP_DMSC_C_RED_SHIFT 16U +#define ISP_DMSC_C_BLUE +#define ISP_DMSC_C_BLUE_MASK 0x000001ffU +#define ISP_DMSC_C_BLUE_SHIFT 0U +#define ISP_DMSC_X_NS +#define ISP_DMSC_X_NS_MASK 0x000f0000U +#define ISP_DMSC_X_NS_SHIFT 16U +#define ISP_DMSC_X_NF +#define ISP_DMSC_X_NF_MASK 0x0000001f +#define ISP_DMSC_X_NF_SHIFT 0U +#define ISP_DMSC_Y_NS +#define ISP_DMSC_Y_NS_MASK 0x000f0000U +#define ISP_DMSC_Y_NS_SHIFT 16U +#define ISP_DMSC_Y_NF +#define ISP_DMSC_Y_NF_MASK 0x0000001fU +#define ISP_DMSC_Y_NF_SHIFT 0U +#define ISP_DMSC_Y_NF +#define ISP_DMSC_Y_NF_MASK 0x0000001fU +#define ISP_DMSC_Y_NF_SHIFT 0U +#define ISP_DMSC_IMAGE_H_SIZE +#define ISP_DMSC_IMAGE_H_SIZE_MASK 0x0000ffffU +#define ISP_DMSC_IMAGE_H_SIZE_SHIFT 0U +#define ISP_DMSC_IMAGE_H_BLANK +#define ISP_DMSC_IMAGE_H_BLANK_MASK 0xffff0000U +#define ISP_DMSC_IMAGE_H_BLANK_SHIFT 16U +#define ISP_DMSC_H_BLANK +#define ISP_DMSC_H_BLANK_MASK 0xffff0000U +#define ISP_DMSC_H_BLANK_SHIFT 16U +#define ISP_GREEN_EQUILIBTATE_TH +#define ISP_GREEN_EQUILIBTATE_TH_MASK 0x0001fffeU +#define ISP_GREEN_EQUILIBTATE_TH_SHIFT 1U +#define ISP_GREEN_EQUILIBTATE_ENABLE +#define ISP_GREEN_EQUILIBTATE_ENABLE_MASK 0x00000001U +#define ISP_GREEN_EQUILIBTATE_ENABLE_SHIFT 0U +#define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY +#define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY_MASK 0x0000ffffU +#define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY_SHIFT 0U +#define ISP_CURVE_MODE +#define ISP_CURVE_MODE_MASK 0x00000006U +#define ISP_CURVE_MODE_SHIFT 1U +#define ISP_CURVE_ENABLE +#define ISP_CURVE_ENABLE_MASK 0x00000001U +#define ISP_CURVE_ENABLE_SHIFT 0U +#define ISP_CURVE_LUT_X_ADDR +#define ISP_CURVE_LUT_X_ADDR_MASK 0x0000007fU +#define ISP_CURVE_LUT_X_ADDR_SHIFT 0U +#define ISP_CURVE_LUT_X_WRITE_DATA +#define ISP_CURVE_LUT_X_WRITE_DATA_MASK 0x000000fffU +#define ISP_CURVE_LUT_X_WRITE_DATA_SHIFT 0U +#define ISP_CURVE_LUT_LUMA_ADDR +#define ISP_CURVE_LUT_LUMA_ADDR_MASK 0x0000007fU +#define ISP_CURVE_LUT_LUMA_ADDR_SHIFT 0U +#define ISP_CURVE_LUT_LUMA_WRITE_DATA +#define ISP_CURVE_LUT_LUMA_WRITE_DATA_MASK 0x000007ffU +#define ISP_CURVE_LUT_LUMA_WRITE_DATA_SHIFT 0U +#define ISP_CURVE_LUT_CHROMA_ADDR +#define ISP_CURVE_LUT_CHROMA_ADDR_MASK 0x0000007fU +#define ISP_CURVE_LUT_CHROMA_ADDR_SHIFT 0U +#define ISP_CURVE_LUT_CHROMA_WRITE_DATA +#define ISP_CURVE_LUT_CHROMA_WRITE_DATA_MASK 0x00000fffU +#define ISP_CURVE_LUT_CHROMA_WRITE_DATA_SHIFT 0U +#define ISP_CURVE_LUT_SHIFT_ADDR +#define ISP_CURVE_LUT_SHIFT_ADDR_MASK 0x0000007fU +#define ISP_CURVE_LUT_SHIFT_ADDR_SHIFT 0U +#define ISP_CURVE_LUT_SHIFT_WRITE_DATA +#define ISP_CURVE_LUT_SHIFT_WRITE_DATA_MASK 0x0000001fU +#define ISP_CURVE_LUT_SHIFT_WRITE_DATA_SHIFT 0U +#define ISP_DIGITAL_GAIN_R +#define ISP_DIGITAL_GAIN_R_MASK 0xffff0000U +#define ISP_DIGITAL_GAIN_R_SHIFT 16U +#define ISP_DIGITAL_GAIN_B +#define ISP_DIGITAL_GAIN_B_MASK 0x0000ffffU +#define ISP_DIGITAL_GAIN_B_SHIFT 0U +#define ISP_DIGITAL_GAIN_GR +#define ISP_DIGITAL_GAIN_GR_MASK 0xffff0000U +#define ISP_DIGITAL_GAIN_GR_SHIFT 16U +#define ISP_DIGITAL_GAIN_GB +#define ISP_DIGITAL_GAIN_GB_MASK 0x0000ffffU +#define ISP_DIGITAL_GAIN_GB_SHIFT 0U +/*! Register: isp_vsync_delay: (0x00000730)*/ +/*! Slice: vsync_delya:*/ +#define ISP_VSYNC_DELAY +#define ISP_VSYNC_DELAY_MASK 0x01FFFFFFU +#define ISP_VSYNC_DELAY_SHIFT 0U +/*! Register: isp_vsync_delay: (0x00000730)*/ +/*! Slice: reg_vsync_sel:*/ +#define ISP_VSYNC_DELAY_SEL +#define ISP_VSYNC_DELAY_SEL_MASK 0x80000000U +#define ISP_VSYNC_DELAY_SEL_SHIFT 31U +#define WDR4_DUMMY_BLK +#define WDR4_DUMMY_BLK_MASK (0xffff << 16 ) +#define WDR4_DUMMY_BLK_SHIFT 16U + +#define WDR4_DUMMY_BLK_EN +#define WDR4_DUMMY_BLK_EN_MASK 0x1 << 15 +#define WDR4_DUMMY_BLK_EN_SHIFT 15U + +#define WDR4_SOFT_RESET_FLAG +#define WDR4_SOFT_RESET_FLAG_MASK 0x1 << 1 +#define WDR4_SOFT_RESET_FLAG_SHIFT 1U + +#define WDR4_ENABLE +#define WDR4_ENABLE_MASK 0x1 << 0 +#define WDR4_ENABLE_SHIFT 0U + +#define WDR4_OUTPUT_SHIFT_BIT +#define WDR4_OUTPUT_SHIFT_BIT_MASK (0x3f << 6 ) +#define WDR4_OUTPUT_SHIFT_BIT_SHIFT 6U + +#define WDR4_PIXEL_SHIFT_BIT +#define WDR4_PIXEL_SHIFT_BIT_MASK (0x3f << 0 ) +#define WDR4_PIXEL_SHIFT_BIT_SHIFT 0U + +#define WDR4_BLOCK_HEIGHT +#define WDR4_BLOCK_HEIGHT_MASK (0x1ff << 9 ) +#define WDR4_BLOCK_HEIGHT_SHIFT 9U + +#define WDR4_BLOCK_WIDTH +#define WDR4_BLOCK_WIDTH_MASK (0x1ff << 0 ) +#define WDR4_BLOCK_WIDTH_SHIFT 0U + +#define WDR4_BLOCK_AREA_INVERSE +#define WDR4_BLOCK_AREA_INVERSE_MASK (0xfffff << 0 ) +#define WDR4_BLOCK_AREA_INVERSE_SHIFT 0U + +#define WDR4_VALUE_WEIGHT_3 +#define WDR4_VALUE_WEIGHT_3_MASK (0x1f << 15 ) +#define WDR4_VALUE_WEIGHT_3_SHIFT 15U + +#define WDR4_VALUE_WEIGHT_2 +#define WDR4_VALUE_WEIGHT_2_MASK (0x1f << 10 ) +#define WDR4_VALUE_WEIGHT_2_SHIFT 10U + +#define WDR4_VALUE_WEIGHT_1 +#define WDR4_VALUE_WEIGHT_1_MASK (0x1f << 5 ) +#define WDR4_VALUE_WEIGHT_1_SHIFT 5U + +#define WDR4_VALUE_WEIGHT_0 +#define WDR4_VALUE_WEIGHT_0_MASK (0x1f << 0 ) +#define WDR4_VALUE_WEIGHT_0_SHIFT 0U + +#define WDR4_TOTAL_STRENGTH +#define WDR4_TOTAL_STRENGTH_MASK (0xff << 24 ) +#define WDR4_TOTAL_STRENGTH_SHIFT 24U + +#define WDR4_LOCAL_STRENGTH +#define WDR4_LOCAL_STRENGTH_MASK (0xff << 16 ) +#define WDR4_LOCAL_STRENGTH_SHIFT 16U + +#define WDR4_GLOBAL_STRENGTH +#define WDR4_GLOBAL_STRENGTH_MASK (0xff << 8 ) +#define WDR4_GLOBAL_STRENGTH_SHIFT 8U + +#define WDR4_LOW_STRENGTH +#define WDR4_LOW_STRENGTH_MASK (0xff << 0 ) +#define WDR4_LOW_STRENGTH_SHIFT 0U + +#define WDR4_HIGH_STRENGTH +#define WDR4_HIGH_STRENGTH_MASK (0xff << 16 ) +#define WDR4_HIGH_STRENGTH_SHIFT 16U + +#define WDR4_DRC_BAYER_RATIOLSVS +#define WDR4_DRC_BAYER_RATIOLSVS_MASK (0xff << 8 ) +#define WDR4_DRC_BAYER_RATIOLSVS_SHIFT 8U + +#define WDR4_DRC_BAYER_RATIO +#define WDR4_DRC_BAYER_RATIO_MASK (0xff << 0 ) +#define WDR4_DRC_BAYER_RATIO_SHIFT 0U + +#define WDR4_CONTRAST +#define WDR4_CONTRAST_MASK (0x7ff << 10 ) +#define WDR4_CONTRAST_SHIFT 10U + +#define WDR4_FLAT_STRENGTH +#define WDR4_FLAT_STRENGTH_MASK (0x1f << 5 ) +#define WDR4_FLAT_STRENGTH_SHIFT 5U + +#define WDR4_FLAT_THR +#define WDR4_FLAT_THR_MASK (0x1f << 0 ) +#define WDR4_FLAT_THR_SHIFT 0U + +#define WDR4_PIXEL_MERGE_SLOPE +#define WDR4_PIXEL_MERGE_SLOPE_MASK (0xff << 24 ) +#define WDR4_PIXEL_MERGE_SLOPE_SHIFT 24U + +#define WDR4_PIXEL_MERGE_BASE +#define WDR4_PIXEL_MERGE_BASE_MASK (0xff << 16 ) +#define WDR4_PIXEL_MERGE_BASE_SHIFT 16U + +#define WDR4_PIXEL_ADJUST_SLOPE +#define WDR4_PIXEL_ADJUST_SLOPE_MASK (0xff << 8 ) +#define WDR4_PIXEL_ADJUST_SLOPE_SHIFT 8U + +#define WDR4_PIXEL_ADJUST_BASE +#define WDR4_PIXEL_ADJUST_BASE_MASK (0xff << 0 ) +#define WDR4_PIXEL_ADJUST_BASE_SHIFT 0U + +#define WDR4_ENTROPY_SLOPE +#define WDR4_ENTROPY_SLOPE_MASK (0x3ff << 10 ) +#define WDR4_ENTROPY_SLOPE_SHIFT 10U + +#define WDR4_ENTROPY_BASE +#define WDR4_ENTROPY_BASE_MASK (0x3ff << 0 ) +#define WDR4_ENTROPY_BASE_SHIFT 0U + +#define WDR4_BILITERAL_WIDTH_SIGMA +#define WDR4_BILITERAL_WIDTH_SIGMA_MASK (0xfffff << 0 ) +#define WDR4_BILITERAL_WIDTH_SIGMA_SHIFT 0U + +#define WDR4_BILITERAL_HEIGHT_SIGMA +#define WDR4_BILITERAL_HEIGHT_SIGMA_MASK (0xfffff << 0 ) +#define WDR4_BILITERAL_HEIGHT_SIGMA_SHIFT 0U + +#define WDR4_BILITERAL_VALUE_SIGMA +#define WDR4_BILITERAL_VALUE_SIGMA_MASK (0xfffff << 0 ) +#define WDR4_BILITERAL_VALUE_SIGMA_SHIFT 0U + +#define WDR4_BLOCK_COL_FLAG +#define WDR4_BLOCK_COL_FLAG_MASK (0xffffffff << 0 ) +#define WDR4_BLOCK_COL_FLAG_SHIFT 0U + +#define WDR4_BLOCK_ROW_FLAG +#define WDR4_BLOCK_ROW_FLAG_MASK (0xffffffff << 0 ) +#define WDR4_BLOCK_ROW_FLAG_SHIFT 0U + +#define WDR4_FRAME_AVERAGE +#define WDR4_FRAME_AVERAGE_MASK (0xffffffff << 0 ) +#define WDR4_FRAME_AVERAGE_SHIFT 0U + +#define WDR4_FRAME_STD +#define WDR4_FRAME_STD_MASK (0xffffffff << 0 ) +#define WDR4_FRAME_STD_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE0_0 +#define WDR4_HISTOGRAM_CURVE0_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE0_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE1 +#define WDR4_HISTOGRAM_CURVE1_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE1_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE0_1 +#define WDR4_HISTOGRAM_CURVE0_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE0_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE2 +#define WDR4_HISTOGRAM_CURVE2_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE2_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE3_0 +#define WDR4_HISTOGRAM_CURVE3_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE3_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE4 +#define WDR4_HISTOGRAM_CURVE4_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE4_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE3_1 +#define WDR4_HISTOGRAM_CURVE3_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE3_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE5 +#define WDR4_HISTOGRAM_CURVE5_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE5_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE6_0 +#define WDR4_HISTOGRAM_CURVE6_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE6_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE7 +#define WDR4_HISTOGRAM_CURVE7_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE7_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE6_1 +#define WDR4_HISTOGRAM_CURVE6_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE6_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE8 +#define WDR4_HISTOGRAM_CURVE8_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE8_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE9_0 +#define WDR4_HISTOGRAM_CURVE9_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE9_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE10 +#define WDR4_HISTOGRAM_CURVE10_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE10_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE9_1 +#define WDR4_HISTOGRAM_CURVE9_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE9_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE11 +#define WDR4_HISTOGRAM_CURVE11_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE11_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE12_0 +#define WDR4_HISTOGRAM_CURVE12_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE12_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE13 +#define WDR4_HISTOGRAM_CURVE13_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE13_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE12_1 +#define WDR4_HISTOGRAM_CURVE12_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE12_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE14 +#define WDR4_HISTOGRAM_CURVE14_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE14_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE15_0 +#define WDR4_HISTOGRAM_CURVE15_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE15_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE16 +#define WDR4_HISTOGRAM_CURVE16_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE16_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE15_1 +#define WDR4_HISTOGRAM_CURVE15_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE15_1_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE17 +#define WDR4_HISTOGRAM_CURVE17_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE17_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE18_0 +#define WDR4_HISTOGRAM_CURVE18_0_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE18_0_SHIFT 20U + +#define WDR4_HISTOGRAM_CURVE19 +#define WDR4_HISTOGRAM_CURVE19_MASK (0xfffff << 0 ) +#define WDR4_HISTOGRAM_CURVE19_SHIFT 0U + +#define WDR4_HISTOGRAM_CURVE18_1 +#define WDR4_HISTOGRAM_CURVE18_1_MASK (0x3ff << 20 ) +#define WDR4_HISTOGRAM_CURVE18_1_SHIFT 20U + +#define WDR4_ENTROPY_CONVERT0 +#define WDR4_ENTROPY_CONVERT0_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT0_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT1 +#define WDR4_ENTROPY_CONVERT1_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT1_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT2 +#define WDR4_ENTROPY_CONVERT2_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT2_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT3 +#define WDR4_ENTROPY_CONVERT3_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT3_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT4 +#define WDR4_ENTROPY_CONVERT4_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT4_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT5 +#define WDR4_ENTROPY_CONVERT5_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT5_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT6 +#define WDR4_ENTROPY_CONVERT6_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT6_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT7 +#define WDR4_ENTROPY_CONVERT7_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT7_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT8 +#define WDR4_ENTROPY_CONVERT8_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT8_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT9 +#define WDR4_ENTROPY_CONVERT9_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT9_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT10 +#define WDR4_ENTROPY_CONVERT10_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT10_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT11 +#define WDR4_ENTROPY_CONVERT11_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT11_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT12 +#define WDR4_ENTROPY_CONVERT12_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT12_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT13 +#define WDR4_ENTROPY_CONVERT13_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT13_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT14 +#define WDR4_ENTROPY_CONVERT14_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT14_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT15 +#define WDR4_ENTROPY_CONVERT15_MASK (0x1ff << 18 ) +#define WDR4_ENTROPY_CONVERT15_SHIFT 18U + +#define WDR4_ENTROPY_CONVERT16 +#define WDR4_ENTROPY_CONVERT16_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT16_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT17 +#define WDR4_ENTROPY_CONVERT17_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT17_SHIFT 0U + +#define WDR4_ENTROPY_CONVERT18 +#define WDR4_ENTROPY_CONVERT18_MASK (0x1ff << 9 ) +#define WDR4_ENTROPY_CONVERT18_SHIFT 9U + +#define WDR4_ENTROPY_CONVERT19 +#define WDR4_ENTROPY_CONVERT19_MASK (0x1ff << 0 ) +#define WDR4_ENTROPY_CONVERT19_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE0_0 +#define WDR4_GAMMA_PRE_CURVE0_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE0_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE1 +#define WDR4_GAMMA_PRE_CURVE1_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE1_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE0_1 +#define WDR4_GAMMA_PRE_CURVE0_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE0_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE2 +#define WDR4_GAMMA_PRE_CURVE2_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE2_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE3_0 +#define WDR4_GAMMA_PRE_CURVE3_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE3_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE4 +#define WDR4_GAMMA_PRE_CURVE4_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE4_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE3_1 +#define WDR4_GAMMA_PRE_CURVE3_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE3_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE5 +#define WDR4_GAMMA_PRE_CURVE5_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE5_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE6_0 +#define WDR4_GAMMA_PRE_CURVE6_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE6_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE7 +#define WDR4_GAMMA_PRE_CURVE7_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE7_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE6_1 +#define WDR4_GAMMA_PRE_CURVE6_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE6_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE8 +#define WDR4_GAMMA_PRE_CURVE8_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE8_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE9_0 +#define WDR4_GAMMA_PRE_CURVE9_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE9_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE10 +#define WDR4_GAMMA_PRE_CURVE10_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE10_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE9_1 +#define WDR4_GAMMA_PRE_CURVE9_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE9_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE11 +#define WDR4_GAMMA_PRE_CURVE11_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE11_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE12_0 +#define WDR4_GAMMA_PRE_CURVE12_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE12_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE13 +#define WDR4_GAMMA_PRE_CURVE13_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE13_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE12_1 +#define WDR4_GAMMA_PRE_CURVE12_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE12_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE14 +#define WDR4_GAMMA_PRE_CURVE14_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE14_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE15_0 +#define WDR4_GAMMA_PRE_CURVE15_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE15_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE16 +#define WDR4_GAMMA_PRE_CURVE16_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE16_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE15_1 +#define WDR4_GAMMA_PRE_CURVE15_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE15_1_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE17 +#define WDR4_GAMMA_PRE_CURVE17_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE17_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE18_0 +#define WDR4_GAMMA_PRE_CURVE18_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE18_0_SHIFT 20U + +#define WDR4_GAMMA_PRE_CURVE19 +#define WDR4_GAMMA_PRE_CURVE19_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_PRE_CURVE19_SHIFT 0U + +#define WDR4_GAMMA_PRE_CURVE18_1 +#define WDR4_GAMMA_PRE_CURVE18_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_PRE_CURVE18_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE0_0 +#define WDR4_GAMMA_UP_CURVE0_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE0_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE1 +#define WDR4_GAMMA_UP_CURVE1_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE1_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE0_1 +#define WDR4_GAMMA_UP_CURVE0_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE0_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE2 +#define WDR4_GAMMA_UP_CURVE2_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE2_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE3_0 +#define WDR4_GAMMA_UP_CURVE3_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE3_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE4 +#define WDR4_GAMMA_UP_CURVE4_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE4_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE3_1 +#define WDR4_GAMMA_UP_CURVE3_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE3_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE5 +#define WDR4_GAMMA_UP_CURVE5_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE5_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE6_0 +#define WDR4_GAMMA_UP_CURVE6_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE6_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE7 +#define WDR4_GAMMA_UP_CURVE7_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE7_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE6_1 +#define WDR4_GAMMA_UP_CURVE6_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE6_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE8 +#define WDR4_GAMMA_UP_CURVE8_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE8_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE9_0 +#define WDR4_GAMMA_UP_CURVE9_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE9_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE10 +#define WDR4_GAMMA_UP_CURVE10_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE10_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE9_1 +#define WDR4_GAMMA_UP_CURVE9_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE9_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE11 +#define WDR4_GAMMA_UP_CURVE11_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE11_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE12_0 +#define WDR4_GAMMA_UP_CURVE12_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE12_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE13 +#define WDR4_GAMMA_UP_CURVE13_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE13_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE12_1 +#define WDR4_GAMMA_UP_CURVE12_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE12_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE14 +#define WDR4_GAMMA_UP_CURVE14_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE14_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE15_0 +#define WDR4_GAMMA_UP_CURVE15_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE15_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE16 +#define WDR4_GAMMA_UP_CURVE16_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE16_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE15_1 +#define WDR4_GAMMA_UP_CURVE15_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE15_1_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE17 +#define WDR4_GAMMA_UP_CURVE17_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE17_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE18_0 +#define WDR4_GAMMA_UP_CURVE18_0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE18_0_SHIFT 20U + +#define WDR4_GAMMA_UP_CURVE19 +#define WDR4_GAMMA_UP_CURVE19_MASK (0xfffff << 0 ) +#define WDR4_GAMMA_UP_CURVE19_SHIFT 0U + +#define WDR4_GAMMA_UP_CURVE18_1 +#define WDR4_GAMMA_UP_CURVE18_1_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_UP_CURVE18_1_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE0 +#define WDR4_GAMMA_DOWN_CURVE0_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE0_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE1 +#define WDR4_GAMMA_DOWN_CURVE1_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE1_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE2 +#define WDR4_GAMMA_DOWN_CURVE2_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE2_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE3 +#define WDR4_GAMMA_DOWN_CURVE3_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE3_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE4 +#define WDR4_GAMMA_DOWN_CURVE4_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE4_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE5 +#define WDR4_GAMMA_DOWN_CURVE5_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE5_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE6 +#define WDR4_GAMMA_DOWN_CURVE6_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE6_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE7 +#define WDR4_GAMMA_DOWN_CURVE7_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE7_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE8 +#define WDR4_GAMMA_DOWN_CURVE8_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE8_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE9 +#define WDR4_GAMMA_DOWN_CURVE9_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE9_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE10 +#define WDR4_GAMMA_DOWN_CURVE10_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE10_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE11 +#define WDR4_GAMMA_DOWN_CURVE11_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE11_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE12 +#define WDR4_GAMMA_DOWN_CURVE12_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE12_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE13 +#define WDR4_GAMMA_DOWN_CURVE13_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE13_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE14 +#define WDR4_GAMMA_DOWN_CURVE14_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE14_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE15 +#define WDR4_GAMMA_DOWN_CURVE15_MASK (0x3ff << 20 ) +#define WDR4_GAMMA_DOWN_CURVE15_SHIFT 20U + +#define WDR4_GAMMA_DOWN_CURVE16 +#define WDR4_GAMMA_DOWN_CURVE16_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE16_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE17 +#define WDR4_GAMMA_DOWN_CURVE17_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE17_SHIFT 0U + +#define WDR4_GAMMA_DOWN_CURVE18 +#define WDR4_GAMMA_DOWN_CURVE18_MASK (0x3ff << 10 ) +#define WDR4_GAMMA_DOWN_CURVE18_SHIFT 10U + +#define WDR4_GAMMA_DOWN_CURVE19 +#define WDR4_GAMMA_DOWN_CURVE19_MASK (0x3ff << 0 ) +#define WDR4_GAMMA_DOWN_CURVE19_SHIFT 0U + +#define WDR4_DISTANCE_WEIGHT_CURVE0 +#define WDR4_DISTANCE_WEIGHT_CURVE0_MASK (0x7f << 21 ) +#define WDR4_DISTANCE_WEIGHT_CURVE0_SHIFT 21U + +#define WDR4_DISTANCE_WEIGHT_CURVE1 +#define WDR4_DISTANCE_WEIGHT_CURVE1_MASK (0x7f << 14 ) +#define WDR4_DISTANCE_WEIGHT_CURVE1_SHIFT 14U + +#define WDR4_DISTANCE_WEIGHT_CURVE2 +#define WDR4_DISTANCE_WEIGHT_CURVE2_MASK (0x7f << 7 ) +#define WDR4_DISTANCE_WEIGHT_CURVE2_SHIFT 7U + +#define WDR4_DISTANCE_WEIGHT_CURVE3 +#define WDR4_DISTANCE_WEIGHT_CURVE3_MASK (0x7f << 0 ) +#define WDR4_DISTANCE_WEIGHT_CURVE3_SHIFT 0U + +#define WDR4_DISTANCE_WEIGHT_CURVE4 +#define WDR4_DISTANCE_WEIGHT_CURVE4_MASK (0x7f << 21 ) +#define WDR4_DISTANCE_WEIGHT_CURVE4_SHIFT 21U + +#define WDR4_DISTANCE_WEIGHT_CURVE5 +#define WDR4_DISTANCE_WEIGHT_CURVE5_MASK (0x7f << 14 ) +#define WDR4_DISTANCE_WEIGHT_CURVE5_SHIFT 14U + +#define WDR4_DISTANCE_WEIGHT_CURVE6 +#define WDR4_DISTANCE_WEIGHT_CURVE6_MASK (0x7f << 7 ) +#define WDR4_DISTANCE_WEIGHT_CURVE6_SHIFT 7U + +#define WDR4_DISTANCE_WEIGHT_CURVE7 +#define WDR4_DISTANCE_WEIGHT_CURVE7_MASK (0x7f << 0 ) +#define WDR4_DISTANCE_WEIGHT_CURVE7_SHIFT 0U + +#define WDR4_DISTANCE_WEIGHT_CURVE8 +#define WDR4_DISTANCE_WEIGHT_CURVE8_MASK (0x7f << 21 ) +#define WDR4_DISTANCE_WEIGHT_CURVE8_SHIFT 21U + +#define WDR4_DISTANCE_WEIGHT_CURVE9 +#define WDR4_DISTANCE_WEIGHT_CURVE9_MASK (0x7f << 14 ) +#define WDR4_DISTANCE_WEIGHT_CURVE9_SHIFT 14U + +#define WDR4_DISTANCE_WEIGHT_CURVE10 +#define WDR4_DISTANCE_WEIGHT_CURVE10_MASK (0x7f << 7 ) +#define WDR4_DISTANCE_WEIGHT_CURVE10_SHIFT 7U + +#define WDR4_DISTANCE_WEIGHT_CURVE11 +#define WDR4_DISTANCE_WEIGHT_CURVE11_MASK (0x7f << 0 ) +#define WDR4_DISTANCE_WEIGHT_CURVE11_SHIFT 0U + +#define WDR4_DISTANCE_WEIGHT_CURVE12 +#define WDR4_DISTANCE_WEIGHT_CURVE12_MASK (0x7f << 21 ) +#define WDR4_DISTANCE_WEIGHT_CURVE12_SHIFT 21U + +#define WDR4_DISTANCE_WEIGHT_CURVE13 +#define WDR4_DISTANCE_WEIGHT_CURVE13_MASK (0x7f << 14 ) +#define WDR4_DISTANCE_WEIGHT_CURVE13_SHIFT 14U + +#define WDR4_DISTANCE_WEIGHT_CURVE14 +#define WDR4_DISTANCE_WEIGHT_CURVE14_MASK (0x7f << 7 ) +#define WDR4_DISTANCE_WEIGHT_CURVE14_SHIFT 7U + +#define WDR4_DISTANCE_WEIGHT_CURVE15 +#define WDR4_DISTANCE_WEIGHT_CURVE15_MASK (0x7f << 0 ) +#define WDR4_DISTANCE_WEIGHT_CURVE15_SHIFT 0U + +#define WDR4_DISTANCE_WEIGHT_CURVE16 +#define WDR4_DISTANCE_WEIGHT_CURVE16_MASK (0x7f << 21 ) +#define WDR4_DISTANCE_WEIGHT_CURVE16_SHIFT 21U + +#define WDR4_DISTANCE_WEIGHT_CURVE17 +#define WDR4_DISTANCE_WEIGHT_CURVE17_MASK (0x7f << 14 ) +#define WDR4_DISTANCE_WEIGHT_CURVE17_SHIFT 14U + +#define WDR4_DISTANCE_WEIGHT_CURVE18 +#define WDR4_DISTANCE_WEIGHT_CURVE18_MASK (0x7f << 7 ) +#define WDR4_DISTANCE_WEIGHT_CURVE18_SHIFT 7U + +#define WDR4_DISTANCE_WEIGHT_CURVE19 +#define WDR4_DISTANCE_WEIGHT_CURVE19_MASK (0x7f << 0 ) +#define WDR4_DISTANCE_WEIGHT_CURVE19_SHIFT 0U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE0 +#define WDR4_DIFFERENCE_WEIGHT_CURVE0_MASK (0x7f << 21 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE0_SHIFT 21U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE1 +#define WDR4_DIFFERENCE_WEIGHT_CURVE1_MASK (0x7f << 14 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE1_SHIFT 14U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE2 +#define WDR4_DIFFERENCE_WEIGHT_CURVE2_MASK (0x7f << 7 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE2_SHIFT 7U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE3 +#define WDR4_DIFFERENCE_WEIGHT_CURVE3_MASK (0x7f << 0 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE3_SHIFT 0U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE4 +#define WDR4_DIFFERENCE_WEIGHT_CURVE4_MASK (0x7f << 21 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE4_SHIFT 21U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE5 +#define WDR4_DIFFERENCE_WEIGHT_CURVE5_MASK (0x7f << 14 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE5_SHIFT 14U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE6 +#define WDR4_DIFFERENCE_WEIGHT_CURVE6_MASK (0x7f << 7 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE6_SHIFT 7U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE7 +#define WDR4_DIFFERENCE_WEIGHT_CURVE7_MASK (0x7f << 0 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE7_SHIFT 0U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE8 +#define WDR4_DIFFERENCE_WEIGHT_CURVE8_MASK (0x7f << 21 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE8_SHIFT 21U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE9 +#define WDR4_DIFFERENCE_WEIGHT_CURVE9_MASK (0x7f << 14 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE9_SHIFT 14U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE10 +#define WDR4_DIFFERENCE_WEIGHT_CURVE10_MASK (0x7f << 7 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE10_SHIFT 7U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE11 +#define WDR4_DIFFERENCE_WEIGHT_CURVE11_MASK (0x7f << 0 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE11_SHIFT 0U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE12 +#define WDR4_DIFFERENCE_WEIGHT_CURVE12_MASK (0x7f << 21 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE12_SHIFT 21U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE13 +#define WDR4_DIFFERENCE_WEIGHT_CURVE13_MASK (0x7f << 14 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE13_SHIFT 14U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE14 +#define WDR4_DIFFERENCE_WEIGHT_CURVE14_MASK (0x7f << 7 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE14_SHIFT 7U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE15 +#define WDR4_DIFFERENCE_WEIGHT_CURVE15_MASK (0x7f << 0 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE15_SHIFT 0U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE16 +#define WDR4_DIFFERENCE_WEIGHT_CURVE16_MASK (0x7f << 21 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE16_SHIFT 21U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE17 +#define WDR4_DIFFERENCE_WEIGHT_CURVE17_MASK (0x7f << 14 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE17_SHIFT 14U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE18 +#define WDR4_DIFFERENCE_WEIGHT_CURVE18_MASK (0x7f << 7 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE18_SHIFT 7U + +#define WDR4_DIFFERENCE_WEIGHT_CURVE19 +#define WDR4_DIFFERENCE_WEIGHT_CURVE19_MASK (0x7f << 0 ) +#define WDR4_DIFFERENCE_WEIGHT_CURVE19_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT0 +#define WDR4_GLOBAL_CURVE_INVERT0_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT0_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT1 +#define WDR4_GLOBAL_CURVE_INVERT1_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT1_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT2 +#define WDR4_GLOBAL_CURVE_INVERT2_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT2_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT3 +#define WDR4_GLOBAL_CURVE_INVERT3_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT3_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT4 +#define WDR4_GLOBAL_CURVE_INVERT4_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT4_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT5 +#define WDR4_GLOBAL_CURVE_INVERT5_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT5_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT6 +#define WDR4_GLOBAL_CURVE_INVERT6_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT6_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT7 +#define WDR4_GLOBAL_CURVE_INVERT7_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT7_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT8 +#define WDR4_GLOBAL_CURVE_INVERT8_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT8_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT9 +#define WDR4_GLOBAL_CURVE_INVERT9_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT9_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT10 +#define WDR4_GLOBAL_CURVE_INVERT10_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT10_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT11 +#define WDR4_GLOBAL_CURVE_INVERT11_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT11_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT12 +#define WDR4_GLOBAL_CURVE_INVERT12_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT12_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT13 +#define WDR4_GLOBAL_CURVE_INVERT13_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT13_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT14 +#define WDR4_GLOBAL_CURVE_INVERT14_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT14_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT15 +#define WDR4_GLOBAL_CURVE_INVERT15_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT15_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT16 +#define WDR4_GLOBAL_CURVE_INVERT16_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT16_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT17 +#define WDR4_GLOBAL_CURVE_INVERT17_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT17_SHIFT 0U + +#define WDR4_GLOBAL_CURVE_INVERT18 +#define WDR4_GLOBAL_CURVE_INVERT18_MASK (0xfff << 12 ) +#define WDR4_GLOBAL_CURVE_INVERT18_SHIFT 12U + +#define WDR4_GLOBAL_CURVE_INVERT19 +#define WDR4_GLOBAL_CURVE_INVERT19_MASK (0xfff << 0 ) +#define WDR4_GLOBAL_CURVE_INVERT19_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT0_0 +#define WDR4_LINEAR_CURVE_INVERT0_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT0_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT1 +#define WDR4_LINEAR_CURVE_INVERT1_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT1_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT0_1 +#define WDR4_LINEAR_CURVE_INVERT0_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT0_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT2 +#define WDR4_LINEAR_CURVE_INVERT2_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT2_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT3_0 +#define WDR4_LINEAR_CURVE_INVERT3_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT3_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT4 +#define WDR4_LINEAR_CURVE_INVERT4_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT4_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT3_1 +#define WDR4_LINEAR_CURVE_INVERT3_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT3_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT5 +#define WDR4_LINEAR_CURVE_INVERT5_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT5_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT6_0 +#define WDR4_LINEAR_CURVE_INVERT6_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT6_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT7 +#define WDR4_LINEAR_CURVE_INVERT7_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT7_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT6_1 +#define WDR4_LINEAR_CURVE_INVERT6_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT6_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT8 +#define WDR4_LINEAR_CURVE_INVERT8_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT8_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT9_0 +#define WDR4_LINEAR_CURVE_INVERT9_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT9_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT10 +#define WDR4_LINEAR_CURVE_INVERT10_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT10_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT9_1 +#define WDR4_LINEAR_CURVE_INVERT9_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT9_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT11 +#define WDR4_LINEAR_CURVE_INVERT11_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT11_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT12_0 +#define WDR4_LINEAR_CURVE_INVERT12_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT12_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT13 +#define WDR4_LINEAR_CURVE_INVERT13_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT13_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT12_1 +#define WDR4_LINEAR_CURVE_INVERT12_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT12_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT14 +#define WDR4_LINEAR_CURVE_INVERT14_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT14_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT15_0 +#define WDR4_LINEAR_CURVE_INVERT15_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT15_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT16 +#define WDR4_LINEAR_CURVE_INVERT16_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT16_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT15_1 +#define WDR4_LINEAR_CURVE_INVERT15_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT15_1_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT17 +#define WDR4_LINEAR_CURVE_INVERT17_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT17_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT18_0 +#define WDR4_LINEAR_CURVE_INVERT18_0_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT18_0_SHIFT 18U + +#define WDR4_LINEAR_CURVE_INVERT19 +#define WDR4_LINEAR_CURVE_INVERT19_MASK (0x3ffff << 0 ) +#define WDR4_LINEAR_CURVE_INVERT19_SHIFT 0U + +#define WDR4_LINEAR_CURVE_INVERT18_1 +#define WDR4_LINEAR_CURVE_INVERT18_1_MASK (0x1ff << 18 ) +#define WDR4_LINEAR_CURVE_INVERT18_1_SHIFT 18U + +#define WDR4_SMOOTH_INVERT_CURVE0 +#define WDR4_SMOOTH_INVERT_CURVE0_MASK (0xff << 24 ) +#define WDR4_SMOOTH_INVERT_CURVE0_SHIFT 24U + +#define WDR4_SMOOTH_INVERT_CURVE1 +#define WDR4_SMOOTH_INVERT_CURVE1_MASK (0xff << 16 ) +#define WDR4_SMOOTH_INVERT_CURVE1_SHIFT 16U + +#define WDR4_SMOOTH_INVERT_CURVE2 +#define WDR4_SMOOTH_INVERT_CURVE2_MASK (0xff << 8 ) +#define WDR4_SMOOTH_INVERT_CURVE2_SHIFT 8U + +#define WDR4_SMOOTH_INVERT_CURVE3 +#define WDR4_SMOOTH_INVERT_CURVE3_MASK (0xff << 0 ) +#define WDR4_SMOOTH_INVERT_CURVE3_SHIFT 0U + +#define WDR4_SMOOTH_INVERT_CURVE4 +#define WDR4_SMOOTH_INVERT_CURVE4_MASK (0xff << 24 ) +#define WDR4_SMOOTH_INVERT_CURVE4_SHIFT 24U + +#define WDR4_SMOOTH_INVERT_CURVE5 +#define WDR4_SMOOTH_INVERT_CURVE5_MASK (0xff << 16 ) +#define WDR4_SMOOTH_INVERT_CURVE5_SHIFT 16U + +#define WDR4_SMOOTH_INVERT_CURVE6 +#define WDR4_SMOOTH_INVERT_CURVE6_MASK (0xff << 8 ) +#define WDR4_SMOOTH_INVERT_CURVE6_SHIFT 8U + +#define WDR4_SMOOTH_INVERT_CURVE7 +#define WDR4_SMOOTH_INVERT_CURVE7_MASK (0xff << 0 ) +#define WDR4_SMOOTH_INVERT_CURVE7_SHIFT 0U + +#define WDR4_SMOOTH_INVERT_CURVE8 +#define WDR4_SMOOTH_INVERT_CURVE8_MASK (0xff << 24 ) +#define WDR4_SMOOTH_INVERT_CURVE8_SHIFT 24U + +#define WDR4_SMOOTH_INVERT_CURVE9 +#define WDR4_SMOOTH_INVERT_CURVE9_MASK (0xff << 16 ) +#define WDR4_SMOOTH_INVERT_CURVE9_SHIFT 16U + +#define WDR4_SMOOTH_INVERT_CURVE10 +#define WDR4_SMOOTH_INVERT_CURVE10_MASK (0xff << 8 ) +#define WDR4_SMOOTH_INVERT_CURVE10_SHIFT 8U + +#define WDR4_SMOOTH_INVERT_CURVE11 +#define WDR4_SMOOTH_INVERT_CURVE11_MASK (0xff << 0 ) +#define WDR4_SMOOTH_INVERT_CURVE11_SHIFT 0U + +#define WDR4_SMOOTH_INVERT_CURVE12 +#define WDR4_SMOOTH_INVERT_CURVE12_MASK (0xff << 24 ) +#define WDR4_SMOOTH_INVERT_CURVE12_SHIFT 24U + +#define WDR4_SMOOTH_INVERT_CURVE13 +#define WDR4_SMOOTH_INVERT_CURVE13_MASK (0xff << 16 ) +#define WDR4_SMOOTH_INVERT_CURVE13_SHIFT 16U + +#define WDR4_SMOOTH_INVERT_CURVE14 +#define WDR4_SMOOTH_INVERT_CURVE14_MASK (0xff << 8 ) +#define WDR4_SMOOTH_INVERT_CURVE14_SHIFT 8U + +#define WDR4_SMOOTH_INVERT_CURVE15 +#define WDR4_SMOOTH_INVERT_CURVE15_MASK (0xff << 0 ) +#define WDR4_SMOOTH_INVERT_CURVE15_SHIFT 0U + +#define WDR4_SMOOTH_INVERT_CURVE16 +#define WDR4_SMOOTH_INVERT_CURVE16_MASK (0xff << 24 ) +#define WDR4_SMOOTH_INVERT_CURVE16_SHIFT 24U + +#define WDR4_SMOOTH_INVERT_CURVE17 +#define WDR4_SMOOTH_INVERT_CURVE17_MASK (0xff << 16 ) +#define WDR4_SMOOTH_INVERT_CURVE17_SHIFT 16U + +#define WDR4_SMOOTH_INVERT_CURVE18 +#define WDR4_SMOOTH_INVERT_CURVE18_MASK (0xff << 8 ) +#define WDR4_SMOOTH_INVERT_CURVE18_SHIFT 8U + +#define WDR4_SMOOTH_INVERT_CURVE19 +#define WDR4_SMOOTH_INVERT_CURVE19_MASK (0xff << 0 ) +#define WDR4_SMOOTH_INVERT_CURVE19_SHIFT 0U + +#define WDR4_HISTOGRAM_SHIFT0 +#define WDR4_HISTOGRAM_SHIFT0_MASK (0x1f << 25 ) +#define WDR4_HISTOGRAM_SHIFT0_SHIFT 25U + +#define WDR4_HISTOGRAM_SHIFT1 +#define WDR4_HISTOGRAM_SHIFT1_MASK (0x1f << 20 ) +#define WDR4_HISTOGRAM_SHIFT1_SHIFT 20U + +#define WDR4_HISTOGRAM_SHIFT2 +#define WDR4_HISTOGRAM_SHIFT2_MASK (0x1f << 15 ) +#define WDR4_HISTOGRAM_SHIFT2_SHIFT 15U + +#define WDR4_HISTOGRAM_SHIFT3 +#define WDR4_HISTOGRAM_SHIFT3_MASK (0x1f << 10 ) +#define WDR4_HISTOGRAM_SHIFT3_SHIFT 10U + +#define WDR4_HISTOGRAM_SHIFT4 +#define WDR4_HISTOGRAM_SHIFT4_MASK (0x1f << 5 ) +#define WDR4_HISTOGRAM_SHIFT4_SHIFT 5U + +#define WDR4_HISTOGRAM_SHIFT5 +#define WDR4_HISTOGRAM_SHIFT5_MASK (0x1f << 0 ) +#define WDR4_HISTOGRAM_SHIFT5_SHIFT 0U + +#define WDR4_HISTOGRAM_SHIFT6 +#define WDR4_HISTOGRAM_SHIFT6_MASK (0x1f << 25 ) +#define WDR4_HISTOGRAM_SHIFT6_SHIFT 25U + +#define WDR4_HISTOGRAM_SHIFT7 +#define WDR4_HISTOGRAM_SHIFT7_MASK (0x1f << 20 ) +#define WDR4_HISTOGRAM_SHIFT7_SHIFT 20U + +#define WDR4_HISTOGRAM_SHIFT8 +#define WDR4_HISTOGRAM_SHIFT8_MASK (0x1f << 15 ) +#define WDR4_HISTOGRAM_SHIFT8_SHIFT 15U + +#define WDR4_HISTOGRAM_SHIFT9 +#define WDR4_HISTOGRAM_SHIFT9_MASK (0x1f << 10 ) +#define WDR4_HISTOGRAM_SHIFT9_SHIFT 10U + +#define WDR4_HISTOGRAM_SHIFT10 +#define WDR4_HISTOGRAM_SHIFT10_MASK (0x1f << 5 ) +#define WDR4_HISTOGRAM_SHIFT10_SHIFT 5U + +#define WDR4_HISTOGRAM_SHIFT11 +#define WDR4_HISTOGRAM_SHIFT11_MASK (0x1f << 0 ) +#define WDR4_HISTOGRAM_SHIFT11_SHIFT 0U + +#define WDR4_HISTOGRAM_SHIFT12 +#define WDR4_HISTOGRAM_SHIFT12_MASK (0x1f << 25 ) +#define WDR4_HISTOGRAM_SHIFT12_SHIFT 25U + +#define WDR4_HISTOGRAM_SHIFT13 +#define WDR4_HISTOGRAM_SHIFT13_MASK (0x1f << 20 ) +#define WDR4_HISTOGRAM_SHIFT13_SHIFT 20U + +#define WDR4_HISTOGRAM_SHIFT14 +#define WDR4_HISTOGRAM_SHIFT14_MASK (0x1f << 15 ) +#define WDR4_HISTOGRAM_SHIFT14_SHIFT 15U + +#define WDR4_HISTOGRAM_SHIFT15 +#define WDR4_HISTOGRAM_SHIFT15_MASK (0x1f << 10 ) +#define WDR4_HISTOGRAM_SHIFT15_SHIFT 10U + +#define WDR4_HISTOGRAM_SHIFT16 +#define WDR4_HISTOGRAM_SHIFT16_MASK (0x1f << 5 ) +#define WDR4_HISTOGRAM_SHIFT16_SHIFT 5U + +#define WDR4_HISTOGRAM_SHIFT17 +#define WDR4_HISTOGRAM_SHIFT17_MASK (0x1f << 0 ) +#define WDR4_HISTOGRAM_SHIFT17_SHIFT 0U + +#define WDR4_HISTOGRAM_SHIFT18 +#define WDR4_HISTOGRAM_SHIFT18_MASK (0x1f << 5 ) +#define WDR4_HISTOGRAM_SHIFT18_SHIFT 5U + +#define WDR4_HISTOGRAM_SHIFT19 +#define WDR4_HISTOGRAM_SHIFT19_MASK (0x1f << 0 ) +#define WDR4_HISTOGRAM_SHIFT19_SHIFT 0U + +#define WDR4_HISTOGRAM0_SHIFT0 +#define WDR4_HISTOGRAM0_SHIFT0_MASK (0xf << 28 ) +#define WDR4_HISTOGRAM0_SHIFT0_SHIFT 28U + +#define WDR4_HISTOGRAM0_SHIFT1 +#define WDR4_HISTOGRAM0_SHIFT1_MASK (0xf << 24 ) +#define WDR4_HISTOGRAM0_SHIFT1_SHIFT 24U + +#define WDR4_HISTOGRAM0_SHIFT2 +#define WDR4_HISTOGRAM0_SHIFT2_MASK (0xf << 20 ) +#define WDR4_HISTOGRAM0_SHIFT2_SHIFT 20U + +#define WDR4_HISTOGRAM0_SHIFT3 +#define WDR4_HISTOGRAM0_SHIFT3_MASK (0xf << 16 ) +#define WDR4_HISTOGRAM0_SHIFT3_SHIFT 16U + +#define WDR4_HISTOGRAM0_SHIFT4 +#define WDR4_HISTOGRAM0_SHIFT4_MASK (0xf << 12 ) +#define WDR4_HISTOGRAM0_SHIFT4_SHIFT 12U + +#define WDR4_HISTOGRAM0_SHIFT5 +#define WDR4_HISTOGRAM0_SHIFT5_MASK (0xf << 8 ) +#define WDR4_HISTOGRAM0_SHIFT5_SHIFT 8U + +#define WDR4_HISTOGRAM0_SHIFT6 +#define WDR4_HISTOGRAM0_SHIFT6_MASK (0xf << 4 ) +#define WDR4_HISTOGRAM0_SHIFT6_SHIFT 4U + +#define WDR4_HISTOGRAM0_SHIFT7 +#define WDR4_HISTOGRAM0_SHIFT7_MASK (0xf << 0 ) +#define WDR4_HISTOGRAM0_SHIFT7_SHIFT 0U + +#define WDR4_HISTOGRAM0_SHIFT8 +#define WDR4_HISTOGRAM0_SHIFT8_MASK (0xf << 28 ) +#define WDR4_HISTOGRAM0_SHIFT8_SHIFT 28U + +#define WDR4_HISTOGRAM0_SHIFT9 +#define WDR4_HISTOGRAM0_SHIFT9_MASK (0xf << 24 ) +#define WDR4_HISTOGRAM0_SHIFT9_SHIFT 24U + +#define WDR4_HISTOGRAM0_SHIFT10 +#define WDR4_HISTOGRAM0_SHIFT10_MASK (0xf << 20 ) +#define WDR4_HISTOGRAM0_SHIFT10_SHIFT 20U + +#define WDR4_HISTOGRAM0_SHIFT11 +#define WDR4_HISTOGRAM0_SHIFT11_MASK (0xf << 16 ) +#define WDR4_HISTOGRAM0_SHIFT11_SHIFT 16U + +#define WDR4_HISTOGRAM0_SHIFT12 +#define WDR4_HISTOGRAM0_SHIFT12_MASK (0xf << 12 ) +#define WDR4_HISTOGRAM0_SHIFT12_SHIFT 12U + +#define WDR4_HISTOGRAM0_SHIFT13 +#define WDR4_HISTOGRAM0_SHIFT13_MASK (0xf << 8 ) +#define WDR4_HISTOGRAM0_SHIFT13_SHIFT 8U + +#define WDR4_HISTOGRAM0_SHIFT14 +#define WDR4_HISTOGRAM0_SHIFT14_MASK (0xf << 4 ) +#define WDR4_HISTOGRAM0_SHIFT14_SHIFT 4U + +#define WDR4_HISTOGRAM0_SHIFT15 +#define WDR4_HISTOGRAM0_SHIFT15_MASK (0xf << 0 ) +#define WDR4_HISTOGRAM0_SHIFT15_SHIFT 0U + +#define WDR4_HISTOGRAM0_SHIFT16 +#define WDR4_HISTOGRAM0_SHIFT16_MASK (0xf << 12 ) +#define WDR4_HISTOGRAM0_SHIFT16_SHIFT 12U + +#define WDR4_HISTOGRAM0_SHIFT17 +#define WDR4_HISTOGRAM0_SHIFT17_MASK (0xf << 8 ) +#define WDR4_HISTOGRAM0_SHIFT17_SHIFT 8U + +#define WDR4_HISTOGRAM0_SHIFT18 +#define WDR4_HISTOGRAM0_SHIFT18_MASK (0xf << 4 ) +#define WDR4_HISTOGRAM0_SHIFT18_SHIFT 4U + +#define WDR4_HISTOGRAM0_SHIFT19 +#define WDR4_HISTOGRAM0_SHIFT19_MASK (0xf << 0 ) +#define WDR4_HISTOGRAM0_SHIFT19_SHIFT 0U + +#define WDR4_TOTAL_STRENGTH_SHD +#define WDR4_TOTAL_STRENGTH_SHD_MASK (0xff << 24 ) +#define WDR4_TOTAL_STRENGTH_SHD_SHIFT 24U + +#define WDR4_LOCAL_STRENGTH_SHD +#define WDR4_LOCAL_STRENGTH_SHD_MASK (0xff << 16 ) +#define WDR4_LOCAL_STRENGTH_SHD_SHIFT 16U + +#define WDR4_GLOBAL_STRENGTH_SHD +#define WDR4_GLOBAL_STRENGTH_SHD_MASK (0xff << 8 ) +#define WDR4_GLOBAL_STRENGTH_SHD_SHIFT 8U + +#define WDR4_LOW_STRENGTH_SHD +#define WDR4_LOW_STRENGTH_SHD_MASK (0xff << 0 ) +#define WDR4_LOW_STRENGTH_SHD_SHIFT 0U + +#define WDR4_HIGH_STRENGTH_SHD +#define WDR4_HIGH_STRENGTH_SHD_MASK (0xff << 16 ) +#define WDR4_HIGH_STRENGTH_SHD_SHIFT 16U + +#define WDR4_DRC_BAYER_RATIOLSVS_SHD +#define WDR4_DRC_BAYER_RATIOLSVS_SHD_MASK (0xff << 8 ) +#define WDR4_DRC_BAYER_RATIOLSVS_SHD_SHIFT 8U + +#define WDR4_DRC_BAYER_RATIO_SHD +#define WDR4_DRC_BAYER_RATIO_SHD_MASK (0xff << 0 ) +#define WDR4_DRC_BAYER_RATIO_SHD_SHIFT 0U + +#define WDR4_CONTRAST_SHD +#define WDR4_CONTRAST_SHD_MASK (0x7ff << 10 ) +#define WDR4_CONTRAST_SHD_SHIFT 10U + +#define WDR4_FLAT_STRENGTH_SHD +#define WDR4_FLAT_STRENGTH_SHD_MASK (0x1f << 5 ) +#define WDR4_FLAT_STRENGTH_SHD_SHIFT 5U + +#define WDR4_FLAT_THR_SHD +#define WDR4_FLAT_THR_SHD_MASK (0x1f << 0 ) +#define WDR4_FLAT_THR_SHD_SHIFT 0U + +#define WDR4_PIXEL_MERGE_SLOPE_SHD +#define WDR4_PIXEL_MERGE_SLOPE_SHD_MASK (0xff << 24 ) +#define WDR4_PIXEL_MERGE_SLOPE_SHD_SHIFT 24U + +#define WDR4_PIXEL_MERGE_BASE_SHD +#define WDR4_PIXEL_MERGE_BASE_SHD_MASK (0xff << 16 ) +#define WDR4_PIXEL_MERGE_BASE_SHD_SHIFT 16U + +#define WDR4_PIXEL_ADJUST_SLOPE_SHD +#define WDR4_PIXEL_ADJUST_SLOPE_SHD_MASK (0xff << 8 ) +#define WDR4_PIXEL_ADJUST_SLOPE_SHD_SHIFT 8U + +#define WDR4_PIXEL_ADJUST_BASE_SHD +#define WDR4_PIXEL_ADJUST_BASE_SHD_MASK (0xff << 0 ) +#define WDR4_PIXEL_ADJUST_BASE_SHD_SHIFT 0U + +#define WDR4_ENABLE_SHD +#define WDR4_ENABLE_SHD_MASK 0x1 << 20 +#define WDR4_ENABLE_SHD_SHIFT 20U + +#define WDR4_ENTROPY_SLOPE_SHD +#define WDR4_ENTROPY_SLOPE_SHD_MASK (0x3ff << 10 ) +#define WDR4_ENTROPY_SLOPE_SHD_SHIFT 10U + +#define WDR4_ENTROPY_BASE_SHD +#define WDR4_ENTROPY_BASE_SHD_MASK (0x3ff << 0 ) +#define WDR4_ENTROPY_BASE_SHD_SHIFT 0U + +#define DENOISE3D_V20_INVGAMMA_EN +#define DENOISE3D_V20_INVGAMMA_EN_MASK (0x1 << 11) +#define DENOISE3D_V20_INVGAMMA_EN_SHIFT 11U + +#define DENOISE3D_V20_PREGAMMA_EN +#define DENOISE3D_V20_PREGAMMA_EN_MASK (0x1 << 10) +#define DENOISE3D_V20_PREGAMMA_EN_SHIFT 10U + +#define DENOISE3D_V20_ERODE_EN +#define DENOISE3D_V20_ERODE_EN_MASK (0x1 << 9) +#define DENOISE3D_V20_ERODE_EN_SHIFT 9U + +#define DENOISE3D_V20_MOTION_CONV_EN +#define DENOISE3D_V20_MOTION_CONV_EN_MASK (0x1 << 8) +#define DENOISE3D_V20_MOTION_CONV_EN_SHIFT 8U + +#define DENOISE3D_V20_INV_DGAIN_EN +#define DENOISE3D_V20_INV_DGAIN_EN_MASK (0x1 << 7) +#define DENOISE3D_V20_INV_DGAIN_EN_SHIFT 7U + +#define DENOISE3D_V20_INV_AWB_GAIN_EN +#define DENOISE3D_V20_INV_AWB_GAIN_EN_MASK (0x1 << 6) +#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHIFT 6U + +#define DENOISE3D_V20_COMP_LUMA_EN +#define DENOISE3D_V20_COMP_LUMA_EN_MASK (0x1 << 5) +#define DENOISE3D_V20_COMP_LUMA_EN_SHIFT 5U + +#define DENOISE3D_V20_REF_RESET +#define DENOISE3D_V20_REF_RESET_MASK (0x1 << 4) +#define DENOISE3D_V20_REF_RESET_SHIFT 4U + +#define DENOISE3D_V20_MOTION_DILATE_ENABLE +#define DENOISE3D_V20_MOTION_DILATE_ENABLE_MASK (0x1 << 3) +#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHIFT 3U + +#define DENOISE3D_V20_NLM_ENABLE +#define DENOISE3D_V20_NLM_ENABLE_MASK (0x1 << 2) +#define DENOISE3D_V20_NLM_ENABLE_SHIFT 2U + +#define DENOISE3D_V20_TNR_ENABLE +#define DENOISE3D_V20_TNR_ENABLE_MASK (0x1 << 1) +#define DENOISE3D_V20_TNR_ENABLE_SHIFT 1U + +#define DENOISE3D_V20_ENABLE +#define DENOISE3D_V20_ENABLE_MASK (0x1 << 0) +#define DENOISE3D_V20_ENABLE_SHIFT 0U + +#define DENOISE3D_V20_TNR_STRENGTH +#define DENOISE3D_V20_TNR_STRENGTH_MASK (0xff << 0 ) +#define DENOISE3D_V20_TNR_STRENGTH_SHIFT 0U + +#define DENOISE3D_V20_NOISE_LEVEL +#define DENOISE3D_V20_NOISE_LEVEL_MASK (0xffff << 16 ) +#define DENOISE3D_V20_NOISE_LEVEL_SHIFT 16U + +#define DENOISE3D_V20_NOISE_MEAN +#define DENOISE3D_V20_NOISE_MEAN_MASK (0xffff << 0 ) +#define DENOISE3D_V20_NOISE_MEAN_SHIFT 0U + +#define DENOISE3D_V20_NOSIE_THRESH +#define DENOISE3D_V20_NOSIE_THRESH_MASK (0xffff << 16 ) +#define DENOISE3D_V20_NOSIE_THRESH_SHIFT 16U + +#define DENOISE3D_V20_MOTION_MEAN +#define DENOISE3D_V20_MOTION_MEAN_MASK (0xffff << 0 ) +#define DENOISE3D_V20_MOTION_MEAN_SHIFT 0U + +#define DENOISE3D_V20_TNR_RANGE_H +#define DENOISE3D_V20_TNR_RANGE_H_MASK (0xf << 12 ) +#define DENOISE3D_V20_TNR_RANGE_H_SHIFT 12U + +#define DENOISE3D_V20_TNR_RANGE_V +#define DENOISE3D_V20_TNR_RANGE_V_MASK (0xf << 8 ) +#define DENOISE3D_V20_TNR_RANGE_V_SHIFT 8U + +#define DENOISE3D_V20_TNR_DILATE_RANGE_H +#define DENOISE3D_V20_TNR_DILATE_RANGE_H_MASK (0xf << 4 ) +#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHIFT 4U + +#define DENOISE3D_V20_TNR_DILATE_RANGE_V +#define DENOISE3D_V20_TNR_DILATE_RANGE_V_MASK (0xf << 0 ) +#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHIFT 0U + +#define DENOISE3D_V20_MOTION_INV +#define DENOISE3D_V20_MOTION_INV_MASK (0xfffff << 0 ) +#define DENOISE3D_V20_MOTION_INV_SHIFT 0U + +#define DENOISE3D_V20_THR_UPDATE +#define DENOISE3D_V20_THR_UPDATE_MASK (0x7ff << 16 ) +#define DENOISE3D_V20_THR_UPDATE_SHIFT 16U + +#define DENOISE3D_V20_MOTION_THR_UPDATE +#define DENOISE3D_V20_MOTION_THR_UPDATE_MASK (0x7ff << 0 ) +#define DENOISE3D_V20_MOTION_THR_UPDATE_SHIFT 0U + +#define DENOISE3D_V20_MOTION_PRE_WEIGHT +#define DENOISE3D_V20_MOTION_PRE_WEIGHT_MASK (0x3f << 16 ) +#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHIFT 16U + +#define DENOISE3D_V20_MOTION_SLOPE +#define DENOISE3D_V20_MOTION_SLOPE_MASK (0x7ff << 0 ) +#define DENOISE3D_V20_MOTION_SLOPE_SHIFT 0U + +#define DENOISE3D_V20_MOTION_CONV_SHIFT +#define DENOISE3D_V20_MOTION_CONV_SHIFT_MASK (0xf << 28 ) +#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHIFT 28U + +#define DENOISE3D_V20_MOTION_CONV_MAX +#define DENOISE3D_V20_MOTION_CONV_MAX_MASK (0x7ff << 17 ) +#define DENOISE3D_V20_MOTION_CONV_MAX_SHIFT 17U + +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_MASK (0x3f << 11 ) +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHIFT 11U + +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_MASK (0x3f << 5 ) +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHIFT 5U + +#define DENOISE3D_V20_SAD_WEIGHT +#define DENOISE3D_V20_SAD_WEIGHT_MASK (0x1f << 0 ) +#define DENOISE3D_V20_SAD_WEIGHT_SHIFT 0U + +#define DENOISE3D_V20_PIXEL_VAL_SHIFT +#define DENOISE3D_V20_PIXEL_VAL_SHIFT_MASK (0x7ff << 20 ) +#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHIFT 20U + +#define DENOISE3D_V20_PIXEL_SLOP +#define DENOISE3D_V20_PIXEL_SLOP_MASK (0xff << 12 ) +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT 12U + +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT_MASK (0xf << 8 ) +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT_SHIFT 8U + +#define DENOISE3D_V20_PIXEL_SLOP_MIN +#define DENOISE3D_V20_PIXEL_SLOP_MIN_MASK (0xff << 0 ) +#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHIFT 0U + +#define DENOISE3D_V20_INVGAMMA_EN_SHD +#define DENOISE3D_V20_INVGAMMA_EN_SHD_MASK 0x1 << 11 +#define DENOISE3D_V20_INVGAMMA_EN_SHD_SHIFT 11U + +#define DENOISE3D_V20_PREGAMMA_EN_SHD +#define DENOISE3D_V20_PREGAMMA_EN_SHD_MASK 0x1 << 10 +#define DENOISE3D_V20_PREGAMMA_EN_SHD_SHIFT 10U + +#define DENOISE3D_V20_ERODE_EN_SHD +#define DENOISE3D_V20_ERODE_EN_SHD_MASK 0x1 << 9 +#define DENOISE3D_V20_ERODE_EN_SHD_SHIFT 9U + +#define DENOISE3D_V20_MOTION_CONV_EN_SHD +#define DENOISE3D_V20_MOTION_CONV_EN_SHD_MASK 0x1 << 8 +#define DENOISE3D_V20_MOTION_CONV_EN_SHD_SHIFT 8U + +#define DENOISE3D_V20_INV_DGAIN_EN_SHD +#define DENOISE3D_V20_INV_DGAIN_EN_SHD_MASK 0x1 << 7 +#define DENOISE3D_V20_INV_DGAIN_EN_SHD_SHIFT 7U + +#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD +#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD_MASK 0x1 << 6 +#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD_SHIFT 6U + +#define DENOISE3D_V20_COMP_LUMA_EN_SHD +#define DENOISE3D_V20_COMP_LUMA_EN_SHD_MASK 0x1 << 5 +#define DENOISE3D_V20_COMP_LUMA_EN_SHD_SHIFT 5U + +#define DENOISE3D_V20_REF_RESET_SHD +#define DENOISE3D_V20_REF_RESET_SHD_MASK 0x1 << 4 +#define DENOISE3D_V20_REF_RESET_SHD_SHIFT 4U + +#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD +#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD_MASK 0x1 << 3 +#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD_SHIFT 3U + +#define DENOISE3D_V20_NLM_ENABLE_SHD +#define DENOISE3D_V20_NLM_ENABLE_SHD_MASK 0x1 << 2 +#define DENOISE3D_V20_NLM_ENABLE_SHD_SHIFT 2U + +#define DENOISE3D_V20_TNR_ENABLE_SHD +#define DENOISE3D_V20_TNR_ENABLE_SHD_MASK 0x1 << 1 +#define DENOISE3D_V20_TNR_ENABLE_SHD_SHIFT 1U + +#define DENOISE3D_V20_ENABLE_SHD +#define DENOISE3D_V20_ENABLE_SHD_MASK 0x1 << 0 +#define DENOISE3D_V20_ENABLE_SHD_SHIFT 0U + +#define DENOISE3D_V20_TNR_STRENGTH_SHD +#define DENOISE3D_V20_TNR_STRENGTH_SHD_MASK (0xff << 0 ) +#define DENOISE3D_V20_TNR_STRENGTH_SHD_SHIFT 0U + +#define DENOISE3D_V20_NOISE_LEVEL_SHD +#define DENOISE3D_V20_NOISE_LEVEL_SHD_MASK (0x3fff << 16 ) +#define DENOISE3D_V20_NOISE_LEVEL_SHD_SHIFT 16U + +#define DENOISE3D_V20_NOISE_MEAN_SHD +#define DENOISE3D_V20_NOISE_MEAN_SHD_MASK (0x3fff << 0 ) +#define DENOISE3D_V20_NOISE_MEAN_SHD_SHIFT 0U + +#define DENOISE3D_V20_NOSIE_THRESH_SHD +#define DENOISE3D_V20_NOSIE_THRESH_SHD_MASK (0x3fff << 16 ) +#define DENOISE3D_V20_NOSIE_THRESH_SHD_SHIFT 16U + +#define DENOISE3D_V20_MOTION_MEAN_SHD +#define DENOISE3D_V20_MOTION_MEAN_SHD_MASK (0x3fff << 0 ) +#define DENOISE3D_V20_MOTION_MEAN_SHD_SHIFT 0U + +#define DENOISE3D_V20_TNR_RANGE_H_SHD +#define DENOISE3D_V20_TNR_RANGE_H_SHD_MASK (0x3 << 8 ) +#define DENOISE3D_V20_TNR_RANGE_H_SHD_SHIFT 8U + +#define DENOISE3D_V20_TNR_RANGE_V_SHD +#define DENOISE3D_V20_TNR_RANGE_V_SHD_MASK (0x3 << 6 ) +#define DENOISE3D_V20_TNR_RANGE_V_SHD_SHIFT 6U + +#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD +#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD_MASK (0x7 << 3 ) +#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD_SHIFT 3U + +#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD +#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD_MASK (0x7 << 0 ) +#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD_SHIFT 0U + +#define DENOISE3D_V20_MOTION_INV_SHD +#define DENOISE3D_V20_MOTION_INV_SHD_MASK (0xfffff << 0 ) +#define DENOISE3D_V20_MOTION_INV_SHD_SHIFT 0U + +#define DENOISE3D_V20_THR_UPDATE_SHD +#define DENOISE3D_V20_THR_UPDATE_SHD_MASK (0x7ff << 16 ) +#define DENOISE3D_V20_THR_UPDATE_SHD_SHIFT 16U + +#define DENOISE3D_V20_MOTION_THR_UPDATE_SHD +#define DENOISE3D_V20_MOTION_THR_UPDATE_SHD_MASK (0x7ff << 0 ) +#define DENOISE3D_V20_MOTION_THR_UPDATE_SHD_SHIFT 0U + +#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD +#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD_MASK (0x7ff << 16 ) +#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD_SHIFT 16U + +#define DENOISE3D_V20_MOTION_SLOPE_SHD +#define DENOISE3D_V20_MOTION_SLOPE_SHD_MASK (0x7ff << 0 ) +#define DENOISE3D_V20_MOTION_SLOPE_SHD_SHIFT 0U + +#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD +#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD_MASK (0xf << 28 ) +#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD_SHIFT 28U + +#define DENOISE3D_V20_MOTION_CONV_MAX_SHD +#define DENOISE3D_V20_MOTION_CONV_MAX_SHD_MASK (0x7ff << 17 ) +#define DENOISE3D_V20_MOTION_CONV_MAX_SHD_SHIFT 17U + +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD_MASK (0x3f << 11 ) +#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD_SHIFT 11U + +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD_MASK (0x3f << 5 ) +#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD_SHIFT 5U + +#define DENOISE3D_V20_SAD_WEIGHT_SHD +#define DENOISE3D_V20_SAD_WEIGHT_SHD_MASK (0x1f << 0 ) +#define DENOISE3D_V20_SAD_WEIGHT_SHD_SHIFT 0U + +#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD +#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD_MASK (0x7ff << 20 ) +#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD_SHIFT 20U + +#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD +#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD_MASK (0xff << 12 ) +#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD_SHIFT 12U + +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD_MASK (0xf << 8 ) +#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD_SHIFT 8U + +#define DENOISE3D_V20_BG_VAL_SUM +#define DENOISE3D_V20_BG_VAL_SUM_MASK (0xffffffff << 0 ) +#define DENOISE3D_V20_BG_VAL_SUM_SHIFT 0U + +#define DENOISE3D_V20_MO_VAL_SUM +#define DENOISE3D_V20_MO_VAL_SUM_MASK (0xffffffff << 0 ) +#define DENOISE3D_V20_MO_VAL_SUM_SHIFT 0U + +#define DENOISE3D_V20_BG_PIX_CNT +#define DENOISE3D_V20_BG_PIX_CNT_MASK (0xffffffff << 0 ) +#define DENOISE3D_V20_BG_PIX_CNT_SHIFT 0U + +#define DENOISE3D_V20_MO_PIX_CNT +#define DENOISE3D_V20_MO_PIX_CNT_MASK (0xffffffff << 0 ) +#define DENOISE3D_V20_MO_PIX_CNT_SHIFT 0U + +#define DENOISE3D_V20_FRAME_AVG +#define DENOISE3D_V20_FRAME_AVG_MASK (0xffffffff << 0 ) +#define DENOISE3D_V20_FRAME_AVG_SHIFT 0U + +#define DENOISE3D_V20_DUMMY_HBLANK +#define DENOISE3D_V20_DUMMY_HBLANK_MASK (0xffff << 0 ) +#define DENOISE3D_V20_DUMMY_HBLANK_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_2_A +#define DENOISE3D2_PREGAMMA_Y_2_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_2_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_1 +#define DENOISE3D2_PREGAMMA_Y_1_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_1_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_0 +#define DENOISE3D2_PREGAMMA_Y_0_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_0_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_2_B +#define DENOISE3D2_PREGAMMA_Y_2_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_2_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_4 +#define DENOISE3D2_PREGAMMA_Y_4_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_4_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_3 +#define DENOISE3D2_PREGAMMA_Y_3_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_3_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_7_A +#define DENOISE3D2_PREGAMMA_Y_7_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_7_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_6 +#define DENOISE3D2_PREGAMMA_Y_6_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_6_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_5 +#define DENOISE3D2_PREGAMMA_Y_5_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_5_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_7_B +#define DENOISE3D2_PREGAMMA_Y_7_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_7_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_9 +#define DENOISE3D2_PREGAMMA_Y_9_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_9_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_8 +#define DENOISE3D2_PREGAMMA_Y_8_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_8_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_12_A +#define DENOISE3D2_PREGAMMA_Y_12_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_12_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_11 +#define DENOISE3D2_PREGAMMA_Y_11_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_11_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_10 +#define DENOISE3D2_PREGAMMA_Y_10_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_10_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_12_B +#define DENOISE3D2_PREGAMMA_Y_12_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_12_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_14 +#define DENOISE3D2_PREGAMMA_Y_14_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_14_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_13 +#define DENOISE3D2_PREGAMMA_Y_13_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_13_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_17_A +#define DENOISE3D2_PREGAMMA_Y_17_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_17_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_16 +#define DENOISE3D2_PREGAMMA_Y_16_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_16_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_15 +#define DENOISE3D2_PREGAMMA_Y_15_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_15_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_17_B +#define DENOISE3D2_PREGAMMA_Y_17_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_17_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_19 +#define DENOISE3D2_PREGAMMA_Y_19_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_19_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_18 +#define DENOISE3D2_PREGAMMA_Y_18_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_18_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_22_A +#define DENOISE3D2_PREGAMMA_Y_22_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_22_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_21 +#define DENOISE3D2_PREGAMMA_Y_21_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_21_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_20 +#define DENOISE3D2_PREGAMMA_Y_20_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_20_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_22_B +#define DENOISE3D2_PREGAMMA_Y_22_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_22_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_24 +#define DENOISE3D2_PREGAMMA_Y_24_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_24_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_23 +#define DENOISE3D2_PREGAMMA_Y_23_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_23_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_27_A +#define DENOISE3D2_PREGAMMA_Y_27_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_27_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_26 +#define DENOISE3D2_PREGAMMA_Y_26_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_26_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_25 +#define DENOISE3D2_PREGAMMA_Y_25_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_25_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_27_B +#define DENOISE3D2_PREGAMMA_Y_27_B_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_27_B_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_29 +#define DENOISE3D2_PREGAMMA_Y_29_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_29_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_28 +#define DENOISE3D2_PREGAMMA_Y_28_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_28_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_32_A +#define DENOISE3D2_PREGAMMA_Y_32_A_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_32_A_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_31 +#define DENOISE3D2_PREGAMMA_Y_31_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_31_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_30 +#define DENOISE3D2_PREGAMMA_Y_30_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_30_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_32_B +#define DENOISE3D2_PREGAMMA_Y_32_B_MASK (0x3f << 0 ) +#define DENOISE3D2_PREGAMMA_Y_32_B_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_2_A_SHD +#define DENOISE3D2_PREGAMMA_Y_2_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_2_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_1_SHD +#define DENOISE3D2_PREGAMMA_Y_1_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_1_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_0_SHD +#define DENOISE3D2_PREGAMMA_Y_0_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_0_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_2_B_SHD +#define DENOISE3D2_PREGAMMA_Y_2_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_2_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_4_SHD +#define DENOISE3D2_PREGAMMA_Y_4_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_4_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_3_SHD +#define DENOISE3D2_PREGAMMA_Y_3_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_3_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_7_A_SHD +#define DENOISE3D2_PREGAMMA_Y_7_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_7_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_6_SHD +#define DENOISE3D2_PREGAMMA_Y_6_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_6_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_5_SHD +#define DENOISE3D2_PREGAMMA_Y_5_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_5_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_7_B_SHD +#define DENOISE3D2_PREGAMMA_Y_7_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_7_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_9_SHD +#define DENOISE3D2_PREGAMMA_Y_9_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_9_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_8_SHD +#define DENOISE3D2_PREGAMMA_Y_8_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_8_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_12_A_SHD +#define DENOISE3D2_PREGAMMA_Y_12_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_12_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_11_SHD +#define DENOISE3D2_PREGAMMA_Y_11_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_11_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_10_SHD +#define DENOISE3D2_PREGAMMA_Y_10_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_10_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_12_B_SHD +#define DENOISE3D2_PREGAMMA_Y_12_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_12_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_14_SHD +#define DENOISE3D2_PREGAMMA_Y_14_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_14_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_13_SHD +#define DENOISE3D2_PREGAMMA_Y_13_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_13_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_17_A_SHD +#define DENOISE3D2_PREGAMMA_Y_17_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_17_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_16_SHD +#define DENOISE3D2_PREGAMMA_Y_16_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_16_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_15_SHD +#define DENOISE3D2_PREGAMMA_Y_15_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_15_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_17_B_SHD +#define DENOISE3D2_PREGAMMA_Y_17_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_17_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_19_SHD +#define DENOISE3D2_PREGAMMA_Y_19_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_19_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_18_SHD +#define DENOISE3D2_PREGAMMA_Y_18_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_18_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_22_A_SHD +#define DENOISE3D2_PREGAMMA_Y_22_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_22_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_21_SHD +#define DENOISE3D2_PREGAMMA_Y_21_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_21_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_20_SHD +#define DENOISE3D2_PREGAMMA_Y_20_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_20_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_22_B_SHD +#define DENOISE3D2_PREGAMMA_Y_22_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_22_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_24_SHD +#define DENOISE3D2_PREGAMMA_Y_24_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_24_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_23_SHD +#define DENOISE3D2_PREGAMMA_Y_23_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_23_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_27_A_SHD +#define DENOISE3D2_PREGAMMA_Y_27_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_27_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_26_SHD +#define DENOISE3D2_PREGAMMA_Y_26_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_26_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_25_SHD +#define DENOISE3D2_PREGAMMA_Y_25_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_25_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_27_B_SHD +#define DENOISE3D2_PREGAMMA_Y_27_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_27_B_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_29_SHD +#define DENOISE3D2_PREGAMMA_Y_29_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_29_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_28_SHD +#define DENOISE3D2_PREGAMMA_Y_28_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_28_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_32_A_SHD +#define DENOISE3D2_PREGAMMA_Y_32_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_PREGAMMA_Y_32_A_SHD_SHIFT 24U + +#define DENOISE3D2_PREGAMMA_Y_31_SHD +#define DENOISE3D2_PREGAMMA_Y_31_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_PREGAMMA_Y_31_SHD_SHIFT 12U + +#define DENOISE3D2_PREGAMMA_Y_30_SHD +#define DENOISE3D2_PREGAMMA_Y_30_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_PREGAMMA_Y_30_SHD_SHIFT 0U + +#define DENOISE3D2_PREGAMMA_Y_32_B_SHD +#define DENOISE3D2_PREGAMMA_Y_32_B_SHD_MASK (0x3f << 0 ) +#define DENOISE3D2_PREGAMMA_Y_32_B_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_2_A +#define DENOISE3D2_INVGAMMA_Y_2_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_2_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_1 +#define DENOISE3D2_INVGAMMA_Y_1_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_1_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_0 +#define DENOISE3D2_INVGAMMA_Y_0_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_0_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_2_B +#define DENOISE3D2_INVGAMMA_Y_2_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_2_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_4 +#define DENOISE3D2_INVGAMMA_Y_4_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_4_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_3 +#define DENOISE3D2_INVGAMMA_Y_3_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_3_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_7_A +#define DENOISE3D2_INVGAMMA_Y_7_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_7_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_6 +#define DENOISE3D2_INVGAMMA_Y_6_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_6_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_5 +#define DENOISE3D2_INVGAMMA_Y_5_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_5_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_7_B +#define DENOISE3D2_INVGAMMA_Y_7_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_7_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_9 +#define DENOISE3D2_INVGAMMA_Y_9_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_9_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_8 +#define DENOISE3D2_INVGAMMA_Y_8_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_8_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_12_A +#define DENOISE3D2_INVGAMMA_Y_12_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_12_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_11 +#define DENOISE3D2_INVGAMMA_Y_11_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_11_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_10 +#define DENOISE3D2_INVGAMMA_Y_10_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_10_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_12_B +#define DENOISE3D2_INVGAMMA_Y_12_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_12_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_14 +#define DENOISE3D2_INVGAMMA_Y_14_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_14_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_13 +#define DENOISE3D2_INVGAMMA_Y_13_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_13_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_17_A +#define DENOISE3D2_INVGAMMA_Y_17_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_17_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_16 +#define DENOISE3D2_INVGAMMA_Y_16_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_16_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_15 +#define DENOISE3D2_INVGAMMA_Y_15_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_15_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_17_B +#define DENOISE3D2_INVGAMMA_Y_17_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_17_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_19 +#define DENOISE3D2_INVGAMMA_Y_19_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_19_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_18 +#define DENOISE3D2_INVGAMMA_Y_18_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_18_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_22_A +#define DENOISE3D2_INVGAMMA_Y_22_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_22_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_21 +#define DENOISE3D2_INVGAMMA_Y_21_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_21_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_20 +#define DENOISE3D2_INVGAMMA_Y_20_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_20_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_22_B +#define DENOISE3D2_INVGAMMA_Y_22_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_22_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_24 +#define DENOISE3D2_INVGAMMA_Y_24_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_24_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_23 +#define DENOISE3D2_INVGAMMA_Y_23_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_23_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_27_A +#define DENOISE3D2_INVGAMMA_Y_27_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_27_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_26 +#define DENOISE3D2_INVGAMMA_Y_26_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_26_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_25 +#define DENOISE3D2_INVGAMMA_Y_25_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_25_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_27_B +#define DENOISE3D2_INVGAMMA_Y_27_B_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_27_B_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_29 +#define DENOISE3D2_INVGAMMA_Y_29_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_29_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_28 +#define DENOISE3D2_INVGAMMA_Y_28_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_28_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_32_A +#define DENOISE3D2_INVGAMMA_Y_32_A_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_32_A_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_31 +#define DENOISE3D2_INVGAMMA_Y_31_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_31_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_30 +#define DENOISE3D2_INVGAMMA_Y_30_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_30_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_32_B +#define DENOISE3D2_INVGAMMA_Y_32_B_MASK (0x3f << 0 ) +#define DENOISE3D2_INVGAMMA_Y_32_B_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_2_A_SHD +#define DENOISE3D2_INVGAMMA_Y_2_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_2_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_1_SHD +#define DENOISE3D2_INVGAMMA_Y_1_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_1_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_0_SHD +#define DENOISE3D2_INVGAMMA_Y_0_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_0_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_2_B_SHD +#define DENOISE3D2_INVGAMMA_Y_2_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_2_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_4_SHD +#define DENOISE3D2_INVGAMMA_Y_4_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_4_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_3_SHD +#define DENOISE3D2_INVGAMMA_Y_3_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_3_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_7_A_SHD +#define DENOISE3D2_INVGAMMA_Y_7_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_7_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_6_SHD +#define DENOISE3D2_INVGAMMA_Y_6_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_6_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_5_SHD +#define DENOISE3D2_INVGAMMA_Y_5_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_5_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_7_B_SHD +#define DENOISE3D2_INVGAMMA_Y_7_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_7_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_9_SHD +#define DENOISE3D2_INVGAMMA_Y_9_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_9_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_8_SHD +#define DENOISE3D2_INVGAMMA_Y_8_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_8_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_12_A_SHD +#define DENOISE3D2_INVGAMMA_Y_12_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_12_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_11_SHD +#define DENOISE3D2_INVGAMMA_Y_11_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_11_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_10_SHD +#define DENOISE3D2_INVGAMMA_Y_10_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_10_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_12_B_SHD +#define DENOISE3D2_INVGAMMA_Y_12_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_12_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_14_SHD +#define DENOISE3D2_INVGAMMA_Y_14_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_14_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_13_SHD +#define DENOISE3D2_INVGAMMA_Y_13_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_13_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_17_A_SHD +#define DENOISE3D2_INVGAMMA_Y_17_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_17_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_16_SHD +#define DENOISE3D2_INVGAMMA_Y_16_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_16_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_15_SHD +#define DENOISE3D2_INVGAMMA_Y_15_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_15_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_17_B_SHD +#define DENOISE3D2_INVGAMMA_Y_17_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_17_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_19_SHD +#define DENOISE3D2_INVGAMMA_Y_19_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_19_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_18_SHD +#define DENOISE3D2_INVGAMMA_Y_18_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_18_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_22_A_SHD +#define DENOISE3D2_INVGAMMA_Y_22_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_22_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_21_SHD +#define DENOISE3D2_INVGAMMA_Y_21_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_21_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_20_SHD +#define DENOISE3D2_INVGAMMA_Y_20_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_20_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_22_B_SHD +#define DENOISE3D2_INVGAMMA_Y_22_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_22_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_24_SHD +#define DENOISE3D2_INVGAMMA_Y_24_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_24_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_23_SHD +#define DENOISE3D2_INVGAMMA_Y_23_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_23_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_27_A_SHD +#define DENOISE3D2_INVGAMMA_Y_27_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_27_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_26_SHD +#define DENOISE3D2_INVGAMMA_Y_26_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_26_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_25_SHD +#define DENOISE3D2_INVGAMMA_Y_25_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_25_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_27_B_SHD +#define DENOISE3D2_INVGAMMA_Y_27_B_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_27_B_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_29_SHD +#define DENOISE3D2_INVGAMMA_Y_29_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_29_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_28_SHD +#define DENOISE3D2_INVGAMMA_Y_28_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_28_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_32_A_SHD +#define DENOISE3D2_INVGAMMA_Y_32_A_SHD_MASK (0x3f << 24 ) +#define DENOISE3D2_INVGAMMA_Y_32_A_SHD_SHIFT 24U + +#define DENOISE3D2_INVGAMMA_Y_31_SHD +#define DENOISE3D2_INVGAMMA_Y_31_SHD_MASK (0xfff << 12 ) +#define DENOISE3D2_INVGAMMA_Y_31_SHD_SHIFT 12U + +#define DENOISE3D2_INVGAMMA_Y_30_SHD +#define DENOISE3D2_INVGAMMA_Y_30_SHD_MASK (0xfff << 0 ) +#define DENOISE3D2_INVGAMMA_Y_30_SHD_SHIFT 0U + +#define DENOISE3D2_INVGAMMA_Y_32_B_SHD +#define DENOISE3D2_INVGAMMA_Y_32_B_SHD_MASK (0x3f << 0 ) +#define DENOISE3D2_INVGAMMA_Y_32_B_SHD_SHIFT 0U + +#define DENOISE3D2_NLM_STRENGTH_SLOPE +#define DENOISE3D2_NLM_STRENGTH_SLOPE_MASK (0xff << 0 ) +#define DENOISE3D2_NLM_STRENGTH_SLOPE_SHIFT 0U + +#define DENOISE3D2_TNR +#define DENOISE3D2_TNR_MASK (0x7ff << 0 ) +#define DENOISE3D2_TNR_SHIFT 0U + +#define PP_RD_YUV_CFG_UPDATE +#define PP_RD_YUV_CFG_UPDATE_MASK 0x1 << 7 +#define PP_RD_YUV_CFG_UPDATE_SHIFT 7U + +#define PP_RD_YUV_AUTO_UPDATE +#define PP_RD_YUV_AUTO_UPDATE_MASK 0x1 << 6 +#define PP_RD_YUV_AUTO_UPDATE_SHIFT 6U + +#define PP_INIT_OFFSET_EN +#define PP_INIT_OFFSET_EN_MASK 0x1 << 5 +#define PP_INIT_OFFSET_EN_SHIFT 5U + +#define PP_INIT_BASE_EN +#define PP_INIT_BASE_EN_MASK 0x1 << 4 +#define PP_INIT_BASE_EN_SHIFT 4U + +#define PP_MI_CFG_UPD +#define PP_MI_CFG_UPD_MASK 0x1 << 3 +#define PP_MI_CFG_UPD_SHIFT 3U + +#define PP_MI_SKIP +#define PP_MI_SKIP_MASK 0x1 << 2 +#define PP_MI_SKIP_SHIFT 2U + +#define PP_AUTO_UPDATE +#define PP_AUTO_UPDATE_MASK 0x1 << 1 +#define PP_AUTO_UPDATE_SHIFT 1U + +#define PP_PINGPONG_ENABLE +#define PP_PINGPONG_ENABLE_MASK 0x1 << 0 +#define PP_PINGPONG_ENABLE_SHIFT 0U + +#define PP_RD_RAW_ENABLE +#define PP_RD_RAW_ENABLE_MASK 0x1 << 31 +#define PP_RD_RAW_ENABLE_SHIFT 31U + +#define PP_RD_RAW_ALIGNED +#define PP_RD_RAW_ALIGNED_MASK (0x3 << 29 ) +#define PP_RD_RAW_ALIGNED_SHIFT 29U + +#define PP_RD_RAW_BIT +#define PP_RD_RAW_BIT_MASK (0x7 << 26 ) +#define PP_RD_RAW_BIT_SHIFT 26U + +#define PP_RD_YUV_NVY +#define PP_RD_YUV_NVY_MASK (0x3 << 24 ) +#define PP_RD_YUV_NVY_SHIFT 24U + +#define PP_RD_YUV_NV21 +#define PP_RD_YUV_NV21_MASK 0x1 << 23 +#define PP_RD_YUV_NV21_SHIFT 23U + +#define PP_RD_YUV_ALIGNED +#define PP_RD_YUV_ALIGNED_MASK 0x1 << 22 +#define PP_RD_YUV_ALIGNED_SHIFT 22U + +#define PP_RD_YUV_STR +#define PP_RD_YUV_STR_MASK (0x3 << 20 ) +#define PP_RD_YUV_STR_SHIFT 20U + +#define PP_RD_YUV_FMT +#define PP_RD_YUV_FMT_MASK (0x3 << 18 ) +#define PP_RD_YUV_FMT_SHIFT 18U + +#define PP_RD_YUV_BIT +#define PP_RD_YUV_BIT_MASK 0x1 << 17 +#define PP_RD_YUV_BIT_SHIFT 17U + +#define PP_WR_RAW_SEL +#define PP_WR_RAW_SEL_MASK 0x1 << 16 +#define PP_WR_RAW_SEL_SHIFT 16U + +#define PP_WR_RAW_ALIGNED +#define PP_WR_RAW_ALIGNED_MASK (0x3 << 14 ) +#define PP_WR_RAW_ALIGNED_SHIFT 14U + +#define PP_WR_RAW_BIT +#define PP_WR_RAW_BIT_MASK (0x7 << 11 ) +#define PP_WR_RAW_BIT_SHIFT 11U + +#define PP_WR_YUV_WORD_ALIGNED_MSB_EN +#define PP_WR_YUV_WORD_ALIGNED_MSB_EN_MASK 0x1 << 10 +#define PP_WR_YUV_WORD_ALIGNED_MSB_EN_SHIFT 10U + +#define PP_WR_YUV_WORD_ALIGNED +#define PP_WR_YUV_WORD_ALIGNED_MASK 0x1 << 9 +#define PP_WR_YUV_WORD_ALIGNED_SHIFT 9U + +#define PP_WR_YUV_NVY +#define PP_WR_YUV_NVY_MASK (0x3 << 7 ) +#define PP_WR_YUV_NVY_SHIFT 7U + +#define PP_WR_YUV_NV21 +#define PP_WR_YUV_NV21_MASK 0x1 << 6 +#define PP_WR_YUV_NV21_SHIFT 6U + +#define PP_WR_YUV_ALIGNED +#define PP_WR_YUV_ALIGNED_MASK 0x1 << 5 +#define PP_WR_YUV_ALIGNED_SHIFT 5U + +#define PP_WR_YUV_STR +#define PP_WR_YUV_STR_MASK (0x3 << 3 ) +#define PP_WR_YUV_STR_SHIFT 3U + +#define PP_WR_YUV_FMT +#define PP_WR_YUV_FMT_MASK (0x3 << 1 ) +#define PP_WR_YUV_FMT_SHIFT 1U + +#define PP_WR_YUV_BIT +#define PP_WR_YUV_BIT_MASK 0x1 << 0 +#define PP_WR_YUV_BIT_SHIFT 0U + +#define PP_RD_SWAP_V +#define PP_RD_SWAP_V_MASK 0xf << 24 +#define PP_RD_SWAP_V_SHIFT 24U + +#define PP_RD_SWAP_U +#define PP_RD_SWAP_U_MASK 0xf << 20 +#define PP_RD_SWAP_U_SHIFT 20U + +#define PP_RD_SWAP_Y +#define PP_RD_SWAP_Y_MASK 0xf << 16 +#define PP_RD_SWAP_Y_SHIFT 16U + +#define PP_WR_SWAP_V +#define PP_WR_SWAP_V_MASK 0xf << 8 +#define PP_WR_SWAP_V_SHIFT 8U + +#define PP_WR_SWAP_U +#define PP_WR_SWAP_U_MASK 0xf << 4 +#define PP_WR_SWAP_U_SHIFT 4U + +#define PP_WR_SWAP_Y +#define PP_WR_SWAP_Y_MASK 0xf << 0 +#define PP_WR_SWAP_Y_SHIFT 0U + +#define PP_Y_BASE_AD_INIT +#define PP_Y_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define PP_Y_BASE_AD_INIT_SHIFT 4U + +#define PP_Y_SIZE_INIT +#define PP_Y_SIZE_INIT_MASK (0x1ffffff << 4 ) +#define PP_Y_SIZE_INIT_SHIFT 4U + +#define PP_Y_OFFS_CNT_INIT +#define PP_Y_OFFS_CNT_INIT_MASK (0x1ffffff << 4 ) +#define PP_Y_OFFS_CNT_INIT_SHIFT 4U + +#define PP_Y_LLENGH +#define PP_Y_LLENGH_MASK (0xffffffff << 0 ) +#define PP_Y_LLENGH_SHIFT 0U + +#define PP_Y_PIC_WIDTH +#define PP_Y_PIC_WIDTH_MASK (0xffffffff << 0 ) +#define PP_Y_PIC_WIDTH_SHIFT 0U + +#define PP_Y_PIC_HEIGHT +#define PP_Y_PIC_HEIGHT_MASK (0xffffffff << 0 ) +#define PP_Y_PIC_HEIGHT_SHIFT 0U + +#define PP_Y_PIC_SIZE +#define PP_Y_PIC_SIZE_MASK (0xffffffff << 0 ) +#define PP_Y_PIC_SIZE_SHIFT 0U + +#define PP_CB_BASE_AD_INIT +#define PP_CB_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define PP_CB_BASE_AD_INIT_SHIFT 4U + +#define PP_CB_SIZE_INIT +#define PP_CB_SIZE_INIT_MASK (0xffffff << 4 ) +#define PP_CB_SIZE_INIT_SHIFT 4U + +#define PP_CB_OFFS_CNT_INIT +#define PP_CB_OFFS_CNT_INIT_MASK (0xffffff << 4 ) +#define PP_CB_OFFS_CNT_INIT_SHIFT 4U + +#define PP_CR_BASE_AD_INIT +#define PP_CR_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define PP_CR_BASE_AD_INIT_SHIFT 4U + +#define PP_CR_SIZE_INIT +#define PP_CR_SIZE_INIT_MASK (0xffffff << 4 ) +#define PP_CR_SIZE_INIT_SHIFT 4U + +#define PP_CR_OFFS_CNT_INIT +#define PP_CR_OFFS_CNT_INIT_MASK (0xffffff << 4 ) +#define PP_CR_OFFS_CNT_INIT_SHIFT 4U + +#define PP_Y_BASE_AD_INIT2 +#define PP_Y_BASE_AD_INIT2_MASK (0xfffffff << 4 ) +#define PP_Y_BASE_AD_INIT2_SHIFT 4U + +#define PP_CB_BASE_AD_INIT2 +#define PP_CB_BASE_AD_INIT2_MASK (0xfffffff << 4 ) +#define PP_CB_BASE_AD_INIT2_SHIFT 4U + +#define PP_CR_BASE_AD_INIT2 +#define PP_CR_BASE_AD_INIT2_MASK (0xfffffff << 4 ) +#define PP_CR_BASE_AD_INIT2_SHIFT 4U + +#define PP_Y_OFFS_CNT_START +#define PP_Y_OFFS_CNT_START_MASK (0x1ffffff << 4 ) +#define PP_Y_OFFS_CNT_START_SHIFT 4U + +#define PP_CB_OFFS_CNT_START +#define PP_CB_OFFS_CNT_START_MASK (0xffffff << 4 ) +#define PP_CB_OFFS_CNT_START_SHIFT 4U + +#define PP_CR_OFFS_CNT_START +#define PP_CR_OFFS_CNT_START_MASK (0xffffff << 4 ) +#define PP_CR_OFFS_CNT_START_SHIFT 4U + +#define PP_Y_BASE_AD +#define PP_Y_BASE_AD_MASK (0xfffffff << 4 ) +#define PP_Y_BASE_AD_SHIFT 4U + +#define PP_Y_SIZE +#define PP_Y_SIZE_MASK (0x1ffffff << 4 ) +#define PP_Y_SIZE_SHIFT 4U + +#define PP_Y_OFFS_CNT +#define PP_Y_OFFS_CNT_MASK (0x1ffffff << 4 ) +#define PP_Y_OFFS_CNT_SHIFT 4U + +#define PP_CB_BASE_AD +#define PP_CB_BASE_AD_MASK (0xfffffff << 4 ) +#define PP_CB_BASE_AD_SHIFT 4U + +#define PP_CB_SIZE +#define PP_CB_SIZE_MASK (0xffffff << 4 ) +#define PP_CB_SIZE_SHIFT 4U + +#define PP_CB_OFFS_CNT +#define PP_CB_OFFS_CNT_MASK (0xffffff << 4 ) +#define PP_CB_OFFS_CNT_SHIFT 4U + +#define PP_CR_BASE_AD +#define PP_CR_BASE_AD_MASK (0xfffffff << 4 ) +#define PP_CR_BASE_AD_SHIFT 4U + +#define PP_CR_SIZE +#define PP_CR_SIZE_MASK (0xffffff << 4 ) +#define PP_CR_SIZE_SHIFT 4U + +#define PP_CR_OFFS_CNT +#define PP_CR_OFFS_CNT_MASK (0xffffff << 4 ) +#define PP_CR_OFFS_CNT_SHIFT 4U + +#define PP_DMA_Y_PIC_WIDTH +#define PP_DMA_Y_PIC_WIDTH_MASK (0x7fff << 0 ) +#define PP_DMA_Y_PIC_WIDTH_SHIFT 0U + +#define PP_DMA_Y_PIC_LLENGTH +#define PP_DMA_Y_PIC_LLENGTH_MASK (0xffffffff << 0 ) +#define PP_DMA_Y_PIC_LLENGTH_SHIFT 0U + +#define PP_DMA_Y_PIC_SIZE +#define PP_DMA_Y_PIC_SIZE_MASK (0xfffffff << 0 ) +#define PP_DMA_Y_PIC_SIZE_SHIFT 0U + +#define PP_DMA_CB_PIC_START_AD +#define PP_DMA_CB_PIC_START_AD_MASK (0xfffffff << 4 ) +#define PP_DMA_CB_PIC_START_AD_SHIFT 4U + +#define PP_DMA_CR_PIC_START_AD +#define PP_DMA_CR_PIC_START_AD_MASK (0xfffffff << 4 ) +#define PP_DMA_CR_PIC_START_AD_SHIFT 4U + +#define PP_DMA_Y_PIC_START_AD +#define PP_DMA_Y_PIC_START_AD_MASK (0xfffffff << 4 ) +#define PP_DMA_Y_PIC_START_AD_SHIFT 4U + +#define PP_DMA_CB_PIC_START_AD +#define PP_DMA_CB_PIC_START_AD_MASK (0xfffffff << 4 ) +#define PP_DMA_CB_PIC_START_AD_SHIFT 4U + +#define PP_DMA_CR_PIC_START_AD +#define PP_DMA_CR_PIC_START_AD_MASK (0xfffffff << 4 ) +#define PP_DMA_CR_PIC_START_AD_SHIFT 4U + +#define PP_DMA_Y_PIC_LVAL +#define PP_DMA_Y_PIC_LVAL_MASK (0xffff << 0 ) +#define PP_DMA_Y_PIC_LVAL_SHIFT 0U + + + +#define HDR_DMA_START_CONTINUOUS +#define HDR_DMA_START_CONTINUOUS_MASK 0x1 << 8 +#define HDR_DMA_START_CONTINUOUS_SHIFT 8U + +#define HDR_DMA_START +#define HDR_DMA_START_MASK 0x1 << 7 +#define HDR_DMA_START_SHIFT 7U + +#define HDR_WR_ENABLE +#define HDR_WR_ENABLE_MASK 0x1 << 6 +#define HDR_WR_ENABLE_SHIFT 6U + +#define HDR_RD_RAW_CFG_UPDATE +#define HDR_RD_RAW_CFG_UPDATE_MASK 0x1 << 5 +#define HDR_RD_RAW_CFG_UPDATE_SHIFT 5U + +#define HDR_RD_RAW_AUTO_UPDATE +#define HDR_RD_RAW_AUTO_UPDATE_MASK 0x1 << 4 +#define HDR_RD_RAW_AUTO_UPDATE_SHIFT 4U + +#define HDR_INIT_OFFSET_EN +#define HDR_INIT_OFFSET_EN_MASK 0x1 << 3 +#define HDR_INIT_OFFSET_EN_SHIFT 3U + +#define HDR_INIT_BASE_EN +#define HDR_INIT_BASE_EN_MASK 0x1 << 2 +#define HDR_INIT_BASE_EN_SHIFT 2U + +#define HDR_MI_CFG_UPD +#define HDR_MI_CFG_UPD_MASK 0x1 << 1 +#define HDR_MI_CFG_UPD_SHIFT 1U + +#define HDR_AUTO_UPDATE +#define HDR_AUTO_UPDATE_MASK 0x1 << 0 +#define HDR_AUTO_UPDATE_SHIFT 0U + +#define HDR_RD_RAW_ALIGNED +#define HDR_RD_RAW_ALIGNED_MASK (0x3 << 24 ) +#define HDR_RD_RAW_ALIGNED_SHIFT 24U + +#define HDR_RD_VS_BIT +#define HDR_RD_VS_BIT_MASK (0x3 << 22 ) +#define HDR_RD_VS_BIT_SHIFT 22U + +#define HDR_RD_S_BIT +#define HDR_RD_S_BIT_MASK (0x3 << 20 ) +#define HDR_RD_S_BIT_SHIFT 20U + +#define HDR_RD_L_BIT +#define HDR_RD_L_BIT_MASK (0x3 << 18 ) +#define HDR_RD_L_BIT_SHIFT 18U + +#define HDR_RD_STR +#define HDR_RD_STR_MASK (0x3 << 16 ) +#define HDR_RD_STR_SHIFT 16U + +#define HDR_WR_RAW_ALIGNED +#define HDR_WR_RAW_ALIGNED_MASK (0x3 << 8 ) +#define HDR_WR_RAW_ALIGNED_SHIFT 8U + +#define HDR_WR_VS_BIT +#define HDR_WR_VS_BIT_MASK (0x3 << 6 ) +#define HDR_WR_VS_BIT_SHIFT 6U + +#define HDR_WR_S_BIT +#define HDR_WR_S_BIT_MASK (0x3 << 4 ) +#define HDR_WR_S_BIT_SHIFT 4U + +#define HDR_WR_L_BIT +#define HDR_WR_L_BIT_MASK (0x3 << 2 ) +#define HDR_WR_L_BIT_SHIFT 2U + +#define HDR_WR_STR +#define HDR_WR_STR_MASK (0x3 << 0 ) +#define HDR_WR_STR_SHIFT 0U + +#define HDR_DMA_START_BY_LINES +#define HDR_DMA_START_BY_LINES_MASK (0xffff << 0 ) +#define HDR_DMA_START_BY_LINES_SHIFT 0U + +#define HDR_RD_SWAP_RAW +#define HDR_RD_SWAP_RAW_MASK (0xf << 16 ) +#define HDR_RD_SWAP_RAW_SHIFT 16U + +#define HDR_WR_SWAP_RAW +#define HDR_WR_SWAP_RAW_MASK (0xf << 0 ) +#define HDR_WR_SWAP_RAW_SHIFT 0U + +#define HDR_BUS_SW_EN +#define HDR_BUS_SW_EN_MASK 0x1 << 23 +#define HDR_BUS_SW_EN_SHIFT 23U + +#define HDR_RD_BURST_LEN +#define HDR_RD_BURST_LEN_MASK (0x3 << 21 ) +#define HDR_RD_BURST_LEN_SHIFT 21U + +#define HDR_WR_BURST_LEN +#define HDR_WR_BURST_LEN_MASK (0x3 << 19 ) +#define HDR_WR_BURST_LEN_SHIFT 19U + +#define HDR_RD_ID_EN +#define HDR_RD_ID_EN_MASK 0x1 << 18 +#define HDR_RD_ID_EN_SHIFT 18U + +#define HDR_RD_ID_CFG +#define HDR_RD_ID_CFG_MASK (0xff << 10 ) +#define HDR_RD_ID_CFG_SHIFT 10U + +#define HDR_WR_ID_EN +#define HDR_WR_ID_EN_MASK 0x1 << 8 +#define HDR_WR_ID_EN_SHIFT 8U + +#define HDR_WR_ID_CFG +#define HDR_WR_ID_CFG_MASK (0xff << 0 ) +#define HDR_WR_ID_CFG_SHIFT 0U + +#define HDR_BUS_TIMEO_EN +#define HDR_BUS_TIMEO_EN_MASK 0x1 << 31 +#define HDR_BUS_TIMEO_EN_SHIFT 31U + +#define HDR_BUS_TIMEO +#define HDR_BUS_TIMEO_MASK (0x7fffffff << 0 ) +#define HDR_BUS_TIMEO_SHIFT 0U + +#define HDR_L_PIC_WIDTH +#define HDR_L_PIC_WIDTH_MASK (0xffffffff << 0 ) +#define HDR_L_PIC_WIDTH_SHIFT 0U + +#define HDR_L_PIC_HEIGHT +#define HDR_L_PIC_HEIGHT_MASK (0xffffffff << 0 ) +#define HDR_L_PIC_HEIGHT_SHIFT 0U + +#define HDR_L_BASE_AD_INIT +#define HDR_L_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_L_BASE_AD_INIT_SHIFT 4U + +#define HDR_L_SIZE_INIT +#define HDR_L_SIZE_INIT_MASK (0x1ffffff << 4 ) +#define HDR_L_SIZE_INIT_SHIFT 4U + +#define HDR_L_OFFS_CNT_INIT +#define HDR_L_OFFS_CNT_INIT_MASK (0x1ffffff << 4 ) +#define HDR_L_OFFS_CNT_INIT_SHIFT 4U + +#define HDR_L_LLENGTH +#define HDR_L_LLENGTH_MASK (0xffffffff << 0 ) +#define HDR_L_LLENGTH_SHIFT 0U + +#define HDR_L_PIC_LVAL +#define HDR_L_PIC_LVAL_MASK (0xffff << 0 ) +#define HDR_L_PIC_LVAL_SHIFT 0U + +#define HDR_L_IRQ_OFFS_INIT +#define HDR_L_IRQ_OFFS_INIT_MASK (0xffffffff << 0 ) +#define HDR_L_IRQ_OFFS_INIT_SHIFT 0U + +#define HDR_L_OFFS_CNT_START +#define HDR_L_OFFS_CNT_START_MASK (0x1ffffff << 4 ) +#define HDR_L_OFFS_CNT_START_SHIFT 4U + +#define HDR_L_BASE_AD_SHD +#define HDR_L_BASE_AD_SHD_MASK (0xfffffff << 4 ) +#define HDR_L_BASE_AD_SHD_SHIFT 4U + +#define HDR_L_SIZE_SHD +#define HDR_L_SIZE_SHD_MASK (0x1ffffff << 4 ) +#define HDR_L_SIZE_SHD_SHIFT 4U + +#define HDR_L_OFFS_CNT +#define HDR_L_OFFS_CNT_MASK (0x1ffffff << 4 ) +#define HDR_L_OFFS_CNT_SHIFT 4U + +#define HDR_L_IRQ_OFFS_SHD +#define HDR_L_IRQ_OFFS_SHD_MASK (0xffffffff << 0 ) +#define HDR_L_IRQ_OFFS_SHD_SHIFT 0U + +#define HDR_S_BASE_AD_INIT +#define HDR_S_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_S_BASE_AD_INIT_SHIFT 4U + +#define HDR_S_SIZE_INIT +#define HDR_S_SIZE_INIT_MASK (0x1ffffff << 4 ) +#define HDR_S_SIZE_INIT_SHIFT 4U + +#define HDR_S_OFFS_CNT_INIT +#define HDR_S_OFFS_CNT_INIT_MASK (0x1ffffff << 4 ) +#define HDR_S_OFFS_CNT_INIT_SHIFT 4U + +#define HDR_S_LLENGTH +#define HDR_S_LLENGTH_MASK (0xffffffff << 0 ) +#define HDR_S_LLENGTH_SHIFT 0U + +#define HDR_S_PIC_LVAL +#define HDR_S_PIC_LVAL_MASK (0xffff << 0 ) +#define HDR_S_PIC_LVAL_SHIFT 0U + +#define HDR_S_IRQ_OFFS_INIT +#define HDR_S_IRQ_OFFS_INIT_MASK (0xffffffff << 0 ) +#define HDR_S_IRQ_OFFS_INIT_SHIFT 0U + +#define HDR_S_OFFS_CNT_START +#define HDR_S_OFFS_CNT_START_MASK (0x1ffffff << 4 ) +#define HDR_S_OFFS_CNT_START_SHIFT 4U + +#define HDR_S_BASE_AD_SHD +#define HDR_S_BASE_AD_SHD_MASK (0xfffffff << 4 ) +#define HDR_S_BASE_AD_SHD_SHIFT 4U + +#define HDR_S_SIZE_SHD +#define HDR_S_SIZE_SHD_MASK (0x1ffffff << 4 ) +#define HDR_S_SIZE_SHD_SHIFT 4U + +#define HDR_S_OFFS_CNT +#define HDR_S_OFFS_CNT_MASK (0x1ffffff << 4 ) +#define HDR_S_OFFS_CNT_SHIFT 4U + +#define HDR_S_IRQ_OFFS_SHD +#define HDR_S_IRQ_OFFS_SHD_MASK (0xffffffff << 0 ) +#define HDR_S_IRQ_OFFS_SHD_SHIFT 0U + +#define HDR_VS_BASE_AD_INIT +#define HDR_VS_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_VS_BASE_AD_INIT_SHIFT 4U + +#define HDR_VS_SIZE_INIT +#define HDR_VS_SIZE_INIT_MASK (0x1ffffff << 4 ) +#define HDR_VS_SIZE_INIT_SHIFT 4U + +#define HDR_VS_OFFS_CNT_INIT +#define HDR_VS_OFFS_CNT_INIT_MASK (0x1ffffff << 4 ) +#define HDR_VS_OFFS_CNT_INIT_SHIFT 4U + +#define HDR_VS_LLENGTH +#define HDR_VS_LLENGTH_MASK (0xffffffff << 0 ) +#define HDR_VS_LLENGTH_SHIFT 0U + +#define HDR_VS_PIC_LVAL +#define HDR_VS_PIC_LVAL_MASK (0xffff << 0 ) +#define HDR_VS_PIC_LVAL_SHIFT 0U + +#define HDR_VS_IRQ_OFFS_INIT +#define HDR_VS_IRQ_OFFS_INIT_MASK (0xffffffff << 0 ) +#define HDR_VS_IRQ_OFFS_INIT_SHIFT 0U + +#define HDR_VS_OFFS_CNT_START +#define HDR_VS_OFFS_CNT_START_MASK (0x1ffffff << 4 ) +#define HDR_VS_OFFS_CNT_START_SHIFT 4U + +#define HDR_VS_BASE_AD_SHD +#define HDR_VS_BASE_AD_SHD_MASK (0xfffffff << 4 ) +#define HDR_VS_BASE_AD_SHD_SHIFT 4U + +#define HDR_VS_SIZE_SHD +#define HDR_VS_SIZE_SHD_MASK (0x1ffffff << 4 ) +#define HDR_VS_SIZE_SHD_SHIFT 4U + +#define HDR_VS_OFFS_CNT +#define HDR_VS_OFFS_CNT_MASK (0x1ffffff << 4 ) +#define HDR_VS_OFFS_CNT_SHIFT 4U + +#define HDR_VS_IRQ_OFFS_SHD +#define HDR_VS_IRQ_OFFS_SHD_MASK (0xffffffff << 0 ) +#define HDR_VS_IRQ_OFFS_SHD_SHIFT 0U + +#define HDR_DMA_PIC_WIDTH +#define HDR_DMA_PIC_WIDTH_MASK (0x7fff << 0 ) +#define HDR_DMA_PIC_WIDTH_SHIFT 0U + +#define HDR_DMA_PIC_HEIGHT +#define HDR_DMA_PIC_HEIGHT_MASK (0x7fff << 0 ) +#define HDR_DMA_PIC_HEIGHT_SHIFT 0U + +#define HDR_DMA_L_BASE_AD_INIT +#define HDR_DMA_L_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_L_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_L_SIZE_INIT +#define HDR_DMA_L_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_L_SIZE_INIT_SHIFT 4U + +#define HDR_DMA_L_PIC_LLENGTH +#define HDR_DMA_L_PIC_LLENGTH_MASK (0xfffffff << 4 ) +#define HDR_DMA_L_PIC_LLENGTH_SHIFT 4U + +#define HDR_DMA_L_WIDTH_BYTES +#define HDR_DMA_L_WIDTH_BYTES_MASK (0xffff << 0 ) +#define HDR_DMA_L_WIDTH_BYTES_SHIFT 0U + +#define HDR_DMA_L_BASE_AD_INIT +#define HDR_DMA_L_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_L_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_L_SIZE_INIT +#define HDR_DMA_L_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_L_SIZE_INIT_SHIFT 4U + +#define HDR_DMA_S_BASE_AD_INIT +#define HDR_DMA_S_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_S_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_S_SIZE_INIT +#define HDR_DMA_S_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_S_SIZE_INIT_SHIFT 4U + +#define HDR_DMA_S_PIC_LLENGTH +#define HDR_DMA_S_PIC_LLENGTH_MASK (0xfffffff << 4 ) +#define HDR_DMA_S_PIC_LLENGTH_SHIFT 4U + +#define HDR_DMA_S_WIDTH_BYTES +#define HDR_DMA_S_WIDTH_BYTES_MASK (0xffff << 0 ) +#define HDR_DMA_S_WIDTH_BYTES_SHIFT 0U + +#define HDR_DMA_S_BASE_AD_INIT +#define HDR_DMA_S_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_S_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_S_SIZE_INIT +#define HDR_DMA_S_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_S_SIZE_INIT_SHIFT 4U + +#define HDR_DMA_VS_BASE_AD_INIT +#define HDR_DMA_VS_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_VS_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_VS_SIZE_INIT +#define HDR_DMA_VS_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_VS_SIZE_INIT_SHIFT 4U + +#define HDR_DMA_VS_PIC_LLENGTH +#define HDR_DMA_VS_PIC_LLENGTH_MASK (0xfffffff << 4 ) +#define HDR_DMA_VS_PIC_LLENGTH_SHIFT 4U + +#define HDR_DMA_VS_WIDTH_BYTES +#define HDR_DMA_VS_WIDTH_BYTES_MASK (0xffff << 0 ) +#define HDR_DMA_VS_WIDTH_BYTES_SHIFT 0U + +#define HDR_DMA_VS_BASE_AD_INIT +#define HDR_DMA_VS_BASE_AD_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_VS_BASE_AD_INIT_SHIFT 4U + +#define HDR_DMA_VS_SIZE_INIT +#define HDR_DMA_VS_SIZE_INIT_MASK (0xfffffff << 4 ) +#define HDR_DMA_VS_SIZE_INIT_SHIFT 4U + +#define HDR_RT_VSYNC_POL +#define HDR_RT_VSYNC_POL_MASK (0x1 << 8) +#define HDR_RT_VSYNC_POL_SHIFT 8U + +#define HDR_RT_HSYNC_POL +#define HDR_RT_HSYNC_POL_MASK (0x1 << 7) +#define HDR_RT_HSYNC_POL_SHIFT 7U + +#define HDR_RETIMING_ENABLE +#define HDR_RETIMING_ENABLE_MASK 0x1 << 6 +#define HDR_RETIMING_ENABLE_SHIFT 6U + +#define LONG_USE_DDR_ONLY_EN +#define LONG_USE_DDR_ONLY_EN_MASK 0x1 << 5 +#define LONG_USE_DDR_ONLY_EN_SHIFT 5U + +#define SHORT_USE_DDR_ONLY_EN +#define SHORT_USE_DDR_ONLY_EN_MASK 0x1 << 4 +#define SHORT_USE_DDR_ONLY_EN_SHIFT 4U + +#define DUMP_MODE_EN +#define DUMP_MODE_EN_MASK 0x1 << 3 +#define DUMP_MODE_EN_SHIFT 3U + +#define L_VS_COMBINING_ENABLE +#define L_VS_COMBINING_ENABLE_MASK 0x1 << 2 +#define L_VS_COMBINING_ENABLE_SHIFT 2U + +#define EXPOSURE_COUNT +#define EXPOSURE_COUNT_MASK (0x3 << 0 ) +#define EXPOSURE_COUNT_SHIFT 0U + +#define HDR_INTERVAL1 +#define HDR_INTERVAL1_MASK (0xffff << 16 ) +#define HDR_INTERVAL1_SHIFT 16U + +#define HDR_INTERVAL0 +#define HDR_INTERVAL0_MASK (0xffff << 0 ) +#define HDR_INTERVAL0_SHIFT 0U + +#define PART_TWO_ENABLE +#define PART_TWO_ENABLE_MASK 0x1 << 23 +#define PART_TWO_ENABLE_SHIFT 23U + +#define PART_ONE_ENABLE +#define PART_ONE_ENABLE_MASK 0x1 << 22 +#define PART_ONE_ENABLE_SHIFT 22U + +#define SOFT_RST_PRE_FILT +#define SOFT_RST_PRE_FILT_MASK 0x1 << 21 +#define SOFT_RST_PRE_FILT_SHIFT 21U + +#define DEMOSAIC_THRESHOLD +#define DEMOSAIC_THRESHOLD_MASK (0xff << 13 ) +#define DEMOSAIC_THRESHOLD_SHIFT 13U + +#define STAGE1_SELECT +#define STAGE1_SELECT_MASK (0xf << 9 ) +#define STAGE1_SELECT_SHIFT 9U + +#define OUT_RGB_BAYER_PATTERN +#define OUT_RGB_BAYER_PATTERN_MASK (0x3 << 7 ) +#define OUT_RGB_BAYER_PATTERN_SHIFT 7U + +#define RGBIR_BAYER_PATTERN +#define RGBIR_BAYER_PATTERN_MASK (0xf << 3 ) +#define RGBIR_BAYER_PATTERN_SHIFT 3U + +#define GREEN_FILT_ENABLE +#define GREEN_FILT_ENABLE_MASK 0x1 << 2 +#define GREEN_FILT_ENABLE_SHIFT 2U + +#define GREEN_FILT_MODE +#define GREEN_FILT_MODE_MASK 0x1 << 1 +#define GREEN_FILT_MODE_SHIFT 1U + +#define ISP_PRE_FILT_ENABLE +#define ISP_PRE_FILT_ENABLE_MASK 0x1 << 0 +#define ISP_PRE_FILT_ENABLE_SHIFT 0U + +#define ISP_PRE_FILT_BLS_A +#define ISP_PRE_FILT_BLS_A_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_BLS_A_SHIFT 0U + +#define ISP_PRE_FILT_BLS_B +#define ISP_PRE_FILT_BLS_B_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_BLS_B_SHIFT 0U + +#define ISP_PRE_FILT_BLS_C +#define ISP_PRE_FILT_BLS_C_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_BLS_C_SHIFT 0U + +#define ISP_PRE_FILT_BLS_D +#define ISP_PRE_FILT_BLS_D_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_BLS_D_SHIFT 0U + +#define ISP_PRE_FILT_GAIN_R +#define ISP_PRE_FILT_GAIN_R_MASK (0x3ff << 0 ) +#define ISP_PRE_FILT_GAIN_R_SHIFT 0U + +#define ISP_PRE_FILT_GAIN_G +#define ISP_PRE_FILT_GAIN_G_MASK (0x3ff << 0 ) +#define ISP_PRE_FILT_GAIN_G_SHIFT 0U + +#define ISP_PRE_FILT_GAIN_B +#define ISP_PRE_FILT_GAIN_B_MASK (0x3ff << 0 ) +#define ISP_PRE_FILT_GAIN_B_SHIFT 0U + +#define ISP_PRE_FILT_DPC_TH_MED_R +#define ISP_PRE_FILT_DPC_TH_MED_R_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_DPC_TH_MED_R_SHIFT 16U + +#define ISP_PRE_FILT_DPC_TH_AVG_R +#define ISP_PRE_FILT_DPC_TH_AVG_R_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_DPC_TH_AVG_R_SHIFT 0U + +#define ISP_PRE_FILT_DPC_TH_MED_G +#define ISP_PRE_FILT_DPC_TH_MED_G_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_DPC_TH_MED_G_SHIFT 16U + +#define ISP_PRE_FILT_DPC_TH_AVG_G +#define ISP_PRE_FILT_DPC_TH_AVG_G_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_DPC_TH_AVG_G_SHIFT 0U + +#define ISP_PRE_FILT_DPC_TH_MED_B +#define ISP_PRE_FILT_DPC_TH_MED_B_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_DPC_TH_MED_B_SHIFT 16U + +#define ISP_PRE_FILT_DPC_TH_AVG_B +#define ISP_PRE_FILT_DPC_TH_AVG_B_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_DPC_TH_AVG_B_SHIFT 0U + +#define ISP_PRE_FILT_DPC_TH_MED_IR +#define ISP_PRE_FILT_DPC_TH_MED_IR_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_DPC_TH_MED_IR_SHIFT 16U + +#define ISP_PRE_FILT_DPC_TH_AVG_IR +#define ISP_PRE_FILT_DPC_TH_AVG_IR_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_DPC_TH_AVG_IR_SHIFT 0U + +#define ISP_PRE_FILT_CC_00 +#define ISP_PRE_FILT_CC_00_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_00_SHIFT 16U + +#define ISP_PRE_FILT_CC_01 +#define ISP_PRE_FILT_CC_01_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_01_SHIFT 0U + +#define ISP_PRE_FILT_CC_02 +#define ISP_PRE_FILT_CC_02_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_02_SHIFT 16U + +#define ISP_PRE_FILT_CC_03 +#define ISP_PRE_FILT_CC_03_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_03_SHIFT 0U + +#define ISP_PRE_FILT_CC_10 +#define ISP_PRE_FILT_CC_10_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_10_SHIFT 16U + +#define ISP_PRE_FILT_CC_11 +#define ISP_PRE_FILT_CC_11_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_11_SHIFT 0U + +#define ISP_PRE_FILT_CC_12 +#define ISP_PRE_FILT_CC_12_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_12_SHIFT 16U + +#define ISP_PRE_FILT_CC_13 +#define ISP_PRE_FILT_CC_13_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_13_SHIFT 0U + +#define ISP_PRE_FILT_CC_20 +#define ISP_PRE_FILT_CC_20_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_20_SHIFT 16U + +#define ISP_PRE_FILT_CC_21 +#define ISP_PRE_FILT_CC_21_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_21_SHIFT 0U + +#define ISP_PRE_FILT_CC_22 +#define ISP_PRE_FILT_CC_22_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_22_SHIFT 16U + +#define ISP_PRE_FILT_CC_23 +#define ISP_PRE_FILT_CC_23_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_23_SHIFT 0U + +#define ISP_PRE_FILT_CC_00_SHD +#define ISP_PRE_FILT_CC_00_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_00_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_01_SHD +#define ISP_PRE_FILT_CC_01_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_01_SHD_SHIFT 0U + +#define ISP_PRE_FILT_CC_02_SHD +#define ISP_PRE_FILT_CC_02_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_02_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_03_SHD +#define ISP_PRE_FILT_CC_03_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_03_SHD_SHIFT 0U + +#define ISP_PRE_FILT_CC_10_SHD +#define ISP_PRE_FILT_CC_10_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_10_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_11_SHD +#define ISP_PRE_FILT_CC_11_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_11_SHD_SHIFT 0U + +#define ISP_PRE_FILT_CC_12_SHD +#define ISP_PRE_FILT_CC_12_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_12_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_13_SHD +#define ISP_PRE_FILT_CC_13_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_13_SHD_SHIFT 0U + +#define ISP_PRE_FILT_CC_20_SHD +#define ISP_PRE_FILT_CC_20_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_20_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_21_SHD +#define ISP_PRE_FILT_CC_21_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_21_SHD_SHIFT 0U + +#define ISP_PRE_FILT_CC_22_SHD +#define ISP_PRE_FILT_CC_22_SHD_MASK (0x7ff << 16 ) +#define ISP_PRE_FILT_CC_22_SHD_SHIFT 16U + +#define ISP_PRE_FILT_CC_23_SHD +#define ISP_PRE_FILT_CC_23_SHD_MASK (0x7ff << 0 ) +#define ISP_PRE_FILT_CC_23_SHD_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PX1 +#define ISP_PRE_FILT_IR_DES_PX1_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PX1_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY2 +#define ISP_PRE_FILT_IR_DES_PY2_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY2_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY1 +#define ISP_PRE_FILT_IR_DES_PY1_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY1_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY4 +#define ISP_PRE_FILT_IR_DES_PY4_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY4_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY3 +#define ISP_PRE_FILT_IR_DES_PY3_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY3_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY6 +#define ISP_PRE_FILT_IR_DES_PY6_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY6_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY5 +#define ISP_PRE_FILT_IR_DES_PY5_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY5_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY8 +#define ISP_PRE_FILT_IR_DES_PY8_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY8_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY7 +#define ISP_PRE_FILT_IR_DES_PY7_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY7_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY10 +#define ISP_PRE_FILT_IR_DES_PY10_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY10_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY9 +#define ISP_PRE_FILT_IR_DES_PY9_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY9_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY12 +#define ISP_PRE_FILT_IR_DES_PY12_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY12_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY11 +#define ISP_PRE_FILT_IR_DES_PY11_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY11_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY14 +#define ISP_PRE_FILT_IR_DES_PY14_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY14_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY13 +#define ISP_PRE_FILT_IR_DES_PY13_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY13_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PY16 +#define ISP_PRE_FILT_IR_DES_PY16_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_IR_DES_PY16_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PY15 +#define ISP_PRE_FILT_IR_DES_PY15_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_IR_DES_PY15_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PD4 +#define ISP_PRE_FILT_IR_DES_PD4_MASK (0xff << 24 ) +#define ISP_PRE_FILT_IR_DES_PD4_SHIFT 24U + +#define ISP_PRE_FILT_IR_DES_PD3 +#define ISP_PRE_FILT_IR_DES_PD3_MASK (0xff << 16 ) +#define ISP_PRE_FILT_IR_DES_PD3_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PD2 +#define ISP_PRE_FILT_IR_DES_PD2_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DES_PD2_SHIFT 8U + +#define ISP_PRE_FILT_IR_DES_PD1 +#define ISP_PRE_FILT_IR_DES_PD1_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DES_PD1_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PD8 +#define ISP_PRE_FILT_IR_DES_PD8_MASK (0xff << 24 ) +#define ISP_PRE_FILT_IR_DES_PD8_SHIFT 24U + +#define ISP_PRE_FILT_IR_DES_PD7 +#define ISP_PRE_FILT_IR_DES_PD7_MASK (0xff << 16 ) +#define ISP_PRE_FILT_IR_DES_PD7_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PD6 +#define ISP_PRE_FILT_IR_DES_PD6_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DES_PD6_SHIFT 8U + +#define ISP_PRE_FILT_IR_DES_PD5 +#define ISP_PRE_FILT_IR_DES_PD5_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DES_PD5_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PD12 +#define ISP_PRE_FILT_IR_DES_PD12_MASK (0xff << 24 ) +#define ISP_PRE_FILT_IR_DES_PD12_SHIFT 24U + +#define ISP_PRE_FILT_IR_DES_PD11 +#define ISP_PRE_FILT_IR_DES_PD11_MASK (0xff << 16 ) +#define ISP_PRE_FILT_IR_DES_PD11_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PD10 +#define ISP_PRE_FILT_IR_DES_PD10_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DES_PD10_SHIFT 8U + +#define ISP_PRE_FILT_IR_DES_PD9 +#define ISP_PRE_FILT_IR_DES_PD9_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DES_PD9_SHIFT 0U + +#define ISP_PRE_FILT_IR_DES_PD15 +#define ISP_PRE_FILT_IR_DES_PD15_MASK (0xff << 16 ) +#define ISP_PRE_FILT_IR_DES_PD15_SHIFT 16U + +#define ISP_PRE_FILT_IR_DES_PD14 +#define ISP_PRE_FILT_IR_DES_PD14_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DES_PD14_SHIFT 8U + +#define ISP_PRE_FILT_IR_DES_PD13 +#define ISP_PRE_FILT_IR_DES_PD13_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DES_PD13_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PX1 +#define ISP_PRE_FILT_L_DES_PX1_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PX1_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY2 +#define ISP_PRE_FILT_L_DES_PY2_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY2_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY1 +#define ISP_PRE_FILT_L_DES_PY1_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY1_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY4 +#define ISP_PRE_FILT_L_DES_PY4_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY4_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY3 +#define ISP_PRE_FILT_L_DES_PY3_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY3_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY6 +#define ISP_PRE_FILT_L_DES_PY6_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY6_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY5 +#define ISP_PRE_FILT_L_DES_PY5_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY5_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY8 +#define ISP_PRE_FILT_L_DES_PY8_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY8_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY7 +#define ISP_PRE_FILT_L_DES_PY7_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY7_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY10 +#define ISP_PRE_FILT_L_DES_PY10_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY10_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY9 +#define ISP_PRE_FILT_L_DES_PY9_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY9_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY12 +#define ISP_PRE_FILT_L_DES_PY12_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY12_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY11 +#define ISP_PRE_FILT_L_DES_PY11_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY11_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY14 +#define ISP_PRE_FILT_L_DES_PY14_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY14_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY13 +#define ISP_PRE_FILT_L_DES_PY13_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY13_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PY16 +#define ISP_PRE_FILT_L_DES_PY16_MASK (0xffff << 16 ) +#define ISP_PRE_FILT_L_DES_PY16_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PY15 +#define ISP_PRE_FILT_L_DES_PY15_MASK (0xffff << 0 ) +#define ISP_PRE_FILT_L_DES_PY15_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PD4 +#define ISP_PRE_FILT_L_DES_PD4_MASK (0xff << 24 ) +#define ISP_PRE_FILT_L_DES_PD4_SHIFT 24U + +#define ISP_PRE_FILT_L_DES_PD3 +#define ISP_PRE_FILT_L_DES_PD3_MASK (0xff << 16 ) +#define ISP_PRE_FILT_L_DES_PD3_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PD2 +#define ISP_PRE_FILT_L_DES_PD2_MASK (0xff << 8 ) +#define ISP_PRE_FILT_L_DES_PD2_SHIFT 8U + +#define ISP_PRE_FILT_L_DES_PD1 +#define ISP_PRE_FILT_L_DES_PD1_MASK (0xff << 0 ) +#define ISP_PRE_FILT_L_DES_PD1_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PD8 +#define ISP_PRE_FILT_L_DES_PD8_MASK (0xff << 24 ) +#define ISP_PRE_FILT_L_DES_PD8_SHIFT 24U + +#define ISP_PRE_FILT_L_DES_PD7 +#define ISP_PRE_FILT_L_DES_PD7_MASK (0xff << 16 ) +#define ISP_PRE_FILT_L_DES_PD7_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PD6 +#define ISP_PRE_FILT_L_DES_PD6_MASK (0xff << 8 ) +#define ISP_PRE_FILT_L_DES_PD6_SHIFT 8U + +#define ISP_PRE_FILT_L_DES_PD5 +#define ISP_PRE_FILT_L_DES_PD5_MASK (0xff << 0 ) +#define ISP_PRE_FILT_L_DES_PD5_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PD12 +#define ISP_PRE_FILT_L_DES_PD12_MASK (0xff << 24 ) +#define ISP_PRE_FILT_L_DES_PD12_SHIFT 24U + +#define ISP_PRE_FILT_L_DES_PD11 +#define ISP_PRE_FILT_L_DES_PD11_MASK (0xff << 16 ) +#define ISP_PRE_FILT_L_DES_PD11_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PD10 +#define ISP_PRE_FILT_L_DES_PD10_MASK (0xff << 8 ) +#define ISP_PRE_FILT_L_DES_PD10_SHIFT 8U + +#define ISP_PRE_FILT_L_DES_PD9 +#define ISP_PRE_FILT_L_DES_PD9_MASK (0xff << 0 ) +#define ISP_PRE_FILT_L_DES_PD9_SHIFT 0U + +#define ISP_PRE_FILT_L_DES_PD15 +#define ISP_PRE_FILT_L_DES_PD15_MASK (0xff << 16 ) +#define ISP_PRE_FILT_L_DES_PD15_SHIFT 16U + +#define ISP_PRE_FILT_L_DES_PD14 +#define ISP_PRE_FILT_L_DES_PD14_MASK (0xff << 8 ) +#define ISP_PRE_FILT_L_DES_PD14_SHIFT 8U + +#define ISP_PRE_FILT_L_DES_PD13 +#define ISP_PRE_FILT_L_DES_PD13_MASK (0xff << 0 ) +#define ISP_PRE_FILT_L_DES_PD13_SHIFT 0U + +#define PREFILT_THRESH_BL0 +#define PREFILT_THRESH_BL0_MASK (0x3ff << 0 ) +#define PREFILT_THRESH_BL0_SHIFT 0U + +#define PREFILT_THRESH_BL1 +#define PREFILT_THRESH_BL1_MASK (0x3ff << 0 ) +#define PREFILT_THRESH_BL1_SHIFT 0U + +#define PREFILT_THRESH_SH0 +#define PREFILT_THRESH_SH0_MASK (0x3ff << 0 ) +#define PREFILT_THRESH_SH0_SHIFT 0U + +#define PREFILT_THRESH_SH1 +#define PREFILT_THRESH_SH1_MASK (0x3ff << 0 ) +#define PREFILT_THRESH_SH1_SHIFT 0U + +#define LUM_WEIGHT_GAIN +#define LUM_WEIGHT_GAIN_MASK (0x7 << 16 ) +#define LUM_WEIGHT_GAIN_SHIFT 16U + +#define LUM_WEIGHT_KINK +#define LUM_WEIGHT_KINK_MASK (0xff << 8 ) +#define LUM_WEIGHT_KINK_SHIFT 8U + +#define LUM_WEIGHT_MIN +#define LUM_WEIGHT_MIN_MASK (0xff << 0 ) +#define LUM_WEIGHT_MIN_SHIFT 0U + +#define PREFILT_FAC_SH1 +#define PREFILT_FAC_SH1_MASK (0x3f << 0 ) +#define PREFILT_FAC_SH1_SHIFT 0U + +#define PREFILT_FAC_SH0 +#define PREFILT_FAC_SH0_MASK (0x3f << 0 ) +#define PREFILT_FAC_SH0_SHIFT 0U + +#define PREFILT_FAC_MID +#define PREFILT_FAC_MID_MASK (0x3f << 0 ) +#define PREFILT_FAC_MID_SHIFT 0U + +#define PREFILT_FAC_BL0 +#define PREFILT_FAC_BL0_MASK (0x3f << 0 ) +#define PREFILT_FAC_BL0_SHIFT 0U + +#define PREFILT_FAC_BL1 +#define PREFILT_FAC_BL1_MASK (0x3f << 0 ) +#define PREFILT_FAC_BL1_SHIFT 0U + +#define ISP_PRE_FILT_IR_DENOISE_SW3 +#define ISP_PRE_FILT_IR_DENOISE_SW3_MASK (0xff << 24 ) +#define ISP_PRE_FILT_IR_DENOISE_SW3_SHIFT 24U + +#define ISP_PRE_FILT_IR_DENOISE_SW2 +#define ISP_PRE_FILT_IR_DENOISE_SW2_MASK (0xff << 16 ) +#define ISP_PRE_FILT_IR_DENOISE_SW2_SHIFT 16U + +#define ISP_PRE_FILT_IR_DENOISE_SW1 +#define ISP_PRE_FILT_IR_DENOISE_SW1_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DENOISE_SW1_SHIFT 8U + +#define ISP_PRE_FILT_IR_DENOISE_SW0 +#define ISP_PRE_FILT_IR_DENOISE_SW0_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DENOISE_SW0_SHIFT 0U + +#define ISP_PRE_FILT_IR_DENOISE_SW5 +#define ISP_PRE_FILT_IR_DENOISE_SW5_MASK (0xff << 8 ) +#define ISP_PRE_FILT_IR_DENOISE_SW5_SHIFT 8U + +#define ISP_PRE_FILT_IR_DENOISE_SW4 +#define ISP_PRE_FILT_IR_DENOISE_SW4_MASK (0xff << 0 ) +#define ISP_PRE_FILT_IR_DENOISE_SW4_SHIFT 0U + +#define PRE_FILT_H_SIZE +#define PRE_FILT_H_SIZE_MASK (0x7fff << 0 ) +#define PRE_FILT_H_SIZE_SHIFT 0U + +#define PRE_FILT_V_SIZE +#define PRE_FILT_V_SIZE_MASK (0x3fff << 0 ) +#define PRE_FILT_V_SIZE_SHIFT 0U + +#define PRE_FILT_DMY_HB +#define PRE_FILT_DMY_HB_MASK (0x1fff << 0 ) +#define PRE_FILT_DMY_HB_SHIFT 0U + + +#define SP2_DMA_RAW_WIDTH_BYTES +#define SP2_DMA_RAW_WIDTH_BYTES_MASK (0xffff << 0 ) +#define SP2_DMA_RAW_WIDTH_BYTES_SHIFT 0U + +#define PPW_Y_BUF_FULL +#define PPW_Y_BUF_FULL_MASK (0x1 << 26) +#define PPW_Y_BUF_FULL_SHIFT 26U + +#define PPW_U_BUF_FULL +#define PPW_U_BUF_FULL_MASK (0x1 << 25) +#define PPW_U_BUF_FULL_SHIFT 25U + +#define PPW_V_BUF_FULL +#define PPW_V_BUF_FULL_MASK (0x1 << 24) +#define PPW_V_BUF_FULL_SHIFT 24U + +#define PPR_Y_BUF_FULL +#define PPR_Y_BUF_FULL_MASK (0x1 << 23) +#define PPR_Y_BUF_FULL_SHIFT 23U + +#define SP2_RAW2_W_BUF_FULL +#define SP2_RAW2_W_BUF_FULL_MASK (0x1 << 22) +#define SP2_RAW2_W_BUF_FULL_SHIFT 22U + +#define SP2_RAW2_R_BUF_FULL +#define SP2_RAW2_R_BUF_FULL_MASK (0x1 << 21) +#define SP2_RAW2_R_BUF_FULL_SHIFT 21U + +#define HDR_W_BUF_FULL +#define HDR_W_BUF_FULL_MASK (0x1 << 20) +#define HDR_W_BUF_FULL_SHIFT 20U + +#define HDR_R_BUF_FULL +#define HDR_R_BUF_FULL_MASK (0x1 << 19) +#define HDR_R_BUF_FULL_SHIFT 19U + +#define SP2_RAW2_DMA_READY +#define SP2_RAW2_DMA_READY_MASK (0x1 << 18) +#define SP2_RAW2_DMA_READY_SHIFT 18U + +#define PPR_DMA_READY +#define PPR_DMA_READY_MASK (0x1 << 17) +#define PPR_DMA_READY_SHIFT 17U + +#define WRAP_PPW_CR +#define WRAP_PPW_CR_MASK (0x1 << 15) +#define WRAP_PPW_CR_SHIFT 15U + +#define WRAP_PPW_CB +#define WRAP_PPW_CB_MASK (0x1 << 14) +#define WRAP_PPW_CB_SHIFT 14U + +#define WRAP_PPW_Y +#define WRAP_PPW_Y_MASK (0x1 << 13) +#define WRAP_PPW_Y_SHIFT 13U + +#define SP2_RAW2_FRAME_END +#define SP2_RAW2_FRAME_END_MASK (0x1 << 12) +#define SP2_RAW2_FRAME_END_SHIFT 12U + +#define PPW_FRAME_END +#define PPW_FRAME_END_MASK (0x1 << 11) +#define PPW_FRAME_END_SHIFT 11U + +#define HDR_VS_DMA_READY +#define HDR_VS_DMA_READY_MASK (0x1 << 10) +#define HDR_VS_DMA_READY_SHIFT 10U + +#define HDR_S_DMA_READY +#define HDR_S_DMA_READY_MASK (0x1 << 9) +#define HDR_S_DMA_READY_SHIFT 9U + +#define HDR_L_DMA_READY +#define HDR_L_DMA_READY_MASK (0x1 << 8) +#define HDR_L_DMA_READY_SHIFT 8U + +#define WRAP_HDR_VS +#define WRAP_HDR_VS_MASK (0x1 << 7) +#define WRAP_HDR_VS_SHIFT 7U + +#define WRAP_HDR_S +#define WRAP_HDR_S_MASK (0x1 << 6) +#define WRAP_HDR_S_SHIFT 6U + +#define WRAP_HDR_L +#define WRAP_HDR_L_MASK (0x1 << 5) +#define WRAP_HDR_L_SHIFT 5U + +#define HDR_VS_FRAME_END +#define HDR_VS_FRAME_END_MASK (0x1 << 4) +#define HDR_VS_FRAME_END_SHIFT 4U + +#define HDR_S_FRAME_END +#define HDR_S_FRAME_END_MASK (0x1 << 3) +#define HDR_S_FRAME_END_SHIFT 3U + +#define HDR_L_FRAME_END +#define HDR_L_FRAME_END_MASK (0x1 << 2) +#define HDR_L_FRAME_END_SHIFT 2U + +#define MI_RT_BUS_BUSERR +#define MI_RT_BUS_BUSERR_MASK (0x1 << 1) +#define MI_RT_BUS_BUSERR_SHIFT 1U + +#define MI_RT_BUS_TIMEO +#define MI_RT_BUS_TIMEO_MASK (0x1 << 0) +#define MI_RT_BUS_TIMEO_SHIFT 0U + +#endif /* _MRV_ALL_REGS_H */ diff --git a/vvcam_ry/isp/mrv_dec_all_regs.h b/vvcam_ry/isp/mrv_dec_all_regs.h new file mode 100755 index 0000000..c4b6fcf --- /dev/null +++ b/vvcam_ry/isp/mrv_dec_all_regs.h @@ -0,0 +1,1148 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +/** +*----------------------------------------------------------------------------- +* $HeadURL$ +* $Author$ +* $Rev$ +* $Date$ +*----------------------------------------------------------------------------- +* @file mrv_dec_all_regs.h +* +* 
+*
+* Description:
+*   This header file exports the module register structure and masks.
+*   it should not be included directly by your driver/application, it will be
+*   exported by the _regs_io.h header file.
+*
+*
+*/ +/*****************************************************************************/ + +#ifndef _MRV_DEC_ALL_REGS_H +#define _MRV_DEC_ALL_REGS_H + +/*! Mrv Dec All Register layout */ +typedef struct { + uint32_t _notused_0[(0x24 - 0x00) / 4]; + uint32_t isp_dec_chipRev; /*!<(r) */ + uint32_t isp_dec_chipDate; /*!<(r) */ + uint32_t _notused_1[(0x98 - 0x2c) / 4]; + uint32_t isp_dec_hichipPatchRev; /*!<(r) */ + uint32_t _notused_2[(0xA8 - 0x9c) / 4]; + uint32_t isp_dec_productId; /*!<(r) */ + + uint32_t _notused_3[(0x800 - 0xAc) / 4]; + uint32_t isp_dec_ctrl; /*!<(rw), DEC_BASE + 0x00000000 */ + uint32_t isp_dec_ctrl_ex; /*!<(rw), DEC_BASE + 0x00000004 */ + uint32_t isp_dec_ctrl_ex2; /*!<(rw), DEC_BASE + 0x00000008 */ + uint32_t isp_dec_intr_enbl; /*!<(rw), DEC_BASE + 0x0000000C */ + uint32_t isp_dec_intr_enbl_ex; /*!<(rw), DEC_BASE + 0x00000010 */ + uint32_t isp_dec_intr_enbl_ex2; /*!<(rw), DEC_BASE + 0x00000014 */ + uint32_t isp_dec_intr_acknowledge; /*!<(ro), DEC_BASE + 0x00000018 */ + uint32_t isp_dec_intr_acknowledge_ex; /*!<(ro), DEC_BASE + 0x0000001C */ + uint32_t isp_dec_intr_acknowledge_ex2; /*!<(ro), DEC_BASE + 0x00000020 */ + uint32_t isp_dec_tile_status_debug; /*!<(ro), DEC_BASE + 0x00000024 */ + uint32_t isp_dec_encoder_debug; /*!<(ro), DEC_BASE + 0x00000028 */ + uint32_t isp_dec_decoder_debug; /*!<(ro), DEC_BASE + 0x0000002C */ + uint32_t isp_dec_total_reads_in; /*!<(ro), DEC_BASE + 0x00000030 */ + uint32_t isp_dec_total_writes_in; /*!<(ro), DEC_BASE + 0x00000034 */ + uint32_t isp_dec_total_read_bursts_in; /*!<(ro), DEC_BASE + 0x00000038 */ + uint32_t isp_dec_total_write_bursts_in; /*!<(ro), DEC_BASE + 0x0000003C */ + uint32_t isp_dec_total_read_reqs_in; /*!<(ro), DEC_BASE + 0x00000040 */ + uint32_t isp_dec_total_write_reqs_in; /*!<(ro), DEC_BASE + 0x00000044 */ + uint32_t isp_dec_total_read_lasts_in; /*!<(ro), DEC_BASE + 0x00000048 */ + uint32_t isp_dec_total_write_lasts_in; /*!<(ro), DEC_BASE + 0x0000004C */ + uint32_t isp_dec_total_write_response_in; /*!<(ro), DEC_BASE + 0x00000050 */ + uint32_t isp_dec_total_reads_out; /*!<(ro), DEC_BASE + 0x00000054 */ + uint32_t isp_dec_total_writes_out; /*!<(ro), DEC_BASE + 0x00000058 */ + uint32_t isp_dec_total_read_bursts_out; /*!<(ro), DEC_BASE + 0x0000005C */ + uint32_t isp_dec_total_write_bursts_out; /*!<(ro), DEC_BASE + 0x00000060 */ + uint32_t isp_dec_total_read_reqs_out; /*!<(ro), DEC_BASE + 0x00000064 */ + uint32_t isp_dec_total_write_reqs_out; /*!<(ro), DEC_BASE + 0x00000068 */ + uint32_t isp_dec_total_read_lasts_out; /*!<(ro), DEC_BASE + 0x0000006C */ + uint32_t isp_dec_total_write_lasts_out; /*!<(ro), DEC_BASE + 0x00000070 */ + uint32_t isp_dec_total_write_response_out; /*!<(ro), DEC_BASE + 0x00000074 */ + uint32_t isp_dec_status; /*!<(ro), DEC_BASE + 0x00000078 */ + uint32_t isp_dec_debug_info_select; /*!<(rw), DEC_BASE + 0x0000007C */ + uint32_t isp_dec_read_config_0; /*!<(rw), DEC_BASE + 0x00000080 */ + uint32_t isp_dec_read_config_1; /*!<(rw), DEC_BASE + 0x00000084 */ + uint32_t isp_dec_read_config_2; /*!<(rw), DEC_BASE + 0x00000088 */ + uint32_t isp_dec_read_config_3; /*!<(rw), DEC_BASE + 0x0000008C */ + uint32_t isp_dec_read_config_4; /*!<(rw), DEC_BASE + 0x00000090 */ + uint32_t isp_dec_read_config_5; /*!<(rw), DEC_BASE + 0x00000094 */ + uint32_t isp_dec_read_config_6; /*!<(rw), DEC_BASE + 0x00000098 */ + uint32_t isp_dec_read_config_7; /*!<(rw), DEC_BASE + 0x0000009C */ + uint32_t isp_dec_read_config_8; /*!<(rw), DEC_BASE + 0x000000A0 */ + uint32_t isp_dec_read_config_9; /*!<(rw), DEC_BASE + 0x000000A4 */ + uint32_t isp_dec_read_config_10; /*!<(rw), DEC_BASE + 0x000000A8 */ + uint32_t isp_dec_read_config_11; /*!<(rw), DEC_BASE + 0x000000AC */ + uint32_t isp_dec_read_config_12; /*!<(rw), DEC_BASE + 0x000000B0 */ + uint32_t isp_dec_read_config_13; /*!<(rw), DEC_BASE + 0x000000B4 */ + uint32_t isp_dec_read_config_14; /*!<(rw), DEC_BASE + 0x000000B8 */ + uint32_t isp_dec_read_config_15; /*!<(rw), DEC_BASE + 0x000000BC */ + uint32_t isp_dec_read_config_16; /*!<(rw), DEC_BASE + 0x000000C0 */ + uint32_t isp_dec_read_config_17; /*!<(rw), DEC_BASE + 0x000000C4 */ + uint32_t isp_dec_read_config_18; /*!<(rw), DEC_BASE + 0x000000C8 */ + uint32_t isp_dec_read_config_19; /*!<(rw), DEC_BASE + 0x000000CC */ + uint32_t isp_dec_read_config_20; /*!<(rw), DEC_BASE + 0x000000D0 */ + uint32_t isp_dec_read_config_21; /*!<(rw), DEC_BASE + 0x000000D4 */ + uint32_t isp_dec_read_config_22; /*!<(rw), DEC_BASE + 0x000000D8 */ + uint32_t isp_dec_read_config_23; /*!<(rw), DEC_BASE + 0x000000DC */ + uint32_t isp_dec_read_config_24; /*!<(rw), DEC_BASE + 0x000000E0 */ + uint32_t isp_dec_read_config_25; /*!<(rw), DEC_BASE + 0x000000E4 */ + uint32_t isp_dec_read_config_26; /*!<(rw), DEC_BASE + 0x000000E8 */ + uint32_t isp_dec_read_config_27; /*!<(rw), DEC_BASE + 0x000000EC */ + uint32_t isp_dec_read_config_28; /*!<(rw), DEC_BASE + 0x000000F0 */ + uint32_t isp_dec_read_config_29; /*!<(rw), DEC_BASE + 0x000000F4 */ + uint32_t isp_dec_read_config_30; /*!<(rw), DEC_BASE + 0x000000F8 */ + uint32_t isp_dec_read_config_31; /*!<(rw), DEC_BASE + 0x000000FC */ + uint32_t isp_dec_read_ex_config_0; /*!<(rw), DEC_BASE + 0x00000100 */ + uint32_t isp_dec_read_ex_config_1; /*!<(rw), DEC_BASE + 0x00000104 */ + uint32_t isp_dec_read_ex_config_2; /*!<(rw), DEC_BASE + 0x00000108 */ + uint32_t isp_dec_read_ex_config_3; /*!<(rw), DEC_BASE + 0x0000010C */ + uint32_t isp_dec_read_ex_config_4; /*!<(rw), DEC_BASE + 0x00000110 */ + uint32_t isp_dec_read_ex_config_5; /*!<(rw), DEC_BASE + 0x00000114 */ + uint32_t isp_dec_read_ex_config_6; /*!<(rw), DEC_BASE + 0x00000118 */ + uint32_t isp_dec_read_ex_config_7; /*!<(rw), DEC_BASE + 0x0000011C */ + uint32_t isp_dec_read_ex_config_8; /*!<(rw), DEC_BASE + 0x00000120 */ + uint32_t isp_dec_read_ex_config_9; /*!<(rw), DEC_BASE + 0x00000124 */ + uint32_t isp_dec_read_ex_config_10; /*!<(rw), DEC_BASE + 0x00000128 */ + uint32_t isp_dec_read_ex_config_11; /*!<(rw), DEC_BASE + 0x0000012C */ + uint32_t isp_dec_read_ex_config_12; /*!<(rw), DEC_BASE + 0x00000130 */ + uint32_t isp_dec_read_ex_config_13; /*!<(rw), DEC_BASE + 0x00000134 */ + uint32_t isp_dec_read_ex_config_14; /*!<(rw), DEC_BASE + 0x00000138 */ + uint32_t isp_dec_read_ex_config_15; /*!<(rw), DEC_BASE + 0x0000013C */ + uint32_t isp_dec_read_ex_config_16; /*!<(rw), DEC_BASE + 0x00000140 */ + uint32_t isp_dec_read_ex_config_17; /*!<(rw), DEC_BASE + 0x00000144 */ + uint32_t isp_dec_read_ex_config_18; /*!<(rw), DEC_BASE + 0x00000148 */ + uint32_t isp_dec_read_ex_config_19; /*!<(rw), DEC_BASE + 0x0000014C */ + uint32_t isp_dec_read_ex_config_20; /*!<(rw), DEC_BASE + 0x00000150 */ + uint32_t isp_dec_read_ex_config_21; /*!<(rw), DEC_BASE + 0x00000154 */ + uint32_t isp_dec_read_ex_config_22; /*!<(rw), DEC_BASE + 0x00000158 */ + uint32_t isp_dec_read_ex_config_23; /*!<(rw), DEC_BASE + 0x0000015C */ + uint32_t isp_dec_read_ex_config_24; /*!<(rw), DEC_BASE + 0x00000160 */ + uint32_t isp_dec_read_ex_config_25; /*!<(rw), DEC_BASE + 0x00000164 */ + uint32_t isp_dec_read_ex_config_26; /*!<(rw), DEC_BASE + 0x00000168 */ + uint32_t isp_dec_read_ex_config_27; /*!<(rw), DEC_BASE + 0x0000016C */ + uint32_t isp_dec_read_ex_config_28; /*!<(rw), DEC_BASE + 0x00000170 */ + uint32_t isp_dec_read_ex_config_29; /*!<(rw), DEC_BASE + 0x00000174 */ + uint32_t isp_dec_read_ex_config_30; /*!<(rw), DEC_BASE + 0x00000178 */ + uint32_t isp_dec_read_ex_config_31; /*!<(rw), DEC_BASE + 0x0000017C */ + uint32_t isp_dec_write_config_0; /*!<(rw), DEC_BASE + 0x00000180 */ + uint32_t isp_dec_write_config_1; /*!<(rw), DEC_BASE + 0x00000184 */ + uint32_t isp_dec_write_config_2; /*!<(rw), DEC_BASE + 0x00000188 */ + uint32_t isp_dec_write_config_3; /*!<(rw), DEC_BASE + 0x0000018C */ + uint32_t isp_dec_write_config_4; /*!<(rw), DEC_BASE + 0x00000190 */ + uint32_t isp_dec_write_config_5; /*!<(rw), DEC_BASE + 0x00000194 */ + uint32_t isp_dec_write_config_6; /*!<(rw), DEC_BASE + 0x00000198 */ + uint32_t isp_dec_write_config_7; /*!<(rw), DEC_BASE + 0x0000019C */ + uint32_t isp_dec_write_config_8; /*!<(rw), DEC_BASE + 0x000001A0 */ + uint32_t isp_dec_write_config_9; /*!<(rw), DEC_BASE + 0x000001A4 */ + uint32_t isp_dec_write_config_10; /*!<(rw), DEC_BASE + 0x000001A8 */ + uint32_t isp_dec_write_config_11; /*!<(rw), DEC_BASE + 0x000001AC */ + uint32_t isp_dec_write_config_12; /*!<(rw), DEC_BASE + 0x000001B0 */ + uint32_t isp_dec_write_config_13; /*!<(rw), DEC_BASE + 0x000001B4 */ + uint32_t isp_dec_write_config_14; /*!<(rw), DEC_BASE + 0x000001B8 */ + uint32_t isp_dec_write_config_15; /*!<(rw), DEC_BASE + 0x000001BC */ + uint32_t isp_dec_write_config_16; /*!<(rw), DEC_BASE + 0x000001C0 */ + uint32_t isp_dec_write_config_17; /*!<(rw), DEC_BASE + 0x000001C4 */ + uint32_t isp_dec_write_config_18; /*!<(rw), DEC_BASE + 0x000001C8 */ + uint32_t isp_dec_write_config_19; /*!<(rw), DEC_BASE + 0x000001CC */ + uint32_t isp_dec_write_config_20; /*!<(rw), DEC_BASE + 0x000001D0 */ + uint32_t isp_dec_write_config_21; /*!<(rw), DEC_BASE + 0x000001D4 */ + uint32_t isp_dec_write_config_22; /*!<(rw), DEC_BASE + 0x000001D8 */ + uint32_t isp_dec_write_config_23; /*!<(rw), DEC_BASE + 0x000001DC */ + uint32_t isp_dec_write_config_24; /*!<(rw), DEC_BASE + 0x000001E0 */ + uint32_t isp_dec_write_config_25; /*!<(rw), DEC_BASE + 0x000001E4 */ + uint32_t isp_dec_write_config_26; /*!<(rw), DEC_BASE + 0x000001E8 */ + uint32_t isp_dec_write_config_27; /*!<(rw), DEC_BASE + 0x000001EC */ + uint32_t isp_dec_write_config_28; /*!<(rw), DEC_BASE + 0x000001F0 */ + uint32_t isp_dec_write_config_29; /*!<(rw), DEC_BASE + 0x000001F4 */ + uint32_t isp_dec_write_config_30; /*!<(rw), DEC_BASE + 0x000001F8 */ + uint32_t isp_dec_write_config_31; /*!<(rw), DEC_BASE + 0x000001FC */ + uint32_t isp_dec_write_ex_config_0; /*!<(rw), DEC_BASE + 0x00000200 */ + uint32_t isp_dec_write_ex_config_1; /*!<(rw), DEC_BASE + 0x00000204 */ + uint32_t isp_dec_write_ex_config_2; /*!<(rw), DEC_BASE + 0x00000208 */ + uint32_t isp_dec_write_ex_config_3; /*!<(rw), DEC_BASE + 0x0000020C */ + uint32_t isp_dec_write_ex_config_4; /*!<(rw), DEC_BASE + 0x00000210 */ + uint32_t isp_dec_write_ex_config_5; /*!<(rw), DEC_BASE + 0x00000214 */ + uint32_t isp_dec_write_ex_config_6; /*!<(rw), DEC_BASE + 0x00000218 */ + uint32_t isp_dec_write_ex_config_7; /*!<(rw), DEC_BASE + 0x0000021C */ + uint32_t isp_dec_write_ex_config_8; /*!<(rw), DEC_BASE + 0x00000220 */ + uint32_t isp_dec_write_ex_config_9; /*!<(rw), DEC_BASE + 0x00000224 */ + uint32_t isp_dec_write_ex_config_10; /*!<(rw), DEC_BASE + 0x00000228 */ + uint32_t isp_dec_write_ex_config_11; /*!<(rw), DEC_BASE + 0x0000022C */ + uint32_t isp_dec_write_ex_config_12; /*!<(rw), DEC_BASE + 0x00000230 */ + uint32_t isp_dec_write_ex_config_13; /*!<(rw), DEC_BASE + 0x00000234 */ + uint32_t isp_dec_write_ex_config_14; /*!<(rw), DEC_BASE + 0x00000238 */ + uint32_t isp_dec_write_ex_config_15; /*!<(rw), DEC_BASE + 0x0000023C */ + uint32_t isp_dec_write_ex_config_16; /*!<(rw), DEC_BASE + 0x00000240 */ + uint32_t isp_dec_write_ex_config_17; /*!<(rw), DEC_BASE + 0x00000244 */ + uint32_t isp_dec_write_ex_config_18; /*!<(rw), DEC_BASE + 0x00000248 */ + uint32_t isp_dec_write_ex_config_19; /*!<(rw), DEC_BASE + 0x0000024C */ + uint32_t isp_dec_write_ex_config_20; /*!<(rw), DEC_BASE + 0x00000250 */ + uint32_t isp_dec_write_ex_config_21; /*!<(rw), DEC_BASE + 0x00000254 */ + uint32_t isp_dec_write_ex_config_22; /*!<(rw), DEC_BASE + 0x00000258 */ + uint32_t isp_dec_write_ex_config_23; /*!<(rw), DEC_BASE + 0x0000025C */ + uint32_t isp_dec_write_ex_config_24; /*!<(rw), DEC_BASE + 0x00000260 */ + uint32_t isp_dec_write_ex_config_25; /*!<(rw), DEC_BASE + 0x00000264 */ + uint32_t isp_dec_write_ex_config_26; /*!<(rw), DEC_BASE + 0x00000268 */ + uint32_t isp_dec_write_ex_config_27; /*!<(rw), DEC_BASE + 0x0000026C */ + uint32_t isp_dec_write_ex_config_28; /*!<(rw), DEC_BASE + 0x00000270 */ + uint32_t isp_dec_write_ex_config_29; /*!<(rw), DEC_BASE + 0x00000274 */ + uint32_t isp_dec_write_ex_config_30; /*!<(rw), DEC_BASE + 0x00000278 */ + uint32_t isp_dec_write_ex_config_31; /*!<(rw), DEC_BASE + 0x0000027C */ + uint32_t isp_dec_read_buffer_base_0; /*!<(rw), DEC_BASE + 0x00000280 */ + uint32_t isp_dec_read_buffer_base_1; /*!<(rw), DEC_BASE + 0x00000284 */ + uint32_t isp_dec_read_buffer_base_2; /*!<(rw), DEC_BASE + 0x00000288 */ + uint32_t isp_dec_read_buffer_base_3; /*!<(rw), DEC_BASE + 0x0000028C */ + uint32_t isp_dec_read_buffer_base_4; /*!<(rw), DEC_BASE + 0x00000290 */ + uint32_t isp_dec_read_buffer_base_5; /*!<(rw), DEC_BASE + 0x00000294 */ + uint32_t isp_dec_read_buffer_base_6; /*!<(rw), DEC_BASE + 0x00000298 */ + uint32_t isp_dec_read_buffer_base_7; /*!<(rw), DEC_BASE + 0x0000029C */ + uint32_t isp_dec_read_buffer_base_8; /*!<(rw), DEC_BASE + 0x000002A0 */ + uint32_t isp_dec_read_buffer_base_9; /*!<(rw), DEC_BASE + 0x000002A4 */ + uint32_t isp_dec_read_buffer_base_10; /*!<(rw), DEC_BASE + 0x000002A8 */ + uint32_t isp_dec_read_buffer_base_11; /*!<(rw), DEC_BASE + 0x000002AC */ + uint32_t isp_dec_read_buffer_base_12; /*!<(rw), DEC_BASE + 0x000002B0 */ + uint32_t isp_dec_read_buffer_base_13; /*!<(rw), DEC_BASE + 0x000002B4 */ + uint32_t isp_dec_read_buffer_base_14; /*!<(rw), DEC_BASE + 0x000002B8 */ + uint32_t isp_dec_read_buffer_base_15; /*!<(rw), DEC_BASE + 0x000002BC */ + uint32_t isp_dec_read_buffer_base_16; /*!<(rw), DEC_BASE + 0x000002C0 */ + uint32_t isp_dec_read_buffer_base_17; /*!<(rw), DEC_BASE + 0x000002C4 */ + uint32_t isp_dec_read_buffer_base_18; /*!<(rw), DEC_BASE + 0x000002C8 */ + uint32_t isp_dec_read_buffer_base_19; /*!<(rw), DEC_BASE + 0x000002CC */ + uint32_t isp_dec_read_buffer_base_20; /*!<(rw), DEC_BASE + 0x000002D0 */ + uint32_t isp_dec_read_buffer_base_21; /*!<(rw), DEC_BASE + 0x000002D4 */ + uint32_t isp_dec_read_buffer_base_22; /*!<(rw), DEC_BASE + 0x000002D8 */ + uint32_t isp_dec_read_buffer_base_23; /*!<(rw), DEC_BASE + 0x000002DC */ + uint32_t isp_dec_read_buffer_base_24; /*!<(rw), DEC_BASE + 0x000002E0 */ + uint32_t isp_dec_read_buffer_base_25; /*!<(rw), DEC_BASE + 0x000002E4 */ + uint32_t isp_dec_read_buffer_base_26; /*!<(rw), DEC_BASE + 0x000002E8 */ + uint32_t isp_dec_read_buffer_base_27; /*!<(rw), DEC_BASE + 0x000002EC */ + uint32_t isp_dec_read_buffer_base_28; /*!<(rw), DEC_BASE + 0x000002F0 */ + uint32_t isp_dec_read_buffer_base_29; /*!<(rw), DEC_BASE + 0x000002F4 */ + uint32_t isp_dec_read_buffer_base_30; /*!<(rw), DEC_BASE + 0x000002F8 */ + uint32_t isp_dec_read_buffer_base_31; /*!<(rw), DEC_BASE + 0x000002FC */ + uint32_t isp_dec_read_buffer_base_ex_0; /*!<(rw), DEC_BASE + 0x00000300 */ + uint32_t isp_dec_read_buffer_base_ex_1; /*!<(rw), DEC_BASE + 0x00000304 */ + uint32_t isp_dec_read_buffer_base_ex_2; /*!<(rw), DEC_BASE + 0x00000308 */ + uint32_t isp_dec_read_buffer_base_ex_3; /*!<(rw), DEC_BASE + 0x0000030C */ + uint32_t isp_dec_read_buffer_base_ex_4; /*!<(rw), DEC_BASE + 0x00000310 */ + uint32_t isp_dec_read_buffer_base_ex_5; /*!<(rw), DEC_BASE + 0x00000314 */ + uint32_t isp_dec_read_buffer_base_ex_6; /*!<(rw), DEC_BASE + 0x00000318 */ + uint32_t isp_dec_read_buffer_base_ex_7; /*!<(rw), DEC_BASE + 0x0000031C */ + uint32_t isp_dec_read_buffer_base_ex_8; /*!<(rw), DEC_BASE + 0x00000320 */ + uint32_t isp_dec_read_buffer_base_ex_9; /*!<(rw), DEC_BASE + 0x00000324 */ + uint32_t isp_dec_read_buffer_base_ex_10; /*!<(rw), DEC_BASE + 0x00000328 */ + uint32_t isp_dec_read_buffer_base_ex_11; /*!<(rw), DEC_BASE + 0x0000032C */ + uint32_t isp_dec_read_buffer_base_ex_12; /*!<(rw), DEC_BASE + 0x00000330 */ + uint32_t isp_dec_read_buffer_base_ex_13; /*!<(rw), DEC_BASE + 0x00000334 */ + uint32_t isp_dec_read_buffer_base_ex_14; /*!<(rw), DEC_BASE + 0x00000338 */ + uint32_t isp_dec_read_buffer_base_ex_15; /*!<(rw), DEC_BASE + 0x0000033C */ + uint32_t isp_dec_read_buffer_base_ex_16; /*!<(rw), DEC_BASE + 0x00000340 */ + uint32_t isp_dec_read_buffer_base_ex_17; /*!<(rw), DEC_BASE + 0x00000344 */ + uint32_t isp_dec_read_buffer_base_ex_18; /*!<(rw), DEC_BASE + 0x00000348 */ + uint32_t isp_dec_read_buffer_base_ex_19; /*!<(rw), DEC_BASE + 0x0000034C */ + uint32_t isp_dec_read_buffer_base_ex_20; /*!<(rw), DEC_BASE + 0x00000350 */ + uint32_t isp_dec_read_buffer_base_ex_21; /*!<(rw), DEC_BASE + 0x00000354 */ + uint32_t isp_dec_read_buffer_base_ex_22; /*!<(rw), DEC_BASE + 0x00000358 */ + uint32_t isp_dec_read_buffer_base_ex_23; /*!<(rw), DEC_BASE + 0x0000035C */ + uint32_t isp_dec_read_buffer_base_ex_24; /*!<(rw), DEC_BASE + 0x00000360 */ + uint32_t isp_dec_read_buffer_base_ex_25; /*!<(rw), DEC_BASE + 0x00000364 */ + uint32_t isp_dec_read_buffer_base_ex_26; /*!<(rw), DEC_BASE + 0x00000368 */ + uint32_t isp_dec_read_buffer_base_ex_27; /*!<(rw), DEC_BASE + 0x0000036C */ + uint32_t isp_dec_read_buffer_base_ex_28; /*!<(rw), DEC_BASE + 0x00000370 */ + uint32_t isp_dec_read_buffer_base_ex_29; /*!<(rw), DEC_BASE + 0x00000374 */ + uint32_t isp_dec_read_buffer_base_ex_30; /*!<(rw), DEC_BASE + 0x00000378 */ + uint32_t isp_dec_read_buffer_base_ex_31; /*!<(rw), DEC_BASE + 0x0000037C */ + uint32_t isp_dec_read_buffer_end_0; /*!<(rw), DEC_BASE + 0x00000380 */ + uint32_t isp_dec_read_buffer_end_1; /*!<(rw), DEC_BASE + 0x00000384 */ + uint32_t isp_dec_read_buffer_end_2; /*!<(rw), DEC_BASE + 0x00000388 */ + uint32_t isp_dec_read_buffer_end_3; /*!<(rw), DEC_BASE + 0x0000038C */ + uint32_t isp_dec_read_buffer_end_4; /*!<(rw), DEC_BASE + 0x00000390 */ + uint32_t isp_dec_read_buffer_end_5; /*!<(rw), DEC_BASE + 0x00000394 */ + uint32_t isp_dec_read_buffer_end_6; /*!<(rw), DEC_BASE + 0x00000398 */ + uint32_t isp_dec_read_buffer_end_7; /*!<(rw), DEC_BASE + 0x0000039C */ + uint32_t isp_dec_read_buffer_end_8; /*!<(rw), DEC_BASE + 0x000003A0 */ + uint32_t isp_dec_read_buffer_end_9; /*!<(rw), DEC_BASE + 0x000003A4 */ + uint32_t isp_dec_read_buffer_end_10; /*!<(rw), DEC_BASE + 0x000003A8 */ + uint32_t isp_dec_read_buffer_end_11; /*!<(rw), DEC_BASE + 0x000003AC */ + uint32_t isp_dec_read_buffer_end_12; /*!<(rw), DEC_BASE + 0x000003B0 */ + uint32_t isp_dec_read_buffer_end_13; /*!<(rw), DEC_BASE + 0x000003B4 */ + uint32_t isp_dec_read_buffer_end_14; /*!<(rw), DEC_BASE + 0x000003B8 */ + uint32_t isp_dec_read_buffer_end_15; /*!<(rw), DEC_BASE + 0x000003BC */ + uint32_t isp_dec_read_buffer_end_16; /*!<(rw), DEC_BASE + 0x000003C0 */ + uint32_t isp_dec_read_buffer_end_17; /*!<(rw), DEC_BASE + 0x000003C4 */ + uint32_t isp_dec_read_buffer_end_18; /*!<(rw), DEC_BASE + 0x000003C8 */ + uint32_t isp_dec_read_buffer_end_19; /*!<(rw), DEC_BASE + 0x000003CC */ + uint32_t isp_dec_read_buffer_end_20; /*!<(rw), DEC_BASE + 0x000003D0 */ + uint32_t isp_dec_read_buffer_end_21; /*!<(rw), DEC_BASE + 0x000003D4 */ + uint32_t isp_dec_read_buffer_end_22; /*!<(rw), DEC_BASE + 0x000003D8 */ + uint32_t isp_dec_read_buffer_end_23; /*!<(rw), DEC_BASE + 0x000003DC */ + uint32_t isp_dec_read_buffer_end_24; /*!<(rw), DEC_BASE + 0x000003E0 */ + uint32_t isp_dec_read_buffer_end_25; /*!<(rw), DEC_BASE + 0x000003E4 */ + uint32_t isp_dec_read_buffer_end_26; /*!<(rw), DEC_BASE + 0x000003E8 */ + uint32_t isp_dec_read_buffer_end_27; /*!<(rw), DEC_BASE + 0x000003EC */ + uint32_t isp_dec_read_buffer_end_28; /*!<(rw), DEC_BASE + 0x000003F0 */ + uint32_t isp_dec_read_buffer_end_29; /*!<(rw), DEC_BASE + 0x000003F4 */ + uint32_t isp_dec_read_buffer_end_30; /*!<(rw), DEC_BASE + 0x000003F8 */ + uint32_t isp_dec_read_buffer_end_31; /*!<(rw), DEC_BASE + 0x000003FC */ + uint32_t isp_dec_read_buffer_end_ex_0; /*!<(rw), DEC_BASE + 0x00000400 */ + uint32_t isp_dec_read_buffer_end_ex_1; /*!<(rw), DEC_BASE + 0x00000404 */ + uint32_t isp_dec_read_buffer_end_ex_2; /*!<(rw), DEC_BASE + 0x00000408 */ + uint32_t isp_dec_read_buffer_end_ex_3; /*!<(rw), DEC_BASE + 0x0000040C */ + uint32_t isp_dec_read_buffer_end_ex_4; /*!<(rw), DEC_BASE + 0x00000410 */ + uint32_t isp_dec_read_buffer_end_ex_5; /*!<(rw), DEC_BASE + 0x00000414 */ + uint32_t isp_dec_read_buffer_end_ex_6; /*!<(rw), DEC_BASE + 0x00000418 */ + uint32_t isp_dec_read_buffer_end_ex_7; /*!<(rw), DEC_BASE + 0x0000041C */ + uint32_t isp_dec_read_buffer_end_ex_8; /*!<(rw), DEC_BASE + 0x00000420 */ + uint32_t isp_dec_read_buffer_end_ex_9; /*!<(rw), DEC_BASE + 0x00000424 */ + uint32_t isp_dec_read_buffer_end_ex_10; /*!<(rw), DEC_BASE + 0x00000428 */ + uint32_t isp_dec_read_buffer_end_ex_11; /*!<(rw), DEC_BASE + 0x0000042C */ + uint32_t isp_dec_read_buffer_end_ex_12; /*!<(rw), DEC_BASE + 0x00000430 */ + uint32_t isp_dec_read_buffer_end_ex_13; /*!<(rw), DEC_BASE + 0x00000434 */ + uint32_t isp_dec_read_buffer_end_ex_14; /*!<(rw), DEC_BASE + 0x00000438 */ + uint32_t isp_dec_read_buffer_end_ex_15; /*!<(rw), DEC_BASE + 0x0000043C */ + uint32_t isp_dec_read_buffer_end_ex_16; /*!<(rw), DEC_BASE + 0x00000440 */ + uint32_t isp_dec_read_buffer_end_ex_17; /*!<(rw), DEC_BASE + 0x00000444 */ + uint32_t isp_dec_read_buffer_end_ex_18; /*!<(rw), DEC_BASE + 0x00000448 */ + uint32_t isp_dec_read_buffer_end_ex_19; /*!<(rw), DEC_BASE + 0x0000044C */ + uint32_t isp_dec_read_buffer_end_ex_20; /*!<(rw), DEC_BASE + 0x00000450 */ + uint32_t isp_dec_read_buffer_end_ex_21; /*!<(rw), DEC_BASE + 0x00000454 */ + uint32_t isp_dec_read_buffer_end_ex_22; /*!<(rw), DEC_BASE + 0x00000458 */ + uint32_t isp_dec_read_buffer_end_ex_23; /*!<(rw), DEC_BASE + 0x0000045C */ + uint32_t isp_dec_read_buffer_end_ex_24; /*!<(rw), DEC_BASE + 0x00000460 */ + uint32_t isp_dec_read_buffer_end_ex_25; /*!<(rw), DEC_BASE + 0x00000464 */ + uint32_t isp_dec_read_buffer_end_ex_26; /*!<(rw), DEC_BASE + 0x00000468 */ + uint32_t isp_dec_read_buffer_end_ex_27; /*!<(rw), DEC_BASE + 0x0000046C */ + uint32_t isp_dec_read_buffer_end_ex_28; /*!<(rw), DEC_BASE + 0x00000470 */ + uint32_t isp_dec_read_buffer_end_ex_29; /*!<(rw), DEC_BASE + 0x00000474 */ + uint32_t isp_dec_read_buffer_end_ex_30; /*!<(rw), DEC_BASE + 0x00000478 */ + uint32_t isp_dec_read_buffer_end_ex_31; /*!<(rw), DEC_BASE + 0x0000047C */ + uint32_t isp_dec_read_flush_cache_0; /*!<(rw), DEC_BASE + 0x00000480 */ + uint32_t isp_dec_read_flush_cache_1; /*!<(rw), DEC_BASE + 0x00000484 */ + uint32_t isp_dec_read_flush_cache_2; /*!<(rw), DEC_BASE + 0x00000488 */ + uint32_t isp_dec_read_flush_cache_3; /*!<(rw), DEC_BASE + 0x0000048C */ + uint32_t isp_dec_read_flush_cache_4; /*!<(rw), DEC_BASE + 0x00000490 */ + uint32_t isp_dec_read_flush_cache_5; /*!<(rw), DEC_BASE + 0x00000494 */ + uint32_t isp_dec_read_flush_cache_6; /*!<(rw), DEC_BASE + 0x00000498 */ + uint32_t isp_dec_read_flush_cache_7; /*!<(rw), DEC_BASE + 0x0000049C */ + uint32_t isp_dec_read_flush_cache_8; /*!<(rw), DEC_BASE + 0x000004A0 */ + uint32_t isp_dec_read_flush_cache_9; /*!<(rw), DEC_BASE + 0x000004A4 */ + uint32_t isp_dec_read_flush_cache_10; /*!<(rw), DEC_BASE + 0x000004A8 */ + uint32_t isp_dec_read_flush_cache_11; /*!<(rw), DEC_BASE + 0x000004AC */ + uint32_t isp_dec_read_flush_cache_12; /*!<(rw), DEC_BASE + 0x000004B0 */ + uint32_t isp_dec_read_flush_cache_13; /*!<(rw), DEC_BASE + 0x000004B4 */ + uint32_t isp_dec_read_flush_cache_14; /*!<(rw), DEC_BASE + 0x000004B8 */ + uint32_t isp_dec_read_flush_cache_15; /*!<(rw), DEC_BASE + 0x000004BC */ + uint32_t isp_dec_read_flush_cache_16; /*!<(rw), DEC_BASE + 0x000004C0 */ + uint32_t isp_dec_read_flush_cache_17; /*!<(rw), DEC_BASE + 0x000004C4 */ + uint32_t isp_dec_read_flush_cache_18; /*!<(rw), DEC_BASE + 0x000004C8 */ + uint32_t isp_dec_read_flush_cache_19; /*!<(rw), DEC_BASE + 0x000004CC */ + uint32_t isp_dec_read_flush_cache_20; /*!<(rw), DEC_BASE + 0x000004D0 */ + uint32_t isp_dec_read_flush_cache_21; /*!<(rw), DEC_BASE + 0x000004D4 */ + uint32_t isp_dec_read_flush_cache_22; /*!<(rw), DEC_BASE + 0x000004D8 */ + uint32_t isp_dec_read_flush_cache_23; /*!<(rw), DEC_BASE + 0x000004DC */ + uint32_t isp_dec_read_flush_cache_24; /*!<(rw), DEC_BASE + 0x000004E0 */ + uint32_t isp_dec_read_flush_cache_25; /*!<(rw), DEC_BASE + 0x000004E4 */ + uint32_t isp_dec_read_flush_cache_26; /*!<(rw), DEC_BASE + 0x000004E8 */ + uint32_t isp_dec_read_flush_cache_27; /*!<(rw), DEC_BASE + 0x000004EC */ + uint32_t isp_dec_read_flush_cache_28; /*!<(rw), DEC_BASE + 0x000004F0 */ + uint32_t isp_dec_read_flush_cache_29; /*!<(rw), DEC_BASE + 0x000004F4 */ + uint32_t isp_dec_read_flush_cache_30; /*!<(rw), DEC_BASE + 0x000004F8 */ + uint32_t isp_dec_read_flush_cache_31; /*!<(rw), DEC_BASE + 0x000004FC */ + uint32_t isp_dec_read_flush_cache_ex_0; /*!<(rw), DEC_BASE + 0x00000500 */ + uint32_t isp_dec_read_flush_cache_ex_1; /*!<(rw), DEC_BASE + 0x00000504 */ + uint32_t isp_dec_read_flush_cache_ex_2; /*!<(rw), DEC_BASE + 0x00000508 */ + uint32_t isp_dec_read_flush_cache_ex_3; /*!<(rw), DEC_BASE + 0x0000050C */ + uint32_t isp_dec_read_flush_cache_ex_4; /*!<(rw), DEC_BASE + 0x00000510 */ + uint32_t isp_dec_read_flush_cache_ex_5; /*!<(rw), DEC_BASE + 0x00000514 */ + uint32_t isp_dec_read_flush_cache_ex_6; /*!<(rw), DEC_BASE + 0x00000518 */ + uint32_t isp_dec_read_flush_cache_ex_7; /*!<(rw), DEC_BASE + 0x0000051C */ + uint32_t isp_dec_read_flush_cache_ex_8; /*!<(rw), DEC_BASE + 0x00000520 */ + uint32_t isp_dec_read_flush_cache_ex_9; /*!<(rw), DEC_BASE + 0x00000524 */ + uint32_t isp_dec_read_flush_cache_ex_10; /*!<(rw), DEC_BASE + 0x00000528 */ + uint32_t isp_dec_read_flush_cache_ex_11; /*!<(rw), DEC_BASE + 0x0000052C */ + uint32_t isp_dec_read_flush_cache_ex_12; /*!<(rw), DEC_BASE + 0x00000530 */ + uint32_t isp_dec_read_flush_cache_ex_13; /*!<(rw), DEC_BASE + 0x00000534 */ + uint32_t isp_dec_read_flush_cache_ex_14; /*!<(rw), DEC_BASE + 0x00000538 */ + uint32_t isp_dec_read_flush_cache_ex_15; /*!<(rw), DEC_BASE + 0x0000053C */ + uint32_t isp_dec_read_flush_cache_ex_16; /*!<(rw), DEC_BASE + 0x00000540 */ + uint32_t isp_dec_read_flush_cache_ex_17; /*!<(rw), DEC_BASE + 0x00000544 */ + uint32_t isp_dec_read_flush_cache_ex_18; /*!<(rw), DEC_BASE + 0x00000548 */ + uint32_t isp_dec_read_flush_cache_ex_19; /*!<(rw), DEC_BASE + 0x0000054C */ + uint32_t isp_dec_read_flush_cache_ex_20; /*!<(rw), DEC_BASE + 0x00000550 */ + uint32_t isp_dec_read_flush_cache_ex_21; /*!<(rw), DEC_BASE + 0x00000554 */ + uint32_t isp_dec_read_flush_cache_ex_22; /*!<(rw), DEC_BASE + 0x00000558 */ + uint32_t isp_dec_read_flush_cache_ex_23; /*!<(rw), DEC_BASE + 0x0000055C */ + uint32_t isp_dec_read_flush_cache_ex_24; /*!<(rw), DEC_BASE + 0x00000560 */ + uint32_t isp_dec_read_flush_cache_ex_25; /*!<(rw), DEC_BASE + 0x00000564 */ + uint32_t isp_dec_read_flush_cache_ex_26; /*!<(rw), DEC_BASE + 0x00000568 */ + uint32_t isp_dec_read_flush_cache_ex_27; /*!<(rw), DEC_BASE + 0x0000056C */ + uint32_t isp_dec_read_flush_cache_ex_28; /*!<(rw), DEC_BASE + 0x00000570 */ + uint32_t isp_dec_read_flush_cache_ex_29; /*!<(rw), DEC_BASE + 0x00000574 */ + uint32_t isp_dec_read_flush_cache_ex_30; /*!<(rw), DEC_BASE + 0x00000578 */ + uint32_t isp_dec_read_flush_cache_ex_31; /*!<(rw), DEC_BASE + 0x0000057C */ + uint32_t isp_dec_write_buffer_base_0; /*!<(rw), DEC_BASE + 0x00000580 */ + uint32_t isp_dec_write_buffer_base_1; /*!<(rw), DEC_BASE + 0x00000584 */ + uint32_t isp_dec_write_buffer_base_2; /*!<(rw), DEC_BASE + 0x00000588 */ + uint32_t isp_dec_write_buffer_base_3; /*!<(rw), DEC_BASE + 0x0000058C */ + uint32_t isp_dec_write_buffer_base_4; /*!<(rw), DEC_BASE + 0x00000590 */ + uint32_t isp_dec_write_buffer_base_5; /*!<(rw), DEC_BASE + 0x00000594 */ + uint32_t isp_dec_write_buffer_base_6; /*!<(rw), DEC_BASE + 0x00000598 */ + uint32_t isp_dec_write_buffer_base_7; /*!<(rw), DEC_BASE + 0x0000059C */ + uint32_t isp_dec_write_buffer_base_8; /*!<(rw), DEC_BASE + 0x000005A0 */ + uint32_t isp_dec_write_buffer_base_9; /*!<(rw), DEC_BASE + 0x000005A4 */ + uint32_t isp_dec_write_buffer_base_10; /*!<(rw), DEC_BASE + 0x000005A8 */ + uint32_t isp_dec_write_buffer_base_11; /*!<(rw), DEC_BASE + 0x000005AC */ + uint32_t isp_dec_write_buffer_base_12; /*!<(rw), DEC_BASE + 0x000005B0 */ + uint32_t isp_dec_write_buffer_base_13; /*!<(rw), DEC_BASE + 0x000005B4 */ + uint32_t isp_dec_write_buffer_base_14; /*!<(rw), DEC_BASE + 0x000005B8 */ + uint32_t isp_dec_write_buffer_base_15; /*!<(rw), DEC_BASE + 0x000005BC */ + uint32_t isp_dec_write_buffer_base_16; /*!<(rw), DEC_BASE + 0x000005C0 */ + uint32_t isp_dec_write_buffer_base_17; /*!<(rw), DEC_BASE + 0x000005C4 */ + uint32_t isp_dec_write_buffer_base_18; /*!<(rw), DEC_BASE + 0x000005C8 */ + uint32_t isp_dec_write_buffer_base_19; /*!<(rw), DEC_BASE + 0x000005CC */ + uint32_t isp_dec_write_buffer_base_20; /*!<(rw), DEC_BASE + 0x000005D0 */ + uint32_t isp_dec_write_buffer_base_21; /*!<(rw), DEC_BASE + 0x000005D4 */ + uint32_t isp_dec_write_buffer_base_22; /*!<(rw), DEC_BASE + 0x000005D8 */ + uint32_t isp_dec_write_buffer_base_23; /*!<(rw), DEC_BASE + 0x000005DC */ + uint32_t isp_dec_write_buffer_base_24; /*!<(rw), DEC_BASE + 0x000005E0 */ + uint32_t isp_dec_write_buffer_base_25; /*!<(rw), DEC_BASE + 0x000005E4 */ + uint32_t isp_dec_write_buffer_base_26; /*!<(rw), DEC_BASE + 0x000005E8 */ + uint32_t isp_dec_write_buffer_base_27; /*!<(rw), DEC_BASE + 0x000005EC */ + uint32_t isp_dec_write_buffer_base_28; /*!<(rw), DEC_BASE + 0x000005F0 */ + uint32_t isp_dec_write_buffer_base_29; /*!<(rw), DEC_BASE + 0x000005F4 */ + uint32_t isp_dec_write_buffer_base_30; /*!<(rw), DEC_BASE + 0x000005F8 */ + uint32_t isp_dec_write_buffer_base_31; /*!<(rw), DEC_BASE + 0x000005FC */ + uint32_t isp_dec_write_buffer_base_ex_0; /*!<(rw), DEC_BASE + 0x00000600 */ + uint32_t isp_dec_write_buffer_base_ex_1; /*!<(rw), DEC_BASE + 0x00000604 */ + uint32_t isp_dec_write_buffer_base_ex_2; /*!<(rw), DEC_BASE + 0x00000608 */ + uint32_t isp_dec_write_buffer_base_ex_3; /*!<(rw), DEC_BASE + 0x0000060C */ + uint32_t isp_dec_write_buffer_base_ex_4; /*!<(rw), DEC_BASE + 0x00000610 */ + uint32_t isp_dec_write_buffer_base_ex_5; /*!<(rw), DEC_BASE + 0x00000614 */ + uint32_t isp_dec_write_buffer_base_ex_6; /*!<(rw), DEC_BASE + 0x00000618 */ + uint32_t isp_dec_write_buffer_base_ex_7; /*!<(rw), DEC_BASE + 0x0000061C */ + uint32_t isp_dec_write_buffer_base_ex_8; /*!<(rw), DEC_BASE + 0x00000620 */ + uint32_t isp_dec_write_buffer_base_ex_9; /*!<(rw), DEC_BASE + 0x00000624 */ + uint32_t isp_dec_write_buffer_base_ex_10; /*!<(rw), DEC_BASE + 0x00000628 */ + uint32_t isp_dec_write_buffer_base_ex_11; /*!<(rw), DEC_BASE + 0x0000062C */ + uint32_t isp_dec_write_buffer_base_ex_12; /*!<(rw), DEC_BASE + 0x00000630 */ + uint32_t isp_dec_write_buffer_base_ex_13; /*!<(rw), DEC_BASE + 0x00000634 */ + uint32_t isp_dec_write_buffer_base_ex_14; /*!<(rw), DEC_BASE + 0x00000638 */ + uint32_t isp_dec_write_buffer_base_ex_15; /*!<(rw), DEC_BASE + 0x0000063C */ + uint32_t isp_dec_write_buffer_base_ex_16; /*!<(rw), DEC_BASE + 0x00000640 */ + uint32_t isp_dec_write_buffer_base_ex_17; /*!<(rw), DEC_BASE + 0x00000644 */ + uint32_t isp_dec_write_buffer_base_ex_18; /*!<(rw), DEC_BASE + 0x00000648 */ + uint32_t isp_dec_write_buffer_base_ex_19; /*!<(rw), DEC_BASE + 0x0000064C */ + uint32_t isp_dec_write_buffer_base_ex_20; /*!<(rw), DEC_BASE + 0x00000650 */ + uint32_t isp_dec_write_buffer_base_ex_21; /*!<(rw), DEC_BASE + 0x00000654 */ + uint32_t isp_dec_write_buffer_base_ex_22; /*!<(rw), DEC_BASE + 0x00000658 */ + uint32_t isp_dec_write_buffer_base_ex_23; /*!<(rw), DEC_BASE + 0x0000065C */ + uint32_t isp_dec_write_buffer_base_ex_24; /*!<(rw), DEC_BASE + 0x00000660 */ + uint32_t isp_dec_write_buffer_base_ex_25; /*!<(rw), DEC_BASE + 0x00000664 */ + uint32_t isp_dec_write_buffer_base_ex_26; /*!<(rw), DEC_BASE + 0x00000668 */ + uint32_t isp_dec_write_buffer_base_ex_27; /*!<(rw), DEC_BASE + 0x0000066C */ + uint32_t isp_dec_write_buffer_base_ex_28; /*!<(rw), DEC_BASE + 0x00000670 */ + uint32_t isp_dec_write_buffer_base_ex_29; /*!<(rw), DEC_BASE + 0x00000674 */ + uint32_t isp_dec_write_buffer_base_ex_30; /*!<(rw), DEC_BASE + 0x00000678 */ + uint32_t isp_dec_write_buffer_base_ex_31; /*!<(rw), DEC_BASE + 0x0000067C */ + uint32_t isp_dec_write_buffer_end_0; /*!<(rw), DEC_BASE + 0x00000680 */ + uint32_t isp_dec_write_buffer_end_1; /*!<(rw), DEC_BASE + 0x00000684 */ + uint32_t isp_dec_write_buffer_end_2; /*!<(rw), DEC_BASE + 0x00000688 */ + uint32_t isp_dec_write_buffer_end_3; /*!<(rw), DEC_BASE + 0x0000068C */ + uint32_t isp_dec_write_buffer_end_4; /*!<(rw), DEC_BASE + 0x00000690 */ + uint32_t isp_dec_write_buffer_end_5; /*!<(rw), DEC_BASE + 0x00000694 */ + uint32_t isp_dec_write_buffer_end_6; /*!<(rw), DEC_BASE + 0x00000698 */ + uint32_t isp_dec_write_buffer_end_7; /*!<(rw), DEC_BASE + 0x0000069C */ + uint32_t isp_dec_write_buffer_end_8; /*!<(rw), DEC_BASE + 0x000006A0 */ + uint32_t isp_dec_write_buffer_end_9; /*!<(rw), DEC_BASE + 0x000006A4 */ + uint32_t isp_dec_write_buffer_end_10; /*!<(rw), DEC_BASE + 0x000006A8 */ + uint32_t isp_dec_write_buffer_end_11; /*!<(rw), DEC_BASE + 0x000006AC */ + uint32_t isp_dec_write_buffer_end_12; /*!<(rw), DEC_BASE + 0x000006B0 */ + uint32_t isp_dec_write_buffer_end_13; /*!<(rw), DEC_BASE + 0x000006B4 */ + uint32_t isp_dec_write_buffer_end_14; /*!<(rw), DEC_BASE + 0x000006B8 */ + uint32_t isp_dec_write_buffer_end_15; /*!<(rw), DEC_BASE + 0x000006BC */ + uint32_t isp_dec_write_buffer_end_16; /*!<(rw), DEC_BASE + 0x000006C0 */ + uint32_t isp_dec_write_buffer_end_17; /*!<(rw), DEC_BASE + 0x000006C4 */ + uint32_t isp_dec_write_buffer_end_18; /*!<(rw), DEC_BASE + 0x000006C8 */ + uint32_t isp_dec_write_buffer_end_19; /*!<(rw), DEC_BASE + 0x000006CC */ + uint32_t isp_dec_write_buffer_end_20; /*!<(rw), DEC_BASE + 0x000006D0 */ + uint32_t isp_dec_write_buffer_end_21; /*!<(rw), DEC_BASE + 0x000006D4 */ + uint32_t isp_dec_write_buffer_end_22; /*!<(rw), DEC_BASE + 0x000006D8 */ + uint32_t isp_dec_write_buffer_end_23; /*!<(rw), DEC_BASE + 0x000006DC */ + uint32_t isp_dec_write_buffer_end_24; /*!<(rw), DEC_BASE + 0x000006E0 */ + uint32_t isp_dec_write_buffer_end_25; /*!<(rw), DEC_BASE + 0x000006E4 */ + uint32_t isp_dec_write_buffer_end_26; /*!<(rw), DEC_BASE + 0x000006E8 */ + uint32_t isp_dec_write_buffer_end_27; /*!<(rw), DEC_BASE + 0x000006EC */ + uint32_t isp_dec_write_buffer_end_28; /*!<(rw), DEC_BASE + 0x000006F0 */ + uint32_t isp_dec_write_buffer_end_29; /*!<(rw), DEC_BASE + 0x000006F4 */ + uint32_t isp_dec_write_buffer_end_30; /*!<(rw), DEC_BASE + 0x000006F8 */ + uint32_t isp_dec_write_buffer_end_31; /*!<(rw), DEC_BASE + 0x000006FC */ + uint32_t isp_dec_write_buffer_end_ex_0; /*!<(rw), DEC_BASE + 0x00000700 */ + uint32_t isp_dec_write_buffer_end_ex_1; /*!<(rw), DEC_BASE + 0x00000704 */ + uint32_t isp_dec_write_buffer_end_ex_2; /*!<(rw), DEC_BASE + 0x00000708 */ + uint32_t isp_dec_write_buffer_end_ex_3; /*!<(rw), DEC_BASE + 0x0000070C */ + uint32_t isp_dec_write_buffer_end_ex_4; /*!<(rw), DEC_BASE + 0x00000710 */ + uint32_t isp_dec_write_buffer_end_ex_5; /*!<(rw), DEC_BASE + 0x00000714 */ + uint32_t isp_dec_write_buffer_end_ex_6; /*!<(rw), DEC_BASE + 0x00000718 */ + uint32_t isp_dec_write_buffer_end_ex_7; /*!<(rw), DEC_BASE + 0x0000071C */ + uint32_t isp_dec_write_buffer_end_ex_8; /*!<(rw), DEC_BASE + 0x00000720 */ + uint32_t isp_dec_write_buffer_end_ex_9; /*!<(rw), DEC_BASE + 0x00000724 */ + uint32_t isp_dec_write_buffer_end_ex_10; /*!<(rw), DEC_BASE + 0x00000728 */ + uint32_t isp_dec_write_buffer_end_ex_11; /*!<(rw), DEC_BASE + 0x0000072C */ + uint32_t isp_dec_write_buffer_end_ex_12; /*!<(rw), DEC_BASE + 0x00000730 */ + uint32_t isp_dec_write_buffer_end_ex_13; /*!<(rw), DEC_BASE + 0x00000734 */ + uint32_t isp_dec_write_buffer_end_ex_14; /*!<(rw), DEC_BASE + 0x00000738 */ + uint32_t isp_dec_write_buffer_end_ex_15; /*!<(rw), DEC_BASE + 0x0000073C */ + uint32_t isp_dec_write_buffer_end_ex_16; /*!<(rw), DEC_BASE + 0x00000740 */ + uint32_t isp_dec_write_buffer_end_ex_17; /*!<(rw), DEC_BASE + 0x00000744 */ + uint32_t isp_dec_write_buffer_end_ex_18; /*!<(rw), DEC_BASE + 0x00000748 */ + uint32_t isp_dec_write_buffer_end_ex_19; /*!<(rw), DEC_BASE + 0x0000074C */ + uint32_t isp_dec_write_buffer_end_ex_20; /*!<(rw), DEC_BASE + 0x00000750 */ + uint32_t isp_dec_write_buffer_end_ex_21; /*!<(rw), DEC_BASE + 0x00000754 */ + uint32_t isp_dec_write_buffer_end_ex_22; /*!<(rw), DEC_BASE + 0x00000758 */ + uint32_t isp_dec_write_buffer_end_ex_23; /*!<(rw), DEC_BASE + 0x0000075C */ + uint32_t isp_dec_write_buffer_end_ex_24; /*!<(rw), DEC_BASE + 0x00000760 */ + uint32_t isp_dec_write_buffer_end_ex_25; /*!<(rw), DEC_BASE + 0x00000764 */ + uint32_t isp_dec_write_buffer_end_ex_26; /*!<(rw), DEC_BASE + 0x00000768 */ + uint32_t isp_dec_write_buffer_end_ex_27; /*!<(rw), DEC_BASE + 0x0000076C */ + uint32_t isp_dec_write_buffer_end_ex_28; /*!<(rw), DEC_BASE + 0x00000770 */ + uint32_t isp_dec_write_buffer_end_ex_29; /*!<(rw), DEC_BASE + 0x00000774 */ + uint32_t isp_dec_write_buffer_end_ex_30; /*!<(rw), DEC_BASE + 0x00000778 */ + uint32_t isp_dec_write_buffer_end_ex_31; /*!<(rw), DEC_BASE + 0x0000077C */ + uint32_t isp_dec_write_flush_cache_0; /*!<(rw), DEC_BASE + 0x00000780 */ + uint32_t isp_dec_write_flush_cache_1; /*!<(rw), DEC_BASE + 0x00000784 */ + uint32_t isp_dec_write_flush_cache_2; /*!<(rw), DEC_BASE + 0x00000788 */ + uint32_t isp_dec_write_flush_cache_3; /*!<(rw), DEC_BASE + 0x0000078C */ + uint32_t isp_dec_write_flush_cache_4; /*!<(rw), DEC_BASE + 0x00000790 */ + uint32_t isp_dec_write_flush_cache_5; /*!<(rw), DEC_BASE + 0x00000794 */ + uint32_t isp_dec_write_flush_cache_6; /*!<(rw), DEC_BASE + 0x00000798 */ + uint32_t isp_dec_write_flush_cache_7; /*!<(rw), DEC_BASE + 0x0000079C */ + uint32_t isp_dec_write_flush_cache_8; /*!<(rw), DEC_BASE + 0x000007A0 */ + uint32_t isp_dec_write_flush_cache_9; /*!<(rw), DEC_BASE + 0x000007A4 */ + uint32_t isp_dec_write_flush_cache_10; /*!<(rw), DEC_BASE + 0x000007A8 */ + uint32_t isp_dec_write_flush_cache_11; /*!<(rw), DEC_BASE + 0x000007AC */ + uint32_t isp_dec_write_flush_cache_12; /*!<(rw), DEC_BASE + 0x000007B0 */ + uint32_t isp_dec_write_flush_cache_13; /*!<(rw), DEC_BASE + 0x000007B4 */ + uint32_t isp_dec_write_flush_cache_14; /*!<(rw), DEC_BASE + 0x000007B8 */ + uint32_t isp_dec_write_flush_cache_15; /*!<(rw), DEC_BASE + 0x000007BC */ + uint32_t isp_dec_write_flush_cache_16; /*!<(rw), DEC_BASE + 0x000007C0 */ + uint32_t isp_dec_write_flush_cache_17; /*!<(rw), DEC_BASE + 0x000007C4 */ + uint32_t isp_dec_write_flush_cache_18; /*!<(rw), DEC_BASE + 0x000007C8 */ + uint32_t isp_dec_write_flush_cache_19; /*!<(rw), DEC_BASE + 0x000007CC */ + uint32_t isp_dec_write_flush_cache_20; /*!<(rw), DEC_BASE + 0x000007D0 */ + uint32_t isp_dec_write_flush_cache_21; /*!<(rw), DEC_BASE + 0x000007D4 */ + uint32_t isp_dec_write_flush_cache_22; /*!<(rw), DEC_BASE + 0x000007D8 */ + uint32_t isp_dec_write_flush_cache_23; /*!<(rw), DEC_BASE + 0x000007DC */ + uint32_t isp_dec_write_flush_cache_24; /*!<(rw), DEC_BASE + 0x000007E0 */ + uint32_t isp_dec_write_flush_cache_25; /*!<(rw), DEC_BASE + 0x000007E4 */ + uint32_t isp_dec_write_flush_cache_26; /*!<(rw), DEC_BASE + 0x000007E8 */ + uint32_t isp_dec_write_flush_cache_27; /*!<(rw), DEC_BASE + 0x000007EC */ + uint32_t isp_dec_write_flush_cache_28; /*!<(rw), DEC_BASE + 0x000007F0 */ + uint32_t isp_dec_write_flush_cache_29; /*!<(rw), DEC_BASE + 0x000007F4 */ + uint32_t isp_dec_write_flush_cache_30; /*!<(rw), DEC_BASE + 0x000007F8 */ + uint32_t isp_dec_write_flush_cache_31; /*!<(rw), DEC_BASE + 0x000007FC */ + uint32_t isp_dec_write_flush_cache_ex_0; /*!<(rw), DEC_BASE + 0x00000800 */ + uint32_t isp_dec_write_flush_cache_ex_1; /*!<(rw), DEC_BASE + 0x00000804 */ + uint32_t isp_dec_write_flush_cache_ex_2; /*!<(rw), DEC_BASE + 0x00000808 */ + uint32_t isp_dec_write_flush_cache_ex_3; /*!<(rw), DEC_BASE + 0x0000080C */ + uint32_t isp_dec_write_flush_cache_ex_4; /*!<(rw), DEC_BASE + 0x00000810 */ + uint32_t isp_dec_write_flush_cache_ex_5; /*!<(rw), DEC_BASE + 0x00000814 */ + uint32_t isp_dec_write_flush_cache_ex_6; /*!<(rw), DEC_BASE + 0x00000818 */ + uint32_t isp_dec_write_flush_cache_ex_7; /*!<(rw), DEC_BASE + 0x0000081C */ + uint32_t isp_dec_write_flush_cache_ex_8; /*!<(rw), DEC_BASE + 0x00000820 */ + uint32_t isp_dec_write_flush_cache_ex_9; /*!<(rw), DEC_BASE + 0x00000824 */ + uint32_t isp_dec_write_flush_cache_ex_10; /*!<(rw), DEC_BASE + 0x00000828 */ + uint32_t isp_dec_write_flush_cache_ex_11; /*!<(rw), DEC_BASE + 0x0000082C */ + uint32_t isp_dec_write_flush_cache_ex_12; /*!<(rw), DEC_BASE + 0x00000830 */ + uint32_t isp_dec_write_flush_cache_ex_13; /*!<(rw), DEC_BASE + 0x00000834 */ + uint32_t isp_dec_write_flush_cache_ex_14; /*!<(rw), DEC_BASE + 0x00000838 */ + uint32_t isp_dec_write_flush_cache_ex_15; /*!<(rw), DEC_BASE + 0x0000083C */ + uint32_t isp_dec_write_flush_cache_ex_16; /*!<(rw), DEC_BASE + 0x00000840 */ + uint32_t isp_dec_write_flush_cache_ex_17; /*!<(rw), DEC_BASE + 0x00000844 */ + uint32_t isp_dec_write_flush_cache_ex_18; /*!<(rw), DEC_BASE + 0x00000848 */ + uint32_t isp_dec_write_flush_cache_ex_19; /*!<(rw), DEC_BASE + 0x0000084C */ + uint32_t isp_dec_write_flush_cache_ex_20; /*!<(rw), DEC_BASE + 0x00000850 */ + uint32_t isp_dec_write_flush_cache_ex_21; /*!<(rw), DEC_BASE + 0x00000854 */ + uint32_t isp_dec_write_flush_cache_ex_22; /*!<(rw), DEC_BASE + 0x00000858 */ + uint32_t isp_dec_write_flush_cache_ex_23; /*!<(rw), DEC_BASE + 0x0000085C */ + uint32_t isp_dec_write_flush_cache_ex_24; /*!<(rw), DEC_BASE + 0x00000860 */ + uint32_t isp_dec_write_flush_cache_ex_25; /*!<(rw), DEC_BASE + 0x00000864 */ + uint32_t isp_dec_write_flush_cache_ex_26; /*!<(rw), DEC_BASE + 0x00000868 */ + uint32_t isp_dec_write_flush_cache_ex_27; /*!<(rw), DEC_BASE + 0x0000086C */ + uint32_t isp_dec_write_flush_cache_ex_28; /*!<(rw), DEC_BASE + 0x00000870 */ + uint32_t isp_dec_write_flush_cache_ex_29; /*!<(rw), DEC_BASE + 0x00000874 */ + uint32_t isp_dec_write_flush_cache_ex_30; /*!<(rw), DEC_BASE + 0x00000878 */ + uint32_t isp_dec_write_flush_cache_ex_31; /*!<(rw), DEC_BASE + 0x0000087C */ + uint32_t isp_dec_read_cache_base_0; /*!<(rw), DEC_BASE + 0x00000880 */ + uint32_t isp_dec_read_cache_base_1; /*!<(rw), DEC_BASE + 0x00000884 */ + uint32_t isp_dec_read_cache_base_2; /*!<(rw), DEC_BASE + 0x00000888 */ + uint32_t isp_dec_read_cache_base_3; /*!<(rw), DEC_BASE + 0x0000088C */ + uint32_t isp_dec_read_cache_base_4; /*!<(rw), DEC_BASE + 0x00000890 */ + uint32_t isp_dec_read_cache_base_5; /*!<(rw), DEC_BASE + 0x00000894 */ + uint32_t isp_dec_read_cache_base_6; /*!<(rw), DEC_BASE + 0x00000898 */ + uint32_t isp_dec_read_cache_base_7; /*!<(rw), DEC_BASE + 0x0000089C */ + uint32_t isp_dec_read_cache_base_8; /*!<(rw), DEC_BASE + 0x000008A0 */ + uint32_t isp_dec_read_cache_base_9; /*!<(rw), DEC_BASE + 0x000008A4 */ + uint32_t isp_dec_read_cache_base_10; /*!<(rw), DEC_BASE + 0x000008A8 */ + uint32_t isp_dec_read_cache_base_11; /*!<(rw), DEC_BASE + 0x000008AC */ + uint32_t isp_dec_read_cache_base_12; /*!<(rw), DEC_BASE + 0x000008B0 */ + uint32_t isp_dec_read_cache_base_13; /*!<(rw), DEC_BASE + 0x000008B4 */ + uint32_t isp_dec_read_cache_base_14; /*!<(rw), DEC_BASE + 0x000008B8 */ + uint32_t isp_dec_read_cache_base_15; /*!<(rw), DEC_BASE + 0x000008BC */ + uint32_t isp_dec_read_cache_base_16; /*!<(rw), DEC_BASE + 0x000008C0 */ + uint32_t isp_dec_read_cache_base_17; /*!<(rw), DEC_BASE + 0x000008C4 */ + uint32_t isp_dec_read_cache_base_18; /*!<(rw), DEC_BASE + 0x000008C8 */ + uint32_t isp_dec_read_cache_base_19; /*!<(rw), DEC_BASE + 0x000008CC */ + uint32_t isp_dec_read_cache_base_20; /*!<(rw), DEC_BASE + 0x000008D0 */ + uint32_t isp_dec_read_cache_base_21; /*!<(rw), DEC_BASE + 0x000008D4 */ + uint32_t isp_dec_read_cache_base_22; /*!<(rw), DEC_BASE + 0x000008D8 */ + uint32_t isp_dec_read_cache_base_23; /*!<(rw), DEC_BASE + 0x000008DC */ + uint32_t isp_dec_read_cache_base_24; /*!<(rw), DEC_BASE + 0x000008E0 */ + uint32_t isp_dec_read_cache_base_25; /*!<(rw), DEC_BASE + 0x000008E4 */ + uint32_t isp_dec_read_cache_base_26; /*!<(rw), DEC_BASE + 0x000008E8 */ + uint32_t isp_dec_read_cache_base_27; /*!<(rw), DEC_BASE + 0x000008EC */ + uint32_t isp_dec_read_cache_base_28; /*!<(rw), DEC_BASE + 0x000008F0 */ + uint32_t isp_dec_read_cache_base_29; /*!<(rw), DEC_BASE + 0x000008F4 */ + uint32_t isp_dec_read_cache_base_30; /*!<(rw), DEC_BASE + 0x000008F8 */ + uint32_t isp_dec_read_cache_base_31; /*!<(rw), DEC_BASE + 0x000008FC */ + uint32_t isp_dec_read_cache_base_ex_0; /*!<(rw), DEC_BASE + 0x00000900 */ + uint32_t isp_dec_read_cache_base_ex_1; /*!<(rw), DEC_BASE + 0x00000904 */ + uint32_t isp_dec_read_cache_base_ex_2; /*!<(rw), DEC_BASE + 0x00000908 */ + uint32_t isp_dec_read_cache_base_ex_3; /*!<(rw), DEC_BASE + 0x0000090C */ + uint32_t isp_dec_read_cache_base_ex_4; /*!<(rw), DEC_BASE + 0x00000910 */ + uint32_t isp_dec_read_cache_base_ex_5; /*!<(rw), DEC_BASE + 0x00000914 */ + uint32_t isp_dec_read_cache_base_ex_6; /*!<(rw), DEC_BASE + 0x00000918 */ + uint32_t isp_dec_read_cache_base_ex_7; /*!<(rw), DEC_BASE + 0x0000091C */ + uint32_t isp_dec_read_cache_base_ex_8; /*!<(rw), DEC_BASE + 0x00000920 */ + uint32_t isp_dec_read_cache_base_ex_9; /*!<(rw), DEC_BASE + 0x00000924 */ + uint32_t isp_dec_read_cache_base_ex_10; /*!<(rw), DEC_BASE + 0x00000928 */ + uint32_t isp_dec_read_cache_base_ex_11; /*!<(rw), DEC_BASE + 0x0000092C */ + uint32_t isp_dec_read_cache_base_ex_12; /*!<(rw), DEC_BASE + 0x00000930 */ + uint32_t isp_dec_read_cache_base_ex_13; /*!<(rw), DEC_BASE + 0x00000934 */ + uint32_t isp_dec_read_cache_base_ex_14; /*!<(rw), DEC_BASE + 0x00000938 */ + uint32_t isp_dec_read_cache_base_ex_15; /*!<(rw), DEC_BASE + 0x0000093C */ + uint32_t isp_dec_read_cache_base_ex_16; /*!<(rw), DEC_BASE + 0x00000940 */ + uint32_t isp_dec_read_cache_base_ex_17; /*!<(rw), DEC_BASE + 0x00000944 */ + uint32_t isp_dec_read_cache_base_ex_18; /*!<(rw), DEC_BASE + 0x00000948 */ + uint32_t isp_dec_read_cache_base_ex_19; /*!<(rw), DEC_BASE + 0x0000094C */ + uint32_t isp_dec_read_cache_base_ex_20; /*!<(rw), DEC_BASE + 0x00000950 */ + uint32_t isp_dec_read_cache_base_ex_21; /*!<(rw), DEC_BASE + 0x00000954 */ + uint32_t isp_dec_read_cache_base_ex_22; /*!<(rw), DEC_BASE + 0x00000958 */ + uint32_t isp_dec_read_cache_base_ex_23; /*!<(rw), DEC_BASE + 0x0000095C */ + uint32_t isp_dec_read_cache_base_ex_24; /*!<(rw), DEC_BASE + 0x00000960 */ + uint32_t isp_dec_read_cache_base_ex_25; /*!<(rw), DEC_BASE + 0x00000964 */ + uint32_t isp_dec_read_cache_base_ex_26; /*!<(rw), DEC_BASE + 0x00000968 */ + uint32_t isp_dec_read_cache_base_ex_27; /*!<(rw), DEC_BASE + 0x0000096C */ + uint32_t isp_dec_read_cache_base_ex_28; /*!<(rw), DEC_BASE + 0x00000970 */ + uint32_t isp_dec_read_cache_base_ex_29; /*!<(rw), DEC_BASE + 0x00000974 */ + uint32_t isp_dec_read_cache_base_ex_30; /*!<(rw), DEC_BASE + 0x00000978 */ + uint32_t isp_dec_read_cache_base_ex_31; /*!<(rw), DEC_BASE + 0x0000097C */ + uint32_t isp_dec_write_cache_base_0; /*!<(rw), DEC_BASE + 0x00000980 */ + uint32_t isp_dec_write_cache_base_1; /*!<(rw), DEC_BASE + 0x00000984 */ + uint32_t isp_dec_write_cache_base_2; /*!<(rw), DEC_BASE + 0x00000988 */ + uint32_t isp_dec_write_cache_base_3; /*!<(rw), DEC_BASE + 0x0000098C */ + uint32_t isp_dec_write_cache_base_4; /*!<(rw), DEC_BASE + 0x00000990 */ + uint32_t isp_dec_write_cache_base_5; /*!<(rw), DEC_BASE + 0x00000994 */ + uint32_t isp_dec_write_cache_base_6; /*!<(rw), DEC_BASE + 0x00000998 */ + uint32_t isp_dec_write_cache_base_7; /*!<(rw), DEC_BASE + 0x0000099C */ + uint32_t isp_dec_write_cache_base_8; /*!<(rw), DEC_BASE + 0x000009A0 */ + uint32_t isp_dec_write_cache_base_9; /*!<(rw), DEC_BASE + 0x000009A4 */ + uint32_t isp_dec_write_cache_base_10; /*!<(rw), DEC_BASE + 0x000009A8 */ + uint32_t isp_dec_write_cache_base_11; /*!<(rw), DEC_BASE + 0x000009AC */ + uint32_t isp_dec_write_cache_base_12; /*!<(rw), DEC_BASE + 0x000009B0 */ + uint32_t isp_dec_write_cache_base_13; /*!<(rw), DEC_BASE + 0x000009B4 */ + uint32_t isp_dec_write_cache_base_14; /*!<(rw), DEC_BASE + 0x000009B8 */ + uint32_t isp_dec_write_cache_base_15; /*!<(rw), DEC_BASE + 0x000009BC */ + uint32_t isp_dec_write_cache_base_16; /*!<(rw), DEC_BASE + 0x000009C0 */ + uint32_t isp_dec_write_cache_base_17; /*!<(rw), DEC_BASE + 0x000009C4 */ + uint32_t isp_dec_write_cache_base_18; /*!<(rw), DEC_BASE + 0x000009C8 */ + uint32_t isp_dec_write_cache_base_19; /*!<(rw), DEC_BASE + 0x000009CC */ + uint32_t isp_dec_write_cache_base_20; /*!<(rw), DEC_BASE + 0x000009D0 */ + uint32_t isp_dec_write_cache_base_21; /*!<(rw), DEC_BASE + 0x000009D4 */ + uint32_t isp_dec_write_cache_base_22; /*!<(rw), DEC_BASE + 0x000009D8 */ + uint32_t isp_dec_write_cache_base_23; /*!<(rw), DEC_BASE + 0x000009DC */ + uint32_t isp_dec_write_cache_base_24; /*!<(rw), DEC_BASE + 0x000009E0 */ + uint32_t isp_dec_write_cache_base_25; /*!<(rw), DEC_BASE + 0x000009E4 */ + uint32_t isp_dec_write_cache_base_26; /*!<(rw), DEC_BASE + 0x000009E8 */ + uint32_t isp_dec_write_cache_base_27; /*!<(rw), DEC_BASE + 0x000009EC */ + uint32_t isp_dec_write_cache_base_28; /*!<(rw), DEC_BASE + 0x000009F0 */ + uint32_t isp_dec_write_cache_base_29; /*!<(rw), DEC_BASE + 0x000009F4 */ + uint32_t isp_dec_write_cache_base_30; /*!<(rw), DEC_BASE + 0x000009F8 */ + uint32_t isp_dec_write_cache_base_31; /*!<(rw), DEC_BASE + 0x000009FC */ + uint32_t isp_dec_write_cache_base_ex_0; /*!<(rw), DEC_BASE + 0x00000A00 */ + uint32_t isp_dec_write_cache_base_ex_1; /*!<(rw), DEC_BASE + 0x00000A04 */ + uint32_t isp_dec_write_cache_base_ex_2; /*!<(rw), DEC_BASE + 0x00000A08 */ + uint32_t isp_dec_write_cache_base_ex_3; /*!<(rw), DEC_BASE + 0x00000A0C */ + uint32_t isp_dec_write_cache_base_ex_4; /*!<(rw), DEC_BASE + 0x00000A10 */ + uint32_t isp_dec_write_cache_base_ex_5; /*!<(rw), DEC_BASE + 0x00000A14 */ + uint32_t isp_dec_write_cache_base_ex_6; /*!<(rw), DEC_BASE + 0x00000A18 */ + uint32_t isp_dec_write_cache_base_ex_7; /*!<(rw), DEC_BASE + 0x00000A1C */ + uint32_t isp_dec_write_cache_base_ex_8; /*!<(rw), DEC_BASE + 0x00000A20 */ + uint32_t isp_dec_write_cache_base_ex_9; /*!<(rw), DEC_BASE + 0x00000A24 */ + uint32_t isp_dec_write_cache_base_ex_10; /*!<(rw), DEC_BASE + 0x00000A28 */ + uint32_t isp_dec_write_cache_base_ex_11; /*!<(rw), DEC_BASE + 0x00000A2C */ + uint32_t isp_dec_write_cache_base_ex_12; /*!<(rw), DEC_BASE + 0x00000A30 */ + uint32_t isp_dec_write_cache_base_ex_13; /*!<(rw), DEC_BASE + 0x00000A34 */ + uint32_t isp_dec_write_cache_base_ex_14; /*!<(rw), DEC_BASE + 0x00000A38 */ + uint32_t isp_dec_write_cache_base_ex_15; /*!<(rw), DEC_BASE + 0x00000A3C */ + uint32_t isp_dec_write_cache_base_ex_16; /*!<(rw), DEC_BASE + 0x00000A40 */ + uint32_t isp_dec_write_cache_base_ex_17; /*!<(rw), DEC_BASE + 0x00000A44 */ + uint32_t isp_dec_write_cache_base_ex_18; /*!<(rw), DEC_BASE + 0x00000A48 */ + uint32_t isp_dec_write_cache_base_ex_19; /*!<(rw), DEC_BASE + 0x00000A4C */ + uint32_t isp_dec_write_cache_base_ex_20; /*!<(rw), DEC_BASE + 0x00000A50 */ + uint32_t isp_dec_write_cache_base_ex_21; /*!<(rw), DEC_BASE + 0x00000A54 */ + uint32_t isp_dec_write_cache_base_ex_22; /*!<(rw), DEC_BASE + 0x00000A58 */ + uint32_t isp_dec_write_cache_base_ex_23; /*!<(rw), DEC_BASE + 0x00000A5C */ + uint32_t isp_dec_write_cache_base_ex_24; /*!<(rw), DEC_BASE + 0x00000A60 */ + uint32_t isp_dec_write_cache_base_ex_25; /*!<(rw), DEC_BASE + 0x00000A64 */ + uint32_t isp_dec_write_cache_base_ex_26; /*!<(rw), DEC_BASE + 0x00000A68 */ + uint32_t isp_dec_write_cache_base_ex_27; /*!<(rw), DEC_BASE + 0x00000A6C */ + uint32_t isp_dec_write_cache_base_ex_28; /*!<(rw), DEC_BASE + 0x00000A70 */ + uint32_t isp_dec_write_cache_base_ex_29; /*!<(rw), DEC_BASE + 0x00000A74 */ + uint32_t isp_dec_write_cache_base_ex_30; /*!<(rw), DEC_BASE + 0x00000A78 */ + uint32_t isp_dec_write_cache_base_ex_31; /*!<(rw), DEC_BASE + 0x00000A7C */ + uint32_t isp_dec_debug_info_out; /*!<(ro), DEC_BASE + 0x00000A80 */ + uint32_t isp_dec_debug_0; /*!<(ro), DEC_BASE + 0x00000A84 */ + uint32_t isp_dec_debug_1; /*!<(ro), DEC_BASE + 0x00000A88 */ + uint32_t isp_dec_debug_2; /*!<(ro), DEC_BASE + 0x00000A8C */ + uint32_t isp_dec_debug_3; /*!<(ro), DEC_BASE + 0x00000A90 */ + uint32_t isp_dec_debug_4; /*!<(ro), DEC_BASE + 0x00000A94 */ + uint32_t isp_dec_debug_5; /*!<(ro), DEC_BASE + 0x00000A98 */ + uint32_t isp_dec_state_commit; /*!<(ro), DEC_BASE + 0x00000A9C */ + uint32_t isp_dec_debug_6; /*!<(ro), DEC_BASE + 0x00000AA0 */ + uint32_t isp_dec_debug_7; /*!<(ro), DEC_BASE + 0x00000AA4 */ + uint32_t isp_dec_tile_128_type_0; /*!<(ro), DEC_BASE + 0x00000AA8 */ + uint32_t isp_dec_tile_128_type_1; /*!<(ro), DEC_BASE + 0x00000AAC */ + uint32_t isp_dec_tile_128_type_2; /*!<(ro), DEC_BASE + 0x00000AB0 */ + uint32_t isp_dec_tile_128_type_3; /*!<(ro), DEC_BASE + 0x00000AB4 */ + uint32_t isp_dec_tile_256_type_0; /*!<(ro), DEC_BASE + 0x00000AB8 */ + uint32_t isp_dec_tile_256_type_1; /*!<(ro), DEC_BASE + 0x00000ABC */ + uint32_t isp_dec_tile_256_type_2; /*!<(ro), DEC_BASE + 0x00000AC0 */ + uint32_t isp_dec_tile_256_type_3; /*!<(ro), DEC_BASE + 0x00000AC4 */ + uint32_t isp_dec_tile_256_type_4; /*!<(ro), DEC_BASE + 0x00000AC8 */ + uint32_t isp_dec_tile_256_type_5; /*!<(ro), DEC_BASE + 0x00000ACC */ + uint32_t isp_dec_tile_256_type_6; /*!<(ro), DEC_BASE + 0x00000AD0 */ + uint32_t isp_dec_tile_256_type_7; /*!<(ro), DEC_BASE + 0x00000AD4 */ + uint32_t isp_dec_debug_read_gate_domain_clk_counter; /*!<(ro), DEC_BASE + 0x00000AD8 */ + uint32_t isp_dec_debug_write_gate_domain_clk_counter; /*!<(ro), DEC_BASE + 0x00000ADC */ + uint32_t isp_dec_debug_other_gate_domain_clk_counter; /*!<(ro), DEC_BASE + 0x00000AE0 */ + uint32_t isp_dec_fast_clear_value_0; /*!<(rw), DEC_BASE + 0x00000B00 */ + uint32_t isp_dec_fast_clear_value_1; /*!<(rw), DEC_BASE + 0x00000B04 */ + uint32_t isp_dec_fast_clear_value_2; /*!<(rw), DEC_BASE + 0x00000B08 */ + uint32_t isp_dec_fast_clear_value_3; /*!<(rw), DEC_BASE + 0x00000B0C */ + uint32_t isp_dec_fast_clear_value_4; /*!<(rw), DEC_BASE + 0x00000B10 */ + uint32_t isp_dec_fast_clear_value_5; /*!<(rw), DEC_BASE + 0x00000B14 */ + uint32_t isp_dec_fast_clear_value_6; /*!<(rw), DEC_BASE + 0x00000B18 */ + uint32_t isp_dec_fast_clear_value_7; /*!<(rw), DEC_BASE + 0x00000B1C */ + uint32_t isp_dec_fast_clear_value_8; /*!<(rw), DEC_BASE + 0x00000B20 */ + uint32_t isp_dec_fast_clear_value_9; /*!<(rw), DEC_BASE + 0x00000B24 */ + uint32_t isp_dec_fast_clear_value_10; /*!<(rw), DEC_BASE + 0x00000B28 */ + uint32_t isp_dec_fast_clear_value_11; /*!<(rw), DEC_BASE + 0x00000B2C */ + uint32_t isp_dec_fast_clear_value_12; /*!<(rw), DEC_BASE + 0x00000B30 */ + uint32_t isp_dec_fast_clear_value_13; /*!<(rw), DEC_BASE + 0x00000B34 */ + uint32_t isp_dec_fast_clear_value_14; /*!<(rw), DEC_BASE + 0x00000B38 */ + uint32_t isp_dec_fast_clear_value_15; /*!<(rw), DEC_BASE + 0x00000B3C */ + uint32_t isp_dec_fast_clear_value_16; /*!<(rw), DEC_BASE + 0x00000B40 */ + uint32_t isp_dec_fast_clear_value_17; /*!<(rw), DEC_BASE + 0x00000B44 */ + uint32_t isp_dec_fast_clear_value_18; /*!<(rw), DEC_BASE + 0x00000B48 */ + uint32_t isp_dec_fast_clear_value_19; /*!<(rw), DEC_BASE + 0x00000B4C */ + uint32_t isp_dec_fast_clear_value_20; /*!<(rw), DEC_BASE + 0x00000B50 */ + uint32_t isp_dec_fast_clear_value_21; /*!<(rw), DEC_BASE + 0x00000B54 */ + uint32_t isp_dec_fast_clear_value_22; /*!<(rw), DEC_BASE + 0x00000B58 */ + uint32_t isp_dec_fast_clear_value_23; /*!<(rw), DEC_BASE + 0x00000B5C */ + uint32_t isp_dec_fast_clear_value_24; /*!<(rw), DEC_BASE + 0x00000B60 */ + uint32_t isp_dec_fast_clear_value_25; /*!<(rw), DEC_BASE + 0x00000B64 */ + uint32_t isp_dec_fast_clear_value_26; /*!<(rw), DEC_BASE + 0x00000B68 */ + uint32_t isp_dec_fast_clear_value_27; /*!<(rw), DEC_BASE + 0x00000B6C */ + uint32_t isp_dec_fast_clear_value_28; /*!<(rw), DEC_BASE + 0x00000B70 */ + uint32_t isp_dec_fast_clear_value_29; /*!<(rw), DEC_BASE + 0x00000B74 */ + uint32_t isp_dec_fast_clear_value_30; /*!<(rw), DEC_BASE + 0x00000B78 */ + uint32_t isp_dec_fast_clear_value_31; /*!<(rw), DEC_BASE + 0x00000B7C */ + uint32_t isp_dec_fast_clear_value_ex_0; /*!<(rw), DEC_BASE + 0x00000B80 */ + uint32_t isp_dec_fast_clear_value_ex_1; /*!<(rw), DEC_BASE + 0x00000B84 */ + uint32_t isp_dec_fast_clear_value_ex_2; /*!<(rw), DEC_BASE + 0x00000B88 */ + uint32_t isp_dec_fast_clear_value_ex_3; /*!<(rw), DEC_BASE + 0x00000B8C */ + uint32_t isp_dec_fast_clear_value_ex_4; /*!<(rw), DEC_BASE + 0x00000B90 */ + uint32_t isp_dec_fast_clear_value_ex_5; /*!<(rw), DEC_BASE + 0x00000B94 */ + uint32_t isp_dec_fast_clear_value_ex_6; /*!<(rw), DEC_BASE + 0x00000B98 */ + uint32_t isp_dec_fast_clear_value_ex_7; /*!<(rw), DEC_BASE + 0x00000B9C */ + uint32_t isp_dec_fast_clear_value_ex_8; /*!<(rw), DEC_BASE + 0x00000BA0 */ + uint32_t isp_dec_fast_clear_value_ex_9; /*!<(rw), DEC_BASE + 0x00000BA4 */ + uint32_t isp_dec_fast_clear_value_ex_10; /*!<(rw), DEC_BASE + 0x00000BA8 */ + uint32_t isp_dec_fast_clear_value_ex_11; /*!<(rw), DEC_BASE + 0x00000BAC */ + uint32_t isp_dec_fast_clear_value_ex_12; /*!<(rw), DEC_BASE + 0x00000BB0 */ + uint32_t isp_dec_fast_clear_value_ex_13; /*!<(rw), DEC_BASE + 0x00000BB4 */ + uint32_t isp_dec_fast_clear_value_ex_14; /*!<(rw), DEC_BASE + 0x00000BB8 */ + uint32_t isp_dec_fast_clear_value_ex_15; /*!<(rw), DEC_BASE + 0x00000BBC */ + uint32_t isp_dec_fast_clear_value_ex_16; /*!<(rw), DEC_BASE + 0x00000BC0 */ + uint32_t isp_dec_fast_clear_value_ex_17; /*!<(rw), DEC_BASE + 0x00000BC4 */ + uint32_t isp_dec_fast_clear_value_ex_18; /*!<(rw), DEC_BASE + 0x00000BC8 */ + uint32_t isp_dec_fast_clear_value_ex_19; /*!<(rw), DEC_BASE + 0x00000BCC */ + uint32_t isp_dec_fast_clear_value_ex_20; /*!<(rw), DEC_BASE + 0x00000BD0 */ + uint32_t isp_dec_fast_clear_value_ex_21; /*!<(rw), DEC_BASE + 0x00000BD4 */ + uint32_t isp_dec_fast_clear_value_ex_22; /*!<(rw), DEC_BASE + 0x00000BD8 */ + uint32_t isp_dec_fast_clear_value_ex_23; /*!<(rw), DEC_BASE + 0x00000BDC */ + uint32_t isp_dec_fast_clear_value_ex_24; /*!<(rw), DEC_BASE + 0x00000BE0 */ + uint32_t isp_dec_fast_clear_value_ex_25; /*!<(rw), DEC_BASE + 0x00000BE4 */ + uint32_t isp_dec_fast_clear_value_ex_26; /*!<(rw), DEC_BASE + 0x00000BE8 */ + uint32_t isp_dec_fast_clear_value_ex_27; /*!<(rw), DEC_BASE + 0x00000BEC */ + uint32_t isp_dec_fast_clear_value_ex_28; /*!<(rw), DEC_BASE + 0x00000BF0 */ + uint32_t isp_dec_fast_clear_value_ex_29; /*!<(rw), DEC_BASE + 0x00000BF4 */ + uint32_t isp_dec_fast_clear_value_ex_30; /*!<(rw), DEC_BASE + 0x00000BF8 */ + uint32_t isp_dec_fast_clear_value_ex_31; /*!<(rw), DEC_BASE + 0x00000BFC */ + +} MrvDecAllRegister_t; + +/*! Register: isp_dec_ctrl (DEC_BASE + 0x00000000)*/ +/*! Slice: isp_dec_ctrl_flush:*/ +#define DEC_CTRL_FLUSH +#define DEC_CTRL_FLUSH_MASK 0x00000001U +#define DEC_CTRL_FLUSH_SHIFT 0U + +/*! Slice: isp_dec_ctrl_disable_compression:*/ +#define DEC_CTRL_DISABLE_COMPRESSION +#define DEC_CTRL_DISABLE_COMPRESSION_MASK 0x00000002U +#define DEC_CTRL_DISABLE_COMPRESSION_SHIFT 1U + +/*! Slice: isp_dec_ctrl_disable_ram_clock_gating:*/ +#define DEC_CTRL_DISABLE_RAM_CLOCK_GATING +#define DEC_CTRL_DISABLE_RAM_CLOCK_GATING_MASK 0x00000004U +#define DEC_CTRL_DISABLE_RAM_CLOCK_GATING_SHIFT 2U + +/*! Slice: isp_dec_ctrl_disable_debug_registers:*/ +#define DEC_CTRL_DISABLE_DEBUG_REGISTERS +#define DEC_CTRL_DISABLE_DEBUG_REGISTERS_MASK 0x00000008U +#define DEC_CTRL_DISABLE_DEBUG_REGISTERS_SHIFT 3U + +/*! Slice: isp_dec_ctrl_soft_reset:*/ +#define DEC_CTRL_SOFT_RESET +#define DEC_CTRL_SOFT_RESET_MASK 0x00000010U +#define DEC_CTRL_SOFT_RESET_SHIFT 4U + +/*! Slice: isp_dec_ctrl_flush_dcache:*/ +#define DEC_CTRL_FLUSH_DCACHE +#define DEC_CTRL_FLUSH_DCACHE_MASK 0x00000040U +#define DEC_CTRL_FLUSH_DCACHE_SHIFT 6U + +/*! Slice: isp_dec_ctrl_disable_dcache:*/ +#define DEC_CTRL_DISABLE_DCACHE +#define DEC_CTRL_DISABLE_DCACHE_MASK 0x00000080U +#define DEC_CTRL_DISABLE_DCACHE_SHIFT 7U + +/*! Slice: isp_dec_ctrl_disable_hw_flush:*/ +#define DEC_CTRL_DISABLE_HW_FLUSH +#define DEC_CTRL_DISABLE_HW_FLUSH_MASK 0x00010000U +#define DEC_CTRL_DISABLE_HW_FLUSH_SHIFT 16U + +/*! Slice: isp_dec_ctrl_clk_dis:*/ +#define DEC_CTRL_CLK_DIS +#define DEC_CTRL_CLK_DIS_MASK 0x00FC0000U +#define DEC_CTRL_CLK_DIS_SHIFT 17U + +/*! Slice: isp_dec_ctrl_sw_flush_id:*/ +#define DEC_CTRL_SW_FLUSH_ID +#define DEC_CTRL_SW_FLUSH_ID_MASK 0x00020000U +#define DEC_CTRL_SW_FLUSH_ID_SHIFT 18U + +/*! Slice: isp_dec_ctrl_disable_cache_prefetch:*/ +#define DEC_CTRL_DISABLE_CACHE_PREFETCH +#define DEC_CTRL_DISABLE_CACHE_PREFETCH_MASK 0x02000000U +#define DEC_CTRL_DISABLE_CACHE_PREFETCH_SHIFT 25U + +/*! Slice: isp_dec_ctrl_hw_update_shadow_reg_mode:*/ +#define DEC_CTRL_HW_UPDATE_SHADOW_REG_MODE +#define DEC_CTRL_HW_UPDATE_SHADOW_REG_MODE_MASK 0x10000000U +#define DEC_CTRL_HW_UPDATE_SHADOW_REG_MODE_SHIFT 28U + +/*! Slice: isp_dec_ctrl_soft_update_shadow_reg:*/ +#define DEC_CTRL_SOFT_UPDATE_SHADOW_REG +#define DEC_CTRL_SOFT_UPDATE_SHADOW_REG_MASK 0x20000000U +#define DEC_CTRL_SOFT_UPDATE_SHADOW_REG_SHIFT 29U + +/*! Slice: isp_dec_ctrl_disable_module_clock_gating:*/ +#define DEC_CTRL_DISABLE_MODULE_CLOCK_GATING +#define DEC_CTRL_DISABLE_MODULE_CLOCK_GATING_MASK 0x40000000U +#define DEC_CTRL_DISABLE_MODULE_CLOCK_GATING_SHIFT 30U + +/*! Slice: isp_dec_ctrl_disable_global_clock_gating:*/ +#define DEC_CTRL_DISABLE_GLOBAL_CLOCK_GATING +#define DEC_CTRL_DISABLE_GLOBAL_CLOCK_GATING_MASK 0x80000000U +#define DEC_CTRL_DISABLE_GLOBAL_CLOCK_GATING_SHIFT 31U + +/*! Register: isp_dec_ctrl_ex (DEC_BASE + 0x00000004)*/ +/*! Slice: isp_dec_ctrl_ex_enable_burst_split:*/ +#define DEC_CTRL_EX_ENABLE_BURST_SPLIT +#define DEC_CTRL_EX_ENABLE_BURST_SPLIT_MASK 0x00010000U +#define DEC_CTRL_EX_ENABLE_BURST_SPLIT_SHIFT 16U + +/*! Slice: isp_dec_ctrl_ex_enable_end_address_check:*/ +#define DEC_CTRL_EX_ENABLE_END_ADDRESS_RANGE_CHECK +#define DEC_CTRL_EX_ENABLE_END_ADDRESS_RANGE_CHECK_MASK 0x00020000U +#define DEC_CTRL_EX_ENABLE_END_ADDRESS_RANGE_CHECK_SHIFT 17U + +/*! Slice: isp_dec_ctrl_ex_write_miss_policy:*/ +#define DEC_CTRL_EX_WRITE_MISS_POLICY +#define DEC_CTRL_EX_WRITE_MISS_POLICY_MASK 0x00080000U +#define DEC_CTRL_EX_WRITE_MISS_POLICY_SHIFT 19U + +/*! Slice: isp_dec_ctrl_ex_read_miss_policy:*/ +#define DEC_CTRL_EX_READ_MISS_POLICY +#define DEC_CTRL_EX_READ_MISS_POLICY_MASK 0x20000000U +#define DEC_CTRL_EX_READ_MISS_POLICY_SHIFT 29U + +/*! Register: isp_dec_ctrl_ex2 (DEC_BASE + 0x00000008)*/ +/*! Slice: isp_dec_ctrl_ex2_tile_status_read_id:*/ +#define DEC_CTRL_EX2_TILE_STATUS_READ_ID +#define DEC_CTRL_EX2_TILE_STATUS_READ_ID_MASK 0x0000007FU +#define DEC_CTRL_EX2_TILE_STATUS_READ_ID_SHIFT 0U + +/*! Slice: isp_dec_ctrl_ex2_tile_status_write_id:*/ +#define DEC_CTRL_EX2_TILE_STATUS_WRITE_ID +#define DEC_CTRL_EX2_TILE_STATUS_WRITE_ID_MASK 0x0003F80U +#define DEC_CTRL_EX2_TILE_STATUS_WRITE_ID_SHIFT 7U + +/*! Register: isp_dec_intr_enbl (DEC_BASE + 0x0000000C)*/ +/*! Slice: isp_dec_intr_enbl_vec:*/ +#define DEC_INTR_ENBL_VEC +#define DEC_INTR_ENBL_VEC_MASK 0xFFFFFFFFU +#define DEC_INTR_ENBL_VEC_SHIFT 0U + +/*! Register: isp_dec_intr_enbl_ex (DEC_BASE + 0x00000010)*/ +/*! Slice: isp_dec_intr_enbl_ex_vec:*/ +#define DEC_INTR_ENBL_EX_VEC +#define DEC_INTR_ENBL_EX_VEC_MASK 0xFFFFFFFFU +#define DEC_INTR_ENBL_EX_VEC_SHIFT 0U + +/*! Register: isp_dec_intr_enbl_ex2 (DEC_BASE + 0x00000014)*/ +/*! Slice: isp_dec_intr_enbl_ex2_vec:*/ +#define DEC_INTR_ENBL_EX2_VEC +#define DEC_INTR_ENBL_EX2_VEC_MASK 0xFFFFFFFFU +#define DEC_INTR_ENBL_EX2_VEC_SHIFT 0U + +/*! Register: isp_dec_read_config (DEC_BASE + 0x00000080)*/ +/*! Slice: isp_dec_read_config_compression_enable:*/ +#define DEC_READ_CONFIG_COMPRESSION_ENABLE +#define DEC_READ_CONFIG_COMPRESSION_ENABLE_MASK 0x00000001U +#define DEC_READ_CONFIG_COMPRESSION_ENABLE_SHIFT 0U + +/*! Slice: isp_dec_read_config_compression_format:*/ +#define DEC_READ_CONFIG_COMPRESSION_FORMAT +#define DEC_READ_CONFIG_COMPRESSION_FORMAT_MASK 0x000000F8U +#define DEC_READ_CONFIG_COMPRESSION_FORMAT_SHIFT 3U + +/*! Slice: isp_dec_read_config_compression_align_mode:*/ +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE_MASK 0x00030000U +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE_SHIFT 16U + +/*! Slice: isp_dec_read_config_compression_align_mode1:*/ +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE1 +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE1_MASK 0x001C0000U +#define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE1_SHIFT 18U + +/*! Slice: isp_dec_read_config_tile_mode:*/ +#define DEC_READ_CONFIG_TILE_MODE +#define DEC_READ_CONFIG_TILE_MODE_MASK 0x7E000000U +#define DEC_READ_CONFIG_TILE_MODE_SHIFT 25U + +/*! Register: isp_dec_read_ex_config (DEC_BASE + 0x00000100)*/ +/*! Slice: isp_dec_read_ex_config_bit_depth:*/ +#define DEC_READ_EX_CONFIG_BIT_DEPTH +#define DEC_READ_EX_CONFIG_BIT_DEPTH_MASK 0x00070000U +#define DEC_READ_EX_CONFIG_BIT_DEPTH_SHIFT 16U + +/*! Slice: isp_dec_read_ex_config_tile_y:*/ +#define DEC_READ_EX_CONFIG_TILE_Y +#define DEC_READ_EX_CONFIG_TILE_Y_MASK 0x00080000U +#define DEC_READ_EX_CONFIG_TILE_Y_SHIFT 19U + +/*! Register: isp_dec_write_config (DEC_BASE + 0x00000180)*/ +/*! Slice: isp_dec_write_config_compression_enable:*/ +#define DEC_WRITE_CONFIG_COMPRESSION_ENABLE +#define DEC_WRITE_CONFIG_COMPRESSION_ENABLE_MASK 0x00000001U +#define DEC_WRITE_CONFIG_COMPRESSION_ENABLE_SHIFT 0U + +/*! Slice: isp_dec_write_config_compression_format:*/ +#define DEC_WRITE_CONFIG_COMPRESSION_FORMAT +#define DEC_WRITE_CONFIG_COMPRESSION_FORMAT_MASK 0x000000F8U +#define DEC_WRITE_CONFIG_COMPRESSION_FORMAT_SHIFT 3U + +/*! Slice: isp_dec_write_config_compression_align_mode:*/ +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE_MASK 0x00030000U +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE_SHIFT 16U + +/*! Slice: isp_dec_write_config_compression_align_mode1:*/ +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE1 +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE1_MASK 0x001C0000U +#define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE1_SHIFT 18U + +/*! Slice: isp_dec_write_config_tile_mode:*/ +#define DEC_WRITE_CONFIG_TILE_MODE +#define DEC_WRITE_CONFIG_TILE_MODE_MASK 0x7E000000U +#define DEC_WRITE_CONFIG_TILE_MODE_SHIFT 25U + +/*! Register: isp_dec_write_ex_config (DEC_BASE + 0x00000200)*/ +/*! Slice: isp_dec_write_ex_config_bit_depth:*/ +#define DEC_WRITE_EX_CONFIG_BIT_DEPTH +#define DEC_WRITE_EX_CONFIG_BIT_DEPTH_MASK 0x00070000U +#define DEC_WRITE_EX_CONFIG_BIT_DEPTH_SHIFT 16U + +/*! Slice: isp_dec_write_ex_config_tile_y:*/ +#define DEC_WRITE_EX_CONFIG_TILE_Y +#define DEC_WRITE_EX_CONFIG_TILE_Y_MASK 0x00080000U +#define DEC_WRITE_EX_CONFIG_TILE_Y_SHIFT 19U + +/*! Register: isp_dec_read_buffer_base (DEC_BASE + 0x00000280)*/ +/*! Slice: isp_dec_read_buffer_base:*/ +#define DEC_READ_BUFFER_BASE +#define DEC_READ_BUFFER_BASE_MASK 0xFFFFFFFFU +#define DEC_READ_BUFFER_BASE_SHIFT 0U + +/*! Register: isp_dec_read_buffer_base_ex (DEC_BASE + 0x00000300)*/ +/*! Slice: isp_dec_read_buffer_base_ex:*/ +#define DEC_READ_BUFFER_BASE_EX +#define DEC_READ_BUFFER_BASE_EX_MASK 0x000000FFU +#define DEC_READ_BUFFER_BASE_EX_SHIFT 0U + +/*! Register: isp_dec_read_buffer_end (DEC_BASE + 0x00000380)*/ +/*! Slice: isp_dec_read_buffer_end:*/ +#define DEC_READ_BUFFER_END +#define DEC_READ_BUFFER_END_MASK 0xFFFFFFFFU +#define DEC_READ_BUFFER_END_SHIFT 0U + +/*! Register: isp_dec_read_buffer_end_ex (DEC_BASE + 0x00000400)*/ +/*! Slice: isp_dec_read_buffer_end_ex:*/ +#define DEC_READ_BUFFER_END_EX +#define DEC_READ_BUFFER_END_EX_MASK 0x000000FFU +#define DEC_READ_BUFFER_END_EX_SHIFT 0U + +/*! Register: isp_dec_read_flush_cache (DEC_BASE + 0x00000480)*/ +/*! Slice: isp_dec_read_flush_cache:*/ +#define DEC_READ_FLUSH_CACHE +#define DEC_READ_FLUSH_CACHE_MASK 0xFFFFFFFFU +#define DEC_READ_FLUSH_CACHE_SHIFT 0U + +/*! Register: isp_dec_read_flush_cache_ex (DEC_BASE + 0x00000500)*/ +/*! Slice: isp_dec_read_flush_cache_ex:*/ +#define DEC_READ_FLUSH_CACHE_EX +#define DEC_READ_FLUSH_CACHE_EX_MASK 0xFFFFFFFFU +#define DEC_READ_FLUSH_CACHE_EX_SHIFT 0U + +/*! Register: isp_dec_write_buffer_base (DEC_BASE + 0x00000580)*/ +/*! Slice: isp_dec_write_buffer_base:*/ +#define DEC_WRITE_BUFFER_BASE +#define DEC_WRITE_BUFFER_BASE_MASK 0xFFFFFFFFU +#define DEC_WRITE_BUFFER_BASE_SHIFT 0U + +/*! Register: isp_dec_write_buffer_base_ex (DEC_BASE + 0x00000600)*/ +/*! Slice: isp_dec_write_buffer_base_ex:*/ +#define DEC_WRITE_BUFFER_BASE_EX +#define DEC_WRITE_BUFFER_BASE_EX_MASK 0x000000FFU +#define DEC_WRITE_BUFFER_BASE_EX_SHIFT 0U + +/*! Register: isp_dec_write_buffer_end (DEC_BASE + 0x00000680)*/ +/*! Slice: isp_dec_write_buffer_end:*/ +#define DEC_WRITE_BUFFER_END +#define DEC_WRITE_BUFFER_END_MASK 0xFFFFFFFFU +#define DEC_WRITE_BUFFER_END_SHIFT 0U + +/*! Register: isp_dec_write_buffer_end_ex (DEC_BASE + 0x00000700)*/ +/*! Slice: isp_dec_write_buffer_end_ex:*/ +#define DEC_WRITE_BUFFER_END_EX +#define DEC_WRITE_BUFFER_END_EX_MASK 0x000000FFU +#define DEC_WRITE_BUFFER_END_EX_SHIFT 0U + +/*! Register: isp_dec_write_flush_cache (DEC_BASE + 0x00000780)*/ +/*! Slice: isp_dec_write_flush_cache:*/ +#define DEC_WRITE_FLUSH_CACHE +#define DEC_WRITE_FLUSH_CACHE_MASK 0xFFFFFFFFU +#define DEC_WRITE_FLUSH_CACHE_SHIFT 0U + +/*! Register: isp_dec_write_flush_cache_ex (DEC_BASE + 0x00000800)*/ +/*! Slice: isp_dec_write_flush_cache_ex:*/ +#define DEC_WRITE_FLUSH_CACHE_EX +#define DEC_WRITE_FLUSH_CACHE_EX_MASK 0xFFFFFFFFU +#define DEC_WRITE_FLUSH_CACHE_EX_SHIFT 0U + +/*! Register: isp_dec_read_cache_base (DEC_BASE + 0x00000880)*/ +/*! Slice: isp_dec_read_cache_base:*/ +#define DEC_READ_CACHE_BASE +#define DEC_READ_CACHE_BASE_MASK 0xFFFFFFFFU +#define DEC_READ_CACHE_BASE_SHIFT 0U + +/*! Register: isp_dec_read_cache_base_ex (DEC_BASE + 0x00000900)*/ +/*! Slice: isp_dec_read_cache_base_ex:*/ +#define DEC_READ_CACHE_BASE_EX +#define DEC_READ_CACHE_BASE_EX_MASK 0xFFFFFFFFU +#define DEC_READ_CACHE_BASE_EX_SHIFT 0U + +/*! Register: isp_dec_write_cache_base (DEC_BASE + 0x00000980)*/ +/*! Slice: isp_dec_write_cache_base:*/ +#define DEC_WRITE_CACHE_BASE +#define DEC_WRITE_CACHE_BASE_MASK 0xFFFFFFFFU +#define DEC_WRITE_CACHE_BASE_SHIFT 0U + +/*! Register: isp_dec_write_cache_base_ex (DEC_BASE + 0x00000A00)*/ +/*! Slice: isp_dec_write_cache_base_ex:*/ +#define DEC_WRITE_CACHE_BASE_EX +#define DEC_WRITE_CACHE_BASE_EX_MASK 0xFFFFFFFFU +#define DEC_WRITE_CACHE_BASE_EX_SHIFT 0U + +#endif /* _MRV_DEC_DEC_ALL_REGS_H */ diff --git a/vvcam_ry/native/Makefile b/vvcam_ry/native/Makefile new file mode 100755 index 0000000..723477d --- /dev/null +++ b/vvcam_ry/native/Makefile @@ -0,0 +1,22 @@ +include Param.mk +all: + echo VERSION_CFG = $(VERSION_CFG) +# @cd gpio_i2c; make || exit $$?; cp vvcam_i2c.ko ../bin/ +# @cd csi; make || exit $$?; cp bm_csi.ko bm_visys.ko ../bin/ +# @cd sensor; make || exit $$?; cp vvcam_sensor.ko ../bin/ + @cd isp; make || exit $$?; cp vvcam_isp_ry.ko ../bin/ +# @cd soc; make || exit $$?; cp vvcam_soc.ko ../bin/ +# @cd dw200; make || exit $$?; cp vvcam_dw200.ko ../bin/ +# @cd dec400; make || exit $$?; cp vvcam_dec400.ko ../bin/ +# @cd vi_pre; make || exit $$?; cp vi_pre.ko ../bin/ +clean: +# @cd gpio_i2c; make clean +# @cd csi; make clean +# @cd sensor; make clean + @cd isp; make clean +# @cd soc; make clean +# @cd dw200; make clean +# @cd dec400; make clean +# @cd vi_pre; make clean +cleanall: + diff --git a/vvcam_ry/native/Param.mk b/vvcam_ry/native/Param.mk new file mode 100755 index 0000000..8c898e6 --- /dev/null +++ b/vvcam_ry/native/Param.mk @@ -0,0 +1,57 @@ +#VERSION_CFG := ISP8000NANO_V1802 +#KERNEL :=/opt/vsi_isp_kernel_tree/4.8.0-41-generic-x86/build +#KERNEL :=/lib/modules/$(shell uname -r)/build +KERNEL :=$(LINUX_DIR) +KERNEL_SRC :=$(KERNEL) + +EXTRA_CFLAGS += -DWITH_VVCAM +EXTRA_CFLAGS += -DWITH_VVCAM_DUAL + +EXTRA_CFLAGS += -DVVCSI0_BASE=0xDE200000 +EXTRA_CFLAGS += -DVVCSI1_BASE=0xDE300000 +EXTRA_CFLAGS += -DVVCSI_SIZE=0x00200000 + +EXTRA_CFLAGS += -DVVCAM_I2C0_BASE=0xDE3080f0 +EXTRA_CFLAGS += -DVVCAM_I2C1_BASE=0xDE3080f4 +EXTRA_CFLAGS += -DVVCAM_I2C_SIZE=0x00000004 + +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS0=8 +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS1=9 + + +ifeq ($(VERSION_CFG), ISP8000_V2009) +EXTRA_CFLAGS += -DVVISP0_BASE=0xDE600000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xDE700000 +else +EXTRA_CFLAGS += -DVVISP0_BASE=0xFFE4100000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xFFE4110000 +endif +EXTRA_CFLAGS += -DISP_REG_SIZE=0x00010000 + +EXTRA_CFLAGS += -DDWE_REG_BASE=0xFFE4130C00 +EXTRA_CFLAGS += -DDWE_REG_SIZE=0x00010000 +#EXTRA_CFLAGS += -DDWE_REG_RESET=0xffe4130000 +EXTRA_CFLAGS += -DVSE_REG_BASE=0xFFE4130000 +EXTRA_CFLAGS += -DVSE_REG_SIZE=0x00010000 +#EXTRA_CFLAGS += -DVSE_REG_RESET=0xffe4130000 + +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0xC0000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x1000000 + +EXTRA_CFLAGS += -DVVCTRL_BASE=0xDE308000 +EXTRA_CFLAGS += -DVVCTRL_SIZE=0x00001000 + +EXTRA_CFLAGS += -DISP_HW_NUMBER=1 +EXTRA_CFLAGS += -DUSE_FPGA +EXTRA_CFLAGS += -D$(VERSION_CFG) + +#SENSR0_TYPE := ov2775 +#SENSR1_TYPE := ov2775 +#SENSR0_TYPE := imx334 +#SENSR1_TYPE := imx334 + +SENSR0_TYPE := ov5693 +SENSR1_TYPE := ov5693 + +PLATFORM := gen6 + diff --git a/vvcam_ry/native/Param_base.mk b/vvcam_ry/native/Param_base.mk new file mode 100755 index 0000000..fbfea1b --- /dev/null +++ b/vvcam_ry/native/Param_base.mk @@ -0,0 +1,54 @@ +#VERSION_CFG := ISP8000NANO_V1802 +#KERNEL :=/opt/vsi_isp_kernel_tree/4.8.0-41-generic-x86/build +KERNEL :=/lib/modules/$(shell uname -r)/build + +EXTRA_CFLAGS += -DWITH_VVCAM +EXTRA_CFLAGS += -DWITH_VVCAM_DUAL + +EXTRA_CFLAGS += -DVVCSI0_BASE=0xDE200000 +EXTRA_CFLAGS += -DVVCSI1_BASE=0xDE300000 +EXTRA_CFLAGS += -DVVCSI_SIZE=0x00200000 + +EXTRA_CFLAGS += -DVVCAM_I2C0_BASE=0xDE3080f0 +EXTRA_CFLAGS += -DVVCAM_I2C1_BASE=0xDE3080f4 +EXTRA_CFLAGS += -DVVCAM_I2C_SIZE=0x00000004 + +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS0=8 +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS1=9 + + +ifeq ($(VERSION_CFG), ISP8000_V2009) +EXTRA_CFLAGS += -DVVISP0_BASE=0xDE600000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xDE700000 +else +EXTRA_CFLAGS += -DVVISP0_BASE=0xDE000000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xDE100000 +endif +EXTRA_CFLAGS += -DISP_REG_SIZE=0x00010000 + +EXTRA_CFLAGS += -DDWE_REG_BASE=0xDE380C00 +EXTRA_CFLAGS += -DDWE_REG_SIZE=0x00010000 +EXTRA_CFLAGS += -DDWE_REG_RESET=0xDE308250 +EXTRA_CFLAGS += -DVSE_REG_BASE=0xDE380000 +EXTRA_CFLAGS += -DVSE_REG_SIZE=0x00010000 +EXTRA_CFLAGS += -DVSE_REG_RESET=0xDE308250 + + +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0x10000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x10000000 + +EXTRA_CFLAGS += -DVVCTRL_BASE=0xDE308000 +EXTRA_CFLAGS += -DVVCTRL_SIZE=0x00001000 + +EXTRA_CFLAGS += -DISP_HW_NUMBER=1 +EXTRA_CFLAGS += -DUSE_FPGA +EXTRA_CFLAGS += -D$(VERSION_CFG) + +#SENSR0_TYPE := ov2775 +#SENSR1_TYPE := ov2775 + +SENSR0_TYPE := ov5693 +SENSR1_TYPE := ov5693 + +PLATFORM := gen6 + diff --git a/vvcam_ry/native/Param_thead_light.mk b/vvcam_ry/native/Param_thead_light.mk new file mode 100755 index 0000000..13f4477 --- /dev/null +++ b/vvcam_ry/native/Param_thead_light.mk @@ -0,0 +1,56 @@ +#VERSION_CFG := ISP8000NANO_V1802 +#KERNEL :=/opt/vsi_isp_kernel_tree/4.8.0-41-generic-x86/build +#KERNEL :=/lib/modules/$(shell uname -r)/build +KERNEL :=$(LINUX_DIR) + +EXTRA_CFLAGS += -DWITH_VVCAM +EXTRA_CFLAGS += -DWITH_VVCAM_DUAL + +EXTRA_CFLAGS += -DVVCSI0_BASE=0xDE200000 +EXTRA_CFLAGS += -DVVCSI1_BASE=0xDE300000 +EXTRA_CFLAGS += -DVVCSI_SIZE=0x00200000 + +EXTRA_CFLAGS += -DVVCAM_I2C0_BASE=0xDE3080f0 +EXTRA_CFLAGS += -DVVCAM_I2C1_BASE=0xDE3080f4 +EXTRA_CFLAGS += -DVVCAM_I2C_SIZE=0x00000004 + +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS0=8 +EXTRA_CFLAGS += -DVVSENSOR_I2C_BUS1=9 + + +ifeq ($(VERSION_CFG), ISP8000_V2009) +EXTRA_CFLAGS += -DVVISP0_BASE=0xDE600000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xDE700000 +else +EXTRA_CFLAGS += -DVVISP0_BASE=0xFFE4100000 +EXTRA_CFLAGS += -DVVISP1_BASE=0xFFE4110000 +endif +EXTRA_CFLAGS += -DISP_REG_SIZE=0x00010000 + +EXTRA_CFLAGS += -DDWE_REG_BASE=0xFFE4130C00 +EXTRA_CFLAGS += -DDWE_REG_SIZE=0x00010000 +#EXTRA_CFLAGS += -DDWE_REG_RESET=0xffe4130000 +EXTRA_CFLAGS += -DVSE_REG_BASE=0xFFE4130000 +EXTRA_CFLAGS += -DVSE_REG_SIZE=0x00010000 +#EXTRA_CFLAGS += -DVSE_REG_RESET=0xffe4130000 + +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0xD0000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x10000000 + +EXTRA_CFLAGS += -DVVCTRL_BASE=0xDE308000 +EXTRA_CFLAGS += -DVVCTRL_SIZE=0x00001000 + +EXTRA_CFLAGS += -DISP_HW_NUMBER=1 +EXTRA_CFLAGS += -DUSE_FPGA +EXTRA_CFLAGS += -D$(VERSION_CFG) + +#SENSR0_TYPE := ov2775 +#SENSR1_TYPE := ov2775 +#SENSR0_TYPE := imx334 +#SENSR1_TYPE := imx334 + +SENSR0_TYPE := ov5693 +SENSR1_TYPE := ov5693 + +PLATFORM := gen6 + diff --git a/vvcam_ry/native/bin/insmod.sh b/vvcam_ry/native/bin/insmod.sh new file mode 100755 index 0000000..09b5b2a --- /dev/null +++ b/vvcam_ry/native/bin/insmod.sh @@ -0,0 +1,11 @@ +#!/bin/sh +#insmod vvcam_i2c.ko +insmod vvcam_sensor.ko +#insmod vvcam_csi.ko +insmod bm_visys.ko +insmod bm_csi.ko +insmod vvcam_isp.ko +insmod vvcam_soc.ko +insmod vvcam_dw200.ko +insmod vi_pre.ko +insmod vvcam_isp_ry.ko diff --git a/vvcam_ry/native/bin/rmmod.sh b/vvcam_ry/native/bin/rmmod.sh new file mode 100755 index 0000000..d6a9cc6 --- /dev/null +++ b/vvcam_ry/native/bin/rmmod.sh @@ -0,0 +1,9 @@ +#!/bin/sh +rmmod vvcam_dw200.ko +rmmod vvcam_soc +rmmod vvcam_isp +rmmod vvcam_sensor +rmmod vvcam_csi +rmmod vvcam_i2c +rmmod vi_pre +rmmod vvcam_isp_ry diff --git a/vvcam_ry/native/csi/Makefile b/vvcam_ry/native/csi/Makefile new file mode 100755 index 0000000..e291f03 --- /dev/null +++ b/vvcam_ry/native/csi/Makefile @@ -0,0 +1,23 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_csi + +#obj-m +=$(TARGET).o +# +#$(TARGET)-objs += csi_ioctl.o +#$(TARGET)-objs += ./nwl/platform_nwl_csi_driver.o +#$(TARGET)-objs += vvcam_csi_driver.o + +EXTRA_CFLAGS += -I$(PWD)/ +EXTRA_CFLAGS += -I$(PWD)/nwl/ + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) +# make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam_ry/native/csi/Makefilee b/vvcam_ry/native/csi/Makefilee new file mode 100755 index 0000000..c543904 --- /dev/null +++ b/vvcam_ry/native/csi/Makefilee @@ -0,0 +1,23 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_csi + +obj-m +=$(TARGET).o + +$(TARGET)-objs += csi_ioctl.o +$(TARGET)-objs += ./nwl/platform_nwl_csi_driver.o +$(TARGET)-objs += vvcam_csi_driver.o + +EXTRA_CFLAGS += -I$(PWD)/ +EXTRA_CFLAGS += -I$(PWD)/nwl/ + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + # make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam_ry/native/csi/bm_csi_dphy.c b/vvcam_ry/native/csi/bm_csi_dphy.c new file mode 100755 index 0000000..6bcc5b5 --- /dev/null +++ b/vvcam_ry/native/csi/bm_csi_dphy.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "bm_printk.h" +#include "bm_csi_ioctl.h" +#include "bm_csi_hw.h" +#include "bm_csi_dphy.h" +#include "dw-dphy-rx.h" + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +#define REG_DPHY_OFFSET 0x40 + +int bm_csi_dphy_write_reg(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct bm_csi_reg_t reg; + check_retval(copy_from_user(®, args, sizeof(reg))); + struct dw_dphy_rx *dphy = drvdata->dphy; + + writel(reg.value, dphy->base_address + reg.offset); + bm_info("%s addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value); +} + +int bm_csi_dphy_init(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct dw_dphy_rx *dphy = drvdata->dphy; +/* + dphy->dphy_freq = 20000000; + dphy->phy_type = 1; + dphy->dphy_te_len = BIT12; + dphy->lanes_config = CTRL_4_LANES; + dphy->dphy_gen = GEN3; + dphy->max_lanes = CTRL_4_LANES; + dphy->lp_time = 1000; //ns + dphy->base_address = drvdata->base + REG_DPHY_OFFSET; + //dphy->dphy1_if_addr =visysreg + dw_dphy_reset(dphy); + dw_dphy_power_on(dphy); + dw_dphy_init(dphy); + */ + return 0; +} + +int bm_csi_dphy_uinit(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct dw_dphy_rx *dphy = &drvdata->dphy; + dw_dphy_reset(dphy); + dw_dphy_power_off(dphy); +} + +int bm_csi_dphy_reset(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct dw_dphy_rx *dphy = &drvdata->dphy; + dw_dphy_reset(dphy); +} diff --git a/vvcam_ry/native/csi/bm_csi_dphy.h b/vvcam_ry/native/csi/bm_csi_dphy.h new file mode 100755 index 0000000..cc3890b --- /dev/null +++ b/vvcam_ry/native/csi/bm_csi_dphy.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _BM_CSI_DPHY_H_ +#define _BM_CSI_DPHY_H_ + +#include + +int dw_dphy_rx_probe(struct platform_device *pdev, void __iomem *dphy1_if_addr); +int dw_dphy_rx_remove(struct platform_device *pdev); + +#endif /*_BM_CSI_DPHY_H_ */ + + diff --git a/vvcam_ry/native/csi/bm_csi_driver.c b/vvcam_ry/native/csi/bm_csi_driver.c new file mode 100755 index 0000000..d5d90dd --- /dev/null +++ b/vvcam_ry/native/csi/bm_csi_driver.c @@ -0,0 +1,331 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "bm_printk.h" +#include "bm_csi_ioctl.h" +#include "bm_csi_hw.h" +#include "bm_csi_dphy.h" +//#include "dw-csi-plat.h" + +#define BM_DRIVER_NAME "vivcsi" +#define BM_DRIVER_MAXCNT 3 + +static struct class *bm_driver_class; +static unsigned int bm_driver_major = 0; +static unsigned int bm_driver_minor = 0; +static unsigned int device_register_index = 0; + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +static unsigned int bm_csi_poll(struct file * filp, poll_table *wait) +{ + return 0; +} + +void bm_csi_work(struct work_struct *work) +{ +} + +irqreturn_t bm_csi_irq(int irq, void *dev_id) +{ + bm_info("enter %s\n", __func__); + return IRQ_HANDLED; +} + +static int bm_csi_open(struct inode * inode, struct file * file) +{ + struct bm_csi_drvdata *drvdata; + + bm_info("enter %s\n", __func__); + + drvdata = container_of(inode->i_cdev, struct bm_csi_drvdata, cdev); + file->private_data = drvdata; + + return 0; +}; + +static long bm_csi_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct bm_csi_drvdata *drvdata; + bm_info("enter %s\n", __func__); + + drvdata = file->private_data; + if (drvdata == NULL) { + bm_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + mutex_lock(&drvdata->mutex); + switch (cmd) { + case BMCSI_IOC_WRITE_REG: + ret = bm_csi_write_reg(drvdata, (void *)arg); + break; + case BMCSI_IOC_READ_REG: + ret = bm_csi_read_reg(drvdata, (void *)arg); + break; + case BMCSI_IOC_INIT: + ret = bm_csi_init(drvdata, (void *)arg); + break; + case BMCSI_IOC_EXIT: + ret = bm_csi_exit(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_RESET: + ret = bm_csi_reset(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_POWER: + ret = bm_csi_set_power(drvdata, (void *)arg); + break; + case BMCSI_IOC_G_POWER: + ret = bm_csi_get_power(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_CLOCK: + ret = bm_csi_set_clock(drvdata, (void *)arg); + break; + case BMCSI_IOC_G_CLOCK: + ret = bm_csi_get_clock(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_STREAM: + ret = bm_csi_set_stream(drvdata, (void *)arg); + break; + case BMCSI_IOC_G_STREAM: + ret = bm_csi_get_stream(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_FMT: + ret = bm_csi_set_fmt(drvdata, (void *)arg); + break; + case BMCSI_IOC_G_FMT: + ret = bm_csi_get_fmt(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_VC_SELECT: + ret = bm_csi_set_vc_select(drvdata, (void *)arg); + break; + case BMCSI_IOC_G_VC_SELECT: + ret = bm_csi_get_vc_select(drvdata, (void *)arg); + break; + case BMCSI_IOC_S_LANE_CFG: + ret = bm_csi_set_lane_cfg(drvdata, (void *)arg); + break; + case BMCSI_IOC_MAX: + break; + default: + ret = -EPERM; + bm_err("%s: unsupported command %d", __func__, cmd); + break; + } + mutex_unlock(&drvdata->mutex); + return ret; +}; + +static int bm_csi_release(struct inode * inode, struct file * file) +{ + bm_info("enter %s\n", __func__); + return 0; +}; + +static int bm_csi_mmap(struct file *pFile, struct vm_area_struct *vma) +{ + bm_info("enter %s\n", __func__); + return 0; +}; + +struct file_operations bm_csi_fops = { + .owner = THIS_MODULE, + .open = bm_csi_open, + .release = bm_csi_release, + .unlocked_ioctl = bm_csi_ioctl, + .mmap = bm_csi_mmap, + .poll = bm_csi_poll, +}; + +static int bm_csi_probe(struct platform_device *pdev) +{ + int ret = 0; + struct bm_csi_drvdata *drvdata; + struct resource *iores_mem; + void __iomem *visys_addr; + + u32 value; + + bm_info("enter %s\n", __func__); + pdev->id = device_register_index; + if (pdev->id >= BM_DRIVER_MAXCNT) { + bm_err("%s:pdev id is %d error\n", __func__, pdev->id); + return -EINVAL; + } + + drvdata = devm_kzalloc(&pdev->dev,sizeof(struct bm_csi_drvdata), GFP_KERNEL); + if (drvdata == NULL) { + bm_err("%s:alloc struct drvdata error\n", __func__); + return -ENOMEM; + } + + iores_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + drvdata->base = devm_ioremap_resource(&pdev->dev, iores_mem); + bm_info("%s: [%s%d]: drvdata->base=0x%px, phy_addr base=0x%llx\n", __func__, + BM_DRIVER_NAME, pdev->id, drvdata->base, iores_mem->start); + drvdata->device_idx = pdev->id; + mutex_init(&drvdata->mutex); + drvdata->irq_num = platform_get_irq(pdev, 0); + bm_info("%s:[%s%d]: pdriver_dev->irq_num=%d\n", __func__, "BM_CSI", pdev->id, drvdata->irq_num); + + platform_set_drvdata(pdev, drvdata); + + if (pdev->id == 0) { + if (bm_driver_major == 0) { + ret = alloc_chrdev_region(&drvdata->devt, 0, BM_DRIVER_MAXCNT, BM_DRIVER_NAME); + if (ret != 0) { + bm_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + bm_driver_major = MAJOR(drvdata->devt); + bm_driver_minor = MINOR(drvdata->devt); + } else { + drvdata->devt = MKDEV(bm_driver_major, bm_driver_minor); + ret = register_chrdev_region(drvdata->devt, BM_DRIVER_MAXCNT, BM_DRIVER_NAME); + if (ret) { + bm_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + bm_driver_class = class_create(THIS_MODULE, BM_DRIVER_NAME); + if (IS_ERR(bm_driver_class)) { + bm_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + + drvdata->devt = MKDEV(bm_driver_major, bm_driver_minor + pdev->id); + cdev_init(&drvdata->cdev, &bm_csi_fops); + ret = cdev_add(&drvdata->cdev, drvdata->devt, 1); + if ( ret ) { + bm_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } else { + bm_info("%s[%d]:cdev_add OK, major=%d, minor=%d\n", __func__, __LINE__, + bm_driver_major, bm_driver_minor + pdev->id); + } + drvdata->class = bm_driver_class; + device_create(drvdata->class, NULL, drvdata->devt, + drvdata, "%s%d", BM_DRIVER_NAME, pdev->id); + + /*read version*/ + value = readl(drvdata->base + 0x0); + bm_info("offset=04, value is:0x%08x\n", value); + + //visys_addr = platform_get_resource(pdev, IORESOURCE_MEM, 1); + + visys_addr = devm_platform_ioremap_resource(pdev, 1); + dw_dphy_rx_probe(pdev, visys_addr); + + drvdata->reset = visys_addr; + dw_csi_probe(pdev); + + device_register_index++; + bm_info("exit %s:[%s%d]\n", __func__, BM_DRIVER_NAME, pdev->id); + + return 0; +} + +static int bm_csi_remove(struct platform_device *pdev) +{ + struct bm_csi_drvdata *drvdata; + + bm_info("enter %s\n", __func__); + dw_dphy_rx_remove(pdev); + dw_csi_remove(pdev); + + device_register_index--; + drvdata = platform_get_drvdata(pdev); + free_irq(drvdata->irq_num, drvdata); + cdev_del(&drvdata->cdev); + device_destroy(drvdata->class, drvdata->devt); + unregister_chrdev_region(drvdata->devt, BM_DRIVER_MAXCNT); + mutex_destroy(&drvdata->mutex); + if (device_register_index == 0) { + class_destroy(drvdata->class); + } + devm_kfree(&pdev->dev, drvdata); + + bm_info("exit %s\n", __func__); + return 0; +} + +static const struct of_device_id bm_csi_of_match[] = { + { .compatible = "thead,light-bm-csi", }, + { /* sentinel */ }, +}; + +static struct platform_driver bm_csi_driver = { + .probe = bm_csi_probe, + .remove = bm_csi_remove, + .driver = { + .name = BM_DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(bm_csi_of_match), + } +}; + +static int __init bm_csi_init_module(void) +{ + int ret = 0; + + bm_info("enter %s\n", __func__); + ret = platform_driver_register(&bm_csi_driver); + if (ret) { + bm_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit bm_csi_exit_module(void) +{ + bm_info("enter %s\n", __func__); + platform_driver_unregister(&bm_csi_driver); +} + +module_init(bm_csi_init_module); +module_exit(bm_csi_exit_module); + +MODULE_AUTHOR("Liu Yitong"); +MODULE_DESCRIPTION("BAREMETAL-CSI"); +MODULE_LICENSE("GPL"); diff --git a/vvcam_ry/native/csi/bm_csi_hw.c b/vvcam_ry/native/csi/bm_csi_hw.c new file mode 100755 index 0000000..fdc6c79 --- /dev/null +++ b/vvcam_ry/native/csi/bm_csi_hw.c @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "bm_printk.h" +#include "bm_csi_ioctl.h" +#include "bm_csi_hw.h" +#include "dw-dphy-rx.h" +#include "bm_csi_dphy.h" + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +int bm_csi_write_reg(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct bm_csi_reg_t reg; + check_retval(copy_from_user(®, args, sizeof(reg))); + writel(reg.value, drvdata->base + reg.offset); + bm_info("%s addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value); + return 0; +} + +int bm_csi_read_reg(struct bm_csi_drvdata *drvdata, void *__user args) +{ + struct bm_csi_reg_t reg; + check_retval(copy_from_user(®, args, sizeof(reg))); + reg.value = readl(drvdata->base + reg.offset); + check_retval(copy_to_user(args, ®, sizeof(reg))); + bm_info("%s addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value); + return 0; +} + +int bm_csi_init(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: csi init\n", __func__); + return 0; +} + +int bm_csi_exit(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: csi exit\n", __func__); + return 0; +} + +int bm_csi_reset(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: csi reset success\n", __func__); + dw_csi_soc_reset(drvdata->reset); + //bm_csi_dphy_reset(); + return 0; +} + +static int csi_power_on_sta = 0; +int bm_csi_set_power(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: csi set power\n", __func__); + check_retval(copy_from_user(&csi_power_on_sta, args, sizeof(csi_power_on_sta))); + dw_mipi_csi_s_power(&drvdata->csi_dev, csi_power_on_sta); + return 0; +} + +int bm_csi_get_power(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: csi get power\n", __func__); + check_retval(copy_to_user(args, &csi_power_on_sta, sizeof(csi_power_on_sta))); + return 0; +} + +int bm_csi_set_clock(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + check_retval(copy_to_user(args, &csi_power_on_sta, sizeof(csi_power_on_sta))); + return 0; +} + +int bm_csi_get_clock(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_set_stream(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_get_stream(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_set_fmt(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_get_fmt(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_set_vc_select(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_get_vc_select(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} + +int bm_csi_set_lane_cfg(struct bm_csi_drvdata *drvdata, void *__user args) +{ + bm_info("%s: \n", __func__); + return 0; +} diff --git a/vvcam_ry/native/csi/bm_csi_hw.h b/vvcam_ry/native/csi/bm_csi_hw.h new file mode 100755 index 0000000..caa7984 --- /dev/null +++ b/vvcam_ry/native/csi/bm_csi_hw.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _BM_CSI_HW_H_ +#define _BM_CSI_HW_H_ + +#include +#include +#include "dw-dphy-rx.h" +#include "dw-mipi-csi.h" +#include "dw-csi-data.h" +#include "dw-dphy-data.h" + +struct bm_csi_drvdata { + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex mutex; + unsigned int device_idx; + void __iomem *base; + void __iomem *reset; + struct dw_dphy_rx *dphy; + struct dw_csi csi_dev; + struct dw_csih_pdata csi_pdata; + struct dw_phy_pdata dphy_pdata; + int irq_num; + void *private; // can be bm_csi_drvdata_private, but not use now +}; + +struct bm_csi_drvdata_private { + int private_tmp; +}; + +int bm_csi_write_reg(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_read_reg(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_init(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_exit(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_reset(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_power(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_get_power(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_clock(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_get_clock(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_stream(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_get_stream(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_fmt(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_get_fmt(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_vc_select(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_get_vc_select(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_set_lane_cfg(struct bm_csi_drvdata *drvdata, void *__user args); + +/*csi dphy*/ +int bm_csi_dphy_write_reg(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_dphy_init(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_dphy_uinit(struct bm_csi_drvdata *drvdata, void *__user args); +int bm_csi_dphy_reset(struct bm_csi_drvdata *drvdata, void *__user args); + +void dw_csi_soc_reset(void __iomem *io_mem); +int dw_csi_probe(struct platform_device *pdev); +int dw_csi_remove(struct platform_device *pdev); + +#endif /* _BM_CSI_HW_H_*/ diff --git a/vvcam_ry/native/csi/bm_csi_ioctl.h b/vvcam_ry/native/csi/bm_csi_ioctl.h new file mode 100755 index 0000000..d0ef259 --- /dev/null +++ b/vvcam_ry/native/csi/bm_csi_ioctl.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: liuyitong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _BM_CSI_IOCTL_H_ +#define _BM_CSI_IOCTL_H_ + +#include + +enum { + BMCSI_IOC_S_RESET = _IO('r', 0), + BMCSI_IOC_S_POWER, + BMCSI_IOC_G_POWER, + BMCSI_IOC_S_CLOCK, + BMCSI_IOC_G_CLOCK, + BMCSI_IOC_S_STREAM, + BMCSI_IOC_G_STREAM, + BMCSI_IOC_S_FMT, + BMCSI_IOC_G_FMT, + BMCSI_IOC_S_VC_SELECT, + BMCSI_IOC_G_VC_SELECT, + BMCSI_IOC_S_LANE_CFG, + BMCSI_IOC_INIT, + BMCSI_IOC_EXIT, + BMCSI_IOC_WRITE_REG, + BMCSI_IOC_READ_REG, + BMCSI_IOC_MAX, +}; + +struct bm_csi_reg_t { + unsigned int offset; + unsigned int value; +}; + +#endif /* _BM_CSI_IOCTL_H_*/ diff --git a/vvcam_ry/native/csi/bm_printk.h b/vvcam_ry/native/csi/bm_printk.h new file mode 100755 index 0000000..4490bee --- /dev/null +++ b/vvcam_ry/native/csi/bm_printk.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: LuChongzhi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __BM_PRINTK__ +#define __BM_PRINTK__ + +#include +#include +#include +#include +#include + +/* + * These can be used to print at the various log levels. + * All of these will print unconditionally, although note that pr_debug() + * and other debug macros are compiled out unless either DEBUG is defined + * or CONFIG_DYNAMIC_DEBUG is set. + */ +#define bm_emerg(fmt, ...) \ + printk(KERN_EMERG pr_fmt(fmt), ##__VA_ARGS__) +#define bm_alert(fmt, ...) \ + printk(KERN_ALERT pr_fmt(fmt), ##__VA_ARGS__) +#define bm_crit(fmt, ...) \ + printk(KERN_CRIT pr_fmt(fmt), ##__VA_ARGS__) +#define bm_err(fmt, ...) \ + printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) +#define bm_warning(fmt, ...) \ + printk(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__) +#define bm_warn pr_warning + +#ifdef DEBUG +#define bm_notice(fmt, ...) \ + printk(KERN_NOTICE pr_fmt(fmt), ##__VA_ARGS__) +#define bm_info(fmt, ...) \ + printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__) +#else +#define bm_notice(fmt, ...) +#define bm_info(fmt, ...) +#endif + +#endif /* __BM_PRINTK__ */ diff --git a/vvcam_ry/native/csi/dphy_gen b/vvcam_ry/native/csi/dphy_gen new file mode 100755 index 0000000..e69de29 diff --git a/vvcam_ry/native/csi/dw-csi-data.h b/vvcam_ry/native/csi/dw-csi-data.h new file mode 100755 index 0000000..10015fd --- /dev/null +++ b/vvcam_ry/native/csi/dw-csi-data.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 platform data + * + * Author: Luis Oliveira + */ + +#include +#include "dw-mipi-csi-pltfrm.h" + +#ifndef __DW_CSI_DATA__ +#define __DW_CSI_DATA__ + +struct dw_csih_pdata { + u8 eotp_enabled; + u32 hs_freq; + u32 lanes; + u32 pclk; + u32 fps; + u32 bpp; + u8 id; +}; + +static const struct pdata_names csis[] = { + { .name = "dw-csi.0", }, + { .name = "dw-csi.1", }, +}; + +#endif /*__DW_CSI_DATA__ */ diff --git a/vvcam_ry/native/csi/dw-csi-plat.c b/vvcam_ry/native/csi/dw-csi-plat.c new file mode 100755 index 0000000..881a810 --- /dev/null +++ b/vvcam_ry/native/csi/dw-csi-plat.c @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 Host controller driver. + * Platform driver + * + * Author: Luis Oliveira + */ + +#include "dw-csi-data.h" +#include "dw-dphy-data.h" +#include "dw-csi-plat.h" + +#include "bm_csi_hw.h" + +const struct mipi_dt csi_dt[] = { + { + .hex = CSI_2_YUV420_8, + .name = "YUV420_8bits", + }, { + .hex = CSI_2_YUV420_10, + .name = "YUV420_10bits", + }, { + .hex = CSI_2_YUV420_8_LEG, + .name = "YUV420_8bits_LEGACY", + }, { + .hex = CSI_2_YUV420_8_SHIFT, + .name = "YUV420_8bits_SHIFT", + }, { + .hex = CSI_2_YUV420_10_SHIFT, + .name = "YUV420_10bits_SHIFT", + }, { + .hex = CSI_2_YUV422_8, + .name = "YUV442_8bits", + }, { + .hex = CSI_2_YUV422_10, + .name = "YUV442_10bits", + }, { + .hex = CSI_2_RGB444, + .name = "RGB444", + }, { + .hex = CSI_2_RGB555, + .name = "RGB555", + }, { + .hex = CSI_2_RGB565, + .name = "RGB565", + }, { + .hex = CSI_2_RGB666, + .name = "RGB666", + }, { + .hex = CSI_2_RGB888, + .name = "RGB888", + }, { + .hex = CSI_2_RAW6, + .name = "RAW6", + }, { + .hex = CSI_2_RAW7, + .name = "RAW7", + }, { + .hex = CSI_2_RAW8, + .name = "RAW8", + }, { + .hex = CSI_2_RAW10, + .name = "RAW10", + }, { + .hex = CSI_2_RAW12, + .name = "RAW12", + }, { + .hex = CSI_2_RAW14, + .name = "RAW14", + }, { + .hex = CSI_2_RAW16, + .name = "RAW16", + }, +}; + +static struct mipi_fmt * +find_dw_mipi_csi_format(uint32_t mbus_code) +{ + unsigned int i; + + pr_info("%s entered mbus: 0x%x\n", __func__, mbus_code); + + for (i = 0; i < ARRAY_SIZE(dw_mipi_csi_formats); i++) + if (mbus_code == dw_mipi_csi_formats[i].mbus_code) { + pr_info("Found mbus 0x%x\n", dw_mipi_csi_formats[i].mbus_code); + return &dw_mipi_csi_formats[i]; + } + return NULL; +} + +static int dw_mipi_csi_enum_mbus_code(int index, uint32_t *code) +{ + if (index != 0) + return -EINVAL; + + *code = dw_mipi_csi_formats[index].mbus_code; + return 0; +} + +static struct mipi_fmt * +dw_mipi_csi_try_format(uint32_t mbus_code) +{ + struct mipi_fmt *fmt; + + fmt = find_dw_mipi_csi_format(mbus_code); + if (!fmt) + fmt = &dw_mipi_csi_formats[0]; + + return fmt; +} + +struct mipi_fmt * +dw_mipi_csi_get_format(struct dw_csi *dev) +{ + dev_info(dev->dev, + "%s got v4l2_mbus_pixelcode. 0x%x\n", __func__, + dev->fmt->mbus_code); + dev_info(dev->dev, + "%s got width. 0x%x\n", __func__, + dev->fmt->width); + dev_info(dev->dev, + "%s got height. 0x%x\n", __func__, + dev->fmt->height); + return dev->fmt; +} + +static int +dw_mipi_csi_set_fmt(struct platform_device *pdev, + uint32_t mbus_code, uint32_t width, uint32_t height) +{ + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *dev = &drvdata->csi_dev; + + struct mipi_fmt *dev_fmt = NULL; + int i; + dev_info(dev->dev, + "%s got mbus_pixelcode. 0x%x\n", __func__, + mbus_code); + + dev_fmt = dw_mipi_csi_try_format(mbus_code); + + dev_info(dev->dev, + "%s got v4l2_mbus_pixelcode. 0x%x\n", __func__, + dev_fmt->mbus_code); + if (!dev_fmt) + return -EINVAL; + + if (dev_fmt) { + dev->fmt->mbus_code = dev_fmt->mbus_code; + dev->fmt->width = width; + dev->fmt->height = height; + dw_mipi_csi_set_ipi_fmt(dev); + } + dev_info(dev->dev, "Width: %d, Height: %d of Demo\n", width, height); + if (width > 0 && height > 0) { + dw_mipi_csi_fill_timings(dev, width, height); +/* + demo_writel(dev, + DEMO_ACTIVE_WIDTH, fmt->format.width); + demo_writel(dev, + DEMO_ACTIVE_HEIGHT, fmt->format.height); +*/ + dev_vdbg(dev->dev, + "(core/demosaic) : width=%d/%d, height=%d/%d\n", + dev->hw.htotal - (dev->hw.hbp + + dev->hw.hsd + + dev->hw.hsa), + width, + dev->hw.vactive, + height); + dev_info(dev->dev, + "(core/demosaic) : width=%d/%d, height=%d/%d\n", + dev->hw.htotal - (dev->hw.hbp + + dev->hw.hsd + + dev->hw.hsa), + width, + dev->hw.vactive, + height); + + } else { + dev_vdbg(dev->dev, "%s unacceptable values 0x%x.\n", + __func__, width); + dev_vdbg(dev->dev, "%s unacceptable values 0x%x.\n", + __func__, height); + dev_info(dev->dev, "%s unacceptable values 0x%x.\n", + __func__, width); + dev_info(dev->dev, "%s unacceptable values 0x%x.\n", + __func__, height); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(csi_dt); i++) + if (csi_dt[i].hex == dev->ipi_dt) { + dev_vdbg(dev->dev, "Using data type %s\n", + csi_dt[i].name); + dev_info(dev->dev, "Using data type %s\n", + csi_dt[i].name); + } + return 0; +} + +static int +dw_mipi_csi_get_fmt(struct platform_device *pdev, + struct mipi_fmt *fmt) +{ + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *dev = &drvdata->csi_dev; + + struct mipi_fmt *mf = dw_mipi_csi_get_format(dev); + if (!mf) + return -EINVAL; + + mutex_lock(&dev->lock); + *fmt = *mf; + mutex_unlock(&dev->lock); + + return 0; +} + +int dw_mipi_csi_s_power(struct dw_csi *dev, int on) +{ + dev_info(dev->dev, "%s: on=%d\n", __func__, on); + + if (on) { + dw_mipi_csi_hw_stdby(dev); + dw_mipi_csi_start(dev); + } else { + phy_power_off(dev->phy); + dw_mipi_csi_mask_irq_power_off(dev); + /* reset data type */ + dev->ipi_dt = 0x0; + } + return 0; +} + +int dw_mipi_csi_log_status(struct dw_csi *dev) +{ + dw_mipi_csi_dump(dev); + + return 0; +} + +#if IS_ENABLED(CONFIG_VIDEO_ADV_DEBUG) +int +dw_mipi_csi_g_register(struct v4l2_subdev *sd, uint32_t reg) +{ + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *dev = &drvdata->csi_dev; + + dev_vdbg(dev->dev, "%s: reg=%llu\n", __func__, reg); + reg->val = dw_mipi_csi_read(dev, reg); + + return 0; +} +#endif + +#if 0 +static int dw_mipi_csi_init_cfg(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg) +{ + struct v4l2_mbus_framefmt *format = + v4l2_subdev_get_try_format(sd, cfg, 0); + + format->colorspace = V4L2_COLORSPACE_SRGB; + format->code = MEDIA_BUS_FMT_RGB888_1X24; + format->field = V4L2_FIELD_NONE; + + return 0; +} +#endif + +static irqreturn_t dw_mipi_csi_irq1(int irq, void *dev_id) +{ + struct dw_csi *csi_dev = dev_id; + + dw_mipi_csi_irq_handler(csi_dev); + + return IRQ_HANDLED; +} + +void dw_csi_soc_reset(void __iomem *io_mem) +{ +#define VISYS_SW_RST 0x100 + uint32_t reg_val = 0; + reg_val = readl(io_mem + VISYS_SW_RST); + reg_val &= ~(1 << 16); + writel(reg_val, io_mem + VISYS_SW_RST); + reg_val |= 1 << 16; + writel(reg_val, io_mem + VISYS_SW_RST); +} + +static const struct of_device_id dw_mipi_csi_of_match[]; + +int dw_csi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dw_csi *csi; + struct dw_dphy_rx *dphy; + struct dw_csih_pdata *pdata; + struct bm_csi_drvdata *drvdata; + int ret; + + if (!IS_ENABLED(CONFIG_OF)) + + dev_vdbg(dev, "Probing started\n"); + + /* Resource allocation */ + drvdata = platform_get_drvdata(pdev); + + csi = &drvdata->csi_dev; + dphy = drvdata->dphy; + pdata = &drvdata->csi_pdata; + + mutex_init(&csi->lock); + spin_lock_init(&csi->slock); + csi->dev = dev; + + /*set csi phy*/ + csi->phy = dphy->phy; + csi->base_address = drvdata->base; + if (IS_ERR(csi->base_address)) { + dev_err(dev, "base address not set.\n"); + return PTR_ERR(csi->base_address); + } + + csi->ctrl_irq_number = drvdata->irq_num; + if (csi->ctrl_irq_number < 0) { + dev_err(dev, "irq number %d not set.\n", csi->ctrl_irq_number); + ret = csi->ctrl_irq_number; + goto end; + } + + ret = devm_request_irq(dev, csi->ctrl_irq_number, + dw_mipi_csi_irq1, IRQF_SHARED, + dev_name(dev), csi); + if (ret) { + dev_err(dev, "irq csi %d failed\n", pdata->id); + goto end; + } + + csi->fmt = &dw_mipi_csi_formats[0]; + csi->fmt->mbus_code = dw_mipi_csi_formats[0].mbus_code; +/* + to do pad init +*/ + csi->hw.num_lanes = pdata->lanes; + csi->hw.pclk = pdata->pclk; + csi->hw.fps = pdata->fps; + csi->hw.dphy_freq = pdata->hs_freq; + + //csi soc reset + dw_csi_soc_reset(drvdata->reset); + #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_csi_create_capabilities_sysfs(pdev); +#endif + dw_mipi_csi_get_version(csi); + dw_mipi_csi_specific_mappings(csi); + dw_mipi_csi_mask_irq_power_off(csi); + + dev_info(dev, "DW MIPI CSI-2 Host registered successfully HW v%u.%u\n", + csi->hw_version_major, csi->hw_version_minor); + + ret = phy_init(csi->phy); + if (ret) { + dev_err(&csi->phy->dev, "phy init failed --> %d\n", ret); + goto end; + } + + return 0; +end: + return ret; +} + +int dw_csi_remove(struct platform_device *pdev) +{ + struct bm_csi_drvdata *drvdata; + drvdata = platform_get_drvdata(pdev); + dw_csi_remove_capabilities_sysfs(pdev); + //struct dw_csi *mipi_csi = &drvdata->csi_dev; + //csi soc reset + dw_csi_soc_reset(drvdata->reset); + dev_info(&pdev->dev, "DW MIPI CSI-2 Host module removed\n"); + + return 0; +} + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Luis Oliveira "); +MODULE_DESCRIPTION("Synopsys DesignWare MIPI CSI-2 Host Platform driver"); diff --git a/vvcam_ry/native/csi/dw-csi-plat.h b/vvcam_ry/native/csi/dw-csi-plat.h new file mode 100755 index 0000000..cc8117b --- /dev/null +++ b/vvcam_ry/native/csi/dw-csi-plat.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 Synopsys, Inc. + * + * Synopsys DesignWare MIPI CSI-2 Host controller driver. + * Supported bus formats + * + * Author: Luis Oliveira + */ + +#ifndef _DW_CSI_PLAT_H__ +#define _DW_CSI_PLAT_H__ + +#include "dw-mipi-csi.h" + +/** Color Space Converter Block **/ +#define CSC_UNIT_NR 1 +#define CSC_COREID 0x0000 +#define CSC_CFG 0x0004 +#define CSC_COEF_A(x) (0x0008 + ((x) * 4)) +#define CSC_COEF_B(x) (0x0018 + ((x) * 4)) +#define CSC_COEF_C(x) (0x0028 + ((x) * 4)) +#define CSC_LIMIT_DN 0x0038 +#define CSC_LIMIT_UP 0x003C +#define CSC_VID_CFG 0x0040 + +/** Demosaic Block **/ +#define DEMO_CONTROL 0x0 +#define DEMO_GLOBAL_INT_EN 0x4 +#define DEMO_IP_INT_EN_REG 0x8 +#define DEMO_IP_INT_SATUS_REG 0xC +#define DEMO_ACTIVE_WIDTH 0x10 +#define DEMO_ACTIVE_HEIGHT 0x18 +#define DEMO_BAYER_PHASE 0x28//0x20 + +#define BAYER_RGGB 0x0 +#define BAYER_GRBG 0x1 +#define BAYER_GBRG 0x2 +#define BAYER_BGGR 0x3 + +/* Video formats supported by the MIPI CSI-2 */ +static struct mipi_fmt dw_mipi_csi_formats[] = { + { + /* RAW 8 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .depth = 8, + }, { + /* RAW 6 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR6_1X8, + .depth = 8, + }, { + /* RAW 7 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR7_1X8, + .depth = 8, + }, { + /* RAW 10 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .depth = 10, + }, { + /* RAW 8 */ + .mbus_code = 0x3001, + .depth = 8, + }, { + /* RAW 12 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .depth = 12, + }, { + /* RAW 14 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR14_1X14, + .depth = 14, + }, { + /* RAW 16 */ + .mbus_code = MEDIA_BUS_FMT_SBGGR16_1X16, + .depth = 16, + }, { + /* RGB 666 */ + .mbus_code = MEDIA_BUS_FMT_RGB666_1X18, + .depth = 18, + }, { + /* RGB 565 */ + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_BE, + .depth = 16, + }, { + /* BGR 565 */ + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, + .depth = 16, + }, { + /* RGB 555 */ + .mbus_code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, + .depth = 16, + }, { + /* BGR 555 */ + .mbus_code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, + .depth = 16, + }, { + /* RGB 444 */ + .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE, + .depth = 16, + }, { + /* RGB 444 */ + .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE, + .depth = 16, + }, { + /* RGB 888 */ + .mbus_code = MEDIA_BUS_FMT_RGB888_2X12_LE, + .depth = 24, + }, { + /* BGR 888 */ + .mbus_code = MEDIA_BUS_FMT_RGB888_2X12_BE, + .depth = 24, + }, { + /* BGR 888 */ + .mbus_code = MEDIA_BUS_FMT_RGB888_1X24, + .depth = 24, + }, { + /* YUV 422 8-bit */ + .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16, + .depth = 16, + }, { + /* YUV 422 10-bit */ + .mbus_code = MEDIA_BUS_FMT_UYVY10_1X20, + .depth = 24, + }, { + /* YUV 420 8-bit LEGACY */ + .mbus_code = MEDIA_BUS_FMT_Y8_1X8, + .depth = 8, + }, { + /* YUV 420 8-bit LEGACY */ + .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16, + .depth = 24, + }, { + /* YUV 420 10-bit */ + .mbus_code = MEDIA_BUS_FMT_VUY8_1X24, + .depth = 24, + }, { + /* YUV 420 8-bit */ + .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, + .depth = 24, + }, { + /* YUV 420 10-bit */ + .mbus_code = MEDIA_BUS_FMT_Y10_1X10, + .depth = 10, + }, +}; + +#endif /* _DW_CSI_PLAT_H__ */ diff --git a/vvcam_ry/native/csi/dw-csi-sysfs.c b/vvcam_ry/native/csi/dw-csi-sysfs.c new file mode 100755 index 0000000..7cbeca2 --- /dev/null +++ b/vvcam_ry/native/csi/dw-csi-sysfs.c @@ -0,0 +1,673 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 Host controller driver. + * SysFS components for the platform driver + * + * Author: Luis Oliveira + */ + +#include "dw-mipi-csi.h" +#include "bm_csi_hw.h" + +static ssize_t core_version_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "v.%d.%d*\n", csi_dev->hw_version_major, + csi_dev->hw_version_minor); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t n_lanes_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long lanes; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &lanes); + if (ret < 0) + return ret; + + if (lanes > 8) { + dev_err(dev, "Invalid number of lanes %lu\n", lanes); + return count; + } + + dev_info(dev, "Lanes %lu\n", lanes); + csi_dev->hw.num_lanes = lanes; + + return count; +} + +static ssize_t n_lanes_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.num_lanes); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t core_reset_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + /* Reset Controller and DPHY */ + phy_reset(csi_dev->phy); + dw_mipi_csi_reset(csi_dev); + + snprintf(buffer, 10, "Reset\n"); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t data_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long dt; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &dt); + if (ret < 0) + return ret; + + if (dt < 0x18 || dt > 0x2F) { + dev_err(dev, "Invalid data type %lx\n", dt); + return count; + } + + dev_info(dev, "Data type 0x%lx\n", dt); + csi_dev->ipi_dt = dt; + + dw_mipi_csi_set_ipi_fmt(csi_dev); + + return count; +} + +static ssize_t data_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->ipi_dt); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t hsa_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long hsa; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &hsa); + if (ret < 0) + return ret; + + if (hsa > 0xFFF) { + dev_err(dev, "Invalid HSA time %lx\n", hsa); + return count; + } + + dev_info(dev, "HSA time 0x%lx\n", hsa); + csi_dev->hw.hsa = hsa; + + return count; +} + +static ssize_t hsa_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.hsa); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t hbp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long hbp; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &hbp); + if (ret < 0) + return ret; + + if (hbp > 0xFFF) { + dev_err(dev, "Invalid HBP time %lx\n", hbp); + return count; + } + + dev_info(dev, "HBP time 0x%lx\n", hbp); + csi_dev->hw.hbp = hbp; + + return count; +} + +static ssize_t hbp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.hbp); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t hsd_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long hsd; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &hsd); + if (ret < 0) + return ret; + + if (hsd > 0xFFF) { + dev_err(dev, "Invalid HSD time %lx\n", hsd); + return count; + } + + dev_info(dev, "HSD time 0x%lx\n", hsd); + csi_dev->hw.hsd = hsd; + + return count; +} + +static ssize_t hsd_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.hsd); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t vsa_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long vsa; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &vsa); + if (ret < 0) + return ret; + + if (vsa > 0x3FF) { + dev_err(dev, "Invalid VSA period %lx\n", vsa); + return count; + } + + dev_info(dev, "VSA period 0x%lx\n", vsa); + csi_dev->hw.vsa = vsa; + + return count; +} + +static ssize_t vsa_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.vsa); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t vbp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long vbp; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &vbp); + if (ret < 0) + return ret; + + if (vbp > 0x2FF) { + dev_err(dev, "Invalid VBP period %lx\n", vbp); + return count; + } + + dev_info(dev, "VBP period 0x%lx\n", vbp); + csi_dev->hw.vbp = vbp; + + return count; +} + +static ssize_t vbp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.vbp); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t vfp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long vfp; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 16, &vfp); + if (ret < 0) + return ret; + + if (vfp > 0x3ff) { + dev_err(dev, "Invalid VFP period %lx\n", vfp); + return count; + } + + dev_info(dev, "VFP period 0x%lx\n", vfp); + csi_dev->hw.vfp = vfp; + + return count; +} + +static ssize_t vfp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%x\n", csi_dev->hw.vfp); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t virtual_channel_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long virtual_ch; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &virtual_ch); + if (ret < 0) + return ret; + + if ((signed int)virtual_ch < 0 || (signed int)virtual_ch > 8) { + dev_err(dev, "Invalid Virtual Channel %lu\n", virtual_ch); + return count; + } + + dev_info(dev, "Virtual Channel %lu\n", virtual_ch); + csi_dev->hw.virtual_ch = virtual_ch; + + return count; +} + +static ssize_t virtual_channel_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.virtual_ch); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t ipi_color_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long ipi_color_mode; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &ipi_color_mode); + if (ret < 0) + return ret; + + if ((signed int)ipi_color_mode < 0 || (signed int)ipi_color_mode > 1) { + dev_err(dev, + "Wrong Color Mode %lu, (48 bits -> 0 or 16 bits -> 1\n", + ipi_color_mode); + return count; + } + + dev_info(dev, "IPI Color mode %lu\n", ipi_color_mode); + csi_dev->hw.ipi_color_mode = ipi_color_mode; + + return count; +} + +static ssize_t ipi_color_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.ipi_color_mode); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t ipi_auto_flush_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long ipi_auto_flush; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &ipi_auto_flush); + if (ret < 0) + return ret; + + if ((signed int)ipi_auto_flush < 0 || (signed int)ipi_auto_flush > 1) { + dev_err(dev, + "Invalid Auto Flush Mode %lu, (No -> 0 or Yes -> 1\n", + ipi_auto_flush); + return count; + } + + dev_info(dev, "IPI Auto Flush %lu\n", ipi_auto_flush); + csi_dev->hw.ipi_auto_flush = ipi_auto_flush; + + return count; +} + +static ssize_t ipi_auto_flush_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.ipi_auto_flush); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t ipi_timings_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long ipi_mode; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &ipi_mode); + if (ret < 0) + return ret; + + if ((signed int)ipi_mode < 0 || (signed int)ipi_mode > 1) { + dev_err(dev, + "Invalid Timing Source %lu (Camera:0|Controller:1)\n", + ipi_mode); + return count; + } + + dev_info(dev, "IPI Color mode %lu\n", ipi_mode); + csi_dev->hw.ipi_mode = ipi_mode; + + return count; +} + +static ssize_t ipi_timings_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.ipi_mode); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t output_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long output; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &output); + if (ret < 0) + return ret; + + if ((signed int)output < 0 || (signed int)output > 1) { + dev_err(dev, + "Invalid Core output %lu to be used \ + (IPI-> 0 or IDI->1 or BOTH- 2\n", + output); + return count; + } + + dev_info(dev, "IPI Color mode %lu\n", output); + csi_dev->hw.output = output; + + return count; +} + +static ssize_t output_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + char buffer[10]; + + snprintf(buffer, 10, "%d\n", csi_dev->hw.output); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t csi_power_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + + int ret; + unsigned long on; + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_csi *csi_dev = &drvdata->csi_dev; + + ret = kstrtoul(buf, 10, &on); + if (ret < 0) + return ret; + + dw_mipi_csi_s_power(csi_dev, on); + printk("csi set power: %lu\n", on); + + return count; +} + +static DEVICE_ATTR_RO(core_version); +static DEVICE_ATTR_RO(core_reset); +static DEVICE_ATTR_RW(n_lanes); +static DEVICE_ATTR_RW(data_type); +static DEVICE_ATTR_RW(hsa); +static DEVICE_ATTR_RW(hbp); +static DEVICE_ATTR_RW(hsd); +static DEVICE_ATTR_RW(vsa); +static DEVICE_ATTR_RW(vbp); +static DEVICE_ATTR_RW(vfp); +static DEVICE_ATTR_RW(virtual_channel); +static DEVICE_ATTR_RW(ipi_color_mode); +static DEVICE_ATTR_RW(ipi_auto_flush); +static DEVICE_ATTR_RW(ipi_timings_mode); +static DEVICE_ATTR_RW(output_type); +static DEVICE_ATTR_WO(csi_power); + +int dw_csi_create_capabilities_sysfs(struct platform_device *pdev) +{ + device_create_file(&pdev->dev, &dev_attr_core_version); + device_create_file(&pdev->dev, &dev_attr_core_reset); + device_create_file(&pdev->dev, &dev_attr_n_lanes); + device_create_file(&pdev->dev, &dev_attr_data_type); + device_create_file(&pdev->dev, &dev_attr_hsa); + device_create_file(&pdev->dev, &dev_attr_hbp); + device_create_file(&pdev->dev, &dev_attr_hsd); + device_create_file(&pdev->dev, &dev_attr_vsa); + device_create_file(&pdev->dev, &dev_attr_vbp); + device_create_file(&pdev->dev, &dev_attr_vfp); + device_create_file(&pdev->dev, &dev_attr_virtual_channel); + device_create_file(&pdev->dev, &dev_attr_ipi_color_mode); + device_create_file(&pdev->dev, &dev_attr_ipi_auto_flush); + device_create_file(&pdev->dev, &dev_attr_ipi_timings_mode); + device_create_file(&pdev->dev, &dev_attr_output_type); + device_create_file(&pdev->dev, &dev_attr_csi_power); + + return 0; +} + +int dw_csi_remove_capabilities_sysfs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_core_version); + device_remove_file(&pdev->dev, &dev_attr_core_reset); + device_remove_file(&pdev->dev, &dev_attr_n_lanes); + device_remove_file(&pdev->dev, &dev_attr_data_type); + device_remove_file(&pdev->dev, &dev_attr_hsa); + device_remove_file(&pdev->dev, &dev_attr_hbp); + device_remove_file(&pdev->dev, &dev_attr_hsd); + device_remove_file(&pdev->dev, &dev_attr_vsa); + device_remove_file(&pdev->dev, &dev_attr_vbp); + device_remove_file(&pdev->dev, &dev_attr_vfp); + device_remove_file(&pdev->dev, &dev_attr_virtual_channel); + device_remove_file(&pdev->dev, &dev_attr_ipi_color_mode); + device_remove_file(&pdev->dev, &dev_attr_ipi_auto_flush); + device_remove_file(&pdev->dev, &dev_attr_ipi_timings_mode); + device_remove_file(&pdev->dev, &dev_attr_output_type); + device_remove_file(&pdev->dev, &dev_attr_csi_power); + + return 0; +} diff --git a/vvcam_ry/native/csi/dw-dphy-data.h b/vvcam_ry/native/csi/dw-dphy-data.h new file mode 100755 index 0000000..bddd5eb --- /dev/null +++ b/vvcam_ry/native/csi/dw-dphy-data.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY platform data + * + * Author: Luis Oliveira + */ + +#include +#include +#include + +#ifndef __DW_DPHY_DATA_H__ +#define __DW_DPHY_DATA_H__ + +struct dw_phy_pdata { + u32 dphy_frequency; + u8 dphy_te_len; + u32 config_8l; + u8 dphy_gen; + u8 phy_type; + u8 id; +}; + +static const struct pdata_names phys[] = { + { .name = "phy-dw-dphy.0.0", }, + { .name = "phy-dw-dphy.1.1", }, +}; + +struct dw_dphy_rx; + +struct plat_dw_dphy { + int (*get_resources)(struct device *dev, struct dw_dphy_rx *dphy); +}; +#endif /*__DW_DPHY_DATA_H__ */ diff --git a/vvcam_ry/native/csi/dw-dphy-plat.c b/vvcam_ry/native/csi/dw-dphy-plat.c new file mode 100755 index 0000000..3706ed6 --- /dev/null +++ b/vvcam_ry/native/csi/dw-dphy-plat.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY controller driver. + * Platform driver + * + * Author: Luis Oliveira + */ + +#include +#include +#include "dw-dphy-rx.h" +#include "bm_csi_hw.h" + +/* Global variable for compatibility mode, this could be override later */ +static int phy_type = 1; //Changed to fit single phy 0 - single | 1 - 8 lanes phy + +module_param(phy_type, int, 0664); +MODULE_PARM_DESC(phy_type, "Disable compatibility mode for D-PHY G128"); + +static struct phy_ops dw_dphy_ops = { + .init = dw_dphy_init, + .reset = dw_dphy_reset, + .power_on = dw_dphy_power_on, + .power_off = dw_dphy_power_off, + .owner = THIS_MODULE, +}; + +static int get_resources(struct device *dev, struct dw_dphy_rx *dphy) +{ + int ret = 0; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_phy_pdata *pdata = &drvdata->dphy_pdata; + + dphy->dphy_freq = pdata->dphy_frequency; + dphy->dphy_te_len = pdata->dphy_te_len; + dphy->dphy_gen = pdata->dphy_gen; + drvdata->dphy = dphy; + + return ret; +} + +static int phy_register(struct device *dev) +{ + int ret = 0; + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + struct dw_phy_pdata *pdata = &drvdata->dphy_pdata; + + ret = phy_create_lookup(dphy->phy, + phys[pdata->id].name, + csis[pdata->id].name); + if (ret) + dev_err(dev, "Failed to create dphy lookup\n"); + else + dev_warn(dev, "Created dphy lookup [%s] --> [%s]\n", + phys[pdata->id].name, csis[pdata->id].name); + + + return ret; +} + +static void phy_unregister(struct device *dev) +{ + if (!dev->of_node) { + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + struct dw_phy_pdata *pdata = &drvdata->dphy_pdata; + + phy_remove_lookup(dphy->phy, + phys[pdata->id].name, csis[pdata->id].name); + dev_warn(dev, "Removed dphy lookup [%s] --> [%s]\n", + phys[pdata->id].name, csis[pdata->id].name); + } +} + +#define REG_DPHY_OFFSET 0x40 +int dw_dphy_rx_probe(struct platform_device *pdev, void __iomem *dphy1_if_addr) +{ + struct device *dev = &pdev->dev; + struct dw_dphy_rx *dphy; + struct bm_csi_drvdata *drvdata; + + dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); + if (!dphy) + return -ENOMEM; + + drvdata = platform_get_drvdata(pdev); + dphy->base_address = drvdata->base + REG_DPHY_OFFSET; + drvdata->dphy= dphy; + dphy->dphy1_if_addr = dphy1_if_addr; + + if (IS_ERR(dphy->base_address)) { + dev_err(&pdev->dev, "error requesting base address\n"); + return PTR_ERR(dphy->base_address); + } + + if (get_resources(dev, dphy)) { + dev_err(dev, "failed to parse PHY resources\n"); + return -EINVAL; + } + + dphy->phy = devm_phy_create(dev, NULL, &dw_dphy_ops); + if (IS_ERR(dphy->phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(dphy->phy); + } + + phy_set_drvdata(dphy->phy, dphy); + + if (phy_register(dev)) { + dev_err(dev, "failed to register PHY\n"); + return -EINVAL; + } + + dphy->lp_time = 1000; /* 1000 ns */ + dphy->lanes_config = dw_dphy_setup_config(dphy); + + dev_info(&dphy->phy->dev, "Probing dphy finished\n"); + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_dphy_create_capabilities_sysfs(pdev); +#endif + + return 0; +} + +int dw_dphy_rx_remove(struct platform_device *pdev) +{ + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + + dev_info(&dphy->phy->dev, "phy removed\n"); + phy_unregister(&pdev->dev); + dw_dphy_remove_capabilities_sysfs(pdev); + + return 0; +} + +MODULE_DESCRIPTION("Synopsys DesignWare MIPI DPHY Rx driver"); +MODULE_AUTHOR("Luis Oliveira "); +MODULE_LICENSE("GPL v2"); diff --git a/vvcam_ry/native/csi/dw-dphy-rx.c b/vvcam_ry/native/csi/dw-dphy-rx.c new file mode 100755 index 0000000..79c5038 --- /dev/null +++ b/vvcam_ry/native/csi/dw-dphy-rx.c @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY controller driver + * Core functions + * + * Author: Luis Oliveira + */ + +#include "dw-dphy-rx.h" +#include "bm_csi_dphy.h" +#include "bm_printk.h" + +struct range_dphy_gen2 { + u32 freq; + u8 hsfregrange; +}; + +struct range_dphy_gen2 range_gen2[] = { + { 80, 0x00 }, { 90, 0x10 }, { 100, 0x20 }, { 110, 0x30 }, + { 120, 0x01 }, { 130, 0x11 }, { 140, 0x21 }, { 150, 0x31 }, + { 160, 0x02 }, { 170, 0x12 }, { 180, 0x22 }, { 190, 0x32 }, + { 205, 0x03 }, { 220, 0x13 }, { 235, 0x23 }, { 250, 0x33 }, + { 275, 0x04 }, { 300, 0x14 }, { 325, 0x05 }, { 350, 0x15 }, + { 400, 0x25 }, { 450, 0x06 }, { 500, 0x16 }, { 550, 0x07 }, + { 600, 0x17 }, { 650, 0x08 }, { 700, 0x18 }, { 750, 0x09 }, + { 800, 0x19 }, { 850, 0x29 }, { 900, 0x39 }, { 950, 0x0A }, + { 1000, 0x1A }, { 1050, 0x2A }, { 1100, 0x3A }, { 1150, 0x0B }, + { 1200, 0x1B }, { 1250, 0x2B }, { 1300, 0x3B }, { 1350, 0x0C }, + { 1400, 0x1C }, { 1450, 0x2C }, { 1500, 0x3C }, { 1550, 0x0D }, + { 1600, 0x1D }, { 1650, 0x2D }, { 1700, 0x0E }, { 1750, 0x1E }, + { 1800, 0x2E }, { 1850, 0x3E }, { 1900, 0x0F }, { 1950, 0x1F }, + { 2000, 0x2F }, +}; + +struct range_dphy_gen3 { + u32 freq; + u8 hsfregrange; + u32 osc_freq_target; +}; + +struct range_dphy_gen3 range_gen3[] = { + { 80, 0x00, 0x1B6 }, { 90, 0x10, 0x1B6 }, { 100, 0x20, 0x1B6 }, + { 110, 0x30, 0x1B6 }, { 120, 0x01, 0x1B6 }, { 130, 0x11, 0x1B6 }, + { 140, 0x21, 0x1B6 }, { 150, 0x31, 0x1B6 }, { 160, 0x02, 0x1B6 }, + { 170, 0x12, 0x1B6 }, { 180, 0x22, 0x1B6 }, { 190, 0x32, 0x1B6 }, + { 205, 0x03, 0x1B6 }, { 220, 0x13, 0x1B6 }, { 235, 0x23, 0x1B6 }, + { 250, 0x33, 0x1B6 }, { 275, 0x04, 0x1B6 }, { 300, 0x14, 0x1B6 }, + { 325, 0x25, 0x1B6 }, { 350, 0x35, 0x1B6 }, { 400, 0x05, 0x1B6 }, + { 450, 0x16, 0x1B6 }, { 500, 0x26, 0x1B6 }, { 550, 0x37, 0x1B6 }, + { 600, 0x07, 0x1B6 }, { 650, 0x18, 0x1B6 }, { 700, 0x28, 0x1B6 }, + { 750, 0x39, 0x1B6 }, { 800, 0x09, 0x1B6 }, { 850, 0x19, 0x1B6 }, + { 900, 0x29, 0x1B6 }, { 950, 0x3A, 0x1B6 }, { 1000, 0x0A, 0x1B6 }, + { 1050, 0x1A, 0x1B6 }, { 1100, 0x2A, 0x1B6 }, { 1150, 0x3B, 0x1B6 }, + { 1200, 0x0B, 0x1B6 }, { 1250, 0x1B, 0x1B6 }, { 1300, 0x2B, 0x1B6 }, + { 1350, 0x3C, 0x1B6 }, { 1400, 0x0C, 0x1B6 }, { 1450, 0x1C, 0x1B6 }, + { 1500, 0x2C, 0x1B6 }, { 1550, 0x3D, 0x10F }, { 1600, 0x0D, 0x118 }, + { 1650, 0x1D, 0x121 }, { 1700, 0x2E, 0x12A }, { 1750, 0x3E, 0x132 }, + { 1800, 0x0E, 0x13B }, { 1850, 0x1E, 0x144 }, { 1900, 0x2F, 0x14D }, + { 1950, 0x3F, 0x155 }, { 2000, 0x0F, 0x15E }, { 2050, 0x40, 0x167 }, + { 2100, 0x41, 0x170 }, { 2150, 0x42, 0x178 }, { 2200, 0x43, 0x181 }, + { 2250, 0x44, 0x18A }, { 2300, 0x45, 0x193 }, { 2350, 0x46, 0x19B }, + { 2400, 0x47, 0x1A4 }, { 2450, 0x48, 0x1AD }, { 2500, 0x49, 0x1B6 } +}; + +u8 dw_dphy_setup_config(struct dw_dphy_rx *dphy) +{ +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +#if 0 + int ret; + + if (dphy->max_lanes == CTRL_4_LANES) { + dev_vdbg(&dphy->phy->dev, "CONFIG 4L\n"); + return CTRL_4_LANES; + } + if (IS_ENABLED(CONFIG_OF)) { + ret = gpio_request(dphy->config_8l, "config"); + if (ret < 0) { + dev_vdbg(&dphy->phy->dev, + "could not acquire config (err=%d)\n", ret); + return ret; + } + ret = gpio_get_value(dphy->config_8l); + gpio_free(dphy->config_8l); + } else { + ret = dphy->config_8l; + } + + dev_vdbg(&dphy->phy->dev, + "Booting in [%s] mode\n", + ret == CTRL_8_LANES ? "8L" : "4+4L"); + return ret; +#endif +#endif /* CONFIG_DWC_MIPI_TC_DPHY_GEN3 */ + return CTRL_4_LANES; +} + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +//extern int k_bm_visys_write_reg(uint32_t offset, uint32_t value); +//extern int k_bm_visys_read_reg(uint32_t offset, uint32_t *value); + +void dw_dphy_if_write(struct dw_dphy_rx *dphy, u32 address, u32 data) +{ + writel(data, dphy->dphy1_if_addr + address); + //k_bm_visys_write_reg(address, data); +} + +u32 dw_dphy_if_read(struct dw_dphy_rx *dphy, u32 address) +{ + u32 if1 = 0; + if1 = readl(dphy->dphy1_if_addr + address); + //k_bm_visys_read_reg(address, &if1); + return if1; +} +#endif + +void dw_dphy_write(struct dw_dphy_rx *dphy, u32 address, u32 data) +{ + iowrite32(data, dphy->base_address + address); + + if (dphy->lanes_config == CTRL_4_LANES) + return; + return; + + if (address == R_CSI2_DPHY_TST_CTRL0) + iowrite32(data, dphy->base_address + R_CSI2_DPHY2_TST_CTRL0); + else if (address == R_CSI2_DPHY_TST_CTRL1) + iowrite32(data, dphy->base_address + R_CSI2_DPHY2_TST_CTRL1); +} + +u32 dw_dphy_read(struct dw_dphy_rx *dphy, u32 address) +{ + int dphy1 = 0, dphy2 = 0; + + dphy1 = ioread32(dphy->base_address + address); + + if (dphy->lanes_config == CTRL_4_LANES) + goto end; + + goto end; + + if (address == R_CSI2_DPHY_TST_CTRL0) + dphy2 = ioread32(dphy->base_address + R_CSI2_DPHY2_TST_CTRL0); + else if (address == R_CSI2_DPHY_TST_CTRL1) + dphy2 = ioread32(dphy->base_address + R_CSI2_DPHY2_TST_CTRL1); + else + return -ENODEV; +end: + return dphy1; +} + +void dw_dphy_write_msk(struct dw_dphy_rx *dev, u32 address, u32 data, u8 shift, + u8 width) +{ + u32 temp = dw_dphy_read(dev, address); + u32 mask = (1 << width) - 1; + + temp &= ~(mask << shift); + temp |= (data & mask) << shift; + dw_dphy_write(dev, address, temp); +} + +static void dw_dphy_te_12b_write(struct dw_dphy_rx *dphy, u16 addr, u8 data) +{ + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, PHY_TESTDIN, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)(addr >> 8), + PHY_TESTDIN, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)addr, PHY_TESTDIN, + 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)data, PHY_TESTDIN, + 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); +} + +static void dw_dphy_te_8b_write(struct dw_dphy_rx *dphy, u8 addr, u8 data) +{ + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_TST_CTRL1, addr); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_TST_CTRL1, data); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); +} + +static void dw_dphy_te_write(struct dw_dphy_rx *dphy, u16 addr, u8 data) +{ + dphy->dphy_te_len = BIT12; + if (dphy->dphy_te_len == BIT12) + dw_dphy_te_12b_write(dphy, addr, data); + else + dw_dphy_te_8b_write(dphy, addr, data); +} + +static int dw_dphy_te_12b_read(struct dw_dphy_rx *dphy, u32 addr) +{ + u8 ret; + + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, PHY_TESTDIN, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)(addr >> 8), + PHY_TESTDIN, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)addr, PHY_TESTDIN, + 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, 0, PHY_TESTDIN); + ret = dw_dphy_read_msk(dphy, R_CSI2_DPHY_TST_CTRL1, PHY_TESTDOUT, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1); + + return ret; +} + +static int dw_dphy_te_8b_read(struct dw_dphy_rx *dphy, u32 addr) +{ + u8 ret; + + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, addr, PHY_TESTDIN, 8); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTDIN, 8); + ret = dw_dphy_read_msk(dphy, R_CSI2_DPHY_TST_CTRL1, PHY_TESTDOUT, 8); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1); + + return ret; +} + +int dw_dphy_te_read(struct dw_dphy_rx *dphy, u32 addr) +{ + int ret; + + if (dphy->dphy_te_len == BIT12) + ret = dw_dphy_te_12b_read(dphy, addr); + else + ret = dw_dphy_te_12b_read(dphy, addr); + //ret = dw_dphy_te_8b_read(dphy, addr); + + return ret; +} + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +static void dw_dphy_if_init(struct dw_dphy_rx *dphy) +{ + bm_info("enter %s\n", __func__); + //dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + //dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, TX_PHY); + //dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1); + //dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, GLUELOGIC); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RX_PHY); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0); + //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1); +} +#endif + +static void dw_dphy_gen3_12bit_tc_power_up(struct dw_dphy_rx *dphy, uint8_t hsfregrange) +{ +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, GLUELOGIC); +#endif + dw_dphy_te_write(dphy, CFGCLKFREQRANGE_RX, 0x1C); + dw_dphy_te_write(dphy, 0x6, hsfregrange); + + /* CLKSEL | UPDATEPLL | SHADOW_CLEAR | SHADOW_CTRL | FORCEPLL */ + //dw_dphy_te_write(dphy, BYPASS, 0x3F); + + /* IO_DS3 | IO_DS2 | IO_DS1 | IO_DS0 */ + if (dphy->dphy_freq > 1500) + dw_dphy_te_write(dphy, IO_DS, 0x0F); +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RX_PHY | 0x2); +#endif +} + +static void dw_dphy_gen3_8bit_tc_power_up(struct dw_dphy_rx *dphy) +{ + u32 input_freq = dphy->dphy_freq / 1000; +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, GLUELOGIC); + dw_dphy_te_write(dphy, CFGCLKFREQRANGE_RX, 0x1C); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET); + dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RX_PHY); +#endif + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX0_MSB, 0x03); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX0_LSB, 0x02); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX1_MSB, 0x03); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX1_LSB, 0x02); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX2_MSB, 0x03); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX2_LSB, 0x02); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX3_MSB, 0x03); + dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX3_LSB, 0x02); + dw_dphy_te_write(dphy, BANDGAP_CTRL, 0x80); + + if (input_freq < 2000) + dw_dphy_te_write(dphy, HS_RX_CTRL_LANE0, 0xC0); + + if (input_freq < 1000) { + dw_dphy_te_write(dphy, HS_RX_CTRL_LANE1, 0xC0); + dw_dphy_te_write(dphy, HS_RX_CTRL_LANE2, 0xC0); + dw_dphy_te_write(dphy, HS_RX_CTRL_LANE3, 0xC0); + } +} + +int dw_dphy_g118_settle(struct dw_dphy_rx *dphy) +{ + u32 input_freq, total_settle, settle_time, byte_clk, lp_time; + + lp_time = dphy->lp_time; + input_freq = dphy->dphy_freq / 1000; + + settle_time = (8 * (1000000 / (input_freq))) + 115000; + byte_clk = (8000000 / (input_freq)); + total_settle = (settle_time + lp_time * 1000) / byte_clk; + + if (total_settle > 0xFF) + total_settle = 0xFF; + + return total_settle; +} + +static void dw_dphy_pwr_down(struct dw_dphy_rx *dphy) +{ + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1); + if (dphy->lanes_config == CTRL_8_LANES) + dw_dphy_write_msk(dphy, R_CSI2_DPHY2_TST_CTRL0, 0, PHY_TESTCLK, + 1); + + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0); +} + +static void dw_dphy_pwr_up(struct dw_dphy_rx *dphy) +{ + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1); + if (dphy->lanes_config == CTRL_8_LANES) + dw_dphy_write_msk(dphy, R_CSI2_DPHY2_TST_CTRL0, 1, PHY_TESTCLK, + 1); + dev_vdbg(&dphy->phy->dev, "DPHY power up.\n"); + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); +} + +static int dw_dphy_gen3_12bit_configure(struct dw_dphy_rx *dphy) +{ + u32 input_freq = dphy->dphy_freq; + u8 range = 0; + + dev_vdbg(&dphy->phy->dev, "12bit: PHY GEN 3: Freq: %u\n", input_freq); + for (range = 0; (range < ARRAY_SIZE(range_gen3) - 1) && + ((input_freq / 1000) > range_gen3[range].freq); + range++) + ; + + dw_dphy_gen3_12bit_tc_power_up(dphy, range_gen3[range].hsfregrange); + + uint8_t lp_time = dphy->lp_time; + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_17, lp_time);//SET SETTLE TIME + + dw_dphy_te_write(dphy, RX_SYS_1, range_gen3[range].hsfregrange); + dw_dphy_te_write(dphy, RX_SYS_0, 0x20); + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_2, + (u8)range_gen3[range].osc_freq_target); + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_3, + (u8)(range_gen3[range].osc_freq_target >> 8)); + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_4, 0x01); + + if (dphy->phy_type) { + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_1, 0x01); + dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_0, 0x80); + } + + if (dphy->phy_type || input_freq <= 1500) + dw_dphy_te_write(dphy, RX_SYS_7, 0x38); + + return 0; +} + +static int dw_dphy_gen3_8bit_configure(struct dw_dphy_rx *dphy) +{ + u32 input_freq = dphy->dphy_freq; + u8 data; + u8 range = 0; + + dev_vdbg(&dphy->phy->dev, "8bit: PHY GEN 3: Freq: %u\n", input_freq); + for (range = 0; (range < ARRAY_SIZE(range_gen3) - 1) && + ((input_freq / 1000) > range_gen3[range].freq); + range++) + ; + + dw_dphy_te_write(dphy, RX_SKEW_CAL, dw_dphy_g118_settle(dphy)); + data = 1 << 7 | range_gen3[range].hsfregrange; + dw_dphy_te_write(dphy, HSFREQRANGE_8BIT, data); + dw_dphy_gen3_8bit_tc_power_up(dphy); + + return 0; +} + +static int dw_dphy_gen2_configure(struct dw_dphy_rx *dphy) +{ + u32 input_freq = dphy->dphy_freq; + u8 data; + u8 range = 0; + + /* provide an initial active-high test clear pulse in TESTCLR */ + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1); + dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1); + + dev_vdbg(&dphy->phy->dev, "PHY GEN 2: Freq: %u\n", input_freq); + for (range = 0; (range < ARRAY_SIZE(range_gen2) - 1) && + ((input_freq / 1000) > range_gen2[range].freq); range++) + ; + + data = range_gen2[range].hsfregrange << 1; + dw_dphy_te_write(dphy, HSFREQRANGE_8BIT, data); + + return 0; +} + +static int dw_dphy_configure(struct dw_dphy_rx *dphy) +{ + + bm_info("enter %s\n", __func__); + dw_dphy_pwr_down(dphy); + dphy->dphy_gen = GEN3; + if (dphy->dphy_gen == GEN3) { +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + dw_dphy_if_init(dphy); +#endif + dphy->dphy_te_len = BIT12; + if (dphy->dphy_te_len == BIT12) + dw_dphy_gen3_12bit_configure(dphy); + else + dw_dphy_gen3_8bit_configure(dphy); + } else { + dw_dphy_gen2_configure(dphy); + } + dw_dphy_pwr_up(dphy); + + return 0; +} + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + +#if 0 +int dw_dphy_if_set_idelay(struct dw_dphy_rx *dphy, u8 dly, u8 cells) +{ + u32 val = 0; + + dw_dphy_if_write(dphy, IDLYCFG, 0); + dw_dphy_if_write(dphy, IDLYSEL, cells); + dw_dphy_if_write(dphy, IDLYCNTINVAL, dly); + + /* Pulse Value Set */ + dw_dphy_if_write(dphy, IDLYCFG, 1); + usleep_range(10, 20); + dw_dphy_if_write(dphy, IDLYCFG, 0); + + /* Pulse IDELAY CTRL Reset */ + dw_dphy_if_write(dphy, DPHY1REGRSTN, 0); + usleep_range(10, 20); + dw_dphy_if_write(dphy, DPHY1REGRSTN, 1); + + /* Get Value*/ + val = dw_dphy_if_read(dphy, IDLYCNTOUTVAL); + + if (val != dly) { + dev_vdbg(&dphy->phy->dev, + "odelay config failed, set %d get %d", dly, val); + return -EINVAL; + } + + return 0; +} + +int dw_dphy_if_get_idelay(struct dw_dphy_rx *dphy) +{ + return dw_dphy_if_read(dphy, IDLYCNTOUTVAL); +} + +int dw_dphy_if_set_idelay_lane(struct dw_dphy_rx *dphy, u8 dly, u8 lane) +{ + int cell; + + switch (lane) { + case 0: + for (cell = 3; cell <= 10; cell++) + dw_dphy_if_set_idelay(dphy, dly, cell); + break; + case 1: + for (cell = 14; cell <= 21; cell++) + dw_dphy_if_set_idelay(dphy, dly, cell); + break; + case 2: + for (cell = 24; cell <= 31; cell++) + dw_dphy_if_set_idelay(dphy, dly, cell); + break; + case 3: + for (cell = 34; cell <= 41; cell++) + dw_dphy_if_set_idelay(dphy, dly, cell); + break; + case 4: /* ALL */ + dw_dphy_if_set_idelay(dphy, dly, 0x7F); + break; + default: + dev_err(&dphy->phy->dev, "Lane Value not recognized\n"); + return -1; + } + return 0; +} +#endif +#endif + +int dw_dphy_init(struct phy *phy) +{ + struct dw_dphy_rx *dphy = phy_get_drvdata(phy); + + dev_warn(&dphy->phy->dev, "Init DPHY.\n"); + + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0); + + return 0; +} + +static int dw_dphy_set_phy_state(struct dw_dphy_rx *dphy, u32 on) +{ + + u8 hs_freq; + + bm_info("enter %s\n", __func__); + dphy->lanes_config = dw_dphy_setup_config(dphy); + + if (dphy->dphy_te_len == BIT12) + hs_freq = RX_SYS_1; + else + hs_freq = HSFREQRANGE_8BIT; + + if (on) { + dw_dphy_configure(dphy); + dev_info(&dphy->phy->dev, + "HS Code: 0X%x\n", dw_dphy_te_read(dphy, hs_freq)); + } else { + dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + } + + return 0; +} + +int dw_dphy_power_on(struct phy *phy) +{ + struct dw_dphy_rx *dphy = phy_get_drvdata(phy); + + dev_info(&dphy->phy->dev, "DPHY Power ON\n"); + bm_info("enter %s\n", __func__); + + return dw_dphy_set_phy_state(dphy, 1); +} + +int dw_dphy_power_off(struct phy *phy) +{ + struct dw_dphy_rx *dphy = phy_get_drvdata(phy); + + return dw_dphy_set_phy_state(dphy, 0); +} + +int dw_dphy_reset(struct phy *phy) +{ + struct dw_dphy_rx *dphy = phy_get_drvdata(phy); + + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + usleep_range(100, 200); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); + + return 0; +} diff --git a/vvcam_ry/native/csi/dw-dphy-rx.h b/vvcam_ry/native/csi/dw-dphy-rx.h new file mode 100755 index 0000000..5ee1999 --- /dev/null +++ b/vvcam_ry/native/csi/dw-dphy-rx.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY controller driver + * + * Author: Luis Oliveira + */ + +#ifndef __PHY_SNPS_DPHY_RX_H__ +#define __PHY_SNPS_DPHY_RX_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* DPHY interface register bank*/ + +#define R_CSI2_DPHY_SHUTDOWNZ 0x0 +#define R_CSI2_DPHY_RSTZ 0x4 +#define R_CSI2_DPHY_RX 0x8 +#define R_CSI2_DPHY_STOPSTATE 0xC +#define R_CSI2_DPHY_TST_CTRL0 0x10 +#define R_CSI2_DPHY_TST_CTRL1 0x14 +#define R_CSI2_DPHY2_TST_CTRL0 0x18 +#define R_CSI2_DPHY2_TST_CTRL1 0x1C + +enum dphy_id_mask { + DPHY_ID_LANE_SUPPORT = 0, + DPHY_ID_IF = 4, + DPHY_ID_GEN = 8, +}; + +enum dphy_gen_values { + GEN1, + GEN2, + GEN3, +}; + +enum dphy_interface_length { + BIT8 = 8, + BIT12 = 12, +}; + +enum tst_ctrl0 { + PHY_TESTCLR, + PHY_TESTCLK, +}; + +enum tst_ctrl1 { + PHY_TESTDIN = 0, + PHY_TESTDOUT = 8, + PHY_TESTEN = 16, +}; + +enum lanes_config_values { + CTRL_4_LANES, + CTRL_8_LANES, +}; + +enum dphy_tc { + CFGCLKFREQRANGE_TX = 0x02, + CFGCLKFREQRANGE_RX = 0x05, + BYPASS = 0x20, + IO_DS = 0x30, +}; + +enum dphy_8bit_interface_addr { + BANDGAP_CTRL = 0x24, + HS_RX_CTRL_LANE0 = 0x42, + HSFREQRANGE_8BIT = 0x44, + OSC_FREQ_TARGET_RX0_LSB = 0x4e, + OSC_FREQ_TARGET_RX0_MSB = 0x4f, + HS_RX_CTRL_LANE1 = 0x52, + OSC_FREQ_TARGET_RX1_LSB = 0x5e, + OSC_FREQ_TARGET_RX1_MSB = 0x5f, + RX_SKEW_CAL = 0x7e, + HS_RX_CTRL_LANE2 = 0x82, + OSC_FREQ_TARGET_RX2_LSB = 0x8e, + OSC_FREQ_TARGET_RX2_MSB = 0x8f, + HS_RX_CTRL_LANE3 = 0x92, + OSC_FREQ_TARGET_RX3_LSB = 0x9e, + OSC_FREQ_TARGET_RX3_MSB = 0x9f, +}; + +enum dphy_12bit_interface_addr { + RX_SYS_0 = 0x01, + RX_SYS_1 = 0x02, + RX_SYS_7 = 0x08, + RX_RX_STARTUP_OVR_0 = 0xe0, + RX_RX_STARTUP_OVR_1 = 0xe1, + RX_RX_STARTUP_OVR_2 = 0xe2, + RX_RX_STARTUP_OVR_3 = 0xe3, + RX_RX_STARTUP_OVR_4 = 0xe4, + RX_RX_STARTUP_OVR_17 = 0xf1, +}; + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +/* Testchip interface register bank */ +#define IDLYCFG 0x00 +#define IDLYSEL 0x04 +#define IDLYCNTINVAL 0x08 +#define IDLYCNTOUTVAL 0x0c +#define DPHY1REGRSTN 0x10 +#define DPHYZCALSTAT 0x14 +#define DPHYZCALCTRL 0x18 +#define DPHYLANE0STAT 0x1c +#define DPHYLANE1STAT 0x20 +#define DPHYLANE2STAT 0x24 +#define DPHYLANE3STAT 0x28 +#define DPHYCLKSTAT 0x2c +#define DPHYZCLKCTRL 0x30 +#define TCGENPURPOSOUT 0x34 +#define TCGENPURPOSIN 0x38 +#define DPHYGENERICOUT 0x3c +#define DPHYGENERICIN 0x40 + +#define DPHYGLUEIFTESTER 0x180 +#define DPHYID 0x100 + +#define DPHY_DEFAULT_FREQ 300000 + +enum glueiftester { + RESET = 0, + TX_PHY = 0x100 | (0x1 << 4), + RX_PHY = 0x100 | (0x2 << 4), + GLUELOGIC = 0x100 | (0x4 << 4), +}; +#endif + +/** + * struct phy specifies associated phy component + * struct cfg to pass mipi dphy specific configurations + * @lanes_config lanes configuration + * @dphy_freq operating frequency of the d-phy (mbps) + * @phy_type dphy can be of two types, passed here + * @dphy_gen dphy can be of three generations, passed here + * @dphy_te_len bus width + * @max_lanes maximum number of lanes + * @lp_time time in low-power + * @base_address memmory address of dphy test interface + * @dphy1_if_addr gluelogic dphy 1 memmory address of interface + * @dphy2_if_addr gluelogic dphy 2 memmory address of interface + * @config_8l eight lanes configuration + */ + +struct dw_dphy_rx { + struct phy *phy; + struct phy_configure_opts_mipi_dphy *cfg; + u32 lanes_config; + u32 dphy_freq; //MBPS + u32 phy_type; + u32 dphy_gen; + u32 dphy_te_len; + u32 max_lanes; + u32 lp_time; + void __iomem *base_address; +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) + void __iomem *dphy1_if_addr; + void __iomem *dphy2_if_addr; + u8 config_8l; + u8 (*get_config_8l)(struct device *dev, struct dw_dphy_rx *dphy); +#endif + u8 (*phy_register)(struct device *dev); + void (*phy_unregister)(struct device *dev); +}; + +int dw_dphy_init(struct phy *phy); +int dw_dphy_reset(struct phy *phy); +int dw_dphy_power_off(struct phy *phy); +int dw_dphy_power_on(struct phy *phy); +u8 dw_dphy_setup_config(struct dw_dphy_rx *dphy); +void dw_dphy_write(struct dw_dphy_rx *dphy, u32 address, u32 data); +u32 dw_dphy_read(struct dw_dphy_rx *dphy, u32 address); +int dw_dphy_te_read(struct dw_dphy_rx *dphy, u32 addr); + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +u32 dw_dphy_if_read(struct dw_dphy_rx *dphy, u32 address); +int dw_dphy_if_get_idelay(struct dw_dphy_rx *dphy); +int dw_dphy_if_set_idelay_lane(struct dw_dphy_rx *dphy, u8 dly, u8 lane); +int dw_dphy_create_capabilities_sysfs(struct platform_device *pdev); +int dw_dphy_remove_capabilities_sysfs(struct platform_device *pdev); + +static inline +u32 dw_dphy_if_read_msk(struct dw_dphy_rx *dphy, + u32 address, u8 shift, u8 width) +{ + return (dw_dphy_if_read(dphy, address) >> shift) & ((1 << width) - 1); +} +#endif /*IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)*/ + +static inline struct phy *dw_dphy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct dw_dphy_rx *dphy = dev_get_drvdata(dev); + + return dphy->phy; +} + +static inline +u32 dw_dphy_read_msk(struct dw_dphy_rx *dev, u32 address, u8 shift, u8 width) +{ + return (dw_dphy_read(dev, address) >> shift) & ((1 << width) - 1); +} +#endif /*__PHY_SNPS_DPHY_RX_H__*/ diff --git a/vvcam_ry/native/csi/dw-dphy-sysfs.c b/vvcam_ry/native/csi/dw-dphy-sysfs.c new file mode 100755 index 0000000..30aeae0 --- /dev/null +++ b/vvcam_ry/native/csi/dw-dphy-sysfs.c @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI D-PHY controller driver. + * SysFS components for the platform driver + * + * Author: Luis Oliveira + */ + +//#define DEBUG 1 +#include "dw-dphy-rx.h" +#include "bm_csi_hw.h" + +static ssize_t dphy_reset_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + char buffer[15]; + + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0); + usleep_range(100, 200); + dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t dphy_freq_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int ret; + unsigned long freq; + + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + + ret = kstrtoul(buf, 10, &freq); + if (ret < 0) + return ret; + + if (freq > 2500) { + dev_info(dev, "Freq must be under 2500 Mhz\n"); + return count; + } + if (freq < 80) { + dev_info(dev, "Freq must be over 80 Mhz\n"); + return count; + } + + dev_vdbg(dev, "Data Rate %lu Mbps\n", freq); + dphy->dphy_freq = freq*1000; + + return count; +} + +static ssize_t dphy_freq_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + char buffer[15]; + + snprintf(buffer, + sizeof(buffer), + "Freq %d\n", dphy->dphy_freq); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t dphy_addr_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + unsigned long addr; + int ret; + + ret = kstrtoul(buf, 10, &addr); + + if (ret < 0) + return ret; + + //payload = (u16)val; + //addr = (u16)(val >> 16); + + //dev_vdbg(dev, "addr 0x%lX\n", val); + //dev_vdbg(dev, "payload: 0x%X\n", addr); + //dev_vdbg(dev, "Addr [0x%x] -> 0x%x\n", (unsigned int)addr, + // dw_dphy_te_read(dphy, addr)); + + printk("<0>""addr 0x%lX\n", addr); + printk("<0>""Addr [0x%x] -> 0x%x\n", (unsigned int)addr, + dw_dphy_te_read(dphy, addr)); + + + return count; +} + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +#if 0 +static ssize_t idelay_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + char buffer[15]; + + snprintf(buffer, + sizeof(buffer), "idelay %d\n", dw_dphy_if_get_idelay(dphy)); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t idelay_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + unsigned long val; + u8 lane, delay; + int ret; + + ret = kstrtoul(buf, 16, &val); + if (ret < 0) + return ret; + + lane = (u8)val; + delay = (u8)(val >> 8); + + dev_vdbg(dev, "Lanes %u\n", lane); + dev_vdbg(dev, "Delay %u\n", delay); + + dw_dphy_if_set_idelay_lane(dphy, delay, lane); + + return count; +} +#endif +#endif + +static ssize_t len_config_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + unsigned long length; + int ret; + + ret = kstrtoul(buf, 10, &length); + if (ret < 0) + return ret; + + if (length == BIT8) + dev_vdbg(dev, "Configured for 8-bit interface\n"); + else if (length == BIT12) + dev_vdbg(dev, "Configured for 12-bit interface\n"); + else + return count; + + dphy->dphy_te_len = length; + + return count; +} + +static ssize_t len_config_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + char buffer[20]; + + snprintf(buffer, sizeof(buffer), "Length %d\n", dphy->dphy_te_len); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static ssize_t dw_dphy_g118_settle_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + unsigned long lp_time; + int ret; + + ret = kstrtoul(buf, 10, &lp_time); + if (ret < 0) + return ret; + + if (lp_time > 1 && lp_time < 10000) { + dphy->lp_time = lp_time; + } else { + dev_vdbg(dev, "Invalid Value configuring for 1000 ns\n"); + dphy->lp_time = 1000; + } + + dphy->lp_time = lp_time; + + return count; +} + +static ssize_t dw_dphy_g118_settle_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev); + struct dw_dphy_rx *dphy = drvdata->dphy; + char buffer[10]; + + snprintf(buffer, sizeof(buffer), "Settle %d ns\n", dphy->lp_time); + + return strlcpy(buf, buffer, PAGE_SIZE); +} + +static DEVICE_ATTR_RO(dphy_reset); +static DEVICE_ATTR_RW(dphy_freq); +static DEVICE_ATTR_WO(dphy_addr); +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +//static DEVICE_ATTR_RW(idelay); +#endif +static DEVICE_ATTR_RW(len_config); +static DEVICE_ATTR_RW(dw_dphy_g118_settle); + +int dw_dphy_create_capabilities_sysfs(struct platform_device *pdev) +{ + device_create_file(&pdev->dev, &dev_attr_dphy_reset); + device_create_file(&pdev->dev, &dev_attr_dphy_freq); + device_create_file(&pdev->dev, &dev_attr_dphy_addr); +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +// device_create_file(&pdev->dev, &dev_attr_idelay); +#endif + device_create_file(&pdev->dev, &dev_attr_len_config); + device_create_file(&pdev->dev, &dev_attr_dw_dphy_g118_settle); + return 0; +} + +int dw_dphy_remove_capabilities_sysfs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_dphy_reset); + device_remove_file(&pdev->dev, &dev_attr_dphy_freq); + device_remove_file(&pdev->dev, &dev_attr_dphy_addr); +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +// device_create_file(&pdev->dev, &dev_attr_idelay); +#endif + device_remove_file(&pdev->dev, &dev_attr_len_config); + device_remove_file(&pdev->dev, &dev_attr_dw_dphy_g118_settle); + return 0; +} diff --git a/vvcam_ry/native/csi/dw-mipi-csi-pltfrm.h b/vvcam_ry/native/csi/dw-mipi-csi-pltfrm.h new file mode 100755 index 0000000..948db4e --- /dev/null +++ b/vvcam_ry/native/csi/dw-mipi-csi-pltfrm.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 Host media entities + * + * Author: Luis Oliveira + */ + +#ifndef __DW_MIPI_CSI_PLTFRM_INCLUDES_H_ +#define __DW_MIPI_CSI_PLTFRM_INCLUDES_H_ + +#include +#include +#include +#include + +#define MAX_WIDTH 3280 +#define MAX_HEIGHT 1852 + +/* The subdevices' group IDs. */ +#define GRP_ID_SENSOR (10) +#define GRP_ID_CSI (20) +#define GRP_ID_VIF (30) +#define GRP_ID_VIDEODEV (40) + +#define CSI_MAX_ENTITIES (2) +#define VIF_MAX_ENTITIES (2) +#define PLAT_MAX_SENSORS (2) + +struct pdata_names { + char *name; +}; + +enum video_dev_pads { + VIDEO_DEV_SD_PAD_SINK_VIF1, + VIDEO_DEV_SD_PAD_SINK_VIF2, + VIDEO_DEV_SD_PAD_SOURCE_DMA, + VIDEO_DEV_SD_PADS_NUM, +}; + +enum vif_pads { + VIF_PAD_SINK_CSI, + VIF_PAD_SOURCE_DMA, + VIF_PADS_NUM, +}; + +enum mipi_csi_pads { + CSI_PAD_SINK, + CSI_PAD_SOURCE, + CSI_PADS_NUM, +}; + +struct plat_csi_source_info { + u16 flags; + u16 mux_id; +}; + +struct plat_csi_fmt { + char *name; + u32 mbus_code; + u32 fourcc; + u8 depth; +}; + +struct plat_csi_media_pipeline; + +/* + * Media pipeline operations to be called from within a video node, i.e. the + * last entity within the pipeline. Implemented by related media device driver. + */ +struct plat_csi_media_pipeline_ops { + int (*prepare)(struct plat_csi_media_pipeline *p, + struct media_entity *me); + int (*unprepare)(struct plat_csi_media_pipeline *p); + int (*open)(struct plat_csi_media_pipeline *p, struct media_entity *me, + bool resume); + int (*close)(struct plat_csi_media_pipeline *p); + int (*set_stream)(struct plat_csi_media_pipeline *p, bool state); + int (*set_format)(struct plat_csi_media_pipeline *p, + struct v4l2_subdev_format *fmt); +}; + +struct plat_csi_video_entity { + struct video_device vdev; + struct plat_csi_media_pipeline *pipe; +}; + +struct plat_csi_media_pipeline { + struct media_pipeline mp; + const struct plat_csi_media_pipeline_ops *ops; +}; + +static inline struct plat_csi_video_entity +*vdev_to_plat_csi_video_entity(struct video_device *vdev) +{ + return container_of(vdev, struct plat_csi_video_entity, vdev); +} + +#define plat_csi_pipeline_call(ent, op, args...) \ + (!(ent) ? -ENOENT : (((ent)->pipe->ops && (ent)->pipe->ops->op) ? \ + (ent)->pipe->ops->op(((ent)->pipe), ##args) : -ENOIOCTLCMD)) \ + +#endif /* __DW_MIPI_CSI_PLTFRM_INCLUDES_H_ */ diff --git a/vvcam_ry/native/csi/dw-mipi-csi.c b/vvcam_ry/native/csi/dw-mipi-csi.c new file mode 100755 index 0000000..cea2c8b --- /dev/null +++ b/vvcam_ry/native/csi/dw-mipi-csi.c @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 Host controller driver + * Core MIPI CSI-2 functions + * + * Author: Luis Oliveira + */ + +#include "dw-mipi-csi.h" + +static struct R_CSI2 reg = { + .VERSION = 0x00, + .N_LANES = 0x04, + .CTRL_RESETN = 0x08, + .INTERRUPT = 0x0C, + .DATA_IDS_1 = 0x10, + .DATA_IDS_2 = 0x14, + .IPI_MODE = 0x80, + .IPI_VCID = 0x84, + .IPI_DATA_TYPE = 0x88, + .IPI_MEM_FLUSH = 0x8C, + .IPI_HSA_TIME = 0x90, + .IPI_HBP_TIME = 0x94, + .IPI_HSD_TIME = 0x98, + .IPI_HLINE_TIME = 0x9C, + .IPI_SOFTRSTN = 0xA0, + .IPI_ADV_FEATURES = 0xAC, + .IPI_VSA_LINES = 0xB0, + .IPI_VBP_LINES = 0xB4, + .IPI_VFP_LINES = 0xB8, + .IPI_VACTIVE_LINES = 0xBC, + .INT_PHY_FATAL = 0xe0, + .MASK_INT_PHY_FATAL = 0xe4, + .FORCE_INT_PHY_FATAL = 0xe8, + .INT_PKT_FATAL = 0xf0, + .MASK_INT_PKT_FATAL = 0xf4, + .FORCE_INT_PKT_FATAL = 0xf8, + .INT_PHY = 0x110, + .MASK_INT_PHY = 0x114, + .FORCE_INT_PHY = 0x118, + .INT_LINE = 0x130, + .MASK_INT_LINE = 0x134, + .FORCE_INT_LINE = 0x138, + .INT_IPI = 0x140, + .MASK_INT_IPI = 0x144, + .FORCE_INT_IPI = 0x148, +}; + +struct interrupt_type csi_int = { + .PHY_FATAL = BIT(0), + .PKT_FATAL = BIT(1), + .PHY = BIT(16), +}; + +#define dw_print(VAR) \ + dev_info(csi_dev->dev, "%s: 0x%x: %X\n", "##VAR##",\ + VAR, dw_mipi_csi_read(csi_dev, VAR)) + +void dw_mipi_csi_write_part(struct dw_csi *dev, u32 address, u32 data, + u8 shift, u8 width) +{ + u32 mask = (1 << width) - 1; + u32 temp = dw_mipi_csi_read(dev, address); + + temp &= ~(mask << shift); + temp |= (data & mask) << shift; + dw_mipi_csi_write(dev, address, temp); +} + +void dw_mipi_csi_reset(struct dw_csi *csi_dev) +{ + dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 0); + usleep_range(100, 200); + dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 1); +} + +int dw_mipi_csi_mask_irq_power_off(struct dw_csi *csi_dev) +{ + if (csi_dev->hw_version_major == 1) { + /* set only one lane (lane 0) as active (ON) */ + dw_mipi_csi_write(csi_dev, reg.N_LANES, 0); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY_FATAL, 0); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PKT_FATAL, 0); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY, 0); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_LINE, 0); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_IPI, 0); + + /* only for version 1.30 */ + if (csi_dev->hw_version_minor == 30) + dw_mipi_csi_write(csi_dev, + reg.MASK_INT_FRAME_FATAL, 0); + + dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 0); + + /* only for version 1.40 */ + if (csi_dev->hw_version_minor == 40) { + dw_mipi_csi_write(csi_dev, + reg.MSK_BNDRY_FRAME_FATAL, 0); + dw_mipi_csi_write(csi_dev, + reg.MSK_SEQ_FRAME_FATAL, 0); + dw_mipi_csi_write(csi_dev, + reg.MSK_CRC_FRAME_FATAL, 0); + dw_mipi_csi_write(csi_dev, reg.MSK_PLD_CRC_FATAL, 0); + dw_mipi_csi_write(csi_dev, reg.MSK_DATA_ID, 0); + dw_mipi_csi_write(csi_dev, reg.MSK_ECC_CORRECT, 0); + } + } + + return 0; +} + +int dw_mipi_csi_hw_stdby(struct dw_csi *csi_dev) +{ + if (csi_dev->hw_version_major == 1) { + /* set only one lane (lane 0) as active (ON) */ + dw_mipi_csi_reset(csi_dev); + dw_mipi_csi_write(csi_dev, reg.N_LANES, 0); + phy_init(csi_dev->phy); + + /* only for version 1.30 */ + if (csi_dev->hw_version_minor == 30) + dw_mipi_csi_write(csi_dev, + reg.MASK_INT_FRAME_FATAL, + GENMASK(31, 0)); + + /* common */ + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY_FATAL, + GENMASK(8, 0)); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PKT_FATAL, + GENMASK(1, 0)); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY, GENMASK(23, 0)); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_LINE, GENMASK(23, 0)); + dw_mipi_csi_write(csi_dev, reg.MASK_INT_IPI, GENMASK(5, 0)); + + /* only for version 1.40 */ + if (csi_dev->hw_version_minor == 40) { + dw_mipi_csi_write(csi_dev, + reg.MSK_BNDRY_FRAME_FATAL, + GENMASK(31, 0)); + dw_mipi_csi_write(csi_dev, + reg.MSK_SEQ_FRAME_FATAL, + GENMASK(31, 0)); + dw_mipi_csi_write(csi_dev, + reg.MSK_CRC_FRAME_FATAL, + GENMASK(31, 0)); + dw_mipi_csi_write(csi_dev, + reg.MSK_PLD_CRC_FATAL, + GENMASK(31, 0)); + dw_mipi_csi_write(csi_dev, + reg.MSK_DATA_ID, GENMASK(31, 0)); + dw_mipi_csi_write(csi_dev, + reg.MSK_ECC_CORRECT, GENMASK(31, 0)); + } + } + return 0; +} + +void dw_mipi_csi_set_ipi_fmt(struct dw_csi *csi_dev) +{ + struct device *dev = csi_dev->dev; + + if (csi_dev->ipi_dt) { + dw_mipi_csi_write(csi_dev, reg.IPI_DATA_TYPE, csi_dev->ipi_dt); + /*switch (csi_dev->ipi_dt) { + case CSI_2_YUV420_8: + //case CSI_2_YUV420_8_LEG: + case CSI_2_YUV420_8_SHIFT: + break; + case CSI_2_YUV420_10: + case CSI_2_YUV420_10_SHIFT: + break; + }*/ + } else { + switch (csi_dev->fmt->mbus_code) { + + case MEDIA_BUS_FMT_RGB666_1X18: + csi_dev->ipi_dt = CSI_2_RGB666; + break; + + case MEDIA_BUS_FMT_RGB565_2X8_BE: + case MEDIA_BUS_FMT_RGB565_2X8_LE: + csi_dev->ipi_dt = CSI_2_RGB565; + break; + + case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE: + case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: + csi_dev->ipi_dt = CSI_2_RGB555; + break; + + case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE: + case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE: + csi_dev->ipi_dt = CSI_2_RGB444; + break; + + break; + case MEDIA_BUS_FMT_RGB888_2X12_LE: + case MEDIA_BUS_FMT_RGB888_2X12_BE: + csi_dev->ipi_dt = CSI_2_RGB888; + break; + + case MEDIA_BUS_FMT_SBGGR10_1X10: + case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE: + csi_dev->ipi_dt = CSI_2_RAW10; + break; + + case MEDIA_BUS_FMT_SBGGR12_1X12: + csi_dev->ipi_dt = CSI_2_RAW12; + break; + + case MEDIA_BUS_FMT_SBGGR14_1X14: + csi_dev->ipi_dt = CSI_2_RAW14; + break; + + case MEDIA_BUS_FMT_SBGGR16_1X16: + csi_dev->ipi_dt = CSI_2_RAW16; + break; + + case MEDIA_BUS_FMT_SBGGR8_1X8: + csi_dev->ipi_dt = CSI_2_RAW8; + break; + + case MEDIA_BUS_FMT_YVYU8_1X16: + csi_dev->ipi_dt = CSI_2_YUV422_8; + break; + + case MEDIA_BUS_FMT_VYUY8_1X16: + csi_dev->ipi_dt = CSI_2_YUV422_8; + break; + + case MEDIA_BUS_FMT_UYVY10_1X20: + csi_dev->ipi_dt = CSI_2_YUV422_10; + break; + + case MEDIA_BUS_FMT_YUYV8_1X16: + csi_dev->ipi_dt = CSI_2_YUV420_8_LEG; + break; + + case MEDIA_BUS_FMT_UYVY8_1X16: + csi_dev->ipi_dt = CSI_2_YUV420_8; + break; + + case MEDIA_BUS_FMT_VUY8_1X24: + csi_dev->ipi_dt = CSI_2_YUV420_10; + break; + + case MEDIA_BUS_FMT_Y8_1X8: + csi_dev->ipi_dt = CSI_2_RAW8; + break; + + case MEDIA_BUS_FMT_Y10_1X10: + csi_dev->ipi_dt = CSI_2_RAW8; + break; + + case MEDIA_BUS_FMT_SBGGR6_1X8: + csi_dev->ipi_dt = CSI_2_RAW6; + break; + + case MEDIA_BUS_FMT_SBGGR7_1X8: + csi_dev->ipi_dt = CSI_2_RAW7; + break; + + default: + break; + } + dw_mipi_csi_write(csi_dev, reg.IPI_DATA_TYPE, csi_dev->ipi_dt); + } + dev_info(dev, "Selected IPI Data Type 0x%X\n", csi_dev->ipi_dt); +} + +void dw_mipi_csi_fill_timings(struct dw_csi *dev, uint32_t width, uint32_t height) +{ + dev->hw.virtual_ch = 0; + dev->hw.ipi_color_mode = COLOR48; + dev->hw.ipi_auto_flush = 1; + dev->hw.ipi_mode = CAMERA_TIMING; + dev->hw.ipi_cut_through = CTINACTIVE; + dev->hw.ipi_adv_features = LINE_EVENT_SELECTION(EVSELAUTO); + dev->hw.htotal = width + dev->hw.hsa + + dev->hw.hbp + dev->hw.hsd; + dev->hw.vactive = height; + dev->hw.output = 2; + + dev_dbg(dev->dev, "*********** timings *********\n"); + dev_dbg(dev->dev, "Horizontal Sync Active: %d\n", dev->hw.hsa); + dev_dbg(dev->dev, "Horizontal Back Porch: %d\n", dev->hw.hbp); + dev_dbg(dev->dev, "Horizontal Width: %d\n", width); + dev_dbg(dev->dev, "Horizontal Total: %d\n", dev->hw.htotal); + dev_dbg(dev->dev, "Vertical Sync Active: %d\n", dev->hw.vsa); + dev_dbg(dev->dev, "Vertical Back Porch: %d\n", dev->hw.vbp); + dev_dbg(dev->dev, "Vertical Front Porch: %d\n", dev->hw.vfp); + dev_dbg(dev->dev, "Vertical Active: %d\n", dev->hw.vactive); +} + +void dw_mipi_csi_start(struct dw_csi *csi_dev) +{ + struct device *dev = csi_dev->dev; + + dw_mipi_csi_write(csi_dev, reg.N_LANES, (csi_dev->hw.num_lanes - 1)); + dev_info(dev, "number of lanes: %d\n", csi_dev->hw.num_lanes); + + /* IPI Related Configuration */ + if (csi_dev->hw.output == IPI_OUT || csi_dev->hw.output == BOTH_OUT) { + if (csi_dev->hw_version_major >= 1) { + if (csi_dev->hw_version_minor >= 20) + dw_mipi_csi_write(csi_dev, + reg.IPI_ADV_FEATURES, + csi_dev->hw.ipi_adv_features); + if (csi_dev->hw_version_minor >= 30) + dw_mipi_csi_write(csi_dev, + reg.IPI_SOFTRSTN, 0x1); + } + /* address | data, | shift | width */ + dw_mipi_csi_write_part(csi_dev, reg.IPI_MODE, 1, 24, 1); + dw_mipi_csi_write_part(csi_dev, + reg.IPI_MODE, + csi_dev->hw.ipi_mode, + 0, 1); + if (csi_dev->hw.ipi_mode == CAMERA_TIMING) { + dw_mipi_csi_write(csi_dev, + reg.IPI_ADV_FEATURES, + LINE_EVENT_SELECTION(EVSELPROG) | + EN_VIDEO | + EN_LINE_START | + EN_NULL | + EN_BLANKING | + EN_EMBEDDED); + } + dw_mipi_csi_write_part(csi_dev, + reg.IPI_MODE, + csi_dev->hw.ipi_color_mode, + 8, 1); + dw_mipi_csi_write_part(csi_dev, + reg.IPI_MODE, + csi_dev->hw.ipi_cut_through, + 16, 1); + dw_mipi_csi_write_part(csi_dev, + reg.IPI_VCID, + csi_dev->hw.virtual_ch, + 0, 2); + dw_mipi_csi_write_part(csi_dev, + reg.IPI_MEM_FLUSH, + csi_dev->hw.ipi_auto_flush, + 8, 1); + + dev_vdbg(dev, "*********** config *********\n"); + dev_vdbg(dev, "IPI enable: %s\n", + csi_dev->hw.output ? "YES" : "NO"); + dev_vdbg(dev, "video mode transmission type: %s timming\n", + csi_dev->hw.ipi_mode ? "controller" : "camera"); + dev_vdbg(dev, "Color Mode: %s\n", + csi_dev->hw.ipi_color_mode ? "16 bits" : "48 bits"); + dev_vdbg(dev, "Cut Through Mode: %s\n", + csi_dev->hw.ipi_cut_through ? "enable" : "disable"); + dev_vdbg(dev, "Virtual Channel: %d\n", + csi_dev->hw.virtual_ch); + dev_vdbg(dev, "Auto-flush: %d\n", + csi_dev->hw.ipi_auto_flush); + dw_mipi_csi_write(csi_dev, reg.IPI_SOFTRSTN, 1); + + if (csi_dev->hw.ipi_mode == AUTO_TIMING) + phy_power_on(csi_dev->phy); + + dw_mipi_csi_write(csi_dev, + reg.IPI_HSA_TIME, csi_dev->hw.hsa); + dw_mipi_csi_write(csi_dev, + reg.IPI_HBP_TIME, csi_dev->hw.hbp); + dw_mipi_csi_write(csi_dev, + reg.IPI_HSD_TIME, csi_dev->hw.hsd); + dw_mipi_csi_write(csi_dev, + reg.IPI_HLINE_TIME, csi_dev->hw.htotal); + dw_mipi_csi_write(csi_dev, + reg.IPI_VSA_LINES, csi_dev->hw.vsa); + dw_mipi_csi_write(csi_dev, + reg.IPI_VBP_LINES, csi_dev->hw.vbp); + dw_mipi_csi_write(csi_dev, + reg.IPI_VFP_LINES, csi_dev->hw.vfp); + dw_mipi_csi_write(csi_dev, + reg.IPI_VACTIVE_LINES, csi_dev->hw.vactive); + } + phy_power_on(csi_dev->phy); +} + +int dw_mipi_csi_irq_handler(struct dw_csi *csi_dev) +{ + struct device *dev = csi_dev->dev; + u32 global_int_status, i_sts; + unsigned long flags; + + spin_lock_irqsave(&csi_dev->slock, flags); + global_int_status = dw_mipi_csi_read(csi_dev, reg.INTERRUPT); + + if (global_int_status & csi_int.PHY_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PHY_FATAL); + dev_err_ratelimited(dev, "int %08X: PHY FATAL: %08X\n", + reg.INT_PHY_FATAL, i_sts); + } + + if (global_int_status & csi_int.PKT_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PKT_FATAL); + dev_err_ratelimited(dev, "int %08X: PKT FATAL: %08X\n", + reg.INT_PKT_FATAL, i_sts); + } + + if (global_int_status & csi_int.FRAME_FATAL && + csi_dev->hw_version_major == 1 && + csi_dev->hw_version_minor == 30) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_FRAME_FATAL); + dev_err_ratelimited(dev, "int %08X: FRAME FATAL: %08X\n", + reg.INT_FRAME_FATAL, i_sts); + } + + if (global_int_status & csi_int.PHY) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PHY); + dev_err_ratelimited(dev, "int %08X: PHY: %08X\n", + reg.INT_PHY, i_sts); + } + + if (global_int_status & csi_int.PKT && + csi_dev->hw_version_major == 1 && + csi_dev->hw_version_minor <= 30) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PKT); + dev_err_ratelimited(dev, "int %08X: PKT: %08X\n", + reg.INT_PKT, i_sts); + } + + if (global_int_status & csi_int.LINE) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_LINE); + dev_err_ratelimited(dev, "int %08X: LINE: %08X\n", + reg.INT_LINE, i_sts); + } + + if (global_int_status & csi_int.IPI) { + i_sts = dw_mipi_csi_read(csi_dev, reg.INT_IPI); + dev_err_ratelimited(dev, "int %08X: IPI: %08X\n", + reg.INT_IPI, i_sts); + } + + if (global_int_status & csi_int.BNDRY_FRAME_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_BNDRY_FRAME_FATAL); + dev_err_ratelimited(dev, + "int %08X: ST_BNDRY_FRAME_FATAL: %08X\n", + reg.ST_BNDRY_FRAME_FATAL, i_sts); + } + + if (global_int_status & csi_int.SEQ_FRAME_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_SEQ_FRAME_FATAL); + dev_err_ratelimited(dev, + "int %08X: ST_SEQ_FRAME_FATAL: %08X\n", + reg.ST_SEQ_FRAME_FATAL, i_sts); + } + + if (global_int_status & csi_int.CRC_FRAME_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_CRC_FRAME_FATAL); + dev_err_ratelimited(dev, + "int %08X: ST_CRC_FRAME_FATAL: %08X\n", + reg.ST_CRC_FRAME_FATAL, i_sts); + } + + if (global_int_status & csi_int.PLD_CRC_FATAL) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_PLD_CRC_FATAL); + dev_err_ratelimited(dev, + "int %08X: ST_PLD_CRC_FATAL: %08X\n", + reg.ST_PLD_CRC_FATAL, i_sts); + } + + if (global_int_status & csi_int.DATA_ID) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_DATA_ID); + dev_err_ratelimited(dev, "int %08X: ST_DATA_ID: %08X\n", + reg.ST_DATA_ID, i_sts); + } + + if (global_int_status & csi_int.ECC_CORRECTED) { + i_sts = dw_mipi_csi_read(csi_dev, reg.ST_ECC_CORRECT); + dev_err_ratelimited(dev, "int %08X: ST_ECC_CORRECT: %08X\n", + reg.ST_ECC_CORRECT, i_sts); + } + + spin_unlock_irqrestore(&csi_dev->slock, flags); + + return 1; +} + +void dw_mipi_csi_get_version(struct dw_csi *csi_dev) +{ + u32 hw_version; + + hw_version = dw_mipi_csi_read(csi_dev, reg.VERSION); + csi_dev->hw_version_major = (u8)((hw_version >> 24) - '0'); + csi_dev->hw_version_minor = (u8)((hw_version >> 16) - '0'); + csi_dev->hw_version_minor = csi_dev->hw_version_minor * 10; + csi_dev->hw_version_minor += (u8)((hw_version >> 8) - '0'); +} + +int dw_mipi_csi_specific_mappings(struct dw_csi *csi_dev) +{ + struct device *dev = csi_dev->dev; + + if (csi_dev->hw_version_major == 1) { + if (csi_dev->hw_version_minor == 30) { + /* + * Hardware registers that were + * exclusive to version < 1.40 + */ + reg.INT_FRAME_FATAL = 0x100; + reg.MASK_INT_FRAME_FATAL = 0x104; + reg.FORCE_INT_FRAME_FATAL = 0x108; + reg.INT_PKT = 0x120; + reg.MASK_INT_PKT = 0x124; + reg.FORCE_INT_PKT = 0x128; + + /* interrupt source present until this release */ + csi_int.PKT = BIT(17); + csi_int.LINE = BIT(18); + csi_int.IPI = BIT(19); + csi_int.FRAME_FATAL = BIT(2); + + } else if (csi_dev->hw_version_minor == 40) { + /* + * HW registers that were added + * to version 1.40 + */ + reg.ST_BNDRY_FRAME_FATAL = 0x280; + reg.MSK_BNDRY_FRAME_FATAL = 0x284; + reg.FORCE_BNDRY_FRAME_FATAL = 0x288; + reg.ST_SEQ_FRAME_FATAL = 0x290; + reg.MSK_SEQ_FRAME_FATAL = 0x294; + reg.FORCE_SEQ_FRAME_FATAL = 0x298; + reg.ST_CRC_FRAME_FATAL = 0x2a0; + reg.MSK_CRC_FRAME_FATAL = 0x2a4; + reg.FORCE_CRC_FRAME_FATAL = 0x2a8; + reg.ST_PLD_CRC_FATAL = 0x2b0; + reg.MSK_PLD_CRC_FATAL = 0x2b4; + reg.FORCE_PLD_CRC_FATAL = 0x2b8; + reg.ST_DATA_ID = 0x2c0; + reg.MSK_DATA_ID = 0x2c4; + reg.FORCE_DATA_ID = 0x2c8; + reg.ST_ECC_CORRECT = 0x2d0; + reg.MSK_ECC_CORRECT = 0x2d4; + reg.FORCE_ECC_CORRECT = 0x2d8; + reg.DATA_IDS_VC_1 = 0x0; + reg.DATA_IDS_VC_2 = 0x0; + reg.VC_EXTENSION = 0x0; + + /* interrupts map were changed */ + csi_int.LINE = BIT(17); + csi_int.IPI = BIT(18); + csi_int.BNDRY_FRAME_FATAL = BIT(2); + csi_int.SEQ_FRAME_FATAL = BIT(3); + csi_int.CRC_FRAME_FATAL = BIT(4); + csi_int.PLD_CRC_FATAL = BIT(5); + csi_int.DATA_ID = BIT(6); + csi_int.ECC_CORRECTED = BIT(7); + + } else { + dev_info(dev, "Version minor not supported."); + } + } else { + dev_info(dev, "Version major not supported."); + } + return 0; +} + +void dw_mipi_csi_dump(struct dw_csi *csi_dev) +{ + dw_print(reg.VERSION); + dw_print(reg.N_LANES); + dw_print(reg.CTRL_RESETN); + dw_print(reg.INTERRUPT); + dw_print(reg.DATA_IDS_1); + dw_print(reg.DATA_IDS_2); + dw_print(reg.IPI_MODE); + dw_print(reg.IPI_VCID); + dw_print(reg.IPI_DATA_TYPE); + dw_print(reg.IPI_MEM_FLUSH); + dw_print(reg.IPI_HSA_TIME); + dw_print(reg.IPI_HBP_TIME); + dw_print(reg.IPI_HSD_TIME); + dw_print(reg.IPI_HLINE_TIME); + dw_print(reg.IPI_SOFTRSTN); + dw_print(reg.IPI_ADV_FEATURES); + dw_print(reg.IPI_VSA_LINES); + dw_print(reg.IPI_VBP_LINES); + dw_print(reg.IPI_VFP_LINES); + dw_print(reg.IPI_VACTIVE_LINES); + dw_print(reg.IPI_DATA_TYPE); + dw_print(reg.VERSION); + dw_print(reg.IPI_ADV_FEATURES); +} diff --git a/vvcam_ry/native/csi/dw-mipi-csi.h b/vvcam_ry/native/csi/dw-mipi-csi.h new file mode 100755 index 0000000..5c5579f --- /dev/null +++ b/vvcam_ry/native/csi/dw-mipi-csi.h @@ -0,0 +1,285 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. + * + * Synopsys DesignWare MIPI CSI-2 Host controller driver + * + * Author: Luis Oliveira + */ + +#ifndef _DW_MIPI_CSI_H__ +#define _DW_MIPI_CSI_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Advanced features */ +#define IPI_DT_OVERWRITE BIT(0) +#define DATA_TYPE_OVERWRITE(dt) (((dt) & GENMASK(5, 0)) << 8) +#define LINE_EVENT_SELECTION(n) ((n) << 16) + +enum line_event { + EVSELAUTO = 0, + EVSELPROG = 1, +}; + +#define EN_VIDEO BIT(17) +#define EN_LINE_START BIT(18) +#define EN_NULL BIT(19) +#define EN_BLANKING BIT(20) +#define EN_EMBEDDED BIT(21) +#define IPI_SYNC_EVENT_MODE(n) ((n) << 24) + +enum sync_event { + SYNCEVFSN = 0, + SYNCEVFS = 1, +}; + +/* DW MIPI CSI-2 register addresses*/ + +struct R_CSI2 { + u16 VERSION; + u16 N_LANES; + u16 CTRL_RESETN; + u16 INTERRUPT; + u16 DATA_IDS_1; + u16 DATA_IDS_2; + u16 DATA_IDS_VC_1; + u16 DATA_IDS_VC_2; + u16 IPI_MODE; + u16 IPI_VCID; + u16 IPI_DATA_TYPE; + u16 IPI_MEM_FLUSH; + u16 IPI_HSA_TIME; + u16 IPI_HBP_TIME; + u16 IPI_HSD_TIME; + u16 IPI_HLINE_TIME; + u16 IPI_SOFTRSTN; + u16 IPI_ADV_FEATURES; + u16 IPI_VSA_LINES; + u16 IPI_VBP_LINES; + u16 IPI_VFP_LINES; + u16 IPI_VACTIVE_LINES; + u16 VC_EXTENSION; + u16 INT_PHY_FATAL; + u16 MASK_INT_PHY_FATAL; + u16 FORCE_INT_PHY_FATAL; + u16 INT_PKT_FATAL; + u16 MASK_INT_PKT_FATAL; + u16 FORCE_INT_PKT_FATAL; + u16 INT_FRAME_FATAL; + u16 MASK_INT_FRAME_FATAL; + u16 FORCE_INT_FRAME_FATAL; + u16 INT_PHY; + u16 MASK_INT_PHY; + u16 FORCE_INT_PHY; + u16 INT_PKT; + u16 MASK_INT_PKT; + u16 FORCE_INT_PKT; + u16 INT_LINE; + u16 MASK_INT_LINE; + u16 FORCE_INT_LINE; + u16 INT_IPI; + u16 MASK_INT_IPI; + u16 FORCE_INT_IPI; + u16 ST_BNDRY_FRAME_FATAL; + u16 MSK_BNDRY_FRAME_FATAL; + u16 FORCE_BNDRY_FRAME_FATAL; + u16 ST_SEQ_FRAME_FATAL; + u16 MSK_SEQ_FRAME_FATAL; + u16 FORCE_SEQ_FRAME_FATAL; + u16 ST_CRC_FRAME_FATAL; + u16 MSK_CRC_FRAME_FATAL; + u16 FORCE_CRC_FRAME_FATAL; + u16 ST_PLD_CRC_FATAL; + u16 MSK_PLD_CRC_FATAL; + u16 FORCE_PLD_CRC_FATAL; + u16 ST_DATA_ID; + u16 MSK_DATA_ID; + u16 FORCE_DATA_ID; + u16 ST_ECC_CORRECT; + u16 MSK_ECC_CORRECT; + u16 FORCE_ECC_CORRECT; +}; + +/* Interrupt Masks */ +struct interrupt_type { + u32 PHY_FATAL; + u32 PKT_FATAL; + u32 FRAME_FATAL; + u32 PHY; + u32 PKT; + u32 LINE; + u32 IPI; + u32 BNDRY_FRAME_FATAL; + u32 SEQ_FRAME_FATAL; + u32 CRC_FRAME_FATAL; + u32 PLD_CRC_FATAL; + u32 DATA_ID; + u32 ECC_CORRECTED; +}; + +/* IPI Data Types */ +enum data_type { + CSI_2_YUV420_8 = 0x18, + CSI_2_YUV420_10 = 0x19, + CSI_2_YUV420_8_LEG = 0x1A, + CSI_2_YUV420_8_SHIFT = 0x1C, + CSI_2_YUV420_10_SHIFT = 0x1D, + CSI_2_YUV422_8 = 0x1E, + CSI_2_YUV422_10 = 0x1F, + CSI_2_RGB444 = 0x20, + CSI_2_RGB555 = 0x21, + CSI_2_RGB565 = 0x22, + CSI_2_RGB666 = 0x23, + CSI_2_RGB888 = 0x24, + CSI_2_RAW6 = 0x28, + CSI_2_RAW7 = 0x29, + CSI_2_RAW8 = 0x2A, + CSI_2_RAW10 = 0x2B, + CSI_2_RAW12 = 0x2C, + CSI_2_RAW14 = 0x2D, + CSI_2_RAW16 = 0x2E, + CSI_2_RAW20 = 0x2F, + USER_DEFINED_1 = 0x30, + USER_DEFINED_2 = 0x31, + USER_DEFINED_3 = 0x32, + USER_DEFINED_4 = 0x33, + USER_DEFINED_5 = 0x34, + USER_DEFINED_6 = 0x35, + USER_DEFINED_7 = 0x36, + USER_DEFINED_8 = 0x37, +}; + +/* DWC MIPI CSI-2 output types */ +enum output { + IPI_OUT = 0, + IDI_OUT = 1, + BOTH_OUT = 2 +}; + +/* IPI color components */ +enum color_mode { + COLOR48 = 0, + COLOR16 = 1 +}; + +/* IPI cut through */ +enum cut_through { + CTINACTIVE = 0, + CTACTIVE = 1 +}; + +/* IPI output types */ +enum ipi_output { + CAMERA_TIMING = 0, + AUTO_TIMING = 1 +}; + +/* Format template */ +struct mipi_fmt { + u32 mbus_code; + u8 depth; + u32 width; + u32 height; +}; + +struct mipi_dt { + u32 hex; + char *name; +}; + +/* CSI specific configuration */ +struct csi_data { + u32 num_lanes; + u32 dphy_freq; //MBPS + u32 pclk; + u32 fps; + u32 bpp; + u32 output; + u32 ipi_mode; + u32 ipi_adv_features; + u32 ipi_cut_through; + u32 ipi_color_mode; + u32 ipi_auto_flush; + u32 virtual_ch; + u32 hsa; + u32 hbp; + u32 hsd; + u32 htotal; + u32 vsa; + u32 vbp; + u32 vfp; + u32 vactive; +}; + +/* Structure to embed device driver information */ +struct dw_csi { + //struct v4l2_subdev sd; + //struct video_device vdev; + //struct v4l2_device v4l2_dev; + struct device *dev; + //struct media_pad pads[CSI_PADS_NUM]; + struct mipi_fmt *fmt; + //struct v4l2_mbus_framefmt format; + void __iomem *base_address; + void __iomem *demo; + void __iomem *csc; + int ctrl_irq_number; + int demosaic_irq; + struct csi_data hw; + struct reset_control *rst; + struct phy *phy; + struct dw_csih_pdata *config; + struct mutex lock; /* protect resources sharing */ + spinlock_t slock; /* interrupt handling lock */ + u8 ipi_dt; + u8 index; + u8 hw_version_major; + u16 hw_version_minor; +}; + +void dw_mipi_csi_reset(struct dw_csi *csi_dev); +int dw_mipi_csi_mask_irq_power_off(struct dw_csi *csi_dev); +int dw_mipi_csi_hw_stdby(struct dw_csi *csi_dev); +void dw_mipi_csi_set_ipi_fmt(struct dw_csi *csi_dev); +void dw_mipi_csi_start(struct dw_csi *csi_dev); +int dw_mipi_csi_irq_handler(struct dw_csi *csi_dev); +void dw_mipi_csi_get_version(struct dw_csi *csi_dev); +int dw_mipi_csi_specific_mappings(struct dw_csi *csi_dev); +void dw_mipi_csi_fill_timings(struct dw_csi *dev, uint32_t width, uint32_t height); +void dw_mipi_csi_dump(struct dw_csi *csi_dev); + +#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3) +int dw_csi_create_capabilities_sysfs(struct platform_device *pdev); +int dw_csi_remove_capabilities_sysfs(struct platform_device *pdev); +#endif + +int dw_mipi_csi_s_power(struct dw_csi *dev, int on); +int dw_mipi_csi_log_status(struct dw_csi *dev); + +static inline void dw_mipi_csi_write(struct dw_csi *dev, + u32 address, u32 data) +{ + writel(data, dev->base_address + address); +} + +static inline u32 dw_mipi_csi_read(struct dw_csi *dev, u32 address) +{ + return readl(dev->base_address + address); +} + +#endif /*_DW_MIPI_CSI_H__ */ diff --git a/vvcam_ry/native/csi/nwl/platform_nwl_csi_driver.c b/vvcam_ry/native/csi/nwl/platform_nwl_csi_driver.c new file mode 100755 index 0000000..3671dee --- /dev/null +++ b/vvcam_ry/native/csi/nwl/platform_nwl_csi_driver.c @@ -0,0 +1,168 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#if defined(ISP8000L_V2008) || defined(ISP8000_V2009) +#include //Fix thead compile error. +#endif + + +#include "nwl_regs.h" +#include "csi_ioctl.h" + +static int nwl_register_write(void * dev,unsigned int addr, unsigned int data) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + writel(data, base_addr + addr); + + return 0; +} + +#if 0 +static int nwl_register_read(void * dev,unsigned int addr, unsigned int *data) +{ + void __iomem *base_addr; + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + base_addr = nwl_csi_dev->base; + + *data = readl(base_addr + addr); + + return 0; +} +#endif + +int vvnative_csi_set_stream_control(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + u32 clock_status; + u32 data_status; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + if (nwl_csi_dev->streaming_enable) + { + clock_status = 0x01; + data_status = 0xFF; + } + else + { + clock_status = 0x00; + data_status = 0x00; + } + + nwl_register_write(dev,MRV_MIPICSI_LANES_CLK, clock_status); + nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, data_status); + return 0; +} + +int vvnative_csi_set_cfg(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + nwl_register_write(dev,MRV_MIPICSI_NUM_LANES, nwl_csi_dev->csi_lane_cfg.mipi_lane_num); + + return 0; +} + +int vvnative_csi_module_init(void * dev) +{ + struct vvcam_csi_dev *nwl_csi_dev; + + if (dev == NULL) + return -1; + nwl_csi_dev = dev; + + nwl_register_write(dev,MRV_MIPICSI_NUM_LANES, 0x04); + nwl_register_write(dev,MRV_MIPICSI_LANES_CLK, 0x01); + nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, 0x0F); + nwl_register_write(dev,MRV_MIPICSI_IGNORE_VC, 0x01); + + nwl_register_write(dev,MRV_MIPICSI_FIFO_SENSD_LEVEL, 0x41); + nwl_register_write(dev,MRV_MIPICSI_VID_VSYNC, 0x20); + nwl_register_write(dev,MRV_MIPICSI_VID_HSYNC_FP, 0x20); + nwl_register_write(dev,MRV_MIPICSI_VID_HSYNC, 0x01); + nwl_register_write(dev,MRV_MIPICSI_VID_HSYNC_BP, 0x20); + + if (nwl_csi_dev->device_idx == 0) + { + nwl_register_write(dev,MRV_MIPICSI0_CTRL, 0x4); + }else + { + nwl_register_write(dev,MRV_MIPICSI1_CTRL, 0x4); + } + + return 0; +} + +int vvnative_csi_module_exit(void * dev) +{ + + return 0; +} diff --git a/vvcam_ry/native/dec400/Makefile b/vvcam_ry/native/dec400/Makefile new file mode 100755 index 0000000..d17df4c --- /dev/null +++ b/vvcam_ry/native/dec400/Makefile @@ -0,0 +1,19 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_dec400 + +obj-m +=$(TARGET).o + +$(TARGET)-objs += dec400.o +$(TARGET)-objs += dec400_ioctl.o +EXTRA_CFLAGS += -I$(PWD)/../../common + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean diff --git a/vvcam_ry/native/dec400/dec400.c b/vvcam_ry/native/dec400/dec400.c new file mode 100755 index 0000000..d4fe125 --- /dev/null +++ b/vvcam_ry/native/dec400/dec400.c @@ -0,0 +1,211 @@ +/* + * Verisilicon DEC400 Driver for FalconLite. + * + * Author: Wei Weiyu + * + * Copyright (C) 2020 VeriSilicon Microelectronics (Shanghai) Co., Ltd. + * + */ + +#include "dec400.h" +#include "dec400_ioctl.h" + +static unsigned int dec400_major = 0; +static unsigned int dec400_minor = 0; +struct class *dec400_class; +static unsigned int device_register_index = 0; + +static int dec400_open(struct inode * inode, struct file * file) +{ + struct dec400_dev *pdriver_dev; + + pr_info("entry %s\n", __func__); + pdriver_dev = container_of(inode->i_cdev, struct dec400_dev, cdev); + file->private_data = pdriver_dev; + + pr_info("exit %s\n", __func__); + return 0; +}; + +static long dec400_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct dec400_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + mutex_lock(&pdriver_dev->mutex); + ret = dec400_priv_ioctl(pdriver_dev, cmd ,(void *)arg); + mutex_unlock(&pdriver_dev->mutex); + + pr_info("exit %s\n", __func__); + + return ret; +}; + +static int dec400_release(struct inode * inode, struct file * file) +{ + struct dec400_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + + pdriver_dev = container_of(inode->i_cdev, struct dec400_dev, cdev); + file->private_data = pdriver_dev; + + pr_info("exit %s\n", __func__); + + return 0; +}; + +struct file_operations dec400_fops = { + .owner = THIS_MODULE, + .open = dec400_open, + .release = dec400_release, + .unlocked_ioctl = dec400_ioctl, + .mmap = NULL, + .poll = NULL, +}; + +static int dec400_probe(struct platform_device *pdev) +{ + int ret = 0; + struct dec400_dev *pdriver_dev; + struct resource *mem; + + pr_info("enter %s\n", __func__); + pdev->id = device_register_index; + if (pdev->id >= DEC400_MAXCNT) { + pr_err("%s:pdev id is %d error\n", __func__, pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev, sizeof(struct dec400_dev), GFP_KERNEL); + if (pdriver_dev == NULL) { + pr_err("%s:alloc struct dec400_dev error\n", __func__); + return -ENOMEM; + } + pr_info("%s:isp[%d]: pdriver_dev =0x%px\n", __func__, pdev->id, pdriver_dev); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pdriver_dev->reg_base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(pdriver_dev->reg_base)) + return PTR_ERR(pdriver_dev->reg_base); + pr_info("%s:isp[%d]: pdriver_dev->base=0x%px\n", __func__, + pdev->id, pdriver_dev->reg_base); + + pdriver_dev->id = pdev->id; + mutex_init(&pdriver_dev->mutex); + platform_set_drvdata(pdev, pdriver_dev); + + if (device_register_index == 0) { + int ret; + + if (dec400_major == 0) { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, DEC400_MAXCNT, DEC400_NAME); + if (ret != 0) { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + dec400_major = MAJOR(pdriver_dev->devt); + dec400_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(dec400_major, dec400_minor); + ret = register_chrdev_region(pdriver_dev->devt, DEC400_MAXCNT, DEC400_NAME); + if (ret) { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + dec400_class = class_create(THIS_MODULE, DEC400_NAME); + if (IS_ERR(dec400_class)) { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(dec400_major, dec400_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &dec400_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = dec400_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", DEC400_NAME, pdev->id); + + device_register_index++; + pr_info("exit %s:[%d]\n", __func__, pdev->id); + + return ret; +} + + +static int dec400_remove(struct platform_device *pdev) +{ + struct dec400_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + device_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, DEC400_MAXCNT); + if (device_register_index == 0) { + class_destroy(pdriver_dev->class); + } + return 0; +} + + +static const struct of_device_id dec400_of_match_table[] = { + { .compatible = "thead,dec400", }, + { }, +}; +MODULE_DEVICE_TABLE(of, dec400_of_match_table); + +static struct platform_driver dec400_driver = { + .probe = dec400_probe, + .remove = dec400_remove, + .driver = { + .owner = THIS_MODULE, + .name = DEC_DEV_NAME, + .of_match_table = dec400_of_match_table, + }, +}; + +static int __init dec400_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&dec400_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit dec400_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&dec400_driver); +} + +module_init(dec400_init_module); +module_exit(dec400_exit_module); + +MODULE_DESCRIPTION("DEC400"); +MODULE_LICENSE("GPL"); diff --git a/vvcam_ry/native/dec400/dec400.h b/vvcam_ry/native/dec400/dec400.h new file mode 100755 index 0000000..e76556d --- /dev/null +++ b/vvcam_ry/native/dec400/dec400.h @@ -0,0 +1,192 @@ +/* + * Verisilicon DEC400 Driver for FalconLite. + * + * Author: Wei Weiyu + * + * Copyright (C) 2020 VeriSilicon Microelectronics (Shanghai) Co., Ltd. + * + */ + +#ifndef __DEC_H__ +#define __DEC_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEC_DEV_NAME "thead,dec400" +#define DEC400_NAME "dec" +#define DEC400_MAXCNT 3 + +#define DEC_CHIP_REV 0x00 +#define DEC_CHIP_DATA 0x04 +#define DEC_CONTROL 0x0800 +#define DEC_CONTROL_EX 0x0804 +#define DEC_CONTROL_EX2 0x0808 +#define DEC_INTR_EN 0x080c +#define DEC_INTR_EN_EX 0x0810 +#define DEC_INTR_EN_EX2 0x0814 +#define DEC_WRITE_CFG_CH(n) (0x0980 + (n) * 4) +#define DEC_WRITE_EX_CFG_CH(n) (0x0a00 + (n) * 4) +#define DEC_WRITE_BUF_BASE_CH(n) (0x0d80 + (n) * 4) +#define DEC_WRITE_BUF_END_CH(n) (0x0e80 + (n) * 4) +#define DEC_WRITE_CACHE_BASE_CH(n) (0x1180 + (n) * 4) +#define DEC_READ_CFG_CH(n) (0x0880 + (n) * 4) +#define DEC_READ_EX_CFG_CH(n) (0x0900 + (n) * 4) +#define DEC_READ_BUF_BASE_CH(n) (0x0A80 + (n) * 4) +#define DEC_READ_BUF_END_CH(n) (0x0B80 + (n) * 4) +#define DEC_READ_CACHE_BASE_CH(n) (0x1080 + (n) * 4) + + +/* dec register bit config */ +enum dec_control_regval { + DEC_FLUSH = 1 << 0, + DEC_EN = 0 << 1, + DEC_BYPASS = 1 << 1, + DEC_RAM_CLK_GATING_EN = 1 << 2, + DEC_DEBUG_REG_EN = 0 << 3, + DEC_DEBUG_REG_DIS = 1 << 3, + DEC_SOFT_RESET = 1 << 4, + DEC_WRITE_ALIGN_MODE = 1 << 8, + DEC_HW_FLUSH_DIS = 1 << 16, + DEC_HW_FLUSH_EN = 0 << 16 +}; + +/* dec register bit config ex */ +enum dec_control_ex_regval { + WRITE_MISS_POLICY = 1 << 19, + READ_MISS_POLICY = 1 << 29, +}; + +enum dec_intr_regval { + DEC_INTR_AXI_BUS_ERR = 1 << 31 +}; + +enum dec_write_cfg_regval { + DEC_COMPRESS_EN = 1 << 0, + DEC_FMT_ARGB8 = 0 << 3, + DEC_FMT_XRGB8 = 1 << 3, + DEC_FMT_AYUV = 2 << 3, + DEC_FMT_UYVY = 3 << 3, + DEC_FMT_YUY2 = 4 << 3, + DEC_FMT_YUV_ONLY = 5 << 3, + DEC_FMT_UV_MIX = 6 << 3, + DEC_FMT_ARGB4 = 7 << 3, + DEC_FMT_XRGB4 = 8 << 3, + DEC_FMT_A1RGB5 = 9 << 3, + DEC_FMT_X1RGB5 = 10 << 3, + DEC_FMT_R5G6B5 = 11 << 3, + DEC_FMT_A2R10G10B10 = 15 << 3, + DEC_FMT_BAYER = 16 << 3, + DEC_FMT_COEFFICIENT = 18 << 3, + DEC_FMT_ARGB16 = 19 << 3, + DEC_FMT_X2RGB10 = 21 << 3, + DEC_ALIGN_1_BYTE = 0 << 16, + DEC_ALIGN_16_BYTE = 1 << 16, + DEC_ALIGN_32_BYTE = 2 << 16, + DEC_ALIGN_64_BYTE = 3 << 16, + DEC_TILE8X8_XMAJOR = 0 << 25, + DEC_TILE8X8_YMAJOR = 1 << 25, + DEC_TILE16X4 = 2 << 25, + DEC_TILE8X4 = 3 << 25, + DEC_TILE4X8 = 4 << 25, + DEC_RASTER16X4 = 6 << 25, + DEC_TILE64X4 = 7 << 25, + DEC_TILE32X4 = 8 << 25, + DEC_RASTER256X1 = 9 << 25, + DEC_RASTER128X1 = 10 << 25, + DEC_RASTER64X4 = 11 << 25, + DEC_RASTER256X2 = 12 << 25, + DEC_RASTER128X2 = 13 << 25, + DEC_RASTER128X4 = 14 << 25, + DEC_RASTER64X1 = 15 << 25, + DEC_TILE16X8 = 16 << 25, + DEC_TILE8X16 = 17 << 25, + DEC_RASTER512X1 = 18 << 25, + DEC_RASTER32X4 = 19 << 25, + DEC_RASTER64X2 = 20 << 25, + DEC_RASTER32X2 = 21 << 25, + DEC_RASTER32X1 = 22 << 25, + DEC_RASTER16X1 = 23 << 25, + DEC_TILE128X4 = 24 << 25, + DEC_TILE256X4 = 25 << 25, + DEC_TILE512X4 = 26 << 25, + DEC_TILE16X16 = 27 << 25, + DEC_TILE32X16 = 28 << 25, + DEC_TILE64X16 = 29 << 25, + DEC_TILE128X8 = 30 << 25, + DEC_TILE8X4_S = 31 << 25, + DEC_TILE16X4_S = 32 << 25, + DEC_TILE32X4_S = 33 << 25, + DEC_TILE16X4_LSB = 34 << 25, + DEC_TILE32X4_LSB = 35 << 25, + DEC_TILE32X8 = 36 << 25 +}; + +enum dec_write_ex_cfg_regval { + DEC_BIT_DEPTH_8 = 0 << 16, + DEC_BIT_DEPTH_10 = 1 << 16, + DEC_BIT_DEPTH_12 = 2 << 16, + DEC_BIT_DEPTH_14 = 3 << 16, + DEC_BIT_DEPTH_16 = 4 << 16 +}; + +enum dec_enable { + DEC_ON = 0, + DEC_OFF = 1 +}; + +struct dec_timming { + u32 h_len; + u32 h_stride; + + u32 v_len; + u32 y_total; + u32 uv_total; + u32 buffer_offset; +}; + +static struct dec_timming dec_timing[] = { + { 0x280, 0x280, 0x1e0, 0x4b000, 0x25800, 0x96000 }, //640x480 + { 0x200, 0x200, 0x200, 0x40000, 0x20000, 0x80000 }, //512x512 + { 0x500, 0x500, 0x2d0, 0xe1000, 0x70800, 0x1C2000 }, //1280x720 + { 0x780, 0x780, 0x438, 0x1fa400, 0xfd200, 0x3f4800 } //1920x1080 +}; + +struct dec400_dev { + int id; + //int irq; + dev_t devt; + struct class *class; + struct cdev cdev; + struct mutex mutex; + + //enum dec_enable en; + + //enum vs_format fmt; + //enum vs_vdieo_resolution res; + + //struct device *dev; + void __iomem *reg_base; + + //struct v4l2_subdev sd; + //struct vs_video_device *vdev; + + //struct workqueue_struct *work_queue; + //struct delayed_work q_buf_wk; +}; + +#endif diff --git a/vvcam_ry/native/dec400/dec400_ioctl.c b/vvcam_ry/native/dec400/dec400_ioctl.c new file mode 100755 index 0000000..fd2e4da --- /dev/null +++ b/vvcam_ry/native/dec400/dec400_ioctl.c @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include "dec400.h" +#include "dec400_ioctl.h" + +#define DEC400_WRITE_PHYSICAL_ADDR 0xc2a00000 +//#define DEC400_WRITE_PHYSICAL_ADDR 0xe10b8000 + +#define DEC400_READ_PHYSICAL_ADDR 0xe0ac8000 + +#define RES 3 +#define DEBUG + +static void dec400_write(struct dec400_dev *dec, unsigned int addr, unsigned int val) +{ + writel(val, dec->reg_base + addr); +} + +static void dec400_set_bypass(struct dec400_dev *dec, void *args) +{ + dec400_write(dec, DEC_CONTROL, DEC_BYPASS); +} + +static int dec400_compress_init(struct dec400_dev *dec, void *args) +{ + unsigned int val = 0; + + //val = 0; + //val |= DEC_EN; + //val |= 0x00FC0000; //need confirm with VSI, no any description + //dec400_write(dec, DEC_CONTROL, val); //val 0x00FC0000 + dec400_write(dec, DEC_CONTROL, 0x100008c); //0x101008c + + //val = 0; + //val |= WRITE_MISS_POLICY; + //dec400_write(dec, DEC_CONTROL_EX, val);//0x00080000 + dec400_write(dec, DEC_CONTROL_EX, 0xa0000); + + //Tile status cache's AXI read/write ID. + //val = 0x00410104; + //dec400_write(dec, DEC_CONTROL_EX2, val); + dec400_write(dec, DEC_CONTROL_EX2, 0x3fe840); + + //enable intr + dec400_write(dec, 0x80c, 0xffffffff); + dec400_write(dec, 0x810, 0xffffffff); + dec400_write(dec, 0x814, 0xffffffff); + + return 0; +} + +static int dec400_mmu_config(struct dec400_dev *dec, void *args) +{ + #define ISP0_PAGE_TABLE_ARRAY_ADDR 0xEEFFFFF0 + unsigned int val = 0; + + val = 0; + val |= DEC_EN; + val |= 0x00FC0000; //need confirm with VSI, no any description + dec400_write(dec, DEC_CONTROL, val); //val 0x00FC0000 + + dec400_write(dec, 0x0388, 0x00000001); //0xE2 gcregMMUAHBControlRegAddrs + + // table array base address + //0xFEFFFFF0 + dec400_write(dec, 0x038C, ISP0_PAGE_TABLE_ARRAY_ADDR); // 0xE3 gcregMMUAHBTableArrayBaseAddressLowRegAddrs + + //WriteRegister(reg_base, 0x00184, 0x00000001);//gcregMMUConfigurationRegAddrs, flush + dec400_write(dec, 0x01AC, 0x00000000);//dcreMMUConfigRegAddrs + + return 0; +} + +static int dec400_compress_set_buffer(struct dec400_dev *dec, void *args) +{ + unsigned int y_start = 0, y_end = 0, y_cache = 0; + unsigned int uv_start = 0, uv_end = 0, uv_cache = 0; + unsigned int val = 0; + + y_start = DEC400_WRITE_PHYSICAL_ADDR; + y_end = y_start + dec_timing[RES].y_total - 1; + y_cache = y_start + dec_timing[RES].buffer_offset; + + uv_start = y_start + dec_timing[RES].y_total; + uv_end = uv_start + dec_timing[RES].uv_total - 1; + uv_cache = y_cache + dec_timing[RES].uv_total; + +#ifdef DEBUG + pr_info("%s, dec400 y_start = 0x%x, y_end = 0x%x, uv_start = 0x%x, uv_end = 0x%x\n", + __func__, y_start, y_end, uv_start, uv_end); + pr_info("%s, dec400 y_cache = 0x%x, uv_cache = 0x%x\n", __func__, y_cache, uv_cache); +#endif + + val = 0; + val |= DEC_COMPRESS_EN; + val |= DEC_FMT_YUV_ONLY; + val |= DEC_ALIGN_32_BYTE; + val |= DEC_RASTER128X1; + dec400_write(dec, DEC_WRITE_CFG_CH(0), val); + dec400_write(dec, DEC_WRITE_EX_CFG_CH(0), 0); + dec400_write(dec, DEC_WRITE_BUF_BASE_CH(0), y_start); + dec400_write(dec, DEC_WRITE_BUF_END_CH(0), y_end); + dec400_write(dec, DEC_WRITE_CACHE_BASE_CH(0), y_cache); + dec400_write(dec, 0xf80, 0xffffffff); + +#ifdef DEBUG + pr_info("%s, dec400 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n", + __func__, + DEC_WRITE_CFG_CH(0), val, + DEC_WRITE_EX_CFG_CH(0), 0, + DEC_WRITE_BUF_BASE_CH(0), y_start, + DEC_WRITE_BUF_END_CH(0), y_end, + DEC_WRITE_CACHE_BASE_CH(0), y_cache); +#endif + + + val = 0; + val |= DEC_COMPRESS_EN; + val |= DEC_FMT_UV_MIX; + val |= DEC_ALIGN_32_BYTE; + val |= DEC_RASTER64X1; + dec400_write(dec, DEC_WRITE_CFG_CH(1), val); + dec400_write(dec, DEC_WRITE_EX_CFG_CH(1), 0); + dec400_write(dec, DEC_WRITE_BUF_BASE_CH(1), uv_start); + dec400_write(dec, DEC_WRITE_BUF_END_CH(1), uv_end); + dec400_write(dec, DEC_WRITE_CACHE_BASE_CH(1), uv_cache); + dec400_write(dec, 0xf84, 0xffffffff); + +#ifdef DEBUG + pr_info("%s, dec400+1 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n", + __func__, + DEC_WRITE_CFG_CH(1), val, + DEC_WRITE_EX_CFG_CH(1), 0, + DEC_WRITE_BUF_BASE_CH(1), uv_start, + DEC_WRITE_BUF_END_CH(1), uv_end, + DEC_WRITE_CACHE_BASE_CH(1), uv_cache); +#endif + + return 0; +} + +static int dec400_decompress_init(struct dec400_dev *dec, void *args) +{ + unsigned int val = 0; + + //val = 0; + //val |= DEC_EN; + //val |= 0x00FC0000; //need confirm with VSI, no any description + //dec400_write(dec, DEC_CONTROL, val); //val 0x00FC0000 + dec400_write(dec, DEC_CONTROL, 0x100008c); //0x101008c + + //val = 0; + //val |= WRITE_MISS_POLICY; + //dec400_write(dec, DEC_CONTROL_EX, val);//0x00080000 + dec400_write(dec, DEC_CONTROL_EX, 0xa0000); + + //Tile status cache's AXI read/write ID. + //val = 0x00410104; + //dec400_write(dec, DEC_CONTROL_EX2, val); + dec400_write(dec, DEC_CONTROL_EX2, 0x3fe840); + + //enable intr + dec400_write(dec, 0x80c, 0xffffffff); + dec400_write(dec, 0x810, 0xffffffff); + dec400_write(dec, 0x814, 0xffffffff); + + return 0; +} + +static int dec400_decompress_set_buffer(struct dec400_dev *dec, void *args) +{ + unsigned int y_start = 0, y_end = 0, y_cache = 0; + unsigned int uv_start = 0, uv_end = 0, uv_cache = 0; + unsigned int val = 0; + + y_start = DEC400_READ_PHYSICAL_ADDR; + y_end = y_start + dec_timing[RES].y_total - 1; + //y_cache = y_start + dec_timing[RES].buffer_offset; + y_cache = DEC400_WRITE_PHYSICAL_ADDR + dec_timing[RES].buffer_offset; + + uv_start = y_start + dec_timing[RES].y_total; + uv_end = uv_start + dec_timing[RES].uv_total - 1; + uv_cache = y_cache + dec_timing[RES].uv_total; + +#ifdef DEBUG + pr_info("%s, dec400 y_start = 0x%x, y_end = 0x%x, uv_start = 0x%x, uv_end = 0x%x\n", + __func__, y_start, y_end, uv_start, uv_end); + pr_info("%s, dec400 y_cache = 0x%x, uv_cache = 0x%x\n", __func__, y_cache, uv_cache); +#endif +#if 0 + dec400_write(dec, 0x00000880, 0x14020029); + dec400_write(dec, 0x00000900, 0x00000000); + dec400_write(dec, 0x00000A80, y_start); + dec400_write(dec, 0x00001080, y_cache); + dec400_write(dec, 0x00000B80, y_end); + dec400_write(dec, 0x00000884, 0x1E020031); + dec400_write(dec, 0x00000904, 0x00000000); + dec400_write(dec, 0x00000A84, uv_start); + dec400_write(dec, 0x00001084, uv_cache); + dec400_write(dec, 0x00000B84, uv_end); +#endif + val = 0; + val |= DEC_COMPRESS_EN; + val |= DEC_FMT_YUV_ONLY; + val |= DEC_ALIGN_32_BYTE; + val |= DEC_RASTER128X1; + dec400_write(dec, DEC_READ_CFG_CH(0), val); + dec400_write(dec, DEC_READ_EX_CFG_CH(0), 0); + dec400_write(dec, DEC_READ_BUF_BASE_CH(0), y_start); + dec400_write(dec, DEC_READ_BUF_END_CH(0), y_end); + dec400_write(dec, DEC_READ_CACHE_BASE_CH(0), y_cache); + +#ifdef DEBUG + pr_info("%s, dec400+1 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n", + __func__, + DEC_READ_CFG_CH(0), val, + DEC_READ_EX_CFG_CH(0), 0, + DEC_READ_BUF_BASE_CH(0), y_start, + DEC_READ_BUF_END_CH(0), y_end, + DEC_READ_CACHE_BASE_CH(0), y_cache); +#endif + val = 0; + val |= DEC_COMPRESS_EN; + val |= DEC_FMT_UV_MIX; + val |= DEC_ALIGN_32_BYTE; + val |= DEC_RASTER64X1; + dec400_write(dec, DEC_READ_CFG_CH(1), val); + dec400_write(dec, DEC_READ_EX_CFG_CH(1), 0); + dec400_write(dec, DEC_READ_BUF_BASE_CH(1), uv_start); + dec400_write(dec, DEC_READ_BUF_END_CH(1), uv_end); + dec400_write(dec, DEC_READ_CACHE_BASE_CH(1), uv_cache); + +#ifdef DEBUG + pr_info("%s, dec400+1 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n", + __func__, + DEC_READ_CFG_CH(1), val, + DEC_READ_EX_CFG_CH(1), 0, + DEC_READ_BUF_BASE_CH(1), uv_start, + DEC_READ_BUF_END_CH(1), uv_end, + DEC_READ_CACHE_BASE_CH(1), uv_cache); +#endif + return 0; +} + +unsigned int dec400_priv_ioctl(struct dec400_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + if (!dev) { + pr_err("%s invalid para\n", __func__); + return ret; + } + + switch (cmd) { + case DEC400IOC_RESET: + ret = 0; + break; + case DEC400IOC_COMPRESS_INIT: + ret = dec400_compress_init(dev, args); + break; + case DEC400IOC_COMPRESS_SET_BUFFER: + ret = dec400_compress_set_buffer(dev, args); + break; + case DEC400IOC_DECOMPRESS_INIT: + ret = dec400_decompress_init(dev, args); + break; + case DEC400IOC_DECOMPRESS_SET_BUFFER: + ret = dec400_decompress_set_buffer(dev, args); + break; + case DEC400IOC_MMU_CONFIG: + ret = dec400_mmu_config(dev, args); + break; + default: + pr_err("unsupported command %d\n", cmd); + break; + } + + return ret; +} diff --git a/vvcam_ry/native/dec400/dec400_ioctl.h b/vvcam_ry/native/dec400/dec400_ioctl.h new file mode 100755 index 0000000..8d543a3 --- /dev/null +++ b/vvcam_ry/native/dec400/dec400_ioctl.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _DEC400_IOC_H_ +#define _DEC400_IOC_H_ +#include + +enum { + DEC400IOC_RESET = 0, + DEC400IOC_WRITE_REG, + DEC400IOC_READ_REG, + DEC400IOC_COMPRESS_INIT, + DEC400IOC_DECOMPRESS_INIT, + DEC400IOC_COMPRESS_SET_BUFFER, + DEC400IOC_DECOMPRESS_SET_BUFFER, + DEC400IOC_MMU_CONFIG +}; +extern unsigned int dec400_priv_ioctl(struct dec400_dev *dev, unsigned int cmd, void *args); + +#endif /* _DEC400_IOC_H_ */ diff --git a/vvcam_ry/native/dw200/Makefile b/vvcam_ry/native/dw200/Makefile new file mode 100755 index 0000000..3279fae --- /dev/null +++ b/vvcam_ry/native/dw200/Makefile @@ -0,0 +1,23 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_dw200 + +obj-m +=$(TARGET).o + +$(TARGET)-objs += vvcam_dwe_driver_of.o +$(TARGET)-objs += ../../dw200/vivdw200_irq_queue.o +$(TARGET)-objs += ../../dw200/dw200_ioctl.o +EXTRA_CFLAGS += -I$(PWD)/../../dw200 +EXTRA_CFLAGS += -I$(PWD)/../../common + + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam_ry/native/dw200/vvcam_dwe_driver.c b/vvcam_ry/native/dw200/vvcam_dwe_driver.c new file mode 100755 index 0000000..71e505c --- /dev/null +++ b/vvcam_ry/native/dw200/vvcam_dwe_driver.c @@ -0,0 +1,389 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dw200_ioctl.h" +#include "vivdw200_irq_queue.h" + +#define VIVCAM_DWE_NAME "vivdw200" +#define VIVCAM_DWE_MAXCNT 1 + + +struct vvcam_dwe_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + void *private; + unsigned int irq_num; + bool irq_trigger; + wait_queue_head_t irq_wait; +}; + +static unsigned int vvcam_dwe_major = 0; +static unsigned int vvcam_dwe_minor = 0; +struct class *vvcam_dwe_class; +static unsigned int devise_register_index = 0; + +static unsigned int vvcam_dwe_poll(struct file * filp, poll_table *wait) +{ + unsigned int mask = 0; + struct vvcam_dwe_driver_dev *pdriver_dev = filp->private_data; + poll_wait(filp, &pdriver_dev->irq_wait, wait); + + pr_info("poll dwe_irq %d\n", pdriver_dev->irq_trigger); + + if (pdriver_dev->irq_trigger) { + mask |= POLLIN |POLLRDNORM; + pr_info("poll notify user space\n"); + pdriver_dev->irq_trigger = false; + } + return mask; +} + +irqreturn_t vivdw200_interrupt(int irq, void* dev_id) +{ + pr_info(" %s enter\n", __func__); + vivdw200_mis_t node; + unsigned int dwe_mis, vse_mis; + struct vvcam_dwe_driver_dev *pdriver_dev = dev_id; + struct dw200_subdev *pdw200 = (struct dw200_subdev *)pdriver_dev->private; + dwe_mis = 0; + vse_mis = 0; + + dwe_read_irq((struct dw200_subdev *)pdw200, &dwe_mis); + dwe_mis = dwe_mis & (~0xff00); + + if (0 != dwe_mis) { + pr_info(" %s dwe mis 0x%08x\n", __func__, dwe_mis); + dwe_clear_irq((struct dw200_subdev *)pdw200, dwe_mis <<24); + + node.val = dwe_mis; + vivdw200_write_circle_queue(&node, &pdw200->dwe_circle_list); + pdriver_dev->irq_trigger |= true; + + } + + vse_read_irq((struct dw200_subdev *)pdw200, &vse_mis); + + if (0 != vse_mis) { + pr_info(" %s vse mis 0x%08x\n", __func__, vse_mis); + vse_clear_irq((struct dw200_subdev *)pdw200, vse_mis); + node.val = vse_mis; + vivdw200_write_circle_queue(&node, &pdw200->vse_circle_list); + pdriver_dev->irq_trigger |= true; + } + if (dwe_mis || vse_mis){ + wake_up_interruptible(&pdriver_dev->irq_wait); + } else { + return IRQ_NONE; + } + pr_info(" %s exit\n", __func__); + return IRQ_HANDLED; +} +static int vvcam_dwe_open(struct inode * inode, struct file * file) +{ + struct vvcam_dwe_driver_dev *pdriver_dev; + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_dwe_driver_dev, cdev); + file->private_data = pdriver_dev; + struct dw200_subdev * pdw200; + pdw200 = (struct dw200_subdev *)pdriver_dev->private; + /*create circle queue*/ + vivdw200_create_circle_queue(&(pdw200->dwe_circle_list), QUEUE_NODE_COUNT); + vivdw200_create_circle_queue(&(pdw200->vse_circle_list), QUEUE_NODE_COUNT); + return 0; +}; + +static long vvcam_dwe_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vvcam_dwe_driver_dev *pdriver_dev; + struct dw200_subdev* pdwe_dev; + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + pdwe_dev = pdriver_dev->private; + + ret = dw200_priv_ioctl(pdwe_dev, cmd ,(void *)arg); + return ret; +}; + +static int vvcam_dwe_release(struct inode * inode, struct file * file) +{ + struct vvcam_dwe_driver_dev *pdriver_dev; + pdriver_dev = file->private_data; + struct dw200_subdev * pdw200; + pdw200 = (struct dw200_subdev *)pdriver_dev->private; + + /*destory circle queue*/ + vivdw200_destroy_circle_queue(&(pdw200->dwe_circle_list)); + vivdw200_destroy_circle_queue(&(pdw200->vse_circle_list)); + return 0; +}; + +struct file_operations vvcam_dwe_fops = { + .owner = THIS_MODULE, + .open = vvcam_dwe_open, + .release = vvcam_dwe_release, + .unlocked_ioctl = vvcam_dwe_ioctl, + .poll = vvcam_dwe_poll, +}; + +static int vvcam_dwe_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vvcam_dwe_driver_dev *pdriver_dev; + struct dw200_subdev * pdwe_dev; + struct resource *mem; + + pr_info("enter %s\n", __func__); + + if (pdev->id >= VIVCAM_DWE_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_dwe_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_soc_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_dwe_driver_dev )); + + + pdwe_dev = devm_kzalloc(&pdev->dev,sizeof(struct dw200_subdev), GFP_KERNEL); + if (pdwe_dev == NULL) + { + pr_err("%s:alloc struct vvcam_soc_dev error\n", __func__); + return -ENOMEM; + } + memset(pdwe_dev,0,sizeof(struct dw200_subdev )); + + pdwe_dev->dwe_base = ioremap(DWE_REG_BASE, DWE_REG_SIZE); + pdwe_dev->vse_base = ioremap(VSE_REG_BASE, VSE_REG_SIZE); + pdwe_dev->dwe_reset = ioremap(DWE_REG_RESET, 4); + pdwe_dev->vse_reset = ioremap(VSE_REG_RESET, 4); + + pdriver_dev->private = pdwe_dev; + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + pdriver_dev->irq_num = platform_get_irq(pdev, 0); + ret = devm_request_irq(&pdev->dev, 16, (irq_handler_t)vivdw200_interrupt, IRQF_SHARED|IRQF_TRIGGER_RISING, VIVCAM_DWE_NAME, (void*)pdriver_dev);// pdriver_dev->irq_num + if (ret != 0) { + pr_err("%s:request irq error\n", __func__); + return ret; + } + init_waitqueue_head(&pdriver_dev->irq_wait); + if (devise_register_index == 0) + { + if (vvcam_dwe_major == 0) + { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_DWE_MAXCNT, VIVCAM_DWE_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_dwe_major = MAJOR(pdriver_dev->devt); + vvcam_dwe_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_dwe_major, vvcam_dwe_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_DWE_MAXCNT, VIVCAM_DWE_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + vvcam_dwe_class = class_create(THIS_MODULE, VIVCAM_DWE_NAME); + if (IS_ERR(vvcam_dwe_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_dwe_major, vvcam_dwe_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_dwe_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_dwe_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s", VIVCAM_DWE_NAME); + + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int vvcam_dwe_remove(struct platform_device *pdev) +{ + struct vvcam_dwe_driver_dev *pdriver_dev; + struct dw200_subdev * pdwe_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + pdwe_dev = pdriver_dev->private; + iounmap(pdwe_dev->dwe_base); + iounmap(pdwe_dev->vse_base); + iounmap(pdwe_dev->dwe_reset); + iounmap(pdwe_dev->vse_reset); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_DWE_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + + return 0; +} + +static struct platform_driver vvcam_dwe_driver = { + .probe = vvcam_dwe_probe, + .remove = vvcam_dwe_remove, + .driver = { + .name = VIVCAM_DWE_NAME, + .owner = THIS_MODULE, + } +}; + +static void vvcam_dwe_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + + +static struct resource vvcam_dwe_resource[] = { + [0] = { + .start = DWE_REG_BASE, + .end = DWE_REG_BASE, + .flags = IORESOURCE_MEM, + }, +}; +static struct platform_device vvcam_dwe_pdev = { + .name = VIVCAM_DWE_NAME, + .id = 0, + .resource = vvcam_dwe_resource, + .num_resources = 1, + .dev.release = vvcam_dwe_pdev_release, +}; + +static int __init vvcam_dwe_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_device_register(&vvcam_dwe_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } + + ret = platform_driver_register(&vvcam_dwe_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + platform_device_unregister(&vvcam_dwe_pdev); + return ret; + } + + return ret; +} + +static void __exit vvcam_dwe_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_dwe_driver); + platform_device_unregister(&vvcam_dwe_pdev); +} + +module_init(vvcam_dwe_init_module); +module_exit(vvcam_dwe_exit_module); + +MODULE_DESCRIPTION("DWE"); +MODULE_LICENSE("GPL"); diff --git a/vvcam_ry/native/dw200/vvcam_dwe_driver_of.c b/vvcam_ry/native/dw200/vvcam_dwe_driver_of.c new file mode 100755 index 0000000..50b0fe5 --- /dev/null +++ b/vvcam_ry/native/dw200/vvcam_dwe_driver_of.c @@ -0,0 +1,405 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dw200_ioctl.h" +#include "vivdw200_irq_queue.h" + +#define VIVCAM_DWE_NAME "vivdw200" +#define VIVCAM_DWE_MAXCNT 1 + + +struct vvcam_dwe_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + void *private; + unsigned int irq_num[2]; + bool irq_trigger; + wait_queue_head_t irq_wait; +}; + +static unsigned int vvcam_dwe_major = 0; +static unsigned int vvcam_dwe_minor = 0; +struct class *vvcam_dwe_class; +static unsigned int devise_register_index = 0; + +static unsigned int vvcam_dwe_poll(struct file * filp, poll_table *wait) +{ + unsigned int mask = 0; + struct vvcam_dwe_driver_dev *pdriver_dev = filp->private_data; + poll_wait(filp, &pdriver_dev->irq_wait, wait); + + pr_info("poll dwe_irq %d\n", pdriver_dev->irq_trigger); + + if (pdriver_dev->irq_trigger) { + mask |= POLLIN |POLLRDNORM; + pr_info("poll notify user space\n"); + pdriver_dev->irq_trigger = false; + } + + return mask; +} + +irqreturn_t vivdw200_interrupt(int irq, void* dev_id) +{ + pr_info(" %s enter\n", __func__); + vivdw200_mis_t node; + unsigned int dwe_mis, vse_mis; + struct vvcam_dwe_driver_dev *pdriver_dev = dev_id; + struct dw200_subdev *pdw200 = (struct dw200_subdev *)pdriver_dev->private; + dwe_mis = 0; + vse_mis = 0; + + dwe_read_irq((struct dw200_subdev *)pdw200, &dwe_mis); + dwe_mis = dwe_mis & (~0xff00); + + if (0 != dwe_mis) { + pr_info(" %s dwe mis 0x%08x\n", __func__, dwe_mis); + dwe_clear_irq((struct dw200_subdev *)pdw200, dwe_mis <<24); + + node.val = dwe_mis; + vivdw200_write_circle_queue(&node, &pdw200->dwe_circle_list); + pdriver_dev->irq_trigger |= true; + + } + + vse_read_irq((struct dw200_subdev *)pdw200, &vse_mis); + + if (0 != vse_mis) { + pr_info(" %s vse mis 0x%08x\n", __func__, vse_mis); + vse_clear_irq((struct dw200_subdev *)pdw200, vse_mis); + node.val = vse_mis; + vivdw200_write_circle_queue(&node, &pdw200->vse_circle_list); + pdriver_dev->irq_trigger |= true; + } + if (dwe_mis || vse_mis){ + wake_up_interruptible(&pdriver_dev->irq_wait); + } else { + return IRQ_NONE; + } + pr_info(" %s exit\n", __func__); + return IRQ_HANDLED; +} + +static int vvcam_dwe_open(struct inode * inode, struct file * file) +{ + struct vvcam_dwe_driver_dev *pdriver_dev; + struct dw200_subdev * pdw200; + pdriver_dev = container_of(inode->i_cdev, struct vvcam_dwe_driver_dev, cdev); + file->private_data = pdriver_dev; + + pdw200 = (struct dw200_subdev *)pdriver_dev->private; + /*create circle queue*/ + vivdw200_create_circle_queue(&(pdw200->dwe_circle_list), QUEUE_NODE_COUNT); + vivdw200_create_circle_queue(&(pdw200->vse_circle_list), QUEUE_NODE_COUNT); + + return 0; +}; + +static long vvcam_dwe_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vvcam_dwe_driver_dev *pdriver_dev; + struct dw200_subdev* pdwe_dev; + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + pdwe_dev = pdriver_dev->private; + + ret = dw200_priv_ioctl(pdwe_dev, cmd ,(void *)arg); + return ret; +}; + +static int vvcam_dwe_release(struct inode * inode, struct file * file) +{ + struct vvcam_dwe_driver_dev *pdriver_dev; + pdriver_dev = file->private_data; + struct dw200_subdev * pdw200; + pdw200 = (struct dw200_subdev *)pdriver_dev->private; + + /*destory circle queue*/ + vivdw200_destroy_circle_queue(&(pdw200->dwe_circle_list)); + vivdw200_destroy_circle_queue(&(pdw200->vse_circle_list)); + + return 0; +}; + +struct file_operations vvcam_dwe_fops = { + .owner = THIS_MODULE, + .open = vvcam_dwe_open, + .release = vvcam_dwe_release, + .unlocked_ioctl = vvcam_dwe_ioctl, + .poll = vvcam_dwe_poll, +}; + +static int vvcam_dwe_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vvcam_dwe_driver_dev *pdriver_dev; + struct dw200_subdev * pdwe_dev; +// struct resource *mem; + + pr_info("enter %s\n", __func__); + + if (pdev->id >= VIVCAM_DWE_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_dwe_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_soc_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_dwe_driver_dev )); + + pdwe_dev = devm_kzalloc(&pdev->dev,sizeof(struct dw200_subdev), GFP_KERNEL); + if (pdwe_dev == NULL) + { + pr_err("%s:alloc struct vvcam_soc_dev error\n", __func__); + return -ENOMEM; + } + memset(pdwe_dev,0,sizeof(struct dw200_subdev )); + + pdwe_dev->dwe_base = ioremap(DWE_REG_BASE, DWE_REG_SIZE); + pdwe_dev->vse_base = ioremap(VSE_REG_BASE, VSE_REG_SIZE); +#ifdef DWE_REG_RESET + pdwe_dev->dwe_reset = ioremap(DWE_REG_RESET, 4); +#endif +#ifdef VSE_REG_RESET + pdwe_dev->vse_reset = ioremap(VSE_REG_RESET, 4); +#endif + pdriver_dev->private = pdwe_dev; + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + pdriver_dev->irq_num[0] = platform_get_irq(pdev, 0); + if (pdriver_dev->irq_num[0] == 0) { + pr_err("%s:dw200_[%d]: could not map IRQ\n", __func__, pdev->id); + dev_err(&pdev->dev, "could not map IRQ.\n"); + return -ENXIO; + } + pr_info("%s:dw200_[%d]: pdriver_dev->irq_num[0]=%d\n", __func__, pdev->id, pdriver_dev->irq_num[0]); + + pdriver_dev->irq_num[1] = platform_get_irq(pdev, 1); + if (pdriver_dev->irq_num[1] == 0) { + pr_err("%s:dw200_[%d]: could not map IRQ\n", __func__, pdev->id); + dev_err(&pdev->dev, "could not map IRQ.\n"); + return -ENXIO; + } + pr_info("%s:dw200_[%d]: pdriver_dev->irq_num[1]=%d\n", __func__, pdev->id, pdriver_dev->irq_num[1]); + + ret = request_irq(pdriver_dev->irq_num[0], vivdw200_interrupt, + IRQF_SHARED|IRQF_TRIGGER_RISING, "DEWARP_IRQ", (char *)pdriver_dev); + if (ret) { + pr_err("%s[%d]:request irq error!\n", __func__, __LINE__); + return ret; + } + + ret = request_irq(pdriver_dev->irq_num[1], vivdw200_interrupt, + IRQF_SHARED|IRQF_TRIGGER_RISING, "SCALAR_IRQ", (char *)pdriver_dev); + if (ret) { + pr_err("%s[%d]:request irq error!\n", __func__, __LINE__); + return ret; + } + +#if 0 + ret = devm_request_irq(&pdev->dev, 16, (irq_handler_t)vivdw200_interrupt, IRQF_SHARED|IRQF_TRIGGER_RISING, VIVCAM_DWE_NAME, (void*)pdriver_dev);// pdriver_dev->irq_num + if (ret != 0) { + pr_err("%s:request irq error\n", __func__); + return ret; + } +#endif + init_waitqueue_head(&pdriver_dev->irq_wait); + + if (devise_register_index == 0) + { + if (vvcam_dwe_major == 0) + { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_DWE_MAXCNT, VIVCAM_DWE_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_dwe_major = MAJOR(pdriver_dev->devt); + vvcam_dwe_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_dwe_major, vvcam_dwe_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_DWE_MAXCNT, VIVCAM_DWE_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + vvcam_dwe_class = class_create(THIS_MODULE, VIVCAM_DWE_NAME); + if (IS_ERR(vvcam_dwe_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_dwe_major, vvcam_dwe_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_dwe_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_dwe_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s", VIVCAM_DWE_NAME); + + devise_register_index++; + pr_info("exit %s:[%d]\n", __func__, pdev->id); + return ret; +} + +static int vvcam_dwe_remove(struct platform_device *pdev) +{ + struct vvcam_dwe_driver_dev *pdriver_dev; + struct dw200_subdev * pdwe_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + free_irq(pdriver_dev->irq_num[0], pdriver_dev); + free_irq(pdriver_dev->irq_num[1], pdriver_dev); + + pdwe_dev = pdriver_dev->private; + iounmap(pdwe_dev->dwe_base); + iounmap(pdwe_dev->vse_base); + iounmap(pdwe_dev->dwe_reset); + iounmap(pdwe_dev->vse_reset); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_DWE_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + + return 0; +} + +static const struct of_device_id dewarp_of_match[] = { + { .compatible = "thead,light-dewarp", }, + { /* sentinel */ }, +}; + +static struct platform_driver vvcam_dwe_driver = { + .probe = vvcam_dwe_probe, + .remove = vvcam_dwe_remove, + .driver = { + .name = VIVCAM_DWE_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(dewarp_of_match), + } +}; + +static int __init vvcam_dwe_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&vvcam_dwe_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit vvcam_dwe_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_dwe_driver); +} + +module_init(vvcam_dwe_init_module); +module_exit(vvcam_dwe_exit_module); + +MODULE_DESCRIPTION("DWE"); +MODULE_LICENSE("GPL"); diff --git a/vvcam_ry/native/gpio_i2c/Makefile b/vvcam_ry/native/gpio_i2c/Makefile new file mode 100755 index 0000000..9d70353 --- /dev/null +++ b/vvcam_ry/native/gpio_i2c/Makefile @@ -0,0 +1,17 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_i2c + +obj-m +=$(TARGET).o +$(TARGET)-objs += soc_i2c_driver.o + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam_ry/native/gpio_i2c/soc_i2c_driver.c b/vvcam_ry/native/gpio_i2c/soc_i2c_driver.c new file mode 100755 index 0000000..e5c3e96 --- /dev/null +++ b/vvcam_ry/native/gpio_i2c/soc_i2c_driver.c @@ -0,0 +1,437 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct soc_gpio_i2c{ + struct i2c_adapter adap; + unsigned long phy_base_addr; + unsigned long size; + void __iomem * virt_base_addr; + spinlock_t lock; +}; + + +static void i2c_gpio_setsda_val(void *source, int state) +{ + struct soc_gpio_i2c *i2c = source; + int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~0x1)) | (0x10 | (state & 0x01)); + + writel(reg_data, i2c->virt_base_addr); + return ; +} + +static void i2c_gpio_setscl_val(void *source, int state) +{ + struct soc_gpio_i2c *i2c = source; + int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~(0x1 << 8))) | ((0x10 | (state & 0x01)) << 8); + + writel(reg_data, i2c->virt_base_addr); + return ; +} + +static int i2c_gpio_getsda(void *source) +{ + struct soc_gpio_i2c *i2c = source; + unsigned int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~0x10)); + writel(reg_data, i2c->virt_base_addr); + + return (readl(i2c->virt_base_addr) & 0x01); +} +// Start :When SCL is High ,SDA Change to low +static void i2c_gpio_start(void *source) +{ + i2c_gpio_setscl_val(source, 1); + i2c_gpio_setsda_val(source, 1); + udelay(5); + i2c_gpio_setsda_val(source, 0); + udelay(1); + return; +} +//Send Bit : When SCL is LOW, sda change;When SCL is HIgh,SDA hold; +static void i2c_gpio_send_byte(void *source, unsigned char val) +{ + int bit_idx; + for (bit_idx=7; bit_idx >= 0; bit_idx--) + { + i2c_gpio_setscl_val(source, 0); + i2c_gpio_setsda_val(source, (val >> bit_idx) & 0x01); + udelay(1); + i2c_gpio_setscl_val(source, 1); + udelay(1); + } + i2c_gpio_setscl_val(source, 0); + i2c_gpio_setsda_val(source, 1); + return; +} +//Read Bit: When SCL is High read data; +static unsigned char i2c_gpio_read_byte(void *source) +{ + int bit_idx; + unsigned char data = 0; + + i2c_gpio_getsda(source);//SDA change to read + + for(bit_idx=7; bit_idx>=0; bit_idx--) + { + + i2c_gpio_setscl_val(source, 1); + udelay(1); + data = (data << 1) | i2c_gpio_getsda(source); + i2c_gpio_setscl_val(source, 0); + udelay(1); + } + return data; +} + +static int i2c_gpio_wait_ack(void *source) +{ + unsigned int i2c_retry_ack_cnt = 0; + + i2c_gpio_getsda(source);//SDA change to read + udelay(1); + i2c_gpio_setscl_val(source, 1); + + while(i2c_gpio_getsda(source) == 1) + { + udelay(1); + if (i2c_retry_ack_cnt++ > 20) + { + return 0; + } + } + i2c_gpio_setscl_val(source, 0); + return 1; +} + +static void i2c_gpio_stop(void *source) +{ + i2c_gpio_setsda_val(source, 0); + udelay(1); + i2c_gpio_setscl_val(source, 1); + udelay(1); + i2c_gpio_setsda_val(source, 1); + return; +} + +static int i2c_gpio_write(void *source,struct i2c_msg *msg) +{ + + unsigned char slave_address; + unsigned char *buf; + int i; + slave_address = (msg->addr) << 1; + buf = msg->buf; + + i2c_gpio_start(source); + i2c_gpio_send_byte(source, slave_address); + if (i2c_gpio_wait_ack(source) == 0) return -1; + + for (i = 0; i < msg->len; i++) + { + i2c_gpio_send_byte(source, buf[i]); + i2c_gpio_wait_ack(source); + } + + i2c_gpio_stop(source); + return 0; +} + +static int i2c_gpio_read(void *source,struct i2c_msg *msg) +{ + unsigned char slave_address; + unsigned char *buf; + int i; + slave_address = ((msg->addr) << 1) | 0x01; + buf = msg->buf; + + i2c_gpio_start(source); + i2c_gpio_send_byte(source, slave_address); + if (i2c_gpio_wait_ack(source) == 0) return -1; + + for (i = 0; i < msg->len; i++) + { + buf[i] = i2c_gpio_read_byte(source); + i2c_gpio_wait_ack(source); + } + + return 0; +} + +static int i2c_gpio_xfer(struct i2c_adapter *adapter, + struct i2c_msg *msgs, int num) +{ + int result; + int i; + struct soc_gpio_i2c *i2c; + void *source; + + source = i2c_get_adapdata(adapter); + i2c = source; + + for (i=0; idev, sizeof(struct soc_gpio_i2c), GFP_KERNEL); + if (!i2c) + { + return -ENOMEM; + } + memset(i2c, 0, sizeof(struct soc_gpio_i2c)); + //mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + //i2c->virt_base_addr = devm_ioremap_resource(&pdev->dev, mem); + if (pdev->id == VVSENSOR_I2C_BUS0) + { + i2c->virt_base_addr = ioremap(VVCAM_I2C0_BASE, VVCAM_I2C_SIZE); + + }else + { + i2c->virt_base_addr = ioremap(VVCAM_I2C1_BASE, VVCAM_I2C_SIZE); + } + + if (i2c->virt_base_addr == NULL) + { + return -1; + } + + if (IS_ERR(i2c->virt_base_addr)) + return PTR_ERR(i2c->virt_base_addr); + + + spin_lock_init(&(i2c->lock)); + + adap = &i2c->adap; + platform_set_drvdata(pdev, i2c); + + i2c_set_adapdata(adap, i2c); + adap->owner = THIS_MODULE; + snprintf(adap->name, sizeof(adap->name), "soc_gpio_i2c"); + adap->timeout = 2 * HZ; + adap->retries = 0; + adap->algo = &gpio_i2c_algo; + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + adap->dev.parent = &pdev->dev; + adap->nr = pdev->id; + adap->dev.of_node = pdev->dev.of_node; + + ret = i2c_add_numbered_adapter(adap); + if (ret) + { + pr_info("%s:i2c_add_adapter failed 0x%x\n", __func__, ret); + kfree(i2c); + return ret; + } + + return 0; +} + +static int soc_gpio_i2c_remove(struct platform_device *pdev) +{ + struct soc_gpio_i2c *i2c; + + i2c = platform_get_drvdata(pdev); + i2c_del_adapter(&(i2c->adap)); + + iounmap(i2c->virt_base_addr); + + return 0; +} + +static struct platform_driver soc_gpio_i2c_driver = { + .probe = soc_gpio_i2c_probe, + .remove = soc_gpio_i2c_remove, + .driver = { + .name = "soc_gpio_i2c", + .owner = THIS_MODULE, + }, +}; + +static void soc_gpio_i2c_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); + return; +} + + +#ifdef WITH_VVCAM +static struct resource soc_gpio_i2c0_resource[] = { + [0] = { + .start = VVCAM_I2C0_BASE, + .end = VVCAM_I2C0_BASE + VVCAM_I2C_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + + +static struct platform_device soc_gpio_i2c0_pdev = { + .name = "soc_gpio_i2c", + .id = VVSENSOR_I2C_BUS0, + .resource = soc_gpio_i2c0_resource, + .num_resources = 0, + .dev.release = soc_gpio_i2c_release, +}; +#endif + +#ifdef WITH_VVCAM_DUAL +static struct resource soc_gpio_i2c1_resource[] = { + [0] = { + .start = VVCAM_I2C1_BASE, + .end = VVCAM_I2C1_BASE + VVCAM_I2C_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device soc_gpio_i2c1_pdev = { + .name = "soc_gpio_i2c", + .id = VVSENSOR_I2C_BUS1, + .resource = soc_gpio_i2c1_resource, + .num_resources = 0, + .dev.release = soc_gpio_i2c_release, +}; +#endif + +static int __init soc_gpio_i2c_driver_init_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_register(&soc_gpio_i2c_driver); +#ifdef WITH_VVCAM + platform_device_register(&soc_gpio_i2c0_pdev); +#endif +#ifdef WITH_VVCAM_DUAL + platform_device_register(&soc_gpio_i2c1_pdev); +#endif + return 0; +} +static void __exit soc_gpio_i2c_driver_exit_module(void) +{ +#ifdef WITH_VVCAM + platform_device_unregister(&soc_gpio_i2c0_pdev); +#endif +#ifdef WITH_VVCAM_DUAL + platform_device_unregister(&soc_gpio_i2c1_pdev); +#endif + platform_driver_unregister(&soc_gpio_i2c_driver); + + + return; +} + +module_init(soc_gpio_i2c_driver_init_module); +module_exit(soc_gpio_i2c_driver_exit_module); + +MODULE_DESCRIPTION("SENSOR"); +MODULE_LICENSE("GPL"); + + + + diff --git a/vvcam_ry/native/isp/Makefile b/vvcam_ry/native/isp/Makefile new file mode 100755 index 0000000..6c2bd27 --- /dev/null +++ b/vvcam_ry/native/isp/Makefile @@ -0,0 +1,41 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_isp_ry + +obj-m +=$(TARGET).o +$(TARGET)-objs += vvcam_isp_driver_of.o +$(TARGET)-objs += ../../isp/isp_miv1.o +$(TARGET)-objs += ../../isp/isp_miv2.o +$(TARGET)-objs += ../../isp/isp_wdr3.o +$(TARGET)-objs += ../../isp/isp_wdr4.o +$(TARGET)-objs += ../../isp/isp_wdr.o +$(TARGET)-objs += ../../isp/isp_3dnr.o +$(TARGET)-objs += ../../isp/isp_3dnr2.o +$(TARGET)-objs += ../../isp/isp_tdnr3.o +$(TARGET)-objs += ../../isp/isp_hdr.o +$(TARGET)-objs += ../../isp/isp_dpf.o +$(TARGET)-objs += ../../isp/isp_compand.o +$(TARGET)-objs += ../../isp/isp_gcmono.o +$(TARGET)-objs += ../../isp/isp_rgbgamma.o +$(TARGET)-objs += ../../isp/isp_ioctl.o +$(TARGET)-objs += ../../isp/isp_dmsc2.o +$(TARGET)-objs += ../../isp/isp_rgbir.o +$(TARGET)-objs += ../../isp/isp_irq_queue.o + + + +EXTRA_CFLAGS += -I$(PWD)/../../isp +EXTRA_CFLAGS += -I$(PWD)/../../driver +EXTRA_CFLAGS += -I$(PWD)/../../common + + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam_ry/native/isp/vvcam_isp_driver.c b/vvcam_ry/native/isp/vvcam_isp_driver.c new file mode 100755 index 0000000..0e1d830 --- /dev/null +++ b/vvcam_ry/native/isp/vvcam_isp_driver.c @@ -0,0 +1,573 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "isp_ioctl.h" +#include "mrv_all_regs.h" +#include "isp_wdr.h" + +extern MrvAllRegister_t *all_regs; + +static ulong vvImgBufBase = 0x10000000; +module_param(vvImgBufBase, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvImgBufBase, "Base addrss of memory reserved for ISP"); + +static ulong vvImgBufSize = 0x10000000; +module_param(vvImgBufSize, ulong, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); +MODULE_PARM_DESC(vvImgBufSize, "Size of memory reserved for ISP"); + +#define VIVCAM_ISP_NAME "vivisp" +#define VIVCAM_ISP_MAXCNT 2 +#define VIVCAM_ISP_IRQ_NUMBER 16 + +struct vvcam_isp_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + unsigned int device_idx; + struct timer_list isp_timer; + struct work_struct vvnative_wq; + wait_queue_head_t irq_wait; + int irq_num; + void *private; +}; + +static unsigned int vvcam_isp_major = 0; +static unsigned int vvcam_isp_minor = 0; +static struct class *vvcam_isp_class; +static unsigned int devise_register_index = 0; +static bool isp_irq = false; +static unsigned int vvnative_isp_poll(struct file * filp, poll_table *wait) +{ + unsigned int mask = 0; + struct vvcam_isp_driver_dev *pdriver_dev = filp->private_data; + poll_wait(filp, &pdriver_dev->irq_wait, wait); + + //pr_info("poll isp_irq %d\n", isp_irq); + + if (isp_irq) { + mask |= POLLIN |POLLRDNORM; + isp_irq = false; + } + return mask; +} + +static void vvnative_isp_work(struct work_struct *work) +{ + /*Todo update those module that does not have shandow register*/ + struct vvcam_isp_driver_dev *pdriver_dev = container_of(work, struct vvcam_isp_driver_dev, vvnative_wq); + + struct isp_ic_dev * pisp_dev = pdriver_dev->private; + pr_info("%s enter \n", __func__); + + isp_irq = true; + wake_up_interruptible(&pdriver_dev->irq_wait); + if (pisp_dev->isp_mis & MRV_ISP_MIS_FRAME_MASK) { + if (pisp_dev->wdr.changed) { + pr_info("%s pisp_dev->wdr.changed %d\n", __func__, + pisp_dev->wdr.changed); + isp_s_wdr(pisp_dev); + } + if (pisp_dev->flt.changed) { + pr_info("%s pisp_dev->flt.changed %d\n", __func__, + pisp_dev->flt.changed); + isp_s_flt(pisp_dev); + } +#ifndef ISP_CPROC_SHD_RY + if (pisp_dev->cproc.changed) { + pr_info("%s pisp_dev->cproc.changed %d\n", __func__, + pisp_dev->cproc.changed); + isp_s_cproc(pisp_dev); + } +#endif + if (pisp_dev->gamma_out.changed) { + pr_info("%s pisp_dev->gamma_out.changed %d\n", __func__, + pisp_dev->gamma_out.changed); + isp_s_gamma_out(pisp_dev); + } + + } + +} + +static irqreturn_t vvcam_isp_irq(int irq, void *dev_id) +{ + struct vvcam_isp_driver_dev *pdriver_dev ; + struct isp_ic_dev * pisp_dev; + u32 isp_mis, mi_mis, mi_mis_addr, mi_icr_addr; +#ifdef ISP_MIV2_RY + u32 miv2_mis1, miv2_mis3; +#endif + #if defined(ISP_MI_PP_READ_RY) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE_RY) || defined (ISP_MI_HDR_RY) + u32 miv2_mis2; +#endif + pdriver_dev = (struct vvcam_isp_driver_dev *)dev_id; + pisp_dev = pdriver_dev->private; + isp_mis = isp_read_reg(pisp_dev, REG_ADDR(isp_mis)); +#ifdef ISP_MIV2_RY + mi_icr_addr = REG_ADDR(miv2_icr); + mi_mis_addr = REG_ADDR(miv2_mis); + miv2_mis1 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis1)); + if (miv2_mis1) { + pr_info("%s mi mis1 0x%08x\n", __func__, miv2_mis1); + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr1), miv2_mis1); + } + + miv2_mis3 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis3)); + if (miv2_mis3) { + pr_info("%s mi mis3 0x%08x\n", __func__, miv2_mis3); + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr3), miv2_mis3); + } +#elif defined(ISP_MIV1) + mi_icr_addr = REG_ADDR(mi_icr); + mi_mis_addr = REG_ADDR(mi_mis); +#endif + + mi_mis = isp_read_reg(pisp_dev, mi_mis_addr); + #if defined(ISP_MI_PP_READ_RY) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE_RY) || defined (ISP_MI_HDR_RY) + miv2_mis2 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis2)); + pr_info("%s isp mis 0x%08x, mi mis 0x%08x post mis 0x%08x\n", __func__, \ + isp_mis, mi_mis, miv2_mis2); +#else + pr_info("%s isp mis 0x%08x, mi mis 0x%08x\n", __func__, \ + isp_mis, mi_mis); +#endif + + if (isp_mis) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_ISP_IRQ; + mis_data.val = isp_mis; + pisp_dev->isp_mis = isp_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + isp_write_reg(pisp_dev, REG_ADDR(isp_icr), isp_mis); + if(isp_mis & MRV_ISP_ISR_ISP_OFF_MASK) + isp_write_reg(pisp_dev, REG_ADDR(isp_imsc), isp_mis& (~MRV_ISP_ISR_ISP_OFF_MASK)); + } + + if (mi_mis) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI_IRQ; + mis_data.val = mi_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + + isp_write_reg(pisp_dev, mi_icr_addr, mi_mis); + } +#ifdef ISP_MIV2_RY + if (miv2_mis1) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI1_IRQ; + mis_data.val = mi_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + + isp_write_reg(pisp_dev, mi_icr_addr, mi_mis); + } +#endif + + #if defined(ISP_MI_PP_READ_RY) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE_RY) || defined (ISP_MI_HDR_RY) + if (miv2_mis2) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI2_IRQ; + mis_data.val = miv2_mis2; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr2), miv2_mis2); + } +#endif + + #if defined(ISP_MI_PP_READ_RY) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE_RY) || defined (ISP_MI_HDR_RY) + if (isp_mis != 0 ||mi_mis != 0 || miv2_mis2 != 0) { + #else + if (isp_mis != 0 ||mi_mis != 0 ) { +#endif + schedule_work(&pdriver_dev->vvnative_wq); + } else { + return IRQ_NONE; + } + return IRQ_HANDLED; +} + +static int vvcam_isp_open(struct inode * inode, struct file * file) +{ + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + pdriver_dev = container_of(inode->i_cdev, struct vvcam_isp_driver_dev, cdev); + file->private_data = pdriver_dev; + pisp_dev = pdriver_dev->private; + /*create circle queue*/ + isp_irq_create_circle_queue(&(pisp_dev->circle_list), QUEUE_NODE_COUNT); + return 0; +}; + +static long vvcam_isp_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + pr_err("%s:cmd = %d\n", __func__, cmd); + + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + pisp_dev = pdriver_dev->private; + //pr_info("%s:isp[%d] pdriver_dev =0x%px\n", __func__,pdriver_dev->device_idx,pdriver_dev); + //pr_info("%s:pisp_dev =0x%px\n", __func__,pisp_dev); + + mutex_lock(&pdriver_dev->vvmutex); + ret = isp_priv_ioctl(pisp_dev, cmd ,(void __user *)arg); + mutex_unlock(&pdriver_dev->vvmutex); + + return ret; +}; + +static int vvcam_isp_release(struct inode * inode, struct file * file) +{ + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev *pisp_dev; + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_isp_driver_dev, cdev); + file->private_data = pdriver_dev; + pisp_dev = pdriver_dev->private; + pr_info("enter %s\n", __func__); + isp_irq_destroy_circle_queue(&(pisp_dev->circle_list)); + + return 0; +}; + +static int vvcam_isp_mmap(struct file *pFile, struct vm_area_struct *vma) +{ + int ret = 0; + + ulong phy_base_addr = 0; + + unsigned long pfn_start = (phy_base_addr >> PAGE_SHIFT) + vma->vm_pgoff; + unsigned long size = vma->vm_end - vma->vm_start; + pr_info("phy: 0x%lx, size: 0x%lx\n", pfn_start << PAGE_SHIFT, size); + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + if (remap_pfn_range(vma, vma->vm_start,pfn_start,size, vma->vm_page_prot)) + { + pr_err("-->%s: remap_pfn_range error!\n", __func__); + return -EIO; + } + + return ret; +}; + +static struct file_operations vvcam_isp_fops = { + .owner = THIS_MODULE, + .open = vvcam_isp_open, + .release = vvcam_isp_release, + .unlocked_ioctl = vvcam_isp_ioctl, + .mmap = vvcam_isp_mmap, + .poll = vvnative_isp_poll, +}; + +static int vvcam_isp_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + struct resource *mem; + + pr_info("enter %s\n", __func__); + + if (pdev->id >= VIVCAM_ISP_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_isp_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_isp_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_isp_driver_dev )); + pr_info("%s:isp[%d]: pdriver_dev =0x%px\n", __func__,pdev->id,pdriver_dev); + + pisp_dev = devm_kzalloc(&pdev->dev,sizeof(struct isp_ic_dev), GFP_KERNEL); + if (pisp_dev == NULL) + { + pr_err("%s:alloc struct isp_ic_dev error\n", __func__); + return -ENOMEM; + } + memset(pisp_dev,0,sizeof(struct isp_ic_dev )); + pr_info("%s:isp[%d]: psensor_dev =0x%px\n", __func__,pdev->id,pisp_dev); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pisp_dev->base = devm_ioremap_resource(&pdev->dev, mem); + pisp_dev->reset = NULL; + + pdriver_dev->private = pisp_dev; + pdriver_dev->device_idx = pdev->id; + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + + pdriver_dev->irq_num = platform_get_irq(pdev, 0); + + if (devise_register_index == 0) + { + /*init work queue*/ + INIT_WORK(&pdriver_dev->vvnative_wq, vvnative_isp_work); + + ret = devm_request_irq(&pdev->dev, pdriver_dev->irq_num, vvcam_isp_irq, + IRQF_TRIGGER_RISING|IRQF_SHARED, "ISP_IRQ", (char *)pdriver_dev); + if (ret) { + pr_err("%s[%d]:request irq error!\n", __func__, __LINE__); + return ret; + } + init_waitqueue_head(&pdriver_dev->irq_wait); + if (vvcam_isp_major == 0) + { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_ISP_MAXCNT, VIVCAM_ISP_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_isp_major = MAJOR(pdriver_dev->devt); + vvcam_isp_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_isp_major, vvcam_isp_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_ISP_MAXCNT, VIVCAM_ISP_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + vvcam_isp_class = class_create(THIS_MODULE, VIVCAM_ISP_NAME); + if (IS_ERR(vvcam_isp_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_isp_major, vvcam_isp_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_isp_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_isp_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VIVCAM_ISP_NAME, pdev->id); + + + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int vvcam_isp_remove(struct platform_device *pdev) +{ + struct vvcam_isp_driver_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + // free_irq(pdriver_dev->irq_num, pdriver_dev); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_ISP_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + return 0; +} + +static struct platform_driver vvcam_isp_driver = { + .probe = vvcam_isp_probe, + .remove = vvcam_isp_remove, + .driver = { + .name = VIVCAM_ISP_NAME, + .owner = THIS_MODULE, + } +}; + +static void vvcam_isp_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +#ifdef WITH_VVCAM +static struct resource vvcam_isp0_resource[] = { + [0] = { + .start = VVISP0_BASE, + .end = VVISP0_BASE + ISP_REG_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = VIVCAM_ISP_IRQ_NUMBER, + .end = VIVCAM_ISP_IRQ_NUMBER, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device vvcam_isp_pdev = { + .name = VIVCAM_ISP_NAME, + .id = 0, + .resource = vvcam_isp0_resource, + .num_resources = ARRAY_SIZE(vvcam_isp0_resource), + .dev.release = vvcam_isp_pdev_release, +}; +#endif + +#ifdef WITH_VVCAM_DUAL +static struct resource vvcam_isp1_resource[] = { + [0] = { + .start = VVISP1_BASE, + .end = VVISP1_BASE + ISP_REG_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = VIVCAM_ISP_IRQ_NUMBER, + .end = VIVCAM_ISP_IRQ_NUMBER, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device vvcam_isp_dual_pdev = { + .name = VIVCAM_ISP_NAME, + .id = 1, + .resource = vvcam_isp1_resource, + .num_resources = ARRAY_SIZE(vvcam_isp1_resource), + .dev.release = vvcam_isp_pdev_release, +}; +#endif + +static int __init vvcam_isp_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); +#ifdef WITH_VVCAM + ret = platform_device_register(&vvcam_isp_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } +#endif + +#ifdef WITH_VVCAM_DUAL + ret = platform_device_register(&vvcam_isp_dual_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } +#endif + + ret = platform_driver_register(&vvcam_isp_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit vvcam_isp_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_isp_driver); +#ifdef WITH_VVCAM + platform_device_unregister(&vvcam_isp_pdev); +#endif + +#ifdef WITH_VVCAM_DUAL + platform_device_unregister(&vvcam_isp_dual_pdev); +#endif +} + +module_init(vvcam_isp_init_module); +module_exit(vvcam_isp_exit_module); + +MODULE_DESCRIPTION("ISP"); +MODULE_LICENSE("GPL"); diff --git a/vvcam_ry/native/isp/vvcam_isp_driver_of.c b/vvcam_ry/native/isp/vvcam_isp_driver_of.c new file mode 100755 index 0000000..3d9c815 --- /dev/null +++ b/vvcam_ry/native/isp/vvcam_isp_driver_of.c @@ -0,0 +1,641 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "isp_ioctl.h" +#include "mrv_all_regs.h" +#include "isp_wdr.h" + +extern MrvAllRegister_t *all_regs; + +#define VIVCAM_ISP_NAME "vivisp_ry" +#define VIVCAM_ISP_MAXCNT 1 +#define VIVCAM_ISP_IRQ_NUMBER 16 + +struct vvcam_isp_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + unsigned int device_idx; + struct timer_list isp_timer; + struct work_struct vvnative_wq; + wait_queue_head_t irq_wait; + int irq_num[2]; + void *private; + struct clk *aclk; + struct clk *hclk; + struct clk *cclk; + struct platform_device *pdev; +}; + +static unsigned int vvcam_isp_major = 0; +static unsigned int vvcam_isp_minor = 0; +static struct class *vvcam_isp_class; +static unsigned int devise_register_index = 0; +static bool isp_irq = false; +static unsigned int vvnative_isp_poll(struct file * filp, poll_table *wait) +{ + unsigned int mask = 0; + struct vvcam_isp_driver_dev *pdriver_dev = filp->private_data; + poll_wait(filp, &pdriver_dev->irq_wait, wait); + + //pr_info("poll isp_irq %d\n", isp_irq); + + if (isp_irq) { + mask |= POLLIN |POLLRDNORM; + isp_irq = false; + } + return mask; +} + +static void vvnative_isp_work(struct work_struct *work) +{ + /*Todo update those module that does not have shandow register*/ + struct vvcam_isp_driver_dev *pdriver_dev = container_of(work, struct vvcam_isp_driver_dev, vvnative_wq); + + struct isp_ic_dev * pisp_dev = pdriver_dev->private; + //pr_info("%s enter \n", __func__); + + isp_irq = true; + wake_up_interruptible(&pdriver_dev->irq_wait); + if (pisp_dev->isp_mis & MRV_ISP_MIS_FRAME_MASK) { + if (pisp_dev->wdr.changed) { + pr_info("%s pisp_dev->wdr.changed %d\n", __func__, + pisp_dev->wdr.changed); + isp_s_wdr(pisp_dev); + } + if (pisp_dev->flt.changed) { + pr_info("%s pisp_dev->flt.changed %d\n", __func__, + pisp_dev->flt.changed); + isp_s_flt(pisp_dev); + } +#ifndef ISP_CPROC_SHD_RY + if (pisp_dev->cproc.changed) { + pr_info("%s pisp_dev->cproc.changed %d\n", __func__, + pisp_dev->cproc.changed); + isp_s_cproc(pisp_dev); + } +#endif + if (pisp_dev->gamma_out.changed) { + pr_info("%s pisp_dev->gamma_out.changed %d\n", __func__, + pisp_dev->gamma_out.changed); + isp_s_gamma_out(pisp_dev); + } + + } + +} + +static irqreturn_t vvcam_isp_irq(int irq, void *dev_id) +{ + struct vvcam_isp_driver_dev *pdriver_dev ; + struct isp_ic_dev * pisp_dev; + u32 isp_mis, mi_mis, mi_mis_addr, mi_icr_addr; +#ifdef ISP_MIV2_RY + u32 miv2_mis1, miv2_mis3; +#endif + #if defined(ISP_MI_PP_READ_RY) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE_RY) || defined (ISP_MI_HDR_RY) + u32 miv2_mis2; +#endif + pdriver_dev = (struct vvcam_isp_driver_dev *)dev_id; + pisp_dev = pdriver_dev->private; + isp_mis = isp_read_reg(pisp_dev, REG_ADDR(isp_mis)); +#ifdef ISP_MIV2_RY + mi_icr_addr = REG_ADDR(miv2_icr); + mi_mis_addr = REG_ADDR(miv2_mis); + miv2_mis1 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis1)); + if (miv2_mis1) { + /*pr_info("%s mi mis1 0x%08x\n", __func__, miv2_mis1);*/ + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr1), miv2_mis1); + } +#ifdef POST_ISP_SDK_TEST + miv2_mis3 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis3)); + if (miv2_mis3) { + pr_info("%s mi mis3 0x%08x\n", __func__, miv2_mis3); + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr3), miv2_mis3); + } +#endif +#elif defined(ISP_MIV1_RY) + mi_icr_addr = REG_ADDR(mi_icr); + mi_mis_addr = REG_ADDR(mi_mis); +#endif + + /*mi_mis = isp_read_reg(pisp_dev, mi_mis_addr);*/ + #if defined(ISP_MI_PP_READ_RY) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE_RY) || defined (ISP_MI_HDR_RY) + miv2_mis2 = isp_read_reg(pisp_dev, REG_ADDR(miv2_mis2)); + /*pr_info("%s isp mis 0x%08x, mi mis 0x%08x post mis 0x%08x\n", __func__, \ + isp_mis, mi_mis, miv2_mis2);*/ +#else + /*pr_info("%s isp mis 0x%08x, mi mis 0x%08x\n", __func__, \ + isp_mis, mi_mis);*/ +#endif + if (isp_mis) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_ISP_IRQ; + mis_data.val = isp_mis; + pisp_dev->isp_mis = isp_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + isp_write_reg(pisp_dev, REG_ADDR(isp_icr), isp_mis); + if(isp_mis & MRV_ISP_MIS_ISP_OFF_MASK) { + isp_write_reg(pisp_dev, REG_ADDR(isp_imsc), isp_read_reg(pisp_dev, REG_ADDR(isp_imsc))&(~MRV_ISP_MIS_ISP_OFF_MASK)); + } + if (isp_mis & MRV_ISP_MIS_FLASH_ON_MASK) + mi_mis |= 0x1; + } + + if (mi_mis) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI_IRQ; + mis_data.val = mi_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + + isp_write_reg(pisp_dev, mi_icr_addr, mi_mis); + } +#ifdef ISP_MIV2_RY + if (miv2_mis1) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI1_IRQ; + mis_data.val = mi_mis; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + + isp_write_reg(pisp_dev, mi_icr_addr, mi_mis); + } +#endif + + #if defined(ISP_MI_PP_READ_RY) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE_RY) || defined (ISP_MI_HDR_RY) + if (miv2_mis2) { + isp_mis_t mis_data; + mis_data.irq_src = SRC_MI2_IRQ; + mis_data.val = miv2_mis2; + isp_irq_write_circle_queue(&mis_data, &pisp_dev->circle_list); + isp_write_reg(pisp_dev, REG_ADDR(miv2_icr2), miv2_mis2); + } +#endif + #if defined(ISP_MI_PP_READ_RY) || defined (ISP_3DNR_V3) || defined (ISP_MI_PP_WRITE_RY) || defined (ISP_MI_HDR_RY) + if (isp_mis != 0 ||mi_mis != 0 || miv2_mis2 != 0) { + #else + if (isp_mis != 0 ||mi_mis != 0 ) { +#endif + schedule_work(&pdriver_dev->vvnative_wq); + } else { + return IRQ_HANDLED; // return IRQ_NONE; + } + return IRQ_HANDLED; +} + +static int vvcam_isp_runtime_suspend(struct device *dev) +{ + struct vvcam_isp_driver_dev *pdriver_dev = dev_get_drvdata(dev); + clk_disable_unprepare(pdriver_dev->aclk); + clk_disable_unprepare(pdriver_dev->hclk); + clk_disable_unprepare(pdriver_dev->cclk); + pr_info("ry %s\n", __func__); + return 0; +} +static int vvcam_isp_runtime_resume(struct device *dev) +{ + struct vvcam_isp_driver_dev *pdriver_dev = dev_get_drvdata(dev); + int ret = 0; + ret = clk_prepare_enable(pdriver_dev->cclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable core clock\n"); + //return ret; + } + ret = clk_prepare_enable(pdriver_dev->hclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable ahb clock\n"); + clk_disable_unprepare(pdriver_dev->cclk); + //return ret; + } + ret = clk_prepare_enable(pdriver_dev->aclk); + if (ret < 0) { + dev_err(dev, "could not prepare or enable axi clock\n"); + clk_disable_unprepare(pdriver_dev->cclk); + clk_disable_unprepare(pdriver_dev->hclk); + //return ret; + } + pr_info("%s ry Enabled clock\n", __func__); + return ret; +} +static const struct dev_pm_ops vvcam_isp_runtime_pm_ops = { + SET_RUNTIME_PM_OPS(vvcam_isp_runtime_suspend, vvcam_isp_runtime_resume, NULL) +}; + + +static int vvcam_isp_open(struct inode * inode, struct file * file) +{ + int ret = 0; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_isp_driver_dev, cdev); + file->private_data = pdriver_dev; + pisp_dev = pdriver_dev->private; + /*create circle queue*/ + isp_irq_create_circle_queue(&(pisp_dev->circle_list), QUEUE_NODE_COUNT); + struct device *dev = &pdriver_dev->pdev->dev; + + if (pm_runtime_get_sync(dev)) { + ret = vvcam_isp_runtime_resume(dev); + if (ret) + pr_err("fail to resume isp %s %d\n", __func__, __LINE__); + } + + return 0; +}; + +static long vvcam_isp_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + pisp_dev = pdriver_dev->private; + //pr_info("%s:isp[%d] pdriver_dev =0x%px\n", __func__,pdriver_dev->device_idx,pdriver_dev); + //pr_info("%s:pisp_dev =0x%px\n", __func__,pisp_dev); + + mutex_lock(&pdriver_dev->vvmutex); + ret = isp_priv_ioctl(pisp_dev, cmd ,(void __user *)arg); + mutex_unlock(&pdriver_dev->vvmutex); + + return ret; +}; + +static int vvcam_isp_release(struct inode * inode, struct file * file) +{ + int ret = 0; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev *pisp_dev; + if ((inode == NULL) || (file == NULL) ) { + printk("%s: %dx\n", __func__, __LINE__); + return 0; + } + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_isp_driver_dev, cdev); + file->private_data = pdriver_dev; + pisp_dev = pdriver_dev->private; + pr_info("enter %s\n", __func__); + isp_irq_destroy_circle_queue(&(pisp_dev->circle_list)); + + struct device *dev = &pdriver_dev->pdev->dev; + + if (pm_runtime_put_sync(dev)) { + pr_info("fail to resume isp %s %d\n", __func__, __LINE__); + } + + return 0; +}; + +static int vvcam_isp_mmap(struct file *pFile, struct vm_area_struct *vma) +{ + int ret = 0; + + ulong phy_base_addr = 0; + + unsigned long pfn_start = (phy_base_addr >> PAGE_SHIFT) + vma->vm_pgoff; + unsigned long size = vma->vm_end - vma->vm_start; + pr_info("phy: 0x%lx, size: 0x%lx\n", pfn_start << PAGE_SHIFT, size); + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + if (remap_pfn_range(vma, vma->vm_start,pfn_start,size, vma->vm_page_prot)) + { + pr_err("-->%s: remap_pfn_range error!\n", __func__); + return -EIO; + } + + return ret; +}; + +static struct file_operations vvcam_isp_fops = { + .owner = THIS_MODULE, + .open = vvcam_isp_open, + .release = vvcam_isp_release, + .unlocked_ioctl = vvcam_isp_ioctl, + .mmap = vvcam_isp_mmap, + .poll = vvnative_isp_poll, +}; + +static int vvcam_isp_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device_node *np; + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + struct resource *mem; + + pr_info("enter %s\n", __func__); + + pdev->id = devise_register_index; + if (pdev->id >= VIVCAM_ISP_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_isp_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_isp_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_isp_driver_dev )); + pr_info("%s:isp[%d]: pdriver_dev =0x%px\n", __func__,pdev->id,pdriver_dev); + + pisp_dev = devm_kzalloc(&pdev->dev,sizeof(struct isp_ic_dev), GFP_KERNEL); + if (pisp_dev == NULL) + { + pr_err("%s:alloc struct isp_ic_dev error\n", __func__); + return -ENOMEM; + } + memset(pisp_dev,0,sizeof(struct isp_ic_dev )); + pr_info("%s:isp[%d]: psensor_dev =0x%px\n", __func__,pdev->id,pisp_dev); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pisp_dev->base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(pisp_dev->base)) + return PTR_ERR(pisp_dev->base); + pr_info("%s:isp[%d]: pisp_dev->base=0x%px, phy_addr base=0x%llx\n", __func__, + pdev->id, pisp_dev->base, mem->start); + + pisp_dev->reset = NULL; + pisp_dev->device = &pdev->dev; + pdriver_dev->private = pisp_dev; + pdriver_dev->device_idx = pdev->id; + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + pdriver_dev->pdev = pdev; + + pdriver_dev->irq_num[0] = platform_get_irq(pdev, 0); + if (pdriver_dev->irq_num[0] == 0) { + pr_err("%s:isp[%d]: could not map IRQ\n", __func__, pdev->id); + dev_err(&pdev->dev, "could not map IRQ.\n"); + return -ENXIO; + } + pr_info("%s:isp[%d]: pdriver_dev->irq_num[0]=%d\n", __func__, pdev->id, pdriver_dev->irq_num[0]); + + pdriver_dev->irq_num[1] = platform_get_irq(pdev, 1); + if (pdriver_dev->irq_num[1] == 0) { + pr_err("%s:isp[%d]: could not map IRQ\n", __func__, pdev->id); + dev_err(&pdev->dev, "could not map IRQ.\n"); + return -ENXIO; + } + pr_info("%s:isp[%d]: pdriver_dev->irq_num[1]=%d\n", __func__, pdev->id, pdriver_dev->irq_num[1]); + + /*init work queue*/ + INIT_WORK(&pdriver_dev->vvnative_wq, vvnative_isp_work); + + ret = devm_request_irq(&pdev->dev, pdriver_dev->irq_num[0], vvcam_isp_irq, + IRQF_TRIGGER_RISING | IRQF_SHARED, "ISP_IRQ", (char *)pdriver_dev); + if (ret) { + pr_err("%s[%d]:request irq error!\n", __func__, __LINE__); + return ret; + } + + ret = devm_request_irq(&pdev->dev, pdriver_dev->irq_num[1], vvcam_isp_irq, + IRQF_TRIGGER_RISING, "MI_IRQ", (char *)pdriver_dev); + if (ret) { + pr_err("%s[%d]:request irq error!\n", __func__, __LINE__); + return ret; + } + + init_waitqueue_head(&pdriver_dev->irq_wait); + + +/*parse clk info from dts*/ + pdriver_dev->aclk = devm_clk_get(&pdev->dev, "aclk"); + if (IS_ERR(pdriver_dev->aclk)) { + dev_err(&pdev->dev, "failed to get aclk"); + //return -1; + } + pdriver_dev->hclk = devm_clk_get(&pdev->dev, "hclk"); + if (IS_ERR(pdriver_dev->hclk)) { + dev_err(&pdev->dev, "failed to get hclk"); + //return -1; + } + + pdriver_dev->cclk = devm_clk_get(&pdev->dev, "cclk"); + if (IS_ERR(pdriver_dev->aclk)) { + dev_err(&pdev->dev, "failed to get core_clk"); + //return -1; + } + dev_err(&pdev->dev, "parse clk success"); + if ((devise_register_index == 0)) { + int ret; + if (vvcam_isp_major == 0) { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_ISP_MAXCNT, VIVCAM_ISP_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_isp_major = MAJOR(pdriver_dev->devt); + vvcam_isp_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_isp_major, vvcam_isp_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_ISP_MAXCNT, VIVCAM_ISP_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + vvcam_isp_class = class_create(THIS_MODULE, VIVCAM_ISP_NAME); + if (IS_ERR(vvcam_isp_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_isp_major, vvcam_isp_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_isp_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_isp_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VIVCAM_ISP_NAME, pdev->id); + + struct device *dev = &pdriver_dev->pdev->dev; + pm_runtime_enable(dev); + + ret = vvcam_isp_runtime_resume(dev); + if (ret < 0) { + dev_err(dev, "fail to resume isp ry\n"); + } + vvcam_isp_runtime_suspend(dev); + if (ret < 0) { + dev_err(dev, "fail to suspend isp ry\n"); + } + + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int vvcam_isp_remove(struct platform_device *pdev) +{ + struct vvcam_isp_driver_dev *pdriver_dev; + struct isp_ic_dev * pisp_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + pisp_dev = pdriver_dev->private; + + if (pisp_dev->ut_addr != NULL) { + #define UT_USED_SIZE 0x01000000 + dma_free_coherent(&pdev->dev, UT_USED_SIZE, + pisp_dev->ut_addr, pisp_dev->ut_phy_addr); + } + + free_irq(pdriver_dev->irq_num[0], pdriver_dev); + free_irq(pdriver_dev->irq_num[1], pdriver_dev); + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + + + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_ISP_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + return 0; +} + +static const struct of_device_id isp_of_match[] = { + { .compatible = "thead,light-isp_ry", }, + { /* sentinel */ }, +}; + +static struct platform_driver vvcam_isp_driver = { + .probe = vvcam_isp_probe, + .remove = vvcam_isp_remove, + .driver = { + .name = VIVCAM_ISP_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(isp_of_match), + .pm = &vvcam_isp_runtime_pm_ops, + } +}; + + + +static int __init vvcam_isp_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&vvcam_isp_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit vvcam_isp_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_isp_driver); +} + +module_init(vvcam_isp_init_module); +module_exit(vvcam_isp_exit_module); + +MODULE_DESCRIPTION("ISP"); +MODULE_LICENSE("GPL"); diff --git a/vvcam_ry/native/sensor/Makefile b/vvcam_ry/native/sensor/Makefile new file mode 100755 index 0000000..0ff19e0 --- /dev/null +++ b/vvcam_ry/native/sensor/Makefile @@ -0,0 +1,76 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_sensor + +obj-m +=$(TARGET).o +$(TARGET)-objs += vvcam_sensor_driver.o +$(TARGET)-objs += sensor_ioctl.o + +EXTRA_CFLAGS += -I$(PWD)/../../common + +ifeq ($(SENSR0_TYPE), ov2775) +$(TARGET)-objs += ./omnivision_ov2775/ov2775_driver.o +$(TARGET)-objs += ./omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.o +EXTRA_CFLAGS += -I$(PWD)/omnivision_ov2775 +EXTRA_CFLAGS += -DSENSR0_FUNCTION=ov2775_function +endif + +ifeq ($(SENSR1_TYPE), ov2775) +#$(TARGET)-objs += ./omnivision_ov2775/ov2775_driver.o +#$(TARGET)-objs += ./omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.o +#EXTRA_CFLAGS += -I$(PWD)/omnivision_ov2775 +EXTRA_CFLAGS += -DSENSR1_FUNCTION=ov2775_function +endif + +ifeq ($(SENSR0_TYPE), imx334) +$(TARGET)-objs += ./sony_imx334/imx334_driver.o +$(TARGET)-objs += ./sony_imx334/imx334_mipi4lane_1080p_30fps_linear.o +EXTRA_CFLAGS += -I$(PWD)/sony_imx334 +EXTRA_CFLAGS += -DSENSR0_FUNCTION=imx334_function +endif + +ifeq ($(SENSR1_TYPE), imx334) +#$(TARGET)-objs += ./omnivision_ov5693/ov2775_driver.o +#$(TARGET)-objs += ./omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.o +#EXTRA_CFLAGS += -I$(PWD)/omnivision_ov2775 +EXTRA_CFLAGS += -DSENSR1_FUNCTION=imx334_function +endif + +ifeq ($(SENSR0_TYPE), ov5693) +$(TARGET)-objs += ./omnivision_ov5693/ov5693_driver.o +$(TARGET)-objs += ./omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.o +EXTRA_CFLAGS += -I$(PWD)/omnivision_ov5693 +EXTRA_CFLAGS += -DSENSR0_FUNCTION=ov5693_function +endif + +ifeq ($(SENSR1_TYPE), ov5693) +#$(TARGET)-objs += ./omnivision_ov5693/ov5693_driver.o +#$(TARGET)-objs += ./omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.o +#EXTRA_CFLAGS += -I$(PWD)/omnivision_ov5693 +EXTRA_CFLAGS += -DSENSR1_FUNCTION=ov5693_function +endif + + + + + +ifeq ($(PLATFORM), gen6) +$(TARGET)-objs += ./platform/platform_gen6_driver.o +EXTRA_CFLAGS += -I$(PWD)/platform +endif + +EXTRA_CFLAGS += -DSENSR0_TYPE +EXTRA_CFLAGS += -DSENSR1_TYPE + +EXTRA_CFLAGS += -I$(PWD)/ + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_driver.c b/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_driver.c new file mode 100755 index 0000000..e3faa35 --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_driver.c @@ -0,0 +1,493 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "os02k10_reg_cfg.h" + +#define SENSOR_CLK 51000000 + +static struct vvcam_mode_info pos02k10_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_arry *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pos02k10_mode_info); + + memcpy(pmode_info_arry->modes,pos02k10_mode_info,sizeof(pos02k10_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pos02k10_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pos02k10_mode_info[i].index == pmode->index) + { + psensor_mode = &(pos02k10_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&os02k10_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.MaxFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.MaxFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.interrgation_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&os02k10_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.MaxFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.MaxFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.interrgation_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3012, 0x01); + }else + { + ret = sensor_write_reg(ctx, 0x3012, 0x00); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.MaxFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s os02k10_function = +{ + .sensor_name = "os02k10", + .reserve_id = 0x2770, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_driver.h b/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_driver.h new file mode 100755 index 0000000..56cdd59 --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OMNIVISION_OS02k10_H_ +#define _OMNIVISION_OS02k10_H_ + +extern struct vvcam_sensor_function_s os02k10_function; + + +#endif diff --git a/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_mipi4lane_1080p_30fps_linear.c b/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..b75ff99 --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,310 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data os02k10_mipi4lane_1080p_30fps_linear_reg[] = { +{0x0100,0x00}, +{0x302a,0x00}, +{0x0103,0x01}, +{0x0109,0x01}, +{0x0104,0x02}, +{0x0102,0x00}, +{0x0303,0x04}, +{0x0305,0x4c}, +{0x0306,0x00}, +{0x0317,0x0a}, +{0x0323,0x07}, +{0x0324,0x01}, +{0x0325,0xb0}, +{0x0327,0x07}, +{0x300f,0x11}, +{0x3012,0x21}, +{0x3026,0x10}, +{0x3027,0x08}, +{0x302d,0x24}, +{0x3106,0x10}, +{0x3400,0x00}, +{0x3406,0x08}, +{0x3408,0x05}, +{0x340c,0x05}, +{0x3425,0x51}, +{0x3426,0x10}, +{0x3427,0x14}, +{0x3428,0x50}, +{0x3429,0x10}, +{0x342a,0x10}, +{0x342b,0x04}, +{0x3504,0x08}, +{0x3508,0x01}, +{0x3509,0x00}, +{0x3544,0x08}, +{0x3548,0x01}, +{0x3549,0x00}, +{0x3584,0x08}, +{0x3588,0x01}, +{0x3589,0x00}, +{0x3601,0x70}, +{0x3604,0xe3}, +{0x3605,0xff}, +{0x3606,0x01}, +{0x3608,0xa8}, +{0x360a,0xd0}, +{0x360b,0x08}, +{0x360e,0xc8}, +{0x360f,0x66}, +{0x3610,0x81}, +{0x3611,0x89}, +{0x3612,0x4e}, +{0x3613,0xbd}, +{0x362a,0x0e}, +{0x362b,0x0e}, +{0x362c,0x0e}, +{0x362d,0x0e}, +{0x362e,0x0c}, +{0x362f,0x1a}, +{0x3630,0x32}, +{0x3631,0x64}, +{0x3638,0x00}, +{0x3643,0x00}, +{0x3644,0x00}, +{0x3645,0x00}, +{0x3646,0x00}, +{0x3647,0x00}, +{0x3648,0x00}, +{0x3649,0x00}, +{0x364a,0x04}, +{0x364c,0x0e}, +{0x364d,0x0e}, +{0x364e,0x0e}, +{0x364f,0x0e}, +{0x3650,0xff}, +{0x3651,0xff}, +{0x3661,0x07}, +{0x3662,0x00}, +{0x3663,0x20}, +{0x3665,0x12}, +{0x3667,0xd4}, +{0x3668,0x80}, +{0x366f,0x00}, +{0x3671,0x08}, +{0x3673,0x2a}, +{0x3681,0x80}, +{0x3700,0x26}, +{0x3701,0x1e}, +{0x3702,0x25}, +{0x3703,0x28}, +{0x3706,0xb1}, +{0x3707,0x0a}, +{0x3708,0x34}, +{0x3709,0x50}, +{0x370a,0x02}, +{0x370b,0x21}, +{0x3714,0x01}, +{0x371b,0x13}, +{0x371c,0x00}, +{0x371d,0x08}, +{0x3756,0xe7}, +{0x3757,0xe7}, +{0x3762,0x1d}, +{0x376c,0x00}, +{0x3776,0x03}, +{0x3777,0x22}, +{0x3779,0x60}, +{0x377c,0x48}, +{0x379c,0x4d}, +{0x3784,0x06}, +{0x3785,0x0a}, +{0x37d1,0xb1}, +{0x37d2,0x02}, +{0x37d3,0x21}, +{0x37d5,0xb1}, +{0x37d6,0x02}, +{0x37d7,0x21}, +{0x37d8,0x01}, +{0x37dc,0x00}, +{0x3790,0x10}, +{0x3793,0x04}, +{0x3794,0x07}, +{0x3796,0x00}, +{0x3797,0x02}, +{0x37a1,0x80}, +{0x37bb,0x88}, +{0x37be,0x01}, +{0x37bf,0x00}, +{0x37c0,0x01}, +{0x37c7,0x56}, +{0x37ca,0x21}, +{0x37cd,0x90}, +{0x37cf,0x02}, +{0x3800,0x00}, +{0x3801,0x00}, +{0x3802,0x00}, +{0x3803,0x04}, +{0x3804,0x07}, +{0x3805,0x8f}, +{0x3806,0x04}, +{0x3807,0x43}, +{0x3808,0x07}, +{0x3809,0x80}, +{0x380a,0x04}, +{0x380b,0x38}, +{0x380c,0x0e}, +{0x380d,0xc8}, +{0x380e,0x05}, +{0x380f,0xb4}, +{0x3811,0x08}, +{0x3813,0x04}, +{0x3814,0x01}, +{0x3815,0x01}, +{0x3816,0x01}, +{0x3817,0x01}, +{0x381c,0x00}, +{0x3820,0x02}, +{0x3821,0x00}, +{0x3822,0x14}, +{0x384c,0x04}, +{0x384d,0xc8}, +{0x3858,0x0d}, +{0x3865,0x00}, +{0x3866,0xc0}, +{0x3867,0x00}, +{0x3868,0xc0}, +{0x3900,0x13}, +{0x3940,0x13}, +{0x3980,0x13}, +{0x3c01,0x11}, +{0x3c05,0x00}, +{0x3c0f,0x1c}, +{0x3c12,0x0d}, +{0x3c19,0x01}, +{0x3c21,0x40}, +{0x3c3b,0x18}, +{0x3c3d,0xc9}, +{0x3c55,0xcb}, +{0x3c5d,0xec}, +{0x3c5e,0xec}, +{0x3ce0,0x00}, +{0x3ce1,0x00}, +{0x3ce2,0x00}, +{0x3ce3,0x00}, +{0x3d8c,0x70}, +{0x3d8d,0x10}, +{0x4001,0x2f}, +{0x4033,0x80}, +{0x4008,0x02}, +{0x4009,0x11}, +{0x4004,0x01}, +{0x4005,0x00}, +{0x400a,0x03}, +{0x400b,0x40}, +{0x410f,0x01}, +{0x402e,0x01}, +{0x402f,0x00}, +{0x4030,0x01}, +{0x4031,0x00}, +{0x4032,0x9f}, +{0x4050,0x00}, +{0x4051,0x07}, +{0x4288,0xcf}, +{0x4289,0x03}, +{0x428a,0x46}, +{0x430b,0xff}, +{0x430c,0xff}, +{0x430d,0x00}, +{0x430e,0x00}, +{0x4500,0x18}, +{0x4501,0x18}, +{0x4504,0x00}, +{0x4507,0x02}, +{0x4603,0x00}, +{0x4640,0x62}, +{0x4646,0xaa}, +{0x4647,0x55}, +{0x4648,0x99}, +{0x4649,0x66}, +{0x464d,0x00}, +{0x4654,0x11}, +{0x4655,0x22}, +{0x4800,0x04}, +{0x4810,0xff}, +{0x4811,0xff}, +{0x480e,0x00}, +{0x4813,0x00}, +{0x4837,0x0c}, +{0x484b,0x27}, +{0x4d00,0x4e}, +{0x4d01,0x0c}, +{0x4d09,0x4f}, +{0x5000,0x1f}, +{0x5080,0x00}, +{0x50c0,0x00}, +{0x5100,0x00}, +{0x5200,0x00}, +{0x5201,0x70}, +{0x5202,0x03}, +{0x5203,0x7f}, +{0x3501,0x01}, +{0x380e,0x18}, +{0x380f,0x18}, +{0x3501,0x03}, +{0x3502,0x74}, +{0x0100,0x01}, +}; + +struct vvcam_sccb_array os02k10_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(os02k10_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = os02k10_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_reg_cfg.h b/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_reg_cfg.h new file mode 100755 index 0000000..eff9c12 --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_os02k10/os02k10_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OS02k10_REG_CFG_H_ +#define _OS02k10_REG_CFG_H_ + +extern struct vvcam_sccb_array os02k10_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_driver.c b/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_driver.c new file mode 100755 index 0000000..7461861 --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_driver.c @@ -0,0 +1,493 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "ov2775_reg_cfg.h" + +#define SENSOR_CLK 51000000 + +static struct vvcam_mode_info pov2775_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_array *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pov2775_mode_info); + + memcpy(pmode_info_arry->modes,pov2775_mode_info,sizeof(pov2775_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pov2775_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pov2775_mode_info[i].index == pmode->index) + { + psensor_mode = &(pov2775_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&ov2775_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&ov2775_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3012, 0x01); + }else + { + ret = sensor_write_reg(ctx, 0x3012, 0x00); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s ov2775_function = +{ + .sensor_name = "ov2775", + .reserve_id = 0x2770, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_driver.h b/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_driver.h new file mode 100755 index 0000000..e027d75 --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OMNIVISION_OV2775_H_ +#define _OMNIVISION_OV2775_H_ + +extern struct vvcam_sensor_function_s ov2775_function; + + +#endif diff --git a/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.c b/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..28c0ad3 --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,1880 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data ov2775_mipi4lane_1080p_30fps_linear_reg[] = { + {0x3000, 0x02}, + {0x3001, 0x28}, + {0x3002, 0x03}, + {0x3003, 0x01}, + {0x3004, 0x05}, + {0x3005, 0x26}, + {0x3006, 0x00}, + {0x3007, 0x07}, + {0x3008, 0x01}, + {0x3009, 0x00}, + {0x300c, 0x6c}, + {0x300e, 0x80}, + {0x300f, 0x00}, + {0x3012, 0x00}, + {0x3013, 0x00}, + {0x3014, 0xc4}, + {0x3015, 0x00}, + {0x3017, 0x00}, + {0x3018, 0x00}, + {0x3019, 0x00}, + {0x301a, 0x00}, + {0x301b, 0x0e}, + {0x301e, 0x17}, + {0x301f, 0xe1}, + {0x3030, 0x02}, + {0x3031, 0x62}, + {0x3032, 0xf0}, + {0x3033, 0x30}, + {0x3034, 0x3f}, + {0x3035, 0x5f}, + {0x3036, 0x02}, + {0x3037, 0x9f}, + {0x3038, 0x04}, + {0x3039, 0xb7}, + {0x303a, 0x04}, + {0x303b, 0x07}, + {0x303c, 0xf0}, + {0x303d, 0x00}, + {0x303e, 0x0b}, + {0x303f, 0xe3}, + {0x3040, 0xf3}, + {0x3041, 0x29}, + {0x3042, 0xf6}, + {0x3043, 0x65}, + {0x3044, 0x06}, + {0x3045, 0x0f}, + {0x3046, 0x59}, + {0x3047, 0x07}, + {0x3048, 0x82}, + {0x3049, 0xcf}, + {0x304a, 0x12}, + {0x304b, 0x40}, + {0x304c, 0x33}, + {0x304d, 0xa4}, + {0x304e, 0x0b}, + {0x304f, 0x3d}, + {0x3050, 0x10}, + {0x3060, 0x00}, + {0x3061, 0x64}, + {0x3062, 0x00}, + {0x3063, 0xe4}, + {0x3066, 0x80}, + {0x3080, 0x00}, + {0x3081, 0x00}, + {0x3082, 0x01}, + {0x3083, 0xe3}, + {0x3084, 0x06}, + {0x3085, 0x00}, + {0x3086, 0x10}, + {0x3087, 0x10}, + {0x3089, 0x00}, + {0x308a, 0x01}, + {0x3093, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x00}, + {0x30aa, 0x00}, + {0x30ab, 0x00}, + {0x30ac, 0x07}, + {0x30ad, 0x90}, + {0x30ae, 0x04}, + {0x30af, 0x48}, + {0x30b0, 0x04}, + {0x30b1, 0x7e}, + {0x30b2, 0x04}, + {0x30b3, 0x65}, + {0x30b4, 0x00}, + {0x30b5, 0x00}, + {0x30b6, 0x00}, + {0x30b7, 0x10}, + {0x30b8, 0x00}, + {0x30b9, 0x02}, + {0x30ba, 0x10}, + {0x30bb, 0x00}, + {0x30bc, 0x00}, + {0x30bd, 0x03}, + {0x30be, 0x5c}, + {0x30bf, 0x00}, + {0x30c0, 0x05}, + {0x30c1, 0x00}, + {0x30c2, 0x20}, + {0x30c3, 0x00}, + {0x30c4, 0x4a}, + {0x30c5, 0x00}, + {0x30c7, 0x00}, + {0x30c8, 0x00}, + {0x30d1, 0x00}, + {0x30d2, 0x00}, + {0x30d3, 0x80}, + {0x30d4, 0x00}, + {0x30d9, 0x09}, + {0x30da, 0x64}, + {0x30dd, 0x00}, + {0x30de, 0x16}, + {0x30df, 0x00}, + {0x30e0, 0x17}, + {0x30e1, 0x00}, + {0x30e2, 0x18}, + {0x30e3, 0x10}, + {0x30e4, 0x04}, + {0x30e5, 0x00}, + {0x30e6, 0x00}, + {0x30e7, 0x00}, + {0x30e8, 0x00}, + {0x30e9, 0x00}, + {0x30ea, 0x00}, + {0x30eb, 0x00}, + {0x30ec, 0x00}, + {0x30ed, 0x00}, + {0x3101, 0x00}, + {0x3102, 0x00}, + {0x3103, 0x00}, + {0x3104, 0x00}, + {0x3105, 0x8c}, + {0x3106, 0x87}, + {0x3107, 0xc0}, + {0x3108, 0x9d}, + {0x3109, 0x8d}, + {0x310a, 0x8d}, + {0x310b, 0x6a}, + {0x310c, 0x3a}, + {0x310d, 0x5a}, + {0x310e, 0x00}, + {0x3120, 0x00}, + {0x3121, 0x00}, + {0x3122, 0x00}, + {0x3123, 0xf0}, + {0x3124, 0x00}, + {0x3125, 0x70}, + {0x3126, 0x1f}, + {0x3127, 0x0f}, + {0x3128, 0x00}, + {0x3129, 0x3a}, + {0x312a, 0x02}, + {0x312b, 0x0f}, + {0x312c, 0x00}, + {0x312d, 0x0f}, + {0x312e, 0x1d}, + {0x312f, 0x00}, + {0x3130, 0x00}, + {0x3131, 0x00}, + {0x3132, 0x00}, + {0x3140, 0x0a}, + {0x3141, 0x03}, + {0x3142, 0x00}, + {0x3143, 0x00}, + {0x3144, 0x00}, + {0x3145, 0x00}, + {0x3146, 0x00}, + {0x3147, 0x00}, + {0x3148, 0x00}, + {0x3149, 0x00}, + {0x314a, 0x00}, + {0x314b, 0x00}, + {0x314c, 0x00}, + {0x314d, 0x00}, + {0x314e, 0x1c}, + {0x314f, 0xff}, + {0x3150, 0xff}, + {0x3151, 0xff}, + {0x3152, 0x10}, + {0x3153, 0x10}, + {0x3154, 0x10}, + {0x3155, 0x00}, + {0x3156, 0x03}, + {0x3157, 0x00}, + {0x3158, 0x0f}, + {0x3159, 0xff}, + {0x315a, 0x01}, + {0x315b, 0x00}, + {0x315c, 0x01}, + {0x315d, 0x00}, + {0x315e, 0x01}, + {0x315f, 0x00}, + {0x3160, 0x00}, + {0x3161, 0x40}, + {0x3162, 0x00}, + {0x3163, 0x40}, + {0x3164, 0x00}, + {0x3165, 0x40}, + {0x3190, 0x08}, + {0x3191, 0x99}, + {0x3193, 0x08}, + {0x3194, 0x13}, + {0x3195, 0x33}, + {0x3196, 0x00}, + {0x3197, 0x10}, + {0x3198, 0x00}, + {0x3199, 0x7f}, + {0x319a, 0x80}, + {0x319b, 0xff}, + {0x319c, 0x80}, + {0x319d, 0xbf}, + {0x319e, 0xc0}, + {0x319f, 0xff}, + {0x31a0, 0x24}, + {0x31a1, 0x55}, + {0x31a2, 0x00}, + {0x31a3, 0x00}, + {0x31a6, 0x00}, + {0x31a7, 0x00}, + {0x31b0, 0x00}, + {0x31b1, 0x00}, + {0x31b2, 0x02}, + {0x31b3, 0x00}, + {0x31b4, 0x00}, + {0x31b5, 0x01}, + {0x31b6, 0x00}, + {0x31b7, 0x00}, + {0x31b8, 0x00}, + {0x31b9, 0x00}, + {0x31ba, 0x00}, + {0x31d0, 0x3c}, + {0x31d1, 0x34}, + {0x31d2, 0x3c}, + {0x31d3, 0x00}, + {0x31d4, 0x2d}, + {0x31d5, 0x00}, + {0x31d6, 0x01}, + {0x31d7, 0x06}, + {0x31d8, 0x00}, + {0x31d9, 0x64}, + {0x31da, 0x00}, + {0x31db, 0x30}, + {0x31dc, 0x04}, + {0x31dd, 0x69}, + {0x31de, 0x0a}, + {0x31df, 0x3c}, + {0x31e0, 0x04}, + {0x31e1, 0x32}, + {0x31e2, 0x00}, + {0x31e3, 0x00}, + {0x31e4, 0x08}, + {0x31e5, 0x80}, + {0x31e6, 0x00}, + {0x31e7, 0x2c}, + {0x31e8, 0x6c}, + {0x31e9, 0xac}, + {0x31ea, 0xec}, + {0x31eb, 0x3f}, + {0x31ec, 0x0f}, + {0x31ed, 0x20}, + {0x31ee, 0x04}, + {0x31ef, 0x48}, + {0x31f0, 0x07}, + {0x31f1, 0x90}, + {0x31f2, 0x04}, + {0x31f3, 0x48}, + {0x31f4, 0x07}, + {0x31f5, 0x90}, + {0x31f6, 0x04}, + {0x31f7, 0x48}, + {0x31f8, 0x07}, + {0x31f9, 0x90}, + {0x31fa, 0x04}, + {0x31fb, 0x48}, + {0x31fd, 0xcb}, + {0x31fe, 0x0f}, + {0x31ff, 0x03}, + {0x3200, 0x00}, + {0x3201, 0xff}, + {0x3202, 0x00}, + {0x3203, 0xff}, + {0x3204, 0xff}, + {0x3205, 0xff}, + {0x3206, 0xff}, + {0x3207, 0xff}, + {0x3208, 0xff}, + {0x3209, 0xff}, + {0x320a, 0xff}, + {0x320b, 0x1b}, + {0x320c, 0x1f}, + {0x320d, 0x1e}, + {0x320e, 0x30}, + {0x320f, 0x2d}, + {0x3210, 0x2c}, + {0x3211, 0x2b}, + {0x3212, 0x2a}, + {0x3213, 0x24}, + {0x3214, 0x22}, + {0x3215, 0x00}, + {0x3216, 0x04}, + {0x3217, 0x2c}, + {0x3218, 0x6c}, + {0x3219, 0xac}, + {0x321a, 0xec}, + {0x321b, 0x00}, + {0x3230, 0x3a}, + {0x3231, 0x00}, + {0x3232, 0x80}, + {0x3233, 0x00}, + {0x3234, 0x10}, + {0x3235, 0xaa}, + {0x3236, 0x55}, + {0x3237, 0x99}, + {0x3238, 0x66}, + {0x3239, 0x08}, + {0x323a, 0x88}, + {0x323b, 0x00}, + {0x323c, 0x00}, + {0x323d, 0x03}, + {0x3250, 0x33}, + {0x3251, 0x00}, + {0x3252, 0x20}, + {0x3253, 0x00}, + {0x3254, 0x00}, + {0x3255, 0x01}, + {0x3256, 0x00}, + {0x3257, 0x00}, + {0x3258, 0x00}, + {0x3270, 0x01}, + {0x3271, 0x60}, + {0x3272, 0xc0}, + {0x3273, 0x00}, + {0x3274, 0x80}, + {0x3275, 0x40}, + {0x3276, 0x02}, + {0x3277, 0x08}, + {0x3278, 0x10}, + {0x3279, 0x04}, + {0x327a, 0x00}, + {0x327b, 0x03}, + {0x327c, 0x10}, + {0x327d, 0x60}, + {0x327e, 0xc0}, + {0x327f, 0x06}, + {0x3288, 0x10}, + {0x3289, 0x00}, + {0x328a, 0x08}, + {0x328b, 0x00}, + {0x328c, 0x04}, + {0x328d, 0x00}, + {0x328e, 0x02}, + {0x328f, 0x00}, + {0x3290, 0x20}, + {0x3291, 0x00}, + {0x3292, 0x10}, + {0x3293, 0x00}, + {0x3294, 0x08}, + {0x3295, 0x00}, + {0x3296, 0x04}, + {0x3297, 0x00}, + {0x3298, 0x40}, + {0x3299, 0x00}, + {0x329a, 0x20}, + {0x329b, 0x00}, + {0x329c, 0x10}, + {0x329d, 0x00}, + {0x329e, 0x08}, + {0x329f, 0x00}, + {0x32a0, 0x7f}, + {0x32a1, 0xff}, + {0x32a2, 0x40}, + {0x32a3, 0x00}, + {0x32a4, 0x20}, + {0x32a5, 0x00}, + {0x32a6, 0x10}, + {0x32a7, 0x00}, + {0x32a8, 0x00}, + {0x32a9, 0x00}, + {0x32aa, 0x00}, + {0x32ab, 0x00}, + {0x32ac, 0x00}, + {0x32ad, 0x00}, + {0x32ae, 0x00}, + {0x32af, 0x00}, + {0x32b0, 0x00}, + {0x32b1, 0x00}, + {0x32b2, 0x00}, + {0x32b3, 0x00}, + {0x32b4, 0x00}, + {0x32b5, 0x00}, + {0x32b6, 0x00}, + {0x32b7, 0x00}, + {0x32b8, 0x00}, + {0x32b9, 0x00}, + {0x32ba, 0x00}, + {0x32bb, 0x00}, + {0x32bc, 0x00}, + {0x32bd, 0x00}, + {0x32be, 0x00}, + {0x32bf, 0x00}, + {0x32c0, 0x00}, + {0x32c1, 0x00}, + {0x32c2, 0x00}, + {0x32c3, 0x00}, + {0x32c4, 0x00}, + {0x32c5, 0x00}, + {0x32c6, 0x00}, + {0x32c7, 0x00}, + {0x32c8, 0x87}, + {0x32c9, 0x00}, + {0x3330, 0x03}, + {0x3331, 0xc8}, + {0x3332, 0x02}, + {0x3333, 0x24}, + {0x3334, 0x00}, + {0x3335, 0x00}, + {0x3336, 0x00}, + {0x3337, 0x00}, + {0x3338, 0x03}, + {0x3339, 0xc8}, + {0x333a, 0x02}, + {0x333b, 0x24}, + {0x333c, 0x00}, + {0x333d, 0x00}, + {0x333e, 0x00}, + {0x333f, 0x00}, + {0x3340, 0x03}, + {0x3341, 0xc8}, + {0x3342, 0x02}, + {0x3343, 0x24}, + {0x3344, 0x00}, + {0x3345, 0x00}, + {0x3346, 0x00}, + {0x3347, 0x00}, + {0x3348, 0x40}, + {0x3349, 0x00}, + {0x334a, 0x00}, + {0x334b, 0x00}, + {0x334c, 0x00}, + {0x334d, 0x00}, + {0x334e, 0x80}, + {0x3360, 0x01}, + {0x3361, 0x00}, + {0x3362, 0x01}, + {0x3363, 0x00}, + {0x3364, 0x01}, + {0x3365, 0x00}, + {0x3366, 0x01}, + {0x3367, 0x00}, + {0x3368, 0x01}, + {0x3369, 0x00}, + {0x336a, 0x01}, + {0x336b, 0x00}, + {0x336c, 0x01}, + {0x336d, 0x00}, + {0x336e, 0x01}, + {0x336f, 0x00}, + {0x3370, 0x01}, + {0x3371, 0x00}, + {0x3372, 0x01}, + {0x3373, 0x00}, + {0x3374, 0x01}, + {0x3375, 0x00}, + {0x3376, 0x01}, + {0x3377, 0x00}, + {0x3378, 0x00}, + {0x3379, 0x00}, + {0x337a, 0x00}, + {0x337b, 0x00}, + {0x337c, 0x00}, + {0x337d, 0x00}, + {0x337e, 0x00}, + {0x337f, 0x00}, + {0x3380, 0x00}, + {0x3381, 0x00}, + {0x3382, 0x00}, + {0x3383, 0x00}, + {0x3384, 0x00}, + {0x3385, 0x00}, + {0x3386, 0x00}, + {0x3387, 0x00}, + {0x3388, 0x00}, + {0x3389, 0x00}, + {0x338a, 0x00}, + {0x338b, 0x00}, + {0x338c, 0x00}, + {0x338d, 0x00}, + {0x338e, 0x00}, + {0x338f, 0x00}, + {0x3390, 0x00}, + {0x3391, 0x00}, + {0x3392, 0x00}, + {0x3393, 0x00}, + {0x3394, 0x00}, + {0x3395, 0x00}, + {0x3396, 0x00}, + {0x3397, 0x00}, + {0x3398, 0x00}, + {0x3399, 0x00}, + {0x339a, 0x00}, + {0x339b, 0x00}, + {0x33b0, 0x00}, + {0x33b1, 0x50}, + {0x33b2, 0x01}, + {0x33b3, 0xff}, + {0x33b4, 0xe0}, + {0x33b5, 0x6b}, + {0x33b6, 0x00}, + {0x33b7, 0x00}, + {0x33b8, 0x00}, + {0x33b9, 0x00}, + {0x33ba, 0x00}, + {0x33bb, 0x1f}, + {0x33bc, 0x01}, + {0x33bd, 0x01}, + {0x33be, 0x01}, + {0x33bf, 0x01}, + {0x33c0, 0x00}, + {0x33c1, 0x00}, + {0x33c2, 0x00}, + {0x33c3, 0x00}, + {0x33e0, 0x14}, + {0x33e1, 0x0f}, + {0x33e2, 0x02}, + {0x33e3, 0x01}, + {0x33e4, 0x01}, + {0x33e5, 0x01}, + {0x33e6, 0x00}, + {0x33e7, 0x04}, + {0x33e8, 0x0c}, + {0x33e9, 0x02}, + {0x33ea, 0x02}, + {0x33eb, 0x02}, + {0x33ec, 0x03}, + {0x33ed, 0x01}, + {0x33ee, 0x02}, + {0x33ef, 0x08}, + {0x33f0, 0x08}, + {0x33f1, 0x04}, + {0x33f2, 0x04}, + {0x33f3, 0x00}, + {0x33f4, 0x03}, + {0x33f5, 0x14}, + {0x33f6, 0x0f}, + {0x33f7, 0x02}, + {0x33f8, 0x01}, + {0x33f9, 0x01}, + {0x33fa, 0x01}, + {0x33fb, 0x00}, + {0x33fc, 0x04}, + {0x33fd, 0x0c}, + {0x33fe, 0x02}, + {0x33ff, 0x02}, + {0x3400, 0x02}, + {0x3401, 0x03}, + {0x3402, 0x01}, + {0x3403, 0x02}, + {0x3404, 0x08}, + {0x3405, 0x08}, + {0x3406, 0x04}, + {0x3407, 0x04}, + {0x3408, 0x00}, + {0x3409, 0x03}, + {0x340a, 0x14}, + {0x340b, 0x0f}, + {0x340c, 0x04}, + {0x340d, 0x02}, + {0x340e, 0x01}, + {0x340f, 0x01}, + {0x3410, 0x00}, + {0x3411, 0x04}, + {0x3412, 0x0c}, + {0x3413, 0x02}, + {0x3414, 0x02}, + {0x3415, 0x02}, + {0x3416, 0x03}, + {0x3417, 0x02}, + {0x3418, 0x05}, + {0x3419, 0x0a}, + {0x341a, 0x08}, + {0x341b, 0x04}, + {0x341c, 0x04}, + {0x341d, 0x00}, + {0x341e, 0x03}, + {0x3440, 0x00}, + {0x3441, 0x00}, + {0x3442, 0x00}, + {0x3443, 0x00}, + {0x3444, 0x02}, + {0x3445, 0xf0}, + {0x3446, 0x02}, + {0x3447, 0x08}, + {0x3448, 0x00}, + {0x3460, 0x40}, + {0x3461, 0x40}, + {0x3462, 0x40}, + {0x3463, 0x40}, + {0x3464, 0x03}, + {0x3465, 0x01}, + {0x3466, 0x01}, + {0x3467, 0x02}, + {0x3468, 0x30}, + {0x3469, 0x00}, + {0x346a, 0x33}, + {0x346b, 0xbf}, + {0x3480, 0x40}, + {0x3481, 0x00}, + {0x3482, 0x00}, + {0x3483, 0x00}, + {0x3484, 0x0d}, + {0x3485, 0x00}, + {0x3486, 0x00}, + {0x3487, 0x00}, + {0x3488, 0x00}, + {0x3489, 0x00}, + {0x348a, 0x00}, + {0x348b, 0x04}, + {0x348c, 0x00}, + {0x348d, 0x01}, + {0x348f, 0x01}, + {0x3030, 0x0a}, + {0x3030, 0x02}, + {0x7000, 0x58}, + {0x7001, 0x7a}, + {0x7002, 0x1a}, + {0x7003, 0xc1}, + {0x7004, 0x03}, + {0x7005, 0xda}, + {0x7006, 0xbd}, + {0x7007, 0x03}, + {0x7008, 0xbd}, + {0x7009, 0x06}, + {0x700a, 0xe6}, + {0x700b, 0xec}, + {0x700c, 0xbc}, + {0x700d, 0xff}, + {0x700e, 0xbc}, + {0x700f, 0x73}, + {0x7010, 0xda}, + {0x7011, 0x72}, + {0x7012, 0x76}, + {0x7013, 0xb6}, + {0x7014, 0xee}, + {0x7015, 0xcf}, + {0x7016, 0xac}, + {0x7017, 0xd0}, + {0x7018, 0xac}, + {0x7019, 0xd1}, + {0x701a, 0x50}, + {0x701b, 0xac}, + {0x701c, 0xd2}, + {0x701d, 0xbc}, + {0x701e, 0x2e}, + {0x701f, 0xb4}, + {0x7020, 0x00}, + {0x7021, 0xdc}, + {0x7022, 0xdf}, + {0x7023, 0xb0}, + {0x7024, 0x6e}, + {0x7025, 0xbd}, + {0x7026, 0x01}, + {0x7027, 0xd7}, + {0x7028, 0xed}, + {0x7029, 0xe1}, + {0x702a, 0x36}, + {0x702b, 0x30}, + {0x702c, 0xd3}, + {0x702d, 0x2e}, + {0x702e, 0x54}, + {0x702f, 0x46}, + {0x7030, 0xbc}, + {0x7031, 0x22}, + {0x7032, 0x66}, + {0x7033, 0xbc}, + {0x7034, 0x24}, + {0x7035, 0x2c}, + {0x7036, 0x28}, + {0x7037, 0xbc}, + {0x7038, 0x3c}, + {0x7039, 0xa1}, + {0x703a, 0xac}, + {0x703b, 0xd8}, + {0x703c, 0xd6}, + {0x703d, 0xb4}, + {0x703e, 0x04}, + {0x703f, 0x46}, + {0x7040, 0xb7}, + {0x7041, 0x04}, + {0x7042, 0xbe}, + {0x7043, 0x08}, + {0x7044, 0xc3}, + {0x7045, 0xd9}, + {0x7046, 0xad}, + {0x7047, 0xc3}, + {0x7048, 0xbc}, + {0x7049, 0x19}, + {0x704a, 0xc1}, + {0x704b, 0x27}, + {0x704c, 0xe7}, + {0x704d, 0x00}, + {0x704e, 0x50}, + {0x704f, 0x20}, + {0x7050, 0xb8}, + {0x7051, 0x02}, + {0x7052, 0xbc}, + {0x7053, 0x17}, + {0x7054, 0xdb}, + {0x7055, 0xc7}, + {0x7056, 0xb8}, + {0x7057, 0x00}, + {0x7058, 0x28}, + {0x7059, 0x54}, + {0x705a, 0xb4}, + {0x705b, 0x14}, + {0x705c, 0xab}, + {0x705d, 0xbe}, + {0x705e, 0x06}, + {0x705f, 0xd8}, + {0x7060, 0xd6}, + {0x7061, 0x00}, + {0x7062, 0xb4}, + {0x7063, 0xc7}, + {0x7064, 0x07}, + {0x7065, 0xb9}, + {0x7066, 0x05}, + {0x7067, 0xee}, + {0x7068, 0xe6}, + {0x7069, 0xad}, + {0x706a, 0xb4}, + {0x706b, 0x26}, + {0x706c, 0x19}, + {0x706d, 0xc1}, + {0x706e, 0x3a}, + {0x706f, 0xc3}, + {0x7070, 0xaf}, + {0x7071, 0x00}, + {0x7072, 0xc0}, + {0x7073, 0x3c}, + {0x7074, 0xc3}, + {0x7075, 0xbe}, + {0x7076, 0xe7}, + {0x7077, 0x00}, + {0x7078, 0x15}, + {0x7079, 0xc2}, + {0x707a, 0x40}, + {0x707b, 0xc3}, + {0x707c, 0xa4}, + {0x707d, 0xc0}, + {0x707e, 0x3c}, + {0x707f, 0x00}, + {0x7080, 0xb9}, + {0x7081, 0x64}, + {0x7082, 0x29}, + {0x7083, 0x00}, + {0x7084, 0xb8}, + {0x7085, 0x12}, + {0x7086, 0xbe}, + {0x7087, 0x01}, + {0x7088, 0xd0}, + {0x7089, 0xbc}, + {0x708a, 0x01}, + {0x708b, 0xac}, + {0x708c, 0x37}, + {0x708d, 0xd2}, + {0x708e, 0xac}, + {0x708f, 0x45}, + {0x7090, 0xad}, + {0x7091, 0x28}, + {0x7092, 0x00}, + {0x7093, 0xb8}, + {0x7094, 0x00}, + {0x7095, 0xbc}, + {0x7096, 0x01}, + {0x7097, 0x36}, + {0x7098, 0xd3}, + {0x7099, 0x30}, + {0x709a, 0x04}, + {0x709b, 0xe0}, + {0x709c, 0xd8}, + {0x709d, 0xb4}, + {0x709e, 0xe9}, + {0x709f, 0x00}, + {0x70a0, 0xbe}, + {0x70a1, 0x05}, + {0x70a2, 0x62}, + {0x70a3, 0x07}, + {0x70a4, 0xb9}, + {0x70a5, 0x05}, + {0x70a6, 0xad}, + {0x70a7, 0xc3}, + {0x70a8, 0xcf}, + {0x70a9, 0x00}, + {0x70aa, 0x15}, + {0x70ab, 0xc2}, + {0x70ac, 0x59}, + {0x70ad, 0xc3}, + {0x70ae, 0xc9}, + {0x70af, 0xc0}, + {0x70b0, 0x55}, + {0x70b1, 0x00}, + {0x70b2, 0x46}, + {0x70b3, 0xa1}, + {0x70b4, 0xb9}, + {0x70b5, 0x64}, + {0x70b6, 0x29}, + {0x70b7, 0x00}, + {0x70b8, 0xb8}, + {0x70b9, 0x02}, + {0x70ba, 0xbe}, + {0x70bb, 0x02}, + {0x70bc, 0xd0}, + {0x70bd, 0xdc}, + {0x70be, 0xac}, + {0x70bf, 0xbc}, + {0x70c0, 0x01}, + {0x70c1, 0x37}, + {0x70c2, 0xac}, + {0x70c3, 0xd2}, + {0x70c4, 0x45}, + {0x70c5, 0xad}, + {0x70c6, 0x28}, + {0x70c7, 0x00}, + {0x70c8, 0xb8}, + {0x70c9, 0x00}, + {0x70ca, 0xbc}, + {0x70cb, 0x01}, + {0x70cc, 0x36}, + {0x70cd, 0x30}, + {0x70ce, 0xe0}, + {0x70cf, 0xd8}, + {0x70d0, 0xb5}, + {0x70d1, 0x0b}, + {0x70d2, 0xd6}, + {0x70d3, 0xbe}, + {0x70d4, 0x07}, + {0x70d5, 0x00}, + {0x70d6, 0x62}, + {0x70d7, 0x07}, + {0x70d8, 0xb9}, + {0x70d9, 0x05}, + {0x70da, 0xad}, + {0x70db, 0xc3}, + {0x70dc, 0xcf}, + {0x70dd, 0x46}, + {0x70de, 0xcd}, + {0x70df, 0x07}, + {0x70e0, 0xcd}, + {0x70e1, 0x00}, + {0x70e2, 0xe3}, + {0x70e3, 0x18}, + {0x70e4, 0xc2}, + {0x70e5, 0xa2}, + {0x70e6, 0xb9}, + {0x70e7, 0x64}, + {0x70e8, 0xd1}, + {0x70e9, 0xdd}, + {0x70ea, 0xac}, + {0x70eb, 0xcf}, + {0x70ec, 0xdf}, + {0x70ed, 0xb5}, + {0x70ee, 0x19}, + {0x70ef, 0x46}, + {0x70f0, 0x50}, + {0x70f1, 0xb6}, + {0x70f2, 0xee}, + {0x70f3, 0xe8}, + {0x70f4, 0xe6}, + {0x70f5, 0xbc}, + {0x70f6, 0x31}, + {0x70f7, 0xe1}, + {0x70f8, 0x36}, + {0x70f9, 0x30}, + {0x70fa, 0xd3}, + {0x70fb, 0x2e}, + {0x70fc, 0x54}, + {0x70fd, 0xbd}, + {0x70fe, 0x03}, + {0x70ff, 0xec}, + {0x7100, 0x2c}, + {0x7101, 0x50}, + {0x7102, 0x20}, + {0x7103, 0x04}, + {0x7104, 0xb8}, + {0x7105, 0x02}, + {0x7106, 0xbc}, + {0x7107, 0x18}, + {0x7108, 0xc7}, + {0x7109, 0xb8}, + {0x710a, 0x00}, + {0x710b, 0x28}, + {0x710c, 0x54}, + {0x710d, 0xbc}, + {0x710e, 0x02}, + {0x710f, 0xb4}, + {0x7110, 0xda}, + {0x7111, 0xbe}, + {0x7112, 0x04}, + {0x7113, 0xd6}, + {0x7114, 0xd8}, + {0x7115, 0xab}, + {0x7116, 0x00}, + {0x7117, 0x62}, + {0x7118, 0x07}, + {0x7119, 0xb9}, + {0x711a, 0x05}, + {0x711b, 0xad}, + {0x711c, 0xc3}, + {0x711d, 0xbc}, + {0x711e, 0xe7}, + {0x711f, 0xb9}, + {0x7120, 0x64}, + {0x7121, 0x29}, + {0x7122, 0x00}, + {0x7123, 0xb8}, + {0x7124, 0x02}, + {0x7125, 0xbe}, + {0x7126, 0x00}, + {0x7127, 0x45}, + {0x7128, 0xad}, + {0x7129, 0xe2}, + {0x712a, 0x28}, + {0x712b, 0x00}, + {0x712c, 0xb8}, + {0x712d, 0x00}, + {0x712e, 0xe0}, + {0x712f, 0xd8}, + {0x7130, 0xb4}, + {0x7131, 0xe9}, + {0x7132, 0xbe}, + {0x7133, 0x03}, + {0x7134, 0x00}, + {0x7135, 0x30}, + {0x7136, 0x62}, + {0x7137, 0x07}, + {0x7138, 0xb9}, + {0x7139, 0x05}, + {0x713a, 0xad}, + {0x713b, 0xc3}, + {0x713c, 0xcf}, + {0x713d, 0x42}, + {0x713e, 0xe4}, + {0x713f, 0xcd}, + {0x7140, 0x07}, + {0x7141, 0xcd}, + {0x7142, 0x00}, + {0x7143, 0x00}, + {0x7144, 0x17}, + {0x7145, 0xc2}, + {0x7146, 0xbb}, + {0x7147, 0xde}, + {0x7148, 0xcf}, + {0x7149, 0xdf}, + {0x714a, 0xac}, + {0x714b, 0xd1}, + {0x714c, 0x44}, + {0x714d, 0xac}, + {0x714e, 0xb9}, + {0x714f, 0x76}, + {0x7150, 0xb8}, + {0x7151, 0x08}, + {0x7152, 0xb6}, + {0x7153, 0xfe}, + {0x7154, 0xb4}, + {0x7155, 0xca}, + {0x7156, 0xd6}, + {0x7157, 0xd8}, + {0x7158, 0xab}, + {0x7159, 0x00}, + {0x715a, 0xe1}, + {0x715b, 0x36}, + {0x715c, 0x30}, + {0x715d, 0xd3}, + {0x715e, 0xbc}, + {0x715f, 0x29}, + {0x7160, 0xb4}, + {0x7161, 0x1f}, + {0x7162, 0xaa}, + {0x7163, 0xbd}, + {0x7164, 0x01}, + {0x7165, 0xb8}, + {0x7166, 0x0c}, + {0x7167, 0x45}, + {0x7168, 0xa4}, + {0x7169, 0xbd}, + {0x716a, 0x03}, + {0x716b, 0xec}, + {0x716c, 0xbc}, + {0x716d, 0x3d}, + {0x716e, 0xc3}, + {0x716f, 0xcf}, + {0x7170, 0x42}, + {0x7171, 0xb8}, + {0x7172, 0x00}, + {0x7173, 0xe4}, + {0x7174, 0xd5}, + {0x7175, 0x00}, + {0x7176, 0xb6}, + {0x7177, 0x00}, + {0x7178, 0x74}, + {0x7179, 0xbd}, + {0x717a, 0x03}, + {0x717b, 0xb5}, + {0x717c, 0x39}, + {0x717d, 0x40}, + {0x717e, 0x58}, + {0x717f, 0xdd}, + {0x7180, 0x19}, + {0x7181, 0xc1}, + {0x7182, 0xc8}, + {0x7183, 0xbd}, + {0x7184, 0x06}, + {0x7185, 0x17}, + {0x7186, 0xc1}, + {0x7187, 0xc6}, + {0x7188, 0xe8}, + {0x7189, 0x00}, + {0x718a, 0xc0}, + {0x718b, 0xc8}, + {0x718c, 0xe6}, + {0x718d, 0x95}, + {0x718e, 0x15}, + {0x718f, 0x00}, + {0x7190, 0xbc}, + {0x7191, 0x19}, + {0x7192, 0xb9}, + {0x7193, 0xf6}, + {0x7194, 0x14}, + {0x7195, 0xc1}, + {0x7196, 0xd0}, + {0x7197, 0xd1}, + {0x7198, 0xac}, + {0x7199, 0x37}, + {0x719a, 0xbc}, + {0x719b, 0x35}, + {0x719c, 0x36}, + {0x719d, 0x30}, + {0x719e, 0xe1}, + {0x719f, 0xd3}, + {0x71a0, 0x7a}, + {0x71a1, 0xb6}, + {0x71a2, 0x0c}, + {0x71a3, 0xff}, + {0x71a4, 0xb4}, + {0x71a5, 0xc7}, + {0x71a6, 0xd9}, + {0x71a7, 0x00}, + {0x71a8, 0xbd}, + {0x71a9, 0x01}, + {0x71aa, 0x56}, + {0x71ab, 0xc0}, + {0x71ac, 0xda}, + {0x71ad, 0xb4}, + {0x71ae, 0x1f}, + {0x71af, 0x56}, + {0x71b0, 0xaa}, + {0x71b1, 0xbc}, + {0x71b2, 0x08}, + {0x71b3, 0x00}, + {0x71b4, 0x57}, + {0x71b5, 0xe8}, + {0x71b6, 0xb5}, + {0x71b7, 0x36}, + {0x71b8, 0x00}, + {0x71b9, 0x54}, + {0x71ba, 0xe7}, + {0x71bb, 0xc8}, + {0x71bc, 0xb4}, + {0x71bd, 0x1f}, + {0x71be, 0x56}, + {0x71bf, 0xaa}, + {0x71c0, 0xbc}, + {0x71c1, 0x08}, + {0x71c2, 0x57}, + {0x71c3, 0x00}, + {0x71c4, 0xb5}, + {0x71c5, 0x36}, + {0x71c6, 0x00}, + {0x71c7, 0x54}, + {0x71c8, 0xc8}, + {0x71c9, 0xb5}, + {0x71ca, 0x18}, + {0x71cb, 0xd9}, + {0x71cc, 0x00}, + {0x71cd, 0xbd}, + {0x71ce, 0x01}, + {0x71cf, 0x56}, + {0x71d0, 0x08}, + {0x71d1, 0x57}, + {0x71d2, 0xe8}, + {0x71d3, 0xb4}, + {0x71d4, 0x42}, + {0x71d5, 0x00}, + {0x71d6, 0x54}, + {0x71d7, 0xe7}, + {0x71d8, 0xc8}, + {0x71d9, 0xab}, + {0x71da, 0x00}, + {0x71db, 0x66}, + {0x71dc, 0x62}, + {0x71dd, 0x06}, + {0x71de, 0x74}, + {0x71df, 0xb9}, + {0x71e0, 0x05}, + {0x71e1, 0xb7}, + {0x71e2, 0x14}, + {0x71e3, 0x0e}, + {0x71e4, 0xb7}, + {0x71e5, 0x04}, + {0x71e6, 0xc8}, + {0x7600, 0x04}, + {0x7601, 0x80}, + {0x7602, 0x07}, + {0x7603, 0x44}, + {0x7604, 0x05}, + {0x7605, 0x33}, + {0x7606, 0x0f}, + {0x7607, 0x00}, + {0x7608, 0x07}, + {0x7609, 0x40}, + {0x760a, 0x04}, + {0x760b, 0xe5}, + {0x760c, 0x06}, + {0x760d, 0x50}, + {0x760e, 0x04}, + {0x760f, 0xe4}, + {0x7610, 0x00}, + {0x7611, 0x00}, + {0x7612, 0x06}, + {0x7613, 0x5c}, + {0x7614, 0x00}, + {0x7615, 0x0f}, + {0x7616, 0x06}, + {0x7617, 0x1c}, + {0x7618, 0x00}, + {0x7619, 0x02}, + {0x761a, 0x06}, + {0x761b, 0xa2}, + {0x761c, 0x00}, + {0x761d, 0x01}, + {0x761e, 0x06}, + {0x761f, 0xae}, + {0x7620, 0x00}, + {0x7621, 0x0e}, + {0x7622, 0x05}, + {0x7623, 0x30}, + {0x7624, 0x07}, + {0x7625, 0x00}, + {0x7626, 0x0f}, + {0x7627, 0x00}, + {0x7628, 0x04}, + {0x7629, 0xe5}, + {0x762a, 0x05}, + {0x762b, 0x33}, + {0x762c, 0x06}, + {0x762d, 0x12}, + {0x762e, 0x00}, + {0x762f, 0x01}, + {0x7630, 0x06}, + {0x7631, 0x52}, + {0x7632, 0x00}, + {0x7633, 0x01}, + {0x7634, 0x06}, + {0x7635, 0x5e}, + {0x7636, 0x04}, + {0x7637, 0xe4}, + {0x7638, 0x00}, + {0x7639, 0x01}, + {0x763a, 0x05}, + {0x763b, 0x30}, + {0x763c, 0x0f}, + {0x763d, 0x00}, + {0x763e, 0x06}, + {0x763f, 0xa6}, + {0x7640, 0x00}, + {0x7641, 0x02}, + {0x7642, 0x06}, + {0x7643, 0x26}, + {0x7644, 0x00}, + {0x7645, 0x02}, + {0x7646, 0x05}, + {0x7647, 0x33}, + {0x7648, 0x06}, + {0x7649, 0x20}, + {0x764a, 0x0f}, + {0x764b, 0x00}, + {0x764c, 0x06}, + {0x764d, 0x56}, + {0x764e, 0x00}, + {0x764f, 0x02}, + {0x7650, 0x06}, + {0x7651, 0x16}, + {0x7652, 0x05}, + {0x7653, 0x33}, + {0x7654, 0x06}, + {0x7655, 0x10}, + {0x7656, 0x0f}, + {0x7657, 0x00}, + {0x7658, 0x06}, + {0x7659, 0x10}, + {0x765a, 0x0f}, + {0x765b, 0x00}, + {0x765c, 0x06}, + {0x765d, 0x20}, + {0x765e, 0x0f}, + {0x765f, 0x00}, + {0x7660, 0x00}, + {0x7661, 0x00}, + {0x7662, 0x00}, + {0x7663, 0x02}, + {0x7664, 0x04}, + {0x7665, 0xe5}, + {0x7666, 0x04}, + {0x7667, 0xe4}, + {0x7668, 0x0f}, + {0x7669, 0x00}, + {0x766a, 0x00}, + {0x766b, 0x00}, + {0x766c, 0x00}, + {0x766d, 0x01}, + {0x766e, 0x04}, + {0x766f, 0xe5}, + {0x7670, 0x04}, + {0x7671, 0xe4}, + {0x7672, 0x0f}, + {0x7673, 0x00}, + {0x7674, 0x00}, + {0x7675, 0x02}, + {0x7676, 0x04}, + {0x7677, 0xe4}, + {0x7678, 0x00}, + {0x7679, 0x02}, + {0x767a, 0x04}, + {0x767b, 0xc4}, + {0x767c, 0x00}, + {0x767d, 0x02}, + {0x767e, 0x04}, + {0x767f, 0xc4}, + {0x7680, 0x05}, + {0x7681, 0x83}, + {0x7682, 0x0f}, + {0x7683, 0x00}, + {0x7684, 0x00}, + {0x7685, 0x02}, + {0x7686, 0x04}, + {0x7687, 0xe4}, + {0x7688, 0x00}, + {0x7689, 0x02}, + {0x768a, 0x04}, + {0x768b, 0xc4}, + {0x768c, 0x00}, + {0x768d, 0x02}, + {0x768e, 0x04}, + {0x768f, 0xc4}, + {0x7690, 0x05}, + {0x7691, 0x83}, + {0x7692, 0x03}, + {0x7693, 0x0b}, + {0x7694, 0x05}, + {0x7695, 0x83}, + {0x7696, 0x00}, + {0x7697, 0x07}, + {0x7698, 0x05}, + {0x7699, 0x03}, + {0x769a, 0x00}, + {0x769b, 0x05}, + {0x769c, 0x05}, + {0x769d, 0x32}, + {0x769e, 0x05}, + {0x769f, 0x30}, + {0x76a0, 0x00}, + {0x76a1, 0x02}, + {0x76a2, 0x05}, + {0x76a3, 0x78}, + {0x76a4, 0x00}, + {0x76a5, 0x01}, + {0x76a6, 0x05}, + {0x76a7, 0x7c}, + {0x76a8, 0x03}, + {0x76a9, 0x9a}, + {0x76aa, 0x05}, + {0x76ab, 0x83}, + {0x76ac, 0x00}, + {0x76ad, 0x04}, + {0x76ae, 0x05}, + {0x76af, 0x03}, + {0x76b0, 0x00}, + {0x76b1, 0x03}, + {0x76b2, 0x05}, + {0x76b3, 0x32}, + {0x76b4, 0x05}, + {0x76b5, 0x30}, + {0x76b6, 0x00}, + {0x76b7, 0x02}, + {0x76b8, 0x05}, + {0x76b9, 0x78}, + {0x76ba, 0x00}, + {0x76bb, 0x01}, + {0x76bc, 0x05}, + {0x76bd, 0x7c}, + {0x76be, 0x03}, + {0x76bf, 0x99}, + {0x76c0, 0x05}, + {0x76c1, 0x83}, + {0x76c2, 0x00}, + {0x76c3, 0x03}, + {0x76c4, 0x05}, + {0x76c5, 0x03}, + {0x76c6, 0x00}, + {0x76c7, 0x01}, + {0x76c8, 0x05}, + {0x76c9, 0x32}, + {0x76ca, 0x05}, + {0x76cb, 0x30}, + {0x76cc, 0x00}, + {0x76cd, 0x02}, + {0x76ce, 0x05}, + {0x76cf, 0x78}, + {0x76d0, 0x00}, + {0x76d1, 0x01}, + {0x76d2, 0x05}, + {0x76d3, 0x7c}, + {0x76d4, 0x03}, + {0x76d5, 0x98}, + {0x76d6, 0x05}, + {0x76d7, 0x83}, + {0x76d8, 0x00}, + {0x76d9, 0x00}, + {0x76da, 0x05}, + {0x76db, 0x03}, + {0x76dc, 0x00}, + {0x76dd, 0x01}, + {0x76de, 0x05}, + {0x76df, 0x32}, + {0x76e0, 0x05}, + {0x76e1, 0x30}, + {0x76e2, 0x00}, + {0x76e3, 0x02}, + {0x76e4, 0x05}, + {0x76e5, 0x78}, + {0x76e6, 0x00}, + {0x76e7, 0x01}, + {0x76e8, 0x05}, + {0x76e9, 0x7c}, + {0x76ea, 0x03}, + {0x76eb, 0x97}, + {0x76ec, 0x05}, + {0x76ed, 0x83}, + {0x76ee, 0x00}, + {0x76ef, 0x00}, + {0x76f0, 0x05}, + {0x76f1, 0x03}, + {0x76f2, 0x05}, + {0x76f3, 0x32}, + {0x76f4, 0x05}, + {0x76f5, 0x30}, + {0x76f6, 0x00}, + {0x76f7, 0x02}, + {0x76f8, 0x05}, + {0x76f9, 0x78}, + {0x76fa, 0x00}, + {0x76fb, 0x01}, + {0x76fc, 0x05}, + {0x76fd, 0x7c}, + {0x76fe, 0x03}, + {0x76ff, 0x96}, + {0x7700, 0x05}, + {0x7701, 0x83}, + {0x7702, 0x05}, + {0x7703, 0x03}, + {0x7704, 0x05}, + {0x7705, 0x32}, + {0x7706, 0x05}, + {0x7707, 0x30}, + {0x7708, 0x00}, + {0x7709, 0x02}, + {0x770a, 0x05}, + {0x770b, 0x78}, + {0x770c, 0x00}, + {0x770d, 0x01}, + {0x770e, 0x05}, + {0x770f, 0x7c}, + {0x7710, 0x03}, + {0x7711, 0x95}, + {0x7712, 0x05}, + {0x7713, 0x83}, + {0x7714, 0x05}, + {0x7715, 0x03}, + {0x7716, 0x05}, + {0x7717, 0x32}, + {0x7718, 0x05}, + {0x7719, 0x30}, + {0x771a, 0x00}, + {0x771b, 0x02}, + {0x771c, 0x05}, + {0x771d, 0x78}, + {0x771e, 0x00}, + {0x771f, 0x01}, + {0x7720, 0x05}, + {0x7721, 0x7c}, + {0x7722, 0x03}, + {0x7723, 0x94}, + {0x7724, 0x05}, + {0x7725, 0x83}, + {0x7726, 0x00}, + {0x7727, 0x01}, + {0x7728, 0x05}, + {0x7729, 0x03}, + {0x772a, 0x00}, + {0x772b, 0x01}, + {0x772c, 0x05}, + {0x772d, 0x32}, + {0x772e, 0x05}, + {0x772f, 0x30}, + {0x7730, 0x00}, + {0x7731, 0x02}, + {0x7732, 0x05}, + {0x7733, 0x78}, + {0x7734, 0x00}, + {0x7735, 0x01}, + {0x7736, 0x05}, + {0x7737, 0x7c}, + {0x7738, 0x03}, + {0x7739, 0x93}, + {0x773a, 0x05}, + {0x773b, 0x83}, + {0x773c, 0x00}, + {0x773d, 0x00}, + {0x773e, 0x05}, + {0x773f, 0x03}, + {0x7740, 0x00}, + {0x7741, 0x00}, + {0x7742, 0x05}, + {0x7743, 0x32}, + {0x7744, 0x05}, + {0x7745, 0x30}, + {0x7746, 0x00}, + {0x7747, 0x02}, + {0x7748, 0x05}, + {0x7749, 0x78}, + {0x774a, 0x00}, + {0x774b, 0x01}, + {0x774c, 0x05}, + {0x774d, 0x7c}, + {0x774e, 0x03}, + {0x774f, 0x92}, + {0x7750, 0x05}, + {0x7751, 0x83}, + {0x7752, 0x05}, + {0x7753, 0x03}, + {0x7754, 0x00}, + {0x7755, 0x00}, + {0x7756, 0x05}, + {0x7757, 0x32}, + {0x7758, 0x05}, + {0x7759, 0x30}, + {0x775a, 0x00}, + {0x775b, 0x02}, + {0x775c, 0x05}, + {0x775d, 0x78}, + {0x775e, 0x00}, + {0x775f, 0x01}, + {0x7760, 0x05}, + {0x7761, 0x7c}, + {0x7762, 0x03}, + {0x7763, 0x91}, + {0x7764, 0x05}, + {0x7765, 0x83}, + {0x7766, 0x05}, + {0x7767, 0x03}, + {0x7768, 0x05}, + {0x7769, 0x32}, + {0x776a, 0x05}, + {0x776b, 0x30}, + {0x776c, 0x00}, + {0x776d, 0x02}, + {0x776e, 0x05}, + {0x776f, 0x78}, + {0x7770, 0x00}, + {0x7771, 0x01}, + {0x7772, 0x05}, + {0x7773, 0x7c}, + {0x7774, 0x03}, + {0x7775, 0x90}, + {0x7776, 0x05}, + {0x7777, 0x83}, + {0x7778, 0x05}, + {0x7779, 0x03}, + {0x777a, 0x05}, + {0x777b, 0x32}, + {0x777c, 0x05}, + {0x777d, 0x30}, + {0x777e, 0x00}, + {0x777f, 0x02}, + {0x7780, 0x05}, + {0x7781, 0x78}, + {0x7782, 0x00}, + {0x7783, 0x01}, + {0x7784, 0x05}, + {0x7785, 0x7c}, + {0x7786, 0x02}, + {0x7787, 0x90}, + {0x7788, 0x05}, + {0x7789, 0x03}, + {0x778a, 0x07}, + {0x778b, 0x00}, + {0x778c, 0x0f}, + {0x778d, 0x00}, + {0x778e, 0x08}, + {0x778f, 0x30}, + {0x7790, 0x08}, + {0x7791, 0xee}, + {0x7792, 0x0f}, + {0x7793, 0x00}, + {0x7794, 0x05}, + {0x7795, 0x33}, + {0x7796, 0x04}, + {0x7797, 0xe5}, + {0x7798, 0x06}, + {0x7799, 0x52}, + {0x779a, 0x04}, + {0x779b, 0xe4}, + {0x779c, 0x00}, + {0x779d, 0x00}, + {0x779e, 0x06}, + {0x779f, 0x5e}, + {0x77a0, 0x00}, + {0x77a1, 0x0f}, + {0x77a2, 0x06}, + {0x77a3, 0x1e}, + {0x77a4, 0x00}, + {0x77a5, 0x02}, + {0x77a6, 0x06}, + {0x77a7, 0xa2}, + {0x77a8, 0x00}, + {0x77a9, 0x01}, + {0x77aa, 0x06}, + {0x77ab, 0xae}, + {0x77ac, 0x00}, + {0x77ad, 0x03}, + {0x77ae, 0x05}, + {0x77af, 0x30}, + {0x77b0, 0x09}, + {0x77b1, 0x19}, + {0x77b2, 0x0f}, + {0x77b3, 0x00}, + {0x77b4, 0x05}, + {0x77b5, 0x33}, + {0x77b6, 0x04}, + {0x77b7, 0xe5}, + {0x77b8, 0x06}, + {0x77b9, 0x52}, + {0x77ba, 0x04}, + {0x77bb, 0xe4}, + {0x77bc, 0x00}, + {0x77bd, 0x00}, + {0x77be, 0x06}, + {0x77bf, 0x5e}, + {0x77c0, 0x00}, + {0x77c1, 0x0f}, + {0x77c2, 0x06}, + {0x77c3, 0x1e}, + {0x77c4, 0x00}, + {0x77c5, 0x02}, + {0x77c6, 0x06}, + {0x77c7, 0xa2}, + {0x77c8, 0x00}, + {0x77c9, 0x01}, + {0x77ca, 0x06}, + {0x77cb, 0xae}, + {0x77cc, 0x00}, + {0x77cd, 0x03}, + {0x77ce, 0x05}, + {0x77cf, 0x30}, + {0x77d0, 0x0f}, + {0x77d1, 0x00}, + {0x77d2, 0x00}, + {0x77d3, 0x00}, + {0x77d4, 0x00}, + {0x77d5, 0x02}, + {0x77d6, 0x04}, + {0x77d7, 0xe5}, + {0x77d8, 0x04}, + {0x77d9, 0xe4}, + {0x77da, 0x05}, + {0x77db, 0x33}, + {0x77dc, 0x07}, + {0x77dd, 0x10}, + {0x77de, 0x00}, + {0x77df, 0x00}, + {0x77e0, 0x01}, + {0x77e1, 0xbb}, + {0x77e2, 0x00}, + {0x77e3, 0x00}, + {0x77e4, 0x01}, + {0x77e5, 0xaa}, + {0x77e6, 0x00}, + {0x77e7, 0x00}, + {0x77e8, 0x01}, + {0x77e9, 0x99}, + {0x77ea, 0x00}, + {0x77eb, 0x00}, + {0x77ec, 0x01}, + {0x77ed, 0x88}, + {0x77ee, 0x00}, + {0x77ef, 0x00}, + {0x77f0, 0x01}, + {0x77f1, 0x77}, + {0x77f2, 0x00}, + {0x77f3, 0x00}, + {0x77f4, 0x01}, + {0x77f5, 0x66}, + {0x77f6, 0x00}, + {0x77f7, 0x00}, + {0x77f8, 0x01}, + {0x77f9, 0x55}, + {0x77fa, 0x00}, + {0x77fb, 0x00}, + {0x77fc, 0x01}, + {0x77fd, 0x44}, + {0x77fe, 0x00}, + {0x77ff, 0x00}, + {0x7800, 0x01}, + {0x7801, 0x33}, + {0x7802, 0x00}, + {0x7803, 0x00}, + {0x7804, 0x01}, + {0x7805, 0x22}, + {0x7806, 0x00}, + {0x7807, 0x00}, + {0x7808, 0x01}, + {0x7809, 0x11}, + {0x780a, 0x00}, + {0x780b, 0x00}, + {0x780c, 0x01}, + {0x780d, 0x00}, + {0x780e, 0x01}, + {0x780f, 0xff}, + {0x7810, 0x07}, + {0x7811, 0x00}, + {0x7812, 0x02}, + {0x7813, 0xa0}, + {0x7814, 0x0f}, + {0x7815, 0x00}, + {0x7816, 0x08}, + {0x7817, 0x35}, + {0x7818, 0x06}, + {0x7819, 0x52}, + {0x781a, 0x04}, + {0x781b, 0xe4}, + {0x781c, 0x00}, + {0x781d, 0x00}, + {0x781e, 0x06}, + {0x781f, 0x5e}, + {0x7820, 0x05}, + {0x7821, 0x33}, + {0x7822, 0x09}, + {0x7823, 0x19}, + {0x7824, 0x06}, + {0x7825, 0x1e}, + {0x7826, 0x05}, + {0x7827, 0x33}, + {0x7828, 0x00}, + {0x7829, 0x01}, + {0x782a, 0x06}, + {0x782b, 0x24}, + {0x782c, 0x06}, + {0x782d, 0x20}, + {0x782e, 0x0f}, + {0x782f, 0x00}, + {0x7830, 0x08}, + {0x7831, 0x35}, + {0x7832, 0x07}, + {0x7833, 0x10}, + {0x7834, 0x00}, + {0x7835, 0x00}, + {0x7836, 0x01}, + {0x7837, 0xbb}, + {0x7838, 0x00}, + {0x7839, 0x00}, + {0x783a, 0x01}, + {0x783b, 0xaa}, + {0x783c, 0x00}, + {0x783d, 0x00}, + {0x783e, 0x01}, + {0x783f, 0x99}, + {0x7840, 0x00}, + {0x7841, 0x00}, + {0x7842, 0x01}, + {0x7843, 0x88}, + {0x7844, 0x00}, + {0x7845, 0x00}, + {0x7846, 0x01}, + {0x7847, 0x77}, + {0x7848, 0x00}, + {0x7849, 0x00}, + {0x784a, 0x01}, + {0x784b, 0x66}, + {0x784c, 0x00}, + {0x784d, 0x00}, + {0x784e, 0x01}, + {0x784f, 0x55}, + {0x7850, 0x00}, + {0x7851, 0x00}, + {0x7852, 0x01}, + {0x7853, 0x44}, + {0x7854, 0x00}, + {0x7855, 0x00}, + {0x7856, 0x01}, + {0x7857, 0x33}, + {0x7858, 0x00}, + {0x7859, 0x00}, + {0x785a, 0x01}, + {0x785b, 0x22}, + {0x785c, 0x00}, + {0x785d, 0x00}, + {0x785e, 0x01}, + {0x785f, 0x11}, + {0x7860, 0x00}, + {0x7861, 0x00}, + {0x7862, 0x01}, + {0x7863, 0x00}, + {0x7864, 0x07}, + {0x7865, 0x00}, + {0x7866, 0x01}, + {0x7867, 0xff}, + {0x7868, 0x02}, + {0x7869, 0xa0}, + {0x786a, 0x0f}, + {0x786b, 0x00}, + {0x786c, 0x08}, + {0x786d, 0x3a}, + {0x786e, 0x08}, + {0x786f, 0x6a}, + {0x7870, 0x0f}, + {0x7871, 0x00}, + {0x7872, 0x04}, + {0x7873, 0xc0}, + {0x7874, 0x09}, + {0x7875, 0x19}, + {0x7876, 0x04}, + {0x7877, 0x99}, + {0x7878, 0x07}, + {0x7879, 0x14}, + {0x787a, 0x00}, + {0x787b, 0x01}, + {0x787c, 0x04}, + {0x787d, 0xa4}, + {0x787e, 0x00}, + {0x787f, 0x07}, + {0x7880, 0x04}, + {0x7881, 0xa6}, + {0x7882, 0x00}, + {0x7883, 0x00}, + {0x7884, 0x04}, + {0x7885, 0xa0}, + {0x7886, 0x04}, + {0x7887, 0x80}, + {0x7888, 0x04}, + {0x7889, 0x00}, + {0x788a, 0x05}, + {0x788b, 0x03}, + {0x788c, 0x06}, + {0x788d, 0x00}, + {0x788e, 0x0f}, + {0x788f, 0x00}, + {0x7890, 0x0f}, + {0x7891, 0x00}, + {0x7892, 0x0f}, + {0x7893, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x05}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x88}, + {0x30ae, 0x04}, + {0x30af, 0x40}, + {0x30b0, 0x0d}, + {0x30b1, 0xde}, + {0x30b2, 0x04}, + {0x30b3, 0x66}, + {0x30b6, 0x01}, + {0x30b7, 0x15}, + {0x3196, 0x00}, + {0x3197, 0x0a}, + {0x3195, 0x29}, + {0x315a, 0x02}, + {0x315b, 0x00}, + {0x30bb, 0x40}, + {0x3250, 0xf7}, + {0x30a8, 0x00}, + {0x30a9, 0x04}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x80}, + {0x30ae, 0x04}, + {0x30af, 0x38}, + {0x3012, 0x01}, +}; + +struct vvcam_sccb_array ov2775_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(ov2775_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = ov2775_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_reg_cfg.h b/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_reg_cfg.h new file mode 100755 index 0000000..9f76577 --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_ov2775/ov2775_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OV2775_REG_CFG_H_ +#define _OV2775_REG_CFG_H_ + +extern struct vvcam_sccb_array ov2775_mipi4lane_1080p_30fps_linear_arry; + +#endif \ No newline at end of file diff --git a/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_driver.c b/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_driver.c new file mode 100755 index 0000000..80cbd39 --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_driver.c @@ -0,0 +1,442 @@ +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "ov5693_reg_cfg.h" + +#define SENSOR_CLK 51000000 + +static struct vvcam_mode_info pov5693_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_array *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pov5693_mode_info); + + memcpy(pmode_info_arry->modes,pov5693_mode_info,sizeof(pov5693_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} + +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pov5693_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pov5693_mode_info[i].index == pmode->index) + { + psensor_mode = &(pov5693_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&ov5693_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&ov5693_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x100, 0x01); + }else + { + ret = sensor_write_reg(ctx, 0x100, 0x0); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s ov5693_function = +{ + .sensor_name = "ov5693", + .reserve_id = 0x5600, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_driver.h b/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_driver.h new file mode 100755 index 0000000..f8e5acd --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_driver.h @@ -0,0 +1,7 @@ +#ifndef _OMNIVISION_OV5693_H_ +#define _OMNIVISION_OV5693_H_ + +extern struct vvcam_sensor_function_s ov5693_function; + + +#endif diff --git a/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.c b/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..a9261be --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,1827 @@ +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data ov5693_mipi4lane_1080p_30fps_linear_reg[] = { + {0x3000, 0x02}, + {0x3001, 0x28}, + {0x3002, 0x03}, + {0x3003, 0x01}, + {0x3004, 0x05}, + {0x3005, 0x26}, + {0x3006, 0x00}, + {0x3007, 0x07}, + {0x3008, 0x01}, + {0x3009, 0x00}, + {0x300c, 0x6c}, + {0x300e, 0x80}, + {0x300f, 0x00}, + {0x3012, 0x00}, + {0x3013, 0x00}, + {0x3014, 0xc4}, + {0x3015, 0x00}, + {0x3017, 0x00}, + {0x3018, 0x00}, + {0x3019, 0x00}, + {0x301a, 0x00}, + {0x301b, 0x0e}, + {0x301e, 0x17}, + {0x301f, 0xe1}, + {0x3030, 0x02}, + {0x3031, 0x62}, + {0x3032, 0xf0}, + {0x3033, 0x30}, + {0x3034, 0x3f}, + {0x3035, 0x5f}, + {0x3036, 0x02}, + {0x3037, 0x9f}, + {0x3038, 0x04}, + {0x3039, 0xb7}, + {0x303a, 0x04}, + {0x303b, 0x07}, + {0x303c, 0xf0}, + {0x303d, 0x00}, + {0x303e, 0x0b}, + {0x303f, 0xe3}, + {0x3040, 0xf3}, + {0x3041, 0x29}, + {0x3042, 0xf6}, + {0x3043, 0x65}, + {0x3044, 0x06}, + {0x3045, 0x0f}, + {0x3046, 0x59}, + {0x3047, 0x07}, + {0x3048, 0x82}, + {0x3049, 0xcf}, + {0x304a, 0x12}, + {0x304b, 0x40}, + {0x304c, 0x33}, + {0x304d, 0xa4}, + {0x304e, 0x0b}, + {0x304f, 0x3d}, + {0x3050, 0x10}, + {0x3060, 0x00}, + {0x3061, 0x64}, + {0x3062, 0x00}, + {0x3063, 0xe4}, + {0x3066, 0x80}, + {0x3080, 0x00}, + {0x3081, 0x00}, + {0x3082, 0x01}, + {0x3083, 0xe3}, + {0x3084, 0x06}, + {0x3085, 0x00}, + {0x3086, 0x10}, + {0x3087, 0x10}, + {0x3089, 0x00}, + {0x308a, 0x01}, + {0x3093, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x00}, + {0x30aa, 0x00}, + {0x30ab, 0x00}, + {0x30ac, 0x07}, + {0x30ad, 0x90}, + {0x30ae, 0x04}, + {0x30af, 0x48}, + {0x30b0, 0x04}, + {0x30b1, 0x7e}, + {0x30b2, 0x04}, + {0x30b3, 0x65}, + {0x30b4, 0x00}, + {0x30b5, 0x00}, + {0x30b6, 0x00}, + {0x30b7, 0x10}, + {0x30b8, 0x00}, + {0x30b9, 0x02}, + {0x30ba, 0x10}, + {0x30bb, 0x00}, + {0x30bc, 0x00}, + {0x30bd, 0x03}, + {0x30be, 0x5c}, + {0x30bf, 0x00}, + {0x30c0, 0x05}, + {0x30c1, 0x00}, + {0x30c2, 0x20}, + {0x30c3, 0x00}, + {0x30c4, 0x4a}, + {0x30c5, 0x00}, + {0x30c7, 0x00}, + {0x30c8, 0x00}, + {0x30d1, 0x00}, + {0x30d2, 0x00}, + {0x30d3, 0x80}, + {0x30d4, 0x00}, + {0x30d9, 0x09}, + {0x30da, 0x64}, + {0x30dd, 0x00}, + {0x30de, 0x16}, + {0x30df, 0x00}, + {0x30e0, 0x17}, + {0x30e1, 0x00}, + {0x30e2, 0x18}, + {0x30e3, 0x10}, + {0x30e4, 0x04}, + {0x30e5, 0x00}, + {0x30e6, 0x00}, + {0x30e7, 0x00}, + {0x30e8, 0x00}, + {0x30e9, 0x00}, + {0x30ea, 0x00}, + {0x30eb, 0x00}, + {0x30ec, 0x00}, + {0x30ed, 0x00}, + {0x3101, 0x00}, + {0x3102, 0x00}, + {0x3103, 0x00}, + {0x3104, 0x00}, + {0x3105, 0x8c}, + {0x3106, 0x87}, + {0x3107, 0xc0}, + {0x3108, 0x9d}, + {0x3109, 0x8d}, + {0x310a, 0x8d}, + {0x310b, 0x6a}, + {0x310c, 0x3a}, + {0x310d, 0x5a}, + {0x310e, 0x00}, + {0x3120, 0x00}, + {0x3121, 0x00}, + {0x3122, 0x00}, + {0x3123, 0xf0}, + {0x3124, 0x00}, + {0x3125, 0x70}, + {0x3126, 0x1f}, + {0x3127, 0x0f}, + {0x3128, 0x00}, + {0x3129, 0x3a}, + {0x312a, 0x02}, + {0x312b, 0x0f}, + {0x312c, 0x00}, + {0x312d, 0x0f}, + {0x312e, 0x1d}, + {0x312f, 0x00}, + {0x3130, 0x00}, + {0x3131, 0x00}, + {0x3132, 0x00}, + {0x3140, 0x0a}, + {0x3141, 0x03}, + {0x3142, 0x00}, + {0x3143, 0x00}, + {0x3144, 0x00}, + {0x3145, 0x00}, + {0x3146, 0x00}, + {0x3147, 0x00}, + {0x3148, 0x00}, + {0x3149, 0x00}, + {0x314a, 0x00}, + {0x314b, 0x00}, + {0x314c, 0x00}, + {0x314d, 0x00}, + {0x314e, 0x1c}, + {0x314f, 0xff}, + {0x3150, 0xff}, + {0x3151, 0xff}, + {0x3152, 0x10}, + {0x3153, 0x10}, + {0x3154, 0x10}, + {0x3155, 0x00}, + {0x3156, 0x03}, + {0x3157, 0x00}, + {0x3158, 0x0f}, + {0x3159, 0xff}, + {0x315a, 0x01}, + {0x315b, 0x00}, + {0x315c, 0x01}, + {0x315d, 0x00}, + {0x315e, 0x01}, + {0x315f, 0x00}, + {0x3160, 0x00}, + {0x3161, 0x40}, + {0x3162, 0x00}, + {0x3163, 0x40}, + {0x3164, 0x00}, + {0x3165, 0x40}, + {0x3190, 0x08}, + {0x3191, 0x99}, + {0x3193, 0x08}, + {0x3194, 0x13}, + {0x3195, 0x33}, + {0x3196, 0x00}, + {0x3197, 0x10}, + {0x3198, 0x00}, + {0x3199, 0x7f}, + {0x319a, 0x80}, + {0x319b, 0xff}, + {0x319c, 0x80}, + {0x319d, 0xbf}, + {0x319e, 0xc0}, + {0x319f, 0xff}, + {0x31a0, 0x24}, + {0x31a1, 0x55}, + {0x31a2, 0x00}, + {0x31a3, 0x00}, + {0x31a6, 0x00}, + {0x31a7, 0x00}, + {0x31b0, 0x00}, + {0x31b1, 0x00}, + {0x31b2, 0x02}, + {0x31b3, 0x00}, + {0x31b4, 0x00}, + {0x31b5, 0x01}, + {0x31b6, 0x00}, + {0x31b7, 0x00}, + {0x31b8, 0x00}, + {0x31b9, 0x00}, + {0x31ba, 0x00}, + {0x31d0, 0x3c}, + {0x31d1, 0x34}, + {0x31d2, 0x3c}, + {0x31d3, 0x00}, + {0x31d4, 0x2d}, + {0x31d5, 0x00}, + {0x31d6, 0x01}, + {0x31d7, 0x06}, + {0x31d8, 0x00}, + {0x31d9, 0x64}, + {0x31da, 0x00}, + {0x31db, 0x30}, + {0x31dc, 0x04}, + {0x31dd, 0x69}, + {0x31de, 0x0a}, + {0x31df, 0x3c}, + {0x31e0, 0x04}, + {0x31e1, 0x32}, + {0x31e2, 0x00}, + {0x31e3, 0x00}, + {0x31e4, 0x08}, + {0x31e5, 0x80}, + {0x31e6, 0x00}, + {0x31e7, 0x2c}, + {0x31e8, 0x6c}, + {0x31e9, 0xac}, + {0x31ea, 0xec}, + {0x31eb, 0x3f}, + {0x31ec, 0x0f}, + {0x31ed, 0x20}, + {0x31ee, 0x04}, + {0x31ef, 0x48}, + {0x31f0, 0x07}, + {0x31f1, 0x90}, + {0x31f2, 0x04}, + {0x31f3, 0x48}, + {0x31f4, 0x07}, + {0x31f5, 0x90}, + {0x31f6, 0x04}, + {0x31f7, 0x48}, + {0x31f8, 0x07}, + {0x31f9, 0x90}, + {0x31fa, 0x04}, + {0x31fb, 0x48}, + {0x31fd, 0xcb}, + {0x31fe, 0x0f}, + {0x31ff, 0x03}, + {0x3200, 0x00}, + {0x3201, 0xff}, + {0x3202, 0x00}, + {0x3203, 0xff}, + {0x3204, 0xff}, + {0x3205, 0xff}, + {0x3206, 0xff}, + {0x3207, 0xff}, + {0x3208, 0xff}, + {0x3209, 0xff}, + {0x320a, 0xff}, + {0x320b, 0x1b}, + {0x320c, 0x1f}, + {0x320d, 0x1e}, + {0x320e, 0x30}, + {0x320f, 0x2d}, + {0x3210, 0x2c}, + {0x3211, 0x2b}, + {0x3212, 0x2a}, + {0x3213, 0x24}, + {0x3214, 0x22}, + {0x3215, 0x00}, + {0x3216, 0x04}, + {0x3217, 0x2c}, + {0x3218, 0x6c}, + {0x3219, 0xac}, + {0x321a, 0xec}, + {0x321b, 0x00}, + {0x3230, 0x3a}, + {0x3231, 0x00}, + {0x3232, 0x80}, + {0x3233, 0x00}, + {0x3234, 0x10}, + {0x3235, 0xaa}, + {0x3236, 0x55}, + {0x3237, 0x99}, + {0x3238, 0x66}, + {0x3239, 0x08}, + {0x323a, 0x88}, + {0x323b, 0x00}, + {0x323c, 0x00}, + {0x323d, 0x03}, + {0x3250, 0x33}, + {0x3251, 0x00}, + {0x3252, 0x20}, + {0x3253, 0x00}, + {0x3254, 0x00}, + {0x3255, 0x01}, + {0x3256, 0x00}, + {0x3257, 0x00}, + {0x3258, 0x00}, + {0x3270, 0x01}, + {0x3271, 0x60}, + {0x3272, 0xc0}, + {0x3273, 0x00}, + {0x3274, 0x80}, + {0x3275, 0x40}, + {0x3276, 0x02}, + {0x3277, 0x08}, + {0x3278, 0x10}, + {0x3279, 0x04}, + {0x327a, 0x00}, + {0x327b, 0x03}, + {0x327c, 0x10}, + {0x327d, 0x60}, + {0x327e, 0xc0}, + {0x327f, 0x06}, + {0x3288, 0x10}, + {0x3289, 0x00}, + {0x328a, 0x08}, + {0x328b, 0x00}, + {0x328c, 0x04}, + {0x328d, 0x00}, + {0x328e, 0x02}, + {0x328f, 0x00}, + {0x3290, 0x20}, + {0x3291, 0x00}, + {0x3292, 0x10}, + {0x3293, 0x00}, + {0x3294, 0x08}, + {0x3295, 0x00}, + {0x3296, 0x04}, + {0x3297, 0x00}, + {0x3298, 0x40}, + {0x3299, 0x00}, + {0x329a, 0x20}, + {0x329b, 0x00}, + {0x329c, 0x10}, + {0x329d, 0x00}, + {0x329e, 0x08}, + {0x329f, 0x00}, + {0x32a0, 0x7f}, + {0x32a1, 0xff}, + {0x32a2, 0x40}, + {0x32a3, 0x00}, + {0x32a4, 0x20}, + {0x32a5, 0x00}, + {0x32a6, 0x10}, + {0x32a7, 0x00}, + {0x32a8, 0x00}, + {0x32a9, 0x00}, + {0x32aa, 0x00}, + {0x32ab, 0x00}, + {0x32ac, 0x00}, + {0x32ad, 0x00}, + {0x32ae, 0x00}, + {0x32af, 0x00}, + {0x32b0, 0x00}, + {0x32b1, 0x00}, + {0x32b2, 0x00}, + {0x32b3, 0x00}, + {0x32b4, 0x00}, + {0x32b5, 0x00}, + {0x32b6, 0x00}, + {0x32b7, 0x00}, + {0x32b8, 0x00}, + {0x32b9, 0x00}, + {0x32ba, 0x00}, + {0x32bb, 0x00}, + {0x32bc, 0x00}, + {0x32bd, 0x00}, + {0x32be, 0x00}, + {0x32bf, 0x00}, + {0x32c0, 0x00}, + {0x32c1, 0x00}, + {0x32c2, 0x00}, + {0x32c3, 0x00}, + {0x32c4, 0x00}, + {0x32c5, 0x00}, + {0x32c6, 0x00}, + {0x32c7, 0x00}, + {0x32c8, 0x87}, + {0x32c9, 0x00}, + {0x3330, 0x03}, + {0x3331, 0xc8}, + {0x3332, 0x02}, + {0x3333, 0x24}, + {0x3334, 0x00}, + {0x3335, 0x00}, + {0x3336, 0x00}, + {0x3337, 0x00}, + {0x3338, 0x03}, + {0x3339, 0xc8}, + {0x333a, 0x02}, + {0x333b, 0x24}, + {0x333c, 0x00}, + {0x333d, 0x00}, + {0x333e, 0x00}, + {0x333f, 0x00}, + {0x3340, 0x03}, + {0x3341, 0xc8}, + {0x3342, 0x02}, + {0x3343, 0x24}, + {0x3344, 0x00}, + {0x3345, 0x00}, + {0x3346, 0x00}, + {0x3347, 0x00}, + {0x3348, 0x40}, + {0x3349, 0x00}, + {0x334a, 0x00}, + {0x334b, 0x00}, + {0x334c, 0x00}, + {0x334d, 0x00}, + {0x334e, 0x80}, + {0x3360, 0x01}, + {0x3361, 0x00}, + {0x3362, 0x01}, + {0x3363, 0x00}, + {0x3364, 0x01}, + {0x3365, 0x00}, + {0x3366, 0x01}, + {0x3367, 0x00}, + {0x3368, 0x01}, + {0x3369, 0x00}, + {0x336a, 0x01}, + {0x336b, 0x00}, + {0x336c, 0x01}, + {0x336d, 0x00}, + {0x336e, 0x01}, + {0x336f, 0x00}, + {0x3370, 0x01}, + {0x3371, 0x00}, + {0x3372, 0x01}, + {0x3373, 0x00}, + {0x3374, 0x01}, + {0x3375, 0x00}, + {0x3376, 0x01}, + {0x3377, 0x00}, + {0x3378, 0x00}, + {0x3379, 0x00}, + {0x337a, 0x00}, + {0x337b, 0x00}, + {0x337c, 0x00}, + {0x337d, 0x00}, + {0x337e, 0x00}, + {0x337f, 0x00}, + {0x3380, 0x00}, + {0x3381, 0x00}, + {0x3382, 0x00}, + {0x3383, 0x00}, + {0x3384, 0x00}, + {0x3385, 0x00}, + {0x3386, 0x00}, + {0x3387, 0x00}, + {0x3388, 0x00}, + {0x3389, 0x00}, + {0x338a, 0x00}, + {0x338b, 0x00}, + {0x338c, 0x00}, + {0x338d, 0x00}, + {0x338e, 0x00}, + {0x338f, 0x00}, + {0x3390, 0x00}, + {0x3391, 0x00}, + {0x3392, 0x00}, + {0x3393, 0x00}, + {0x3394, 0x00}, + {0x3395, 0x00}, + {0x3396, 0x00}, + {0x3397, 0x00}, + {0x3398, 0x00}, + {0x3399, 0x00}, + {0x339a, 0x00}, + {0x339b, 0x00}, + {0x33b0, 0x00}, + {0x33b1, 0x50}, + {0x33b2, 0x01}, + {0x33b3, 0xff}, + {0x33b4, 0xe0}, + {0x33b5, 0x6b}, + {0x33b6, 0x00}, + {0x33b7, 0x00}, + {0x33b8, 0x00}, + {0x33b9, 0x00}, + {0x33ba, 0x00}, + {0x33bb, 0x1f}, + {0x33bc, 0x01}, + {0x33bd, 0x01}, + {0x33be, 0x01}, + {0x33bf, 0x01}, + {0x33c0, 0x00}, + {0x33c1, 0x00}, + {0x33c2, 0x00}, + {0x33c3, 0x00}, + {0x33e0, 0x14}, + {0x33e1, 0x0f}, + {0x33e2, 0x02}, + {0x33e3, 0x01}, + {0x33e4, 0x01}, + {0x33e5, 0x01}, + {0x33e6, 0x00}, + {0x33e7, 0x04}, + {0x33e8, 0x0c}, + {0x33e9, 0x02}, + {0x33ea, 0x02}, + {0x33eb, 0x02}, + {0x33ec, 0x03}, + {0x33ed, 0x01}, + {0x33ee, 0x02}, + {0x33ef, 0x08}, + {0x33f0, 0x08}, + {0x33f1, 0x04}, + {0x33f2, 0x04}, + {0x33f3, 0x00}, + {0x33f4, 0x03}, + {0x33f5, 0x14}, + {0x33f6, 0x0f}, + {0x33f7, 0x02}, + {0x33f8, 0x01}, + {0x33f9, 0x01}, + {0x33fa, 0x01}, + {0x33fb, 0x00}, + {0x33fc, 0x04}, + {0x33fd, 0x0c}, + {0x33fe, 0x02}, + {0x33ff, 0x02}, + {0x3400, 0x02}, + {0x3401, 0x03}, + {0x3402, 0x01}, + {0x3403, 0x02}, + {0x3404, 0x08}, + {0x3405, 0x08}, + {0x3406, 0x04}, + {0x3407, 0x04}, + {0x3408, 0x00}, + {0x3409, 0x03}, + {0x340a, 0x14}, + {0x340b, 0x0f}, + {0x340c, 0x04}, + {0x340d, 0x02}, + {0x340e, 0x01}, + {0x340f, 0x01}, + {0x3410, 0x00}, + {0x3411, 0x04}, + {0x3412, 0x0c}, + {0x3413, 0x02}, + {0x3414, 0x02}, + {0x3415, 0x02}, + {0x3416, 0x03}, + {0x3417, 0x02}, + {0x3418, 0x05}, + {0x3419, 0x0a}, + {0x341a, 0x08}, + {0x341b, 0x04}, + {0x341c, 0x04}, + {0x341d, 0x00}, + {0x341e, 0x03}, + {0x3440, 0x00}, + {0x3441, 0x00}, + {0x3442, 0x00}, + {0x3443, 0x00}, + {0x3444, 0x02}, + {0x3445, 0xf0}, + {0x3446, 0x02}, + {0x3447, 0x08}, + {0x3448, 0x00}, + {0x3460, 0x40}, + {0x3461, 0x40}, + {0x3462, 0x40}, + {0x3463, 0x40}, + {0x3464, 0x03}, + {0x3465, 0x01}, + {0x3466, 0x01}, + {0x3467, 0x02}, + {0x3468, 0x30}, + {0x3469, 0x00}, + {0x346a, 0x33}, + {0x346b, 0xbf}, + {0x3480, 0x40}, + {0x3481, 0x00}, + {0x3482, 0x00}, + {0x3483, 0x00}, + {0x3484, 0x0d}, + {0x3485, 0x00}, + {0x3486, 0x00}, + {0x3487, 0x00}, + {0x3488, 0x00}, + {0x3489, 0x00}, + {0x348a, 0x00}, + {0x348b, 0x04}, + {0x348c, 0x00}, + {0x348d, 0x01}, + {0x348f, 0x01}, + {0x3030, 0x0a}, + {0x3030, 0x02}, + {0x7000, 0x58}, + {0x7001, 0x7a}, + {0x7002, 0x1a}, + {0x7003, 0xc1}, + {0x7004, 0x03}, + {0x7005, 0xda}, + {0x7006, 0xbd}, + {0x7007, 0x03}, + {0x7008, 0xbd}, + {0x7009, 0x06}, + {0x700a, 0xe6}, + {0x700b, 0xec}, + {0x700c, 0xbc}, + {0x700d, 0xff}, + {0x700e, 0xbc}, + {0x700f, 0x73}, + {0x7010, 0xda}, + {0x7011, 0x72}, + {0x7012, 0x76}, + {0x7013, 0xb6}, + {0x7014, 0xee}, + {0x7015, 0xcf}, + {0x7016, 0xac}, + {0x7017, 0xd0}, + {0x7018, 0xac}, + {0x7019, 0xd1}, + {0x701a, 0x50}, + {0x701b, 0xac}, + {0x701c, 0xd2}, + {0x701d, 0xbc}, + {0x701e, 0x2e}, + {0x701f, 0xb4}, + {0x7020, 0x00}, + {0x7021, 0xdc}, + {0x7022, 0xdf}, + {0x7023, 0xb0}, + {0x7024, 0x6e}, + {0x7025, 0xbd}, + {0x7026, 0x01}, + {0x7027, 0xd7}, + {0x7028, 0xed}, + {0x7029, 0xe1}, + {0x702a, 0x36}, + {0x702b, 0x30}, + {0x702c, 0xd3}, + {0x702d, 0x2e}, + {0x702e, 0x54}, + {0x702f, 0x46}, + {0x7030, 0xbc}, + {0x7031, 0x22}, + {0x7032, 0x66}, + {0x7033, 0xbc}, + {0x7034, 0x24}, + {0x7035, 0x2c}, + {0x7036, 0x28}, + {0x7037, 0xbc}, + {0x7038, 0x3c}, + {0x7039, 0xa1}, + {0x703a, 0xac}, + {0x703b, 0xd8}, + {0x703c, 0xd6}, + {0x703d, 0xb4}, + {0x703e, 0x04}, + {0x703f, 0x46}, + {0x7040, 0xb7}, + {0x7041, 0x04}, + {0x7042, 0xbe}, + {0x7043, 0x08}, + {0x7044, 0xc3}, + {0x7045, 0xd9}, + {0x7046, 0xad}, + {0x7047, 0xc3}, + {0x7048, 0xbc}, + {0x7049, 0x19}, + {0x704a, 0xc1}, + {0x704b, 0x27}, + {0x704c, 0xe7}, + {0x704d, 0x00}, + {0x704e, 0x50}, + {0x704f, 0x20}, + {0x7050, 0xb8}, + {0x7051, 0x02}, + {0x7052, 0xbc}, + {0x7053, 0x17}, + {0x7054, 0xdb}, + {0x7055, 0xc7}, + {0x7056, 0xb8}, + {0x7057, 0x00}, + {0x7058, 0x28}, + {0x7059, 0x54}, + {0x705a, 0xb4}, + {0x705b, 0x14}, + {0x705c, 0xab}, + {0x705d, 0xbe}, + {0x705e, 0x06}, + {0x705f, 0xd8}, + {0x7060, 0xd6}, + {0x7061, 0x00}, + {0x7062, 0xb4}, + {0x7063, 0xc7}, + {0x7064, 0x07}, + {0x7065, 0xb9}, + {0x7066, 0x05}, + {0x7067, 0xee}, + {0x7068, 0xe6}, + {0x7069, 0xad}, + {0x706a, 0xb4}, + {0x706b, 0x26}, + {0x706c, 0x19}, + {0x706d, 0xc1}, + {0x706e, 0x3a}, + {0x706f, 0xc3}, + {0x7070, 0xaf}, + {0x7071, 0x00}, + {0x7072, 0xc0}, + {0x7073, 0x3c}, + {0x7074, 0xc3}, + {0x7075, 0xbe}, + {0x7076, 0xe7}, + {0x7077, 0x00}, + {0x7078, 0x15}, + {0x7079, 0xc2}, + {0x707a, 0x40}, + {0x707b, 0xc3}, + {0x707c, 0xa4}, + {0x707d, 0xc0}, + {0x707e, 0x3c}, + {0x707f, 0x00}, + {0x7080, 0xb9}, + {0x7081, 0x64}, + {0x7082, 0x29}, + {0x7083, 0x00}, + {0x7084, 0xb8}, + {0x7085, 0x12}, + {0x7086, 0xbe}, + {0x7087, 0x01}, + {0x7088, 0xd0}, + {0x7089, 0xbc}, + {0x708a, 0x01}, + {0x708b, 0xac}, + {0x708c, 0x37}, + {0x708d, 0xd2}, + {0x708e, 0xac}, + {0x708f, 0x45}, + {0x7090, 0xad}, + {0x7091, 0x28}, + {0x7092, 0x00}, + {0x7093, 0xb8}, + {0x7094, 0x00}, + {0x7095, 0xbc}, + {0x7096, 0x01}, + {0x7097, 0x36}, + {0x7098, 0xd3}, + {0x7099, 0x30}, + {0x709a, 0x04}, + {0x709b, 0xe0}, + {0x709c, 0xd8}, + {0x709d, 0xb4}, + {0x709e, 0xe9}, + {0x709f, 0x00}, + {0x70a0, 0xbe}, + {0x70a1, 0x05}, + {0x70a2, 0x62}, + {0x70a3, 0x07}, + {0x70a4, 0xb9}, + {0x70a5, 0x05}, + {0x70a6, 0xad}, + {0x70a7, 0xc3}, + {0x70a8, 0xcf}, + {0x70a9, 0x00}, + {0x70aa, 0x15}, + {0x70ab, 0xc2}, + {0x70ac, 0x59}, + {0x70ad, 0xc3}, + {0x70ae, 0xc9}, + {0x70af, 0xc0}, + {0x70b0, 0x55}, + {0x70b1, 0x00}, + {0x70b2, 0x46}, + {0x70b3, 0xa1}, + {0x70b4, 0xb9}, + {0x70b5, 0x64}, + {0x70b6, 0x29}, + {0x70b7, 0x00}, + {0x70b8, 0xb8}, + {0x70b9, 0x02}, + {0x70ba, 0xbe}, + {0x70bb, 0x02}, + {0x70bc, 0xd0}, + {0x70bd, 0xdc}, + {0x70be, 0xac}, + {0x70bf, 0xbc}, + {0x70c0, 0x01}, + {0x70c1, 0x37}, + {0x70c2, 0xac}, + {0x70c3, 0xd2}, + {0x70c4, 0x45}, + {0x70c5, 0xad}, + {0x70c6, 0x28}, + {0x70c7, 0x00}, + {0x70c8, 0xb8}, + {0x70c9, 0x00}, + {0x70ca, 0xbc}, + {0x70cb, 0x01}, + {0x70cc, 0x36}, + {0x70cd, 0x30}, + {0x70ce, 0xe0}, + {0x70cf, 0xd8}, + {0x70d0, 0xb5}, + {0x70d1, 0x0b}, + {0x70d2, 0xd6}, + {0x70d3, 0xbe}, + {0x70d4, 0x07}, + {0x70d5, 0x00}, + {0x70d6, 0x62}, + {0x70d7, 0x07}, + {0x70d8, 0xb9}, + {0x70d9, 0x05}, + {0x70da, 0xad}, + {0x70db, 0xc3}, + {0x70dc, 0xcf}, + {0x70dd, 0x46}, + {0x70de, 0xcd}, + {0x70df, 0x07}, + {0x70e0, 0xcd}, + {0x70e1, 0x00}, + {0x70e2, 0xe3}, + {0x70e3, 0x18}, + {0x70e4, 0xc2}, + {0x70e5, 0xa2}, + {0x70e6, 0xb9}, + {0x70e7, 0x64}, + {0x70e8, 0xd1}, + {0x70e9, 0xdd}, + {0x70ea, 0xac}, + {0x70eb, 0xcf}, + {0x70ec, 0xdf}, + {0x70ed, 0xb5}, + {0x70ee, 0x19}, + {0x70ef, 0x46}, + {0x70f0, 0x50}, + {0x70f1, 0xb6}, + {0x70f2, 0xee}, + {0x70f3, 0xe8}, + {0x70f4, 0xe6}, + {0x70f5, 0xbc}, + {0x70f6, 0x31}, + {0x70f7, 0xe1}, + {0x70f8, 0x36}, + {0x70f9, 0x30}, + {0x70fa, 0xd3}, + {0x70fb, 0x2e}, + {0x70fc, 0x54}, + {0x70fd, 0xbd}, + {0x70fe, 0x03}, + {0x70ff, 0xec}, + {0x7100, 0x2c}, + {0x7101, 0x50}, + {0x7102, 0x20}, + {0x7103, 0x04}, + {0x7104, 0xb8}, + {0x7105, 0x02}, + {0x7106, 0xbc}, + {0x7107, 0x18}, + {0x7108, 0xc7}, + {0x7109, 0xb8}, + {0x710a, 0x00}, + {0x710b, 0x28}, + {0x710c, 0x54}, + {0x710d, 0xbc}, + {0x710e, 0x02}, + {0x710f, 0xb4}, + {0x7110, 0xda}, + {0x7111, 0xbe}, + {0x7112, 0x04}, + {0x7113, 0xd6}, + {0x7114, 0xd8}, + {0x7115, 0xab}, + {0x7116, 0x00}, + {0x7117, 0x62}, + {0x7118, 0x07}, + {0x7119, 0xb9}, + {0x711a, 0x05}, + {0x711b, 0xad}, + {0x711c, 0xc3}, + {0x711d, 0xbc}, + {0x711e, 0xe7}, + {0x711f, 0xb9}, + {0x7120, 0x64}, + {0x7121, 0x29}, + {0x7122, 0x00}, + {0x7123, 0xb8}, + {0x7124, 0x02}, + {0x7125, 0xbe}, + {0x7126, 0x00}, + {0x7127, 0x45}, + {0x7128, 0xad}, + {0x7129, 0xe2}, + {0x712a, 0x28}, + {0x712b, 0x00}, + {0x712c, 0xb8}, + {0x712d, 0x00}, + {0x712e, 0xe0}, + {0x712f, 0xd8}, + {0x7130, 0xb4}, + {0x7131, 0xe9}, + {0x7132, 0xbe}, + {0x7133, 0x03}, + {0x7134, 0x00}, + {0x7135, 0x30}, + {0x7136, 0x62}, + {0x7137, 0x07}, + {0x7138, 0xb9}, + {0x7139, 0x05}, + {0x713a, 0xad}, + {0x713b, 0xc3}, + {0x713c, 0xcf}, + {0x713d, 0x42}, + {0x713e, 0xe4}, + {0x713f, 0xcd}, + {0x7140, 0x07}, + {0x7141, 0xcd}, + {0x7142, 0x00}, + {0x7143, 0x00}, + {0x7144, 0x17}, + {0x7145, 0xc2}, + {0x7146, 0xbb}, + {0x7147, 0xde}, + {0x7148, 0xcf}, + {0x7149, 0xdf}, + {0x714a, 0xac}, + {0x714b, 0xd1}, + {0x714c, 0x44}, + {0x714d, 0xac}, + {0x714e, 0xb9}, + {0x714f, 0x76}, + {0x7150, 0xb8}, + {0x7151, 0x08}, + {0x7152, 0xb6}, + {0x7153, 0xfe}, + {0x7154, 0xb4}, + {0x7155, 0xca}, + {0x7156, 0xd6}, + {0x7157, 0xd8}, + {0x7158, 0xab}, + {0x7159, 0x00}, + {0x715a, 0xe1}, + {0x715b, 0x36}, + {0x715c, 0x30}, + {0x715d, 0xd3}, + {0x715e, 0xbc}, + {0x715f, 0x29}, + {0x7160, 0xb4}, + {0x7161, 0x1f}, + {0x7162, 0xaa}, + {0x7163, 0xbd}, + {0x7164, 0x01}, + {0x7165, 0xb8}, + {0x7166, 0x0c}, + {0x7167, 0x45}, + {0x7168, 0xa4}, + {0x7169, 0xbd}, + {0x716a, 0x03}, + {0x716b, 0xec}, + {0x716c, 0xbc}, + {0x716d, 0x3d}, + {0x716e, 0xc3}, + {0x716f, 0xcf}, + {0x7170, 0x42}, + {0x7171, 0xb8}, + {0x7172, 0x00}, + {0x7173, 0xe4}, + {0x7174, 0xd5}, + {0x7175, 0x00}, + {0x7176, 0xb6}, + {0x7177, 0x00}, + {0x7178, 0x74}, + {0x7179, 0xbd}, + {0x717a, 0x03}, + {0x717b, 0xb5}, + {0x717c, 0x39}, + {0x717d, 0x40}, + {0x717e, 0x58}, + {0x717f, 0xdd}, + {0x7180, 0x19}, + {0x7181, 0xc1}, + {0x7182, 0xc8}, + {0x7183, 0xbd}, + {0x7184, 0x06}, + {0x7185, 0x17}, + {0x7186, 0xc1}, + {0x7187, 0xc6}, + {0x7188, 0xe8}, + {0x7189, 0x00}, + {0x718a, 0xc0}, + {0x718b, 0xc8}, + {0x718c, 0xe6}, + {0x718d, 0x95}, + {0x718e, 0x15}, + {0x718f, 0x00}, + {0x7190, 0xbc}, + {0x7191, 0x19}, + {0x7192, 0xb9}, + {0x7193, 0xf6}, + {0x7194, 0x14}, + {0x7195, 0xc1}, + {0x7196, 0xd0}, + {0x7197, 0xd1}, + {0x7198, 0xac}, + {0x7199, 0x37}, + {0x719a, 0xbc}, + {0x719b, 0x35}, + {0x719c, 0x36}, + {0x719d, 0x30}, + {0x719e, 0xe1}, + {0x719f, 0xd3}, + {0x71a0, 0x7a}, + {0x71a1, 0xb6}, + {0x71a2, 0x0c}, + {0x71a3, 0xff}, + {0x71a4, 0xb4}, + {0x71a5, 0xc7}, + {0x71a6, 0xd9}, + {0x71a7, 0x00}, + {0x71a8, 0xbd}, + {0x71a9, 0x01}, + {0x71aa, 0x56}, + {0x71ab, 0xc0}, + {0x71ac, 0xda}, + {0x71ad, 0xb4}, + {0x71ae, 0x1f}, + {0x71af, 0x56}, + {0x71b0, 0xaa}, + {0x71b1, 0xbc}, + {0x71b2, 0x08}, + {0x71b3, 0x00}, + {0x71b4, 0x57}, + {0x71b5, 0xe8}, + {0x71b6, 0xb5}, + {0x71b7, 0x36}, + {0x71b8, 0x00}, + {0x71b9, 0x54}, + {0x71ba, 0xe7}, + {0x71bb, 0xc8}, + {0x71bc, 0xb4}, + {0x71bd, 0x1f}, + {0x71be, 0x56}, + {0x71bf, 0xaa}, + {0x71c0, 0xbc}, + {0x71c1, 0x08}, + {0x71c2, 0x57}, + {0x71c3, 0x00}, + {0x71c4, 0xb5}, + {0x71c5, 0x36}, + {0x71c6, 0x00}, + {0x71c7, 0x54}, + {0x71c8, 0xc8}, + {0x71c9, 0xb5}, + {0x71ca, 0x18}, + {0x71cb, 0xd9}, + {0x71cc, 0x00}, + {0x71cd, 0xbd}, + {0x71ce, 0x01}, + {0x71cf, 0x56}, + {0x71d0, 0x08}, + {0x71d1, 0x57}, + {0x71d2, 0xe8}, + {0x71d3, 0xb4}, + {0x71d4, 0x42}, + {0x71d5, 0x00}, + {0x71d6, 0x54}, + {0x71d7, 0xe7}, + {0x71d8, 0xc8}, + {0x71d9, 0xab}, + {0x71da, 0x00}, + {0x71db, 0x66}, + {0x71dc, 0x62}, + {0x71dd, 0x06}, + {0x71de, 0x74}, + {0x71df, 0xb9}, + {0x71e0, 0x05}, + {0x71e1, 0xb7}, + {0x71e2, 0x14}, + {0x71e3, 0x0e}, + {0x71e4, 0xb7}, + {0x71e5, 0x04}, + {0x71e6, 0xc8}, + {0x7600, 0x04}, + {0x7601, 0x80}, + {0x7602, 0x07}, + {0x7603, 0x44}, + {0x7604, 0x05}, + {0x7605, 0x33}, + {0x7606, 0x0f}, + {0x7607, 0x00}, + {0x7608, 0x07}, + {0x7609, 0x40}, + {0x760a, 0x04}, + {0x760b, 0xe5}, + {0x760c, 0x06}, + {0x760d, 0x50}, + {0x760e, 0x04}, + {0x760f, 0xe4}, + {0x7610, 0x00}, + {0x7611, 0x00}, + {0x7612, 0x06}, + {0x7613, 0x5c}, + {0x7614, 0x00}, + {0x7615, 0x0f}, + {0x7616, 0x06}, + {0x7617, 0x1c}, + {0x7618, 0x00}, + {0x7619, 0x02}, + {0x761a, 0x06}, + {0x761b, 0xa2}, + {0x761c, 0x00}, + {0x761d, 0x01}, + {0x761e, 0x06}, + {0x761f, 0xae}, + {0x7620, 0x00}, + {0x7621, 0x0e}, + {0x7622, 0x05}, + {0x7623, 0x30}, + {0x7624, 0x07}, + {0x7625, 0x00}, + {0x7626, 0x0f}, + {0x7627, 0x00}, + {0x7628, 0x04}, + {0x7629, 0xe5}, + {0x762a, 0x05}, + {0x762b, 0x33}, + {0x762c, 0x06}, + {0x762d, 0x12}, + {0x762e, 0x00}, + {0x762f, 0x01}, + {0x7630, 0x06}, + {0x7631, 0x52}, + {0x7632, 0x00}, + {0x7633, 0x01}, + {0x7634, 0x06}, + {0x7635, 0x5e}, + {0x7636, 0x04}, + {0x7637, 0xe4}, + {0x7638, 0x00}, + {0x7639, 0x01}, + {0x763a, 0x05}, + {0x763b, 0x30}, + {0x763c, 0x0f}, + {0x763d, 0x00}, + {0x763e, 0x06}, + {0x763f, 0xa6}, + {0x7640, 0x00}, + {0x7641, 0x02}, + {0x7642, 0x06}, + {0x7643, 0x26}, + {0x7644, 0x00}, + {0x7645, 0x02}, + {0x7646, 0x05}, + {0x7647, 0x33}, + {0x7648, 0x06}, + {0x7649, 0x20}, + {0x764a, 0x0f}, + {0x764b, 0x00}, + {0x764c, 0x06}, + {0x764d, 0x56}, + {0x764e, 0x00}, + {0x764f, 0x02}, + {0x7650, 0x06}, + {0x7651, 0x16}, + {0x7652, 0x05}, + {0x7653, 0x33}, + {0x7654, 0x06}, + {0x7655, 0x10}, + {0x7656, 0x0f}, + {0x7657, 0x00}, + {0x7658, 0x06}, + {0x7659, 0x10}, + {0x765a, 0x0f}, + {0x765b, 0x00}, + {0x765c, 0x06}, + {0x765d, 0x20}, + {0x765e, 0x0f}, + {0x765f, 0x00}, + {0x7660, 0x00}, + {0x7661, 0x00}, + {0x7662, 0x00}, + {0x7663, 0x02}, + {0x7664, 0x04}, + {0x7665, 0xe5}, + {0x7666, 0x04}, + {0x7667, 0xe4}, + {0x7668, 0x0f}, + {0x7669, 0x00}, + {0x766a, 0x00}, + {0x766b, 0x00}, + {0x766c, 0x00}, + {0x766d, 0x01}, + {0x766e, 0x04}, + {0x766f, 0xe5}, + {0x7670, 0x04}, + {0x7671, 0xe4}, + {0x7672, 0x0f}, + {0x7673, 0x00}, + {0x7674, 0x00}, + {0x7675, 0x02}, + {0x7676, 0x04}, + {0x7677, 0xe4}, + {0x7678, 0x00}, + {0x7679, 0x02}, + {0x767a, 0x04}, + {0x767b, 0xc4}, + {0x767c, 0x00}, + {0x767d, 0x02}, + {0x767e, 0x04}, + {0x767f, 0xc4}, + {0x7680, 0x05}, + {0x7681, 0x83}, + {0x7682, 0x0f}, + {0x7683, 0x00}, + {0x7684, 0x00}, + {0x7685, 0x02}, + {0x7686, 0x04}, + {0x7687, 0xe4}, + {0x7688, 0x00}, + {0x7689, 0x02}, + {0x768a, 0x04}, + {0x768b, 0xc4}, + {0x768c, 0x00}, + {0x768d, 0x02}, + {0x768e, 0x04}, + {0x768f, 0xc4}, + {0x7690, 0x05}, + {0x7691, 0x83}, + {0x7692, 0x03}, + {0x7693, 0x0b}, + {0x7694, 0x05}, + {0x7695, 0x83}, + {0x7696, 0x00}, + {0x7697, 0x07}, + {0x7698, 0x05}, + {0x7699, 0x03}, + {0x769a, 0x00}, + {0x769b, 0x05}, + {0x769c, 0x05}, + {0x769d, 0x32}, + {0x769e, 0x05}, + {0x769f, 0x30}, + {0x76a0, 0x00}, + {0x76a1, 0x02}, + {0x76a2, 0x05}, + {0x76a3, 0x78}, + {0x76a4, 0x00}, + {0x76a5, 0x01}, + {0x76a6, 0x05}, + {0x76a7, 0x7c}, + {0x76a8, 0x03}, + {0x76a9, 0x9a}, + {0x76aa, 0x05}, + {0x76ab, 0x83}, + {0x76ac, 0x00}, + {0x76ad, 0x04}, + {0x76ae, 0x05}, + {0x76af, 0x03}, + {0x76b0, 0x00}, + {0x76b1, 0x03}, + {0x76b2, 0x05}, + {0x76b3, 0x32}, + {0x76b4, 0x05}, + {0x76b5, 0x30}, + {0x76b6, 0x00}, + {0x76b7, 0x02}, + {0x76b8, 0x05}, + {0x76b9, 0x78}, + {0x76ba, 0x00}, + {0x76bb, 0x01}, + {0x76bc, 0x05}, + {0x76bd, 0x7c}, + {0x76be, 0x03}, + {0x76bf, 0x99}, + {0x76c0, 0x05}, + {0x76c1, 0x83}, + {0x76c2, 0x00}, + {0x76c3, 0x03}, + {0x76c4, 0x05}, + {0x76c5, 0x03}, + {0x76c6, 0x00}, + {0x76c7, 0x01}, + {0x76c8, 0x05}, + {0x76c9, 0x32}, + {0x76ca, 0x05}, + {0x76cb, 0x30}, + {0x76cc, 0x00}, + {0x76cd, 0x02}, + {0x76ce, 0x05}, + {0x76cf, 0x78}, + {0x76d0, 0x00}, + {0x76d1, 0x01}, + {0x76d2, 0x05}, + {0x76d3, 0x7c}, + {0x76d4, 0x03}, + {0x76d5, 0x98}, + {0x76d6, 0x05}, + {0x76d7, 0x83}, + {0x76d8, 0x00}, + {0x76d9, 0x00}, + {0x76da, 0x05}, + {0x76db, 0x03}, + {0x76dc, 0x00}, + {0x76dd, 0x01}, + {0x76de, 0x05}, + {0x76df, 0x32}, + {0x76e0, 0x05}, + {0x76e1, 0x30}, + {0x76e2, 0x00}, + {0x76e3, 0x02}, + {0x76e4, 0x05}, + {0x76e5, 0x78}, + {0x76e6, 0x00}, + {0x76e7, 0x01}, + {0x76e8, 0x05}, + {0x76e9, 0x7c}, + {0x76ea, 0x03}, + {0x76eb, 0x97}, + {0x76ec, 0x05}, + {0x76ed, 0x83}, + {0x76ee, 0x00}, + {0x76ef, 0x00}, + {0x76f0, 0x05}, + {0x76f1, 0x03}, + {0x76f2, 0x05}, + {0x76f3, 0x32}, + {0x76f4, 0x05}, + {0x76f5, 0x30}, + {0x76f6, 0x00}, + {0x76f7, 0x02}, + {0x76f8, 0x05}, + {0x76f9, 0x78}, + {0x76fa, 0x00}, + {0x76fb, 0x01}, + {0x76fc, 0x05}, + {0x76fd, 0x7c}, + {0x76fe, 0x03}, + {0x76ff, 0x96}, + {0x7700, 0x05}, + {0x7701, 0x83}, + {0x7702, 0x05}, + {0x7703, 0x03}, + {0x7704, 0x05}, + {0x7705, 0x32}, + {0x7706, 0x05}, + {0x7707, 0x30}, + {0x7708, 0x00}, + {0x7709, 0x02}, + {0x770a, 0x05}, + {0x770b, 0x78}, + {0x770c, 0x00}, + {0x770d, 0x01}, + {0x770e, 0x05}, + {0x770f, 0x7c}, + {0x7710, 0x03}, + {0x7711, 0x95}, + {0x7712, 0x05}, + {0x7713, 0x83}, + {0x7714, 0x05}, + {0x7715, 0x03}, + {0x7716, 0x05}, + {0x7717, 0x32}, + {0x7718, 0x05}, + {0x7719, 0x30}, + {0x771a, 0x00}, + {0x771b, 0x02}, + {0x771c, 0x05}, + {0x771d, 0x78}, + {0x771e, 0x00}, + {0x771f, 0x01}, + {0x7720, 0x05}, + {0x7721, 0x7c}, + {0x7722, 0x03}, + {0x7723, 0x94}, + {0x7724, 0x05}, + {0x7725, 0x83}, + {0x7726, 0x00}, + {0x7727, 0x01}, + {0x7728, 0x05}, + {0x7729, 0x03}, + {0x772a, 0x00}, + {0x772b, 0x01}, + {0x772c, 0x05}, + {0x772d, 0x32}, + {0x772e, 0x05}, + {0x772f, 0x30}, + {0x7730, 0x00}, + {0x7731, 0x02}, + {0x7732, 0x05}, + {0x7733, 0x78}, + {0x7734, 0x00}, + {0x7735, 0x01}, + {0x7736, 0x05}, + {0x7737, 0x7c}, + {0x7738, 0x03}, + {0x7739, 0x93}, + {0x773a, 0x05}, + {0x773b, 0x83}, + {0x773c, 0x00}, + {0x773d, 0x00}, + {0x773e, 0x05}, + {0x773f, 0x03}, + {0x7740, 0x00}, + {0x7741, 0x00}, + {0x7742, 0x05}, + {0x7743, 0x32}, + {0x7744, 0x05}, + {0x7745, 0x30}, + {0x7746, 0x00}, + {0x7747, 0x02}, + {0x7748, 0x05}, + {0x7749, 0x78}, + {0x774a, 0x00}, + {0x774b, 0x01}, + {0x774c, 0x05}, + {0x774d, 0x7c}, + {0x774e, 0x03}, + {0x774f, 0x92}, + {0x7750, 0x05}, + {0x7751, 0x83}, + {0x7752, 0x05}, + {0x7753, 0x03}, + {0x7754, 0x00}, + {0x7755, 0x00}, + {0x7756, 0x05}, + {0x7757, 0x32}, + {0x7758, 0x05}, + {0x7759, 0x30}, + {0x775a, 0x00}, + {0x775b, 0x02}, + {0x775c, 0x05}, + {0x775d, 0x78}, + {0x775e, 0x00}, + {0x775f, 0x01}, + {0x7760, 0x05}, + {0x7761, 0x7c}, + {0x7762, 0x03}, + {0x7763, 0x91}, + {0x7764, 0x05}, + {0x7765, 0x83}, + {0x7766, 0x05}, + {0x7767, 0x03}, + {0x7768, 0x05}, + {0x7769, 0x32}, + {0x776a, 0x05}, + {0x776b, 0x30}, + {0x776c, 0x00}, + {0x776d, 0x02}, + {0x776e, 0x05}, + {0x776f, 0x78}, + {0x7770, 0x00}, + {0x7771, 0x01}, + {0x7772, 0x05}, + {0x7773, 0x7c}, + {0x7774, 0x03}, + {0x7775, 0x90}, + {0x7776, 0x05}, + {0x7777, 0x83}, + {0x7778, 0x05}, + {0x7779, 0x03}, + {0x777a, 0x05}, + {0x777b, 0x32}, + {0x777c, 0x05}, + {0x777d, 0x30}, + {0x777e, 0x00}, + {0x777f, 0x02}, + {0x7780, 0x05}, + {0x7781, 0x78}, + {0x7782, 0x00}, + {0x7783, 0x01}, + {0x7784, 0x05}, + {0x7785, 0x7c}, + {0x7786, 0x02}, + {0x7787, 0x90}, + {0x7788, 0x05}, + {0x7789, 0x03}, + {0x778a, 0x07}, + {0x778b, 0x00}, + {0x778c, 0x0f}, + {0x778d, 0x00}, + {0x778e, 0x08}, + {0x778f, 0x30}, + {0x7790, 0x08}, + {0x7791, 0xee}, + {0x7792, 0x0f}, + {0x7793, 0x00}, + {0x7794, 0x05}, + {0x7795, 0x33}, + {0x7796, 0x04}, + {0x7797, 0xe5}, + {0x7798, 0x06}, + {0x7799, 0x52}, + {0x779a, 0x04}, + {0x779b, 0xe4}, + {0x779c, 0x00}, + {0x779d, 0x00}, + {0x779e, 0x06}, + {0x779f, 0x5e}, + {0x77a0, 0x00}, + {0x77a1, 0x0f}, + {0x77a2, 0x06}, + {0x77a3, 0x1e}, + {0x77a4, 0x00}, + {0x77a5, 0x02}, + {0x77a6, 0x06}, + {0x77a7, 0xa2}, + {0x77a8, 0x00}, + {0x77a9, 0x01}, + {0x77aa, 0x06}, + {0x77ab, 0xae}, + {0x77ac, 0x00}, + {0x77ad, 0x03}, + {0x77ae, 0x05}, + {0x77af, 0x30}, + {0x77b0, 0x09}, + {0x77b1, 0x19}, + {0x77b2, 0x0f}, + {0x77b3, 0x00}, + {0x77b4, 0x05}, + {0x77b5, 0x33}, + {0x77b6, 0x04}, + {0x77b7, 0xe5}, + {0x77b8, 0x06}, + {0x77b9, 0x52}, + {0x77ba, 0x04}, + {0x77bb, 0xe4}, + {0x77bc, 0x00}, + {0x77bd, 0x00}, + {0x77be, 0x06}, + {0x77bf, 0x5e}, + {0x77c0, 0x00}, + {0x77c1, 0x0f}, + {0x77c2, 0x06}, + {0x77c3, 0x1e}, + {0x77c4, 0x00}, + {0x77c5, 0x02}, + {0x77c6, 0x06}, + {0x77c7, 0xa2}, + {0x77c8, 0x00}, + {0x77c9, 0x01}, + {0x77ca, 0x06}, + {0x77cb, 0xae}, + {0x77cc, 0x00}, + {0x77cd, 0x03}, + {0x77ce, 0x05}, + {0x77cf, 0x30}, + {0x77d0, 0x0f}, + {0x77d1, 0x00}, + {0x77d2, 0x00}, + {0x77d3, 0x00}, + {0x77d4, 0x00}, + {0x77d5, 0x02}, + {0x77d6, 0x04}, + {0x77d7, 0xe5}, + {0x77d8, 0x04}, + {0x77d9, 0xe4}, + {0x77da, 0x05}, + {0x77db, 0x33}, + {0x77dc, 0x07}, + {0x77dd, 0x10}, + {0x77de, 0x00}, + {0x77df, 0x00}, + {0x77e0, 0x01}, + {0x77e1, 0xbb}, + {0x77e2, 0x00}, + {0x77e3, 0x00}, + {0x77e4, 0x01}, + {0x77e5, 0xaa}, + {0x77e6, 0x00}, + {0x77e7, 0x00}, + {0x77e8, 0x01}, + {0x77e9, 0x99}, + {0x77ea, 0x00}, + {0x77eb, 0x00}, + {0x77ec, 0x01}, + {0x77ed, 0x88}, + {0x77ee, 0x00}, + {0x77ef, 0x00}, + {0x77f0, 0x01}, + {0x77f1, 0x77}, + {0x77f2, 0x00}, + {0x77f3, 0x00}, + {0x77f4, 0x01}, + {0x77f5, 0x66}, + {0x77f6, 0x00}, + {0x77f7, 0x00}, + {0x77f8, 0x01}, + {0x77f9, 0x55}, + {0x77fa, 0x00}, + {0x77fb, 0x00}, + {0x77fc, 0x01}, + {0x77fd, 0x44}, + {0x77fe, 0x00}, + {0x77ff, 0x00}, + {0x7800, 0x01}, + {0x7801, 0x33}, + {0x7802, 0x00}, + {0x7803, 0x00}, + {0x7804, 0x01}, + {0x7805, 0x22}, + {0x7806, 0x00}, + {0x7807, 0x00}, + {0x7808, 0x01}, + {0x7809, 0x11}, + {0x780a, 0x00}, + {0x780b, 0x00}, + {0x780c, 0x01}, + {0x780d, 0x00}, + {0x780e, 0x01}, + {0x780f, 0xff}, + {0x7810, 0x07}, + {0x7811, 0x00}, + {0x7812, 0x02}, + {0x7813, 0xa0}, + {0x7814, 0x0f}, + {0x7815, 0x00}, + {0x7816, 0x08}, + {0x7817, 0x35}, + {0x7818, 0x06}, + {0x7819, 0x52}, + {0x781a, 0x04}, + {0x781b, 0xe4}, + {0x781c, 0x00}, + {0x781d, 0x00}, + {0x781e, 0x06}, + {0x781f, 0x5e}, + {0x7820, 0x05}, + {0x7821, 0x33}, + {0x7822, 0x09}, + {0x7823, 0x19}, + {0x7824, 0x06}, + {0x7825, 0x1e}, + {0x7826, 0x05}, + {0x7827, 0x33}, + {0x7828, 0x00}, + {0x7829, 0x01}, + {0x782a, 0x06}, + {0x782b, 0x24}, + {0x782c, 0x06}, + {0x782d, 0x20}, + {0x782e, 0x0f}, + {0x782f, 0x00}, + {0x7830, 0x08}, + {0x7831, 0x35}, + {0x7832, 0x07}, + {0x7833, 0x10}, + {0x7834, 0x00}, + {0x7835, 0x00}, + {0x7836, 0x01}, + {0x7837, 0xbb}, + {0x7838, 0x00}, + {0x7839, 0x00}, + {0x783a, 0x01}, + {0x783b, 0xaa}, + {0x783c, 0x00}, + {0x783d, 0x00}, + {0x783e, 0x01}, + {0x783f, 0x99}, + {0x7840, 0x00}, + {0x7841, 0x00}, + {0x7842, 0x01}, + {0x7843, 0x88}, + {0x7844, 0x00}, + {0x7845, 0x00}, + {0x7846, 0x01}, + {0x7847, 0x77}, + {0x7848, 0x00}, + {0x7849, 0x00}, + {0x784a, 0x01}, + {0x784b, 0x66}, + {0x784c, 0x00}, + {0x784d, 0x00}, + {0x784e, 0x01}, + {0x784f, 0x55}, + {0x7850, 0x00}, + {0x7851, 0x00}, + {0x7852, 0x01}, + {0x7853, 0x44}, + {0x7854, 0x00}, + {0x7855, 0x00}, + {0x7856, 0x01}, + {0x7857, 0x33}, + {0x7858, 0x00}, + {0x7859, 0x00}, + {0x785a, 0x01}, + {0x785b, 0x22}, + {0x785c, 0x00}, + {0x785d, 0x00}, + {0x785e, 0x01}, + {0x785f, 0x11}, + {0x7860, 0x00}, + {0x7861, 0x00}, + {0x7862, 0x01}, + {0x7863, 0x00}, + {0x7864, 0x07}, + {0x7865, 0x00}, + {0x7866, 0x01}, + {0x7867, 0xff}, + {0x7868, 0x02}, + {0x7869, 0xa0}, + {0x786a, 0x0f}, + {0x786b, 0x00}, + {0x786c, 0x08}, + {0x786d, 0x3a}, + {0x786e, 0x08}, + {0x786f, 0x6a}, + {0x7870, 0x0f}, + {0x7871, 0x00}, + {0x7872, 0x04}, + {0x7873, 0xc0}, + {0x7874, 0x09}, + {0x7875, 0x19}, + {0x7876, 0x04}, + {0x7877, 0x99}, + {0x7878, 0x07}, + {0x7879, 0x14}, + {0x787a, 0x00}, + {0x787b, 0x01}, + {0x787c, 0x04}, + {0x787d, 0xa4}, + {0x787e, 0x00}, + {0x787f, 0x07}, + {0x7880, 0x04}, + {0x7881, 0xa6}, + {0x7882, 0x00}, + {0x7883, 0x00}, + {0x7884, 0x04}, + {0x7885, 0xa0}, + {0x7886, 0x04}, + {0x7887, 0x80}, + {0x7888, 0x04}, + {0x7889, 0x00}, + {0x788a, 0x05}, + {0x788b, 0x03}, + {0x788c, 0x06}, + {0x788d, 0x00}, + {0x788e, 0x0f}, + {0x788f, 0x00}, + {0x7890, 0x0f}, + {0x7891, 0x00}, + {0x7892, 0x0f}, + {0x7893, 0x00}, + {0x30a0, 0x00}, + {0x30a1, 0x00}, + {0x30a2, 0x00}, + {0x30a3, 0x00}, + {0x30a4, 0x07}, + {0x30a5, 0x8f}, + {0x30a6, 0x04}, + {0x30a7, 0x47}, + {0x30a8, 0x00}, + {0x30a9, 0x05}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x88}, + {0x30ae, 0x04}, + {0x30af, 0x40}, + {0x30b0, 0x0d}, + {0x30b1, 0xde}, + {0x30b2, 0x04}, + {0x30b3, 0x66}, + {0x30b6, 0x01}, + {0x30b7, 0x15}, + {0x3196, 0x00}, + {0x3197, 0x0a}, + {0x3195, 0x29}, + {0x315a, 0x02}, + {0x315b, 0x00}, + {0x30bb, 0x40}, + {0x3250, 0xf7}, + {0x30a8, 0x00}, + {0x30a9, 0x04}, + {0x30aa, 0x00}, + {0x30ab, 0x04}, + {0x30ac, 0x07}, + {0x30ad, 0x80}, + {0x30ae, 0x04}, + {0x30af, 0x38}, + {0x3012, 0x01}, +}; + +struct vvcam_sccb_array ov5693_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(ov5693_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = ov5693_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_reg_cfg.h b/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_reg_cfg.h new file mode 100755 index 0000000..243d8fb --- /dev/null +++ b/vvcam_ry/native/sensor/omnivision_ov5693/ov5693_reg_cfg.h @@ -0,0 +1,6 @@ +#ifndef _OV5693_REG_CFG_H_ +#define _OV5693_REG_CFG_H_ + +extern struct vvcam_sccb_array ov5693_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam_ry/native/sensor/platform/platform_gen6_driver.c b/vvcam_ry/native/sensor/platform/platform_gen6_driver.c new file mode 100755 index 0000000..84c7be0 --- /dev/null +++ b/vvcam_ry/native/sensor/platform/platform_gen6_driver.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include "vvsensor.h" + + +int32_t sensor_reset(void *dev) +{ + return 0; +} + +int32_t sensor_set_clk(void *dev, uint32_t clk) +{ + return 0; +} + +int32_t sensor_get_clk(void *dev, uint32_t *pclk) +{ + return 0; +} + +int32_t sensor_set_power(void *dev, uint32_t power) +{ + return 0; +} + +int32_t sensor_get_power(void *dev, uint32_t *ppower) +{ + return 0; +} + diff --git a/vvcam_ry/native/sensor/sensor_common.h b/vvcam_ry/native/sensor/sensor_common.h new file mode 100755 index 0000000..fd3b3fe --- /dev/null +++ b/vvcam_ry/native/sensor/sensor_common.h @@ -0,0 +1,109 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _SENSOR_COMMON_H_ +#define _SENSOR_COMMON_H_ +#include +#include "vvsensor.h" + +struct vvcam_sensor_function_s +{ + uint8_t sensor_name[16]; + uint32_t reserve_id; + uint32_t sensor_clk; + struct sensor_mipi_info mipi_info; + + int32_t (*sensor_get_chip_id) (void *ctx, uint32_t *chip_id); + int32_t (*sensor_init) (void *ctx, struct vvcam_mode_info *pmode); + int32_t (*sensor_set_stream) (void *ctx, uint32_t status); + int32_t (*sensor_set_exp) (void *ctx, uint32_t exp_line); + int32_t (*sensor_set_vs_exp) (void *ctx, uint32_t exp_line); + int32_t (*sensor_set_gain) (void *ctx, uint32_t gain); + int32_t (*sensor_set_vs_gain) (void *ctx, uint32_t gain); + int32_t (*sensor_set_fps) (void *ctx, uint32_t fps); + int32_t (*sensor_set_resolution)(void *ctx, uint32_t width, uint32_t height); + int32_t (*sensor_set_hdr_mode) (void *ctx, uint32_t hdr_mode); + int32_t (*sensor_query) (void *ctx, struct vvcam_mode_info_array *pmode_info_arry); +}; + +struct vvcam_sensor_dev { + long phy_addr; + long reg_size; + void __iomem *base; + int32_t device_idx; + + uint8_t i2c_bus; + void* i2c_client; + struct vvcam_sccb_cfg_s sensor_sccb_cfg; + struct vvcam_sccb_cfg_s focus_sccb_cfg; + struct vvcam_sensor_function_s sensor_func; + + struct vvcam_mode_info sensor_mode; + struct vvcam_ae_info_s ae_info; +}; + +int32_t sensor_reset(void *dev); +int32_t sensor_set_clk(void *dev, uint32_t clk); +int32_t sensor_get_clk(void *dev, uint32_t *pclk); +int32_t sensor_set_power(void *dev, uint32_t power); +int32_t sensor_get_power(void *dev, uint32_t *ppower); + +int32_t vvcam_sensor_i2c_write(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t data); +int32_t vvcam_sensor_i2c_read(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t *pdata); + +int vvnative_sensor_init(struct vvcam_sensor_dev *dev); +int vvnative_sensor_deinit(struct vvcam_sensor_dev *dev); +long sensor_priv_ioctl(struct vvcam_sensor_dev *dev, unsigned int cmd, void *args); + + +#endif \ No newline at end of file diff --git a/vvcam_ry/native/sensor/sensor_ioctl.c b/vvcam_ry/native/sensor/sensor_ioctl.c new file mode 100755 index 0000000..98f07ec --- /dev/null +++ b/vvcam_ry/native/sensor/sensor_ioctl.c @@ -0,0 +1,698 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" + +extern struct vvcam_sensor_function_s SENSR0_FUNCTION; +extern struct vvcam_sensor_function_s SENSR1_FUNCTION; + +static int32_t vvcam_sensor_sccb_config(struct vvcam_sensor_dev *dev, struct vvcam_sccb_cfg_s *sccb_config) +{ + dev->sensor_sccb_cfg.slave_addr = sccb_config->slave_addr; + dev->sensor_sccb_cfg.addr_byte = sccb_config->addr_byte; + dev->sensor_sccb_cfg.data_byte = sccb_config->data_byte; + return 0; +} +static int32_t vvcam_focus_sccb_config(struct vvcam_sensor_dev *dev, struct vvcam_sccb_cfg_s *sccb_config) +{ + dev->sensor_sccb_cfg.slave_addr = sccb_config->slave_addr; + dev->sensor_sccb_cfg.addr_byte = sccb_config->addr_byte; + dev->sensor_sccb_cfg.data_byte = sccb_config->data_byte; + return 0; +} + +static int vvcam_i2c_write_reg(struct i2c_client *client,unsigned int slave_address, + unsigned int reg_addr,unsigned int reg_length, + unsigned int data, unsigned int data_length) +{ + int ret; + unsigned int i; + struct i2c_msg msgs[2]; + unsigned char sendbuf[16]; + unsigned int send_len = 0; + + if (client == NULL) + return -1; + memset(msgs,0,sizeof(msgs)); + memset(sendbuf,0,sizeof(sendbuf)); + + for (i=0; i < reg_length; i++) + { + sendbuf[send_len++] = (reg_addr >> ((reg_length -1 - i)<<3)) & 0xff; + } + for (i=0; i < data_length; i++) + { + sendbuf[send_len++] = (data >> ((data_length -1 - i)<<3)) & 0xff; + } + + msgs[0].addr = slave_address; + msgs[0].flags = client->flags & I2C_M_TEN; + msgs[0].len = send_len; + msgs[0].buf = sendbuf; + + ret = i2c_transfer(client->adapter, msgs, 1); + if (ret != 1) + { + return -1; + } +// pr_info("-->%s: slave_address[0x%x] addr[0x%04x] = 0x%04x addr_byte[%d] data_byte[%d]!\n", __func__,slave_address,reg_addr,data,reg_length,data_length); + return 0; +} + +static int vvcam_i2c_read_reg(struct i2c_client *client,unsigned int slave_address, + unsigned int reg_addr,unsigned int reg_length, + unsigned char * pdata, unsigned int data_length) +{ + int ret; + unsigned int i; + struct i2c_msg msgs[2]; + unsigned char sendbuf[16]; + unsigned int send_len = 0; + unsigned char readbuf[16]; + + if (client == NULL || pdata == NULL) + return -1; + + memset(msgs,0,sizeof(msgs)); + memset(sendbuf,0,sizeof(sendbuf)); + memset(readbuf,0,sizeof(readbuf)); + + for (i=0; i < reg_length; i++) + { + sendbuf[send_len++] = (reg_addr >> ((reg_length -1 - i)<<3)) & 0xff; + } + + msgs[0].addr = slave_address; + msgs[0].flags = client->flags & I2C_M_TEN; + msgs[0].len = send_len; + msgs[0].buf = sendbuf; + + msgs[1].addr = slave_address; + msgs[1].flags = client->flags & I2C_M_TEN; + msgs[1].flags |= I2C_M_RD; + msgs[1].len = data_length; + msgs[1].buf = readbuf; + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret != 2) + { + return -1; + } + + for (i=0; i < data_length; i++) + { + pdata[i] = readbuf[data_length -1 - i]; + } + + return 0; +} + +int32_t vvcam_sensor_i2c_write(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t data) +{ + int32_t ret = 0; + struct vvcam_sccb_data; + + if((NULL == dev)) + { + return -1; + } + + ret = vvcam_i2c_write_reg(dev->i2c_client,dev->sensor_sccb_cfg.slave_addr, + address,dev->sensor_sccb_cfg.addr_byte, + data,dev->sensor_sccb_cfg.data_byte); + + return ret; +} + +int32_t vvcam_sensor_i2c_read(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t *pdata) +{ + int32_t ret = 0; + struct vvcam_sccb_data; + + if((NULL == dev)) + { + return -1; + } + + ret = vvcam_i2c_read_reg(dev->i2c_client,dev->sensor_sccb_cfg.slave_addr, + address, dev->sensor_sccb_cfg.addr_byte, + (unsigned char *)pdata, dev->sensor_sccb_cfg.data_byte); + + return ret; +} + +int32_t vvcam_sensor_i2c_write_array(struct vvcam_sensor_dev *dev, void *args) +{ + int ret = 0; + int index =0; + struct vvcam_sccb_array array; + struct vvcam_sccb_data sccb_data; + + if((NULL == dev)||(NULL == args)) + { + return -1; + } + + copy_from_user(&array, args, sizeof(struct vvcam_sccb_array)); + + for (index = 0; index < array.count; index++) + { + copy_from_user(&sccb_data, &(array.sccb_data[index]), sizeof(struct vvcam_sccb_data)); + ret = vvcam_sensor_i2c_write(dev, sccb_data.addr, sccb_data.data); + if (ret != 0) + { + return ret; + } + } + + return 0; +} + +int vvcam_sensor_i2c_read_array(struct vvcam_sensor_dev *dev, void *args) +{ + int ret = 0; + int index =0; + struct vvcam_sccb_array array; + struct vvcam_sccb_data sccb_data; + + if((NULL == dev)||(NULL == args)) + { + return -1; + } + + copy_from_user(&array, args, sizeof(struct vvcam_sccb_array)); + + for (index = 0; index < array.count; index++) + { + copy_from_user(&sccb_data, &(array.sccb_data[index]), sizeof(struct vvcam_sccb_data)); + ret = vvcam_sensor_i2c_read(dev, sccb_data.addr, &sccb_data.data); + if (ret != 0) + { + return ret; + } + copy_to_user(&(array.sccb_data[index]), &sccb_data, sizeof(struct vvcam_sccb_data)); + } + + return 0; + +} + +int32_t vvcam_focus_i2c_write(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t data) +{ + int32_t ret = 0; + struct vvcam_sccb_data; + + if((NULL == dev)) + { + return -1; + } + + ret = vvcam_i2c_write_reg(dev->i2c_client,dev->focus_sccb_cfg.slave_addr, + address,dev->focus_sccb_cfg.addr_byte, + data,dev->focus_sccb_cfg.data_byte); + + return ret; +} + +int32_t vvcam_focus_i2c_read(struct vvcam_sensor_dev *dev, uint32_t address, uint32_t *pdata) +{ + int32_t ret = 0; + struct vvcam_sccb_data; + + if((NULL == dev)) + { + return -1; + } + + ret = vvcam_i2c_read_reg(dev->i2c_client,dev->focus_sccb_cfg.slave_addr, + address,dev->focus_sccb_cfg.addr_byte, + (unsigned char *)pdata,dev->focus_sccb_cfg.data_byte); + + return ret; +} + +long sensor_priv_ioctl(struct vvcam_sensor_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + if (!dev) + { + pr_err("-->%s: null point!\n", __func__); + return ret; + } + + printk("-->%s: cmd = %d!\n", __func__,cmd); + switch (cmd) + { + case VVSENSORIOC_RESET: + { + ret = sensor_reset(dev); + break; + } + + case VVSENSORIOC_S_CLK: + { + uint32_t clk; + copy_from_user(&clk, args, sizeof(clk)); + ret = sensor_set_clk(dev, clk); + break; + } + + case VVSENSORIOC_G_CLK: + { + uint32_t clk; + ret = sensor_get_clk(dev, &clk); + copy_to_user(args, &clk, sizeof(clk)); + break; + } + + case VVSENSORIOC_S_POWER: + { + uint32_t power; + copy_from_user(&power, args, sizeof(power)); + ret = sensor_set_power(dev, power); + break; + } + + case VVSENSORIOC_G_POWER: + { + uint32_t power; + ret = sensor_get_power(dev, &power); + copy_to_user(args, &power, sizeof(power)); + break; + } + + case VVSENSORIOC_SENSOR_SCCB_CFG: + { + struct vvcam_sccb_cfg_s sccb_config; + copy_from_user(&sccb_config, args, sizeof(sccb_config)); + ret = vvcam_sensor_sccb_config(dev,&sccb_config); + break; + } + + case VVSENSORIOC_FOCUS_SCCB_CFG: + { + struct vvcam_sccb_cfg_s sccb_config; + copy_from_user(&sccb_config, args, sizeof(sccb_config)); + ret = vvcam_focus_sccb_config(dev,&sccb_config); + break; + } + + case VVSENSORIOC_WRITE_REG: + { + struct vvcam_sccb_data sccb_data; + copy_from_user(&sccb_data, args, sizeof(sccb_data)); + ret = vvcam_sensor_i2c_write(dev, sccb_data.addr, sccb_data.data); + break; + } + + case VVSENSORIOC_READ_REG: + { + struct vvcam_sccb_data sccb_data; + copy_from_user(&sccb_data, args, sizeof(sccb_data)); + ret = vvcam_sensor_i2c_read(dev, sccb_data.addr, &sccb_data.data); + copy_to_user(args, &sccb_data, sizeof(sccb_data)); + break; + } + + case VVSENSORIOC_WRITE_ARRAY: + { + ret = vvcam_sensor_i2c_write_array(dev, args); + break; + } + + case VVSENSORIOC_READ_ARRAY: + { + ret = vvcam_sensor_i2c_read_array(dev, args); + break; + } + + case VVSENSORIOC_AF_WRITE_REG: + { + struct vvcam_sccb_data sccb_data; + copy_from_user(&sccb_data, args, sizeof(sccb_data)); + ret = vvcam_focus_i2c_write(dev, sccb_data.addr, sccb_data.data); + break; + } + + case VVSENSORIOC_AF_READ_REG: + { + struct vvcam_sccb_data sccb_data; + copy_from_user(&sccb_data, args, sizeof(sccb_data)); + ret = vvcam_focus_i2c_read(dev, sccb_data.addr, &sccb_data.data); + copy_to_user(args, &sccb_data, sizeof(sccb_data)); + break; + } + + case VVSENSORIOC_G_MIPI: + { + ret = 0; + dev->sensor_func.mipi_info.sensor_data_bit = dev->sensor_mode.bit_width; + copy_to_user(args,&(dev->sensor_func.mipi_info),sizeof(struct sensor_mipi_info)); + break; + } + + case VVSENSORIOC_G_NAME: + { + ret = 0; + copy_to_user(args,dev->sensor_func.sensor_name,16); + break; + } + + case VVSENSORIOC_G_RESERVE_ID: + { + ret = 0; + copy_to_user(args,&(dev->sensor_func.reserve_id),sizeof(uint32_t)); + break; + } + + case VVSENSORIOC_G_CHIP_ID: + { + uint32_t chip_id = 0; + if (dev->sensor_func.sensor_get_chip_id == NULL) + { + return -1; + } + ret = dev->sensor_func.sensor_get_chip_id(dev,&chip_id); + copy_to_user(args, &chip_id, sizeof(chip_id)); + break; + } + + case VVSENSORIOC_S_INIT: + { + + struct vvcam_mode_info sensor_mode; + copy_from_user(&sensor_mode, args, sizeof(struct vvcam_mode_info)); + if (dev->sensor_func.sensor_init == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_init(dev,&sensor_mode); + break; + } + + case VVSENSORIOC_S_STREAM: + { + uint32_t stream_status; + copy_from_user(&stream_status, args, sizeof(stream_status)); + if (dev->sensor_func.sensor_set_stream == NULL) + { + return -1; + } + ret = dev->sensor_func.sensor_set_stream(dev, stream_status); + break; + } + + case VVSENSORIOC_S_EXP: + { + uint32_t exp_line; + copy_from_user(&exp_line, args, sizeof(exp_line)); + + if (dev->sensor_func.sensor_set_exp == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_set_exp(dev,exp_line); + + break; + } + + case VVSENSORIOC_S_VSEXP: + { + uint32_t exp_line; + copy_from_user(&exp_line, args, sizeof(exp_line)); + + if (dev->sensor_func.sensor_set_vs_exp == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_set_vs_exp(dev,exp_line); + + break; + } + + case VVSENSORIOC_S_GAIN: + { + uint32_t gain; + copy_from_user(&gain, args, sizeof(gain)); + + if (dev->sensor_func.sensor_set_gain == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_set_gain(dev, gain); + + break; + } + + case VVSENSORIOC_S_VSGAIN: + { + uint32_t gain; + copy_from_user(&gain, args, sizeof(gain)); + + if (dev->sensor_func.sensor_set_vs_gain == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_set_vs_gain(dev, gain); + break; + } + + case VVSENSORIOC_S_FPS: + { + uint32_t fps; + copy_from_user(&fps, args, sizeof(fps)); + + if (dev->sensor_func.sensor_set_fps == NULL) + { + return -1; + } + + ret = dev->sensor_func.sensor_set_fps(dev,fps); + + break; + } + + case VVSENSORIOC_G_FPS: + { + ret = 0; + copy_to_user(args, &(dev->ae_info.cur_fps),sizeof(uint32_t)); + break; + } + + case VVSENSORIOC_S_FRAMESIZE: + { + ret = 0; + break; + } + + case VVSENSORIOC_ENUM_FRAMESIZES: + { + ret = 0; + break; + } + + case VVSENSORIOC_S_HDR_MODE: + { + uint32_t hdr_mode; + copy_from_user(&hdr_mode, args, sizeof(hdr_mode)); + + if (dev->sensor_func.sensor_set_hdr_mode == NULL) + { + return -1; + } + ret = dev->sensor_func.sensor_set_hdr_mode(dev, hdr_mode); + + break; + } + + case VVSENSORIOC_G_HDR_MODE: + { + ret = 0; + copy_to_user(args,&(dev->sensor_mode.hdr_mode),sizeof(uint32_t)); + break; + } + + case VVSENSORIOC_S_HDR_RADIO: + { + ret = 0; + copy_from_user(&(dev->ae_info.hdr_radio),args,sizeof(uint32_t)); + break; + + } + + case VVSENSORIOC_G_AE_INFO: + { + ret = 0; + copy_to_user(args,&(dev->ae_info),sizeof(struct vvcam_ae_info_s)); + break; + } + + case VVSENSORIOC_QUERY: + { + struct vvcam_mode_info_array sensor_mode_info_arry; + memset(&sensor_mode_info_arry,0,sizeof(sensor_mode_info_arry)); + + if (dev->sensor_func.sensor_query == NULL) + { + return -1; + } + ret = dev->sensor_func.sensor_query(dev, &sensor_mode_info_arry); + if (ret == 0) + { + copy_to_user(args, &sensor_mode_info_arry, sizeof(sensor_mode_info_arry)); + } + + break; + } + + case VVSENSORIOC_G_SENSOR_MODE: + { + copy_to_user(args, &(dev->sensor_mode), sizeof(struct vvcam_mode_info)); + break; + } + + default: + { + pr_err("unsupported command %d\n", cmd); + break; + } + + } + + return ret; +} + +static struct i2c_board_info i2c_info = { + //I2C_BOARD_INFO("OV2775", 0x6c>>1), + //I2C_BOARD_INFO("OV2775", 0x20>>1), + I2C_BOARD_INFO("OV5693", 0x6c>>1), +}; + +static int vvcam_register_i2c_client(struct vvcam_sensor_dev *dev) +{ + struct i2c_adapter *adap; + + //adap = i2c_get_adapter(dev->i2c_bus); + adap = i2c_get_adapter(1); + if (adap == NULL) + { + pr_err("[%s]:i2c_get_adapter i2c_bus %d failed\n",__func__,dev->i2c_bus); + return -1; + } + dev->i2c_client = i2c_new_device(adap, &i2c_info); + + i2c_put_adapter(adap); + + if (dev->i2c_client == NULL) + { + pr_err("[%s]:i2c_new_device i2c_bus %d failed\n",__func__,dev->i2c_bus); + return -1; + } + + return 0; +} + +static void vvcam_unregister_i2c_client(struct vvcam_sensor_dev *dev) +{ + i2c_unregister_device(dev->i2c_client); +} + +int vvnative_sensor_init(struct vvcam_sensor_dev *dev) +{ + int ret = 0; + + dev->sensor_sccb_cfg.slave_addr = 0x6c >> 1; + //dev->sensor_sccb_cfg.slave_addr = 0x20 >> 1; + dev->sensor_sccb_cfg.addr_byte = 2; + dev->sensor_sccb_cfg.data_byte = 1; + + if (dev->device_idx == 0) + { + dev->i2c_bus = 1; + memcpy(&(dev->sensor_func),&(SENSR0_FUNCTION),sizeof(struct vvcam_sensor_function_s)); + + }else + { + dev->i2c_bus = 1; + memcpy(&(dev->sensor_func),&(SENSR1_FUNCTION),sizeof(struct vvcam_sensor_function_s)); + } + + ret = vvcam_register_i2c_client(dev); + if (ret != 0) + { + pr_err("[%s]: vvcam_register_i2c_client sensor_idx = %d failed\n",__func__,dev->device_idx); + return -1; + } + + return ret; +} + +int vvnative_sensor_deinit(struct vvcam_sensor_dev *dev) +{ + int ret = 0; + + vvcam_unregister_i2c_client(dev); + + return ret; +} diff --git a/vvcam_ry/native/sensor/sony_imx290/imx290_driver.c b/vvcam_ry/native/sensor/sony_imx290/imx290_driver.c new file mode 100755 index 0000000..a879014 --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx290/imx290_driver.c @@ -0,0 +1,406 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "imx290_reg_cfg.h" + +#define SENSOR_CLK 51000000 + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + ret = sensor_read_reg(ctx, 0x31dc, &chip_id_high); + + *chip_id = (chip_id_high & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct sensor_mode_s * psensor_mode) +{ + int32_t ret = 0; + if (!ctx || !psensor_mode) + { + return -1; + } + + if((psensor_mode->max_fps == 30) && + (psensor_mode->width == 1920) && + (psensor_mode->height == 1080) && + (psensor_mode->hdr_mode == SENSOR_MODE_LINEAR)) + { + ret = sensor_write_reg_arry(ctx,&imx290_mipi4lane_1080p_30fps_linear_arry); + if (ret != 0) + { + return -1; + } + psensor_mode->cur_fps = psensor_mode->max_fps; + psensor_mode->ae_info.DefaultFrameLengthLines = 0x4705; + psensor_mode->ae_info.CurFrameLengthLines = psensor_mode->ae_info.DefaultFrameLengthLines; + psensor_mode->ae_info.one_line_exp_time_ns = 69607;//ns + psensor_mode->ae_info.max_integration_time = psensor_mode->ae_info.CurFrameLengthLines -4; + psensor_mode->ae_info.min_integration_time = 1; + psensor_mode->ae_info.gain_accuracy = 1024; + psensor_mode->ae_info.max_gain = 22 * psensor_mode->ae_info.gain_accuracy; + psensor_mode->ae_info.min_gain = 3 * psensor_mode->ae_info.gain_accuracy; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3000, 0x00); + }else + { + ret = sensor_write_reg(ctx, 0x3000, 0x01); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, struct sensor_mode_s *psensor_mode, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + + + if (psensor_mode->hdr_mode == SENSOR_MODE_LINEAR) + { + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + } + else if (psensor_mode->hdr_mode == SENSOR_HDR_MODE_3DOL) + { + hcg_gain = gain; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, struct sensor_mode_s *psensor_mode, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, struct sensor_mode_s *psensor_mode, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + + if (fps > psensor_mode->max_fps) + { + return -1; + } + FrameLengthLines = psensor_mode->max_fps * psensor_mode->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != psensor_mode->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + psensor_mode->ae_info.CurFrameLengthLines = FrameLengthLines; + psensor_mode->ae_info.max_integration_time = FrameLengthLines-3; + psensor_mode->cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, struct sensor_mode_s *psensor_mode, + uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, struct sensor_mode_s *psensor_mode, uint32_t hdr_mode) +{ + int32_t ret = 0; + if (hdr_mode == psensor_mode->hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + ret = sensor_write_reg(ctx, 0x3190, 0x08); + } + else if(hdr_mode == SENSOR_HDR_MODE_2DOL) + { + ret = -1; + } + else if(hdr_mode == SENSOR_HDR_MODE_3DOL) + { + ret = sensor_write_reg(ctx, 0x3190, 0x05); + } + return ret; +} + +struct vvcam_sensor_function_s imx290_function = +{ + .sensor_name = "imx290", + .reserve_id = 0x290, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + .mipi_info.sensor_data_bit = 12, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, +}; diff --git a/vvcam_ry/native/sensor/sony_imx290/imx290_driver.h b/vvcam_ry/native/sensor/sony_imx290/imx290_driver.h new file mode 100755 index 0000000..89d7626 --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx290/imx290_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OMNIVISION_IMX290_H_ +#define _OMNIVISION_IMX290_H_ + +extern struct vvcam_sensor_function_s imx290_function; + + +#endif diff --git a/vvcam_ry/native/sensor/sony_imx290/imx290_mipi4lane_1080p_30fps_linear.c b/vvcam_ry/native/sensor/sony_imx290/imx290_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..8b41158 --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx290/imx290_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data imx290_mipi4lane_1080p_30fps_linear_reg[] = { + {0x3000, 0x01}, + {0x3002, 0x01}, + {0x3005, 0x01}, + {0x3129, 0x00}, + {0x317c, 0x00}, + {0x31ec, 0x0e}, + {0x3441, 0x0c}, + {0x3442, 0x0c}, + {0x3007, 0x00}, + {0x300c, 0x00}, + {0x300f, 0x00}, + {0x3010, 0x21}, + {0x3012, 0x64}, + {0x3016, 0x09}, + {0x3017, 0x00}, + {0x3009, 0x12}, + {0x3014, 0x0b}, + {0x3018, 0x47}, + {0x3019, 0x05}, + {0x3020, 0x01}, + {0x3021, 0x00}, + {0x3024, 0x00}, + {0x3025, 0x00}, + {0x3028, 0x00}, + {0x3029, 0x00}, + {0x3030, 0x00}, + {0x3031, 0x00}, + {0x3034, 0x00}, + {0x3035, 0x00}, + {0x305c, 0x18}, + {0x305d, 0x03}, + {0x305e, 0x20}, + {0x305f, 0x01}, + {0x3070, 0x02}, + {0x3071, 0x11}, + {0x309b, 0x10}, + {0x309c, 0x22}, + {0x30a2, 0x02}, + {0x30a6, 0x20}, + {0x30a8, 0x20}, + {0x30aa, 0x20}, + {0x30ac, 0x20}, + {0x30b0, 0x43}, + {0x3119, 0x9e}, + {0x311c, 0x1e}, + {0x311e, 0x08}, + {0x3128, 0x05}, + {0x313d, 0x83}, + {0x3150, 0x03}, + {0x317e, 0x00}, + {0x315e, 0x1a}, + {0x3164, 0x1a}, + {0x32b8, 0x50}, + {0x32b9, 0x10}, + {0x32ba, 0x00}, + {0x32bb, 0x04}, + {0x32c8, 0x50}, + {0x32c9, 0x10}, + {0x32ca, 0x00}, + {0x32cb, 0x04}, + {0x332c, 0xd3}, + {0x332d, 0x10}, + {0x332e, 0x0d}, + {0x3358, 0x06}, + {0x3359, 0xe1}, + {0x335a, 0x11}, + {0x3360, 0x1e}, + {0x3361, 0x61}, + {0x3362, 0x10}, + {0x33b0, 0x50}, + {0x33b2, 0x1a}, + {0x33b3, 0x04}, + {0x3414, 0x0a}, + {0x3418, 0x49}, + {0x3419, 0x04}, + {0x3444, 0x20}, + {0x3445, 0x25}, + {0x3446, 0x47}, + {0x3447, 0x00}, + {0x3448, 0x1f}, + {0x3449, 0x00}, + {0x344a, 0x17}, + {0x344b, 0x00}, + {0x344c, 0x0f}, + {0x344d, 0x00}, + {0x344e, 0x17}, + {0x344f, 0x00}, + {0x3450, 0x47}, + {0x3451, 0x00}, + {0x3452, 0x0f}, + {0x3453, 0x00}, + {0x3454, 0x0f}, + {0x3455, 0x00}, + {0x3480, 0x49}, + {0x3000, 0x00}, + {0x3002, 0x00}, + {0x304b, 0x0a}, +}; + +struct vvcam_sccb_array imx290_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(imx290_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = imx290_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam_ry/native/sensor/sony_imx290/imx290_reg_cfg.h b/vvcam_ry/native/sensor/sony_imx290/imx290_reg_cfg.h new file mode 100755 index 0000000..6f22812 --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx290/imx290_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _IMX290_REG_CFG_H_ +#define _IMX290_REG_CFG_H_ + +extern struct vvcam_sccb_array imx290_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam_ry/native/sensor/sony_imx327/imx327_driver.c b/vvcam_ry/native/sensor/sony_imx327/imx327_driver.c new file mode 100755 index 0000000..c6369fa --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx327/imx327_driver.c @@ -0,0 +1,449 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "imx327_reg_cfg.h" + +#define SENSOR_CLK 37125000 + +static struct vvcam_mode_info pimx327_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_arry *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pimx327_mode_info); + + memcpy(pmode_info_arry->modes,pimx327_mode_info,sizeof(pimx327_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + //ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + //ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + //*chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pimx327_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pimx327_mode_info[i].index == pmode->index) + { + psensor_mode = &(pimx327_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&imx327_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.MaxFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.MaxFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.interrgation_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&imx327_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.MaxFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.MaxFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.interrgation_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3002, 0x00); + ret = sensor_write_reg(ctx, 0x3000, 0x00); + }else + { + ret = sensor_write_reg(ctx, 0x3000, 0x01); + ret = sensor_write_reg(ctx, 0x3002, 0x01); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + //ret = sensor_write_reg(ctx, 0x3467, 0x00); + //ret |= sensor_write_reg(ctx, 0x3464, 0x04); +// ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + //ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + //ret |= sensor_write_reg(ctx, 0x3464, 0x14); + //ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + //ret = sensor_write_reg(ctx, 0x3467, 0x00); + //ret |= sensor_write_reg(ctx, 0x3464, 0x04); + //ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + //ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + //ret |= sensor_write_reg(ctx, 0x3464, 0x14); + //ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + // ret = sensor_write_reg(ctx, 0x3467, 0x00); + /// ret |= sensor_write_reg(ctx, 0x3464, 0x04); + // ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + // ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + // ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + // ret |= sensor_write_reg(ctx, 0x3464, 0x14); + // ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + // hcg_gain = gain * hdr_radio / 11; + // sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + // lcg_gain = gain; + /// sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + +// ret = sensor_read_reg(ctx, 0x30bb, ®_val); +// reg_val &= ~0x0f; +/// reg_val |= (lcg_again<<2)&0x03; +/// reg_val |= hcg_again & 0x03; +/// +/// ret = sensor_write_reg(ctx, 0x3467, 0x00); +// ret |= sensor_write_reg(ctx, 0x3464, 0x04); +// +// ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); +// ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); +// +// ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); +// ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); +// +/// ret |= sensor_write_reg(ctx, 0x30bb, reg_val); +// ret |= sensor_write_reg(ctx, 0x3464, 0x14); +// ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + +// reg_val &= ~0x30; +// reg_val |= (again & 0x03) << 4; +// ret = sensor_write_reg(ctx, 0x3467, 0x00); +// ret |= sensor_write_reg(ctx, 0x3464, 0x04); +/// ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); +// ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); +// ret |= sensor_write_reg(ctx, 0x30bb, reg_val); +// ret |= sensor_write_reg(ctx, 0x3464, 0x14); +// ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.MaxFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { +// ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); +// ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + // ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + // ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s imx327_function = +{ + .sensor_name = "imx327", + .reserve_id = 0x327, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam_ry/native/sensor/sony_imx327/imx327_driver.h b/vvcam_ry/native/sensor/sony_imx327/imx327_driver.h new file mode 100755 index 0000000..d2c7016 --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx327/imx327_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _SONY_IMX327_H_ +#define _SONY_IMX327_H_ + +extern struct vvcam_sensor_function_s imx327_function; + + +#endif diff --git a/vvcam_ry/native/sensor/sony_imx327/imx327_mipi4lane_1080p_30fps_linear.c b/vvcam_ry/native/sensor/sony_imx327/imx327_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..b47475b --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx327/imx327_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data imx327_mipi4lane_1080p_30fps_linear_reg[] = { + +{0x3000, 0x01}, +{0x3001, 0x00}, +{0x3002, 0x01}, +{0x3003, 0x00}, +{0x300C, 0x3B}, +{0x300D, 0x2A}, +{0x3030, 0xc4}, +{0x3031, 0x1c}, +{0x3034, 0xEC}, +{0x3035, 0x0a}, +{0x3058, 0x72}, +{0x3059, 0x06}, +{0x30E8, 0x14}, +{0x314C, 0x29}, +{0x314D, 0x01}, +{0x315A, 0x03}, +{0x3168, 0xA0}, +{0x316A, 0x7E}, +{0x31A1, 0x00}, +{0x3288, 0x21}, +{0x328A, 0x02}, +{0x3414, 0x05}, +{0x3416, 0x18}, +{0x35AC, 0x0E}, +{0x3648, 0x01}, +{0x364A, 0x04}, +{0x364C, 0x04}, +{0x3678, 0x01}, +{0x367C, 0x31}, +{0x367E, 0x31}, +{0x3708, 0x02}, +{0x3714, 0x01}, +{0x3715, 0x02}, +{0x3716, 0x02}, +{0x3717, 0x02}, +{0x371C, 0x3D}, +{0x371D, 0x3F}, +{0x372C, 0x00}, +{0x372D, 0x00}, +{0x372E, 0x46}, +{0x372F, 0x00}, +{0x3730, 0x89}, +{0x3731, 0x00}, +{0x3732, 0x08}, +{0x3733, 0x01}, +{0x3734, 0xFE}, +{0x3735, 0x05}, +{0x375D, 0x00}, +{0x375E, 0x00}, +{0x375F, 0x61}, +{0x3760, 0x06}, +{0x3768, 0x1B}, +{0x3769, 0x1B}, +{0x376A, 0x1A}, +{0x376B, 0x19}, +{0x376C, 0x18}, +{0x376D, 0x14}, +{0x376E, 0x0F}, +{0x3776, 0x00}, +{0x3777, 0x00}, +{0x3778, 0x46}, +{0x3779, 0x00}, +{0x377A, 0x08}, +{0x377B, 0x01}, +{0x377C, 0x45}, +{0x377D, 0x01}, +{0x377E, 0x23}, +{0x377F, 0x02}, +{0x3780, 0xD9}, +{0x3781, 0x03}, +{0x3782, 0xF5}, +{0x3783, 0x06}, +{0x3784, 0xA5}, +{0x3788, 0x0F}, +{0x378A, 0xD9}, +{0x378B, 0x03}, +{0x378C, 0xEB}, +{0x378D, 0x05}, +{0x378E, 0x87}, +{0x378F, 0x06}, +{0x3790, 0xF5}, +{0x3792, 0x43}, +{0x3794, 0x7A}, +{0x3796, 0xA1}, +{0x3E04, 0x0E}, +}; + +struct vvcam_sccb_array imx327_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(imx327_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = imx327_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam_ry/native/sensor/sony_imx327/imx327_reg_cfg.h b/vvcam_ry/native/sensor/sony_imx327/imx327_reg_cfg.h new file mode 100755 index 0000000..1cf0c67 --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx327/imx327_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _IMX327_REG_CFG_H_ +#define _IMX327_REG_CFG_H_ + +extern struct vvcam_sccb_array imx327_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam_ry/native/sensor/sony_imx334/imx334_driver.c b/vvcam_ry/native/sensor/sony_imx334/imx334_driver.c new file mode 100755 index 0000000..f78965e --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx334/imx334_driver.c @@ -0,0 +1,494 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "vvsensor.h" +#include "sensor_common.h" +#include "imx334_reg_cfg.h" + +#define SENSOR_CLK 74250000 + +static struct vvcam_mode_info pimx334_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_3DOL, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + }, + { + .index = 2, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_GBRG, + } +}; + + +static int32_t sensor_query(void *ctx, struct vvcam_mode_info_array *pmode_info_arry) +{ + if (!pmode_info_arry) + { + return -1; + } + pmode_info_arry->count = ARRAY_SIZE(pimx334_mode_info); + + memcpy(pmode_info_arry->modes,pimx334_mode_info,sizeof(pimx334_mode_info)); + + return 0; +} + +static int32_t sensor_write_reg(void *ctx, uint32_t reg, uint32_t val) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_write(dev, reg, val); + + return ret; +} +static int32_t sensor_read_reg(void *ctx, uint32_t reg, uint32_t *pval) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + ret = vvcam_sensor_i2c_read(dev, reg, pval); + + return ret; +} + +static int32_t sensor_write_reg_arry(void *ctx, struct vvcam_sccb_array *parray) +{ + int32_t ret = 0; + int32_t index = 0; + struct vvcam_sensor_dev *dev = ctx; + + for (index = 0; index < parray->count; index++) + { + ret = vvcam_sensor_i2c_write(dev, parray->sccb_data[index].addr, parray->sccb_data[index].data); + if (ret != 0) + { + return ret; + } + } + + return ret; +} + +static int32_t sensor_get_chip_id(void *ctx, uint32_t *chip_id) +{ + int32_t ret = 0; + int32_t chip_id_high = 0; + int32_t chip_id_low = 0; + ret = sensor_read_reg(ctx, 0x300a, &chip_id_high); + ret |= sensor_read_reg(ctx, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + + return ret; +} + +static int32_t sensor_init(void *ctx, struct vvcam_mode_info *pmode) +{ + int32_t ret = 0; + int32_t i = 0; + struct vvcam_sensor_dev *dev = ctx; + struct vvcam_mode_info *psensor_mode = NULL; + + for (i=0; i < sizeof(pimx334_mode_info)/ sizeof(struct vvcam_mode_info); i++) + { + if (pimx334_mode_info[i].index == pmode->index) + { + psensor_mode = &(pimx334_mode_info[i]); + break; + } + } + + if (psensor_mode == NULL) + { + return -1; + } + + memcpy(&(dev->sensor_mode),psensor_mode,sizeof(struct vvcam_mode_info)); + + switch(dev->sensor_mode.index) + { + case 0: + ret = sensor_write_reg_arry(ctx,&imx334_mipi4lane_1080p_30fps_linear_arry); + + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + case 1: + ret = sensor_write_reg_arry(ctx,&imx334_mipi4lane_1080p_30fps_linear_arry); + dev->ae_info.DefaultFrameLengthLines = 0x466; + dev->ae_info.CurFrameLengthLines = dev->ae_info.DefaultFrameLengthLines; + dev->ae_info.one_line_exp_time_ns = 69607;//ns + + dev->ae_info.max_integration_time = dev->ae_info.CurFrameLengthLines -4; + dev->ae_info.min_integration_time = 1; + dev->ae_info.integration_accuracy = 1; + + dev->ae_info.gain_accuracy = 1024; + dev->ae_info.max_gain = 22 * dev->ae_info.gain_accuracy; + dev->ae_info.min_gain = 3 * dev->ae_info.gain_accuracy; + + dev->ae_info.cur_fps = dev->sensor_mode.fps; + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_stream(void *ctx, uint32_t status) +{ + int32_t ret = 0; + if (status) + { + ret = sensor_write_reg(ctx, 0x3002, 0x00); + ret = sensor_write_reg(ctx, 0x3000, 0x00); + }else + { + ret = sensor_write_reg(ctx, 0x3000, 0x01); + ret = sensor_write_reg(ctx, 0x3002, 0x01); + } + + return ret; +} + +static int32_t sensor_set_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b6, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b7, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; +} + +static int32_t sensor_set_vs_exp(void *ctx, uint32_t exp_line) +{ + int32_t ret = 0; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x30b8, (exp_line>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b9, exp_line & 0xff); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + return ret; + +} + +static int32_t sensor_calc_gain(uint32_t total_gain, uint32_t *pagain, uint32_t *pdgain, uint32_t *phcg) +{ + uint32_t sensor_gain; + + sensor_gain = total_gain; + + if(sensor_gain <= 3072)// 3 * gain_accuracy + { + sensor_gain = 3072; + } + else if((sensor_gain >= 22528) && (sensor_gain < 23552)) //gain >22*gain_accuracy && gain < 23*gain_accuracy + { + sensor_gain = 22528; + } + + if (sensor_gain < 4480) //gain < 4.375 * gain_accuracy + { + *pagain = 1; + *phcg = 1; + } + else if(sensor_gain < 8960)//gain < 8.75 * gain_accuracy + { + *pagain = 2; + *phcg = 1; + } + else if(sensor_gain < 22528)//gain < 22 * gain_accuracy + { + *pagain = 3; + *phcg = 1; + } + else if(sensor_gain < 44990)//gain < 44 * gain_accuracy + { + *pagain = 0; + *phcg = 11; + } + else if (sensor_gain < 89320)//gain < 88 * gain_accuracy + { + *pagain = 1; + *phcg = 11; + } + else if (sensor_gain < 179498)//gain < 176 * gain_accuracy + { + *pagain = 2; + *phcg = 11; + }else + { + *pagain = 3; + *phcg = 11; + } + *pdgain = ((sensor_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; + +} + +static int32_t sensor_set_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t hcg = 1; + + uint32_t hcg_gain; + uint32_t lcg_gain; + + uint32_t hcg_again = 0; + uint32_t hcg_dgain = 0; + uint32_t lcg_again = 0; + uint32_t lcg_dgain = 0; + + uint32_t reg_val = 0; + uint32_t hdr_radio; + + struct vvcam_sensor_dev *dev = ctx; + + hdr_radio= dev->ae_info.hdr_radio; + + switch(dev->sensor_mode.index) + { + case 0: + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + if (hcg == 1) + { + reg_val &= ~(1<<6); //LCG + }else + { + reg_val |= (1<<6); //HCG + } + reg_val &= ~0x03; + reg_val |= again; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315a, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + case 1: + hcg_gain = gain * hdr_radio / 11; + sensor_calc_gain(gain, &hcg_again, &hcg_dgain, &hcg); + lcg_gain = gain; + sensor_calc_gain(gain, &lcg_again, &lcg_dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + reg_val &= ~0x0f; + reg_val |= (lcg_again<<2)&0x03; + reg_val |= hcg_again & 0x03; + + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + + ret |= sensor_write_reg(ctx, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315b, hcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315d, lcg_dgain & 0xff); + + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + break; + default: + break; + } + + return ret; +} + +static int32_t sensor_set_vs_gain(void *ctx, uint32_t gain) +{ + int32_t ret = 0; + uint32_t again = 0; + uint32_t dgain = 0; + uint32_t sensor_gain; + uint32_t hcg = 1; + uint32_t reg_val = 0; + + sensor_gain = gain; + + sensor_calc_gain(gain, &again, &dgain, &hcg); + + ret = sensor_read_reg(ctx, 0x30bb, ®_val); + + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + ret = sensor_write_reg(ctx, 0x3467, 0x00); + ret |= sensor_write_reg(ctx, 0x3464, 0x04); + ret |= sensor_write_reg(ctx, 0x315e, (dgain>>8) & 0xff); + ret |= sensor_write_reg(ctx, 0x315f, dgain & 0xff); + ret |= sensor_write_reg(ctx, 0x30bb, reg_val); + ret |= sensor_write_reg(ctx, 0x3464, 0x14); + ret |= sensor_write_reg(ctx, 0x3467, 0x01); + + return ret; + +} + +static int32_t sensor_set_fps(void *ctx, uint32_t fps) +{ + int32_t ret = 0; + uint32_t FrameLengthLines = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (fps > dev->sensor_mode.fps) + { + return -1; + } + FrameLengthLines = dev->sensor_mode.fps * dev->ae_info.DefaultFrameLengthLines / fps; + + if (FrameLengthLines != dev->ae_info.CurFrameLengthLines) + { + ret = sensor_write_reg(ctx, 0x30b2, (FrameLengthLines >> 8) & 0xff); + ret |= sensor_write_reg(ctx, 0x30b3, FrameLengthLines & 0xff); + if (ret != 0) + { + return -1; + } + dev->ae_info.CurFrameLengthLines = FrameLengthLines; + dev->ae_info.max_integration_time = FrameLengthLines-3; + dev->ae_info.cur_fps = fps; + } + return ret; +} + +static int32_t sensor_set_resolution(void *ctx, uint32_t width, uint32_t height) +{ + return 0; +} + +static int32_t sensor_set_hdr_mode(void *ctx, uint32_t hdr_mode) +{ + int32_t ret = 0; + struct vvcam_sensor_dev *dev = ctx; + + if (hdr_mode == dev->sensor_mode.hdr_mode) + { + return 0; + } + if (hdr_mode == SENSOR_MODE_LINEAR) + { + // ret = sensor_write_reg(ctx, 0x3190, 0x08); + dev->sensor_mode.hdr_mode = SENSOR_MODE_LINEAR; + } + else if(hdr_mode == SENSOR_MODE_HDR_STITCH) + { + // ret = sensor_write_reg(ctx, 0x3190, 0x05); + dev->sensor_mode.hdr_mode = SENSOR_MODE_HDR_STITCH; + } + return ret; +} + +struct vvcam_sensor_function_s imx334_function = +{ + .sensor_name = "imx334", + .reserve_id = 0x334, + .sensor_clk = SENSOR_CLK, + .mipi_info.mipi_lane = 4, + + .sensor_get_chip_id = sensor_get_chip_id, + .sensor_init = sensor_init, + .sensor_set_stream = sensor_set_stream, + .sensor_set_exp = sensor_set_exp, + .sensor_set_vs_exp = sensor_set_vs_exp, + .sensor_set_gain = sensor_set_gain, + .sensor_set_vs_gain = sensor_set_vs_gain, + .sensor_set_fps = sensor_set_fps, + .sensor_set_resolution = sensor_set_resolution, + .sensor_set_hdr_mode = sensor_set_hdr_mode, + .sensor_query = sensor_query, +}; diff --git a/vvcam_ry/native/sensor/sony_imx334/imx334_driver.h b/vvcam_ry/native/sensor/sony_imx334/imx334_driver.h new file mode 100755 index 0000000..104f95f --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx334/imx334_driver.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _OMNIVISION_IMX334_H_ +#define _OMNIVISION_IMX334_H_ + +extern struct vvcam_sensor_function_s imx334_function; + + +#endif diff --git a/vvcam_ry/native/sensor/sony_imx334/imx334_mipi4lane_1080p_30fps_linear.c b/vvcam_ry/native/sensor/sony_imx334/imx334_mipi4lane_1080p_30fps_linear.c new file mode 100755 index 0000000..c4ed859 --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx334/imx334_mipi4lane_1080p_30fps_linear.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include "vvsensor.h" +#include "sensor_common.h" + + +struct vvcam_sccb_data imx334_mipi4lane_1080p_30fps_linear_reg[] = { + +{0x3000, 0x01}, +{0x3001, 0x00}, +{0x3002, 0x01}, +{0x3003, 0x00}, +{0x300C, 0x3B}, +{0x300D, 0x2A}, +{0x3030, 0xc4}, +{0x3031, 0x1c}, +{0x3034, 0xEC}, +{0x3035, 0x0a}, +{0x3058, 0x72}, +{0x3059, 0x06}, +{0x30E8, 0x14}, +{0x314C, 0x29}, +{0x314D, 0x01}, +{0x315A, 0x03}, +{0x3168, 0xA0}, +{0x316A, 0x7E}, +{0x31A1, 0x00}, +{0x3288, 0x21}, +{0x328A, 0x02}, +{0x3414, 0x05}, +{0x3416, 0x18}, +{0x35AC, 0x0E}, +{0x3648, 0x01}, +{0x364A, 0x04}, +{0x364C, 0x04}, +{0x3678, 0x01}, +{0x367C, 0x31}, +{0x367E, 0x31}, +{0x3708, 0x02}, +{0x3714, 0x01}, +{0x3715, 0x02}, +{0x3716, 0x02}, +{0x3717, 0x02}, +{0x371C, 0x3D}, +{0x371D, 0x3F}, +{0x372C, 0x00}, +{0x372D, 0x00}, +{0x372E, 0x46}, +{0x372F, 0x00}, +{0x3730, 0x89}, +{0x3731, 0x00}, +{0x3732, 0x08}, +{0x3733, 0x01}, +{0x3734, 0xFE}, +{0x3735, 0x05}, +{0x375D, 0x00}, +{0x375E, 0x00}, +{0x375F, 0x61}, +{0x3760, 0x06}, +{0x3768, 0x1B}, +{0x3769, 0x1B}, +{0x376A, 0x1A}, +{0x376B, 0x19}, +{0x376C, 0x18}, +{0x376D, 0x14}, +{0x376E, 0x0F}, +{0x3776, 0x00}, +{0x3777, 0x00}, +{0x3778, 0x46}, +{0x3779, 0x00}, +{0x377A, 0x08}, +{0x377B, 0x01}, +{0x377C, 0x45}, +{0x377D, 0x01}, +{0x377E, 0x23}, +{0x377F, 0x02}, +{0x3780, 0xD9}, +{0x3781, 0x03}, +{0x3782, 0xF5}, +{0x3783, 0x06}, +{0x3784, 0xA5}, +{0x3788, 0x0F}, +{0x378A, 0xD9}, +{0x378B, 0x03}, +{0x378C, 0xEB}, +{0x378D, 0x05}, +{0x378E, 0x87}, +{0x378F, 0x06}, +{0x3790, 0xF5}, +{0x3792, 0x43}, +{0x3794, 0x7A}, +{0x3796, 0xA1}, +{0x3E04, 0x0E}, +}; + +struct vvcam_sccb_array imx334_mipi4lane_1080p_30fps_linear_arry = { + .count = sizeof(imx334_mipi4lane_1080p_30fps_linear_reg) / sizeof(struct vvcam_sccb_data), + .sccb_data = imx334_mipi4lane_1080p_30fps_linear_reg, +}; diff --git a/vvcam_ry/native/sensor/sony_imx334/imx334_reg_cfg.h b/vvcam_ry/native/sensor/sony_imx334/imx334_reg_cfg.h new file mode 100755 index 0000000..8cdf80f --- /dev/null +++ b/vvcam_ry/native/sensor/sony_imx334/imx334_reg_cfg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _IMX334_REG_CFG_H_ +#define _IMX334_REG_CFG_H_ + +extern struct vvcam_sccb_array imx334_mipi4lane_1080p_30fps_linear_arry; + +#endif diff --git a/vvcam_ry/native/sensor/vvcam_sensor_driver.c b/vvcam_ry/native/sensor/vvcam_sensor_driver.c new file mode 100755 index 0000000..f08d995 --- /dev/null +++ b/vvcam_ry/native/sensor/vvcam_sensor_driver.c @@ -0,0 +1,341 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vvsensor.h" +#include "sensor_common.h" + +#define VIVCAM_SENSOR_NAME "vivcam" +#define VIVCAM_SENSOR_MAXCNT 2 + + +struct vvcam_sensor_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + void *private; +}; + +static unsigned int vvcam_sensor_major = 0; +static unsigned int vvcam_sensor_minor = 0; +struct class *vvcam_sensor_class; +static unsigned int devise_register_index = 0; + + +static int vvcam_sensor_open(struct inode * inode, struct file * file) +{ + struct vvcam_sensor_driver_dev *pdriver_dev; + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_sensor_driver_dev, cdev); + file->private_data = pdriver_dev; + + return 0; +}; + +static long vvcam_sensor_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vvcam_sensor_driver_dev *pdriver_dev; + struct vvcam_sensor_dev * psensor_dev; + + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + psensor_dev = pdriver_dev->private; + pr_info("%s:pdriver_dev =0x%p\n", __func__,pdriver_dev); + pr_info("%s:sensor[%d] psensor_dev =0x%p\n", __func__,psensor_dev->device_idx,psensor_dev); + + mutex_lock(&pdriver_dev->vvmutex); + ret = sensor_priv_ioctl(psensor_dev, cmd ,(void *)arg); + mutex_unlock(&pdriver_dev->vvmutex); + + return ret; +}; + +static int vvcam_sensor_release(struct inode * inode, struct file * file) +{ + return 0; +}; + +struct file_operations vvcam_sensor_fops = { + .owner = THIS_MODULE, + .open = vvcam_sensor_open, + .release = vvcam_sensor_release, + .unlocked_ioctl = vvcam_sensor_ioctl, +}; + +static int vvcam_sensor_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vvcam_sensor_driver_dev *pdriver_dev; + struct vvcam_sensor_dev * psensor_dev; + + pr_info("enter %s\n", __func__); + + if (pdev->id >= VIVCAM_SENSOR_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_sensor_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_sensor_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_sensor_driver_dev )); + pr_info("%s:sensor[%d]: pdriver_dev =0x%p\n", __func__,pdev->id,pdriver_dev); + + psensor_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_sensor_dev), GFP_KERNEL); + if (psensor_dev == NULL) + { + pr_err("%s:alloc struct vvcam_sensor_dev error\n", __func__); + return -ENOMEM; + } + memset(psensor_dev,0,sizeof(struct vvcam_sensor_dev )); + pr_info("%s:sensor[%d]: psensor_dev =0x%p\n", __func__,pdev->id,psensor_dev); + psensor_dev->device_idx = pdev->id; + + ret = vvnative_sensor_init(psensor_dev); + if (ret != 0) + { + pr_err("%s:vvnative_sensor_init error\n", __func__); + return -EIO; + } + + pdriver_dev->private = psensor_dev; + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + + if (devise_register_index == 0) + { + if (vvcam_sensor_major == 0) + { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_SENSOR_MAXCNT, VIVCAM_SENSOR_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_sensor_major = MAJOR(pdriver_dev->devt); + vvcam_sensor_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_sensor_major, vvcam_sensor_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_SENSOR_MAXCNT, VIVCAM_SENSOR_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + vvcam_sensor_class = class_create(THIS_MODULE, VIVCAM_SENSOR_NAME); + if (IS_ERR(vvcam_sensor_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_sensor_major, vvcam_sensor_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_sensor_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_sensor_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VIVCAM_SENSOR_NAME, pdev->id); + + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int vvcam_sensor_remove(struct platform_device *pdev) +{ + struct vvcam_sensor_driver_dev *pdriver_dev; + struct vvcam_sensor_dev * psensor_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + psensor_dev = pdriver_dev->private; + vvnative_sensor_deinit(psensor_dev); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_SENSOR_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + + return 0; +} + +static struct platform_driver vvcam_sensor_driver = { + .probe = vvcam_sensor_probe, + .remove = vvcam_sensor_remove, + .driver = { + .name = VIVCAM_SENSOR_NAME, + .owner = THIS_MODULE, + } +}; + +static void vvcam_sensor_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +#ifdef WITH_VVCAM +static struct platform_device vvcam_sensor_pdev = { + .name = VIVCAM_SENSOR_NAME, + .id = 0, + .dev.release = vvcam_sensor_pdev_release, +}; +#endif + +#ifdef WITH_VVCAM_DUAL +static struct platform_device vvcam_sensor_dual_pdev = { + .name = VIVCAM_SENSOR_NAME, + .id = 1, + .dev.release = vvcam_sensor_pdev_release, +}; +#endif + +static int __init vvcam_sensor_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + +#ifdef WITH_VVCAM + ret = platform_device_register(&vvcam_sensor_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } +#endif + +#ifdef WITH_VVCAM_DUAL + ret = platform_device_register(&vvcam_sensor_dual_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } +#endif + + ret = platform_driver_register(&vvcam_sensor_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit vvcam_sensor_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_sensor_driver); + +#ifdef WITH_VVCAM + platform_device_unregister(&vvcam_sensor_pdev); +#endif + +#ifdef WITH_VVCAM_DUAL + platform_device_unregister(&vvcam_sensor_dual_pdev); +#endif + +} + +module_init(vvcam_sensor_init_module); +module_exit(vvcam_sensor_exit_module); + +MODULE_DESCRIPTION("SENSOR"); +MODULE_LICENSE("GPL"); diff --git a/vvcam_ry/native/soc/Makefile b/vvcam_ry/native/soc/Makefile new file mode 100755 index 0000000..122a899 --- /dev/null +++ b/vvcam_ry/native/soc/Makefile @@ -0,0 +1,20 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vvcam_soc + +obj-m +=$(TARGET).o +$(TARGET)-objs += vvcam_soc_driver.o +$(TARGET)-objs += soc_ioctl.o +$(TARGET)-objs += vivsoc_hub.o +$(TARGET)-objs += vsi_core_gen6.o + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean + diff --git a/vvcam_ry/native/soc/soc_ioctl.c b/vvcam_ry/native/soc/soc_ioctl.c new file mode 100755 index 0000000..0cb5a3f --- /dev/null +++ b/vvcam_ry/native/soc/soc_ioctl.c @@ -0,0 +1,261 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef __KERNEL__ +#include +#include +#include +#include + +#define pr_info printf +#define pr_err printf +#define copy_from_user(a, b, c) soc_copy_data(a, b, c) +#define copy_to_user(a, b, c) soc_copy_data(a, b, c) +#define __user +#define __iomem + +void soc_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); +} + +#else // __KERNEL__ +#include /* Module support */ +#include + +#endif + +#include "soc_ioctl.h" +#include "vivsoc_hub.h" + + +long soc_priv_ioctl(struct vvcam_soc_dev *dev, unsigned int cmd, void __user *args) +{ + int ret = -1; + struct soc_control_context soc_ctrl; + if (!dev) { + return ret; + } + + switch (cmd) { + /* ISP part */ + case VVSOC_IOC_S_RESET_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* DWE part */ + case VVSOC_IOC_S_RESET_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* VSE part */ + case VVSOC_IOC_S_RESET_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + + /* CSI part */ + case VVSOC_IOC_S_RESET_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* sensor part */ + case VVSOC_IOC_S_RESET_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + + default: + pr_err("unsupported command %d", cmd); + break; + } + + return ret; +} + +extern struct vvcam_soc_function_s gen6_soc_function; + +int vvnative_soc_init(struct vvcam_soc_dev *dev) +{ + if (dev == NULL) + { + pr_err("[%s] dev is NULL\n", __func__); + return -1; + } + + vivsoc_register_hardware(dev, &gen6_soc_function); + return 0; +} + +int vvnative_soc_deinit(struct vvcam_soc_dev *dev) +{ + return 0; +} + + diff --git a/vvcam_ry/native/soc/soc_ioctl.h b/vvcam_ry/native/soc/soc_ioctl.h new file mode 100755 index 0000000..ed2c1d4 --- /dev/null +++ b/vvcam_ry/native/soc/soc_ioctl.h @@ -0,0 +1,158 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _SOC_IOC_H_ +#define _SOC_IOC_H_ + +#ifndef __KERNEL__ +#include +#endif + +#include + +enum { + VVSOC_IOC_S_RESET_ISP = _IO('r', 0), + VVSOC_IOC_S_POWER_ISP, + VVSOC_IOC_G_POWER_ISP, + VVSOC_IOC_S_CLOCK_ISP, + VVSOC_IOC_G_CLOCK_ISP, + + VVSOC_IOC_S_RESET_DWE, + VVSOC_IOC_S_POWER_DWE, + VVSOC_IOC_G_POWER_DWE, + VVSOC_IOC_S_CLOCK_DWE, + VVSOC_IOC_G_CLOCK_DWE, + + VVSOC_IOC_S_RESET_VSE, + VVSOC_IOC_S_POWER_VSE, + VVSOC_IOC_G_POWER_VSE, + VVSOC_IOC_S_CLOCK_VSE, + VVSOC_IOC_G_CLOCK_VSE, + + VVSOC_IOC_S_RESET_CSI, + VVSOC_IOC_S_POWER_CSI, + VVSOC_IOC_G_POWER_CSI, + VVSOC_IOC_S_CLOCK_CSI, + VVSOC_IOC_G_CLOCK_CSI, + + VVSOC_IOC_S_RESET_SENSOR, + VVSOC_IOC_S_POWER_SENSOR, + VVSOC_IOC_G_POWER_SENSOR, + VVSOC_IOC_S_CLOCK_SENSOR, + VVSOC_IOC_G_CLOCK_SENSOR, + + VVSOC_IOC_S_RESET_ISP_RY, + VVSOC_IOC_S_POWER_ISP_RY, + VVSOC_IOC_G_POWER_ISP_RY, + VVSOC_IOC_S_CLOCK_ISP_RY, + VVSOC_IOC_G_CLOCK_ISP_RY, + + VVSOC_IOC_MAX, +}; + +struct soc_control_context { + uint32_t device_idx; + uint32_t control_value; +}; + +struct vvcam_soc_func_s +{ + int (*set_power)(void*,unsigned int,unsigned int); + int (*get_power)(void*,unsigned int,unsigned int *); + int (*set_reset)(void*,unsigned int,unsigned int); + int (*set_clk)(void*,unsigned int,unsigned int); + int (*get_clk)(void*,unsigned int,unsigned int *); +}; + +struct vvcam_soc_function_s +{ + struct vvcam_soc_func_s isp_func; + struct vvcam_soc_func_s dwe_func; + struct vvcam_soc_func_s vse_func; + struct vvcam_soc_func_s csi_func; + struct vvcam_soc_func_s sensor_func; +}; + +struct vvcam_soc_access_s +{ + int (*write)(void * ctx, uint32_t address, uint32_t data); + int (*read)(void * ctx, uint32_t address, uint32_t *data); +}; + + +#ifdef __KERNEL__ + +struct vvcam_soc_dev { + void __iomem *base; + struct soc_control_context isp0; + struct soc_control_context isp1; + struct soc_control_context dwe; + struct soc_control_context vse; + struct vvcam_soc_function_s soc_func; + struct vvcam_soc_access_s soc_access; + void * csi_private; +}; +// internal functions + +long soc_priv_ioctl(struct vvcam_soc_dev *dev, unsigned int cmd, void __user *args); +int vvnative_soc_init(struct vvcam_soc_dev *dev); +int vvnative_soc_deinit(struct vvcam_soc_dev *dev); + + + +#else +//User space connections + + +#endif + +#endif // _SOC_IOC_H_ diff --git a/vvcam_ry/native/soc/vivsoc_hub.c b/vvcam_ry/native/soc/vivsoc_hub.c new file mode 100755 index 0000000..12c2c26 --- /dev/null +++ b/vvcam_ry/native/soc/vivsoc_hub.c @@ -0,0 +1,586 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include + +#include "soc_ioctl.h" +#include "vivsoc_hub.h" +#include "vsi_core_gen6.h" + + +int vivsoc_hub_isp_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_dwe_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_vse_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_csi_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +unsigned int vivsoc_register_hardware(struct vvcam_soc_dev *dev, struct vvcam_soc_function_s *func) +{ + if (func == NULL) + { + return -1; + } + + memcpy(&dev->soc_func,func,sizeof(struct vvcam_soc_function_s)); + + dev->soc_access.write = gen6_write_reg; + dev->soc_access.read = gen6_read_reg; + + return 0; +} + + + + diff --git a/vvcam_ry/native/soc/vivsoc_hub.h b/vvcam_ry/native/soc/vivsoc_hub.h new file mode 100755 index 0000000..3c99805 --- /dev/null +++ b/vvcam_ry/native/soc/vivsoc_hub.h @@ -0,0 +1,88 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VIVSOC_HUB_H_ +#define _VIVSOC_HUB_H_ + +int vivsoc_hub_isp_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_dwe_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_vse_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_csi_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_sensor_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +unsigned int vivsoc_register_hardware(struct vvcam_soc_dev *dev, struct vvcam_soc_function_s *func); + +#endif /* _VIVSOC_HUB_H_ */ diff --git a/vvcam_ry/native/soc/vsi_core_gen6.c b/vvcam_ry/native/soc/vsi_core_gen6.c new file mode 100755 index 0000000..f018174 --- /dev/null +++ b/vvcam_ry/native/soc/vsi_core_gen6.c @@ -0,0 +1,362 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#if defined(ISP8000L_V2008) || defined(ISP8000_V2009) +#include //Fix thead compile error. +#endif + +#include "soc_ioctl.h" +#include "vsi_core_gen6.h" + + int gen6_write_reg(void* dev,unsigned int addr,unsigned int val) +{ + struct vvcam_soc_dev *soc_dev; + + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + writel(val,soc_dev->base + addr); + + return 0; +} + + int gen6_read_reg(void* dev,unsigned int addr,unsigned int *val) +{ + struct vvcam_soc_dev *soc_dev; + + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + *val = readl(soc_dev->base + addr); + + return 0; +} + + +static int gen6_set_isp_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_isp_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_isp_reset(void* dev,unsigned int id,unsigned int status) +{ + + unsigned int reg_addr; + unsigned int reg_value; + unsigned int ret; + struct vvcam_soc_dev *soc_dev;; + + reg_addr = 0; + ret = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + pr_info("isp reset enter id = %d, status = %d\n", id, status); + if (soc_dev == NULL) + return -1; + + if (id == 0) + { + reg_addr = REG_TPG0; + }else{ + reg_addr = REG_TPG1; + } + + reg_addr = 0x100; + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<0); + + }else{ + reg_value |= (1<<0); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + pr_info("isp reset exit\n"); + + return ret; +} + +static int gen6_set_isp_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_isp_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + +static int gen6_set_dwe_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_dwe_power(void* dev, unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_dwe_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + unsigned int reg_addr; + unsigned int reg_value; + struct vvcam_soc_dev *soc_dev; + pr_info("dw200 reset enter id = %d, status = %d\n", id, status); + + soc_dev = (struct vvcam_soc_dev *)dev; + reg_addr = 0; + if (soc_dev == NULL) + return -1; + + reg_addr = REG_DWE_CTRL; + reg_addr = 0x100; + + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<31); + }else{ + reg_value |= (1<<31); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + pr_info("dw200 reset exit\n"); + + return ret; +} + +static int gen6_set_dwe_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_dwe_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +static int gen6_set_vse_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_vse_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_vse_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev; + unsigned int reg_addr; + unsigned int reg_value; + + soc_dev = (struct vvcam_soc_dev *)dev; + reg_addr = 0; + if (soc_dev == NULL) + return -1; + + reg_addr = REG_VSE_CTRL; + + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<0); + }else{ + reg_value |= (1<<0); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + + return ret; +} + +static int gen6_set_vse_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_vse_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +static int gen6_set_csi_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_csi_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_csi_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev; + unsigned int reg_addr; + unsigned int reg_value; + + soc_dev = (struct vvcam_soc_dev *)dev; + reg_addr = 0; + if (soc_dev == NULL) + return -1; + + if (id == 0) + { + reg_addr = REG_TPG0; + }else{ + reg_addr = REG_TPG1; + } + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<4 | 1<<28); + }else{ + reg_value |= 0x30000210; + } + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + + return ret; +} + +static int gen6_set_csi_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_csi_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + +static int gen6_set_sensor_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_sensor_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_sensor_reset(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_set_sensor_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_sensor_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +struct vvcam_soc_function_s gen6_soc_function = { + .isp_func.set_power = gen6_set_isp_power, + .isp_func.get_power = gen6_get_isp_power, + .isp_func.set_reset = gen6_set_isp_reset, + .isp_func.set_clk = gen6_set_isp_clk, + .isp_func.get_clk = gen6_get_isp_clk, + + .dwe_func.set_power = gen6_set_dwe_power, + .dwe_func.get_power = gen6_get_dwe_power, + .dwe_func.set_reset = gen6_set_dwe_reset, + .dwe_func.set_clk = gen6_set_dwe_clk, + .dwe_func.get_clk = gen6_get_dwe_clk, + + .vse_func.set_power = gen6_set_vse_power, + .vse_func.get_power = gen6_get_vse_power, + .vse_func.set_reset = gen6_set_vse_reset, + .vse_func.set_clk = gen6_set_vse_clk, + .vse_func.get_clk = gen6_get_vse_clk, + + .csi_func.set_power = gen6_set_csi_power, + .csi_func.get_power = gen6_get_csi_power, + .csi_func.set_reset = gen6_set_csi_reset, + .csi_func.set_clk = gen6_set_csi_clk, + .csi_func.get_clk = gen6_get_csi_clk, + + .sensor_func.set_power = gen6_set_sensor_power, + .sensor_func.get_power = gen6_get_sensor_power, + .sensor_func.set_reset = gen6_set_sensor_reset, + .sensor_func.set_clk = gen6_set_sensor_clk, + .sensor_func.get_clk = gen6_get_sensor_clk, +}; + + + diff --git a/vvcam_ry/native/soc/vsi_core_gen6.h b/vvcam_ry/native/soc/vsi_core_gen6.h new file mode 100755 index 0000000..f1b6521 --- /dev/null +++ b/vvcam_ry/native/soc/vsi_core_gen6.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VSI_CORE_GEN6_H +#define _VSI_CORE_GEN6_H + + +#define REG_TPG0 0x300 +#define REG_TPG1 0x310 +#define REG_DWE_CTRL 0x250 +#define REG_VSE_CTRL 0x254 + + + +extern struct vvcam_soc_function_s gen6_soc_function; +int gen6_write_reg(void* dev,unsigned int addr,unsigned int val); +int gen6_read_reg(void* dev,unsigned int addr,unsigned int *val); + +#endif diff --git a/vvcam_ry/native/soc/vvcam_soc_driver.c b/vvcam_ry/native/soc/vvcam_soc_driver.c new file mode 100755 index 0000000..6ee3fcd --- /dev/null +++ b/vvcam_ry/native/soc/vvcam_soc_driver.c @@ -0,0 +1,308 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "soc_ioctl.h" + +#define VIVCAM_SOC_NAME "vivsoc" +#define VIVCAM_SOC_MAXCNT 2 + + +struct vvcam_soc_driver_dev +{ + struct cdev cdev; + dev_t devt; + struct class *class; + struct mutex vvmutex; + void *private; +}; + +static unsigned int vvcam_soc_major = 0; +static unsigned int vvcam_soc_minor = 0; +static struct class *vvcam_soc_class; +static unsigned int devise_register_index = 0; + + +static int vvcam_soc_open(struct inode * inode, struct file * file) +{ + struct vvcam_soc_driver_dev *pdriver_dev; + + pdriver_dev = container_of(inode->i_cdev, struct vvcam_soc_driver_dev, cdev); + file->private_data = pdriver_dev; + + return 0; +}; + +static long vvcam_soc_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vvcam_soc_driver_dev *pdriver_dev; + struct vvcam_soc_dev* psoc_dev; + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) + { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + psoc_dev = pdriver_dev->private; + ret = soc_priv_ioctl(psoc_dev, cmd , (void __user *)arg); + return ret; +}; + +static int vvcam_soc_release(struct inode * inode, struct file * file) +{ + return 0; +}; + +static struct file_operations vvcam_soc_fops = { + .owner = THIS_MODULE, + .open = vvcam_soc_open, + .release = vvcam_soc_release, + .unlocked_ioctl = vvcam_soc_ioctl, +}; + +static int vvcam_soc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vvcam_soc_driver_dev *pdriver_dev; + struct vvcam_soc_dev * psoc_dev; +// struct resource *mem; + + pr_info("enter %s\n", __func__); + + if (pdev->id >= VIVCAM_SOC_MAXCNT) + { + pr_err("%s:pdev id is %d error\n", __func__,pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_soc_driver_dev), GFP_KERNEL); + if (pdriver_dev == NULL) + { + pr_err("%s:alloc struct vvcam_soc_driver_dev error\n", __func__); + return -ENOMEM; + } + memset(pdriver_dev,0,sizeof(struct vvcam_soc_driver_dev )); + + + psoc_dev = devm_kzalloc(&pdev->dev,sizeof(struct vvcam_soc_dev), GFP_KERNEL); + if (psoc_dev == NULL) + { + pr_err("%s:alloc struct vvcam_soc_dev error\n", __func__); + return -ENOMEM; + } + memset(psoc_dev,0,sizeof(struct vvcam_soc_dev )); + + //mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + //psoc_dev->base = devm_ioremap_resource(&pdev->dev, mem); + psoc_dev->base = ioremap(VVCTRL_BASE, VVCTRL_SIZE); + if (IS_ERR(psoc_dev->base )) + return PTR_ERR(psoc_dev->base ); + + pdriver_dev->private = psoc_dev; + mutex_init(&pdriver_dev->vvmutex); + platform_set_drvdata(pdev, pdriver_dev); + + vvnative_soc_init(psoc_dev); + if (devise_register_index == 0) + { + if (vvcam_soc_major == 0) + { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VIVCAM_SOC_MAXCNT, VIVCAM_SOC_NAME); + if (ret != 0) + { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vvcam_soc_major = MAJOR(pdriver_dev->devt); + vvcam_soc_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vvcam_soc_major, vvcam_soc_minor); + ret = register_chrdev_region(pdriver_dev->devt, VIVCAM_SOC_MAXCNT, VIVCAM_SOC_NAME); + if (ret) + { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + + vvcam_soc_class = class_create(THIS_MODULE, VIVCAM_SOC_NAME); + if (IS_ERR(vvcam_soc_class)) + { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vvcam_soc_major, vvcam_soc_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vvcam_soc_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) + { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vvcam_soc_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VIVCAM_SOC_NAME, pdev->id); + + devise_register_index++; + pr_info("exit %s\n", __func__); + return ret; +} + +static int vvcam_soc_remove(struct platform_device *pdev) +{ + struct vvcam_soc_driver_dev *pdriver_dev; + struct vvcam_soc_dev * psoc_dev; + + pr_info("enter %s\n", __func__); + devise_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + psoc_dev = pdriver_dev->private; + iounmap(psoc_dev->base); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VIVCAM_SOC_MAXCNT); + if (devise_register_index == 0) + { + class_destroy(pdriver_dev->class); + } + + return 0; +} + +static struct platform_driver vvcam_soc_driver = { + .probe = vvcam_soc_probe, + .remove = vvcam_soc_remove, + .driver = { + .name = VIVCAM_SOC_NAME, + .owner = THIS_MODULE, + } +}; + +static void vvcam_soc_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + + +static struct resource vvcam_soc_resource[] = { + [0] = { + .start = VVCTRL_BASE, + .end = VVCTRL_BASE + VVCTRL_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; +static struct platform_device vvcam_soc_pdev = { + .name = VIVCAM_SOC_NAME, + .id = 0, + .resource = vvcam_soc_resource, + .num_resources = 1, + .dev.release = vvcam_soc_pdev_release, +}; + +static int __init vvcam_soc_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_device_register(&vvcam_soc_pdev); + if (ret) + { + pr_err("register platform device failed.\n"); + return ret; + } + + ret = platform_driver_register(&vvcam_soc_driver); + if (ret) + { + pr_err("register platform driver failed.\n"); + platform_device_unregister(&vvcam_soc_pdev); + return ret; + } + + return ret; +} + +static void __exit vvcam_soc_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vvcam_soc_driver); + platform_device_unregister(&vvcam_soc_pdev); +} + +module_init(vvcam_soc_init_module); +module_exit(vvcam_soc_exit_module); + +MODULE_DESCRIPTION("ISP"); +MODULE_LICENSE("GPL"); \ No newline at end of file diff --git a/vvcam_ry/native/vi_pre/Makefile b/vvcam_ry/native/vi_pre/Makefile new file mode 100755 index 0000000..2232b08 --- /dev/null +++ b/vvcam_ry/native/vi_pre/Makefile @@ -0,0 +1,19 @@ +include $(PWD)/../Param.mk +include $(PWD)/../../version/$(VERSION_CFG).mk +TARGET = vi_pre + +obj-m +=$(TARGET).o + +$(TARGET)-objs += vi_pre_driver_of.o +$(TARGET)-objs += vi_pre_ioctl.o +EXTRA_CFLAGS += -I$(PWD)/../../common + +PWD :=$(shell pwd) + +all: + make -C $(KERNEL) M=$(PWD) modules +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install +clean: + rm -rf $($(TARGET)-objs) + make -C $(KERNEL) M=`pwd` clean diff --git a/vvcam_ry/native/vi_pre/vi_pre.h b/vvcam_ry/native/vi_pre/vi_pre.h new file mode 100755 index 0000000..2cf349a --- /dev/null +++ b/vvcam_ry/native/vi_pre/vi_pre.h @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: Shenwuyi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __VI_PRE_H__ +#define __VI_PRE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VI_PRE_DEV_NAME "vi_pre" +#define VI_PRE_NAME "vipre" +#define VI_PRE_MAXCNT 1 + +#define HDRPRO_CTRL(n) (0x0094 + (n-1) * 4) +#define HDRPRO_COE(n) (0x009c + (n-1) * 4) +#define HDRPRO_LINW(n) (0x00b0 + (n-1) * 4) +#define HDRPRO_LINA(n) (0x00d0 + (n-1) * 4) +#define HDRPRO_LINB(n) (0x0110 + (n-1) * 4) +#define MIPI2DMA_CTRL(n) (0x0198 + (n) * 4) + + +#define VIPRE_BUS_ERR (1 << 5) +#define VIPRE_FIFO_OVER (1 << 4) +#define VIPRE_IDLE_DONE (1 << 3) +#define VIPRE_NMOVERFLOW (1 << 2) +#define VIPRE_LINE_DONE (1 << 1) +#define VIPRE_FRAME_DONE (1 << 0) + +/* hdrpro_ctrl1 reg bit config */ +enum hdrpro_ctrl1_regval { + //RAWMOD_HDRPRO + HDRPRO_CTRL1_RAW6 = 0 << 21, + HDRPRO_CTRL1_RAW7 = 1 << 21, + HDRPRO_CTRL1_RAW8 = 2 << 21, + HDRPRO_CTRL1_RAW10 = 3 << 21, + HDRPRO_CTRL1_RAW12 = 4 << 21, + //BAYER_MODSEL + HDRPRO_CTRL1_BAYER_MODSEL_BAYER_A = 0 << 19, + HDRPRO_CTRL1_BAYER_MODSEL_BAYER_B = 1 << 19, + HDRPRO_CTRL1_BAYER_MODSEL_BAYER_C = 2 << 19, + HDRPRO_CTRL1_BAYER_MODSEL_BAYER_D = 3 << 19, + + //COLOR_MODSEL + HDRPRO_CTRL1_COLER_MODSEL_BLACK_NODOWN_2X2 = 0 << 16, + HDRPRO_CTRL1_COLER_MODSEL_BLACK_DOWN_2X2 = 1 << 16, + HDRPRO_CTRL1_COLER_MODSEL_RGB_NODOWN_2X2 = 2 << 16, + HDRPRO_CTRL1_COLER_MODSEL_RGB_DOWN_2X2 = 3 << 16, + HDRPRO_CTRL1_COLER_MODSEL_RGB_NODOWN_3X3 = 4 << 16, + HDRPRO_CTRL1_COLER_MODSEL_RGB_DOWN_3X3 = 5 << 16, + + //HDRPRO_EN + HDRPRO_BYPASS = 0 << 0, + HDRPRO_EN = 1 << 0 +}; + +/* mipi2dma ctrl0 */ +enum mipi2dma_ctrl0_regval { + //RAWMOD + MIPI2DMA_CTRL0_RAW6 = 0 << 4, + MIPI2DMA_CTRL0_RAW7 = 1 << 4, + MIPI2DMA_CTRL0_RAW8 = 2 << 4, + MIPI2DMA_CTRL0_RAW10 = 3 << 4, + MIPI2DMA_CTRL0_RAW12 = 4 << 4, + + //RAWPOS + MIPI2DMA_CTRL0_LOW_BIT_MODE = 0 << 3, + MIPI2DMA_CTRL0_HIGH_BIT_MODE = 1 << 3, + //mnum + MIPI2DMA_CTRL0_1_FRAME = 0 << 1, + MIPI2DMA_CTRL0_2_FRAME = 1 << 1, + MIPI2DMA_CTRL0_3_FRAME = 2 << 1, + MIPI2DMA_CTRL0_4_FRAME = 3 << 1, + //mnmod + MIPI2DMA_CTRL0_MODE_M_FRAME = 0 << 0, + MIPI2DMA_CTRL0_MODE_N_LINE = 1 << 0, +}; + +/* mipi2dma ctrl1 */ +enum mipi2dma_ctrl1_regval { + //MIPI2DMA_WBURSTLEN + MIPI2DMA_CTRL1_WBURSTLEN_4 = 3 << 16, + MIPI2DMA_CTRL1_WBURSTLEN_8 = 7 << 16, + MIPI2DMA_CTRL1_WBURSTLEN_16 = 15 << 16, +}; + +/* mipi2dma ctrl10 */ +enum mipi2dma_ctrl10_regval { + MIPI2DMA_START = 1 << 0, + MIPI2DMA_STOP = 0 << 0, +}; + +/* mipi2dma ctrl51 */ +enum mipi2dma_ctrl51_regval { + MIPI2DMA_CTRL51_CROSS_4K_EN = 1 << 0, + MIPI2DMA_CTRL51_CROSS_4K_DIS = 0 << 0, +}; + +//MIPI2DMA +#define MIPI2DMA_CTRL1_WOSNUM_SHIFT 0 + +#define MIPI2DMA_CTRL3_VERTICAL_SHIFT 16 +#define MIPI2DMA_CTRL3_HORIZON_SHIFT 0 + +#define MIPI2DMA_CTRL4_BURSTREM_SHIFT 27 +#define MIPI2DMA_CTRL4_READNUM_SHIFT 16 +#define MIPI2DMA_CTRL4_HORIZON_CNT128_SHIFT 0 + +#define MIPI2DMA_CTRL5_N_NLINENUM_SHIFT 16 +#define MIPI2DMA_CTRL5_N_LINENUM_SHIFT 0 + +#define MIPI2DMA_CTRL6_N_STRIDE_SHIFT 0 + +#define MIPI2DMA_CTRL7_M0_STRIDE_SHIFT 16 +#define MIPI2DMA_CTRL7_M1_STRIDE_SHIFT 0 + +#define MIPI2DMA_CTRL8_M2_STRIDE_SHIFT 16 +#define MIPI2DMA_CTRL8_M3_STRIDE_SHIFT 0 + +#define MIPI2DMA_CTRL15_N_SADDR_ID0_H_SHIFT 0 +#define MIPI2DMA_CTRL16_N_SADDR_ID0_L_SHIFT 0 +#define MIPI2DMA_CTRL17_N_SADDR_ID1_H_SHIFT 0 +#define MIPI2DMA_CTRL18_N_SADDR_ID1_L_SHIFT 0 +#define MIPI2DMA_CTRL19_N_SADDR_ID2_H_SHIFT 0 +#define MIPI2DMA_CTRL20_N_SADDR_ID2_L_SHIFT 0 + +#define MIPI2DMA_CTRL25_M0_SADDR_ID0_H_SHIFT 0 +#define MIPI2DMA_CTRL26_M0_SADDR_ID0_L_SHIFT 0 +#define MIPI2DMA_CTRL27_M0_SADDR_ID1_H_SHIFT 0 +#define MIPI2DMA_CTRL28_M0_SADDR_ID1_L_SHIFT 0 +#define MIPI2DMA_CTRL29_M0_SADDR_ID2_H_SHIFT 0 +#define MIPI2DMA_CTRL30_M0_SADDR_ID2_L_SHIFT 0 + +#define MIPI2DMA_CTRL31_M1_SADDR_ID0_H_SHIFT 0 +#define MIPI2DMA_CTRL32_M1_SADDR_ID0_L_SHIFT 0 +#define MIPI2DMA_CTRL33_M1_SADDR_ID1_H_SHIFT 0 +#define MIPI2DMA_CTRL34_M1_SADDR_ID1_L_SHIFT 0 +#define MIPI2DMA_CTRL35_M1_SADDR_ID2_H_SHIFT 0 +#define MIPI2DMA_CTRL36_M1_SADDR_ID2_L_SHIFT 0 + +#define MIPI2DMA_CTRL37_M2_SADDR_ID0_H_SHIFT 0 +#define MIPI2DMA_CTRL38_M2_SADDR_ID0_L_SHIFT 0 +#define MIPI2DMA_CTRL39_M2_SADDR_ID1_H_SHIFT 0 +#define MIPI2DMA_CTRL40_M2_SADDR_ID1_L_SHIFT 0 +#define MIPI2DMA_CTRL41_M2_SADDR_ID2_H_SHIFT 0 +#define MIPI2DMA_CTRL42_M2_SADDR_ID2_L_SHIFT 0 + +#define MIPI2DMA_CTRL44_BUSERR_MASK_SHIFT 21 +#define MIPI2DMA_CTRL44_FIFO_OVERERR_MASK_SHIFT 20 +#define MIPI2DMA_CTRL44_IDLE_DONE_MASK_SHIFT 19 +#define MIPI2DMA_CTRL44_MN_OVERERR_MASK_SHIFT 18 +#define MIPI2DMA_CTRL44_NLINE_DONE_MASK_SHIFT 17 +#define MIPI2DMA_CTRL44_MFRAME_DONE_MASK_SHIFT 16 + +#define MIPI2DMA_CTRL45_M3_SADDR_ID0_H_SHIFT 0 +#define MIPI2DMA_CTRL46_M3_SADDR_ID0_L_SHIFT 0 +#define MIPI2DMA_CTRL47_M3_SADDR_ID1_H_SHIFT 0 +#define MIPI2DMA_CTRL48_M3_SADDR_ID1_L_SHIFT 0 +#define MIPI2DMA_CTRL49_M3_SADDR_ID2_H_SHIFT 0 +#define MIPI2DMA_CTRL50_M3_SADDR_ID2_L_SHIFT 0 + +//HDRPRO + +#define HDRPRO_CTRL1_HDRPRO_RAWMOD_MASK 0x00e00000 + +#define HDRPRO_CTRL1_HDRPRO_ID_SHIFT 1 + +#define HDRPRO_CTRL2_VERTICAL_MASK 0x1fff0000 +#define HDRPRO_CTRL2_HORIZON_MASK 0x00001fff + +#define HDRPRO_CTRL2_VERTICAL_SHIFT 16 +#define HDRPRO_CTRL2_HORIZON_SHIFT 0 + +#define HDRPRO_COE1_BE_BLACK_WR_SHIFT 28 +#define HDRPRO_COE1_BE_BLACK_WB_SHIFT 24 +#define HDRPRO_COE1_BE_BLACK_WG0_SHIFT 20 +#define HDRPRO_COE1_BE_BLACK_WG1_SHIFT 16 +#define HDRPRO_COE1_BE_BLACK_WG0_00_SHIFT 12 +#define HDRPRO_COE1_BE_BLACK_WG0_01_SHIFT 8 +#define HDRPRO_COE1_BE_BLACK_WG0_02_SHIFT 4 +#define HDRPRO_COE1_BE_BLACK_WG0_10_SHIFT 0 + +#define HDRPRO_COE2_BE_BLACK_WG0_11_SHIFT 28 +#define HDRPRO_COE2_BE_BLACK_WG0_12_SHIFT 24 +#define HDRPRO_COE2_BE_BLACK_WG0_20_SHIFT 20 +#define HDRPRO_COE2_BE_BLACK_WG0_21_SHIFT 16 +#define HDRPRO_COE2_BE_BLACK_WG0_22_SHIFT 12 +#define HDRPRO_COE2_BE_BLACK_WG1_00_SHIFT 8 +#define HDRPRO_COE2_BE_BLACK_WG1_01_SHIFT 4 +#define HDRPRO_COE2_BE_BLACK_WG1_02_SHIFT 0 + +#define HDRPRO_COE3_BE_BLACK_WG1_10_SHIFT 28 +#define HDRPRO_COE3_BE_BLACK_WG1_11_SHIFT 24 +#define HDRPRO_COE3_BE_BLACK_WG1_12_SHIFT 20 +#define HDRPRO_COE3_BE_BLACK_WG1_20_SHIFT 16 +#define HDRPRO_COE3_BE_BLACK_WG1_21_SHIFT 12 +#define HDRPRO_COE3_BE_BLACK_WG1_22_SHIFT 8 +#define HDRPRO_COE3_BE_BLACK_WR_00_SHIFT 4 +#define HDRPRO_COE3_BE_BLACK_WR_01_SHIFT 0 + +#define HDRPRO_COE4_BE_BLACK_WR_02_SHIFT 28 +#define HDRPRO_COE4_BE_BLACK_WR_10_SHIFT 24 +#define HDRPRO_COE4_BE_BLACK_WR_11_SHIFT 20 +#define HDRPRO_COE4_BE_BLACK_WR_12_SHIFT 16 +#define HDRPRO_COE4_BE_BLACK_WR_20_SHIFT 12 +#define HDRPRO_COE4_BE_BLACK_WR_21_SHIFT 8 +#define HDRPRO_COE4_BE_BLACK_WR_22_SHIFT 4 +#define HDRPRO_COE4_BE_BLACK_WB_00_SHIFT 0 + +#define HDRPRO_COE5_BE_BLACK_WB_01_SHIFT 28 +#define HDRPRO_COE5_BE_BLACK_WB_02_SHIFT 24 +#define HDRPRO_COE5_BE_BLACK_WB_10_SHIFT 20 +#define HDRPRO_COE5_BE_BLACK_WB_11_SHIFT 16 +#define HDRPRO_COE5_BE_BLACK_WB_12_SHIFT 12 +#define HDRPRO_COE5_BE_BLACK_WB_20_SHIFT 8 +#define HDRPRO_COE5_BE_BLACK_WB_21_SHIFT 4 +#define HDRPRO_COE5_BE_BLACK_WB_22_SHIFT 0 + +#define HDRPRO_LINW1_W1_SHIFT 16 +#define HDRPRO_LINW1_W2_SHIFT 0 +#define HDRPRO_LINW2_W3_SHIFT 16 +#define HDRPRO_LINW2_W4_SHIFT 0 +#define HDRPRO_LINW3_W5_SHIFT 16 +#define HDRPRO_LINW3_W6_SHIFT 0 +#define HDRPRO_LINW4_W7_SHIFT 16 +#define HDRPRO_LINW4_W8_SHIFT 0 +#define HDRPRO_LINW5_W9_SHIFT 16 +#define HDRPRO_LINW5_W10_SHIFT 0 +#define HDRPRO_LINW6_W11_SHIFT 16 +#define HDRPRO_LINW6_W12_SHIFT 0 +#define HDRPRO_LINW7_W13_SHIFT 16 +#define HDRPRO_LINW7_W14_SHIFT 0 +#define HDRPRO_LINW8_W15_SHIFT 16 +#define HDRPRO_LINW8_W16_SHIFT 0 + +#define HDRPRO_LINA1_A1_SHIFT 0 +#define HDRPRO_LINA2_A2_SHIFT 0 +#define HDRPRO_LINA3_A3_SHIFT 0 +#define HDRPRO_LINA4_A4_SHIFT 0 +#define HDRPRO_LINA5_A5_SHIFT 0 +#define HDRPRO_LINA6_A6_SHIFT 0 +#define HDRPRO_LINA7_A7_SHIFT 0 +#define HDRPRO_LINA8_A8_SHIFT 0 +#define HDRPRO_LINA9_A9_SHIFT 0 +#define HDRPRO_LINA10_A10_SHIFT 0 +#define HDRPRO_LINA11_A11_SHIFT 0 +#define HDRPRO_LINA12_A12_SHIFT 0 +#define HDRPRO_LINA13_A13_SHIFT 0 +#define HDRPRO_LINA14_A14_SHIFT 0 +#define HDRPRO_LINA15_A15_SHIFT 0 +#define HDRPRO_LINA16_A16_SHIFT 0 + +#define HDRPRO_LINB1_B1_SHIFT 0 +#define HDRPRO_LINB2_B2_SHIFT 0 +#define HDRPRO_LINB3_B3_SHIFT 0 +#define HDRPRO_LINB4_B4_SHIFT 0 +#define HDRPRO_LINB5_B5_SHIFT 0 +#define HDRPRO_LINB6_B6_SHIFT 0 +#define HDRPRO_LINB7_B7_SHIFT 0 +#define HDRPRO_LINB8_B8_SHIFT 0 +#define HDRPRO_LINB9_B9_SHIFT 0 +#define HDRPRO_LINB10_B10_SHIFT 0 +#define HDRPRO_LINB11_B11_SHIFT 0 +#define HDRPRO_LINB12_B12_SHIFT 0 +#define HDRPRO_LINB13_B13_SHIFT 0 +#define HDRPRO_LINB14_B14_SHIFT 0 +#define HDRPRO_LINB15_B15_SHIFT 0 +#define HDRPRO_LINB16_B16_SHIFT 0 + + +struct vi_pre_dev { + int id; + int irq; + dev_t devt; + struct class *class; + struct cdev cdev; + struct mutex mutex; + void __iomem *reg_base; + unsigned long cnt[3]; //used to cnt frame num or line num; + bool is_mframe_mode; +}; +#endif/*__VI_PRE_H__*/ diff --git a/vvcam_ry/native/vi_pre/vi_pre_driver_of.c b/vvcam_ry/native/vi_pre/vi_pre_driver_of.c new file mode 100755 index 0000000..9bcd694 --- /dev/null +++ b/vvcam_ry/native/vi_pre/vi_pre_driver_of.c @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: Shenwuyi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "vi_pre.h" +#include "vi_pre_ioctl.h" + +static unsigned int vi_pre_major = 0; +static unsigned int vi_pre_minor = 0; +struct class *vi_pre_class; +static unsigned int device_register_index = 0; + +static int vi_pre_open(struct inode * inode, struct file * file) +{ + struct vi_pre_dev *pdriver_dev; + + pr_info("entry %s\n", __func__); + pdriver_dev = container_of(inode->i_cdev, struct vi_pre_dev, cdev); + file->private_data = pdriver_dev; + + pr_info("exit %s\n", __func__); + return 0; +}; + +static long vi_pre_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct vi_pre_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + pdriver_dev = file->private_data; + if (pdriver_dev == NULL) { + pr_err("%s:file private is null point error\n", __func__); + return -ENOMEM; + } + + mutex_lock(&pdriver_dev->mutex); + ret = vi_pre_priv_ioctl(pdriver_dev, cmd ,(void *)arg); + mutex_unlock(&pdriver_dev->mutex); + + pr_info("exit %s\n", __func__); + + return ret; +}; + +static int vi_pre_release(struct inode * inode, struct file * file) +{ + struct vi_pre_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + + pdriver_dev = container_of(inode->i_cdev, struct vi_pre_dev, cdev); + file->private_data = pdriver_dev; + + pr_info("exit %s\n", __func__); + + return 0; +}; + +struct file_operations vi_pre_fops = { + .owner = THIS_MODULE, + .open = vi_pre_open, + .release = vi_pre_release, + .unlocked_ioctl = vi_pre_ioctl, + .mmap = NULL, + .poll = NULL, +}; + +static int vi_pre_probe(struct platform_device *pdev) +{ + int ret = 0; + struct vi_pre_dev *pdriver_dev; + struct resource *mem; + + pr_info("enter %s\n", __func__); + pdev->id = device_register_index; + if (pdev->id >= VI_PRE_MAXCNT) { + pr_err("%s:pdev id is %d error\n", __func__, pdev->id); + return -EINVAL; + } + + pdriver_dev = devm_kzalloc(&pdev->dev, sizeof(struct vi_pre_dev), GFP_KERNEL); + if (pdriver_dev == NULL) { + pr_err("%s:alloc struct vi_pre_dev error\n", __func__); + return -ENOMEM; + } + pr_info("%s:isp[%d]: pdriver_dev =0x%px\n", __func__, pdev->id, pdriver_dev); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pdriver_dev->reg_base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(pdriver_dev->reg_base)) + return PTR_ERR(pdriver_dev->reg_base); + pr_info("%s:isp[%d]: pdriver_dev->base=0x%px\n", __func__, + pdev->id, pdriver_dev->reg_base); + + pdriver_dev->id = pdev->id; + mutex_init(&pdriver_dev->mutex); + platform_set_drvdata(pdev, pdriver_dev); + + if (device_register_index == 0) { + int ret; + + if (vi_pre_major == 0) { + ret = alloc_chrdev_region(&pdriver_dev->devt, 0, VI_PRE_MAXCNT, VI_PRE_NAME); + if (ret != 0) { + pr_err("%s:alloc_chrdev_region error\n", __func__); + return ret; + } + vi_pre_major = MAJOR(pdriver_dev->devt); + vi_pre_minor = MINOR(pdriver_dev->devt); + } + else + { + pdriver_dev->devt = MKDEV(vi_pre_major, vi_pre_minor); + ret = register_chrdev_region(pdriver_dev->devt, VI_PRE_MAXCNT, VI_PRE_NAME); + if (ret) { + pr_err("%s:register_chrdev_region error\n", __func__); + return ret; + } + } + vi_pre_class = class_create(THIS_MODULE, VI_PRE_NAME); + if (IS_ERR(vi_pre_class)) { + pr_err("%s[%d]:class_create error!\n", __func__, __LINE__); + return -EINVAL; + } + } + pdriver_dev->devt = MKDEV(vi_pre_major, vi_pre_minor + pdev->id); + + cdev_init(&pdriver_dev->cdev, &vi_pre_fops); + ret = cdev_add(&pdriver_dev->cdev, pdriver_dev->devt, 1); + if ( ret ) { + pr_err("%s[%d]:cdev_add error!\n", __func__, __LINE__); + return ret; + } + pdriver_dev->class = vi_pre_class; + device_create(pdriver_dev->class, NULL, pdriver_dev->devt, + pdriver_dev, "%s%d", VI_PRE_NAME, pdev->id); + + device_register_index++; + pr_info("exit %s:[%d]\n", __func__, pdev->id); + + return ret; +} + + +static int vi_pre_remove(struct platform_device *pdev) +{ + struct vi_pre_dev *pdriver_dev; + + pr_info("enter %s\n", __func__); + device_register_index--; + pdriver_dev = platform_get_drvdata(pdev); + + cdev_del(&pdriver_dev->cdev); + device_destroy(pdriver_dev->class, pdriver_dev->devt); + unregister_chrdev_region(pdriver_dev->devt, VI_PRE_MAXCNT); + if (device_register_index == 0) { + class_destroy(pdriver_dev->class); + } + return 0; +} + + +static const struct of_device_id vi_pre_of_match_table[] = { + { .compatible = "thead,vi_pre", }, + { }, +}; + +static struct platform_driver vi_pre_driver = { + .probe = vi_pre_probe, + .remove = vi_pre_remove, + .driver = { + .owner = THIS_MODULE, + .name = VI_PRE_DEV_NAME, + .of_match_table = vi_pre_of_match_table, + }, +}; + +static int __init vi_pre_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&vi_pre_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + pr_info("exit %s\n", __func__); + + return ret; +} + +static void __exit vi_pre_exit_module(void) +{ + pr_info("enter %s\n", __func__); + + platform_driver_unregister(&vi_pre_driver); + pr_info("exit %s\n", __func__); +} + +module_init(vi_pre_init_module); +module_exit(vi_pre_exit_module); + +MODULE_DESCRIPTION("VI_PRE"); +MODULE_LICENSE("GPL"); diff --git a/vvcam_ry/native/vi_pre/vi_pre_ioctl.c b/vvcam_ry/native/vi_pre/vi_pre_ioctl.c new file mode 100755 index 0000000..ea8a5c7 --- /dev/null +++ b/vvcam_ry/native/vi_pre/vi_pre_ioctl.c @@ -0,0 +1,748 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: Shenwuyi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include "vi_pre.h" +#include "vi_pre_ioctl.h" + +#define check_retval(x)\ + do {\ + if ((x))\ + return -EIO;\ + } while (0) + +static void vi_pre_write(struct vi_pre_dev *dec, unsigned int addr, unsigned int val) +{ + writel(val, dec->reg_base + addr); +} + +static int vi_pre_write_reg(struct vi_pre_dev *dev, void *__user args) +{ + struct vi_pre_reg_t reg, reg1; + check_retval(copy_from_user(®, args, sizeof(reg))); + writel(reg.value, dev->reg_base + reg.offset); + pr_info("%s addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value); + + reg1.value = readl(dev->reg_base + reg.offset); + pr_info("%s rad back addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg1.value); + return 0; +} + +static int vi_pre_read_reg(struct vi_pre_dev *dev, void *__user args) +{ + struct vi_pre_reg_t reg; + check_retval(copy_from_user(®, args, sizeof(reg))); + reg.value = readl(dev->reg_base + reg.offset); + check_retval(copy_to_user(args, ®, sizeof(reg))); + pr_info("%s addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value); + return 0; +} +static unsigned int vi_pre_read(struct vi_pre_dev *dev, unsigned int addr) +{ + return readl(dev->reg_base + addr); +} + +static int vi_pre_set_hdrpro(struct vi_pre_dev *dev, void *args) +{ + int ret = 0; + unsigned int val = 0; + + val = vi_pre_read(dev, HDRPRO_CTRL(1)); + val |= HDRPRO_EN; + val |= HDRPRO_CTRL1_BAYER_MODSEL_BAYER_C; + val |= HDRPRO_CTRL1_COLER_MODSEL_BLACK_NODOWN_2X2; + val &= ~HDRPRO_CTRL1_HDRPRO_RAWMOD_MASK; + val |= HDRPRO_CTRL1_RAW10; + vi_pre_write(dev, HDRPRO_CTRL(1), val); + + val = vi_pre_read(dev, HDRPRO_CTRL(2)); + val &= ~HDRPRO_CTRL2_VERTICAL_MASK; + val |= (480 << HDRPRO_CTRL2_VERTICAL_SHIFT); + val &= ~HDRPRO_CTRL2_HORIZON_MASK; + val |= (640 << HDRPRO_CTRL2_HORIZON_SHIFT); + vi_pre_write(dev, HDRPRO_CTRL(2), val); + + val = vi_pre_read(dev, HDRPRO_COE(1)); + val |= (8 << HDRPRO_COE1_BE_BLACK_WR_SHIFT); + val |= (6 << HDRPRO_COE1_BE_BLACK_WB_SHIFT); + val |= (4 << HDRPRO_COE1_BE_BLACK_WG0_SHIFT); + val |= (2 << HDRPRO_COE1_BE_BLACK_WG1_SHIFT); + val |= (1 << HDRPRO_COE1_BE_BLACK_WG0_00_SHIFT); + val |= (2 << HDRPRO_COE1_BE_BLACK_WG0_01_SHIFT); + val |= (3 << HDRPRO_COE1_BE_BLACK_WG0_02_SHIFT); + val |= (4 << HDRPRO_COE1_BE_BLACK_WG0_10_SHIFT); + vi_pre_write(dev, HDRPRO_COE(1), val); + + val = vi_pre_read(dev, HDRPRO_COE(2)); + val |= (5 << HDRPRO_COE2_BE_BLACK_WG0_11_SHIFT); + val |= (6 << HDRPRO_COE2_BE_BLACK_WG0_12_SHIFT); + val |= (7 << HDRPRO_COE2_BE_BLACK_WG0_20_SHIFT); + val |= (8 << HDRPRO_COE2_BE_BLACK_WG0_21_SHIFT); + val |= (9 << HDRPRO_COE2_BE_BLACK_WG0_22_SHIFT); + val |= (1 << HDRPRO_COE2_BE_BLACK_WG1_00_SHIFT); + val |= (2 << HDRPRO_COE2_BE_BLACK_WG1_01_SHIFT); + val |= (3 << HDRPRO_COE2_BE_BLACK_WG1_02_SHIFT); + vi_pre_write(dev, HDRPRO_COE(2), val); + + val = vi_pre_read(dev, HDRPRO_COE(3)); + val |= (4 << HDRPRO_COE3_BE_BLACK_WG1_10_SHIFT); + val |= (5 << HDRPRO_COE3_BE_BLACK_WG1_11_SHIFT); + val |= (6 << HDRPRO_COE3_BE_BLACK_WG1_12_SHIFT); + val |= (7 << HDRPRO_COE3_BE_BLACK_WG1_20_SHIFT); + val |= (8 << HDRPRO_COE3_BE_BLACK_WG1_21_SHIFT); + val |= (9 << HDRPRO_COE3_BE_BLACK_WG1_22_SHIFT); + val |= (1 << HDRPRO_COE3_BE_BLACK_WR_00_SHIFT); + val |= (2 << HDRPRO_COE3_BE_BLACK_WR_01_SHIFT); + vi_pre_write(dev, HDRPRO_COE(3), val); + + val = vi_pre_read(dev, HDRPRO_COE(4)); + val |= (3 << HDRPRO_COE4_BE_BLACK_WR_02_SHIFT); + val |= (4 << HDRPRO_COE4_BE_BLACK_WR_10_SHIFT); + val |= (5 << HDRPRO_COE4_BE_BLACK_WR_11_SHIFT); + val |= (6 << HDRPRO_COE4_BE_BLACK_WR_12_SHIFT); + val |= (7 << HDRPRO_COE4_BE_BLACK_WR_20_SHIFT); + val |= (8 << HDRPRO_COE4_BE_BLACK_WR_21_SHIFT); + val |= (9 << HDRPRO_COE4_BE_BLACK_WR_22_SHIFT); + val |= (1 << HDRPRO_COE4_BE_BLACK_WB_00_SHIFT); + vi_pre_write(dev, HDRPRO_COE(4), val); + + val = vi_pre_read(dev, HDRPRO_COE(5)); + val |= (2 << HDRPRO_COE5_BE_BLACK_WB_02_SHIFT); + val |= (3 << HDRPRO_COE5_BE_BLACK_WB_10_SHIFT); + val |= (4 << HDRPRO_COE5_BE_BLACK_WB_11_SHIFT); + val |= (5 << HDRPRO_COE5_BE_BLACK_WB_12_SHIFT); + val |= (6 << HDRPRO_COE5_BE_BLACK_WB_20_SHIFT); + val |= (7 << HDRPRO_COE5_BE_BLACK_WB_21_SHIFT); + val |= (8 << HDRPRO_COE5_BE_BLACK_WB_22_SHIFT); + val |= (9 << HDRPRO_COE5_BE_BLACK_WB_01_SHIFT); + vi_pre_write(dev, HDRPRO_COE(5), val); + + val = vi_pre_read(dev, HDRPRO_LINW(1)); + val |= (0x100 << HDRPRO_LINW1_W1_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(1), val); + + val = vi_pre_read(dev, HDRPRO_LINA(1)); + val |= (0 << HDRPRO_LINA1_A1_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(1), val); + + val = vi_pre_read(dev, HDRPRO_LINB(1)); + val |= (0x1000 << HDRPRO_LINB1_B1_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(1), val); + + val = vi_pre_read(dev, HDRPRO_LINW(2)); + val |= (0x100 << HDRPRO_LINW1_W2_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(2), val); + + val = vi_pre_read(dev, HDRPRO_LINA(2)); + val |= (0x1fff << HDRPRO_LINA2_A2_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(2), val); + + val = vi_pre_read(dev, HDRPRO_LINB(2)); + val |= (0x1f00 << HDRPRO_LINB2_B2_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(2), val); + + val = vi_pre_read(dev, HDRPRO_LINW(3)); + val |= (0x100 << HDRPRO_LINW2_W3_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(3), val); + + val = vi_pre_read(dev, HDRPRO_LINA(3)); + val |= (0x2fff << HDRPRO_LINA3_A3_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(3), val); + + val = vi_pre_read(dev, HDRPRO_LINB(3)); + val |= (0x2000 << HDRPRO_LINB3_B3_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(3), val); + + val = vi_pre_read(dev, HDRPRO_LINW(4)); + val |= (0x100 << HDRPRO_LINW2_W4_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(4), val); + + val = vi_pre_read(dev, HDRPRO_LINA(4)); + val |= (0x3fff << HDRPRO_LINA4_A4_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(4), val); + + val = vi_pre_read(dev, HDRPRO_LINB(4)); + val |= (0x3000 << HDRPRO_LINB4_B4_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(4), val); + + val = vi_pre_read(dev, HDRPRO_LINW(5)); + val |= (0x100 << HDRPRO_LINW3_W5_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(5), val); + + val = vi_pre_read(dev, HDRPRO_LINA(5)); + val |= (0x4fff << HDRPRO_LINA5_A5_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(5), val); + + val = vi_pre_read(dev, HDRPRO_LINB(5)); + val |= (0x4000 << HDRPRO_LINB5_B5_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(5), val); + + val = vi_pre_read(dev, HDRPRO_LINW(6)); + val |= (0x100 << HDRPRO_LINW3_W6_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(6), val); + + val = vi_pre_read(dev, HDRPRO_LINA(6)); + val |= (0x5fff << HDRPRO_LINA6_A6_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(6), val); + + val = vi_pre_read(dev, HDRPRO_LINB(6)); + val |= (0x5000 << HDRPRO_LINB6_B6_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(6), val); + + val = vi_pre_read(dev, HDRPRO_LINW(7)); + val |= (0x100 << HDRPRO_LINW4_W7_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(7), val); + + val = vi_pre_read(dev, HDRPRO_LINA(7)); + val |= (0x6fff << HDRPRO_LINA7_A7_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(7), val); + + val = vi_pre_read(dev, HDRPRO_LINB(7)); + val |= (0x6000 << HDRPRO_LINB7_B7_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(7), val); + + val = vi_pre_read(dev, HDRPRO_LINW(8)); + val |= (0x100 << HDRPRO_LINW4_W8_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(8), val); + + val = vi_pre_read(dev, HDRPRO_LINA(8)); + val |= (0x7fff << HDRPRO_LINA8_A8_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(8), val); + + val = vi_pre_read(dev, HDRPRO_LINB(8)); + val |= (0x7000 << HDRPRO_LINB8_B8_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(8), val); + + val = vi_pre_read(dev, HDRPRO_LINW(9)); + val |= (0x100 << HDRPRO_LINW5_W9_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(9), val); + + val = vi_pre_read(dev, HDRPRO_LINA(9)); + val |= (0x8fff << HDRPRO_LINA9_A9_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(9), val); + + val = vi_pre_read(dev, HDRPRO_LINB(9)); + val |= (0x8000 << HDRPRO_LINB9_B9_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(9), val); + + val = vi_pre_read(dev, HDRPRO_LINW(10)); + val |= (0x100 << HDRPRO_LINW5_W10_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(10), val); + + val = vi_pre_read(dev, HDRPRO_LINA(10)); + val |= (0x9fff << HDRPRO_LINA10_A10_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(10), val); + + val = vi_pre_read(dev, HDRPRO_LINB(10)); + val |= (0x9000 << HDRPRO_LINB10_B10_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(10), val); + + val = vi_pre_read(dev, HDRPRO_LINW(11)); + val |= (0x100 << HDRPRO_LINW6_W11_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(11), val); + + val = vi_pre_read(dev, HDRPRO_LINA(11)); + val |= (0xafff << HDRPRO_LINA11_A11_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(11), val); + + val = vi_pre_read(dev, HDRPRO_LINB(11)); + val |= (0xa000 << HDRPRO_LINB11_B11_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(11), val); + + val = vi_pre_read(dev, HDRPRO_LINW(12)); + val |= (0x100 << HDRPRO_LINW6_W12_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(12), val); + + val = vi_pre_read(dev, HDRPRO_LINA(12)); + val |= (0xbfff << HDRPRO_LINA12_A12_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(12), val); + + val = vi_pre_read(dev, HDRPRO_LINB(12)); + val |= (0xb000 << HDRPRO_LINB12_B12_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(12), val); + + val = vi_pre_read(dev, HDRPRO_LINW(13)); + val |= (0x100 << HDRPRO_LINW7_W13_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(13), val); + + val = vi_pre_read(dev, HDRPRO_LINA(13)); + val |= (0xcfff << HDRPRO_LINA13_A13_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(13), val); + + val = vi_pre_read(dev, HDRPRO_LINB(13)); + val |= (0xc000 << HDRPRO_LINB13_B13_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(13), val); + + val = vi_pre_read(dev, HDRPRO_LINW(14)); + val |= (0x100 << HDRPRO_LINW7_W14_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(14), val); + + val = vi_pre_read(dev, HDRPRO_LINA(14)); + val |= (0xdfff << HDRPRO_LINA14_A14_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(14), val); + + val = vi_pre_read(dev, HDRPRO_LINB(14)); + val |= (0xd000 << HDRPRO_LINB14_B14_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(14), val); + + val = vi_pre_read(dev, HDRPRO_LINW(15)); + val |= (0x100 << HDRPRO_LINW8_W15_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(15), val); + + val = vi_pre_read(dev, HDRPRO_LINA(15)); + val |= (0xefff << HDRPRO_LINA15_A15_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(15), val); + + val = vi_pre_read(dev, HDRPRO_LINB(15)); + val |= (0xe000 << HDRPRO_LINB15_B15_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(15), val); + + val = vi_pre_read(dev, HDRPRO_LINW(16)); + val |= (0x100 << HDRPRO_LINW8_W16_SHIFT); + vi_pre_write(dev, HDRPRO_LINW(16), val); + + val = vi_pre_read(dev, HDRPRO_LINA(16)); + val |= (0xffff << HDRPRO_LINA16_A16_SHIFT); + vi_pre_write(dev, HDRPRO_LINA(16), val); + + val = vi_pre_read(dev, HDRPRO_LINB(16)); + val |= (0xffff << HDRPRO_LINB16_B16_SHIFT); + vi_pre_write(dev, HDRPRO_LINB(16), val); + + return ret; +} + +static int vi_pre_set_mipi2dma_n_line(struct vi_pre_dev *dev, void *args) +{ +#define WIDTH 640 +#define HEIGHT 480 +#define RAW_SIZE 16 //RAW12 +#define BURST_LEN 16 +#define OUT_STANDING 1024 +//K > N, N>2 +#define K_LINE 32 +#define N_LINE 16 + + int ret = 0; + unsigned int val = 0; + unsigned int stride = 0; + unsigned int horizon_cnt128 = 0; + unsigned int readnum = 0; + + stride = WIDTH * RAW_SIZE / 8; + horizon_cnt128 = stride / 16; + readnum = horizon_cnt128 / BURST_LEN; + + //base mode config + //val = vi_pre_read(dev, MIPI2DMA_CTRL(0)); + val = 0; + val |= MIPI2DMA_CTRL0_MODE_N_LINE; + val |= MIPI2DMA_CTRL0_RAW10; + val |= MIPI2DMA_CTRL0_HIGH_BIT_MODE; + //val |= MIPI2DMA_CTRL0_4_FRAME; + vi_pre_write(dev, MIPI2DMA_CTRL(0), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(1)); + val = 0; + val |= MIPI2DMA_CTRL1_WBURSTLEN_16; + val |= ((OUT_STANDING - 1) << MIPI2DMA_CTRL1_WOSNUM_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(1), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(3)); + val = 0; + val |= (WIDTH << MIPI2DMA_CTRL3_HORIZON_SHIFT); + val |= (HEIGHT << MIPI2DMA_CTRL3_VERTICAL_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(3), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(4)); + val = 0; + //need calculate BURSTREM by unsing the function from vipre doc + val |= (BURST_LEN << MIPI2DMA_CTRL4_BURSTREM_SHIFT); + val |= (readnum << MIPI2DMA_CTRL4_READNUM_SHIFT); + val |= (horizon_cnt128 << MIPI2DMA_CTRL4_HORIZON_CNT128_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(4), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(5)); + val = 0; + val |= (N_LINE << MIPI2DMA_CTRL5_N_NLINENUM_SHIFT); + val |= (K_LINE << MIPI2DMA_CTRL5_N_LINENUM_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(5), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(6)); + val = 0; + val |= (stride << MIPI2DMA_CTRL6_N_STRIDE_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(6), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(51)); + val |= MIPI2DMA_CTRL51_CROSS_4K_EN; + vi_pre_write(dev, MIPI2DMA_CTRL(51), val); + + //feedback config to default + //clear INV_FLAG + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(11), val); + + //clear N_LINENUM_NEW_ID0 + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(12), val); + //clear N_LINENUM_NEW_ID1 + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(13), val); + //clear N_LINENUM_NEW_ID2 + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(14), val); + + //clear N_num_done_idx + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(21), val); + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(22), val); + + //N ID0 address + //val = vi_pre_read(dev, MIPI2DMA_CTRL(15)); + val = 0; + val |= (0x0 << MIPI2DMA_CTRL15_N_SADDR_ID0_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(15), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(16)); + val = 0; + val |= (0xf0000000 << MIPI2DMA_CTRL16_N_SADDR_ID0_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(16), val); + + //N ID1 address + //val = vi_pre_read(dev, MIPI2DMA_CTRL(17)); + val = 0; + val |= (0x0 << MIPI2DMA_CTRL17_N_SADDR_ID1_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(17), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(18)); + val = 0; + val |= (0xf1000000 << MIPI2DMA_CTRL18_N_SADDR_ID1_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(18), val); + + //N ID2 address + //val = vi_pre_read(dev, MIPI2DMA_CTRL(19)); + val = 0; + val |= (0x0 << MIPI2DMA_CTRL19_N_SADDR_ID2_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(19), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(20)); + val = 0; + val |= (0xf2000000 << MIPI2DMA_CTRL20_N_SADDR_ID2_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(20), val); + + // int status clean & mask + //val = vi_pre_read(dev, MIPI2DMA_CTRL(44)); + //enable all interrupt + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(44), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(10)); + val |= MIPI2DMA_START; + vi_pre_write(dev, MIPI2DMA_CTRL(10), val); + + return ret; +} + +static int vi_pre_set_mipi2dma_m_frame(struct vi_pre_dev *dev, void *args) +{ +#define WIDTH 640 +#define HEIGHT 480 +#define RAW_SIZE 16 //RAW12 +#define BURST_LEN 16 +#define OUT_STANDING 1024 + + int ret = 0; + unsigned int val = 0; + unsigned int stride = 0; + unsigned int horizon_cnt128 = 0; + unsigned int readnum = 0; + + stride = WIDTH * RAW_SIZE / 8; + horizon_cnt128 = stride / 16; + readnum = horizon_cnt128 / BURST_LEN; + + //base mode config + //val = vi_pre_read(dev, MIPI2DMA_CTRL(0)); + val = 0; + val |= MIPI2DMA_CTRL0_MODE_M_FRAME; + val |= MIPI2DMA_CTRL0_RAW10; + val |= MIPI2DMA_CTRL0_HIGH_BIT_MODE; + val |= MIPI2DMA_CTRL0_4_FRAME; + vi_pre_write(dev, MIPI2DMA_CTRL(0), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(1)); + val = 0; + val |= MIPI2DMA_CTRL1_WBURSTLEN_16; + val |= ((OUT_STANDING - 1) << MIPI2DMA_CTRL1_WOSNUM_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(1), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(3)); + val = 0; + val |= (WIDTH << MIPI2DMA_CTRL3_HORIZON_SHIFT); + val |= (HEIGHT << MIPI2DMA_CTRL3_VERTICAL_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(3), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(4)); + val = 0; + //need calculate BURSTREM by unsing the function from vipre doc + val |= (BURST_LEN << MIPI2DMA_CTRL4_BURSTREM_SHIFT); + val |= (readnum << MIPI2DMA_CTRL4_READNUM_SHIFT); + val |= (horizon_cnt128 << MIPI2DMA_CTRL4_HORIZON_CNT128_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(4), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(7)); + val = 0; + val |= (stride << MIPI2DMA_CTRL7_M0_STRIDE_SHIFT); + val |= (stride << MIPI2DMA_CTRL7_M1_STRIDE_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(7), val); + + //val = vi_pre_read(dev, MIPI2DMA_CTRL(8)); + val = 0; + val |= (stride << MIPI2DMA_CTRL8_M2_STRIDE_SHIFT); + val |= (stride << MIPI2DMA_CTRL8_M3_STRIDE_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(8), val); + + //M0 ADDR + val = vi_pre_read(dev, MIPI2DMA_CTRL(25)); + val |= (0x0 << MIPI2DMA_CTRL25_M0_SADDR_ID0_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(25), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(26)); + val |= (0xF0000000 << MIPI2DMA_CTRL26_M0_SADDR_ID0_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(26), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(27)); + val |= (0x0 << MIPI2DMA_CTRL27_M0_SADDR_ID1_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(27), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(28)); + val |= (0xF1000000 << MIPI2DMA_CTRL28_M0_SADDR_ID1_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(28), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(29)); + val |= (0x0 << MIPI2DMA_CTRL29_M0_SADDR_ID2_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(29), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(30)); + val |= (0xF2000000 << MIPI2DMA_CTRL30_M0_SADDR_ID2_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(30), val); + + //M1 ADDR + val = vi_pre_read(dev, MIPI2DMA_CTRL(31)); + val |= (0x0 << MIPI2DMA_CTRL31_M1_SADDR_ID0_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(31), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(32)); + val |= (0xF3000000 << MIPI2DMA_CTRL32_M1_SADDR_ID0_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(32), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(33)); + val |= (0x0 << MIPI2DMA_CTRL33_M1_SADDR_ID1_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(33), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(34)); + val |= (0xF4000000 << MIPI2DMA_CTRL34_M1_SADDR_ID1_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(34), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(35)); + val |= (0x0 << MIPI2DMA_CTRL35_M1_SADDR_ID2_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(35), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(36)); + val |= (0xF5000000 << MIPI2DMA_CTRL36_M1_SADDR_ID2_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(36), val); + + //M2 ADDR + val = vi_pre_read(dev, MIPI2DMA_CTRL(37)); + val |= (0x0 << MIPI2DMA_CTRL37_M2_SADDR_ID0_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(37), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(38)); + val |= (0xF6000000 << MIPI2DMA_CTRL38_M2_SADDR_ID0_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(38), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(39)); + val |= (0x0 << MIPI2DMA_CTRL39_M2_SADDR_ID1_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(39), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(40)); + val |= (0xF7000000 << MIPI2DMA_CTRL40_M2_SADDR_ID1_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(40), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(41)); + val |= (0x0 << MIPI2DMA_CTRL41_M2_SADDR_ID2_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(41), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(42)); + val |= (0xF8000000 << MIPI2DMA_CTRL42_M2_SADDR_ID2_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(42), val); + + //M3 ADDR + val = vi_pre_read(dev, MIPI2DMA_CTRL(45)); + val |= (0x0 << MIPI2DMA_CTRL45_M3_SADDR_ID0_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(45), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(46)); + val |= (0xF9000000 << MIPI2DMA_CTRL46_M3_SADDR_ID0_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(46), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(47)); + val |= (0x0 << MIPI2DMA_CTRL47_M3_SADDR_ID1_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(47), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(48)); + val |= (0xFa000000 << MIPI2DMA_CTRL48_M3_SADDR_ID1_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(48), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(49)); + val |= (0x0 << MIPI2DMA_CTRL49_M3_SADDR_ID2_H_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(49), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(50)); + val |= (0xFb000000 << MIPI2DMA_CTRL50_M3_SADDR_ID2_L_SHIFT); + vi_pre_write(dev, MIPI2DMA_CTRL(50), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(51)); + val |= MIPI2DMA_CTRL51_CROSS_4K_EN; + vi_pre_write(dev, MIPI2DMA_CTRL(51), val); + + // feedback config to default + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(11), val); + + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(23), val); + + val = 0; + vi_pre_write(dev, MIPI2DMA_CTRL(24), val); + + // int status clean & mask + //val = vi_pre_read(dev, MIPI2DMA_CTRL(44)); + //enable all interrupt + val = 0; //open all interrupt + vi_pre_write(dev, MIPI2DMA_CTRL(44), val); + + val = vi_pre_read(dev, MIPI2DMA_CTRL(10)); + val |= MIPI2DMA_START; + vi_pre_write(dev, MIPI2DMA_CTRL(10), val); + + return ret; +} + +static u16 read_interrupt_status(struct vi_pre_dev *dev) +{ + return vi_pre_read(dev, MIPI2DMA_CTRL(44)) & 0x1ff; +} + +static u32 mframe_frame_done_flag(struct vi_pre_dev *dev) +{ + return vi_pre_read(dev, MIPI2DMA_CTRL(43)) & 0xfff; +} + +static void mframe_frame_done_flag_clear(struct vi_pre_dev *dev, u32 mask) +{ + u32 reg_val = vi_pre_read(dev, MIPI2DMA_CTRL(43)); + reg_val |= mask; + vi_pre_write(dev, MIPI2DMA_CTRL(43), mask); +} +static int get_frame_num(struct vi_pre_dev *dev) +{ + u32 reg_val = vi_pre_read(dev, MIPI2DMA_CTRL(0)); + reg_val &= (3 << 2); + return (reg_val >> 2) + 1; +} + +static void dma_period_clear(struct vi_pre_dev *dev, int ch) +{ + u32 reg_val = vi_pre_read(dev, MIPI2DMA_CTRL(11)); + if (reg_val & (1 << ch)) { + reg_val &= ~(1 << ch); + } else { + reg_val |= (1 << ch); + } + vi_pre_write(dev, MIPI2DMA_CTRL(11), reg_val); +} + +void vi_pre_interrupt_handler(struct vi_pre_dev *dev) +{ + u32 status = read_interrupt_status(dev); + u32 f_done_sta = 0; + int i = 0; + + if (status & VIPRE_FRAME_DONE) { + f_done_sta = mframe_frame_done_flag(dev); + for(i = 11; i >= 0; i--) { + if (f_done_sta & (1 << i)) { + if (i >= 8) { + dev->cnt[0]++; + } else if (i >= 4) { + dev->cnt[1]++; + } else { + dev->cnt[2]++; + } + } + } + mframe_frame_done_flag_clear(dev, f_done_sta); + /*TODO send event*/ + //printk("frame done %x\n", f_done_sta); + } else if (status & VIPRE_LINE_DONE) { + //u32 nline_done_sta =; + //pdriver_dev->cnt++; + //printk("line done %x\n", f_done_sta); + } + //u32 line_cnt = pdriver_dev->cnt * get_nline_int_period(pdriver_dev); + if (dev->is_mframe_mode) { + for(i = 0; i < 3; i++) { + if(dev->cnt[i] < get_frame_num(dev)) { + continue; + } + dev->cnt[i] = 0; + dma_period_clear(dev, i); + } + } +} + +unsigned int vi_pre_priv_ioctl(struct vi_pre_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + if (!dev) { + pr_err("%s invalid para\n", __func__); + return ret; + } + + switch (cmd) { + case VI_PRE_IOCTL_RESET: + ret = 0; + break; + case VI_PRE_IOCTL_WRITE_REG: + ret = vi_pre_write_reg(dev, (void *)args); + break; + case VI_PRE_IOCTL_READ_REG: + ret = vi_pre_read_reg(dev, (void *)args); + break; + case VI_PRE_IOCTL_SET_HDRPRO: + ret = vi_pre_set_hdrpro(dev, args); + break; + case VI_PRE_IOCTL_SET_MIPI2DMA_M_FRMAE: + ret = vi_pre_set_mipi2dma_m_frame(dev, args); + break; + case VI_PRE_IOCTL_SET_MIPI2DMA_N_LINE: + ret = vi_pre_set_mipi2dma_n_line(dev, args); + break; + default: + pr_err("unsupported command %d\n", cmd); + break; + } + + return ret; +} diff --git a/vvcam_ry/native/vi_pre/vi_pre_ioctl.h b/vvcam_ry/native/vi_pre/vi_pre_ioctl.h new file mode 100755 index 0000000..c28a59c --- /dev/null +++ b/vvcam_ry/native/vi_pre/vi_pre_ioctl.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: Shenwuyi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _VI_PRE_IOC_H_ +#define _VI_PRE_IOC_H_ +#include + +struct vi_pre_reg_t { + unsigned int offset; + unsigned int value; +}; + +enum { + VI_PRE_IOCTL_RESET = 0, + VI_PRE_IOCTL_WRITE_REG, + VI_PRE_IOCTL_READ_REG, + VI_PRE_IOCTL_SET_MIPI2DMA_M_FRMAE, + VI_PRE_IOCTL_SET_MIPI2DMA_N_LINE, + VI_PRE_IOCTL_SET_HDRPRO, + VI_PRE_IOCTL_MAX +}; +extern unsigned int vi_pre_priv_ioctl(struct vi_pre_dev *dev, unsigned int cmd, void *args); + +#endif /* _VI_PRE_IOC_H_ */ diff --git a/vvcam_ry/native/vi_pre/vi_pre_reg.h b/vvcam_ry/native/vi_pre/vi_pre_reg.h new file mode 100755 index 0000000..588ed62 --- /dev/null +++ b/vvcam_ry/native/vi_pre/vi_pre_reg.h @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: Shenwuyi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _VI_PRE_REG_H_ +#define _VI_PRE_REG_H_ +#define G1_MUX3_2 0x0 +#define G1_MODSEL 0x4 +#define G1_IDNUM 0x8 +#define G1_RESCFG 0xC +#define G1_HDRCTRL0 0x10 +#define G1_HDRCTRL1 0x14 +#define G1_HDRCTRL2 0x18 +#define G1_HDRCTRL3 0x1C +#define G1_HDRCTRL4 0x20 +#define G1_ERR_MAKS 0x24 +#define G1_VMARGINCFG_IPI1 0x28 +#define G1_HMARGINCFG_IPI1 0x2C +#define G1_VMARGINCFG_IPI2 0x30 +#define G1_HMARGINCFG_IPI2 0x34 +#define G1_VMARGINCFG_IPI3 0x38 +#define G1_HMARGINCFG_IPI3 0x3C +#define G1_RESCFG2 0x40 +#define G1_RESCFG3 0x44 +#define G2_RESEV 0x48 +#define G2_MODSEL 0x4C +#define G2_IDNUM 0x50 +#define G2_RESCFG 0x54 +#define G2_HDRCTRL0 0x58 +#define G2_HDRCTRL1 0x5C +#define G2_HDRCTRL2 0x60 +#define G2_HDRCTRL3 0x64 +#define G2_HDRCTRL4 0x68 +#define G2_ERR_MAKS 0x6C +#define G2_VMARGINCFG_IPI1 0x70 +#define G2_HMARGINCFG_IPI1 0x74 +#define G2_VMARGINCFG_IPI2 0x78 +#define G2_HMARGINCFG_IPI2 0x7C +#define G2_VMARGINCFG_IPI3 0x80 +#define G2_HMARGINCFG_IPI3 0x84 +#define G2_RESCFG2 0x88 +#define G2_RESCFG3 0x8C +#define ISPSEL 0x90 +#define HDRPRO_CTRL1 0x94 +#define HDRPRO_CTRL2 0x98 +#define HDRPRO_COE1 0x9C +#define HDRPRO_COE2 0xA0 +#define HDRPRO_COE3 0xA4 +#define HDRPRO_COE4 0xA8 +#define HDRPRO_COE5 0xAC +#define HDRPRO_LINW1 0xB0 +#define HDRPRO_LINW2 0xB4 +#define HDRPRO_LINW3 0xB8 +#define HDRPRO_LINW4 0xBC +#define HDRPRO_LINW5 0xC0 +#define HDRPRO_LINW6 0xC4 +#define HDRPRO_LINW7 0xC8 +#define HDRPRO_LINW8 0xCC +#define HDRPRO_LINA1 0xD0 +#define HDRPRO_LINA2 0xD4 +#define HDRPRO_LINA3 0xD8 +#define HDRPRO_LINA4 0xDC +#define HDRPRO_LINA5 0xE0 +#define HDRPRO_LINA6 0xE4 +#define HDRPRO_LINA7 0xE8 +#define HDRPRO_LINA8 0xEC +#define HDRPRO_LINA9 0xF0 +#define HDRPRO_LINA10 0xF4 +#define HDRPRO_LINA11 0xF8 +#define HDRPRO_LINA12 0xFC +#define HDRPRO_LINA13 0x100 +#define HDRPRO_LINA14 0x104 +#define HDRPRO_LINA15 0x108 +#define HDRPRO_LINA16 0x10C +#define HDRPRO_LINB1 0x110 +#define HDRPRO_LINB2 0x114 +#define HDRPRO_LINB3 0x118 +#define HDRPRO_LINB4 0x11C +#define HDRPRO_LINB5 0x120 +#define HDRPRO_LINB6 0x124 +#define HDRPRO_LINB7 0x128 +#define HDRPRO_LINB8 0x12C +#define HDRPRO_LINB9 0x130 +#define HDRPRO_LINB10 0x134 +#define HDRPRO_LINB11 0x138 +#define HDRPRO_LINB12 0x13C +#define HDRPRO_LINB13 0x140 +#define HDRPRO_LINB14 0x144 +#define HDRPRO_LINB15 0x148 +#define HDRPRO_LINB16 0x14C +#define G0_RESEV 0x150 +#define G0_MODSEL 0x154 +#define G0_IDNUM 0x158 +#define G0_RESCFG 0x15C +#define G0_HDRCTRL0 0x160 +#define G0_HDRCTRL1 0x164 +#define G0_HDRCTRL2 0x168 +#define G0_HDRCTRL3 0x16C +#define G0_HDRCTRL4 0x170 +#define G0_ERR_MAKS 0x174 +#define G0_VMARGINCFG_IPI1 0x178 +#define G0_HMARGINCFG_IPI1 0x17C +#define G0_VMARGINCFG_IPI2 0x180 +#define G0_HMARGINCFG_IPI2 0x184 +#define G0_VMARGINCFG_IPI3 0x188 +#define G0_HMARGINCFG_IPI3 0x18C +#define G0_RESCFG2 0x190 +#define G0_RESCFG3 0x194 +#define MIPI2DMA_CTRL0 0x198 +#define MIPI2DMA_CTRL1 0x19C +#define MIPI2DMA_CTRL2 0x1A0 +#define MIPI2DMA_CTRL3 0x1A4 +#define MIPI2DMA_CTRL4 0x1A8 +#define MIPI2DMA_CTRL5 0x1AC +#define MIPI2DMA_CTRL6 0x1B0 +#define MIPI2DMA_CTRL7 0x1B4 +#define MIPI2DMA_CTRL8 0x1B8 +#define MIPI2DMA_CTRL9 0x1BC +#define MIPI2DMA_CTRL10 0x1C0 +#define MIPI2DMA_CTRL11 0x1C4 +#define MIPI2DMA_CTRL12 0x1C8 +#define MIPI2DMA_CTRL13 0x1CC +#define MIPI2DMA_CTRL14 0x1D0 +#define MIPI2DMA_CTRL15 0x1D4 +#define MIPI2DMA_CTRL16 0x1D8 +#define MIPI2DMA_CTRL17 0x1DC +#define MIPI2DMA_CTRL18 0x1E0 +#define MIPI2DMA_CTRL19 0x1E4 +#define MIPI2DMA_CTRL20 0x1E8 +#define MIPI2DMA_CTRL21 0x1EC +#define MIPI2DMA_CTRL22 0x1F0 +#define MIPI2DMA_CTRL23 0x1F4 +#define MIPI2DMA_CTRL24 0x1F8 +#define MIPI2DMA_CTRL25 0x1FC +#define MIPI2DMA_CTRL26 0x200 +#define MIPI2DMA_CTRL27 0x204 +#define MIPI2DMA_CTRL28 0x208 +#define MIPI2DMA_CTRL29 0x20C +#define MIPI2DMA_CTRL30 0x210 +#define MIPI2DMA_CTRL31 0x214 +#define MIPI2DMA_CTRL32 0x218 +#define MIPI2DMA_CTRL33 0x21C +#define MIPI2DMA_CTRL34 0x220 +#define MIPI2DMA_CTRL35 0x224 +#define MIPI2DMA_CTRL36 0x228 +#define MIPI2DMA_CTRL37 0x22C +#define MIPI2DMA_CTRL38 0x230 +#define MIPI2DMA_CTRL39 0x234 +#define MIPI2DMA_CTRL40 0x238 +#define MIPI2DMA_CTRL41 0x23C +#define MIPI2DMA_CTRL42 0x240 +#define MIPI2DMA_CTRL43 0x244 +#define MIPI2DMA_CTRL44 0x248 +#define MIPI2DMA_CTRL45 0x24C +#define MIPI2DMA_CTRL46 0x250 +#define MIPI2DMA_CTRL47 0x254 +#define MIPI2DMA_CTRL48 0x258 +#define MIPI2DMA_CTRL49 0x25C +#define MIPI2DMA_CTRL50 0x260 +#define MIPI2DMA_CTRL51 0x264 +#endif /*_VI_PRE_REG_H_*/ \ No newline at end of file diff --git a/vvcam_ry/readme-android.txt b/vvcam_ry/readme-android.txt new file mode 100755 index 0000000..2b979d0 --- /dev/null +++ b/vvcam_ry/readme-android.txt @@ -0,0 +1,9 @@ +To build under android top dir, please follow below steps. +1. clone the git under ANDROID_ROOT/vendor/nxp-opensource +2. check out to branch integration_vsi_4.0.8p2_android +3. cd ANDROID_ROOT +4. source build/envsetup.sh +5. lunch evk_8mp-userdebug +6. ./imx-make.sh kernel -j8 +7. ./imx-make.sh vvcam (add "-c" for clean build) +8. generate the ko in ANDROID_ROOT/out/target/product/evk_8mp/obj/VVCAM_OBJ/vvcam.ko diff --git a/vvcam_ry/readme.txt b/vvcam_ry/readme.txt new file mode 100755 index 0000000..063fef4 --- /dev/null +++ b/vvcam_ry/readme.txt @@ -0,0 +1,37 @@ +isp kernel driver (verisilicon) + +file description: + vvcam/common/video.c - register v4l2 video device, filename is /dev/videox, process standard v4l2 command. + vvcam/driver/isp_driver.c - register v4l2 subdev, filename is /dev/v4l-subdevx, supply full isp options for all modules. + units/ispdrv/isp/ic_dev.h - defined all isp main/sub modules structure. + units/ispdrv/isp/isp_ioctl.h - defined all isp ioctls and internal functions. + units/ispdrv/isp/isp_ioctl.c - dispatch ioctl and implement isp main functions.(need create new file if module code number larger than 100, such as wdr3, 3dnr) + units/ispdrv/isp/cma.h - continuous memory allocator, user may need replace it. + +setup environment: + cd appshell + source environment-setup--linux + source environment-setup-x86_64-linux + +build: + cd vvcam/native + make VERSION_CFG=ISP8000NANO_V1802 +clean: + cd vvcam/native + make clean + +install: + cd vvcam/native/bin + ./insmod.sh + +unistall: + cd vvcam/native/bin + ./rmmod.sh + + +porting guide: + 1. modify ISP_REG_BASE and ISP_REG_BASE in version.h + 2. modify RESERVED_MEM_BASE and RESERVED_MEM_SIZE in version.h + 3. for use cma, user need modify linux dts file to map the device memory. + or replace vb2_cma_alloc to default vb2 mem_ops. + diff --git a/vvcam_ry/readme_v4l2.txt b/vvcam_ry/readme_v4l2.txt new file mode 100755 index 0000000..f6df294 --- /dev/null +++ b/vvcam_ry/readme_v4l2.txt @@ -0,0 +1,65 @@ +build +x86 +make BUILD_TYPE=fpga WITH_DWE=1 VERSION=ISP8000NANO_V1802 +arm64 +make VERSION=ISP8000NANO_V1802 KERNEL_SRC=$(arm_kernel_src) + +generate kernel modules, support hot plug. +find -name *.ko +./v4l2/vvcam-dwe.ko +./v4l2/sensor/ov2775/ov2775.ko +./v4l2/sensor/os08a20/os08a20.ko +./v4l2/csi/samsung/vvcam-csis.ko +./v4l2/video/vvcam-video.ko +./v4l2/vvcam-isp.ko +.. + + + + +(1)编译imx8-media-dev.ko +mkdir build_v8 && cd build_v8 +make ARCH=arm64 menuconfig + Device Drivers ---> + [*] Staging drivers ---> + [*] Media staging drivers ---> + i.MX8QXP/QM Camera ISI/MIPI Features support ---> + IMX8 Media Device Driver +make -j4 + +(2)编译vvcam +DWE disable IRQ: +make VERSION=ISP8000NANO_V1802 KERNEL_SRC=$(arm_kernel_src) ENABLE_IRQ=no + +DWE enable IRQ: +make VERSION=ISP8000NANO_V1802 KERNEL_SRC=$(arm_kernel_src) ENABLE_IRQ=yes + +(3)加载KO +ov2775 insmod: +cp $Kernel_SRC/driver/staging/media/imx/imx8-media-dev.ko to your board directory +insmod vvcam-video.ko +insmod ov2775.ko +insmod vvcam-dwe.ko +insmod vvcam-isp.ko +insmod imx8-media-dev.ko + + +os08a20 insmod: +cp $Kernel_SRC/driver/staging/media/imx/imx8-media-dev.ko to your board directory +insmod vvcam-video.ko +insmod os08a20.ko +insmod vvcam-dwe.ko +insmod vvcam-isp.ko +insmod imx8-media-dev.ko + +T-Head Light insmod: +insmod vvcam-video.ko +insmod ov2775.ko +insmod vvcam-csis.ko +insmod vvcam-dwe.ko +insmod vvcam-isp.ko + +(4)运行server: +./isp_media_server CAMERA0 & + + diff --git a/vvcam_ry/soc/soc_ioctl.c b/vvcam_ry/soc/soc_ioctl.c new file mode 100755 index 0000000..02e7bd7 --- /dev/null +++ b/vvcam_ry/soc/soc_ioctl.c @@ -0,0 +1,261 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef __KERNEL__ +#include +#include +#include +#include + +#define pr_info printf +#define pr_err printf +#define copy_from_user(a, b, c) soc_copy_data(a, b, c) +#define copy_to_user(a, b, c) soc_copy_data(a, b, c) +#define __user +#define __iomem + +void soc_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); +} + +#else // __KERNEL__ +#include /* Module support */ +#include + +#endif + +#include "soc_ioctl.h" +#include "vivsoc_hub.h" + + +long soc_priv_ioctl(struct vvcam_soc_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + struct soc_control_context soc_ctrl; + if (!dev) { + return ret; + } + + switch (cmd) { + /* ISP part */ + case VVSOC_IOC_S_RESET_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_ISP: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* DWE part */ + case VVSOC_IOC_S_RESET_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_dwe_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_DWE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_isp_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* VSE part */ + case VVSOC_IOC_S_RESET_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_VSE: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_vse_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + + /* CSI part */ + case VVSOC_IOC_S_RESET_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_CSI: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_csi_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + /* sensor part */ + case VVSOC_IOC_S_RESET_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_reset(dev, &soc_ctrl); + break; + + case VVSOC_IOC_S_POWER_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_s_power_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_POWER_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_g_power_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + case VVSOC_IOC_S_CLOCK_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_s_clock_ctrl(dev, &soc_ctrl); + break; + + case VVSOC_IOC_G_CLOCK_SENSOR: + copy_from_user(&soc_ctrl, args, sizeof(soc_ctrl)); + ret = vivsoc_hub_sensor_g_clock_ctrl(dev, &soc_ctrl); + copy_to_user(args, &soc_ctrl, sizeof(soc_ctrl)); + break; + + + default: + pr_err("unsupported command %d", cmd); + break; + } + + return ret; +} + +extern struct vvcam_soc_function_s gen6_soc_function; + +int vvnative_soc_init(struct vvcam_soc_dev *dev) +{ + if (dev == NULL) + { + pr_err("[%s] dev is NULL\n", __func__); + return -1; + } + + vivsoc_register_hardware(dev, &gen6_soc_function); + return 0; +} + +int vvnative_soc_deinit(struct vvcam_soc_dev *dev) +{ + return 0; +} + + diff --git a/vvcam_ry/soc/soc_ioctl.h b/vvcam_ry/soc/soc_ioctl.h new file mode 100755 index 0000000..6d01f40 --- /dev/null +++ b/vvcam_ry/soc/soc_ioctl.h @@ -0,0 +1,158 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _SOC_IOC_H_ +#define _SOC_IOC_H_ + +#ifndef __KERNEL__ +#include +#endif + +#include + +enum { + VVSOC_IOC_S_RESET_ISP = _IO('r', 0), + VVSOC_IOC_S_POWER_ISP, + VVSOC_IOC_G_POWER_ISP, + VVSOC_IOC_S_CLOCK_ISP, + VVSOC_IOC_G_CLOCK_ISP, + + VVSOC_IOC_S_RESET_DWE, + VVSOC_IOC_S_POWER_DWE, + VVSOC_IOC_G_POWER_DWE, + VVSOC_IOC_S_CLOCK_DWE, + VVSOC_IOC_G_CLOCK_DWE, + + VVSOC_IOC_S_RESET_VSE, + VVSOC_IOC_S_POWER_VSE, + VVSOC_IOC_G_POWER_VSE, + VVSOC_IOC_S_CLOCK_VSE, + VVSOC_IOC_G_CLOCK_VSE, + + VVSOC_IOC_S_RESET_CSI, + VVSOC_IOC_S_POWER_CSI, + VVSOC_IOC_G_POWER_CSI, + VVSOC_IOC_S_CLOCK_CSI, + VVSOC_IOC_G_CLOCK_CSI, + + VVSOC_IOC_S_RESET_SENSOR, + VVSOC_IOC_S_POWER_SENSOR, + VVSOC_IOC_G_POWER_SENSOR, + VVSOC_IOC_S_CLOCK_SENSOR, + VVSOC_IOC_G_CLOCK_SENSOR, + + VVSOC_IOC_S_RESET_ISP_RY, + VVSOC_IOC_S_POWER_ISP_RY, + VVSOC_IOC_G_POWER_ISP_RY, + VVSOC_IOC_S_CLOCK_ISP_RY, + VVSOC_IOC_G_CLOCK_ISP_RY, + + VVSOC_IOC_MAX, +}; + +struct soc_control_context { + uint32_t device_idx; + uint32_t control_value; +}; + +struct vvcam_soc_func_s +{ + int (*set_power)(void*,unsigned int,unsigned int); + int (*get_power)(void*,unsigned int,unsigned int *); + int (*set_reset)(void*,unsigned int,unsigned int); + int (*set_clk)(void*,unsigned int,unsigned int); + int (*get_clk)(void*,unsigned int,unsigned int *); +}; + +struct vvcam_soc_function_s +{ + struct vvcam_soc_func_s isp_func; + struct vvcam_soc_func_s dwe_func; + struct vvcam_soc_func_s vse_func; + struct vvcam_soc_func_s csi_func; + struct vvcam_soc_func_s sensor_func; +}; + +struct vvcam_soc_access_s +{ + int (*write)(void * ctx, uint32_t address, uint32_t data); + int (*read)(void * ctx, uint32_t address, uint32_t *data); +}; + + +#ifdef __KERNEL__ + +struct vvcam_soc_dev { + void __iomem *base; + struct soc_control_context isp0; + struct soc_control_context isp1; + struct soc_control_context dwe; + struct soc_control_context vse; + struct vvcam_soc_function_s soc_func; + struct vvcam_soc_access_s soc_access; + void * csi_private; +}; +// internal functions + +long soc_priv_ioctl(struct vvcam_soc_dev *dev, unsigned int cmd, void *args); +int vvnative_soc_init(struct vvcam_soc_dev *dev); +int vvnative_soc_deinit(struct vvcam_soc_dev *dev); + + + +#else +//User space connections + + +#endif + +#endif // _SOC_IOC_H_ diff --git a/vvcam_ry/soc/vivsoc_hub.c b/vvcam_ry/soc/vivsoc_hub.c new file mode 100755 index 0000000..12c2c26 --- /dev/null +++ b/vvcam_ry/soc/vivsoc_hub.c @@ -0,0 +1,586 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include + +#include "soc_ioctl.h" +#include "vivsoc_hub.h" +#include "vsi_core_gen6.h" + + +int vivsoc_hub_isp_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_isp_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.isp_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.isp_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_dwe_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_dwe_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.dwe_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.dwe_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_vse_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_vse_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.vse_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.vse_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +int vivsoc_hub_csi_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_csi_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.csi_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.csi_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_reset == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_reset(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_power(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.get_power == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.get_power(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.set_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.set_clk(dev, soc_ctrl->device_idx, soc_ctrl->control_value); + + return ret; +} + +int vivsoc_hub_sensor_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl) +{ + int ret = 0; + if ((dev==NULL) || (soc_ctrl == NULL)) + { + pr_err("[%s]:dev is null\n", __func__); + return -1; + } + + if (dev->soc_func.sensor_func.get_clk == NULL) + { + pr_err("[%s] function is null\n", __func__); + return -1; + } + + ret = dev->soc_func.sensor_func.get_clk(dev, soc_ctrl->device_idx, &soc_ctrl->control_value); + + return ret; +} + + + +unsigned int vivsoc_register_hardware(struct vvcam_soc_dev *dev, struct vvcam_soc_function_s *func) +{ + if (func == NULL) + { + return -1; + } + + memcpy(&dev->soc_func,func,sizeof(struct vvcam_soc_function_s)); + + dev->soc_access.write = gen6_write_reg; + dev->soc_access.read = gen6_read_reg; + + return 0; +} + + + + diff --git a/vvcam_ry/soc/vivsoc_hub.h b/vvcam_ry/soc/vivsoc_hub.h new file mode 100755 index 0000000..3c99805 --- /dev/null +++ b/vvcam_ry/soc/vivsoc_hub.h @@ -0,0 +1,88 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VIVSOC_HUB_H_ +#define _VIVSOC_HUB_H_ + +int vivsoc_hub_isp_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_isp_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_dwe_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_dwe_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_vse_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_vse_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_csi_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_csi_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +int vivsoc_hub_sensor_reset(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_s_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_g_power_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_s_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); +int vivsoc_hub_sensor_g_clock_ctrl(struct vvcam_soc_dev *dev, struct soc_control_context * soc_ctrl); + +unsigned int vivsoc_register_hardware(struct vvcam_soc_dev *dev, struct vvcam_soc_function_s *func); + +#endif /* _VIVSOC_HUB_H_ */ diff --git a/vvcam_ry/soc/vsi/soc_i2c.c b/vvcam_ry/soc/vsi/soc_i2c.c new file mode 100755 index 0000000..51d7345 --- /dev/null +++ b/vvcam_ry/soc/vsi/soc_i2c.c @@ -0,0 +1,372 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct soc_gpio_i2c{ + struct i2c_adapter adap; + unsigned long phy_base_addr; + unsigned long size; + void __iomem * virt_base_addr; + spinlock_t lock; +}; + + +static void i2c_gpio_setsda_val(void *source, int state) +{ + struct soc_gpio_i2c *i2c = source; + int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~0x1)) | (0x10 | (state & 0x01)); + + writel(reg_data, i2c->virt_base_addr); + return ; +} + +static void i2c_gpio_setscl_val(void *source, int state) +{ + struct soc_gpio_i2c *i2c = source; + int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~(0x1 << 8))) | ((0x10 | (state & 0x01)) << 8); + + writel(reg_data, i2c->virt_base_addr); + return ; +} + +static int i2c_gpio_getsda(void *source) +{ + struct soc_gpio_i2c *i2c = source; + unsigned int reg_data; + + reg_data = readl(i2c->virt_base_addr); + reg_data = (reg_data & (~0x10)); + writel(reg_data, i2c->virt_base_addr); + + return (readl(i2c->virt_base_addr) & 0x01); +} +// Start :When SCL is High ,SDA Change to low +static void i2c_gpio_start(void *source) +{ + i2c_gpio_setscl_val(source, 1); + i2c_gpio_setsda_val(source, 1); + udelay(5); + i2c_gpio_setsda_val(source, 0); + udelay(1); + return; +} +//Send Bit : When SCL is LOW, sda change;When SCL is HIgh,SDA hold; +static void i2c_gpio_send_byte(void *source, unsigned char val) +{ + int bit_idx; + for (bit_idx=7; bit_idx >= 0; bit_idx--) + { + i2c_gpio_setscl_val(source, 0); + i2c_gpio_setsda_val(source, (val >> bit_idx) & 0x01); + udelay(1); + i2c_gpio_setscl_val(source, 1); + udelay(1); + } + i2c_gpio_setscl_val(source, 0); + i2c_gpio_setsda_val(source, 1); + return; +} +//Read Bit: When SCL is High read data; +static unsigned char i2c_gpio_read_byte(void *source) +{ + int bit_idx; + unsigned char data = 0; + + i2c_gpio_getsda(source);//SDA change to read + + for(bit_idx=7; bit_idx>=0; bit_idx--) + { + + i2c_gpio_setscl_val(source, 1); + udelay(1); + data = (data << 1) | i2c_gpio_getsda(source); + i2c_gpio_setscl_val(source, 0); + udelay(1); + } + return data; +} + +static int i2c_gpio_wait_ack(void *source) +{ + unsigned int i2c_retry_ack_cnt = 0; + + i2c_gpio_getsda(source);//SDA change to read + udelay(1); + i2c_gpio_setscl_val(source, 1); + + while(i2c_gpio_getsda(source) == 1) + { + udelay(1); + if (i2c_retry_ack_cnt++ > 20) + { + return 0; + } + } + i2c_gpio_setscl_val(source, 0); + return 1; +} + +static void i2c_gpio_stop(void *source) +{ + i2c_gpio_setsda_val(source, 0); + udelay(1); + i2c_gpio_setscl_val(source, 1); + udelay(1); + i2c_gpio_setsda_val(source, 1); + return; +} + +static int i2c_gpio_write(void *source,struct i2c_msg *msg) +{ + + unsigned char slave_address; + unsigned char *buf; + int i; + slave_address = (msg->addr) << 1; + buf = msg->buf; + + i2c_gpio_start(source); + i2c_gpio_send_byte(source, slave_address); + if (i2c_gpio_wait_ack(source) == 0) return -1; + + for (i = 0; i < msg->len; i++) + { + i2c_gpio_send_byte(source, buf[i]); + i2c_gpio_wait_ack(source); + } + + i2c_gpio_stop(source); + return 0; +} + +static int i2c_gpio_read(void *source,struct i2c_msg *msg) +{ + unsigned char slave_address; + unsigned char *buf; + int i; + slave_address = ((msg->addr) << 1) | 0x01; + buf = msg->buf; + + i2c_gpio_start(source); + i2c_gpio_send_byte(source, slave_address); + if (i2c_gpio_wait_ack(source) == 0) return -1; + + for (i = 0; i < msg->len; i++) + { + buf[i] = i2c_gpio_read_byte(source); + i2c_gpio_wait_ack(source); + } + + return 0; +} + +static int i2c_gpio_xfer(struct i2c_adapter *adapter, + struct i2c_msg *msgs, int num) +{ + int result; + int i; + struct soc_gpio_i2c *i2c; + void *source; + + source = i2c_get_adapdata(adapter); + i2c = source; + + for (i=0; idev, sizeof(struct soc_gpio_i2c), GFP_KERNEL); + if (!i2c) + { + return -ENOMEM; + } + memset(i2c, 0, sizeof(struct soc_gpio_i2c)); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + i2c->phy_base_addr = mem->start; + i2c->size = mem->end - mem->start + 1; + //i2c->virt_base_addr = devm_ioremap_resource(&pdev->dev, mem); + //if (IS_ERR(i2c->virt_base_addr)) + // return PTR_ERR(i2c->virt_base_addr); + i2c->virt_base_addr = (void __iomem *)mem->name; + + spin_lock_init(&(i2c->lock)); + + adap = &i2c->adap; + platform_set_drvdata(pdev, adap); + + i2c_set_adapdata(adap, i2c); + adap->owner = THIS_MODULE; + snprintf(adap->name, sizeof(adap->name), "soc_gpio_i2c"); + adap->timeout = 2 * HZ; + adap->retries = 0; + adap->algo = &gpio_i2c_algo; + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + adap->dev.parent = &pdev->dev; + adap->nr = pdev->id; + adap->dev.of_node = pdev->dev.of_node; + + ret = i2c_add_numbered_adapter(adap); + if (ret) + { + pr_info("%s:i2c_add_adapter failed 0x%x\n", __func__, ret); + kfree(i2c); + return ret; + } + + return 0; +} + +static int soc_gpio_i2c_remove(struct platform_device *pdev) +{ + struct i2c_adapter *adap; + + adap = platform_get_drvdata(pdev); + i2c_del_adapter(adap); + + return 0; +} + +static struct platform_driver soc_gpio_i2c_driver = { + .probe = soc_gpio_i2c_probe, + .remove = soc_gpio_i2c_remove, + .driver = { + .name = "soc_gpio_i2c", + .owner = THIS_MODULE, + }, +}; + +static unsigned int i2c_driver_register_flag = 0; + +int soc_gpio_i2c_driver_init(void) +{ + if (i2c_driver_register_flag == 0) + { + platform_driver_register(&soc_gpio_i2c_driver); + } + i2c_driver_register_flag++; + return 0; +} +void soc_gpio_i2c_driver_exit(void) +{ + if (i2c_driver_register_flag == 1) + { + pr_info("enter %s\n", __func__); + platform_driver_unregister(&soc_gpio_i2c_driver); + } + + i2c_driver_register_flag--; + return; +} + + + + + + diff --git a/vvcam_ry/soc/vsi/soc_i2c.h b/vvcam_ry/soc/vsi/soc_i2c.h new file mode 100755 index 0000000..5789029 --- /dev/null +++ b/vvcam_ry/soc/vsi/soc_i2c.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _SOC_I2C_H_ +#define _SOC_I2C_H_ + +//int gen6_i2c_wr(unsigned int dev_address, unsigned int reg_address, unsigned int reg_data); +//unsigned int gen6_i2c_rd(unsigned int dev_address, unsigned int reg_address); + +int soc_gpio_i2c_driver_init(void); +void soc_gpio_i2c_driver_exit(void); +int soc_gpio_i2c_register_bus(unsigned int index,unsigned int bus,unsigned long base_addr, unsigned int size, + void * virt_base); + +void soc_gpio_i2c_unregister_bus(unsigned int index); + + +#endif diff --git a/vvcam_ry/soc/vsi/soc_i2c_dev.c b/vvcam_ry/soc/vsi/soc_i2c_dev.c new file mode 100755 index 0000000..9e2e7e2 --- /dev/null +++ b/vvcam_ry/soc/vsi/soc_i2c_dev.c @@ -0,0 +1,146 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include + + +static void soc_gpio_i2c_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); + return; +} + + +static struct resource soc_gpio_i2c0_resource[] = { + [0] = { + .start = 0x00, + .end = 0x00, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device soc_gpio_i2c0_pdev = { + .name = "soc_gpio_i2c", + .id = -1, + .resource = soc_gpio_i2c0_resource, + .num_resources = 1, + .dev.release = soc_gpio_i2c_release, +}; + +static struct resource soc_gpio_i2c1_resource[] = { + [0] = { + .start = 0x00, + .end = 0x00, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device soc_gpio_i2c1_pdev = { + .name = "soc_gpio_i2c", + .id = -1, + .resource = soc_gpio_i2c1_resource, + .num_resources = 1, + .dev.release = soc_gpio_i2c_release, +}; + +int soc_gpio_i2c_register_bus(unsigned int index,unsigned int bus,unsigned long base_addr, unsigned int size, + void * virt_base) +{ + int ret = 0; + struct platform_device * i2c_pdev; + pr_info("enter %s\n", __func__); + + switch(index) + { + case 0: + i2c_pdev = &soc_gpio_i2c0_pdev; + break; + case 1: + i2c_pdev = &soc_gpio_i2c1_pdev; + break; + default : + return -1; + } + + i2c_pdev->id = bus; + i2c_pdev->resource[0].start = base_addr; + i2c_pdev->resource[0].end = base_addr + size - 1; + i2c_pdev->resource[0].name = virt_base; + + ret = platform_device_register(i2c_pdev); + + pr_info("exit %s\n", __func__); + return ret; +} + +void soc_gpio_i2c_unregister_bus(unsigned int index) +{ + struct platform_device * i2c_pdev; + + switch(index) + { + case 0: + i2c_pdev = &soc_gpio_i2c0_pdev; + break; + case 1: + i2c_pdev = &soc_gpio_i2c1_pdev; + break; + default : + return; + } + + platform_device_unregister(i2c_pdev); + + return ; +} + diff --git a/vvcam_ry/soc/vsi_core_gen6.c b/vvcam_ry/soc/vsi_core_gen6.c new file mode 100755 index 0000000..1751971 --- /dev/null +++ b/vvcam_ry/soc/vsi_core_gen6.c @@ -0,0 +1,353 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#include +#include +#include "soc_ioctl.h" +#include "vsi_core_gen6.h" + + int gen6_write_reg(void* dev,unsigned int addr,unsigned int val) +{ + struct vvcam_soc_dev *soc_dev; + + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + writel(val,soc_dev->base + addr); + + return 0; +} + + int gen6_read_reg(void* dev,unsigned int addr,unsigned int *val) +{ + struct vvcam_soc_dev *soc_dev; + + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + *val = readl(soc_dev->base + addr); + + return 0; +} + + +static int gen6_set_isp_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_isp_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_isp_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev;; + unsigned int reg_addr; + unsigned int reg_value; + + reg_addr = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + if (id == 0) + { + reg_addr = REG_TPG0; + }else{ + reg_addr = REG_TPG1; + } + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<24); + + }else{ + reg_value |= (1<<24); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + ret |= soc_dev->soc_access.write(dev,REG_TPG0,reg_value); + + return ret; +} + +static int gen6_set_isp_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_isp_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + +static int gen6_set_dwe_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_dwe_power(void* dev, unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_dwe_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev;; + unsigned int reg_addr; + unsigned int reg_value; + + reg_addr = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + reg_addr = REG_DWE_CTRL; + + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<0); + }else{ + reg_value |= (1<<0); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + + return ret; +} + +static int gen6_set_dwe_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_dwe_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +static int gen6_set_vse_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_vse_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_vse_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev;; + unsigned int reg_addr; + unsigned int reg_value; + reg_addr = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + reg_addr = REG_VSE_CTRL; + + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<0); + }else{ + reg_value |= (1<<0); + } + + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + + return ret; +} + +static int gen6_set_vse_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_vse_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +static int gen6_set_csi_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_csi_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_csi_reset(void* dev,unsigned int id,unsigned int status) +{ + unsigned int ret = 0; + struct vvcam_soc_dev *soc_dev;; + unsigned int reg_addr; + unsigned int reg_value; + + reg_addr = 0; + soc_dev = (struct vvcam_soc_dev *)dev; + + if (soc_dev == NULL) + return -1; + + if (id == 0) + { + reg_addr = REG_TPG0; + }else{ + reg_addr = REG_TPG1; + } + + ret = soc_dev->soc_access.read(dev,reg_addr,®_value); + if (status == 0) + { + reg_value &= ~(1<<4 | 1<<28); + }else{ + reg_value |= 0x30000210; + } + ret |= soc_dev->soc_access.write(dev,reg_addr,reg_value); + + return ret; +} + +static int gen6_set_csi_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_csi_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + +static int gen6_set_sensor_power(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_get_sensor_power(void* dev,unsigned int id,unsigned int *status) +{ + return 0; +} + +static int gen6_set_sensor_reset(void* dev,unsigned int id,unsigned int status) +{ + return 0; +} + +static int gen6_set_sensor_clk(void* dev,unsigned int id,unsigned int freq) +{ + return 0; +} + +static int gen6_get_sensor_clk(void* dev,unsigned int id,unsigned int *freq) +{ + return 0; +} + + +struct vvcam_soc_function_s gen6_soc_function = { + .isp_func.set_power = gen6_set_isp_power, + .isp_func.get_power = gen6_get_isp_power, + .isp_func.set_reset = gen6_set_isp_reset, + .isp_func.set_clk = gen6_set_isp_clk, + .isp_func.get_clk = gen6_get_isp_clk, + + .dwe_func.set_power = gen6_set_dwe_power, + .dwe_func.get_power = gen6_get_dwe_power, + .dwe_func.set_reset = gen6_set_dwe_reset, + .dwe_func.set_clk = gen6_set_dwe_clk, + .dwe_func.get_clk = gen6_get_dwe_clk, + + .vse_func.set_power = gen6_set_vse_power, + .vse_func.get_power = gen6_get_vse_power, + .vse_func.set_reset = gen6_set_vse_reset, + .vse_func.set_clk = gen6_set_vse_clk, + .vse_func.get_clk = gen6_get_vse_clk, + + .csi_func.set_power = gen6_set_csi_power, + .csi_func.get_power = gen6_get_csi_power, + .csi_func.set_reset = gen6_set_csi_reset, + .csi_func.set_clk = gen6_set_csi_clk, + .csi_func.get_clk = gen6_get_csi_clk, + + .sensor_func.set_power = gen6_set_sensor_power, + .sensor_func.get_power = gen6_get_sensor_power, + .sensor_func.set_reset = gen6_set_sensor_reset, + .sensor_func.set_clk = gen6_set_sensor_clk, + .sensor_func.get_clk = gen6_get_sensor_clk, +}; + + + diff --git a/vvcam_ry/soc/vsi_core_gen6.h b/vvcam_ry/soc/vsi_core_gen6.h new file mode 100755 index 0000000..082d63d --- /dev/null +++ b/vvcam_ry/soc/vsi_core_gen6.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VSI_CORE_GEN6_H +#define _VSI_CORE_GEN6_H + + +#define REG_TPG0 0x300 +#define REG_TPG1 0x310 +#define REG_DWE_CTRL 0x250 +#define REG_VSE_CTRL 0x254 + + + + int gen6_write_reg(void* dev,unsigned int addr,unsigned int val); + int gen6_read_reg(void* dev,unsigned int addr,unsigned int *val); + +#endif diff --git a/vvcam_ry/v4l2/Kbuild b/vvcam_ry/v4l2/Kbuild new file mode 100755 index 0000000..3c10313 --- /dev/null +++ b/vvcam_ry/v4l2/Kbuild @@ -0,0 +1,94 @@ +ifeq ($(BUILD_TYPE), fpga) +INCLUDE_DIR := /usr/src/linux-headers-$(shell uname -r) +KERNEL_SRC := $(INCLUDE_DIR) +endif + +SRC := $(shell pwd) + +ANDROID := no +ifeq ($(ANDROID), yes) +PWD := $(shell pwd) +#PWD := $(ANDROID_BUILD_TOP)/vendor/nxp-opensource/verisilicon_sw_isp_vvcam/vvcam/v4l2 +endif + +EXTRA_CFLAGS += -I$(PWD)/../common/ +EXTRA_CFLAGS += -I$(PWD)/../isp/ +EXTRA_CFLAGS += -I$(PWD)/../v4l2/ + +# Enable interrupt mode for vvcam modules (yes, no) +ENABLE_IRQ := yes + +ifeq ($(ENABLE_IRQ), yes) + EXTRA_CFLAGS += -DENABLE_IRQ +endif + +ifeq ($(ANDROID), no) +EXTRA_CFLAGS += -O2 -Wall +endif + +obj-m += video/ + +include $(PWD)/../version/ISP8000L_V2008.mk + +EXTRA_CFLAGS += -DISP_REG_SIZE=0x00010000 +EXTRA_CFLAGS += -DDEC_REG_BASE=0x00600000 +EXTRA_CFLAGS += -DDEC_REG_SIZE=0x2000 +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0xB0000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x10000000 + +vvcam-isp-objs += ../isp/isp_miv1.o +vvcam-isp-objs += ../isp/isp_miv2.o +vvcam-isp-objs += ../isp/isp_wdr3.o +vvcam-isp-objs += ../isp/isp_wdr.o +vvcam-isp-objs += ../isp/isp_3dnr.o +vvcam-isp-objs += ../isp/isp_hdr.o +vvcam-isp-objs += ../isp/isp_dpf.o +vvcam-isp-objs += ../isp/isp_compand.o +vvcam-isp-objs += ../isp/isp_gcmono.o +vvcam-isp-objs += ../isp/isp_ioctl.o +vvcam-isp-objs += ../isp/isp_rgbgamma.o +vvcam-isp-objs += ../isp/isp_rgbir.o +#vvcam-isp-objs += ../isp/isp_dec.o +#vvcam-isp_objs += ../isp/isp_dmsc2.o +vvcam-isp-objs += ../isp/isp_isr.o + +# lucz: Add for ISP8000L compile error +vvcam-isp-objs += ../isp/isp_3dnr2.o +vvcam-isp-objs += ../isp/isp_dmsc2.o +vvcam-isp-objs += ../isp/isp_wdr4.o +vvcam-isp-objs += ../isp/isp_tdnr3.o +vvcam-isp-objs += ../isp/isp_irq_queue.o + +ifeq ($(ENABLE_IRQ), yes) + vvcam-isp-objs += isp_driver_of.o +else + vvcam-isp-objs += isp_driver.o +endif +vvcam-isp-objs += video/vvbuf.o +obj-m += vvcam-isp.o + +EXTRA_CFLAGS += -I$(PWD)/../dwe/ +vvcam-dwe-objs += ../dwe/dwe_ioctl.o +vvcam-dwe-objs += ../dwe/dwe_isr.o +ifeq ($(ENABLE_IRQ), yes) + vvcam-dwe-objs += dwe_driver_of.o + vvcam-dwe-objs += dwe_devcore.o +else + vvcam-dwe-objs += dwe_driver.o +endif +vvcam-dwe-objs += video/vvbuf.o +obj-m += vvcam-dwe.o + +obj-m += csi/ +obj-m += sensor/ + +V := 1 + +all: + @$(MAKE) V=$(V) -C $(KERNEL_DIR) ARCH=$(ARCH_TYPE) M=$(SRC) ENABLE_IRQ=$(ENABLE_IRQ) modules + +clean: + @rm -rf modules.order Module.symvers + @find ../ -name "*.o" | xargs rm -f + @find ../ -name "*.ko" | xargs rm -f + diff --git a/vvcam_ry/v4l2/Makefile b/vvcam_ry/v4l2/Makefile new file mode 100755 index 0000000..7047ec5 --- /dev/null +++ b/vvcam_ry/v4l2/Makefile @@ -0,0 +1,93 @@ +ifeq ($(BUILD_TYPE), fpga) +#INCLUDE_DIR := /usr/src/linux-headers-$(shell uname -r) +KERNEL_SRC := $(KERNEL) +endif + +SRC := $(shell pwd) +PWD := $(shell pwd) + +EXTRA_CFLAGS += -I$(PWD)/../common/ +EXTRA_CFLAGS += -I$(PWD)/../isp/ +EXTRA_CFLAGS += -I$(PWD)/../v4l2/ + +# Enable interrupt mode for vvcam modules (yes, no) +ENABLE_IRQ := yes + +ifeq ($(ENABLE_IRQ), yes) + EXTRA_CFLAGS += -DENABLE_IRQ +endif + +EXTRA_CFLAGS += -O2 -Wall + +obj-m += video/ + +include ../version/ISP8000L_V2008.mk + +EXTRA_CFLAGS += -DISP_REG_SIZE=0x00010000 +EXTRA_CFLAGS += -DDEC_REG_BASE=0x00600000 +EXTRA_CFLAGS += -DDEC_REG_SIZE=0x2000 +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0xB0000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x10000000 + +vvcam-isp-objs += ../isp/isp_miv1.o +vvcam-isp-objs += ../isp/isp_miv2.o +vvcam-isp-objs += ../isp/isp_wdr3.o +vvcam-isp-objs += ../isp/isp_wdr.o +vvcam-isp-objs += ../isp/isp_3dnr.o +vvcam-isp-objs += ../isp/isp_hdr.o +vvcam-isp-objs += ../isp/isp_dpf.o +vvcam-isp-objs += ../isp/isp_compand.o +vvcam-isp-objs += ../isp/isp_gcmono.o +vvcam-isp-objs += ../isp/isp_ioctl.o +vvcam-isp-objs += ../isp/isp_rgbgamma.o +vvcam-isp-objs += ../isp/isp_rgbir.o +#vvcam-isp-objs += ../isp/isp_dec.o +#vvcam-isp_objs += ../isp/isp_dmsc2.o +vvcam-isp-objs += ../isp/isp_isr.o +vvcam-isp-objs += ../isp/isp_tdnr3.o +ifeq ($(ENABLE_IRQ), yes) + vvcam-isp-objs += isp_driver_of.o +else + vvcam-isp-objs += isp_driver.o +endif +vvcam-isp-objs += video/vvbuf.o +obj-m += vvcam-isp.o + +EXTRA_CFLAGS += -I$(PWD)/../dwe/ +vvcam-dwe-objs += ../dwe/dwe_ioctl.o +vvcam-dwe-objs += ../dwe/dwe_isr.o +ifeq ($(ENABLE_IRQ), yes) + vvcam-dwe-objs += dwe_driver_of.o + vvcam-dwe-objs += dwe_devcore.o +else + vvcam-dwe-objs += dwe_driver.o +endif +vvcam-dwe-objs += video/vvbuf.o +obj-m += vvcam-dwe.o + +obj-m += csi/ +obj-m += sensor/ + +$(info PWD=$(PWD)) +$(info KERNEL_SRC=$(KERNEL_SRC)) +$(info SRC=$(SRC)) +$(info obj-m=$(obj-m)) +$(info EXTRA_CFLAGS=$(EXTRA_CFLAGS)) + +all: + make -C $(KERNEL_SRC) M=$(SRC) ENABLE_IRQ=$(ENABLE_IRQ) + +modules_install: + make -C $(KERNEL_SRC) M=$(SRC) modules_install + +clean: +# make -C $(KERNEL_SRC) M=$(SRC) clean + find . -name '*.o' -delete + find . -name '*.ko' -delete + find . -name '*.cmd' -delete + find . -name '*.mod' -delete + find . -name 'modules.order' -delete + find . -name 'Module.symvers' -delete + find . -name '*.mod.c' -delete + rm -f $(vvcam-dwe-objs) + rm -f $(vvcam-isp-objs) diff --git a/vvcam_ry/v4l2/csi/Makefile b/vvcam_ry/v4l2/csi/Makefile new file mode 100755 index 0000000..8b640e6 --- /dev/null +++ b/vvcam_ry/v4l2/csi/Makefile @@ -0,0 +1,2 @@ +#obj-m += samsung/ +obj-m += dw/ diff --git a/vvcam_ry/v4l2/csi/dw/Makefile b/vvcam_ry/v4l2/csi/dw/Makefile new file mode 100755 index 0000000..7dc836b --- /dev/null +++ b/vvcam_ry/v4l2/csi/dw/Makefile @@ -0,0 +1,4 @@ +EXTRA_CFLAGS += -I$(PWD)/../common/ +vvcam-csis-objs += mipi-csi2-dw.o + +obj-m += vvcam-csis.o diff --git a/vvcam_ry/v4l2/csi/dw/mipi-csi2-dw.c b/vvcam_ry/v4l2/csi/dw/mipi-csi2-dw.c new file mode 100755 index 0000000..207a11a --- /dev/null +++ b/vvcam_ry/v4l2/csi/dw/mipi-csi2-dw.c @@ -0,0 +1,1267 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: LuChongzhi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vvcsioc.h" +#include "mipi-csi2-dw.h" + +#define CSIS_DRIVER_NAME "mipi-csi2-dw" +#define CSIS_SUBDEV_NAME "mipi-csi2-dw-subdev" +#define CSIS_MAX_ENTITIES 2 +#define CSIS0_MAX_LANES 4 +#define CSIS1_MAX_LANES 2 + +#define MIPI_CSIS_OF_NODE_NAME "csi" + +#define MIPI_CSIS_VC0_PAD_SINK 0 +#define MIPI_CSIS_VC1_PAD_SINK 1 +#define MIPI_CSIS_VC2_PAD_SINK 2 +#define MIPI_CSIS_VC3_PAD_SINK 3 + +#define MIPI_CSIS_VC0_PAD_SOURCE 4 +#define MIPI_CSIS_VC1_PAD_SOURCE 5 +#define MIPI_CSIS_VC2_PAD_SOURCE 6 +#define MIPI_CSIS_VC3_PAD_SOURCE 7 +#define MIPI_CSIS_VCX_PADS_NUM 8 + +#define MIPI_CSIS_DEF_PIX_WIDTH 1920 +#define MIPI_CSIS_DEF_PIX_HEIGHT 1080 + +#define CSI_HW_INTERRUPT + +struct mipi_csis_event { + u32 mask; + const char *const name; + unsigned int counter; +}; + +/** + * struct csis_pix_format - CSIS pixel format description + * @pix_width_alignment: horizontal pixel alignment, width will be + * multiple of 2^pix_width_alignment + * @code: corresponding media bus code + * @fmt_reg: MIPI_CSIS_CONFIG register value + * @data_alignment: MIPI-CSI data alignment in bits + */ +struct csis_pix_format { + unsigned int pix_width_alignment; + u32 code; + u32 fmt_reg; + u8 data_alignment; +}; + +struct csis_pktbuf { + u32 *data; + unsigned int len; +}; + +struct csis_hw_reset1 { + struct regmap *src; + u8 req_src; + u8 rst_bit; +}; + +struct csi_state; +typedef int (*mipi_csis_phy_reset_t) (struct csi_state *state); + +static const struct mipi_csis_event mipi_csis_events[] = { + /* Errors */ + {MIPI_CSIS_INTSRC_ERR_SOT_HS, "SOT Error"}, + {MIPI_CSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error"}, + {MIPI_CSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error"}, + {MIPI_CSIS_INTSRC_ERR_OVER, "FIFO Overflow Error"}, + {MIPI_CSIS_INTSRC_ERR_ECC, "ECC Error"}, + {MIPI_CSIS_INTSRC_ERR_CRC, "CRC Error"}, + {MIPI_CSIS_INTSRC_ERR_UNKNOWN, "Unknown Error"}, + /* Non-image data receive events */ + {MIPI_CSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame"}, + {MIPI_CSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame"}, + {MIPI_CSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame"}, + {MIPI_CSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame"}, + /* Frame start/end */ + {MIPI_CSIS_INTSRC_FRAME_START, "Frame Start"}, + {MIPI_CSIS_INTSRC_FRAME_END, "Frame End"}, +}; + +#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) + +/** + * struct csi_state - the driver's internal state data structure + * @lock: mutex serializing the subdev and power management operations, + * protecting @format and @flags members + * @sd: v4l2_subdev associated with CSIS device instance + * @index: the hardware instance index + * @pdev: CSIS platform device + * @phy: pointer to the CSIS generic PHY + * @regs: mmaped I/O registers memory + * @supplies: CSIS regulator supplies + * @clock: CSIS clocks + * @irq: requested s5p-mipi-csis irq number + * @flags: the state variable for power and streaming control + * @clock_frequency: device bus clock frequency + * @hs_settle: HS-RX settle time + * @clk_settle: Clk settle time + * @num_lanes: number of MIPI-CSI data lanes used + * @max_num_lanes: maximum number of MIPI-CSI data lanes supported + * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM + * @csis_fmt: current CSIS pixel format + * @format: common media bus format for the source and sink pad + * @slock: spinlock protecting structure members below + * @pkt_buf: the frame embedded (non-image) data buffer + * @events: MIPI-CSIS event (error) counters + */ +struct csi_state { + struct v4l2_subdev sd; + struct mutex lock; + struct device *dev; + struct v4l2_device *v4l2_dev; + + struct media_pad pads[MIPI_CSIS_VCX_PADS_NUM]; + + u8 index; + struct platform_device *pdev; + struct phy *phy; + void __iomem *regs; + struct clk *mipi_clk; + struct clk *phy_clk; + struct clk *disp_axi; + struct clk *disp_apb; + int irq; + u32 flags; + + u32 clk_frequency; + u32 hs_settle; + u32 clk_settle; + u32 num_lanes; + u32 max_num_lanes; + u8 wclk_ext; + + u8 vchannel; + const struct csis_pix_format *csis_fmt; + struct v4l2_mbus_framefmt format; + + spinlock_t slock; + struct csis_pktbuf pkt_buf; + struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; + + struct v4l2_async_subdev asd; + struct v4l2_async_notifier subdev_notifier; + struct v4l2_async_subdev *async_subdevs[2]; + + struct csis_hw_reset1 hw_reset; + struct regulator *mipi_phy_regulator; + + struct regmap *gasket; + struct regmap *gpr; + struct regmap *mix_gpr; + struct reset_control *soft_resetn; + struct reset_control *clk_enable; + struct reset_control *mipi_reset; + + mipi_csis_phy_reset_t phy_reset_fn; + bool hdr; +}; + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug level (0-2)"); + +static const struct csis_pix_format mipi_csis_formats[] = { + { + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGBRG10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGRBG10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SRGGB10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SBGGR12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGBRG12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGRBG12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SRGGB12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_RGB888_1X24, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RGB888, + .data_alignment = 24, + }, + { + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_VYUY8_2X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SBGGR8_1X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8, + .data_alignment = 8, + } +}; + +typedef int (*mipi_csis_phy_reset_t) (struct csi_state *state); + +#define mipi_csis_write(__csis, __r, __v) writel(__v, __csis->regs + __r) +#define mipi_csis_read(__csis, __r) readl(__csis->regs + __r) + +static void dump_csis_regs(struct csi_state *state, const char *label) +{ + v4l2_dbg(2, debug, &state->sd, "--- %s ---\n", label); + // TODO: +} + +static void dump_gasket_regs(struct csi_state *state, const char *label) +{ + v4l2_dbg(2, debug, &state->sd, "--- %s ---\n", label); + // TODO: +} + +static inline struct csi_state *mipi_sd_to_csi_state(struct v4l2_subdev *sdev) +{ + pr_info("enter %s\n", __func__); + return container_of(sdev, struct csi_state, sd); +} + +static inline struct csi_state *notifier_to_mipi_dev( + struct v4l2_async_notifier *n) +{ + pr_debug("enter %s\n", __func__); + return container_of(n, struct csi_state, subdev_notifier); +} + +static struct media_pad *csis_get_remote_sensor_pad(struct csi_state *state) +{ + struct v4l2_subdev *subdev = &state->sd; + struct media_pad *sink_pad, *source_pad; + int i; + + pr_debug("enter %s\n", __func__); + + while (1) { + source_pad = NULL; + for (i = 0; i < subdev->entity.num_pads; i++) { + sink_pad = &subdev->entity.pads[i]; + + if (sink_pad->flags & MEDIA_PAD_FL_SINK) { + source_pad = media_entity_remote_pad(sink_pad); + if (source_pad) + break; + } + } + /* return first pad point in the loop */ + return source_pad; + } + + if (i == subdev->entity.num_pads) + v4l2_err(&state->sd, "%s, No remote pad found!\n", __func__); + + return NULL; +} + +static struct v4l2_subdev *csis_get_remote_subdev(struct csi_state *state, + const char *const label) +{ + struct media_pad *source_pad; + struct v4l2_subdev *sen_sd; + + pr_debug("enter %s\n", __func__); + + /* Get remote source pad */ + source_pad = csis_get_remote_sensor_pad(state); + if (!source_pad) { + v4l2_err(&state->sd, "%s, No remote pad found!\n", label); + return NULL; + } + + /* Get remote source pad subdev */ + sen_sd = media_entity_to_v4l2_subdev(source_pad->entity); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", label); + return NULL; + } + + return sen_sd; +} + +const struct csis_pix_format *find_csis_format(u32 code) +{ + int i; + pr_debug("enter %s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) + if (code == mipi_csis_formats[i].code) + return &mipi_csis_formats[i]; + return NULL; +} + +static void mipi_csis_clean_irq(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + // TODO +} + +static void mipi_csis_enable_interrupts(struct csi_state *state, bool on) +{ + pr_debug("enter %s\n", __func__); + // TODO +} + +void mipi_csis_sw_reset(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + // TODO +} + +static int mipi_csis_phy_init(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + // TODO + return 0; +} + +static void mipi_csis_phy_reset(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + // TODO +} + +static void mipi_csis_system_enable(struct csi_state *state, int on) +{ + pr_debug("enter %s\n", __func__); + // TODO +} + +/* Called with the state.lock mutex held */ +static void __mipi_csis_set_format(struct csi_state *state) +{ + struct v4l2_mbus_framefmt *mf = &state->format; + + v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n", + mf->code, mf->width, mf->height); + + // TODO +} + +static void mipi_csis_set_hsync_settle(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + // TODO +} + +void mipi_csis_set_params(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + // TODO +} + +static int mipi_csis_clk_enable(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + // TODO +} + +static void mipi_csis_clk_disable(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + // TODO +} + +static int mipi_csis_clk_get(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + // TODO + return 0; +} + +static int disp_mix_sft_rstn(struct reset_control *reset, bool enable) +{ + pr_debug("enter %s\n", __func__); + // TODO + return 0; +} + +static int disp_mix_clks_enable(struct reset_control *reset, bool enable) +{ + pr_debug("enter %s\n", __func__); + // TODO + return 0; +} + +void disp_mix_gasket_config(struct csi_state *state) +{ + /* gasket is imx's pincontrol related configuration. + Refer from: git@github.com:Avnet/linux-imx.git + drivers/pinctrl/freescale/pinctrl-imx8mp.c + */ + pr_debug("enter %s\n", __func__); +} + +static void disp_mix_gasket_enable(struct csi_state *state, bool enable) +{ + pr_debug("enter %s\n", __func__); +} + +static void mipi_csis_start_stream(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + mipi_csis_sw_reset(state); + + disp_mix_gasket_config(state); + mipi_csis_set_params(state); + + mipi_csis_system_enable(state, true); + disp_mix_gasket_enable(state, true); + mipi_csis_enable_interrupts(state, true); + + msleep(5); +} + +static void mipi_csis_stop_stream(struct csi_state *state) +{ + pr_debug("enter %s\n", __func__); + mipi_csis_enable_interrupts(state, false); + + mipi_csis_system_enable(state, false); + disp_mix_gasket_enable(state, false); +} + +static void mipi_csis_clear_counters(struct csi_state *state) +{ + unsigned long flags; + int i; + pr_debug("enter %s\n", __func__); + spin_lock_irqsave(&state->slock, flags); + for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) + state->events[i].counter = 0; + spin_unlock_irqrestore(&state->slock, flags); +} + +static void mipi_csis_log_counters(struct csi_state *state, bool non_errors) +{ + int i = non_errors ? MIPI_CSIS_NUM_EVENTS : MIPI_CSIS_NUM_EVENTS - 4; + unsigned long flags; + pr_debug("enter %s\n", __func__); + spin_lock_irqsave(&state->slock, flags); + + for (i--; i >= 0; i--) { + if (state->events[i].counter > 0 || debug) + v4l2_info(&state->sd, "%s events: %d\n", + state->events[i].name, + state->events[i].counter); + } + spin_unlock_irqrestore(&state->slock, flags); +} + +static int mipi_csi2_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + pr_debug("enter %s\n", __func__); + return 0; +} + +static const struct media_entity_operations mipi_csi2_sd_media_ops = { + .link_setup = mipi_csi2_link_setup, +}; + +/* + * V4L2 subdev operations + */ +int mipi_csis_s_power(struct v4l2_subdev *mipi_sd, int on) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + pr_debug("enter %s\n", __func__); + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, core, s_power, on); +} + +int mipi_csis_s_stream(struct v4l2_subdev *mipi_sd, int enable) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + + v4l2_dbg(1, debug, mipi_sd, "%s: %d, state: 0x%x\n", + __func__, enable, state->flags); + + if (enable) { + pm_runtime_get_sync(state->dev); + mipi_csis_clear_counters(state); + mipi_csis_start_stream(state); + dump_csis_regs(state, __func__); + dump_gasket_regs(state, __func__); + } else { + mipi_csis_stop_stream(state); + if (debug > 0) + mipi_csis_log_counters(state, true); + pm_runtime_put(state->dev); + } + + return 0; +} + +static int mipi_csis_set_fmt(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_mbus_framefmt *mf = &format->format; + struct csis_pix_format const *csis_fmt; + struct media_pad *source_pad; + struct v4l2_subdev *sen_sd; + int ret; + + /* Get remote source pad */ + source_pad = csis_get_remote_sensor_pad(state); + if (!source_pad) { + v4l2_err(&state->sd, "%s, No remote pad found!\n", __func__); + return -EINVAL; + } + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + format->pad = source_pad->index; + mf->code = MEDIA_BUS_FMT_UYVY8_2X8; + ret = v4l2_subdev_call(sen_sd, pad, set_fmt, NULL, format); + if (ret < 0) { + v4l2_err(&state->sd, "%s, set sensor format fail\n", __func__); + return -EINVAL; + } + + csis_fmt = find_csis_format(mf->code); + if (!csis_fmt) { + csis_fmt = &mipi_csis_formats[0]; + mf->code = csis_fmt->code; + } + + return 0; +} + +static int mipi_csis_get_fmt(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_mbus_framefmt *mf = &state->format; + struct media_pad *source_pad; + struct v4l2_subdev *sen_sd; + int ret; + + /* Get remote source pad */ + source_pad = csis_get_remote_sensor_pad(state); + if (!source_pad) { + v4l2_err(&state->sd, "%s, No remote pad found!\n", __func__); + return -EINVAL; + } + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + format->pad = source_pad->index; + ret = v4l2_subdev_call(sen_sd, pad, get_fmt, NULL, format); + if (ret < 0) { + v4l2_err(&state->sd, "%s, call get_fmt of subdev failed!\n", + __func__); + return ret; + } + + memcpy(mf, &format->format, sizeof(struct v4l2_mbus_framefmt)); + return 0; +} + +static int mipi_csis_s_rx_buffer(struct v4l2_subdev *mipi_sd, void *buf, + unsigned int *size) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + unsigned long flags; + + *size = min_t(unsigned int, *size, MIPI_CSIS_PKTDATA_SIZE); + + spin_lock_irqsave(&state->slock, flags); + state->pkt_buf.data = buf; + state->pkt_buf.len = *size; + spin_unlock_irqrestore(&state->slock, flags); + + return 0; +} + +static int mipi_csis_s_frame_interval(struct v4l2_subdev *mipi_sd, struct v4l2_subdev_frame_interval + *interval) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, video, s_frame_interval, interval); +} + +static int mipi_csis_g_frame_interval(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, video, g_frame_interval, interval); +} + +static int mipi_csis_enum_framesizes(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, pad, enum_frame_size, NULL, fse); +} + +static int mipi_csis_enum_frameintervals(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum + *fie) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, pad, enum_frame_interval, NULL, fie); +} + +static int mipi_csis_log_status(struct v4l2_subdev *mipi_sd) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + + mutex_lock(&state->lock); + mipi_csis_log_counters(state, true); + if (debug) { + dump_csis_regs(state, __func__); + dump_gasket_regs(state, __func__); + } + mutex_unlock(&state->lock); + return 0; +} + + +int csis_s_fmt(struct v4l2_subdev *sd, struct csi_sam_format *fmt) +{ + u32 code; + const struct csis_pix_format *csis_format; + struct csi_state *state = container_of(sd, struct csi_state, sd); + + switch (fmt->format) { + case V4L2_PIX_FMT_SBGGR10: + code = MEDIA_BUS_FMT_SBGGR10_1X10; + break; + case V4L2_PIX_FMT_SGBRG10: + code = MEDIA_BUS_FMT_SGBRG10_1X10; + break; + case V4L2_PIX_FMT_SGRBG10: + code = MEDIA_BUS_FMT_SGRBG10_1X10; + break; + case V4L2_PIX_FMT_SRGGB10: + code = MEDIA_BUS_FMT_SRGGB10_1X10; + break; + case V4L2_PIX_FMT_SBGGR12: + code = MEDIA_BUS_FMT_SBGGR12_1X12; + break; + case V4L2_PIX_FMT_SGBRG12: + code = MEDIA_BUS_FMT_SGBRG12_1X12; + break; + case V4L2_PIX_FMT_SGRBG12: + code = MEDIA_BUS_FMT_SGRBG12_1X12; + break; + case V4L2_PIX_FMT_SRGGB12: + code = MEDIA_BUS_FMT_SRGGB12_1X12; + break; + default: + return -EINVAL; + } + csis_format = find_csis_format(code); + if (csis_format == NULL) + return -EINVAL; + + state->csis_fmt = csis_format; + state->format.width = fmt->width; + state->format.height = fmt->height; + disp_mix_gasket_config(state); + mipi_csis_set_params(state); + return 0; +} + +int csis_s_hdr(struct v4l2_subdev *sd, bool enable) +{ + struct csi_state *state = container_of(sd, struct csi_state, sd); + pr_debug("enter %s: %d\n", __func__, enable); + state->hdr = enable; + return 0; +} + +int csis_ioc_qcap(struct v4l2_subdev *dev, void *args) +{ + struct csi_state *state = mipi_sd_to_csi_state(dev); + struct v4l2_capability *cap = (struct v4l2_capability *)args; + pr_info("enter %s\n", __func__); + strcpy((char *)cap->driver, "csi_dw_subdev"); + cap->bus_info[0] = state->index; + pr_info("%s: cap->driver=%s, state->index=%d\n", + __func__, (char *)cap->driver, state->index); + return 0; +} + +#ifdef __KERNEL__ +#define USER_TO_KERNEL(TYPE) \ + do {\ + TYPE tmp; \ + arg = (void *)(&tmp); \ + copy_from_user(arg, arg_user, sizeof(TYPE));\ + } while (0) + +#define KERNEL_TO_USER(TYPE) \ + copy_to_user(arg_user, arg, sizeof(TYPE)); +#else +#define USER_TO_KERNEL(TYPE) +#define KERNEL_TO_USER(TYPE) +#endif +long csis_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg_user) +{ + int ret = 1; + struct csi_state *state = container_of(sd, struct csi_state, sd); + void *arg = arg_user; + + pr_debug("enter %s\n", __func__); + switch (cmd) { + case VVCSIOC_RESET: + mipi_csis_sw_reset(state); + ret = 0; + break; + case VVCSIOC_POWERON: + ret = mipi_csis_s_power(sd, 1); + break; + case VVCSIOC_POWEROFF: + ret = mipi_csis_s_power(sd, 0); + break; + case VVCSIOC_STREAMON: + ret = mipi_csis_s_stream(sd, 1); + break; + case VVCSIOC_STREAMOFF: + ret = mipi_csis_s_stream(sd, 0); + break; + case VVCSIOC_S_FMT: { + USER_TO_KERNEL(struct csi_sam_format); + ret = csis_s_fmt(sd, (struct csi_sam_format *)arg); + break; + } + case VVCSIOC_S_HDR: { + USER_TO_KERNEL(bool); + ret = csis_s_hdr(sd, *(bool *) arg); + break; + } + case VIDIOC_QUERYCAP: + ret = csis_ioc_qcap(sd, arg); + break; + default: + pr_err("unsupported csi-sam command %d.", cmd); + break; + } + + return ret; +} + +static struct v4l2_subdev_core_ops mipi_csis_core_ops = { + .s_power = mipi_csis_s_power, + .log_status = mipi_csis_log_status, + .ioctl = csis_priv_ioctl, +}; + +static struct v4l2_subdev_video_ops mipi_csis_video_ops = { + .s_rx_buffer = mipi_csis_s_rx_buffer, + .s_stream = mipi_csis_s_stream, + + .g_frame_interval = mipi_csis_g_frame_interval, + .s_frame_interval = mipi_csis_s_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { + .enum_frame_size = mipi_csis_enum_framesizes, + .enum_frame_interval = mipi_csis_enum_frameintervals, + .get_fmt = mipi_csis_get_fmt, + .set_fmt = mipi_csis_set_fmt, +}; + +static struct v4l2_subdev_ops mipi_csis_subdev_ops = { + .core = &mipi_csis_core_ops, + .video = &mipi_csis_video_ops, + .pad = &mipi_csis_pad_ops, +}; + +static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) +{ + pr_debug("enter %s\n", __func__); + // TODO + return IRQ_HANDLED; +} + +static int mipi_csis_parse_dt(struct platform_device *pdev, + struct csi_state *state) +{ + pr_info("enter %s\n", __func__); + struct device_node *node = pdev->dev.of_node; + + state->index = of_alias_get_id(node, "csi"); // dts: csi0 = &mipi_csi_0; + pr_info("[%s:%d] state->index=%d\n", __func__, __LINE__, state->index); + state->index = 0; // dts: csi0 = &mipi_csi_0; + pr_info("[%s:%d] state->index=%d (hardcode)\n", __func__, __LINE__, state->index); + + if (of_property_read_u32 + (node, "clock-frequency", &state->clk_frequency)) + state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; + pr_info("[%s:%d] clock-frequency=%d\n", __func__, __LINE__, state->clk_frequency); + + if (of_property_read_u32(node, "bus-width", &state->max_num_lanes)) + return -EINVAL; + pr_info("[%s:%d] bus-width=%d\n", __func__, __LINE__, state->max_num_lanes); + + node = of_graph_get_next_endpoint(node, NULL); + if (!node) { + dev_err(&pdev->dev, "No port node at %s\n", node->full_name); + return -EINVAL; + } + + /* Get MIPI CSI-2 bus configration from the endpoint node. */ + of_property_read_u32(node, "csis-hs-settle", &state->hs_settle); + of_property_read_u32(node, "csis-clk-settle", &state->clk_settle); + of_property_read_u32(node, "data-lanes", &state->num_lanes); + pr_info("[%s:%d] hs_settle=%d, clk_settle=%d, num_lanes=%d\n", + __func__, __LINE__, + state->hs_settle, state->clk_settle, state->num_lanes); + + state->wclk_ext = of_property_read_bool(node, "csis-wclk"); + pr_info("[%s:%d] csis-wclk=%d\n", __func__, __LINE__, state->wclk_ext); + + of_node_put(node); + return 0; +} + +static const struct of_device_id mipi_csis_of_match[]; + +/* init subdev */ +static int mipi_csis_subdev_init(struct v4l2_subdev *mipi_sd, + struct platform_device *pdev, + const struct v4l2_subdev_ops *ops) +{ + struct csi_state *state = platform_get_drvdata(pdev); + int ret = 0; + + v4l2_subdev_init(mipi_sd, ops); + mipi_sd->owner = THIS_MODULE; + snprintf(mipi_sd->name, sizeof(mipi_sd->name), "%s.%d", + CSIS_SUBDEV_NAME, state->index); + mipi_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + mipi_sd->entity.function = MEDIA_ENT_F_IO_V4L; + mipi_sd->dev = &pdev->dev; + + state->csis_fmt = &mipi_csis_formats[0]; + state->format.code = mipi_csis_formats[0].code; + state->format.width = MIPI_CSIS_DEF_PIX_WIDTH; + state->format.height = MIPI_CSIS_DEF_PIX_HEIGHT; + + /* This allows to retrieve the platform device id by the host driver */ + v4l2_set_subdevdata(mipi_sd, state); + + state->v4l2_dev = kzalloc(sizeof(*state->v4l2_dev), GFP_KERNEL); + if (WARN_ON(!state->v4l2_dev)) { + ret = -ENOMEM; + goto end; + } + + ret = v4l2_device_register(&(pdev->dev), state->v4l2_dev); + if (WARN_ON(ret < 0)) + goto end; + + ret = v4l2_device_register_subdev(state->v4l2_dev, mipi_sd); + + if (ret) { + pr_err("failed to register csis-subdev %d\n", ret); + goto end; + } + + ret = v4l2_device_register_subdev_nodes(state->v4l2_dev); +end: + return ret; +} + +static int mipi_csis_of_parse_resets(struct csi_state *state) +{ + return 0; +} + +static int mipi_csis_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct v4l2_subdev *mipi_sd; + struct resource *mem_res; + struct csi_state *state; + const struct of_device_id *of_id; + mipi_csis_phy_reset_t phy_reset_fn; + int ret = -ENOMEM; + pr_info("enter %s\n", __func__); + + state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); + if (!state) + return -ENOMEM; + pr_info("[%s:%d]\n", __func__, __LINE__); + + mutex_init(&state->lock); + spin_lock_init(&state->slock); + + /* WA on VSI platform, need insmod dynamically for debug */ + pdev->dev.of_node = + of_find_compatible_node(NULL, NULL, "thead,light-mipi-csi"); + + state->pdev = pdev; + mipi_sd = &state->sd; + state->dev = dev; + + ret = mipi_csis_parse_dt(pdev, state); + if (ret < 0) + return ret; + pr_info("[%s:%d]\n", __func__, __LINE__); + + /* Hardcode here */ + state->num_lanes = 4; + state->hs_settle = 0x10; + + if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) { + dev_err(dev, "Unsupported number of data lanes: %d (max. %d)\n", + state->num_lanes, state->max_num_lanes); + return -EINVAL; + } + pr_info("[%s:%d]\n", __func__, __LINE__); + + ret = mipi_csis_phy_init(state); + if (ret < 0) + return ret; + + of_id = of_match_node(mipi_csis_of_match, dev->of_node); + if (!of_id || !of_id->data) { + dev_err(dev, "No match data for %s\n", dev_name(dev)); + return -EINVAL; + } + phy_reset_fn = of_id->data; // = mipi_csis_of_match.data = mipi_csis_phy_reset + state->phy_reset_fn = phy_reset_fn; + + ret = of_clk_set_defaults(dev->of_node, false); + if (ret < 0) { + pr_err("clk: couldn't set desired clock for CSI\n"); + return ret; + } + pr_info("[%s:%d]\n", __func__, __LINE__); + + ret = mipi_csis_of_parse_resets(state); + if (ret < 0) { + dev_err(dev, "Can not parse reset control\n"); + return ret; + } + pr_info("[%s:%d]\n", __func__, __LINE__); + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + state->regs = devm_ioremap_resource(dev, mem_res); + //state->regs = ioremap(0x32e40000, 0x00001000); + if (IS_ERR(state->regs)) + return PTR_ERR(state->regs); + pr_info("[%s:%d]\n", __func__, __LINE__); + + state->irq = platform_get_irq(pdev, 0); + if (state->irq < 0) { + dev_err(dev, "Failed to get irq\n"); + return state->irq; + } + pr_info("[%s:%d]\n", __func__, __LINE__); + + ret = mipi_csis_clk_get(state); + if (ret < 0) + return ret; + pr_info("[%s:%d]\n", __func__, __LINE__); + + ret = mipi_csis_clk_enable(state); + if (ret < 0) + return ret; + pr_info("[%s:%d]\n", __func__, __LINE__); + + disp_mix_clks_enable(state->clk_enable, true); + disp_mix_sft_rstn(state->soft_resetn, false); + phy_reset_fn(state); + + /* mipi_csis_clk_disable(state); */ + + ret = devm_request_irq(dev, state->irq, mipi_csis_irq_handler, 0, + dev_name(dev), state); + if (ret) { + dev_err(dev, "Interrupt request failed\n"); + return ret; + } + pr_info("[%s:%d]\n", __func__, __LINE__); + + platform_set_drvdata(pdev, state); + ret = mipi_csis_subdev_init(&state->sd, pdev, &mipi_csis_subdev_ops); + if (ret < 0) { + dev_err(dev, "mipi csi subdev init failed\n"); + return ret; + } + pr_info("[%s:%d]\n", __func__, __LINE__); + + state->pads[MIPI_CSIS_VC0_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC1_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC2_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC3_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC0_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + state->pads[MIPI_CSIS_VC1_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + state->pads[MIPI_CSIS_VC2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + state->pads[MIPI_CSIS_VC3_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + ret = + media_entity_pads_init(&state->sd.entity, MIPI_CSIS_VCX_PADS_NUM, + state->pads); + if (ret < 0) { + dev_err(dev, "mipi csi entity pad init failed\n"); + return ret; + } + pr_info("[%s:%d]\n", __func__, __LINE__); + + memcpy(state->events, mipi_csis_events, sizeof(state->events)); + state->sd.entity.ops = &mipi_csi2_sd_media_ops; + + pm_runtime_enable(dev); + /* mipi_csis_s_stream(&state->sd, 1); */ + + dev_info(&pdev->dev, + "lanes: %d, hs_settle: %d, clk_settle: %d, wclk: %d, freq: %u\n", + state->num_lanes, state->hs_settle, state->clk_settle, + state->wclk_ext, state->clk_frequency); + pr_info("[%s:%d]\n", __func__, __LINE__); + return 0; +} + +static int mipi_csis_system_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev);; +} + +static int mipi_csis_system_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + + return 0; +} + +static int mipi_csis_runtime_suspend(struct device *dev) +{ + struct csi_state *state = dev_get_drvdata(dev); + int ret; + + ret = regulator_disable(state->mipi_phy_regulator); + if (ret < 0) + return ret; + + disp_mix_clks_enable(state->clk_enable, false); + mipi_csis_clk_disable(state); + return 0; +} + +static int mipi_csis_runtime_resume(struct device *dev) +{ + struct csi_state *state = dev_get_drvdata(dev); + int ret; + + ret = regulator_enable(state->mipi_phy_regulator); + if (ret < 0) + return ret; + + ret = mipi_csis_clk_enable(state); + if (ret < 0) + return ret; + + disp_mix_clks_enable(state->clk_enable, true); + disp_mix_sft_rstn(state->soft_resetn, false); + + if (state->phy_reset_fn) + state->phy_reset_fn(state); + + return 0; +} + +static int mipi_csis_remove(struct platform_device *pdev) +{ + struct csi_state *state = platform_get_drvdata(pdev); + + media_entity_cleanup(&state->sd.entity); + + v4l2_device_unregister_subdev(&state->sd); + v4l2_device_disconnect(state->v4l2_dev); + v4l2_device_put(state->v4l2_dev); + + return 0; +} + +static const struct dev_pm_ops mipi_csis_pm_ops = { + SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, + NULL) + SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_system_suspend, + mipi_csis_system_resume) +}; + +static const struct of_device_id mipi_csis_of_match[] = { + {.compatible = "thead,light-mipi-csi", + .data = (void *)&mipi_csis_phy_reset, + }, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, mipi_csis_of_match); + +static struct platform_driver mipi_csis_driver = { + .driver = { + .name = CSIS_DRIVER_NAME, + .owner = THIS_MODULE, + .pm = &mipi_csis_pm_ops, + .of_match_table = mipi_csis_of_match, + }, + .probe = mipi_csis_probe, + .remove = mipi_csis_remove, +}; + +static int __init csi_init_module(void) +{ + int ret = 0; + pr_debug("enter %s\n", __func__); + + ret = platform_driver_register(&mipi_csis_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + return ret; +} + +static void __exit csi_exit_module(void) +{ + pr_debug("enter %s\n", __func__); + platform_driver_unregister(&mipi_csis_driver); +} + +module_init(csi_init_module); +module_exit(csi_exit_module); + +MODULE_DESCRIPTION("T-Head MIPI-CSI2 receiver driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("CSI Capture"); +MODULE_VERSION("1.0"); diff --git a/vvcam_ry/v4l2/csi/dw/mipi-csi2-dw.h b/vvcam_ry/v4l2/csi/dw/mipi-csi2-dw.h new file mode 100755 index 0000000..e0abba4 --- /dev/null +++ b/vvcam_ry/v4l2/csi/dw/mipi-csi2-dw.h @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited + * Author: LuChongzhi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Register map definition */ + +/* CSIS version */ +#define MIPI_CSIS_VERSION 0x00 + +/* CSIS common control */ +#define MIPI_CSIS_CMN_CTRL 0x04 +#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW (1 << 16) +#define MIPI_CSIS_CMN_CTRL_HDR_MODE (1 << 11) +#define MIPI_CSIS_CMN_CTRL_INTER_MODE (1 << 10) +#define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8 +#define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) +#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL (1 << 2) +#define MIPI_CSIS_CMN_CTRL_RESET (1 << 1) +#define MIPI_CSIS_CMN_CTRL_ENABLE (1 << 0) + +/* CSIS clock control */ +#define MIPI_CSIS_CLK_CTRL 0x08 +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) (x << 28) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) (x << 24) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) (x << 20) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) (x << 16) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) +#define MIPI_CSIS_CLK_CTRL_WCLK_SRC (1 << 0) + +/* CSIS Interrupt mask */ +#define MIPI_CSIS_INTMSK 0x10 +#define MIPI_CSIS_INTMSK_EVEN_BEFORE (1 << 31) +#define MIPI_CSIS_INTMSK_EVEN_AFTER (1 << 30) +#define MIPI_CSIS_INTMSK_ODD_BEFORE (1 << 29) +#define MIPI_CSIS_INTMSK_ODD_AFTER (1 << 28) +#define MIPI_CSIS_INTMSK_FRAME_START (1 << 24) +#define MIPI_CSIS_INTMSK_FRAME_END (1 << 20) +#define MIPI_CSIS_INTMSK_ERR_SOT_HS (1 << 16) +#define MIPI_CSIS_INTMSK_ERR_LOST_FS (1 << 12) +#define MIPI_CSIS_INTMSK_ERR_LOST_FE (1 << 8) +#define MIPI_CSIS_INTMSK_ERR_OVER (1 << 4) +#define MIPI_CSIS_INTMSK_ERR_WRONG_CFG (1 << 3) +#define MIPI_CSIS_INTMSK_ERR_ECC (1 << 2) +#define MIPI_CSIS_INTMSK_ERR_CRC (1 << 1) +#define MIPI_CSIS_INTMSK_ERR_UNKNOWN (1 << 0) + +/* CSIS Interrupt source */ +#define MIPI_CSIS_INTSRC 0x14 +#define MIPI_CSIS_INTSRC_EVEN_BEFORE (1 << 31) +#define MIPI_CSIS_INTSRC_EVEN_AFTER (1 << 30) +#define MIPI_CSIS_INTSRC_EVEN (0x3 << 30) +#define MIPI_CSIS_INTSRC_ODD_BEFORE (1 << 29) +#define MIPI_CSIS_INTSRC_ODD_AFTER (1 << 28) +#define MIPI_CSIS_INTSRC_ODD (0x3 << 28) +#define MIPI_CSIS_INTSRC_NON_IMAGE_DATA (0xf << 28) +#define MIPI_CSIS_INTSRC_FRAME_START (1 << 24) +#define MIPI_CSIS_INTSRC_FRAME_END (1 << 20) +#define MIPI_CSIS_INTSRC_ERR_SOT_HS (1 << 16) +#define MIPI_CSIS_INTSRC_ERR_LOST_FS (1 << 12) +#define MIPI_CSIS_INTSRC_ERR_LOST_FE (1 << 8) +#define MIPI_CSIS_INTSRC_ERR_OVER (1 << 4) +#define MIPI_CSIS_INTSRC_ERR_WRONG_CFG (1 << 3) +#define MIPI_CSIS_INTSRC_ERR_ECC (1 << 2) +#define MIPI_CSIS_INTSRC_ERR_CRC (1 << 1) +#define MIPI_CSIS_INTSRC_ERR_UNKNOWN (1 << 0) +#define MIPI_CSIS_INTSRC_ERRORS 0xfffff + +/* D-PHY status control */ +#define MIPI_CSIS_DPHYSTATUS 0x20 +#define MIPI_CSIS_DPHYSTATUS_ULPS_DAT (1 << 8) +#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT (1 << 4) +#define MIPI_CSIS_DPHYSTATUS_ULPS_CLK (1 << 1) +#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK (1 << 0) + +/* D-PHY common control */ +#define MIPI_CSIS_DPHYCTRL 0x24 +#define MIPI_CSIS_DPHYCTRL_HSS_MASK (0xff << 24) +#define MIPI_CSIS_DPHYCTRL_HSS_OFFSET 24 +#define MIPI_CSIS_DPHYCTRL_SCLKS_MASK (0x3 << 22) +#define MIPI_CSIS_DPHYCTRL_SCLKS_OFFSET 22 +#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK (1 << 6) +#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT (1 << 5) +#define MIPI_CSIS_DPHYCTRL_ENABLE_DAT (1 << 1) +#define MIPI_CSIS_DPHYCTRL_ENABLE_CLK (1 << 0) +#define MIPI_CSIS_DPHYCTRL_ENABLE (0x1f << 0) + +/* D-PHY Master and Slave Control register Low */ +#define MIPI_CSIS_DPHYBCTRL_L 0x30 +/* D-PHY Master and Slave Control register High */ +#define MIPI_CSIS_DPHYBCTRL_H 0x34 +/* D-PHY Slave Control register Low */ +#define MIPI_CSIS_DPHYSCTRL_L 0x38 +/* D-PHY Slave Control register High */ +#define MIPI_CSIS_DPHYSCTRL_H 0x3c + +/* ISP Configuration register */ +#define MIPI_CSIS_ISPCONFIG_CH0 0x40 +#define MIPI_CSIS_ISPCONFIG_CH0_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH0_PIXEL_MODE_SHIFT 12 + +#define MIPI_CSIS_ISPCONFIG_CH1 0x50 +#define MIPI_CSIS_ISPCONFIG_CH1_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH1_PIXEL_MODE_SHIFT 12 + +#define MIPI_CSIS_ISPCONFIG_CH2 0x60 +#define MIPI_CSIS_ISPCONFIG_CH2_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH2_PIXEL_MODE_SHIFT 12 + +#define MIPI_CSIS_ISPCONFIG_CH3 0x70 +#define MIPI_CSIS_ISPCONFIG_CH3_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH3_PIXEL_MODE_SHIFT 12 + +#define PIXEL_MODE_SINGLE_PIXEL_MODE 0x0 +#define PIXEL_MODE_DUAL_PIXEL_MODE 0x1 +#define PIXEL_MODE_QUAD_PIXEL_MODE 0x2 +#define PIXEL_MODE_INVALID_PIXEL_MODE 0x3 + +#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) +#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) (x << 24) +#define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT (1 << 12) +#define MIPI_CSIS_ISPCFG_ALIGN_32BIT (1 << 11) +#define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT (0x1e << 2) +#define MIPI_CSIS_ISPCFG_FMT_RAW8 (0x2a << 2) +#define MIPI_CSIS_ISPCFG_FMT_RAW10 (0x2b << 2) +#define MIPI_CSIS_ISPCFG_FMT_RAW12 (0x2c << 2) +#define MIPI_CSIS_ISPCFG_FMT_RGB888 (0x24 << 2) +#define MIPI_CSIS_ISPCFG_FMT_RGB565 (0x22 << 2) +/* User defined formats, x = 1...4 */ +#define MIPI_CSIS_ISPCFG_FMT_USER(x) ((0x30 + x - 1) << 2) +#define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) + +/* ISP Image Resolution register */ +#define MIPI_CSIS_ISPRESOL_CH0 0x44 +#define MIPI_CSIS_ISPRESOL_CH1 0x54 +#define MIPI_CSIS_ISPRESOL_CH2 0x64 +#define MIPI_CSIS_ISPRESOL_CH3 0x74 +#define CSIS_MAX_PIX_WIDTH 0xffff +#define CSIS_MAX_PIX_HEIGHT 0xffff + +/* ISP SYNC register */ +#define MIPI_CSIS_ISPSYNC_CH0 0x48 +#define MIPI_CSIS_ISPSYNC_CH1 0x58 +#define MIPI_CSIS_ISPSYNC_CH2 0x68 +#define MIPI_CSIS_ISPSYNC_CH3 0x78 + +#define MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET 18 +#define MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET 12 +#define MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET 0 + +#define MIPI_CSIS_FRAME_COUNTER_CH0 0x0100 +#define MIPI_CSIS_FRAME_COUNTER_CH1 0x0104 +#define MIPI_CSIS_FRAME_COUNTER_CH2 0x0108 +#define MIPI_CSIS_FRAME_COUNTER_CH3 0x010C + +/* Non-image packet data buffers */ +#define MIPI_CSIS_PKTDATA_ODD 0x2000 +#define MIPI_CSIS_PKTDATA_EVEN 0x3000 +#define MIPI_CSIS_PKTDATA_SIZE SZ_4K + +#define DEFAULT_SCLK_CSIS_FREQ 166000000UL + +/* display_mix_clk_en_csr */ +#define DISP_MIX_GASKET_0_CTRL 0x00 +#define GASKET_0_CTRL_DATA_TYPE(x) (((x) & (0x3F)) << 8) +#define GASKET_0_CTRL_DATA_TYPE_MASK ((0x3FUL) << (8)) + +#define GASKET_0_CTRL_DATA_TYPE_YUV420_8 0x18 +#define GASKET_0_CTRL_DATA_TYPE_YUV420_10 0x19 +#define GASKET_0_CTRL_DATA_TYPE_LE_YUV420_8 0x1a +#define GASKET_0_CTRL_DATA_TYPE_CS_YUV420_8 0x1c +#define GASKET_0_CTRL_DATA_TYPE_CS_YUV420_10 0x1d +#define GASKET_0_CTRL_DATA_TYPE_YUV422_8 0x1e +#define GASKET_0_CTRL_DATA_TYPE_YUV422_10 0x1f +#define GASKET_0_CTRL_DATA_TYPE_RGB565 0x22 +#define GASKET_0_CTRL_DATA_TYPE_RGB666 0x23 +#define GASKET_0_CTRL_DATA_TYPE_RGB888 0x24 +#define GASKET_0_CTRL_DATA_TYPE_RAW6 0x28 +#define GASKET_0_CTRL_DATA_TYPE_RAW7 0x29 +#define GASKET_0_CTRL_DATA_TYPE_RAW8 0x2a +#define GASKET_0_CTRL_DATA_TYPE_RAW10 0x2b +#define GASKET_0_CTRL_DATA_TYPE_RAW12 0x2c +#define GASKET_0_CTRL_DATA_TYPE_RAW14 0x2d + +#define GASKET_0_CTRL_DUAL_COMP_ENABLE BIT(1) +#define GASKET_0_CTRL_ENABLE BIT(0) + +#define DISP_MIX_GASKET_0_HSIZE 0x04 +#define DISP_MIX_GASKET_0_VSIZE 0x08 diff --git a/vvcam_ry/v4l2/csi/samsung/Makefile b/vvcam_ry/v4l2/csi/samsung/Makefile new file mode 100755 index 0000000..a5d37ee --- /dev/null +++ b/vvcam_ry/v4l2/csi/samsung/Makefile @@ -0,0 +1,4 @@ +EXTRA_CFLAGS += -I$(PWD)/../common/ +vvcam-csis-objs += mxc-mipi-csi2-sam.o + +obj-m += vvcam-csis.o diff --git a/vvcam_ry/v4l2/csi/samsung/mxc-mipi-csi2-sam.c b/vvcam_ry/v4l2/csi/samsung/mxc-mipi-csi2-sam.c new file mode 100755 index 0000000..743bfe0 --- /dev/null +++ b/vvcam_ry/v4l2/csi/samsung/mxc-mipi-csi2-sam.c @@ -0,0 +1,1837 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * Copyright 2019 NXP + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Based on Samsung S5P/EXYNOS SoC series MIPI-CSI receiver driver + * + * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd. + * Author: Sylwester Nawrocki + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vvcsioc.h" + +#include + +#define CSIS_DRIVER_NAME "mxc-mipi-csi2-sam" +#define CSIS_SUBDEV_NAME "mxc-mipi-csi2" +#define CSIS_MAX_ENTITIES 2 +#define CSIS0_MAX_LANES 4 +#define CSIS1_MAX_LANES 2 + +#define MIPI_CSIS_OF_NODE_NAME "csi" + +#define MIPI_CSIS_VC0_PAD_SINK 0 +#define MIPI_CSIS_VC1_PAD_SINK 1 +#define MIPI_CSIS_VC2_PAD_SINK 2 +#define MIPI_CSIS_VC3_PAD_SINK 3 + +#define MIPI_CSIS_VC0_PAD_SOURCE 4 +#define MIPI_CSIS_VC1_PAD_SOURCE 5 +#define MIPI_CSIS_VC2_PAD_SOURCE 6 +#define MIPI_CSIS_VC3_PAD_SOURCE 7 +#define MIPI_CSIS_VCX_PADS_NUM 8 + +#define MIPI_CSIS_DEF_PIX_WIDTH 1920 +#define MIPI_CSIS_DEF_PIX_HEIGHT 1080 + +/* Register map definition */ + +/* CSIS version */ +#define MIPI_CSIS_VERSION 0x00 + +/* CSIS common control */ +#define MIPI_CSIS_CMN_CTRL 0x04 +#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW (1 << 16) +#define MIPI_CSIS_CMN_CTRL_HDR_MODE (1 << 11) +#define MIPI_CSIS_CMN_CTRL_INTER_MODE (1 << 10) +#define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8 +#define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) +#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL (1 << 2) +#define MIPI_CSIS_CMN_CTRL_RESET (1 << 1) +#define MIPI_CSIS_CMN_CTRL_ENABLE (1 << 0) + +/* CSIS clock control */ +#define MIPI_CSIS_CLK_CTRL 0x08 +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) (x << 28) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) (x << 24) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) (x << 20) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) (x << 16) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) +#define MIPI_CSIS_CLK_CTRL_WCLK_SRC (1 << 0) + +/* CSIS Interrupt mask */ +#define MIPI_CSIS_INTMSK 0x10 +#define MIPI_CSIS_INTMSK_EVEN_BEFORE (1 << 31) +#define MIPI_CSIS_INTMSK_EVEN_AFTER (1 << 30) +#define MIPI_CSIS_INTMSK_ODD_BEFORE (1 << 29) +#define MIPI_CSIS_INTMSK_ODD_AFTER (1 << 28) +#define MIPI_CSIS_INTMSK_FRAME_START (1 << 24) +#define MIPI_CSIS_INTMSK_FRAME_END (1 << 20) +#define MIPI_CSIS_INTMSK_ERR_SOT_HS (1 << 16) +#define MIPI_CSIS_INTMSK_ERR_LOST_FS (1 << 12) +#define MIPI_CSIS_INTMSK_ERR_LOST_FE (1 << 8) +#define MIPI_CSIS_INTMSK_ERR_OVER (1 << 4) +#define MIPI_CSIS_INTMSK_ERR_WRONG_CFG (1 << 3) +#define MIPI_CSIS_INTMSK_ERR_ECC (1 << 2) +#define MIPI_CSIS_INTMSK_ERR_CRC (1 << 1) +#define MIPI_CSIS_INTMSK_ERR_UNKNOWN (1 << 0) + +/* CSIS Interrupt source */ +#define MIPI_CSIS_INTSRC 0x14 +#define MIPI_CSIS_INTSRC_EVEN_BEFORE (1 << 31) +#define MIPI_CSIS_INTSRC_EVEN_AFTER (1 << 30) +#define MIPI_CSIS_INTSRC_EVEN (0x3 << 30) +#define MIPI_CSIS_INTSRC_ODD_BEFORE (1 << 29) +#define MIPI_CSIS_INTSRC_ODD_AFTER (1 << 28) +#define MIPI_CSIS_INTSRC_ODD (0x3 << 28) +#define MIPI_CSIS_INTSRC_NON_IMAGE_DATA (0xf << 28) +#define MIPI_CSIS_INTSRC_FRAME_START (1 << 24) +#define MIPI_CSIS_INTSRC_FRAME_END (1 << 20) +#define MIPI_CSIS_INTSRC_ERR_SOT_HS (1 << 16) +#define MIPI_CSIS_INTSRC_ERR_LOST_FS (1 << 12) +#define MIPI_CSIS_INTSRC_ERR_LOST_FE (1 << 8) +#define MIPI_CSIS_INTSRC_ERR_OVER (1 << 4) +#define MIPI_CSIS_INTSRC_ERR_WRONG_CFG (1 << 3) +#define MIPI_CSIS_INTSRC_ERR_ECC (1 << 2) +#define MIPI_CSIS_INTSRC_ERR_CRC (1 << 1) +#define MIPI_CSIS_INTSRC_ERR_UNKNOWN (1 << 0) +#define MIPI_CSIS_INTSRC_ERRORS 0xfffff + +/* D-PHY status control */ +#define MIPI_CSIS_DPHYSTATUS 0x20 +#define MIPI_CSIS_DPHYSTATUS_ULPS_DAT (1 << 8) +#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT (1 << 4) +#define MIPI_CSIS_DPHYSTATUS_ULPS_CLK (1 << 1) +#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK (1 << 0) + +/* D-PHY common control */ +#define MIPI_CSIS_DPHYCTRL 0x24 +#define MIPI_CSIS_DPHYCTRL_HSS_MASK (0xff << 24) +#define MIPI_CSIS_DPHYCTRL_HSS_OFFSET 24 +#define MIPI_CSIS_DPHYCTRL_SCLKS_MASK (0x3 << 22) +#define MIPI_CSIS_DPHYCTRL_SCLKS_OFFSET 22 +#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK (1 << 6) +#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT (1 << 5) +#define MIPI_CSIS_DPHYCTRL_ENABLE_DAT (1 << 1) +#define MIPI_CSIS_DPHYCTRL_ENABLE_CLK (1 << 0) +#define MIPI_CSIS_DPHYCTRL_ENABLE (0x1f << 0) + +/* D-PHY Master and Slave Control register Low */ +#define MIPI_CSIS_DPHYBCTRL_L 0x30 +/* D-PHY Master and Slave Control register High */ +#define MIPI_CSIS_DPHYBCTRL_H 0x34 +/* D-PHY Slave Control register Low */ +#define MIPI_CSIS_DPHYSCTRL_L 0x38 +/* D-PHY Slave Control register High */ +#define MIPI_CSIS_DPHYSCTRL_H 0x3c + +/* ISP Configuration register */ +#define MIPI_CSIS_ISPCONFIG_CH0 0x40 +#define MIPI_CSIS_ISPCONFIG_CH0_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH0_PIXEL_MODE_SHIFT 12 + +#define MIPI_CSIS_ISPCONFIG_CH1 0x50 +#define MIPI_CSIS_ISPCONFIG_CH1_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH1_PIXEL_MODE_SHIFT 12 + +#define MIPI_CSIS_ISPCONFIG_CH2 0x60 +#define MIPI_CSIS_ISPCONFIG_CH2_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH2_PIXEL_MODE_SHIFT 12 + +#define MIPI_CSIS_ISPCONFIG_CH3 0x70 +#define MIPI_CSIS_ISPCONFIG_CH3_PIXEL_MODE_MASK (0x3 << 12) +#define MIPI_CSIS_ISPCONFIG_CH3_PIXEL_MODE_SHIFT 12 + +#define PIXEL_MODE_SINGLE_PIXEL_MODE 0x0 +#define PIXEL_MODE_DUAL_PIXEL_MODE 0x1 +#define PIXEL_MODE_QUAD_PIXEL_MODE 0x2 +#define PIXEL_MODE_INVALID_PIXEL_MODE 0x3 + +#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) +#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) (x << 24) +#define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT (1 << 12) +#define MIPI_CSIS_ISPCFG_ALIGN_32BIT (1 << 11) +#define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT (0x1e << 2) +#define MIPI_CSIS_ISPCFG_FMT_RAW8 (0x2a << 2) +#define MIPI_CSIS_ISPCFG_FMT_RAW10 (0x2b << 2) +#define MIPI_CSIS_ISPCFG_FMT_RAW12 (0x2c << 2) +#define MIPI_CSIS_ISPCFG_FMT_RGB888 (0x24 << 2) +#define MIPI_CSIS_ISPCFG_FMT_RGB565 (0x22 << 2) +/* User defined formats, x = 1...4 */ +#define MIPI_CSIS_ISPCFG_FMT_USER(x) ((0x30 + x - 1) << 2) +#define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) + +/* ISP Image Resolution register */ +#define MIPI_CSIS_ISPRESOL_CH0 0x44 +#define MIPI_CSIS_ISPRESOL_CH1 0x54 +#define MIPI_CSIS_ISPRESOL_CH2 0x64 +#define MIPI_CSIS_ISPRESOL_CH3 0x74 +#define CSIS_MAX_PIX_WIDTH 0xffff +#define CSIS_MAX_PIX_HEIGHT 0xffff + +/* ISP SYNC register */ +#define MIPI_CSIS_ISPSYNC_CH0 0x48 +#define MIPI_CSIS_ISPSYNC_CH1 0x58 +#define MIPI_CSIS_ISPSYNC_CH2 0x68 +#define MIPI_CSIS_ISPSYNC_CH3 0x78 + +#define MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET 18 +#define MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET 12 +#define MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET 0 + +#define MIPI_CSIS_FRAME_COUNTER_CH0 0x0100 +#define MIPI_CSIS_FRAME_COUNTER_CH1 0x0104 +#define MIPI_CSIS_FRAME_COUNTER_CH2 0x0108 +#define MIPI_CSIS_FRAME_COUNTER_CH3 0x010C + +/* Non-image packet data buffers */ +#define MIPI_CSIS_PKTDATA_ODD 0x2000 +#define MIPI_CSIS_PKTDATA_EVEN 0x3000 +#define MIPI_CSIS_PKTDATA_SIZE SZ_4K + +#define DEFAULT_SCLK_CSIS_FREQ 166000000UL + +/* display_mix_clk_en_csr */ +#define DISP_MIX_GASKET_0_CTRL 0x00 +#define GASKET_0_CTRL_DATA_TYPE(x) (((x) & (0x3F)) << 8) +#define GASKET_0_CTRL_DATA_TYPE_MASK ((0x3FUL) << (8)) + +#define GASKET_0_CTRL_DATA_TYPE_YUV420_8 0x18 +#define GASKET_0_CTRL_DATA_TYPE_YUV420_10 0x19 +#define GASKET_0_CTRL_DATA_TYPE_LE_YUV420_8 0x1a +#define GASKET_0_CTRL_DATA_TYPE_CS_YUV420_8 0x1c +#define GASKET_0_CTRL_DATA_TYPE_CS_YUV420_10 0x1d +#define GASKET_0_CTRL_DATA_TYPE_YUV422_8 0x1e +#define GASKET_0_CTRL_DATA_TYPE_YUV422_10 0x1f +#define GASKET_0_CTRL_DATA_TYPE_RGB565 0x22 +#define GASKET_0_CTRL_DATA_TYPE_RGB666 0x23 +#define GASKET_0_CTRL_DATA_TYPE_RGB888 0x24 +#define GASKET_0_CTRL_DATA_TYPE_RAW6 0x28 +#define GASKET_0_CTRL_DATA_TYPE_RAW7 0x29 +#define GASKET_0_CTRL_DATA_TYPE_RAW8 0x2a +#define GASKET_0_CTRL_DATA_TYPE_RAW10 0x2b +#define GASKET_0_CTRL_DATA_TYPE_RAW12 0x2c +#define GASKET_0_CTRL_DATA_TYPE_RAW14 0x2d + +#define GASKET_0_CTRL_DUAL_COMP_ENABLE BIT(1) +#define GASKET_0_CTRL_ENABLE BIT(0) + +#define DISP_MIX_GASKET_0_HSIZE 0x04 +#define DISP_MIX_GASKET_0_VSIZE 0x08 + +struct mipi_csis_event { + u32 mask; + const char *const name; + unsigned int counter; +}; + +/** + * struct csis_pix_format - CSIS pixel format description + * @pix_width_alignment: horizontal pixel alignment, width will be + * multiple of 2^pix_width_alignment + * @code: corresponding media bus code + * @fmt_reg: MIPI_CSIS_CONFIG register value + * @data_alignment: MIPI-CSI data alignment in bits + */ +struct csis_pix_format { + unsigned int pix_width_alignment; + u32 code; + u32 fmt_reg; + u8 data_alignment; +}; + +struct csis_pktbuf { + u32 *data; + unsigned int len; +}; + +struct csis_hw_reset1 { + struct regmap *src; + u8 req_src; + u8 rst_bit; +}; + +struct csi_state; +typedef int (*mipi_csis_phy_reset_t) (struct csi_state *state); + +static const struct mipi_csis_event mipi_csis_events[] = { + /* Errors */ + {MIPI_CSIS_INTSRC_ERR_SOT_HS, "SOT Error"}, + {MIPI_CSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error"}, + {MIPI_CSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error"}, + {MIPI_CSIS_INTSRC_ERR_OVER, "FIFO Overflow Error"}, + {MIPI_CSIS_INTSRC_ERR_ECC, "ECC Error"}, + {MIPI_CSIS_INTSRC_ERR_CRC, "CRC Error"}, + {MIPI_CSIS_INTSRC_ERR_UNKNOWN, "Unknown Error"}, + /* Non-image data receive events */ + {MIPI_CSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame"}, + {MIPI_CSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame"}, + {MIPI_CSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame"}, + {MIPI_CSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame"}, + /* Frame start/end */ + {MIPI_CSIS_INTSRC_FRAME_START, "Frame Start"}, + {MIPI_CSIS_INTSRC_FRAME_END, "Frame End"}, +}; + +#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) + +/** + * struct csi_state - the driver's internal state data structure + * @lock: mutex serializing the subdev and power management operations, + * protecting @format and @flags members + * @sd: v4l2_subdev associated with CSIS device instance + * @index: the hardware instance index + * @pdev: CSIS platform device + * @phy: pointer to the CSIS generic PHY + * @regs: mmaped I/O registers memory + * @supplies: CSIS regulator supplies + * @clock: CSIS clocks + * @irq: requested s5p-mipi-csis irq number + * @flags: the state variable for power and streaming control + * @clock_frequency: device bus clock frequency + * @hs_settle: HS-RX settle time + * @clk_settle: Clk settle time + * @num_lanes: number of MIPI-CSI data lanes used + * @max_num_lanes: maximum number of MIPI-CSI data lanes supported + * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM + * @csis_fmt: current CSIS pixel format + * @format: common media bus format for the source and sink pad + * @slock: spinlock protecting structure members below + * @pkt_buf: the frame embedded (non-image) data buffer + * @events: MIPI-CSIS event (error) counters + */ +struct csi_state { + struct v4l2_subdev sd; + struct mutex lock; + struct device *dev; + struct v4l2_device *v4l2_dev; + + struct media_pad pads[MIPI_CSIS_VCX_PADS_NUM]; + + u8 index; + struct platform_device *pdev; + struct phy *phy; + void __iomem *regs; + struct clk *mipi_clk; + struct clk *phy_clk; + struct clk *disp_axi; + struct clk *disp_apb; + int irq; + u32 flags; + + u32 clk_frequency; + u32 hs_settle; + u32 clk_settle; + u32 num_lanes; + u32 max_num_lanes; + u8 wclk_ext; + + u8 vchannel; + const struct csis_pix_format *csis_fmt; + struct v4l2_mbus_framefmt format; + + spinlock_t slock; + struct csis_pktbuf pkt_buf; + struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; + + struct v4l2_async_subdev asd; + struct v4l2_async_notifier subdev_notifier; + struct v4l2_async_subdev *async_subdevs[2]; + + struct csis_hw_reset1 hw_reset; + struct regulator *mipi_phy_regulator; + + struct regmap *gasket; + struct regmap *gpr; + struct regmap *mix_gpr; + struct reset_control *soft_resetn; + struct reset_control *clk_enable; + struct reset_control *mipi_reset; + + mipi_csis_phy_reset_t phy_reset_fn; + bool hdr; +}; + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug level (0-2)"); + +static const struct csis_pix_format mipi_csis_formats[] = { + { + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGBRG10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGRBG10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SRGGB10_1X10, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SBGGR12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGBRG12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SGRBG12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SRGGB12_1X12, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_RGB888_1X24, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RGB888, + .data_alignment = 24, + }, + { + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_VYUY8_2X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT, + .data_alignment = 16, + }, + { + .code = MEDIA_BUS_FMT_SBGGR8_1X8, + .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8, + .data_alignment = 8, + } +}; + +typedef int (*mipi_csis_phy_reset_t) (struct csi_state *state); + +#define mipi_csis_write(__csis, __r, __v) writel(__v, __csis->regs + __r) +#define mipi_csis_read(__csis, __r) readl(__csis->regs + __r) + +static void dump_csis_regs(struct csi_state *state, const char *label) +{ + struct { + u32 offset; + const char *const name; + } registers[] = { + { + 0x00, "CSIS_VERSION"}, { + 0x04, "CSIS_CMN_CTRL"}, { + 0x08, "CSIS_CLK_CTRL"}, { + 0x10, "CSIS_INTMSK"}, { + 0x14, "CSIS_INTSRC"}, { + 0x20, "CSIS_DPHYSTATUS"}, { + 0x24, "CSIS_DPHYCTRL"}, { + 0x30, "CSIS_DPHYBCTRL_L"}, { + 0x34, "CSIS_DPHYBCTRL_H"}, { + 0x38, "CSIS_DPHYSCTRL_L"}, { + 0x3C, "CSIS_DPHYSCTRL_H"}, { + 0x40, "CSIS_ISPCONFIG_CH0"}, { + 0x50, "CSIS_ISPCONFIG_CH1"}, { + 0x60, "CSIS_ISPCONFIG_CH2"}, { + 0x70, "CSIS_ISPCONFIG_CH3"}, { + 0x44, "CSIS_ISPRESOL_CH0"}, { + 0x54, "CSIS_ISPRESOL_CH1"}, { + 0x64, "CSIS_ISPRESOL_CH2"}, { + 0x74, "CSIS_ISPRESOL_CH3"}, { + 0x48, "CSIS_ISPSYNC_CH0"}, { + 0x58, "CSIS_ISPSYNC_CH1"}, { + 0x68, "CSIS_ISPSYNC_CH2"}, { + 0x78, "CSIS_ISPSYNC_CH3"},}; + u32 i; + + v4l2_dbg(2, debug, &state->sd, "--- %s ---\n", label); + + for (i = 0; i < ARRAY_SIZE(registers); i++) { + u32 cfg = mipi_csis_read(state, registers[i].offset); + v4l2_dbg(2, debug, &state->sd, "%20s[%x]: 0x%.8x\n", + registers[i].name, registers[i].offset, cfg); + } +} + +static void dump_gasket_regs(struct csi_state *state, const char *label) +{ + struct { + u32 offset; + const char *const name; + } registers[] = { + { + 0x60, "GPR_GASKET_0_CTRL"}, { + 0x64, "GPR_GASKET_0_HSIZE"}, { + 0x68, "GPR_GASKET_0_VSIZE"},}; + u32 i, cfg; + + v4l2_dbg(2, debug, &state->sd, "--- %s ---\n", label); + + for (i = 0; i < ARRAY_SIZE(registers); i++) { + regmap_read(state->gasket, registers[i].offset, &cfg); + v4l2_dbg(2, debug, &state->sd, "%20s[%x]: 0x%.8x\n", + registers[i].name, registers[i].offset, cfg); + } +} + +static inline struct csi_state *mipi_sd_to_csi_state(struct v4l2_subdev *sdev) +{ + return container_of(sdev, struct csi_state, sd); +} + +static inline struct csi_state *notifier_to_mipi_dev( + struct v4l2_async_notifier *n) +{ + return container_of(n, struct csi_state, subdev_notifier); +} + +static struct media_pad *csis_get_remote_sensor_pad(struct csi_state *state) +{ + struct v4l2_subdev *subdev = &state->sd; + struct media_pad *sink_pad, *source_pad; + int i; + + while (1) { + source_pad = NULL; + for (i = 0; i < subdev->entity.num_pads; i++) { + sink_pad = &subdev->entity.pads[i]; + + if (sink_pad->flags & MEDIA_PAD_FL_SINK) { + source_pad = media_entity_remote_pad(sink_pad); + if (source_pad) + break; + } + } + /* return first pad point in the loop */ + return source_pad; + } + + if (i == subdev->entity.num_pads) + v4l2_err(&state->sd, "%s, No remote pad found!\n", __func__); + + return NULL; +} + +static struct v4l2_subdev *csis_get_remote_subdev(struct csi_state *state, + const char *const label) +{ + struct media_pad *source_pad; + struct v4l2_subdev *sen_sd; + + /* Get remote source pad */ + source_pad = csis_get_remote_sensor_pad(state); + if (!source_pad) { + v4l2_err(&state->sd, "%s, No remote pad found!\n", label); + return NULL; + } + + /* Get remote source pad subdev */ + sen_sd = media_entity_to_v4l2_subdev(source_pad->entity); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", label); + return NULL; + } + + return sen_sd; +} + +const struct csis_pix_format *find_csis_format(u32 code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) + if (code == mipi_csis_formats[i].code) + return &mipi_csis_formats[i]; + return NULL; +} + +#ifdef CSI_HW_INTERRUPT +static void mipi_csis_clean_irq(struct csi_state *state) +{ + u32 status; + + status = mipi_csis_read(state, MIPI_CSIS_INTSRC); + mipi_csis_write(state, MIPI_CSIS_INTSRC, status); + + status = mipi_csis_read(state, MIPI_CSIS_INTMSK); + mipi_csis_write(state, MIPI_CSIS_INTMSK, status); +} + +static void mipi_csis_enable_interrupts(struct csi_state *state, bool on) +{ + u32 val; + + mipi_csis_clean_irq(state); + + val = mipi_csis_read(state, MIPI_CSIS_INTMSK); + if (on) + val |= 0x0FFFFF1F; + else + val &= ~0x0FFFFF1F; + mipi_csis_write(state, MIPI_CSIS_INTMSK, val); +} +#endif + +void mipi_csis_sw_reset(struct csi_state *state) +{ + u32 val; + + val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); + val |= MIPI_CSIS_CMN_CTRL_RESET; + mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); + + udelay(20); +} + +static int mipi_csis_phy_init(struct csi_state *state) +{ + state->mipi_phy_regulator = devm_regulator_get(state->dev, "mipi-phy"); + if (IS_ERR(state->mipi_phy_regulator)) { + dev_err(state->dev, "Fail to get mipi-phy regulator\n"); + return PTR_ERR(state->mipi_phy_regulator); + } + + regulator_set_voltage(state->mipi_phy_regulator, 1000000, 1000000); + return 0; +} + +static void mipi_csis_phy_reset_mx8mn(struct csi_state *state) +{ +#if 0 + struct reset_control *reset = state->mipi_reset; + + reset_control_assert(reset); + usleep_range(10, 20); + + reset_control_deassert(reset); + usleep_range(10, 20); +#else + u32 val; + + regmap_read(state->gpr, 0x00, &val); + val |= 0x30000; + if (state->index == 1) + val |= 0x40000000; + regmap_write(state->gpr, 0x00, val); + regmap_write(state->mix_gpr, 0x138, 0x8d8360); + +#endif +} + +static void mipi_csis_system_enable(struct csi_state *state, int on) +{ + u32 val, mask; + + val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); + if (on) + val |= MIPI_CSIS_CMN_CTRL_ENABLE; + else + val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; + mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); + + val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL); + val &= ~MIPI_CSIS_DPHYCTRL_ENABLE; + if (on) { + mask = (1 << (state->num_lanes + 1)) - 1; + val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE); + } + mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val); +} + +/* Called with the state.lock mutex held */ +static void __mipi_csis_set_format(struct csi_state *state) +{ + struct v4l2_mbus_framefmt *mf = &state->format; + u32 val; + + v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n", + mf->code, mf->width, mf->height); + + /* Color format */ + val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0); + val &= ~MIPI_CSIS_ISPCFG_FMT_MASK; + val |= state->csis_fmt->fmt_reg; + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val); + + val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0); + val &= ~MIPI_CSIS_ISPCONFIG_CH0_PIXEL_MODE_MASK; + if (state->csis_fmt->fmt_reg == MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT) + val |= (PIXEL_MODE_DUAL_PIXEL_MODE << + MIPI_CSIS_ISPCONFIG_CH0_PIXEL_MODE_SHIFT); + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val); + + /* Pixel resolution */ + val = mf->width | (mf->height << 16); + mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val); + if (state->hdr) { + mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH1, val); + mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH2, val); + mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH3, val); + val = state->csis_fmt->fmt_reg; + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH1, val | 1); + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH2, val | 2); + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH3, val | 3); + } +} + +static void mipi_csis_set_hsync_settle(struct csi_state *state) +{ + u32 val; + + val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL); + val &= ~MIPI_CSIS_DPHYCTRL_HSS_MASK; + val |= (state->hs_settle << 24) | (state->clk_settle << 22); + mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val); +} + +void mipi_csis_set_params(struct csi_state *state) +{ + u32 val; + val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); + val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; + val |= (state->num_lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; + val |= MIPI_CSIS_CMN_CTRL_HDR_MODE; + mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); + + __mipi_csis_set_format(state); + mipi_csis_set_hsync_settle(state); + + val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0); + if (state->csis_fmt->data_alignment == 32) + val |= MIPI_CSIS_ISPCFG_ALIGN_32BIT; + else /* Normal output */ + val &= ~MIPI_CSIS_ISPCFG_ALIGN_32BIT; + mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val); + + val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) | + (0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) | + (0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET); + mipi_csis_write(state, MIPI_CSIS_ISPSYNC_CH0, val); + + val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL); + val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC; + if (state->wclk_ext) + val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; + val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); + val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; + mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val); + + mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_L, 0x1f4); + mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_H, 0); + + /* Update the shadow register. */ + val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); + val |= (MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | + MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); + if (state->hdr) { + val |= MIPI_CSIS_CMN_CTRL_HDR_MODE; + val |= 0xE0000; + } + mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); +} + +static int mipi_csis_clk_enable(struct csi_state *state) +{ + struct device *dev = state->dev; + int ret; + + ret = clk_prepare_enable(state->mipi_clk); + if (ret) { + dev_err(dev, "enable mipi_clk failed!\n"); + return ret; + } +#if 0 + ret = clk_prepare_enable(state->phy_clk); + if (ret) { + dev_err(dev, "enable phy_clk failed!\n"); + return ret; + } + + ret = clk_prepare_enable(state->disp_axi); + if (ret) { + dev_err(dev, "enable disp_axi clk failed!\n"); + return ret; + } + + ret = clk_prepare_enable(state->disp_apb); + if (ret) { + dev_err(dev, "enable disp_apb clk failed!\n"); + return ret; + } +#endif + return 0; +} + +static void mipi_csis_clk_disable(struct csi_state *state) +{ + clk_disable_unprepare(state->mipi_clk); +#if 0 + clk_disable_unprepare(state->phy_clk); + clk_disable_unprepare(state->disp_axi); + clk_disable_unprepare(state->disp_apb); +#endif +} + +static int mipi_csis_clk_get(struct csi_state *state) +{ + struct device *dev = &state->pdev->dev; + int ret = true; + + state->mipi_clk = devm_clk_get(dev, "mipi_clk"); + if (IS_ERR(state->mipi_clk)) { + dev_err(dev, "Could not get mipi csi clock\n"); + return -ENODEV; + } +#if 0 + state->phy_clk = devm_clk_get(dev, "phy_clk"); + if (IS_ERR(state->phy_clk)) { + dev_err(dev, "Could not get mipi phy clock\n"); + return -ENODEV; + } + + state->disp_axi = devm_clk_get(dev, "disp_axi"); + if (IS_ERR(state->disp_axi)) { + dev_warn(dev, "Could not get disp_axi clock\n"); + return -ENODEV; + } + + state->disp_apb = devm_clk_get(dev, "disp_apb"); + if (IS_ERR(state->disp_apb)) { + dev_warn(dev, "Could not get disp apb clock\n"); + return -ENODEV; + } +#endif + /* Set clock rate */ + if (state->clk_frequency) { + ret = clk_set_rate(state->mipi_clk, state->clk_frequency); + if (ret < 0) { + dev_err(dev, "set rate filed, rate=%d\n", + state->clk_frequency); + return -EINVAL; + } + } else { + dev_WARN(dev, "No clock frequency specified!\n"); + } + + return 0; +} + +static int disp_mix_sft_rstn(struct reset_control *reset, bool enable) +{ +#if 0 + int ret; + + ret = enable ? reset_control_assert(reset) : + reset_control_deassert(reset); + return ret; +#else + return 0; +#endif +} + +static int disp_mix_clks_enable(struct reset_control *reset, bool enable) +{ +#if 0 + int ret; + + ret = enable ? reset_control_assert(reset) : + reset_control_deassert(reset); + return ret; +#else + return 0; +#endif +} + +void disp_mix_gasket_config(struct csi_state *state) +{ + struct regmap *gasket = state->gasket; + struct csis_pix_format const *fmt = state->csis_fmt; + struct v4l2_mbus_framefmt *mf = &state->format; + s32 fmt_val = -EINVAL; + u32 val; + + switch (fmt->code) { + case MEDIA_BUS_FMT_RGB888_1X24: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RGB888; + break; + case MEDIA_BUS_FMT_YUYV8_2X8: + case MEDIA_BUS_FMT_YVYU8_2X8: + case MEDIA_BUS_FMT_UYVY8_2X8: + case MEDIA_BUS_FMT_VYUY8_2X8: + fmt_val = GASKET_0_CTRL_DATA_TYPE_YUV422_8; + break; + case MEDIA_BUS_FMT_SBGGR10_1X10: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW10; + break; + case MEDIA_BUS_FMT_SGBRG10_1X10: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW10; + break; + case MEDIA_BUS_FMT_SGRBG10_1X10: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW10; + break; + case MEDIA_BUS_FMT_SRGGB10_1X10: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW10; + break; + case MEDIA_BUS_FMT_SBGGR12_1X12: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW12; + break; + case MEDIA_BUS_FMT_SGBRG12_1X12: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW12; + break; + case MEDIA_BUS_FMT_SGRBG12_1X12: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW12; + break; + case MEDIA_BUS_FMT_SRGGB12_1X12: + fmt_val = GASKET_0_CTRL_DATA_TYPE_RAW12; + break; + default: + pr_err("gasket not support format %d\n", fmt->code); + return; + } + + regmap_read(gasket, DISP_MIX_GASKET_0_CTRL, &val); + if (fmt_val == GASKET_0_CTRL_DATA_TYPE_YUV422_8) + val |= GASKET_0_CTRL_DUAL_COMP_ENABLE; + val |= GASKET_0_CTRL_DATA_TYPE(fmt_val); + regmap_write(gasket, DISP_MIX_GASKET_0_CTRL, val); + + if (WARN_ON(!mf->width || !mf->height)) + return; + + regmap_write(gasket, DISP_MIX_GASKET_0_HSIZE, mf->width); + regmap_write(gasket, DISP_MIX_GASKET_0_VSIZE, mf->height); +} + +static void disp_mix_gasket_enable(struct csi_state *state, bool enable) +{ + struct regmap *gasket = state->gasket; + + if (enable) + regmap_update_bits(gasket, DISP_MIX_GASKET_0_CTRL, + GASKET_0_CTRL_ENABLE, GASKET_0_CTRL_ENABLE); + else + regmap_update_bits(gasket, DISP_MIX_GASKET_0_CTRL, + GASKET_0_CTRL_ENABLE, 0); +} + +static void mipi_csis_start_stream(struct csi_state *state) +{ + mipi_csis_sw_reset(state); + + disp_mix_gasket_config(state); + mipi_csis_set_params(state); + + mipi_csis_system_enable(state, true); + disp_mix_gasket_enable(state, true); +#ifdef CSI_HW_INTERRUPT + mipi_csis_enable_interrupts(state, true); +#endif + msleep(5); +} + +static void mipi_csis_stop_stream(struct csi_state *state) +{ +#ifdef CSI_HW_INTERRUPT + mipi_csis_enable_interrupts(state, false); +#endif + mipi_csis_system_enable(state, false); + disp_mix_gasket_enable(state, false); +} + +static void mipi_csis_clear_counters(struct csi_state *state) +{ + unsigned long flags; + int i; + + spin_lock_irqsave(&state->slock, flags); + for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) + state->events[i].counter = 0; + spin_unlock_irqrestore(&state->slock, flags); +} + +static void mipi_csis_log_counters(struct csi_state *state, bool non_errors) +{ + int i = non_errors ? MIPI_CSIS_NUM_EVENTS : MIPI_CSIS_NUM_EVENTS - 4; + unsigned long flags; + + spin_lock_irqsave(&state->slock, flags); + + for (i--; i >= 0; i--) { + if (state->events[i].counter > 0 || debug) + v4l2_info(&state->sd, "%s events: %d\n", + state->events[i].name, + state->events[i].counter); + } + spin_unlock_irqrestore(&state->slock, flags); +} + +static int mipi_csi2_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static const struct media_entity_operations mipi_csi2_sd_media_ops = { + .link_setup = mipi_csi2_link_setup, +}; + +/* + * V4L2 subdev operations + */ +int mipi_csis_s_power(struct v4l2_subdev *mipi_sd, int on) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, core, s_power, on); +} + +int mipi_csis_s_stream(struct v4l2_subdev *mipi_sd, int enable) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + + v4l2_dbg(1, debug, mipi_sd, "%s: %d, state: 0x%x\n", + __func__, enable, state->flags); + + if (enable) { + pm_runtime_get_sync(state->dev); + mipi_csis_clear_counters(state); + mipi_csis_start_stream(state); + dump_csis_regs(state, __func__); + dump_gasket_regs(state, __func__); + } else { + mipi_csis_stop_stream(state); + if (debug > 0) + mipi_csis_log_counters(state, true); + pm_runtime_put(state->dev); + } + + return 0; +} + +static int mipi_csis_set_fmt(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_mbus_framefmt *mf = &format->format; + struct csis_pix_format const *csis_fmt; + struct media_pad *source_pad; + struct v4l2_subdev *sen_sd; + int ret; + + /* Get remote source pad */ + source_pad = csis_get_remote_sensor_pad(state); + if (!source_pad) { + v4l2_err(&state->sd, "%s, No remote pad found!\n", __func__); + return -EINVAL; + } + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + format->pad = source_pad->index; + mf->code = MEDIA_BUS_FMT_UYVY8_2X8; + ret = v4l2_subdev_call(sen_sd, pad, set_fmt, NULL, format); + if (ret < 0) { + v4l2_err(&state->sd, "%s, set sensor format fail\n", __func__); + return -EINVAL; + } + + csis_fmt = find_csis_format(mf->code); + if (!csis_fmt) { + csis_fmt = &mipi_csis_formats[0]; + mf->code = csis_fmt->code; + } + + return 0; +} + +static int mipi_csis_get_fmt(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_mbus_framefmt *mf = &state->format; + struct media_pad *source_pad; + struct v4l2_subdev *sen_sd; + int ret; + + /* Get remote source pad */ + source_pad = csis_get_remote_sensor_pad(state); + if (!source_pad) { + v4l2_err(&state->sd, "%s, No remote pad found!\n", __func__); + return -EINVAL; + } + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + format->pad = source_pad->index; + ret = v4l2_subdev_call(sen_sd, pad, get_fmt, NULL, format); + if (ret < 0) { + v4l2_err(&state->sd, "%s, call get_fmt of subdev failed!\n", + __func__); + return ret; + } + + memcpy(mf, &format->format, sizeof(struct v4l2_mbus_framefmt)); + return 0; +} + +static int mipi_csis_s_rx_buffer(struct v4l2_subdev *mipi_sd, void *buf, + unsigned int *size) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + unsigned long flags; + + *size = min_t(unsigned int, *size, MIPI_CSIS_PKTDATA_SIZE); + + spin_lock_irqsave(&state->slock, flags); + state->pkt_buf.data = buf; + state->pkt_buf.len = *size; + spin_unlock_irqrestore(&state->slock, flags); + + return 0; +} + +static int mipi_csis_s_frame_interval(struct v4l2_subdev *mipi_sd, struct v4l2_subdev_frame_interval + *interval) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, video, s_frame_interval, interval); +} + +static int mipi_csis_g_frame_interval(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, video, g_frame_interval, interval); +} + +static int mipi_csis_enum_framesizes(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, pad, enum_frame_size, NULL, fse); +} + +static int mipi_csis_enum_frameintervals(struct v4l2_subdev *mipi_sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum + *fie) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + struct v4l2_subdev *sen_sd; + + /* Get remote source pad subdev */ + sen_sd = csis_get_remote_subdev(state, __func__); + if (!sen_sd) { + v4l2_err(&state->sd, "%s, No remote subdev found!\n", __func__); + return -EINVAL; + } + + return v4l2_subdev_call(sen_sd, pad, enum_frame_interval, NULL, fie); +} + +static int mipi_csis_log_status(struct v4l2_subdev *mipi_sd) +{ + struct csi_state *state = mipi_sd_to_csi_state(mipi_sd); + + mutex_lock(&state->lock); + mipi_csis_log_counters(state, true); + if (debug) { + dump_csis_regs(state, __func__); + dump_gasket_regs(state, __func__); + } + mutex_unlock(&state->lock); + return 0; +} + + +int csis_s_fmt(struct v4l2_subdev *sd, struct csi_sam_format *fmt) +{ + u32 code; + const struct csis_pix_format *csis_format; + struct csi_state *state = container_of(sd, struct csi_state, sd); + + switch (fmt->format) { + case V4L2_PIX_FMT_SBGGR10: + code = MEDIA_BUS_FMT_SBGGR10_1X10; + break; + case V4L2_PIX_FMT_SGBRG10: + code = MEDIA_BUS_FMT_SGBRG10_1X10; + break; + case V4L2_PIX_FMT_SGRBG10: + code = MEDIA_BUS_FMT_SGRBG10_1X10; + break; + case V4L2_PIX_FMT_SRGGB10: + code = MEDIA_BUS_FMT_SRGGB10_1X10; + break; + case V4L2_PIX_FMT_SBGGR12: + code = MEDIA_BUS_FMT_SBGGR12_1X12; + break; + case V4L2_PIX_FMT_SGBRG12: + code = MEDIA_BUS_FMT_SGBRG12_1X12; + break; + case V4L2_PIX_FMT_SGRBG12: + code = MEDIA_BUS_FMT_SGRBG12_1X12; + break; + case V4L2_PIX_FMT_SRGGB12: + code = MEDIA_BUS_FMT_SRGGB12_1X12; + break; + default: + return -EINVAL; + } + csis_format = find_csis_format(code); + if (csis_format == NULL) + return -EINVAL; + + state->csis_fmt = csis_format; + state->format.width = fmt->width; + state->format.height = fmt->height; + disp_mix_gasket_config(state); + mipi_csis_set_params(state); + return 0; +} + +int csis_s_hdr(struct v4l2_subdev *sd, bool enable) +{ + struct csi_state *state = container_of(sd, struct csi_state, sd); + pr_debug("enter %s: %d\n", __func__, enable); + state->hdr = enable; + return 0; +} + +int csis_ioc_qcap(struct v4l2_subdev *dev, void *args) +{ + struct csi_state *state = mipi_sd_to_csi_state(dev); + struct v4l2_capability *cap = (struct v4l2_capability *)args; + strcpy((char *)cap->driver, "csi_sam_subdev"); + cap->bus_info[0] = state->index; + return 0; +} + +#ifdef __KERNEL__ +#define USER_TO_KERNEL(TYPE) \ + do {\ + TYPE tmp; \ + arg = (void *)(&tmp); \ + copy_from_user(arg, arg_user, sizeof(TYPE));\ + } while (0) + +#define KERNEL_TO_USER(TYPE) \ + copy_to_user(arg_user, arg, sizeof(TYPE)); +#else +#define USER_TO_KERNEL(TYPE) +#define KERNEL_TO_USER(TYPE) +#endif +long csis_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg_user) +{ + int ret = 1; + struct csi_state *state = container_of(sd, struct csi_state, sd); + void *arg = arg_user; + + pr_debug("enter %s\n", __func__); + switch (cmd) { + case VVCSIOC_RESET: + mipi_csis_sw_reset(state); + ret = 0; + break; + case VVCSIOC_POWERON: + ret = mipi_csis_s_power(sd, 1); + break; + case VVCSIOC_POWEROFF: + ret = mipi_csis_s_power(sd, 0); + break; + case VVCSIOC_STREAMON: + ret = mipi_csis_s_stream(sd, 1); + break; + case VVCSIOC_STREAMOFF: + ret = mipi_csis_s_stream(sd, 0); + break; + case VVCSIOC_S_FMT: { + USER_TO_KERNEL(struct csi_sam_format); + ret = csis_s_fmt(sd, (struct csi_sam_format *)arg); + break; + } + case VVCSIOC_S_HDR: { + USER_TO_KERNEL(bool); + ret = csis_s_hdr(sd, *(bool *) arg); + break; + } + case VIDIOC_QUERYCAP: + ret = csis_ioc_qcap(sd, arg); + break; + default: + pr_err("unsupported csi-sam command %d.", cmd); + break; + } + + return ret; +} + +static struct v4l2_subdev_core_ops mipi_csis_core_ops = { + .s_power = mipi_csis_s_power, + .log_status = mipi_csis_log_status, + .ioctl = csis_priv_ioctl, +}; + +static struct v4l2_subdev_video_ops mipi_csis_video_ops = { + .s_rx_buffer = mipi_csis_s_rx_buffer, + .s_stream = mipi_csis_s_stream, + + .g_frame_interval = mipi_csis_g_frame_interval, + .s_frame_interval = mipi_csis_s_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { + .enum_frame_size = mipi_csis_enum_framesizes, + .enum_frame_interval = mipi_csis_enum_frameintervals, + .get_fmt = mipi_csis_get_fmt, + .set_fmt = mipi_csis_set_fmt, +}; + +static struct v4l2_subdev_ops mipi_csis_subdev_ops = { + .core = &mipi_csis_core_ops, + .video = &mipi_csis_video_ops, + .pad = &mipi_csis_pad_ops, +}; + +#ifdef CSI_HW_INTERRUPT +static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) +{ + struct csi_state *state = dev_id; + struct csis_pktbuf *pktbuf = &state->pkt_buf; + unsigned long flags; + u32 status; + + status = mipi_csis_read(state, MIPI_CSIS_INTSRC); + + spin_lock_irqsave(&state->slock, flags); + if ((status & MIPI_CSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) { + u32 offset; + + if (status & MIPI_CSIS_INTSRC_EVEN) + offset = MIPI_CSIS_PKTDATA_EVEN; + else + offset = MIPI_CSIS_PKTDATA_ODD; + + memcpy(pktbuf->data, state->regs + offset, pktbuf->len); + pktbuf->data = NULL; + rmb(); + } + + /* Update the event/error counters */ + if ((status & MIPI_CSIS_INTSRC_ERRORS) || debug) { + int i; + for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { + if (!(status & state->events[i].mask)) + continue; + state->events[i].counter++; + v4l2_dbg(2, debug, &state->sd, "%s: %d\n", + state->events[i].name, + state->events[i].counter); + } + v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status); + } + spin_unlock_irqrestore(&state->slock, flags); + + mipi_csis_write(state, MIPI_CSIS_INTSRC, status); + return IRQ_HANDLED; +} +#endif + +static int mipi_csis_parse_dt(struct platform_device *pdev, + struct csi_state *state) +{ + struct device_node *node = pdev->dev.of_node; + + state->index = of_alias_get_id(node, "csi"); + + if (of_property_read_u32 + (node, "clock-frequency", &state->clk_frequency)) + state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; + + if (of_property_read_u32(node, "bus-width", &state->max_num_lanes)) + return -EINVAL; + + node = of_graph_get_next_endpoint(node, NULL); + if (!node) { + dev_err(&pdev->dev, "No port node at %s\n", node->full_name); + return -EINVAL; + } + + /* Get MIPI CSI-2 bus configration from the endpoint node. */ + of_property_read_u32(node, "csis-hs-settle", &state->hs_settle); + of_property_read_u32(node, "csis-clk-settle", &state->clk_settle); + of_property_read_u32(node, "data-lanes", &state->num_lanes); + + state->wclk_ext = of_property_read_bool(node, "csis-wclk"); + + of_node_put(node); + return 0; +} + +static const struct of_device_id mipi_csis_of_match[]; + +/* init subdev */ +static int mipi_csis_subdev_init(struct v4l2_subdev *mipi_sd, + struct platform_device *pdev, + const struct v4l2_subdev_ops *ops) +{ + struct csi_state *state = platform_get_drvdata(pdev); + int ret = 0; + + v4l2_subdev_init(mipi_sd, ops); + mipi_sd->owner = THIS_MODULE; + snprintf(mipi_sd->name, sizeof(mipi_sd->name), "%s.%d", + CSIS_SUBDEV_NAME, state->index); + mipi_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + mipi_sd->entity.function = MEDIA_ENT_F_IO_V4L; + mipi_sd->dev = &pdev->dev; + + state->csis_fmt = &mipi_csis_formats[0]; + state->format.code = mipi_csis_formats[0].code; + state->format.width = MIPI_CSIS_DEF_PIX_WIDTH; + state->format.height = MIPI_CSIS_DEF_PIX_HEIGHT; + + /* This allows to retrieve the platform device id by the host driver */ + v4l2_set_subdevdata(mipi_sd, state); + + state->v4l2_dev = kzalloc(sizeof(*state->v4l2_dev), GFP_KERNEL); + if (WARN_ON(!state->v4l2_dev)) { + ret = -ENOMEM; + goto end; + } + + ret = v4l2_device_register(&(pdev->dev), state->v4l2_dev); + if (WARN_ON(ret < 0)) + goto end; + + ret = v4l2_device_register_subdev(state->v4l2_dev, mipi_sd); + + if (ret) { + pr_err("failed to register csis-subdev %d\n", ret); + goto end; + } + + ret = v4l2_device_register_subdev_nodes(state->v4l2_dev); +end: + return ret; +} + +static int mipi_csis_of_parse_resets(struct csi_state *state) +{ +#if 0 + int ret; + struct device *dev = state->dev; + struct device_node *np = dev->of_node; + struct device_node *parent, *child; + struct of_phandle_args args; + struct reset_control *rstc; + const char *compat; + uint32_t len, rstc_num = 0; + + ret = of_parse_phandle_with_args(np, "resets", "#reset-cells", + 0, &args); + if (ret) + return ret; + + parent = args.np; + for_each_child_of_node(parent, child) { + compat = of_get_property(child, "compatible", NULL); + if (!compat) + continue; + + rstc = of_reset_control_array_get(child, false, false, true); + if (IS_ERR(rstc)) + continue; + + len = strlen(compat); + if (!of_compat_cmp("csi,soft-resetn", compat, len)) { + state->soft_resetn = rstc; + rstc_num++; + } else if (!of_compat_cmp("csi,clk-enable", compat, len)) { + state->clk_enable = rstc; + rstc_num++; + } else if (!of_compat_cmp("csi,mipi-reset", compat, len)) { + state->mipi_reset = rstc; + rstc_num++; + } else { + dev_warn(dev, "invalid csis reset node: %s\n", compat); + } + } + + if (!rstc_num) { + dev_err(dev, "no invalid reset control exists\n"); + return -EINVAL; + } + of_node_put(parent); + +#else + return 0; +#endif +} + +static int mipi_csis_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct v4l2_subdev *mipi_sd; + struct resource *mem_res; + struct csi_state *state; + struct device_node *media_mix_gpr; + const struct of_device_id *of_id; + mipi_csis_phy_reset_t phy_reset_fn; + int ret = -ENOMEM; + + state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); + if (!state) + return -ENOMEM; + + mutex_init(&state->lock); + spin_lock_init(&state->slock); + + /* WA on VSI platform, need insmod dynamically for debug */ + pdev->dev.of_node = + of_find_compatible_node(NULL, NULL, "fsl,imx8mp-mipi-csi"); + media_mix_gpr = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-ldb"); + + state->pdev = pdev; + mipi_sd = &state->sd; + state->dev = dev; + + ret = mipi_csis_parse_dt(pdev, state); + if (ret < 0) + return ret; + + /* Hardcode here */ + state->num_lanes = 4; + state->hs_settle = 0x10; + + if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) { + dev_err(dev, "Unsupported number of data lanes: %d (max. %d)\n", + state->num_lanes, state->max_num_lanes); + return -EINVAL; + } + + ret = mipi_csis_phy_init(state); + if (ret < 0) + return ret; + + of_id = of_match_node(mipi_csis_of_match, dev->of_node); + if (!of_id || !of_id->data) { + dev_err(dev, "No match data for %s\n", dev_name(dev)); + return -EINVAL; + } + phy_reset_fn = of_id->data; + state->phy_reset_fn = phy_reset_fn; + + state->gasket = + syscon_regmap_lookup_by_phandle(dev->of_node, "csi-gpr"); + if (IS_ERR(state->gasket)) { + dev_err(dev, "failed to get csi gasket\n"); + return PTR_ERR(state->gasket); + } + + state->gpr = syscon_regmap_lookup_by_phandle(dev->of_node, "csi-gpr2"); + if (IS_ERR(state->gpr)) { + dev_err(dev, "failed to get csi gpr\n"); + return PTR_ERR(state->gpr); + } + + state->mix_gpr = syscon_regmap_lookup_by_phandle(media_mix_gpr, "gpr"); + if (IS_ERR(state->mix_gpr)) { + dev_err(dev, "failed to get mix gpr\n"); + return PTR_ERR(state->mix_gpr); + } + + ret = of_clk_set_defaults(dev->of_node, false); + if (ret < 0) { + pr_err("clk: couldn't set desired clock for CSI\n"); + return ret; + } + + ret = mipi_csis_of_parse_resets(state); + if (ret < 0) { + dev_err(dev, "Can not parse reset control\n"); + return ret; + } + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + //state->regs = devm_ioremap_resource(dev, mem_res); + state->regs = ioremap(0x32e40000, 0x00001000); + if (IS_ERR(state->regs)) + return PTR_ERR(state->regs); +#ifdef CSI_HW_INTERRUPT + state->irq = platform_get_irq(pdev, 0); + if (state->irq < 0) { + dev_err(dev, "Failed to get irq\n"); + return state->irq; + } +#endif + ret = mipi_csis_clk_get(state); + if (ret < 0) + return ret; + + ret = mipi_csis_clk_enable(state); + if (ret < 0) + return ret; + + disp_mix_clks_enable(state->clk_enable, true); + disp_mix_sft_rstn(state->soft_resetn, false); + phy_reset_fn(state); + + /* mipi_csis_clk_disable(state); */ +#ifdef CSI_HW_INTERRUPT + ret = devm_request_irq(dev, state->irq, mipi_csis_irq_handler, 0, + dev_name(dev), state); + if (ret) { + dev_err(dev, "Interrupt request failed\n"); + return ret; + } +#endif + + platform_set_drvdata(pdev, state); + ret = mipi_csis_subdev_init(&state->sd, pdev, &mipi_csis_subdev_ops); + if (ret < 0) { + dev_err(dev, "mipi csi subdev init failed\n"); + return ret; + } + + state->pads[MIPI_CSIS_VC0_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC1_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC2_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC3_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + state->pads[MIPI_CSIS_VC0_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + state->pads[MIPI_CSIS_VC1_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + state->pads[MIPI_CSIS_VC2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + state->pads[MIPI_CSIS_VC3_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + ret = + media_entity_pads_init(&state->sd.entity, MIPI_CSIS_VCX_PADS_NUM, + state->pads); + if (ret < 0) { + dev_err(dev, "mipi csi entity pad init failed\n"); + return ret; + } + + memcpy(state->events, mipi_csis_events, sizeof(state->events)); + state->sd.entity.ops = &mipi_csi2_sd_media_ops; + + pm_runtime_enable(dev); + /* mipi_csis_s_stream(&state->sd, 1); */ + + dev_info(&pdev->dev, + "lanes: %d, hs_settle: %d, clk_settle: %d, wclk: %d, freq: %u\n", + state->num_lanes, state->hs_settle, state->clk_settle, + state->wclk_ext, state->clk_frequency); + return 0; +} + +static int mipi_csis_system_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev);; +} + +static int mipi_csis_system_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + + return 0; +} + +static int mipi_csis_runtime_suspend(struct device *dev) +{ + struct csi_state *state = dev_get_drvdata(dev); + int ret; + + ret = regulator_disable(state->mipi_phy_regulator); + if (ret < 0) + return ret; + + disp_mix_clks_enable(state->clk_enable, false); + mipi_csis_clk_disable(state); + return 0; +} + +static int mipi_csis_runtime_resume(struct device *dev) +{ + struct csi_state *state = dev_get_drvdata(dev); + int ret; + + ret = regulator_enable(state->mipi_phy_regulator); + if (ret < 0) + return ret; + + ret = mipi_csis_clk_enable(state); + if (ret < 0) + return ret; + + disp_mix_clks_enable(state->clk_enable, true); + disp_mix_sft_rstn(state->soft_resetn, false); + + if (state->phy_reset_fn) + state->phy_reset_fn(state); + + return 0; +} + +static int mipi_csis_remove(struct platform_device *pdev) +{ + struct csi_state *state = platform_get_drvdata(pdev); + + media_entity_cleanup(&state->sd.entity); + + v4l2_device_unregister_subdev(&state->sd); + v4l2_device_disconnect(state->v4l2_dev); + v4l2_device_put(state->v4l2_dev); + + return 0; +} + +static const struct dev_pm_ops mipi_csis_pm_ops = { + SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, + NULL) + SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_system_suspend, + mipi_csis_system_resume) +}; + +static const struct of_device_id mipi_csis_of_match[] = { + {.compatible = "fsl,imx8mn-mipi-csi", + .data = (void *)&mipi_csis_phy_reset_mx8mn, + }, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, mipi_csis_of_match); + +static struct platform_driver mipi_csis_driver = { + .driver = { + .name = CSIS_DRIVER_NAME, + .owner = THIS_MODULE, + .pm = &mipi_csis_pm_ops, + .of_match_table = mipi_csis_of_match, + }, + .probe = mipi_csis_probe, + .remove = mipi_csis_remove, +}; + +static int __init csi_init_module(void) +{ + int ret = 0; + pr_debug("enter %s\n", __func__); + + ret = platform_driver_register(&mipi_csis_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + return ret; +} + +static void __exit csi_exit_module(void) +{ + pr_debug("enter %s\n", __func__); + platform_driver_unregister(&mipi_csis_driver); +} + +module_init(csi_init_module); +module_exit(csi_exit_module); + +MODULE_DESCRIPTION("Freescale MIPI-CSI2 receiver driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("CSI Capture"); +MODULE_VERSION("1.0"); diff --git a/vvcam_ry/v4l2/dts/nxp_imx8mp/imx8mp-evk-dual-ov2775.dts b/vvcam_ry/v4l2/dts/nxp_imx8mp/imx8mp-evk-dual-ov2775.dts new file mode 100755 index 0000000..32fa36c --- /dev/null +++ b/vvcam_ry/v4l2/dts/nxp_imx8mp/imx8mp-evk-dual-ov2775.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2021 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + ov2775_0: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_0_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /delete-node/ov5640_mipi@3c; + + ov2775_1: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_1_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + clock-frequency = <266000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; + + port@0 { + endpoint { + remote-endpoint = <&ov2775_mipi_0_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov2775_mipi_1_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; diff --git a/vvcam_ry/v4l2/dts/nxp_imx8mp/imx8mp-evk.dts b/vvcam_ry/v4l2/dts/nxp_imx8mp/imx8mp-evk.dts new file mode 100755 index 0000000..91d926c --- /dev/null +++ b/vvcam_ry/v4l2/dts/nxp_imx8mp/imx8mp-evk.dts @@ -0,0 +1,1343 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MPlus EVK board"; + compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@0x55800000 { + no-map; + reg = <0 0x55800000 0 0x800000>; + }; + }; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; /* LED GREEN */ + }; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai3>; + audio-codec = <&codec>; + asrc-controller = <&easrc>; + codec-master; + /* JD2: hp detect high for headphone*/ + hp-det = <3 0>; + hp-det-gpios = <&gpio4 28 0>; + mic-det-gpios = <&gpio4 28 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "Mic Jack", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-xcvr"; + model = "imx-audio-xcvr"; + cpu-dai = <&xcvr>; + }; + + lvds_backlight: lvds_backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 100000>; + status = "okay"; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&clk { + init-on-array = ; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev1: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + lvds_bridge: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + + port { + it6263_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio4>; + interrupts = <19 8>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; + + ov5640_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + + port { + ov5640_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ov5640_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "disabled"; + + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + wlf,shared-lrclk; + SPKVDD1-supply = <®_audio_pwr>; + }; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + pinctrl-assert-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; + status = "disabled";/* can2 pin conflict with pdm: gpio low select pdm, gpio high select can2 */ +}; + +&hdmimix_clk { + status = "okay"; +}; + +&hdmimix_reset { + status = "okay"; +}; + +&hdmi_pavi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&lcdif1 { + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; + + thres-low = <1 2>; /* (FIFO * 1 / 2) */ + thres-high = <3 4>; /* (FIFO * 3 / 4) */ +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds_out: endpoint { + remote-endpoint = <&it6263_in>; + }; + }; + }; +}; + +&ldb_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&pcie{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_PCIE_AUX>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <500000000>, <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + status = "okay"; +}; + +&pcie_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + ext_osc = <1>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_PCIE_AUX>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <500000000>, <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + status = "disabled"; +}; + +&pcie_phy{ + ext_osc = <1>; + status = "okay"; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MP_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usb3_phy0 { + vbus-power-supply = <&ptn5110>; + fsl,phy-tx-vref-tune = <6>; + fsl,phy-tx-rise-tune = <0>; + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-comp-dis-tune = <7>; + fsl,pcs-tx-deemph-3p5db = <0x21>; + fsl,phy-pcs-tx-swing-full = <0x7f>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune = <2>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_typec: typec1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + >; + }; + + pinctrl_typec_mux: typec1muxgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x16 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usb1_vbus: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_csi0_pwn: csi0_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19 + >; + }; + + pinctrl_csi0_rst: csi0_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 + >; + }; + + pinctrl_csi_mclk: csi_mclk_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x59 + >; + }; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_vc8000e { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&gpu_2d { + status = "okay"; +}; + +&ml_vipsi { + status = "okay"; +}; + +&mix_gpu_ml { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_0_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov5640_mipi_1_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&dsp { + status = "okay"; +}; diff --git a/vvcam_ry/v4l2/dts/nxp_imx8mp/imx8mp.dtsi b/vvcam_ry/v4l2/dts/nxp_imx8mp/imx8mp.dtsi new file mode 100755 index 0000000..ae5a504 --- /dev/null +++ b/vvcam_ry/v4l2/dts/nxp_imx8mp/imx8mp.dtsi @@ -0,0 +1,2460 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "imx8mp-pinfunc.h" + +/ { + compatible = "fsl,imx8mp"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + isi0 = &isi_0; + isi1 = &isi_1; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + isp0 = &isp_0; + isp1 = &isp_1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + clocks = <&clk IMX8MP_CLK_ARM>; + operating-points-v2 = <&a53_opp_table>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x8a0>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0xa0>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1000000>; + opp-supported-hw = <0x20>, <0x3>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + ddr_pmu0: ddr_pmu@3d800000 { + compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; + reg = <0x0 0x3d800000 0x0 0x400000>; + interrupts = ; + }; + + edacmc: memory-controller@3d400000 { + compatible = "fsl,imx8mp-ddrc"; + reg = <0x0 0x3d400000 0x0 0x400000>; + interrupts = ; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ocram: ocram@900000 { + no-map; + reg = <0 0x900000 0 0x70000>; + }; + +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@56000000 { + * reg = <0 0x56000000 0 0x2000000>; + * no-map; + * }; + */ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x40000000 0 0xC0000000>; + linux,cma-default; + }; + + dsp_reserved: dsp@92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock-ext2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock-ext3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock-ext4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>, + <&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>, + <&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>, + <&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>, + <&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + }; + + power-domains { + compatible = "simple-bus"; + + /* HSIO SS */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + active-wakeup; + rpm-always-on; + #power-domain-cells = <0>; + domain-index = <0>; + domain-name = "hsiomix"; + }; + + pcie_pd: pcie-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <1>; + domain-name = "pcie"; + parent-domains = <&hsiomix_pd>; + }; + + usb_otg1_pd: usbotg1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + + usb_otg2_pd: usbotg2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <3>; + domain-name = "usb_otg2"; + parent-domains = <&hsiomix_pd>; + }; + + /* MLMIX */ + mlmix_pd: mlmix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <4>; + domain-name = "mlmix"; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + }; + + audiomix_pd: audiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <5>; + domain-name = "audiomix"; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI_DIV>; + }; + + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "gpumix"; + clocks = <&clk IMX8MP_CLK_GPU_ROOT>, <&clk IMX8MP_CLK_GPU_AHB>, + <&clk IMX8MP_CLK_GPU_AXI>; + }; + + gpu2d_pd: gpu2d-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <7>; + domain-name = "gpu2d"; + parent-domains = <&gpumix_pd>; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; + }; + + gpu3d_pd: gpu3d-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <8>; + domain-name = "gpu3d"; + parent-domains = <&gpumix_pd>; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_DIV>; + }; + + vpumix_pd: vpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <9>; + domain-name = "vpumix"; + clocks =<&clk IMX8MP_CLK_VPU_ROOT>; + }; + + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <10>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + }; + + vpu_g2_pd: vpug2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <11>; + domain-name = "vpu_g2"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + }; + + vpu_h1_pd: vpuh1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <12>; + domain-name = "vpu_h1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + }; + + mediamix_pd: mediamix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <13>; + domain-name = "mediamix"; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + }; + + ispdwp_pd: power-domain@14 { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <14>; + domain-name = "ispdwp"; + parent-domains = <&mediamix_pd>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>; + }; + + mipi_phy1_pd: mipiphy1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <15>; + domain-name = "mipi_phy1"; + parent-domains = <&mediamix_pd>; + }; + + mipi_phy2_pd: mipiphy2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <16>; + domain-name = "mipi_phy2"; + parent-domains = <&mediamix_pd>; + }; + + hdmimix_pd: hdmimix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <17>; + domain-name = "hdmimix"; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>; + }; + + hdmi_phy_pd: hdmiphy-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <18>; + domain-name = "hdmi_phy"; + parent-domains = <&hdmimix_pd>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <8000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0x0>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + soc-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0x1>; + trips { + soc_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + + aips1: bus@30000000 { + compatible = "simple-bus"; + reg = <0x30000000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tmu: tmu@30260000 { + compatible = "fsl,imx8mp-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + #thermal-sensor-cells = <1>; + }; + + wdog1: watchdog@30280000 { + compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mp-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mp-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; + /* For nvmem subnodes */ + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + + eth_mac1: mac-address@640 { + reg = <0x90 6>; + }; + + eth_mac2: mac-address@650 { + reg = <0x96 6>; + }; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", + "syscon"; + reg = <0x30360000 0x10000>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "snvs-rtc"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "snvs"; + linux,keycode = ; + wakeup-source; + }; + }; + + clk: clock-controller@30380000 { + compatible = "fsl,imx8mp-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + assigned-clocks = <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_NOC_IO>, + <&clk IMX8MP_CLK_GIC>, + <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, + <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, + <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, + <800000000>, + <500000000>, + <400000000>, + <800000000>, + <400000000>, + <393216000>, + <361267200>, + <1039500000>; + }; + + src: src@30390000 { + compatible = "fsl,imx8mp-src", "fsl,imx8mq-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = ; + #reset-cells = <1>; + }; + }; + + aips2: bus@30400000 { + compatible = "simple-bus"; + reg = <0x30400000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pwm1: pwm@30660000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, + <&clk IMX8MP_CLK_PWM1_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, + <&clk IMX8MP_CLK_PWM2_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, + <&clk IMX8MP_CLK_PWM3_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, + <&clk IMX8MP_CLK_PWM4_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + system_counter: timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x306a0000 0x20000>; + interrupts = ; + clocks = <&osc_24m>; + clock-names = "per"; + }; + }; + + aips3: bus@30800000 { + compatible = "simple-bus"; + reg = <0x30800000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, + <&clk IMX8MP_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, + <&clk IMX8MP_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, + <&clk IMX8MP_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART1_ROOT>, + <&clk IMX8MP_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART3_ROOT>, + <&clk IMX8MP_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART2_ROOT>, + <&clk IMX8MP_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + flexcan1: can@308c0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source= <0>; + fsl,stop-mode = <&gpr 0x10 4 0x10 20>; + status = "disabled"; + }; + + flexcan2: can@308d0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308d0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source= <0>; + fsl,stop-mode = <&gpr 0x10 5 0x10 21>; + status = "disabled"; + }; + + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_AHB>, + <&clk IMX8MP_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART4_ROOT>, + <&clk IMX8MP_CLK_UART4_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mu: mu@30aa0000 { + compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + + i2c5: i2c@30ad0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30ad0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; + status = "disabled"; + }; + + i2c6: i2c@30ae0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + reg = <0x30ae0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; + status = "disabled"; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@30b50000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC3_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, + <&clk IMX8MP_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; + status = "disabled"; + }; + + sdma1: dma-controller@30bd0000 { + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, + <&clk IMX8MP_CLK_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + fec: ethernet@30be0000 { + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = , + , + ; + clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, + <&clk IMX8MP_CLK_SIM_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_TIMER>, + <&clk IMX8MP_CLK_ENET_REF>, + <&clk IMX8MP_CLK_ENET_PHY_REF>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_TIMER>, + <&clk IMX8MP_CLK_ENET_REF>, + <&clk IMX8MP_CLK_ENET_TIMER>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + eqos: ethernet@30bf0000 { + compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x30bf0000 0x10000>; + interrupts = , + ; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, + <&clk IMX8MP_CLK_QOS_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <100000000>, <125000000>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + intf_mode = <&gpr 0x4>; + status = "disabled"; + }; + }; + + aips5: bus@30c00000 { + compatible = "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spba-bus@30c00000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sai1: sai@30c10000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c10000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xff 0xff>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai2: sai@30c20000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c20000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai3: sai@30c30000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c30000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0x3 0x3>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai5: sai@30c50000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c50000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai6: sai@30c60000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c60000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai7: sai@30c80000 { + compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x30c80000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + easrc: easrc@30c90000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x30c90000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + micfil: micfil@30ca0000 { + compatible = "fsl,imx8mp-micfil"; + reg = <0x30ca0000 0x10000>; + interrupts = , + , + , + ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_PDM_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_PDM_ROOT>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&clk IMX8MP_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + aud2htx: aud2htx@30cb0000 { + compatible = "fsl,imx8mp-aud2htx"; + reg = <0x30cb0000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; + clock-names = "bus"; + dmas = <&sdma2 26 2 0>; + dma-names = "tx"; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + xcvr: xcvr@30cc0000 { + compatible = "fsl,imx8mp-xcvr"; + reg = <0x30cc0000 0x800>, + <0x30cc0800 0x400>, + <0x30cc0c00 0x080>, + <0x30cc0e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + , + /* XCVR IRQ 1 */ + , + /* XCVR PHY - SPDIF wakeup IRQ */ + ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; + dma-names = "rx", "tx"; + resets = <&audiomix_reset 0>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + }; + + sdma3: dma-controller@30e00000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; + reg = <0x30e00000 0x10000>; + interrupts = ; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sdma2: dma-controller@30e10000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; + reg = <0x30e10000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + audiomix: audiomix@30e20000 { + compatible = "fsl,imx8mp-audiomix"; + reg = <0x30e20000 0x10000>; + + audiomix_clk: clock-controller { + compatible = "fsl,imx8mp-audiomix-clk"; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "audio_root"; + power-domains = <&audiomix_pd>; + }; + + audiomix_reset: reset-controller { + compatible = "fsl,imx8mp-audiomix-reset"; + power-domains = <&audiomix_pd>; + #reset-cells = <1>; + }; + + audiomix_dsp: audiomix_dsp { + compatible = "fsl,audiomix-dsp"; + }; + }; + + mu2: mu2@30e60000 { + compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; + reg = <0x30E60000 0x10000>; + interrupts = ; + fsl,dsp_ap_mu_id = <2>; + #mbox-cells = <2>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; + status = "okay"; + }; + }; + + aips4: bus@32c00000 { + compatible = "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mipi_dsi: mipi_dsi@32e60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-mipi-dsim"; + reg = <0x32e60000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <12000000>; + interrupts = ; + power-domains = <&mipi_phy1_pd>; + blk-ctl = <&mediamix_blk_ctl>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + lcdif1: lcd-controller@32e80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif1"; + reg = <0x32e80000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <500000000>, <200000000>; + interrupts = ; + blk-ctl = <&mediamix_blk_ctl>; + power-domains = <&mediamix_pd>; + status = "disabled"; + + lcdif1_disp: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + lcdif2: lcd-controller@32e90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif2"; + reg = <0x32e90000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&mediamix_pd>; + status = "disabled"; + + lcdif2_disp: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + lcdif2_disp_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ldb_ch0>; + }; + + lcdif2_disp_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ldb_ch1>; + }; + }; + }; + + mediamix_blk_ctl: blk-ctl@32ec0000 { + compatible = "fsl,imx8mp-mediamix-blk-ctl", + "syscon"; + reg = <0x32ec0000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + }; + + ldb: ldb@32ec005c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ldb"; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + gpr = <&mediamix_blk_ctl>; + power-domains = <&mediamix_pd>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch0: endpoint { + remote-endpoint = <&lcdif2_disp_ldb_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch1: endpoint { + remote-endpoint = <&lcdif2_disp_ldb_ch1>; + }; + }; + }; + }; + + /* TODO for HDMI PHY power on */ + hdmi_blk: hdmi-blk@32fc0000 { + compatible = "syscon"; + reg = <0x32fc0000 0x1000>; + }; + + hdmimix: hdmimix@32fc0000 { + compatible = "fsl,imx8mp-audiomix", "fsl,imx8mp-hdmimix"; + reg = <0x32fc0000 0x1000>; + + hdmimix_clk: clock-controller { + compatible = "fsl,imx8mp-hdmimix-clk"; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_DUMMY>; + clock-names = "dummy"; + status = "disabled"; + }; + + hdmimix_reset: reset-controller { + compatible = "fsl,imx8mp-hdmimix-reset"; + #reset-cells = <1>; + status = "disabled"; + }; + }; + + irqsteer_hdmi: irqsteer@32fc2000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_IRQS_STEER_CLK>; + clock-names = "ipg"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <200000000>; + resets = <&hdmimix_reset IMX_HDMIMIX_IRQ_STEER_RESET>; + status = "disabled"; + }; + + hdmi_pavi: hdmi-pai-pvi@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pavi"; + reg = <0x32fc4000 0x1000>; + clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_VID_LINK_PIX_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_GPA_CLK>; + clock-names = "pvi_clk", "pai_clk"; + resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PAI_RESET>, + <&hdmimix_reset IMX_HDMIMIX_HDMI_PVI_RESET>; + reset-names = "pai_rst", "pvi_rst"; + status = "disabled"; + }; + + lcdif3: lcd-controller@32fc6000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif3"; + reg = <0x32fc6000 0x10000>; + clocks = <&hdmiphy 0>, + <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_B_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_TX_PIX_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_B_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PDI_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PIX_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_SPU_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_NOC_HDMI_CLK>; + clock-names = "pix", "disp-axi", "disp-apb", + "mix_apb","mix_axi", "xtl_24m", "mix_pix", "lcdif_apb", + "lcdif_axi", "lcdif_pdi", "lcdif_pix", "lcdif_spu", + "noc_hdmi"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + resets = <&hdmimix_reset IMX_HDMIMIX_LCDIF_RESET>; + power-domains = <&hdmimix_pd>; + status = "disabled"; + + lcdif3_disp: port@0 { + reg = <0>; + + lcdif3_to_hdmi: endpoint { + remote-endpoint = <&hdmi_from_lcdif3>; + }; + }; + }; + + hdmi: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi"; + reg = <0x32fd8000 0x7eff>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_INT_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PREP_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SKP_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SFR_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIXEL_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_CEC_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_HPI_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_FDCC_REF_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIPE_CLK_SEL>; + clock-names = "iahb", "isfr", + "phy_int", "prep_clk", "skp_clk", "sfr_clk", "pix_clk", + "cec_clk", "apb_clk", "hpi_clk", "fdcc_ref", "pipe_clk"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <200000000>, <500000000>, <24000000>; + phys = <&hdmiphy>; + phy-names = "hdmi"; + resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_TX_RESET>; + gpr = <&hdmi_blk>; + power-domains = <&hdmi_phy_pd>; + status = "disabled"; + + port@0 { + hdmi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_hdmi>; + }; + }; + }; + + hdmiphy: hdmiphy@32fdff00 { + compatible = "fsl,samsung-hdmi-phy"; + reg = <0x32fdff00 0x100>; + #clock-cells = <1>; + clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>; + clock-names = "apb", "ref"; + clock-output-names = "hdmi_phy"; + #phy-cells = <0>; + resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PHY_RESET>; + status = "disabled"; + }; + + mediamix_gasket0: gasket@32ec0060 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0060 0x28>; + }; + + mediamix_gasket1: gasket@32ec0090 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0090 0x28>; + }; + + ldb_phy: phy@32ec0128 { + compatible = "fsl,imx8mp-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&mediamix_blk_ctl>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "apb"; + power-domains = <&mediamix_pd>; + status = "disabled"; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + mediamix_gpr: media_gpr@32ec0008 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0008 0x4>; + }; + + isi_chain_buf: isi_chain@32e02000{ + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32e02000 0x4>; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + isi_0: isi@32e00000 { + compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; + reg = <0x32e00000 0x2000>; + interrupts = ; + interface = <2 0 2>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + no-reset-control; + power-domains = <&mediamix_pd>; + isi_chain = <&isi_chain_buf>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + + m2m_device{ + compatible = "imx-isi-m2m"; + status = "disabled"; + }; + }; + + isi_1: isi@32e02000 { + compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; + reg = <0x32e02000 0x2000>; + interrupts = ; + interface = <3 0 2>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + no-reset-control; + power-domains = <&mediamix_pd>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isp_0: isp@32e10000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e10000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + power-domains = <&ispdwp_pd>; + id = <0>; + gpr = <&mediamix_blk_ctl>; + status = "disabled"; + }; + + isp_1: isp@32e20000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e20000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + power-domains = <&ispdwp_pd>; + id = <1>; + gpr = <&mediamix_blk_ctl>; + status = "disabled"; + }; + + /* FIXME: it's just for reference, should be refined later. */ + dewarp: dwe@32e30000 { + compatible = "fsl,imx8mp-dwe"; + reg = <0x32e30000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + power-domains = <&ispdwp_pd>; + id = <0>; + status = "disabled"; + }; + + mipi_csi_0: csi@32e40000 { + compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; + reg = <0x32e40000 0x10000>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "mipi_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + bus-width = <4>; + csi-gpr = <&mediamix_gasket0>; + gpr = <&mediamix_blk_ctl>; + no-reset-control; + power-domains = <&mipi_phy1_pd>; + status = "disabled"; + }; + + mipi_csi_1: csi@32e50000 { + compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; + reg = <0x32e50000 0x10000>; + interrupts = ; + clock-frequency = <266000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "mipi_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; + bus-width = <4>; + csi-gpr = <&mediamix_gasket1>; + gpr = <&mediamix_blk_ctl>; + no-reset-control; + power-domains = <&mipi_phy2_pd>; + status = "disabled"; + }; + }; + }; + }; + + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mp-pcie-phy"; + reg = <0x0 0x32f00000 0x0 0x10000>; + clocks = <&clk IMX8MP_CLK_DUMMY>; + clock-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + + hsio_mix: hsio-mix@32f10000 { + compatible = "fsl,imx8mp-hsio-mix"; + reg = <0x0 0x32f10000 0x0 0x8>; + }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0 0x33000000 0 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8MP_CLK_NAND_ROOT>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pcie: pcie@33800000 { + compatible = "fsl,imx8mp-pcie", "snps,dw-pcie"; + reg = <0x0 0x33800000 0x0 0x400000>, + <0x0 0x1ff00000 0x0 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <3>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIEPHY_PERST>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + fsl,imx8mp-hsio-mix = <&hsio_mix>; + status = "disabled"; + }; + + pcie_ep: pcie_ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x0 0x33800000 0x0 0x000400000>, + <0x0 0x18000000 0x0 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIEPHY_PERST>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + fsl,imx8mp-hsio-mix = <&hsio_mix>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + + gpu_3d: gpu3d@38000000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x38000000 0x0 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_DIV>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "shader", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE_SRC>, + <&clk IMX8MP_CLK_GPU3D_SHADER_SRC>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <1000000000>, + <800000000>, <400000000>; + power-domains = <&gpu3d_pd>; + status = "disabled"; + }; + + gpu_2d: gpu2d@38008000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x38008000 0x0 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_SRC>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; + power-domains = <&gpu2d_pd>; + status = "disabled"; + }; + + usb3_phy0: usb-phy@381f0040 { + compatible = "fsl,imx8mp-usb-phy"; + reg = <0 0x381f0040 0 0x40>; + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_0: usb@32f10100 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0 0x32f10100 0 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "suspend"; + interrupts = ; + power-domains = <&hsiomix_pd>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_dwc3_0: dwc3@38100000 { + compatible = "snps,dwc3"; + reg = <0 0x38100000 0 0x10000>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_USB_CORE_REF>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = ; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u2-freeclk-exists-quirk; + status = "disabled"; + }; + + }; + + usb3_phy1: usb-phy@382f0040 { + compatible = "fsl,imx8mp-usb-phy"; + reg = <0 0x382f0040 0 0x40>; + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_1: usb@32f10108 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0 0x32f10108 0 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "suspend"; + interrupts = ; + power-domains = <&hsiomix_pd>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_dwc3_1: dwc3@38200000 { + compatible = "snps,dwc3"; + reg = <0 0x38200000 0 0x10000>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_USB_CORE_REF>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = ; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u2-freeclk-exists-quirk; + status = "disabled"; + }; + }; + + vpu_g1: vpu_g1@38300000 { + compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; + reg = <0x0 0x38300000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <800000000>; + power-domains = <&vpu_g1_pd>; + status = "disabled"; + }; + + vpu_g2: vpu_g2@38310000 { + compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; + reg = <0x0 0x38310000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <700000000>, <800000000>, <700000000>; + power-domains = <&vpu_g2_pd>; + status = "disabled"; + }; + + vpu_vc8000e: vpu_vc8000e@38320000 { + compatible = "nxp,imx8mp-hantro-vc8000e"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_vc8000e"; + interrupts = ; + interrupt-names = "irq_hantro_vc8000e"; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro_vc8000e", "clk_hantro_vc8000e_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <800000000>; + power-domains = <&vpu_h1_pd>; + status = "disabled"; + }; + + ml_vipsi: vipsi@38500000 { + compatible = "fsl,imx8-gpu", "fsl,imx8-vipsi"; + reg = <0x0 0x38500000 0x0 0x20000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + clock-names = "core", "shader", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_ML_SRC>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; + power-domains = <&mlmix_pd>; + status = "disabled"; + }; + + dsp: dsp@3b6e8000 { + compatible = "fsl,imx8mp-dsp-v1"; + memory-region = <&dsp_reserved>; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; + clock-names = "ocram", "core", "debug", "mu2"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&audiomix_pd>; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mu2 2 0>, + <&mu2 2 1>, + <&mu2 3 0>, + <&mu2 3 1>; + status = "disabled"; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif1_disp>, + <&lcdif2_disp>, + <&lcdif3_disp>; + }; + + imx_ion: imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + mix_gpu_ml: mix_gpu_ml { + compatible = "fsl,imx8mp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d>, <&ml_vipsi>, <&gpu_2d>; + reg = <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8mq-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; + }; + + i2c_rpbus_3: i2c-rpbus-3 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + etm0: etm@28440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28440000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_0>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + etm1: etm@28540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28540000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_1>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + etm2: etm@28640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28640000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_2>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port2>; + }; + }; + }; + }; + + etm3: etm@28740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28740000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_3>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port3>; + }; + }; + }; + }; + + funnel0: funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + + }; + + funnel1: funnel@28c03000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x28c03000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + /* M7 input */ + }; + }; + + port@2 { + reg = <2>; + hugo_funnel_in_port2: endpoint { + /* DSP input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@28c04000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x28c04000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr@28c06000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x28c06000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; +}; diff --git a/vvcam_ry/v4l2/dw200_driver.c b/vvcam_ry/v4l2/dw200_driver.c new file mode 100755 index 0000000..89b6082 --- /dev/null +++ b/vvcam_ry/v4l2/dw200_driver.c @@ -0,0 +1,256 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dw200_driver.h" +#include "dw200_ioctl.h" + +#define DEVICE_NAME "vvcam-dw200" + +int dw200_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, 2, NULL); +} + +int dw200_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +#ifdef CONFIG_COMPAT +static long dw200_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct dw200_device *dw200_dev = v4l2_get_subdevdata(sd); + + return dw200_priv_ioctl(&dw200_dev->ic_dev, cmd, arg); +} + +long dw200_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return dw200_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long dw200_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct dw200_device *dw200_dev = v4l2_get_subdevdata(sd); + + return dw200_priv_ioctl(&^dw200_dev->ic_dev, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +int dw200_set_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static struct v4l2_subdev_core_ops dw200_v4l2_subdev_core_ops = { + .ioctl = dw200_ioctl, + .subscribe_event = dw200_subscribe_event, + .unsubscribe_event = dw200_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops dw200_v4l2_subdev_video_ops = { + .s_stream = dw200_set_stream, +}; + +static struct v4l2_subdev_ops dw200_v4l2_subdev_ops = { + .core = &dw200_v4l2_subdev_core_ops, + .video = &dw200_v4l2_subdev_video_ops, +}; + +int dw200_hw_probe(struct platform_device *pdev) +{ + struct dw200_device *dw200_dev; + int rc = 0; + + pr_info("enter %s\n", __func__); + dw200_dev = kzalloc(sizeof(struct dw200_device), GFP_KERNEL); + if (!dw200_dev) { + rc = -ENOMEM; + goto end; + } + + v4l2_subdev_init(&dw200_dev->sd, &dw200_v4l2_subdev_ops); + snprintf(dw200_dev->sd.name, sizeof(dw200_dev->sd.name), DEVICE_NAME); + dw200_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dw200_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + dw200_dev->sd.owner = THIS_MODULE; + v4l2_set_subdevdata(&dw200_dev->sd, dw200_dev); + dw200_dev->vd = kzalloc(sizeof(*dw200_dev->vd), GFP_KERNEL); + if (WARN_ON(!dw200_dev->vd)) { + rc = -ENOMEM; + goto end; + } + + rc = v4l2_device_register(&(pdev->dev), dw200_dev->vd); + if (WARN_ON(rc < 0)) + goto end; + + rc = v4l2_device_register_subdev(dw200_dev->vd, &dw200_dev->sd); + if (rc) { + pr_err("failed to register subdev %d\n", rc); + goto end; + } + dw200_dev->ic_dev.dwe_base = ioremap(DWE_REG_BASE, DWE_REG_SIZE); + dw200_dev->ic_dev.vse_base = ioremap(VSE_REG_BASE, VSE_REG_SIZE); +#ifdef DWE_REG_RESET + dw200_dev->ic_dev.dwe_reset = ioremap(DWE_REG_RESET, 4); +#endif +#ifdef VSE_REG_RESET + dw200_dev->ic_dev.vse_reset = ioremap(VSE_REG_RESET, 4); +#endif + pr_info("dw200 ioremap addr: 0x%08x 0x%08x %p", DWE_REG_BASE, + DWE_REG_SIZE, dw200_dev->ic_dev.dwe_base); + platform_set_drvdata(pdev, dw200_dev); + rc = v4l2_device_register_subdev_nodes(dw200_dev->vd); + return 0; +end: + return rc; +} + +int dw200_hw_remove(struct platform_device *pdev) +{ + struct dw200_device *dw200 = platform_get_drvdata(pdev); + + pr_info("enter %s\n", __func__); + if (!dw200) + return -EINVAL; + + v4l2_device_unregister_subdev(&dw200->sd); + v4l2_device_disconnect(dw200->vd); + v4l2_device_put(dw200->vd); + + iounmap(dw200->ic_dev.dwe_base); + iounmap(dw200->ic_dev.vse_base); +#ifdef DWE_REG_RESET + iounmap(dw200->ic_dev.dwe_reset); +#endif +#ifdef VSE_REG_RESET + iounmap(dw200->ic_dev.vse_reset); +#endif + kzfree(dw200); + + return 0; +} + +static struct platform_driver viv_dw200_driver = { + .probe = dw200_hw_probe, + .remove = dw200_hw_remove, + .driver = { + .name = DEVICE_NAME, + .owner = THIS_MODULE, + } +}; + +static void dw200_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +static struct platform_device viv_dw200_pdev = { + .name = DEVICE_NAME, + .dev.release = dw200_pdev_release, +}; + +static int __init viv_dw200_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + ret = platform_device_register(&viv_dw200_pdev); + if (ret) { + pr_err("register platform device failed.\n"); + return ret; + } + + ret = platform_driver_register(&viv_dw200_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + platform_device_unregister(&viv_dw200_pdev); + return ret; + } + return ret; +} + +static void __exit viv_dw200_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_dw200_driver); + platform_device_unregister(&viv_dw200_pdev); +} + +module_init(viv_dw200_init_module); +module_exit(viv_dw200_exit_module); + +MODULE_AUTHOR("zhiye.yin@verisilicon.com"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Dewarp200"); +MODULE_VERSION("1.0"); diff --git a/vvcam_ry/v4l2/dw200_driver.h b/vvcam_ry/v4l2/dw200_driver.h new file mode 100755 index 0000000..6384908 --- /dev/null +++ b/vvcam_ry/v4l2/dw200_driver.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DW200_DRIVER_H_ +#define _DW200_DRIVER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dw200_subdev.h" + +struct dw200_device { + /* Driver private data */ + struct v4l2_subdev sd; + struct v4l2_device *vd; + struct dw200_subdev ic_dev; +}; + +#endif // _DW200_DRIVER_H_ diff --git a/vvcam_ry/v4l2/dwe_devcore.c b/vvcam_ry/v4l2/dwe_devcore.c new file mode 100755 index 0000000..93e2046 --- /dev/null +++ b/vvcam_ry/v4l2/dwe_devcore.c @@ -0,0 +1,228 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include "dwe_driver.h" +#include "dwe_ioctl.h" + +LIST_HEAD(devcore_list); +static DEFINE_SPINLOCK(devcore_list_lock); + +long dwe_devcore_ioctl(struct dwe_device *dwe, unsigned int cmd, void *args) +{ + struct dwe_ic_dev *dev = &dwe->core->ic_dev; + int which; + long ret = 0; + + switch (cmd) { + case DWEIOC_RESET: + break; + case DWEIOC_S_PARAMS: + which = dev->which[dwe->id]; /*just set the current one*/ + viv_check_retval(copy_from_user(&dev->info[dwe->id][which], + args, sizeof(dev->info[dwe->id][which]))); + break; + case DWEIOC_START: + if (dwe->state & STATE_DRIVER_STARTED) + break; + mutex_lock(&dwe->core->mutex); + if (dwe->core->state == 0) { + ret = dwe_priv_ioctl(&dwe->core->ic_dev, + DWEIOC_RESET, NULL); + ret |= dwe_priv_ioctl(&dwe->core->ic_dev, cmd, args); + } + dwe->core->state++; + mutex_unlock(&dwe->core->mutex); + dwe->state |= STATE_DRIVER_STARTED; + break; + case DWEIOC_STOP: + if (!(dwe->state & STATE_DRIVER_STARTED)) + break; + dwe->state &= ~STATE_DRIVER_STARTED; + mutex_lock(&dwe->core->mutex); + dwe->core->state--; + if (dwe->core->state == 0) + ret = dwe_priv_ioctl(&dwe->core->ic_dev, cmd, args); + mutex_unlock(&dwe->core->mutex); + break; + case DWEIOC_SET_LUT: { + struct lut_info info; + + viv_check_retval(copy_from_user(&info, args, sizeof(info))); + if (info.port < MAX_CFG_NUM) + dev->dist_map[dwe->id][info.port] = info.addr; + else + pr_err("map num exceeds the max cfg num.\n"); + break; + } + case VIDIOC_QUERYCAP: { + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "viv_dewarp100"); + cap->bus_info[0] = (__u8)dwe->id; + break; + } + default: + return dwe_priv_ioctl(&dwe->core->ic_dev, cmd, args); + } + return ret; +} + +static int dwe_core_match(struct dwe_devcore *core, struct resource *res) +{ + return core && res && core->start == res->start && + core->end == res->end; +} + +static int dwe_core_get_index(struct dwe_ic_dev *dev, struct vb2_dc_buf *buf) +{ + struct dwe_devcore *core = + container_of(dev, struct dwe_devcore, ic_dev); + int i; + + for (i = 0; i < MAX_DWE_NUM; ++i) + if (core->src_pads[i] == buf->pad) + return i; + return -1; +} + +struct dwe_devcore *dwe_devcore_init(struct dwe_device *dwe, + struct resource *res) +{ + struct dwe_devcore *core, *found = NULL; + unsigned long flags; + int rc; + + spin_lock_irqsave(&devcore_list_lock, flags); + if (!list_empty(&devcore_list)) { + list_for_each_entry(core, &devcore_list, entry) { + if (core->match && core->match(core, res)) { + found = core; + break; + } + } + } + spin_unlock_irqrestore(&devcore_list_lock, flags); + + if (found) { + found->src_pads[dwe->id] = &dwe->pads[DWE_PAD_SINK]; + found->ic_dev.src_bctx[dwe->id] = &dwe->bctx[DWE_PAD_SOURCE]; + found->ic_dev.state[dwe->id] = &dwe->state; + refcount_inc(&found->refcount); + return found; + } + + core = kzalloc(sizeof(struct dwe_devcore), GFP_KERNEL); + + if (!core) + return NULL; + + core->ic_dev.base = devm_ioremap_resource(dwe->sd.dev, res); + if (IS_ERR(core->ic_dev.base)) { + pr_err("failed to get ioremap resource.\n"); + goto end; + } + core->start = res->start; + core->end = res->end; + +#ifdef DWE_REG_RESET + core->ic_dev.reset = ioremap(DWE_REG_RESET, 4); +#endif + pr_debug("dwe ioremap addr: %llx\n", (u64)core->ic_dev.base); + + vvbuf_ctx_init(&core->bctx[DWE_PAD_SINK]); + core->ic_dev.sink_bctx = &core->bctx[DWE_PAD_SINK]; + + core->irq = dwe->irq; + pr_debug("request_irq num:%d, rc:%d\n", dwe->irq, rc); + + spin_lock_init(&core->ic_dev.irqlock); + + core->match = dwe_core_match; + core->src_pads[dwe->id] = &dwe->pads[DWE_PAD_SINK]; + core->ic_dev.src_bctx[dwe->id] = &dwe->bctx[DWE_PAD_SOURCE]; + core->ic_dev.state[dwe->id] = &dwe->state; + core->ic_dev.get_index = dwe_core_get_index; + + mutex_init(&core->mutex); + refcount_set(&core->refcount, 1); + + spin_lock_irqsave(&devcore_list_lock, flags); + list_add_tail(&core->entry, &devcore_list); + spin_unlock_irqrestore(&devcore_list_lock, flags); + + return core; +end: + kfree(core); + return NULL; +} + +void dwe_devcore_deinit(struct dwe_device *dwe) +{ + struct dwe_devcore *core = dwe->core; + unsigned long flags; + + if (!core) + return; + + if (refcount_dec_and_test(&core->refcount)) { + spin_lock_irqsave(&devcore_list_lock, flags); + list_del(&core->entry); + spin_unlock_irqrestore(&devcore_list_lock, flags); + vvbuf_ctx_deinit(&core->bctx[DWE_PAD_SINK]); + +#ifdef DWE_REG_RESET + iounmap(core->ic_dev.reset); +#endif + mutex_destroy(&core->mutex); + kfree(core); + } +} diff --git a/vvcam_ry/v4l2/dwe_driver.c b/vvcam_ry/v4l2/dwe_driver.c new file mode 100755 index 0000000..482d941 --- /dev/null +++ b/vvcam_ry/v4l2/dwe_driver.c @@ -0,0 +1,365 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dwe_driver.h" +#include "dwe_ioctl.h" +#define DEVICE_NAME "vvcam-dwe" + +int dwe_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, 2, NULL); +} + +int dwe_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +#ifdef CONFIG_COMPAT +static long dwe_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd); + + return dwe_priv_ioctl(&dwe_dev->ic_dev, cmd, arg); +} + +long dwe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return dwe_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long dwe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd); + + return dwe_priv_ioctl(&dwe_dev->ic_dev, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +static int dwe_enable_clocks(struct dwe_device *dwe_dev) +{ + int ret; + + ret = clk_prepare_enable(dwe_dev->clk_core); + if (ret) + return ret; + + ret = clk_prepare_enable(dwe_dev->clk_axi); + if (ret) + goto disable_clk_core; + + ret = clk_prepare_enable(dwe_dev->clk_ahb); + if (ret) + goto disable_clk_axi; + + return 0; + +disable_clk_axi: + clk_disable_unprepare(dwe_dev->clk_axi); +disable_clk_core: + clk_disable_unprepare(dwe_dev->clk_core); + + return ret; +} + +static void dwe_disable_clocks(struct dwe_device *dwe_dev) +{ + clk_disable_unprepare(dwe_dev->clk_ahb); + clk_disable_unprepare(dwe_dev->clk_axi); + clk_disable_unprepare(dwe_dev->clk_core); +} + + +int dwe_set_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static struct v4l2_subdev_core_ops dwe_v4l2_subdev_core_ops = { + .ioctl = dwe_ioctl, + .subscribe_event = dwe_subscribe_event, + .unsubscribe_event = dwe_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops dwe_v4l2_subdev_video_ops = { + .s_stream = dwe_set_stream, +}; + +static struct v4l2_subdev_ops dwe_v4l2_subdev_ops = { + .core = &dwe_v4l2_subdev_core_ops, + .video = &dwe_v4l2_subdev_video_ops, +}; + +static int dwe_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pm_runtime_get_sync(sd->dev); + return 0; +} + +static int dwe_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pm_runtime_put_sync(sd->dev); + return 0; +} + +static struct v4l2_subdev_internal_ops dwe_internal_ops = { + .open = dwe_open, + .close = dwe_close, +}; + +int dwe_hw_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dwe_device *dwe_dev; + struct resource *mem_res; + int rc = 0; + + pr_info("enter %s\n", __func__); + dwe_dev = kzalloc(sizeof(struct dwe_device), GFP_KERNEL); + if (!dwe_dev) { + rc = -ENOMEM; + goto end; + } + +#if 0 // DO NOT set clock in FPGA version. lucz + dwe_dev->clk_core = devm_clk_get(dev, "core"); + if (IS_ERR(dwe_dev->clk_core)) { + rc = PTR_ERR(dwe_dev->clk_core); + dev_err(dev, "can't get core clock: %d\n", rc); + return rc; + } + + dwe_dev->clk_axi = devm_clk_get(dev, "axi"); + if (IS_ERR(dwe_dev->clk_axi)) { + rc = PTR_ERR(dwe_dev->clk_axi); + dev_err(dev, "can't get axi clock: %d\n", rc); + return rc; + } + + dwe_dev->clk_ahb = devm_clk_get(dev, "ahb"); + if (IS_ERR(dwe_dev->clk_ahb)) { + rc = PTR_ERR(dwe_dev->clk_ahb); + dev_err(dev, "can't get ahb clock: %d\n", rc); + return rc; + } +#endif + + dwe_dev->sd.internal_ops = &dwe_internal_ops; + + v4l2_subdev_init(&dwe_dev->sd, &dwe_v4l2_subdev_ops); + snprintf(dwe_dev->sd.name, sizeof(dwe_dev->sd.name), DEVICE_NAME); + dwe_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dwe_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + dwe_dev->sd.owner = THIS_MODULE; + dwe_dev->sd.dev = &pdev->dev; + v4l2_set_subdevdata(&dwe_dev->sd, dwe_dev); + dwe_dev->vd = kzalloc(sizeof(*dwe_dev->vd), GFP_KERNEL); + if (WARN_ON(!dwe_dev->vd)) { + rc = -ENOMEM; + goto end; + } + + rc = v4l2_device_register(&(pdev->dev), dwe_dev->vd); + if (WARN_ON(rc < 0)) + goto end; + + rc = v4l2_device_register_subdev(dwe_dev->vd, &dwe_dev->sd); + if (rc) { + pr_err("failed to register subdev %d\n", rc); + goto end; + } + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dwe_dev->ic_dev.base = devm_ioremap_resource(&pdev->dev, mem_res); + if (IS_ERR(dwe_dev->ic_dev.base)) { + pr_err("failed to get ioremap resource.\n"); + goto end; + } + +#ifdef DWE_REG_RESET + dwe_dev->ic_dev.reset = ioremap(DWE_REG_RESET, 4); +#endif + platform_set_drvdata(pdev, dwe_dev); + rc = v4l2_device_register_subdev_nodes(dwe_dev->vd); + pm_runtime_enable(&pdev->dev); + pr_info("vvcam dewarp driver probed\n"); + return 0; +end: + return rc; +} + +int dwe_hw_remove(struct platform_device *pdev) +{ + struct dwe_device *dwe = platform_get_drvdata(pdev); + + pr_info("enter %s\n", __func__); + + if (!dwe) + return -1; + pm_runtime_disable(&pdev->dev); + v4l2_device_unregister_subdev(&dwe->sd); + v4l2_device_disconnect(dwe->vd); + v4l2_device_put(dwe->vd); + +#ifdef DWE_REG_RESET + iounmap(dwe->ic_dev.reset); +#endif + kfree(dwe); + pr_info("vvcam dewarp driver removed\n"); + return 0; +} + +static int dwe_system_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev); +} + +static int dwe_system_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + + return 0; +} + +static int dwe_runtime_suspend(struct device *dev) +{ + struct dwe_device *dwe_dev = dev_get_drvdata(dev); + + dwe_disable_clocks(dwe_dev); + + return 0; +} + +static int dwe_runtime_resume(struct device *dev) +{ + struct dwe_device *dwe_dev = dev_get_drvdata(dev); + + dwe_enable_clocks(dwe_dev); + + return 0; +} + +static const struct dev_pm_ops dwe_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(dwe_system_suspend, dwe_system_resume) + SET_RUNTIME_PM_OPS(dwe_runtime_suspend, dwe_runtime_resume, NULL) +}; + +static const struct of_device_id dwe_of_match[] = { + {.compatible = DWE_COMPAT_NAME,}, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, dwe_of_match); + +static struct platform_driver viv_dwe_driver = { + .probe = dwe_hw_probe, + .remove = dwe_hw_remove, + .driver = { + .name = DWE_DEVICE_NAME, + .owner = THIS_MODULE, + .of_match_table = dwe_of_match, + .pm = &dwe_pm_ops, + } +}; + +static int __init viv_dwe_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + ret = platform_driver_register(&viv_dwe_driver); + if (ret) + pr_err("register platform driver failed.\n"); + + return ret; +} + +static void __exit viv_dwe_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_dwe_driver); +} + +module_init(viv_dwe_init_module); +module_exit(viv_dwe_exit_module); + +MODULE_AUTHOR("zhiye.yin@verisilicon.com"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Dewarp"); +MODULE_VERSION("1.0"); diff --git a/vvcam_ry/v4l2/dwe_driver.h b/vvcam_ry/v4l2/dwe_driver.h new file mode 100755 index 0000000..6927b80 --- /dev/null +++ b/vvcam_ry/v4l2/dwe_driver.h @@ -0,0 +1,101 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _DWE_DRIVER_H_ +#define _DWE_DRIVER_H_ + +#include "dwe_dev.h" +#include "video/vvbuf.h" + +#ifdef ENABLE_IRQ +struct dwe_devcore { + struct vvbuf_ctx bctx[DWE_PADS_NUM]; + struct dwe_ic_dev ic_dev; + struct media_pad *src_pads[MAX_DWE_NUM]; + struct mutex mutex; + int state; + refcount_t refcount; + resource_size_t start; + resource_size_t end; + int (*match)(struct dwe_devcore *core, struct resource *res); + int irq; + struct list_head entry; +}; +#endif + +struct dwe_device { + struct vvbuf_ctx bctx[DWE_PADS_NUM]; + /* Driver private data */ + struct v4l2_subdev sd; +#ifdef ENABLE_IRQ + struct dwe_devcore *core; + struct media_pad pads[DWE_PADS_NUM]; + int state; + int id; + int irq; +#else + struct v4l2_device *vd; + struct dwe_ic_dev ic_dev; +#endif + struct clk *clk_core; + struct clk *clk_axi; + struct clk *clk_ahb; + int refcnt; +}; + +#ifdef ENABLE_IRQ +struct dwe_devcore *dwe_devcore_init(struct dwe_device *dwe, + struct resource *res); +void dwe_devcore_deinit(struct dwe_device *dwe); +long dwe_devcore_ioctl(struct dwe_device *dwe, unsigned int cmd, void *args); +#endif +#endif /* _DWE_DRIVER_H_ */ diff --git a/vvcam_ry/v4l2/dwe_driver_of.c b/vvcam_ry/v4l2/dwe_driver_of.c new file mode 100755 index 0000000..5ed1e56 --- /dev/null +++ b/vvcam_ry/v4l2/dwe_driver_of.c @@ -0,0 +1,560 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include + +#include "dwe_driver.h" +#include "dwe_ioctl.h" + +#define DEWARP_NODE_NUM (2) + +static struct dwe_device *pdwe_dev[DEWARP_NODE_NUM] = {NULL}; + +int dwe_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, 2, NULL); +} + +int dwe_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +#ifdef CONFIG_COMPAT +static long dwe_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + return dwe_devcore_ioctl(v4l2_get_subdevdata(sd), cmd, arg); +} + +long dwe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return dwe_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long dwe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return dwe_devcore_ioctl(v4l2_get_subdevdata(sd), cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +static int dwe_enable_clocks(struct dwe_device *dwe_dev) +{ + int ret; + ret = clk_prepare_enable(dwe_dev->clk_core); + if (ret) + return ret; + + ret = clk_prepare_enable(dwe_dev->clk_axi); + if (ret) + goto disable_clk_core; + + ret = clk_prepare_enable(dwe_dev->clk_ahb); + if (ret) + goto disable_clk_axi; + + return 0; + +disable_clk_axi: + clk_disable_unprepare(dwe_dev->clk_axi); +disable_clk_core: + clk_disable_unprepare(dwe_dev->clk_core); + + return ret; +} + +static void dwe_disable_clocks(struct dwe_device *dwe_dev) +{ + clk_disable_unprepare(dwe_dev->clk_ahb); + clk_disable_unprepare(dwe_dev->clk_axi); + clk_disable_unprepare(dwe_dev->clk_core); +} + +int dwe_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd); + struct vvbuf_ctx *ctx; + struct media_pad *pad; + unsigned long flags; + int state; + + if (!enable) + dwe_dev->state &= ~STATE_STREAM_STARTED; + else + dwe_dev->state |= STATE_STREAM_STARTED; + + pad = &dwe_dev->pads[DWE_PAD_SINK]; + pad = media_entity_remote_pad(pad); + + if (pad && is_media_entity_v4l2_subdev(pad->entity)) { + sd = media_entity_to_v4l2_subdev(pad->entity); + v4l2_subdev_call(sd, video, s_stream, enable); + } + + if (!enable) { + mutex_lock(&dwe_dev->core->mutex); + state = dwe_dev->core->state; + mutex_unlock(&dwe_dev->core->mutex); + if (state <= 0) { + ctx = &dwe_dev->core->bctx[DWE_PAD_SINK]; + spin_lock_irqsave(&ctx->irqlock, flags); + if (!list_empty(&ctx->dmaqueue)) + list_del_init(&ctx->dmaqueue); + spin_unlock_irqrestore(&ctx->irqlock, flags); + } + + ctx = &dwe_dev->bctx[DWE_PAD_SOURCE]; + spin_lock_irqsave(&ctx->irqlock, flags); + if (!list_empty(&ctx->dmaqueue)) + list_del_init(&ctx->dmaqueue); + spin_unlock_irqrestore(&ctx->irqlock, flags); + } + return 0; +} + +static struct v4l2_subdev_core_ops dwe_v4l2_subdev_core_ops = { + .ioctl = dwe_ioctl, + .subscribe_event = dwe_subscribe_event, + .unsubscribe_event = dwe_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops dwe_v4l2_subdev_video_ops = { + .s_stream = dwe_set_stream, +}; + +static struct v4l2_subdev_ops dwe_v4l2_subdev_ops = { + .core = &dwe_v4l2_subdev_core_ops, + .video = &dwe_v4l2_subdev_video_ops, +}; + +static int dwe_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static const struct media_entity_operations dwe_media_ops = { + .link_setup = dwe_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +static void dwe_src_buf_notify(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf) +{ + struct v4l2_subdev *sd; + struct dwe_device *dwe; + unsigned long flags; + + if (unlikely(!ctx || !buf)) + return; + + sd = media_entity_to_v4l2_subdev(buf->pad->entity); + dwe = container_of(sd, struct dwe_device, sd); + + if (!dwe || !(dwe->state & STATE_STREAM_STARTED)) { + vvbuf_ready(ctx, buf->pad, buf); + return; + } + + ctx = &dwe->core->bctx[DWE_PAD_SINK]; + + spin_lock_irqsave(&ctx->irqlock, flags); + list_add_tail(&buf->irqlist, &ctx->dmaqueue); + spin_unlock_irqrestore(&ctx->irqlock, flags); + + dwe_on_buf_update(&dwe->core->ic_dev); +} + +static const struct vvbuf_ops dwe_src_buf_ops = { + .notify = dwe_src_buf_notify, +}; + +static void dwe_dst_buf_notify(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf) +{ + struct v4l2_subdev *sd; + struct dwe_device *dwe; + unsigned long flags; + + if (unlikely(!ctx || !buf)) + return; + + sd = media_entity_to_v4l2_subdev(buf->pad->entity); + dwe = container_of(sd, struct dwe_device, sd); + + spin_lock_irqsave(&ctx->irqlock, flags); + list_add_tail(&buf->irqlist, &ctx->dmaqueue); + spin_unlock_irqrestore(&ctx->irqlock, flags); + + if (dwe) + dwe_on_buf_update(&dwe->core->ic_dev); +} + +static const struct vvbuf_ops dwe_dst_buf_ops = { + .notify = dwe_dst_buf_notify, +}; + +static void fake_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +static struct platform_device fake_pdev = { + .name = "fsl,fake-imx8mp-dwe", + .id = 1, + .dev.release = fake_pdev_release, +}; + +static int dwe_fake_pdev_creat(void) +{ + return platform_device_register(&fake_pdev); +} + +static void dwe_fake_pdev_destory(void) +{ + platform_device_unregister(&fake_pdev); +} + +static int dwe_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pm_runtime_get_sync(pdwe_dev[0]->sd.dev); + + pdwe_dev[0]->refcnt++; + if (pdwe_dev[0]->refcnt == 1){ + msleep(1); + dwe_clear_interrupts(&pdwe_dev[0]->core->ic_dev); + if (devm_request_irq(pdwe_dev[0]->sd.dev, pdwe_dev[0]->irq, dwe_hw_isr, IRQF_SHARED, + dev_name(pdwe_dev[0]->sd.dev), &pdwe_dev[0]->core->ic_dev) != 0) { + pr_err("failed to request irq.\n"); + pdwe_dev[0]->refcnt = 0; + pm_runtime_put_sync(pdwe_dev[0]->sd.dev); + return -1; + } + } + return 0; +} + +static int dwe_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pdwe_dev[0]->refcnt--; + if (pdwe_dev[0]->refcnt < 0) { + pdwe_dev[0]->refcnt = 0; + return 0; + } + + if (pdwe_dev[0]->refcnt == 0) { + devm_free_irq(pdwe_dev[0]->sd.dev, pdwe_dev[0]->irq, &pdwe_dev[0]->core->ic_dev); + dwe_clear_interrupts(&pdwe_dev[0]->core->ic_dev); + msleep(5); + } + + pm_runtime_put(pdwe_dev[0]->sd.dev); + return 0; +} + +static struct v4l2_subdev_internal_ops dwe_internal_ops = { + .open = dwe_open, + .close = dwe_close, +}; + +int dwe_hw_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dwe_device *dwe_dev; + struct resource *mem_res; + int irq; + int rc, i, index; + int dev_id; + + pr_info("enter %s\n", __func__); + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem_res) { + pr_err("can't fetch device resource info\n"); + return -ENODEV; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + pr_err("failed to get irq number.\n"); + return -ENODEV; + } + + rc = dwe_fake_pdev_creat(); + if (rc < 0) { + pr_err("failed to creat fake pdev for dwe1.\n"); + goto dewarp_destory_fake_pdev; + } + + for (dev_id = 0; dev_id < DEWARP_NODE_NUM; dev_id++) { + pdwe_dev[dev_id] = + kzalloc(sizeof(struct dwe_device), GFP_KERNEL); + if (!pdwe_dev[dev_id]) { + if (dev_id == 0) + goto dewarp_destory_fake_pdev; + else { + dev_id = dev_id - 1; + goto dewarp_entity_pads_deinit; + } + + } + + dwe_dev = pdwe_dev[dev_id]; + dwe_dev->id = dev_id; +#if 0 // 暂时关闭clock相关的控制 + if (dev_id == 0){ + dwe_dev->clk_core = devm_clk_get(dev, "core"); + if (IS_ERR(dwe_dev->clk_core)) { + rc = PTR_ERR(dwe_dev->clk_core); + dev_err(dev, "can't get core clock: %d\n", rc); + return rc; + } + + dwe_dev->clk_axi = devm_clk_get(dev, "axi"); + if (IS_ERR(dwe_dev->clk_axi)) { + rc = PTR_ERR(dwe_dev->clk_axi); + dev_err(dev, "can't get axi clock: %d\n", rc); + return rc; + } + + dwe_dev->clk_ahb = devm_clk_get(dev, "ahb"); + if (IS_ERR(dwe_dev->clk_ahb)) { + rc = PTR_ERR(dwe_dev->clk_ahb); + dev_err(dev, "can't get ahb clock: %d\n", rc); + return rc; + } + } +#endif + dwe_dev->sd.internal_ops = &dwe_internal_ops; + v4l2_subdev_init(&dwe_dev->sd, &dwe_v4l2_subdev_ops); + snprintf(dwe_dev->sd.name, sizeof(dwe_dev->sd.name), + "%s.%d", DWE_DEVICE_NAME, dwe_dev->id); + dwe_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dwe_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + dwe_dev->sd.owner = THIS_MODULE; + + v4l2_set_subdevdata(&dwe_dev->sd, dwe_dev); + + if (dev_id == 0) + dwe_dev->sd.dev = &pdev->dev; + else + dwe_dev->sd.dev = &fake_pdev.dev; + pr_info("%s:%d dwe_dev->sd->name=%s, dev_name(dwe_dev->sd.dev)=%s\n", + __func__, __LINE__, + dwe_dev->sd.name, dev_name(dwe_dev->sd.dev)); + dwe_dev->sd.entity.name = dwe_dev->sd.name; + dwe_dev->sd.entity.obj_type = MEDIA_ENTITY_TYPE_V4L2_SUBDEV; + dwe_dev->sd.entity.function = MEDIA_ENT_F_IO_V4L; + dwe_dev->sd.entity.ops = &dwe_media_ops; + dwe_dev->pads[DWE_PAD_SINK].flags = + MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT; + dwe_dev->pads[DWE_PAD_SOURCE].flags = + MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT; + rc = media_entity_pads_init(&dwe_dev->sd.entity, + DWE_PADS_NUM, dwe_dev->pads); + if (rc < 0) + goto dewarp_entity_pads_deinit; + pr_info("%s:%d\n", __func__, __LINE__); + } + + for (dev_id = 0; dev_id < DEWARP_NODE_NUM; dev_id++) { + dwe_dev = pdwe_dev[dev_id]; + for (i = 0; i < DWE_PADS_NUM; ++i) + vvbuf_ctx_init(&dwe_dev->bctx[i]); + + dwe_dev->bctx[DWE_PAD_SINK].ops = &dwe_src_buf_ops; + dwe_dev->bctx[DWE_PAD_SOURCE].ops = &dwe_dst_buf_ops; + dwe_dev->irq = irq; + + dwe_dev->core = dwe_devcore_init(dwe_dev, mem_res); + dwe_dev->sd.fwnode = of_fwnode_handle(pdev->dev.of_node); + + rc = v4l2_async_register_subdev(&dwe_dev->sd); + if (rc < 0) + goto dewarp_core_deinit; + pr_info("%s:%d\n", __func__, __LINE__); + } + pm_runtime_enable(&pdev->dev); + pr_info("vvcam dewarp driver probed\n"); + return 0; + +dewarp_core_deinit: + dwe_devcore_deinit(pdwe_dev[0]); + for (index = 0; index <= dev_id; index++) { + dwe_dev = pdwe_dev[index]; + for (i = 0; i < DWE_PADS_NUM; i++) + vvbuf_ctx_deinit(&dwe_dev->bctx[i]); + } + dev_id = DEWARP_NODE_NUM - 1; + +dewarp_entity_pads_deinit: + for (index = 0; index <= dev_id; index++) { + dwe_dev = pdwe_dev[index]; + media_entity_cleanup(&dwe_dev->sd.entity); + kfree(dwe_dev); + } +dewarp_destory_fake_pdev: + dwe_fake_pdev_destory(); + return rc; +} + +int dwe_hw_remove(struct platform_device *pdev) +{ + struct dwe_device *dwe_dev; + int dev_id; + int i; + + pr_info("enter %s\n", __func__); + pm_runtime_disable(&pdev->dev); + dwe_devcore_deinit(pdwe_dev[0]); + + for (dev_id = 0; dev_id < DEWARP_NODE_NUM; dev_id++) { + dwe_dev = pdwe_dev[dev_id]; + for (i = 0; i < DWE_PADS_NUM; i++) + vvbuf_ctx_deinit(&dwe_dev->bctx[i]); + media_entity_cleanup(&dwe_dev->sd.entity); + v4l2_async_unregister_subdev(&dwe_dev->sd); + kfree(dwe_dev); + } + dwe_fake_pdev_destory(); + pr_info("vvcam dewarp driver removed\n"); + return 0; +} + +static int dwe_system_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev); +} + +static int dwe_system_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + + return 0; +} + +static int dwe_runtime_suspend(struct device *dev) +{ + struct dwe_device *dwe_dev = pdwe_dev[0]; + + dwe_disable_clocks(dwe_dev); + + return 0; +} + +static int dwe_runtime_resume(struct device *dev) +{ + struct dwe_device *dwe_dev = pdwe_dev[0]; + + dwe_enable_clocks(dwe_dev); + + return 0; +} + +static const struct dev_pm_ops dwe_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(dwe_system_suspend, dwe_system_resume) + SET_RUNTIME_PM_OPS(dwe_runtime_suspend, dwe_runtime_resume, NULL) +}; + +static const struct of_device_id dwe_of_match[] = { + {.compatible = DWE_COMPAT_NAME,}, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, dwe_of_match); + +static struct platform_driver viv_dwe_driver = { + .probe = dwe_hw_probe, + .remove = dwe_hw_remove, + .driver = { + .name = DWE_DEVICE_NAME, + .owner = THIS_MODULE, + .of_match_table = dwe_of_match, + .pm = &dwe_pm_ops, + } +}; + +static int __init viv_dwe_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + ret = platform_driver_register(&viv_dwe_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + return ret; +} + +static void __exit viv_dwe_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_dwe_driver); +} + +module_init(viv_dwe_init_module); +module_exit(viv_dwe_exit_module); + +MODULE_AUTHOR("zhiye.yin@verisilicon.com"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Dewarp"); +MODULE_VERSION("1.0"); diff --git a/vvcam_ry/v4l2/isp_driver.c b/vvcam_ry/v4l2/isp_driver.c new file mode 100755 index 0000000..1cf6010 --- /dev/null +++ b/vvcam_ry/v4l2/isp_driver.c @@ -0,0 +1,508 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "isp_driver.h" +#include "isp_ioctl.h" +#include "mrv_all_bits.h" +#include "viv_video_kevent.h" + +struct clk *clk_isp; + +extern MrvAllRegister_t *all_regs; + +#ifdef CONFIG_COMPAT +static long isp_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + return isp_priv_ioctl(&isp_dev->ic_dev, cmd, arg); +} + +long isp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return isp_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long isp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + return isp_priv_ioctl(&isp_dev->ic_dev, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +static int isp_enable_clocks(struct isp_device *isp_dev) +{ + int ret; + + ret = clk_prepare_enable(isp_dev->clk_core); + if (ret) + return ret; + + ret = clk_prepare_enable(isp_dev->clk_axi); + if (ret) + goto disable_clk_core; + + ret = clk_prepare_enable(isp_dev->clk_ahb); + if (ret) + goto disable_clk_axi; + + return 0; + +disable_clk_axi: + clk_disable_unprepare(isp_dev->clk_axi); +disable_clk_core: + clk_disable_unprepare(isp_dev->clk_core); + + return ret; +} + +static void isp_disable_clocks(struct isp_device *isp_dev) +{ + clk_disable_unprepare(isp_dev->clk_ahb); + clk_disable_unprepare(isp_dev->clk_axi); + clk_disable_unprepare(isp_dev->clk_core); +} + +int isp_set_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static void isp_post_event(struct isp_ic_dev *dev, void *data, size_t size) +{ + struct isp_device *isp_dev; + struct video_device *vdev; + struct v4l2_event event; + + if (!dev || !data || !size) + return; + + isp_dev = container_of(dev, struct isp_device, ic_dev); + vdev = isp_dev->sd.devnode; + if (!vdev) + return; + + memset(&event, 0, sizeof(event)); + memcpy(event.u.data, data, min_t(size_t, size, 64)); + event.type = VIV_VIDEO_ISPIRQ_TYPE; + v4l2_event_queue(vdev, &event); +} + +static int isp_subdev_subscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, struct v4l2_event_subscription *sub) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + if (sub->type != VIV_VIDEO_ISPIRQ_TYPE) + return -EINVAL; + + if (!isp_dev->ic_dev.post_event) + isp_dev->ic_dev.post_event = isp_post_event; + + return v4l2_event_subscribe(fh, sub, 8, NULL); +} + +static int isp_subdev_unsubscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, struct v4l2_event_subscription *sub) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + if (sub->type != VIV_VIDEO_ISPIRQ_TYPE) + return -EINVAL; + + if (isp_dev->ic_dev.post_event) + isp_dev->ic_dev.post_event = NULL; + + return v4l2_event_unsubscribe(fh, sub); +} + +static struct v4l2_subdev_core_ops isp_v4l2_subdev_core_ops = { + .ioctl = isp_ioctl, + .subscribe_event = isp_subdev_subscribe_event, + .unsubscribe_event = isp_subdev_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops isp_v4l2_subdev_video_ops = { + .s_stream = isp_set_stream, +}; + + +irqreturn_t isp_hw_isr_reg_update(int irq, void *data) +{ + u32 isp_mis, isp_ctrl; + + struct isp_irq_data irq_data; + struct isp_ic_dev *dev = (struct isp_ic_dev *)data; + + if (!dev) + return IRQ_HANDLED; + + isp_mis = isp_read_reg(dev, REG_ADDR(isp_mis)); + isp_write_reg(dev, REG_ADDR(isp_icr), isp_mis); + + + if (isp_mis) { + if (isp_mis & MRV_ISP_MIS_FRAME_MASK) { + if (dev->isp_update_flag & ISP_FLT_UPDATE) { + isp_s_flt(dev); + dev->isp_update_flag &= (~ISP_FLT_UPDATE); + } + + if (dev->gamma_out.changed) { + isp_s_gamma_out(dev); + } + + if(dev->update_gamma_en) { + isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl)); + REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, + dev->gamma_out.enableGamma); + isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl); + dev->update_gamma_en = false; + } + + } + + memset(&irq_data, 0, sizeof(irq_data)); + irq_data.val = isp_mis; + if (dev->post_event) + dev->post_event(dev, &irq_data, sizeof(irq_data)); + } + return IRQ_HANDLED; +} + +struct v4l2_subdev_ops isp_v4l2_subdev_ops = { + .core = &isp_v4l2_subdev_core_ops, + .video = &isp_v4l2_subdev_video_ops, +}; + +static int isp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pm_runtime_get_sync(sd->dev); + return 0; +} + +static int isp_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pm_runtime_put_sync(sd->dev); + return 0; +} + +static struct v4l2_subdev_internal_ops isp_internal_ops = { + .open = isp_open, + .close = isp_close, +}; + +int isp_hw_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct isp_device *isp_dev; + struct resource *mem_res; + int irq; + int rc; + struct device_node *mem_node; + + pr_info("enter %s\n", __func__); + isp_dev = kzalloc(sizeof(struct isp_device), GFP_KERNEL); + if (!isp_dev) { + goto end; + } + + rc = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node), + "id", &isp_dev->id); + if (rc) { + pr_info("isp device id not found, use the default.\n"); + isp_dev->id = 0; + } + isp_dev->ic_dev.id = isp_dev->id; + + isp_dev->clk_core = devm_clk_get(dev, "core"); + if (IS_ERR(isp_dev->clk_core)) { + rc = PTR_ERR(isp_dev->clk_core); + dev_err(dev, "can't get core clock: %d\n", rc); + return rc; + } + + isp_dev->clk_axi = devm_clk_get(dev, "axi"); + if (IS_ERR(isp_dev->clk_axi)) { + rc = PTR_ERR(isp_dev->clk_axi); + dev_err(dev, "can't get axi clock: %d\n", rc); + return rc; + } + + isp_dev->clk_ahb = devm_clk_get(dev, "ahb"); + if (IS_ERR(isp_dev->clk_ahb)) { + rc = PTR_ERR(isp_dev->clk_ahb); + dev_err(dev, "can't get ahb clock: %d\n", rc); + return rc; + } + + isp_dev->sd.internal_ops = &isp_internal_ops; + +#ifdef ISP8000NANO_V1802 + isp_dev->ic_dev.mix_gpr = syscon_regmap_lookup_by_phandle( + pdev->dev.of_node, "gpr"); + if (IS_ERR(isp_dev->ic_dev.mix_gpr)) { + pr_warn("failed to get mix gpr\n"); + isp_dev->ic_dev.mix_gpr = NULL; + return -ENOMEM; + } +#endif + mem_node = of_parse_phandle(pdev->dev.of_node, "memory-region", 0); + if (!mem_node) { + pr_err("No memory-region found\n"); + return -ENODEV; + } + + isp_dev->ic_dev.rmem = of_reserved_mem_lookup(mem_node); + if (!isp_dev->ic_dev.rmem) { + pr_err("of_reserved_mem_lookup() returned NULL\n"); + return -ENODEV; + } + + v4l2_subdev_init(&isp_dev->sd, &isp_v4l2_subdev_ops); + snprintf(isp_dev->sd.name, sizeof(isp_dev->sd.name), + "vvcam-isp.%d", isp_dev->ic_dev.id); + isp_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + isp_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + isp_dev->sd.owner = THIS_MODULE; + isp_dev->sd.dev = &pdev->dev; + v4l2_set_subdevdata(&isp_dev->sd, isp_dev); + isp_dev->vd = kzalloc(sizeof(*isp_dev->vd), GFP_KERNEL); + if (WARN_ON(!isp_dev->vd)) { + rc = -ENOMEM; + goto end; + } + + rc = v4l2_device_register(&(pdev->dev), isp_dev->vd); + if (WARN_ON(rc < 0)) + goto end; + + rc = v4l2_device_register_subdev(isp_dev->vd, &isp_dev->sd); + if (rc) { + pr_err("failed to register subdev %d\n", rc); + goto end; + } + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + isp_dev->ic_dev.base = devm_ioremap_resource(&pdev->dev, mem_res); + if (IS_ERR(isp_dev->ic_dev.base)) { + pr_err("failed to get ioremap resource.\n"); + goto end; + } + +#ifdef ISP_REG_RESET + isp_dev->ic_dev.reset = ioremap(ISP_REG_RESET, 4); +#endif + pr_debug("ioremap addr: %p", isp_dev->ic_dev.base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + pr_err("failed to get irq number.\n"); + goto end; + } + + rc = devm_request_irq(&pdev->dev, irq, isp_hw_isr_reg_update, IRQF_SHARED, + dev_name(&pdev->dev), &isp_dev->ic_dev); + if (rc) { + pr_err("failed to request irq.\n"); + irq = -1; + goto end; + } + isp_dev->irq = irq; + pr_debug("request_irq num:%d, rc:%d", irq, rc); + + platform_set_drvdata(pdev, isp_dev); + rc = v4l2_device_register_subdev_nodes(isp_dev->vd); + + pm_runtime_enable(&pdev->dev); + pr_info("vvcam isp driver registered\n"); + return 0; +end: + if (irq >= 0) + devm_free_irq(&pdev->dev, irq, &isp_dev->ic_dev); + kfree(isp_dev); + return 1; +} + +int isp_hw_remove(struct platform_device *pdev) +{ + struct isp_device *isp = platform_get_drvdata(pdev); + + pr_info("enter %s\n", __func__); + if (!isp) + return -1; + devm_free_irq(&pdev->dev, isp->irq, &isp->ic_dev); + v4l2_device_unregister_subdev(&isp->sd); + if (isp->vd) { + v4l2_device_disconnect(isp->vd); + v4l2_device_put(isp->vd); + } + + kfree(isp); + pm_runtime_disable(&pdev->dev); + return 0; +} + +static int isp_system_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev);; +} + +static int isp_system_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + + return 0; +} + +static int isp_runtime_suspend(struct device *dev) +{ + struct isp_device *isp_dev = dev_get_drvdata(dev); + + isp_disable_clocks(isp_dev); + + return 0; +} + +static int isp_runtime_resume(struct device *dev) +{ + struct isp_device *isp_dev = dev_get_drvdata(dev); + + isp_enable_clocks(isp_dev); + + return 0; +} + +static const struct dev_pm_ops isp_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(isp_system_suspend, isp_system_resume) + SET_RUNTIME_PM_OPS(isp_runtime_suspend, isp_runtime_resume, NULL) +}; + +static const struct of_device_id isp_of_match[] = { + {.compatible = "fsl,imx8mp-isp",}, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, isp_of_match); + +static struct platform_driver viv_isp_driver = { + .probe = isp_hw_probe, + .remove = isp_hw_remove, + .driver = { + .name = "vvcam-isp", + .owner = THIS_MODULE, + .of_match_table = isp_of_match, + .pm = &isp_pm_ops, + } +}; + +static int __init viv_isp_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&viv_isp_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit viv_isp_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_isp_driver); +} + +module_init(viv_isp_init_module); +module_exit(viv_isp_exit_module); + +MODULE_AUTHOR("Verisilicon ISP SW Team"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Verisilicon-ISP"); +MODULE_VERSION("1.0"); diff --git a/vvcam_ry/v4l2/isp_driver.h b/vvcam_ry/v4l2/isp_driver.h new file mode 100755 index 0000000..571fffd --- /dev/null +++ b/vvcam_ry/v4l2/isp_driver.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_DRIVER_H_ +#define _ISP_DRIVER_H_ + +#include "ic_dev.h" +#include "video/vvbuf.h" + +struct isp_device { + struct vvbuf_ctx bctx; + /* Driver private data */ + struct v4l2_subdev sd; +#ifndef ENABLE_IRQ + struct v4l2_device *vd; +#endif + struct isp_ic_dev ic_dev; + struct clk *clk_core; + struct clk *clk_axi; + struct clk *clk_ahb; + int refcnt; +#ifdef ENABLE_IRQ + struct media_pad pads[ISP_PADS_NUM]; + int state; +#endif + int irq; + + int id; +}; + +#endif /* _ISP_DRIVER_H_ */ diff --git a/vvcam_ry/v4l2/isp_driver_of.c b/vvcam_ry/v4l2/isp_driver_of.c new file mode 100755 index 0000000..1eea32f --- /dev/null +++ b/vvcam_ry/v4l2/isp_driver_of.c @@ -0,0 +1,631 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include + +#include "isp_driver.h" +#include "isp_ioctl.h" +#include "mrv_all_bits.h" +#include "viv_video_kevent.h" + +struct clk *clk_isp; + +extern MrvAllRegister_t *all_regs; + +#ifdef CONFIG_COMPAT +static long isp_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + return isp_priv_ioctl(&isp_dev->ic_dev, cmd, arg); +} + +long isp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return isp_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long isp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + return isp_priv_ioctl(&isp_dev->ic_dev, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +static int isp_enable_clocks(struct isp_device *isp_dev) +{ + int ret; + + ret = clk_prepare_enable(isp_dev->clk_core); + if (ret) + return ret; + + ret = clk_prepare_enable(isp_dev->clk_axi); + if (ret) + goto disable_clk_core; + + ret = clk_prepare_enable(isp_dev->clk_ahb); + if (ret) + goto disable_clk_axi; + + return 0; + +disable_clk_axi: + clk_disable_unprepare(isp_dev->clk_axi); +disable_clk_core: + clk_disable_unprepare(isp_dev->clk_core); + + return ret; +} + +static void isp_disable_clocks(struct isp_device *isp_dev) +{ + clk_disable_unprepare(isp_dev->clk_ahb); + clk_disable_unprepare(isp_dev->clk_axi); + clk_disable_unprepare(isp_dev->clk_core); +} + +int isp_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + struct vvbuf_ctx *ctx = &isp_dev->bctx; + struct vb2_dc_buf *buf; + + if (!enable) { + isp_dev->state &= ~STATE_STREAM_STARTED; + buf = vvbuf_try_dqbuf(ctx); + if (!buf) + return 0; + + do { + vvbuf_try_dqbuf_done(ctx, buf); + if (buf->flags) + kfree(buf); + } while ((buf = vvbuf_try_dqbuf(ctx))); + } else + isp_dev->state |= STATE_STREAM_STARTED; + return 0; +} + +static void isp_post_event(struct isp_ic_dev *dev, void *data, size_t size) +{ + struct isp_device *isp_dev; + struct video_device *vdev; + struct v4l2_event event; + + if (!dev || !data || !size) + return; + + isp_dev = container_of(dev, struct isp_device, ic_dev); + vdev = isp_dev->sd.devnode; + if (!vdev) + return; + + memset(&event, 0, sizeof(event)); + memcpy(event.u.data, data, min_t(size_t, size, 64)); + event.type = VIV_VIDEO_ISPIRQ_TYPE; + v4l2_event_queue(vdev, &event); +} + +static int isp_subdev_subscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, struct v4l2_event_subscription *sub) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + if (sub->type != VIV_VIDEO_ISPIRQ_TYPE) + return -EINVAL; + + if (!isp_dev->ic_dev.post_event) + isp_dev->ic_dev.post_event = isp_post_event; + + return v4l2_event_subscribe(fh, sub, 8, NULL); +} + +static int isp_subdev_unsubscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, struct v4l2_event_subscription *sub) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + if (sub->type != VIV_VIDEO_ISPIRQ_TYPE) + return -EINVAL; + + if (isp_dev->ic_dev.post_event) + isp_dev->ic_dev.post_event = NULL; + + return v4l2_event_unsubscribe(fh, sub); +} + +static struct v4l2_subdev_core_ops isp_v4l2_subdev_core_ops = { + .ioctl = isp_ioctl, + .subscribe_event = isp_subdev_subscribe_event, + .unsubscribe_event = isp_subdev_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops isp_v4l2_subdev_video_ops = { + .s_stream = isp_set_stream, +}; + +struct v4l2_subdev_ops isp_v4l2_subdev_ops = { + .core = &isp_v4l2_subdev_core_ops, + .video = &isp_v4l2_subdev_video_ops, +}; + +static int isp_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static const struct media_entity_operations isp_media_ops = { + .link_setup = isp_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +static void isp_buf_notify(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf) +{ + struct v4l2_subdev *sd; + struct isp_device *isp; + unsigned long flags; + + if (unlikely(!ctx || !buf)) + return; + + sd = media_entity_to_v4l2_subdev(buf->pad->entity); + isp = container_of(sd, struct isp_device, sd); + if (!(isp->state & STATE_STREAM_STARTED)) { + if (buf->flags) { + kfree(buf); + return; + } + } + + spin_lock_irqsave(&ctx->irqlock, flags); + list_add_tail(&buf->irqlist, &ctx->dmaqueue); + spin_unlock_irqrestore(&ctx->irqlock, flags); +} + +static const struct vvbuf_ops isp_buf_ops = { + .notify = isp_buf_notify, +}; + +static int isp_buf_alloc(struct isp_ic_dev *dev, struct isp_buffer_context *buf) +{ + struct isp_device *isp_dev; + struct vb2_dc_buf *buff, *b; + unsigned long flags; + + if (!dev || !buf) + return -EINVAL; + + isp_dev = container_of(dev, struct isp_device, ic_dev); + + buff = kzalloc(sizeof(struct vb2_dc_buf), GFP_KERNEL); + if (!buff) + return -ENOMEM; + + buff->pad = &isp_dev->pads[ISP_PAD_SOURCE]; + /*single plane*/ +#ifdef ISP_MP_34BIT + buff->dma = buf->addr_y << 2; +#else + buff->dma = buf->addr_y; +#endif + buff->flags = 1; + + spin_lock_irqsave(&isp_dev->bctx.irqlock, flags); + list_for_each_entry(b, &isp_dev->bctx.dmaqueue, irqlist) { + if (b->dma == buff->dma) { + list_del(&b->irqlist); + if (b->flags) + kfree(b); + break; + } + } + list_add_tail(&buff->irqlist, &isp_dev->bctx.dmaqueue); + spin_unlock_irqrestore(&isp_dev->bctx.irqlock, flags); + return 0; +} + +static int isp_buf_free(struct isp_ic_dev *dev, struct vb2_dc_buf *buf) +{ + struct isp_device *isp_dev; + struct vvbuf_ctx *ctx; + + if (buf && buf->flags) + kfree(buf); + + if (!dev) + return -EINVAL; + + isp_dev = container_of(dev, struct isp_device, ic_dev); + ctx = &isp_dev->bctx; + + buf = vvbuf_try_dqbuf(ctx); + if (!buf || !buf->flags) + return 0; + + do { + vvbuf_try_dqbuf_done(ctx, buf); + kfree(buf); + } while ((buf = vvbuf_try_dqbuf(ctx))); + return 0; +} + +static int isp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + pm_runtime_get_sync(sd->dev); + + isp_dev->refcnt++; + if (isp_dev->refcnt == 1) { + msleep(1); + isp_clear_interrupts(&isp_dev->ic_dev); + if (devm_request_irq(sd->dev, isp_dev->irq, isp_hw_isr, IRQF_SHARED, + dev_name(sd->dev), &isp_dev->ic_dev) != 0) { + pr_err("failed to request irq.\n"); + isp_dev->refcnt = 0; + pm_runtime_put_sync(sd->dev); + return -1; + } + } + return 0; +} + +static int isp_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct isp_device *isp_dev = v4l2_get_subdevdata(sd); + + isp_dev->refcnt--; + if (isp_dev->refcnt < 0) { + isp_dev->refcnt = 0; + return 0; + } + + if (isp_dev->refcnt == 0){ + devm_free_irq(sd->dev, isp_dev->irq, &isp_dev->ic_dev); + isp_priv_ioctl(&isp_dev->ic_dev, ISPIOC_RESET, NULL); + isp_clear_interrupts(&isp_dev->ic_dev); + msleep(5); + } + + pm_runtime_put(sd->dev); + return 0; +} + +static struct v4l2_subdev_internal_ops isp_internal_ops = { + .open = isp_open, + .close = isp_close, +}; + +int isp_hw_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct isp_device *isp_dev; + struct resource *mem_res; + int irq; + int rc; + struct device_node *mem_node; + + pr_info("enter %s\n", __func__); + isp_dev = kzalloc(sizeof(struct isp_device), GFP_KERNEL); + if (!isp_dev) + return -ENOMEM; + + pr_info("%s:%d\n", __func__, __LINE__); + + rc = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node), + "id", &isp_dev->id); + if (rc) { + pr_info("isp device id not found, use the default.\n"); + isp_dev->id = 0; + } + isp_dev->ic_dev.id = isp_dev->id; + pr_info("%s:%d\n", __func__, __LINE__); + +#if 0 + isp_dev->clk_core = devm_clk_get(dev, "core"); + if (IS_ERR(isp_dev->clk_core)) { + rc = PTR_ERR(isp_dev->clk_core); + dev_err(dev, "can't get core clock: %d\n", rc); + return rc; + } + + isp_dev->clk_axi = devm_clk_get(dev, "axi"); + if (IS_ERR(isp_dev->clk_axi)) { + rc = PTR_ERR(isp_dev->clk_axi); + dev_err(dev, "can't get axi clock: %d\n", rc); + return rc; + } + + isp_dev->clk_ahb = devm_clk_get(dev, "ahb"); + if (IS_ERR(isp_dev->clk_ahb)) { + rc = PTR_ERR(isp_dev->clk_ahb); + dev_err(dev, "can't get ahb clock: %d\n", rc); + return rc; + } +#endif + isp_dev->sd.internal_ops = &isp_internal_ops; + +#ifdef ISP8000NANO_V1802 + isp_dev->ic_dev.mix_gpr = syscon_regmap_lookup_by_phandle( + pdev->dev.of_node, "gpr"); + if (IS_ERR(isp_dev->ic_dev.mix_gpr)) { + pr_warn("failed to get mix gpr\n"); + isp_dev->ic_dev.mix_gpr = NULL; + return -ENOMEM; + } +#endif + mem_node = of_parse_phandle(pdev->dev.of_node, "memory-region", 0); + if (!mem_node) { + pr_err("No memory-region found\n"); + return -ENODEV; + } + pr_info("%s:%d\n", __func__, __LINE__); + + isp_dev->ic_dev.rmem = of_reserved_mem_lookup(mem_node); + if (!isp_dev->ic_dev.rmem) { + pr_err("of_reserved_mem_lookup() returned NULL\n"); + return -ENODEV; + } + pr_info("%s:%d\n", __func__, __LINE__); + + v4l2_subdev_init(&isp_dev->sd, &isp_v4l2_subdev_ops); + snprintf(isp_dev->sd.name, sizeof(isp_dev->sd.name), + "%s.%d", ISP_DEVICE_NAME, isp_dev->id); + isp_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + isp_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + isp_dev->sd.owner = THIS_MODULE; + v4l2_set_subdevdata(&isp_dev->sd, isp_dev); + isp_dev->sd.dev = &pdev->dev; + pr_info("%s:%d\n", __func__, __LINE__); + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + isp_dev->ic_dev.base = devm_ioremap_resource(&pdev->dev, mem_res); + if (IS_ERR(isp_dev->ic_dev.base)) { + pr_err("failed to get ioremap resource.\n"); + goto end; + } + pr_info("%s:%d\n", __func__, __LINE__); + +#ifdef ISP_REG_RESET + isp_dev->ic_dev.reset = ioremap(ISP_REG_RESET, 4); +#endif + pr_debug("ioremap addr: %p", isp_dev->ic_dev.base); + isp_dev->ic_dev.state = &isp_dev->state; + + vvbuf_ctx_init(&isp_dev->bctx); + isp_dev->bctx.ops = &isp_buf_ops; + isp_dev->ic_dev.bctx = &isp_dev->bctx; + + isp_dev->ic_dev.alloc = isp_buf_alloc; + isp_dev->ic_dev.free = isp_buf_free; + pr_info("%s:%d\n", __func__, __LINE__); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + pr_err("failed to get irq number.\n"); + goto end; + } + pr_info("%s:%d\n", __func__, __LINE__); + + isp_dev->irq = irq; + pr_debug("request_irq num:%d, rc:%d", irq, rc); + + platform_set_drvdata(pdev, isp_dev); + + isp_dev->sd.entity.name = isp_dev->sd.name; + isp_dev->sd.entity.obj_type = MEDIA_ENTITY_TYPE_V4L2_SUBDEV; + isp_dev->sd.entity.function = MEDIA_ENT_F_IO_V4L; + isp_dev->sd.entity.ops = &isp_media_ops; + isp_dev->pads[ISP_PAD_SOURCE].flags = + MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT; + rc = media_entity_pads_init(&isp_dev->sd.entity, + ISP_PADS_NUM, isp_dev->pads); + pr_info("%s:%d\n", __func__, __LINE__); + if (rc) + goto end; + pr_info("%s:%d\n", __func__, __LINE__); + isp_dev->sd.fwnode = of_fwnode_handle(pdev->dev.of_node); + rc = v4l2_async_register_subdev(&isp_dev->sd); + if (rc) + goto end; + pr_info("%s:%d\n", __func__, __LINE__); + pm_runtime_enable(&pdev->dev); + + pr_info("vvcam isp driver registered\n"); + return 0; +end: + pr_info("%s:%d\n", __func__, __LINE__); + vvbuf_ctx_deinit(&isp_dev->bctx); + kfree(isp_dev); + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + return rc; +} + +int isp_hw_remove(struct platform_device *pdev) +{ + struct isp_device *isp = platform_get_drvdata(pdev); + + pr_info("enter %s\n", __func__); + if (!isp) + return -1; + + + vvbuf_ctx_deinit(&isp->bctx); + media_entity_cleanup(&isp->sd.entity); + v4l2_async_unregister_subdev(&isp->sd); + + kfree(isp); + pm_runtime_disable(&pdev->dev); + pr_info("vvcam isp driver removed\n"); + return 0; +} + +static int isp_system_suspend(struct device *dev) +{ + struct platform_device *pdev; + struct isp_device *isp = NULL; + pdev = container_of(dev, struct platform_device, dev); + isp = platform_get_drvdata(pdev); + if(!isp){ + dev_err(dev, "isp suspend failed!\n"); + return -1; + } + + if(isp->ic_dev.streaming == true) { + isp_stop_stream(&isp->ic_dev); + } + + return pm_runtime_force_suspend(dev); +} + +static int isp_system_resume(struct device *dev) +{ + int ret; + struct platform_device *pdev; + struct isp_device *isp = NULL; + ret = pm_runtime_force_resume(dev); + if (ret < 0) { + dev_err(dev, "force resume %s failed!\n", dev_name(dev)); + return ret; + } + pdev = container_of(dev, struct platform_device, dev); + isp = platform_get_drvdata(pdev); + if(!isp){ + dev_err(dev, "isp resume failed!\n"); + return -1; + } + + if(isp->ic_dev.streaming == true) { + isp_start_stream(&isp->ic_dev, 1); + } + return 0; +} + +static int isp_runtime_suspend(struct device *dev) +{ + struct isp_device *isp_dev = dev_get_drvdata(dev); + + isp_disable_clocks(isp_dev); + + return 0; +} + +static int isp_runtime_resume(struct device *dev) +{ + struct isp_device *isp_dev = dev_get_drvdata(dev); + + isp_enable_clocks(isp_dev); + + return 0; +} + +static const struct dev_pm_ops isp_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(isp_system_suspend, isp_system_resume) + SET_RUNTIME_PM_OPS(isp_runtime_suspend, isp_runtime_resume, NULL) +}; + +static const struct of_device_id isp_of_match[] = { + {.compatible = ISP_COMPAT_NAME,}, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, isp_of_match); + +static struct platform_driver viv_isp_driver = { + .probe = isp_hw_probe, + .remove = isp_hw_remove, + .driver = { + .name = ISP_DEVICE_NAME, + .owner = THIS_MODULE, + .of_match_table = isp_of_match, + .pm = &isp_pm_ops, + } +}; + +static int __init viv_isp_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + + ret = platform_driver_register(&viv_isp_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + return ret; + } + + return ret; +} + +static void __exit viv_isp_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_isp_driver); +} + +module_init(viv_isp_init_module); +module_exit(viv_isp_exit_module); + +MODULE_AUTHOR("Verisilicon ISP SW Team"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Verisilicon-ISP"); +MODULE_VERSION("1.0"); diff --git a/vvcam_ry/v4l2/script/insmod.sh b/vvcam_ry/v4l2/script/insmod.sh new file mode 100755 index 0000000..1ce60ca --- /dev/null +++ b/vvcam_ry/v4l2/script/insmod.sh @@ -0,0 +1,9 @@ +#!/bin/bash +set -x +cd /bsp/isp/ko +insmod vvcam-video.ko +insmod ov2775.ko +insmod vvcam-csis.ko +insmod vvcam-dwe.ko +insmod vvcam-isp.ko +lsmod diff --git a/vvcam_ry/v4l2/sensor/Makefile b/vvcam_ry/v4l2/sensor/Makefile new file mode 100755 index 0000000..416a895 --- /dev/null +++ b/vvcam_ry/v4l2/sensor/Makefile @@ -0,0 +1,5 @@ +obj-m += ov2775/ +#obj-m += os08a20/ +#obj-m += camera-proxy-driver/ + + diff --git a/vvcam_ry/v4l2/sensor/camera-proxy-driver/COPYING b/vvcam_ry/v4l2/sensor/camera-proxy-driver/COPYING new file mode 100755 index 0000000..29676c9 --- /dev/null +++ b/vvcam_ry/v4l2/sensor/camera-proxy-driver/COPYING @@ -0,0 +1,132 @@ + +GNU GENERAL PUBLIC LICENSE + +Version 2, June 1991 + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. +Preamble + +The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation`s software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. + +To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. + +For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. + +We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. + +Also, for each author`s protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors` reputations. + +Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone`s free use or not licensed at all. + +The precise terms and conditions for copying, distribution and modification follow. + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + +0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. + +1. You may copy and distribute verbatim copies of the Program`s source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. + +You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. + +2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: + +a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. +b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. +c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) +These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. + +3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: + +a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, +b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, +c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) +The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. + +If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. + +4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. + +5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. + +6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients` exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. + +7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. + +This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. + +8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. + +9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. + +10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. + +NO WARRANTY + +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs + +If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. + +one line to give the program`s name and an idea of what it does. +Copyright (C) yyyy name of author + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this when it starts in an interactive mode: + +Gnomovision version 69, Copyright (C) year name of author +Gnomovision comes with ABSOLUTELY NO WARRANTY; for details +type `show w`. This is free software, and you are welcome +to redistribute it under certain conditions; type `show c` +for details. +The hypothetical commands `show w` and `show c` should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w` and `show c`; they could even be mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: + +Yoyodyne, Inc., hereby disclaims all copyright +interest in the program `Gnomovision` +(which makes passes at compilers) written +by James Hacker. + +signature of Ty Coon, 1 April 1989 +Ty Coon, President of Vice +This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. + diff --git a/vvcam_ry/v4l2/sensor/camera-proxy-driver/Makefile b/vvcam_ry/v4l2/sensor/camera-proxy-driver/Makefile new file mode 100755 index 0000000..a1dccb6 --- /dev/null +++ b/vvcam_ry/v4l2/sensor/camera-proxy-driver/Makefile @@ -0,0 +1,3 @@ +EXTRA_CFLAGS += -I$(PWD)/../common/ -DISP8000NANO_V1802 -O2 -Werror +basler-camera-driver-vvcam-objs += basler-camera-driver-vvcam/basler-camera-driver-vvcam.o +obj-m += basler-camera-driver-vvcam.o diff --git a/vvcam_ry/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.c b/vvcam_ry/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.c new file mode 100755 index 0000000..a98f453 --- /dev/null +++ b/vvcam_ry/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.c @@ -0,0 +1,1060 @@ +/* + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2018 NXP + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + */ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "basler-camera-driver-vvcam.h" +#include "vvsensor.h" + +/*global variable*/ +static struct register_access ra_tmp; + + +/* compact name as v4l2_capability->driver is limited to 16 characters */ +#ifdef CONFIG_BASLER_CAMERA_VVCAM +#define SENSOR_NAME "basler-vvcam" +#else +#define SENSOR_NAME "basler-camera" +#endif + + +/* + * ABRM register offsets + * + */ +#define ABRM_GENCP_VERSION 0x0 +#define ABRM_MANUFACTURER_NAME 0x4 +#define ABRM_MODEL_NAME 0x44 +#define ABRM_FAMILY_NAME 0x84 +#define ABRM_DEVICE_VERSION 0xC4 +#define ABRM_MANUFACTURER_INFO 0x104 +#define ABRM_SERIAL_NUMBER 0x144 +#define ABRM_USER_DEFINED_NAME 0x184 +#define ABRM_DEVICE_CAPABILITIES 0x1C4 + +/* + * ABRM register bits + * + */ +#define ABRM_DEVICE_CAPABILITIES_USER_DEFINED_NAMES_SUPPORT 0x1 +#define ABRM_DEVICE_CAPABILITIES_STRING_ENCODING 0x0f +#define ABRM_DEVICE_CAPABILITIES_FAMILY_NAME 0x100 + + +/* + * Maximum read i2c burst + * + * TODO: To be replace by a register call of SBRM + * + */ +#define I2C_MAXIMUM_READ_BURST 8 + + + +static int basler_read_register_chunk(struct i2c_client* client, __u8* buffer, __u8 buffer_size, __u16 register_address); + +static int basler_camera_s_ctrl(struct v4l2_ctrl *ctrl); +static int basler_camera_g_volatile_ctrl(struct v4l2_ctrl *ctrl); +static int basler_camera_validate(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr); +static void basler_camera_init(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr); +static bool basler_camera_equal(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr1, union v4l2_ctrl_ptr ptr2); + +struct basler_camera_dev { + struct i2c_client *i2c_client; + struct v4l2_device *v4l2_dev; + struct v4l2_subdev sd; + struct media_pad pad; + + /* lock to protect all members below */ + struct mutex lock; + + int power_count; + struct v4l2_ctrl_handler ctrl_handler; + + struct basler_device_information device_information; + + int csi; +}; + +/** + * basler_write_burst - issue a burst I2C message in master transmit mode + * @client: Handle to slave device + * @ra_p: Data structure that hold the register address and data that will be written to the slave + * + * Returns negative errno, or else the number of bytes written. + */ +static int basler_write_burst(struct i2c_client *client, + struct register_access *ra_p) +{ + int ret; + __u16 old_address; + + if (ra_p->data_size > sizeof(ra_p->data)){ + dev_err(&client->dev, "i2c burst array too big, max allowed %lu, got %d\n", sizeof(ra_p->data), ra_p->data_size); + return -EINVAL; + } + + old_address = ra_p->address; + ra_p->address = cpu_to_be16(ra_p->address); + + if (I2CREAD == (ra_p->command | I2CREAD)){ + ra_tmp.address = ra_p->address; + ra_tmp.data_size = ra_p->data_size; + old_address = ra_p->address; + return ra_p->data_size; + } + else if(I2CWRITE == (ra_p->command | I2CWRITE)){ + ret = i2c_master_send(client, (char *)ra_p, ra_p->data_size + sizeof(ra_p->address)); + + if(ret) + ra_p->data_size = ret; + + old_address = ra_p->address; + return ret; + } + else + return -EPERM; +} + +/** + * basler_read_burst - issue a burst I2C message in master transmit mode + * @client: Handle to slave device + * @ra_p: Data structure store the data read from slave + * + * Note: Before data can read use basler_write_burst with read command + * to send the register address + * + * Returns negative errno, or else the number of bytes written. + */ +static int basler_read_burst(struct i2c_client *client, + struct register_access *ra_p) +{ + int ret; + + ret = basler_read_register_chunk(client, ra_p->data, ra_tmp.data_size, + ra_tmp.address); + if (ret < 0) + ra_p->data_size = 0; + else + ra_p->data_size = ret; + + return ret; +} + + +static int basler_read_register_chunk(struct i2c_client* client, __u8* buffer, __u8 buffer_size, __u16 register_address) +{ + struct i2c_msg msgs[2] = {}; + int ret = 0; + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].buf = (__u8 *)®ister_address; + msgs[0].len = sizeof(register_address); + + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].buf = buffer; + msgs[1].len = buffer_size; + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret < 0) { + pr_err("i2c_transfer() failed: %d\n", ret); + return ret; + } + + if (ret != 2) { + pr_err("i2c_transfer() incomplete"); + return -EIO; + } + + return msgs[1].len; +} + +static int basler_read_register(struct i2c_client* client, __u8* buffer, __u8 buffer_size, __u16 register_address) +{ + int ret = 0; + __u8 l_read_bytes = 0; + + do { + __be16 l_register_address = cpu_to_be16(register_address + l_read_bytes); + + ret = basler_read_register_chunk(client, (__u8*) buffer + l_read_bytes, (__u8) min(I2C_MAXIMUM_READ_BURST, ((int)buffer_size - l_read_bytes)), l_register_address); + if (ret < 0) + { + pr_err("basler_read_register_chunk() failed: %d\n", ret); + return ret; + } + else if (ret == 0) + { + pr_err("basler_read_register_chunk() read 0 bytes.\n"); + return -EIO; + } + + l_read_bytes = l_read_bytes + ret; + } while (l_read_bytes < buffer_size); + + return l_read_bytes; +} + + +static int basler_retrieve_device_information(struct i2c_client* client, struct basler_device_information* bdi) +{ + int ret = 0; + __u64 deviceCapabilities = 0; + __be64 deviceCapabilitiesBe = 0; + __u32 gencpVersionBe = 0; + + bdi->_magic = BDI_MAGIC; + + ret = basler_read_register(client, (__u8*) &deviceCapabilitiesBe, sizeof(deviceCapabilitiesBe), ABRM_DEVICE_CAPABILITIES); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == sizeof(deviceCapabilitiesBe)) + { + deviceCapabilities = be64_to_cpu(deviceCapabilitiesBe); + pr_debug("deviceCapabilities = 0x%llx\n", deviceCapabilities); + pr_debug("String Encoding = 0x%llx\n", (deviceCapabilities & ABRM_DEVICE_CAPABILITIES_STRING_ENCODING) >> 4); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + ret = basler_read_register(client, (__u8*) &gencpVersionBe, sizeof(gencpVersionBe), ABRM_GENCP_VERSION); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == sizeof(gencpVersionBe)) + { + bdi->gencpVersion = be32_to_cpu(gencpVersionBe); + pr_debug("l_gencpVersion = %d.%d\n", (bdi->gencpVersion & 0xffff0000) >> 16, bdi->gencpVersion & 0xffff); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + ret = basler_read_register(client, bdi->deviceVersion, GENCP_STRING_BUFFER_SIZE, ABRM_DEVICE_VERSION); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->deviceVersion = %s\n", bdi->deviceVersion); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + ret = basler_read_register(client, bdi->serialNumber, GENCP_STRING_BUFFER_SIZE, ABRM_SERIAL_NUMBER); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->serialNumber = %s\n", bdi->serialNumber); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + ret = basler_read_register(client, bdi->manufacturerName, GENCP_STRING_BUFFER_SIZE, ABRM_MANUFACTURER_NAME); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->manufacturerName = %s\n", bdi->manufacturerName); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + ret = basler_read_register(client, bdi->modelName, GENCP_STRING_BUFFER_SIZE, ABRM_MODEL_NAME); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->modelName = %s\n", bdi->modelName); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + if (deviceCapabilities & ABRM_DEVICE_CAPABILITIES_FAMILY_NAME) + { + ret = basler_read_register(client, bdi->familyName, GENCP_STRING_BUFFER_SIZE, ABRM_FAMILY_NAME); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->familyName = %s\n", bdi->familyName); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + } + else + pr_notice("ABRM FamilyName not supported\n"); + + if (deviceCapabilities & ABRM_DEVICE_CAPABILITIES_USER_DEFINED_NAMES_SUPPORT) + { + ret = basler_read_register(client, bdi->userDefinedName, GENCP_STRING_BUFFER_SIZE, ABRM_USER_DEFINED_NAME); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->userDefinedName = %s\n", bdi->userDefinedName); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + } + else + pr_notice("ABRM UserDefinedName not supported\n"); + + ret = basler_read_register(client, bdi->manufacturerInfo, GENCP_STRING_BUFFER_SIZE, ABRM_MANUFACTURER_INFO); + if (ret < 0) + { + pr_err("basler_read_register() failed: %d\n", ret); + return ret; + } + else if (ret == GENCP_STRING_BUFFER_SIZE) + { + pr_debug("bdi->manufacturerInfo = %s\n", bdi->manufacturerInfo); + } + else { + pr_err("basler_read_register() not read full buffer = %d bytes\n", ret); + return -EIO; + } + + /* + * If the strings are in ASCII - print it. + */ + if (((deviceCapabilities & ABRM_DEVICE_CAPABILITIES_STRING_ENCODING) >> 4) == 0) + { + pr_info("ABRM: Manufacturer: %s, Model: %s, Device: %s, Serial: %s\n", bdi->manufacturerName, bdi->modelName, bdi->deviceVersion, bdi->serialNumber); + } + + return 0; +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4,19,0) // since 4.19.0-rc1 +static int basler_retrieve_csi_information(struct basler_camera_dev *sensor, + struct basler_csi_information* bci) +{ + struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = V4L2_MBUS_CSI2_DPHY }; + struct device *dev = &sensor->i2c_client->dev; + struct device_node *ep; + int ret; + + /* We need a function that searches for the device that holds + * the csi-2 bus information. For now we put the bus information + * also into the sensor endpoint itself. + */ + ep = of_graph_get_next_endpoint(dev->of_node, NULL); + if (!ep) { + dev_err(dev, "missing endpoint node\n"); + return -ENODEV; + } + + ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &bus_cfg); + of_node_put(ep); + if (ret) { + dev_err(dev, "failed to parse endpoint\n"); + return ret; + } + + if (bus_cfg.bus_type != V4L2_MBUS_CSI2_DPHY || + bus_cfg.bus.mipi_csi2.num_data_lanes == 0 || + bus_cfg.nr_of_link_frequencies == 0) { + dev_err(dev, "missing CSI-2 properties in endpoint\n"); + ret = -ENODATA; + } else { + int i; + bci->max_lane_frequency = bus_cfg.link_frequencies[0]; + bci->lane_count = bus_cfg.bus.mipi_csi2.num_data_lanes; + for (i = 0; i < bus_cfg.bus.mipi_csi2.num_data_lanes; ++i) { + bci->lane_assignment[i] = bus_cfg.bus.mipi_csi2.data_lanes[i]; + } + ret = 0; + } + return ret; +} +#else +static int basler_retrieve_csi_information(struct basler_camera_dev *sensor, + struct basler_csi_information* bci) +{ + struct device *dev = &sensor->i2c_client->dev; + struct v4l2_fwnode_endpoint *endpoint; + struct device_node *ep; + int ret; + + /* We need a function that searches for the device that holds + * the csi-2 bus information. For now we put the bus information + * also into the sensor endpoint itself. + */ + ep = of_graph_get_next_endpoint(dev->of_node, NULL); + if (!ep) { + dev_err(dev, "missing endpoint node\n"); + return -ENODEV; + } + + endpoint = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep)); + of_node_put(ep); + if (IS_ERR(endpoint)) { + dev_err(dev, "failed to parse endpoint\n"); + return PTR_ERR(endpoint); + } + + if (endpoint->bus_type != V4L2_MBUS_CSI2 || + endpoint->bus.mipi_csi2.num_data_lanes == 0 || + endpoint->nr_of_link_frequencies == 0) { + dev_err(dev, "missing CSI-2 properties in endpoint\n"); + ret = -ENODATA; + } else { + int i; + bci->max_lane_frequency = endpoint->link_frequencies[0]; + bci->lane_count = endpoint->bus.mipi_csi2.num_data_lanes; + for (i = 0; i < endpoint->bus.mipi_csi2.num_data_lanes; ++i) { + bci->lane_assignment[i] = endpoint->bus.mipi_csi2.data_lanes[i]; + } + ret = 0; + } + + v4l2_fwnode_endpoint_free(endpoint); + return ret; +} +#endif + +static inline struct basler_camera_dev *to_basler_camera_dev(struct v4l2_subdev *sd) +{ + return container_of(sd, struct basler_camera_dev, sd); +} + +static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) +{ + return &container_of(ctrl->handler, struct basler_camera_dev, + ctrl_handler)->sd; +} + +/** + * basler_camera_set_fmt - set format of the camera + * + * Note: Will be done in user space + * + * Returns always zero + */ +static int basler_camera_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + return 0; +} + +/** + * basler_camera_s_stream - start camera streaming + * + * Note: Will be done in user space + * + * Returns always zero + */ +static int basler_camera_s_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static int basler_camera_s_power(struct v4l2_subdev *sd, int on) +{ + struct basler_camera_dev *sensor = to_basler_camera_dev(sd); + + mutex_lock(&sensor->lock); + + /* Update the power count. */ + sensor->power_count += on ? 1 : -1; + WARN_ON(sensor->power_count < 0); + + mutex_unlock(&sensor->lock); + + return 0; +} + +static int basler_ioc_qcap(struct basler_camera_dev *sensor, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + strcpy((char *)cap->driver, SENSOR_NAME); + + sprintf((char *)cap->bus_info, "csi%d",sensor->csi); //bus_info[0:7]-csi number + if(sensor->i2c_client->adapter) + { + //bus_info[8]-i2c bus dev number + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = (__u8)sensor->i2c_client->adapter->nr; + } + else + { + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = 0xFF; + } + + + + + return 0; +} + +/* +Use USER_TO_KERNEL/KERNEL_TO_USER to fix "uaccess" exception on run time. +Also, use "copy_ret" to fix the build issue as below. +error: ignoring return value of function declared with 'warn_unused_result' attribute. +*/ + +#ifdef __KERNEL__ +#define USER_TO_KERNEL(TYPE) \ + do {\ + TYPE tmp; \ + unsigned long copy_ret; \ + arg = (void *)(&tmp); \ + copy_ret = copy_from_user(arg, arg_user, sizeof(TYPE));\ + } while (0) + +#define KERNEL_TO_USER(TYPE) \ + do {\ + unsigned long copy_ret; \ + copy_ret = copy_to_user(arg_user, arg, sizeof(TYPE));\ + } while (0) +#else +#define USER_TO_KERNEL(TYPE) +#define KERNEL_TO_USER(TYPE) +#endif + + +static long basler_camera_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg_user) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct basler_camera_dev * sensor = to_basler_camera_dev(sd); + void *arg = arg_user; + + int ret = -1; + + switch (cmd) { + case VIDIOC_QUERYCAP: + ret = basler_ioc_qcap(sensor, arg); + break; + + case BASLER_IOC_G_INTERFACE_VERSION: + { + USER_TO_KERNEL(__u32); + *((__u32*)arg) = (((__u32)BASLER_INTERFACE_VERSION_MAJOR) << 16) | BASLER_INTERFACE_VERSION_MINOR; + KERNEL_TO_USER(__u32); + ret = 0; + break; + } + + case BASLER_IOC_READ_REGISTER: + { + struct register_access *ra_p; + USER_TO_KERNEL(struct register_access); + ra_p = (struct register_access *)arg; + ret = basler_read_register(client, + ra_p->data, + ra_p->data_size, + ra_p->address); + if (ret < 0) + ra_p->data_size = 0; + else + ra_p->data_size = ret; + KERNEL_TO_USER(struct register_access); + } + break; + + case BASLER_IOC_WRITE_REGISTER: + { + struct register_access ra; + struct register_access * ra_p; + USER_TO_KERNEL(struct register_access); + ra_p = (struct register_access *)arg; + + memcpy (&ra, ra_p, sizeof(ra)); + ra.address = cpu_to_be16(ra_p->address); + + ret = i2c_master_send(client, (char *)&ra, ra.data_size + sizeof(ra.address)); + if(ret) { + ra_p->data_size = ret; + ret = 0; + } + else + ret = -EIO; + } + break; + + case BASLER_IOC_G_DEVICE_INFORMATION: + { + USER_TO_KERNEL(struct basler_device_information); + memcpy((struct basler_device_information *)arg, &sensor->device_information, sizeof(struct basler_device_information)); + KERNEL_TO_USER(struct basler_device_information); + ret = 0; + break; + } + + case BASLER_IOC_G_CSI_INFORMATION: + { + USER_TO_KERNEL(struct basler_csi_information); + ret = basler_retrieve_csi_information(sensor, (struct basler_csi_information*)arg); + KERNEL_TO_USER(struct basler_csi_information); + break; + } + + default: + break; + } + return ret; +} + +static const struct v4l2_subdev_core_ops basler_camera_core_ops = { + .s_power = basler_camera_s_power, + .ioctl = basler_camera_priv_ioctl, +}; + +static const struct v4l2_subdev_video_ops basler_camera_video_ops = { + .s_stream = basler_camera_s_stream, +}; + +static const struct v4l2_subdev_pad_ops basler_camera_pad_ops = { + .set_fmt = basler_camera_set_fmt, +}; + +static const struct v4l2_subdev_ops basler_camera_subdev_ops = { + .core = &basler_camera_core_ops, + .video = &basler_camera_video_ops, + .pad = &basler_camera_pad_ops, +}; + +static const struct v4l2_ctrl_ops basler_camera_ctrl_ops = { + .g_volatile_ctrl = basler_camera_g_volatile_ctrl, + .s_ctrl = basler_camera_s_ctrl, +}; + +static const struct v4l2_ctrl_type_ops basler_camera_ctrl_type_ops = { + .validate = basler_camera_validate, + .init = basler_camera_init, + .equal = basler_camera_equal, +}; + +/** + * basler_camera_validate + * + * Note: Not needed by access-register control + * + * Returns always zero + */ +static int basler_camera_validate(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr ) +{ + return 0; +} + +/** + * basler_camera_init + * + * Note: Not needed by access-register control + * + */ +static void basler_camera_init(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr ) +{ +} + +/** + * basler_camera_equal + * + * Note: Not needed by access-register control + * + * Returns always zero + */ +static bool basler_camera_equal(const struct v4l2_ctrl *ctrl, u32 idx, union v4l2_ctrl_ptr ptr1, union v4l2_ctrl_ptr ptr2 ) +{ + return 0; +} + +static const struct v4l2_ctrl_config ctrl_access_register = { + .ops = &basler_camera_ctrl_ops, + .type_ops = &basler_camera_ctrl_type_ops, + .id = V4L2_CID_BASLER_ACCESS_REGISTER, + .name = "basler-access-register", + .type = V4L2_CTRL_TYPE_U32+1, + .flags = V4L2_CTRL_FLAG_EXECUTE_ON_WRITE | V4L2_CTRL_FLAG_VOLATILE, + .step = 1, + .dims = {1}, + .elem_size = sizeof(struct register_access), +}; + +static const struct v4l2_ctrl_config ctrl_basler_device_information = { + .ops = &basler_camera_ctrl_ops, + .type_ops = &basler_camera_ctrl_type_ops, + .id = V4L2_CID_BASLER_DEVICE_INFORMATION, + .name = "basler-device-information", + .type = V4L2_CTRL_TYPE_U32+1, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + .step = 1, + .dims = {1}, + .elem_size = sizeof(struct basler_device_information), +}; + +static const struct v4l2_ctrl_config ctrl_basler_interface_version = { + .ops = &basler_camera_ctrl_ops, + .type_ops = &basler_camera_ctrl_type_ops, + .id = V4L2_CID_BASLER_INTERFACE_VERSION, + .name = "basler-interface-version", + .type = V4L2_CTRL_TYPE_INTEGER, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + .min = 0x0, + .max = 0xffffffff, + .def = (BASLER_INTERFACE_VERSION_MAJOR << 16) | BASLER_INTERFACE_VERSION_MINOR, + .step = 1, +}; + +static const struct v4l2_ctrl_config ctrl_basler_csi_information = { + .ops = &basler_camera_ctrl_ops, + .type_ops = &basler_camera_ctrl_type_ops, + .id = V4L2_CID_BASLER_CSI_INFORMATION, + .name = "basler-csi-information", + .type = V4L2_CTRL_TYPE_U32+1, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + .step = 1, + .dims = {1}, + .elem_size = sizeof(struct basler_csi_information), +}; + +static int basler_camera_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct v4l2_subdev *sd = ctrl_to_sd(ctrl); + struct basler_camera_dev *sensor = to_basler_camera_dev(sd); + struct i2c_client *client = sensor->i2c_client; + int ret; + struct register_access *fp_ra_new; + + switch (ctrl->id) { + case V4L2_CID_BASLER_ACCESS_REGISTER: + + if (ctrl->elem_size != sizeof(struct register_access)) + return -ENOMEM; + + fp_ra_new = (struct register_access*) ctrl->p_new.p; + if(basler_write_burst(client, fp_ra_new)) + ret = 0; + else + ret = -EIO; + + break; + + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int basler_camera_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct v4l2_subdev *sd = ctrl_to_sd(ctrl); + struct basler_camera_dev *sensor = to_basler_camera_dev(sd); + struct i2c_client *client = sensor->i2c_client; + int ret; + struct register_access *fp_ra_new = NULL; + struct basler_device_information* l_bdi = NULL; + + switch (ctrl->id) { + case V4L2_CID_BASLER_ACCESS_REGISTER: + + fp_ra_new = (struct register_access*) ctrl->p_new.p; + + if (ctrl->elem_size == sizeof(struct register_access)) + { + if(basler_read_burst(client, fp_ra_new)) + ret = 0; + else + ret = -EIO; + } + else { + ret = -ENOMEM; + } + break; + + case V4L2_CID_BASLER_DEVICE_INFORMATION: + + l_bdi = (struct basler_device_information*) ctrl->p_new.p; + + if (ctrl->elem_size == sizeof(struct basler_device_information)) + { + memcpy(l_bdi, &sensor->device_information, sizeof(struct basler_device_information)); + ret = 0; + } + else + { + ret = -ENOMEM; + } + break; + + case V4L2_CID_BASLER_CSI_INFORMATION: + if (ctrl->elem_size == sizeof(struct basler_csi_information)) + { + struct basler_csi_information* l_bci = NULL; + l_bci = (struct basler_csi_information*) ctrl->p_new.p; + ret = basler_retrieve_csi_information(sensor, l_bci); + } + else + { + ret = -ENOMEM; + } + break; + + default: + ret = -EINVAL; + break; + } + + return ret; +} + + +/** + * basler_camera_link_setup + * + * Note: Function is needed by imx8qm + * + * Returns always zero + */ +static int basler_camera_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static const struct media_entity_operations basler_camera_sd_media_ops = { + .link_setup = basler_camera_link_setup, +}; + + +static int basler_camera_init_controls(struct basler_camera_dev *sensor) +{ + struct v4l2_ctrl_handler *hdl = &sensor->ctrl_handler; + int ret; + + v4l2_ctrl_handler_init(hdl, 32); + + /* we can use our own mutex for the ctrl lock */ + hdl->lock = &sensor->lock; + + v4l2_ctrl_new_custom(hdl, &ctrl_access_register, NULL); + if (hdl->error) + { + dev_err(&sensor->i2c_client->dev, "Register ctrl access_register failed: %d\n", hdl->error); + ret = hdl->error; + goto free_ctrls; + } + + v4l2_ctrl_new_custom(hdl, &ctrl_basler_device_information, NULL); + if (hdl->error) + { + dev_err(&sensor->i2c_client->dev, "Register ctrl device_information failed: %d\n", hdl->error); + ret = hdl->error; + goto free_ctrls; + } + + v4l2_ctrl_new_custom(hdl, &ctrl_basler_interface_version, NULL); + if (hdl->error) + { + dev_err(&sensor->i2c_client->dev, "Register ctrl interface_version failed: %d\n", hdl->error); + ret = hdl->error; + goto free_ctrls; + } + + v4l2_ctrl_new_custom(hdl, &ctrl_basler_csi_information, NULL); + if (hdl->error) + { + dev_err(&sensor->i2c_client->dev, "Register ctrl csi_information failed: %d\n", hdl->error); + ret = hdl->error; + goto free_ctrls; + } + + sensor->sd.ctrl_handler = hdl; + return 0; + +free_ctrls: + v4l2_ctrl_handler_free(hdl); + dev_dbg(sensor->sd.v4l2_dev->dev, "%s: ctrl handler error.\n", __func__); + return ret; +} + +static int basler_camera_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct basler_camera_dev *sensor; + int ret; + + dev_dbg(dev, " %s driver start probing\n", SENSOR_NAME); + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + dev_err(dev, "I2C_FUNC_I2C not supported\n"); + return -ENODEV; + } + + sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + + sensor->i2c_client = client; + + ret = of_property_read_u32(dev->of_node, "csi_id", &(sensor->csi)); + if (ret) { + dev_err(dev, "csi id missing or invalid\n"); + return ret; + } + + v4l2_i2c_subdev_init(&sensor->sd, client, &basler_camera_subdev_ops); + + ret = basler_retrieve_device_information(client, &sensor->device_information); + if (ret) + return ret; + + sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + sensor->pad.flags = MEDIA_PAD_FL_SOURCE; + + sensor->sd.entity.ops = &basler_camera_sd_media_ops; + ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad); + if (ret) + return ret; + + mutex_init(&sensor->lock); + + ret = basler_camera_init_controls(sensor); + if (ret) + goto entity_cleanup; + + ret = v4l2_async_register_subdev_sensor_common(&sensor->sd); + if (ret) + goto entity_cleanup; + + dev_dbg(dev, " %s driver probed\n", SENSOR_NAME); + return 0; + +entity_cleanup: + mutex_destroy(&sensor->lock); + media_entity_cleanup(&sensor->sd.entity); + return ret; +} + +static int basler_camera_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct basler_camera_dev *sensor = to_basler_camera_dev(sd); + + v4l2_async_unregister_subdev(&sensor->sd); + sensor->sd.ctrl_handler = NULL; + v4l2_ctrl_handler_free(&sensor->ctrl_handler); + mutex_destroy(&sensor->lock); + media_entity_cleanup(&sensor->sd.entity); + + return 0; +} + +static const struct i2c_device_id basler_camera_id[] = { + { "basler-camera-vvcam", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, basler_camera_id); + +static const struct of_device_id basler_camera_dt_ids[] = { +#ifdef CONFIG_BASLER_CAMERA_VVCAM + { .compatible = "basler,basler-camera-vvcam" }, +#else + { .compatible = "basler,basler-camera" }, +#endif + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, basler_camera_dt_ids); + +static struct +#ifdef CONFIG_BASLER_CAMERA_VVCAM + i2c_driver basler_camera_i2c_driver_vvcam +#else + i2c_driver basler_camera_i2c_driver +#endif + = { + .driver = { + .owner = THIS_MODULE, +#ifdef CONFIG_BASLER_CAMERA_VVCAM + .name = "basler-camera-vvcam", +#else + .name = "basler-camera", +#endif + .of_match_table = basler_camera_dt_ids, + }, + .id_table = basler_camera_id, + .probe = basler_camera_probe, + .remove = basler_camera_remove, +}; + +#ifdef CONFIG_BASLER_CAMERA_VVCAM +module_i2c_driver(basler_camera_i2c_driver_vvcam); +#else +module_i2c_driver(basler_camera_i2c_driver); +#endif + +MODULE_DESCRIPTION("Basler camera subdev driver for vvcam"); +MODULE_AUTHOR("Sebastian Suesens "); +MODULE_LICENSE("GPL"); diff --git a/vvcam_ry/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.h b/vvcam_ry/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.h new file mode 100755 index 0000000..c7597fa --- /dev/null +++ b/vvcam_ry/v4l2/sensor/camera-proxy-driver/basler-camera-driver-vvcam/basler-camera-driver-vvcam.h @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2018 NXP + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + */ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef BASLER_CAMERA_DRIVER_VVCAM_H +#define BASLER_CAMERA_DRIVER_VVCAM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __KERNEL__ + +#include +#include + +#endif /* __KERNEL__ */ + +#define V4L2_CID_PROXY_BASE (V4L2_CTRL_CLASS_USER | 0x1000) +#define V4L2_CID_BASLER_INTERFACE_VERSION (V4L2_CID_PROXY_BASE+1) +#define V4L2_CID_BASLER_ACCESS_REGISTER (V4L2_CID_PROXY_BASE+2) +#define V4L2_CID_BASLER_DEVICE_INFORMATION (V4L2_CID_PROXY_BASE+3) +#define V4L2_CID_BASLER_CSI_INFORMATION (V4L2_CID_PROXY_BASE+4) + +#define I2CREAD (1) +#define I2CWRITE (2) + +#define GENCP_STRING_BUFFER_SIZE (64) +#define STRING_TERMINATION (1) +#define BDI_MAGIC (84513200) + +/* + * Basler interface Version + */ +#define BASLER_INTERFACE_VERSION_MAJOR ((__u16) 1) +#define BASLER_INTERFACE_VERSION_MINOR ((__u16) 0) + + +/* + Write register: + IOCTL VIDIOC_S_EXT_CTRLS with command == I2CWRITE + address, size and value + + Read register: + IOCTL VIDIOC_S_EXT_CTRLS with command == I2CREAD + address and size + then IOCTL VIDIOC_G_EXT_CTRLS returns value + + For the maximum buffer size to use in a read or write command please consider the values + "Maximum Write Transfer Length" and "Maximum Read Transfer Length" as described in the MCM Interface Specification. + These values can differ on the different sensor modules. +*/ +struct register_access { + __u16 address; /* Register address; host endianness*/ + __u8 data[256]; /* Read/Write register value - target endianness */ + __u16 data_size; /* Host endianness */ + __u8 command; /* On a VIDIOC_S_EXT_CTRLS identifies to store the register address */ +}; + +struct basler_device_information { + __u32 _magic; + __u32 gencpVersion; + __u8 manufacturerName[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 modelName[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 familyName[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 deviceVersion[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 manufacturerInfo[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 serialNumber[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; + __u8 userDefinedName[GENCP_STRING_BUFFER_SIZE + STRING_TERMINATION]; +}; + +/** + * struct basler_csi_information - sensor specific csi2 bus configuration. + * The cid to query this structure is V4L2_CID_BASLER_CSI_INFORMATION. + * + * @max_lanefrequency Max theoretical CSI frequency per lane in hertz. + * @lanecount Available CSI lane count. + * @laneassignment describes the physical CSI-2 connection between host and camera module. + * The index starts with 0 as CSI lane 1 of the host. + * The value starts with 1 as the CSI lane 1 of the sensor. + */ +struct basler_csi_information { + __u64 max_lane_frequency; + __u8 lane_count; + __u8 lane_assignment[4]; +}; + +enum { + BASLER_IOC_G_INTERFACE_VERSION = 0x100, + BASLER_IOC_READ_REGISTER, + BASLER_IOC_WRITE_REGISTER, + BASLER_IOC_G_DEVICE_INFORMATION, + BASLER_IOC_G_CSI_INFORMATION +}; + + +#ifdef ISP8000NANO_V1802 +#define CONFIG_BASLER_CAMERA_VVCAM +#endif + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* BASLER_CAMERA_DRIVER_VVCAM_H */ diff --git a/vvcam_ry/v4l2/sensor/os08a20/Makefile b/vvcam_ry/v4l2/sensor/os08a20/Makefile new file mode 100755 index 0000000..f9ccd3f --- /dev/null +++ b/vvcam_ry/v4l2/sensor/os08a20/Makefile @@ -0,0 +1,3 @@ +EXTRA_CFLAGS += -I$(PWD)/../common/ -O2 -Werror +os08a20-objs += os08a20_mipi_v3.o +obj-m += os08a20.o diff --git a/vvcam_ry/v4l2/sensor/os08a20/os08a20_mipi_v3.c b/vvcam_ry/v4l2/sensor/os08a20/os08a20_mipi_v3.c new file mode 100755 index 0000000..29fbcac --- /dev/null +++ b/vvcam_ry/v4l2/sensor/os08a20/os08a20_mipi_v3.c @@ -0,0 +1,1637 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vvsensor.h" + +#include "os08a20_regs_1080p.h" +#include "os08a20_regs_1080p_hdr.h" +#include "os08a20_regs_4k.h" +#include "os08a20_regs_4k_hdr.h" +#include "os08a20_regs_1080p_hdr.h" + +#define OS08a20_VOLTAGE_ANALOG 2800000 +#define OS08a20_VOLTAGE_DIGITAL_CORE 1500000 +#define OS08a20_VOLTAGE_DIGITAL_IO 1800000 + +#define MIN_FPS 15 +#define MAX_FPS 30 +#define DEFAULT_FPS 30 + +#define OS08a20_XCLK_MIN 6000000 +#define OS08a20_XCLK_MAX 24000000 + +#define OS08a20_CHIP_ID_HIGH_BYTE 0x300A +#define OS08a20_CHIP_ID_LOW_BYTE 0x300B + +#define OS08a20_SENS_PAD_SOURCE 0 +#define OS08a20_SENS_PADS_NUM 1 + +enum os08a20_mode { + os08a20_mode_MIN = 0, + os08a20_mode_4K_3840_2160 = 0, + os08a20_mode_1080P_1920_1080 = 0, + os08a20_mode_720P_1280_720 = 1, + os08a20_mode_NTSC_720_480 = 2, + os08a20_mode_VGA_640_480 = 3, + os08a20_mode_QVGA_320_240 = 4, + os08a20_mode_QSXGA_2592_1944 = 5, + os08a20_mode_MAX, + os08a20_mode_INIT = 0xff, /* only for sensor init */ +}; + +enum os08a20_frame_rate { + os08a20_15_fps, + os08a20_30_fps +}; + +struct os08a20_datafmt { + u32 code; + enum v4l2_colorspace colorspace; +}; + +/* image size under 1280 * 960 are SUBSAMPLING + * image size upper 1280 * 960 are SCALING + */ +enum os08a20_downsize_mode { + SUBSAMPLING, + SCALING, +}; + +struct os08a20_mode_info { + enum os08a20_mode mode; + enum os08a20_downsize_mode dn_mode; + u32 width; + u32 height; + struct vvsensor_reg_value_t *init_data_ptr; + u32 init_data_size; + u32 bit_width; + u32 fps; + bool is_default; + u32 stitching_mode; +}; + +struct os08a20_pll_info { + enum os08a20_mode mode; + struct vvsensor_reg_value_t *init_data_ptr; + u32 init_data_size; +}; + +struct os08a20_hs_info { + u32 width; + u32 height; + u32 frame_rate; + u32 val; +}; + +struct os08a20 { + struct regulator *io_regulator; + struct regulator *core_regulator; + struct regulator *analog_regulator; + struct v4l2_subdev subdev; + struct v4l2_device *v4l2_dev; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + const struct os08a20_datafmt *fmt; + struct v4l2_captureparm streamcap; + struct media_pad pads[OS08a20_SENS_PADS_NUM]; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + u32 mclk; + u8 mclk_source; + struct clk *sensor_clk; + int csi; + + void (*io_init) (struct os08a20 *); + int pwn_gpio, rst_gpio; + bool hdr; + int fps; + + vvcam_mode_info_t cur_mode; + struct mutex lock; +}; + +#define client_to_os08a20(client)\ + container_of(i2c_get_clientdata(client), struct os08a20, subdev) + +long os08a20_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg); +static void os08a20_stop(struct os08a20 *sensor); +s32 os08a20_write_reg(struct os08a20 *sensor, u16 reg, u8 val); + +static struct vvcam_mode_info pos08a20_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 10, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x492, + .one_line_exp_time_ns = 14250, + .max_integration_time = 0x492 - 8, + .min_integration_time = 8, + .gain_accuracy = 1024, + .max_gain = 62 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = os08a20_init_setting_1080p, + .reg_data_count = ARRAY_SIZE(os08a20_init_setting_1080p), + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_DUAL_DCG, + .bit_width = 10, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x492, + .one_line_exp_time_ns = 14250, + .max_integration_time = 0x492 - 8, + .min_integration_time = 8, + .gain_accuracy = 1024, + .max_gain = 62 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = os08a20_init_setting_1080p_hdr, + .reg_data_count = ARRAY_SIZE(os08a20_init_setting_1080p_hdr), + }, + { + .index = 2, + .width = 3840, + .height = 2160, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 12, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x924, + .one_line_exp_time_ns = 14250, + .max_integration_time = 0x924 - 64 - 4, + .min_integration_time = 8, + .gain_accuracy = 1024, + .max_gain = 62 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = os08a20_init_setting_4k, + .reg_data_count = ARRAY_SIZE(os08a20_init_setting_4k), + }, + { + .index = 3, + .width = 3840, + .height = 2160, + .fps = 15, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_L_AND_S, + .bit_width = 10, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x924, + .one_line_exp_time_ns = 14250, + .max_integration_time = 0x924 - 64 - 4,//T_long + Tshort < VTS - 4 + .min_integration_time = 8, + .gain_accuracy = 1024, + .max_gain = 62 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = os08a20_init_setting_4k_hdr, + .reg_data_count = ARRAY_SIZE(os08a20_init_setting_4k_hdr), + }, +}; + + +static struct os08a20_hs_info hs_setting[] = { + {1920, 1080, 30, 0x0B}, + {1920, 1080, 15, 0x10}, + {3840, 2160, 30, 0x0B}, + {3840, 2160, 20, 0x10}, +}; + +static int os08a20_probe(struct i2c_client *adapter, + const struct i2c_device_id *device_id); +static int os08a20_remove(struct i2c_client *client); + +static void os08a20_stop(struct os08a20 *sensor); + +static const struct i2c_device_id os08a20_id[] = { + {"ov2775", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, os08a20_id); + +static int __maybe_unused os08a20_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct os08a20 *sensor = client_to_os08a20(client); + + if (sensor->on) { + os08a20_stop(sensor); + } + + return 0; +} + +static int __maybe_unused os08a20_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct os08a20 *sensor = client_to_os08a20(client); + + if (sensor->on) { + os08a20_write_reg(sensor, 0x0100, 0x01); + } + return 0; +} + + +static const struct dev_pm_ops os08a20_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(os08a20_suspend, os08a20_resume) +}; +static const struct of_device_id os08a20_dt_ids[] = { + { .compatible = "ovti,ov2775" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, os08a20_dt_ids); + +static struct i2c_driver os08a20_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov2775", + .pm = &os08a20_pm_ops, + .of_match_table = os08a20_dt_ids, + }, + .probe = os08a20_probe, + .remove = os08a20_remove, + .id_table = os08a20_id, +}; + +#if 0 +static const struct os08a20_datafmt os08a20_colour_fmts[] = { + {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG}, + {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG}, +}; +#else +static const struct os08a20_datafmt os08a20_colour_fmts[] = { + {MEDIA_BUS_FMT_SBGGR12_1X12, V4L2_COLORSPACE_JPEG}, +}; +#endif + +#if 0 +static enum os08a20_frame_rate to_os08a20_frame_rate(struct v4l2_fract + *timeperframe) +{ + enum os08a20_frame_rate rate; + u32 tgt_fps; /* target frames per secound */ + + pr_info("enter %s\n", __func__); + tgt_fps = timeperframe->denominator / timeperframe->numerator; + + if (tgt_fps == 30) + rate = os08a20_30_fps; + else if (tgt_fps == 15) + rate = os08a20_15_fps; + else + rate = -EINVAL; + + return rate; +} +#endif + +static __u16 find_hs_configure(struct os08a20 *sensor) +{ + struct device *dev = &sensor->i2c_client->dev; + struct v4l2_fract *timeperframe = &sensor->streamcap.timeperframe; + struct v4l2_pix_format *pix = &sensor->pix; + u32 frame_rate = timeperframe->denominator / timeperframe->numerator; + int i; + + pr_info("enter %s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(hs_setting); i++) { + if (hs_setting[i].width == pix->width && + hs_setting[i].height == pix->height && + hs_setting[i].frame_rate == frame_rate) + return hs_setting[i].val; + } + + if (i == ARRAY_SIZE(hs_setting)) + dev_err(dev, "%s can not find hs configure\n", __func__); + + return -EINVAL; +} + +/* Find a data format by a pixel code in an array */ +static const struct os08a20_datafmt +*os08a20_find_datafmt(u32 code) +{ + int i; + + pr_debug("enter %s\n", __func__); + for (i = 0; i < ARRAY_SIZE(os08a20_colour_fmts); i++) + if (os08a20_colour_fmts[i].code == code) + return os08a20_colour_fmts + i; + + return NULL; +} + +static inline void os08a20_power_up(struct os08a20 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (gpio_is_valid(sensor->pwn_gpio)) { + gpio_set_value_cansleep(sensor->pwn_gpio, 1); + } +} + +static inline void os08a20_power_down(struct os08a20 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (gpio_is_valid(sensor->pwn_gpio)) { + gpio_set_value_cansleep(sensor->pwn_gpio, 0); + } +} + +static inline void os08a20_reset(struct os08a20 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (!gpio_is_valid(sensor->rst_gpio)) + return; + + gpio_set_value_cansleep(sensor->rst_gpio, 0); + msleep(20); + + gpio_set_value_cansleep(sensor->rst_gpio, 1); + msleep(20); +} + +static int os08a20_regulator_enable(struct os08a20 *sensor) +{ + int ret = 0; + struct device *dev = &(sensor->i2c_client->dev); + + pr_debug("enter %s\n", __func__); + if (sensor->io_regulator) + { + regulator_set_voltage(sensor->io_regulator, + OS08a20_VOLTAGE_DIGITAL_IO, + OS08a20_VOLTAGE_DIGITAL_IO); + ret = regulator_enable(sensor->io_regulator); + if (ret) + { + dev_err(dev, "set io voltage failed\n"); + return ret; + } + } + + if (sensor->analog_regulator) + { + regulator_set_voltage(sensor->analog_regulator, + OS08a20_VOLTAGE_ANALOG, + OS08a20_VOLTAGE_ANALOG); + ret = regulator_enable(sensor->analog_regulator); + if (ret) + { + dev_err(dev, "set analog voltage failed\n"); + goto err_disable_io; + } + } + + if (sensor->core_regulator) + { + regulator_set_voltage(sensor->core_regulator, + OS08a20_VOLTAGE_DIGITAL_CORE, + OS08a20_VOLTAGE_DIGITAL_CORE); + ret = regulator_enable(sensor->core_regulator); + if (ret) { + dev_err(dev, "set core voltage failed\n"); + goto err_disable_analog; + } + } + + return 0; + +err_disable_analog: + regulator_disable(sensor->analog_regulator); +err_disable_io: + regulator_disable(sensor->io_regulator); + return ret; +} + +static void os08a20_regulator_disable(struct os08a20 *sensor) +{ + int ret = 0; + struct device *dev = &(sensor->i2c_client->dev); + + if (sensor->core_regulator) + { + ret = regulator_disable(sensor->core_regulator); + if (ret < 0) + dev_err(dev, "core regulator disable failed\n"); + } + + if (sensor->analog_regulator) + { + ret = regulator_disable(sensor->analog_regulator); + if (ret < 0) + dev_err(dev, "analog regulator disable failed\n"); + } + + if (sensor->io_regulator) + { + ret = regulator_disable(sensor->io_regulator); + if (ret < 0) + dev_err(dev, "io regulator disable failed\n"); + } + return ; +} + + +s32 os08a20_write_reg(struct os08a20 *sensor, u16 reg, u8 val) +{ + u8 au8Buf[3] = { 0 }; + + au8Buf[0] = reg >> 8; + au8Buf[1] = reg & 0xff; + au8Buf[2] = val; + if (i2c_master_send(sensor->i2c_client, au8Buf, 3) < 0) { + pr_err("Write reg error: reg=%x, val=%x\n", reg, val); + return -1; + } + + return 0; +} + +s32 os08a20_read_reg(struct os08a20 *sensor, u16 reg, u8 *val) +{ + struct device *dev = &sensor->i2c_client->dev; + u8 au8RegBuf[2] = { 0 }; + u8 u8RdVal = 0; + + au8RegBuf[0] = reg >> 8; + au8RegBuf[1] = reg & 0xff; + + if (i2c_master_send(sensor->i2c_client, au8RegBuf, 2) != 2) { + dev_err(dev, "Read reg error: reg=%x\n", reg); + return -1; + } + + if (i2c_master_recv(sensor->i2c_client, &u8RdVal, 1) != 1) { + dev_err(dev, "Read reg error: reg=%x, val=%x\n", reg, u8RdVal); + return -1; + } + + *val = u8RdVal; + return u8RdVal; +} + +static int os08a20_set_clk_rate(struct os08a20 *sensor) +{ + u32 tgt_xclk; /* target xclk */ + int ret; + + /* mclk */ + tgt_xclk = sensor->mclk; + tgt_xclk = min_t(u32, tgt_xclk, (u32) OS08a20_XCLK_MAX); + tgt_xclk = max_t(u32, tgt_xclk, (u32) OS08a20_XCLK_MIN); + sensor->mclk = tgt_xclk; + + pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); + ret = clk_set_rate(sensor->sensor_clk, sensor->mclk); + if (ret < 0) + pr_debug("set rate filed, rate=%d\n", sensor->mclk); + return ret; +} + +/* download os08a20 settings to sensor through i2c */ +static int os08a20_download_firmware(struct os08a20 *sensor, + struct vvsensor_reg_value_t *mode_setting, + s32 size) +{ + register u32 delay_ms = 0; + register u16 reg_addr = 0; + register u8 mask = 0; + register u8 val = 0; + u8 reg_val = 0; + int i, retval = 0; + + pr_err("enter %s\n", __func__); + for (i = 0; i < size; ++i, ++mode_setting) { + delay_ms = mode_setting->delay; + reg_addr = mode_setting->addr; + val = mode_setting->val; + mask = mode_setting->mask; + + if (mask) { + retval = os08a20_read_reg(sensor, reg_addr, ®_val); + if (retval < 0) + break; + + reg_val &= ~(u8)mask; + val &= mask; + val |= reg_val; + } + + retval = os08a20_write_reg(sensor, reg_addr, val); + os08a20_read_reg(sensor, reg_addr, ®_val); + + if (retval < 0) + break; + + if (delay_ms) + msleep(delay_ms); + } + + return retval; +} + +static void os08a20_start(struct os08a20 *sensor) +{ + pr_err("enter %s\n", __func__); + os08a20_write_reg(sensor, 0x0100, 0x01); + msleep(100); +} + +static void os08a20_stop(struct os08a20 *sensor) +{ + pr_err("enter %s\n", __func__); + os08a20_write_reg(sensor, 0x0100, 0x00); +} + +/*! + * os08a20_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl + * @s: pointer to standard V4L2 device structure + * @on: indicates power mode (on or off) + * + * Turns the power on or off, depending on the value of on and returns the + * appropriate error code. + */ +static int os08a20_s_power(struct v4l2_subdev *sd, int on) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + + pr_debug("enter %s\n", __func__); + if (on) + clk_prepare_enable(sensor->sensor_clk); + else + clk_disable_unprepare(sensor->sensor_clk); + + sensor->on = on; + return 0; +} + +/*! + * os08a20_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 sub device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int os08a20_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + pr_debug("enter %s\n", __func__); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ov5460_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 sub device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int os08a20_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; + u32 tgt_fps; /* target frames per secound */ + enum os08a20_mode mode = a->parm.capture.capturemode; + int ret = 0; + + pr_debug("enter %s\n", __func__); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + /* Check that the new frame rate is allowed. */ + if ((timeperframe->numerator == 0) || + (timeperframe->denominator == 0)) { + timeperframe->denominator = DEFAULT_FPS; + timeperframe->numerator = 1; + } + + tgt_fps = timeperframe->denominator / timeperframe->numerator; + + if (tgt_fps > MAX_FPS) { + timeperframe->denominator = MAX_FPS; + timeperframe->numerator = 1; + } else if (tgt_fps < MIN_FPS) { + timeperframe->denominator = MIN_FPS; + timeperframe->numerator = 1; + } + + if (mode > os08a20_mode_MAX || mode < os08a20_mode_MIN) { + pr_err("The camera mode[%d] is not supported!\n", mode); + return -EINVAL; + } + + sensor->streamcap.capturemode = mode; + sensor->streamcap.timeperframe = *timeperframe; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_debug(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +static int os08a20_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + + pr_debug("enter %s\n", __func__); + if (enable) + os08a20_start(sensor); + else + os08a20_stop(sensor); + + sensor->on = enable; + return 0; +} + +#if 0 +static struct os08a20_mode_info *get_max_resolution(enum os08a20_frame_rate rate) +{ + u32 max_width; + enum os08a20_mode mode; + int i; + + pr_debug("enter %s\n", __func__); + mode = 0; + max_width = os08a20_mode_info_data[rate][0].width; + + for (i = 0; i < (os08a20_mode_MAX + 1); i++) { + if (os08a20_mode_info_data[rate][i].width > max_width) { + max_width = os08a20_mode_info_data[rate][i].width; + mode = i; + } + } + return &os08a20_mode_info_data[rate][mode]; +} + +static struct os08a20_mode_info *match(struct v4l2_mbus_framefmt *fmt, + enum os08a20_frame_rate rate) +{ + struct os08a20_mode_info *info; + int i; + + pr_debug("enter %s\n", __func__); + for (i = 0; i < (os08a20_mode_MAX + 1); i++) { + if (fmt->width == os08a20_mode_info_data[rate][i].width && + fmt->height == os08a20_mode_info_data[rate][i].height) { + info = &os08a20_mode_info_data[rate][i]; + break; + } + } + if (i == os08a20_mode_MAX + 1) + info = NULL; + + return info; +} + +static void try_to_find_resolution(struct os08a20 *sensor, + struct v4l2_mbus_framefmt *mf) +{ + enum os08a20_mode mode = sensor->streamcap.capturemode; + struct v4l2_fract *timeperframe = &sensor->streamcap.timeperframe; + enum os08a20_frame_rate frame_rate = to_os08a20_frame_rate(timeperframe); + struct device *dev = &sensor->i2c_client->dev; + struct os08a20_mode_info *info; + bool found = false; + + pr_debug("enter %s\n", __func__); + if ((mf->width == os08a20_mode_info_data[frame_rate][mode].width) && + (mf->height == os08a20_mode_info_data[frame_rate][mode].height)) { + info = &os08a20_mode_info_data[frame_rate][mode]; + found = true; + } else { + /* get mode info according to frame user's width and height */ + info = match(mf, frame_rate); + if (info == NULL) { + frame_rate ^= 0x1; + info = match(mf, frame_rate); + if (info) { + sensor->streamcap.capturemode = -1; + dev_err(dev, "%s %dx%d only support %s(fps)\n", + __func__, info->width, info->height, + (frame_rate == 0) ? "15fps" : "30fps"); + return; + } + goto max_resolution; + } + found = true; + } + + /* get max resolution to resize */ +max_resolution: + if (!found) { + frame_rate ^= 0x1; + info = get_max_resolution(frame_rate); + } + + sensor->streamcap.capturemode = info->mode; + sensor->streamcap.timeperframe.denominator = (frame_rate) ? 30 : 15; + sensor->pix.width = info->width; + sensor->pix.height = info->height; +} +#endif + +static int os08a20_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *mf = &format->format; + const struct os08a20_datafmt *fmt = os08a20_find_datafmt(mf->code); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + unsigned int i; + struct vvsensor_reg_value_t *mode_setting = NULL; + int array_size = 0; + + pr_debug("enter %s\n", __func__); + if (format->pad) { + return -EINVAL; + } + + if (!fmt) { + mf->code = os08a20_colour_fmts[0].code; + mf->colorspace = os08a20_colour_fmts[0].colorspace; + } + + mf->field = V4L2_FIELD_NONE; + /* old search method, vsi need change to + search resolution by width/height */ + /* try_to_find_resolution(sensor, mf); */ + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + return 0; + + for (i=0; ihdr) + { + if (mf->width == pos08a20_mode_info[i].width && + mf->height == pos08a20_mode_info[i].height && + pos08a20_mode_info[i].hdr_mode != SENSOR_MODE_LINEAR) + { + memcpy(&(sensor->cur_mode), &pos08a20_mode_info[i], sizeof(struct vvcam_mode_info)); + mode_setting = pos08a20_mode_info[i].preg_data; + array_size = pos08a20_mode_info[i].reg_data_count; + return os08a20_download_firmware(sensor, mode_setting, array_size); + } + }else + { + if (mf->width == pos08a20_mode_info[i].width && + mf->height == pos08a20_mode_info[i].height && + pos08a20_mode_info[i].hdr_mode == SENSOR_MODE_LINEAR) + { + memcpy(&(sensor->cur_mode), &pos08a20_mode_info[i], sizeof(struct vvcam_mode_info)); + mode_setting = pos08a20_mode_info[i].preg_data; + array_size = pos08a20_mode_info[i].reg_data_count; + return os08a20_download_firmware(sensor, mode_setting, array_size); + } + } + } + + pr_err("%s search error: %d %d\n", __func__, mf->width, mf->height); + return -EINVAL;; +} + +static int os08a20_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *mf = &format->format; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + + pr_debug("enter %s\n", __func__); + if (format->pad) + return -EINVAL; + + memset(mf, 0, sizeof(struct v4l2_mbus_framefmt)); + + mf->code = os08a20_colour_fmts[0].code; + mf->colorspace = os08a20_colour_fmts[0].colorspace; + mf->width = sensor->pix.width; + mf->height = sensor->pix.height; + mf->field = V4L2_FIELD_NONE; + mf->reserved[1] = find_hs_configure(sensor); + + dev_dbg(&client->dev, + "%s code=0x%x, w/h=(%d,%d), colorspace=%d, field=%d\n", + __func__, mf->code, mf->width, mf->height, mf->colorspace, + mf->field); + + return 0; +} + +static int os08a20_enum_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + pr_debug("enter %s\n", __func__); + if (code->pad || code->index >= ARRAY_SIZE(os08a20_colour_fmts)) + return -EINVAL; + + code->code = os08a20_colour_fmts[code->index].code; + return 0; +} + +/*! + * os08a20_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int os08a20_enum_framesizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + pr_debug("enter %s\n", __func__); + if (fse->index > ARRAY_SIZE(pos08a20_mode_info)) + return -EINVAL; + + fse->min_width = pos08a20_mode_info[fse->index].width; + fse->max_width = fse->min_width; + fse->min_height = pos08a20_mode_info[fse->index].height; + fse->max_height = fse->min_height; + + return 0; +} + +/*! + * os08a20_enum_frameintervals - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMEINTERVALS ioctl + * @s: pointer to standard V4L2 device structure + * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int os08a20_enum_frameintervals(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum + *fie) +{ + + pr_debug("enter %s\n", __func__); + if (fie->index < 0 || fie->index > os08a20_mode_MAX) + return -EINVAL; + + if (fie->width == 0 || fie->height == 0 || fie->code == 0) { + pr_warn("Please assign pixel format, width and height.\n"); + return -EINVAL; + } + + fie->interval.numerator = 1; + fie->interval.denominator = pos08a20_mode_info[fie->index].fps; + + return 0; +} + +static int os08a20_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static struct v4l2_subdev_video_ops os08a20_subdev_video_ops = { + .g_parm = os08a20_g_parm, + .s_parm = os08a20_s_parm, + .s_stream = os08a20_s_stream, +}; + +static const struct v4l2_subdev_pad_ops os08a20_subdev_pad_ops = { + .enum_frame_size = os08a20_enum_framesizes, + .enum_frame_interval = os08a20_enum_frameintervals, + .enum_mbus_code = os08a20_enum_code, + .set_fmt = os08a20_set_fmt, + .get_fmt = os08a20_get_fmt, +}; + +static struct v4l2_subdev_core_ops os08a20_subdev_core_ops = { + .s_power = os08a20_s_power, + .ioctl = os08a20_priv_ioctl, +}; + +static struct v4l2_subdev_ops os08a20_subdev_ops = { + .core = &os08a20_subdev_core_ops, + .video = &os08a20_subdev_video_ops, + .pad = &os08a20_subdev_pad_ops, +}; + +static const struct media_entity_operations os08a20_sd_media_ops = { + .link_setup = os08a20_link_setup, +}; + +/*! + * os08a20 I2C probe function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ + +static int os08a20_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct pinctrl *pinctrl; + struct device *dev = &client->dev; + struct v4l2_subdev *sd; + int retval; + u8 reg_val = 0; + u16 chip_id = 0; + struct os08a20 *sensor; + + pr_debug("enter %s\n", __func__); + sensor = devm_kmalloc(dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + /* Set initial values for the sensor struct. */ + memset(sensor, 0, sizeof(*sensor)); + sensor->i2c_client = client; + + /* os08a20 pinctrl */ + pinctrl = devm_pinctrl_get_select_default(dev); + if (IS_ERR(pinctrl)) { + dev_err(dev, "setup pinctrl failed\n"); + return PTR_ERR(pinctrl); + } + + /* request power down pin */ + sensor->pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); + if (!gpio_is_valid(sensor->pwn_gpio)) + dev_warn(dev, "No sensor pwdn pin available"); + else { + retval = devm_gpio_request_one(dev, sensor->pwn_gpio, + GPIOF_OUT_INIT_HIGH, + "os08a20_mipi_pwdn"); + if (retval < 0) { + dev_warn(dev, "Failed to set power pin\n"); + dev_warn(dev, "retval=%d\n", retval); + return retval; + } + } + + /* request reset pin */ + sensor->rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); + if (!gpio_is_valid(sensor->rst_gpio)) + dev_warn(dev, "No sensor reset pin available"); + else { + retval = devm_gpio_request_one(dev, sensor->rst_gpio, + GPIOF_OUT_INIT_HIGH, + "os08a20_mipi_reset"); + if (retval < 0) { + dev_warn(dev, "Failed to set reset pin\n"); + return retval; + } + } + + /* Set initial values for the sensor struct. */ + sensor->sensor_clk = devm_clk_get(dev, "csi_mclk"); + if (IS_ERR(sensor->sensor_clk)) { + /* assuming clock enabled by default */ + sensor->sensor_clk = NULL; + dev_err(dev, "clock-frequency missing or invalid\n"); + return PTR_ERR(sensor->sensor_clk); + } + + retval = of_property_read_u32(dev->of_node, "mclk", &(sensor->mclk)); + if (retval) { + dev_err(dev, "mclk missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "mclk_source", + (u32 *)&(sensor->mclk_source)); + if (retval) { + dev_err(dev, "mclk_source missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "csi_id", &(sensor->csi)); + if (retval) { + dev_err(dev, "csi id missing or invalid\n"); + return retval; + } + sensor->io_regulator = devm_regulator_get(dev, "DOVDD"); + if (IS_ERR(sensor->io_regulator)) + { + dev_err(dev, "cannot get io regulator\n"); + return PTR_ERR(sensor->io_regulator); + } + + sensor->core_regulator = devm_regulator_get(dev, "DVDD"); + if (IS_ERR(sensor->core_regulator)) + { + dev_err(dev, "cannot get core regulator\n"); + return PTR_ERR(sensor->core_regulator); + } + + sensor->analog_regulator = devm_regulator_get(dev, "AVDD"); + if (IS_ERR(sensor->analog_regulator)) + { + dev_err(dev, "cannot get analog regulator\n"); + return PTR_ERR(sensor->analog_regulator); + } + + retval = os08a20_regulator_enable(sensor); + if (retval) { + dev_err(dev, "regulator enable failed\n"); + return retval; + } + + /* Set mclk rate before clk on */ + os08a20_set_clk_rate(sensor); + + retval = clk_prepare_enable(sensor->sensor_clk); + if (retval < 0) { + dev_err(dev, "%s: enable sensor clk fail\n", __func__); + goto probe_err_regulator_disable; + } + os08a20_power_up(sensor); + os08a20_reset(sensor); + + sensor->io_init = os08a20_reset; + + sensor->pix.pixelformat = V4L2_PIX_FMT_UYVY; + sensor->pix.width =pos08a20_mode_info[0].width; + sensor->pix.height = pos08a20_mode_info[0].height; + sensor->streamcap.capability = V4L2_MODE_HIGHQUALITY | + V4L2_CAP_TIMEPERFRAME; + sensor->streamcap.capturemode = 0; + sensor->streamcap.timeperframe.denominator = pos08a20_mode_info[0].fps; + sensor->streamcap.timeperframe.numerator = 1; + + chip_id = 0; + os08a20_read_reg(sensor, OS08a20_CHIP_ID_HIGH_BYTE,®_val); + chip_id |= reg_val << 8; + os08a20_read_reg(sensor, OS08a20_CHIP_ID_LOW_BYTE, ®_val); + chip_id |= reg_val; + if (chip_id != 0x5308) { + pr_warn("camera os08a20 is not found\n"); + goto probe_err_power_down; + } + + sd = &sensor->subdev; + v4l2_i2c_subdev_init(sd, client, &os08a20_subdev_ops); + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + sensor->pads[OS08a20_SENS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + + retval = media_entity_pads_init(&sd->entity, OS08a20_SENS_PADS_NUM, + sensor->pads); + sd->entity.ops = &os08a20_sd_media_ops; + if (retval < 0) + goto probe_err_power_down; + + retval = v4l2_async_register_subdev_sensor_common(sd); + if (retval < 0) { + dev_err(&client->dev,"%s--Async register failed, ret=%d\n", __func__,retval); + goto probe_err_entity_cleanup; + } + mutex_init(&sensor->lock); + + pr_info("%s camera mipi os08a20, is found\n", __func__); + return 0; + +probe_err_entity_cleanup: + media_entity_cleanup(&sd->entity); +probe_err_power_down: + os08a20_power_down(sensor); + clk_disable_unprepare(sensor->sensor_clk); +probe_err_regulator_disable: + os08a20_regulator_disable(sensor); + return retval; +} + +/*! + * os08a20 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int os08a20_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct os08a20 *sensor = client_to_os08a20(client); + + pr_info("enter %s\n", __func__); + + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + os08a20_power_down(sensor); + clk_disable_unprepare(sensor->sensor_clk); + os08a20_regulator_disable(sensor); + mutex_destroy(&sensor->lock); + + return 0; +} + +module_i2c_driver(os08a20_i2c_driver); +MODULE_DESCRIPTION("OS08a20 MIPI Camera Subdev Driver"); +MODULE_LICENSE("GPL"); + +int sensor_calc_gain(__u32 total_gain, __u32 *pagain, __u32 *pdgain) +{ + if (total_gain < 1024) + { + total_gain = 1024; + } + + if(total_gain < (0x7c0 << 3)) + { + *pdgain = 0x400; + *pagain = (total_gain << 7) / *pdgain;//(128 * 1024)/1024 = 128 + + }else + { + *pagain = 0x7c0; + *pdgain = (total_gain << 7) / 0x7c0; + } + return 0; +} + +int os08a20_s_long_gain(struct os08a20 *sensor, __u32 new_gain) +{ + __u32 again = 0; + __u32 dgain = 0; + int ret = 0; + + sensor_calc_gain(new_gain, &again, &dgain); + + ret |= os08a20_write_reg(sensor, 0x3508, (again >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x3509, again & 0xff); + + ret |= os08a20_write_reg(sensor, 0x350a, (dgain >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x350b, dgain & 0x00FF); + + return ret; +} + +int os08a20_s_short_gain(struct os08a20 *sensor, __u32 new_gain) +{ + __u32 again = 0; + __u32 dgain = 0; + int ret = 0; + + sensor_calc_gain(new_gain, &again, &dgain); + + ret |= os08a20_write_reg(sensor, 0x350c, (again >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x350d, again & 0xff); + + ret |= os08a20_write_reg(sensor, 0x350e, (dgain >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x350f, dgain & 0x00FF); + + return ret; +} + +int os08a20_s_long_exp(struct os08a20 *sensor, __u32 exp) +{ + int ret = 0; + ret |= os08a20_write_reg(sensor, 0x3501, (exp >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x3502, exp & 0xff); + + return ret; +} + +int os08a20_s_short_exp(struct os08a20 *sensor, __u32 exp) +{ + int ret = 0; + ret |= os08a20_write_reg(sensor, 0x3511, (exp >> 8) & 0xff); + ret |= os08a20_write_reg(sensor, 0x3512, exp & 0xff); + + return ret; +} + +int os08a20_g_gain(struct os08a20 *sensor, struct vvsensor_gain_context *gain) +{ + return 0; +} + +int os08a20_g_version(struct os08a20 *sensor, __u32 *version) +{ + __u8 val = 0; + + os08a20_read_reg(sensor, 0x300a, &val); + *version = val << 8; + os08a20_read_reg(sensor, 0x300b, &val); + *version |= val; + return 0; +} + + +int os08a20_s_hdr(struct os08a20 *sensor, bool enable) +{ + pr_debug("%s: %d\n", __func__, enable); + sensor->hdr = enable; + return 0; +} + +int os08a20_s_clk(struct os08a20 *sensor, __u32 clk) +{ + pr_debug("%s: %d\n", __func__, clk); + os08a20_write_reg(sensor, 0x3005, clk); + return 0; +} + +int os08a20_g_clk(struct os08a20 *sensor, __u32 *clk) +{ + u8 val; + os08a20_read_reg(sensor, 0x3005, &val); + *clk = val; + return 0; +} + +int os08a20_s_fps(struct os08a20 *sensor, __u32 fps) +{ + u32 vts; + pr_debug("%s: %d\n", __func__, fps); + if (fps < 5) { + fps = 5; + } + if (fps > sensor->cur_mode.fps){ + fps = sensor->cur_mode.fps; + } + sensor->fps = fps; + + vts = sensor->cur_mode.fps * sensor->cur_mode.ae_info.DefaultFrameLengthLines / sensor->fps; + + os08a20_write_reg(sensor, 0x380e, (vts >> 8)&0xff); + os08a20_write_reg(sensor, 0x380f, vts&0xff); + + if (sensor->hdr) + { + sensor->cur_mode.ae_info.cur_fps = sensor->fps; + sensor->cur_mode.ae_info.CurFrameLengthLines = vts; + sensor->cur_mode.ae_info.max_integration_time = vts - 64 - 4; + }else + { + sensor->cur_mode.ae_info.cur_fps = sensor->fps; + sensor->cur_mode.ae_info.CurFrameLengthLines = vts; + sensor->cur_mode.ae_info.max_integration_time = vts - 8; + } + + return 0; +} + +int os08a20_g_fps(struct os08a20 *sensor, __u32 *fps) +{ + *fps = sensor->fps; + return 0; +} + +int os08a20_g_chipid(struct os08a20 *sensor, __u32 *chip_id) +{ + int ret = 0; + __u8 chip_id_high = 0; + __u8 chip_id_low = 0; + ret = os08a20_read_reg(sensor, 0x300a, &chip_id_high); + ret |= os08a20_read_reg(sensor, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + return ret; +} + +int os08a20_ioc_qcap(struct os08a20 *sensor, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "os08a20"); + sprintf((char *)cap->bus_info, "csi%d",sensor->csi); + if(sensor->i2c_client->adapter) + {//bus_info[8]-i2c bus dev number + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = (__u8)sensor->i2c_client->adapter->nr; + } + else + { + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = 0xFF; + } + + return 0; +} + +int os08a20_ioc_query_mode(struct os08a20 *sensor, struct vvcam_mode_info_array *array) +{ + array->count = ARRAY_SIZE(pos08a20_mode_info); +#ifdef __KERNEL__ + unsigned long copy_ret = 0; + pr_debug("sensor %p\n", sensor); + copy_ret = copy_to_user(&array->modes,pos08a20_mode_info,sizeof(pos08a20_mode_info)); +#else + memcpy(&array->modes,pos08a20_mode_info,sizeof(pos08a20_mode_info)); +#endif + return 0; +} + +int os08a20_g_mode(struct os08a20 *sensor, struct vvcam_mode_info *pmode) +{ + int i = 0; + struct vvcam_mode_info *pcur_mode = NULL; + + if (sensor->cur_mode.index == pmode->index && + sensor->cur_mode.width != 0 && + sensor->cur_mode.height != 0) + { + pcur_mode = &(sensor->cur_mode); + memcpy(pmode,pcur_mode,sizeof(struct vvcam_mode_info)); + return 0; + } + + for(i=0; i < ARRAY_SIZE(pos08a20_mode_info); i++) + { + if (pmode->index == pos08a20_mode_info[i].index) + { + pcur_mode = &pos08a20_mode_info[i]; + break; + } + } + + if (pcur_mode == NULL) + { + return -1; + } + + memcpy(pmode,pcur_mode,sizeof(struct vvcam_mode_info)); + return 0; +} + + +/* +Use USER_TO_KERNEL/KERNEL_TO_USER to fix "uaccess" exception on run time. +Also, use "copy_ret" to fix the build issue as below. +error: ignoring return value of function declared with 'warn_unused_result' attribute. +*/ + +#ifdef __KERNEL__ +#define USER_TO_KERNEL(TYPE) \ + do {\ + TYPE tmp; \ + unsigned long copy_ret; \ + arg = (void *)(&tmp); \ + copy_ret = copy_from_user(arg, arg_user, sizeof(TYPE));\ + } while (0) + +#define KERNEL_TO_USER(TYPE) \ + do {\ + unsigned long copy_ret; \ + copy_ret = copy_to_user(arg_user, arg, sizeof(TYPE));\ + } while (0) +#else +#define USER_TO_KERNEL(TYPE) +#define KERNEL_TO_USER(TYPE) +#endif + +long os08a20_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg_user) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct os08a20 *sensor = client_to_os08a20(client); + struct vvcam_sccb_data reg; + int ret = 0; + void *arg = arg_user; + + /* pr_info("enter %s\n", __func__); */ + mutex_lock(&sensor->lock); + switch (cmd) { + case VVSENSORIOC_WRITE_REG: { + USER_TO_KERNEL(struct vvcam_sccb_data); + reg = *(struct vvcam_sccb_data *)arg; + ret = os08a20_write_reg(sensor, reg.addr, (u8)reg.data) < 0; + break; + } + case VVSENSORIOC_READ_REG: { + struct vvcam_sccb_data *preg; + u8 val; + USER_TO_KERNEL(struct vvcam_sccb_data); + preg = (struct vvcam_sccb_data *)arg; + ret = os08a20_read_reg(sensor, (u16) preg->addr, &val) < 0; + preg->data = val; + KERNEL_TO_USER(struct vvcam_sccb_data); + break; + } + case VVSENSORIOC_S_STREAM: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_stream(sd, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_EXP: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_long_exp(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_VSEXP: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_short_exp(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_GAIN: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_long_gain(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_VSGAIN: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_short_gain(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_FPS: { + USER_TO_KERNEL(__u32); + ret = os08a20_s_fps(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_G_FPS: { + USER_TO_KERNEL(__u32); + ret = os08a20_g_fps(sensor, (__u32 *)arg); + KERNEL_TO_USER(__u32); + break; + } + case VVSENSORIOC_S_CLK: { + USER_TO_KERNEL(__u32); + //ret = os08a20_s_clk(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_G_CLK: { + USER_TO_KERNEL(__u32); + ret = os08a20_g_clk(sensor, (__u32 *)arg); + KERNEL_TO_USER(__u32); + break; + } + case VIDIOC_QUERYCAP: + ret = os08a20_ioc_qcap(sensor, arg); + break; + case VVSENSORIOC_G_CHIP_ID: { + USER_TO_KERNEL(__u32); + ret = os08a20_g_chipid(sensor, (__u32 *)arg); + ret = (ret < 0) ? -1 : 0; + KERNEL_TO_USER(__u32); + break; + } + case VVSENSORIOC_G_RESERVE_ID: { + __u32 correct_id = 0x5308; + ret = copy_to_user(arg_user, &correct_id, sizeof(__u32)); + ret = ret? -1 : 0; + break; + } + case VVSENSORIOC_S_HDR_MODE: { + USER_TO_KERNEL(bool); + ret = os08a20_s_hdr(sensor, *(bool *)arg); + break; + } + case VVSENSORIOC_QUERY: { + //USER_TO_KERNEL(struct vvcam_mode_info_array); + os08a20_ioc_query_mode(sensor, arg); + //KERNEL_TO_USER(struct vvcam_mode_info_array); + break; + } + case VVSENSORIOC_G_SENSOR_MODE: { + USER_TO_KERNEL(struct vvcam_mode_info); + os08a20_g_mode(sensor, arg); + KERNEL_TO_USER(struct vvcam_mode_info); + break; + } + default: + /* pr_err("unsupported os08a20 command %d.", cmd); */ + break; + } + mutex_unlock(&sensor->lock); + + return ret; +} diff --git a/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_1080p.h b/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_1080p.h new file mode 100755 index 0000000..4588ba8 --- /dev/null +++ b/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_1080p.h @@ -0,0 +1,246 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVCAM_OS08a20_REGS_1080P_H_ +#define _VVCAM_OS08a20_REGS_1080P_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t os08a20_init_setting_1080p[] = { + {0x0100, 0x00, 0, 0}, + {0x0103, 0x01, 0, 0}, + {0x0303, 0x01, 0, 0}, + {0x0305, 0x32, 0, 0}, + {0x0306, 0x00, 0, 0}, + {0x0308, 0x03, 0, 0}, + {0x0309, 0x04, 0, 0}, + {0x032a, 0x00, 0, 0}, + {0x300f, 0x11, 0, 0}, + {0x3010, 0x01, 0, 0}, + {0x3011, 0x04, 0, 0}, + {0x3012, 0x41, 0, 0}, + {0x3016, 0xf0, 0, 0}, + {0x301e, 0x98, 0, 0}, + {0x3031, 0xa9, 0, 0}, + {0x3103, 0x92, 0, 0}, + {0x3104, 0x01, 0, 0}, + {0x3106, 0x10, 0, 0}, + {0x3400, 0x04, 0, 0}, + {0x3025, 0x03, 0, 0}, + {0x3425, 0x01, 0, 0}, + {0x3428, 0x01, 0, 0}, + {0x3406, 0x08, 0, 0}, + {0x3408, 0x03, 0, 0}, + {0x340c, 0xff, 0, 0}, + {0x340d, 0xff, 0, 0}, + {0x031e, 0x09, 0, 0}, + {0x3501, 0x04, 0, 0}, + {0x3502, 0x62, 0, 0}, + {0x3505, 0x83, 0, 0}, + {0x3508, 0x00, 0, 0}, + {0x3509, 0x80, 0, 0}, + {0x350a, 0x04, 0, 0}, + {0x350b, 0x00, 0, 0}, + {0x350c, 0x00, 0, 0}, + {0x350d, 0x80, 0, 0}, + {0x350e, 0x04, 0, 0}, + {0x350f, 0x00, 0, 0}, + {0x3600, 0x09, 0, 0}, + {0x3603, 0x2c, 0, 0}, + {0x3605, 0x50, 0, 0}, + {0x3609, 0xb5, 0, 0}, + {0x3610, 0x39, 0, 0}, + {0x360c, 0x01, 0, 0}, + {0x3628, 0xa4, 0, 0}, + {0x362d, 0x10, 0, 0}, + {0x3660, 0x43, 0, 0}, + {0x3661, 0x06, 0, 0}, + {0x3662, 0x00, 0, 0}, + {0x3663, 0x28, 0, 0}, + {0x3664, 0x0d, 0, 0}, + {0x366a, 0x38, 0, 0}, + {0x366b, 0xa0, 0, 0}, + {0x366d, 0x00, 0, 0}, + {0x366e, 0x00, 0, 0}, + {0x3680, 0x00, 0, 0}, + {0x36c0, 0x00, 0, 0}, + {0x3701, 0x02, 0, 0}, + {0x373b, 0x02, 0, 0}, + {0x373c, 0x02, 0, 0}, + {0x3736, 0x02, 0, 0}, + {0x3737, 0x02, 0, 0}, + {0x3705, 0x00, 0, 0}, + {0x3706, 0x39, 0, 0}, + {0x370a, 0x00, 0, 0}, + {0x370b, 0x98, 0, 0}, + {0x3709, 0x49, 0, 0}, + {0x3714, 0x22, 0, 0}, + {0x371c, 0x00, 0, 0}, + {0x371d, 0x08, 0, 0}, + {0x3740, 0x1b, 0, 0}, + {0x3741, 0x04, 0, 0}, + {0x375e, 0x0b, 0, 0}, + {0x3760, 0x10, 0, 0}, + {0x3776, 0x10, 0, 0}, + {0x3781, 0x02, 0, 0}, + {0x3782, 0x04, 0, 0}, + {0x3783, 0x02, 0, 0}, + {0x3784, 0x08, 0, 0}, + {0x3785, 0x08, 0, 0}, + {0x3788, 0x01, 0, 0}, + {0x3789, 0x01, 0, 0}, + {0x3797, 0x04, 0, 0}, + {0x3762, 0x11, 0, 0}, + {0x3800, 0x00, 0, 0}, + {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, + {0x3803, 0x0c, 0, 0}, + {0x3804, 0x0e, 0, 0}, + {0x3805, 0xff, 0, 0}, + {0x3806, 0x08, 0, 0}, + {0x3807, 0x6f, 0, 0}, + {0x3808, 0x07, 0, 0}, + {0x3809, 0x80, 0, 0}, + {0x380a, 0x04, 0, 0}, + {0x380b, 0x38, 0, 0}, + {0x380c, 0x08, 0, 0}, + {0x380d, 0x04, 0, 0}, + {0x380e, 0x04, 0, 0}, + {0x380f, 0x92, 0, 0}, + {0x3813, 0x08, 0, 0}, + {0x3814, 0x03, 0, 0}, + {0x3815, 0x01, 0, 0}, + {0x3816, 0x03, 0, 0}, + {0x3817, 0x01, 0, 0}, + {0x381c, 0x00, 0, 0}, + {0x3820, 0x05, 0, 0}, + {0x3821, 0x01, 0, 0}, + {0x3823, 0x08, 0, 0}, + {0x3826, 0x00, 0, 0}, + {0x3827, 0x08, 0, 0}, + {0x382d, 0x08, 0, 0}, + {0x3832, 0x02, 0, 0}, + {0x3833, 0x00, 0, 0}, + {0x383c, 0x48, 0, 0}, + {0x383d, 0xff, 0, 0}, + {0x3d85, 0x0b, 0, 0}, + {0x3d84, 0x40, 0, 0}, + {0x3d8c, 0x63, 0, 0}, + {0x3d8d, 0xd7, 0, 0}, + {0x4000, 0xf8, 0, 0}, + {0x4001, 0x2b, 0, 0}, + {0x4004, 0x00, 0, 0}, + {0x4005, 0x40, 0, 0}, + {0x400a, 0x01, 0, 0}, + {0x400f, 0xa0, 0, 0}, + {0x4010, 0x12, 0, 0}, + {0x4018, 0x00, 0, 0}, + {0x4008, 0x02, 0, 0}, + {0x4009, 0x05, 0, 0}, + {0x401a, 0x58, 0, 0}, + {0x4050, 0x00, 0, 0}, + {0x4051, 0x01, 0, 0}, + {0x4028, 0x2f, 0, 0}, + {0x4052, 0x00, 0, 0}, + {0x4053, 0x80, 0, 0}, + {0x4054, 0x00, 0, 0}, + {0x4055, 0x80, 0, 0}, + {0x4056, 0x00, 0, 0}, + {0x4057, 0x80, 0, 0}, + {0x4058, 0x00, 0, 0}, + {0x4059, 0x80, 0, 0}, + {0x430b, 0xff, 0, 0}, + {0x430c, 0xff, 0, 0}, + {0x430d, 0x00, 0, 0}, + {0x430e, 0x00, 0, 0}, + {0x4501, 0x98, 0, 0}, + {0x4502, 0x00, 0, 0}, + {0x4643, 0x00, 0, 0}, + {0x4640, 0x01, 0, 0}, + {0x4641, 0x04, 0, 0}, + {0x4800, 0x64, 0, 0}, + {0x4809, 0x2b, 0, 0}, + {0x4813, 0x90, 0, 0}, + {0x4817, 0x04, 0, 0}, + {0x4833, 0x18, 0, 0}, + {0x4837, 0x14, 0, 0}, + {0x483b, 0x00, 0, 0}, + {0x484b, 0x03, 0, 0}, + {0x4850, 0x7c, 0, 0}, + {0x4852, 0x06, 0, 0}, + {0x4856, 0x58, 0, 0}, + {0x4857, 0xaa, 0, 0}, + {0x4862, 0x0a, 0, 0}, + {0x4869, 0x18, 0, 0}, + {0x486a, 0xaa, 0, 0}, + {0x486e, 0x03, 0, 0}, + {0x486f, 0x55, 0, 0}, + {0x4875, 0xf0, 0, 0}, + {0x5000, 0x89, 0, 0}, + {0x5001, 0x42, 0, 0}, + {0x5004, 0x40, 0, 0}, + {0x5005, 0x00, 0, 0}, + {0x5180, 0x00, 0, 0}, + {0x5181, 0x10, 0, 0}, + {0x580b, 0x03, 0, 0}, + {0x4d00, 0x03, 0, 0}, + {0x4d01, 0xc9, 0, 0}, + {0x4d02, 0xbc, 0, 0}, + {0x4d03, 0xc6, 0, 0}, + {0x4d04, 0x4a, 0, 0}, + {0x4d05, 0x25, 0, 0}, + {0x4700, 0x2b, 0, 0}, + {0x4e00, 0x2b, 0, 0}, + }; + +#endif diff --git a/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_1080p_hdr.h b/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_1080p_hdr.h new file mode 100755 index 0000000..796f9e2 --- /dev/null +++ b/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_1080p_hdr.h @@ -0,0 +1,248 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OS08a20_REGS_1080PHDR_H_ +#define _VVCAM_OS08a20_REGS_1080PHDR_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t os08a20_init_setting_1080p_hdr[] = { + {0x0100, 0x00, 0, 0}, + {0x0103, 0x01, 0, 0}, + {0x0303, 0x01, 0, 0}, + {0x0305, 0x32, 0, 0}, + {0x0306, 0x00, 0, 0}, + {0x0308, 0x03, 0, 0}, + {0x0309, 0x04, 0, 0}, + {0x032a, 0x00, 0, 0}, + {0x300f, 0x11, 0, 0}, + {0x3010, 0x01, 0, 0}, + {0x3011, 0x04, 0, 0}, + {0x3012, 0x41, 0, 0}, + {0x3016, 0xf0, 0, 0}, + {0x301e, 0x98, 0, 0}, + {0x3031, 0xa9, 0, 0}, + {0x3103, 0x92, 0, 0}, + {0x3104, 0x01, 0, 0}, + {0x3106, 0x10, 0, 0}, + {0x340c, 0xff, 0, 0}, + {0x340d, 0xff, 0, 0}, + {0x031e, 0x09, 0, 0}, + {0x3501, 0x04, 0, 0}, + {0x3502, 0x62, 0, 0}, + {0x3505, 0x83, 0, 0}, + {0x3508, 0x00, 0, 0}, + {0x3509, 0x80, 0, 0}, + {0x350a, 0x04, 0, 0}, + {0x350b, 0x00, 0, 0}, + {0x350c, 0x00, 0, 0}, + {0x350d, 0x80, 0, 0}, + {0x3511, 0x04, 0, 0}, + {0x3512, 0x64, 0, 0}, + {0x350e, 0x04, 0, 0}, + {0x350f, 0x00, 0, 0}, + {0x3600, 0x09, 0, 0}, + {0x3603, 0x2c, 0, 0}, + {0x3605, 0x50, 0, 0}, + {0x3609, 0xb5, 0, 0}, + {0x3610, 0x39, 0, 0}, + {0x360c, 0x01, 0, 0}, + {0x3628, 0xa4, 0, 0}, + {0x362d, 0x10, 0, 0}, + {0x3660, 0x42, 0, 0}, + {0x3661, 0x07, 0, 0}, + {0x3662, 0x00, 0, 0}, + {0x3663, 0x28, 0, 0}, + {0x3664, 0x0d, 0, 0}, + {0x366a, 0x38, 0, 0}, + {0x366b, 0xa0, 0, 0}, + {0x366d, 0x00, 0, 0}, + {0x366e, 0x00, 0, 0}, + {0x3680, 0x00, 0, 0}, + {0x36c0, 0x00, 0, 0}, + {0x3701, 0x02, 0, 0}, + {0x373b, 0x02, 0, 0}, + {0x373c, 0x02, 0, 0}, + {0x3736, 0x02, 0, 0}, + {0x3737, 0x02, 0, 0}, + {0x3705, 0x00, 0, 0}, + {0x3706, 0x39, 0, 0}, + {0x370a, 0x00, 0, 0}, + {0x370b, 0x98, 0, 0}, + {0x3709, 0x49, 0, 0}, + {0x3714, 0x22, 0, 0}, + {0x371c, 0x00, 0, 0}, + {0x371d, 0x08, 0, 0}, + {0x3740, 0x1b, 0, 0}, + {0x3741, 0x04, 0, 0}, + {0x375e, 0x0b, 0, 0}, + {0x3760, 0x10, 0, 0}, + {0x3776, 0x10, 0, 0}, + {0x3781, 0x02, 0, 0}, + {0x3782, 0x04, 0, 0}, + {0x3783, 0x02, 0, 0}, + {0x3784, 0x08, 0, 0}, + {0x3785, 0x08, 0, 0}, + {0x3788, 0x01, 0, 0}, + {0x3789, 0x01, 0, 0}, + {0x3797, 0x04, 0, 0}, + {0x3762, 0x11, 0, 0}, + {0x3800, 0x00, 0, 0}, + {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, + {0x3803, 0x0c, 0, 0}, + {0x3804, 0x0e, 0, 0}, + {0x3805, 0xff, 0, 0}, + {0x3806, 0x08, 0, 0}, + {0x3807, 0x6f, 0, 0}, + {0x3808, 0x07, 0, 0}, + {0x3809, 0x80, 0, 0}, + {0x380a, 0x04, 0, 0}, + {0x380b, 0x38, 0, 0}, + {0x380c, 0x08, 0, 0}, + {0x380d, 0x04, 0, 0}, + {0x380e, 0x04, 0, 0}, + {0x380f, 0x92, 0, 0}, + {0x3813, 0x08, 0, 0}, + {0x3814, 0x03, 0, 0}, + {0x3815, 0x01, 0, 0}, + {0x3816, 0x03, 0, 0}, + {0x3817, 0x01, 0, 0}, + {0x381c, 0x08, 0, 0}, + {0x3820, 0x05, 0, 0}, + {0x3821, 0x21, 0, 0}, + {0x3823, 0x08, 0, 0}, + {0x3826, 0x00, 0, 0}, + {0x3827, 0x08, 0, 0}, + {0x382d, 0x08, 0, 0}, + {0x3832, 0x02, 0, 0}, + {0x3833, 0x01, 0, 0}, + {0x383c, 0x48, 0, 0}, + {0x383d, 0xff, 0, 0}, + {0x3d85, 0x0b, 0, 0}, + {0x3d84, 0x40, 0, 0}, + {0x3d8c, 0x63, 0, 0}, + {0x3d8d, 0xd7, 0, 0}, + {0x4000, 0xf8, 0, 0}, + {0x4001, 0x2b, 0, 0}, + {0x4004, 0x00, 0, 0}, + {0x4005, 0x40, 0, 0}, + {0x400a, 0x01, 0, 0}, + {0x400f, 0xa0, 0, 0}, + {0x4010, 0x12, 0, 0}, + {0x4018, 0x00, 0, 0}, + {0x4008, 0x02, 0, 0}, + {0x4009, 0x05, 0, 0}, + {0x401a, 0x58, 0, 0}, + {0x4050, 0x00, 0, 0}, + {0x4051, 0x01, 0, 0}, + {0x4028, 0x2f, 0, 0}, + {0x4052, 0x00, 0, 0}, + {0x4053, 0x80, 0, 0}, + {0x4054, 0x00, 0, 0}, + {0x4055, 0x80, 0, 0}, + {0x4056, 0x00, 0, 0}, + {0x4057, 0x80, 0, 0}, + {0x4058, 0x00, 0, 0}, + {0x4059, 0x80, 0, 0}, + {0x430b, 0xff, 0, 0}, + {0x430c, 0xff, 0, 0}, + {0x430d, 0x00, 0, 0}, + {0x430e, 0x00, 0, 0}, + {0x4501, 0x98, 0, 0}, + {0x4502, 0x00, 0, 0}, + {0x4643, 0x00, 0, 0}, + {0x4640, 0x01, 0, 0}, + {0x4641, 0x04, 0, 0}, + {0x4800, 0x64, 0, 0}, + {0x4809, 0x2b, 0, 0}, + {0x4813, 0x98, 0, 0}, + {0x4817, 0x04, 0, 0}, + {0x4833, 0x18, 0, 0}, + {0x4837, 0x14, 0, 0}, + {0x483b, 0x00, 0, 0}, + {0x484b, 0x03, 0, 0}, + {0x4850, 0x7c, 0, 0}, + {0x4852, 0x06, 0, 0}, + {0x4856, 0x58, 0, 0}, + {0x4857, 0xaa, 0, 0}, + {0x4862, 0x0a, 0, 0}, + {0x4869, 0x18, 0, 0}, + {0x486a, 0xaa, 0, 0}, + {0x486e, 0x07, 0, 0}, + {0x486f, 0x55, 0, 0}, + {0x4875, 0xf0, 0, 0}, + {0x5000, 0x89, 0, 0}, + {0x5001, 0x42, 0, 0}, + {0x5004, 0x40, 0, 0}, + {0x5005, 0x00, 0, 0}, + {0x5180, 0x00, 0, 0}, + {0x5181, 0x10, 0, 0}, + {0x580b, 0x03, 0, 0}, + {0x4d00, 0x03, 0, 0}, + {0x4d01, 0xc9, 0, 0}, + {0x4d02, 0xbc, 0, 0}, + {0x4d03, 0xc6, 0, 0}, + {0x4d04, 0x4a, 0, 0}, + {0x4d05, 0x25, 0, 0}, + {0x4700, 0x2b, 0, 0}, + {0x4e00, 0x2b, 0, 0}, + {0x3501, 0x04, 0, 0}, + {0x3502, 0x5d, 0, 0}, + {0x3511, 0x00, 0, 0}, + {0x3512, 0x20, 0, 0}, + {0x3833, 0x01, 0, 0}, +}; + +#endif diff --git a/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_4k.h b/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_4k.h new file mode 100755 index 0000000..3229edc --- /dev/null +++ b/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_4k.h @@ -0,0 +1,255 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OS08a20_REGS_4K_H_ +#define _VVCAM_OS08a20_REGS_4K_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t os08a20_init_setting_4k[] = { + {0x0100, 0x00, 0, 0}, + {0x0001, 0xf2, 0, 0}, + {0x0103, 0x01, 0, 0}, + {0x0303, 0x01, 0, 0}, + {0x0305, 0x5a, 0, 0}, + {0x0306, 0x00, 0, 0}, + {0x0308, 0x03, 0, 0}, + {0x0309, 0x04, 0, 0}, + {0x032a, 0x00, 0, 0}, + {0x300f, 0x11, 0, 0}, + {0x3010, 0x01, 0, 0}, + {0x3011, 0x04, 0, 0}, + {0x3012, 0x41, 0, 0}, + {0x3016, 0xf0, 0, 0}, + {0x301e, 0x98, 0, 0}, + {0x3031, 0xa9, 0, 0}, + {0x3103, 0x92, 0, 0}, + {0x3104, 0x01, 0, 0}, + {0x3106, 0x10, 0, 0}, + {0x3400, 0x04, 0, 0}, + {0x3025, 0x03, 0, 0}, + {0x3425, 0x01, 0, 0}, + {0x3428, 0x01, 0, 0}, + {0x3406, 0x08, 0, 0}, + {0x3408, 0x03, 0, 0}, + {0x340c, 0xff, 0, 0}, + {0x340d, 0xff, 0, 0}, + {0x031e, 0x0a, 0, 0}, + {0x3501, 0x08, 0, 0}, + {0x3502, 0xe5, 0, 0}, + {0x3505, 0x83, 0, 0}, + {0x3508, 0x00, 0, 0}, + {0x3509, 0x80, 0, 0}, + {0x350a, 0x04, 0, 0}, + {0x350b, 0x00, 0, 0}, + {0x350c, 0x00, 0, 0}, + {0x350d, 0x80, 0, 0}, + {0x350e, 0x04, 0, 0}, + {0x350f, 0x00, 0, 0}, + {0x3600, 0x00, 0, 0}, + {0x3603, 0x2c, 0, 0}, + {0x3605, 0x50, 0, 0}, + {0x3609, 0xdb, 0, 0}, + {0x3610, 0x39, 0, 0}, + {0x360c, 0x01, 0, 0}, + {0x3628, 0xa4, 0, 0}, + {0x362d, 0x10, 0, 0}, + {0x3660, 0xd3, 0, 0}, + {0x3661, 0x06, 0, 0}, + {0x3662, 0x00, 0, 0}, + {0x3663, 0x28, 0, 0}, + {0x3664, 0x0d, 0, 0}, + {0x366a, 0x38, 0, 0}, + {0x366b, 0xa0, 0, 0}, + {0x366d, 0x00, 0, 0}, + {0x366e, 0x00, 0, 0}, + {0x3680, 0x00, 0, 0}, + {0x36c0, 0x00, 0, 0}, + {0x3701, 0x02, 0, 0}, + {0x373b, 0x02, 0, 0}, + {0x373c, 0x02, 0, 0}, + {0x3736, 0x02, 0, 0}, + {0x3737, 0x02, 0, 0}, + {0x3705, 0x00, 0, 0}, + {0x3706, 0x72, 0, 0}, + {0x370a, 0x01, 0, 0}, + {0x370b, 0x30, 0, 0}, + {0x3709, 0x48, 0, 0}, + {0x3714, 0x21, 0, 0}, + {0x371c, 0x00, 0, 0}, + {0x371d, 0x08, 0, 0}, + {0x3740, 0x1b, 0, 0}, + {0x3741, 0x04, 0, 0}, + {0x375e, 0x0b, 0, 0}, + {0x3760, 0x10, 0, 0}, + {0x3776, 0x10, 0, 0}, + {0x3781, 0x02, 0, 0}, + {0x3782, 0x04, 0, 0}, + {0x3783, 0x02, 0, 0}, + {0x3784, 0x08, 0, 0}, + {0x3785, 0x08, 0, 0}, + {0x3788, 0x01, 0, 0}, + {0x3789, 0x01, 0, 0}, + {0x3797, 0x04, 0, 0}, + {0x3762, 0x11, 0, 0}, + {0x3800, 0x00, 0, 0}, + {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, + {0x3803, 0x0c, 0, 0}, + {0x3804, 0x0e, 0, 0}, + {0x3805, 0xff, 0, 0}, + {0x3806, 0x08, 0, 0}, + {0x3807, 0x6f, 0, 0}, + {0x3808, 0x0f, 0, 0}, + {0x3809, 0x00, 0, 0}, + {0x380a, 0x08, 0, 0}, + {0x380b, 0x70, 0, 0}, + {0x380c, 0x08, 0, 0}, /* hts_h */ + {0x380d, 0x04, 0, 0}, /* hts_l */ + {0x380e, 0x0D, 0, 0}, /* vts_h */ + {0x380f, 0x8F, 0, 0}, /* vts_l */ + {0x3813, 0x10, 0, 0}, + {0x3814, 0x01, 0, 0}, + {0x3815, 0x01, 0, 0}, + {0x3816, 0x01, 0, 0}, + {0x3817, 0x01, 0, 0}, + {0x381c, 0x00, 0, 0}, + {0x3820, 0x04, 0, 0}, + {0x3821, 0x00, 0, 0}, + {0x3823, 0x08, 0, 0}, + {0x3826, 0x00, 0, 0}, + {0x3827, 0x08, 0, 0}, + {0x382d, 0x08, 0, 0}, + {0x3832, 0x02, 0, 0}, + {0x3833, 0x00, 0, 0}, + {0x383c, 0x48, 0, 0}, + {0x383d, 0xff, 0, 0}, + {0x3d85, 0x0b, 0, 0}, + {0x3d84, 0x40, 0, 0}, + {0x3d8c, 0x63, 0, 0}, + {0x3d8d, 0xd7, 0, 0}, + {0x4000, 0xf8, 0, 0}, + {0x4001, 0x2b, 0, 0}, + {0x4004, 0x00, 0, 0}, + {0x4005, 0x40, 0, 0}, + {0x400a, 0x01, 0, 0}, + {0x400f, 0xa0, 0, 0}, + {0x4010, 0x12, 0, 0}, + {0x4018, 0x00, 0, 0}, + {0x4008, 0x02, 0, 0}, + {0x4009, 0x0d, 0, 0}, + {0x401a, 0x58, 0, 0}, + {0x4050, 0x00, 0, 0}, + {0x4051, 0x01, 0, 0}, + {0x4028, 0x2f, 0, 0}, + {0x4052, 0x00, 0, 0}, + {0x4053, 0x80, 0, 0}, + {0x4054, 0x00, 0, 0}, + {0x4055, 0x80, 0, 0}, + {0x4056, 0x00, 0, 0}, + {0x4057, 0x80, 0, 0}, + {0x4058, 0x00, 0, 0}, + {0x4059, 0x80, 0, 0}, + {0x430b, 0xff, 0, 0}, + {0x430c, 0xff, 0, 0}, + {0x430d, 0x00, 0, 0}, + {0x430e, 0x00, 0, 0}, + {0x4501, 0x18, 0, 0}, + {0x4502, 0x00, 0, 0}, + {0x4600, 0x00, 0, 0}, + {0x4601, 0x20, 0, 0}, + {0x4603, 0x01, 0, 0}, + {0x4643, 0x00, 0, 0}, + {0x4640, 0x01, 0, 0}, + {0x4641, 0x04, 0, 0}, + {0x4800, 0x64, 0, 0}, + {0x4809, 0x2b, 0, 0}, + {0x4813, 0x90, 0, 0}, + {0x4817, 0x04, 0, 0}, + {0x4833, 0x18, 0, 0}, + {0x4837, 0x0b, 0, 0}, + {0x483b, 0x00, 0, 0}, + {0x484b, 0x03, 0, 0}, + {0x4850, 0x7c, 0, 0}, + {0x4852, 0x06, 0, 0}, + {0x4856, 0x58, 0, 0}, + {0x4857, 0xaa, 0, 0}, + {0x4862, 0x0a, 0, 0}, + {0x4869, 0x18, 0, 0}, + {0x486a, 0xaa, 0, 0}, + {0x486e, 0x03, 0, 0}, + {0x486f, 0x55, 0, 0}, + {0x4875, 0xf0, 0, 0}, + {0x5000, 0x89, 0, 0}, + {0x5001, 0x42, 0, 0}, + {0x5004, 0x40, 0, 0}, + {0x5005, 0x00, 0, 0}, + {0x5180, 0x00, 0, 0}, + {0x5181, 0x10, 0, 0}, + {0x580b, 0x03, 0, 0}, + {0x4d00, 0x03, 0, 0}, + {0x4d01, 0xc9, 0, 0}, + {0x4d02, 0xbc, 0, 0}, + {0x4d03, 0xc6, 0, 0}, + {0x4d04, 0x4a, 0, 0}, + {0x4d05, 0x25, 0, 0}, + {0x4700, 0x2b, 0, 0}, + {0x4e00, 0x2b, 0, 0}, + {0x3501, 0x09, 0, 0}, + {0x3502, 0x01, 0, 0}, + {0x0100, 0x01, 0, 0}, +}; + +#endif + diff --git a/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_4k_hdr.h b/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_4k_hdr.h new file mode 100755 index 0000000..ad0019f --- /dev/null +++ b/vvcam_ry/v4l2/sensor/os08a20/os08a20_regs_4k_hdr.h @@ -0,0 +1,258 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OS08a20_REGS_4kPHDR_H_ +#define _VVCAM_OS08a20_REGS_4kPHDR_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t os08a20_init_setting_4k_hdr[] = { + {0x0100, 0x00, 0, 0}, + {0x0103, 0x01, 0, 0}, + + {0x030c, 0x00, 0, 0}, + {0x0303, 0x01, 0, 0}, + {0x0304, 0x00, 0, 0}, + {0x0305, 0x5a, 0, 0}, + {0x0306, 0x00, 0, 0}, + {0x0307, 0x00, 0, 0}, + {0x0308, 0x03, 0, 0}, + {0x0309, 0x04, 0, 0}, + {0x301e, 0x98, 0, 0}, + + {0x032a, 0x00, 0, 0}, + {0x300f, 0x11, 0, 0}, + {0x3010, 0x01, 0, 0}, + {0x3011, 0x04, 0, 0}, + {0x3012, 0x41, 0, 0}, + {0x3016, 0xf0, 0, 0}, + {0x3031, 0xa9, 0, 0}, + {0x3103, 0x92, 0, 0}, + {0x3104, 0x01, 0, 0}, + {0x3106, 0x10, 0, 0}, + {0x340c, 0xff, 0, 0}, + {0x340d, 0xff, 0, 0}, + {0x031e, 0x09, 0, 0}, + {0x3501, 0x08, 0, 0}, + {0x3502, 0xe5, 0, 0}, + {0x3505, 0x83, 0, 0}, + {0x3508, 0x00, 0, 0}, + {0x3509, 0x80, 0, 0}, + {0x350a, 0x04, 0, 0}, + {0x350b, 0x00, 0, 0}, + {0x350c, 0x00, 0, 0}, + {0x350d, 0x80, 0, 0}, + {0x350e, 0x04, 0, 0}, + {0x350f, 0x00, 0, 0}, + {0x3600, 0x00, 0, 0}, + {0x3603, 0x2c, 0, 0}, + {0x3605, 0x50, 0, 0}, + {0x3609, 0xb5, 0, 0}, + {0x3610, 0x39, 0, 0}, + {0x360c, 0x01, 0, 0}, + {0x3628, 0xa4, 0, 0}, + {0x362d, 0x10, 0, 0}, + {0x3660, 0x42, 0, 0}, + {0x3661, 0x07, 0, 0}, + {0x3662, 0x00, 0, 0}, + {0x3663, 0x28, 0, 0}, + {0x3664, 0x0d, 0, 0}, + {0x366a, 0x38, 0, 0}, + {0x366b, 0xa0, 0, 0}, + {0x366d, 0x00, 0, 0}, + {0x366e, 0x00, 0, 0}, + {0x3680, 0x00, 0, 0}, + {0x36c0, 0x00, 0, 0}, + {0x3701, 0x02, 0, 0}, + {0x373b, 0x02, 0, 0}, + {0x373c, 0x02, 0, 0}, + {0x3736, 0x02, 0, 0}, + {0x3737, 0x02, 0, 0}, + {0x3705, 0x00, 0, 0}, + {0x3706, 0x39, 0, 0}, + {0x370a, 0x00, 0, 0}, + {0x370b, 0x98, 0, 0}, + {0x3709, 0x49, 0, 0}, + {0x3714, 0x21, 0, 0}, + {0x371c, 0x00, 0, 0}, + {0x371d, 0x08, 0, 0}, + {0x3740, 0x1b, 0, 0}, + {0x3741, 0x04, 0, 0}, + {0x375e, 0x0b, 0, 0}, + {0x3760, 0x10, 0, 0}, + {0x3776, 0x10, 0, 0}, + {0x3781, 0x02, 0, 0}, + {0x3782, 0x04, 0, 0}, + {0x3783, 0x02, 0, 0}, + {0x3784, 0x08, 0, 0}, + {0x3785, 0x08, 0, 0}, + {0x3788, 0x01, 0, 0}, + {0x3789, 0x01, 0, 0}, + {0x3797, 0x04, 0, 0}, + {0x3762, 0x11, 0, 0}, + {0x3800, 0x00, 0, 0}, + {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, + {0x3803, 0x0c, 0, 0}, + {0x3804, 0x0e, 0, 0}, + {0x3805, 0xff, 0, 0}, + {0x3806, 0x08, 0, 0}, + {0x3807, 0x6f, 0, 0}, + {0x3808, 0x0f, 0, 0}, + {0x3809, 0x00, 0, 0}, + {0x380a, 0x08, 0, 0}, + {0x380b, 0x70, 0, 0}, + {0x380c, 0x08, 0, 0}, + {0x380d, 0x04, 0, 0}, + {0x380e, 0x09, 0, 0}, + {0x380f, 0x24, 0, 0}, + {0x3813, 0x10, 0, 0}, + {0x3814, 0x01, 0, 0}, + {0x3815, 0x01, 0, 0}, + {0x3816, 0x01, 0, 0}, + {0x3817, 0x01, 0, 0}, + {0x381c, 0x08, 0, 0}, + {0x3820, 0x04, 0, 0}, + {0x3821, 0x20, 0, 0}, + {0x3823, 0x08, 0, 0}, + {0x3826, 0x00, 0, 0}, + {0x3827, 0x08, 0, 0}, + {0x382d, 0x08, 0, 0}, + {0x3832, 0x02, 0, 0}, + {0x3833, 0x00, 0, 0}, + {0x383c, 0x48, 0, 0}, + {0x383d, 0xff, 0, 0}, + {0x3d85, 0x0b, 0, 0}, + {0x3d84, 0x40, 0, 0}, + {0x3d8c, 0x63, 0, 0}, + {0x3d8d, 0xd7, 0, 0}, + {0x4000, 0xf8, 0, 0}, + {0x4001, 0x2b, 0, 0}, + {0x4004, 0x00, 0, 0}, + {0x4005, 0x40, 0, 0}, + {0x400a, 0x01, 0, 0}, + {0x400f, 0xa0, 0, 0}, + {0x4010, 0x12, 0, 0}, + {0x4018, 0x00, 0, 0}, + {0x4008, 0x02, 0, 0}, + {0x4009, 0x0d, 0, 0}, + {0x401a, 0x58, 0, 0}, + {0x4050, 0x00, 0, 0}, + {0x4051, 0x01, 0, 0}, + {0x4028, 0x2f, 0, 0}, + {0x4052, 0x00, 0, 0}, + {0x4053, 0x80, 0, 0}, + {0x4054, 0x00, 0, 0}, + {0x4055, 0x80, 0, 0}, + {0x4056, 0x00, 0, 0}, + {0x4057, 0x80, 0, 0}, + {0x4058, 0x00, 0, 0}, + {0x4059, 0x80, 0, 0}, + {0x430b, 0xff, 0, 0}, + {0x430c, 0xff, 0, 0}, + {0x430d, 0x00, 0, 0}, + {0x430e, 0x00, 0, 0}, + {0x4501, 0x18, 0, 0}, + {0x4502, 0x00, 0, 0}, + {0x4643, 0x00, 0, 0}, + {0x4640, 0x01, 0, 0}, + {0x4641, 0x04, 0, 0}, + {0x4800, 0x64, 0, 0}, + {0x4809, 0x2b, 0, 0}, + {0x4813, 0x98, 0, 0}, + {0x4817, 0x04, 0, 0}, + {0x4833, 0x18, 0, 0}, + {0x4837, 0x0b, 0, 0}, + {0x483b, 0x00, 0, 0}, + {0x484b, 0x03, 0, 0}, + {0x4850, 0x7c, 0, 0}, + {0x4852, 0x06, 0, 0}, + {0x4856, 0x58, 0, 0}, + {0x4857, 0xaa, 0, 0}, + {0x4862, 0x0a, 0, 0}, + {0x4869, 0x18, 0, 0}, + {0x486a, 0xaa, 0, 0}, + {0x486e, 0x07, 0, 0}, + {0x486f, 0x55, 0, 0}, + {0x4875, 0xf0, 0, 0}, + {0x5000, 0x09, 0, 0}, + {0x5001, 0x42, 0, 0}, + {0x5004, 0x40, 0, 0}, + {0x5005, 0x00, 0, 0}, + {0x5180, 0x00, 0, 0}, + {0x5181, 0x10, 0, 0}, + {0x580b, 0x03, 0, 0}, + {0x4d00, 0x03, 0, 0}, + {0x4d01, 0xc9, 0, 0}, + {0x4d02, 0xbc, 0, 0}, + {0x4d03, 0xc6, 0, 0}, + {0x4d04, 0x4a, 0, 0}, + {0x4d05, 0x25, 0, 0}, + {0x4700, 0x2b, 0, 0}, + {0x4e00, 0x2b, 0, 0}, + {0x3501, 0x04, 0, 0}, + {0x3502, 0xb0, 0, 0}, + {0x3508, 0x00, 0, 0}, + {0x3509, 0x80, 0, 0}, + {0x350a, 0x00, 0, 0}, + {0x350b, 0x80, 0, 0}, + {0x3511, 0x00, 0, 0}, + {0x3512, 0x3c, 0, 0}, + {0x350c, 0x06, 0, 0}, + {0x350d, 0x00, 0, 0}, + {0x350e, 0x00, 0, 0}, + {0x350f, 0x80, 0, 0}, +}; + +#endif diff --git a/vvcam_ry/v4l2/sensor/ov2775/Makefile b/vvcam_ry/v4l2/sensor/ov2775/Makefile new file mode 100755 index 0000000..1f4b2ee --- /dev/null +++ b/vvcam_ry/v4l2/sensor/ov2775/Makefile @@ -0,0 +1,3 @@ +EXTRA_CFLAGS += -I$(PWD)/../common/ -O2 -Wall +ov2775-objs += ov2775_mipi_v3.o +obj-m += ov2775.o diff --git a/vvcam_ry/v4l2/sensor/ov2775/ov2775_mipi_v3.c b/vvcam_ry/v4l2/sensor/ov2775/ov2775_mipi_v3.c new file mode 100755 index 0000000..5546de6 --- /dev/null +++ b/vvcam_ry/v4l2/sensor/ov2775/ov2775_mipi_v3.c @@ -0,0 +1,1903 @@ +/* + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2018 NXP + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vvsensor.h" + +#include "ov2775_regs_1080p.h" +#include "ov2775_regs_1080p_hdr.h" +#include "ov2775_regs_1080p_hdr_low_freq.h" +#include "ov2775_regs_720p.h" +#include "ov2775_regs_1080p_native_hdr.h" + +#define OV2775_VOLTAGE_ANALOG 2800000 +#define OV2775_VOLTAGE_DIGITAL_CORE 1500000 +#define OV2775_VOLTAGE_DIGITAL_IO 1800000 + +#define OV2775_XCLK_MIN 6000000 +#define OV2775_XCLK_MAX 24000000 + +#define OV2775_CHIP_ID_HIGH_BYTE 0x300A +#define OV2775_CHIP_ID_LOW_BYTE 0x300B + +#define OV2775_SENS_PAD_SOURCE 0 +#define OV2775_SENS_PADS_NUM 1 + +struct ov2775_datafmt { + u32 code; + enum v4l2_colorspace colorspace; +}; + +struct ov2775 { + struct regulator *io_regulator; + struct regulator *core_regulator; + struct regulator *analog_regulator; + struct v4l2_subdev subdev; + struct v4l2_device *v4l2_dev; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + const struct ov2775_datafmt *fmt; + struct v4l2_captureparm streamcap; + struct media_pad pads[OV2775_SENS_PADS_NUM]; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + u32 mclk; + u8 mclk_source; + u32 sclk; + struct clk *sensor_clk; + int csi; + + void (*io_init) (struct ov2775 *); + int pwn_gpio, rst_gpio; + int hdr; + int fps; + vvcam_mode_info_t cur_mode; + sensor_blc_t blc; + sensor_white_balance_t wb; + struct mutex lock; +}; + +#define client_to_ov2775(client)\ + container_of(i2c_get_clientdata(client), struct ov2775, subdev) + +long ov2775_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg); +static void ov2775_stop(struct ov2775 *sensor); +s32 ov2775_write_reg(struct ov2775 *sensor, u16 reg, u8 val); + +static struct vvcam_mode_info pov2775_mode_info[] = { + { + .index = 0, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 12, + .data_compress.enable = 0, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x466, + .one_line_exp_time_ns = 29625, + .max_integration_time = 0x466 - 2, + .min_integration_time = 1, + .gain_accuracy = 1024, + .max_gain = 21 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = ov2775_init_setting_1080p, + .reg_data_count = ARRAY_SIZE(ov2775_init_setting_1080p), + }, + { + .index = 1, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_DUAL_DCG, + .bit_width = 12, + .data_compress.enable = 0, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x466, + .one_line_exp_time_ns = 59167, + .max_integration_time = 0x466 - 64 - 2, + .min_integration_time = 1, + .gain_accuracy = 1024, + .max_gain = 21 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = ov2775_init_setting_1080p_hdr, + .reg_data_count = ARRAY_SIZE(ov2775_init_setting_1080p_hdr), + }, + { + .index = 2, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_NATIVE, + .bit_width = 12, + .data_compress.enable = 1, + .data_compress.x_bit = 16, + .data_compress.y_bit = 12, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x466, + .one_line_exp_time_ns = 59167, + .max_integration_time = 0x466 - 2, + .min_integration_time = 1, + .gain_accuracy = 1024, + .max_gain = 21 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = ov2775_1080p_native_hdr_regs, + .reg_data_count = ARRAY_SIZE(ov2775_1080p_native_hdr_regs), + }, + { + .index = 3, + .width = 1280, + .height = 720, + .fps = 60, + .hdr_mode = SENSOR_MODE_LINEAR, + .bit_width = 12, + .data_compress.enable = 0, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x466, + .one_line_exp_time_ns = 29583, + .max_integration_time = 0x466 - 2, + .min_integration_time = 1, + .gain_accuracy = 1024, + .max_gain = 21 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = ov2775_init_setting_720p, + .reg_data_count = ARRAY_SIZE(ov2775_init_setting_720p), + }, + { + .index = 4, + .width = 1920, + .height = 1080, + .fps = 30, + .hdr_mode = SENSOR_MODE_HDR_STITCH, + .stitching_mode = SENSOR_STITCHING_DUAL_DCG, + .bit_width = 12, + .data_compress.enable = 0, + .bayer_pattern = BAYER_BGGR, + .ae_info = { + .DefaultFrameLengthLines = 0x466, + .one_line_exp_time_ns = 59167, + .max_integration_time = 0x466 - 64 - 2, + .min_integration_time = 1, + .gain_accuracy = 1024, + .max_gain = 21 * 1024, + .min_gain = 1 * 1024, + }, + .preg_data = ov2775_init_setting_1080p_hdr_low_freq, + .reg_data_count = ARRAY_SIZE(ov2775_init_setting_1080p_hdr_low_freq), + }, +}; + +static int ov2775_probe(struct i2c_client *adapter, + const struct i2c_device_id *device_id); +static int ov2775_remove(struct i2c_client *client); +static void ov2775_stop(struct ov2775 *sensor); + +static const struct i2c_device_id ov2775_id[] = { + {"ov2775", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov2775_id); + +static int __maybe_unused ov2775_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct ov2775 *sensor = client_to_ov2775(client); + + if (sensor->on) { + ov2775_stop(sensor); + } + + return 0; +} + +static int __maybe_unused ov2775_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct ov2775 *sensor = client_to_ov2775(client); + + if (sensor->on) { + ov2775_write_reg(sensor, 0x3012, 0x01); + } + return 0; +} + + +static const struct dev_pm_ops ov2775_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(ov2775_suspend, ov2775_resume) +}; + +static const struct of_device_id ov2775_dt_ids[] = { + { .compatible = "ovti,ov2775" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ov2775_dt_ids); + +static struct i2c_driver ov2775_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov2775", + .pm = &ov2775_pm_ops, + .of_match_table = ov2775_dt_ids, + }, + .probe = ov2775_probe, + .remove = ov2775_remove, + .id_table = ov2775_id, +}; + +#if 0 +static const struct ov2775_datafmt ov2775_colour_fmts[] = { + {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG}, + {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG}, +}; +#else +static const struct ov2775_datafmt ov2775_colour_fmts[] = { + {MEDIA_BUS_FMT_SBGGR12_1X12, V4L2_COLORSPACE_JPEG}, +}; +#endif + +#if 0 +static enum ov2775_frame_rate to_ov2775_frame_rate(struct v4l2_fract + *timeperframe) +{ + enum ov2775_frame_rate rate; + u32 tgt_fps; /* target frames per secound */ + + pr_info("enter %s\n", __func__); + tgt_fps = timeperframe->denominator / timeperframe->numerator; + + if (tgt_fps == 30) + rate = ov2775_30_fps; + else if (tgt_fps == 15) + rate = ov2775_15_fps; + else + rate = -EINVAL; + + return rate; +} +#endif + +/* Find a data format by a pixel code in an array */ +static const struct ov2775_datafmt +*ov2775_find_datafmt(u32 code) +{ + int i; + + pr_debug("enter %s\n", __func__); + for (i = 0; i < ARRAY_SIZE(ov2775_colour_fmts); i++) + if (ov2775_colour_fmts[i].code == code) + return ov2775_colour_fmts + i; + + return NULL; +} + +static inline void ov2775_power_up(struct ov2775 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (!gpio_is_valid(sensor->pwn_gpio)) + return; + + gpio_set_value_cansleep(sensor->pwn_gpio, 1); +} + +static inline void ov2775_power_down(struct ov2775 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (!gpio_is_valid(sensor->pwn_gpio)) + return; + + gpio_set_value_cansleep(sensor->pwn_gpio, 0); +} + +static inline void ov2775_reset(struct ov2775 *sensor) +{ + pr_debug("enter %s\n", __func__); + if (!gpio_is_valid(sensor->rst_gpio)) + return; + + gpio_set_value_cansleep(sensor->rst_gpio, 0); + msleep(20); + + gpio_set_value_cansleep(sensor->rst_gpio, 1); + msleep(20); +} + +static int ov2775_regulator_enable(struct ov2775 *sensor) +{ + int ret = 0; + struct device *dev = &(sensor->i2c_client->dev); + + pr_debug("enter %s\n", __func__); + + if (sensor->io_regulator) + { + regulator_set_voltage(sensor->io_regulator, + OV2775_VOLTAGE_DIGITAL_IO, + OV2775_VOLTAGE_DIGITAL_IO); + ret = regulator_enable(sensor->io_regulator); + if (ret < 0) { + dev_err(dev, "set io voltage failed\n"); + return ret; + } + } + + if (sensor->analog_regulator) + { + regulator_set_voltage(sensor->analog_regulator, + OV2775_VOLTAGE_ANALOG, + OV2775_VOLTAGE_ANALOG); + ret = regulator_enable(sensor->analog_regulator); + if (ret) + { + dev_err(dev, "set analog voltage failed\n"); + goto err_disable_io; + } + + } + + if (sensor->core_regulator) + { + regulator_set_voltage(sensor->core_regulator, + OV2775_VOLTAGE_DIGITAL_CORE, + OV2775_VOLTAGE_DIGITAL_CORE); + ret = regulator_enable(sensor->core_regulator); + if (ret) { + dev_err(dev, "set core voltage failed\n"); + goto err_disable_analog; + } + } + + return 0; + +err_disable_analog: + regulator_disable(sensor->analog_regulator); +err_disable_io: + regulator_disable(sensor->io_regulator); + return ret; +} + +static void ov2775_regulator_disable(struct ov2775 *sensor) +{ + int ret = 0; + struct device *dev = &(sensor->i2c_client->dev); + + if (sensor->core_regulator) + { + ret = regulator_disable(sensor->core_regulator); + if (ret < 0) + dev_err(dev, "core regulator disable failed\n"); + } + + if (sensor->analog_regulator) + { + ret = regulator_disable(sensor->analog_regulator); + if (ret < 0) + dev_err(dev, "analog regulator disable failed\n"); + } + + if (sensor->io_regulator) + { + ret = regulator_disable(sensor->io_regulator); + if (ret < 0) + dev_err(dev, "io regulator disable failed\n"); + } + return ; +} + +s32 ov2775_write_reg(struct ov2775 *sensor, u16 reg, u8 val) +{ + struct device *dev = &sensor->i2c_client->dev; + u8 au8Buf[3] = { 0 }; + + au8Buf[0] = reg >> 8; + au8Buf[1] = reg & 0xff; + au8Buf[2] = val; + + if (i2c_master_send(sensor->i2c_client, au8Buf, 3) < 0) { + dev_err(dev, "Write reg error: reg=%x, val=%x\n", reg, val); + return -1; + } + + return 0; +} + +s32 ov2775_read_reg(struct ov2775 *sensor, u16 reg, u8 *val) +{ + struct device *dev = &sensor->i2c_client->dev; + u8 au8RegBuf[2] = { 0 }; + u8 u8RdVal = 0; + + au8RegBuf[0] = reg >> 8; + au8RegBuf[1] = reg & 0xff; + + if (i2c_master_send(sensor->i2c_client, au8RegBuf, 2) != 2) { + dev_err(dev, "Read reg error: reg=%x\n", reg); + return -1; + } + + if (i2c_master_recv(sensor->i2c_client, &u8RdVal, 1) != 1) { + dev_err(dev, "Read reg error: reg=%x, val=%x\n", reg, u8RdVal); + return -1; + } + + *val = u8RdVal; + + return u8RdVal; +} + +static int ov2775_set_clk_rate(struct ov2775 *sensor) +{ + u32 tgt_xclk; /* target xclk */ + int ret; + + /* mclk */ + tgt_xclk = sensor->mclk; + tgt_xclk = min_t(u32, tgt_xclk, (u32) OV2775_XCLK_MAX); + tgt_xclk = max_t(u32, tgt_xclk, (u32) OV2775_XCLK_MIN); + sensor->mclk = tgt_xclk; + + pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); + ret = clk_set_rate(sensor->sensor_clk, sensor->mclk); + if (ret < 0) + pr_debug("set rate filed, rate=%d\n", sensor->mclk); + return ret; +} + +/* download ov2775 settings to sensor through i2c */ +static int ov2775_download_firmware(struct ov2775 *sensor, + struct vvsensor_reg_value_t *mode_setting, + s32 size) +{ + register u32 delay_ms = 0; + register u16 reg_addr = 0; + register u8 mask = 0; + register u8 val = 0; + u8 reg_val = 0; + int i, retval = 0; + + pr_debug("enter %s\n", __func__); + for (i = 0; i < size; ++i, ++mode_setting) { + delay_ms = mode_setting->delay; + reg_addr = mode_setting->addr; + val = mode_setting->val; + mask = mode_setting->mask; + + if (mask) { + retval = ov2775_read_reg(sensor, reg_addr, ®_val); + if (retval < 0) + break; + + reg_val &= ~(u8)mask; + val &= mask; + val |= reg_val; + } + + retval = ov2775_write_reg(sensor, reg_addr, val); + if (retval < 0) + break; + + if (delay_ms) + msleep(delay_ms); + } + + return retval; +} + +static void ov2775_start(struct ov2775 *sensor) +{ + pr_debug("enter %s\n", __func__); +#if 1 + ov2775_write_reg(sensor, 0x3012, 0x01); +#else + ov2775_write_reg(sensor, 0x3008, 0x02); + ov2775_write_reg(sensor, 0x4202, 0x00); +#endif + /* Color bar control */ + /* ov2775_write_reg(sensor, 0x503d, 0x80); */ + + /* skip the first three frame for 30fps */ + msleep(100); +} + +#if 0 +static int ov2775_change_mode(struct ov2775 *sensor) +{ + struct reg_value *mode_setting = NULL; + enum ov2775_mode mode = sensor->streamcap.capturemode; + enum ov2775_frame_rate frame_rate = + to_ov2775_frame_rate(&sensor->streamcap.timeperframe); + int ArySize = 0, retval = 0; + + pr_debug("enter %s\n", __func__); + if (mode > ov2775_mode_MAX || mode < ov2775_mode_MIN) { + pr_err("Wrong ov2775 mode detected!\n"); + return -1; + } + + mode_setting = ov2775_mode_info_data[frame_rate][mode].init_data_ptr; + ArySize = ov2775_mode_info_data[frame_rate][mode].init_data_size; + + sensor->pix.width = ov2775_mode_info_data[frame_rate][mode].width; + sensor->pix.height = ov2775_mode_info_data[frame_rate][mode].height; + + if (sensor->pix.width == 0 || sensor->pix.height == 0 || + mode_setting == NULL || ArySize == 0) { + pr_err("Not support mode=%d %s\n", mode, + (frame_rate == 0) ? "15(fps)" : "30(fps)"); + return -EINVAL; + } + + retval = ov2775_download_firmware(sensor, mode_setting, ArySize); + + return retval; +} +#endif + +static void ov2775_stop(struct ov2775 *sensor) +{ + int i; + struct vvsensor_reg_value_t *mode_setting; + pr_debug("enter %s\n", __func__); +#if 1 + ov2775_write_reg(sensor, 0x3012, 0x00); + + /* if the sensor re-enter streaming from standby mode + * all registers starting with 0x7000 must be resent + * before setting 0x3012[0]=1. + */ + mode_setting = + (struct vvsensor_reg_value_t *)sensor->cur_mode.preg_data; + for(i = 0; i < sensor->cur_mode.reg_data_count; i++) { + if(mode_setting[i].addr >= 0x7000) { + ov2775_write_reg(sensor, + mode_setting[i].addr, mode_setting[i].val); + } + } + +#else + ov2775_write_reg(sensor, 0x4202, 0x0f); + ov2775_write_reg(sensor, 0x3008, 0x42); + ov2775_write_reg(sensor, 0x4800, 0x24); +#endif + +} + +/*! + * ov2775_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl + * @s: pointer to standard V4L2 device structure + * @on: indicates power mode (on or off) + * + * Turns the power on or off, depending on the value of on and returns the + * appropriate error code. + */ +static int ov2775_s_power(struct v4l2_subdev *sd, int on) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + + pr_debug("enter %s\n", __func__); + if (on) + clk_prepare_enable(sensor->sensor_clk); + else + clk_disable_unprepare(sensor->sensor_clk); + + sensor->on = on; + return 0; +} + +/*! + * ov2775_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 sub device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ov2775_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + pr_debug("enter %s\n", __func__); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ov5460_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 sub device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ov2775_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a) +{ + int ret = 0; + + pr_debug("enter %s\n", __func__); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_debug(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +static int ov2775_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + + pr_debug("enter %s\n", __func__); + if (enable) + ov2775_start(sensor); + else + ov2775_stop(sensor); + + sensor->on = enable; + return 0; +} + +static int ov2775_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *mf = &format->format; + const struct ov2775_datafmt *fmt = ov2775_find_datafmt(mf->code); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + unsigned int i; + struct vvsensor_reg_value_t *mode_setting = NULL; + int array_size = 0; + + pr_debug("enter %s\n", __func__); + if (format->pad) { + return -EINVAL; + } + + if (!fmt) { + mf->code = ov2775_colour_fmts[0].code; + mf->colorspace = ov2775_colour_fmts[0].colorspace; + } + + mf->field = V4L2_FIELD_NONE; + /* old search method, vsi need change to + search resolution by width/height */ + /* try_to_find_resolution(sensor, mf); */ + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + return 0; + + for (i=0; iwidth == pov2775_mode_info[i].width && + mf->height == pov2775_mode_info[i].height && + pov2775_mode_info[i].index == sensor->cur_mode.index) + { + memcpy(&(sensor->cur_mode), &pov2775_mode_info[i], sizeof(struct vvcam_mode_info)); + mode_setting = pov2775_mode_info[i].preg_data; + array_size = pov2775_mode_info[i].reg_data_count; + + return ov2775_download_firmware(sensor, mode_setting, array_size); + } + } + + pr_err("%s search error: %d %d\n", __func__, mf->width, mf->height); + return -EINVAL; +} + +static int ov2775_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *mf = &format->format; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + + pr_debug("enter %s\n", __func__); + if (format->pad) + return -EINVAL; + + memset(mf, 0, sizeof(struct v4l2_mbus_framefmt)); + + mf->code = ov2775_colour_fmts[0].code; + mf->colorspace = ov2775_colour_fmts[0].colorspace; + mf->width = sensor->pix.width; + mf->height = sensor->pix.height; + mf->field = V4L2_FIELD_NONE; + + dev_dbg(&client->dev, + "%s code=0x%x, w/h=(%d,%d), colorspace=%d, field=%d\n", + __func__, mf->code, mf->width, mf->height, mf->colorspace, + mf->field); + + return 0; +} + +static int ov2775_enum_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + pr_debug("enter %s\n", __func__); + if (code->pad || code->index >= ARRAY_SIZE(ov2775_colour_fmts)) + return -EINVAL; + + code->code = ov2775_colour_fmts[code->index].code; + return 0; +} + +/*! + * ov2775_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ov2775_enum_framesizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + pr_debug("enter %s\n", __func__); + + if (fse->index > ARRAY_SIZE(pov2775_mode_info)) + return -EINVAL; + + fse->min_width = pov2775_mode_info[fse->index].width; + fse->max_width = fse->min_width; + fse->min_height = pov2775_mode_info[fse->index].height; + fse->max_height = fse->min_height; + + return 0; +} + +/*! + * ov2775_enum_frameintervals - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMEINTERVALS ioctl + * @s: pointer to standard V4L2 device structure + * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ov2775_enum_frameintervals(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum + *fie) +{ + pr_debug("enter %s\n", __func__); + if (fie->index < 0 || fie->index > ARRAY_SIZE(pov2775_mode_info)) + return -EINVAL; + + if (fie->width == 0 || fie->height == 0 || fie->code == 0) { + pr_warn("Please assign pixel format, width and height.\n"); + return -EINVAL; + } + + fie->interval.numerator = 1; + fie->interval.denominator = pov2775_mode_info[fie->index].fps; + + return 0; +} + +static int ov2775_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static struct v4l2_subdev_video_ops ov2775_subdev_video_ops = { + //.g_parm = ov2775_g_parm, + //.s_parm = ov2775_s_parm, + .s_stream = ov2775_s_stream, +}; + +static const struct v4l2_subdev_pad_ops ov2775_subdev_pad_ops = { + .enum_frame_size = ov2775_enum_framesizes, + .enum_frame_interval = ov2775_enum_frameintervals, + .enum_mbus_code = ov2775_enum_code, + .set_fmt = ov2775_set_fmt, + .get_fmt = ov2775_get_fmt, +}; + +static struct v4l2_subdev_core_ops ov2775_subdev_core_ops = { + .s_power = ov2775_s_power, + .ioctl = ov2775_priv_ioctl, +}; + +static struct v4l2_subdev_ops ov2775_subdev_ops = { + .core = &ov2775_subdev_core_ops, + .video = &ov2775_subdev_video_ops, + .pad = &ov2775_subdev_pad_ops, +}; + +static const struct media_entity_operations ov2775_sd_media_ops = { + .link_setup = ov2775_link_setup, +}; + +/*! + * ov2775 I2C probe function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ + +static int ov2775_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct v4l2_subdev *sd; + int retval; + struct ov2775 *sensor; + u8 reg_val = 0; + u16 chip_id = 0; + + printk("enter %s !!!\n", __func__); + pr_info("enter %s\n", __func__); + + sensor = devm_kmalloc(dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + memset(sensor, 0, sizeof(*sensor)); + sensor->i2c_client = client; + + /* request power down pin */ + sensor->pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); + if (!gpio_is_valid(sensor->pwn_gpio)) + dev_warn(dev, "No sensor pwdn pin available"); + else { + retval = devm_gpio_request_one(dev, sensor->pwn_gpio, + GPIOF_OUT_INIT_HIGH, + "ov2775_mipi_pwdn"); + if (retval < 0) { + dev_warn(dev, "Failed to set power pin\n"); + dev_warn(dev, "retval=%d\n", retval); + return retval; + } + } + pr_info("%s:%d\n", __func__, __LINE__); + + /* request reset pin */ + sensor->rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); + if (!gpio_is_valid(sensor->rst_gpio)) + dev_warn(dev, "No sensor reset pin available"); + else { + retval = devm_gpio_request_one(dev, sensor->rst_gpio, + GPIOF_OUT_INIT_HIGH, + "ov2775_mipi_reset"); + if (retval < 0) { + dev_warn(dev, "Failed to set reset pin\n"); + return retval; + } + } + pr_info("%s:%d\n", __func__, __LINE__); + + /* Set initial values for the sensor struct. */ + sensor->sensor_clk = devm_clk_get(dev, "csi_mclk"); + if (IS_ERR(sensor->sensor_clk)) { + /* assuming clock enabled by default */ + sensor->sensor_clk = NULL; + dev_err(dev, "clock-frequency missing or invalid\n"); + return PTR_ERR(sensor->sensor_clk); + } + pr_info("%s:%d\n", __func__, __LINE__); + + retval = of_property_read_u32(dev->of_node, "mclk", &(sensor->mclk)); + if (retval) { + dev_err(dev, "mclk missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "mclk_source", + (u32 *)&(sensor->mclk_source)); + if (retval) { + dev_err(dev, "mclk_source missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "csi_id", &(sensor->csi)); + if (retval) { + dev_err(dev, "csi id missing or invalid\n"); + return retval; + } +#if 0 // 暂时关闭电源相关的控制 + sensor->io_regulator = devm_regulator_get(dev, "DOVDD"); + if (IS_ERR(sensor->io_regulator)) + { + dev_err(dev, "cannot get io regulator\n"); + return PTR_ERR(sensor->io_regulator); + } + + sensor->core_regulator = devm_regulator_get(dev, "DVDD"); + if (IS_ERR(sensor->core_regulator)) + { + dev_err(dev, "cannot get core regulator\n"); + return PTR_ERR(sensor->core_regulator); + } + + sensor->analog_regulator = devm_regulator_get(dev, "AVDD"); + if (IS_ERR(sensor->analog_regulator)) + { + dev_err(dev, "cannot get analog regulator\n"); + return PTR_ERR(sensor->analog_regulator); + } + + retval = ov2775_regulator_enable(sensor); + if (retval) { + dev_err(dev, "regulator enable failed\n"); + return retval; + } +#endif + /* Set mclk rate before clk on */ + ov2775_set_clk_rate(sensor); + retval = clk_prepare_enable(sensor->sensor_clk); + if (retval < 0) { + dev_err(dev, "%s: enable sensor clk fail\n", __func__); + goto probe_err_regulator_disable; + } + + ov2775_power_up(sensor); + ov2775_reset(sensor); + + sensor->io_init = ov2775_reset; + sensor->pix.pixelformat = V4L2_PIX_FMT_UYVY; + sensor->pix.width = pov2775_mode_info[0].width; + sensor->pix.height = pov2775_mode_info[0].height; + sensor->streamcap.capability = V4L2_MODE_HIGHQUALITY | + V4L2_CAP_TIMEPERFRAME; + sensor->streamcap.capturemode = 0; + sensor->streamcap.timeperframe.denominator = pov2775_mode_info[0].fps; + sensor->streamcap.timeperframe.numerator = 1; + + sensor->blc.blue = 64; + sensor->blc.gb = 64; + sensor->blc.gr = 64; + sensor->blc.red = 64; + sensor->wb.r_gain = 0x1f9; + sensor->wb.gr_gain = 0x104; + sensor->wb.gb_gain = 0x104; + sensor->wb.b_gain = 0x23e; + + chip_id = 0; +#if 0 + ov2775_read_reg(sensor, OV2775_CHIP_ID_HIGH_BYTE,®_val); + chip_id |= reg_val << 8; + ov2775_read_reg(sensor, OV2775_CHIP_ID_LOW_BYTE, ®_val); + chip_id |= reg_val; + if (chip_id != 0x2770) { + pr_warn("camera ov2775 is not found\n"); + goto probe_err_power_down; + } +#else + chip_id = 0x2770; // lucz: TODO , hardcode, fix it later + pr_warn("%s:%d Set chip_id to be 0x2770 forcely\n", __func__, __LINE__); +#endif + sd = &sensor->subdev; + v4l2_i2c_subdev_init(sd, client, &ov2775_subdev_ops); + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + sensor->pads[OV2775_SENS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + + retval = media_entity_pads_init(&sd->entity, OV2775_SENS_PADS_NUM, + sensor->pads); + sd->entity.ops = &ov2775_sd_media_ops; + if (retval < 0) + goto probe_err_power_down; + pr_info("%s:%d\n", __func__, __LINE__); + + sensor->v4l2_dev = kzalloc(sizeof(*sensor->v4l2_dev), GFP_KERNEL); + if (WARN_ON(!sensor->v4l2_dev)) { + retval = -ENOMEM; + pr_info("%s:%d\n", __func__, __LINE__); + goto probe_err_entity_cleanup; + } + + retval = v4l2_device_register(dev, sensor->v4l2_dev); + if (WARN_ON(retval < 0)) + goto probe_err_entity_cleanup; + pr_info("%s:%d\n", __func__, __LINE__); + + retval = v4l2_device_register_subdev(sensor->v4l2_dev, sd); + if (retval < 0) { + dev_err(&client->dev,"%s--Async register failed, ret=%d\n", __func__,retval); + goto probe_err_entity_cleanup; + } + + mutex_init(&sensor->lock); + retval = v4l2_device_register_subdev_nodes(sensor->v4l2_dev); + + pr_info("%s camera mipi ov2775, is found\n", __func__); + + return 0; + +probe_err_entity_cleanup: + media_entity_cleanup(&sd->entity); + pr_info("%s:%d\n", __func__, __LINE__); +probe_err_power_down: + ov2775_power_down(sensor); + clk_disable_unprepare(sensor->sensor_clk); + pr_info("%s:%d\n", __func__, __LINE__); +probe_err_regulator_disable: + ov2775_regulator_disable(sensor); + pr_info("%s:%d\n", __func__, __LINE__); + return retval; + +} + +/*! + * ov2775 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int ov2775_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2775 *sensor = client_to_ov2775(client); + + pr_info("enter %s\n", __func__); + v4l2_device_unregister_subdev(sd); + v4l2_device_disconnect(sensor->v4l2_dev); + v4l2_device_put(sensor->v4l2_dev); + media_entity_cleanup(&sd->entity); + ov2775_power_down(sensor); + clk_disable_unprepare(sensor->sensor_clk); + ov2775_regulator_disable(sensor); + mutex_destroy(&sensor->lock); + return 0; +} + +module_i2c_driver(ov2775_i2c_driver); +MODULE_DESCRIPTION("OV2775 MIPI Camera Subdev Driver"); +MODULE_LICENSE("GPL"); + +int sensor_calc_gain(__u32 total_gain, __u32 *pagain, __u32 *pdgain, __u32 *phcg) +{ + if (total_gain <= 3072) + total_gain = 3072; + else if ((total_gain >= 22528) && (total_gain < 23552)) + total_gain = 22528; + + if (total_gain < 4480) { + *pagain = 1; + *phcg = 1; + } else if (total_gain < 8960) { + *pagain = 2; + *phcg = 1; + } else if (total_gain < 22528) { + *pagain = 3; + *phcg = 1; + } else if (total_gain < 44990) { + *pagain = 0; + *phcg = 11; + } else if (total_gain < 89320) { + *pagain = 1; + *phcg = 11; + } else if (total_gain < 179498) { + *pagain = 2; + *phcg = 11; + } else { + *pagain = 3; + *phcg = 11; + } + + *pdgain = ((total_gain << 8) >> (*pagain)) / (1024 * (*phcg)); + return 0; +} + +int ov2775_s_long_gain(struct ov2775 *sensor, __u32 new_gain) +{ + int ret = 0; + __u8 reg_val; + __u32 hcg; + __u32 hcg_gain; + __u32 hcg_again = 0; + __u32 hcg_dgain = 0; + + hcg_gain = new_gain/10; + + sensor_calc_gain(hcg_gain, &hcg_again, &hcg_dgain, &hcg); + + ret = ov2775_read_reg(sensor, 0x30bb, ®_val); + reg_val &= ~0x03; + reg_val |= hcg_again & 0x03; + + ret = ov2775_write_reg(sensor, 0x3467, 0x00); + ret |= ov2775_write_reg(sensor, 0x3464, 0x04); + + ret |= ov2775_write_reg(sensor, 0x315a, (hcg_dgain>>8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x315b, hcg_dgain & 0xff); + + ret |= ov2775_write_reg(sensor, 0x30bb, reg_val); + ret |= ov2775_write_reg(sensor, 0x3464, 0x14); + ret |= ov2775_write_reg(sensor, 0x3467, 0x01); + + return ret; +} + +int ov2775_s_gain(struct ov2775 *sensor, __u32 new_gain) +{ + int ret = 0; + __u8 reg_val; + __u32 hcg = 0; + __u32 again, dgain; + + __u32 lcg_gain; + __u32 lcg_again = 0; + __u32 lcg_dgain = 0; + + if (sensor->hdr == SENSOR_MODE_LINEAR) { + sensor_calc_gain(new_gain, &again, &dgain, &hcg); + ret = ov2775_read_reg(sensor, 0x30bb, ®_val); + if (hcg == 1) { + reg_val &= ~(1 << 6); + } else { + reg_val |= (1 << 6); + } + reg_val &= ~0x03; + reg_val |= again; + ret = ov2775_write_reg(sensor, 0x3467, 0x00); + ret |= ov2775_write_reg(sensor, 0x3464, 0x04); + ret |= ov2775_write_reg(sensor, 0x315a, (dgain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x315b, dgain & 0xff); + ret |= ov2775_write_reg(sensor, 0x30bb, reg_val); + ret |= ov2775_write_reg(sensor, 0x3464, 0x14); + ret |= ov2775_write_reg(sensor, 0x3467, 0x01); + }else { + lcg_gain = new_gain; + sensor_calc_gain(lcg_gain, &lcg_again, &lcg_dgain, &hcg); + + ret = ov2775_read_reg(sensor, 0x30bb, ®_val); + reg_val &= ~(0x03 << 2); + reg_val |= (lcg_again & 0x03) << 2; + + ret = ov2775_write_reg(sensor, 0x3467, 0x00); + ret |= ov2775_write_reg(sensor, 0x3464, 0x04); + + ret |= ov2775_write_reg(sensor, 0x315c, (lcg_dgain>>8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x315d, lcg_dgain & 0xff); + + ret |= ov2775_write_reg(sensor, 0x30bb, reg_val); + ret |= ov2775_write_reg(sensor, 0x3464, 0x14); + ret |= ov2775_write_reg(sensor, 0x3467, 0x01); + } + return ret; +} + +int ov2775_s_vsgain(struct ov2775 *sensor, __u32 new_gain) +{ + __u32 again = 0; + __u32 dgain, hcg; + __u8 reg_val; + + sensor_calc_gain(new_gain, &again, &dgain, &hcg); + + ov2775_read_reg(sensor, 0x30bb, ®_val); + reg_val &= ~0x30; + reg_val |= (again & 0x03) << 4; + + ov2775_write_reg(sensor, 0x3467, 0x00); + ov2775_write_reg(sensor, 0x3464, 0x04); + + ov2775_write_reg(sensor, 0x315e, (dgain & 0xFF00) >> 8); + ov2775_write_reg(sensor, 0x315f, dgain & (0x00FF)); + ov2775_write_reg(sensor, 0x30bb, reg_val); + + ov2775_write_reg(sensor, 0x3464, 0x14); + ov2775_write_reg(sensor, 0x3467, 0x01); + return 0; +} + +int ov2775_s_long_exp(struct ov2775 *sensor, __u32 exp) +{ + return 0; +} + +int ov2775_s_exp(struct ov2775 *sensor, __u32 exp) +{ + /* pr_info("enter %s 0x%08x\n", __func__, exp); */ + ov2775_write_reg(sensor, 0x3467, 0x00); + ov2775_write_reg(sensor, 0x3464, 0x04); + + ov2775_write_reg(sensor, 0x30b6, (exp & 0xFF00) >> 8); + ov2775_write_reg(sensor, 0x30b7, exp & 0x00FF); + + ov2775_write_reg(sensor, 0x3464, 0x14); + ov2775_write_reg(sensor, 0x3467, 0x01); + return 0; +} + +int ov2775_s_vsexp(struct ov2775 *sensor, __u32 exp) +{ + /* pr_info("enter %s 0x%08x\n", __func__, exp); */ + ov2775_write_reg(sensor, 0x3467, 0x00); + ov2775_write_reg(sensor, 0x3464, 0x04); + + if (exp == 0x16) + exp = 0x15; + + ov2775_write_reg(sensor, 0x30b8, (exp & 0xFF00) >> 8); + ov2775_write_reg(sensor, 0x30b9, exp & 0x00FF); + + ov2775_write_reg(sensor, 0x3464, 0x14); + ov2775_write_reg(sensor, 0x3467, 0x01); + return 0; +} + +int ov2775_g_gain(struct ov2775 *sensor, struct vvsensor_gain_context *gain) +{ + __u8 val = 0; + + ov2775_read_reg(sensor, 0x315a, &val); + gain->dgain = val << 8; + ov2775_read_reg(sensor, 0x315b, &val); + gain->dgain |= val << 0; + ov2775_read_reg(sensor, 0x315c, &val); + gain->dgain |= val << 24; + ov2775_read_reg(sensor, 0x315d, &val); + gain->dgain |= val << 16; + ov2775_read_reg(sensor, 0x30bb, &val); + gain->again = val; + return 0; +} + +int ov2775_g_version(struct ov2775 *sensor, __u32 *version) +{ + __u8 val = 0; + + ov2775_read_reg(sensor, 0x300a, &val); + *version = val << 8; + ov2775_read_reg(sensor, 0x300b, &val); + *version |= val; + return 0; +} + + +int ov2775_s_hdr(struct ov2775 *sensor, int hdr_mode) +{ + pr_debug("%s: %d\n", __func__, hdr_mode); + sensor->hdr = hdr_mode; + return 0; +} + +int ov2775_s_sensor_mode(struct ov2775 *sensor, struct vvcam_mode_info *sensor_mode) +{ + + if(sensor_mode->index < ARRAY_SIZE(pov2775_mode_info) && sensor_mode->index >= 0){ + sensor->cur_mode.index = sensor_mode->index; + }else{ + pr_err("%s Set ov2775 mode index error",__func__); + return -1; + } + + return 0; +} + + +int ov2775_s_clk(struct ov2775 *sensor, __u32 clk) +{ + pr_debug("%s: %d\n", __func__, clk); + ov2775_write_reg(sensor, 0x3005, clk); + return 0; +} + +int ov2775_g_clk(struct ov2775 *sensor, __u32 *clk) +{ + u8 val; + ov2775_read_reg(sensor, 0x3005, &val); + *clk = val; + return 0; +} + +int ov2775_g_sclk(struct ov2775 *sensor, __u32 *sclk_hz) +{ + int ret = 0; + u8 pclk_pll_pre;//0x3004[2:0] + u8 pclk_pll_pdiv;//0x3005[7:0] + u8 pclk_pll_sdiv;//0x3006[0] + u8 pclk_pll_post;//0x3007[3:0] + u32 pclk_pll_m; + u8 pclk_pll_pre_num, pclk_pll_pre_deno; + ret = ov2775_read_reg(sensor, 0x3004, &pclk_pll_pre); + ret |= ov2775_read_reg(sensor, 0x3005, &pclk_pll_pdiv); + ret |= ov2775_read_reg(sensor, 0x3006, &pclk_pll_sdiv); + ret |= ov2775_read_reg(sensor, 0x3007, &pclk_pll_post); + switch(pclk_pll_pre&0x07)//0x3004[2:0] + { + case 0: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 1; break; + case 1: pclk_pll_pre_num = 2; pclk_pll_pre_deno = 3; break; + case 2: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 2; break; + case 3: pclk_pll_pre_num = 2; pclk_pll_pre_deno = 5; break; + case 4: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 3; break; + case 5: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 4; break; + case 6: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 6; break; + default: pclk_pll_pre_num = 1; pclk_pll_pre_deno = 8; break; + } + pclk_pll_post = (pclk_pll_post&0x0F) + 1; + pclk_pll_m = 2*pclk_pll_pdiv + (pclk_pll_sdiv&0x01) + 4; + *sclk_hz = (sensor->mclk/1000*pclk_pll_m*pclk_pll_pre_num/(pclk_pll_pre_deno*pclk_pll_post))*1000; + sensor->sclk = *sclk_hz; + return ret; +} + +int ov2775_s_fps(struct ov2775 *sensor, __u32 fps) +{ + u32 vts; + + if (fps < 5) { + fps = 5; + } + if (fps > sensor->cur_mode.fps){ + fps = sensor->cur_mode.fps; + } + sensor->fps = fps; + + vts = sensor->cur_mode.fps * sensor->cur_mode.ae_info.DefaultFrameLengthLines / sensor->fps; + + ov2775_write_reg(sensor, 0x30B2, (u8)(vts >> 8)); + ov2775_write_reg(sensor, 0x30B3, (u8)(vts & 0xff)); + + if (sensor->cur_mode.hdr_mode != SENSOR_MODE_LINEAR) + { + sensor->cur_mode.ae_info.cur_fps = sensor->fps; + sensor->cur_mode.ae_info.CurFrameLengthLines = vts; + sensor->cur_mode.ae_info.max_integration_time = vts - 64 - 2; + }else + { + sensor->cur_mode.ae_info.cur_fps = sensor->fps; + sensor->cur_mode.ae_info.CurFrameLengthLines = vts; + sensor->cur_mode.ae_info.max_integration_time = vts - 2; + } + return 0; +} + +int ov2775_g_fps(struct ov2775 *sensor, __u32 *fps) +{ + *fps = sensor->fps; + return 0; +} + +int ov2775_g_chipid(struct ov2775 *sensor, __u32 *chip_id) +{ + int ret = 0; + __u8 chip_id_high = 0; + __u8 chip_id_low = 0; + ret = ov2775_read_reg(sensor, 0x300a, &chip_id_high); + ret |= ov2775_read_reg(sensor, 0x300b, &chip_id_low); + + *chip_id = ((chip_id_high & 0xff)<<8) | (chip_id_low & 0xff); + return ret; +} + +int ov2775_ioc_qcap(struct ov2775 *sensor, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "ov2775"); + sprintf((char *)cap->bus_info, "csi%d",sensor->csi);//bus_info[0:7]-csi number + if(sensor->i2c_client->adapter) + {//bus_info[8]-i2c bus dev number + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = (__u8)sensor->i2c_client->adapter->nr; + } + else + { + cap->bus_info[VVCAM_CAP_BUS_INFO_I2C_ADAPTER_NR_POS] = 0xFF; + } + + return 0; +} + +int ov2775_ioc_query_mode(struct ov2775 *sensor, struct vvcam_mode_info_array *array) +{ + array->count = ARRAY_SIZE(pov2775_mode_info); + pr_info("%s: Get %d mode(s)\n", __func__, array->count); + memcpy(&array->modes, pov2775_mode_info, sizeof(pov2775_mode_info)); + + return 0; +} + +int ov2775_g_mode(struct ov2775 *sensor, struct vvcam_mode_info *pmode) +{ + int i = 0; + struct vvcam_mode_info *pcur_mode = NULL; + + if (sensor->cur_mode.index == pmode->index && + sensor->cur_mode.width != 0 && + sensor->cur_mode.height != 0) + { + pcur_mode = &(sensor->cur_mode); + memcpy(pmode,pcur_mode,sizeof(struct vvcam_mode_info)); + return 0; + } + for(i=0; i < ARRAY_SIZE(pov2775_mode_info); i++) + { + if (pmode->index == pov2775_mode_info[i].index) + { + pcur_mode = &pov2775_mode_info[i]; + sensor->fps = pov2775_mode_info[i].fps; + break; + } + } + if (pcur_mode == NULL) + { + return -1; + } + + memcpy(pmode,pcur_mode,sizeof(struct vvcam_mode_info)); + return 0; +} + +int ov2775_s_blc(struct ov2775 *sensor, sensor_blc_t *pblc) +{ + int ret = 0; + int r_offset,gr_offset,gb_offset,b_offset; + unsigned int r_gain,gr_gain,gb_gain,b_gain; + + r_gain = sensor->wb.r_gain; + gr_gain = sensor->wb.gr_gain; + gb_gain = sensor->wb.gb_gain; + b_gain = sensor->wb.b_gain; + + if (r_gain < 0x100) + r_gain = 0x100; + if (gr_gain < 0x100) + gr_gain = 0x100; + if (gb_gain < 0x100) + gb_gain = 0x100; + if (b_gain < 0x100) + b_gain = 0x100; + + r_offset = (r_gain - 0x100) * pblc->red; + gr_offset = (gr_gain - 0x100) * pblc->gr; + gb_offset = (gb_gain - 0X100) * pblc->gb; + b_offset = (b_gain - 0X100) * pblc->blue; + + //R,Gr,Gb,B HCG Offset + ret |= ov2775_write_reg(sensor, 0x3378, (r_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3379, (r_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x337a, r_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x337b, (gr_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x337c, (gr_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x337d, gr_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x337e, (gb_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x337f, (gb_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3380, gb_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x3381, (b_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3382, (b_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3383, b_offset & 0xff); + + //R,Gr,Gb,B LCG Offset + ret |= ov2775_write_reg(sensor, 0x3384, (r_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3385, (r_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3386, r_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x3387, (gr_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3388, (gr_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3389, gr_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x338a, (gb_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x338b, (gb_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x338c, gb_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x338d, (b_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x338e, (b_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x338f, b_offset & 0xff); + + //R,Gr,Gb,B VS Offset + ret |= ov2775_write_reg(sensor, 0x3390, (r_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3391, (r_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3392, r_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x3393, (gr_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3394, (gr_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3395, gr_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x3396, (gb_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3397, (gb_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3398, gb_offset & 0xff); + + ret |= ov2775_write_reg(sensor, 0x3399, (b_offset >> 16) & 0xff); + ret |= ov2775_write_reg(sensor, 0x339a, (b_offset >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x339b, b_offset & 0xff); + + memcpy(&sensor->blc,pblc,sizeof(sensor_blc_t)); + + return ret; +} + + +int ov2775_s_wb(struct ov2775 *sensor, sensor_white_balance_t *wb) +{ + unsigned int r_gain,gr_gain,gb_gain,b_gain; + int ret = 0; + + r_gain = wb->r_gain; // wb->r_gain =256 means gain 1.0 + gr_gain = wb->gr_gain;// wb->gr_gain =256 means gain 1.0 + gb_gain = wb->gb_gain;// wb->gb_gain =256 means gain 1.0 + b_gain = wb->b_gain; // wb->b_gain =256 means gain 1.0 + + //Red,Gr,Gb,Blue HCG Channel + if(sensor->wb.r_gain != wb->r_gain){ + + ret = ov2775_write_reg(sensor, 0x3360, (r_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3361, r_gain & 0xff); + } + if(sensor->wb.gr_gain != wb->gr_gain){ + + ret = ov2775_write_reg(sensor, 0x3362, (gr_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3363, gr_gain & 0xff); + } + if(sensor->wb.gb_gain != wb->gb_gain){ + + ret = ov2775_write_reg(sensor, 0x3364, (gb_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3365, gb_gain & 0xff); + } + if(sensor->wb.b_gain != wb->b_gain){ + + ret = ov2775_write_reg(sensor, 0x3366, (b_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3367, b_gain & 0xff); + } + + //Red,Gr,Gb,Blue LCG Channel + if(sensor->wb.r_gain != wb->r_gain){ + + ret = ov2775_write_reg(sensor, 0x3368, (r_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3369, r_gain & 0xff); + } + if(sensor->wb.gr_gain != wb->gr_gain){ + + ret = ov2775_write_reg(sensor, 0x336a, (gr_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x336b, gr_gain & 0xff); + } + if(sensor->wb.gb_gain != wb->gb_gain){ + + ret = ov2775_write_reg(sensor, 0x336c, (gb_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x336d, gb_gain & 0xff); + } + if(sensor->wb.b_gain != wb->b_gain){ + + ret = ov2775_write_reg(sensor, 0x336e, (b_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x336f, b_gain & 0xff); + } + + //Red,Gr,Gb,Blue VS Channel + if(sensor->wb.r_gain != wb->r_gain){ + + ret = ov2775_write_reg(sensor, 0x3370, (r_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3371, r_gain & 0xff); + } + if(sensor->wb.gr_gain != wb->gr_gain){ + + ret = ov2775_write_reg(sensor, 0x3372, (gr_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3373, gr_gain & 0xff); + } + if(sensor->wb.gb_gain != wb->gb_gain){ + + ret = ov2775_write_reg(sensor, 0x3374, (gb_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3375, gb_gain & 0xff); + } + if(sensor->wb.b_gain != wb->b_gain){ + + ret = ov2775_write_reg(sensor, 0x3376, (b_gain >> 8) & 0xff); + ret |= ov2775_write_reg(sensor, 0x3377, b_gain & 0xff); + } + + if((sensor->wb.gr_gain != wb->gr_gain) || + (sensor->wb.r_gain != wb->r_gain) || + (sensor->wb.b_gain != wb->b_gain) || + (sensor->wb.gb_gain != wb->gb_gain)){ + + ov2775_s_blc(sensor,&sensor->blc); + } + + memcpy(&sensor->wb,wb,sizeof(sensor_white_balance_t)); + + return ret; +} + +int ov2775_get_expand_curve(struct ov2775 *sensor, sensor_expand_curve_t* pexpand_curve) +{ + int i; + if ((pexpand_curve->x_bit) == 12 && (pexpand_curve->y_bit == 16)) + { + uint8_t expand_px[64] = {6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, + 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, + 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, + 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6}; + + memcpy(pexpand_curve->expand_px,expand_px,sizeof(expand_px)); + + pexpand_curve->expand_x_data[0] = 0; + pexpand_curve->expand_y_data[0] = 0; + for(i = 1; i<65; i++) + { + pexpand_curve->expand_x_data[i] = (1 << pexpand_curve->expand_px[i-1]) + pexpand_curve->expand_x_data[i-1]; + + if (pexpand_curve->expand_x_data[i] < 512) + { + pexpand_curve->expand_y_data[i] = pexpand_curve->expand_x_data[i] << 1; + + }else if (pexpand_curve->expand_x_data[i] < 768) + { + pexpand_curve->expand_y_data[i] = (pexpand_curve->expand_x_data[i] - 256) << 2 ; + + }else if (pexpand_curve->expand_x_data[i] < 2560) + { + pexpand_curve->expand_y_data[i] = (pexpand_curve->expand_x_data[i] - 512) << 3 ; + + }else + { + pexpand_curve->expand_y_data[i] = (pexpand_curve->expand_x_data[i] - 2048) << 5; + } + } + return 0; + } + return -1; +} + +/* +Use USER_TO_KERNEL/KERNEL_TO_USER to fix "uaccess" exception on run time. +Also, use "copy_ret" to fix the build issue as below. +error: ignoring return value of function declared with 'warn_unused_result' attribute. +*/ + +#ifdef __KERNEL__ +#define USER_TO_KERNEL(TYPE) \ + do {\ + TYPE tmp; \ + unsigned long copy_ret; \ + arg = (void *)(&tmp); \ + copy_ret = copy_from_user(arg, arg_user, sizeof(TYPE));\ + } while (0) + +#define KERNEL_TO_USER(TYPE) \ + do {\ + unsigned long copy_ret; \ + copy_ret = copy_to_user(arg_user, arg, sizeof(TYPE));\ + } while (0) +#else +#define USER_TO_KERNEL(TYPE) +#define KERNEL_TO_USER(TYPE) +#endif + +long ov2775_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg_user) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2775 *sensor = client_to_ov2775(client); + struct vvcam_sccb_data reg; + int ret = 0; + void *arg = arg_user; + + pr_info("enter %s, cmd=0x%08x\n", __func__, cmd); + mutex_lock(&sensor->lock); + switch (cmd) { + case VVSENSORIOC_WRITE_REG: { + USER_TO_KERNEL(struct vvcam_sccb_data); + reg = *(struct vvcam_sccb_data *)arg; + ret = ov2775_write_reg(sensor, reg.addr, (u8)reg.data) < 0; + break; + } + case VVSENSORIOC_READ_REG: { + struct vvcam_sccb_data *preg; + u8 val; + USER_TO_KERNEL(struct vvcam_sccb_data); + preg = (struct vvcam_sccb_data *)arg; + ret = ov2775_read_reg(sensor, (u16) preg->addr, &val) < 0; + preg->data = val; + KERNEL_TO_USER(struct vvcam_sccb_data); + break; + } + case VVSENSORIOC_S_STREAM: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_stream(sd, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_LONG_EXP: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_long_exp(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_EXP: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_exp(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_VSEXP: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_vsexp(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_LONG_GAIN:{ + USER_TO_KERNEL(__u32); + ret = ov2775_s_long_gain(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_GAIN: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_gain(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_VSGAIN: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_vsgain(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_S_FPS: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_fps(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_G_FPS: { + USER_TO_KERNEL(__u32); + ret = ov2775_g_fps(sensor, (__u32 *)arg); + KERNEL_TO_USER(__u32); + break; + } + case VVSENSORIOC_S_CLK: { + USER_TO_KERNEL(__u32); + ret = ov2775_s_clk(sensor, *(__u32 *)arg); + break; + } + case VVSENSORIOC_G_CLK: { + USER_TO_KERNEL(__u32); + ret = ov2775_g_clk(sensor, (__u32 *)arg); + KERNEL_TO_USER(__u32); + break; + } + case VIDIOC_QUERYCAP: + pr_info("%s, case cmd=VIDIOC_QUERYCAP\n", __func__); + ret = ov2775_ioc_qcap(sensor, arg); + break; + + case VVSENSORIOC_G_CHIP_ID: { + USER_TO_KERNEL(__u32); + ret = ov2775_g_chipid(sensor, (__u32 *)arg); + ret = (ret < 0) ? -1 : 0; + KERNEL_TO_USER(__u32); + break; + } + case VVSENSORIOC_G_RESERVE_ID: { + __u32 correct_id = 0x2770; + ret = copy_to_user(arg_user, &correct_id, sizeof(__u32)); + ret = ret ? -1 : 0; + break; + } + case VVSENSORIOC_S_HDR_MODE: { + USER_TO_KERNEL(int); + ret = ov2775_s_hdr(sensor, *(int *)arg); + break; + } + case VVSENSORIOC_QUERY: { + USER_TO_KERNEL(struct vvcam_mode_info_array); + ret = ov2775_ioc_query_mode(sensor, arg); + KERNEL_TO_USER(struct vvcam_mode_info_array); + break; + } + case VVSENSORIOC_G_SENSOR_MODE:{ + USER_TO_KERNEL(struct vvcam_mode_info); + ret = ov2775_g_mode(sensor, arg); + KERNEL_TO_USER(struct vvcam_mode_info); + break; + } + case VVSENSORIOC_S_WB: { + USER_TO_KERNEL(sensor_white_balance_t); + ret = ov2775_s_wb(sensor,arg); + break; + } + case VVSENSORIOC_S_BLC: { + USER_TO_KERNEL(sensor_blc_t); + ret = ov2775_s_blc(sensor,arg); + break; + } + case VVSENSORIOC_G_EXPAND_CURVE:{ + //USER_TO_KERNEL(sensor_expand_curve_t); + ret = ov2775_get_expand_curve(sensor, arg); + //KERNEL_TO_USER(sensor_expand_curve_t); + break; + } + case VVSENSORIOC_S_SENSOR_MODE: { + USER_TO_KERNEL(struct vvcam_mode_info); + ret = ov2775_s_sensor_mode(sensor, arg); + KERNEL_TO_USER(struct vvcam_mode_info); + break; + } + default: + pr_err("unsupported ov2775 command %d.", cmd); + ret = -1; + break; + } + mutex_unlock(&sensor->lock); + + return ret; +} diff --git a/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p.h b/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p.h new file mode 100755 index 0000000..5486846 --- /dev/null +++ b/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p.h @@ -0,0 +1,1879 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OV2775_REGS_1080P_H_ +#define _VVCAM_OV2775_REGS_1080P_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t ov2775_init_setting_1080p[] = { + {0x3000, 0x02, 0, 0}, + {0x3001, 0x28, 0, 0}, + {0x3002, 0x03, 0, 0}, + {0x3003, 0x01, 0, 0}, + {0x3004, 0x02, 0, 0}, + {0x3005, 0x1e, 0, 0},//768Mbps //{0x3005, 0x26, 0, 0},//960Mbps + {0x3006, 0x00, 0, 0}, + {0x3007, 0x07, 0, 0},//96MHz + {0x3008, 0x01, 0, 0}, + {0x3009, 0x00, 0, 0}, + {0x300c, 0x6c, 0, 0}, + {0x300e, 0x80, 0, 0}, + {0x300f, 0x00, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3013, 0x00, 0, 0}, + {0x3014, 0xc4, 0, 0}, + {0x3015, 0x00, 0, 0}, + {0x3017, 0x00, 0, 0}, + {0x3018, 0x00, 0, 0}, + {0x3019, 0x00, 0, 0}, + {0x301a, 0x00, 0, 0}, + {0x301b, 0x0e, 0, 0}, + {0x301e, 0x17, 0, 0}, + {0x301f, 0xe1, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x3031, 0x62, 0, 0}, + {0x3032, 0xf0, 0, 0}, + {0x3033, 0x30, 0, 0}, + {0x3034, 0x3f, 0, 0}, + {0x3035, 0x5f, 0, 0}, + {0x3036, 0x02, 0, 0}, + {0x3037, 0x9f, 0, 0}, + {0x3038, 0x04, 0, 0}, + {0x3039, 0xb7, 0, 0}, + {0x303a, 0x04, 0, 0}, + {0x303b, 0x07, 0, 0}, + {0x303c, 0xf0, 0, 0}, + {0x303d, 0x00, 0, 0}, + {0x303e, 0x0b, 0, 0}, + {0x303f, 0xe3, 0, 0}, + {0x3040, 0xf3, 0, 0}, + {0x3041, 0x29, 0, 0}, + {0x3042, 0xf6, 0, 0}, + {0x3043, 0x65, 0, 0}, + {0x3044, 0x06, 0, 0}, + {0x3045, 0x0f, 0, 0}, + {0x3046, 0x59, 0, 0}, + {0x3047, 0x07, 0, 0}, + {0x3048, 0x82, 0, 0}, + {0x3049, 0xcf, 0, 0}, + {0x304a, 0x12, 0, 0}, + {0x304b, 0x40, 0, 0}, + {0x304c, 0x33, 0, 0}, + {0x304d, 0xa4, 0, 0}, + {0x304e, 0x0b, 0, 0}, + {0x304f, 0x3d, 0, 0}, + {0x3050, 0x10, 0, 0}, + {0x3060, 0x00, 0, 0}, + {0x3061, 0x64, 0, 0}, + {0x3062, 0x00, 0, 0}, + {0x3063, 0xe4, 0, 0}, + {0x3066, 0x80, 0, 0}, + {0x3080, 0x00, 0, 0}, + {0x3081, 0x00, 0, 0}, + {0x3082, 0x01, 0, 0}, + {0x3083, 0xe3, 0, 0}, + {0x3084, 0x06, 0, 0}, + {0x3085, 0x00, 0, 0}, + {0x3086, 0x10, 0, 0}, + {0x3087, 0x10, 0, 0}, + {0x3089, 0x00, 0, 0}, + {0x308a, 0x01, 0, 0}, + {0x3093, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x00, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x00, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x90, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x48, 0, 0}, + {0x30b0, 0x04, 0, 0}, + {0x30b1, 0x7e, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x65, 0, 0}, + {0x30b4, 0x00, 0, 0}, + {0x30b5, 0x00, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x10, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x02, 0, 0}, + {0x30ba, 0x10, 0, 0}, + {0x30bb, 0x00, 0, 0}, + {0x30bc, 0x00, 0, 0}, + {0x30bd, 0x03, 0, 0}, + {0x30be, 0x5c, 0, 0}, + {0x30bf, 0x00, 0, 0}, + {0x30c0, 0x05, 0, 0}, + {0x30c1, 0x00, 0, 0}, + {0x30c2, 0x20, 0, 0}, + {0x30c3, 0x00, 0, 0}, + {0x30c4, 0x4a, 0, 0}, + {0x30c5, 0x00, 0, 0}, + {0x30c7, 0x00, 0, 0}, + {0x30c8, 0x00, 0, 0}, + {0x30d1, 0x00, 0, 0}, + {0x30d2, 0x00, 0, 0}, + {0x30d3, 0x80, 0, 0}, + {0x30d4, 0x00, 0, 0}, + {0x30d9, 0x09, 0, 0}, + {0x30da, 0x64, 0, 0}, + {0x30dd, 0x00, 0, 0}, + {0x30de, 0x16, 0, 0}, + {0x30df, 0x00, 0, 0}, + {0x30e0, 0x17, 0, 0}, + {0x30e1, 0x00, 0, 0}, + {0x30e2, 0x18, 0, 0}, + {0x30e3, 0x10, 0, 0}, + {0x30e4, 0x04, 0, 0}, + {0x30e5, 0x00, 0, 0}, + {0x30e6, 0x00, 0, 0}, + {0x30e7, 0x00, 0, 0}, + {0x30e8, 0x00, 0, 0}, + {0x30e9, 0x00, 0, 0}, + {0x30ea, 0x00, 0, 0}, + {0x30eb, 0x00, 0, 0}, + {0x30ec, 0x00, 0, 0}, + {0x30ed, 0x00, 0, 0}, + {0x3101, 0x00, 0, 0}, + {0x3102, 0x00, 0, 0}, + {0x3103, 0x00, 0, 0}, + {0x3104, 0x00, 0, 0}, + {0x3105, 0x8c, 0, 0}, + {0x3106, 0x87, 0, 0}, + {0x3107, 0xc0, 0, 0}, + {0x3108, 0x9d, 0, 0}, + {0x3109, 0x8d, 0, 0}, + {0x310a, 0x8d, 0, 0}, + {0x310b, 0x6a, 0, 0}, + {0x310c, 0x3a, 0, 0}, + {0x310d, 0x5a, 0, 0}, + {0x310e, 0x00, 0, 0}, + {0x3120, 0x00, 0, 0}, + {0x3121, 0x00, 0, 0}, + {0x3122, 0x00, 0, 0}, + {0x3123, 0xf0, 0, 0}, + {0x3124, 0x00, 0, 0}, + {0x3125, 0x70, 0, 0}, + {0x3126, 0x1f, 0, 0}, + {0x3127, 0x0f, 0, 0}, + {0x3128, 0x00, 0, 0}, + {0x3129, 0x3a, 0, 0}, + {0x312a, 0x02, 0, 0}, + {0x312b, 0x0f, 0, 0}, + {0x312c, 0x00, 0, 0}, + {0x312d, 0x0f, 0, 0}, + {0x312e, 0x1d, 0, 0}, + {0x312f, 0x00, 0, 0}, + {0x3130, 0x00, 0, 0}, + {0x3131, 0x00, 0, 0}, + {0x3132, 0x00, 0, 0}, + {0x3140, 0x0a, 0, 0}, + {0x3141, 0x03, 0, 0}, + {0x3142, 0x00, 0, 0}, + {0x3143, 0x00, 0, 0}, + {0x3144, 0x00, 0, 0}, + {0x3145, 0x00, 0, 0}, + {0x3146, 0x00, 0, 0}, + {0x3147, 0x00, 0, 0}, + {0x3148, 0x00, 0, 0}, + {0x3149, 0x00, 0, 0}, + {0x314a, 0x00, 0, 0}, + {0x314b, 0x00, 0, 0}, + {0x314c, 0x00, 0, 0}, + {0x314d, 0x00, 0, 0}, + {0x314e, 0x1c, 0, 0}, + {0x314f, 0xff, 0, 0}, + {0x3150, 0xff, 0, 0}, + {0x3151, 0xff, 0, 0}, + {0x3152, 0x10, 0, 0}, + {0x3153, 0x10, 0, 0}, + {0x3154, 0x10, 0, 0}, + {0x3155, 0x00, 0, 0}, + {0x3156, 0x03, 0, 0}, + {0x3157, 0x00, 0, 0}, + {0x3158, 0x0f, 0, 0}, + {0x3159, 0xff, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x00, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x00, 0, 0}, + {0x3160, 0x00, 0, 0}, + {0x3161, 0x40, 0, 0}, + {0x3162, 0x00, 0, 0}, + {0x3163, 0x40, 0, 0}, + {0x3164, 0x00, 0, 0}, + {0x3165, 0x40, 0, 0}, + {0x3190, 0x08, 0, 0}, + {0x3191, 0x99, 0, 0}, + {0x3193, 0x08, 0, 0}, + {0x3194, 0x13, 0, 0}, + {0x3195, 0x33, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x10, 0, 0}, + {0x3198, 0x00, 0, 0}, + {0x3199, 0x7f, 0, 0}, + {0x319a, 0x80, 0, 0}, + {0x319b, 0xff, 0, 0}, + {0x319c, 0x80, 0, 0}, + {0x319d, 0xbf, 0, 0}, + {0x319e, 0xc0, 0, 0}, + {0x319f, 0xff, 0, 0}, + {0x31a0, 0x24, 0, 0}, + {0x31a1, 0x55, 0, 0}, + {0x31a2, 0x00, 0, 0}, + {0x31a3, 0x00, 0, 0}, + {0x31a6, 0x00, 0, 0}, + {0x31a7, 0x00, 0, 0}, + {0x31b0, 0x00, 0, 0}, + {0x31b1, 0x00, 0, 0}, + {0x31b2, 0x02, 0, 0}, + {0x31b3, 0x00, 0, 0}, + {0x31b4, 0x00, 0, 0}, + {0x31b5, 0x01, 0, 0}, + {0x31b6, 0x00, 0, 0}, + {0x31b7, 0x00, 0, 0}, + {0x31b8, 0x00, 0, 0}, + {0x31b9, 0x00, 0, 0}, + {0x31ba, 0x00, 0, 0}, + {0x31d0, 0x3c, 0, 0}, + {0x31d1, 0x34, 0, 0}, + {0x31d2, 0x3c, 0, 0}, + {0x31d3, 0x00, 0, 0}, + {0x31d4, 0x2d, 0, 0}, + {0x31d5, 0x00, 0, 0}, + {0x31d6, 0x01, 0, 0}, + {0x31d7, 0x06, 0, 0}, + {0x31d8, 0x00, 0, 0}, + {0x31d9, 0x64, 0, 0}, + {0x31da, 0x00, 0, 0}, + {0x31db, 0x30, 0, 0}, + {0x31dc, 0x04, 0, 0}, + {0x31dd, 0x69, 0, 0}, + {0x31de, 0x0a, 0, 0}, + {0x31df, 0x3c, 0, 0}, + {0x31e0, 0x04, 0, 0}, + {0x31e1, 0x32, 0, 0}, + {0x31e2, 0x00, 0, 0}, + {0x31e3, 0x00, 0, 0}, + {0x31e4, 0x08, 0, 0}, + {0x31e5, 0x80, 0, 0}, + {0x31e6, 0x00, 0, 0}, + {0x31e7, 0x2c, 0, 0}, + {0x31e8, 0x6c, 0, 0}, + {0x31e9, 0xac, 0, 0}, + {0x31ea, 0xec, 0, 0}, + {0x31eb, 0x3f, 0, 0}, + {0x31ec, 0x07, 0, 0}, + {0x31ed, 0x80, 0, 0}, + {0x31ee, 0x04, 0, 0}, + {0x31ef, 0x38, 0, 0}, + {0x31f0, 0x07, 0, 0}, + {0x31f1, 0x80, 0, 0}, + {0x31f2, 0x04, 0, 0}, + {0x31f3, 0x38, 0, 0}, + {0x31f4, 0x07, 0, 0}, + {0x31f5, 0x80, 0, 0}, + {0x31f6, 0x04, 0, 0}, + {0x31f7, 0x38, 0, 0}, + {0x31f8, 0x07, 0, 0}, + {0x31f9, 0x80, 0, 0}, + {0x31fa, 0x04, 0, 0}, + {0x31fb, 0x38, 0, 0}, + {0x31fd, 0xcb, 0, 0}, + {0x31fe, 0x0f, 0, 0}, + {0x31ff, 0x03, 0, 0}, + {0x3200, 0x00, 0, 0}, + {0x3201, 0xff, 0, 0}, + {0x3202, 0x00, 0, 0}, + {0x3203, 0xff, 0, 0}, + {0x3204, 0xff, 0, 0}, + {0x3205, 0xff, 0, 0}, + {0x3206, 0xff, 0, 0}, + {0x3207, 0xff, 0, 0}, + {0x3208, 0xff, 0, 0}, + {0x3209, 0xff, 0, 0}, + {0x320a, 0xff, 0, 0}, + {0x320b, 0x1b, 0, 0}, + {0x320c, 0x1f, 0, 0}, + {0x320d, 0x1e, 0, 0}, + {0x320e, 0x30, 0, 0}, + {0x320f, 0x2d, 0, 0}, + {0x3210, 0x2c, 0, 0}, + {0x3211, 0x2b, 0, 0}, + {0x3212, 0x2a, 0, 0}, + {0x3213, 0x24, 0, 0}, + {0x3214, 0x22, 0, 0}, + {0x3215, 0x00, 0, 0}, + {0x3216, 0x04, 0, 0}, + {0x3217, 0x2c, 0, 0}, + {0x3218, 0x6c, 0, 0}, + {0x3219, 0xac, 0, 0}, + {0x321a, 0xec, 0, 0}, + {0x321b, 0x00, 0, 0}, + {0x3230, 0x3a, 0, 0}, + {0x3231, 0x00, 0, 0}, + {0x3232, 0x80, 0, 0}, + {0x3233, 0x00, 0, 0}, + {0x3234, 0x10, 0, 0}, + {0x3235, 0xaa, 0, 0}, + {0x3236, 0x55, 0, 0}, + {0x3237, 0x99, 0, 0}, + {0x3238, 0x66, 0, 0}, + {0x3239, 0x08, 0, 0}, + {0x323a, 0x88, 0, 0}, + {0x323b, 0x00, 0, 0}, + {0x323c, 0x00, 0, 0}, + {0x323d, 0x03, 0, 0}, + {0x3250, 0x33, 0, 0}, + {0x3251, 0x00, 0, 0}, + {0x3252, 0x20, 0, 0}, + {0x3253, 0x00, 0, 3}, + {0x3254, 0x00, 0, 0}, + {0x3255, 0x01, 0, 0}, + {0x3256, 0x00, 0, 0}, + {0x3257, 0x00, 0, 0}, + {0x3258, 0x00, 0, 0}, + {0x3270, 0x01, 0, 0}, + {0x3271, 0x60, 0, 0}, + {0x3272, 0xc0, 0, 0}, + {0x3273, 0x00, 0, 0}, + {0x3274, 0x80, 0, 0}, + {0x3275, 0x40, 0, 0}, + {0x3276, 0x02, 0, 0}, + {0x3277, 0x08, 0, 0}, + {0x3278, 0x10, 0, 0}, + {0x3279, 0x04, 0, 0}, + {0x327a, 0x00, 0, 0}, + {0x327b, 0x03, 0, 0}, + {0x327c, 0x10, 0, 0}, + {0x327d, 0x60, 0, 0}, + {0x327e, 0xc0, 0, 0}, + {0x327f, 0x06, 0, 0}, + {0x3288, 0x10, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x08, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x04, 0, 0}, + {0x328d, 0x00, 0, 0}, + {0x328e, 0x02, 0, 0}, + {0x328f, 0x00, 0, 0}, + {0x3290, 0x20, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x10, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x08, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x04, 0, 0}, + {0x3297, 0x00, 0, 0}, + {0x3298, 0x40, 0, 0}, + {0x3299, 0x00, 0, 0}, + {0x329a, 0x20, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x10, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x08, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x40, 0, 0}, + {0x32a3, 0x00, 0, 0}, + {0x32a4, 0x20, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x10, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32a8, 0x00, 0, 0}, + {0x32a9, 0x00, 0, 0}, + {0x32aa, 0x00, 0, 0}, + {0x32ab, 0x00, 0, 0}, + {0x32ac, 0x00, 0, 0}, + {0x32ad, 0x00, 0, 0}, + {0x32ae, 0x00, 0, 0}, + {0x32af, 0x00, 0, 0}, + {0x32b0, 0x00, 0, 0}, + {0x32b1, 0x00, 0, 0}, + {0x32b2, 0x00, 0, 0}, + {0x32b3, 0x00, 0, 0}, + {0x32b4, 0x00, 0, 0}, + {0x32b5, 0x00, 0, 0}, + {0x32b6, 0x00, 0, 0}, + {0x32b7, 0x00, 0, 0}, + {0x32b8, 0x00, 0, 0}, + {0x32b9, 0x00, 0, 0}, + {0x32ba, 0x00, 0, 0}, + {0x32bb, 0x00, 0, 0}, + {0x32bc, 0x00, 0, 0}, + {0x32bd, 0x00, 0, 0}, + {0x32be, 0x00, 0, 0}, + {0x32bf, 0x00, 0, 0}, + {0x32c0, 0x00, 0, 0}, + {0x32c1, 0x00, 0, 0}, + {0x32c2, 0x00, 0, 0}, + {0x32c3, 0x00, 0, 0}, + {0x32c4, 0x00, 0, 0}, + {0x32c5, 0x00, 0, 0}, + {0x32c6, 0x00, 0, 0}, + {0x32c7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x32c9, 0x00, 0, 0}, + {0x3330, 0x03, 0, 0}, + {0x3331, 0xc8, 0, 0}, + {0x3332, 0x02, 0, 0}, + {0x3333, 0x24, 0, 0}, + {0x3334, 0x00, 0, 0}, + {0x3335, 0x00, 0, 0}, + {0x3336, 0x00, 0, 0}, + {0x3337, 0x00, 0, 0}, + {0x3338, 0x03, 0, 0}, + {0x3339, 0xc8, 0, 0}, + {0x333a, 0x02, 0, 0}, + {0x333b, 0x24, 0, 0}, + {0x333c, 0x00, 0, 0}, + {0x333d, 0x00, 0, 0}, + {0x333e, 0x00, 0, 0}, + {0x333f, 0x00, 0, 0}, + {0x3340, 0x03, 0, 0}, + {0x3341, 0xc8, 0, 0}, + {0x3342, 0x02, 0, 0}, + {0x3343, 0x24, 0, 0}, + {0x3344, 0x00, 0, 0}, + {0x3345, 0x00, 0, 0}, + {0x3346, 0x00, 0, 0}, + {0x3347, 0x00, 0, 0}, + {0x3348, 0x40, 0, 0}, + {0x3349, 0x00, 0, 0}, + {0x334a, 0x00, 0, 0}, + {0x334b, 0x00, 0, 0}, + {0x334c, 0x00, 0, 0}, + {0x334d, 0x00, 0, 0}, + {0x334e, 0x80, 0, 0}, + {0x3360, 0x01, 0, 0}, + {0x3361, 0x00, 0, 0}, + {0x3362, 0x01, 0, 0}, + {0x3363, 0x00, 0, 0}, + {0x3364, 0x01, 0, 0}, + {0x3365, 0x00, 0, 0}, + {0x3366, 0x01, 0, 0}, + {0x3367, 0x00, 0, 0}, + {0x3368, 0x01, 0, 0}, + {0x3369, 0x00, 0, 0}, + {0x336a, 0x01, 0, 0}, + {0x336b, 0x00, 0, 0}, + {0x336c, 0x01, 0, 0}, + {0x336d, 0x00, 0, 0}, + {0x336e, 0x01, 0, 0}, + {0x336f, 0x00, 0, 0}, + {0x3370, 0x01, 0, 0}, + {0x3371, 0x00, 0, 0}, + {0x3372, 0x01, 0, 0}, + {0x3373, 0x00, 0, 0}, + {0x3374, 0x01, 0, 0}, + {0x3375, 0x00, 0, 0}, + {0x3376, 0x01, 0, 0}, + {0x3377, 0x00, 0, 0}, + {0x3378, 0x00, 0, 0}, + {0x3379, 0x00, 0, 0}, + {0x337a, 0x00, 0, 0}, + {0x337b, 0x00, 0, 0}, + {0x337c, 0x00, 0, 0}, + {0x337d, 0x00, 0, 0}, + {0x337e, 0x00, 0, 0}, + {0x337f, 0x00, 0, 0}, + {0x3380, 0x00, 0, 0}, + {0x3381, 0x00, 0, 0}, + {0x3382, 0x00, 0, 0}, + {0x3383, 0x00, 0, 0}, + {0x3384, 0x00, 0, 0}, + {0x3385, 0x00, 0, 0}, + {0x3386, 0x00, 0, 0}, + {0x3387, 0x00, 0, 0}, + {0x3388, 0x00, 0, 0}, + {0x3389, 0x00, 0, 0}, + {0x338a, 0x00, 0, 0}, + {0x338b, 0x00, 0, 0}, + {0x338c, 0x00, 0, 0}, + {0x338d, 0x00, 0, 0}, + {0x338e, 0x00, 0, 0}, + {0x338f, 0x00, 0, 0}, + {0x3390, 0x00, 0, 0}, + {0x3391, 0x00, 0, 0}, + {0x3392, 0x00, 0, 0}, + {0x3393, 0x00, 0, 0}, + {0x3394, 0x00, 0, 0}, + {0x3395, 0x00, 0, 0}, + {0x3396, 0x00, 0, 0}, + {0x3397, 0x00, 0, 0}, + {0x3398, 0x00, 0, 0}, + {0x3399, 0x00, 0, 0}, + {0x339a, 0x00, 0, 0}, + {0x339b, 0x00, 0, 0}, + {0x33b0, 0x00, 0, 0}, + {0x33b1, 0x50, 0, 0}, + {0x33b2, 0x01, 0, 0}, + {0x33b3, 0xff, 0, 0}, + {0x33b4, 0xe0, 0, 0}, + {0x33b5, 0x6b, 0, 0}, + {0x33b6, 0x00, 0, 0}, + {0x33b7, 0x00, 0, 0}, + {0x33b8, 0x00, 0, 0}, + {0x33b9, 0x00, 0, 0}, + {0x33ba, 0x00, 0, 0}, + {0x33bb, 0x1f, 0, 0}, + {0x33bc, 0x01, 0, 0}, + {0x33bd, 0x01, 0, 0}, + {0x33be, 0x01, 0, 0}, + {0x33bf, 0x01, 0, 0}, + {0x33c0, 0x00, 0, 0}, + {0x33c1, 0x00, 0, 0}, + {0x33c2, 0x00, 0, 0}, + {0x33c3, 0x00, 0, 0}, + {0x33e0, 0x14, 0, 0}, + {0x33e1, 0x0f, 0, 0}, + {0x33e2, 0x02, 0, 0}, + {0x33e3, 0x01, 0, 0}, + {0x33e4, 0x01, 0, 0}, + {0x33e5, 0x01, 0, 0}, + {0x33e6, 0x00, 0, 0}, + {0x33e7, 0x04, 0, 0}, + {0x33e8, 0x0c, 0, 0}, + {0x33e9, 0x02, 0, 0}, + {0x33ea, 0x02, 0, 0}, + {0x33eb, 0x02, 0, 0}, + {0x33ec, 0x03, 0, 0}, + {0x33ed, 0x01, 0, 0}, + {0x33ee, 0x02, 0, 0}, + {0x33ef, 0x08, 0, 0}, + {0x33f0, 0x08, 0, 0}, + {0x33f1, 0x04, 0, 0}, + {0x33f2, 0x04, 0, 0}, + {0x33f3, 0x00, 0, 0}, + {0x33f4, 0x03, 0, 0}, + {0x33f5, 0x14, 0, 0}, + {0x33f6, 0x0f, 0, 0}, + {0x33f7, 0x02, 0, 0}, + {0x33f8, 0x01, 0, 0}, + {0x33f9, 0x01, 0, 0}, + {0x33fa, 0x01, 0, 0}, + {0x33fb, 0x00, 0, 0}, + {0x33fc, 0x04, 0, 0}, + {0x33fd, 0x0c, 0, 0}, + {0x33fe, 0x02, 0, 0}, + {0x33ff, 0x02, 0, 0}, + {0x3400, 0x02, 0, 0}, + {0x3401, 0x03, 0, 0}, + {0x3402, 0x01, 0, 0}, + {0x3403, 0x02, 0, 0}, + {0x3404, 0x08, 0, 0}, + {0x3405, 0x08, 0, 0}, + {0x3406, 0x04, 0, 0}, + {0x3407, 0x04, 0, 0}, + {0x3408, 0x00, 0, 0}, + {0x3409, 0x03, 0, 0}, + {0x340a, 0x14, 0, 0}, + {0x340b, 0x0f, 0, 0}, + {0x340c, 0x04, 0, 0}, + {0x340d, 0x02, 0, 0}, + {0x340e, 0x01, 0, 0}, + {0x340f, 0x01, 0, 0}, + {0x3410, 0x00, 0, 0}, + {0x3411, 0x04, 0, 0}, + {0x3412, 0x0c, 0, 0}, + {0x3413, 0x02, 0, 0}, + {0x3414, 0x02, 0, 0}, + {0x3415, 0x02, 0, 0}, + {0x3416, 0x03, 0, 0}, + {0x3417, 0x02, 0, 0}, + {0x3418, 0x05, 0, 0}, + {0x3419, 0x0a, 0, 0}, + {0x341a, 0x08, 0, 0}, + {0x341b, 0x04, 0, 0}, + {0x341c, 0x04, 0, 0}, + {0x341d, 0x00, 0, 0}, + {0x341e, 0x03, 0, 0}, + {0x3440, 0x00, 0, 0}, + {0x3441, 0x00, 0, 0}, + {0x3442, 0x00, 0, 0}, + {0x3443, 0x00, 0, 0}, + {0x3444, 0x02, 0, 0}, + {0x3445, 0xf0, 0, 0}, + {0x3446, 0x02, 0, 0}, + {0x3447, 0x08, 0, 0}, + {0x3448, 0x00, 0, 0}, + {0x3460, 0x40, 0, 0}, + {0x3461, 0x40, 0, 0}, + {0x3462, 0x40, 0, 0}, + {0x3463, 0x40, 0, 0}, + {0x3464, 0x03, 0, 0}, + {0x3465, 0x01, 0, 0}, + {0x3466, 0x01, 0, 0}, + {0x3467, 0x02, 0, 0}, + {0x3468, 0x30, 0, 0}, + {0x3469, 0x00, 0, 0}, + {0x346a, 0x33, 0, 0}, + {0x346b, 0xbf, 0, 0}, + {0x3480, 0x40, 0, 0}, + {0x3481, 0x00, 0, 0}, + {0x3482, 0x00, 0, 0}, + {0x3483, 0x00, 0, 0}, + {0x3484, 0x0d, 0, 0}, + {0x3485, 0x00, 0, 0}, + {0x3486, 0x00, 0, 0}, + {0x3487, 0x00, 0, 0}, + {0x3488, 0x00, 0, 0}, + {0x3489, 0x00, 0, 0}, + {0x348a, 0x00, 0, 0}, + {0x348b, 0x04, 0, 0}, + {0x348c, 0x00, 0, 0}, + {0x348d, 0x01, 0, 0}, + {0x348f, 0x01, 0, 0}, + {0x3030, 0x0a, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x7000, 0x58, 0, 0}, + {0x7001, 0x7a, 0, 0}, + {0x7002, 0x1a, 0, 0}, + {0x7003, 0xc1, 0, 0}, + {0x7004, 0x03, 0, 0}, + {0x7005, 0xda, 0, 0}, + {0x7006, 0xbd, 0, 0}, + {0x7007, 0x03, 0, 0}, + {0x7008, 0xbd, 0, 0}, + {0x7009, 0x06, 0, 0}, + {0x700a, 0xe6, 0, 0}, + {0x700b, 0xec, 0, 0}, + {0x700c, 0xbc, 0, 0}, + {0x700d, 0xff, 0, 0}, + {0x700e, 0xbc, 0, 0}, + {0x700f, 0x73, 0, 0}, + {0x7010, 0xda, 0, 0}, + {0x7011, 0x72, 0, 0}, + {0x7012, 0x76, 0, 0}, + {0x7013, 0xb6, 0, 0}, + {0x7014, 0xee, 0, 0}, + {0x7015, 0xcf, 0, 0}, + {0x7016, 0xac, 0, 0}, + {0x7017, 0xd0, 0, 0}, + {0x7018, 0xac, 0, 0}, + {0x7019, 0xd1, 0, 0}, + {0x701a, 0x50, 0, 0}, + {0x701b, 0xac, 0, 0}, + {0x701c, 0xd2, 0, 0}, + {0x701d, 0xbc, 0, 0}, + {0x701e, 0x2e, 0, 0}, + {0x701f, 0xb4, 0, 0}, + {0x7020, 0x00, 0, 0}, + {0x7021, 0xdc, 0, 0}, + {0x7022, 0xdf, 0, 0}, + {0x7023, 0xb0, 0, 0}, + {0x7024, 0x6e, 0, 0}, + {0x7025, 0xbd, 0, 0}, + {0x7026, 0x01, 0, 0}, + {0x7027, 0xd7, 0, 0}, + {0x7028, 0xed, 0, 0}, + {0x7029, 0xe1, 0, 0}, + {0x702a, 0x36, 0, 0}, + {0x702b, 0x30, 0, 0}, + {0x702c, 0xd3, 0, 0}, + {0x702d, 0x2e, 0, 0}, + {0x702e, 0x54, 0, 0}, + {0x702f, 0x46, 0, 0}, + {0x7030, 0xbc, 0, 0}, + {0x7031, 0x22, 0, 0}, + {0x7032, 0x66, 0, 0}, + {0x7033, 0xbc, 0, 0}, + {0x7034, 0x24, 0, 0}, + {0x7035, 0x2c, 0, 0}, + {0x7036, 0x28, 0, 0}, + {0x7037, 0xbc, 0, 0}, + {0x7038, 0x3c, 0, 0}, + {0x7039, 0xa1, 0, 0}, + {0x703a, 0xac, 0, 0}, + {0x703b, 0xd8, 0, 0}, + {0x703c, 0xd6, 0, 0}, + {0x703d, 0xb4, 0, 0}, + {0x703e, 0x04, 0, 0}, + {0x703f, 0x46, 0, 0}, + {0x7040, 0xb7, 0, 0}, + {0x7041, 0x04, 0, 0}, + {0x7042, 0xbe, 0, 0}, + {0x7043, 0x08, 0, 0}, + {0x7044, 0xc3, 0, 0}, + {0x7045, 0xd9, 0, 0}, + {0x7046, 0xad, 0, 0}, + {0x7047, 0xc3, 0, 0}, + {0x7048, 0xbc, 0, 0}, + {0x7049, 0x19, 0, 0}, + {0x704a, 0xc1, 0, 0}, + {0x704b, 0x27, 0, 0}, + {0x704c, 0xe7, 0, 0}, + {0x704d, 0x00, 0, 0}, + {0x704e, 0x50, 0, 0}, + {0x704f, 0x20, 0, 0}, + {0x7050, 0xb8, 0, 0}, + {0x7051, 0x02, 0, 0}, + {0x7052, 0xbc, 0, 0}, + {0x7053, 0x17, 0, 0}, + {0x7054, 0xdb, 0, 0}, + {0x7055, 0xc7, 0, 0}, + {0x7056, 0xb8, 0, 0}, + {0x7057, 0x00, 0, 0}, + {0x7058, 0x28, 0, 0}, + {0x7059, 0x54, 0, 0}, + {0x705a, 0xb4, 0, 0}, + {0x705b, 0x14, 0, 0}, + {0x705c, 0xab, 0, 0}, + {0x705d, 0xbe, 0, 0}, + {0x705e, 0x06, 0, 0}, + {0x705f, 0xd8, 0, 0}, + {0x7060, 0xd6, 0, 0}, + {0x7061, 0x00, 0, 0}, + {0x7062, 0xb4, 0, 0}, + {0x7063, 0xc7, 0, 0}, + {0x7064, 0x07, 0, 0}, + {0x7065, 0xb9, 0, 0}, + {0x7066, 0x05, 0, 0}, + {0x7067, 0xee, 0, 0}, + {0x7068, 0xe6, 0, 0}, + {0x7069, 0xad, 0, 0}, + {0x706a, 0xb4, 0, 0}, + {0x706b, 0x26, 0, 0}, + {0x706c, 0x19, 0, 0}, + {0x706d, 0xc1, 0, 0}, + {0x706e, 0x3a, 0, 0}, + {0x706f, 0xc3, 0, 0}, + {0x7070, 0xaf, 0, 0}, + {0x7071, 0x00, 0, 0}, + {0x7072, 0xc0, 0, 0}, + {0x7073, 0x3c, 0, 0}, + {0x7074, 0xc3, 0, 0}, + {0x7075, 0xbe, 0, 0}, + {0x7076, 0xe7, 0, 0}, + {0x7077, 0x00, 0, 0}, + {0x7078, 0x15, 0, 0}, + {0x7079, 0xc2, 0, 0}, + {0x707a, 0x40, 0, 0}, + {0x707b, 0xc3, 0, 0}, + {0x707c, 0xa4, 0, 0}, + {0x707d, 0xc0, 0, 0}, + {0x707e, 0x3c, 0, 0}, + {0x707f, 0x00, 0, 0}, + {0x7080, 0xb9, 0, 0}, + {0x7081, 0x64, 0, 0}, + {0x7082, 0x29, 0, 0}, + {0x7083, 0x00, 0, 0}, + {0x7084, 0xb8, 0, 0}, + {0x7085, 0x12, 0, 0}, + {0x7086, 0xbe, 0, 0}, + {0x7087, 0x01, 0, 0}, + {0x7088, 0xd0, 0, 0}, + {0x7089, 0xbc, 0, 0}, + {0x708a, 0x01, 0, 0}, + {0x708b, 0xac, 0, 0}, + {0x708c, 0x37, 0, 0}, + {0x708d, 0xd2, 0, 0}, + {0x708e, 0xac, 0, 0}, + {0x708f, 0x45, 0, 0}, + {0x7090, 0xad, 0, 0}, + {0x7091, 0x28, 0, 0}, + {0x7092, 0x00, 0, 0}, + {0x7093, 0xb8, 0, 0}, + {0x7094, 0x00, 0, 0}, + {0x7095, 0xbc, 0, 0}, + {0x7096, 0x01, 0, 0}, + {0x7097, 0x36, 0, 0}, + {0x7098, 0xd3, 0, 0}, + {0x7099, 0x30, 0, 0}, + {0x709a, 0x04, 0, 0}, + {0x709b, 0xe0, 0, 0}, + {0x709c, 0xd8, 0, 0}, + {0x709d, 0xb4, 0, 0}, + {0x709e, 0xe9, 0, 0}, + {0x709f, 0x00, 0, 0}, + {0x70a0, 0xbe, 0, 0}, + {0x70a1, 0x05, 0, 0}, + {0x70a2, 0x62, 0, 0}, + {0x70a3, 0x07, 0, 0}, + {0x70a4, 0xb9, 0, 0}, + {0x70a5, 0x05, 0, 0}, + {0x70a6, 0xad, 0, 0}, + {0x70a7, 0xc3, 0, 0}, + {0x70a8, 0xcf, 0, 0}, + {0x70a9, 0x00, 0, 0}, + {0x70aa, 0x15, 0, 0}, + {0x70ab, 0xc2, 0, 0}, + {0x70ac, 0x59, 0, 0}, + {0x70ad, 0xc3, 0, 0}, + {0x70ae, 0xc9, 0, 0}, + {0x70af, 0xc0, 0, 0}, + {0x70b0, 0x55, 0, 0}, + {0x70b1, 0x00, 0, 0}, + {0x70b2, 0x46, 0, 0}, + {0x70b3, 0xa1, 0, 0}, + {0x70b4, 0xb9, 0, 0}, + {0x70b5, 0x64, 0, 0}, + {0x70b6, 0x29, 0, 0}, + {0x70b7, 0x00, 0, 0}, + {0x70b8, 0xb8, 0, 0}, + {0x70b9, 0x02, 0, 0}, + {0x70ba, 0xbe, 0, 0}, + {0x70bb, 0x02, 0, 0}, + {0x70bc, 0xd0, 0, 0}, + {0x70bd, 0xdc, 0, 0}, + {0x70be, 0xac, 0, 0}, + {0x70bf, 0xbc, 0, 0}, + {0x70c0, 0x01, 0, 0}, + {0x70c1, 0x37, 0, 0}, + {0x70c2, 0xac, 0, 0}, + {0x70c3, 0xd2, 0, 0}, + {0x70c4, 0x45, 0, 0}, + {0x70c5, 0xad, 0, 0}, + {0x70c6, 0x28, 0, 0}, + {0x70c7, 0x00, 0, 0}, + {0x70c8, 0xb8, 0, 0}, + {0x70c9, 0x00, 0, 0}, + {0x70ca, 0xbc, 0, 0}, + {0x70cb, 0x01, 0, 0}, + {0x70cc, 0x36, 0, 0}, + {0x70cd, 0x30, 0, 0}, + {0x70ce, 0xe0, 0, 0}, + {0x70cf, 0xd8, 0, 0}, + {0x70d0, 0xb5, 0, 0}, + {0x70d1, 0x0b, 0, 0}, + {0x70d2, 0xd6, 0, 0}, + {0x70d3, 0xbe, 0, 0}, + {0x70d4, 0x07, 0, 0}, + {0x70d5, 0x00, 0, 0}, + {0x70d6, 0x62, 0, 0}, + {0x70d7, 0x07, 0, 0}, + {0x70d8, 0xb9, 0, 0}, + {0x70d9, 0x05, 0, 0}, + {0x70da, 0xad, 0, 0}, + {0x70db, 0xc3, 0, 0}, + {0x70dc, 0xcf, 0, 0}, + {0x70dd, 0x46, 0, 0}, + {0x70de, 0xcd, 0, 0}, + {0x70df, 0x07, 0, 0}, + {0x70e0, 0xcd, 0, 0}, + {0x70e1, 0x00, 0, 0}, + {0x70e2, 0xe3, 0, 0}, + {0x70e3, 0x18, 0, 0}, + {0x70e4, 0xc2, 0, 0}, + {0x70e5, 0xa2, 0, 0}, + {0x70e6, 0xb9, 0, 0}, + {0x70e7, 0x64, 0, 0}, + {0x70e8, 0xd1, 0, 0}, + {0x70e9, 0xdd, 0, 0}, + {0x70ea, 0xac, 0, 0}, + {0x70eb, 0xcf, 0, 0}, + {0x70ec, 0xdf, 0, 0}, + {0x70ed, 0xb5, 0, 0}, + {0x70ee, 0x19, 0, 0}, + {0x70ef, 0x46, 0, 0}, + {0x70f0, 0x50, 0, 0}, + {0x70f1, 0xb6, 0, 0}, + {0x70f2, 0xee, 0, 0}, + {0x70f3, 0xe8, 0, 0}, + {0x70f4, 0xe6, 0, 0}, + {0x70f5, 0xbc, 0, 0}, + {0x70f6, 0x31, 0, 0}, + {0x70f7, 0xe1, 0, 0}, + {0x70f8, 0x36, 0, 0}, + {0x70f9, 0x30, 0, 0}, + {0x70fa, 0xd3, 0, 0}, + {0x70fb, 0x2e, 0, 0}, + {0x70fc, 0x54, 0, 0}, + {0x70fd, 0xbd, 0, 0}, + {0x70fe, 0x03, 0, 0}, + {0x70ff, 0xec, 0, 0}, + {0x7100, 0x2c, 0, 0}, + {0x7101, 0x50, 0, 0}, + {0x7102, 0x20, 0, 0}, + {0x7103, 0x04, 0, 0}, + {0x7104, 0xb8, 0, 0}, + {0x7105, 0x02, 0, 0}, + {0x7106, 0xbc, 0, 0}, + {0x7107, 0x18, 0, 0}, + {0x7108, 0xc7, 0, 0}, + {0x7109, 0xb8, 0, 0}, + {0x710a, 0x00, 0, 0}, + {0x710b, 0x28, 0, 0}, + {0x710c, 0x54, 0, 0}, + {0x710d, 0xbc, 0, 0}, + {0x710e, 0x02, 0, 0}, + {0x710f, 0xb4, 0, 0}, + {0x7110, 0xda, 0, 0}, + {0x7111, 0xbe, 0, 0}, + {0x7112, 0x04, 0, 0}, + {0x7113, 0xd6, 0, 0}, + {0x7114, 0xd8, 0, 0}, + {0x7115, 0xab, 0, 0}, + {0x7116, 0x00, 0, 0}, + {0x7117, 0x62, 0, 0}, + {0x7118, 0x07, 0, 0}, + {0x7119, 0xb9, 0, 0}, + {0x711a, 0x05, 0, 0}, + {0x711b, 0xad, 0, 0}, + {0x711c, 0xc3, 0, 0}, + {0x711d, 0xbc, 0, 0}, + {0x711e, 0xe7, 0, 0}, + {0x711f, 0xb9, 0, 0}, + {0x7120, 0x64, 0, 0}, + {0x7121, 0x29, 0, 0}, + {0x7122, 0x00, 0, 0}, + {0x7123, 0xb8, 0, 0}, + {0x7124, 0x02, 0, 0}, + {0x7125, 0xbe, 0, 0}, + {0x7126, 0x00, 0, 0}, + {0x7127, 0x45, 0, 0}, + {0x7128, 0xad, 0, 0}, + {0x7129, 0xe2, 0, 0}, + {0x712a, 0x28, 0, 0}, + {0x712b, 0x00, 0, 0}, + {0x712c, 0xb8, 0, 0}, + {0x712d, 0x00, 0, 0}, + {0x712e, 0xe0, 0, 0}, + {0x712f, 0xd8, 0, 0}, + {0x7130, 0xb4, 0, 0}, + {0x7131, 0xe9, 0, 0}, + {0x7132, 0xbe, 0, 0}, + {0x7133, 0x03, 0, 0}, + {0x7134, 0x00, 0, 0}, + {0x7135, 0x30, 0, 0}, + {0x7136, 0x62, 0, 0}, + {0x7137, 0x07, 0, 0}, + {0x7138, 0xb9, 0, 0}, + {0x7139, 0x05, 0, 0}, + {0x713a, 0xad, 0, 0}, + {0x713b, 0xc3, 0, 0}, + {0x713c, 0xcf, 0, 0}, + {0x713d, 0x42, 0, 0}, + {0x713e, 0xe4, 0, 0}, + {0x713f, 0xcd, 0, 0}, + {0x7140, 0x07, 0, 0}, + {0x7141, 0xcd, 0, 0}, + {0x7142, 0x00, 0, 0}, + {0x7143, 0x00, 0, 0}, + {0x7144, 0x17, 0, 0}, + {0x7145, 0xc2, 0, 0}, + {0x7146, 0xbb, 0, 0}, + {0x7147, 0xde, 0, 0}, + {0x7148, 0xcf, 0, 0}, + {0x7149, 0xdf, 0, 0}, + {0x714a, 0xac, 0, 0}, + {0x714b, 0xd1, 0, 0}, + {0x714c, 0x44, 0, 0}, + {0x714d, 0xac, 0, 0}, + {0x714e, 0xb9, 0, 0}, + {0x714f, 0x76, 0, 0}, + {0x7150, 0xb8, 0, 0}, + {0x7151, 0x08, 0, 0}, + {0x7152, 0xb6, 0, 0}, + {0x7153, 0xfe, 0, 0}, + {0x7154, 0xb4, 0, 0}, + {0x7155, 0xca, 0, 0}, + {0x7156, 0xd6, 0, 0}, + {0x7157, 0xd8, 0, 0}, + {0x7158, 0xab, 0, 0}, + {0x7159, 0x00, 0, 0}, + {0x715a, 0xe1, 0, 0}, + {0x715b, 0x36, 0, 0}, + {0x715c, 0x30, 0, 0}, + {0x715d, 0xd3, 0, 0}, + {0x715e, 0xbc, 0, 0}, + {0x715f, 0x29, 0, 0}, + {0x7160, 0xb4, 0, 0}, + {0x7161, 0x1f, 0, 0}, + {0x7162, 0xaa, 0, 0}, + {0x7163, 0xbd, 0, 0}, + {0x7164, 0x01, 0, 0}, + {0x7165, 0xb8, 0, 0}, + {0x7166, 0x0c, 0, 0}, + {0x7167, 0x45, 0, 0}, + {0x7168, 0xa4, 0, 0}, + {0x7169, 0xbd, 0, 0}, + {0x716a, 0x03, 0, 0}, + {0x716b, 0xec, 0, 0}, + {0x716c, 0xbc, 0, 0}, + {0x716d, 0x3d, 0, 0}, + {0x716e, 0xc3, 0, 0}, + {0x716f, 0xcf, 0, 0}, + {0x7170, 0x42, 0, 0}, + {0x7171, 0xb8, 0, 0}, + {0x7172, 0x00, 0, 0}, + {0x7173, 0xe4, 0, 0}, + {0x7174, 0xd5, 0, 0}, + {0x7175, 0x00, 0, 0}, + {0x7176, 0xb6, 0, 0}, + {0x7177, 0x00, 0, 0}, + {0x7178, 0x74, 0, 0}, + {0x7179, 0xbd, 0, 0}, + {0x717a, 0x03, 0, 0}, + {0x717b, 0xb5, 0, 0}, + {0x717c, 0x39, 0, 0}, + {0x717d, 0x40, 0, 0}, + {0x717e, 0x58, 0, 0}, + {0x717f, 0xdd, 0, 0}, + {0x7180, 0x19, 0, 0}, + {0x7181, 0xc1, 0, 0}, + {0x7182, 0xc8, 0, 0}, + {0x7183, 0xbd, 0, 0}, + {0x7184, 0x06, 0, 0}, + {0x7185, 0x17, 0, 0}, + {0x7186, 0xc1, 0, 0}, + {0x7187, 0xc6, 0, 0}, + {0x7188, 0xe8, 0, 0}, + {0x7189, 0x00, 0, 0}, + {0x718a, 0xc0, 0, 0}, + {0x718b, 0xc8, 0, 0}, + {0x718c, 0xe6, 0, 0}, + {0x718d, 0x95, 0, 0}, + {0x718e, 0x15, 0, 0}, + {0x718f, 0x00, 0, 0}, + {0x7190, 0xbc, 0, 0}, + {0x7191, 0x19, 0, 0}, + {0x7192, 0xb9, 0, 0}, + {0x7193, 0xf6, 0, 0}, + {0x7194, 0x14, 0, 0}, + {0x7195, 0xc1, 0, 0}, + {0x7196, 0xd0, 0, 0}, + {0x7197, 0xd1, 0, 0}, + {0x7198, 0xac, 0, 0}, + {0x7199, 0x37, 0, 0}, + {0x719a, 0xbc, 0, 0}, + {0x719b, 0x35, 0, 0}, + {0x719c, 0x36, 0, 0}, + {0x719d, 0x30, 0, 0}, + {0x719e, 0xe1, 0, 0}, + {0x719f, 0xd3, 0, 0}, + {0x71a0, 0x7a, 0, 0}, + {0x71a1, 0xb6, 0, 0}, + {0x71a2, 0x0c, 0, 0}, + {0x71a3, 0xff, 0, 0}, + {0x71a4, 0xb4, 0, 0}, + {0x71a5, 0xc7, 0, 0}, + {0x71a6, 0xd9, 0, 0}, + {0x71a7, 0x00, 0, 0}, + {0x71a8, 0xbd, 0, 0}, + {0x71a9, 0x01, 0, 0}, + {0x71aa, 0x56, 0, 0}, + {0x71ab, 0xc0, 0, 0}, + {0x71ac, 0xda, 0, 0}, + {0x71ad, 0xb4, 0, 0}, + {0x71ae, 0x1f, 0, 0}, + {0x71af, 0x56, 0, 0}, + {0x71b0, 0xaa, 0, 0}, + {0x71b1, 0xbc, 0, 0}, + {0x71b2, 0x08, 0, 0}, + {0x71b3, 0x00, 0, 0}, + {0x71b4, 0x57, 0, 0}, + {0x71b5, 0xe8, 0, 0}, + {0x71b6, 0xb5, 0, 0}, + {0x71b7, 0x36, 0, 0}, + {0x71b8, 0x00, 0, 0}, + {0x71b9, 0x54, 0, 0}, + {0x71ba, 0xe7, 0, 0}, + {0x71bb, 0xc8, 0, 0}, + {0x71bc, 0xb4, 0, 0}, + {0x71bd, 0x1f, 0, 0}, + {0x71be, 0x56, 0, 0}, + {0x71bf, 0xaa, 0, 0}, + {0x71c0, 0xbc, 0, 0}, + {0x71c1, 0x08, 0, 0}, + {0x71c2, 0x57, 0, 0}, + {0x71c3, 0x00, 0, 0}, + {0x71c4, 0xb5, 0, 0}, + {0x71c5, 0x36, 0, 0}, + {0x71c6, 0x00, 0, 0}, + {0x71c7, 0x54, 0, 0}, + {0x71c8, 0xc8, 0, 0}, + {0x71c9, 0xb5, 0, 0}, + {0x71ca, 0x18, 0, 0}, + {0x71cb, 0xd9, 0, 0}, + {0x71cc, 0x00, 0, 0}, + {0x71cd, 0xbd, 0, 0}, + {0x71ce, 0x01, 0, 0}, + {0x71cf, 0x56, 0, 0}, + {0x71d0, 0x08, 0, 0}, + {0x71d1, 0x57, 0, 0}, + {0x71d2, 0xe8, 0, 0}, + {0x71d3, 0xb4, 0, 0}, + {0x71d4, 0x42, 0, 0}, + {0x71d5, 0x00, 0, 0}, + {0x71d6, 0x54, 0, 0}, + {0x71d7, 0xe7, 0, 0}, + {0x71d8, 0xc8, 0, 0}, + {0x71d9, 0xab, 0, 0}, + {0x71da, 0x00, 0, 0}, + {0x71db, 0x66, 0, 0}, + {0x71dc, 0x62, 0, 0}, + {0x71dd, 0x06, 0, 0}, + {0x71de, 0x74, 0, 0}, + {0x71df, 0xb9, 0, 0}, + {0x71e0, 0x05, 0, 0}, + {0x71e1, 0xb7, 0, 0}, + {0x71e2, 0x14, 0, 0}, + {0x71e3, 0x0e, 0, 0}, + {0x71e4, 0xb7, 0, 0}, + {0x71e5, 0x04, 0, 0}, + {0x71e6, 0xc8, 0, 0}, + {0x7600, 0x04, 0, 0}, + {0x7601, 0x80, 0, 0}, + {0x7602, 0x07, 0, 0}, + {0x7603, 0x44, 0, 0}, + {0x7604, 0x05, 0, 0}, + {0x7605, 0x33, 0, 0}, + {0x7606, 0x0f, 0, 0}, + {0x7607, 0x00, 0, 0}, + {0x7608, 0x07, 0, 0}, + {0x7609, 0x40, 0, 0}, + {0x760a, 0x04, 0, 0}, + {0x760b, 0xe5, 0, 0}, + {0x760c, 0x06, 0, 0}, + {0x760d, 0x50, 0, 0}, + {0x760e, 0x04, 0, 0}, + {0x760f, 0xe4, 0, 0}, + {0x7610, 0x00, 0, 0}, + {0x7611, 0x00, 0, 0}, + {0x7612, 0x06, 0, 0}, + {0x7613, 0x5c, 0, 0}, + {0x7614, 0x00, 0, 0}, + {0x7615, 0x0f, 0, 0}, + {0x7616, 0x06, 0, 0}, + {0x7617, 0x1c, 0, 0}, + {0x7618, 0x00, 0, 0}, + {0x7619, 0x02, 0, 0}, + {0x761a, 0x06, 0, 0}, + {0x761b, 0xa2, 0, 0}, + {0x761c, 0x00, 0, 0}, + {0x761d, 0x01, 0, 0}, + {0x761e, 0x06, 0, 0}, + {0x761f, 0xae, 0, 0}, + {0x7620, 0x00, 0, 0}, + {0x7621, 0x0e, 0, 0}, + {0x7622, 0x05, 0, 0}, + {0x7623, 0x30, 0, 0}, + {0x7624, 0x07, 0, 0}, + {0x7625, 0x00, 0, 0}, + {0x7626, 0x0f, 0, 0}, + {0x7627, 0x00, 0, 0}, + {0x7628, 0x04, 0, 0}, + {0x7629, 0xe5, 0, 0}, + {0x762a, 0x05, 0, 0}, + {0x762b, 0x33, 0, 0}, + {0x762c, 0x06, 0, 0}, + {0x762d, 0x12, 0, 0}, + {0x762e, 0x00, 0, 0}, + {0x762f, 0x01, 0, 0}, + {0x7630, 0x06, 0, 0}, + {0x7631, 0x52, 0, 0}, + {0x7632, 0x00, 0, 0}, + {0x7633, 0x01, 0, 0}, + {0x7634, 0x06, 0, 0}, + {0x7635, 0x5e, 0, 0}, + {0x7636, 0x04, 0, 0}, + {0x7637, 0xe4, 0, 0}, + {0x7638, 0x00, 0, 0}, + {0x7639, 0x01, 0, 0}, + {0x763a, 0x05, 0, 0}, + {0x763b, 0x30, 0, 0}, + {0x763c, 0x0f, 0, 0}, + {0x763d, 0x00, 0, 0}, + {0x763e, 0x06, 0, 0}, + {0x763f, 0xa6, 0, 0}, + {0x7640, 0x00, 0, 0}, + {0x7641, 0x02, 0, 0}, + {0x7642, 0x06, 0, 0}, + {0x7643, 0x26, 0, 0}, + {0x7644, 0x00, 0, 0}, + {0x7645, 0x02, 0, 0}, + {0x7646, 0x05, 0, 0}, + {0x7647, 0x33, 0, 0}, + {0x7648, 0x06, 0, 0}, + {0x7649, 0x20, 0, 0}, + {0x764a, 0x0f, 0, 0}, + {0x764b, 0x00, 0, 0}, + {0x764c, 0x06, 0, 0}, + {0x764d, 0x56, 0, 0}, + {0x764e, 0x00, 0, 0}, + {0x764f, 0x02, 0, 0}, + {0x7650, 0x06, 0, 0}, + {0x7651, 0x16, 0, 0}, + {0x7652, 0x05, 0, 0}, + {0x7653, 0x33, 0, 0}, + {0x7654, 0x06, 0, 0}, + {0x7655, 0x10, 0, 0}, + {0x7656, 0x0f, 0, 0}, + {0x7657, 0x00, 0, 0}, + {0x7658, 0x06, 0, 0}, + {0x7659, 0x10, 0, 0}, + {0x765a, 0x0f, 0, 0}, + {0x765b, 0x00, 0, 0}, + {0x765c, 0x06, 0, 0}, + {0x765d, 0x20, 0, 0}, + {0x765e, 0x0f, 0, 0}, + {0x765f, 0x00, 0, 0}, + {0x7660, 0x00, 0, 0}, + {0x7661, 0x00, 0, 0}, + {0x7662, 0x00, 0, 0}, + {0x7663, 0x02, 0, 0}, + {0x7664, 0x04, 0, 0}, + {0x7665, 0xe5, 0, 0}, + {0x7666, 0x04, 0, 0}, + {0x7667, 0xe4, 0, 0}, + {0x7668, 0x0f, 0, 0}, + {0x7669, 0x00, 0, 0}, + {0x766a, 0x00, 0, 0}, + {0x766b, 0x00, 0, 0}, + {0x766c, 0x00, 0, 0}, + {0x766d, 0x01, 0, 0}, + {0x766e, 0x04, 0, 0}, + {0x766f, 0xe5, 0, 0}, + {0x7670, 0x04, 0, 0}, + {0x7671, 0xe4, 0, 0}, + {0x7672, 0x0f, 0, 0}, + {0x7673, 0x00, 0, 0}, + {0x7674, 0x00, 0, 0}, + {0x7675, 0x02, 0, 0}, + {0x7676, 0x04, 0, 0}, + {0x7677, 0xe4, 0, 0}, + {0x7678, 0x00, 0, 0}, + {0x7679, 0x02, 0, 0}, + {0x767a, 0x04, 0, 0}, + {0x767b, 0xc4, 0, 0}, + {0x767c, 0x00, 0, 0}, + {0x767d, 0x02, 0, 0}, + {0x767e, 0x04, 0, 0}, + {0x767f, 0xc4, 0, 0}, + {0x7680, 0x05, 0, 0}, + {0x7681, 0x83, 0, 0}, + {0x7682, 0x0f, 0, 0}, + {0x7683, 0x00, 0, 0}, + {0x7684, 0x00, 0, 0}, + {0x7685, 0x02, 0, 0}, + {0x7686, 0x04, 0, 0}, + {0x7687, 0xe4, 0, 0}, + {0x7688, 0x00, 0, 0}, + {0x7689, 0x02, 0, 0}, + {0x768a, 0x04, 0, 0}, + {0x768b, 0xc4, 0, 0}, + {0x768c, 0x00, 0, 0}, + {0x768d, 0x02, 0, 0}, + {0x768e, 0x04, 0, 0}, + {0x768f, 0xc4, 0, 0}, + {0x7690, 0x05, 0, 0}, + {0x7691, 0x83, 0, 0}, + {0x7692, 0x03, 0, 0}, + {0x7693, 0x0b, 0, 0}, + {0x7694, 0x05, 0, 0}, + {0x7695, 0x83, 0, 0}, + {0x7696, 0x00, 0, 0}, + {0x7697, 0x07, 0, 0}, + {0x7698, 0x05, 0, 0}, + {0x7699, 0x03, 0, 0}, + {0x769a, 0x00, 0, 0}, + {0x769b, 0x05, 0, 0}, + {0x769c, 0x05, 0, 0}, + {0x769d, 0x32, 0, 0}, + {0x769e, 0x05, 0, 0}, + {0x769f, 0x30, 0, 0}, + {0x76a0, 0x00, 0, 0}, + {0x76a1, 0x02, 0, 0}, + {0x76a2, 0x05, 0, 0}, + {0x76a3, 0x78, 0, 0}, + {0x76a4, 0x00, 0, 0}, + {0x76a5, 0x01, 0, 0}, + {0x76a6, 0x05, 0, 0}, + {0x76a7, 0x7c, 0, 0}, + {0x76a8, 0x03, 0, 0}, + {0x76a9, 0x9a, 0, 0}, + {0x76aa, 0x05, 0, 0}, + {0x76ab, 0x83, 0, 0}, + {0x76ac, 0x00, 0, 0}, + {0x76ad, 0x04, 0, 0}, + {0x76ae, 0x05, 0, 0}, + {0x76af, 0x03, 0, 0}, + {0x76b0, 0x00, 0, 0}, + {0x76b1, 0x03, 0, 0}, + {0x76b2, 0x05, 0, 0}, + {0x76b3, 0x32, 0, 0}, + {0x76b4, 0x05, 0, 0}, + {0x76b5, 0x30, 0, 0}, + {0x76b6, 0x00, 0, 0}, + {0x76b7, 0x02, 0, 0}, + {0x76b8, 0x05, 0, 0}, + {0x76b9, 0x78, 0, 0}, + {0x76ba, 0x00, 0, 0}, + {0x76bb, 0x01, 0, 0}, + {0x76bc, 0x05, 0, 0}, + {0x76bd, 0x7c, 0, 0}, + {0x76be, 0x03, 0, 0}, + {0x76bf, 0x99, 0, 0}, + {0x76c0, 0x05, 0, 0}, + {0x76c1, 0x83, 0, 0}, + {0x76c2, 0x00, 0, 0}, + {0x76c3, 0x03, 0, 0}, + {0x76c4, 0x05, 0, 0}, + {0x76c5, 0x03, 0, 0}, + {0x76c6, 0x00, 0, 0}, + {0x76c7, 0x01, 0, 0}, + {0x76c8, 0x05, 0, 0}, + {0x76c9, 0x32, 0, 0}, + {0x76ca, 0x05, 0, 0}, + {0x76cb, 0x30, 0, 0}, + {0x76cc, 0x00, 0, 0}, + {0x76cd, 0x02, 0, 0}, + {0x76ce, 0x05, 0, 0}, + {0x76cf, 0x78, 0, 0}, + {0x76d0, 0x00, 0, 0}, + {0x76d1, 0x01, 0, 0}, + {0x76d2, 0x05, 0, 0}, + {0x76d3, 0x7c, 0, 0}, + {0x76d4, 0x03, 0, 0}, + {0x76d5, 0x98, 0, 0}, + {0x76d6, 0x05, 0, 0}, + {0x76d7, 0x83, 0, 0}, + {0x76d8, 0x00, 0, 0}, + {0x76d9, 0x00, 0, 0}, + {0x76da, 0x05, 0, 0}, + {0x76db, 0x03, 0, 0}, + {0x76dc, 0x00, 0, 0}, + {0x76dd, 0x01, 0, 0}, + {0x76de, 0x05, 0, 0}, + {0x76df, 0x32, 0, 0}, + {0x76e0, 0x05, 0, 0}, + {0x76e1, 0x30, 0, 0}, + {0x76e2, 0x00, 0, 0}, + {0x76e3, 0x02, 0, 0}, + {0x76e4, 0x05, 0, 0}, + {0x76e5, 0x78, 0, 0}, + {0x76e6, 0x00, 0, 0}, + {0x76e7, 0x01, 0, 0}, + {0x76e8, 0x05, 0, 0}, + {0x76e9, 0x7c, 0, 0}, + {0x76ea, 0x03, 0, 0}, + {0x76eb, 0x97, 0, 0}, + {0x76ec, 0x05, 0, 0}, + {0x76ed, 0x83, 0, 0}, + {0x76ee, 0x00, 0, 0}, + {0x76ef, 0x00, 0, 0}, + {0x76f0, 0x05, 0, 0}, + {0x76f1, 0x03, 0, 0}, + {0x76f2, 0x05, 0, 0}, + {0x76f3, 0x32, 0, 0}, + {0x76f4, 0x05, 0, 0}, + {0x76f5, 0x30, 0, 0}, + {0x76f6, 0x00, 0, 0}, + {0x76f7, 0x02, 0, 0}, + {0x76f8, 0x05, 0, 0}, + {0x76f9, 0x78, 0, 0}, + {0x76fa, 0x00, 0, 0}, + {0x76fb, 0x01, 0, 0}, + {0x76fc, 0x05, 0, 0}, + {0x76fd, 0x7c, 0, 0}, + {0x76fe, 0x03, 0, 0}, + {0x76ff, 0x96, 0, 0}, + {0x7700, 0x05, 0, 0}, + {0x7701, 0x83, 0, 0}, + {0x7702, 0x05, 0, 0}, + {0x7703, 0x03, 0, 0}, + {0x7704, 0x05, 0, 0}, + {0x7705, 0x32, 0, 0}, + {0x7706, 0x05, 0, 0}, + {0x7707, 0x30, 0, 0}, + {0x7708, 0x00, 0, 0}, + {0x7709, 0x02, 0, 0}, + {0x770a, 0x05, 0, 0}, + {0x770b, 0x78, 0, 0}, + {0x770c, 0x00, 0, 0}, + {0x770d, 0x01, 0, 0}, + {0x770e, 0x05, 0, 0}, + {0x770f, 0x7c, 0, 0}, + {0x7710, 0x03, 0, 0}, + {0x7711, 0x95, 0, 0}, + {0x7712, 0x05, 0, 0}, + {0x7713, 0x83, 0, 0}, + {0x7714, 0x05, 0, 0}, + {0x7715, 0x03, 0, 0}, + {0x7716, 0x05, 0, 0}, + {0x7717, 0x32, 0, 0}, + {0x7718, 0x05, 0, 0}, + {0x7719, 0x30, 0, 0}, + {0x771a, 0x00, 0, 0}, + {0x771b, 0x02, 0, 0}, + {0x771c, 0x05, 0, 0}, + {0x771d, 0x78, 0, 0}, + {0x771e, 0x00, 0, 0}, + {0x771f, 0x01, 0, 0}, + {0x7720, 0x05, 0, 0}, + {0x7721, 0x7c, 0, 0}, + {0x7722, 0x03, 0, 0}, + {0x7723, 0x94, 0, 0}, + {0x7724, 0x05, 0, 0}, + {0x7725, 0x83, 0, 0}, + {0x7726, 0x00, 0, 0}, + {0x7727, 0x01, 0, 0}, + {0x7728, 0x05, 0, 0}, + {0x7729, 0x03, 0, 0}, + {0x772a, 0x00, 0, 0}, + {0x772b, 0x01, 0, 0}, + {0x772c, 0x05, 0, 0}, + {0x772d, 0x32, 0, 0}, + {0x772e, 0x05, 0, 0}, + {0x772f, 0x30, 0, 0}, + {0x7730, 0x00, 0, 0}, + {0x7731, 0x02, 0, 0}, + {0x7732, 0x05, 0, 0}, + {0x7733, 0x78, 0, 0}, + {0x7734, 0x00, 0, 0}, + {0x7735, 0x01, 0, 0}, + {0x7736, 0x05, 0, 0}, + {0x7737, 0x7c, 0, 0}, + {0x7738, 0x03, 0, 0}, + {0x7739, 0x93, 0, 0}, + {0x773a, 0x05, 0, 0}, + {0x773b, 0x83, 0, 0}, + {0x773c, 0x00, 0, 0}, + {0x773d, 0x00, 0, 0}, + {0x773e, 0x05, 0, 0}, + {0x773f, 0x03, 0, 0}, + {0x7740, 0x00, 0, 0}, + {0x7741, 0x00, 0, 0}, + {0x7742, 0x05, 0, 0}, + {0x7743, 0x32, 0, 0}, + {0x7744, 0x05, 0, 0}, + {0x7745, 0x30, 0, 0}, + {0x7746, 0x00, 0, 0}, + {0x7747, 0x02, 0, 0}, + {0x7748, 0x05, 0, 0}, + {0x7749, 0x78, 0, 0}, + {0x774a, 0x00, 0, 0}, + {0x774b, 0x01, 0, 0}, + {0x774c, 0x05, 0, 0}, + {0x774d, 0x7c, 0, 0}, + {0x774e, 0x03, 0, 0}, + {0x774f, 0x92, 0, 0}, + {0x7750, 0x05, 0, 0}, + {0x7751, 0x83, 0, 0}, + {0x7752, 0x05, 0, 0}, + {0x7753, 0x03, 0, 0}, + {0x7754, 0x00, 0, 0}, + {0x7755, 0x00, 0, 0}, + {0x7756, 0x05, 0, 0}, + {0x7757, 0x32, 0, 0}, + {0x7758, 0x05, 0, 0}, + {0x7759, 0x30, 0, 0}, + {0x775a, 0x00, 0, 0}, + {0x775b, 0x02, 0, 0}, + {0x775c, 0x05, 0, 0}, + {0x775d, 0x78, 0, 0}, + {0x775e, 0x00, 0, 0}, + {0x775f, 0x01, 0, 0}, + {0x7760, 0x05, 0, 0}, + {0x7761, 0x7c, 0, 0}, + {0x7762, 0x03, 0, 0}, + {0x7763, 0x91, 0, 0}, + {0x7764, 0x05, 0, 0}, + {0x7765, 0x83, 0, 0}, + {0x7766, 0x05, 0, 0}, + {0x7767, 0x03, 0, 0}, + {0x7768, 0x05, 0, 0}, + {0x7769, 0x32, 0, 0}, + {0x776a, 0x05, 0, 0}, + {0x776b, 0x30, 0, 0}, + {0x776c, 0x00, 0, 0}, + {0x776d, 0x02, 0, 0}, + {0x776e, 0x05, 0, 0}, + {0x776f, 0x78, 0, 0}, + {0x7770, 0x00, 0, 0}, + {0x7771, 0x01, 0, 0}, + {0x7772, 0x05, 0, 0}, + {0x7773, 0x7c, 0, 0}, + {0x7774, 0x03, 0, 0}, + {0x7775, 0x90, 0, 0}, + {0x7776, 0x05, 0, 0}, + {0x7777, 0x83, 0, 0}, + {0x7778, 0x05, 0, 0}, + {0x7779, 0x03, 0, 0}, + {0x777a, 0x05, 0, 0}, + {0x777b, 0x32, 0, 0}, + {0x777c, 0x05, 0, 0}, + {0x777d, 0x30, 0, 0}, + {0x777e, 0x00, 0, 0}, + {0x777f, 0x02, 0, 0}, + {0x7780, 0x05, 0, 0}, + {0x7781, 0x78, 0, 0}, + {0x7782, 0x00, 0, 0}, + {0x7783, 0x01, 0, 0}, + {0x7784, 0x05, 0, 0}, + {0x7785, 0x7c, 0, 0}, + {0x7786, 0x02, 0, 0}, + {0x7787, 0x90, 0, 0}, + {0x7788, 0x05, 0, 0}, + {0x7789, 0x03, 0, 0}, + {0x778a, 0x07, 0, 0}, + {0x778b, 0x00, 0, 0}, + {0x778c, 0x0f, 0, 0}, + {0x778d, 0x00, 0, 0}, + {0x778e, 0x08, 0, 0}, + {0x778f, 0x30, 0, 0}, + {0x7790, 0x08, 0, 0}, + {0x7791, 0xee, 0, 0}, + {0x7792, 0x0f, 0, 0}, + {0x7793, 0x00, 0, 0}, + {0x7794, 0x05, 0, 0}, + {0x7795, 0x33, 0, 0}, + {0x7796, 0x04, 0, 0}, + {0x7797, 0xe5, 0, 0}, + {0x7798, 0x06, 0, 0}, + {0x7799, 0x52, 0, 0}, + {0x779a, 0x04, 0, 0}, + {0x779b, 0xe4, 0, 0}, + {0x779c, 0x00, 0, 0}, + {0x779d, 0x00, 0, 0}, + {0x779e, 0x06, 0, 0}, + {0x779f, 0x5e, 0, 0}, + {0x77a0, 0x00, 0, 0}, + {0x77a1, 0x0f, 0, 0}, + {0x77a2, 0x06, 0, 0}, + {0x77a3, 0x1e, 0, 0}, + {0x77a4, 0x00, 0, 0}, + {0x77a5, 0x02, 0, 0}, + {0x77a6, 0x06, 0, 0}, + {0x77a7, 0xa2, 0, 0}, + {0x77a8, 0x00, 0, 0}, + {0x77a9, 0x01, 0, 0}, + {0x77aa, 0x06, 0, 0}, + {0x77ab, 0xae, 0, 0}, + {0x77ac, 0x00, 0, 0}, + {0x77ad, 0x03, 0, 0}, + {0x77ae, 0x05, 0, 0}, + {0x77af, 0x30, 0, 0}, + {0x77b0, 0x09, 0, 0}, + {0x77b1, 0x19, 0, 0}, + {0x77b2, 0x0f, 0, 0}, + {0x77b3, 0x00, 0, 0}, + {0x77b4, 0x05, 0, 0}, + {0x77b5, 0x33, 0, 0}, + {0x77b6, 0x04, 0, 0}, + {0x77b7, 0xe5, 0, 0}, + {0x77b8, 0x06, 0, 0}, + {0x77b9, 0x52, 0, 0}, + {0x77ba, 0x04, 0, 0}, + {0x77bb, 0xe4, 0, 0}, + {0x77bc, 0x00, 0, 0}, + {0x77bd, 0x00, 0, 0}, + {0x77be, 0x06, 0, 0}, + {0x77bf, 0x5e, 0, 0}, + {0x77c0, 0x00, 0, 0}, + {0x77c1, 0x0f, 0, 0}, + {0x77c2, 0x06, 0, 0}, + {0x77c3, 0x1e, 0, 0}, + {0x77c4, 0x00, 0, 0}, + {0x77c5, 0x02, 0, 0}, + {0x77c6, 0x06, 0, 0}, + {0x77c7, 0xa2, 0, 0}, + {0x77c8, 0x00, 0, 0}, + {0x77c9, 0x01, 0, 0}, + {0x77ca, 0x06, 0, 0}, + {0x77cb, 0xae, 0, 0}, + {0x77cc, 0x00, 0, 0}, + {0x77cd, 0x03, 0, 0}, + {0x77ce, 0x05, 0, 0}, + {0x77cf, 0x30, 0, 0}, + {0x77d0, 0x0f, 0, 0}, + {0x77d1, 0x00, 0, 0}, + {0x77d2, 0x00, 0, 0}, + {0x77d3, 0x00, 0, 0}, + {0x77d4, 0x00, 0, 0}, + {0x77d5, 0x02, 0, 0}, + {0x77d6, 0x04, 0, 0}, + {0x77d7, 0xe5, 0, 0}, + {0x77d8, 0x04, 0, 0}, + {0x77d9, 0xe4, 0, 0}, + {0x77da, 0x05, 0, 0}, + {0x77db, 0x33, 0, 0}, + {0x77dc, 0x07, 0, 0}, + {0x77dd, 0x10, 0, 0}, + {0x77de, 0x00, 0, 0}, + {0x77df, 0x00, 0, 0}, + {0x77e0, 0x01, 0, 0}, + {0x77e1, 0xbb, 0, 0}, + {0x77e2, 0x00, 0, 0}, + {0x77e3, 0x00, 0, 0}, + {0x77e4, 0x01, 0, 0}, + {0x77e5, 0xaa, 0, 0}, + {0x77e6, 0x00, 0, 0}, + {0x77e7, 0x00, 0, 0}, + {0x77e8, 0x01, 0, 0}, + {0x77e9, 0x99, 0, 0}, + {0x77ea, 0x00, 0, 0}, + {0x77eb, 0x00, 0, 0}, + {0x77ec, 0x01, 0, 0}, + {0x77ed, 0x88, 0, 0}, + {0x77ee, 0x00, 0, 0}, + {0x77ef, 0x00, 0, 0}, + {0x77f0, 0x01, 0, 0}, + {0x77f1, 0x77, 0, 0}, + {0x77f2, 0x00, 0, 0}, + {0x77f3, 0x00, 0, 0}, + {0x77f4, 0x01, 0, 0}, + {0x77f5, 0x66, 0, 0}, + {0x77f6, 0x00, 0, 0}, + {0x77f7, 0x00, 0, 0}, + {0x77f8, 0x01, 0, 0}, + {0x77f9, 0x55, 0, 0}, + {0x77fa, 0x00, 0, 0}, + {0x77fb, 0x00, 0, 0}, + {0x77fc, 0x01, 0, 0}, + {0x77fd, 0x44, 0, 0}, + {0x77fe, 0x00, 0, 0}, + {0x77ff, 0x00, 0, 0}, + {0x7800, 0x01, 0, 0}, + {0x7801, 0x33, 0, 0}, + {0x7802, 0x00, 0, 0}, + {0x7803, 0x00, 0, 0}, + {0x7804, 0x01, 0, 0}, + {0x7805, 0x22, 0, 0}, + {0x7806, 0x00, 0, 0}, + {0x7807, 0x00, 0, 0}, + {0x7808, 0x01, 0, 0}, + {0x7809, 0x11, 0, 0}, + {0x780a, 0x00, 0, 0}, + {0x780b, 0x00, 0, 0}, + {0x780c, 0x01, 0, 0}, + {0x780d, 0x00, 0, 0}, + {0x780e, 0x01, 0, 0}, + {0x780f, 0xff, 0, 0}, + {0x7810, 0x07, 0, 0}, + {0x7811, 0x00, 0, 0}, + {0x7812, 0x02, 0, 0}, + {0x7813, 0xa0, 0, 0}, + {0x7814, 0x0f, 0, 0}, + {0x7815, 0x00, 0, 0}, + {0x7816, 0x08, 0, 0}, + {0x7817, 0x35, 0, 0}, + {0x7818, 0x06, 0, 0}, + {0x7819, 0x52, 0, 0}, + {0x781a, 0x04, 0, 0}, + {0x781b, 0xe4, 0, 0}, + {0x781c, 0x00, 0, 0}, + {0x781d, 0x00, 0, 0}, + {0x781e, 0x06, 0, 0}, + {0x781f, 0x5e, 0, 0}, + {0x7820, 0x05, 0, 0}, + {0x7821, 0x33, 0, 0}, + {0x7822, 0x09, 0, 0}, + {0x7823, 0x19, 0, 0}, + {0x7824, 0x06, 0, 0}, + {0x7825, 0x1e, 0, 0}, + {0x7826, 0x05, 0, 0}, + {0x7827, 0x33, 0, 0}, + {0x7828, 0x00, 0, 0}, + {0x7829, 0x01, 0, 0}, + {0x782a, 0x06, 0, 0}, + {0x782b, 0x24, 0, 0}, + {0x782c, 0x06, 0, 0}, + {0x782d, 0x20, 0, 0}, + {0x782e, 0x0f, 0, 0}, + {0x782f, 0x00, 0, 0}, + {0x7830, 0x08, 0, 0}, + {0x7831, 0x35, 0, 0}, + {0x7832, 0x07, 0, 0}, + {0x7833, 0x10, 0, 0}, + {0x7834, 0x00, 0, 0}, + {0x7835, 0x00, 0, 0}, + {0x7836, 0x01, 0, 0}, + {0x7837, 0xbb, 0, 0}, + {0x7838, 0x00, 0, 0}, + {0x7839, 0x00, 0, 0}, + {0x783a, 0x01, 0, 0}, + {0x783b, 0xaa, 0, 0}, + {0x783c, 0x00, 0, 0}, + {0x783d, 0x00, 0, 0}, + {0x783e, 0x01, 0, 0}, + {0x783f, 0x99, 0, 0}, + {0x7840, 0x00, 0, 0}, + {0x7841, 0x00, 0, 0}, + {0x7842, 0x01, 0, 0}, + {0x7843, 0x88, 0, 0}, + {0x7844, 0x00, 0, 0}, + {0x7845, 0x00, 0, 0}, + {0x7846, 0x01, 0, 0}, + {0x7847, 0x77, 0, 0}, + {0x7848, 0x00, 0, 0}, + {0x7849, 0x00, 0, 0}, + {0x784a, 0x01, 0, 0}, + {0x784b, 0x66, 0, 0}, + {0x784c, 0x00, 0, 0}, + {0x784d, 0x00, 0, 0}, + {0x784e, 0x01, 0, 0}, + {0x784f, 0x55, 0, 0}, + {0x7850, 0x00, 0, 0}, + {0x7851, 0x00, 0, 0}, + {0x7852, 0x01, 0, 0}, + {0x7853, 0x44, 0, 0}, + {0x7854, 0x00, 0, 0}, + {0x7855, 0x00, 0, 0}, + {0x7856, 0x01, 0, 0}, + {0x7857, 0x33, 0, 0}, + {0x7858, 0x00, 0, 0}, + {0x7859, 0x00, 0, 0}, + {0x785a, 0x01, 0, 0}, + {0x785b, 0x22, 0, 0}, + {0x785c, 0x00, 0, 0}, + {0x785d, 0x00, 0, 0}, + {0x785e, 0x01, 0, 0}, + {0x785f, 0x11, 0, 0}, + {0x7860, 0x00, 0, 0}, + {0x7861, 0x00, 0, 0}, + {0x7862, 0x01, 0, 0}, + {0x7863, 0x00, 0, 0}, + {0x7864, 0x07, 0, 0}, + {0x7865, 0x00, 0, 0}, + {0x7866, 0x01, 0, 0}, + {0x7867, 0xff, 0, 0}, + {0x7868, 0x02, 0, 0}, + {0x7869, 0xa0, 0, 0}, + {0x786a, 0x0f, 0, 0}, + {0x786b, 0x00, 0, 0}, + {0x786c, 0x08, 0, 0}, + {0x786d, 0x3a, 0, 0}, + {0x786e, 0x08, 0, 0}, + {0x786f, 0x6a, 0, 0}, + {0x7870, 0x0f, 0, 0}, + {0x7871, 0x00, 0, 0}, + {0x7872, 0x04, 0, 0}, + {0x7873, 0xc0, 0, 0}, + {0x7874, 0x09, 0, 0}, + {0x7875, 0x19, 0, 0}, + {0x7876, 0x04, 0, 0}, + {0x7877, 0x99, 0, 0}, + {0x7878, 0x07, 0, 0}, + {0x7879, 0x14, 0, 0}, + {0x787a, 0x00, 0, 0}, + {0x787b, 0x01, 0, 0}, + {0x787c, 0x04, 0, 0}, + {0x787d, 0xa4, 0, 0}, + {0x787e, 0x00, 0, 0}, + {0x787f, 0x07, 0, 0}, + {0x7880, 0x04, 0, 0}, + {0x7881, 0xa6, 0, 0}, + {0x7882, 0x00, 0, 0}, + {0x7883, 0x00, 0, 0}, + {0x7884, 0x04, 0, 0}, + {0x7885, 0xa0, 0, 0}, + {0x7886, 0x04, 0, 0}, + {0x7887, 0x80, 0, 0}, + {0x7888, 0x04, 0, 0}, + {0x7889, 0x00, 0, 0}, + {0x788a, 0x05, 0, 0}, + {0x788b, 0x03, 0, 0}, + {0x788c, 0x06, 0, 0}, + {0x788d, 0x00, 0, 0}, + {0x788e, 0x0f, 0, 0}, + {0x788f, 0x00, 0, 0}, + {0x7890, 0x0f, 0, 0}, + {0x7891, 0x00, 0, 0}, + {0x7892, 0x0f, 0, 0}, + {0x7893, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x05, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x04, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x80, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x38, 0, 0}, + {0x30b0, 0x0b, 0, 0},//HTS_H 0x0d + {0x30b1, 0x1c, 0, 0},//HTS_L 0xde + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x66, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x80, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x0a, 0, 0}, + {0x3195, 0x29, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x80, 0, 0}, + {0x30bb, 0x01, 0, 0}, + {0x3250, 0xf7, 0, 0}, + + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x08, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x08, 0, 0}, + + + {0x30c0, 0x08, 0, 0}, + {0x3252, 0x20, 0, 0}, +}; + +#endif diff --git a/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr.h b/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr.h new file mode 100755 index 0000000..84bb765 --- /dev/null +++ b/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr.h @@ -0,0 +1,1885 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OV2775_REGS_1080PHDR_H_ +#define _VVCAM_OV2775_REGS_1080PHDR_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t ov2775_init_setting_1080p_hdr[] = { + {0x3000, 0x02, 0, 0}, + {0x3001, 0x28, 0, 0}, + {0x3002, 0x03, 0, 0}, + {0x3003, 0x01, 0, 0}, + {0x3004, 0x02, 0, 0}, + {0x3005, 0x26, 0, 0}, + {0x3006, 0x00, 0, 0}, + {0x3007, 0x07, 0, 0}, + {0x3008, 0x01, 0, 0}, + {0x3009, 0x00, 0, 0}, + {0x300c, 0x6c, 0, 0}, + {0x300e, 0x80, 0, 0}, + {0x300f, 0x00, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3013, 0x00, 0, 0}, + {0x3014, 0xc4, 0, 0}, + {0x3015, 0x00, 0, 0}, + {0x3017, 0x00, 0, 0}, + {0x3018, 0x00, 0, 0}, + {0x3019, 0x00, 0, 0}, + {0x301a, 0x00, 0, 0}, + {0x301b, 0x0e, 0, 0}, + {0x301e, 0x17, 0, 0}, + {0x301f, 0xe1, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x3031, 0x62, 0, 0}, + {0x3032, 0xf0, 0, 0}, + {0x3033, 0x30, 0, 0}, + {0x3034, 0x3f, 0, 0}, + {0x3035, 0x5f, 0, 0}, + {0x3036, 0x02, 0, 0}, + {0x3037, 0x9f, 0, 0}, + {0x3038, 0x04, 0, 0}, + {0x3039, 0xb7, 0, 0}, + {0x303a, 0x04, 0, 0}, + {0x303b, 0x07, 0, 0}, + {0x303c, 0xf0, 0, 0}, + {0x303d, 0x00, 0, 0}, + {0x303e, 0x0b, 0, 0}, + {0x303f, 0xe3, 0, 0}, + {0x3040, 0xf3, 0, 0}, + {0x3041, 0x29, 0, 0}, + {0x3042, 0xf6, 0, 0}, + {0x3043, 0x65, 0, 0}, + {0x3044, 0x06, 0, 0}, + {0x3045, 0x0f, 0, 0}, + {0x3046, 0x59, 0, 0}, + {0x3047, 0x07, 0, 0}, + {0x3048, 0x82, 0, 0}, + {0x3049, 0xcf, 0, 0}, + {0x304a, 0x12, 0, 0}, + {0x304b, 0x40, 0, 0}, + {0x304c, 0x33, 0, 0}, + {0x304d, 0xa4, 0, 0}, + {0x304e, 0x0b, 0, 0}, + {0x304f, 0x3d, 0, 0}, + {0x3050, 0x10, 0, 0}, + {0x3060, 0x00, 0, 0}, + {0x3061, 0x64, 0, 0}, + {0x3062, 0x00, 0, 0}, + {0x3063, 0xe4, 0, 0}, + {0x3066, 0x80, 0, 0}, + {0x3080, 0x00, 0, 0}, + {0x3081, 0x00, 0, 0}, + {0x3082, 0x01, 0, 0}, + {0x3083, 0xe3, 0, 0}, + {0x3084, 0x06, 0, 0}, + {0x3085, 0x00, 0, 0}, + {0x3086, 0x10, 0, 0}, + {0x3087, 0x10, 0, 0}, + {0x3089, 0x00, 0, 0}, + {0x308a, 0x01, 0, 0}, + {0x3093, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x00, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x00, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x90, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x48, 0, 0}, + {0x30b0, 0x08, 0, 0}, + {0x30b1, 0xae, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x65, 0, 0}, + {0x30b4, 0x00, 0, 0}, + {0x30b5, 0x00, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x10, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x02, 0, 0}, + {0x30ba, 0x10, 0, 0}, + {0x30bb, 0x00, 0, 0}, + {0x30bc, 0x00, 0, 0}, + {0x30bd, 0x03, 0, 0}, + {0x30be, 0x5c, 0, 0}, + {0x30bf, 0x00, 0, 0}, + {0x30c0, 0x05, 0, 0}, + {0x30c1, 0x00, 0, 0}, + {0x30c2, 0x20, 0, 0}, + {0x30c3, 0x00, 0, 0}, + {0x30c4, 0x4a, 0, 0}, + {0x30c5, 0x00, 0, 0}, + {0x30c7, 0x00, 0, 0}, + {0x30c8, 0x00, 0, 0}, + {0x30d1, 0x00, 0, 0}, + {0x30d2, 0x00, 0, 0}, + {0x30d3, 0x80, 0, 0}, + {0x30d4, 0x00, 0, 0}, + {0x30d9, 0x09, 0, 0}, + {0x30da, 0x64, 0, 0}, + {0x30dd, 0x00, 0, 0}, + {0x30de, 0x16, 0, 0}, + {0x30df, 0x00, 0, 0}, + {0x30e0, 0x17, 0, 0}, + {0x30e1, 0x00, 0, 0}, + {0x30e2, 0x18, 0, 0}, + {0x30e3, 0x10, 0, 0}, + {0x30e4, 0x04, 0, 0}, + {0x30e5, 0x00, 0, 0}, + {0x30e6, 0x00, 0, 0}, + {0x30e7, 0x00, 0, 0}, + {0x30e8, 0x00, 0, 0}, + {0x30e9, 0x00, 0, 0}, + {0x30ea, 0x00, 0, 0}, + {0x30eb, 0x00, 0, 0}, + {0x30ec, 0x00, 0, 0}, + {0x30ed, 0x00, 0, 0}, + {0x3101, 0x00, 0, 0}, + {0x3102, 0x00, 0, 0}, + {0x3103, 0x00, 0, 0}, + {0x3104, 0x00, 0, 0}, + {0x3105, 0x8c, 0, 0}, + {0x3106, 0x87, 0, 0}, + {0x3107, 0xc0, 0, 0}, + {0x3108, 0x9d, 0, 0}, + {0x3109, 0x8d, 0, 0}, + {0x310a, 0x8d, 0, 0}, + {0x310b, 0x6a, 0, 0}, + {0x310c, 0x3a, 0, 0}, + {0x310d, 0x5a, 0, 0}, + {0x310e, 0x00, 0, 0}, + {0x3120, 0x00, 0, 0}, + {0x3121, 0x00, 0, 0}, + {0x3122, 0x00, 0, 0}, + {0x3123, 0x00, 0, 0}, + {0x3124, 0x00, 0, 0}, + {0x3125, 0x70, 0, 0}, + {0x3126, 0x1f, 0, 0}, + {0x3127, 0x0f, 0, 0}, + {0x3128, 0x00, 0, 0}, + {0x3129, 0x3a, 0, 0}, + {0x312a, 0x02, 0, 0}, + {0x312b, 0x0f, 0, 0}, + {0x312c, 0x00, 0, 0}, + {0x312d, 0x0f, 0, 0}, + {0x312e, 0x1d, 0, 0}, + {0x312f, 0x00, 0, 0}, + {0x3130, 0x00, 0, 0}, + {0x3131, 0x00, 0, 0}, + {0x3132, 0x00, 0, 0}, + {0x3140, 0x0a, 0, 0}, + {0x3141, 0x03, 0, 0}, + {0x3142, 0x00, 0, 0}, + {0x3143, 0x00, 0, 0}, + {0x3144, 0x00, 0, 0}, + {0x3145, 0x00, 0, 0}, + {0x3146, 0x00, 0, 0}, + {0x3147, 0x00, 0, 0}, + {0x3148, 0x00, 0, 0}, + {0x3149, 0x00, 0, 0}, + {0x314a, 0x00, 0, 0}, + {0x314b, 0x00, 0, 0}, + {0x314c, 0x00, 0, 0}, + {0x314d, 0x00, 0, 0}, + {0x314e, 0x1c, 0, 0}, + {0x314f, 0xff, 0, 0}, + {0x3150, 0xff, 0, 0}, + {0x3151, 0xff, 0, 0}, + {0x3152, 0x10, 0, 0}, + {0x3153, 0x10, 0, 0}, + {0x3154, 0x10, 0, 0}, + {0x3155, 0x00, 0, 0}, + {0x3156, 0x03, 0, 0}, + {0x3157, 0x00, 0, 0}, + {0x3158, 0x0f, 0, 0}, + {0x3159, 0xff, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x00, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x00, 0, 0}, + {0x3160, 0x00, 0, 0}, + {0x3161, 0x40, 0, 0}, + {0x3162, 0x00, 0, 0}, + {0x3163, 0x40, 0, 0}, + {0x3164, 0x00, 0, 0}, + {0x3165, 0x40, 0, 0}, + {0x3190, 0x05, 0, 0}, + {0x3191, 0x99, 0, 0}, + {0x3193, 0x08, 0, 0}, + {0x3194, 0x13, 0, 0}, + {0x3195, 0x33, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x10, 0, 0}, + {0x3198, 0x00, 0, 0}, + {0x3199, 0x3f, 0, 0}, + {0x319a, 0x40, 0, 0}, + {0x319b, 0x7f, 0, 0}, + {0x319c, 0x80, 0, 0}, + {0x319d, 0xbf, 0, 0}, + {0x319e, 0xc0, 0, 0}, + {0x319f, 0xff, 0, 0}, + {0x31a0, 0x24, 0, 0}, + {0x31a1, 0x55, 0, 0}, + {0x31a2, 0x00, 0, 0}, + {0x31a3, 0x00, 0, 0}, + {0x31a6, 0x00, 0, 0}, + {0x31a7, 0x00, 0, 0}, + {0x31b0, 0x00, 0, 0}, + {0x31b1, 0x00, 0, 0}, + {0x31b2, 0x02, 0, 0}, + {0x31b3, 0x00, 0, 0}, + {0x31b4, 0x00, 0, 0}, + {0x31b5, 0x01, 0, 0}, + {0x31b6, 0x00, 0, 0}, + {0x31b7, 0x00, 0, 0}, + {0x31b8, 0x00, 0, 0}, + {0x31b9, 0x00, 0, 0}, + {0x31ba, 0x00, 0, 0}, + {0x31d0, 0x3c, 0, 0}, + {0x31d1, 0x34, 0, 0}, + {0x31d2, 0x3c, 0, 0}, + {0x31d3, 0x00, 0, 0}, + {0x31d4, 0x2d, 0, 0}, + {0x31d5, 0x00, 0, 0}, + {0x31d6, 0x01, 0, 0}, + {0x31d7, 0x06, 0, 0}, + {0x31d8, 0x00, 0, 0}, + {0x31d9, 0x64, 0, 0}, + {0x31da, 0x00, 0, 0}, + {0x31db, 0x30, 0, 0}, + {0x31dc, 0x04, 0, 0}, + {0x31dd, 0x69, 0, 0}, + {0x31de, 0x0a, 0, 0}, + {0x31df, 0x3c, 0, 0}, + {0x31e0, 0x04, 0, 0}, + {0x31e1, 0x32, 0, 0}, + {0x31e2, 0x00, 0, 0}, + {0x31e3, 0x00, 0, 0}, + {0x31e4, 0x08, 0, 0}, + {0x31e5, 0x80, 0, 0}, + {0x31e6, 0x00, 0, 0}, + {0x31e7, 0x2c, 0, 0}, + {0x31e8, 0x6c, 0, 0}, + {0x31e9, 0xac, 0, 0}, + {0x31ea, 0xec, 0, 0}, + {0x31eb, 0x3f, 0, 0}, + {0x31ec, 0x07, 0, 0}, + {0x31ed, 0x80, 0, 0}, + {0x31ee, 0x04, 0, 0}, + {0x31ef, 0x38, 0, 0}, + {0x31f0, 0x07, 0, 0}, + {0x31f1, 0x80, 0, 0}, + {0x31f2, 0x04, 0, 0}, + {0x31f3, 0x38, 0, 0}, + {0x31f4, 0x07, 0, 0}, + {0x31f5, 0x80, 0, 0}, + {0x31f6, 0x04, 0, 0}, + {0x31f7, 0x38, 0, 0}, + {0x31f8, 0x07, 0, 0}, + {0x31f9, 0x80, 0, 0}, + {0x31fa, 0x04, 0, 0}, + {0x31fb, 0x38, 0, 0}, + {0x31fd, 0xcb, 0, 0}, + {0x31fe, 0x0f, 0, 0}, + {0x31ff, 0x03, 0, 0}, + {0x3200, 0x00, 0, 0}, + {0x3201, 0xff, 0, 0}, + {0x3202, 0x00, 0, 0}, + {0x3203, 0xff, 0, 0}, + {0x3204, 0xff, 0, 0}, + {0x3205, 0xff, 0, 0}, + {0x3206, 0xff, 0, 0}, + {0x3207, 0xff, 0, 0}, + {0x3208, 0xff, 0, 0}, + {0x3209, 0xff, 0, 0}, + {0x320a, 0xff, 0, 0}, + {0x320b, 0x1b, 0, 0}, + {0x320c, 0x1f, 0, 0}, + {0x320d, 0x1e, 0, 0}, + {0x320e, 0x30, 0, 0}, + {0x320f, 0x2d, 0, 0}, + {0x3210, 0x2c, 0, 0}, + {0x3211, 0x2b, 0, 0}, + {0x3212, 0x2a, 0, 0}, + {0x3213, 0x24, 0, 0}, + {0x3214, 0x22, 0, 0}, + {0x3215, 0x00, 0, 0}, + {0x3216, 0x04, 0, 0}, + {0x3217, 0x2c, 0, 0}, + {0x3218, 0x6c, 0, 0}, + {0x3219, 0xac, 0, 0}, + {0x321a, 0xec, 0, 0}, + {0x321b, 0x00, 0, 0}, + {0x3230, 0x3a, 0, 0}, + {0x3231, 0x00, 0, 0}, + {0x3232, 0x80, 0, 0}, + {0x3233, 0x00, 0, 0}, + {0x3234, 0x10, 0, 0}, + {0x3235, 0xaa, 0, 0}, + {0x3236, 0x55, 0, 0}, + {0x3237, 0x99, 0, 0}, + {0x3238, 0x66, 0, 0}, + {0x3239, 0x08, 0, 0}, + {0x323a, 0x88, 0, 0}, + {0x323b, 0x00, 0, 0}, + {0x323c, 0x00, 0, 0}, + {0x323d, 0x03, 0, 0}, + {0x3250, 0x33, 0, 0}, + {0x3251, 0x00, 0, 0}, + {0x3252, 0x20, 0, 0}, + {0x3253, 0x00, 0, 0}, + {0x3254, 0x11, 0, 0}, + {0x3255, 0x01, 0, 0}, + {0x3256, 0x00, 0, 0}, + {0x3257, 0x00, 0, 0}, + {0x3258, 0x00, 0, 0}, + {0x3270, 0x01, 0, 0}, + {0x3271, 0x60, 0, 0}, + {0x3272, 0xc0, 0, 0}, + {0x3273, 0x00, 0, 0}, + {0x3274, 0x80, 0, 0}, + {0x3275, 0x40, 0, 0}, + {0x3276, 0x02, 0, 0}, + {0x3277, 0x08, 0, 0}, + {0x3278, 0x10, 0, 0}, + {0x3279, 0x04, 0, 0}, + {0x327a, 0x00, 0, 0}, + {0x327b, 0x03, 0, 0}, + {0x327c, 0x10, 0, 0}, + {0x327d, 0x60, 0, 0}, + {0x327e, 0xc0, 0, 0}, + {0x327f, 0x06, 0, 0}, + {0x3288, 0x10, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x08, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x04, 0, 0}, + {0x328d, 0x00, 0, 0}, + {0x328e, 0x02, 0, 0}, + {0x328f, 0x00, 0, 0}, + {0x3290, 0x20, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x10, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x08, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x04, 0, 0}, + {0x3297, 0x00, 0, 0}, + {0x3298, 0x40, 0, 0}, + {0x3299, 0x00, 0, 0}, + {0x329a, 0x20, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x10, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x08, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x40, 0, 0}, + {0x32a3, 0x00, 0, 0}, + {0x32a4, 0x20, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x10, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32a8, 0x00, 0, 0}, + {0x32a9, 0x00, 0, 0}, + {0x32aa, 0x00, 0, 0}, + {0x32ab, 0x00, 0, 0}, + {0x32ac, 0x00, 0, 0}, + {0x32ad, 0x00, 0, 0}, + {0x32ae, 0x00, 0, 0}, + {0x32af, 0x00, 0, 0}, + {0x32b0, 0x00, 0, 0}, + {0x32b1, 0x00, 0, 0}, + {0x32b2, 0x00, 0, 0}, + {0x32b3, 0x00, 0, 0}, + {0x32b4, 0x00, 0, 0}, + {0x32b5, 0x00, 0, 0}, + {0x32b6, 0x00, 0, 0}, + {0x32b7, 0x00, 0, 0}, + {0x32b8, 0x00, 0, 0}, + {0x32b9, 0x00, 0, 0}, + {0x32ba, 0x00, 0, 0}, + {0x32bb, 0x00, 0, 0}, + {0x32bc, 0x00, 0, 0}, + {0x32bd, 0x00, 0, 0}, + {0x32be, 0x00, 0, 0}, + {0x32bf, 0x00, 0, 0}, + {0x32c0, 0x00, 0, 0}, + {0x32c1, 0x00, 0, 0}, + {0x32c2, 0x00, 0, 0}, + {0x32c3, 0x00, 0, 0}, + {0x32c4, 0x00, 0, 0}, + {0x32c5, 0x00, 0, 0}, + {0x32c6, 0x00, 0, 0}, + {0x32c7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x32c9, 0x00, 0, 0}, + {0x3330, 0x03, 0, 0}, + {0x3331, 0xc8, 0, 0}, + {0x3332, 0x02, 0, 0}, + {0x3333, 0x24, 0, 0}, + {0x3334, 0x00, 0, 0}, + {0x3335, 0x00, 0, 0}, + {0x3336, 0x00, 0, 0}, + {0x3337, 0x00, 0, 0}, + {0x3338, 0x03, 0, 0}, + {0x3339, 0xc8, 0, 0}, + {0x333a, 0x02, 0, 0}, + {0x333b, 0x24, 0, 0}, + {0x333c, 0x00, 0, 0}, + {0x333d, 0x00, 0, 0}, + {0x333e, 0x00, 0, 0}, + {0x333f, 0x00, 0, 0}, + {0x3340, 0x03, 0, 0}, + {0x3341, 0xc8, 0, 0}, + {0x3342, 0x02, 0, 0}, + {0x3343, 0x24, 0, 0}, + {0x3344, 0x00, 0, 0}, + {0x3345, 0x00, 0, 0}, + {0x3346, 0x00, 0, 0}, + {0x3347, 0x00, 0, 0}, + {0x3348, 0x40, 0, 0}, + {0x3349, 0x00, 0, 0}, + {0x334a, 0x00, 0, 0}, + {0x334b, 0x00, 0, 0}, + {0x334c, 0x00, 0, 0}, + {0x334d, 0x00, 0, 0}, + {0x334e, 0x80, 0, 0}, + {0x3360, 0x01, 0, 0}, + {0x3361, 0x00, 0, 0}, + {0x3362, 0x01, 0, 0}, + {0x3363, 0x00, 0, 0}, + {0x3364, 0x01, 0, 0}, + {0x3365, 0x00, 0, 0}, + {0x3366, 0x01, 0, 0}, + {0x3367, 0x00, 0, 0}, + {0x3368, 0x01, 0, 0}, + {0x3369, 0x00, 0, 0}, + {0x336a, 0x01, 0, 0}, + {0x336b, 0x00, 0, 0}, + {0x336c, 0x01, 0, 0}, + {0x336d, 0x00, 0, 0}, + {0x336e, 0x01, 0, 0}, + {0x336f, 0x00, 0, 0}, + {0x3370, 0x01, 0, 0}, + {0x3371, 0x00, 0, 0}, + {0x3372, 0x01, 0, 0}, + {0x3373, 0x00, 0, 0}, + {0x3374, 0x01, 0, 0}, + {0x3375, 0x00, 0, 0}, + {0x3376, 0x01, 0, 0}, + {0x3377, 0x00, 0, 0}, + {0x3378, 0x00, 0, 0}, + {0x3379, 0x00, 0, 0}, + {0x337a, 0x00, 0, 0}, + {0x337b, 0x00, 0, 0}, + {0x337c, 0x00, 0, 0}, + {0x337d, 0x00, 0, 0}, + {0x337e, 0x00, 0, 0}, + {0x337f, 0x00, 0, 0}, + {0x3380, 0x00, 0, 0}, + {0x3381, 0x00, 0, 0}, + {0x3382, 0x00, 0, 0}, + {0x3383, 0x00, 0, 0}, + {0x3384, 0x00, 0, 0}, + {0x3385, 0x00, 0, 0}, + {0x3386, 0x00, 0, 0}, + {0x3387, 0x00, 0, 0}, + {0x3388, 0x00, 0, 0}, + {0x3389, 0x00, 0, 0}, + {0x338a, 0x00, 0, 0}, + {0x338b, 0x00, 0, 0}, + {0x338c, 0x00, 0, 0}, + {0x338d, 0x00, 0, 0}, + {0x338e, 0x00, 0, 0}, + {0x338f, 0x00, 0, 0}, + {0x3390, 0x00, 0, 0}, + {0x3391, 0x00, 0, 0}, + {0x3392, 0x00, 0, 0}, + {0x3393, 0x00, 0, 0}, + {0x3394, 0x00, 0, 0}, + {0x3395, 0x00, 0, 0}, + {0x3396, 0x00, 0, 0}, + {0x3397, 0x00, 0, 0}, + {0x3398, 0x00, 0, 0}, + {0x3399, 0x00, 0, 0}, + {0x339a, 0x00, 0, 0}, + {0x339b, 0x00, 0, 0}, + {0x33b0, 0x00, 0, 0}, + {0x33b1, 0x50, 0, 0}, + {0x33b2, 0x01, 0, 0}, + {0x33b3, 0xff, 0, 0}, + {0x33b4, 0xe0, 0, 0}, + {0x33b5, 0x6b, 0, 0}, + {0x33b6, 0x00, 0, 0}, + {0x33b7, 0x00, 0, 0}, + {0x33b8, 0x00, 0, 0}, + {0x33b9, 0x00, 0, 0}, + {0x33ba, 0x00, 0, 0}, + {0x33bb, 0x1f, 0, 0}, + {0x33bc, 0x01, 0, 0}, + {0x33bd, 0x01, 0, 0}, + {0x33be, 0x01, 0, 0}, + {0x33bf, 0x01, 0, 0}, + {0x33c0, 0x00, 0, 0}, + {0x33c1, 0x00, 0, 0}, + {0x33c2, 0x00, 0, 0}, + {0x33c3, 0x00, 0, 0}, + {0x33e0, 0x14, 0, 0}, + {0x33e1, 0x0f, 0, 0}, + {0x33e2, 0x04, 0, 0}, + {0x33e3, 0x02, 0, 0}, + {0x33e4, 0x01, 0, 0}, + {0x33e5, 0x01, 0, 0}, + {0x33e6, 0x00, 0, 0}, + {0x33e7, 0x04, 0, 0}, + {0x33e8, 0x0c, 0, 0}, + {0x33e9, 0x02, 0, 0}, + {0x33ea, 0x02, 0, 0}, + {0x33eb, 0x02, 0, 0}, + {0x33ec, 0x03, 0, 0}, + {0x33ed, 0x02, 0, 0}, + {0x33ee, 0x05, 0, 0}, + {0x33ef, 0x0a, 0, 0}, + {0x33f0, 0x08, 0, 0}, + {0x33f1, 0x04, 0, 0}, + {0x33f2, 0x04, 0, 0}, + {0x33f3, 0x00, 0, 0}, + {0x33f4, 0x03, 0, 0}, + {0x33f5, 0x14, 0, 0}, + {0x33f6, 0x0f, 0, 0}, + {0x33f7, 0x02, 0, 0}, + {0x33f8, 0x01, 0, 0}, + {0x33f9, 0x01, 0, 0}, + {0x33fa, 0x01, 0, 0}, + {0x33fb, 0x00, 0, 0}, + {0x33fc, 0x04, 0, 0}, + {0x33fd, 0x0c, 0, 0}, + {0x33fe, 0x02, 0, 0}, + {0x33ff, 0x02, 0, 0}, + {0x3400, 0x02, 0, 0}, + {0x3401, 0x03, 0, 0}, + {0x3402, 0x01, 0, 0}, + {0x3403, 0x02, 0, 0}, + {0x3404, 0x08, 0, 0}, + {0x3405, 0x08, 0, 0}, + {0x3406, 0x04, 0, 0}, + {0x3407, 0x04, 0, 0}, + {0x3408, 0x00, 0, 0}, + {0x3409, 0x03, 0, 0}, + {0x340a, 0x14, 0, 0}, + {0x340b, 0x0f, 0, 0}, + {0x340c, 0x04, 0, 0}, + {0x340d, 0x02, 0, 0}, + {0x340e, 0x01, 0, 0}, + {0x340f, 0x01, 0, 0}, + {0x3410, 0x00, 0, 0}, + {0x3411, 0x04, 0, 0}, + {0x3412, 0x0c, 0, 0}, + {0x3413, 0x02, 0, 0}, + {0x3414, 0x02, 0, 0}, + {0x3415, 0x02, 0, 0}, + {0x3416, 0x03, 0, 0}, + {0x3417, 0x02, 0, 0}, + {0x3418, 0x05, 0, 0}, + {0x3419, 0x0a, 0, 0}, + {0x341a, 0x08, 0, 0}, + {0x341b, 0x04, 0, 0}, + {0x341c, 0x04, 0, 0}, + {0x341d, 0x00, 0, 0}, + {0x341e, 0x03, 0, 0}, + {0x3440, 0x00, 0, 0}, + {0x3441, 0x00, 0, 0}, + {0x3442, 0x00, 0, 0}, + {0x3443, 0x00, 0, 0}, + {0x3444, 0x02, 0, 0}, + {0x3445, 0xf0, 0, 0}, + {0x3446, 0x02, 0, 0}, + {0x3447, 0x08, 0, 0}, + {0x3448, 0x00, 0, 0}, + {0x3460, 0x40, 0, 0}, + {0x3461, 0x40, 0, 0}, + {0x3462, 0x40, 0, 0}, + {0x3463, 0x40, 0, 0}, + {0x3464, 0x03, 0, 0}, + {0x3465, 0x01, 0, 0}, + {0x3466, 0x01, 0, 0}, + {0x3467, 0x02, 0, 0}, + {0x3468, 0x30, 0, 0}, + {0x3469, 0x00, 0, 0}, + {0x346a, 0x35, 0, 0}, + {0x346b, 0x00, 0, 0}, + {0x3480, 0x40, 0, 0}, + {0x3481, 0x00, 0, 0}, + {0x3482, 0x00, 0, 0}, + {0x3483, 0x00, 0, 0}, + {0x3484, 0x0d, 0, 0}, + {0x3485, 0x00, 0, 0}, + {0x3486, 0x00, 0, 0}, + {0x3487, 0x00, 0, 0}, + {0x3488, 0x00, 0, 0}, + {0x3489, 0x00, 0, 0}, + {0x348a, 0x00, 0, 0}, + {0x348b, 0x04, 0, 0}, + {0x348c, 0x00, 0, 0}, + {0x348d, 0x01, 0, 0}, + {0x348f, 0x01, 0, 0}, + {0x3030, 0x0a, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x7000, 0x58, 0, 0}, + {0x7001, 0x7a, 0, 0}, + {0x7002, 0x1a, 0, 0}, + {0x7003, 0xc1, 0, 0}, + {0x7004, 0x03, 0, 0}, + {0x7005, 0xda, 0, 0}, + {0x7006, 0xbd, 0, 0}, + {0x7007, 0x03, 0, 0}, + {0x7008, 0xbd, 0, 0}, + {0x7009, 0x06, 0, 0}, + {0x700a, 0xe6, 0, 0}, + {0x700b, 0xec, 0, 0}, + {0x700c, 0xbc, 0, 0}, + {0x700d, 0xff, 0, 0}, + {0x700e, 0xbc, 0, 0}, + {0x700f, 0x73, 0, 0}, + {0x7010, 0xda, 0, 0}, + {0x7011, 0x72, 0, 0}, + {0x7012, 0x76, 0, 0}, + {0x7013, 0xb6, 0, 0}, + {0x7014, 0xee, 0, 0}, + {0x7015, 0xcf, 0, 0}, + {0x7016, 0xac, 0, 0}, + {0x7017, 0xd0, 0, 0}, + {0x7018, 0xac, 0, 0}, + {0x7019, 0xd1, 0, 0}, + {0x701a, 0x50, 0, 0}, + {0x701b, 0xac, 0, 0}, + {0x701c, 0xd2, 0, 0}, + {0x701d, 0xbc, 0, 0}, + {0x701e, 0x2e, 0, 0}, + {0x701f, 0xb4, 0, 0}, + {0x7020, 0x00, 0, 0}, + {0x7021, 0xdc, 0, 0}, + {0x7022, 0xdf, 0, 0}, + {0x7023, 0xb0, 0, 0}, + {0x7024, 0x6e, 0, 0}, + {0x7025, 0xbd, 0, 0}, + {0x7026, 0x01, 0, 0}, + {0x7027, 0xd7, 0, 0}, + {0x7028, 0xed, 0, 0}, + {0x7029, 0xe1, 0, 0}, + {0x702a, 0x36, 0, 0}, + {0x702b, 0x30, 0, 0}, + {0x702c, 0xd3, 0, 0}, + {0x702d, 0x2e, 0, 0}, + {0x702e, 0x54, 0, 0}, + {0x702f, 0x46, 0, 0}, + {0x7030, 0xbc, 0, 0}, + {0x7031, 0x22, 0, 0}, + {0x7032, 0x66, 0, 0}, + {0x7033, 0xbc, 0, 0}, + {0x7034, 0x24, 0, 0}, + {0x7035, 0x2c, 0, 0}, + {0x7036, 0x28, 0, 0}, + {0x7037, 0xbc, 0, 0}, + {0x7038, 0x3c, 0, 0}, + {0x7039, 0xa1, 0, 0}, + {0x703a, 0xac, 0, 0}, + {0x703b, 0xd8, 0, 0}, + {0x703c, 0xd6, 0, 0}, + {0x703d, 0xb4, 0, 0}, + {0x703e, 0x04, 0, 0}, + {0x703f, 0x46, 0, 0}, + {0x7040, 0xb7, 0, 0}, + {0x7041, 0x04, 0, 0}, + {0x7042, 0xbe, 0, 0}, + {0x7043, 0x08, 0, 0}, + {0x7044, 0xc3, 0, 0}, + {0x7045, 0xd9, 0, 0}, + {0x7046, 0xad, 0, 0}, + {0x7047, 0xc3, 0, 0}, + {0x7048, 0xbc, 0, 0}, + {0x7049, 0x19, 0, 0}, + {0x704a, 0xc1, 0, 0}, + {0x704b, 0x27, 0, 0}, + {0x704c, 0xe7, 0, 0}, + {0x704d, 0x00, 0, 0}, + {0x704e, 0x50, 0, 0}, + {0x704f, 0x20, 0, 0}, + {0x7050, 0xb8, 0, 0}, + {0x7051, 0x02, 0, 0}, + {0x7052, 0xbc, 0, 0}, + {0x7053, 0x17, 0, 0}, + {0x7054, 0xdb, 0, 0}, + {0x7055, 0xc7, 0, 0}, + {0x7056, 0xb8, 0, 0}, + {0x7057, 0x00, 0, 0}, + {0x7058, 0x28, 0, 0}, + {0x7059, 0x54, 0, 0}, + {0x705a, 0xb4, 0, 0}, + {0x705b, 0x14, 0, 0}, + {0x705c, 0xab, 0, 0}, + {0x705d, 0xbe, 0, 0}, + {0x705e, 0x06, 0, 0}, + {0x705f, 0xd8, 0, 0}, + {0x7060, 0xd6, 0, 0}, + {0x7061, 0x00, 0, 0}, + {0x7062, 0xb4, 0, 0}, + {0x7063, 0xc7, 0, 0}, + {0x7064, 0x07, 0, 0}, + {0x7065, 0xb9, 0, 0}, + {0x7066, 0x05, 0, 0}, + {0x7067, 0xee, 0, 0}, + {0x7068, 0xe6, 0, 0}, + {0x7069, 0xad, 0, 0}, + {0x706a, 0xb4, 0, 0}, + {0x706b, 0x26, 0, 0}, + {0x706c, 0x19, 0, 0}, + {0x706d, 0xc1, 0, 0}, + {0x706e, 0x3a, 0, 0}, + {0x706f, 0xc3, 0, 0}, + {0x7070, 0xaf, 0, 0}, + {0x7071, 0x00, 0, 0}, + {0x7072, 0xc0, 0, 0}, + {0x7073, 0x3c, 0, 0}, + {0x7074, 0xc3, 0, 0}, + {0x7075, 0xbe, 0, 0}, + {0x7076, 0xe7, 0, 0}, + {0x7077, 0x00, 0, 0}, + {0x7078, 0x15, 0, 0}, + {0x7079, 0xc2, 0, 0}, + {0x707a, 0x40, 0, 0}, + {0x707b, 0xc3, 0, 0}, + {0x707c, 0xa4, 0, 0}, + {0x707d, 0xc0, 0, 0}, + {0x707e, 0x3c, 0, 0}, + {0x707f, 0x00, 0, 0}, + {0x7080, 0xb9, 0, 0}, + {0x7081, 0x64, 0, 0}, + {0x7082, 0x29, 0, 0}, + {0x7083, 0x00, 0, 0}, + {0x7084, 0xb8, 0, 0}, + {0x7085, 0x12, 0, 0}, + {0x7086, 0xbe, 0, 0}, + {0x7087, 0x01, 0, 0}, + {0x7088, 0xd0, 0, 0}, + {0x7089, 0xbc, 0, 0}, + {0x708a, 0x01, 0, 0}, + {0x708b, 0xac, 0, 0}, + {0x708c, 0x37, 0, 0}, + {0x708d, 0xd2, 0, 0}, + {0x708e, 0xac, 0, 0}, + {0x708f, 0x45, 0, 0}, + {0x7090, 0xad, 0, 0}, + {0x7091, 0x28, 0, 0}, + {0x7092, 0x00, 0, 0}, + {0x7093, 0xb8, 0, 0}, + {0x7094, 0x00, 0, 0}, + {0x7095, 0xbc, 0, 0}, + {0x7096, 0x01, 0, 0}, + {0x7097, 0x36, 0, 0}, + {0x7098, 0xd3, 0, 0}, + {0x7099, 0x30, 0, 0}, + {0x709a, 0x04, 0, 0}, + {0x709b, 0xe0, 0, 0}, + {0x709c, 0xd8, 0, 0}, + {0x709d, 0xb4, 0, 0}, + {0x709e, 0xe9, 0, 0}, + {0x709f, 0x00, 0, 0}, + {0x70a0, 0xbe, 0, 0}, + {0x70a1, 0x05, 0, 0}, + {0x70a2, 0x62, 0, 0}, + {0x70a3, 0x07, 0, 0}, + {0x70a4, 0xb9, 0, 0}, + {0x70a5, 0x05, 0, 0}, + {0x70a6, 0xad, 0, 0}, + {0x70a7, 0xc3, 0, 0}, + {0x70a8, 0xcf, 0, 0}, + {0x70a9, 0x00, 0, 0}, + {0x70aa, 0x15, 0, 0}, + {0x70ab, 0xc2, 0, 0}, + {0x70ac, 0x59, 0, 0}, + {0x70ad, 0xc3, 0, 0}, + {0x70ae, 0xc9, 0, 0}, + {0x70af, 0xc0, 0, 0}, + {0x70b0, 0x55, 0, 0}, + {0x70b1, 0x00, 0, 0}, + {0x70b2, 0x46, 0, 0}, + {0x70b3, 0xa1, 0, 0}, + {0x70b4, 0xb9, 0, 0}, + {0x70b5, 0x64, 0, 0}, + {0x70b6, 0x29, 0, 0}, + {0x70b7, 0x00, 0, 0}, + {0x70b8, 0xb8, 0, 0}, + {0x70b9, 0x02, 0, 0}, + {0x70ba, 0xbe, 0, 0}, + {0x70bb, 0x02, 0, 0}, + {0x70bc, 0xd0, 0, 0}, + {0x70bd, 0xdc, 0, 0}, + {0x70be, 0xac, 0, 0}, + {0x70bf, 0xbc, 0, 0}, + {0x70c0, 0x01, 0, 0}, + {0x70c1, 0x37, 0, 0}, + {0x70c2, 0xac, 0, 0}, + {0x70c3, 0xd2, 0, 0}, + {0x70c4, 0x45, 0, 0}, + {0x70c5, 0xad, 0, 0}, + {0x70c6, 0x28, 0, 0}, + {0x70c7, 0x00, 0, 0}, + {0x70c8, 0xb8, 0, 0}, + {0x70c9, 0x00, 0, 0}, + {0x70ca, 0xbc, 0, 0}, + {0x70cb, 0x01, 0, 0}, + {0x70cc, 0x36, 0, 0}, + {0x70cd, 0x30, 0, 0}, + {0x70ce, 0xe0, 0, 0}, + {0x70cf, 0xd8, 0, 0}, + {0x70d0, 0xb5, 0, 0}, + {0x70d1, 0x0b, 0, 0}, + {0x70d2, 0xd6, 0, 0}, + {0x70d3, 0xbe, 0, 0}, + {0x70d4, 0x07, 0, 0}, + {0x70d5, 0x00, 0, 0}, + {0x70d6, 0x62, 0, 0}, + {0x70d7, 0x07, 0, 0}, + {0x70d8, 0xb9, 0, 0}, + {0x70d9, 0x05, 0, 0}, + {0x70da, 0xad, 0, 0}, + {0x70db, 0xc3, 0, 0}, + {0x70dc, 0xcf, 0, 0}, + {0x70dd, 0x46, 0, 0}, + {0x70de, 0xcd, 0, 0}, + {0x70df, 0x07, 0, 0}, + {0x70e0, 0xcd, 0, 0}, + {0x70e1, 0x00, 0, 0}, + {0x70e2, 0xe3, 0, 0}, + {0x70e3, 0x18, 0, 0}, + {0x70e4, 0xc2, 0, 0}, + {0x70e5, 0xa2, 0, 0}, + {0x70e6, 0xb9, 0, 0}, + {0x70e7, 0x64, 0, 0}, + {0x70e8, 0xd1, 0, 0}, + {0x70e9, 0xdd, 0, 0}, + {0x70ea, 0xac, 0, 0}, + {0x70eb, 0xcf, 0, 0}, + {0x70ec, 0xdf, 0, 0}, + {0x70ed, 0xb5, 0, 0}, + {0x70ee, 0x19, 0, 0}, + {0x70ef, 0x46, 0, 0}, + {0x70f0, 0x50, 0, 0}, + {0x70f1, 0xb6, 0, 0}, + {0x70f2, 0xee, 0, 0}, + {0x70f3, 0xe8, 0, 0}, + {0x70f4, 0xe6, 0, 0}, + {0x70f5, 0xbc, 0, 0}, + {0x70f6, 0x31, 0, 0}, + {0x70f7, 0xe1, 0, 0}, + {0x70f8, 0x36, 0, 0}, + {0x70f9, 0x30, 0, 0}, + {0x70fa, 0xd3, 0, 0}, + {0x70fb, 0x2e, 0, 0}, + {0x70fc, 0x54, 0, 0}, + {0x70fd, 0xbd, 0, 0}, + {0x70fe, 0x03, 0, 0}, + {0x70ff, 0xec, 0, 0}, + {0x7100, 0x2c, 0, 0}, + {0x7101, 0x50, 0, 0}, + {0x7102, 0x20, 0, 0}, + {0x7103, 0x04, 0, 0}, + {0x7104, 0xb8, 0, 0}, + {0x7105, 0x02, 0, 0}, + {0x7106, 0xbc, 0, 0}, + {0x7107, 0x18, 0, 0}, + {0x7108, 0xc7, 0, 0}, + {0x7109, 0xb8, 0, 0}, + {0x710a, 0x00, 0, 0}, + {0x710b, 0x28, 0, 0}, + {0x710c, 0x54, 0, 0}, + {0x710d, 0xbc, 0, 0}, + {0x710e, 0x02, 0, 0}, + {0x710f, 0xb4, 0, 0}, + {0x7110, 0xda, 0, 0}, + {0x7111, 0xbe, 0, 0}, + {0x7112, 0x04, 0, 0}, + {0x7113, 0xd6, 0, 0}, + {0x7114, 0xd8, 0, 0}, + {0x7115, 0xab, 0, 0}, + {0x7116, 0x00, 0, 0}, + {0x7117, 0x62, 0, 0}, + {0x7118, 0x07, 0, 0}, + {0x7119, 0xb9, 0, 0}, + {0x711a, 0x05, 0, 0}, + {0x711b, 0xad, 0, 0}, + {0x711c, 0xc3, 0, 0}, + {0x711d, 0xbc, 0, 0}, + {0x711e, 0xe7, 0, 0}, + {0x711f, 0xb9, 0, 0}, + {0x7120, 0x64, 0, 0}, + {0x7121, 0x29, 0, 0}, + {0x7122, 0x00, 0, 0}, + {0x7123, 0xb8, 0, 0}, + {0x7124, 0x02, 0, 0}, + {0x7125, 0xbe, 0, 0}, + {0x7126, 0x00, 0, 0}, + {0x7127, 0x45, 0, 0}, + {0x7128, 0xad, 0, 0}, + {0x7129, 0xe2, 0, 0}, + {0x712a, 0x28, 0, 0}, + {0x712b, 0x00, 0, 0}, + {0x712c, 0xb8, 0, 0}, + {0x712d, 0x00, 0, 0}, + {0x712e, 0xe0, 0, 0}, + {0x712f, 0xd8, 0, 0}, + {0x7130, 0xb4, 0, 0}, + {0x7131, 0xe9, 0, 0}, + {0x7132, 0xbe, 0, 0}, + {0x7133, 0x03, 0, 0}, + {0x7134, 0x00, 0, 0}, + {0x7135, 0x30, 0, 0}, + {0x7136, 0x62, 0, 0}, + {0x7137, 0x07, 0, 0}, + {0x7138, 0xb9, 0, 0}, + {0x7139, 0x05, 0, 0}, + {0x713a, 0xad, 0, 0}, + {0x713b, 0xc3, 0, 0}, + {0x713c, 0xcf, 0, 0}, + {0x713d, 0x42, 0, 0}, + {0x713e, 0xe4, 0, 0}, + {0x713f, 0xcd, 0, 0}, + {0x7140, 0x07, 0, 0}, + {0x7141, 0xcd, 0, 0}, + {0x7142, 0x00, 0, 0}, + {0x7143, 0x00, 0, 0}, + {0x7144, 0x17, 0, 0}, + {0x7145, 0xc2, 0, 0}, + {0x7146, 0xbb, 0, 0}, + {0x7147, 0xde, 0, 0}, + {0x7148, 0xcf, 0, 0}, + {0x7149, 0xdf, 0, 0}, + {0x714a, 0xac, 0, 0}, + {0x714b, 0xd1, 0, 0}, + {0x714c, 0x44, 0, 0}, + {0x714d, 0xac, 0, 0}, + {0x714e, 0xb9, 0, 0}, + {0x714f, 0x76, 0, 0}, + {0x7150, 0xb8, 0, 0}, + {0x7151, 0x08, 0, 0}, + {0x7152, 0xb6, 0, 0}, + {0x7153, 0xfe, 0, 0}, + {0x7154, 0xb4, 0, 0}, + {0x7155, 0xca, 0, 0}, + {0x7156, 0xd6, 0, 0}, + {0x7157, 0xd8, 0, 0}, + {0x7158, 0xab, 0, 0}, + {0x7159, 0x00, 0, 0}, + {0x715a, 0xe1, 0, 0}, + {0x715b, 0x36, 0, 0}, + {0x715c, 0x30, 0, 0}, + {0x715d, 0xd3, 0, 0}, + {0x715e, 0xbc, 0, 0}, + {0x715f, 0x29, 0, 0}, + {0x7160, 0xb4, 0, 0}, + {0x7161, 0x1f, 0, 0}, + {0x7162, 0xaa, 0, 0}, + {0x7163, 0xbd, 0, 0}, + {0x7164, 0x01, 0, 0}, + {0x7165, 0xb8, 0, 0}, + {0x7166, 0x0c, 0, 0}, + {0x7167, 0x45, 0, 0}, + {0x7168, 0xa4, 0, 0}, + {0x7169, 0xbd, 0, 0}, + {0x716a, 0x03, 0, 0}, + {0x716b, 0xec, 0, 0}, + {0x716c, 0xbc, 0, 0}, + {0x716d, 0x3d, 0, 0}, + {0x716e, 0xc3, 0, 0}, + {0x716f, 0xcf, 0, 0}, + {0x7170, 0x42, 0, 0}, + {0x7171, 0xb8, 0, 0}, + {0x7172, 0x00, 0, 0}, + {0x7173, 0xe4, 0, 0}, + {0x7174, 0xd5, 0, 0}, + {0x7175, 0x00, 0, 0}, + {0x7176, 0xb6, 0, 0}, + {0x7177, 0x00, 0, 0}, + {0x7178, 0x74, 0, 0}, + {0x7179, 0xbd, 0, 0}, + {0x717a, 0x03, 0, 0}, + {0x717b, 0xb5, 0, 0}, + {0x717c, 0x39, 0, 0}, + {0x717d, 0x40, 0, 0}, + {0x717e, 0x58, 0, 0}, + {0x717f, 0xdd, 0, 0}, + {0x7180, 0x19, 0, 0}, + {0x7181, 0xc1, 0, 0}, + {0x7182, 0xc8, 0, 0}, + {0x7183, 0xbd, 0, 0}, + {0x7184, 0x06, 0, 0}, + {0x7185, 0x17, 0, 0}, + {0x7186, 0xc1, 0, 0}, + {0x7187, 0xc6, 0, 0}, + {0x7188, 0xe8, 0, 0}, + {0x7189, 0x00, 0, 0}, + {0x718a, 0xc0, 0, 0}, + {0x718b, 0xc8, 0, 0}, + {0x718c, 0xe6, 0, 0}, + {0x718d, 0x95, 0, 0}, + {0x718e, 0x15, 0, 0}, + {0x718f, 0x00, 0, 0}, + {0x7190, 0xbc, 0, 0}, + {0x7191, 0x19, 0, 0}, + {0x7192, 0xb9, 0, 0}, + {0x7193, 0xf6, 0, 0}, + {0x7194, 0x14, 0, 0}, + {0x7195, 0xc1, 0, 0}, + {0x7196, 0xd0, 0, 0}, + {0x7197, 0xd1, 0, 0}, + {0x7198, 0xac, 0, 0}, + {0x7199, 0x37, 0, 0}, + {0x719a, 0xbc, 0, 0}, + {0x719b, 0x35, 0, 0}, + {0x719c, 0x36, 0, 0}, + {0x719d, 0x30, 0, 0}, + {0x719e, 0xe1, 0, 0}, + {0x719f, 0xd3, 0, 0}, + {0x71a0, 0x7a, 0, 0}, + {0x71a1, 0xb6, 0, 0}, + {0x71a2, 0x0c, 0, 0}, + {0x71a3, 0xff, 0, 0}, + {0x71a4, 0xb4, 0, 0}, + {0x71a5, 0xc7, 0, 0}, + {0x71a6, 0xd9, 0, 0}, + {0x71a7, 0x00, 0, 0}, + {0x71a8, 0xbd, 0, 0}, + {0x71a9, 0x01, 0, 0}, + {0x71aa, 0x56, 0, 0}, + {0x71ab, 0xc0, 0, 0}, + {0x71ac, 0xda, 0, 0}, + {0x71ad, 0xb4, 0, 0}, + {0x71ae, 0x1f, 0, 0}, + {0x71af, 0x56, 0, 0}, + {0x71b0, 0xaa, 0, 0}, + {0x71b1, 0xbc, 0, 0}, + {0x71b2, 0x08, 0, 0}, + {0x71b3, 0x00, 0, 0}, + {0x71b4, 0x57, 0, 0}, + {0x71b5, 0xe8, 0, 0}, + {0x71b6, 0xb5, 0, 0}, + {0x71b7, 0x36, 0, 0}, + {0x71b8, 0x00, 0, 0}, + {0x71b9, 0x54, 0, 0}, + {0x71ba, 0xe7, 0, 0}, + {0x71bb, 0xc8, 0, 0}, + {0x71bc, 0xb4, 0, 0}, + {0x71bd, 0x1f, 0, 0}, + {0x71be, 0x56, 0, 0}, + {0x71bf, 0xaa, 0, 0}, + {0x71c0, 0xbc, 0, 0}, + {0x71c1, 0x08, 0, 0}, + {0x71c2, 0x57, 0, 0}, + {0x71c3, 0x00, 0, 0}, + {0x71c4, 0xb5, 0, 0}, + {0x71c5, 0x36, 0, 0}, + {0x71c6, 0x00, 0, 0}, + {0x71c7, 0x54, 0, 0}, + {0x71c8, 0xc8, 0, 0}, + {0x71c9, 0xb5, 0, 0}, + {0x71ca, 0x18, 0, 0}, + {0x71cb, 0xd9, 0, 0}, + {0x71cc, 0x00, 0, 0}, + {0x71cd, 0xbd, 0, 0}, + {0x71ce, 0x01, 0, 0}, + {0x71cf, 0x56, 0, 0}, + {0x71d0, 0x08, 0, 0}, + {0x71d1, 0x57, 0, 0}, + {0x71d2, 0xe8, 0, 0}, + {0x71d3, 0xb4, 0, 0}, + {0x71d4, 0x42, 0, 0}, + {0x71d5, 0x00, 0, 0}, + {0x71d6, 0x54, 0, 0}, + {0x71d7, 0xe7, 0, 0}, + {0x71d8, 0xc8, 0, 0}, + {0x71d9, 0xab, 0, 0}, + {0x71da, 0x00, 0, 0}, + {0x71db, 0x66, 0, 0}, + {0x71dc, 0x62, 0, 0}, + {0x71dd, 0x06, 0, 0}, + {0x71de, 0x74, 0, 0}, + {0x71df, 0xb9, 0, 0}, + {0x71e0, 0x05, 0, 0}, + {0x71e1, 0xb7, 0, 0}, + {0x71e2, 0x14, 0, 0}, + {0x71e3, 0x0e, 0, 0}, + {0x71e4, 0xb7, 0, 0}, + {0x71e5, 0x04, 0, 0}, + {0x71e6, 0xc8, 0, 0}, + {0x7600, 0x04, 0, 0}, + {0x7601, 0x80, 0, 0}, + {0x7602, 0x07, 0, 0}, + {0x7603, 0x44, 0, 0}, + {0x7604, 0x05, 0, 0}, + {0x7605, 0x33, 0, 0}, + {0x7606, 0x0f, 0, 0}, + {0x7607, 0x00, 0, 0}, + {0x7608, 0x07, 0, 0}, + {0x7609, 0x40, 0, 0}, + {0x760a, 0x04, 0, 0}, + {0x760b, 0xe5, 0, 0}, + {0x760c, 0x06, 0, 0}, + {0x760d, 0x50, 0, 0}, + {0x760e, 0x04, 0, 0}, + {0x760f, 0xe4, 0, 0}, + {0x7610, 0x00, 0, 0}, + {0x7611, 0x00, 0, 0}, + {0x7612, 0x06, 0, 0}, + {0x7613, 0x5c, 0, 0}, + {0x7614, 0x00, 0, 0}, + {0x7615, 0x0f, 0, 0}, + {0x7616, 0x06, 0, 0}, + {0x7617, 0x1c, 0, 0}, + {0x7618, 0x00, 0, 0}, + {0x7619, 0x02, 0, 0}, + {0x761a, 0x06, 0, 0}, + {0x761b, 0xa2, 0, 0}, + {0x761c, 0x00, 0, 0}, + {0x761d, 0x01, 0, 0}, + {0x761e, 0x06, 0, 0}, + {0x761f, 0xae, 0, 0}, + {0x7620, 0x00, 0, 0}, + {0x7621, 0x0e, 0, 0}, + {0x7622, 0x05, 0, 0}, + {0x7623, 0x30, 0, 0}, + {0x7624, 0x07, 0, 0}, + {0x7625, 0x00, 0, 0}, + {0x7626, 0x0f, 0, 0}, + {0x7627, 0x00, 0, 0}, + {0x7628, 0x04, 0, 0}, + {0x7629, 0xe5, 0, 0}, + {0x762a, 0x05, 0, 0}, + {0x762b, 0x33, 0, 0}, + {0x762c, 0x06, 0, 0}, + {0x762d, 0x12, 0, 0}, + {0x762e, 0x00, 0, 0}, + {0x762f, 0x01, 0, 0}, + {0x7630, 0x06, 0, 0}, + {0x7631, 0x52, 0, 0}, + {0x7632, 0x00, 0, 0}, + {0x7633, 0x01, 0, 0}, + {0x7634, 0x06, 0, 0}, + {0x7635, 0x5e, 0, 0}, + {0x7636, 0x04, 0, 0}, + {0x7637, 0xe4, 0, 0}, + {0x7638, 0x00, 0, 0}, + {0x7639, 0x01, 0, 0}, + {0x763a, 0x05, 0, 0}, + {0x763b, 0x30, 0, 0}, + {0x763c, 0x0f, 0, 0}, + {0x763d, 0x00, 0, 0}, + {0x763e, 0x06, 0, 0}, + {0x763f, 0xa6, 0, 0}, + {0x7640, 0x00, 0, 0}, + {0x7641, 0x02, 0, 0}, + {0x7642, 0x06, 0, 0}, + {0x7643, 0x26, 0, 0}, + {0x7644, 0x00, 0, 0}, + {0x7645, 0x02, 0, 0}, + {0x7646, 0x05, 0, 0}, + {0x7647, 0x33, 0, 0}, + {0x7648, 0x06, 0, 0}, + {0x7649, 0x20, 0, 0}, + {0x764a, 0x0f, 0, 0}, + {0x764b, 0x00, 0, 0}, + {0x764c, 0x06, 0, 0}, + {0x764d, 0x56, 0, 0}, + {0x764e, 0x00, 0, 0}, + {0x764f, 0x02, 0, 0}, + {0x7650, 0x06, 0, 0}, + {0x7651, 0x16, 0, 0}, + {0x7652, 0x05, 0, 0}, + {0x7653, 0x33, 0, 0}, + {0x7654, 0x06, 0, 0}, + {0x7655, 0x10, 0, 0}, + {0x7656, 0x0f, 0, 0}, + {0x7657, 0x00, 0, 0}, + {0x7658, 0x06, 0, 0}, + {0x7659, 0x10, 0, 0}, + {0x765a, 0x0f, 0, 0}, + {0x765b, 0x00, 0, 0}, + {0x765c, 0x06, 0, 0}, + {0x765d, 0x20, 0, 0}, + {0x765e, 0x0f, 0, 0}, + {0x765f, 0x00, 0, 0}, + {0x7660, 0x00, 0, 0}, + {0x7661, 0x00, 0, 0}, + {0x7662, 0x00, 0, 0}, + {0x7663, 0x02, 0, 0}, + {0x7664, 0x04, 0, 0}, + {0x7665, 0xe5, 0, 0}, + {0x7666, 0x04, 0, 0}, + {0x7667, 0xe4, 0, 0}, + {0x7668, 0x0f, 0, 0}, + {0x7669, 0x00, 0, 0}, + {0x766a, 0x00, 0, 0}, + {0x766b, 0x00, 0, 0}, + {0x766c, 0x00, 0, 0}, + {0x766d, 0x01, 0, 0}, + {0x766e, 0x04, 0, 0}, + {0x766f, 0xe5, 0, 0}, + {0x7670, 0x04, 0, 0}, + {0x7671, 0xe4, 0, 0}, + {0x7672, 0x0f, 0, 0}, + {0x7673, 0x00, 0, 0}, + {0x7674, 0x00, 0, 0}, + {0x7675, 0x02, 0, 0}, + {0x7676, 0x04, 0, 0}, + {0x7677, 0xe4, 0, 0}, + {0x7678, 0x00, 0, 0}, + {0x7679, 0x02, 0, 0}, + {0x767a, 0x04, 0, 0}, + {0x767b, 0xc4, 0, 0}, + {0x767c, 0x00, 0, 0}, + {0x767d, 0x02, 0, 0}, + {0x767e, 0x04, 0, 0}, + {0x767f, 0xc4, 0, 0}, + {0x7680, 0x05, 0, 0}, + {0x7681, 0x83, 0, 0}, + {0x7682, 0x0f, 0, 0}, + {0x7683, 0x00, 0, 0}, + {0x7684, 0x00, 0, 0}, + {0x7685, 0x02, 0, 0}, + {0x7686, 0x04, 0, 0}, + {0x7687, 0xe4, 0, 0}, + {0x7688, 0x00, 0, 0}, + {0x7689, 0x02, 0, 0}, + {0x768a, 0x04, 0, 0}, + {0x768b, 0xc4, 0, 0}, + {0x768c, 0x00, 0, 0}, + {0x768d, 0x02, 0, 0}, + {0x768e, 0x04, 0, 0}, + {0x768f, 0xc4, 0, 0}, + {0x7690, 0x05, 0, 0}, + {0x7691, 0x83, 0, 0}, + {0x7692, 0x03, 0, 0}, + {0x7693, 0x0b, 0, 0}, + {0x7694, 0x05, 0, 0}, + {0x7695, 0x83, 0, 0}, + {0x7696, 0x00, 0, 0}, + {0x7697, 0x07, 0, 0}, + {0x7698, 0x05, 0, 0}, + {0x7699, 0x03, 0, 0}, + {0x769a, 0x00, 0, 0}, + {0x769b, 0x05, 0, 0}, + {0x769c, 0x05, 0, 0}, + {0x769d, 0x32, 0, 0}, + {0x769e, 0x05, 0, 0}, + {0x769f, 0x30, 0, 0}, + {0x76a0, 0x00, 0, 0}, + {0x76a1, 0x02, 0, 0}, + {0x76a2, 0x05, 0, 0}, + {0x76a3, 0x78, 0, 0}, + {0x76a4, 0x00, 0, 0}, + {0x76a5, 0x01, 0, 0}, + {0x76a6, 0x05, 0, 0}, + {0x76a7, 0x7c, 0, 0}, + {0x76a8, 0x03, 0, 0}, + {0x76a9, 0x9a, 0, 0}, + {0x76aa, 0x05, 0, 0}, + {0x76ab, 0x83, 0, 0}, + {0x76ac, 0x00, 0, 0}, + {0x76ad, 0x04, 0, 0}, + {0x76ae, 0x05, 0, 0}, + {0x76af, 0x03, 0, 0}, + {0x76b0, 0x00, 0, 0}, + {0x76b1, 0x03, 0, 0}, + {0x76b2, 0x05, 0, 0}, + {0x76b3, 0x32, 0, 0}, + {0x76b4, 0x05, 0, 0}, + {0x76b5, 0x30, 0, 0}, + {0x76b6, 0x00, 0, 0}, + {0x76b7, 0x02, 0, 0}, + {0x76b8, 0x05, 0, 0}, + {0x76b9, 0x78, 0, 0}, + {0x76ba, 0x00, 0, 0}, + {0x76bb, 0x01, 0, 0}, + {0x76bc, 0x05, 0, 0}, + {0x76bd, 0x7c, 0, 0}, + {0x76be, 0x03, 0, 0}, + {0x76bf, 0x99, 0, 0}, + {0x76c0, 0x05, 0, 0}, + {0x76c1, 0x83, 0, 0}, + {0x76c2, 0x00, 0, 0}, + {0x76c3, 0x03, 0, 0}, + {0x76c4, 0x05, 0, 0}, + {0x76c5, 0x03, 0, 0}, + {0x76c6, 0x00, 0, 0}, + {0x76c7, 0x01, 0, 0}, + {0x76c8, 0x05, 0, 0}, + {0x76c9, 0x32, 0, 0}, + {0x76ca, 0x05, 0, 0}, + {0x76cb, 0x30, 0, 0}, + {0x76cc, 0x00, 0, 0}, + {0x76cd, 0x02, 0, 0}, + {0x76ce, 0x05, 0, 0}, + {0x76cf, 0x78, 0, 0}, + {0x76d0, 0x00, 0, 0}, + {0x76d1, 0x01, 0, 0}, + {0x76d2, 0x05, 0, 0}, + {0x76d3, 0x7c, 0, 0}, + {0x76d4, 0x03, 0, 0}, + {0x76d5, 0x98, 0, 0}, + {0x76d6, 0x05, 0, 0}, + {0x76d7, 0x83, 0, 0}, + {0x76d8, 0x00, 0, 0}, + {0x76d9, 0x00, 0, 0}, + {0x76da, 0x05, 0, 0}, + {0x76db, 0x03, 0, 0}, + {0x76dc, 0x00, 0, 0}, + {0x76dd, 0x01, 0, 0}, + {0x76de, 0x05, 0, 0}, + {0x76df, 0x32, 0, 0}, + {0x76e0, 0x05, 0, 0}, + {0x76e1, 0x30, 0, 0}, + {0x76e2, 0x00, 0, 0}, + {0x76e3, 0x02, 0, 0}, + {0x76e4, 0x05, 0, 0}, + {0x76e5, 0x78, 0, 0}, + {0x76e6, 0x00, 0, 0}, + {0x76e7, 0x01, 0, 0}, + {0x76e8, 0x05, 0, 0}, + {0x76e9, 0x7c, 0, 0}, + {0x76ea, 0x03, 0, 0}, + {0x76eb, 0x97, 0, 0}, + {0x76ec, 0x05, 0, 0}, + {0x76ed, 0x83, 0, 0}, + {0x76ee, 0x00, 0, 0}, + {0x76ef, 0x00, 0, 0}, + {0x76f0, 0x05, 0, 0}, + {0x76f1, 0x03, 0, 0}, + {0x76f2, 0x05, 0, 0}, + {0x76f3, 0x32, 0, 0}, + {0x76f4, 0x05, 0, 0}, + {0x76f5, 0x30, 0, 0}, + {0x76f6, 0x00, 0, 0}, + {0x76f7, 0x02, 0, 0}, + {0x76f8, 0x05, 0, 0}, + {0x76f9, 0x78, 0, 0}, + {0x76fa, 0x00, 0, 0}, + {0x76fb, 0x01, 0, 0}, + {0x76fc, 0x05, 0, 0}, + {0x76fd, 0x7c, 0, 0}, + {0x76fe, 0x03, 0, 0}, + {0x76ff, 0x96, 0, 0}, + {0x7700, 0x05, 0, 0}, + {0x7701, 0x83, 0, 0}, + {0x7702, 0x05, 0, 0}, + {0x7703, 0x03, 0, 0}, + {0x7704, 0x05, 0, 0}, + {0x7705, 0x32, 0, 0}, + {0x7706, 0x05, 0, 0}, + {0x7707, 0x30, 0, 0}, + {0x7708, 0x00, 0, 0}, + {0x7709, 0x02, 0, 0}, + {0x770a, 0x05, 0, 0}, + {0x770b, 0x78, 0, 0}, + {0x770c, 0x00, 0, 0}, + {0x770d, 0x01, 0, 0}, + {0x770e, 0x05, 0, 0}, + {0x770f, 0x7c, 0, 0}, + {0x7710, 0x03, 0, 0}, + {0x7711, 0x95, 0, 0}, + {0x7712, 0x05, 0, 0}, + {0x7713, 0x83, 0, 0}, + {0x7714, 0x05, 0, 0}, + {0x7715, 0x03, 0, 0}, + {0x7716, 0x05, 0, 0}, + {0x7717, 0x32, 0, 0}, + {0x7718, 0x05, 0, 0}, + {0x7719, 0x30, 0, 0}, + {0x771a, 0x00, 0, 0}, + {0x771b, 0x02, 0, 0}, + {0x771c, 0x05, 0, 0}, + {0x771d, 0x78, 0, 0}, + {0x771e, 0x00, 0, 0}, + {0x771f, 0x01, 0, 0}, + {0x7720, 0x05, 0, 0}, + {0x7721, 0x7c, 0, 0}, + {0x7722, 0x03, 0, 0}, + {0x7723, 0x94, 0, 0}, + {0x7724, 0x05, 0, 0}, + {0x7725, 0x83, 0, 0}, + {0x7726, 0x00, 0, 0}, + {0x7727, 0x01, 0, 0}, + {0x7728, 0x05, 0, 0}, + {0x7729, 0x03, 0, 0}, + {0x772a, 0x00, 0, 0}, + {0x772b, 0x01, 0, 0}, + {0x772c, 0x05, 0, 0}, + {0x772d, 0x32, 0, 0}, + {0x772e, 0x05, 0, 0}, + {0x772f, 0x30, 0, 0}, + {0x7730, 0x00, 0, 0}, + {0x7731, 0x02, 0, 0}, + {0x7732, 0x05, 0, 0}, + {0x7733, 0x78, 0, 0}, + {0x7734, 0x00, 0, 0}, + {0x7735, 0x01, 0, 0}, + {0x7736, 0x05, 0, 0}, + {0x7737, 0x7c, 0, 0}, + {0x7738, 0x03, 0, 0}, + {0x7739, 0x93, 0, 0}, + {0x773a, 0x05, 0, 0}, + {0x773b, 0x83, 0, 0}, + {0x773c, 0x00, 0, 0}, + {0x773d, 0x00, 0, 0}, + {0x773e, 0x05, 0, 0}, + {0x773f, 0x03, 0, 0}, + {0x7740, 0x00, 0, 0}, + {0x7741, 0x00, 0, 0}, + {0x7742, 0x05, 0, 0}, + {0x7743, 0x32, 0, 0}, + {0x7744, 0x05, 0, 0}, + {0x7745, 0x30, 0, 0}, + {0x7746, 0x00, 0, 0}, + {0x7747, 0x02, 0, 0}, + {0x7748, 0x05, 0, 0}, + {0x7749, 0x78, 0, 0}, + {0x774a, 0x00, 0, 0}, + {0x774b, 0x01, 0, 0}, + {0x774c, 0x05, 0, 0}, + {0x774d, 0x7c, 0, 0}, + {0x774e, 0x03, 0, 0}, + {0x774f, 0x92, 0, 0}, + {0x7750, 0x05, 0, 0}, + {0x7751, 0x83, 0, 0}, + {0x7752, 0x05, 0, 0}, + {0x7753, 0x03, 0, 0}, + {0x7754, 0x00, 0, 0}, + {0x7755, 0x00, 0, 0}, + {0x7756, 0x05, 0, 0}, + {0x7757, 0x32, 0, 0}, + {0x7758, 0x05, 0, 0}, + {0x7759, 0x30, 0, 0}, + {0x775a, 0x00, 0, 0}, + {0x775b, 0x02, 0, 0}, + {0x775c, 0x05, 0, 0}, + {0x775d, 0x78, 0, 0}, + {0x775e, 0x00, 0, 0}, + {0x775f, 0x01, 0, 0}, + {0x7760, 0x05, 0, 0}, + {0x7761, 0x7c, 0, 0}, + {0x7762, 0x03, 0, 0}, + {0x7763, 0x91, 0, 0}, + {0x7764, 0x05, 0, 0}, + {0x7765, 0x83, 0, 0}, + {0x7766, 0x05, 0, 0}, + {0x7767, 0x03, 0, 0}, + {0x7768, 0x05, 0, 0}, + {0x7769, 0x32, 0, 0}, + {0x776a, 0x05, 0, 0}, + {0x776b, 0x30, 0, 0}, + {0x776c, 0x00, 0, 0}, + {0x776d, 0x02, 0, 0}, + {0x776e, 0x05, 0, 0}, + {0x776f, 0x78, 0, 0}, + {0x7770, 0x00, 0, 0}, + {0x7771, 0x01, 0, 0}, + {0x7772, 0x05, 0, 0}, + {0x7773, 0x7c, 0, 0}, + {0x7774, 0x03, 0, 0}, + {0x7775, 0x90, 0, 0}, + {0x7776, 0x05, 0, 0}, + {0x7777, 0x83, 0, 0}, + {0x7778, 0x05, 0, 0}, + {0x7779, 0x03, 0, 0}, + {0x777a, 0x05, 0, 0}, + {0x777b, 0x32, 0, 0}, + {0x777c, 0x05, 0, 0}, + {0x777d, 0x30, 0, 0}, + {0x777e, 0x00, 0, 0}, + {0x777f, 0x02, 0, 0}, + {0x7780, 0x05, 0, 0}, + {0x7781, 0x78, 0, 0}, + {0x7782, 0x00, 0, 0}, + {0x7783, 0x01, 0, 0}, + {0x7784, 0x05, 0, 0}, + {0x7785, 0x7c, 0, 0}, + {0x7786, 0x02, 0, 0}, + {0x7787, 0x90, 0, 0}, + {0x7788, 0x05, 0, 0}, + {0x7789, 0x03, 0, 0}, + {0x778a, 0x07, 0, 0}, + {0x778b, 0x00, 0, 0}, + {0x778c, 0x0f, 0, 0}, + {0x778d, 0x00, 0, 0}, + {0x778e, 0x08, 0, 0}, + {0x778f, 0x30, 0, 0}, + {0x7790, 0x08, 0, 0}, + {0x7791, 0xee, 0, 0}, + {0x7792, 0x0f, 0, 0}, + {0x7793, 0x00, 0, 0}, + {0x7794, 0x05, 0, 0}, + {0x7795, 0x33, 0, 0}, + {0x7796, 0x04, 0, 0}, + {0x7797, 0xe5, 0, 0}, + {0x7798, 0x06, 0, 0}, + {0x7799, 0x52, 0, 0}, + {0x779a, 0x04, 0, 0}, + {0x779b, 0xe4, 0, 0}, + {0x779c, 0x00, 0, 0}, + {0x779d, 0x00, 0, 0}, + {0x779e, 0x06, 0, 0}, + {0x779f, 0x5e, 0, 0}, + {0x77a0, 0x00, 0, 0}, + {0x77a1, 0x0f, 0, 0}, + {0x77a2, 0x06, 0, 0}, + {0x77a3, 0x1e, 0, 0}, + {0x77a4, 0x00, 0, 0}, + {0x77a5, 0x02, 0, 0}, + {0x77a6, 0x06, 0, 0}, + {0x77a7, 0xa2, 0, 0}, + {0x77a8, 0x00, 0, 0}, + {0x77a9, 0x01, 0, 0}, + {0x77aa, 0x06, 0, 0}, + {0x77ab, 0xae, 0, 0}, + {0x77ac, 0x00, 0, 0}, + {0x77ad, 0x03, 0, 0}, + {0x77ae, 0x05, 0, 0}, + {0x77af, 0x30, 0, 0}, + {0x77b0, 0x09, 0, 0}, + {0x77b1, 0x19, 0, 0}, + {0x77b2, 0x0f, 0, 0}, + {0x77b3, 0x00, 0, 0}, + {0x77b4, 0x05, 0, 0}, + {0x77b5, 0x33, 0, 0}, + {0x77b6, 0x04, 0, 0}, + {0x77b7, 0xe5, 0, 0}, + {0x77b8, 0x06, 0, 0}, + {0x77b9, 0x52, 0, 0}, + {0x77ba, 0x04, 0, 0}, + {0x77bb, 0xe4, 0, 0}, + {0x77bc, 0x00, 0, 0}, + {0x77bd, 0x00, 0, 0}, + {0x77be, 0x06, 0, 0}, + {0x77bf, 0x5e, 0, 0}, + {0x77c0, 0x00, 0, 0}, + {0x77c1, 0x0f, 0, 0}, + {0x77c2, 0x06, 0, 0}, + {0x77c3, 0x1e, 0, 0}, + {0x77c4, 0x00, 0, 0}, + {0x77c5, 0x02, 0, 0}, + {0x77c6, 0x06, 0, 0}, + {0x77c7, 0xa2, 0, 0}, + {0x77c8, 0x00, 0, 0}, + {0x77c9, 0x01, 0, 0}, + {0x77ca, 0x06, 0, 0}, + {0x77cb, 0xae, 0, 0}, + {0x77cc, 0x00, 0, 0}, + {0x77cd, 0x03, 0, 0}, + {0x77ce, 0x05, 0, 0}, + {0x77cf, 0x30, 0, 0}, + {0x77d0, 0x0f, 0, 0}, + {0x77d1, 0x00, 0, 0}, + {0x77d2, 0x00, 0, 0}, + {0x77d3, 0x00, 0, 0}, + {0x77d4, 0x00, 0, 0}, + {0x77d5, 0x02, 0, 0}, + {0x77d6, 0x04, 0, 0}, + {0x77d7, 0xe5, 0, 0}, + {0x77d8, 0x04, 0, 0}, + {0x77d9, 0xe4, 0, 0}, + {0x77da, 0x05, 0, 0}, + {0x77db, 0x33, 0, 0}, + {0x77dc, 0x07, 0, 0}, + {0x77dd, 0x10, 0, 0}, + {0x77de, 0x00, 0, 0}, + {0x77df, 0x00, 0, 0}, + {0x77e0, 0x01, 0, 0}, + {0x77e1, 0xbb, 0, 0}, + {0x77e2, 0x00, 0, 0}, + {0x77e3, 0x00, 0, 0}, + {0x77e4, 0x01, 0, 0}, + {0x77e5, 0xaa, 0, 0}, + {0x77e6, 0x00, 0, 0}, + {0x77e7, 0x00, 0, 0}, + {0x77e8, 0x01, 0, 0}, + {0x77e9, 0x99, 0, 0}, + {0x77ea, 0x00, 0, 0}, + {0x77eb, 0x00, 0, 0}, + {0x77ec, 0x01, 0, 0}, + {0x77ed, 0x88, 0, 0}, + {0x77ee, 0x00, 0, 0}, + {0x77ef, 0x00, 0, 0}, + {0x77f0, 0x01, 0, 0}, + {0x77f1, 0x77, 0, 0}, + {0x77f2, 0x00, 0, 0}, + {0x77f3, 0x00, 0, 0}, + {0x77f4, 0x01, 0, 0}, + {0x77f5, 0x66, 0, 0}, + {0x77f6, 0x00, 0, 0}, + {0x77f7, 0x00, 0, 0}, + {0x77f8, 0x01, 0, 0}, + {0x77f9, 0x55, 0, 0}, + {0x77fa, 0x00, 0, 0}, + {0x77fb, 0x00, 0, 0}, + {0x77fc, 0x01, 0, 0}, + {0x77fd, 0x44, 0, 0}, + {0x77fe, 0x00, 0, 0}, + {0x77ff, 0x00, 0, 0}, + {0x7800, 0x01, 0, 0}, + {0x7801, 0x33, 0, 0}, + {0x7802, 0x00, 0, 0}, + {0x7803, 0x00, 0, 0}, + {0x7804, 0x01, 0, 0}, + {0x7805, 0x22, 0, 0}, + {0x7806, 0x00, 0, 0}, + {0x7807, 0x00, 0, 0}, + {0x7808, 0x01, 0, 0}, + {0x7809, 0x11, 0, 0}, + {0x780a, 0x00, 0, 0}, + {0x780b, 0x00, 0, 0}, + {0x780c, 0x01, 0, 0}, + {0x780d, 0x00, 0, 0}, + {0x780e, 0x01, 0, 0}, + {0x780f, 0xff, 0, 0}, + {0x7810, 0x07, 0, 0}, + {0x7811, 0x00, 0, 0}, + {0x7812, 0x02, 0, 0}, + {0x7813, 0xa0, 0, 0}, + {0x7814, 0x0f, 0, 0}, + {0x7815, 0x00, 0, 0}, + {0x7816, 0x08, 0, 0}, + {0x7817, 0x35, 0, 0}, + {0x7818, 0x06, 0, 0}, + {0x7819, 0x52, 0, 0}, + {0x781a, 0x04, 0, 0}, + {0x781b, 0xe4, 0, 0}, + {0x781c, 0x00, 0, 0}, + {0x781d, 0x00, 0, 0}, + {0x781e, 0x06, 0, 0}, + {0x781f, 0x5e, 0, 0}, + {0x7820, 0x05, 0, 0}, + {0x7821, 0x33, 0, 0}, + {0x7822, 0x09, 0, 0}, + {0x7823, 0x19, 0, 0}, + {0x7824, 0x06, 0, 0}, + {0x7825, 0x1e, 0, 0}, + {0x7826, 0x05, 0, 0}, + {0x7827, 0x33, 0, 0}, + {0x7828, 0x00, 0, 0}, + {0x7829, 0x01, 0, 0}, + {0x782a, 0x06, 0, 0}, + {0x782b, 0x24, 0, 0}, + {0x782c, 0x06, 0, 0}, + {0x782d, 0x20, 0, 0}, + {0x782e, 0x0f, 0, 0}, + {0x782f, 0x00, 0, 0}, + {0x7830, 0x08, 0, 0}, + {0x7831, 0x35, 0, 0}, + {0x7832, 0x07, 0, 0}, + {0x7833, 0x10, 0, 0}, + {0x7834, 0x00, 0, 0}, + {0x7835, 0x00, 0, 0}, + {0x7836, 0x01, 0, 0}, + {0x7837, 0xbb, 0, 0}, + {0x7838, 0x00, 0, 0}, + {0x7839, 0x00, 0, 0}, + {0x783a, 0x01, 0, 0}, + {0x783b, 0xaa, 0, 0}, + {0x783c, 0x00, 0, 0}, + {0x783d, 0x00, 0, 0}, + {0x783e, 0x01, 0, 0}, + {0x783f, 0x99, 0, 0}, + {0x7840, 0x00, 0, 0}, + {0x7841, 0x00, 0, 0}, + {0x7842, 0x01, 0, 0}, + {0x7843, 0x88, 0, 0}, + {0x7844, 0x00, 0, 0}, + {0x7845, 0x00, 0, 0}, + {0x7846, 0x01, 0, 0}, + {0x7847, 0x77, 0, 0}, + {0x7848, 0x00, 0, 0}, + {0x7849, 0x00, 0, 0}, + {0x784a, 0x01, 0, 0}, + {0x784b, 0x66, 0, 0}, + {0x784c, 0x00, 0, 0}, + {0x784d, 0x00, 0, 0}, + {0x784e, 0x01, 0, 0}, + {0x784f, 0x55, 0, 0}, + {0x7850, 0x00, 0, 0}, + {0x7851, 0x00, 0, 0}, + {0x7852, 0x01, 0, 0}, + {0x7853, 0x44, 0, 0}, + {0x7854, 0x00, 0, 0}, + {0x7855, 0x00, 0, 0}, + {0x7856, 0x01, 0, 0}, + {0x7857, 0x33, 0, 0}, + {0x7858, 0x00, 0, 0}, + {0x7859, 0x00, 0, 0}, + {0x785a, 0x01, 0, 0}, + {0x785b, 0x22, 0, 0}, + {0x785c, 0x00, 0, 0}, + {0x785d, 0x00, 0, 0}, + {0x785e, 0x01, 0, 0}, + {0x785f, 0x11, 0, 0}, + {0x7860, 0x00, 0, 0}, + {0x7861, 0x00, 0, 0}, + {0x7862, 0x01, 0, 0}, + {0x7863, 0x00, 0, 0}, + {0x7864, 0x07, 0, 0}, + {0x7865, 0x00, 0, 0}, + {0x7866, 0x01, 0, 0}, + {0x7867, 0xff, 0, 0}, + {0x7868, 0x02, 0, 0}, + {0x7869, 0xa0, 0, 0}, + {0x786a, 0x0f, 0, 0}, + {0x786b, 0x00, 0, 0}, + {0x786c, 0x08, 0, 0}, + {0x786d, 0x3a, 0, 0}, + {0x786e, 0x08, 0, 0}, + {0x786f, 0x6a, 0, 0}, + {0x7870, 0x0f, 0, 0}, + {0x7871, 0x00, 0, 0}, + {0x7872, 0x04, 0, 0}, + {0x7873, 0xc0, 0, 0}, + {0x7874, 0x09, 0, 0}, + {0x7875, 0x19, 0, 0}, + {0x7876, 0x04, 0, 0}, + {0x7877, 0x99, 0, 0}, + {0x7878, 0x07, 0, 0}, + {0x7879, 0x14, 0, 0}, + {0x787a, 0x00, 0, 0}, + {0x787b, 0x01, 0, 0}, + {0x787c, 0x04, 0, 0}, + {0x787d, 0xa4, 0, 0}, + {0x787e, 0x00, 0, 0}, + {0x787f, 0x07, 0, 0}, + {0x7880, 0x04, 0, 0}, + {0x7881, 0xa6, 0, 0}, + {0x7882, 0x00, 0, 0}, + {0x7883, 0x00, 0, 0}, + {0x7884, 0x04, 0, 0}, + {0x7885, 0xa0, 0, 0}, + {0x7886, 0x04, 0, 0}, + {0x7887, 0x80, 0, 0}, + {0x7888, 0x04, 0, 0}, + {0x7889, 0x00, 0, 0}, + {0x788a, 0x05, 0, 0}, + {0x788b, 0x03, 0, 0}, + {0x788c, 0x06, 0, 0}, + {0x788d, 0x00, 0, 0}, + {0x788e, 0x0f, 0, 0}, + {0x788f, 0x00, 0, 0}, + {0x7890, 0x0f, 0, 0}, + {0x7891, 0x00, 0, 0}, + {0x7892, 0x0f, 0, 0}, + {0x7893, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x05, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x04, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x80, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x38, 0, 0}, + {0x30b0, 0x0d, 0, 0}, + {0x30b1, 0xde, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x66, 0, 0}, + {0x30b6, 0x01, 0, 0}, + {0x30b7, 0x22, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x20, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x0a, 0, 0}, + {0x3195, 0x2e, 0, 0}, + {0x30bb, 0x14, 0, 0}, + {0x315a, 0x02, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x80, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x80, 0, 0}, + {0x3250, 0xf7, 0, 0}, + {0x3012, 0x00, 0, 0}, + + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x08, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x08, 0, 0}, + + {0x30c0, 0x08, 0, 0}, + {0x3252, 0x20, 0, 0}, +}; + +#endif diff --git a/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr_low_freq.h b/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr_low_freq.h new file mode 100755 index 0000000..d0641fc --- /dev/null +++ b/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p_hdr_low_freq.h @@ -0,0 +1,1885 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OV2775_REGS_1080P_HDR_LOW_FREQ_H_ +#define _VVCAM_OV2775_REGS_1080P_HDR_LOW_FREQ_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t ov2775_init_setting_1080p_hdr_low_freq[] = { + {0x3000, 0x02, 0, 0}, + {0x3001, 0x28, 0, 0}, + {0x3002, 0x03, 0, 0}, + {0x3003, 0x01, 0, 0}, + {0x3004, 0x04, 0, 0},//0x02 + {0x3005, 0x31, 0, 0},//816Mbps //{0x3005, 0x26, 0, 0},//960Mbps + {0x3006, 0x00, 0, 0}, + {0x3007, 0x07, 0, 0},//102MHz + {0x3008, 0x01, 0, 0}, + {0x3009, 0x00, 0, 0}, + {0x300c, 0x6c, 0, 0}, + {0x300e, 0x80, 0, 0}, + {0x300f, 0x00, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3013, 0x00, 0, 0}, + {0x3014, 0xc4, 0, 0}, + {0x3015, 0x00, 0, 0}, + {0x3017, 0x00, 0, 0}, + {0x3018, 0x00, 0, 0}, + {0x3019, 0x00, 0, 0}, + {0x301a, 0x00, 0, 0}, + {0x301b, 0x0e, 0, 0}, + {0x301e, 0x17, 0, 0}, + {0x301f, 0xe1, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x3031, 0x62, 0, 0}, + {0x3032, 0xf0, 0, 0}, + {0x3033, 0x30, 0, 0}, + {0x3034, 0x3f, 0, 0}, + {0x3035, 0x5f, 0, 0}, + {0x3036, 0x02, 0, 0}, + {0x3037, 0x9f, 0, 0}, + {0x3038, 0x04, 0, 0}, + {0x3039, 0xb7, 0, 0}, + {0x303a, 0x04, 0, 0}, + {0x303b, 0x07, 0, 0}, + {0x303c, 0xf0, 0, 0}, + {0x303d, 0x00, 0, 0}, + {0x303e, 0x0b, 0, 0}, + {0x303f, 0xe3, 0, 0}, + {0x3040, 0xf3, 0, 0}, + {0x3041, 0x29, 0, 0}, + {0x3042, 0xf6, 0, 0}, + {0x3043, 0x65, 0, 0}, + {0x3044, 0x06, 0, 0}, + {0x3045, 0x0f, 0, 0}, + {0x3046, 0x59, 0, 0}, + {0x3047, 0x07, 0, 0}, + {0x3048, 0x82, 0, 0}, + {0x3049, 0xcf, 0, 0}, + {0x304a, 0x12, 0, 0}, + {0x304b, 0x40, 0, 0}, + {0x304c, 0x33, 0, 0}, + {0x304d, 0xa4, 0, 0}, + {0x304e, 0x0b, 0, 0}, + {0x304f, 0x3d, 0, 0}, + {0x3050, 0x10, 0, 0}, + {0x3060, 0x00, 0, 0}, + {0x3061, 0x64, 0, 0}, + {0x3062, 0x00, 0, 0}, + {0x3063, 0xe4, 0, 0}, + {0x3066, 0x80, 0, 0}, + {0x3080, 0x00, 0, 0}, + {0x3081, 0x00, 0, 0}, + {0x3082, 0x01, 0, 0}, + {0x3083, 0xe3, 0, 0}, + {0x3084, 0x06, 0, 0}, + {0x3085, 0x00, 0, 0}, + {0x3086, 0x10, 0, 0}, + {0x3087, 0x10, 0, 0}, + {0x3089, 0x00, 0, 0}, + {0x308a, 0x01, 0, 0}, + {0x3093, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x00, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x00, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x90, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x48, 0, 0}, + {0x30b0, 0x08, 0, 0}, + {0x30b1, 0xae, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x65, 0, 0}, + {0x30b4, 0x00, 0, 0}, + {0x30b5, 0x00, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x10, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x02, 0, 0}, + {0x30ba, 0x10, 0, 0}, + {0x30bb, 0x00, 0, 0}, + {0x30bc, 0x00, 0, 0}, + {0x30bd, 0x03, 0, 0}, + {0x30be, 0x5c, 0, 0}, + {0x30bf, 0x00, 0, 0}, + {0x30c0, 0x05, 0, 0}, + {0x30c1, 0x00, 0, 0}, + {0x30c2, 0x20, 0, 0}, + {0x30c3, 0x00, 0, 0}, + {0x30c4, 0x4a, 0, 0}, + {0x30c5, 0x00, 0, 0}, + {0x30c7, 0x00, 0, 0}, + {0x30c8, 0x00, 0, 0}, + {0x30d1, 0x00, 0, 0}, + {0x30d2, 0x00, 0, 0}, + {0x30d3, 0x80, 0, 0}, + {0x30d4, 0x00, 0, 0}, + {0x30d9, 0x09, 0, 0}, + {0x30da, 0x64, 0, 0}, + {0x30dd, 0x00, 0, 0}, + {0x30de, 0x16, 0, 0}, + {0x30df, 0x00, 0, 0}, + {0x30e0, 0x17, 0, 0}, + {0x30e1, 0x00, 0, 0}, + {0x30e2, 0x18, 0, 0}, + {0x30e3, 0x10, 0, 0}, + {0x30e4, 0x04, 0, 0}, + {0x30e5, 0x00, 0, 0}, + {0x30e6, 0x00, 0, 0}, + {0x30e7, 0x00, 0, 0}, + {0x30e8, 0x00, 0, 0}, + {0x30e9, 0x00, 0, 0}, + {0x30ea, 0x00, 0, 0}, + {0x30eb, 0x00, 0, 0}, + {0x30ec, 0x00, 0, 0}, + {0x30ed, 0x00, 0, 0}, + {0x3101, 0x00, 0, 0}, + {0x3102, 0x00, 0, 0}, + {0x3103, 0x00, 0, 0}, + {0x3104, 0x00, 0, 0}, + {0x3105, 0x8c, 0, 0}, + {0x3106, 0x87, 0, 0}, + {0x3107, 0xc0, 0, 0}, + {0x3108, 0x9d, 0, 0}, + {0x3109, 0x8d, 0, 0}, + {0x310a, 0x8d, 0, 0}, + {0x310b, 0x6a, 0, 0}, + {0x310c, 0x3a, 0, 0}, + {0x310d, 0x5a, 0, 0}, + {0x310e, 0x00, 0, 0}, + {0x3120, 0x00, 0, 0}, + {0x3121, 0x00, 0, 0}, + {0x3122, 0x00, 0, 0}, + {0x3123, 0x00, 0, 0}, + {0x3124, 0x00, 0, 0}, + {0x3125, 0x70, 0, 0}, + {0x3126, 0x1f, 0, 0}, + {0x3127, 0x0f, 0, 0}, + {0x3128, 0x00, 0, 0}, + {0x3129, 0x3a, 0, 0}, + {0x312a, 0x02, 0, 0}, + {0x312b, 0x0f, 0, 0}, + {0x312c, 0x00, 0, 0}, + {0x312d, 0x0f, 0, 0}, + {0x312e, 0x1d, 0, 0}, + {0x312f, 0x00, 0, 0}, + {0x3130, 0x00, 0, 0}, + {0x3131, 0x00, 0, 0}, + {0x3132, 0x00, 0, 0}, + {0x3140, 0x0a, 0, 0}, + {0x3141, 0x03, 0, 0}, + {0x3142, 0x00, 0, 0}, + {0x3143, 0x00, 0, 0}, + {0x3144, 0x00, 0, 0}, + {0x3145, 0x00, 0, 0}, + {0x3146, 0x00, 0, 0}, + {0x3147, 0x00, 0, 0}, + {0x3148, 0x00, 0, 0}, + {0x3149, 0x00, 0, 0}, + {0x314a, 0x00, 0, 0}, + {0x314b, 0x00, 0, 0}, + {0x314c, 0x00, 0, 0}, + {0x314d, 0x00, 0, 0}, + {0x314e, 0x1c, 0, 0}, + {0x314f, 0xff, 0, 0}, + {0x3150, 0xff, 0, 0}, + {0x3151, 0xff, 0, 0}, + {0x3152, 0x10, 0, 0}, + {0x3153, 0x10, 0, 0}, + {0x3154, 0x10, 0, 0}, + {0x3155, 0x00, 0, 0}, + {0x3156, 0x03, 0, 0}, + {0x3157, 0x00, 0, 0}, + {0x3158, 0x0f, 0, 0}, + {0x3159, 0xff, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x00, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x00, 0, 0}, + {0x3160, 0x00, 0, 0}, + {0x3161, 0x40, 0, 0}, + {0x3162, 0x00, 0, 0}, + {0x3163, 0x40, 0, 0}, + {0x3164, 0x00, 0, 0}, + {0x3165, 0x40, 0, 0}, + {0x3190, 0x05, 0, 0}, + {0x3191, 0x99, 0, 0}, + {0x3193, 0x08, 0, 0}, + {0x3194, 0x13, 0, 0}, + {0x3195, 0x33, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x10, 0, 0}, + {0x3198, 0x00, 0, 0}, + {0x3199, 0x3f, 0, 0}, + {0x319a, 0x40, 0, 0}, + {0x319b, 0x7f, 0, 0}, + {0x319c, 0x80, 0, 0}, + {0x319d, 0xbf, 0, 0}, + {0x319e, 0xc0, 0, 0}, + {0x319f, 0xff, 0, 0}, + {0x31a0, 0x24, 0, 0}, + {0x31a1, 0x55, 0, 0}, + {0x31a2, 0x00, 0, 0}, + {0x31a3, 0x00, 0, 0}, + {0x31a6, 0x00, 0, 0}, + {0x31a7, 0x00, 0, 0}, + {0x31b0, 0x00, 0, 0}, + {0x31b1, 0x00, 0, 0}, + {0x31b2, 0x02, 0, 0}, + {0x31b3, 0x00, 0, 0}, + {0x31b4, 0x00, 0, 0}, + {0x31b5, 0x01, 0, 0}, + {0x31b6, 0x00, 0, 0}, + {0x31b7, 0x00, 0, 0}, + {0x31b8, 0x00, 0, 0}, + {0x31b9, 0x00, 0, 0}, + {0x31ba, 0x00, 0, 0}, + {0x31d0, 0x3c, 0, 0}, + {0x31d1, 0x34, 0, 0}, + {0x31d2, 0x3c, 0, 0}, + {0x31d3, 0x00, 0, 0}, + {0x31d4, 0x2d, 0, 0}, + {0x31d5, 0x00, 0, 0}, + {0x31d6, 0x01, 0, 0}, + {0x31d7, 0x06, 0, 0}, + {0x31d8, 0x00, 0, 0}, + {0x31d9, 0x64, 0, 0}, + {0x31da, 0x00, 0, 0}, + {0x31db, 0x30, 0, 0}, + {0x31dc, 0x04, 0, 0}, + {0x31dd, 0x69, 0, 0}, + {0x31de, 0x0a, 0, 0}, + {0x31df, 0x3c, 0, 0}, + {0x31e0, 0x04, 0, 0}, + {0x31e1, 0x32, 0, 0}, + {0x31e2, 0x00, 0, 0}, + {0x31e3, 0x00, 0, 0}, + {0x31e4, 0x08, 0, 0}, + {0x31e5, 0x80, 0, 0}, + {0x31e6, 0x00, 0, 0}, + {0x31e7, 0x2c, 0, 0}, + {0x31e8, 0x6c, 0, 0}, + {0x31e9, 0xac, 0, 0}, + {0x31ea, 0xec, 0, 0}, + {0x31eb, 0x3f, 0, 0}, + {0x31ec, 0x07, 0, 0}, + {0x31ed, 0x80, 0, 0}, + {0x31ee, 0x04, 0, 0}, + {0x31ef, 0x38, 0, 0}, + {0x31f0, 0x07, 0, 0}, + {0x31f1, 0x80, 0, 0}, + {0x31f2, 0x04, 0, 0}, + {0x31f3, 0x38, 0, 0}, + {0x31f4, 0x07, 0, 0}, + {0x31f5, 0x80, 0, 0}, + {0x31f6, 0x04, 0, 0}, + {0x31f7, 0x38, 0, 0}, + {0x31f8, 0x07, 0, 0}, + {0x31f9, 0x80, 0, 0}, + {0x31fa, 0x04, 0, 0}, + {0x31fb, 0x38, 0, 0}, + {0x31fd, 0xcb, 0, 0}, + {0x31fe, 0x0f, 0, 0}, + {0x31ff, 0x03, 0, 0}, + {0x3200, 0x00, 0, 0}, + {0x3201, 0xff, 0, 0}, + {0x3202, 0x00, 0, 0}, + {0x3203, 0xff, 0, 0}, + {0x3204, 0xff, 0, 0}, + {0x3205, 0xff, 0, 0}, + {0x3206, 0xff, 0, 0}, + {0x3207, 0xff, 0, 0}, + {0x3208, 0xff, 0, 0}, + {0x3209, 0xff, 0, 0}, + {0x320a, 0xff, 0, 0}, + {0x320b, 0x1b, 0, 0}, + {0x320c, 0x1f, 0, 0}, + {0x320d, 0x1e, 0, 0}, + {0x320e, 0x30, 0, 0}, + {0x320f, 0x2d, 0, 0}, + {0x3210, 0x2c, 0, 0}, + {0x3211, 0x2b, 0, 0}, + {0x3212, 0x2a, 0, 0}, + {0x3213, 0x24, 0, 0}, + {0x3214, 0x22, 0, 0}, + {0x3215, 0x00, 0, 0}, + {0x3216, 0x04, 0, 0}, + {0x3217, 0x2c, 0, 0}, + {0x3218, 0x6c, 0, 0}, + {0x3219, 0xac, 0, 0}, + {0x321a, 0xec, 0, 0}, + {0x321b, 0x00, 0, 0}, + {0x3230, 0x3a, 0, 0}, + {0x3231, 0x00, 0, 0}, + {0x3232, 0x80, 0, 0}, + {0x3233, 0x00, 0, 0}, + {0x3234, 0x10, 0, 0}, + {0x3235, 0xaa, 0, 0}, + {0x3236, 0x55, 0, 0}, + {0x3237, 0x99, 0, 0}, + {0x3238, 0x66, 0, 0}, + {0x3239, 0x08, 0, 0}, + {0x323a, 0x88, 0, 0}, + {0x323b, 0x00, 0, 0}, + {0x323c, 0x00, 0, 0}, + {0x323d, 0x03, 0, 0}, + {0x3250, 0x33, 0, 0}, + {0x3251, 0x00, 0, 0}, + {0x3252, 0x20, 0, 0}, + {0x3253, 0x00, 0, 0}, + {0x3254, 0x11, 0, 0}, + {0x3255, 0x01, 0, 0}, + {0x3256, 0x00, 0, 0}, + {0x3257, 0x00, 0, 0}, + {0x3258, 0x00, 0, 0}, + {0x3270, 0x01, 0, 0}, + {0x3271, 0x60, 0, 0}, + {0x3272, 0xc0, 0, 0}, + {0x3273, 0x00, 0, 0}, + {0x3274, 0x80, 0, 0}, + {0x3275, 0x40, 0, 0}, + {0x3276, 0x02, 0, 0}, + {0x3277, 0x08, 0, 0}, + {0x3278, 0x10, 0, 0}, + {0x3279, 0x04, 0, 0}, + {0x327a, 0x00, 0, 0}, + {0x327b, 0x03, 0, 0}, + {0x327c, 0x10, 0, 0}, + {0x327d, 0x60, 0, 0}, + {0x327e, 0xc0, 0, 0}, + {0x327f, 0x06, 0, 0}, + {0x3288, 0x10, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x08, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x04, 0, 0}, + {0x328d, 0x00, 0, 0}, + {0x328e, 0x02, 0, 0}, + {0x328f, 0x00, 0, 0}, + {0x3290, 0x20, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x10, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x08, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x04, 0, 0}, + {0x3297, 0x00, 0, 0}, + {0x3298, 0x40, 0, 0}, + {0x3299, 0x00, 0, 0}, + {0x329a, 0x20, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x10, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x08, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x40, 0, 0}, + {0x32a3, 0x00, 0, 0}, + {0x32a4, 0x20, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x10, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32a8, 0x00, 0, 0}, + {0x32a9, 0x00, 0, 0}, + {0x32aa, 0x00, 0, 0}, + {0x32ab, 0x00, 0, 0}, + {0x32ac, 0x00, 0, 0}, + {0x32ad, 0x00, 0, 0}, + {0x32ae, 0x00, 0, 0}, + {0x32af, 0x00, 0, 0}, + {0x32b0, 0x00, 0, 0}, + {0x32b1, 0x00, 0, 0}, + {0x32b2, 0x00, 0, 0}, + {0x32b3, 0x00, 0, 0}, + {0x32b4, 0x00, 0, 0}, + {0x32b5, 0x00, 0, 0}, + {0x32b6, 0x00, 0, 0}, + {0x32b7, 0x00, 0, 0}, + {0x32b8, 0x00, 0, 0}, + {0x32b9, 0x00, 0, 0}, + {0x32ba, 0x00, 0, 0}, + {0x32bb, 0x00, 0, 0}, + {0x32bc, 0x00, 0, 0}, + {0x32bd, 0x00, 0, 0}, + {0x32be, 0x00, 0, 0}, + {0x32bf, 0x00, 0, 0}, + {0x32c0, 0x00, 0, 0}, + {0x32c1, 0x00, 0, 0}, + {0x32c2, 0x00, 0, 0}, + {0x32c3, 0x00, 0, 0}, + {0x32c4, 0x00, 0, 0}, + {0x32c5, 0x00, 0, 0}, + {0x32c6, 0x00, 0, 0}, + {0x32c7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x32c9, 0x00, 0, 0}, + {0x3330, 0x03, 0, 0}, + {0x3331, 0xc8, 0, 0}, + {0x3332, 0x02, 0, 0}, + {0x3333, 0x24, 0, 0}, + {0x3334, 0x00, 0, 0}, + {0x3335, 0x00, 0, 0}, + {0x3336, 0x00, 0, 0}, + {0x3337, 0x00, 0, 0}, + {0x3338, 0x03, 0, 0}, + {0x3339, 0xc8, 0, 0}, + {0x333a, 0x02, 0, 0}, + {0x333b, 0x24, 0, 0}, + {0x333c, 0x00, 0, 0}, + {0x333d, 0x00, 0, 0}, + {0x333e, 0x00, 0, 0}, + {0x333f, 0x00, 0, 0}, + {0x3340, 0x03, 0, 0}, + {0x3341, 0xc8, 0, 0}, + {0x3342, 0x02, 0, 0}, + {0x3343, 0x24, 0, 0}, + {0x3344, 0x00, 0, 0}, + {0x3345, 0x00, 0, 0}, + {0x3346, 0x00, 0, 0}, + {0x3347, 0x00, 0, 0}, + {0x3348, 0x40, 0, 0}, + {0x3349, 0x00, 0, 0}, + {0x334a, 0x00, 0, 0}, + {0x334b, 0x00, 0, 0}, + {0x334c, 0x00, 0, 0}, + {0x334d, 0x00, 0, 0}, + {0x334e, 0x80, 0, 0}, + {0x3360, 0x01, 0, 0}, + {0x3361, 0x00, 0, 0}, + {0x3362, 0x01, 0, 0}, + {0x3363, 0x00, 0, 0}, + {0x3364, 0x01, 0, 0}, + {0x3365, 0x00, 0, 0}, + {0x3366, 0x01, 0, 0}, + {0x3367, 0x00, 0, 0}, + {0x3368, 0x01, 0, 0}, + {0x3369, 0x00, 0, 0}, + {0x336a, 0x01, 0, 0}, + {0x336b, 0x00, 0, 0}, + {0x336c, 0x01, 0, 0}, + {0x336d, 0x00, 0, 0}, + {0x336e, 0x01, 0, 0}, + {0x336f, 0x00, 0, 0}, + {0x3370, 0x01, 0, 0}, + {0x3371, 0x00, 0, 0}, + {0x3372, 0x01, 0, 0}, + {0x3373, 0x00, 0, 0}, + {0x3374, 0x01, 0, 0}, + {0x3375, 0x00, 0, 0}, + {0x3376, 0x01, 0, 0}, + {0x3377, 0x00, 0, 0}, + {0x3378, 0x00, 0, 0}, + {0x3379, 0x00, 0, 0}, + {0x337a, 0x00, 0, 0}, + {0x337b, 0x00, 0, 0}, + {0x337c, 0x00, 0, 0}, + {0x337d, 0x00, 0, 0}, + {0x337e, 0x00, 0, 0}, + {0x337f, 0x00, 0, 0}, + {0x3380, 0x00, 0, 0}, + {0x3381, 0x00, 0, 0}, + {0x3382, 0x00, 0, 0}, + {0x3383, 0x00, 0, 0}, + {0x3384, 0x00, 0, 0}, + {0x3385, 0x00, 0, 0}, + {0x3386, 0x00, 0, 0}, + {0x3387, 0x00, 0, 0}, + {0x3388, 0x00, 0, 0}, + {0x3389, 0x00, 0, 0}, + {0x338a, 0x00, 0, 0}, + {0x338b, 0x00, 0, 0}, + {0x338c, 0x00, 0, 0}, + {0x338d, 0x00, 0, 0}, + {0x338e, 0x00, 0, 0}, + {0x338f, 0x00, 0, 0}, + {0x3390, 0x00, 0, 0}, + {0x3391, 0x00, 0, 0}, + {0x3392, 0x00, 0, 0}, + {0x3393, 0x00, 0, 0}, + {0x3394, 0x00, 0, 0}, + {0x3395, 0x00, 0, 0}, + {0x3396, 0x00, 0, 0}, + {0x3397, 0x00, 0, 0}, + {0x3398, 0x00, 0, 0}, + {0x3399, 0x00, 0, 0}, + {0x339a, 0x00, 0, 0}, + {0x339b, 0x00, 0, 0}, + {0x33b0, 0x00, 0, 0}, + {0x33b1, 0x50, 0, 0}, + {0x33b2, 0x01, 0, 0}, + {0x33b3, 0xff, 0, 0}, + {0x33b4, 0xe0, 0, 0}, + {0x33b5, 0x6b, 0, 0}, + {0x33b6, 0x00, 0, 0}, + {0x33b7, 0x00, 0, 0}, + {0x33b8, 0x00, 0, 0}, + {0x33b9, 0x00, 0, 0}, + {0x33ba, 0x00, 0, 0}, + {0x33bb, 0x1f, 0, 0}, + {0x33bc, 0x01, 0, 0}, + {0x33bd, 0x01, 0, 0}, + {0x33be, 0x01, 0, 0}, + {0x33bf, 0x01, 0, 0}, + {0x33c0, 0x00, 0, 0}, + {0x33c1, 0x00, 0, 0}, + {0x33c2, 0x00, 0, 0}, + {0x33c3, 0x00, 0, 0}, + {0x33e0, 0x14, 0, 0}, + {0x33e1, 0x0f, 0, 0}, + {0x33e2, 0x04, 0, 0}, + {0x33e3, 0x02, 0, 0}, + {0x33e4, 0x01, 0, 0}, + {0x33e5, 0x01, 0, 0}, + {0x33e6, 0x00, 0, 0}, + {0x33e7, 0x04, 0, 0}, + {0x33e8, 0x0c, 0, 0}, + {0x33e9, 0x02, 0, 0}, + {0x33ea, 0x02, 0, 0}, + {0x33eb, 0x02, 0, 0}, + {0x33ec, 0x03, 0, 0}, + {0x33ed, 0x02, 0, 0}, + {0x33ee, 0x05, 0, 0}, + {0x33ef, 0x0a, 0, 0}, + {0x33f0, 0x08, 0, 0}, + {0x33f1, 0x04, 0, 0}, + {0x33f2, 0x04, 0, 0}, + {0x33f3, 0x00, 0, 0}, + {0x33f4, 0x03, 0, 0}, + {0x33f5, 0x14, 0, 0}, + {0x33f6, 0x0f, 0, 0}, + {0x33f7, 0x02, 0, 0}, + {0x33f8, 0x01, 0, 0}, + {0x33f9, 0x01, 0, 0}, + {0x33fa, 0x01, 0, 0}, + {0x33fb, 0x00, 0, 0}, + {0x33fc, 0x04, 0, 0}, + {0x33fd, 0x0c, 0, 0}, + {0x33fe, 0x02, 0, 0}, + {0x33ff, 0x02, 0, 0}, + {0x3400, 0x02, 0, 0}, + {0x3401, 0x03, 0, 0}, + {0x3402, 0x01, 0, 0}, + {0x3403, 0x02, 0, 0}, + {0x3404, 0x08, 0, 0}, + {0x3405, 0x08, 0, 0}, + {0x3406, 0x04, 0, 0}, + {0x3407, 0x04, 0, 0}, + {0x3408, 0x00, 0, 0}, + {0x3409, 0x03, 0, 0}, + {0x340a, 0x14, 0, 0}, + {0x340b, 0x0f, 0, 0}, + {0x340c, 0x04, 0, 0}, + {0x340d, 0x02, 0, 0}, + {0x340e, 0x01, 0, 0}, + {0x340f, 0x01, 0, 0}, + {0x3410, 0x00, 0, 0}, + {0x3411, 0x04, 0, 0}, + {0x3412, 0x0c, 0, 0}, + {0x3413, 0x02, 0, 0}, + {0x3414, 0x02, 0, 0}, + {0x3415, 0x02, 0, 0}, + {0x3416, 0x03, 0, 0}, + {0x3417, 0x02, 0, 0}, + {0x3418, 0x05, 0, 0}, + {0x3419, 0x0a, 0, 0}, + {0x341a, 0x08, 0, 0}, + {0x341b, 0x04, 0, 0}, + {0x341c, 0x04, 0, 0}, + {0x341d, 0x00, 0, 0}, + {0x341e, 0x03, 0, 0}, + {0x3440, 0x00, 0, 0}, + {0x3441, 0x00, 0, 0}, + {0x3442, 0x00, 0, 0}, + {0x3443, 0x00, 0, 0}, + {0x3444, 0x02, 0, 0}, + {0x3445, 0xf0, 0, 0}, + {0x3446, 0x02, 0, 0}, + {0x3447, 0x08, 0, 0}, + {0x3448, 0x00, 0, 0}, + {0x3460, 0x40, 0, 0}, + {0x3461, 0x40, 0, 0}, + {0x3462, 0x40, 0, 0}, + {0x3463, 0x40, 0, 0}, + {0x3464, 0x03, 0, 0}, + {0x3465, 0x01, 0, 0}, + {0x3466, 0x01, 0, 0}, + {0x3467, 0x02, 0, 0}, + {0x3468, 0x30, 0, 0}, + {0x3469, 0x00, 0, 0}, + {0x346a, 0x35, 0, 0}, + {0x346b, 0x00, 0, 0}, + {0x3480, 0x40, 0, 0}, + {0x3481, 0x00, 0, 0}, + {0x3482, 0x00, 0, 0}, + {0x3483, 0x00, 0, 0}, + {0x3484, 0x0d, 0, 0}, + {0x3485, 0x00, 0, 0}, + {0x3486, 0x00, 0, 0}, + {0x3487, 0x00, 0, 0}, + {0x3488, 0x00, 0, 0}, + {0x3489, 0x00, 0, 0}, + {0x348a, 0x00, 0, 0}, + {0x348b, 0x04, 0, 0}, + {0x348c, 0x00, 0, 0}, + {0x348d, 0x01, 0, 0}, + {0x348f, 0x01, 0, 0}, + {0x3030, 0x0a, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x7000, 0x58, 0, 0}, + {0x7001, 0x7a, 0, 0}, + {0x7002, 0x1a, 0, 0}, + {0x7003, 0xc1, 0, 0}, + {0x7004, 0x03, 0, 0}, + {0x7005, 0xda, 0, 0}, + {0x7006, 0xbd, 0, 0}, + {0x7007, 0x03, 0, 0}, + {0x7008, 0xbd, 0, 0}, + {0x7009, 0x06, 0, 0}, + {0x700a, 0xe6, 0, 0}, + {0x700b, 0xec, 0, 0}, + {0x700c, 0xbc, 0, 0}, + {0x700d, 0xff, 0, 0}, + {0x700e, 0xbc, 0, 0}, + {0x700f, 0x73, 0, 0}, + {0x7010, 0xda, 0, 0}, + {0x7011, 0x72, 0, 0}, + {0x7012, 0x76, 0, 0}, + {0x7013, 0xb6, 0, 0}, + {0x7014, 0xee, 0, 0}, + {0x7015, 0xcf, 0, 0}, + {0x7016, 0xac, 0, 0}, + {0x7017, 0xd0, 0, 0}, + {0x7018, 0xac, 0, 0}, + {0x7019, 0xd1, 0, 0}, + {0x701a, 0x50, 0, 0}, + {0x701b, 0xac, 0, 0}, + {0x701c, 0xd2, 0, 0}, + {0x701d, 0xbc, 0, 0}, + {0x701e, 0x2e, 0, 0}, + {0x701f, 0xb4, 0, 0}, + {0x7020, 0x00, 0, 0}, + {0x7021, 0xdc, 0, 0}, + {0x7022, 0xdf, 0, 0}, + {0x7023, 0xb0, 0, 0}, + {0x7024, 0x6e, 0, 0}, + {0x7025, 0xbd, 0, 0}, + {0x7026, 0x01, 0, 0}, + {0x7027, 0xd7, 0, 0}, + {0x7028, 0xed, 0, 0}, + {0x7029, 0xe1, 0, 0}, + {0x702a, 0x36, 0, 0}, + {0x702b, 0x30, 0, 0}, + {0x702c, 0xd3, 0, 0}, + {0x702d, 0x2e, 0, 0}, + {0x702e, 0x54, 0, 0}, + {0x702f, 0x46, 0, 0}, + {0x7030, 0xbc, 0, 0}, + {0x7031, 0x22, 0, 0}, + {0x7032, 0x66, 0, 0}, + {0x7033, 0xbc, 0, 0}, + {0x7034, 0x24, 0, 0}, + {0x7035, 0x2c, 0, 0}, + {0x7036, 0x28, 0, 0}, + {0x7037, 0xbc, 0, 0}, + {0x7038, 0x3c, 0, 0}, + {0x7039, 0xa1, 0, 0}, + {0x703a, 0xac, 0, 0}, + {0x703b, 0xd8, 0, 0}, + {0x703c, 0xd6, 0, 0}, + {0x703d, 0xb4, 0, 0}, + {0x703e, 0x04, 0, 0}, + {0x703f, 0x46, 0, 0}, + {0x7040, 0xb7, 0, 0}, + {0x7041, 0x04, 0, 0}, + {0x7042, 0xbe, 0, 0}, + {0x7043, 0x08, 0, 0}, + {0x7044, 0xc3, 0, 0}, + {0x7045, 0xd9, 0, 0}, + {0x7046, 0xad, 0, 0}, + {0x7047, 0xc3, 0, 0}, + {0x7048, 0xbc, 0, 0}, + {0x7049, 0x19, 0, 0}, + {0x704a, 0xc1, 0, 0}, + {0x704b, 0x27, 0, 0}, + {0x704c, 0xe7, 0, 0}, + {0x704d, 0x00, 0, 0}, + {0x704e, 0x50, 0, 0}, + {0x704f, 0x20, 0, 0}, + {0x7050, 0xb8, 0, 0}, + {0x7051, 0x02, 0, 0}, + {0x7052, 0xbc, 0, 0}, + {0x7053, 0x17, 0, 0}, + {0x7054, 0xdb, 0, 0}, + {0x7055, 0xc7, 0, 0}, + {0x7056, 0xb8, 0, 0}, + {0x7057, 0x00, 0, 0}, + {0x7058, 0x28, 0, 0}, + {0x7059, 0x54, 0, 0}, + {0x705a, 0xb4, 0, 0}, + {0x705b, 0x14, 0, 0}, + {0x705c, 0xab, 0, 0}, + {0x705d, 0xbe, 0, 0}, + {0x705e, 0x06, 0, 0}, + {0x705f, 0xd8, 0, 0}, + {0x7060, 0xd6, 0, 0}, + {0x7061, 0x00, 0, 0}, + {0x7062, 0xb4, 0, 0}, + {0x7063, 0xc7, 0, 0}, + {0x7064, 0x07, 0, 0}, + {0x7065, 0xb9, 0, 0}, + {0x7066, 0x05, 0, 0}, + {0x7067, 0xee, 0, 0}, + {0x7068, 0xe6, 0, 0}, + {0x7069, 0xad, 0, 0}, + {0x706a, 0xb4, 0, 0}, + {0x706b, 0x26, 0, 0}, + {0x706c, 0x19, 0, 0}, + {0x706d, 0xc1, 0, 0}, + {0x706e, 0x3a, 0, 0}, + {0x706f, 0xc3, 0, 0}, + {0x7070, 0xaf, 0, 0}, + {0x7071, 0x00, 0, 0}, + {0x7072, 0xc0, 0, 0}, + {0x7073, 0x3c, 0, 0}, + {0x7074, 0xc3, 0, 0}, + {0x7075, 0xbe, 0, 0}, + {0x7076, 0xe7, 0, 0}, + {0x7077, 0x00, 0, 0}, + {0x7078, 0x15, 0, 0}, + {0x7079, 0xc2, 0, 0}, + {0x707a, 0x40, 0, 0}, + {0x707b, 0xc3, 0, 0}, + {0x707c, 0xa4, 0, 0}, + {0x707d, 0xc0, 0, 0}, + {0x707e, 0x3c, 0, 0}, + {0x707f, 0x00, 0, 0}, + {0x7080, 0xb9, 0, 0}, + {0x7081, 0x64, 0, 0}, + {0x7082, 0x29, 0, 0}, + {0x7083, 0x00, 0, 0}, + {0x7084, 0xb8, 0, 0}, + {0x7085, 0x12, 0, 0}, + {0x7086, 0xbe, 0, 0}, + {0x7087, 0x01, 0, 0}, + {0x7088, 0xd0, 0, 0}, + {0x7089, 0xbc, 0, 0}, + {0x708a, 0x01, 0, 0}, + {0x708b, 0xac, 0, 0}, + {0x708c, 0x37, 0, 0}, + {0x708d, 0xd2, 0, 0}, + {0x708e, 0xac, 0, 0}, + {0x708f, 0x45, 0, 0}, + {0x7090, 0xad, 0, 0}, + {0x7091, 0x28, 0, 0}, + {0x7092, 0x00, 0, 0}, + {0x7093, 0xb8, 0, 0}, + {0x7094, 0x00, 0, 0}, + {0x7095, 0xbc, 0, 0}, + {0x7096, 0x01, 0, 0}, + {0x7097, 0x36, 0, 0}, + {0x7098, 0xd3, 0, 0}, + {0x7099, 0x30, 0, 0}, + {0x709a, 0x04, 0, 0}, + {0x709b, 0xe0, 0, 0}, + {0x709c, 0xd8, 0, 0}, + {0x709d, 0xb4, 0, 0}, + {0x709e, 0xe9, 0, 0}, + {0x709f, 0x00, 0, 0}, + {0x70a0, 0xbe, 0, 0}, + {0x70a1, 0x05, 0, 0}, + {0x70a2, 0x62, 0, 0}, + {0x70a3, 0x07, 0, 0}, + {0x70a4, 0xb9, 0, 0}, + {0x70a5, 0x05, 0, 0}, + {0x70a6, 0xad, 0, 0}, + {0x70a7, 0xc3, 0, 0}, + {0x70a8, 0xcf, 0, 0}, + {0x70a9, 0x00, 0, 0}, + {0x70aa, 0x15, 0, 0}, + {0x70ab, 0xc2, 0, 0}, + {0x70ac, 0x59, 0, 0}, + {0x70ad, 0xc3, 0, 0}, + {0x70ae, 0xc9, 0, 0}, + {0x70af, 0xc0, 0, 0}, + {0x70b0, 0x55, 0, 0}, + {0x70b1, 0x00, 0, 0}, + {0x70b2, 0x46, 0, 0}, + {0x70b3, 0xa1, 0, 0}, + {0x70b4, 0xb9, 0, 0}, + {0x70b5, 0x64, 0, 0}, + {0x70b6, 0x29, 0, 0}, + {0x70b7, 0x00, 0, 0}, + {0x70b8, 0xb8, 0, 0}, + {0x70b9, 0x02, 0, 0}, + {0x70ba, 0xbe, 0, 0}, + {0x70bb, 0x02, 0, 0}, + {0x70bc, 0xd0, 0, 0}, + {0x70bd, 0xdc, 0, 0}, + {0x70be, 0xac, 0, 0}, + {0x70bf, 0xbc, 0, 0}, + {0x70c0, 0x01, 0, 0}, + {0x70c1, 0x37, 0, 0}, + {0x70c2, 0xac, 0, 0}, + {0x70c3, 0xd2, 0, 0}, + {0x70c4, 0x45, 0, 0}, + {0x70c5, 0xad, 0, 0}, + {0x70c6, 0x28, 0, 0}, + {0x70c7, 0x00, 0, 0}, + {0x70c8, 0xb8, 0, 0}, + {0x70c9, 0x00, 0, 0}, + {0x70ca, 0xbc, 0, 0}, + {0x70cb, 0x01, 0, 0}, + {0x70cc, 0x36, 0, 0}, + {0x70cd, 0x30, 0, 0}, + {0x70ce, 0xe0, 0, 0}, + {0x70cf, 0xd8, 0, 0}, + {0x70d0, 0xb5, 0, 0}, + {0x70d1, 0x0b, 0, 0}, + {0x70d2, 0xd6, 0, 0}, + {0x70d3, 0xbe, 0, 0}, + {0x70d4, 0x07, 0, 0}, + {0x70d5, 0x00, 0, 0}, + {0x70d6, 0x62, 0, 0}, + {0x70d7, 0x07, 0, 0}, + {0x70d8, 0xb9, 0, 0}, + {0x70d9, 0x05, 0, 0}, + {0x70da, 0xad, 0, 0}, + {0x70db, 0xc3, 0, 0}, + {0x70dc, 0xcf, 0, 0}, + {0x70dd, 0x46, 0, 0}, + {0x70de, 0xcd, 0, 0}, + {0x70df, 0x07, 0, 0}, + {0x70e0, 0xcd, 0, 0}, + {0x70e1, 0x00, 0, 0}, + {0x70e2, 0xe3, 0, 0}, + {0x70e3, 0x18, 0, 0}, + {0x70e4, 0xc2, 0, 0}, + {0x70e5, 0xa2, 0, 0}, + {0x70e6, 0xb9, 0, 0}, + {0x70e7, 0x64, 0, 0}, + {0x70e8, 0xd1, 0, 0}, + {0x70e9, 0xdd, 0, 0}, + {0x70ea, 0xac, 0, 0}, + {0x70eb, 0xcf, 0, 0}, + {0x70ec, 0xdf, 0, 0}, + {0x70ed, 0xb5, 0, 0}, + {0x70ee, 0x19, 0, 0}, + {0x70ef, 0x46, 0, 0}, + {0x70f0, 0x50, 0, 0}, + {0x70f1, 0xb6, 0, 0}, + {0x70f2, 0xee, 0, 0}, + {0x70f3, 0xe8, 0, 0}, + {0x70f4, 0xe6, 0, 0}, + {0x70f5, 0xbc, 0, 0}, + {0x70f6, 0x31, 0, 0}, + {0x70f7, 0xe1, 0, 0}, + {0x70f8, 0x36, 0, 0}, + {0x70f9, 0x30, 0, 0}, + {0x70fa, 0xd3, 0, 0}, + {0x70fb, 0x2e, 0, 0}, + {0x70fc, 0x54, 0, 0}, + {0x70fd, 0xbd, 0, 0}, + {0x70fe, 0x03, 0, 0}, + {0x70ff, 0xec, 0, 0}, + {0x7100, 0x2c, 0, 0}, + {0x7101, 0x50, 0, 0}, + {0x7102, 0x20, 0, 0}, + {0x7103, 0x04, 0, 0}, + {0x7104, 0xb8, 0, 0}, + {0x7105, 0x02, 0, 0}, + {0x7106, 0xbc, 0, 0}, + {0x7107, 0x18, 0, 0}, + {0x7108, 0xc7, 0, 0}, + {0x7109, 0xb8, 0, 0}, + {0x710a, 0x00, 0, 0}, + {0x710b, 0x28, 0, 0}, + {0x710c, 0x54, 0, 0}, + {0x710d, 0xbc, 0, 0}, + {0x710e, 0x02, 0, 0}, + {0x710f, 0xb4, 0, 0}, + {0x7110, 0xda, 0, 0}, + {0x7111, 0xbe, 0, 0}, + {0x7112, 0x04, 0, 0}, + {0x7113, 0xd6, 0, 0}, + {0x7114, 0xd8, 0, 0}, + {0x7115, 0xab, 0, 0}, + {0x7116, 0x00, 0, 0}, + {0x7117, 0x62, 0, 0}, + {0x7118, 0x07, 0, 0}, + {0x7119, 0xb9, 0, 0}, + {0x711a, 0x05, 0, 0}, + {0x711b, 0xad, 0, 0}, + {0x711c, 0xc3, 0, 0}, + {0x711d, 0xbc, 0, 0}, + {0x711e, 0xe7, 0, 0}, + {0x711f, 0xb9, 0, 0}, + {0x7120, 0x64, 0, 0}, + {0x7121, 0x29, 0, 0}, + {0x7122, 0x00, 0, 0}, + {0x7123, 0xb8, 0, 0}, + {0x7124, 0x02, 0, 0}, + {0x7125, 0xbe, 0, 0}, + {0x7126, 0x00, 0, 0}, + {0x7127, 0x45, 0, 0}, + {0x7128, 0xad, 0, 0}, + {0x7129, 0xe2, 0, 0}, + {0x712a, 0x28, 0, 0}, + {0x712b, 0x00, 0, 0}, + {0x712c, 0xb8, 0, 0}, + {0x712d, 0x00, 0, 0}, + {0x712e, 0xe0, 0, 0}, + {0x712f, 0xd8, 0, 0}, + {0x7130, 0xb4, 0, 0}, + {0x7131, 0xe9, 0, 0}, + {0x7132, 0xbe, 0, 0}, + {0x7133, 0x03, 0, 0}, + {0x7134, 0x00, 0, 0}, + {0x7135, 0x30, 0, 0}, + {0x7136, 0x62, 0, 0}, + {0x7137, 0x07, 0, 0}, + {0x7138, 0xb9, 0, 0}, + {0x7139, 0x05, 0, 0}, + {0x713a, 0xad, 0, 0}, + {0x713b, 0xc3, 0, 0}, + {0x713c, 0xcf, 0, 0}, + {0x713d, 0x42, 0, 0}, + {0x713e, 0xe4, 0, 0}, + {0x713f, 0xcd, 0, 0}, + {0x7140, 0x07, 0, 0}, + {0x7141, 0xcd, 0, 0}, + {0x7142, 0x00, 0, 0}, + {0x7143, 0x00, 0, 0}, + {0x7144, 0x17, 0, 0}, + {0x7145, 0xc2, 0, 0}, + {0x7146, 0xbb, 0, 0}, + {0x7147, 0xde, 0, 0}, + {0x7148, 0xcf, 0, 0}, + {0x7149, 0xdf, 0, 0}, + {0x714a, 0xac, 0, 0}, + {0x714b, 0xd1, 0, 0}, + {0x714c, 0x44, 0, 0}, + {0x714d, 0xac, 0, 0}, + {0x714e, 0xb9, 0, 0}, + {0x714f, 0x76, 0, 0}, + {0x7150, 0xb8, 0, 0}, + {0x7151, 0x08, 0, 0}, + {0x7152, 0xb6, 0, 0}, + {0x7153, 0xfe, 0, 0}, + {0x7154, 0xb4, 0, 0}, + {0x7155, 0xca, 0, 0}, + {0x7156, 0xd6, 0, 0}, + {0x7157, 0xd8, 0, 0}, + {0x7158, 0xab, 0, 0}, + {0x7159, 0x00, 0, 0}, + {0x715a, 0xe1, 0, 0}, + {0x715b, 0x36, 0, 0}, + {0x715c, 0x30, 0, 0}, + {0x715d, 0xd3, 0, 0}, + {0x715e, 0xbc, 0, 0}, + {0x715f, 0x29, 0, 0}, + {0x7160, 0xb4, 0, 0}, + {0x7161, 0x1f, 0, 0}, + {0x7162, 0xaa, 0, 0}, + {0x7163, 0xbd, 0, 0}, + {0x7164, 0x01, 0, 0}, + {0x7165, 0xb8, 0, 0}, + {0x7166, 0x0c, 0, 0}, + {0x7167, 0x45, 0, 0}, + {0x7168, 0xa4, 0, 0}, + {0x7169, 0xbd, 0, 0}, + {0x716a, 0x03, 0, 0}, + {0x716b, 0xec, 0, 0}, + {0x716c, 0xbc, 0, 0}, + {0x716d, 0x3d, 0, 0}, + {0x716e, 0xc3, 0, 0}, + {0x716f, 0xcf, 0, 0}, + {0x7170, 0x42, 0, 0}, + {0x7171, 0xb8, 0, 0}, + {0x7172, 0x00, 0, 0}, + {0x7173, 0xe4, 0, 0}, + {0x7174, 0xd5, 0, 0}, + {0x7175, 0x00, 0, 0}, + {0x7176, 0xb6, 0, 0}, + {0x7177, 0x00, 0, 0}, + {0x7178, 0x74, 0, 0}, + {0x7179, 0xbd, 0, 0}, + {0x717a, 0x03, 0, 0}, + {0x717b, 0xb5, 0, 0}, + {0x717c, 0x39, 0, 0}, + {0x717d, 0x40, 0, 0}, + {0x717e, 0x58, 0, 0}, + {0x717f, 0xdd, 0, 0}, + {0x7180, 0x19, 0, 0}, + {0x7181, 0xc1, 0, 0}, + {0x7182, 0xc8, 0, 0}, + {0x7183, 0xbd, 0, 0}, + {0x7184, 0x06, 0, 0}, + {0x7185, 0x17, 0, 0}, + {0x7186, 0xc1, 0, 0}, + {0x7187, 0xc6, 0, 0}, + {0x7188, 0xe8, 0, 0}, + {0x7189, 0x00, 0, 0}, + {0x718a, 0xc0, 0, 0}, + {0x718b, 0xc8, 0, 0}, + {0x718c, 0xe6, 0, 0}, + {0x718d, 0x95, 0, 0}, + {0x718e, 0x15, 0, 0}, + {0x718f, 0x00, 0, 0}, + {0x7190, 0xbc, 0, 0}, + {0x7191, 0x19, 0, 0}, + {0x7192, 0xb9, 0, 0}, + {0x7193, 0xf6, 0, 0}, + {0x7194, 0x14, 0, 0}, + {0x7195, 0xc1, 0, 0}, + {0x7196, 0xd0, 0, 0}, + {0x7197, 0xd1, 0, 0}, + {0x7198, 0xac, 0, 0}, + {0x7199, 0x37, 0, 0}, + {0x719a, 0xbc, 0, 0}, + {0x719b, 0x35, 0, 0}, + {0x719c, 0x36, 0, 0}, + {0x719d, 0x30, 0, 0}, + {0x719e, 0xe1, 0, 0}, + {0x719f, 0xd3, 0, 0}, + {0x71a0, 0x7a, 0, 0}, + {0x71a1, 0xb6, 0, 0}, + {0x71a2, 0x0c, 0, 0}, + {0x71a3, 0xff, 0, 0}, + {0x71a4, 0xb4, 0, 0}, + {0x71a5, 0xc7, 0, 0}, + {0x71a6, 0xd9, 0, 0}, + {0x71a7, 0x00, 0, 0}, + {0x71a8, 0xbd, 0, 0}, + {0x71a9, 0x01, 0, 0}, + {0x71aa, 0x56, 0, 0}, + {0x71ab, 0xc0, 0, 0}, + {0x71ac, 0xda, 0, 0}, + {0x71ad, 0xb4, 0, 0}, + {0x71ae, 0x1f, 0, 0}, + {0x71af, 0x56, 0, 0}, + {0x71b0, 0xaa, 0, 0}, + {0x71b1, 0xbc, 0, 0}, + {0x71b2, 0x08, 0, 0}, + {0x71b3, 0x00, 0, 0}, + {0x71b4, 0x57, 0, 0}, + {0x71b5, 0xe8, 0, 0}, + {0x71b6, 0xb5, 0, 0}, + {0x71b7, 0x36, 0, 0}, + {0x71b8, 0x00, 0, 0}, + {0x71b9, 0x54, 0, 0}, + {0x71ba, 0xe7, 0, 0}, + {0x71bb, 0xc8, 0, 0}, + {0x71bc, 0xb4, 0, 0}, + {0x71bd, 0x1f, 0, 0}, + {0x71be, 0x56, 0, 0}, + {0x71bf, 0xaa, 0, 0}, + {0x71c0, 0xbc, 0, 0}, + {0x71c1, 0x08, 0, 0}, + {0x71c2, 0x57, 0, 0}, + {0x71c3, 0x00, 0, 0}, + {0x71c4, 0xb5, 0, 0}, + {0x71c5, 0x36, 0, 0}, + {0x71c6, 0x00, 0, 0}, + {0x71c7, 0x54, 0, 0}, + {0x71c8, 0xc8, 0, 0}, + {0x71c9, 0xb5, 0, 0}, + {0x71ca, 0x18, 0, 0}, + {0x71cb, 0xd9, 0, 0}, + {0x71cc, 0x00, 0, 0}, + {0x71cd, 0xbd, 0, 0}, + {0x71ce, 0x01, 0, 0}, + {0x71cf, 0x56, 0, 0}, + {0x71d0, 0x08, 0, 0}, + {0x71d1, 0x57, 0, 0}, + {0x71d2, 0xe8, 0, 0}, + {0x71d3, 0xb4, 0, 0}, + {0x71d4, 0x42, 0, 0}, + {0x71d5, 0x00, 0, 0}, + {0x71d6, 0x54, 0, 0}, + {0x71d7, 0xe7, 0, 0}, + {0x71d8, 0xc8, 0, 0}, + {0x71d9, 0xab, 0, 0}, + {0x71da, 0x00, 0, 0}, + {0x71db, 0x66, 0, 0}, + {0x71dc, 0x62, 0, 0}, + {0x71dd, 0x06, 0, 0}, + {0x71de, 0x74, 0, 0}, + {0x71df, 0xb9, 0, 0}, + {0x71e0, 0x05, 0, 0}, + {0x71e1, 0xb7, 0, 0}, + {0x71e2, 0x14, 0, 0}, + {0x71e3, 0x0e, 0, 0}, + {0x71e4, 0xb7, 0, 0}, + {0x71e5, 0x04, 0, 0}, + {0x71e6, 0xc8, 0, 0}, + {0x7600, 0x04, 0, 0}, + {0x7601, 0x80, 0, 0}, + {0x7602, 0x07, 0, 0}, + {0x7603, 0x44, 0, 0}, + {0x7604, 0x05, 0, 0}, + {0x7605, 0x33, 0, 0}, + {0x7606, 0x0f, 0, 0}, + {0x7607, 0x00, 0, 0}, + {0x7608, 0x07, 0, 0}, + {0x7609, 0x40, 0, 0}, + {0x760a, 0x04, 0, 0}, + {0x760b, 0xe5, 0, 0}, + {0x760c, 0x06, 0, 0}, + {0x760d, 0x50, 0, 0}, + {0x760e, 0x04, 0, 0}, + {0x760f, 0xe4, 0, 0}, + {0x7610, 0x00, 0, 0}, + {0x7611, 0x00, 0, 0}, + {0x7612, 0x06, 0, 0}, + {0x7613, 0x5c, 0, 0}, + {0x7614, 0x00, 0, 0}, + {0x7615, 0x0f, 0, 0}, + {0x7616, 0x06, 0, 0}, + {0x7617, 0x1c, 0, 0}, + {0x7618, 0x00, 0, 0}, + {0x7619, 0x02, 0, 0}, + {0x761a, 0x06, 0, 0}, + {0x761b, 0xa2, 0, 0}, + {0x761c, 0x00, 0, 0}, + {0x761d, 0x01, 0, 0}, + {0x761e, 0x06, 0, 0}, + {0x761f, 0xae, 0, 0}, + {0x7620, 0x00, 0, 0}, + {0x7621, 0x0e, 0, 0}, + {0x7622, 0x05, 0, 0}, + {0x7623, 0x30, 0, 0}, + {0x7624, 0x07, 0, 0}, + {0x7625, 0x00, 0, 0}, + {0x7626, 0x0f, 0, 0}, + {0x7627, 0x00, 0, 0}, + {0x7628, 0x04, 0, 0}, + {0x7629, 0xe5, 0, 0}, + {0x762a, 0x05, 0, 0}, + {0x762b, 0x33, 0, 0}, + {0x762c, 0x06, 0, 0}, + {0x762d, 0x12, 0, 0}, + {0x762e, 0x00, 0, 0}, + {0x762f, 0x01, 0, 0}, + {0x7630, 0x06, 0, 0}, + {0x7631, 0x52, 0, 0}, + {0x7632, 0x00, 0, 0}, + {0x7633, 0x01, 0, 0}, + {0x7634, 0x06, 0, 0}, + {0x7635, 0x5e, 0, 0}, + {0x7636, 0x04, 0, 0}, + {0x7637, 0xe4, 0, 0}, + {0x7638, 0x00, 0, 0}, + {0x7639, 0x01, 0, 0}, + {0x763a, 0x05, 0, 0}, + {0x763b, 0x30, 0, 0}, + {0x763c, 0x0f, 0, 0}, + {0x763d, 0x00, 0, 0}, + {0x763e, 0x06, 0, 0}, + {0x763f, 0xa6, 0, 0}, + {0x7640, 0x00, 0, 0}, + {0x7641, 0x02, 0, 0}, + {0x7642, 0x06, 0, 0}, + {0x7643, 0x26, 0, 0}, + {0x7644, 0x00, 0, 0}, + {0x7645, 0x02, 0, 0}, + {0x7646, 0x05, 0, 0}, + {0x7647, 0x33, 0, 0}, + {0x7648, 0x06, 0, 0}, + {0x7649, 0x20, 0, 0}, + {0x764a, 0x0f, 0, 0}, + {0x764b, 0x00, 0, 0}, + {0x764c, 0x06, 0, 0}, + {0x764d, 0x56, 0, 0}, + {0x764e, 0x00, 0, 0}, + {0x764f, 0x02, 0, 0}, + {0x7650, 0x06, 0, 0}, + {0x7651, 0x16, 0, 0}, + {0x7652, 0x05, 0, 0}, + {0x7653, 0x33, 0, 0}, + {0x7654, 0x06, 0, 0}, + {0x7655, 0x10, 0, 0}, + {0x7656, 0x0f, 0, 0}, + {0x7657, 0x00, 0, 0}, + {0x7658, 0x06, 0, 0}, + {0x7659, 0x10, 0, 0}, + {0x765a, 0x0f, 0, 0}, + {0x765b, 0x00, 0, 0}, + {0x765c, 0x06, 0, 0}, + {0x765d, 0x20, 0, 0}, + {0x765e, 0x0f, 0, 0}, + {0x765f, 0x00, 0, 0}, + {0x7660, 0x00, 0, 0}, + {0x7661, 0x00, 0, 0}, + {0x7662, 0x00, 0, 0}, + {0x7663, 0x02, 0, 0}, + {0x7664, 0x04, 0, 0}, + {0x7665, 0xe5, 0, 0}, + {0x7666, 0x04, 0, 0}, + {0x7667, 0xe4, 0, 0}, + {0x7668, 0x0f, 0, 0}, + {0x7669, 0x00, 0, 0}, + {0x766a, 0x00, 0, 0}, + {0x766b, 0x00, 0, 0}, + {0x766c, 0x00, 0, 0}, + {0x766d, 0x01, 0, 0}, + {0x766e, 0x04, 0, 0}, + {0x766f, 0xe5, 0, 0}, + {0x7670, 0x04, 0, 0}, + {0x7671, 0xe4, 0, 0}, + {0x7672, 0x0f, 0, 0}, + {0x7673, 0x00, 0, 0}, + {0x7674, 0x00, 0, 0}, + {0x7675, 0x02, 0, 0}, + {0x7676, 0x04, 0, 0}, + {0x7677, 0xe4, 0, 0}, + {0x7678, 0x00, 0, 0}, + {0x7679, 0x02, 0, 0}, + {0x767a, 0x04, 0, 0}, + {0x767b, 0xc4, 0, 0}, + {0x767c, 0x00, 0, 0}, + {0x767d, 0x02, 0, 0}, + {0x767e, 0x04, 0, 0}, + {0x767f, 0xc4, 0, 0}, + {0x7680, 0x05, 0, 0}, + {0x7681, 0x83, 0, 0}, + {0x7682, 0x0f, 0, 0}, + {0x7683, 0x00, 0, 0}, + {0x7684, 0x00, 0, 0}, + {0x7685, 0x02, 0, 0}, + {0x7686, 0x04, 0, 0}, + {0x7687, 0xe4, 0, 0}, + {0x7688, 0x00, 0, 0}, + {0x7689, 0x02, 0, 0}, + {0x768a, 0x04, 0, 0}, + {0x768b, 0xc4, 0, 0}, + {0x768c, 0x00, 0, 0}, + {0x768d, 0x02, 0, 0}, + {0x768e, 0x04, 0, 0}, + {0x768f, 0xc4, 0, 0}, + {0x7690, 0x05, 0, 0}, + {0x7691, 0x83, 0, 0}, + {0x7692, 0x03, 0, 0}, + {0x7693, 0x0b, 0, 0}, + {0x7694, 0x05, 0, 0}, + {0x7695, 0x83, 0, 0}, + {0x7696, 0x00, 0, 0}, + {0x7697, 0x07, 0, 0}, + {0x7698, 0x05, 0, 0}, + {0x7699, 0x03, 0, 0}, + {0x769a, 0x00, 0, 0}, + {0x769b, 0x05, 0, 0}, + {0x769c, 0x05, 0, 0}, + {0x769d, 0x32, 0, 0}, + {0x769e, 0x05, 0, 0}, + {0x769f, 0x30, 0, 0}, + {0x76a0, 0x00, 0, 0}, + {0x76a1, 0x02, 0, 0}, + {0x76a2, 0x05, 0, 0}, + {0x76a3, 0x78, 0, 0}, + {0x76a4, 0x00, 0, 0}, + {0x76a5, 0x01, 0, 0}, + {0x76a6, 0x05, 0, 0}, + {0x76a7, 0x7c, 0, 0}, + {0x76a8, 0x03, 0, 0}, + {0x76a9, 0x9a, 0, 0}, + {0x76aa, 0x05, 0, 0}, + {0x76ab, 0x83, 0, 0}, + {0x76ac, 0x00, 0, 0}, + {0x76ad, 0x04, 0, 0}, + {0x76ae, 0x05, 0, 0}, + {0x76af, 0x03, 0, 0}, + {0x76b0, 0x00, 0, 0}, + {0x76b1, 0x03, 0, 0}, + {0x76b2, 0x05, 0, 0}, + {0x76b3, 0x32, 0, 0}, + {0x76b4, 0x05, 0, 0}, + {0x76b5, 0x30, 0, 0}, + {0x76b6, 0x00, 0, 0}, + {0x76b7, 0x02, 0, 0}, + {0x76b8, 0x05, 0, 0}, + {0x76b9, 0x78, 0, 0}, + {0x76ba, 0x00, 0, 0}, + {0x76bb, 0x01, 0, 0}, + {0x76bc, 0x05, 0, 0}, + {0x76bd, 0x7c, 0, 0}, + {0x76be, 0x03, 0, 0}, + {0x76bf, 0x99, 0, 0}, + {0x76c0, 0x05, 0, 0}, + {0x76c1, 0x83, 0, 0}, + {0x76c2, 0x00, 0, 0}, + {0x76c3, 0x03, 0, 0}, + {0x76c4, 0x05, 0, 0}, + {0x76c5, 0x03, 0, 0}, + {0x76c6, 0x00, 0, 0}, + {0x76c7, 0x01, 0, 0}, + {0x76c8, 0x05, 0, 0}, + {0x76c9, 0x32, 0, 0}, + {0x76ca, 0x05, 0, 0}, + {0x76cb, 0x30, 0, 0}, + {0x76cc, 0x00, 0, 0}, + {0x76cd, 0x02, 0, 0}, + {0x76ce, 0x05, 0, 0}, + {0x76cf, 0x78, 0, 0}, + {0x76d0, 0x00, 0, 0}, + {0x76d1, 0x01, 0, 0}, + {0x76d2, 0x05, 0, 0}, + {0x76d3, 0x7c, 0, 0}, + {0x76d4, 0x03, 0, 0}, + {0x76d5, 0x98, 0, 0}, + {0x76d6, 0x05, 0, 0}, + {0x76d7, 0x83, 0, 0}, + {0x76d8, 0x00, 0, 0}, + {0x76d9, 0x00, 0, 0}, + {0x76da, 0x05, 0, 0}, + {0x76db, 0x03, 0, 0}, + {0x76dc, 0x00, 0, 0}, + {0x76dd, 0x01, 0, 0}, + {0x76de, 0x05, 0, 0}, + {0x76df, 0x32, 0, 0}, + {0x76e0, 0x05, 0, 0}, + {0x76e1, 0x30, 0, 0}, + {0x76e2, 0x00, 0, 0}, + {0x76e3, 0x02, 0, 0}, + {0x76e4, 0x05, 0, 0}, + {0x76e5, 0x78, 0, 0}, + {0x76e6, 0x00, 0, 0}, + {0x76e7, 0x01, 0, 0}, + {0x76e8, 0x05, 0, 0}, + {0x76e9, 0x7c, 0, 0}, + {0x76ea, 0x03, 0, 0}, + {0x76eb, 0x97, 0, 0}, + {0x76ec, 0x05, 0, 0}, + {0x76ed, 0x83, 0, 0}, + {0x76ee, 0x00, 0, 0}, + {0x76ef, 0x00, 0, 0}, + {0x76f0, 0x05, 0, 0}, + {0x76f1, 0x03, 0, 0}, + {0x76f2, 0x05, 0, 0}, + {0x76f3, 0x32, 0, 0}, + {0x76f4, 0x05, 0, 0}, + {0x76f5, 0x30, 0, 0}, + {0x76f6, 0x00, 0, 0}, + {0x76f7, 0x02, 0, 0}, + {0x76f8, 0x05, 0, 0}, + {0x76f9, 0x78, 0, 0}, + {0x76fa, 0x00, 0, 0}, + {0x76fb, 0x01, 0, 0}, + {0x76fc, 0x05, 0, 0}, + {0x76fd, 0x7c, 0, 0}, + {0x76fe, 0x03, 0, 0}, + {0x76ff, 0x96, 0, 0}, + {0x7700, 0x05, 0, 0}, + {0x7701, 0x83, 0, 0}, + {0x7702, 0x05, 0, 0}, + {0x7703, 0x03, 0, 0}, + {0x7704, 0x05, 0, 0}, + {0x7705, 0x32, 0, 0}, + {0x7706, 0x05, 0, 0}, + {0x7707, 0x30, 0, 0}, + {0x7708, 0x00, 0, 0}, + {0x7709, 0x02, 0, 0}, + {0x770a, 0x05, 0, 0}, + {0x770b, 0x78, 0, 0}, + {0x770c, 0x00, 0, 0}, + {0x770d, 0x01, 0, 0}, + {0x770e, 0x05, 0, 0}, + {0x770f, 0x7c, 0, 0}, + {0x7710, 0x03, 0, 0}, + {0x7711, 0x95, 0, 0}, + {0x7712, 0x05, 0, 0}, + {0x7713, 0x83, 0, 0}, + {0x7714, 0x05, 0, 0}, + {0x7715, 0x03, 0, 0}, + {0x7716, 0x05, 0, 0}, + {0x7717, 0x32, 0, 0}, + {0x7718, 0x05, 0, 0}, + {0x7719, 0x30, 0, 0}, + {0x771a, 0x00, 0, 0}, + {0x771b, 0x02, 0, 0}, + {0x771c, 0x05, 0, 0}, + {0x771d, 0x78, 0, 0}, + {0x771e, 0x00, 0, 0}, + {0x771f, 0x01, 0, 0}, + {0x7720, 0x05, 0, 0}, + {0x7721, 0x7c, 0, 0}, + {0x7722, 0x03, 0, 0}, + {0x7723, 0x94, 0, 0}, + {0x7724, 0x05, 0, 0}, + {0x7725, 0x83, 0, 0}, + {0x7726, 0x00, 0, 0}, + {0x7727, 0x01, 0, 0}, + {0x7728, 0x05, 0, 0}, + {0x7729, 0x03, 0, 0}, + {0x772a, 0x00, 0, 0}, + {0x772b, 0x01, 0, 0}, + {0x772c, 0x05, 0, 0}, + {0x772d, 0x32, 0, 0}, + {0x772e, 0x05, 0, 0}, + {0x772f, 0x30, 0, 0}, + {0x7730, 0x00, 0, 0}, + {0x7731, 0x02, 0, 0}, + {0x7732, 0x05, 0, 0}, + {0x7733, 0x78, 0, 0}, + {0x7734, 0x00, 0, 0}, + {0x7735, 0x01, 0, 0}, + {0x7736, 0x05, 0, 0}, + {0x7737, 0x7c, 0, 0}, + {0x7738, 0x03, 0, 0}, + {0x7739, 0x93, 0, 0}, + {0x773a, 0x05, 0, 0}, + {0x773b, 0x83, 0, 0}, + {0x773c, 0x00, 0, 0}, + {0x773d, 0x00, 0, 0}, + {0x773e, 0x05, 0, 0}, + {0x773f, 0x03, 0, 0}, + {0x7740, 0x00, 0, 0}, + {0x7741, 0x00, 0, 0}, + {0x7742, 0x05, 0, 0}, + {0x7743, 0x32, 0, 0}, + {0x7744, 0x05, 0, 0}, + {0x7745, 0x30, 0, 0}, + {0x7746, 0x00, 0, 0}, + {0x7747, 0x02, 0, 0}, + {0x7748, 0x05, 0, 0}, + {0x7749, 0x78, 0, 0}, + {0x774a, 0x00, 0, 0}, + {0x774b, 0x01, 0, 0}, + {0x774c, 0x05, 0, 0}, + {0x774d, 0x7c, 0, 0}, + {0x774e, 0x03, 0, 0}, + {0x774f, 0x92, 0, 0}, + {0x7750, 0x05, 0, 0}, + {0x7751, 0x83, 0, 0}, + {0x7752, 0x05, 0, 0}, + {0x7753, 0x03, 0, 0}, + {0x7754, 0x00, 0, 0}, + {0x7755, 0x00, 0, 0}, + {0x7756, 0x05, 0, 0}, + {0x7757, 0x32, 0, 0}, + {0x7758, 0x05, 0, 0}, + {0x7759, 0x30, 0, 0}, + {0x775a, 0x00, 0, 0}, + {0x775b, 0x02, 0, 0}, + {0x775c, 0x05, 0, 0}, + {0x775d, 0x78, 0, 0}, + {0x775e, 0x00, 0, 0}, + {0x775f, 0x01, 0, 0}, + {0x7760, 0x05, 0, 0}, + {0x7761, 0x7c, 0, 0}, + {0x7762, 0x03, 0, 0}, + {0x7763, 0x91, 0, 0}, + {0x7764, 0x05, 0, 0}, + {0x7765, 0x83, 0, 0}, + {0x7766, 0x05, 0, 0}, + {0x7767, 0x03, 0, 0}, + {0x7768, 0x05, 0, 0}, + {0x7769, 0x32, 0, 0}, + {0x776a, 0x05, 0, 0}, + {0x776b, 0x30, 0, 0}, + {0x776c, 0x00, 0, 0}, + {0x776d, 0x02, 0, 0}, + {0x776e, 0x05, 0, 0}, + {0x776f, 0x78, 0, 0}, + {0x7770, 0x00, 0, 0}, + {0x7771, 0x01, 0, 0}, + {0x7772, 0x05, 0, 0}, + {0x7773, 0x7c, 0, 0}, + {0x7774, 0x03, 0, 0}, + {0x7775, 0x90, 0, 0}, + {0x7776, 0x05, 0, 0}, + {0x7777, 0x83, 0, 0}, + {0x7778, 0x05, 0, 0}, + {0x7779, 0x03, 0, 0}, + {0x777a, 0x05, 0, 0}, + {0x777b, 0x32, 0, 0}, + {0x777c, 0x05, 0, 0}, + {0x777d, 0x30, 0, 0}, + {0x777e, 0x00, 0, 0}, + {0x777f, 0x02, 0, 0}, + {0x7780, 0x05, 0, 0}, + {0x7781, 0x78, 0, 0}, + {0x7782, 0x00, 0, 0}, + {0x7783, 0x01, 0, 0}, + {0x7784, 0x05, 0, 0}, + {0x7785, 0x7c, 0, 0}, + {0x7786, 0x02, 0, 0}, + {0x7787, 0x90, 0, 0}, + {0x7788, 0x05, 0, 0}, + {0x7789, 0x03, 0, 0}, + {0x778a, 0x07, 0, 0}, + {0x778b, 0x00, 0, 0}, + {0x778c, 0x0f, 0, 0}, + {0x778d, 0x00, 0, 0}, + {0x778e, 0x08, 0, 0}, + {0x778f, 0x30, 0, 0}, + {0x7790, 0x08, 0, 0}, + {0x7791, 0xee, 0, 0}, + {0x7792, 0x0f, 0, 0}, + {0x7793, 0x00, 0, 0}, + {0x7794, 0x05, 0, 0}, + {0x7795, 0x33, 0, 0}, + {0x7796, 0x04, 0, 0}, + {0x7797, 0xe5, 0, 0}, + {0x7798, 0x06, 0, 0}, + {0x7799, 0x52, 0, 0}, + {0x779a, 0x04, 0, 0}, + {0x779b, 0xe4, 0, 0}, + {0x779c, 0x00, 0, 0}, + {0x779d, 0x00, 0, 0}, + {0x779e, 0x06, 0, 0}, + {0x779f, 0x5e, 0, 0}, + {0x77a0, 0x00, 0, 0}, + {0x77a1, 0x0f, 0, 0}, + {0x77a2, 0x06, 0, 0}, + {0x77a3, 0x1e, 0, 0}, + {0x77a4, 0x00, 0, 0}, + {0x77a5, 0x02, 0, 0}, + {0x77a6, 0x06, 0, 0}, + {0x77a7, 0xa2, 0, 0}, + {0x77a8, 0x00, 0, 0}, + {0x77a9, 0x01, 0, 0}, + {0x77aa, 0x06, 0, 0}, + {0x77ab, 0xae, 0, 0}, + {0x77ac, 0x00, 0, 0}, + {0x77ad, 0x03, 0, 0}, + {0x77ae, 0x05, 0, 0}, + {0x77af, 0x30, 0, 0}, + {0x77b0, 0x09, 0, 0}, + {0x77b1, 0x19, 0, 0}, + {0x77b2, 0x0f, 0, 0}, + {0x77b3, 0x00, 0, 0}, + {0x77b4, 0x05, 0, 0}, + {0x77b5, 0x33, 0, 0}, + {0x77b6, 0x04, 0, 0}, + {0x77b7, 0xe5, 0, 0}, + {0x77b8, 0x06, 0, 0}, + {0x77b9, 0x52, 0, 0}, + {0x77ba, 0x04, 0, 0}, + {0x77bb, 0xe4, 0, 0}, + {0x77bc, 0x00, 0, 0}, + {0x77bd, 0x00, 0, 0}, + {0x77be, 0x06, 0, 0}, + {0x77bf, 0x5e, 0, 0}, + {0x77c0, 0x00, 0, 0}, + {0x77c1, 0x0f, 0, 0}, + {0x77c2, 0x06, 0, 0}, + {0x77c3, 0x1e, 0, 0}, + {0x77c4, 0x00, 0, 0}, + {0x77c5, 0x02, 0, 0}, + {0x77c6, 0x06, 0, 0}, + {0x77c7, 0xa2, 0, 0}, + {0x77c8, 0x00, 0, 0}, + {0x77c9, 0x01, 0, 0}, + {0x77ca, 0x06, 0, 0}, + {0x77cb, 0xae, 0, 0}, + {0x77cc, 0x00, 0, 0}, + {0x77cd, 0x03, 0, 0}, + {0x77ce, 0x05, 0, 0}, + {0x77cf, 0x30, 0, 0}, + {0x77d0, 0x0f, 0, 0}, + {0x77d1, 0x00, 0, 0}, + {0x77d2, 0x00, 0, 0}, + {0x77d3, 0x00, 0, 0}, + {0x77d4, 0x00, 0, 0}, + {0x77d5, 0x02, 0, 0}, + {0x77d6, 0x04, 0, 0}, + {0x77d7, 0xe5, 0, 0}, + {0x77d8, 0x04, 0, 0}, + {0x77d9, 0xe4, 0, 0}, + {0x77da, 0x05, 0, 0}, + {0x77db, 0x33, 0, 0}, + {0x77dc, 0x07, 0, 0}, + {0x77dd, 0x10, 0, 0}, + {0x77de, 0x00, 0, 0}, + {0x77df, 0x00, 0, 0}, + {0x77e0, 0x01, 0, 0}, + {0x77e1, 0xbb, 0, 0}, + {0x77e2, 0x00, 0, 0}, + {0x77e3, 0x00, 0, 0}, + {0x77e4, 0x01, 0, 0}, + {0x77e5, 0xaa, 0, 0}, + {0x77e6, 0x00, 0, 0}, + {0x77e7, 0x00, 0, 0}, + {0x77e8, 0x01, 0, 0}, + {0x77e9, 0x99, 0, 0}, + {0x77ea, 0x00, 0, 0}, + {0x77eb, 0x00, 0, 0}, + {0x77ec, 0x01, 0, 0}, + {0x77ed, 0x88, 0, 0}, + {0x77ee, 0x00, 0, 0}, + {0x77ef, 0x00, 0, 0}, + {0x77f0, 0x01, 0, 0}, + {0x77f1, 0x77, 0, 0}, + {0x77f2, 0x00, 0, 0}, + {0x77f3, 0x00, 0, 0}, + {0x77f4, 0x01, 0, 0}, + {0x77f5, 0x66, 0, 0}, + {0x77f6, 0x00, 0, 0}, + {0x77f7, 0x00, 0, 0}, + {0x77f8, 0x01, 0, 0}, + {0x77f9, 0x55, 0, 0}, + {0x77fa, 0x00, 0, 0}, + {0x77fb, 0x00, 0, 0}, + {0x77fc, 0x01, 0, 0}, + {0x77fd, 0x44, 0, 0}, + {0x77fe, 0x00, 0, 0}, + {0x77ff, 0x00, 0, 0}, + {0x7800, 0x01, 0, 0}, + {0x7801, 0x33, 0, 0}, + {0x7802, 0x00, 0, 0}, + {0x7803, 0x00, 0, 0}, + {0x7804, 0x01, 0, 0}, + {0x7805, 0x22, 0, 0}, + {0x7806, 0x00, 0, 0}, + {0x7807, 0x00, 0, 0}, + {0x7808, 0x01, 0, 0}, + {0x7809, 0x11, 0, 0}, + {0x780a, 0x00, 0, 0}, + {0x780b, 0x00, 0, 0}, + {0x780c, 0x01, 0, 0}, + {0x780d, 0x00, 0, 0}, + {0x780e, 0x01, 0, 0}, + {0x780f, 0xff, 0, 0}, + {0x7810, 0x07, 0, 0}, + {0x7811, 0x00, 0, 0}, + {0x7812, 0x02, 0, 0}, + {0x7813, 0xa0, 0, 0}, + {0x7814, 0x0f, 0, 0}, + {0x7815, 0x00, 0, 0}, + {0x7816, 0x08, 0, 0}, + {0x7817, 0x35, 0, 0}, + {0x7818, 0x06, 0, 0}, + {0x7819, 0x52, 0, 0}, + {0x781a, 0x04, 0, 0}, + {0x781b, 0xe4, 0, 0}, + {0x781c, 0x00, 0, 0}, + {0x781d, 0x00, 0, 0}, + {0x781e, 0x06, 0, 0}, + {0x781f, 0x5e, 0, 0}, + {0x7820, 0x05, 0, 0}, + {0x7821, 0x33, 0, 0}, + {0x7822, 0x09, 0, 0}, + {0x7823, 0x19, 0, 0}, + {0x7824, 0x06, 0, 0}, + {0x7825, 0x1e, 0, 0}, + {0x7826, 0x05, 0, 0}, + {0x7827, 0x33, 0, 0}, + {0x7828, 0x00, 0, 0}, + {0x7829, 0x01, 0, 0}, + {0x782a, 0x06, 0, 0}, + {0x782b, 0x24, 0, 0}, + {0x782c, 0x06, 0, 0}, + {0x782d, 0x20, 0, 0}, + {0x782e, 0x0f, 0, 0}, + {0x782f, 0x00, 0, 0}, + {0x7830, 0x08, 0, 0}, + {0x7831, 0x35, 0, 0}, + {0x7832, 0x07, 0, 0}, + {0x7833, 0x10, 0, 0}, + {0x7834, 0x00, 0, 0}, + {0x7835, 0x00, 0, 0}, + {0x7836, 0x01, 0, 0}, + {0x7837, 0xbb, 0, 0}, + {0x7838, 0x00, 0, 0}, + {0x7839, 0x00, 0, 0}, + {0x783a, 0x01, 0, 0}, + {0x783b, 0xaa, 0, 0}, + {0x783c, 0x00, 0, 0}, + {0x783d, 0x00, 0, 0}, + {0x783e, 0x01, 0, 0}, + {0x783f, 0x99, 0, 0}, + {0x7840, 0x00, 0, 0}, + {0x7841, 0x00, 0, 0}, + {0x7842, 0x01, 0, 0}, + {0x7843, 0x88, 0, 0}, + {0x7844, 0x00, 0, 0}, + {0x7845, 0x00, 0, 0}, + {0x7846, 0x01, 0, 0}, + {0x7847, 0x77, 0, 0}, + {0x7848, 0x00, 0, 0}, + {0x7849, 0x00, 0, 0}, + {0x784a, 0x01, 0, 0}, + {0x784b, 0x66, 0, 0}, + {0x784c, 0x00, 0, 0}, + {0x784d, 0x00, 0, 0}, + {0x784e, 0x01, 0, 0}, + {0x784f, 0x55, 0, 0}, + {0x7850, 0x00, 0, 0}, + {0x7851, 0x00, 0, 0}, + {0x7852, 0x01, 0, 0}, + {0x7853, 0x44, 0, 0}, + {0x7854, 0x00, 0, 0}, + {0x7855, 0x00, 0, 0}, + {0x7856, 0x01, 0, 0}, + {0x7857, 0x33, 0, 0}, + {0x7858, 0x00, 0, 0}, + {0x7859, 0x00, 0, 0}, + {0x785a, 0x01, 0, 0}, + {0x785b, 0x22, 0, 0}, + {0x785c, 0x00, 0, 0}, + {0x785d, 0x00, 0, 0}, + {0x785e, 0x01, 0, 0}, + {0x785f, 0x11, 0, 0}, + {0x7860, 0x00, 0, 0}, + {0x7861, 0x00, 0, 0}, + {0x7862, 0x01, 0, 0}, + {0x7863, 0x00, 0, 0}, + {0x7864, 0x07, 0, 0}, + {0x7865, 0x00, 0, 0}, + {0x7866, 0x01, 0, 0}, + {0x7867, 0xff, 0, 0}, + {0x7868, 0x02, 0, 0}, + {0x7869, 0xa0, 0, 0}, + {0x786a, 0x0f, 0, 0}, + {0x786b, 0x00, 0, 0}, + {0x786c, 0x08, 0, 0}, + {0x786d, 0x3a, 0, 0}, + {0x786e, 0x08, 0, 0}, + {0x786f, 0x6a, 0, 0}, + {0x7870, 0x0f, 0, 0}, + {0x7871, 0x00, 0, 0}, + {0x7872, 0x04, 0, 0}, + {0x7873, 0xc0, 0, 0}, + {0x7874, 0x09, 0, 0}, + {0x7875, 0x19, 0, 0}, + {0x7876, 0x04, 0, 0}, + {0x7877, 0x99, 0, 0}, + {0x7878, 0x07, 0, 0}, + {0x7879, 0x14, 0, 0}, + {0x787a, 0x00, 0, 0}, + {0x787b, 0x01, 0, 0}, + {0x787c, 0x04, 0, 0}, + {0x787d, 0xa4, 0, 0}, + {0x787e, 0x00, 0, 0}, + {0x787f, 0x07, 0, 0}, + {0x7880, 0x04, 0, 0}, + {0x7881, 0xa6, 0, 0}, + {0x7882, 0x00, 0, 0}, + {0x7883, 0x00, 0, 0}, + {0x7884, 0x04, 0, 0}, + {0x7885, 0xa0, 0, 0}, + {0x7886, 0x04, 0, 0}, + {0x7887, 0x80, 0, 0}, + {0x7888, 0x04, 0, 0}, + {0x7889, 0x00, 0, 0}, + {0x788a, 0x05, 0, 0}, + {0x788b, 0x03, 0, 0}, + {0x788c, 0x06, 0, 0}, + {0x788d, 0x00, 0, 0}, + {0x788e, 0x0f, 0, 0}, + {0x788f, 0x00, 0, 0}, + {0x7890, 0x0f, 0, 0}, + {0x7891, 0x00, 0, 0}, + {0x7892, 0x0f, 0, 0}, + {0x7893, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x05, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x04, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x80, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x38, 0, 0}, + {0x30b0, 0x0c, 0, 0},//dde + {0x30b1, 0x1c, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x66, 0, 0}, + {0x30b6, 0x01, 0, 0}, + {0x30b7, 0x22, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x20, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x0a, 0, 0}, + {0x3195, 0x2e, 0, 0}, + {0x30bb, 0x14, 0, 0}, + {0x315a, 0x02, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x80, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x80, 0, 0}, + {0x3250, 0xf7, 0, 0}, + {0x3012, 0x00, 0, 0}, + + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x08, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x08, 0, 0}, + + {0x30c0, 0x08, 0, 0}, + {0x3252, 0x20, 0, 0}, +}; + +#endif diff --git a/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p_native_hdr.h b/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p_native_hdr.h new file mode 100755 index 0000000..1081681 --- /dev/null +++ b/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_1080p_native_hdr.h @@ -0,0 +1,1915 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OV2775_REGS_1080P_NATIVE_HDR_H_ +#define _VVCAM_OV2775_REGS_1080P_NATIVE_HDR_H_ + +#include "vvsensor.h" + +/* 1080P RAW12 */ +static struct vvsensor_reg_value_t ov2775_1080p_native_hdr_regs[] = { + {0x3000, 0x02, 0, 0}, + {0x3001, 0x28, 0, 0}, + {0x3002, 0x03, 0, 0}, + {0x3003, 0x01, 0, 0}, + {0x3004, 0x02, 0, 0}, + {0x3005, 0x20, 0, 0},//816Mbps //{0x3005, 0x26, 0, 0},//960Mbps + {0x3006, 0x00, 0, 0}, + {0x3007, 0x07, 0, 0},//102MHz + {0x3008, 0x01, 0, 0}, + {0x3009, 0x00, 0, 0}, + {0x300c, 0x6c, 0, 0}, + {0x300e, 0x80, 0, 0}, + {0x300f, 0x00, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3013, 0x00, 0, 0}, + {0x3014, 0xc4, 0, 0}, + {0x3015, 0x00, 0, 0}, + {0x3017, 0x00, 0, 0}, + {0x3018, 0x00, 0, 0}, + {0x3019, 0x00, 0, 0}, + {0x301a, 0x00, 0, 0}, + {0x301b, 0x0e, 0, 0}, + {0x301e, 0x17, 0, 0}, + {0x301f, 0xe1, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x3031, 0x62, 0, 0}, + {0x3032, 0xf0, 0, 0}, + {0x3033, 0x30, 0, 0}, + {0x3034, 0x3f, 0, 0}, + {0x3035, 0x5f, 0, 0}, + {0x3036, 0x02, 0, 0}, + {0x3037, 0x9f, 0, 0}, + {0x3038, 0x04, 0, 0}, + {0x3039, 0xb7, 0, 0}, + {0x303a, 0x04, 0, 0}, + {0x303b, 0x07, 0, 0}, + {0x303c, 0xf0, 0, 0}, + {0x303d, 0x00, 0, 0}, + {0x303e, 0x0b, 0, 0}, + {0x303f, 0xe3, 0, 0}, + {0x3040, 0xf3, 0, 0}, + {0x3041, 0x29, 0, 0}, + {0x3042, 0xf6, 0, 0}, + {0x3043, 0x65, 0, 0}, + {0x3044, 0x06, 0, 0}, + {0x3045, 0x0f, 0, 0}, + {0x3046, 0x59, 0, 0}, + {0x3047, 0x07, 0, 0}, + {0x3048, 0x82, 0, 0}, + {0x3049, 0xcf, 0, 0}, + {0x304a, 0x12, 0, 0}, + {0x304b, 0x40, 0, 0}, + {0x304c, 0x33, 0, 0}, + {0x304d, 0xa4, 0, 0}, + {0x304e, 0x0b, 0, 0}, + {0x304f, 0x3d, 0, 0}, + {0x3050, 0x10, 0, 0}, + {0x3060, 0x00, 0, 0}, + {0x3061, 0x64, 0, 0}, + {0x3062, 0x00, 0, 0}, + {0x3063, 0xe4, 0, 0}, + {0x3066, 0x80, 0, 0}, + {0x3080, 0x00, 0, 0}, + {0x3081, 0x00, 0, 0}, + {0x3082, 0x01, 0, 0}, + {0x3083, 0xe3, 0, 0}, + {0x3084, 0x06, 0, 0}, + {0x3085, 0x00, 0, 0}, + {0x3086, 0x10, 0, 0}, + {0x3087, 0x10, 0, 0}, + {0x3089, 0x00, 0, 0}, + {0x308a, 0x01, 0, 0}, + {0x3093, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x00, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x00, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x90, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x48, 0, 0}, + {0x30b0, 0x08, 0, 0}, + {0x30b1, 0xae, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x65, 0, 0}, + {0x30b4, 0x00, 0, 0}, + {0x30b5, 0x00, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x10, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x02, 0, 0}, + {0x30ba, 0x10, 0, 0}, + {0x30bb, 0x00, 0, 0}, + {0x30bc, 0x00, 0, 0}, + {0x30bd, 0x03, 0, 0}, + {0x30be, 0x5c, 0, 0}, + {0x30bf, 0x00, 0, 0}, + {0x30c0, 0x05, 0, 0}, + {0x30c1, 0x00, 0, 0}, + {0x30c2, 0x20, 0, 0}, + {0x30c3, 0x00, 0, 0}, + {0x30c4, 0x4a, 0, 0}, + {0x30c5, 0x00, 0, 0}, + {0x30c7, 0x00, 0, 0}, + {0x30c8, 0x00, 0, 0}, + {0x30d1, 0x00, 0, 0}, + {0x30d2, 0x00, 0, 0}, + {0x30d3, 0x80, 0, 0}, + {0x30d4, 0x00, 0, 0}, + {0x30d9, 0x09, 0, 0}, + {0x30da, 0x64, 0, 0}, + {0x30dd, 0x00, 0, 0}, + {0x30de, 0x16, 0, 0}, + {0x30df, 0x00, 0, 0}, + {0x30e0, 0x17, 0, 0}, + {0x30e1, 0x00, 0, 0}, + {0x30e2, 0x18, 0, 0}, + {0x30e3, 0x10, 0, 0}, + {0x30e4, 0x04, 0, 0}, + {0x30e5, 0x00, 0, 0}, + {0x30e6, 0x00, 0, 0}, + {0x30e7, 0x00, 0, 0}, + {0x30e8, 0x00, 0, 0}, + {0x30e9, 0x00, 0, 0}, + {0x30ea, 0x00, 0, 0}, + {0x30eb, 0x00, 0, 0}, + {0x30ec, 0x00, 0, 0}, + {0x30ed, 0x00, 0, 0}, + {0x3101, 0x00, 0, 0}, + {0x3102, 0x00, 0, 0}, + {0x3103, 0x00, 0, 0}, + {0x3104, 0x00, 0, 0}, + {0x3105, 0x8c, 0, 0}, + {0x3106, 0x87, 0, 0}, + {0x3107, 0xc0, 0, 0}, + {0x3108, 0x9d, 0, 0}, + {0x3109, 0x8d, 0, 0}, + {0x310a, 0x8d, 0, 0}, + {0x310b, 0x6a, 0, 0}, + {0x310c, 0x3a, 0, 0}, + {0x310d, 0x5a, 0, 0}, + {0x310e, 0x00, 0, 0}, + {0x3120, 0x00, 0, 0}, + {0x3121, 0x00, 0, 0}, + {0x3122, 0x00, 0, 0}, + {0x3123, 0x00, 0, 0}, + {0x3124, 0x00, 0, 0}, + {0x3125, 0x70, 0, 0}, + {0x3126, 0x1f, 0, 0}, + {0x3127, 0x0f, 0, 0}, + {0x3128, 0x00, 0, 0}, + {0x3129, 0x3a, 0, 0}, + {0x312a, 0x02, 0, 0}, + {0x312b, 0x0f, 0, 0}, + {0x312c, 0x00, 0, 0}, + {0x312d, 0x0f, 0, 0}, + {0x312e, 0x1d, 0, 0}, + {0x312f, 0x00, 0, 0}, + {0x3130, 0x00, 0, 0}, + {0x3131, 0x00, 0, 0}, + {0x3132, 0x00, 0, 0}, + {0x3140, 0x0a, 0, 0}, + {0x3141, 0x03, 0, 0}, + {0x3142, 0x00, 0, 0}, + {0x3143, 0x00, 0, 0}, + {0x3144, 0x00, 0, 0}, + {0x3145, 0x00, 0, 0}, + {0x3146, 0x00, 0, 0}, + {0x3147, 0x00, 0, 0}, + {0x3148, 0x00, 0, 0}, + {0x3149, 0x00, 0, 0}, + {0x314a, 0x00, 0, 0}, + {0x314b, 0x00, 0, 0}, + {0x314c, 0x00, 0, 0}, + {0x314d, 0x00, 0, 0}, + {0x314e, 0x1c, 0, 0}, + {0x314f, 0xff, 0, 0}, + {0x3150, 0xff, 0, 0}, + {0x3151, 0xff, 0, 0}, + {0x3152, 0x10, 0, 0}, + {0x3153, 0x10, 0, 0}, + {0x3154, 0x10, 0, 0}, + {0x3155, 0x00, 0, 0}, + {0x3156, 0x03, 0, 0}, + {0x3157, 0x00, 0, 0}, + {0x3158, 0x0f, 0, 0}, + {0x3159, 0xff, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x00, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x00, 0, 0}, + {0x3160, 0x00, 0, 0}, + {0x3161, 0x40, 0, 0}, + {0x3162, 0x00, 0, 0}, + {0x3163, 0x40, 0, 0}, + {0x3164, 0x00, 0, 0}, + {0x3165, 0x40, 0, 0}, + {0x3190, 0x02, 0, 0}, + {0x3191, 0x99, 0, 0}, + {0x3193, 0x08, 0, 0}, + {0x3194, 0x13, 0, 0}, + {0x3195, 0x33, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x10, 0, 0}, + {0x3198, 0x00, 0, 0}, + {0x3199, 0x7f, 0, 0}, + {0x319a, 0x00, 0, 0}, + {0x319b, 0x00, 0, 0}, + {0x319c, 0x80, 0, 0}, + {0x319d, 0xbf, 0, 0}, + {0x319e, 0xc0, 0, 0}, + {0x319f, 0xff, 0, 0}, + {0x31a0, 0x24, 0, 0}, + {0x31a1, 0x55, 0, 0}, + {0x31a2, 0x00, 0, 0}, + {0x31a3, 0x00, 0, 0}, + {0x31a6, 0x00, 0, 0}, + {0x31a7, 0x00, 0, 0}, + {0x31b0, 0x00, 0, 0}, + {0x31b1, 0x00, 0, 0}, + {0x31b2, 0x02, 0, 0}, + {0x31b3, 0x00, 0, 0}, + {0x31b4, 0x00, 0, 0}, + {0x31b5, 0x01, 0, 0}, + {0x31b6, 0x00, 0, 0}, + {0x31b7, 0x00, 0, 0}, + {0x31b8, 0x00, 0, 0}, + {0x31b9, 0x00, 0, 0}, + {0x31ba, 0x00, 0, 0}, + {0x31d0, 0x3c, 0, 0}, + {0x31d1, 0x34, 0, 0}, + {0x31d2, 0x3c, 0, 0}, + {0x31d3, 0x00, 0, 0}, + {0x31d4, 0x2d, 0, 0}, + {0x31d5, 0x00, 0, 0}, + {0x31d6, 0x01, 0, 0}, + {0x31d7, 0x06, 0, 0}, + {0x31d8, 0x00, 0, 0}, + {0x31d9, 0x64, 0, 0}, + {0x31da, 0x00, 0, 0}, + {0x31db, 0x30, 0, 0}, + {0x31dc, 0x04, 0, 0}, + {0x31dd, 0x69, 0, 0}, + {0x31de, 0x0a, 0, 0}, + {0x31df, 0x3c, 0, 0}, + {0x31e0, 0x04, 0, 0}, + {0x31e1, 0x32, 0, 0}, + {0x31e2, 0x00, 0, 0}, + {0x31e3, 0x00, 0, 0}, + {0x31e4, 0x08, 0, 0}, + {0x31e5, 0x80, 0, 0}, + {0x31e6, 0x00, 0, 0}, + {0x31e7, 0x2c, 0, 0}, + {0x31e8, 0x6c, 0, 0}, + {0x31e9, 0xac, 0, 0}, + {0x31ea, 0xec, 0, 0}, + {0x31eb, 0x3f, 0, 0}, + {0x31ec, 0x07, 0, 0}, + {0x31ed, 0x80, 0, 0}, + {0x31ee, 0x04, 0, 0}, + {0x31ef, 0x38, 0, 0}, + {0x31f0, 0x07, 0, 0}, + {0x31f1, 0x80, 0, 0}, + {0x31f2, 0x04, 0, 0}, + {0x31f3, 0x38, 0, 0}, + {0x31f4, 0x07, 0, 0}, + {0x31f5, 0x80, 0, 0}, + {0x31f6, 0x04, 0, 0}, + {0x31f7, 0x38, 0, 0}, + {0x31f8, 0x07, 0, 0}, + {0x31f9, 0x80, 0, 0}, + {0x31fa, 0x04, 0, 0}, + {0x31fb, 0x38, 0, 0}, + {0x31fd, 0xcb, 0, 0}, + {0x31fe, 0x0f, 0, 0}, + {0x31ff, 0x03, 0, 0}, + {0x3200, 0x00, 0, 0}, + {0x3201, 0xff, 0, 0}, + {0x3202, 0x00, 0, 0}, + {0x3203, 0xff, 0, 0}, + {0x3204, 0xff, 0, 0}, + {0x3205, 0xff, 0, 0}, + {0x3206, 0xff, 0, 0}, + {0x3207, 0xff, 0, 0}, + {0x3208, 0xff, 0, 0}, + {0x3209, 0xff, 0, 0}, + {0x320a, 0xff, 0, 0}, + {0x320b, 0x1b, 0, 0}, + {0x320c, 0x1f, 0, 0}, + {0x320d, 0x1e, 0, 0}, + {0x320e, 0x30, 0, 0}, + {0x320f, 0x2d, 0, 0}, + {0x3210, 0x2c, 0, 0}, + {0x3211, 0x2b, 0, 0}, + {0x3212, 0x2a, 0, 0}, + {0x3213, 0x24, 0, 0}, + {0x3214, 0x22, 0, 0}, + {0x3215, 0x00, 0, 0}, + {0x3216, 0x04, 0, 0}, + {0x3217, 0x2c, 0, 0}, + {0x3218, 0x6c, 0, 0}, + {0x3219, 0xac, 0, 0}, + {0x321a, 0xec, 0, 0}, + {0x321b, 0x00, 0, 0}, + {0x3230, 0x3a, 0, 0}, + {0x3231, 0x00, 0, 0}, + {0x3232, 0x80, 0, 0}, + {0x3233, 0x00, 0, 0}, + {0x3234, 0x10, 0, 0}, + {0x3235, 0xaa, 0, 0}, + {0x3236, 0x55, 0, 0}, + {0x3237, 0x99, 0, 0}, + {0x3238, 0x66, 0, 0}, + {0x3239, 0x08, 0, 0}, + {0x323a, 0x88, 0, 0}, + {0x323b, 0x00, 0, 0}, + {0x323c, 0x00, 0, 0}, + {0x323d, 0x03, 0, 0}, + {0x3250, 0x33, 0, 0}, + {0x3251, 0x00, 0, 0}, + {0x3252, 0x20, 0, 0}, + {0x3253, 0x00, 0, 0}, + {0x3254, 0x11, 0, 0}, + {0x3255, 0x01, 0, 0}, + {0x3256, 0x00, 0, 0}, + {0x3257, 0x00, 0, 0}, + {0x3258, 0x00, 0, 0}, + {0x3270, 0x01, 0, 0}, + {0x3271, 0x60, 0, 0}, + {0x3272, 0xc0, 0, 0}, + {0x3273, 0x00, 0, 0}, + {0x3274, 0x80, 0, 0}, + {0x3275, 0x40, 0, 0}, + {0x3276, 0x02, 0, 0}, + {0x3277, 0x08, 0, 0}, + {0x3278, 0x10, 0, 0}, + {0x3279, 0x04, 0, 0}, + {0x327a, 0x00, 0, 0}, + {0x327b, 0x03, 0, 0}, + {0x327c, 0x10, 0, 0}, + {0x327d, 0x60, 0, 0}, + {0x327e, 0xc0, 0, 0}, + {0x327f, 0x06, 0, 0}, + {0x3288, 0x10, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x08, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x04, 0, 0}, + {0x328d, 0x00, 0, 0}, + {0x328e, 0x02, 0, 0}, + {0x328f, 0x00, 0, 0}, + {0x3290, 0x20, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x10, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x08, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x04, 0, 0}, + {0x3297, 0x00, 0, 0}, + {0x3298, 0x40, 0, 0}, + {0x3299, 0x00, 0, 0}, + {0x329a, 0x20, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x10, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x08, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x40, 0, 0}, + {0x32a3, 0x00, 0, 0}, + {0x32a4, 0x20, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x10, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32a8, 0x00, 0, 0}, + {0x32a9, 0x00, 0, 0}, + {0x32aa, 0x00, 0, 0}, + {0x32ab, 0x00, 0, 0}, + {0x32ac, 0x00, 0, 0}, + {0x32ad, 0x00, 0, 0}, + {0x32ae, 0x00, 0, 0}, + {0x32af, 0x00, 0, 0}, + {0x32b0, 0x00, 0, 0}, + {0x32b1, 0x00, 0, 0}, + {0x32b2, 0x00, 0, 0}, + {0x32b3, 0x00, 0, 0}, + {0x32b4, 0x00, 0, 0}, + {0x32b5, 0x00, 0, 0}, + {0x32b6, 0x00, 0, 0}, + {0x32b7, 0x00, 0, 0}, + {0x32b8, 0x00, 0, 0}, + {0x32b9, 0x00, 0, 0}, + {0x32ba, 0x00, 0, 0}, + {0x32bb, 0x00, 0, 0}, + {0x32bc, 0x00, 0, 0}, + {0x32bd, 0x00, 0, 0}, + {0x32be, 0x00, 0, 0}, + {0x32bf, 0x00, 0, 0}, + {0x32c0, 0x00, 0, 0}, + {0x32c1, 0x00, 0, 0}, + {0x32c2, 0x00, 0, 0}, + {0x32c3, 0x00, 0, 0}, + {0x32c4, 0x00, 0, 0}, + {0x32c5, 0x00, 0, 0}, + {0x32c6, 0x00, 0, 0}, + {0x32c7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x32c9, 0x00, 0, 0}, + {0x3330, 0x03, 0, 0}, + {0x3331, 0xc8, 0, 0}, + {0x3332, 0x02, 0, 0}, + {0x3333, 0x24, 0, 0}, + {0x3334, 0x00, 0, 0}, + {0x3335, 0x00, 0, 0}, + {0x3336, 0x00, 0, 0}, + {0x3337, 0x00, 0, 0}, + {0x3338, 0x03, 0, 0}, + {0x3339, 0xc8, 0, 0}, + {0x333a, 0x02, 0, 0}, + {0x333b, 0x24, 0, 0}, + {0x333c, 0x00, 0, 0}, + {0x333d, 0x00, 0, 0}, + {0x333e, 0x00, 0, 0}, + {0x333f, 0x00, 0, 0}, + {0x3340, 0x03, 0, 0}, + {0x3341, 0xc8, 0, 0}, + {0x3342, 0x02, 0, 0}, + {0x3343, 0x24, 0, 0}, + {0x3344, 0x00, 0, 0}, + {0x3345, 0x00, 0, 0}, + {0x3346, 0x00, 0, 0}, + {0x3347, 0x00, 0, 0}, + {0x3348, 0x40, 0, 0}, + {0x3349, 0x00, 0, 0}, + {0x334a, 0x00, 0, 0}, + {0x334b, 0x00, 0, 0}, + {0x334c, 0x00, 0, 0}, + {0x334d, 0x00, 0, 0}, + {0x334e, 0x80, 0, 0}, + {0x3360, 0x01, 0, 0}, + {0x3361, 0xf9, 0, 0}, + {0x3362, 0x01, 0, 0}, + {0x3363, 0x04, 0, 0}, + {0x3364, 0x01, 0, 0}, + {0x3365, 0x04, 0, 0}, + {0x3366, 0x02, 0, 0}, + {0x3367, 0x3e, 0, 0}, + {0x3368, 0x01, 0, 0}, + {0x3369, 0xf9, 0, 0}, + {0x336a, 0x01, 0, 0}, + {0x336b, 0x04, 0, 0}, + {0x336c, 0x01, 0, 0}, + {0x336d, 0x04, 0, 0}, + {0x336e, 0x02, 0, 0}, + {0x336f, 0x3e, 0, 0}, + {0x3370, 0x01, 0, 0}, + {0x3371, 0xf9, 0, 0}, + {0x3372, 0x01, 0, 0}, + {0x3373, 0x04, 0, 0}, + {0x3374, 0x01, 0, 0}, + {0x3375, 0x04, 0, 0}, + {0x3376, 0x02, 0, 0}, + {0x3377, 0x3e, 0, 0}, + {0x3378, 0x00, 0, 0}, + {0x3379, 0x3e, 0, 0}, + {0x337a, 0x54, 0, 0}, + {0x337b, 0x00, 0, 0}, + {0x337c, 0x01, 0, 0}, + {0x337d, 0x00, 0, 0}, + {0x337e, 0x00, 0, 0}, + {0x337f, 0x01, 0, 0}, + {0x3380, 0x00, 0, 0}, + {0x3381, 0x00, 0, 0}, + {0x3382, 0x4f, 0, 0}, + {0x3383, 0x80, 0, 0}, + {0x3384, 0x00, 0, 0}, + {0x3385, 0x3e, 0, 0}, + {0x3386, 0x54, 0, 0}, + {0x3387, 0x00, 0, 0}, + {0x3388, 0x01, 0, 0}, + {0x3389, 0x00, 0, 0}, + {0x338a, 0x00, 0, 0}, + {0x338b, 0x01, 0, 0}, + {0x338c, 0x00, 0, 0}, + {0x338d, 0x00, 0, 0}, + {0x338e, 0x4f, 0, 0}, + {0x338f, 0x80, 0, 0}, + {0x3390, 0x00, 0, 0}, + {0x3391, 0x3e, 0, 0}, + {0x3392, 0x54, 0, 0}, + {0x3393, 0x00, 0, 0}, + {0x3394, 0x01, 0, 0}, + {0x3395, 0x00, 0, 0}, + {0x3396, 0x00, 0, 0}, + {0x3397, 0x01, 0, 0}, + {0x3398, 0x00, 0, 0}, + {0x3399, 0x00, 0, 0}, + {0x339a, 0x4f, 0, 0}, + {0x339b, 0x80, 0, 0}, + {0x33b0, 0x00, 0, 0}, + {0x33b1, 0x50, 0, 0}, + {0x33b2, 0x01, 0, 0}, + {0x33b3, 0xff, 0, 0}, + {0x33b4, 0xe0, 0, 0}, + {0x33b5, 0x6b, 0, 0}, + {0x33b6, 0x00, 0, 0}, + {0x33b7, 0x00, 0, 0}, + {0x33b8, 0x00, 0, 0}, + {0x33b9, 0x00, 0, 0}, + {0x33ba, 0x00, 0, 0}, + {0x33bb, 0x1f, 0, 0}, + {0x33bc, 0x01, 0, 0}, + {0x33bd, 0x01, 0, 0}, + {0x33be, 0x01, 0, 0}, + {0x33bf, 0x01, 0, 0}, + {0x33c0, 0x00, 0, 0}, + {0x33c1, 0x00, 0, 0}, + {0x33c2, 0x00, 0, 0}, + {0x33c3, 0x00, 0, 0}, + {0x33e0, 0x14, 0, 0}, + {0x33e1, 0x0f, 0, 0}, + {0x33e2, 0x04, 0, 0}, + {0x33e3, 0x02, 0, 0}, + {0x33e4, 0x01, 0, 0}, + {0x33e5, 0x01, 0, 0}, + {0x33e6, 0x00, 0, 0}, + {0x33e7, 0x04, 0, 0}, + {0x33e8, 0x0c, 0, 0}, + {0x33e9, 0x02, 0, 0}, + {0x33ea, 0x02, 0, 0}, + {0x33eb, 0x02, 0, 0}, + {0x33ec, 0x03, 0, 0}, + {0x33ed, 0x02, 0, 0}, + {0x33ee, 0x05, 0, 0}, + {0x33ef, 0x0a, 0, 0}, + {0x33f0, 0x08, 0, 0}, + {0x33f1, 0x04, 0, 0}, + {0x33f2, 0x04, 0, 0}, + {0x33f3, 0x00, 0, 0}, + {0x33f4, 0x03, 0, 0}, + {0x33f5, 0x14, 0, 0}, + {0x33f6, 0x0f, 0, 0}, + {0x33f7, 0x02, 0, 0}, + {0x33f8, 0x01, 0, 0}, + {0x33f9, 0x01, 0, 0}, + {0x33fa, 0x01, 0, 0}, + {0x33fb, 0x00, 0, 0}, + {0x33fc, 0x04, 0, 0}, + {0x33fd, 0x0c, 0, 0}, + {0x33fe, 0x02, 0, 0}, + {0x33ff, 0x02, 0, 0}, + {0x3400, 0x02, 0, 0}, + {0x3401, 0x03, 0, 0}, + {0x3402, 0x01, 0, 0}, + {0x3403, 0x02, 0, 0}, + {0x3404, 0x08, 0, 0}, + {0x3405, 0x08, 0, 0}, + {0x3406, 0x04, 0, 0}, + {0x3407, 0x04, 0, 0}, + {0x3408, 0x00, 0, 0}, + {0x3409, 0x03, 0, 0}, + {0x340a, 0x14, 0, 0}, + {0x340b, 0x0f, 0, 0}, + {0x340c, 0x04, 0, 0}, + {0x340d, 0x02, 0, 0}, + {0x340e, 0x01, 0, 0}, + {0x340f, 0x01, 0, 0}, + {0x3410, 0x00, 0, 0}, + {0x3411, 0x04, 0, 0}, + {0x3412, 0x0c, 0, 0}, + {0x3413, 0x02, 0, 0}, + {0x3414, 0x02, 0, 0}, + {0x3415, 0x02, 0, 0}, + {0x3416, 0x03, 0, 0}, + {0x3417, 0x02, 0, 0}, + {0x3418, 0x05, 0, 0}, + {0x3419, 0x0a, 0, 0}, + {0x341a, 0x08, 0, 0}, + {0x341b, 0x04, 0, 0}, + {0x341c, 0x04, 0, 0}, + {0x341d, 0x00, 0, 0}, + {0x341e, 0x03, 0, 0}, + {0x3440, 0x00, 0, 0}, + {0x3441, 0x00, 0, 0}, + {0x3442, 0x00, 0, 0}, + {0x3443, 0x00, 0, 0}, + {0x3444, 0x02, 0, 0}, + {0x3445, 0xf0, 0, 0}, + {0x3446, 0x02, 0, 0}, + {0x3447, 0x08, 0, 0}, + {0x3448, 0x00, 0, 0}, + {0x3460, 0x40, 0, 0}, + {0x3461, 0x40, 0, 0}, + {0x3462, 0x40, 0, 0}, + {0x3463, 0x40, 0, 0}, + {0x3464, 0x03, 0, 0}, + {0x3465, 0x01, 0, 0}, + {0x3466, 0x01, 0, 0}, + {0x3467, 0x02, 0, 0}, + {0x3468, 0x30, 0, 0}, + {0x3469, 0x00, 0, 0}, + {0x346a, 0x35, 0, 0}, + {0x346b, 0x00, 0, 0}, + {0x3480, 0x40, 0, 0}, + {0x3481, 0x00, 0, 0}, + {0x3482, 0x00, 0, 0}, + {0x3483, 0x00, 0, 0}, + {0x3484, 0x0d, 0, 0}, + {0x3485, 0x00, 0, 0}, + {0x3486, 0x00, 0, 0}, + {0x3487, 0x00, 0, 0}, + {0x3488, 0x00, 0, 0}, + {0x3489, 0x00, 0, 0}, + {0x348a, 0x00, 0, 0}, + {0x348b, 0x04, 0, 0}, + {0x348c, 0x00, 0, 0}, + {0x348d, 0x01, 0, 0}, + {0x348f, 0x01, 0, 0}, + {0x3030, 0x0a, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x7000, 0x58, 0, 0}, + {0x7001, 0x7a, 0, 0}, + {0x7002, 0x1a, 0, 0}, + {0x7003, 0xc1, 0, 0}, + {0x7004, 0x03, 0, 0}, + {0x7005, 0xda, 0, 0}, + {0x7006, 0xbd, 0, 0}, + {0x7007, 0x03, 0, 0}, + {0x7008, 0xbd, 0, 0}, + {0x7009, 0x06, 0, 0}, + {0x700a, 0xe6, 0, 0}, + {0x700b, 0xec, 0, 0}, + {0x700c, 0xbc, 0, 0}, + {0x700d, 0xff, 0, 0}, + {0x700e, 0xbc, 0, 0}, + {0x700f, 0x73, 0, 0}, + {0x7010, 0xda, 0, 0}, + {0x7011, 0x72, 0, 0}, + {0x7012, 0x76, 0, 0}, + {0x7013, 0xb6, 0, 0}, + {0x7014, 0xee, 0, 0}, + {0x7015, 0xcf, 0, 0}, + {0x7016, 0xac, 0, 0}, + {0x7017, 0xd0, 0, 0}, + {0x7018, 0xac, 0, 0}, + {0x7019, 0xd1, 0, 0}, + {0x701a, 0x50, 0, 0}, + {0x701b, 0xac, 0, 0}, + {0x701c, 0xd2, 0, 0}, + {0x701d, 0xbc, 0, 0}, + {0x701e, 0x2e, 0, 0}, + {0x701f, 0xb4, 0, 0}, + {0x7020, 0x00, 0, 0}, + {0x7021, 0xdc, 0, 0}, + {0x7022, 0xdf, 0, 0}, + {0x7023, 0xb0, 0, 0}, + {0x7024, 0x6e, 0, 0}, + {0x7025, 0xbd, 0, 0}, + {0x7026, 0x01, 0, 0}, + {0x7027, 0xd7, 0, 0}, + {0x7028, 0xed, 0, 0}, + {0x7029, 0xe1, 0, 0}, + {0x702a, 0x36, 0, 0}, + {0x702b, 0x30, 0, 0}, + {0x702c, 0xd3, 0, 0}, + {0x702d, 0x2e, 0, 0}, + {0x702e, 0x54, 0, 0}, + {0x702f, 0x46, 0, 0}, + {0x7030, 0xbc, 0, 0}, + {0x7031, 0x22, 0, 0}, + {0x7032, 0x66, 0, 0}, + {0x7033, 0xbc, 0, 0}, + {0x7034, 0x24, 0, 0}, + {0x7035, 0x2c, 0, 0}, + {0x7036, 0x28, 0, 0}, + {0x7037, 0xbc, 0, 0}, + {0x7038, 0x3c, 0, 0}, + {0x7039, 0xa1, 0, 0}, + {0x703a, 0xac, 0, 0}, + {0x703b, 0xd8, 0, 0}, + {0x703c, 0xd6, 0, 0}, + {0x703d, 0xb4, 0, 0}, + {0x703e, 0x04, 0, 0}, + {0x703f, 0x46, 0, 0}, + {0x7040, 0xb7, 0, 0}, + {0x7041, 0x04, 0, 0}, + {0x7042, 0xbe, 0, 0}, + {0x7043, 0x08, 0, 0}, + {0x7044, 0xc3, 0, 0}, + {0x7045, 0xd9, 0, 0}, + {0x7046, 0xad, 0, 0}, + {0x7047, 0xc3, 0, 0}, + {0x7048, 0xbc, 0, 0}, + {0x7049, 0x19, 0, 0}, + {0x704a, 0xc1, 0, 0}, + {0x704b, 0x27, 0, 0}, + {0x704c, 0xe7, 0, 0}, + {0x704d, 0x00, 0, 0}, + {0x704e, 0x50, 0, 0}, + {0x704f, 0x20, 0, 0}, + {0x7050, 0xb8, 0, 0}, + {0x7051, 0x02, 0, 0}, + {0x7052, 0xbc, 0, 0}, + {0x7053, 0x17, 0, 0}, + {0x7054, 0xdb, 0, 0}, + {0x7055, 0xc7, 0, 0}, + {0x7056, 0xb8, 0, 0}, + {0x7057, 0x00, 0, 0}, + {0x7058, 0x28, 0, 0}, + {0x7059, 0x54, 0, 0}, + {0x705a, 0xb4, 0, 0}, + {0x705b, 0x14, 0, 0}, + {0x705c, 0xab, 0, 0}, + {0x705d, 0xbe, 0, 0}, + {0x705e, 0x06, 0, 0}, + {0x705f, 0xd8, 0, 0}, + {0x7060, 0xd6, 0, 0}, + {0x7061, 0x00, 0, 0}, + {0x7062, 0xb4, 0, 0}, + {0x7063, 0xc7, 0, 0}, + {0x7064, 0x07, 0, 0}, + {0x7065, 0xb9, 0, 0}, + {0x7066, 0x05, 0, 0}, + {0x7067, 0xee, 0, 0}, + {0x7068, 0xe6, 0, 0}, + {0x7069, 0xad, 0, 0}, + {0x706a, 0xb4, 0, 0}, + {0x706b, 0x26, 0, 0}, + {0x706c, 0x19, 0, 0}, + {0x706d, 0xc1, 0, 0}, + {0x706e, 0x3a, 0, 0}, + {0x706f, 0xc3, 0, 0}, + {0x7070, 0xaf, 0, 0}, + {0x7071, 0x00, 0, 0}, + {0x7072, 0xc0, 0, 0}, + {0x7073, 0x3c, 0, 0}, + {0x7074, 0xc3, 0, 0}, + {0x7075, 0xbe, 0, 0}, + {0x7076, 0xe7, 0, 0}, + {0x7077, 0x00, 0, 0}, + {0x7078, 0x15, 0, 0}, + {0x7079, 0xc2, 0, 0}, + {0x707a, 0x40, 0, 0}, + {0x707b, 0xc3, 0, 0}, + {0x707c, 0xa4, 0, 0}, + {0x707d, 0xc0, 0, 0}, + {0x707e, 0x3c, 0, 0}, + {0x707f, 0x00, 0, 0}, + {0x7080, 0xb9, 0, 0}, + {0x7081, 0x64, 0, 0}, + {0x7082, 0x29, 0, 0}, + {0x7083, 0x00, 0, 0}, + {0x7084, 0xb8, 0, 0}, + {0x7085, 0x12, 0, 0}, + {0x7086, 0xbe, 0, 0}, + {0x7087, 0x01, 0, 0}, + {0x7088, 0xd0, 0, 0}, + {0x7089, 0xbc, 0, 0}, + {0x708a, 0x01, 0, 0}, + {0x708b, 0xac, 0, 0}, + {0x708c, 0x37, 0, 0}, + {0x708d, 0xd2, 0, 0}, + {0x708e, 0xac, 0, 0}, + {0x708f, 0x45, 0, 0}, + {0x7090, 0xad, 0, 0}, + {0x7091, 0x28, 0, 0}, + {0x7092, 0x00, 0, 0}, + {0x7093, 0xb8, 0, 0}, + {0x7094, 0x00, 0, 0}, + {0x7095, 0xbc, 0, 0}, + {0x7096, 0x01, 0, 0}, + {0x7097, 0x36, 0, 0}, + {0x7098, 0xd3, 0, 0}, + {0x7099, 0x30, 0, 0}, + {0x709a, 0x04, 0, 0}, + {0x709b, 0xe0, 0, 0}, + {0x709c, 0xd8, 0, 0}, + {0x709d, 0xb4, 0, 0}, + {0x709e, 0xe9, 0, 0}, + {0x709f, 0x00, 0, 0}, + {0x70a0, 0xbe, 0, 0}, + {0x70a1, 0x05, 0, 0}, + {0x70a2, 0x62, 0, 0}, + {0x70a3, 0x07, 0, 0}, + {0x70a4, 0xb9, 0, 0}, + {0x70a5, 0x05, 0, 0}, + {0x70a6, 0xad, 0, 0}, + {0x70a7, 0xc3, 0, 0}, + {0x70a8, 0xcf, 0, 0}, + {0x70a9, 0x00, 0, 0}, + {0x70aa, 0x15, 0, 0}, + {0x70ab, 0xc2, 0, 0}, + {0x70ac, 0x59, 0, 0}, + {0x70ad, 0xc3, 0, 0}, + {0x70ae, 0xc9, 0, 0}, + {0x70af, 0xc0, 0, 0}, + {0x70b0, 0x55, 0, 0}, + {0x70b1, 0x00, 0, 0}, + {0x70b2, 0x46, 0, 0}, + {0x70b3, 0xa1, 0, 0}, + {0x70b4, 0xb9, 0, 0}, + {0x70b5, 0x64, 0, 0}, + {0x70b6, 0x29, 0, 0}, + {0x70b7, 0x00, 0, 0}, + {0x70b8, 0xb8, 0, 0}, + {0x70b9, 0x02, 0, 0}, + {0x70ba, 0xbe, 0, 0}, + {0x70bb, 0x02, 0, 0}, + {0x70bc, 0xd0, 0, 0}, + {0x70bd, 0xdc, 0, 0}, + {0x70be, 0xac, 0, 0}, + {0x70bf, 0xbc, 0, 0}, + {0x70c0, 0x01, 0, 0}, + {0x70c1, 0x37, 0, 0}, + {0x70c2, 0xac, 0, 0}, + {0x70c3, 0xd2, 0, 0}, + {0x70c4, 0x45, 0, 0}, + {0x70c5, 0xad, 0, 0}, + {0x70c6, 0x28, 0, 0}, + {0x70c7, 0x00, 0, 0}, + {0x70c8, 0xb8, 0, 0}, + {0x70c9, 0x00, 0, 0}, + {0x70ca, 0xbc, 0, 0}, + {0x70cb, 0x01, 0, 0}, + {0x70cc, 0x36, 0, 0}, + {0x70cd, 0x30, 0, 0}, + {0x70ce, 0xe0, 0, 0}, + {0x70cf, 0xd8, 0, 0}, + {0x70d0, 0xb5, 0, 0}, + {0x70d1, 0x0b, 0, 0}, + {0x70d2, 0xd6, 0, 0}, + {0x70d3, 0xbe, 0, 0}, + {0x70d4, 0x07, 0, 0}, + {0x70d5, 0x00, 0, 0}, + {0x70d6, 0x62, 0, 0}, + {0x70d7, 0x07, 0, 0}, + {0x70d8, 0xb9, 0, 0}, + {0x70d9, 0x05, 0, 0}, + {0x70da, 0xad, 0, 0}, + {0x70db, 0xc3, 0, 0}, + {0x70dc, 0xcf, 0, 0}, + {0x70dd, 0x46, 0, 0}, + {0x70de, 0xcd, 0, 0}, + {0x70df, 0x07, 0, 0}, + {0x70e0, 0xcd, 0, 0}, + {0x70e1, 0x00, 0, 0}, + {0x70e2, 0xe3, 0, 0}, + {0x70e3, 0x18, 0, 0}, + {0x70e4, 0xc2, 0, 0}, + {0x70e5, 0xa2, 0, 0}, + {0x70e6, 0xb9, 0, 0}, + {0x70e7, 0x64, 0, 0}, + {0x70e8, 0xd1, 0, 0}, + {0x70e9, 0xdd, 0, 0}, + {0x70ea, 0xac, 0, 0}, + {0x70eb, 0xcf, 0, 0}, + {0x70ec, 0xdf, 0, 0}, + {0x70ed, 0xb5, 0, 0}, + {0x70ee, 0x19, 0, 0}, + {0x70ef, 0x46, 0, 0}, + {0x70f0, 0x50, 0, 0}, + {0x70f1, 0xb6, 0, 0}, + {0x70f2, 0xee, 0, 0}, + {0x70f3, 0xe8, 0, 0}, + {0x70f4, 0xe6, 0, 0}, + {0x70f5, 0xbc, 0, 0}, + {0x70f6, 0x31, 0, 0}, + {0x70f7, 0xe1, 0, 0}, + {0x70f8, 0x36, 0, 0}, + {0x70f9, 0x30, 0, 0}, + {0x70fa, 0xd3, 0, 0}, + {0x70fb, 0x2e, 0, 0}, + {0x70fc, 0x54, 0, 0}, + {0x70fd, 0xbd, 0, 0}, + {0x70fe, 0x03, 0, 0}, + {0x70ff, 0xec, 0, 0}, + {0x7100, 0x2c, 0, 0}, + {0x7101, 0x50, 0, 0}, + {0x7102, 0x20, 0, 0}, + {0x7103, 0x04, 0, 0}, + {0x7104, 0xb8, 0, 0}, + {0x7105, 0x02, 0, 0}, + {0x7106, 0xbc, 0, 0}, + {0x7107, 0x18, 0, 0}, + {0x7108, 0xc7, 0, 0}, + {0x7109, 0xb8, 0, 0}, + {0x710a, 0x00, 0, 0}, + {0x710b, 0x28, 0, 0}, + {0x710c, 0x54, 0, 0}, + {0x710d, 0xbc, 0, 0}, + {0x710e, 0x02, 0, 0}, + {0x710f, 0xb4, 0, 0}, + {0x7110, 0xda, 0, 0}, + {0x7111, 0xbe, 0, 0}, + {0x7112, 0x04, 0, 0}, + {0x7113, 0xd6, 0, 0}, + {0x7114, 0xd8, 0, 0}, + {0x7115, 0xab, 0, 0}, + {0x7116, 0x00, 0, 0}, + {0x7117, 0x62, 0, 0}, + {0x7118, 0x07, 0, 0}, + {0x7119, 0xb9, 0, 0}, + {0x711a, 0x05, 0, 0}, + {0x711b, 0xad, 0, 0}, + {0x711c, 0xc3, 0, 0}, + {0x711d, 0xbc, 0, 0}, + {0x711e, 0xe7, 0, 0}, + {0x711f, 0xb9, 0, 0}, + {0x7120, 0x64, 0, 0}, + {0x7121, 0x29, 0, 0}, + {0x7122, 0x00, 0, 0}, + {0x7123, 0xb8, 0, 0}, + {0x7124, 0x02, 0, 0}, + {0x7125, 0xbe, 0, 0}, + {0x7126, 0x00, 0, 0}, + {0x7127, 0x45, 0, 0}, + {0x7128, 0xad, 0, 0}, + {0x7129, 0xe2, 0, 0}, + {0x712a, 0x28, 0, 0}, + {0x712b, 0x00, 0, 0}, + {0x712c, 0xb8, 0, 0}, + {0x712d, 0x00, 0, 0}, + {0x712e, 0xe0, 0, 0}, + {0x712f, 0xd8, 0, 0}, + {0x7130, 0xb4, 0, 0}, + {0x7131, 0xe9, 0, 0}, + {0x7132, 0xbe, 0, 0}, + {0x7133, 0x03, 0, 0}, + {0x7134, 0x00, 0, 0}, + {0x7135, 0x30, 0, 0}, + {0x7136, 0x62, 0, 0}, + {0x7137, 0x07, 0, 0}, + {0x7138, 0xb9, 0, 0}, + {0x7139, 0x05, 0, 0}, + {0x713a, 0xad, 0, 0}, + {0x713b, 0xc3, 0, 0}, + {0x713c, 0xcf, 0, 0}, + {0x713d, 0x42, 0, 0}, + {0x713e, 0xe4, 0, 0}, + {0x713f, 0xcd, 0, 0}, + {0x7140, 0x07, 0, 0}, + {0x7141, 0xcd, 0, 0}, + {0x7142, 0x00, 0, 0}, + {0x7143, 0x00, 0, 0}, + {0x7144, 0x17, 0, 0}, + {0x7145, 0xc2, 0, 0}, + {0x7146, 0xbb, 0, 0}, + {0x7147, 0xde, 0, 0}, + {0x7148, 0xcf, 0, 0}, + {0x7149, 0xdf, 0, 0}, + {0x714a, 0xac, 0, 0}, + {0x714b, 0xd1, 0, 0}, + {0x714c, 0x44, 0, 0}, + {0x714d, 0xac, 0, 0}, + {0x714e, 0xb9, 0, 0}, + {0x714f, 0x76, 0, 0}, + {0x7150, 0xb8, 0, 0}, + {0x7151, 0x08, 0, 0}, + {0x7152, 0xb6, 0, 0}, + {0x7153, 0xfe, 0, 0}, + {0x7154, 0xb4, 0, 0}, + {0x7155, 0xca, 0, 0}, + {0x7156, 0xd6, 0, 0}, + {0x7157, 0xd8, 0, 0}, + {0x7158, 0xab, 0, 0}, + {0x7159, 0x00, 0, 0}, + {0x715a, 0xe1, 0, 0}, + {0x715b, 0x36, 0, 0}, + {0x715c, 0x30, 0, 0}, + {0x715d, 0xd3, 0, 0}, + {0x715e, 0xbc, 0, 0}, + {0x715f, 0x29, 0, 0}, + {0x7160, 0xb4, 0, 0}, + {0x7161, 0x1f, 0, 0}, + {0x7162, 0xaa, 0, 0}, + {0x7163, 0xbd, 0, 0}, + {0x7164, 0x01, 0, 0}, + {0x7165, 0xb8, 0, 0}, + {0x7166, 0x0c, 0, 0}, + {0x7167, 0x45, 0, 0}, + {0x7168, 0xa4, 0, 0}, + {0x7169, 0xbd, 0, 0}, + {0x716a, 0x03, 0, 0}, + {0x716b, 0xec, 0, 0}, + {0x716c, 0xbc, 0, 0}, + {0x716d, 0x3d, 0, 0}, + {0x716e, 0xc3, 0, 0}, + {0x716f, 0xcf, 0, 0}, + {0x7170, 0x42, 0, 0}, + {0x7171, 0xb8, 0, 0}, + {0x7172, 0x00, 0, 0}, + {0x7173, 0xe4, 0, 0}, + {0x7174, 0xd5, 0, 0}, + {0x7175, 0x00, 0, 0}, + {0x7176, 0xb6, 0, 0}, + {0x7177, 0x00, 0, 0}, + {0x7178, 0x74, 0, 0}, + {0x7179, 0xbd, 0, 0}, + {0x717a, 0x03, 0, 0}, + {0x717b, 0xb5, 0, 0}, + {0x717c, 0x39, 0, 0}, + {0x717d, 0x40, 0, 0}, + {0x717e, 0x58, 0, 0}, + {0x717f, 0xdd, 0, 0}, + {0x7180, 0x19, 0, 0}, + {0x7181, 0xc1, 0, 0}, + {0x7182, 0xc8, 0, 0}, + {0x7183, 0xbd, 0, 0}, + {0x7184, 0x06, 0, 0}, + {0x7185, 0x17, 0, 0}, + {0x7186, 0xc1, 0, 0}, + {0x7187, 0xc6, 0, 0}, + {0x7188, 0xe8, 0, 0}, + {0x7189, 0x00, 0, 0}, + {0x718a, 0xc0, 0, 0}, + {0x718b, 0xc8, 0, 0}, + {0x718c, 0xe6, 0, 0}, + {0x718d, 0x95, 0, 0}, + {0x718e, 0x15, 0, 0}, + {0x718f, 0x00, 0, 0}, + {0x7190, 0xbc, 0, 0}, + {0x7191, 0x19, 0, 0}, + {0x7192, 0xb9, 0, 0}, + {0x7193, 0xf6, 0, 0}, + {0x7194, 0x14, 0, 0}, + {0x7195, 0xc1, 0, 0}, + {0x7196, 0xd0, 0, 0}, + {0x7197, 0xd1, 0, 0}, + {0x7198, 0xac, 0, 0}, + {0x7199, 0x37, 0, 0}, + {0x719a, 0xbc, 0, 0}, + {0x719b, 0x35, 0, 0}, + {0x719c, 0x36, 0, 0}, + {0x719d, 0x30, 0, 0}, + {0x719e, 0xe1, 0, 0}, + {0x719f, 0xd3, 0, 0}, + {0x71a0, 0x7a, 0, 0}, + {0x71a1, 0xb6, 0, 0}, + {0x71a2, 0x0c, 0, 0}, + {0x71a3, 0xff, 0, 0}, + {0x71a4, 0xb4, 0, 0}, + {0x71a5, 0xc7, 0, 0}, + {0x71a6, 0xd9, 0, 0}, + {0x71a7, 0x00, 0, 0}, + {0x71a8, 0xbd, 0, 0}, + {0x71a9, 0x01, 0, 0}, + {0x71aa, 0x56, 0, 0}, + {0x71ab, 0xc0, 0, 0}, + {0x71ac, 0xda, 0, 0}, + {0x71ad, 0xb4, 0, 0}, + {0x71ae, 0x1f, 0, 0}, + {0x71af, 0x56, 0, 0}, + {0x71b0, 0xaa, 0, 0}, + {0x71b1, 0xbc, 0, 0}, + {0x71b2, 0x08, 0, 0}, + {0x71b3, 0x00, 0, 0}, + {0x71b4, 0x57, 0, 0}, + {0x71b5, 0xe8, 0, 0}, + {0x71b6, 0xb5, 0, 0}, + {0x71b7, 0x36, 0, 0}, + {0x71b8, 0x00, 0, 0}, + {0x71b9, 0x54, 0, 0}, + {0x71ba, 0xe7, 0, 0}, + {0x71bb, 0xc8, 0, 0}, + {0x71bc, 0xb4, 0, 0}, + {0x71bd, 0x1f, 0, 0}, + {0x71be, 0x56, 0, 0}, + {0x71bf, 0xaa, 0, 0}, + {0x71c0, 0xbc, 0, 0}, + {0x71c1, 0x08, 0, 0}, + {0x71c2, 0x57, 0, 0}, + {0x71c3, 0x00, 0, 0}, + {0x71c4, 0xb5, 0, 0}, + {0x71c5, 0x36, 0, 0}, + {0x71c6, 0x00, 0, 0}, + {0x71c7, 0x54, 0, 0}, + {0x71c8, 0xc8, 0, 0}, + {0x71c9, 0xb5, 0, 0}, + {0x71ca, 0x18, 0, 0}, + {0x71cb, 0xd9, 0, 0}, + {0x71cc, 0x00, 0, 0}, + {0x71cd, 0xbd, 0, 0}, + {0x71ce, 0x01, 0, 0}, + {0x71cf, 0x56, 0, 0}, + {0x71d0, 0x08, 0, 0}, + {0x71d1, 0x57, 0, 0}, + {0x71d2, 0xe8, 0, 0}, + {0x71d3, 0xb4, 0, 0}, + {0x71d4, 0x42, 0, 0}, + {0x71d5, 0x00, 0, 0}, + {0x71d6, 0x54, 0, 0}, + {0x71d7, 0xe7, 0, 0}, + {0x71d8, 0xc8, 0, 0}, + {0x71d9, 0xab, 0, 0}, + {0x71da, 0x00, 0, 0}, + {0x71db, 0x66, 0, 0}, + {0x71dc, 0x62, 0, 0}, + {0x71dd, 0x06, 0, 0}, + {0x71de, 0x74, 0, 0}, + {0x71df, 0xb9, 0, 0}, + {0x71e0, 0x05, 0, 0}, + {0x71e1, 0xb7, 0, 0}, + {0x71e2, 0x14, 0, 0}, + {0x71e3, 0x0e, 0, 0}, + {0x71e4, 0xb7, 0, 0}, + {0x71e5, 0x04, 0, 0}, + {0x71e6, 0xc8, 0, 0}, + {0x7600, 0x04, 0, 0}, + {0x7601, 0x80, 0, 0}, + {0x7602, 0x07, 0, 0}, + {0x7603, 0x44, 0, 0}, + {0x7604, 0x05, 0, 0}, + {0x7605, 0x33, 0, 0}, + {0x7606, 0x0f, 0, 0}, + {0x7607, 0x00, 0, 0}, + {0x7608, 0x07, 0, 0}, + {0x7609, 0x40, 0, 0}, + {0x760a, 0x04, 0, 0}, + {0x760b, 0xe5, 0, 0}, + {0x760c, 0x06, 0, 0}, + {0x760d, 0x50, 0, 0}, + {0x760e, 0x04, 0, 0}, + {0x760f, 0xe4, 0, 0}, + {0x7610, 0x00, 0, 0}, + {0x7611, 0x00, 0, 0}, + {0x7612, 0x06, 0, 0}, + {0x7613, 0x5c, 0, 0}, + {0x7614, 0x00, 0, 0}, + {0x7615, 0x0f, 0, 0}, + {0x7616, 0x06, 0, 0}, + {0x7617, 0x1c, 0, 0}, + {0x7618, 0x00, 0, 0}, + {0x7619, 0x02, 0, 0}, + {0x761a, 0x06, 0, 0}, + {0x761b, 0xa2, 0, 0}, + {0x761c, 0x00, 0, 0}, + {0x761d, 0x01, 0, 0}, + {0x761e, 0x06, 0, 0}, + {0x761f, 0xae, 0, 0}, + {0x7620, 0x00, 0, 0}, + {0x7621, 0x0e, 0, 0}, + {0x7622, 0x05, 0, 0}, + {0x7623, 0x30, 0, 0}, + {0x7624, 0x07, 0, 0}, + {0x7625, 0x00, 0, 0}, + {0x7626, 0x0f, 0, 0}, + {0x7627, 0x00, 0, 0}, + {0x7628, 0x04, 0, 0}, + {0x7629, 0xe5, 0, 0}, + {0x762a, 0x05, 0, 0}, + {0x762b, 0x33, 0, 0}, + {0x762c, 0x06, 0, 0}, + {0x762d, 0x12, 0, 0}, + {0x762e, 0x00, 0, 0}, + {0x762f, 0x01, 0, 0}, + {0x7630, 0x06, 0, 0}, + {0x7631, 0x52, 0, 0}, + {0x7632, 0x00, 0, 0}, + {0x7633, 0x01, 0, 0}, + {0x7634, 0x06, 0, 0}, + {0x7635, 0x5e, 0, 0}, + {0x7636, 0x04, 0, 0}, + {0x7637, 0xe4, 0, 0}, + {0x7638, 0x00, 0, 0}, + {0x7639, 0x01, 0, 0}, + {0x763a, 0x05, 0, 0}, + {0x763b, 0x30, 0, 0}, + {0x763c, 0x0f, 0, 0}, + {0x763d, 0x00, 0, 0}, + {0x763e, 0x06, 0, 0}, + {0x763f, 0xa6, 0, 0}, + {0x7640, 0x00, 0, 0}, + {0x7641, 0x02, 0, 0}, + {0x7642, 0x06, 0, 0}, + {0x7643, 0x26, 0, 0}, + {0x7644, 0x00, 0, 0}, + {0x7645, 0x02, 0, 0}, + {0x7646, 0x05, 0, 0}, + {0x7647, 0x33, 0, 0}, + {0x7648, 0x06, 0, 0}, + {0x7649, 0x20, 0, 0}, + {0x764a, 0x0f, 0, 0}, + {0x764b, 0x00, 0, 0}, + {0x764c, 0x06, 0, 0}, + {0x764d, 0x56, 0, 0}, + {0x764e, 0x00, 0, 0}, + {0x764f, 0x02, 0, 0}, + {0x7650, 0x06, 0, 0}, + {0x7651, 0x16, 0, 0}, + {0x7652, 0x05, 0, 0}, + {0x7653, 0x33, 0, 0}, + {0x7654, 0x06, 0, 0}, + {0x7655, 0x10, 0, 0}, + {0x7656, 0x0f, 0, 0}, + {0x7657, 0x00, 0, 0}, + {0x7658, 0x06, 0, 0}, + {0x7659, 0x10, 0, 0}, + {0x765a, 0x0f, 0, 0}, + {0x765b, 0x00, 0, 0}, + {0x765c, 0x06, 0, 0}, + {0x765d, 0x20, 0, 0}, + {0x765e, 0x0f, 0, 0}, + {0x765f, 0x00, 0, 0}, + {0x7660, 0x00, 0, 0}, + {0x7661, 0x00, 0, 0}, + {0x7662, 0x00, 0, 0}, + {0x7663, 0x02, 0, 0}, + {0x7664, 0x04, 0, 0}, + {0x7665, 0xe5, 0, 0}, + {0x7666, 0x04, 0, 0}, + {0x7667, 0xe4, 0, 0}, + {0x7668, 0x0f, 0, 0}, + {0x7669, 0x00, 0, 0}, + {0x766a, 0x00, 0, 0}, + {0x766b, 0x00, 0, 0}, + {0x766c, 0x00, 0, 0}, + {0x766d, 0x01, 0, 0}, + {0x766e, 0x04, 0, 0}, + {0x766f, 0xe5, 0, 0}, + {0x7670, 0x04, 0, 0}, + {0x7671, 0xe4, 0, 0}, + {0x7672, 0x0f, 0, 0}, + {0x7673, 0x00, 0, 0}, + {0x7674, 0x00, 0, 0}, + {0x7675, 0x02, 0, 0}, + {0x7676, 0x04, 0, 0}, + {0x7677, 0xe4, 0, 0}, + {0x7678, 0x00, 0, 0}, + {0x7679, 0x02, 0, 0}, + {0x767a, 0x04, 0, 0}, + {0x767b, 0xc4, 0, 0}, + {0x767c, 0x00, 0, 0}, + {0x767d, 0x02, 0, 0}, + {0x767e, 0x04, 0, 0}, + {0x767f, 0xc4, 0, 0}, + {0x7680, 0x05, 0, 0}, + {0x7681, 0x83, 0, 0}, + {0x7682, 0x0f, 0, 0}, + {0x7683, 0x00, 0, 0}, + {0x7684, 0x00, 0, 0}, + {0x7685, 0x02, 0, 0}, + {0x7686, 0x04, 0, 0}, + {0x7687, 0xe4, 0, 0}, + {0x7688, 0x00, 0, 0}, + {0x7689, 0x02, 0, 0}, + {0x768a, 0x04, 0, 0}, + {0x768b, 0xc4, 0, 0}, + {0x768c, 0x00, 0, 0}, + {0x768d, 0x02, 0, 0}, + {0x768e, 0x04, 0, 0}, + {0x768f, 0xc4, 0, 0}, + {0x7690, 0x05, 0, 0}, + {0x7691, 0x83, 0, 0}, + {0x7692, 0x03, 0, 0}, + {0x7693, 0x0b, 0, 0}, + {0x7694, 0x05, 0, 0}, + {0x7695, 0x83, 0, 0}, + {0x7696, 0x00, 0, 0}, + {0x7697, 0x07, 0, 0}, + {0x7698, 0x05, 0, 0}, + {0x7699, 0x03, 0, 0}, + {0x769a, 0x00, 0, 0}, + {0x769b, 0x05, 0, 0}, + {0x769c, 0x05, 0, 0}, + {0x769d, 0x32, 0, 0}, + {0x769e, 0x05, 0, 0}, + {0x769f, 0x30, 0, 0}, + {0x76a0, 0x00, 0, 0}, + {0x76a1, 0x02, 0, 0}, + {0x76a2, 0x05, 0, 0}, + {0x76a3, 0x78, 0, 0}, + {0x76a4, 0x00, 0, 0}, + {0x76a5, 0x01, 0, 0}, + {0x76a6, 0x05, 0, 0}, + {0x76a7, 0x7c, 0, 0}, + {0x76a8, 0x03, 0, 0}, + {0x76a9, 0x9a, 0, 0}, + {0x76aa, 0x05, 0, 0}, + {0x76ab, 0x83, 0, 0}, + {0x76ac, 0x00, 0, 0}, + {0x76ad, 0x04, 0, 0}, + {0x76ae, 0x05, 0, 0}, + {0x76af, 0x03, 0, 0}, + {0x76b0, 0x00, 0, 0}, + {0x76b1, 0x03, 0, 0}, + {0x76b2, 0x05, 0, 0}, + {0x76b3, 0x32, 0, 0}, + {0x76b4, 0x05, 0, 0}, + {0x76b5, 0x30, 0, 0}, + {0x76b6, 0x00, 0, 0}, + {0x76b7, 0x02, 0, 0}, + {0x76b8, 0x05, 0, 0}, + {0x76b9, 0x78, 0, 0}, + {0x76ba, 0x00, 0, 0}, + {0x76bb, 0x01, 0, 0}, + {0x76bc, 0x05, 0, 0}, + {0x76bd, 0x7c, 0, 0}, + {0x76be, 0x03, 0, 0}, + {0x76bf, 0x99, 0, 0}, + {0x76c0, 0x05, 0, 0}, + {0x76c1, 0x83, 0, 0}, + {0x76c2, 0x00, 0, 0}, + {0x76c3, 0x03, 0, 0}, + {0x76c4, 0x05, 0, 0}, + {0x76c5, 0x03, 0, 0}, + {0x76c6, 0x00, 0, 0}, + {0x76c7, 0x01, 0, 0}, + {0x76c8, 0x05, 0, 0}, + {0x76c9, 0x32, 0, 0}, + {0x76ca, 0x05, 0, 0}, + {0x76cb, 0x30, 0, 0}, + {0x76cc, 0x00, 0, 0}, + {0x76cd, 0x02, 0, 0}, + {0x76ce, 0x05, 0, 0}, + {0x76cf, 0x78, 0, 0}, + {0x76d0, 0x00, 0, 0}, + {0x76d1, 0x01, 0, 0}, + {0x76d2, 0x05, 0, 0}, + {0x76d3, 0x7c, 0, 0}, + {0x76d4, 0x03, 0, 0}, + {0x76d5, 0x98, 0, 0}, + {0x76d6, 0x05, 0, 0}, + {0x76d7, 0x83, 0, 0}, + {0x76d8, 0x00, 0, 0}, + {0x76d9, 0x00, 0, 0}, + {0x76da, 0x05, 0, 0}, + {0x76db, 0x03, 0, 0}, + {0x76dc, 0x00, 0, 0}, + {0x76dd, 0x01, 0, 0}, + {0x76de, 0x05, 0, 0}, + {0x76df, 0x32, 0, 0}, + {0x76e0, 0x05, 0, 0}, + {0x76e1, 0x30, 0, 0}, + {0x76e2, 0x00, 0, 0}, + {0x76e3, 0x02, 0, 0}, + {0x76e4, 0x05, 0, 0}, + {0x76e5, 0x78, 0, 0}, + {0x76e6, 0x00, 0, 0}, + {0x76e7, 0x01, 0, 0}, + {0x76e8, 0x05, 0, 0}, + {0x76e9, 0x7c, 0, 0}, + {0x76ea, 0x03, 0, 0}, + {0x76eb, 0x97, 0, 0}, + {0x76ec, 0x05, 0, 0}, + {0x76ed, 0x83, 0, 0}, + {0x76ee, 0x00, 0, 0}, + {0x76ef, 0x00, 0, 0}, + {0x76f0, 0x05, 0, 0}, + {0x76f1, 0x03, 0, 0}, + {0x76f2, 0x05, 0, 0}, + {0x76f3, 0x32, 0, 0}, + {0x76f4, 0x05, 0, 0}, + {0x76f5, 0x30, 0, 0}, + {0x76f6, 0x00, 0, 0}, + {0x76f7, 0x02, 0, 0}, + {0x76f8, 0x05, 0, 0}, + {0x76f9, 0x78, 0, 0}, + {0x76fa, 0x00, 0, 0}, + {0x76fb, 0x01, 0, 0}, + {0x76fc, 0x05, 0, 0}, + {0x76fd, 0x7c, 0, 0}, + {0x76fe, 0x03, 0, 0}, + {0x76ff, 0x96, 0, 0}, + {0x7700, 0x05, 0, 0}, + {0x7701, 0x83, 0, 0}, + {0x7702, 0x05, 0, 0}, + {0x7703, 0x03, 0, 0}, + {0x7704, 0x05, 0, 0}, + {0x7705, 0x32, 0, 0}, + {0x7706, 0x05, 0, 0}, + {0x7707, 0x30, 0, 0}, + {0x7708, 0x00, 0, 0}, + {0x7709, 0x02, 0, 0}, + {0x770a, 0x05, 0, 0}, + {0x770b, 0x78, 0, 0}, + {0x770c, 0x00, 0, 0}, + {0x770d, 0x01, 0, 0}, + {0x770e, 0x05, 0, 0}, + {0x770f, 0x7c, 0, 0}, + {0x7710, 0x03, 0, 0}, + {0x7711, 0x95, 0, 0}, + {0x7712, 0x05, 0, 0}, + {0x7713, 0x83, 0, 0}, + {0x7714, 0x05, 0, 0}, + {0x7715, 0x03, 0, 0}, + {0x7716, 0x05, 0, 0}, + {0x7717, 0x32, 0, 0}, + {0x7718, 0x05, 0, 0}, + {0x7719, 0x30, 0, 0}, + {0x771a, 0x00, 0, 0}, + {0x771b, 0x02, 0, 0}, + {0x771c, 0x05, 0, 0}, + {0x771d, 0x78, 0, 0}, + {0x771e, 0x00, 0, 0}, + {0x771f, 0x01, 0, 0}, + {0x7720, 0x05, 0, 0}, + {0x7721, 0x7c, 0, 0}, + {0x7722, 0x03, 0, 0}, + {0x7723, 0x94, 0, 0}, + {0x7724, 0x05, 0, 0}, + {0x7725, 0x83, 0, 0}, + {0x7726, 0x00, 0, 0}, + {0x7727, 0x01, 0, 0}, + {0x7728, 0x05, 0, 0}, + {0x7729, 0x03, 0, 0}, + {0x772a, 0x00, 0, 0}, + {0x772b, 0x01, 0, 0}, + {0x772c, 0x05, 0, 0}, + {0x772d, 0x32, 0, 0}, + {0x772e, 0x05, 0, 0}, + {0x772f, 0x30, 0, 0}, + {0x7730, 0x00, 0, 0}, + {0x7731, 0x02, 0, 0}, + {0x7732, 0x05, 0, 0}, + {0x7733, 0x78, 0, 0}, + {0x7734, 0x00, 0, 0}, + {0x7735, 0x01, 0, 0}, + {0x7736, 0x05, 0, 0}, + {0x7737, 0x7c, 0, 0}, + {0x7738, 0x03, 0, 0}, + {0x7739, 0x93, 0, 0}, + {0x773a, 0x05, 0, 0}, + {0x773b, 0x83, 0, 0}, + {0x773c, 0x00, 0, 0}, + {0x773d, 0x00, 0, 0}, + {0x773e, 0x05, 0, 0}, + {0x773f, 0x03, 0, 0}, + {0x7740, 0x00, 0, 0}, + {0x7741, 0x00, 0, 0}, + {0x7742, 0x05, 0, 0}, + {0x7743, 0x32, 0, 0}, + {0x7744, 0x05, 0, 0}, + {0x7745, 0x30, 0, 0}, + {0x7746, 0x00, 0, 0}, + {0x7747, 0x02, 0, 0}, + {0x7748, 0x05, 0, 0}, + {0x7749, 0x78, 0, 0}, + {0x774a, 0x00, 0, 0}, + {0x774b, 0x01, 0, 0}, + {0x774c, 0x05, 0, 0}, + {0x774d, 0x7c, 0, 0}, + {0x774e, 0x03, 0, 0}, + {0x774f, 0x92, 0, 0}, + {0x7750, 0x05, 0, 0}, + {0x7751, 0x83, 0, 0}, + {0x7752, 0x05, 0, 0}, + {0x7753, 0x03, 0, 0}, + {0x7754, 0x00, 0, 0}, + {0x7755, 0x00, 0, 0}, + {0x7756, 0x05, 0, 0}, + {0x7757, 0x32, 0, 0}, + {0x7758, 0x05, 0, 0}, + {0x7759, 0x30, 0, 0}, + {0x775a, 0x00, 0, 0}, + {0x775b, 0x02, 0, 0}, + {0x775c, 0x05, 0, 0}, + {0x775d, 0x78, 0, 0}, + {0x775e, 0x00, 0, 0}, + {0x775f, 0x01, 0, 0}, + {0x7760, 0x05, 0, 0}, + {0x7761, 0x7c, 0, 0}, + {0x7762, 0x03, 0, 0}, + {0x7763, 0x91, 0, 0}, + {0x7764, 0x05, 0, 0}, + {0x7765, 0x83, 0, 0}, + {0x7766, 0x05, 0, 0}, + {0x7767, 0x03, 0, 0}, + {0x7768, 0x05, 0, 0}, + {0x7769, 0x32, 0, 0}, + {0x776a, 0x05, 0, 0}, + {0x776b, 0x30, 0, 0}, + {0x776c, 0x00, 0, 0}, + {0x776d, 0x02, 0, 0}, + {0x776e, 0x05, 0, 0}, + {0x776f, 0x78, 0, 0}, + {0x7770, 0x00, 0, 0}, + {0x7771, 0x01, 0, 0}, + {0x7772, 0x05, 0, 0}, + {0x7773, 0x7c, 0, 0}, + {0x7774, 0x03, 0, 0}, + {0x7775, 0x90, 0, 0}, + {0x7776, 0x05, 0, 0}, + {0x7777, 0x83, 0, 0}, + {0x7778, 0x05, 0, 0}, + {0x7779, 0x03, 0, 0}, + {0x777a, 0x05, 0, 0}, + {0x777b, 0x32, 0, 0}, + {0x777c, 0x05, 0, 0}, + {0x777d, 0x30, 0, 0}, + {0x777e, 0x00, 0, 0}, + {0x777f, 0x02, 0, 0}, + {0x7780, 0x05, 0, 0}, + {0x7781, 0x78, 0, 0}, + {0x7782, 0x00, 0, 0}, + {0x7783, 0x01, 0, 0}, + {0x7784, 0x05, 0, 0}, + {0x7785, 0x7c, 0, 0}, + {0x7786, 0x02, 0, 0}, + {0x7787, 0x90, 0, 0}, + {0x7788, 0x05, 0, 0}, + {0x7789, 0x03, 0, 0}, + {0x778a, 0x07, 0, 0}, + {0x778b, 0x00, 0, 0}, + {0x778c, 0x0f, 0, 0}, + {0x778d, 0x00, 0, 0}, + {0x778e, 0x08, 0, 0}, + {0x778f, 0x30, 0, 0}, + {0x7790, 0x08, 0, 0}, + {0x7791, 0xee, 0, 0}, + {0x7792, 0x0f, 0, 0}, + {0x7793, 0x00, 0, 0}, + {0x7794, 0x05, 0, 0}, + {0x7795, 0x33, 0, 0}, + {0x7796, 0x04, 0, 0}, + {0x7797, 0xe5, 0, 0}, + {0x7798, 0x06, 0, 0}, + {0x7799, 0x52, 0, 0}, + {0x779a, 0x04, 0, 0}, + {0x779b, 0xe4, 0, 0}, + {0x779c, 0x00, 0, 0}, + {0x779d, 0x00, 0, 0}, + {0x779e, 0x06, 0, 0}, + {0x779f, 0x5e, 0, 0}, + {0x77a0, 0x00, 0, 0}, + {0x77a1, 0x0f, 0, 0}, + {0x77a2, 0x06, 0, 0}, + {0x77a3, 0x1e, 0, 0}, + {0x77a4, 0x00, 0, 0}, + {0x77a5, 0x02, 0, 0}, + {0x77a6, 0x06, 0, 0}, + {0x77a7, 0xa2, 0, 0}, + {0x77a8, 0x00, 0, 0}, + {0x77a9, 0x01, 0, 0}, + {0x77aa, 0x06, 0, 0}, + {0x77ab, 0xae, 0, 0}, + {0x77ac, 0x00, 0, 0}, + {0x77ad, 0x03, 0, 0}, + {0x77ae, 0x05, 0, 0}, + {0x77af, 0x30, 0, 0}, + {0x77b0, 0x09, 0, 0}, + {0x77b1, 0x19, 0, 0}, + {0x77b2, 0x0f, 0, 0}, + {0x77b3, 0x00, 0, 0}, + {0x77b4, 0x05, 0, 0}, + {0x77b5, 0x33, 0, 0}, + {0x77b6, 0x04, 0, 0}, + {0x77b7, 0xe5, 0, 0}, + {0x77b8, 0x06, 0, 0}, + {0x77b9, 0x52, 0, 0}, + {0x77ba, 0x04, 0, 0}, + {0x77bb, 0xe4, 0, 0}, + {0x77bc, 0x00, 0, 0}, + {0x77bd, 0x00, 0, 0}, + {0x77be, 0x06, 0, 0}, + {0x77bf, 0x5e, 0, 0}, + {0x77c0, 0x00, 0, 0}, + {0x77c1, 0x0f, 0, 0}, + {0x77c2, 0x06, 0, 0}, + {0x77c3, 0x1e, 0, 0}, + {0x77c4, 0x00, 0, 0}, + {0x77c5, 0x02, 0, 0}, + {0x77c6, 0x06, 0, 0}, + {0x77c7, 0xa2, 0, 0}, + {0x77c8, 0x00, 0, 0}, + {0x77c9, 0x01, 0, 0}, + {0x77ca, 0x06, 0, 0}, + {0x77cb, 0xae, 0, 0}, + {0x77cc, 0x00, 0, 0}, + {0x77cd, 0x03, 0, 0}, + {0x77ce, 0x05, 0, 0}, + {0x77cf, 0x30, 0, 0}, + {0x77d0, 0x0f, 0, 0}, + {0x77d1, 0x00, 0, 0}, + {0x77d2, 0x00, 0, 0}, + {0x77d3, 0x00, 0, 0}, + {0x77d4, 0x00, 0, 0}, + {0x77d5, 0x02, 0, 0}, + {0x77d6, 0x04, 0, 0}, + {0x77d7, 0xe5, 0, 0}, + {0x77d8, 0x04, 0, 0}, + {0x77d9, 0xe4, 0, 0}, + {0x77da, 0x05, 0, 0}, + {0x77db, 0x33, 0, 0}, + {0x77dc, 0x07, 0, 0}, + {0x77dd, 0x10, 0, 0}, + {0x77de, 0x00, 0, 0}, + {0x77df, 0x00, 0, 0}, + {0x77e0, 0x01, 0, 0}, + {0x77e1, 0xbb, 0, 0}, + {0x77e2, 0x00, 0, 0}, + {0x77e3, 0x00, 0, 0}, + {0x77e4, 0x01, 0, 0}, + {0x77e5, 0xaa, 0, 0}, + {0x77e6, 0x00, 0, 0}, + {0x77e7, 0x00, 0, 0}, + {0x77e8, 0x01, 0, 0}, + {0x77e9, 0x99, 0, 0}, + {0x77ea, 0x00, 0, 0}, + {0x77eb, 0x00, 0, 0}, + {0x77ec, 0x01, 0, 0}, + {0x77ed, 0x88, 0, 0}, + {0x77ee, 0x00, 0, 0}, + {0x77ef, 0x00, 0, 0}, + {0x77f0, 0x01, 0, 0}, + {0x77f1, 0x77, 0, 0}, + {0x77f2, 0x00, 0, 0}, + {0x77f3, 0x00, 0, 0}, + {0x77f4, 0x01, 0, 0}, + {0x77f5, 0x66, 0, 0}, + {0x77f6, 0x00, 0, 0}, + {0x77f7, 0x00, 0, 0}, + {0x77f8, 0x01, 0, 0}, + {0x77f9, 0x55, 0, 0}, + {0x77fa, 0x00, 0, 0}, + {0x77fb, 0x00, 0, 0}, + {0x77fc, 0x01, 0, 0}, + {0x77fd, 0x44, 0, 0}, + {0x77fe, 0x00, 0, 0}, + {0x77ff, 0x00, 0, 0}, + {0x7800, 0x01, 0, 0}, + {0x7801, 0x33, 0, 0}, + {0x7802, 0x00, 0, 0}, + {0x7803, 0x00, 0, 0}, + {0x7804, 0x01, 0, 0}, + {0x7805, 0x22, 0, 0}, + {0x7806, 0x00, 0, 0}, + {0x7807, 0x00, 0, 0}, + {0x7808, 0x01, 0, 0}, + {0x7809, 0x11, 0, 0}, + {0x780a, 0x00, 0, 0}, + {0x780b, 0x00, 0, 0}, + {0x780c, 0x01, 0, 0}, + {0x780d, 0x00, 0, 0}, + {0x780e, 0x01, 0, 0}, + {0x780f, 0xff, 0, 0}, + {0x7810, 0x07, 0, 0}, + {0x7811, 0x00, 0, 0}, + {0x7812, 0x02, 0, 0}, + {0x7813, 0xa0, 0, 0}, + {0x7814, 0x0f, 0, 0}, + {0x7815, 0x00, 0, 0}, + {0x7816, 0x08, 0, 0}, + {0x7817, 0x35, 0, 0}, + {0x7818, 0x06, 0, 0}, + {0x7819, 0x52, 0, 0}, + {0x781a, 0x04, 0, 0}, + {0x781b, 0xe4, 0, 0}, + {0x781c, 0x00, 0, 0}, + {0x781d, 0x00, 0, 0}, + {0x781e, 0x06, 0, 0}, + {0x781f, 0x5e, 0, 0}, + {0x7820, 0x05, 0, 0}, + {0x7821, 0x33, 0, 0}, + {0x7822, 0x09, 0, 0}, + {0x7823, 0x19, 0, 0}, + {0x7824, 0x06, 0, 0}, + {0x7825, 0x1e, 0, 0}, + {0x7826, 0x05, 0, 0}, + {0x7827, 0x33, 0, 0}, + {0x7828, 0x00, 0, 0}, + {0x7829, 0x01, 0, 0}, + {0x782a, 0x06, 0, 0}, + {0x782b, 0x24, 0, 0}, + {0x782c, 0x06, 0, 0}, + {0x782d, 0x20, 0, 0}, + {0x782e, 0x0f, 0, 0}, + {0x782f, 0x00, 0, 0}, + {0x7830, 0x08, 0, 0}, + {0x7831, 0x35, 0, 0}, + {0x7832, 0x07, 0, 0}, + {0x7833, 0x10, 0, 0}, + {0x7834, 0x00, 0, 0}, + {0x7835, 0x00, 0, 0}, + {0x7836, 0x01, 0, 0}, + {0x7837, 0xbb, 0, 0}, + {0x7838, 0x00, 0, 0}, + {0x7839, 0x00, 0, 0}, + {0x783a, 0x01, 0, 0}, + {0x783b, 0xaa, 0, 0}, + {0x783c, 0x00, 0, 0}, + {0x783d, 0x00, 0, 0}, + {0x783e, 0x01, 0, 0}, + {0x783f, 0x99, 0, 0}, + {0x7840, 0x00, 0, 0}, + {0x7841, 0x00, 0, 0}, + {0x7842, 0x01, 0, 0}, + {0x7843, 0x88, 0, 0}, + {0x7844, 0x00, 0, 0}, + {0x7845, 0x00, 0, 0}, + {0x7846, 0x01, 0, 0}, + {0x7847, 0x77, 0, 0}, + {0x7848, 0x00, 0, 0}, + {0x7849, 0x00, 0, 0}, + {0x784a, 0x01, 0, 0}, + {0x784b, 0x66, 0, 0}, + {0x784c, 0x00, 0, 0}, + {0x784d, 0x00, 0, 0}, + {0x784e, 0x01, 0, 0}, + {0x784f, 0x55, 0, 0}, + {0x7850, 0x00, 0, 0}, + {0x7851, 0x00, 0, 0}, + {0x7852, 0x01, 0, 0}, + {0x7853, 0x44, 0, 0}, + {0x7854, 0x00, 0, 0}, + {0x7855, 0x00, 0, 0}, + {0x7856, 0x01, 0, 0}, + {0x7857, 0x33, 0, 0}, + {0x7858, 0x00, 0, 0}, + {0x7859, 0x00, 0, 0}, + {0x785a, 0x01, 0, 0}, + {0x785b, 0x22, 0, 0}, + {0x785c, 0x00, 0, 0}, + {0x785d, 0x00, 0, 0}, + {0x785e, 0x01, 0, 0}, + {0x785f, 0x11, 0, 0}, + {0x7860, 0x00, 0, 0}, + {0x7861, 0x00, 0, 0}, + {0x7862, 0x01, 0, 0}, + {0x7863, 0x00, 0, 0}, + {0x7864, 0x07, 0, 0}, + {0x7865, 0x00, 0, 0}, + {0x7866, 0x01, 0, 0}, + {0x7867, 0xff, 0, 0}, + {0x7868, 0x02, 0, 0}, + {0x7869, 0xa0, 0, 0}, + {0x786a, 0x0f, 0, 0}, + {0x786b, 0x00, 0, 0}, + {0x786c, 0x08, 0, 0}, + {0x786d, 0x3a, 0, 0}, + {0x786e, 0x08, 0, 0}, + {0x786f, 0x6a, 0, 0}, + {0x7870, 0x0f, 0, 0}, + {0x7871, 0x00, 0, 0}, + {0x7872, 0x04, 0, 0}, + {0x7873, 0xc0, 0, 0}, + {0x7874, 0x09, 0, 0}, + {0x7875, 0x19, 0, 0}, + {0x7876, 0x04, 0, 0}, + {0x7877, 0x99, 0, 0}, + {0x7878, 0x07, 0, 0}, + {0x7879, 0x14, 0, 0}, + {0x787a, 0x00, 0, 0}, + {0x787b, 0x01, 0, 0}, + {0x787c, 0x04, 0, 0}, + {0x787d, 0xa4, 0, 0}, + {0x787e, 0x00, 0, 0}, + {0x787f, 0x07, 0, 0}, + {0x7880, 0x04, 0, 0}, + {0x7881, 0xa6, 0, 0}, + {0x7882, 0x00, 0, 0}, + {0x7883, 0x00, 0, 0}, + {0x7884, 0x04, 0, 0}, + {0x7885, 0xa0, 0, 0}, + {0x7886, 0x04, 0, 0}, + {0x7887, 0x80, 0, 0}, + {0x7888, 0x04, 0, 0}, + {0x7889, 0x00, 0, 0}, + {0x788a, 0x05, 0, 0}, + {0x788b, 0x03, 0, 0}, + {0x788c, 0x06, 0, 0}, + {0x788d, 0x00, 0, 0}, + {0x788e, 0x0f, 0, 0}, + {0x788f, 0x00, 0, 0}, + {0x7890, 0x0f, 0, 0}, + {0x7891, 0x00, 0, 0}, + {0x7892, 0x0f, 0, 0}, + {0x7893, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x05, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x04, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x80, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x38, 0, 0}, + {0x30b0, 0x0b, 0, 0},//dde + {0x30b1, 0xcb, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x66, 0, 0}, + {0x30b6, 0x04, 0, 0}, + {0x30b7, 0x62, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x0a, 0, 0}, + {0x3195, 0x29, 0, 0}, + {0x3288, 0x2a, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x15, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x0a, 0, 0}, + {0x328d, 0x80, 0, 0}, + {0x328e, 0x05, 0, 0}, + {0x328f, 0x40, 0, 0}, + {0x3290, 0x54, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x2a, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x15, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x0a, 0, 0}, + {0x3297, 0x80, 0, 0}, + {0x3298, 0x7f, 0, 0}, + {0x3299, 0xff, 0, 0}, + {0x329a, 0x54, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x2a, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x15, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x7f, 0, 0}, + {0x32a3, 0xff, 0, 0}, + {0x32a4, 0x54, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x2a, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x3250, 0xf7, 0, 0}, + {0x30bb, 0x14, 0, 0}, + {0x315a, 0x02, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x80, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x80, 0, 0}, + + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x08, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x08, 0, 0}, + + {0x30c0, 0x08, 0, 0}, + {0x3252, 0x20, 0, 0}, +}; + +#endif diff --git a/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_720p.h b/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_720p.h new file mode 100755 index 0000000..bcd64ae --- /dev/null +++ b/vvcam_ry/v4l2/sensor/ov2775/ov2775_regs_720p.h @@ -0,0 +1,1933 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ + +#ifndef _VVCAM_OV2775_REGS_720P_H_ +#define _VVCAM_OV2775_REGS_720P_H_ + +#include "vvsensor.h" + +static struct vvsensor_reg_value_t ov2775_init_setting_720p[] = { + {0x3000, 0x02, 0, 0}, + {0x3001, 0x28, 0, 0}, + {0x3002, 0x03, 0, 0}, + {0x3003, 0x01, 0, 0}, + {0x3004, 0x02, 0, 0}, + {0x3005, 0x26, 0, 0}, + {0x3006, 0x00, 0, 0}, + {0x3007, 0x07, 0, 0}, + {0x3008, 0x01, 0, 0}, + {0x3009, 0x00, 0, 0}, + {0x300c, 0x6c, 0, 0}, + {0x300e, 0x80, 0, 0}, + {0x300f, 0x00, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3013, 0x00, 0, 0}, + {0x3014, 0xc4, 0, 0}, + {0x3015, 0x00, 0, 0}, + {0x3017, 0x00, 0, 0}, + {0x3018, 0x00, 0, 0}, + {0x3019, 0x00, 0, 0}, + {0x301a, 0x00, 0, 0}, + {0x301b, 0x0e, 0, 0}, + {0x301e, 0x17, 0, 0}, + {0x301f, 0xe1, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x3031, 0x62, 0, 0}, + {0x3032, 0xf0, 0, 0}, + {0x3033, 0x30, 0, 0}, + {0x3034, 0x3f, 0, 0}, + {0x3035, 0x5f, 0, 0}, + {0x3036, 0x02, 0, 0}, + {0x3037, 0x9f, 0, 0}, + {0x3038, 0x04, 0, 0}, + {0x3039, 0xb7, 0, 0}, + {0x303a, 0x04, 0, 0}, + {0x303b, 0x07, 0, 0}, + {0x303c, 0xf0, 0, 0}, + {0x303d, 0x00, 0, 0}, + {0x303e, 0x0b, 0, 0}, + {0x303f, 0xe3, 0, 0}, + {0x3040, 0xf3, 0, 0}, + {0x3041, 0x29, 0, 0}, + {0x3042, 0xf6, 0, 0}, + {0x3043, 0x65, 0, 0}, + {0x3044, 0x06, 0, 0}, + {0x3045, 0x0f, 0, 0}, + {0x3046, 0x59, 0, 0}, + {0x3047, 0x07, 0, 0}, + {0x3048, 0x82, 0, 0}, + {0x3049, 0xcf, 0, 0}, + {0x304a, 0x12, 0, 0}, + {0x304b, 0x40, 0, 0}, + {0x304c, 0x33, 0, 0}, + {0x304d, 0xa4, 0, 0}, + {0x304e, 0x0b, 0, 0}, + {0x304f, 0x3d, 0, 0}, + {0x3050, 0x10, 0, 0}, + {0x3060, 0x00, 0, 0}, + {0x3061, 0x64, 0, 0}, + {0x3062, 0x00, 0, 0}, + {0x3063, 0xe4, 0, 0}, + {0x3066, 0x80, 0, 0}, + {0x3080, 0x00, 0, 0}, + {0x3081, 0x00, 0, 0}, + {0x3082, 0x01, 0, 0}, + {0x3083, 0xe3, 0, 0}, + {0x3084, 0x06, 0, 0}, + {0x3085, 0x00, 0, 0}, + {0x3086, 0x10, 0, 0}, + {0x3087, 0x10, 0, 0}, + {0x3089, 0x00, 0, 0}, + {0x308a, 0x01, 0, 0}, + {0x3093, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x00, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x00, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x90, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x48, 0, 0}, + {0x30b0, 0x08, 0, 0}, + {0x30b1, 0xae, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x65, 0, 0}, + {0x30b4, 0x00, 0, 0}, + {0x30b5, 0x00, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0x10, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x02, 0, 0}, + {0x30ba, 0x10, 0, 0}, + {0x30bb, 0x00, 0, 0}, + {0x30bc, 0x00, 0, 0}, + {0x30bd, 0x03, 0, 0}, + {0x30be, 0x5c, 0, 0}, + {0x30bf, 0x00, 0, 0}, + {0x30c0, 0x05, 0, 0}, + {0x30c1, 0x00, 0, 0}, + {0x30c2, 0x20, 0, 0}, + {0x30c3, 0x00, 0, 0}, + {0x30c4, 0x4a, 0, 0}, + {0x30c5, 0x00, 0, 0}, + {0x30c7, 0x00, 0, 0}, + {0x30c8, 0x00, 0, 0}, + {0x30d1, 0x00, 0, 0}, + {0x30d2, 0x00, 0, 0}, + {0x30d3, 0x80, 0, 0}, + {0x30d4, 0x00, 0, 0}, + {0x30d9, 0x09, 0, 0}, + {0x30da, 0x64, 0, 0}, + {0x30dd, 0x00, 0, 0}, + {0x30de, 0x16, 0, 0}, + {0x30df, 0x00, 0, 0}, + {0x30e0, 0x17, 0, 0}, + {0x30e1, 0x00, 0, 0}, + {0x30e2, 0x18, 0, 0}, + {0x30e3, 0x10, 0, 0}, + {0x30e4, 0x04, 0, 0}, + {0x30e5, 0x00, 0, 0}, + {0x30e6, 0x00, 0, 0}, + {0x30e7, 0x00, 0, 0}, + {0x30e8, 0x00, 0, 0}, + {0x30e9, 0x00, 0, 0}, + {0x30ea, 0x00, 0, 0}, + {0x30eb, 0x00, 0, 0}, + {0x30ec, 0x00, 0, 0}, + {0x30ed, 0x00, 0, 0}, + {0x3101, 0x00, 0, 0}, + {0x3102, 0x00, 0, 0}, + {0x3103, 0x00, 0, 0}, + {0x3104, 0x00, 0, 0}, + {0x3105, 0x8c, 0, 0}, + {0x3106, 0x87, 0, 0}, + {0x3107, 0xc0, 0, 0}, + {0x3108, 0x9d, 0, 0}, + {0x3109, 0x8d, 0, 0}, + {0x310a, 0x8d, 0, 0}, + {0x310b, 0x6a, 0, 0}, + {0x310c, 0x3a, 0, 0}, + {0x310d, 0x5a, 0, 0}, + {0x310e, 0x00, 0, 0}, + {0x3120, 0x00, 0, 0}, + {0x3121, 0x00, 0, 0}, + {0x3122, 0x00, 0, 0}, + {0x3123, 0x00, 0, 0}, + {0x3124, 0x00, 0, 0}, + {0x3125, 0x70, 0, 0}, + {0x3126, 0x1f, 0, 0}, + {0x3127, 0x0f, 0, 0}, + {0x3128, 0x00, 0, 0}, + {0x3129, 0x3a, 0, 0}, + {0x312a, 0x02, 0, 0}, + {0x312b, 0x0f, 0, 0}, + {0x312c, 0x00, 0, 0}, + {0x312d, 0x0f, 0, 0}, + {0x312e, 0x1d, 0, 0}, + {0x312f, 0x00, 0, 0}, + {0x3130, 0x00, 0, 0}, + {0x3131, 0x00, 0, 0}, + {0x3132, 0x00, 0, 0}, + {0x3140, 0x0a, 0, 0}, + {0x3141, 0x03, 0, 0}, + {0x3142, 0x00, 0, 0}, + {0x3143, 0x00, 0, 0}, + {0x3144, 0x00, 0, 0}, + {0x3145, 0x00, 0, 0}, + {0x3146, 0x00, 0, 0}, + {0x3147, 0x00, 0, 0}, + {0x3148, 0x00, 0, 0}, + {0x3149, 0x00, 0, 0}, + {0x314a, 0x00, 0, 0}, + {0x314b, 0x00, 0, 0}, + {0x314c, 0x00, 0, 0}, + {0x314d, 0x00, 0, 0}, + {0x314e, 0x1c, 0, 0}, + {0x314f, 0xff, 0, 0}, + {0x3150, 0xff, 0, 0}, + {0x3151, 0xff, 0, 0}, + {0x3152, 0x10, 0, 0}, + {0x3153, 0x10, 0, 0}, + {0x3154, 0x10, 0, 0}, + {0x3155, 0x00, 0, 0}, + {0x3156, 0x03, 0, 0}, + {0x3157, 0x00, 0, 0}, + {0x3158, 0x0f, 0, 0}, + {0x3159, 0xff, 0, 0}, + {0x315a, 0x01, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x00, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x00, 0, 0}, + {0x3160, 0x00, 0, 0}, + {0x3161, 0x40, 0, 0}, + {0x3162, 0x00, 0, 0}, + {0x3163, 0x40, 0, 0}, + {0x3164, 0x00, 0, 0}, + {0x3165, 0x40, 0, 0}, + {0x3190, 0x08, 0, 0}, + {0x3191, 0x99, 0, 0}, + {0x3193, 0x08, 0, 0}, + {0x3194, 0x13, 0, 0}, + {0x3195, 0x33, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x10, 0, 0}, + {0x3198, 0x00, 0, 0}, + {0x3199, 0x3f, 0, 0}, + {0x319a, 0x40, 0, 0}, + {0x319b, 0x7f, 0, 0}, + {0x319c, 0x80, 0, 0}, + {0x319d, 0xbf, 0, 0}, + {0x319e, 0xc0, 0, 0}, + {0x319f, 0xff, 0, 0}, + {0x31a0, 0x24, 0, 0}, + {0x31a1, 0x55, 0, 0}, + {0x31a2, 0x00, 0, 0}, + {0x31a3, 0x00, 0, 0}, + {0x31a6, 0x00, 0, 0}, + {0x31a7, 0x00, 0, 0}, + {0x31b0, 0x00, 0, 0}, + {0x31b1, 0x00, 0, 0}, + {0x31b2, 0x02, 0, 0}, + {0x31b3, 0x00, 0, 0}, + {0x31b4, 0x00, 0, 0}, + {0x31b5, 0x01, 0, 0}, + {0x31b6, 0x00, 0, 0}, + {0x31b7, 0x00, 0, 0}, + {0x31b8, 0x00, 0, 0}, + {0x31b9, 0x00, 0, 0}, + {0x31ba, 0x00, 0, 0}, + {0x31d0, 0x3c, 0, 0}, + {0x31d1, 0x34, 0, 0}, + {0x31d2, 0x3c, 0, 0}, + {0x31d3, 0x00, 0, 0}, + {0x31d4, 0x2d, 0, 0}, + {0x31d5, 0x00, 0, 0}, + {0x31d6, 0x01, 0, 0}, + {0x31d7, 0x06, 0, 0}, + {0x31d8, 0x00, 0, 0}, + {0x31d9, 0x64, 0, 0}, + {0x31da, 0x00, 0, 0}, + {0x31db, 0x30, 0, 0}, + {0x31dc, 0x04, 0, 0}, + {0x31dd, 0x69, 0, 0}, + {0x31de, 0x0a, 0, 0}, + {0x31df, 0x3c, 0, 0}, + {0x31e0, 0x04, 0, 0}, + {0x31e1, 0x32, 0, 0}, + {0x31e2, 0x00, 0, 0}, + {0x31e3, 0x00, 0, 0}, + {0x31e4, 0x08, 0, 0}, + {0x31e5, 0x80, 0, 0}, + {0x31e6, 0x00, 0, 0}, + {0x31e7, 0x2c, 0, 0}, + {0x31e8, 0x6c, 0, 0}, + {0x31e9, 0xac, 0, 0}, + {0x31ea, 0xec, 0, 0}, + {0x31eb, 0x3f, 0, 0}, + {0x31ec, 0x05, 0, 0}, + {0x31ed, 0x00, 0, 0}, + {0x31ee, 0x02, 0, 0}, + {0x31ef, 0xd0, 0, 0}, + {0x31f0, 0x05, 0, 0}, + {0x31f1, 0x00, 0, 0}, + {0x31f2, 0x02, 0, 0}, + {0x31f3, 0xd0, 0, 0}, + {0x31f4, 0x05, 0, 0}, + {0x31f5, 0x00, 0, 0}, + {0x31f6, 0x02, 0, 0}, + {0x31f7, 0xd0, 0, 0}, + {0x31f8, 0x05, 0, 0}, + {0x31f9, 0x00, 0, 0}, + {0x31fa, 0x02, 0, 0}, + {0x31fb, 0xd0, 0, 0}, + {0x31fd, 0xcb, 0, 0}, + {0x31fe, 0x0f, 0, 0}, + {0x31ff, 0x03, 0, 0}, + {0x3200, 0x00, 0, 0}, + {0x3201, 0xff, 0, 0}, + {0x3202, 0x00, 0, 0}, + {0x3203, 0xff, 0, 0}, + {0x3204, 0xff, 0, 0}, + {0x3205, 0xff, 0, 0}, + {0x3206, 0xff, 0, 0}, + {0x3207, 0xff, 0, 0}, + {0x3208, 0xff, 0, 0}, + {0x3209, 0xff, 0, 0}, + {0x320a, 0xff, 0, 0}, + {0x320b, 0x1b, 0, 0}, + {0x320c, 0x1f, 0, 0}, + {0x320d, 0x1e, 0, 0}, + {0x320e, 0x30, 0, 0}, + {0x320f, 0x2d, 0, 0}, + {0x3210, 0x2c, 0, 0}, + {0x3211, 0x2b, 0, 0}, + {0x3212, 0x2a, 0, 0}, + {0x3213, 0x24, 0, 0}, + {0x3214, 0x22, 0, 0}, + {0x3215, 0x00, 0, 0}, + {0x3216, 0x04, 0, 0}, + {0x3217, 0x2c, 0, 0}, + {0x3218, 0x6c, 0, 0}, + {0x3219, 0xac, 0, 0}, + {0x321a, 0xec, 0, 0}, + {0x321b, 0x00, 0, 0}, + {0x3230, 0x3a, 0, 0}, + {0x3231, 0x00, 0, 0}, + {0x3232, 0x80, 0, 0}, + {0x3233, 0x00, 0, 0}, + {0x3234, 0x10, 0, 0}, + {0x3235, 0xaa, 0, 0}, + {0x3236, 0x55, 0, 0}, + {0x3237, 0x99, 0, 0}, + {0x3238, 0x66, 0, 0}, + {0x3239, 0x08, 0, 0}, + {0x323a, 0x88, 0, 0}, + {0x323b, 0x00, 0, 0}, + {0x323c, 0x00, 0, 0}, + {0x323d, 0x03, 0, 0}, + {0x3250, 0x33, 0, 0}, + {0x3251, 0x00, 0, 0}, + {0x3252, 0x20, 0, 0}, + {0x3253, 0x00, 0, 0}, + {0x3254, 0x11, 0, 0}, + {0x3255, 0x01, 0, 0}, + {0x3256, 0x00, 0, 0}, + {0x3257, 0x00, 0, 0}, + {0x3258, 0x00, 0, 0}, + {0x3270, 0x01, 0, 0}, + {0x3271, 0x60, 0, 0}, + {0x3272, 0xc0, 0, 0}, + {0x3273, 0x00, 0, 0}, + {0x3274, 0x80, 0, 0}, + {0x3275, 0x40, 0, 0}, + {0x3276, 0x02, 0, 0}, + {0x3277, 0x08, 0, 0}, + {0x3278, 0x10, 0, 0}, + {0x3279, 0x04, 0, 0}, + {0x327a, 0x00, 0, 0}, + {0x327b, 0x03, 0, 0}, + {0x327c, 0x10, 0, 0}, + {0x327d, 0x60, 0, 0}, + {0x327e, 0xc0, 0, 0}, + {0x327f, 0x06, 0, 0}, + {0x3288, 0x10, 0, 0}, + {0x3289, 0x00, 0, 0}, + {0x328a, 0x08, 0, 0}, + {0x328b, 0x00, 0, 0}, + {0x328c, 0x04, 0, 0}, + {0x328d, 0x00, 0, 0}, + {0x328e, 0x02, 0, 0}, + {0x328f, 0x00, 0, 0}, + {0x3290, 0x20, 0, 0}, + {0x3291, 0x00, 0, 0}, + {0x3292, 0x10, 0, 0}, + {0x3293, 0x00, 0, 0}, + {0x3294, 0x08, 0, 0}, + {0x3295, 0x00, 0, 0}, + {0x3296, 0x04, 0, 0}, + {0x3297, 0x00, 0, 0}, + {0x3298, 0x40, 0, 0}, + {0x3299, 0x00, 0, 0}, + {0x329a, 0x20, 0, 0}, + {0x329b, 0x00, 0, 0}, + {0x329c, 0x10, 0, 0}, + {0x329d, 0x00, 0, 0}, + {0x329e, 0x08, 0, 0}, + {0x329f, 0x00, 0, 0}, + {0x32a0, 0x7f, 0, 0}, + {0x32a1, 0xff, 0, 0}, + {0x32a2, 0x40, 0, 0}, + {0x32a3, 0x00, 0, 0}, + {0x32a4, 0x20, 0, 0}, + {0x32a5, 0x00, 0, 0}, + {0x32a6, 0x10, 0, 0}, + {0x32a7, 0x00, 0, 0}, + {0x32a8, 0x00, 0, 0}, + {0x32a9, 0x00, 0, 0}, + {0x32aa, 0x00, 0, 0}, + {0x32ab, 0x00, 0, 0}, + {0x32ac, 0x00, 0, 0}, + {0x32ad, 0x00, 0, 0}, + {0x32ae, 0x00, 0, 0}, + {0x32af, 0x00, 0, 0}, + {0x32b0, 0x00, 0, 0}, + {0x32b1, 0x00, 0, 0}, + {0x32b2, 0x00, 0, 0}, + {0x32b3, 0x00, 0, 0}, + {0x32b4, 0x00, 0, 0}, + {0x32b5, 0x00, 0, 0}, + {0x32b6, 0x00, 0, 0}, + {0x32b7, 0x00, 0, 0}, + {0x32b8, 0x00, 0, 0}, + {0x32b9, 0x00, 0, 0}, + {0x32ba, 0x00, 0, 0}, + {0x32bb, 0x00, 0, 0}, + {0x32bc, 0x00, 0, 0}, + {0x32bd, 0x00, 0, 0}, + {0x32be, 0x00, 0, 0}, + {0x32bf, 0x00, 0, 0}, + {0x32c0, 0x00, 0, 0}, + {0x32c1, 0x00, 0, 0}, + {0x32c2, 0x00, 0, 0}, + {0x32c3, 0x00, 0, 0}, + {0x32c4, 0x00, 0, 0}, + {0x32c5, 0x00, 0, 0}, + {0x32c6, 0x00, 0, 0}, + {0x32c7, 0x00, 0, 0}, + {0x32c8, 0x87, 0, 0}, + {0x32c9, 0x00, 0, 0}, + {0x3330, 0x03, 0, 0}, + {0x3331, 0xc8, 0, 0}, + {0x3332, 0x02, 0, 0}, + {0x3333, 0x24, 0, 0}, + {0x3334, 0x00, 0, 0}, + {0x3335, 0x00, 0, 0}, + {0x3336, 0x00, 0, 0}, + {0x3337, 0x00, 0, 0}, + {0x3338, 0x03, 0, 0}, + {0x3339, 0xc8, 0, 0}, + {0x333a, 0x02, 0, 0}, + {0x333b, 0x24, 0, 0}, + {0x333c, 0x00, 0, 0}, + {0x333d, 0x00, 0, 0}, + {0x333e, 0x00, 0, 0}, + {0x333f, 0x00, 0, 0}, + {0x3340, 0x03, 0, 0}, + {0x3341, 0xc8, 0, 0}, + {0x3342, 0x02, 0, 0}, + {0x3343, 0x24, 0, 0}, + {0x3344, 0x00, 0, 0}, + {0x3345, 0x00, 0, 0}, + {0x3346, 0x00, 0, 0}, + {0x3347, 0x00, 0, 0}, + {0x3348, 0x40, 0, 0}, + {0x3349, 0x00, 0, 0}, + {0x334a, 0x00, 0, 0}, + {0x334b, 0x00, 0, 0}, + {0x334c, 0x00, 0, 0}, + {0x334d, 0x00, 0, 0}, + {0x334e, 0x80, 0, 0}, + {0x3360, 0x01, 0, 0}, + {0x3361, 0x00, 0, 0}, + {0x3362, 0x01, 0, 0}, + {0x3363, 0x00, 0, 0}, + {0x3364, 0x01, 0, 0}, + {0x3365, 0x00, 0, 0}, + {0x3366, 0x01, 0, 0}, + {0x3367, 0x00, 0, 0}, + {0x3368, 0x01, 0, 0}, + {0x3369, 0x00, 0, 0}, + {0x336a, 0x01, 0, 0}, + {0x336b, 0x00, 0, 0}, + {0x336c, 0x01, 0, 0}, + {0x336d, 0x00, 0, 0}, + {0x336e, 0x01, 0, 0}, + {0x336f, 0x00, 0, 0}, + {0x3370, 0x01, 0, 0}, + {0x3371, 0x00, 0, 0}, + {0x3372, 0x01, 0, 0}, + {0x3373, 0x00, 0, 0}, + {0x3374, 0x01, 0, 0}, + {0x3375, 0x00, 0, 0}, + {0x3376, 0x01, 0, 0}, + {0x3377, 0x00, 0, 0}, + {0x3378, 0x00, 0, 0}, + {0x3379, 0x00, 0, 0}, + {0x337a, 0x00, 0, 0}, + {0x337b, 0x00, 0, 0}, + {0x337c, 0x00, 0, 0}, + {0x337d, 0x00, 0, 0}, + {0x337e, 0x00, 0, 0}, + {0x337f, 0x00, 0, 0}, + {0x3380, 0x00, 0, 0}, + {0x3381, 0x00, 0, 0}, + {0x3382, 0x00, 0, 0}, + {0x3383, 0x00, 0, 0}, + {0x3384, 0x00, 0, 0}, + {0x3385, 0x00, 0, 0}, + {0x3386, 0x00, 0, 0}, + {0x3387, 0x00, 0, 0}, + {0x3388, 0x00, 0, 0}, + {0x3389, 0x00, 0, 0}, + {0x338a, 0x00, 0, 0}, + {0x338b, 0x00, 0, 0}, + {0x338c, 0x00, 0, 0}, + {0x338d, 0x00, 0, 0}, + {0x338e, 0x00, 0, 0}, + {0x338f, 0x00, 0, 0}, + {0x3390, 0x00, 0, 0}, + {0x3391, 0x00, 0, 0}, + {0x3392, 0x00, 0, 0}, + {0x3393, 0x00, 0, 0}, + {0x3394, 0x00, 0, 0}, + {0x3395, 0x00, 0, 0}, + {0x3396, 0x00, 0, 0}, + {0x3397, 0x00, 0, 0}, + {0x3398, 0x00, 0, 0}, + {0x3399, 0x00, 0, 0}, + {0x339a, 0x00, 0, 0}, + {0x339b, 0x00, 0, 0}, + {0x33b0, 0x00, 0, 0}, + {0x33b1, 0x50, 0, 0}, + {0x33b2, 0x01, 0, 0}, + {0x33b3, 0xff, 0, 0}, + {0x33b4, 0xe0, 0, 0}, + {0x33b5, 0x6b, 0, 0}, + {0x33b6, 0x00, 0, 0}, + {0x33b7, 0x00, 0, 0}, + {0x33b8, 0x00, 0, 0}, + {0x33b9, 0x00, 0, 0}, + {0x33ba, 0x00, 0, 0}, + {0x33bb, 0x1f, 0, 0}, + {0x33bc, 0x01, 0, 0}, + {0x33bd, 0x01, 0, 0}, + {0x33be, 0x01, 0, 0}, + {0x33bf, 0x01, 0, 0}, + {0x33c0, 0x00, 0, 0}, + {0x33c1, 0x00, 0, 0}, + {0x33c2, 0x00, 0, 0}, + {0x33c3, 0x00, 0, 0}, + {0x33e0, 0x14, 0, 0}, + {0x33e1, 0x0f, 0, 0}, + {0x33e2, 0x04, 0, 0}, + {0x33e3, 0x02, 0, 0}, + {0x33e4, 0x01, 0, 0}, + {0x33e5, 0x01, 0, 0}, + {0x33e6, 0x00, 0, 0}, + {0x33e7, 0x04, 0, 0}, + {0x33e8, 0x0c, 0, 0}, + {0x33e9, 0x02, 0, 0}, + {0x33ea, 0x02, 0, 0}, + {0x33eb, 0x02, 0, 0}, + {0x33ec, 0x03, 0, 0}, + {0x33ed, 0x02, 0, 0}, + {0x33ee, 0x05, 0, 0}, + {0x33ef, 0x0a, 0, 0}, + {0x33f0, 0x08, 0, 0}, + {0x33f1, 0x04, 0, 0}, + {0x33f2, 0x04, 0, 0}, + {0x33f3, 0x00, 0, 0}, + {0x33f4, 0x03, 0, 0}, + {0x33f5, 0x14, 0, 0}, + {0x33f6, 0x0f, 0, 0}, + {0x33f7, 0x02, 0, 0}, + {0x33f8, 0x01, 0, 0}, + {0x33f9, 0x01, 0, 0}, + {0x33fa, 0x01, 0, 0}, + {0x33fb, 0x00, 0, 0}, + {0x33fc, 0x04, 0, 0}, + {0x33fd, 0x0c, 0, 0}, + {0x33fe, 0x02, 0, 0}, + {0x33ff, 0x02, 0, 0}, + {0x3400, 0x02, 0, 0}, + {0x3401, 0x03, 0, 0}, + {0x3402, 0x01, 0, 0}, + {0x3403, 0x02, 0, 0}, + {0x3404, 0x08, 0, 0}, + {0x3405, 0x08, 0, 0}, + {0x3406, 0x04, 0, 0}, + {0x3407, 0x04, 0, 0}, + {0x3408, 0x00, 0, 0}, + {0x3409, 0x03, 0, 0}, + {0x340a, 0x14, 0, 0}, + {0x340b, 0x0f, 0, 0}, + {0x340c, 0x04, 0, 0}, + {0x340d, 0x02, 0, 0}, + {0x340e, 0x01, 0, 0}, + {0x340f, 0x01, 0, 0}, + {0x3410, 0x00, 0, 0}, + {0x3411, 0x04, 0, 0}, + {0x3412, 0x0c, 0, 0}, + {0x3413, 0x02, 0, 0}, + {0x3414, 0x02, 0, 0}, + {0x3415, 0x02, 0, 0}, + {0x3416, 0x03, 0, 0}, + {0x3417, 0x02, 0, 0}, + {0x3418, 0x05, 0, 0}, + {0x3419, 0x0a, 0, 0}, + {0x341a, 0x08, 0, 0}, + {0x341b, 0x04, 0, 0}, + {0x341c, 0x04, 0, 0}, + {0x341d, 0x00, 0, 0}, + {0x341e, 0x03, 0, 0}, + {0x3440, 0x00, 0, 0}, + {0x3441, 0x00, 0, 0}, + {0x3442, 0x00, 0, 0}, + {0x3443, 0x00, 0, 0}, + {0x3444, 0x02, 0, 0}, + {0x3445, 0xf0, 0, 0}, + {0x3446, 0x02, 0, 0}, + {0x3447, 0x08, 0, 0}, + {0x3448, 0x00, 0, 0}, + {0x3460, 0x40, 0, 0}, + {0x3461, 0x40, 0, 0}, + {0x3462, 0x40, 0, 0}, + {0x3463, 0x40, 0, 0}, + {0x3464, 0x03, 0, 0}, + {0x3465, 0x01, 0, 0}, + {0x3466, 0x01, 0, 0}, + {0x3467, 0x02, 0, 0}, + {0x3468, 0x30, 0, 0}, + {0x3469, 0x00, 0, 0}, + {0x346a, 0x35, 0, 0}, + {0x346b, 0x00, 0, 0}, + {0x3480, 0x40, 0, 0}, + {0x3481, 0x00, 0, 0}, + {0x3482, 0x00, 0, 0}, + {0x3483, 0x00, 0, 0}, + {0x3484, 0x0d, 0, 0}, + {0x3485, 0x00, 0, 0}, + {0x3486, 0x00, 0, 0}, + {0x3487, 0x00, 0, 0}, + {0x3488, 0x00, 0, 0}, + {0x3489, 0x00, 0, 0}, + {0x348a, 0x00, 0, 0}, + {0x348b, 0x04, 0, 0}, + {0x348c, 0x00, 0, 0}, + {0x348d, 0x01, 0, 0}, + {0x348f, 0x01, 0, 0}, + {0x3030, 0x0a, 0, 0}, + {0x3030, 0x02, 0, 0}, + {0x7000, 0x58, 0, 0}, + {0x7001, 0x7a, 0, 0}, + {0x7002, 0x1a, 0, 0}, + {0x7003, 0xc1, 0, 0}, + {0x7004, 0x03, 0, 0}, + {0x7005, 0xda, 0, 0}, + {0x7006, 0xbd, 0, 0}, + {0x7007, 0x03, 0, 0}, + {0x7008, 0xbd, 0, 0}, + {0x7009, 0x06, 0, 0}, + {0x700a, 0xe6, 0, 0}, + {0x700b, 0xec, 0, 0}, + {0x700c, 0xbc, 0, 0}, + {0x700d, 0xff, 0, 0}, + {0x700e, 0xbc, 0, 0}, + {0x700f, 0x73, 0, 0}, + {0x7010, 0xda, 0, 0}, + {0x7011, 0x72, 0, 0}, + {0x7012, 0x76, 0, 0}, + {0x7013, 0xb6, 0, 0}, + {0x7014, 0xee, 0, 0}, + {0x7015, 0xcf, 0, 0}, + {0x7016, 0xac, 0, 0}, + {0x7017, 0xd0, 0, 0}, + {0x7018, 0xac, 0, 0}, + {0x7019, 0xd1, 0, 0}, + {0x701a, 0x50, 0, 0}, + {0x701b, 0xac, 0, 0}, + {0x701c, 0xd2, 0, 0}, + {0x701d, 0xbc, 0, 0}, + {0x701e, 0x2e, 0, 0}, + {0x701f, 0xb4, 0, 0}, + {0x7020, 0x00, 0, 0}, + {0x7021, 0xdc, 0, 0}, + {0x7022, 0xdf, 0, 0}, + {0x7023, 0xb0, 0, 0}, + {0x7024, 0x6e, 0, 0}, + {0x7025, 0xbd, 0, 0}, + {0x7026, 0x01, 0, 0}, + {0x7027, 0xd7, 0, 0}, + {0x7028, 0xed, 0, 0}, + {0x7029, 0xe1, 0, 0}, + {0x702a, 0x36, 0, 0}, + {0x702b, 0x30, 0, 0}, + {0x702c, 0xd3, 0, 0}, + {0x702d, 0x2e, 0, 0}, + {0x702e, 0x54, 0, 0}, + {0x702f, 0x46, 0, 0}, + {0x7030, 0xbc, 0, 0}, + {0x7031, 0x22, 0, 0}, + {0x7032, 0x66, 0, 0}, + {0x7033, 0xbc, 0, 0}, + {0x7034, 0x24, 0, 0}, + {0x7035, 0x2c, 0, 0}, + {0x7036, 0x28, 0, 0}, + {0x7037, 0xbc, 0, 0}, + {0x7038, 0x3c, 0, 0}, + {0x7039, 0xa1, 0, 0}, + {0x703a, 0xac, 0, 0}, + {0x703b, 0xd8, 0, 0}, + {0x703c, 0xd6, 0, 0}, + {0x703d, 0xb4, 0, 0}, + {0x703e, 0x04, 0, 0}, + {0x703f, 0x46, 0, 0}, + {0x7040, 0xb7, 0, 0}, + {0x7041, 0x04, 0, 0}, + {0x7042, 0xbe, 0, 0}, + {0x7043, 0x08, 0, 0}, + {0x7044, 0xc3, 0, 0}, + {0x7045, 0xd9, 0, 0}, + {0x7046, 0xad, 0, 0}, + {0x7047, 0xc3, 0, 0}, + {0x7048, 0xbc, 0, 0}, + {0x7049, 0x19, 0, 0}, + {0x704a, 0xc1, 0, 0}, + {0x704b, 0x27, 0, 0}, + {0x704c, 0xe7, 0, 0}, + {0x704d, 0x00, 0, 0}, + {0x704e, 0x50, 0, 0}, + {0x704f, 0x20, 0, 0}, + {0x7050, 0xb8, 0, 0}, + {0x7051, 0x02, 0, 0}, + {0x7052, 0xbc, 0, 0}, + {0x7053, 0x17, 0, 0}, + {0x7054, 0xdb, 0, 0}, + {0x7055, 0xc7, 0, 0}, + {0x7056, 0xb8, 0, 0}, + {0x7057, 0x00, 0, 0}, + {0x7058, 0x28, 0, 0}, + {0x7059, 0x54, 0, 0}, + {0x705a, 0xb4, 0, 0}, + {0x705b, 0x14, 0, 0}, + {0x705c, 0xab, 0, 0}, + {0x705d, 0xbe, 0, 0}, + {0x705e, 0x06, 0, 0}, + {0x705f, 0xd8, 0, 0}, + {0x7060, 0xd6, 0, 0}, + {0x7061, 0x00, 0, 0}, + {0x7062, 0xb4, 0, 0}, + {0x7063, 0xc7, 0, 0}, + {0x7064, 0x07, 0, 0}, + {0x7065, 0xb9, 0, 0}, + {0x7066, 0x05, 0, 0}, + {0x7067, 0xee, 0, 0}, + {0x7068, 0xe6, 0, 0}, + {0x7069, 0xad, 0, 0}, + {0x706a, 0xb4, 0, 0}, + {0x706b, 0x26, 0, 0}, + {0x706c, 0x19, 0, 0}, + {0x706d, 0xc1, 0, 0}, + {0x706e, 0x3a, 0, 0}, + {0x706f, 0xc3, 0, 0}, + {0x7070, 0xaf, 0, 0}, + {0x7071, 0x00, 0, 0}, + {0x7072, 0xc0, 0, 0}, + {0x7073, 0x3c, 0, 0}, + {0x7074, 0xc3, 0, 0}, + {0x7075, 0xbe, 0, 0}, + {0x7076, 0xe7, 0, 0}, + {0x7077, 0x00, 0, 0}, + {0x7078, 0x15, 0, 0}, + {0x7079, 0xc2, 0, 0}, + {0x707a, 0x40, 0, 0}, + {0x707b, 0xc3, 0, 0}, + {0x707c, 0xa4, 0, 0}, + {0x707d, 0xc0, 0, 0}, + {0x707e, 0x3c, 0, 0}, + {0x707f, 0x00, 0, 0}, + {0x7080, 0xb9, 0, 0}, + {0x7081, 0x64, 0, 0}, + {0x7082, 0x29, 0, 0}, + {0x7083, 0x00, 0, 0}, + {0x7084, 0xb8, 0, 0}, + {0x7085, 0x12, 0, 0}, + {0x7086, 0xbe, 0, 0}, + {0x7087, 0x01, 0, 0}, + {0x7088, 0xd0, 0, 0}, + {0x7089, 0xbc, 0, 0}, + {0x708a, 0x01, 0, 0}, + {0x708b, 0xac, 0, 0}, + {0x708c, 0x37, 0, 0}, + {0x708d, 0xd2, 0, 0}, + {0x708e, 0xac, 0, 0}, + {0x708f, 0x45, 0, 0}, + {0x7090, 0xad, 0, 0}, + {0x7091, 0x28, 0, 0}, + {0x7092, 0x00, 0, 0}, + {0x7093, 0xb8, 0, 0}, + {0x7094, 0x00, 0, 0}, + {0x7095, 0xbc, 0, 0}, + {0x7096, 0x01, 0, 0}, + {0x7097, 0x36, 0, 0}, + {0x7098, 0xd3, 0, 0}, + {0x7099, 0x30, 0, 0}, + {0x709a, 0x04, 0, 0}, + {0x709b, 0xe0, 0, 0}, + {0x709c, 0xd8, 0, 0}, + {0x709d, 0xb4, 0, 0}, + {0x709e, 0xe9, 0, 0}, + {0x709f, 0x00, 0, 0}, + {0x70a0, 0xbe, 0, 0}, + {0x70a1, 0x05, 0, 0}, + {0x70a2, 0x62, 0, 0}, + {0x70a3, 0x07, 0, 0}, + {0x70a4, 0xb9, 0, 0}, + {0x70a5, 0x05, 0, 0}, + {0x70a6, 0xad, 0, 0}, + {0x70a7, 0xc3, 0, 0}, + {0x70a8, 0xcf, 0, 0}, + {0x70a9, 0x00, 0, 0}, + {0x70aa, 0x15, 0, 0}, + {0x70ab, 0xc2, 0, 0}, + {0x70ac, 0x59, 0, 0}, + {0x70ad, 0xc3, 0, 0}, + {0x70ae, 0xc9, 0, 0}, + {0x70af, 0xc0, 0, 0}, + {0x70b0, 0x55, 0, 0}, + {0x70b1, 0x00, 0, 0}, + {0x70b2, 0x46, 0, 0}, + {0x70b3, 0xa1, 0, 0}, + {0x70b4, 0xb9, 0, 0}, + {0x70b5, 0x64, 0, 0}, + {0x70b6, 0x29, 0, 0}, + {0x70b7, 0x00, 0, 0}, + {0x70b8, 0xb8, 0, 0}, + {0x70b9, 0x02, 0, 0}, + {0x70ba, 0xbe, 0, 0}, + {0x70bb, 0x02, 0, 0}, + {0x70bc, 0xd0, 0, 0}, + {0x70bd, 0xdc, 0, 0}, + {0x70be, 0xac, 0, 0}, + {0x70bf, 0xbc, 0, 0}, + {0x70c0, 0x01, 0, 0}, + {0x70c1, 0x37, 0, 0}, + {0x70c2, 0xac, 0, 0}, + {0x70c3, 0xd2, 0, 0}, + {0x70c4, 0x45, 0, 0}, + {0x70c5, 0xad, 0, 0}, + {0x70c6, 0x28, 0, 0}, + {0x70c7, 0x00, 0, 0}, + {0x70c8, 0xb8, 0, 0}, + {0x70c9, 0x00, 0, 0}, + {0x70ca, 0xbc, 0, 0}, + {0x70cb, 0x01, 0, 0}, + {0x70cc, 0x36, 0, 0}, + {0x70cd, 0x30, 0, 0}, + {0x70ce, 0xe0, 0, 0}, + {0x70cf, 0xd8, 0, 0}, + {0x70d0, 0xb5, 0, 0}, + {0x70d1, 0x0b, 0, 0}, + {0x70d2, 0xd6, 0, 0}, + {0x70d3, 0xbe, 0, 0}, + {0x70d4, 0x07, 0, 0}, + {0x70d5, 0x00, 0, 0}, + {0x70d6, 0x62, 0, 0}, + {0x70d7, 0x07, 0, 0}, + {0x70d8, 0xb9, 0, 0}, + {0x70d9, 0x05, 0, 0}, + {0x70da, 0xad, 0, 0}, + {0x70db, 0xc3, 0, 0}, + {0x70dc, 0xcf, 0, 0}, + {0x70dd, 0x46, 0, 0}, + {0x70de, 0xcd, 0, 0}, + {0x70df, 0x07, 0, 0}, + {0x70e0, 0xcd, 0, 0}, + {0x70e1, 0x00, 0, 0}, + {0x70e2, 0xe3, 0, 0}, + {0x70e3, 0x18, 0, 0}, + {0x70e4, 0xc2, 0, 0}, + {0x70e5, 0xa2, 0, 0}, + {0x70e6, 0xb9, 0, 0}, + {0x70e7, 0x64, 0, 0}, + {0x70e8, 0xd1, 0, 0}, + {0x70e9, 0xdd, 0, 0}, + {0x70ea, 0xac, 0, 0}, + {0x70eb, 0xcf, 0, 0}, + {0x70ec, 0xdf, 0, 0}, + {0x70ed, 0xb5, 0, 0}, + {0x70ee, 0x19, 0, 0}, + {0x70ef, 0x46, 0, 0}, + {0x70f0, 0x50, 0, 0}, + {0x70f1, 0xb6, 0, 0}, + {0x70f2, 0xee, 0, 0}, + {0x70f3, 0xe8, 0, 0}, + {0x70f4, 0xe6, 0, 0}, + {0x70f5, 0xbc, 0, 0}, + {0x70f6, 0x31, 0, 0}, + {0x70f7, 0xe1, 0, 0}, + {0x70f8, 0x36, 0, 0}, + {0x70f9, 0x30, 0, 0}, + {0x70fa, 0xd3, 0, 0}, + {0x70fb, 0x2e, 0, 0}, + {0x70fc, 0x54, 0, 0}, + {0x70fd, 0xbd, 0, 0}, + {0x70fe, 0x03, 0, 0}, + {0x70ff, 0xec, 0, 0}, + {0x7100, 0x2c, 0, 0}, + {0x7101, 0x50, 0, 0}, + {0x7102, 0x20, 0, 0}, + {0x7103, 0x04, 0, 0}, + {0x7104, 0xb8, 0, 0}, + {0x7105, 0x02, 0, 0}, + {0x7106, 0xbc, 0, 0}, + {0x7107, 0x18, 0, 0}, + {0x7108, 0xc7, 0, 0}, + {0x7109, 0xb8, 0, 0}, + {0x710a, 0x00, 0, 0}, + {0x710b, 0x28, 0, 0}, + {0x710c, 0x54, 0, 0}, + {0x710d, 0xbc, 0, 0}, + {0x710e, 0x02, 0, 0}, + {0x710f, 0xb4, 0, 0}, + {0x7110, 0xda, 0, 0}, + {0x7111, 0xbe, 0, 0}, + {0x7112, 0x04, 0, 0}, + {0x7113, 0xd6, 0, 0}, + {0x7114, 0xd8, 0, 0}, + {0x7115, 0xab, 0, 0}, + {0x7116, 0x00, 0, 0}, + {0x7117, 0x62, 0, 0}, + {0x7118, 0x07, 0, 0}, + {0x7119, 0xb9, 0, 0}, + {0x711a, 0x05, 0, 0}, + {0x711b, 0xad, 0, 0}, + {0x711c, 0xc3, 0, 0}, + {0x711d, 0xbc, 0, 0}, + {0x711e, 0xe7, 0, 0}, + {0x711f, 0xb9, 0, 0}, + {0x7120, 0x64, 0, 0}, + {0x7121, 0x29, 0, 0}, + {0x7122, 0x00, 0, 0}, + {0x7123, 0xb8, 0, 0}, + {0x7124, 0x02, 0, 0}, + {0x7125, 0xbe, 0, 0}, + {0x7126, 0x00, 0, 0}, + {0x7127, 0x45, 0, 0}, + {0x7128, 0xad, 0, 0}, + {0x7129, 0xe2, 0, 0}, + {0x712a, 0x28, 0, 0}, + {0x712b, 0x00, 0, 0}, + {0x712c, 0xb8, 0, 0}, + {0x712d, 0x00, 0, 0}, + {0x712e, 0xe0, 0, 0}, + {0x712f, 0xd8, 0, 0}, + {0x7130, 0xb4, 0, 0}, + {0x7131, 0xe9, 0, 0}, + {0x7132, 0xbe, 0, 0}, + {0x7133, 0x03, 0, 0}, + {0x7134, 0x00, 0, 0}, + {0x7135, 0x30, 0, 0}, + {0x7136, 0x62, 0, 0}, + {0x7137, 0x07, 0, 0}, + {0x7138, 0xb9, 0, 0}, + {0x7139, 0x05, 0, 0}, + {0x713a, 0xad, 0, 0}, + {0x713b, 0xc3, 0, 0}, + {0x713c, 0xcf, 0, 0}, + {0x713d, 0x42, 0, 0}, + {0x713e, 0xe4, 0, 0}, + {0x713f, 0xcd, 0, 0}, + {0x7140, 0x07, 0, 0}, + {0x7141, 0xcd, 0, 0}, + {0x7142, 0x00, 0, 0}, + {0x7143, 0x00, 0, 0}, + {0x7144, 0x17, 0, 0}, + {0x7145, 0xc2, 0, 0}, + {0x7146, 0xbb, 0, 0}, + {0x7147, 0xde, 0, 0}, + {0x7148, 0xcf, 0, 0}, + {0x7149, 0xdf, 0, 0}, + {0x714a, 0xac, 0, 0}, + {0x714b, 0xd1, 0, 0}, + {0x714c, 0x44, 0, 0}, + {0x714d, 0xac, 0, 0}, + {0x714e, 0xb9, 0, 0}, + {0x714f, 0x76, 0, 0}, + {0x7150, 0xb8, 0, 0}, + {0x7151, 0x08, 0, 0}, + {0x7152, 0xb6, 0, 0}, + {0x7153, 0xfe, 0, 0}, + {0x7154, 0xb4, 0, 0}, + {0x7155, 0xca, 0, 0}, + {0x7156, 0xd6, 0, 0}, + {0x7157, 0xd8, 0, 0}, + {0x7158, 0xab, 0, 0}, + {0x7159, 0x00, 0, 0}, + {0x715a, 0xe1, 0, 0}, + {0x715b, 0x36, 0, 0}, + {0x715c, 0x30, 0, 0}, + {0x715d, 0xd3, 0, 0}, + {0x715e, 0xbc, 0, 0}, + {0x715f, 0x29, 0, 0}, + {0x7160, 0xb4, 0, 0}, + {0x7161, 0x1f, 0, 0}, + {0x7162, 0xaa, 0, 0}, + {0x7163, 0xbd, 0, 0}, + {0x7164, 0x01, 0, 0}, + {0x7165, 0xb8, 0, 0}, + {0x7166, 0x0c, 0, 0}, + {0x7167, 0x45, 0, 0}, + {0x7168, 0xa4, 0, 0}, + {0x7169, 0xbd, 0, 0}, + {0x716a, 0x03, 0, 0}, + {0x716b, 0xec, 0, 0}, + {0x716c, 0xbc, 0, 0}, + {0x716d, 0x3d, 0, 0}, + {0x716e, 0xc3, 0, 0}, + {0x716f, 0xcf, 0, 0}, + {0x7170, 0x42, 0, 0}, + {0x7171, 0xb8, 0, 0}, + {0x7172, 0x00, 0, 0}, + {0x7173, 0xe4, 0, 0}, + {0x7174, 0xd5, 0, 0}, + {0x7175, 0x00, 0, 0}, + {0x7176, 0xb6, 0, 0}, + {0x7177, 0x00, 0, 0}, + {0x7178, 0x74, 0, 0}, + {0x7179, 0xbd, 0, 0}, + {0x717a, 0x03, 0, 0}, + {0x717b, 0xb5, 0, 0}, + {0x717c, 0x39, 0, 0}, + {0x717d, 0x40, 0, 0}, + {0x717e, 0x58, 0, 0}, + {0x717f, 0xdd, 0, 0}, + {0x7180, 0x19, 0, 0}, + {0x7181, 0xc1, 0, 0}, + {0x7182, 0xc8, 0, 0}, + {0x7183, 0xbd, 0, 0}, + {0x7184, 0x06, 0, 0}, + {0x7185, 0x17, 0, 0}, + {0x7186, 0xc1, 0, 0}, + {0x7187, 0xc6, 0, 0}, + {0x7188, 0xe8, 0, 0}, + {0x7189, 0x00, 0, 0}, + {0x718a, 0xc0, 0, 0}, + {0x718b, 0xc8, 0, 0}, + {0x718c, 0xe6, 0, 0}, + {0x718d, 0x95, 0, 0}, + {0x718e, 0x15, 0, 0}, + {0x718f, 0x00, 0, 0}, + {0x7190, 0xbc, 0, 0}, + {0x7191, 0x19, 0, 0}, + {0x7192, 0xb9, 0, 0}, + {0x7193, 0xf6, 0, 0}, + {0x7194, 0x14, 0, 0}, + {0x7195, 0xc1, 0, 0}, + {0x7196, 0xd0, 0, 0}, + {0x7197, 0xd1, 0, 0}, + {0x7198, 0xac, 0, 0}, + {0x7199, 0x37, 0, 0}, + {0x719a, 0xbc, 0, 0}, + {0x719b, 0x35, 0, 0}, + {0x719c, 0x36, 0, 0}, + {0x719d, 0x30, 0, 0}, + {0x719e, 0xe1, 0, 0}, + {0x719f, 0xd3, 0, 0}, + {0x71a0, 0x7a, 0, 0}, + {0x71a1, 0xb6, 0, 0}, + {0x71a2, 0x0c, 0, 0}, + {0x71a3, 0xff, 0, 0}, + {0x71a4, 0xb4, 0, 0}, + {0x71a5, 0xc7, 0, 0}, + {0x71a6, 0xd9, 0, 0}, + {0x71a7, 0x00, 0, 0}, + {0x71a8, 0xbd, 0, 0}, + {0x71a9, 0x01, 0, 0}, + {0x71aa, 0x56, 0, 0}, + {0x71ab, 0xc0, 0, 0}, + {0x71ac, 0xda, 0, 0}, + {0x71ad, 0xb4, 0, 0}, + {0x71ae, 0x1f, 0, 0}, + {0x71af, 0x56, 0, 0}, + {0x71b0, 0xaa, 0, 0}, + {0x71b1, 0xbc, 0, 0}, + {0x71b2, 0x08, 0, 0}, + {0x71b3, 0x00, 0, 0}, + {0x71b4, 0x57, 0, 0}, + {0x71b5, 0xe8, 0, 0}, + {0x71b6, 0xb5, 0, 0}, + {0x71b7, 0x36, 0, 0}, + {0x71b8, 0x00, 0, 0}, + {0x71b9, 0x54, 0, 0}, + {0x71ba, 0xe7, 0, 0}, + {0x71bb, 0xc8, 0, 0}, + {0x71bc, 0xb4, 0, 0}, + {0x71bd, 0x1f, 0, 0}, + {0x71be, 0x56, 0, 0}, + {0x71bf, 0xaa, 0, 0}, + {0x71c0, 0xbc, 0, 0}, + {0x71c1, 0x08, 0, 0}, + {0x71c2, 0x57, 0, 0}, + {0x71c3, 0x00, 0, 0}, + {0x71c4, 0xb5, 0, 0}, + {0x71c5, 0x36, 0, 0}, + {0x71c6, 0x00, 0, 0}, + {0x71c7, 0x54, 0, 0}, + {0x71c8, 0xc8, 0, 0}, + {0x71c9, 0xb5, 0, 0}, + {0x71ca, 0x18, 0, 0}, + {0x71cb, 0xd9, 0, 0}, + {0x71cc, 0x00, 0, 0}, + {0x71cd, 0xbd, 0, 0}, + {0x71ce, 0x01, 0, 0}, + {0x71cf, 0x56, 0, 0}, + {0x71d0, 0x08, 0, 0}, + {0x71d1, 0x57, 0, 0}, + {0x71d2, 0xe8, 0, 0}, + {0x71d3, 0xb4, 0, 0}, + {0x71d4, 0x42, 0, 0}, + {0x71d5, 0x00, 0, 0}, + {0x71d6, 0x54, 0, 0}, + {0x71d7, 0xe7, 0, 0}, + {0x71d8, 0xc8, 0, 0}, + {0x71d9, 0xab, 0, 0}, + {0x71da, 0x00, 0, 0}, + {0x71db, 0x66, 0, 0}, + {0x71dc, 0x62, 0, 0}, + {0x71dd, 0x06, 0, 0}, + {0x71de, 0x74, 0, 0}, + {0x71df, 0xb9, 0, 0}, + {0x71e0, 0x05, 0, 0}, + {0x71e1, 0xb7, 0, 0}, + {0x71e2, 0x14, 0, 0}, + {0x71e3, 0x0e, 0, 0}, + {0x71e4, 0xb7, 0, 0}, + {0x71e5, 0x04, 0, 0}, + {0x71e6, 0xc8, 0, 0}, + {0x7600, 0x04, 0, 0}, + {0x7601, 0x80, 0, 0}, + {0x7602, 0x07, 0, 0}, + {0x7603, 0x44, 0, 0}, + {0x7604, 0x05, 0, 0}, + {0x7605, 0x33, 0, 0}, + {0x7606, 0x0f, 0, 0}, + {0x7607, 0x00, 0, 0}, + {0x7608, 0x07, 0, 0}, + {0x7609, 0x40, 0, 0}, + {0x760a, 0x04, 0, 0}, + {0x760b, 0xe5, 0, 0}, + {0x760c, 0x06, 0, 0}, + {0x760d, 0x50, 0, 0}, + {0x760e, 0x04, 0, 0}, + {0x760f, 0xe4, 0, 0}, + {0x7610, 0x00, 0, 0}, + {0x7611, 0x00, 0, 0}, + {0x7612, 0x06, 0, 0}, + {0x7613, 0x5c, 0, 0}, + {0x7614, 0x00, 0, 0}, + {0x7615, 0x0f, 0, 0}, + {0x7616, 0x06, 0, 0}, + {0x7617, 0x1c, 0, 0}, + {0x7618, 0x00, 0, 0}, + {0x7619, 0x02, 0, 0}, + {0x761a, 0x06, 0, 0}, + {0x761b, 0xa2, 0, 0}, + {0x761c, 0x00, 0, 0}, + {0x761d, 0x01, 0, 0}, + {0x761e, 0x06, 0, 0}, + {0x761f, 0xae, 0, 0}, + {0x7620, 0x00, 0, 0}, + {0x7621, 0x0e, 0, 0}, + {0x7622, 0x05, 0, 0}, + {0x7623, 0x30, 0, 0}, + {0x7624, 0x07, 0, 0}, + {0x7625, 0x00, 0, 0}, + {0x7626, 0x0f, 0, 0}, + {0x7627, 0x00, 0, 0}, + {0x7628, 0x04, 0, 0}, + {0x7629, 0xe5, 0, 0}, + {0x762a, 0x05, 0, 0}, + {0x762b, 0x33, 0, 0}, + {0x762c, 0x06, 0, 0}, + {0x762d, 0x12, 0, 0}, + {0x762e, 0x00, 0, 0}, + {0x762f, 0x01, 0, 0}, + {0x7630, 0x06, 0, 0}, + {0x7631, 0x52, 0, 0}, + {0x7632, 0x00, 0, 0}, + {0x7633, 0x01, 0, 0}, + {0x7634, 0x06, 0, 0}, + {0x7635, 0x5e, 0, 0}, + {0x7636, 0x04, 0, 0}, + {0x7637, 0xe4, 0, 0}, + {0x7638, 0x00, 0, 0}, + {0x7639, 0x01, 0, 0}, + {0x763a, 0x05, 0, 0}, + {0x763b, 0x30, 0, 0}, + {0x763c, 0x0f, 0, 0}, + {0x763d, 0x00, 0, 0}, + {0x763e, 0x06, 0, 0}, + {0x763f, 0xa6, 0, 0}, + {0x7640, 0x00, 0, 0}, + {0x7641, 0x02, 0, 0}, + {0x7642, 0x06, 0, 0}, + {0x7643, 0x26, 0, 0}, + {0x7644, 0x00, 0, 0}, + {0x7645, 0x02, 0, 0}, + {0x7646, 0x05, 0, 0}, + {0x7647, 0x33, 0, 0}, + {0x7648, 0x06, 0, 0}, + {0x7649, 0x20, 0, 0}, + {0x764a, 0x0f, 0, 0}, + {0x764b, 0x00, 0, 0}, + {0x764c, 0x06, 0, 0}, + {0x764d, 0x56, 0, 0}, + {0x764e, 0x00, 0, 0}, + {0x764f, 0x02, 0, 0}, + {0x7650, 0x06, 0, 0}, + {0x7651, 0x16, 0, 0}, + {0x7652, 0x05, 0, 0}, + {0x7653, 0x33, 0, 0}, + {0x7654, 0x06, 0, 0}, + {0x7655, 0x10, 0, 0}, + {0x7656, 0x0f, 0, 0}, + {0x7657, 0x00, 0, 0}, + {0x7658, 0x06, 0, 0}, + {0x7659, 0x10, 0, 0}, + {0x765a, 0x0f, 0, 0}, + {0x765b, 0x00, 0, 0}, + {0x765c, 0x06, 0, 0}, + {0x765d, 0x20, 0, 0}, + {0x765e, 0x0f, 0, 0}, + {0x765f, 0x00, 0, 0}, + {0x7660, 0x00, 0, 0}, + {0x7661, 0x00, 0, 0}, + {0x7662, 0x00, 0, 0}, + {0x7663, 0x02, 0, 0}, + {0x7664, 0x04, 0, 0}, + {0x7665, 0xe5, 0, 0}, + {0x7666, 0x04, 0, 0}, + {0x7667, 0xe4, 0, 0}, + {0x7668, 0x0f, 0, 0}, + {0x7669, 0x00, 0, 0}, + {0x766a, 0x00, 0, 0}, + {0x766b, 0x00, 0, 0}, + {0x766c, 0x00, 0, 0}, + {0x766d, 0x01, 0, 0}, + {0x766e, 0x04, 0, 0}, + {0x766f, 0xe5, 0, 0}, + {0x7670, 0x04, 0, 0}, + {0x7671, 0xe4, 0, 0}, + {0x7672, 0x0f, 0, 0}, + {0x7673, 0x00, 0, 0}, + {0x7674, 0x00, 0, 0}, + {0x7675, 0x02, 0, 0}, + {0x7676, 0x04, 0, 0}, + {0x7677, 0xe4, 0, 0}, + {0x7678, 0x00, 0, 0}, + {0x7679, 0x02, 0, 0}, + {0x767a, 0x04, 0, 0}, + {0x767b, 0xc4, 0, 0}, + {0x767c, 0x00, 0, 0}, + {0x767d, 0x02, 0, 0}, + {0x767e, 0x04, 0, 0}, + {0x767f, 0xc4, 0, 0}, + {0x7680, 0x05, 0, 0}, + {0x7681, 0x83, 0, 0}, + {0x7682, 0x0f, 0, 0}, + {0x7683, 0x00, 0, 0}, + {0x7684, 0x00, 0, 0}, + {0x7685, 0x02, 0, 0}, + {0x7686, 0x04, 0, 0}, + {0x7687, 0xe4, 0, 0}, + {0x7688, 0x00, 0, 0}, + {0x7689, 0x02, 0, 0}, + {0x768a, 0x04, 0, 0}, + {0x768b, 0xc4, 0, 0}, + {0x768c, 0x00, 0, 0}, + {0x768d, 0x02, 0, 0}, + {0x768e, 0x04, 0, 0}, + {0x768f, 0xc4, 0, 0}, + {0x7690, 0x05, 0, 0}, + {0x7691, 0x83, 0, 0}, + {0x7692, 0x03, 0, 0}, + {0x7693, 0x0b, 0, 0}, + {0x7694, 0x05, 0, 0}, + {0x7695, 0x83, 0, 0}, + {0x7696, 0x00, 0, 0}, + {0x7697, 0x07, 0, 0}, + {0x7698, 0x05, 0, 0}, + {0x7699, 0x03, 0, 0}, + {0x769a, 0x00, 0, 0}, + {0x769b, 0x05, 0, 0}, + {0x769c, 0x05, 0, 0}, + {0x769d, 0x32, 0, 0}, + {0x769e, 0x05, 0, 0}, + {0x769f, 0x30, 0, 0}, + {0x76a0, 0x00, 0, 0}, + {0x76a1, 0x02, 0, 0}, + {0x76a2, 0x05, 0, 0}, + {0x76a3, 0x78, 0, 0}, + {0x76a4, 0x00, 0, 0}, + {0x76a5, 0x01, 0, 0}, + {0x76a6, 0x05, 0, 0}, + {0x76a7, 0x7c, 0, 0}, + {0x76a8, 0x03, 0, 0}, + {0x76a9, 0x9a, 0, 0}, + {0x76aa, 0x05, 0, 0}, + {0x76ab, 0x83, 0, 0}, + {0x76ac, 0x00, 0, 0}, + {0x76ad, 0x04, 0, 0}, + {0x76ae, 0x05, 0, 0}, + {0x76af, 0x03, 0, 0}, + {0x76b0, 0x00, 0, 0}, + {0x76b1, 0x03, 0, 0}, + {0x76b2, 0x05, 0, 0}, + {0x76b3, 0x32, 0, 0}, + {0x76b4, 0x05, 0, 0}, + {0x76b5, 0x30, 0, 0}, + {0x76b6, 0x00, 0, 0}, + {0x76b7, 0x02, 0, 0}, + {0x76b8, 0x05, 0, 0}, + {0x76b9, 0x78, 0, 0}, + {0x76ba, 0x00, 0, 0}, + {0x76bb, 0x01, 0, 0}, + {0x76bc, 0x05, 0, 0}, + {0x76bd, 0x7c, 0, 0}, + {0x76be, 0x03, 0, 0}, + {0x76bf, 0x99, 0, 0}, + {0x76c0, 0x05, 0, 0}, + {0x76c1, 0x83, 0, 0}, + {0x76c2, 0x00, 0, 0}, + {0x76c3, 0x03, 0, 0}, + {0x76c4, 0x05, 0, 0}, + {0x76c5, 0x03, 0, 0}, + {0x76c6, 0x00, 0, 0}, + {0x76c7, 0x01, 0, 0}, + {0x76c8, 0x05, 0, 0}, + {0x76c9, 0x32, 0, 0}, + {0x76ca, 0x05, 0, 0}, + {0x76cb, 0x30, 0, 0}, + {0x76cc, 0x00, 0, 0}, + {0x76cd, 0x02, 0, 0}, + {0x76ce, 0x05, 0, 0}, + {0x76cf, 0x78, 0, 0}, + {0x76d0, 0x00, 0, 0}, + {0x76d1, 0x01, 0, 0}, + {0x76d2, 0x05, 0, 0}, + {0x76d3, 0x7c, 0, 0}, + {0x76d4, 0x03, 0, 0}, + {0x76d5, 0x98, 0, 0}, + {0x76d6, 0x05, 0, 0}, + {0x76d7, 0x83, 0, 0}, + {0x76d8, 0x00, 0, 0}, + {0x76d9, 0x00, 0, 0}, + {0x76da, 0x05, 0, 0}, + {0x76db, 0x03, 0, 0}, + {0x76dc, 0x00, 0, 0}, + {0x76dd, 0x01, 0, 0}, + {0x76de, 0x05, 0, 0}, + {0x76df, 0x32, 0, 0}, + {0x76e0, 0x05, 0, 0}, + {0x76e1, 0x30, 0, 0}, + {0x76e2, 0x00, 0, 0}, + {0x76e3, 0x02, 0, 0}, + {0x76e4, 0x05, 0, 0}, + {0x76e5, 0x78, 0, 0}, + {0x76e6, 0x00, 0, 0}, + {0x76e7, 0x01, 0, 0}, + {0x76e8, 0x05, 0, 0}, + {0x76e9, 0x7c, 0, 0}, + {0x76ea, 0x03, 0, 0}, + {0x76eb, 0x97, 0, 0}, + {0x76ec, 0x05, 0, 0}, + {0x76ed, 0x83, 0, 0}, + {0x76ee, 0x00, 0, 0}, + {0x76ef, 0x00, 0, 0}, + {0x76f0, 0x05, 0, 0}, + {0x76f1, 0x03, 0, 0}, + {0x76f2, 0x05, 0, 0}, + {0x76f3, 0x32, 0, 0}, + {0x76f4, 0x05, 0, 0}, + {0x76f5, 0x30, 0, 0}, + {0x76f6, 0x00, 0, 0}, + {0x76f7, 0x02, 0, 0}, + {0x76f8, 0x05, 0, 0}, + {0x76f9, 0x78, 0, 0}, + {0x76fa, 0x00, 0, 0}, + {0x76fb, 0x01, 0, 0}, + {0x76fc, 0x05, 0, 0}, + {0x76fd, 0x7c, 0, 0}, + {0x76fe, 0x03, 0, 0}, + {0x76ff, 0x96, 0, 0}, + {0x7700, 0x05, 0, 0}, + {0x7701, 0x83, 0, 0}, + {0x7702, 0x05, 0, 0}, + {0x7703, 0x03, 0, 0}, + {0x7704, 0x05, 0, 0}, + {0x7705, 0x32, 0, 0}, + {0x7706, 0x05, 0, 0}, + {0x7707, 0x30, 0, 0}, + {0x7708, 0x00, 0, 0}, + {0x7709, 0x02, 0, 0}, + {0x770a, 0x05, 0, 0}, + {0x770b, 0x78, 0, 0}, + {0x770c, 0x00, 0, 0}, + {0x770d, 0x01, 0, 0}, + {0x770e, 0x05, 0, 0}, + {0x770f, 0x7c, 0, 0}, + {0x7710, 0x03, 0, 0}, + {0x7711, 0x95, 0, 0}, + {0x7712, 0x05, 0, 0}, + {0x7713, 0x83, 0, 0}, + {0x7714, 0x05, 0, 0}, + {0x7715, 0x03, 0, 0}, + {0x7716, 0x05, 0, 0}, + {0x7717, 0x32, 0, 0}, + {0x7718, 0x05, 0, 0}, + {0x7719, 0x30, 0, 0}, + {0x771a, 0x00, 0, 0}, + {0x771b, 0x02, 0, 0}, + {0x771c, 0x05, 0, 0}, + {0x771d, 0x78, 0, 0}, + {0x771e, 0x00, 0, 0}, + {0x771f, 0x01, 0, 0}, + {0x7720, 0x05, 0, 0}, + {0x7721, 0x7c, 0, 0}, + {0x7722, 0x03, 0, 0}, + {0x7723, 0x94, 0, 0}, + {0x7724, 0x05, 0, 0}, + {0x7725, 0x83, 0, 0}, + {0x7726, 0x00, 0, 0}, + {0x7727, 0x01, 0, 0}, + {0x7728, 0x05, 0, 0}, + {0x7729, 0x03, 0, 0}, + {0x772a, 0x00, 0, 0}, + {0x772b, 0x01, 0, 0}, + {0x772c, 0x05, 0, 0}, + {0x772d, 0x32, 0, 0}, + {0x772e, 0x05, 0, 0}, + {0x772f, 0x30, 0, 0}, + {0x7730, 0x00, 0, 0}, + {0x7731, 0x02, 0, 0}, + {0x7732, 0x05, 0, 0}, + {0x7733, 0x78, 0, 0}, + {0x7734, 0x00, 0, 0}, + {0x7735, 0x01, 0, 0}, + {0x7736, 0x05, 0, 0}, + {0x7737, 0x7c, 0, 0}, + {0x7738, 0x03, 0, 0}, + {0x7739, 0x93, 0, 0}, + {0x773a, 0x05, 0, 0}, + {0x773b, 0x83, 0, 0}, + {0x773c, 0x00, 0, 0}, + {0x773d, 0x00, 0, 0}, + {0x773e, 0x05, 0, 0}, + {0x773f, 0x03, 0, 0}, + {0x7740, 0x00, 0, 0}, + {0x7741, 0x00, 0, 0}, + {0x7742, 0x05, 0, 0}, + {0x7743, 0x32, 0, 0}, + {0x7744, 0x05, 0, 0}, + {0x7745, 0x30, 0, 0}, + {0x7746, 0x00, 0, 0}, + {0x7747, 0x02, 0, 0}, + {0x7748, 0x05, 0, 0}, + {0x7749, 0x78, 0, 0}, + {0x774a, 0x00, 0, 0}, + {0x774b, 0x01, 0, 0}, + {0x774c, 0x05, 0, 0}, + {0x774d, 0x7c, 0, 0}, + {0x774e, 0x03, 0, 0}, + {0x774f, 0x92, 0, 0}, + {0x7750, 0x05, 0, 0}, + {0x7751, 0x83, 0, 0}, + {0x7752, 0x05, 0, 0}, + {0x7753, 0x03, 0, 0}, + {0x7754, 0x00, 0, 0}, + {0x7755, 0x00, 0, 0}, + {0x7756, 0x05, 0, 0}, + {0x7757, 0x32, 0, 0}, + {0x7758, 0x05, 0, 0}, + {0x7759, 0x30, 0, 0}, + {0x775a, 0x00, 0, 0}, + {0x775b, 0x02, 0, 0}, + {0x775c, 0x05, 0, 0}, + {0x775d, 0x78, 0, 0}, + {0x775e, 0x00, 0, 0}, + {0x775f, 0x01, 0, 0}, + {0x7760, 0x05, 0, 0}, + {0x7761, 0x7c, 0, 0}, + {0x7762, 0x03, 0, 0}, + {0x7763, 0x91, 0, 0}, + {0x7764, 0x05, 0, 0}, + {0x7765, 0x83, 0, 0}, + {0x7766, 0x05, 0, 0}, + {0x7767, 0x03, 0, 0}, + {0x7768, 0x05, 0, 0}, + {0x7769, 0x32, 0, 0}, + {0x776a, 0x05, 0, 0}, + {0x776b, 0x30, 0, 0}, + {0x776c, 0x00, 0, 0}, + {0x776d, 0x02, 0, 0}, + {0x776e, 0x05, 0, 0}, + {0x776f, 0x78, 0, 0}, + {0x7770, 0x00, 0, 0}, + {0x7771, 0x01, 0, 0}, + {0x7772, 0x05, 0, 0}, + {0x7773, 0x7c, 0, 0}, + {0x7774, 0x03, 0, 0}, + {0x7775, 0x90, 0, 0}, + {0x7776, 0x05, 0, 0}, + {0x7777, 0x83, 0, 0}, + {0x7778, 0x05, 0, 0}, + {0x7779, 0x03, 0, 0}, + {0x777a, 0x05, 0, 0}, + {0x777b, 0x32, 0, 0}, + {0x777c, 0x05, 0, 0}, + {0x777d, 0x30, 0, 0}, + {0x777e, 0x00, 0, 0}, + {0x777f, 0x02, 0, 0}, + {0x7780, 0x05, 0, 0}, + {0x7781, 0x78, 0, 0}, + {0x7782, 0x00, 0, 0}, + {0x7783, 0x01, 0, 0}, + {0x7784, 0x05, 0, 0}, + {0x7785, 0x7c, 0, 0}, + {0x7786, 0x02, 0, 0}, + {0x7787, 0x90, 0, 0}, + {0x7788, 0x05, 0, 0}, + {0x7789, 0x03, 0, 0}, + {0x778a, 0x07, 0, 0}, + {0x778b, 0x00, 0, 0}, + {0x778c, 0x0f, 0, 0}, + {0x778d, 0x00, 0, 0}, + {0x778e, 0x08, 0, 0}, + {0x778f, 0x30, 0, 0}, + {0x7790, 0x08, 0, 0}, + {0x7791, 0xee, 0, 0}, + {0x7792, 0x0f, 0, 0}, + {0x7793, 0x00, 0, 0}, + {0x7794, 0x05, 0, 0}, + {0x7795, 0x33, 0, 0}, + {0x7796, 0x04, 0, 0}, + {0x7797, 0xe5, 0, 0}, + {0x7798, 0x06, 0, 0}, + {0x7799, 0x52, 0, 0}, + {0x779a, 0x04, 0, 0}, + {0x779b, 0xe4, 0, 0}, + {0x779c, 0x00, 0, 0}, + {0x779d, 0x00, 0, 0}, + {0x779e, 0x06, 0, 0}, + {0x779f, 0x5e, 0, 0}, + {0x77a0, 0x00, 0, 0}, + {0x77a1, 0x0f, 0, 0}, + {0x77a2, 0x06, 0, 0}, + {0x77a3, 0x1e, 0, 0}, + {0x77a4, 0x00, 0, 0}, + {0x77a5, 0x02, 0, 0}, + {0x77a6, 0x06, 0, 0}, + {0x77a7, 0xa2, 0, 0}, + {0x77a8, 0x00, 0, 0}, + {0x77a9, 0x01, 0, 0}, + {0x77aa, 0x06, 0, 0}, + {0x77ab, 0xae, 0, 0}, + {0x77ac, 0x00, 0, 0}, + {0x77ad, 0x03, 0, 0}, + {0x77ae, 0x05, 0, 0}, + {0x77af, 0x30, 0, 0}, + {0x77b0, 0x09, 0, 0}, + {0x77b1, 0x19, 0, 0}, + {0x77b2, 0x0f, 0, 0}, + {0x77b3, 0x00, 0, 0}, + {0x77b4, 0x05, 0, 0}, + {0x77b5, 0x33, 0, 0}, + {0x77b6, 0x04, 0, 0}, + {0x77b7, 0xe5, 0, 0}, + {0x77b8, 0x06, 0, 0}, + {0x77b9, 0x52, 0, 0}, + {0x77ba, 0x04, 0, 0}, + {0x77bb, 0xe4, 0, 0}, + {0x77bc, 0x00, 0, 0}, + {0x77bd, 0x00, 0, 0}, + {0x77be, 0x06, 0, 0}, + {0x77bf, 0x5e, 0, 0}, + {0x77c0, 0x00, 0, 0}, + {0x77c1, 0x0f, 0, 0}, + {0x77c2, 0x06, 0, 0}, + {0x77c3, 0x1e, 0, 0}, + {0x77c4, 0x00, 0, 0}, + {0x77c5, 0x02, 0, 0}, + {0x77c6, 0x06, 0, 0}, + {0x77c7, 0xa2, 0, 0}, + {0x77c8, 0x00, 0, 0}, + {0x77c9, 0x01, 0, 0}, + {0x77ca, 0x06, 0, 0}, + {0x77cb, 0xae, 0, 0}, + {0x77cc, 0x00, 0, 0}, + {0x77cd, 0x03, 0, 0}, + {0x77ce, 0x05, 0, 0}, + {0x77cf, 0x30, 0, 0}, + {0x77d0, 0x0f, 0, 0}, + {0x77d1, 0x00, 0, 0}, + {0x77d2, 0x00, 0, 0}, + {0x77d3, 0x00, 0, 0}, + {0x77d4, 0x00, 0, 0}, + {0x77d5, 0x02, 0, 0}, + {0x77d6, 0x04, 0, 0}, + {0x77d7, 0xe5, 0, 0}, + {0x77d8, 0x04, 0, 0}, + {0x77d9, 0xe4, 0, 0}, + {0x77da, 0x05, 0, 0}, + {0x77db, 0x33, 0, 0}, + {0x77dc, 0x07, 0, 0}, + {0x77dd, 0x10, 0, 0}, + {0x77de, 0x00, 0, 0}, + {0x77df, 0x00, 0, 0}, + {0x77e0, 0x01, 0, 0}, + {0x77e1, 0xbb, 0, 0}, + {0x77e2, 0x00, 0, 0}, + {0x77e3, 0x00, 0, 0}, + {0x77e4, 0x01, 0, 0}, + {0x77e5, 0xaa, 0, 0}, + {0x77e6, 0x00, 0, 0}, + {0x77e7, 0x00, 0, 0}, + {0x77e8, 0x01, 0, 0}, + {0x77e9, 0x99, 0, 0}, + {0x77ea, 0x00, 0, 0}, + {0x77eb, 0x00, 0, 0}, + {0x77ec, 0x01, 0, 0}, + {0x77ed, 0x88, 0, 0}, + {0x77ee, 0x00, 0, 0}, + {0x77ef, 0x00, 0, 0}, + {0x77f0, 0x01, 0, 0}, + {0x77f1, 0x77, 0, 0}, + {0x77f2, 0x00, 0, 0}, + {0x77f3, 0x00, 0, 0}, + {0x77f4, 0x01, 0, 0}, + {0x77f5, 0x66, 0, 0}, + {0x77f6, 0x00, 0, 0}, + {0x77f7, 0x00, 0, 0}, + {0x77f8, 0x01, 0, 0}, + {0x77f9, 0x55, 0, 0}, + {0x77fa, 0x00, 0, 0}, + {0x77fb, 0x00, 0, 0}, + {0x77fc, 0x01, 0, 0}, + {0x77fd, 0x44, 0, 0}, + {0x77fe, 0x00, 0, 0}, + {0x77ff, 0x00, 0, 0}, + {0x7800, 0x01, 0, 0}, + {0x7801, 0x33, 0, 0}, + {0x7802, 0x00, 0, 0}, + {0x7803, 0x00, 0, 0}, + {0x7804, 0x01, 0, 0}, + {0x7805, 0x22, 0, 0}, + {0x7806, 0x00, 0, 0}, + {0x7807, 0x00, 0, 0}, + {0x7808, 0x01, 0, 0}, + {0x7809, 0x11, 0, 0}, + {0x780a, 0x00, 0, 0}, + {0x780b, 0x00, 0, 0}, + {0x780c, 0x01, 0, 0}, + {0x780d, 0x00, 0, 0}, + {0x780e, 0x01, 0, 0}, + {0x780f, 0xff, 0, 0}, + {0x7810, 0x07, 0, 0}, + {0x7811, 0x00, 0, 0}, + {0x7812, 0x02, 0, 0}, + {0x7813, 0xa0, 0, 0}, + {0x7814, 0x0f, 0, 0}, + {0x7815, 0x00, 0, 0}, + {0x7816, 0x08, 0, 0}, + {0x7817, 0x35, 0, 0}, + {0x7818, 0x06, 0, 0}, + {0x7819, 0x52, 0, 0}, + {0x781a, 0x04, 0, 0}, + {0x781b, 0xe4, 0, 0}, + {0x781c, 0x00, 0, 0}, + {0x781d, 0x00, 0, 0}, + {0x781e, 0x06, 0, 0}, + {0x781f, 0x5e, 0, 0}, + {0x7820, 0x05, 0, 0}, + {0x7821, 0x33, 0, 0}, + {0x7822, 0x09, 0, 0}, + {0x7823, 0x19, 0, 0}, + {0x7824, 0x06, 0, 0}, + {0x7825, 0x1e, 0, 0}, + {0x7826, 0x05, 0, 0}, + {0x7827, 0x33, 0, 0}, + {0x7828, 0x00, 0, 0}, + {0x7829, 0x01, 0, 0}, + {0x782a, 0x06, 0, 0}, + {0x782b, 0x24, 0, 0}, + {0x782c, 0x06, 0, 0}, + {0x782d, 0x20, 0, 0}, + {0x782e, 0x0f, 0, 0}, + {0x782f, 0x00, 0, 0}, + {0x7830, 0x08, 0, 0}, + {0x7831, 0x35, 0, 0}, + {0x7832, 0x07, 0, 0}, + {0x7833, 0x10, 0, 0}, + {0x7834, 0x00, 0, 0}, + {0x7835, 0x00, 0, 0}, + {0x7836, 0x01, 0, 0}, + {0x7837, 0xbb, 0, 0}, + {0x7838, 0x00, 0, 0}, + {0x7839, 0x00, 0, 0}, + {0x783a, 0x01, 0, 0}, + {0x783b, 0xaa, 0, 0}, + {0x783c, 0x00, 0, 0}, + {0x783d, 0x00, 0, 0}, + {0x783e, 0x01, 0, 0}, + {0x783f, 0x99, 0, 0}, + {0x7840, 0x00, 0, 0}, + {0x7841, 0x00, 0, 0}, + {0x7842, 0x01, 0, 0}, + {0x7843, 0x88, 0, 0}, + {0x7844, 0x00, 0, 0}, + {0x7845, 0x00, 0, 0}, + {0x7846, 0x01, 0, 0}, + {0x7847, 0x77, 0, 0}, + {0x7848, 0x00, 0, 0}, + {0x7849, 0x00, 0, 0}, + {0x784a, 0x01, 0, 0}, + {0x784b, 0x66, 0, 0}, + {0x784c, 0x00, 0, 0}, + {0x784d, 0x00, 0, 0}, + {0x784e, 0x01, 0, 0}, + {0x784f, 0x55, 0, 0}, + {0x7850, 0x00, 0, 0}, + {0x7851, 0x00, 0, 0}, + {0x7852, 0x01, 0, 0}, + {0x7853, 0x44, 0, 0}, + {0x7854, 0x00, 0, 0}, + {0x7855, 0x00, 0, 0}, + {0x7856, 0x01, 0, 0}, + {0x7857, 0x33, 0, 0}, + {0x7858, 0x00, 0, 0}, + {0x7859, 0x00, 0, 0}, + {0x785a, 0x01, 0, 0}, + {0x785b, 0x22, 0, 0}, + {0x785c, 0x00, 0, 0}, + {0x785d, 0x00, 0, 0}, + {0x785e, 0x01, 0, 0}, + {0x785f, 0x11, 0, 0}, + {0x7860, 0x00, 0, 0}, + {0x7861, 0x00, 0, 0}, + {0x7862, 0x01, 0, 0}, + {0x7863, 0x00, 0, 0}, + {0x7864, 0x07, 0, 0}, + {0x7865, 0x00, 0, 0}, + {0x7866, 0x01, 0, 0}, + {0x7867, 0xff, 0, 0}, + {0x7868, 0x02, 0, 0}, + {0x7869, 0xa0, 0, 0}, + {0x786a, 0x0f, 0, 0}, + {0x786b, 0x00, 0, 0}, + {0x786c, 0x08, 0, 0}, + {0x786d, 0x3a, 0, 0}, + {0x786e, 0x08, 0, 0}, + {0x786f, 0x6a, 0, 0}, + {0x7870, 0x0f, 0, 0}, + {0x7871, 0x00, 0, 0}, + {0x7872, 0x04, 0, 0}, + {0x7873, 0xc0, 0, 0}, + {0x7874, 0x09, 0, 0}, + {0x7875, 0x19, 0, 0}, + {0x7876, 0x04, 0, 0}, + {0x7877, 0x99, 0, 0}, + {0x7878, 0x07, 0, 0}, + {0x7879, 0x14, 0, 0}, + {0x787a, 0x00, 0, 0}, + {0x787b, 0x01, 0, 0}, + {0x787c, 0x04, 0, 0}, + {0x787d, 0xa4, 0, 0}, + {0x787e, 0x00, 0, 0}, + {0x787f, 0x07, 0, 0}, + {0x7880, 0x04, 0, 0}, + {0x7881, 0xa6, 0, 0}, + {0x7882, 0x00, 0, 0}, + {0x7883, 0x00, 0, 0}, + {0x7884, 0x04, 0, 0}, + {0x7885, 0xa0, 0, 0}, + {0x7886, 0x04, 0, 0}, + {0x7887, 0x80, 0, 0}, + {0x7888, 0x04, 0, 0}, + {0x7889, 0x00, 0, 0}, + {0x788a, 0x05, 0, 0}, + {0x788b, 0x03, 0, 0}, + {0x788c, 0x06, 0, 0}, + {0x788d, 0x00, 0, 0}, + {0x788e, 0x0f, 0, 0}, + {0x788f, 0x00, 0, 0}, + {0x7890, 0x0f, 0, 0}, + {0x7891, 0x00, 0, 0}, + {0x7892, 0x0f, 0, 0}, + {0x7893, 0x00, 0, 0}, + {0x30a0, 0x00, 0, 0}, + {0x30a1, 0x00, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0x00, 0, 0}, + {0x30a4, 0x07, 0, 0}, + {0x30a5, 0x8f, 0, 0}, + {0x30a6, 0x04, 0, 0}, + {0x30a7, 0x47, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x05, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x04, 0, 0}, + {0x30ac, 0x07, 0, 0}, + {0x30ad, 0x88, 0, 0}, + {0x30ae, 0x04, 0, 0}, + {0x30af, 0x40, 0, 0}, + {0x30b0, 0x0d, 0, 0}, + {0x30b1, 0xde, 0, 0}, + {0x30b2, 0x04, 0, 0}, + {0x30b3, 0x66, 0, 0}, + {0x30b6, 0x04, 0, 0}, + {0x30b7, 0x22, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x40, 0, 0}, + {0x3196, 0x00, 0, 0}, + {0x3197, 0x0a, 0, 0}, + {0x3195, 0x2e, 0, 0}, + {0x30bb, 0x14, 0, 0}, + {0x315a, 0x02, 0, 0}, + {0x315b, 0x00, 0, 0}, + {0x315c, 0x01, 0, 0}, + {0x315d, 0x80, 0, 0}, + {0x315e, 0x01, 0, 0}, + {0x315f, 0x80, 0, 0}, + {0x3250, 0xf7, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3000, 0x02, 0, 0}, + {0x3001, 0x28, 0, 0}, + {0x3002, 0x03, 0, 0}, + {0x3003, 0x01, 0, 0}, + {0x3004, 0x05, 0, 0}, + {0x3005, 0x26, 0, 0},//480Mbps + {0x3006, 0x00, 0, 0}, + {0x3007, 0x07, 0, 0},//60Mhz + {0x3008, 0x01, 0, 0}, + {0x3009, 0x00, 0, 0}, + {0x300c, 0x6c, 0, 0}, + {0x300e, 0x80, 0, 0}, + {0x300f, 0x00, 0, 0}, + {0x3012, 0x00, 0, 0}, + {0x3013, 0x00, 0, 0}, + {0x3014, 0xc4, 0, 0}, + {0x3015, 0x00, 0, 0}, + {0x3017, 0x00, 0, 0}, + {0x3018, 0x00, 0, 0}, + {0x3019, 0x00, 0, 0}, + {0x301a, 0x00, 0, 0}, + {0x301b, 0x0e, 0, 0}, + {0x301e, 0x17, 0, 0}, + {0x301f, 0xe1, 0, 0}, + {0x30b0, 0x0a, 0, 0}, + {0x30b1, 0x50, 0, 0}, + {0x3196, 0x06, 0, 0}, + {0x3197, 0x00, 0, 0}, + {0x30b2, 0x02, 0, 0}, + {0x30b3, 0xee, 0, 0}, + {0x30a0, 0x01, 0, 0}, + {0x30a1, 0x40, 0, 0}, + {0x30a2, 0x00, 0, 0}, + {0x30a3, 0xB4, 0, 0}, + {0x30a4, 0x06, 0, 0}, + {0x30a5, 0x4F, 0, 0}, + {0x30a6, 0x03, 0, 0}, + {0x30a7, 0x93, 0, 0}, + {0x30a8, 0x00, 0, 0}, + {0x30a9, 0x08, 0, 0}, + {0x30aa, 0x00, 0, 0}, + {0x30ab, 0x08, 0, 0}, + {0x30ac, 0x05, 0, 0}, + {0x30ad, 0x00, 0, 0}, + {0x30ae, 0x02, 0, 0}, + {0x30af, 0xd0, 0, 0}, + {0x3195, 0x20, 0, 0}, + {0x30c0, 0x08, 0, 0}, + {0x2352, 0x02, 0, 0}, + {0x3252, 0x22, 0, 0}, + {0x30b8, 0x00, 0, 0}, + {0x30b9, 0x0a, 0, 0}, + {0x30ba, 0x00, 0, 0}, + {0x30b6, 0x00, 0, 0}, + {0x30b7, 0xa0, 0, 0}, + {0x30c0, 0x08, 0, 0}, + {0x3252, 0x20, 0, 0}, +}; + +#endif diff --git a/vvcam_ry/v4l2/video/Makefile b/vvcam_ry/v4l2/video/Makefile new file mode 100755 index 0000000..a8abfb1 --- /dev/null +++ b/vvcam_ry/v4l2/video/Makefile @@ -0,0 +1,15 @@ +MODULE_NAME = vvcam-video + +obj-m := $(MODULE_NAME).o +$(MODULE_NAME)-objs := \ + video.o \ + vvbuf.o + +EXTRA_CFLAGS += -I$(PWD)/../common/ +EXTRA_CFLAGS += -DRESERVED_MEM_BASE=0xB0000000 +EXTRA_CFLAGS += -DRESERVED_MEM_SIZE=0x10000000 + +ifeq ($(ENABLE_IRQ), yes) + EXTRA_CFLAGS += -DENABLE_IRQ +endif +EXTRA_CFLAGS += -O2 -Wall diff --git a/vvcam_ry/v4l2/video/cma.c b/vvcam_ry/v4l2/video/cma.c new file mode 100755 index 0000000..b11cb6c --- /dev/null +++ b/vvcam_ry/v4l2/video/cma.c @@ -0,0 +1,277 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include "cma.h" + +#ifdef __KERNEL__ + +struct block_list { + struct block_list *next; + u64 base_addr; + u64 size; +}; + +struct cma_mem_context { + u64 base; + u64 size; + u64 align; + struct block_list free_blocks; + struct block_list used_blocks; +}; + +static struct cma_mem_context *g_cma_mem_ctx; +static inline void add_free_blocks(struct block_list *free_item); +static inline void add_used_blocks(struct block_list *used_item); +struct mutex viv_cma_mutex; + +int vsi_cma_init(u64 base, u64 size, u64 align) +{ + struct block_list *item = NULL; + + pr_debug("enter %s\n", __func__); + if (!size || (size <= align)) + return -EINVAL; + g_cma_mem_ctx = kzalloc(sizeof(struct cma_mem_context), GFP_KERNEL); + memset(g_cma_mem_ctx, 0, sizeof(*g_cma_mem_ctx)); + + g_cma_mem_ctx->base = (base + align - 1) & ~(align - 1); + g_cma_mem_ctx->size = size - (g_cma_mem_ctx->base - base); + g_cma_mem_ctx->align = align; + + pr_debug("addr:0x%llx, size:0x%llx, alignment:0x%llx.\n", + g_cma_mem_ctx->base, g_cma_mem_ctx->size, + g_cma_mem_ctx->align); + + item = kzalloc(sizeof(struct block_list), GFP_KERNEL); + if (!item) { + kzfree(g_cma_mem_ctx); + g_cma_mem_ctx = NULL; + return -ENOMEM; + } + + item->next = NULL; + item->base_addr = g_cma_mem_ctx->base; + item->size = g_cma_mem_ctx->size; + + g_cma_mem_ctx->free_blocks.next = item; + g_cma_mem_ctx->used_blocks.next = NULL; + + mutex_init(&viv_cma_mutex); + return 0; +} + +int vsi_cma_release(void) +{ + int result = 0; + struct block_list *item, *pFree; + + if (!g_cma_mem_ctx->free_blocks.next + || g_cma_mem_ctx->free_blocks.next->next + || g_cma_mem_ctx->used_blocks.next) { + pr_err("Warning memory is not free.\n"); + } + + item = g_cma_mem_ctx->free_blocks.next; + while (item) { + pFree = item; + item = item->next; + /* kzfree(pFree); */ + } + kzfree(g_cma_mem_ctx); + g_cma_mem_ctx = NULL; + + mutex_destroy(&viv_cma_mutex); + return result; +} + +u64 vsi_cma_alloc(u64 size) +{ + u64 addr = ~0U; + struct block_list *item; + struct block_list *found; + mutex_lock(&viv_cma_mutex); + if (!size || (size > g_cma_mem_ctx->size)) { + mutex_unlock(&viv_cma_mutex); + return ~0U; + } + + pr_debug("enter %s\n", __func__); + pr_debug + ("addr:0x%llx, size:0x%llx, alignment:0x%llx, reqsize:0x%llx.\n", + g_cma_mem_ctx->base, g_cma_mem_ctx->size, g_cma_mem_ctx->align, + size); + + size += g_cma_mem_ctx->align - 1; + size &= ~(g_cma_mem_ctx->align - 1); + /*TODO: need to lock this block */ + item = &g_cma_mem_ctx->free_blocks; + while (item->next && (item->next->size < size)) + item = item->next; + + found = item->next; + if (found) { + item->next = found->next; + if ((found->size - size) >= g_cma_mem_ctx->align) { + item = kzalloc(sizeof(struct block_list), GFP_KERNEL); + if (item) { + item->base_addr = found->base_addr + size; + item->size = found->size - size; + found->size = size; + pr_debug("new free block: base_addr=0x%llx,\n", + item->base_addr); + add_free_blocks(item); + } + } + + pr_debug("new used block: base_addr=0x%llx, size=0x%llx \n", + found->base_addr, found->size); + add_used_blocks(found); + addr = found->base_addr; + } + + pr_debug("block allocated: base_addr=0x%llx\n", addr); + mutex_unlock(&viv_cma_mutex); + return addr; +} + +void vsi_cma_free(u64 addr) +{ + pr_debug("enter %s\n", __func__); + pr_debug("block to free: base_addr=0x%llx\n", addr); + mutex_lock(&viv_cma_mutex); + if (addr) { + /*TODO: need to lock this block */ + struct block_list *item, *free_item; + + item = &g_cma_mem_ctx->used_blocks; + while (item->next && (item->next->base_addr != addr)) + item = item->next; + + free_item = item->next; + item->next = free_item->next; + if (((item->base_addr + item->size) != free_item->base_addr) || + ((free_item->base_addr + item->size) != ((free_item->next) ? + free_item->next->base_addr : + (g_cma_mem_ctx->base + + + g_cma_mem_ctx->size)))) { + struct block_list *loc_item; + struct block_list *pre_item = NULL; + struct block_list *success_item = NULL; + loc_item = &g_cma_mem_ctx->free_blocks; + while (loc_item->next) { + if ((loc_item->next->base_addr + + loc_item->next->size) == + free_item->base_addr) { + pre_item = loc_item; + } + if ((free_item->base_addr + free_item->size) == + loc_item->next->base_addr) { + success_item = loc_item; + } + loc_item = loc_item->next; + } + + if (success_item) { + loc_item = success_item->next; + free_item->size += loc_item->size; + success_item->next = loc_item->next; + kzfree(loc_item); + } + + if (pre_item) { + loc_item = pre_item->next; + free_item->base_addr = loc_item->base_addr; + free_item->size += loc_item->size; + pre_item->next = loc_item->next; + kzfree(loc_item); + } + } else { + pr_err("no adjacent block free\n"); + } + add_free_blocks(free_item); + } + mutex_unlock(&viv_cma_mutex); +} + +static inline void add_free_blocks(struct block_list *free_item) +{ + struct block_list *item; + + item = &g_cma_mem_ctx->free_blocks; + while (item->next && (item->next->size < free_item->size)) + item = item->next; + + free_item->next = item->next; + item->next = free_item; + + item = &g_cma_mem_ctx->free_blocks; + while (item->next) + item = item->next; +} + +static inline void add_used_blocks(struct block_list *used_item) +{ + struct block_list *item; + + item = &g_cma_mem_ctx->used_blocks; + while (item->next && (item->next->base_addr < used_item->base_addr)) + item = item->next; + + used_item->next = item->next; + item->next = used_item; + item = &g_cma_mem_ctx->used_blocks; + while (item->next) + item = item->next; +} + +#endif diff --git a/vvcam_ry/v4l2/video/cma.h b/vvcam_ry/v4l2/video/cma.h new file mode 100755 index 0000000..e133d28 --- /dev/null +++ b/vvcam_ry/v4l2/video/cma.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_CMA_H_ +#define _ISP_CMA_H_ + +#include +#include + +int vsi_cma_init(u64 addr, u64 size, u64 align); +int vsi_cma_release(void); +u64 vsi_cma_alloc(u64 size); +void vsi_cma_free(u64 addr); + +#endif /* _ISP_CMA_H_ */ diff --git a/vvcam_ry/v4l2/video/video.c b/vvcam_ry/v4l2/video/video.c new file mode 100755 index 0000000..2122785 --- /dev/null +++ b/vvcam_ry/v4l2/video/video.c @@ -0,0 +1,2241 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG +# include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "video.h" +#include "vvctrl.h" +#include "vvdefs.h" +#include "vvsensor.h" + +#define DEF_PLANE_NO (0) + +static struct viv_video_device *vvdev[VIDEO_NODE_NUM]; +static struct list_head file_list_head[VIDEO_NODE_NUM]; +static spinlock_t file_list_lock[VIDEO_NODE_NUM]; +#ifdef ENABLE_IRQ +static struct media_device mdev; +#endif + +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG +struct ext_dma_buf { + dma_addr_t addr; + void *vaddr; + size_t size; + struct list_head entry; +}; +#endif + +static struct viv_video_fmt formats[] = { + { + .fourcc = V4L2_PIX_FMT_YUYV, + .depth = 16, + .bpp = 2, + }, + { + .fourcc = V4L2_PIX_FMT_NV12, + .depth = 12, + .bpp = 1, + }, + { + .fourcc = V4L2_PIX_FMT_NV16, + .depth = 16, + .bpp = 1, + }, +}; + +static int bayer_pattern_to_format(unsigned int bayer_pattern, + unsigned int bit_width, struct viv_video_fmt *fmt) +{ + int ret = 0; + + if (bayer_pattern == BAYER_BGGR) + if (bit_width == 8) { + fmt->fourcc = V4L2_PIX_FMT_SBGGR8; + fmt->depth = 8; + fmt->bpp = 1; + } else if (bit_width == 10) { + fmt->fourcc = V4L2_PIX_FMT_SBGGR10; + fmt->depth = 16; + fmt->bpp = 2; + } else if (bit_width == 12) { + fmt->fourcc = V4L2_PIX_FMT_SBGGR12; + fmt->depth = 16; + fmt->bpp = 2; + } else + ret = -EPERM; + else if (bayer_pattern == BAYER_GBRG) + if (bit_width == 8) { + fmt->fourcc = V4L2_PIX_FMT_SGBRG8; + fmt->depth = 8; + fmt->bpp = 1; + } else if (bit_width == 10) { + fmt->fourcc = V4L2_PIX_FMT_SGBRG10; + fmt->depth = 16; + fmt->bpp = 2; + } else if (bit_width == 12) { + fmt->fourcc = V4L2_PIX_FMT_SGBRG12; + fmt->depth = 16; + fmt->bpp = 2; + } else + ret = -EPERM; + else if (bayer_pattern == BAYER_GRBG) + if (bit_width == 8) { + fmt->fourcc = V4L2_PIX_FMT_SGRBG8; + fmt->depth = 8; + fmt->bpp = 1; + } else if (bit_width == 10) { + fmt->fourcc = V4L2_PIX_FMT_SGRBG10; + fmt->depth = 16; + fmt->bpp = 2; + } else if (bit_width == 12) { + fmt->fourcc = V4L2_PIX_FMT_SGRBG12; + fmt->depth = 16; + fmt->bpp = 2; + } else + ret = -EPERM; + else if (bayer_pattern == BAYER_RGGB) + if (bit_width == 8) { + fmt->fourcc = V4L2_PIX_FMT_SRGGB8; + fmt->depth = 8; + fmt->bpp = 1; + } else if (bit_width == 10) { + fmt->fourcc = V4L2_PIX_FMT_SRGGB10; + fmt->depth = 16; + fmt->bpp = 2; + } else if (bit_width == 12) { + fmt->fourcc = V4L2_PIX_FMT_SRGGB12; + fmt->depth = 16; + fmt->bpp = 2; + } else + ret = -EPERM; + else + ret = -EPERM; + return ret; +} + +static int viv_post_event(struct v4l2_event *event, void *fh, bool sync) +{ + struct viv_video_file *handle = priv_to_handle(fh); + + if (sync) + reinit_completion(&handle->wait); + + mutex_lock(&handle->event_mutex); + v4l2_event_queue(handle->vdev->video, event); + mutex_unlock(&handle->event_mutex); + + if (sync) { + if (wait_for_completion_timeout(&handle->wait, msecs_to_jiffies( + VIV_VIDEO_EVENT_TIMOUT_MS)) == 0) + return -ETIMEDOUT; + } + return 0; +} + +static int viv_post_simple_event(int id, int streamid, void *fh, bool sync) +{ + struct v4l2_event event; + struct viv_video_event *v_event; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = streamid; + v_event->file = fh; + v_event->sync = sync; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = id; + return viv_post_event(&event, fh, sync); +} + +static int viv_post_control_event(int streamid, void *fh, + struct viv_control_event *control_event) +{ + struct v4l2_event event; + struct viv_video_event *v_event; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = streamid; + v_event->file = fh; + v_event->sync = true; + v_event->addr = control_event->request; + v_event->response = control_event->response; + v_event->buf_index = control_event->id; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_PASS_JSON; + return viv_post_event(&event, fh, true); +} + +static int set_stream(struct viv_video_device *vdev, int enable) +{ + struct v4l2_subdev *sd; + struct media_pad *pad; + + if (!vdev) + return -EINVAL; + + pad = &vdev->video->entity.pads[0]; + if (pad) + pad = media_entity_remote_pad(pad); + + if (pad && is_media_entity_v4l2_subdev(pad->entity)) { + sd = media_entity_to_v4l2_subdev(pad->entity); + v4l2_subdev_call(sd, video, s_stream, enable); + } + return 0; +} + +static int start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct viv_video_file *handle = queue_to_handle(vq); + struct v4l2_fh *fh = &handle->vfh; + + pr_debug("enter %s\n", __func__); + if (handle->streamid >= 0 && handle->state != 2) { + handle->state = 2; + handle->vdev->active = 1; + set_stream(handle->vdev, 1); + viv_post_simple_event(VIV_VIDEO_EVENT_START_STREAM, + handle->streamid, fh, true); + } else { + pr_err("can't start streaming, device busy!\n"); + return -EBUSY; + } + return 0; +} + +static void stop_streaming(struct vb2_queue *vq) +{ + struct viv_video_file *handle = queue_to_handle(vq); + struct vb2_buffer *vb; + + pr_debug("enter %s\n", __func__); + + if (!handle || handle->streamid < 0 || handle->state != 2) + return; + + handle->state = 1; + set_stream(handle->vdev, 0); + viv_post_simple_event(VIV_VIDEO_EVENT_STOP_STREAM, handle->streamid, + &handle->vfh, true); + handle->sequence = 0; + list_for_each_entry(vb, &vq->queued_list, queued_entry) { + if (vb->state == VB2_BUF_STATE_ACTIVE) + vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); + } +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0) +static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], void *alloc_ctxs[]) +{ + struct viv_video_file *handle = queue_to_handle(vq); + unsigned long size = handle->vdev->fmt.fmt.pix.sizeimage; + + pr_debug("enter %s\n", __func__); + if (*nbuffers == 0) + *nbuffers = 1; + while (size * *nbuffers > RESERVED_MEM_SIZE) + (*nbuffers)--; + sizes[0] = size; + return 0; +} +#else +static int queue_setup(struct vb2_queue *q, + unsigned int *num_buffers, unsigned int *num_planes, + unsigned int sizes[], struct device *alloc_devs[]) +{ + struct viv_video_file *handle = queue_to_handle(q); + unsigned long size = handle->vdev->fmt.fmt.pix.sizeimage; + + pr_debug("enter %s\n", __func__); + if (*num_buffers == 0) + *num_buffers = 1; + while (size * *num_buffers > RESERVED_MEM_SIZE) + (*num_buffers)--; + *num_planes = 1; + sizes[0] = size; + return 0; +} +#endif + +static int buffer_init(struct vb2_buffer *vb) +{ + pr_debug("enter %s\n", __func__); + return 0; +} + +static void buffer_queue(struct vb2_buffer *vb) +{ + struct viv_video_file *handle; + struct vb2_v4l2_buffer *vbuf; + struct vb2_dc_buf *buf; +#ifdef ENABLE_IRQ + struct viv_video_device *vdev; + struct media_pad *pad; +#else + struct v4l2_event event; + struct viv_video_event *v_event; +#endif + + if (!vb) + return; + + handle = queue_to_handle(vb->vb2_queue); + vbuf = container_of(vb, struct vb2_v4l2_buffer, vb2_buf); + buf = container_of(vbuf, struct vb2_dc_buf, vb); + if (!buf) + return; + + if (!handle) + return; + +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + buf->dma = vb2_dma_contig_plane_dma_addr(vb, DEF_PLANE_NO); +#endif + +#ifdef ENABLE_IRQ + vdev = handle->vdev; + if (!vdev) + return; + + pad = &vdev->video->entity.pads[0]; + vvbuf_ready(&vdev->bctx, pad, buf); +#endif + +#ifndef ENABLE_IRQ + if (handle->streamid < 0) + return; + + /* pr_debug("buffer_queue %d", vb->index); */ + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = handle->streamid; + v_event->file = &handle->vfh; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + v_event->addr = vb2_dma_contig_plane_dma_addr(vb, DEF_PLANE_NO); +#endif + v_event->buf_index = vb->index; + v_event->sync = false; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_QBUF; + viv_post_event(&event, &handle->vfh, false); +#endif +} + +static struct vb2_ops buffer_ops = { + .queue_setup = queue_setup, + .buf_init = buffer_init, + .buf_queue = buffer_queue, + .start_streaming = start_streaming, + .stop_streaming = stop_streaming, +}; + +static int video_open(struct file *file) +{ + struct viv_video_device *dev = video_drvdata(file); + struct viv_video_file *handle; + unsigned long flags; + int rc; + + pr_debug("enter %s\n", __func__); + handle = kzalloc(sizeof(*handle), GFP_KERNEL); + + v4l2_fh_init(&handle->vfh, dev->video); + v4l2_fh_add(&handle->vfh); + + file->private_data = &handle->vfh; + handle->vdev = dev; + handle->queue.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + handle->queue.drv_priv = handle; + handle->queue.ops = &buffer_ops; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + handle->queue.io_modes = VB2_MMAP | VB2_DMABUF; + handle->queue.mem_ops = &vb2_dma_contig_memops; +#endif + handle->queue.buf_struct_size = sizeof(struct vb2_dc_buf); + handle->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; +#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 5, 0) + handle->queue.dev = dev->v4l2_dev->dev; +#endif + rc = vb2_queue_init(&handle->queue); + if (rc) { + pr_err("can't init vb queue\n"); + v4l2_fh_del(&handle->vfh); + v4l2_fh_exit(&handle->vfh); + kfree(handle); + return rc; + } + mutex_init(&handle->event_mutex); + mutex_init(&handle->buffer_mutex); + init_completion(&handle->wait); + +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + INIT_LIST_HEAD(&handle->extdmaqueue); +#endif + + handle->event_buf.va = kmalloc(VIV_EVENT_BUF_SIZE, GFP_KERNEL); + handle->event_buf.pa = __pa(handle->event_buf.va); + + spin_lock_irqsave(&file_list_lock[handle->vdev->id], flags); + list_add_tail(&handle->entry, &file_list_head[handle->vdev->id]); + spin_unlock_irqrestore(&file_list_lock[handle->vdev->id], flags); + return 0; +} + +static int video_close(struct file *file) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct vb2_buffer *vb; + spinlock_t *lock; + unsigned long flags; + + pr_debug("enter %s\n", __func__); + if (handle) { + if (handle->streamid >= 0 && handle->state == 2) { + set_stream(handle->vdev, 0); + viv_post_simple_event(VIV_VIDEO_EVENT_STOP_STREAM, + handle->streamid, &handle->vfh, + false); + handle->state = 1; + } + if (handle->streamid >= 0 && handle->state == 1) + viv_post_simple_event(VIV_VIDEO_EVENT_DEL_STREAM, + handle->streamid, &handle->vfh, + false); + + if (handle->state > 0) + handle->vdev->active = 0; + handle->state = -1; + handle->streamid = 0; + lock = &file_list_lock[handle->vdev->id]; + spin_lock_irqsave(lock, flags); + list_del(&handle->entry); + spin_unlock_irqrestore(lock, flags); + + list_for_each_entry(vb, &handle->queue.queued_list, + queued_entry) { + if (vb->state == VB2_BUF_STATE_ACTIVE) + vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); + } + + v4l2_fh_del(&handle->vfh); + v4l2_fh_exit(&handle->vfh); + +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + { + struct ext_dma_buf *edb = NULL; + + while (!list_empty(&handle->extdmaqueue)) { + edb = list_first_entry(&handle->extdmaqueue, + struct ext_dma_buf, entry); + if (edb) { + dma_free_attrs(handle->queue.dev, + edb->size, edb->vaddr, + edb->addr, + DMA_ATTR_WRITE_COMBINE); + list_del(&edb->entry); + kfree(edb); + } + } + } +#endif + + vb2_queue_release(&handle->queue); + mutex_destroy(&handle->event_mutex); + mutex_destroy(&handle->buffer_mutex); + kfree(handle->event_buf.va); + kfree(handle); + } + return 0; +} + +static int subscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + int ret; + unsigned long flags; + struct viv_video_file *handle = priv_to_handle(fh); + struct viv_video_device *vdev; + + if (!handle || !sub) + return -EINVAL; + if (unlikely(sub->type != VIV_VIDEO_EVENT_TYPE)) + return v4l2_ctrl_subscribe_event(fh, sub); + ret = v4l2_event_subscribe(fh, sub, 10, 0); + vdev = handle->vdev; + if (!ret && vdev && sub->id == VIV_VIDEO_EVENT_GET_CAPS_SUPPORTS) { + spin_lock_irqsave(&file_list_lock[vdev->id], flags); + vdev->subscribed_cnt++; + spin_unlock_irqrestore(&file_list_lock[vdev->id], flags); + complete_all(&vdev->subscribed_wait); + } + return ret; +} + +static int unsubscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + struct viv_video_file *handle = priv_to_handle(fh); + struct viv_video_file *ph; + struct viv_video_device *vdev; + spinlock_t *lock; + unsigned long flags; + + pr_debug("enter %s\n", __func__); + if (!handle || !handle->vdev || !sub) + return 0; + if (unlikely(sub->type != VIV_VIDEO_EVENT_TYPE)) + return v4l2_event_unsubscribe(fh, sub); + + vdev = handle->vdev; + lock = &file_list_lock[vdev->id]; + spin_lock_irqsave(lock, flags); + list_for_each_entry(ph, &file_list_head[vdev->id], entry) { + if (ph == handle && handle->streamid < 0) { + if (sub->id == VIV_VIDEO_EVENT_GET_CAPS_SUPPORTS) { + vdev->subscribed_cnt--; + if (vdev->subscribed_cnt <= 0) { + reinit_completion( + &vdev->subscribed_wait); + vdev->subscribed_cnt = 0; + } + } + spin_unlock_irqrestore(lock, flags); + return v4l2_event_unsubscribe(fh, sub); + } + } + spin_unlock_irqrestore(lock, flags); + return 0; +} + +#ifndef ENABLE_IRQ +static void viv_buffer_done(struct viv_video_file *handle, u64 addr) +{ + struct vb2_buffer *vb; + + mutex_lock(&handle->buffer_mutex); + list_for_each_entry(vb, &handle->queue.queued_list, queued_entry) { + if (!vb) + continue; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + if (vb2_dma_contig_plane_dma_addr(vb, DEF_PLANE_NO) == addr) { + vb->planes[DEF_PLANE_NO].bytesused = + handle->vdev->fmt.fmt.pix.sizeimage; +#endif +#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 0, 0) + vb->timestamp = ktime_get_ns(); +#endif + vb2_buffer_done(vb, VB2_BUF_STATE_DONE); + mutex_unlock(&handle->buffer_mutex); + return; + } + } + mutex_unlock(&handle->buffer_mutex); +} +#endif + +static int set_caps_mode_event(struct file *file) +{ + struct viv_video_device *dev = video_drvdata(file); + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct v4l2_event event; + struct viv_video_event *v_event; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = 0; + v_event->file = &handle->vfh; + v_event->sync = true; + v_event->buf_index = dev->id; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_SET_CAPSMODE; + return viv_post_event(&event, &handle->vfh, true); +} + +static int get_caps_suppots_event(struct file *file) +{ + struct viv_video_device *dev = video_drvdata(file); + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct v4l2_event event; + struct viv_video_event *v_event; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = 0; + v_event->file = &handle->vfh; + v_event->sync = true; + v_event->buf_index = dev->id; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_GET_CAPS_SUPPORTS; + + if (dev->subscribed_cnt == 0 && + wait_for_completion_timeout(&dev->subscribed_wait, + msecs_to_jiffies(VIV_VIDEO_EVENT_TIMOUT_MS)) == 0) + return -ETIMEDOUT; + return viv_post_event(&event, &handle->vfh, true); +} + +#ifdef ENABLE_IRQ +static struct media_entity *viv_find_entity(struct viv_video_device *dev, + const char *name) +{ + struct v4l2_subdev *sd = NULL; + int i; + + for (i = 0; i < dev->sdcount; ++i) { + if (!strncmp(dev->subdevs[i]->name, name, strlen(name))) { + sd = dev->subdevs[i]; + break; + } + } + return sd ? &sd->entity : NULL; +} + +static int viv_create_link(struct media_entity *source, u16 source_pad, + struct media_entity *sink, u16 sink_pad) +{ + int rc = 0; + u32 flags = MEDIA_LNK_FL_ENABLED; + + if (!source || !sink) + return -EINVAL; + rc = media_create_pad_link(source, source_pad, sink, sink_pad, flags); + if (rc) + goto end; + + rc = media_entity_call(sink, link_setup, &sink->pads[sink_pad], + &source->pads[source_pad], flags); + if (rc) + goto end; + + rc = media_entity_call(source, link_setup, &source->pads[source_pad], + &sink->pads[sink_pad], flags); + if (rc) + goto end; +end: + return rc; +} + +static int viv_create_default_links(struct viv_video_device *dev) +{ + struct media_entity *source, *sink; + + source = viv_find_entity(dev, ISP_DEVICE_NAME); + sink = &dev->video->entity; + return viv_create_link(source, ISP_PAD_SOURCE, sink, 0); +} + +static int viv_config_dwe(struct viv_video_file *handle, bool enable) +{ + struct viv_video_device *vdev = handle->vdev; + int rc; + struct media_entity *source, *sink; + + if (!vdev || !vdev->sdcount) + return -EINVAL; + + if (vdev->dweEnabled == enable) + return 0; + + source = viv_find_entity(vdev, DWE_DEVICE_NAME); + if (!source) + return -EINVAL; + sink = &vdev->video->entity; + media_entity_remove_links(source); + media_entity_remove_links(sink); + + if (!enable) { + source = viv_find_entity(vdev, ISP_DEVICE_NAME); + media_entity_remove_links(source); + rc = viv_create_link(source, ISP_PAD_SOURCE, sink, 0); + if (!rc) + vdev->dweEnabled = false; + return rc; + } + + rc = viv_create_link(source, DWE_PAD_SOURCE, sink, 0); + if (rc) + goto end; + + if (vdev->sdcount > 1) { + source = viv_find_entity(vdev, ISP_DEVICE_NAME); + sink = viv_find_entity(vdev, DWE_DEVICE_NAME); + media_entity_remove_links(source); + if (viv_create_link(source, ISP_PAD_SOURCE, sink, DWE_PAD_SINK)) + pr_err("failed to create link between isp and dwe!\n"); + } + + vdev->dweEnabled = true; +end: + return rc; +} +#endif + +static inline void init_v4l2_fmt(struct v4l2_format *f, unsigned int bpp, + unsigned int depth, unsigned int *bytesperline, + unsigned int *sizeimage) +{ + v4l_bound_align_image(&f->fmt.pix.width, 48, 3840, 2, + &f->fmt.pix.height, 32, 2160, 0, 0); + *bytesperline = ALIGN_UP(f->fmt.pix.width * bpp, 16); + *sizeimage = f->fmt.pix.height * ALIGN_UP(f->fmt.pix.width * depth / 8, 16); +} + +static int viv_set_modeinfo(struct viv_video_file *handle, + struct vvcam_constant_modeinfo *modeinfo) +{ + struct viv_video_device *vdev = handle->vdev; + struct viv_video_fmt fmt; + struct viv_video_fmt *pfmt = NULL; + int i; + + if (modeinfo->w == 0 || modeinfo->h == 0 || modeinfo->fps == 0) { + vdev->modeinfocount = 0; + memset(vdev->modeinfo, 0, sizeof(vdev->modeinfo)); + memset(&vdev->crop, 0, sizeof(struct v4l2_rect)); + memset(&vdev->compose, 0, sizeof(struct v4l2_rect)); + pr_err("modeinfo(w=%d, h=%d, fps=%d is invalid)!\n", + modeinfo->w, modeinfo->h, modeinfo->fps); + return -EINVAL; + } + pr_info("%s: modeinfo(w=%d, h=%d, fps=%d)!\n", + __func__, modeinfo->w, modeinfo->h, modeinfo->fps); + + for (i = 0; i < vdev->modeinfocount; ++i) { + if (vdev->modeinfo[i].index == modeinfo->index) { + pr_debug("sensor mode info already configured!\n"); + return 0; + } + } + + if (vdev->modeinfocount < ARRAY_SIZE(vdev->modeinfo)) { + memcpy(&vdev->modeinfo[vdev->modeinfocount], + modeinfo, sizeof(*modeinfo)); + vdev->modeinfocount++; + } + + if (!bayer_pattern_to_format(modeinfo->brpat, modeinfo->bitw, &fmt) && + vdev->formatscount < ARRAY_SIZE(vdev->formats)) { + for (i = 0; i < vdev->formatscount; ++i) + if (vdev->formats[i].fourcc == fmt.fourcc) + break; + if (i == vdev->formatscount) { + memcpy(&vdev->formats[vdev->formatscount], + &fmt, sizeof(fmt)); + vdev->formatscount++; + } + } + + if (vdev->fmt.fmt.pix.width == 0 || vdev->fmt.fmt.pix.height == 0) { + if (vdev->formats[0].fourcc == 0 || vdev->formats[0].bpp == 0 || + vdev->formats[0].depth == 0 || + vdev->modeinfo[0].w == 0 || vdev->modeinfo[0].h == 0 || + vdev->modeinfo[0].fps == 0) + pr_err("invalid default format!\n"); + + if (vdev->fmt.fmt.pix.pixelformat == 0) { + vdev->fmt.fmt.pix.pixelformat = vdev->formats[0].fourcc; + } + for (i = 0; i < vdev->formatscount; ++i) { + if (vdev->fmt.fmt.pix.pixelformat == vdev->formats[i].fourcc) { + pfmt = &vdev->formats[i]; + break; + } + } + if (pfmt == NULL) + pfmt = &vdev->formats[0]; + + init_v4l2_fmt(&vdev->fmt, pfmt->bpp, pfmt->depth, + &vdev->fmt.fmt.pix.bytesperline, + &vdev->fmt.fmt.pix.sizeimage); + + vdev->timeperframe.numerator = 1; + vdev->timeperframe.denominator = vdev->modeinfo[0].fps; + } + + if (vdev->crop.width == 0 || vdev->crop.height == 0) { + vdev->crop.width = vdev->modeinfo[0].w; + vdev->crop.height = vdev->modeinfo[0].h; + } + + if (vdev->compose.width == 0 || vdev->compose.height == 0) { + vdev->compose.width = vdev->modeinfo[0].w; + vdev->compose.height = vdev->modeinfo[0].h; + } + return 0; +} + +static long private_ioctl(struct file *file, void *fh, + bool valid_prio, unsigned int cmd, void *arg) +{ + struct viv_video_file *handle; + struct viv_video_file *ph; + struct viv_video_event *v_event; + struct ext_buf_info *ext_buf; + struct viv_control_event *control_event; + struct viv_caps_supports *pcaps_supports; + struct viv_video_device *dev = video_drvdata(file); + unsigned long flags; + int rc = 0; + struct reserved_mem *rmem; + + if (!file || !fh) + return -EINVAL; + + handle = priv_to_handle(file->private_data); + if (!handle || handle->state == -1) { + pr_err("call ioctl after file closed\n"); + return -EINVAL; + } + + switch (cmd) { + case VIV_VIDIOC_EVENT_COMPLETE: + v_event = (struct viv_video_event *)arg; + if (v_event->file) { + handle = priv_to_handle(v_event->file); + spin_lock_irqsave( + &file_list_lock[dev->id], flags); + list_for_each_entry(ph, + &file_list_head[dev->id], entry) { + if (ph == handle) { + complete(&handle->wait); + break; + } + } + spin_unlock_irqrestore( + &file_list_lock[dev->id], flags); + } else { + complete(&dev->ctrls.wait); + } + break; +#ifndef ENABLE_IRQ + case VIV_VIDIOC_BUFDONE: { + /* pr_debug("priv ioctl VIV_VIDIOC_BUFDONE\n"); */ + struct v4l2_user_buffer *user_buffer = + (struct v4l2_user_buffer *)arg; + if (!user_buffer->file) + break; + + handle = priv_to_handle(user_buffer->file); + if (!handle || handle->state != 2) + break; + + /* handle the stream closed unexpected. */ + spin_lock_irqsave(&file_list_lock[dev->id], flags); + list_for_each_entry(ph, &file_list_head[dev->id], entry) { + if (ph == handle) { + viv_buffer_done(handle, user_buffer->addr); + break; + } + } + spin_unlock_irqrestore(&file_list_lock[dev->id], flags); + break; + } +#endif + case VIV_VIDIOC_S_STREAMID: + pr_debug("priv ioctl VIV_VIDIOC_S_STREAMID\n"); + handle->streamid = *((int *)arg); + break; +#ifdef ENABLE_IRQ + case VIV_VIDIOC_S_DWECFG: + viv_config_dwe(handle, !!*((int *)arg)); + break; + case VIV_VIDIOC_G_DWECFG: + *((int *)arg) = handle->vdev->dweEnabled ? 1 : 0; + break; +#endif + case VIV_VIDIOC_BUFFER_ALLOC: { + struct ext_buf_info *ext_buf = (struct ext_buf_info *)arg; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + struct ext_dma_buf *edb = kzalloc(sizeof(*edb), GFP_KERNEL); + + pr_debug("priv ioctl VIV_VIDIOC_BUFFER_ALLOC\n"); + if (!edb) { + rc = -ENOMEM; + break; + } + edb->vaddr = dma_alloc_attrs(handle->queue.dev, + ext_buf->size, &ext_buf->addr, + GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); + if (!edb->vaddr) { + pr_err("failed to alloc dma buffer!\n"); + rc = -ENOMEM; + } else { + edb->addr = ext_buf->addr; + edb->size = ext_buf->size; + list_add_tail(&edb->entry, &handle->extdmaqueue); + } +#endif + break; + } + case VIV_VIDIOC_BUFFER_FREE: { + struct ext_buf_info *ext_buf = (struct ext_buf_info *)arg; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + struct ext_dma_buf *b, *edb = NULL; + + pr_debug("priv ioctl VIV_VIDIOC_BUFFER_FREE\n"); + list_for_each_entry(b, &handle->extdmaqueue, entry) { + if (b->addr == ext_buf->addr) { + edb = b; + break; + } + } + + if (edb) { + dma_free_attrs(handle->queue.dev, edb->size, + edb->vaddr, edb->addr, + DMA_ATTR_WRITE_COMBINE); + list_del(&edb->entry); + kfree(edb); + } +#endif + break; + } + case VIV_VIDIOC_CONTROL_EVENT: + pr_debug("priv ioctl VIV_VIDIOC_CONTROL_EVENT\n"); + control_event = (struct viv_control_event *)arg; + rc = viv_post_control_event(handle->streamid, &handle->vfh, + control_event); + break; + case VIV_VIDIOC_QUERY_EXTMEM: + pr_debug("priv ioctl VIV_VIDIOC_QUERY_EXTMEM\n"); + ext_buf = (struct ext_buf_info *)arg; + rmem = (struct reserved_mem *)dev->rmem; + if (!rmem) { + ext_buf->addr = 0; + ext_buf->size = 0; + } else { + ext_buf->addr = rmem->base; + ext_buf->size = rmem->size; + } + break; + case VIV_VIDIOC_S_MODEINFO: + rc = viv_set_modeinfo(handle, arg); + break; + + case VIV_VIDIOC_S_CAPS_MODE: + memcpy(&(dev->caps_mode), arg, sizeof(dev->caps_mode)); + rc = set_caps_mode_event(file); + if (rc == 0) + rc = dev->event_result; + break; + + case VIV_VIDIOC_G_CAPS_MODE: + memcpy(arg, &(dev->caps_mode), sizeof(dev->caps_mode)); + break; + + case VIV_VIDIOC_EVENT_RESULT: + dev->event_result = *(int *)arg; + break; + + case VIV_VIDIOC_GET_CAPS_SUPPORTS:{ + pcaps_supports = (struct viv_caps_supports *)arg; + rc = get_caps_suppots_event(file); + memcpy(pcaps_supports, &(dev->caps_supports), + sizeof(dev->caps_supports)); + break; + } + + case VIV_VIDIOC_SET_CAPS_SUPPORTS: + pcaps_supports = (struct viv_caps_supports *)arg; + memcpy(&(dev->caps_supports), arg, sizeof(dev->caps_supports)); + break; + } + return rc; +} + +static int video_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct viv_video_device *dev = video_drvdata(file); + + pr_debug("enter %s\n", __func__); + strcpy(cap->driver, "viv_v4l2_device"); + strcpy(cap->card, "VIV"); + cap->bus_info[0] = 0; + if (dev) + snprintf((char *)cap->bus_info, sizeof(cap->bus_info), + "platform:viv%d", dev->id); + + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_STREAMING | V4L2_CAP_DEVICE_CAPS; + cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + return 0; +} + +static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct viv_video_device *dev = video_drvdata(file); + + if (f->index < dev->formatscount) { + f->pixelformat = dev->formats[f->index].fourcc; + return 0; + } + return -EINVAL; +} + +static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + *f = handle->vdev->fmt; + return 0; +} + +static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viv_video_device *dev = video_drvdata(file); + struct viv_video_fmt *format = NULL; + int bytesperline, sizeimage; + int i; + + pr_debug("enter %s\n", __func__); + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + for (i = 0; i < dev->formatscount; ++i) { + if (dev->formats[i].fourcc == f->fmt.pix.pixelformat) { + format = &dev->formats[i]; + break; + } + } + if (format == NULL) + return -EINVAL; + + f->fmt.pix.field = dev->fmt.fmt.pix.field; + f->fmt.pix.colorspace = dev->fmt.fmt.pix.colorspace; + init_v4l2_fmt(f, format->bpp, format->depth, &bytesperline, &sizeimage); + if (f->fmt.pix.bytesperline < bytesperline) + f->fmt.pix.bytesperline = bytesperline; + if (f->fmt.pix.sizeimage < sizeimage) + f->fmt.pix.sizeimage = sizeimage; + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int ret; + + pr_debug("enter %s\n", __func__); + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + ret = vidioc_try_fmt_vid_cap(file, priv, f); + + if (ret < 0) + return -EINVAL; + + handle->vdev->fmt = *f; + return ret; +} + +static int vidioc_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *p) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct viv_video_file *ph; + struct viv_video_device *vdev = handle->vdev; + struct v4l2_event event; + struct viv_video_event *v_event; + unsigned long flags; + int ret = 0; + + pr_debug("enter %s %d %d\n", __func__, p->count, p->memory); + if (p->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + spin_lock_irqsave(&file_list_lock[vdev->id], flags); + list_for_each_entry(ph, &file_list_head[vdev->id], entry) { + if (ph->streamid == handle->streamid && + ph != handle && ph->req) { + pr_err("stream is busy %d\n", ph->streamid); + spin_unlock_irqrestore(&file_list_lock[vdev->id], + flags); + return -EBUSY; + } + } + spin_unlock_irqrestore(&file_list_lock[vdev->id], flags); + + if (p->count == 0) + handle->req = false; + else + handle->req = true; + + mutex_lock(&handle->buffer_mutex); + ret = vb2_reqbufs(&handle->queue, p); + mutex_unlock(&handle->buffer_mutex); + + if (p->count == 0) { + memset(p, 0, sizeof(*p)); + return ret; + } + if (ret < 0) + return ret; + + if (handle->streamid < 0 || handle->state > 0) + return ret; + handle->state = 1; + ret = + viv_post_simple_event(VIV_VIDEO_EVENT_NEW_STREAM, handle->streamid, + &handle->vfh, true); + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = handle->streamid; + v_event->file = &handle->vfh; + v_event->addr = handle->vdev->fmt.fmt.pix.width; + v_event->response = handle->vdev->fmt.fmt.pix.height; + v_event->buf_index = handle->vdev->fmt.fmt.pix.pixelformat; + v_event->sync = true; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_SET_FMT; + return viv_post_event(&event, &handle->vfh, true); +} + +static int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int rc = 0; + + pr_debug("enter %s\n", __func__); + + if (p->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + mutex_lock(&handle->buffer_mutex); + rc = vb2_querybuf(&handle->queue, p); + mutex_unlock(&handle->buffer_mutex); + return rc; +} + +static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int rc = 0; + + if (p->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + mutex_lock(&handle->buffer_mutex); +#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 0, 0) + rc = vb2_qbuf(&handle->queue, NULL, p); +#else + rc = vb2_qbuf(&handle->queue, p); +#endif + mutex_unlock(&handle->buffer_mutex); + return rc; +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int rc = 0; + + rc = vb2_dqbuf(&handle->queue, p, file->f_flags & O_NONBLOCK); + p->field = V4L2_FIELD_NONE; + p->sequence = handle->sequence++; + return rc; +} + +static int vidioc_expbuf(struct file *file, void *priv, + struct v4l2_exportbuffer *p) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + + pr_debug("enter %s\n", __func__); + return vb2_expbuf(&handle->queue, p); +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + + pr_debug("enter %s\n", __func__); + return vb2_streamon(&handle->queue, i); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int rc; + + pr_debug("enter %s\n", __func__); + + mutex_lock(&handle->buffer_mutex); + rc = vb2_streamoff(&handle->queue, i); + mutex_unlock(&handle->buffer_mutex); + return rc; +} + +static int vidioc_enum_input(struct file *filep, void *fh, + struct v4l2_input *input) +{ + if (input->index > 0) + return -EINVAL; + + strlcpy(input->name, "camera", sizeof(input->name)); + input->type = V4L2_INPUT_TYPE_CAMERA; + + return 0; +} + +static int vidioc_g_input(struct file *filep, void *fh, unsigned int *input) +{ + *input = 0; + return 0; +} + +static int vidioc_s_input(struct file *filep, void *fh, unsigned int input) +{ + return input == 0 ? 0 : -EINVAL; +} + +static int vidioc_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *fsize) +{ + struct viv_video_device *dev = video_drvdata(file); + struct viv_video_file *handle = priv_to_handle(file->private_data); + int i; + + if (dev->modeinfocount == 0) { + viv_post_simple_event(VIV_VIDEO_EVENT_CREATE_PIPELINE, + handle->streamid, &handle->vfh, true); + } + + if (fsize->index >= dev->modeinfocount) + return -EINVAL; + + for (i = 0; i < dev->formatscount; ++i) + if (dev->formats[i].fourcc == fsize->pixel_format) + break; + + if (i == dev->formatscount) + return -EINVAL; +#if 0 + fsize->stepwise.min_width = 320; + fsize->stepwise.max_width = dev->modeinfo[fsize->index].w; + fsize->stepwise.step_width = 2; + fsize->stepwise.min_height = 240; + fsize->stepwise.max_height = dev->modeinfo[fsize->index].h; + fsize->stepwise.step_height = 2; + + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; +#else + fsize->discrete.width = dev->modeinfo[fsize->index].w; + fsize->discrete.height = dev->modeinfo[fsize->index].h; + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; +#endif + return 0; +} + +static inline void update_timeperframe(struct file *file) +{ + struct viv_video_device *dev = video_drvdata(file); + int i; + + if (dev->timeperframe.numerator == 0 || + dev->timeperframe.denominator == 0) { + dev->timeperframe.numerator = 1; + dev->timeperframe.denominator = 30; + for (i = 0; i < dev->modeinfocount; ++i) { + if (dev->fmt.fmt.pix.width == dev->modeinfo[i].w && + dev->fmt.fmt.pix.height == dev->modeinfo[i].h) { + dev->timeperframe.denominator = + dev->modeinfo[i].fps; + break; + } + } + } +} + +static int vidioc_g_parm(struct file *file, void *fh, + struct v4l2_streamparm *a) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + + if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + update_timeperframe(file); + + memset(&a->parm, 0, sizeof(a->parm)); + a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + a->parm.capture.timeperframe = handle->vdev->timeperframe; + return 0; +} + +static int vidioc_s_parm(struct file *file, void *fh, + struct v4l2_streamparm *a) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + + if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (a->parm.capture.timeperframe.numerator == 0 || + a->parm.capture.timeperframe.denominator == 0) { + update_timeperframe(file); + memset(&a->parm, 0, sizeof(a->parm)); + a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + a->parm.capture.timeperframe = handle->vdev->timeperframe; + return 0; + } + handle->vdev->timeperframe = a->parm.output.timeperframe; + return 0; +} + +static int vidioc_enum_frameintervals(struct file *filp, void *priv, + struct v4l2_frmivalenum *fival) +{ + struct viv_video_device *dev = video_drvdata(filp); + struct viv_video_file *handle = priv_to_handle(filp->private_data); + int i, count = fival->index; + + if (dev->modeinfocount == 0) { + viv_post_simple_event(VIV_VIDEO_EVENT_CREATE_PIPELINE, + handle->streamid, &handle->vfh, true); + } + + if (fival->index >= dev->modeinfocount) + return -EINVAL; + + for (i = 0; i < dev->formatscount; ++i) + if (dev->formats[i].fourcc == fival->pixel_format) + break; + + if (i == dev->formatscount) + return -EINVAL; + + for (i = 0; i < dev->modeinfocount; ++i) { + if (fival->width != dev->modeinfo[i].w || + fival->height != dev->modeinfo[i].h) + continue; + if (count > 0) { + count--; + continue; + } + fival->stepwise.min.numerator = 1; + fival->stepwise.min.denominator = dev->modeinfo[i].fps; + fival->stepwise.max.numerator = 1; + fival->stepwise.max.denominator = 1; + fival->stepwise.step.numerator = 1; + fival->stepwise.step.denominator = dev->modeinfo[i].fps; + fival->type = V4L2_FRMSIZE_TYPE_STEPWISE; + return 0; + } + return -EINVAL; +} + +static int vidioc_g_pixelaspect(struct file *file, void *fh, + int buf_type, struct v4l2_fract *aspect) +{ + if (buf_type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + pr_debug("%s not implemented\n", __func__); + return 0; +} + +static int vidioc_g_selection(struct file *file, void *fh, + struct v4l2_selection *s) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct viv_video_device *vdev = handle->vdev; + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (vdev->modeinfocount == 0) { + viv_post_simple_event(VIV_VIDEO_EVENT_CREATE_PIPELINE, + handle->streamid, &handle->vfh, true); + } + + switch (s->target) { + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + s->r.left = 0; + s->r.top = 0; + s->r.width = vdev->modeinfo[0].w; + s->r.height = vdev->modeinfo[0].h; + break; + case V4L2_SEL_TGT_CROP: + s->r = vdev->crop; + break; + + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + s->r.left = 0; + s->r.top = 0; + s->r.width = vdev->modeinfo[0].w; + s->r.height = vdev->modeinfo[0].h; + break; + case V4L2_SEL_TGT_COMPOSE: + s->r = vdev->compose; + break; + default: + return -EINVAL; + } + return 0; +} + +static int vidioc_s_selection(struct file *file, void *fh, + struct v4l2_selection *s) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + struct viv_video_device *vdev = handle->vdev; + struct v4l2_rect *r; + struct v4l2_event event; + struct viv_video_event *v_event; + struct viv_rect *rect = (struct viv_rect *)handle->event_buf.va; + int rc; + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (vdev->modeinfocount == 0) { + viv_post_simple_event(VIV_VIDEO_EVENT_CREATE_PIPELINE, + handle->streamid, &handle->vfh, true); + } + + switch (s->target) { + case V4L2_SEL_TGT_CROP: + r = &vdev->crop; + break; + case V4L2_SEL_TGT_COMPOSE: + r = &vdev->compose; + break; + default: + return -EINVAL; + } + + if (s->r.top < 0 || s->r.left < 0) + return -EINVAL; + + if (s->r.width == 0 || s->r.height == 0 || + s->r.width > 3840 || s->r.height > 2160) + return -EINVAL; + + if (s->target == V4L2_SEL_TGT_CROP) { + if (s->r.left + s->r.width > vdev->modeinfo[0].w || + s->r.top + s->r.height > vdev->modeinfo[0].h) + return -EINVAL; + } + + if (!rect) + return -ENOMEM; + + rect->left = s->r.left; + rect->top = s->r.top; + rect->width = s->r.width; + rect->height = s->r.height; + + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = handle->streamid; + v_event->file = &(handle->vfh); + v_event->sync = true; + v_event->addr = handle->event_buf.pa; + event.type = VIV_VIDEO_EVENT_TYPE; + if (s->target == V4L2_SEL_TGT_CROP) + event.id = VIV_VIDEO_EVENT_SET_CROP; + else + event.id = VIV_VIDEO_EVENT_SET_COMPOSE; + rc = viv_post_event(&event, &handle->vfh, true); + if (rc == 0) { + s->r.left = rect->left; + s->r.top = rect->top; + s->r.width = rect->width; + s->r.height = rect->height; + *r = s->r; + } + return rc; +} + +int viv_gen_g_ctrl(struct v4l2_ctrl *ctrl) +{ + struct viv_custom_ctrls *cc = + container_of(ctrl->handler, struct viv_custom_ctrls, handler); + struct viv_video_device *vdev = + container_of(cc, struct viv_video_device, ctrls); + struct v4l2_event event; + struct viv_video_event *v_event; + struct v4l2_ctrl_data *p_data; + struct v4l2_ext_control *p_ctrl; + + pr_debug("%s:ctrl->id=0x%x\n", __func__, ctrl->id); + memset(&event, 0, sizeof(event)); + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->file = NULL; + v_event->sync = true; + v_event->addr = vdev->ctrls.buf_pa; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_EXTCTRL2; + + p_data = (struct v4l2_ctrl_data *)vdev->ctrls.buf_va; + if (unlikely(!p_data)) + return -ENOMEM; + + memset(p_data, 0, sizeof(*p_data)); + p_data->dir = V4L2_CTRL_GET; + p_data->ctrls.count = 1; + p_ctrl = nextof(p_data, struct v4l2_ext_control *); + p_ctrl->id = ctrl->id; + + reinit_completion(&vdev->ctrls.wait); + + v4l2_event_queue(vdev->video, &event); + + if (wait_for_completion_timeout(&vdev->ctrls.wait, + msecs_to_jiffies(VIV_VIDEO_EVENT_TIMOUT_MS)) == 0) { + pr_err("connecting to server timed out (g)!"); + *ctrl->p_new.p_s32 = *ctrl->p_cur.p_s32; + return 0; + } + + if (p_ctrl->id == ctrl->id && !p_data->ret) { + *ctrl->p_new.p_s32 = p_ctrl->value; + return 0; + } + return -EINVAL; +} + +int viv_gen_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct viv_custom_ctrls *cc = + container_of(ctrl->handler, struct viv_custom_ctrls, handler); + struct viv_video_device *vdev = + container_of(cc, struct viv_video_device, ctrls); + struct v4l2_event event; + struct viv_video_event *v_event; + struct v4l2_ctrl_data *p_data; + struct v4l2_ext_control *p_ctrl; + + pr_debug("%s:ctrl->id=0x%x\n", __func__, ctrl->id); + memset(&event, 0, sizeof(event)); + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->file = NULL; + v_event->sync = true; + v_event->addr = vdev->ctrls.buf_pa; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_EXTCTRL2; + + p_data = (struct v4l2_ctrl_data *)vdev->ctrls.buf_va; + if (unlikely(!p_data)) + return -ENOMEM; + + memset(p_data, 0, sizeof(*p_data)); + p_data->dir = V4L2_CTRL_SET; + p_data->ctrls.count = 1; + p_ctrl = nextof(p_data, struct v4l2_ext_control *); + p_ctrl->id = ctrl->id; + p_ctrl->value = *ctrl->p_new.p_s32; + + reinit_completion(&vdev->ctrls.wait); + + v4l2_event_queue(vdev->video, &event); + + if (wait_for_completion_timeout(&vdev->ctrls.wait, + msecs_to_jiffies(VIV_VIDEO_EVENT_TIMOUT_MS)) == 0) { + pr_err("connecting to server timed out (s)!"); + return 0; + } + + if (p_ctrl->id == ctrl->id && !p_data->ret) + return 0; + return -EINVAL; +} + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = video_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_expbuf = vidioc_expbuf, + .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_subscribe_event = subscribe_event, + .vidioc_unsubscribe_event = unsubscribe_event, + .vidioc_default = private_ioctl, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_enum_framesizes = vidioc_enum_framesizes, + .vidioc_enum_frameintervals = vidioc_enum_frameintervals, + .vidioc_g_parm = vidioc_g_parm, + .vidioc_s_parm = vidioc_s_parm, + .vidioc_g_pixelaspect = vidioc_g_pixelaspect, + .vidioc_g_selection = vidioc_g_selection, + .vidioc_s_selection = vidioc_s_selection, +}; + +/* sys /dev/mem can't map large memory size */ +static int viv_private_mmap(struct file *file, struct vm_area_struct *vma) +{ + /* Map reserved video memory. */ + if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) + return -EAGAIN; + return 0; +} + +int vidioc_mmap(struct file *file, struct vm_area_struct *vma) +{ + int rc; + struct viv_video_file *handle = priv_to_handle(file->private_data); + +#ifndef ENABLE_IRQ + struct viv_video_device *dev = video_drvdata(file); + struct reserved_mem *rmem = (struct reserved_mem *)dev->rmem; + unsigned long reserved_base_addr = 0; + if (!rmem) + reserved_base_addr = 0; + else + reserved_base_addr = rmem->base; +#endif + +#ifdef ENABLE_IRQ + if (handle->streamid < 0) +#else + if (vma->vm_pgoff >= (reserved_base_addr >> PAGE_SHIFT)) +#endif + rc = viv_private_mmap(file, vma); + else + rc = vb2_mmap(&handle->queue, vma); + return rc; +} + +static unsigned int video_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct viv_video_file *handle = priv_to_handle(file->private_data); + int rc = 0; + + if (handle->streamid < 0) { + poll_wait(file, &handle->vfh.wait, wait); + + if (v4l2_event_pending(&handle->vfh)) + rc = POLLIN | POLLRDNORM; + } else { + mutex_lock(&handle->buffer_mutex); + rc = vb2_poll(&handle->queue, file, wait) | + v4l2_ctrl_poll(file, wait); + mutex_unlock(&handle->buffer_mutex); + } + return rc; +} + +static struct v4l2_file_operations video_ops = { + .owner = THIS_MODULE, + .open = video_open, + .release = video_close, + .poll = video_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = vidioc_mmap, +}; + +static void pdev_release(struct device *dev) +{ + pr_debug("enter %s\n", __func__); +} + +static struct platform_device viv_pdev = { + .name = "vvcam-video", + .dev.release = pdev_release, +}; + +static int viv_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct v4l2_event event; + struct viv_video_event *v_event; + struct viv_custom_ctrls *cc = + container_of(ctrl->handler, struct viv_custom_ctrls, handler); + struct viv_video_device *vdev = + container_of(cc, struct viv_video_device, ctrls); + int ret = -1; + char *szbuf = NULL; + unsigned long timeout = + msecs_to_jiffies(VIV_VIDEO_EVENT_TIMOUT_MS); + + switch (ctrl->id) { + case V4L2_CID_VIV_STRING: { + ret = 0; + szbuf = (char *)vdev->ctrls.buf_va; + if (!ctrl->p_new.p_char || !szbuf) + return -EINVAL; + strcpy(szbuf, ctrl->p_new.p_char); + v_event = (struct viv_video_event *)&event.u.data[0]; + v_event->stream_id = 0; + v_event->file = NULL; + v_event->sync = true; + v_event->addr = vdev->ctrls.buf_pa; + event.type = VIV_VIDEO_EVENT_TYPE; + event.id = VIV_VIDEO_EVENT_EXTCTRL; + + reinit_completion(&vdev->ctrls.wait); + + v4l2_event_queue(vdev->video, &event); + + if (!wait_for_completion_timeout(&vdev->ctrls.wait, timeout)) + ret = -ETIMEDOUT; + strcpy(ctrl->p_new.p_char, szbuf); + break; + } + } + return ret; +} + +static const struct v4l2_ctrl_ops viv_ctrl_ops = { + .s_ctrl = viv_s_ctrl, +}; + +static const struct v4l2_ctrl_config viv_ext_ctrl = { + .ops = &viv_ctrl_ops, + .id = V4L2_CID_VIV_STRING, + .name = "viv_ext_ctrl", + .type = V4L2_CTRL_TYPE_STRING, + .max = VIV_JSON_BUFFER_SIZE-1, + .step = 1, +}; + +#ifdef ENABLE_IRQ +static int viv_notifier_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *sd, struct v4l2_async_subdev *asd) +{ + int i; + struct viv_video_device *dev = container_of(notifier, + struct viv_video_device, subdev_notifier); + + if (!dev) + return 0; + + for (i = 0; i < dev->asdcount; ++i) { + if (dev->asd[i]->match_type == V4L2_ASYNC_MATCH_FWNODE) { + if (sd->dev && dev->asd[i]->match.fwnode == + of_fwnode_handle(sd->dev->of_node)) { + dev->subdevs[dev->sdcount] = sd; + dev->sdcount++; + break; + } + } else if (dev->asd[i]->match_type == + V4L2_ASYNC_MATCH_DEVNAME) { + if (sd->dev && !strcmp(dev->asd[i]->match.device_name, + dev_name(sd->dev))) { + dev->subdevs[dev->sdcount] = sd; + dev->sdcount++; + break; + } + } + } + return 0; +} + +static int viv_notifier_complete(struct v4l2_async_notifier *notifier) +{ + struct viv_video_device *dev = container_of(notifier, + struct viv_video_device, subdev_notifier); + int rc; + + if (!dev) + return 0; + + if (dev->sdcount > 0) { + mutex_lock(&dev->mdev->graph_mutex); + rc = viv_create_default_links(dev); + mutex_unlock(&dev->mdev->graph_mutex); + + if (rc) { + pr_err("failed to create media links!\n"); + return rc; + } + } + + return v4l2_device_register_subdev_nodes(dev->v4l2_dev); +} + +static const struct v4l2_async_notifier_operations sd_async_notifier_ops = { + .bound = viv_notifier_bound, + .complete = viv_notifier_complete, +}; + +static int viv_mdev_link_notify(struct media_link *link, unsigned int flags, + unsigned int notification) +{ + return 0; +} + +static const struct media_device_ops viv_mdev_ops = { + .link_notify = viv_mdev_link_notify, +}; + +static int viv_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +static const struct media_entity_operations viv_media_ops = { + .link_setup = viv_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +static void viv_buf_notify(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf) +{ + struct viv_video_file *fh; + struct viv_video_device *vdev; + u64 cur_ts, interval; + u32 fps; + int i; + + if (!buf || buf->vb.vb2_buf.state != VB2_BUF_STATE_ACTIVE) + return; + + fh = container_of(buf->vb.vb2_buf.vb2_queue, + struct viv_video_file, queue); + vdev = fh->vdev; + if (!vdev->active) + return; + buf->vb.vb2_buf.planes[DEF_PLANE_NO].bytesused = + vdev->fmt.fmt.pix.sizeimage; + cur_ts = ktime_get_ns(); +#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 0, 0) + buf->vb.vb2_buf.timestamp = cur_ts; +#endif + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + /* print fps info for debugging purpose */ + interval = ktime_us_delta(cur_ts,vdev->last_ts); + for (i = 0; i < VIDEO_NODE_NUM; i++) { + if (vdev->id == i) { + if (vdev->duration >= 3 * 1000000/*ms*/) { + vdev->loop_cnt[i]++; + if (vdev->loop_cnt[i] >= 10) { + fps = vdev->frameCnt[i] * 100000000 / vdev->duration; + pr_info("###### video%d(%d) %d.%02d fps ######\n", + vdev->video->num, vdev->id, + fps / 100, fps % 100); + vdev->loop_cnt[i] = 0; + } + vdev->frameCnt[i] = 0; + vdev->duration = 0; + } else if (interval > 0) { + vdev->frameCnt[i]++; + vdev->duration += interval; + } + } + } + vdev->last_ts = cur_ts; +} + +static const struct vvbuf_ops viv_buf_ops = { + .notify = viv_buf_notify, +}; +#endif + +struct dev_node { + enum v4l2_async_match_type match_type; + struct device_node *node; + int id; + const char *name; +}; +static const char * const dwe_dev_compat_name[] = { + "ffe4130000.dwe", "fsl,fake-imx8mp-dwe.1"}; + +#ifdef ENABLE_IRQ +static inline int viv_find_compatible_nodes(struct dev_node *nodes, int size) +{ + static const char * const compat_name[] = { + ISP_COMPAT_NAME}; + struct device_node *node, *avail; + int i, rc, id, cnt = 0; + + for (i = 0; i < ARRAY_SIZE(compat_name) && cnt < size; ++i) { + node = NULL; + for (; cnt < size;) { + node = of_find_compatible_node(node, + NULL, compat_name[i]); + if (!node) + break; + avail = NULL; + id = -1; + rc = fwnode_property_read_u32( + of_fwnode_handle(node), "id", &id); + if (rc) { + if (of_device_is_available(node)) + avail = node; + } else if (of_device_is_available(node)) + avail = node; + + if (avail) { + nodes[cnt].node = avail; + nodes[cnt].id = id; + nodes[cnt].match_type = V4L2_ASYNC_MATCH_FWNODE; + cnt++; + + nodes[cnt].id = id; + nodes[cnt].match_type = V4L2_ASYNC_MATCH_DEVNAME; + nodes[cnt].name = dwe_dev_compat_name[id]; + cnt++; + } + } + } + return cnt; +} +#endif + +static struct reserved_mem * viv_find_isp_reserve_mem(int dev_id) +{ + int i,rc; + int id=0; + struct device_node *node = NULL; + struct device_node *mem_node; + + for (i=0; idev; + media_device_init(&mdev); + pr_info("%s:%d\n", __func__, __LINE__); +#endif + + for (i = 0; i < VIDEO_NODE_NUM; i++) { + pr_info("%s:%d\n", __func__, __LINE__); + spin_lock_init(&file_list_lock[i]); + INIT_LIST_HEAD(&file_list_head[i]); + + vvdev[i] = kzalloc(sizeof(*vdev), GFP_KERNEL); + if (WARN_ON(!vvdev[i])) { + rc = -ENOMEM; + goto probe_end; + } + vdev = vvdev[i]; + vdev->id = i; + vdev->rmem = viv_find_isp_reserve_mem(vdev->id); + vdev->v4l2_dev = kzalloc(sizeof(*vdev->v4l2_dev), GFP_KERNEL); + if (WARN_ON(!vdev->v4l2_dev)) { + rc = -ENOMEM; + goto probe_end; + } + pr_info("%s:%d\n", __func__, __LINE__); + init_completion(&vdev->subscribed_wait); + vdev->subscribed_cnt = 0; + vdev->video = video_device_alloc(); + vdev->video->v4l2_dev = vdev->v4l2_dev; + rc = v4l2_device_register(&pdev->dev, vdev->video->v4l2_dev); + if (WARN_ON(rc < 0)) + goto register_fail; + pr_info("%s:%d\n", __func__, __LINE__); + sprintf(vdev->video->name, "viv_v4l2%d", i); + v4l2_ctrl_handler_init(&vdev->ctrls.handler, 1); + vdev->ctrls.request = v4l2_ctrl_new_custom(&vdev->ctrls.handler, + &viv_ext_ctrl, NULL); + create_controls(&vdev->ctrls.handler); + pr_info("%s:%d\n", __func__, __LINE__); + + vdev->video->release = video_device_release; + vdev->video->fops = &video_ops; + vdev->video->ioctl_ops = &video_ioctl_ops; + vdev->video->minor = -1; + vdev->video->vfl_type = VFL_TYPE_GRABBER; + vdev->video->ctrl_handler = &vdev->ctrls.handler; +#if LINUX_VERSION_CODE > KERNEL_VERSION(5, 0, 0) + vdev->video->device_caps = + V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; +#endif +#ifdef ENABLE_IRQ + video_set_drvdata(vdev->video, vdev); + pr_info("%s:%d\n", __func__, __LINE__); + + + vvbuf_ctx_init(&vdev->bctx); + vdev->bctx.ops = &viv_buf_ops; + + vdev->mdev = &mdev; + vdev->v4l2_dev->mdev = &mdev; + + vdev->video->entity.name = vdev->video->name; + vdev->video->entity.obj_type = MEDIA_ENTITY_TYPE_VIDEO_DEVICE; + vdev->video->entity.function = MEDIA_ENT_F_IO_V4L; + vdev->video->entity.ops = &viv_media_ops; + + vdev->pad.flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT; + rc = media_entity_pads_init(&vdev->video->entity, + 1, &vdev->pad); + if (WARN_ON(rc < 0)) + goto register_fail; + pr_info("%s:%d\n", __func__, __LINE__); + v4l2_async_notifier_init(&vdev->subdev_notifier); + pr_info("%s:%d\n", __func__, __LINE__); + vdev->subdev_notifier.ops = &sd_async_notifier_ops; +#endif + rc = video_register_device(vdev->video, VFL_TYPE_GRABBER, -1); + if (WARN_ON(rc < 0)) + goto register_fail; + pr_info("%s:%d\n", __func__, __LINE__); + +#ifdef ENABLE_IRQ + for (j = 0; j < nodecount; ++j) { + pr_info("%s:%d i=%d, j=%d, nodes[j].id=%d\n", __func__, __LINE__, i, j, nodes[j].id); + if (nodes[j].id == i) { + pr_info("%s:%d nodes[j].match_type=%d\n", __func__, __LINE__, nodes[j].match_type); + switch (nodes[j].match_type) { + case V4L2_ASYNC_MATCH_FWNODE: + asd = v4l2_async_notifier_add_fwnode_subdev( + &vdev->subdev_notifier, + of_fwnode_handle(nodes[j].node), + sizeof(struct v4l2_async_subdev)); + pr_info("%s:%d\n", __func__, __LINE__); + break; + case V4L2_ASYNC_MATCH_DEVNAME: + asd = v4l2_async_notifier_add_devname_subdev( + &vdev->subdev_notifier, + nodes[j].name, + sizeof(struct v4l2_async_subdev)); + pr_info("%s:%d nodes[j].name=%s\n", __func__, __LINE__, nodes[j].name); + break; + default: + asd = NULL; + break; + } + if (asd) { + vdev->asd[vdev->asdcount] = asd; + vdev->asdcount++; + } + } + } + + rc = v4l2_async_notifier_register(vdev->v4l2_dev, + &vdev->subdev_notifier); + if (WARN_ON(rc < 0)) + goto register_fail; + pr_info("%s:%d\n", __func__, __LINE__); +#else + video_set_drvdata(vdev->video, vdev); + + rc = v4l2_device_register_subdev_nodes(vdev->v4l2_dev); +#endif + + vdev->ctrls.buf_va = kmalloc(VIV_JSON_BUFFER_SIZE, GFP_KERNEL); + vdev->ctrls.buf_pa = __pa(vdev->ctrls.buf_va); + init_completion(&vdev->ctrls.wait); + pr_info("%s:%d\n", __func__, __LINE__); + + vdev->fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + vdev->fmt.fmt.pix.field = V4L2_FIELD_NONE; + vdev->fmt.fmt.pix.colorspace = V4L2_COLORSPACE_REC709; + + if (sizeof(vdev->formats) >= sizeof(formats)) { + memcpy(vdev->formats, formats, sizeof(formats)); + vdev->formatscount = ARRAY_SIZE(formats); + } + for (m = 0; m < VIDEO_NODE_NUM; m++) { + vdev->loop_cnt[m] = 0; + vdev->frameCnt[m] = 0; + } + vdev->duration = 0; + vdev->last_ts = 0; + pr_info("%s:%d\n", __func__, __LINE__); + continue; +register_fail: + pr_info("%s:%d\n", __func__, __LINE__); + video_device_release(vdev->video); + } +#ifdef ENABLE_IRQ + if (!rc) + rc = media_device_register(&mdev); + pr_info("%s:%d\n", __func__, __LINE__); +#endif +probe_end: + pr_info("%s:%d\n", __func__, __LINE__); + return rc; +} + +static int viv_video_remove(struct platform_device *pdev) +{ + struct viv_video_device *vdev; + int i; + + for (i = VIDEO_NODE_NUM-1; i >= 0; i--) { + vdev = vvdev[i]; + if (!vdev || !vdev->video) + continue; +#ifdef ENABLE_IRQ + media_entity_cleanup(&vdev->video->entity); + v4l2_async_notifier_cleanup(&vdev->subdev_notifier); + v4l2_async_notifier_unregister(&vdev->subdev_notifier); + v4l2_device_unregister(vdev->v4l2_dev); + kfree(vdev->v4l2_dev); +#endif + video_unregister_device(vdev->video); +#ifdef ENABLE_IRQ + vvbuf_ctx_deinit(&vdev->bctx); +#else + v4l2_device_disconnect(vdev->video->v4l2_dev); + v4l2_device_put(vdev->video->v4l2_dev); +#endif + + kfree(vdev->ctrls.buf_va); + v4l2_ctrl_handler_free(&vdev->ctrls.handler); + kfree(vvdev[i]); + vvdev[i] = NULL; + } + +#ifdef ENABLE_IRQ + media_device_unregister(&mdev); + media_device_cleanup(&mdev); +#endif + return 0; +} + +static struct platform_driver viv_video_driver = { + .probe = viv_video_probe, + .remove = viv_video_remove, + .driver = { + .name = "vvcam-video", + .owner = THIS_MODULE, + }, +}; + +static int __init viv_video_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + ret = platform_device_register(&viv_pdev); + if (ret) { + pr_err("register platform device failed.\n"); + return ret; + } + + ret = platform_driver_register(&viv_video_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + platform_device_unregister(&viv_pdev); + return ret; + } + return ret; +} + +static void __exit viv_video_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_video_driver); + msleep(100); + platform_device_unregister(&viv_pdev); +} + +module_init(viv_video_init_module); +module_exit(viv_video_exit_module); + +MODULE_DESCRIPTION("Verisilicon V4L2 video driver"); +MODULE_AUTHOR("Verisilicon ISP SW Team"); +MODULE_LICENSE("GPL v2"); diff --git a/vvcam_ry/v4l2/video/video.h b/vvcam_ry/v4l2/video/video.h new file mode 100755 index 0000000..2002b2a --- /dev/null +++ b/vvcam_ry/v4l2/video/video.h @@ -0,0 +1,140 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _ISP_VIDEO_H_ +#define _ISP_VIDEO_H_ + +#include +#include +#include +#include +#include +#include + +#include "viv_video_kevent.h" +#include "vvbuf.h" + +#define MAX_SUBDEVS_NUM (8) +#define VIDEO_NODE_NUM (2) + +struct viv_custom_ctrls { + struct v4l2_ctrl_handler handler; + struct v4l2_ctrl *request; + uint64_t buf_pa; + void __iomem *buf_va; + struct completion wait; +}; + +struct viv_video_fmt { + int fourcc; + int depth; + int bpp; +}; + +struct viv_video_device { + struct vvbuf_ctx bctx; + struct video_device *video; + struct v4l2_device *v4l2_dev; + struct v4l2_async_notifier subdev_notifier; + struct v4l2_subdev *subdevs[MAX_SUBDEVS_NUM]; + int sdcount; + struct v4l2_async_subdev *asd[MAX_SUBDEVS_NUM]; + int asdcount; + struct media_device *mdev; + struct media_pad pad; + struct v4l2_format fmt; + struct v4l2_fract timeperframe; + struct v4l2_rect crop, compose; + struct viv_custom_ctrls ctrls; + struct vvcam_constant_modeinfo modeinfo[20]; + int modeinfocount; + struct viv_video_fmt formats[20]; + int formatscount; + int id; + struct viv_caps_mode_s caps_mode; + int event_result; + bool dweEnabled; + struct viv_caps_supports caps_supports; + u64 duration, last_ts, frameCnt[VIDEO_NODE_NUM]; + u32 loop_cnt[VIDEO_NODE_NUM]; + struct completion subscribed_wait; + int subscribed_cnt; + int active; + void *rmem; +}; + +struct viv_video_file { + struct v4l2_fh vfh; + int streamid; + int state; /* 0-free,1-ready,2-streaming,-1-closed */ + int sequence; + bool req; + bool capsqueried; + struct vb2_queue queue; + struct mutex event_mutex; + struct mutex buffer_mutex; + struct completion wait; + struct list_head entry; + struct viv_video_device *vdev; +#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG + struct list_head extdmaqueue; +#endif + struct { + uint64_t pa; + void *va; + } event_buf; +}; + +#define priv_to_handle(priv) container_of(priv, struct viv_video_file, vfh) +#define queue_to_handle(__q) container_of(__q, struct viv_video_file, queue) + +#endif /* _ISP_VIDEO_H_ */ diff --git a/vvcam_ry/v4l2/video/vvbuf.c b/vvcam_ry/v4l2/video/vvbuf.c new file mode 100755 index 0000000..6c35138 --- /dev/null +++ b/vvcam_ry/v4l2/video/vvbuf.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include + +#include "vvbuf.h" + +#ifdef ENABLE_IRQ + +void vvbuf_ctx_init(struct vvbuf_ctx *ctx) +{ + if (unlikely(!ctx)) + return; + + spin_lock_init(&ctx->irqlock); + INIT_LIST_HEAD(&ctx->dmaqueue); +} + +void vvbuf_ctx_deinit(struct vvbuf_ctx *ctx) +{ + /*nop*/ +} + +struct vb2_dc_buf *vvbuf_try_dqbuf(struct vvbuf_ctx *ctx) +{ + struct vb2_dc_buf *buf; + unsigned long flags; + + if (unlikely(!ctx)) + return NULL; + + spin_lock_irqsave(&ctx->irqlock, flags); + if (list_empty(&ctx->dmaqueue)) { + spin_unlock_irqrestore(&ctx->irqlock, flags); + return NULL; + } + + buf = list_first_entry(&ctx->dmaqueue, struct vb2_dc_buf, irqlist); + spin_unlock_irqrestore(&ctx->irqlock, flags); + return buf; +} + +void vvbuf_try_dqbuf_done(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf) +{ + unsigned long flags; + + if (unlikely(!ctx)) + return; + + spin_lock_irqsave(&ctx->irqlock, flags); + if (list_empty(&ctx->dmaqueue)) { + spin_unlock_irqrestore(&ctx->irqlock, flags); + return; + } + + if (buf == list_first_entry(&ctx->dmaqueue, + struct vb2_dc_buf, irqlist)) + list_del(&buf->irqlist); + spin_unlock_irqrestore(&ctx->irqlock, flags); +} + +void vvbuf_ready(struct vvbuf_ctx *ctx, struct media_pad *pad, + struct vb2_dc_buf *buf) +{ + struct video_device *vdev; + struct v4l2_subdev *subdev; + struct vvbuf_ctx *rctx = NULL; + + if (unlikely(!pad || !buf)) + return; + + pad = media_entity_remote_pad(pad); + if (!pad) + return; + + if (is_media_entity_v4l2_video_device(pad->entity)) { + vdev = media_entity_to_video_device(pad->entity); + if (vdev) + rctx = (struct vvbuf_ctx *)video_get_drvdata(vdev); + } else if (is_media_entity_v4l2_subdev(pad->entity)) { + subdev = media_entity_to_v4l2_subdev(pad->entity); + if (subdev) + rctx = (struct vvbuf_ctx *)v4l2_get_subdevdata(subdev); + } + + rctx += pad->index; + buf->pad = pad; + + if (rctx && rctx->ops && rctx->ops->notify) + rctx->ops->notify(rctx, buf); +} + +#endif diff --git a/vvcam_ry/v4l2/video/vvbuf.h b/vvcam_ry/v4l2/video/vvbuf.h new file mode 100755 index 0000000..cfc6bae --- /dev/null +++ b/vvcam_ry/v4l2/video/vvbuf.h @@ -0,0 +1,89 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VVBUF_H_ +#define _VVBUF_H_ + +#include +#include +#include +#include +#include + +struct vb2_dc_buf { + struct vb2_v4l2_buffer vb; + struct media_pad *pad; + struct list_head irqlist; + dma_addr_t dma; + int flags; +}; + +struct vvbuf_ctx; + +struct vvbuf_ops { + void (*notify)(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf); +}; + +struct vvbuf_ctx { + spinlock_t irqlock; + struct list_head dmaqueue; + const struct vvbuf_ops *ops; +}; + +void vvbuf_ctx_init(struct vvbuf_ctx *ctx); +void vvbuf_ctx_deinit(struct vvbuf_ctx *ctx); +struct vb2_dc_buf *vvbuf_try_dqbuf(struct vvbuf_ctx *ctx); +void vvbuf_try_dqbuf_done(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf); +void vvbuf_ready(struct vvbuf_ctx *ctx, struct media_pad *pad, + struct vb2_dc_buf *buf); + +#endif /* _VVBUF_H_ */ diff --git a/vvcam_ry/v4l2/vse_driver.c b/vvcam_ry/v4l2/vse_driver.c new file mode 100755 index 0000000..739cdd3 --- /dev/null +++ b/vvcam_ry/v4l2/vse_driver.c @@ -0,0 +1,246 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vse_driver.h" +#include "vse_ioctl.h" +#define DEVICE_NAME "vvcam-vse" + +int vse_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, 2, NULL); +} + +int vse_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +#ifdef CONFIG_COMPAT +static long vse_ioctl_compat(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct vse_device *vse_dev = v4l2_get_subdevdata(sd); + + return vse_priv_ioctl(&vse_dev->ic_dev, cmd, arg); +} + +long vse_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + return vse_ioctl_compat(sd, cmd, arg); +} +#else /* CONFIG_COMPAT */ +long vse_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct vse_device *vse_dev = v4l2_get_subdevdata(sd); + + return vse_priv_ioctl(&^vse_dev->ic_dev, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +int vse_set_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static struct v4l2_subdev_core_ops vse_v4l2_subdev_core_ops = { + .ioctl = vse_ioctl, + .subscribe_event = vse_subscribe_event, + .unsubscribe_event = vse_unsubscribe_event, +}; + +static struct v4l2_subdev_video_ops vse_v4l2_subdev_video_ops = { + .s_stream = vse_set_stream, +}; + +static struct v4l2_subdev_ops vse_v4l2_subdev_ops = { + .core = &vse_v4l2_subdev_core_ops, + .video = &vse_v4l2_subdev_video_ops, +}; + +int vse_hw_probe(struct platform_device *pdev) +{ + struct vse_device *vse_dev; + int rc = 0; + + pr_info("enter %s\n", __func__); + vse_dev = kzalloc(sizeof(struct vse_device), GFP_KERNEL); + if (!vse_dev) { + rc = -ENOMEM; + goto end; + } + + v4l2_subdev_init(&vse_dev->sd, &vse_v4l2_subdev_ops); + + snprintf(vse_dev->sd.name, sizeof(vse_dev->sd.name), DEVICE_NAME); + vse_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + vse_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; + vse_dev->sd.owner = THIS_MODULE; + v4l2_set_subdevdata(&vse_dev->sd, vse_dev); + vse_dev->vd = kzalloc(sizeof(*vse_dev->vd), GFP_KERNEL); + if (WARN_ON(!vse_dev->vd)) { + rc = -ENOMEM; + goto end; + } + + rc = v4l2_device_register(&(pdev->dev), vse_dev->vd); + if (WARN_ON(rc < 0)) + goto end; + + rc = v4l2_device_register_subdev(vse_dev->vd, &vse_dev->sd); + if (rc) { + pr_err("failed to register subdev %d\n", rc); + goto end; + } + vse_dev->ic_dev.base = ioremap(VSE_REG_BASE, VSE_REG_SIZE); +#ifdef VSE_REG_RESET + vse_dev->ic_dev.reset = ioremap(VSE_REG_RESET, 4); +#endif + pr_info("vse ioremap addr: 0x%08x 0x%08x %p", VSE_REG_BASE, + VSE_REG_SIZE, vse_dev->ic_dev.base); + platform_set_drvdata(pdev, vse_dev); + rc = v4l2_device_register_subdev_nodes(vse_dev->vd); + return rc; +end: + return rc; +} + +int vse_hw_remove(struct platform_device *pdev) +{ + struct vse_device *vse = platform_get_drvdata(pdev); + + pr_info("enter %s\n", __func__); + + if (!vse) + return -1; + + v4l2_device_unregister_subdev(&vse->sd); + v4l2_device_disconnect(vse->vd); + v4l2_device_put(vse->vd); + + iounmap(vse->ic_dev.base); + kzfree(vse); + return 0; +} + +static struct platform_driver viv_vse_driver = { + .probe = vse_hw_probe, + .remove = vse_hw_remove, + .driver = { + .name = DEVICE_NAME, + .owner = THIS_MODULE, + } +}; + +static void vse_pdev_release(struct device *dev) +{ + pr_info("enter %s\n", __func__); +} + +static struct platform_device viv_vse_pdev = { + .name = DEVICE_NAME, + .dev.release = vse_pdev_release, +}; + +static int __init viv_vse_init_module(void) +{ + int ret = 0; + + pr_info("enter %s\n", __func__); + ret = platform_device_register(&viv_vse_pdev); + if (ret) { + pr_err("register platform device failed.\n"); + return ret; + } + + ret = platform_driver_register(&viv_vse_driver); + if (ret) { + pr_err("register platform driver failed.\n"); + platform_device_unregister(&viv_vse_pdev); + return ret; + } + return ret; +} + +static void __exit viv_vse_exit_module(void) +{ + pr_info("enter %s\n", __func__); + platform_driver_unregister(&viv_vse_driver); + platform_device_unregister(&viv_vse_pdev); +} + +module_init(viv_vse_init_module); +module_exit(viv_vse_exit_module); + +MODULE_AUTHOR("zhiye.yin@verisilicon.com"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("VSE"); +MODULE_VERSION("1.0"); diff --git a/vvcam_ry/v4l2/vse_driver.h b/vvcam_ry/v4l2/vse_driver.h new file mode 100755 index 0000000..f2d19ce --- /dev/null +++ b/vvcam_ry/v4l2/vse_driver.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VSE_DRIVER_H_ +#define _VSE_DRIVER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "vse_dev.h" + +struct vse_device { + /* Driver private data */ + struct v4l2_subdev sd; + struct v4l2_device *vd; + struct vse_ic_dev ic_dev; +}; + +#endif /* _VSE_DRIVER_H_ */ diff --git a/vvcam_ry/version/ISP8000L_V2008.mk b/vvcam_ry/version/ISP8000L_V2008.mk new file mode 100755 index 0000000..b57490e --- /dev/null +++ b/vvcam_ry/version/ISP8000L_V2008.mk @@ -0,0 +1,24 @@ +EXTRA_CFLAGS += -DISP_EE +EXTRA_CFLAGS += -DISP_WDR_V4 +EXTRA_CFLAGS += -DISP_WDR_V4_20BIT +EXTRA_CFLAGS += -DISP_DEMOSAIC2 +EXTRA_CFLAGS += -DISP_MIV2 +EXTRA_CFLAGS += -DISP_AEV2 +EXTRA_CFLAGS += -DISP_AEV2_V2 +EXTRA_CFLAGS += -DISP_AE_SHADOW +EXTRA_CFLAGS += -DISP_COMPAND +EXTRA_CFLAGS += -DISPVI_EXPAND_CHAN +EXTRA_CFLAGS += -DISP_RGBIR +EXTRA_CFLAGS += -DISP_RGBGC +EXTRA_CFLAGS += -DISP_CA +EXTRA_CFLAGS += -DISP_HIST256 +EXTRA_CFLAGS += -DISP_HIST64 +EXTRA_CFLAGS += -DISP_3DNR_V3 +EXTRA_CFLAGS += -DISP_2DNR +EXTRA_CFLAGS += -DISP_2DNR_V4 +EXTRA_CFLAGS += -DISP_CPROC_10BIT +EXTRA_CFLAGS += -DISP_CPROC_SHD +EXTRA_CFLAGS += -DISP_LSC_V2 +EXTRA_CFLAGS += -DISP_MI_PP_WRITE +EXTRA_CFLAGS += -DISP_MI_HDR +EXTRA_CFLAGS += -DISP_MI_MCM_WR diff --git a/vvcam_ry/version/ISP8000_V2009.mk b/vvcam_ry/version/ISP8000_V2009.mk new file mode 100755 index 0000000..132653c --- /dev/null +++ b/vvcam_ry/version/ISP8000_V2009.mk @@ -0,0 +1,18 @@ +EXTRA_CFLAGS += -DISP_EE_RY +EXTRA_CFLAGS += -DISP_DEMOSAIC2_RY +EXTRA_CFLAGS += -DISP_MIV2_RY +EXTRA_CFLAGS += -DISP_AEV2_RY +EXTRA_CFLAGS += -DISP_AEV2_V2_RY +EXTRA_CFLAGS += -DISP_AE_SHADOW_RY +EXTRA_CFLAGS += -DISPVI_EXPAND_CHAN_RY +EXTRA_CFLAGS += -DISP_RGBGC_RY +EXTRA_CFLAGS += -DISP_CA_RY +EXTRA_CFLAGS += -DISP_HIST256_RY +EXTRA_CFLAGS += -DISP_HIST64_RY +EXTRA_CFLAGS += -DISP_CPROC_10BIT_RY +EXTRA_CFLAGS += -DISP_CPROC_SHD_RY +EXTRA_CFLAGS += -DISP_MIV2_MI2_RY +EXTRA_CFLAGS += -DISP_MI_HDR_RY +EXTRA_CFLAGS += -DISP_MI_PP_READ_RY +EXTRA_CFLAGS += -DISP_MI_PP_WRITE_RY +EXTRA_CFLAGS += -DISP_MI_MCM_WR_RY diff --git a/vvcam_ry/vse/vse_dev.h b/vvcam_ry/vse/vse_dev.h new file mode 100755 index 0000000..b6b94b1 --- /dev/null +++ b/vvcam_ry/vse/vse_dev.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VSE_DEV_H_ +#define _VSE_DEV_H_ + +#define VSE_OUTPUT_CHANNEL_NUMBER 3 +#define VSE_INPUT_CHANNEL_NUMBER 6 +/* + * NOTICE NOTICE NOTICE: + * First scale output max resolution is 4096*2160 (max size 4096*2160*3 ) + * Second scale output max resolution is 1920*1080 + * Third scale output max resolution is 1280*720 + */ + +#ifndef __KERNEL__ +#define copy_from_user(a, b, c) vse_copy_data(a, b, c) +#define copy_to_user(a, b, c) vse_copy_data(a, b, c) + +typedef bool(*pVseReadBar) (uint32_t bar, uint32_t *data); +typedef bool(*pVseWriteBar) (uint32_t bar, uint32_t data); + +extern void vse_set_func(pVseReadBar read_func, pVseWriteBar write_func); +extern long vse_copy_data(void *dst, void *src, int size); + +#endif + +#include "vvdefs.h" + +struct vse_crop_size { + u32 left; + u32 right; + u32 top; + u32 bottom; +}; + +struct vse_size { + u32 width; + u32 height; +}; + +struct vse_format_conv_settings { + u32 in_format; + u32 out_format; +}; + +struct vse_mi_settings { + bool enable; + u32 out_format; + u32 width; + u32 height; +}; + +struct vse_params { + u32 src_w; + u32 src_h; + u32 in_format; + u32 input_select; + struct vse_crop_size crop_size[3]; + struct vse_size out_size[3]; + struct vse_format_conv_settings format_conv[3]; + bool resize_enable[3]; + struct vse_mi_settings mi_settings[3]; +}; + +struct vse_ic_dev { + struct vse_params params; + void __iomem *base; + void __iomem *reset; +}; + +#endif /* _VSE_DEV_H_ */ diff --git a/vvcam_ry/vse/vse_ioctl.c b/vvcam_ry/vse/vse_ioctl.c new file mode 100755 index 0000000..6f176aa --- /dev/null +++ b/vvcam_ry/vse/vse_ioctl.c @@ -0,0 +1,699 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifdef __KERNEL__ +#include "vse_driver.h" +#else +#include +#include +#include +#endif +#include "vse_ioctl.h" +#include "vse_regs.h" + +#ifndef __KERNEL__ +#ifdef HAL_CMODEL +#define VSE_REGISTER_OFFSET 0 +#else +#define VSE_REGISTER_OFFSET 0x500000 +#endif + +#define VSE_REGISTER_CTL 0x308254 + +pVseReadBar g_read_func; +pVseWriteBar g_write_func; + +void vse_set_func(pVseReadBar read_func, pVseWriteBar write_func) +{ + g_read_func = read_func; + g_write_func = write_func; +} + +void vse_write_reg(struct vse_ic_dev *dev, u32 offset, u32 val) +{ + g_write_func(VSE_REGISTER_OFFSET + offset, val); +} + +u32 vse_read_reg(struct vse_ic_dev *dev, u32 offset) +{ + u32 data; + + g_read_func(VSE_REGISTER_OFFSET + offset, &data); + return data; +} + +long vse_copy_data(void *dst, void *src, int size) +{ + if (dst != src) + memcpy(dst, src, size); + return 0; +} +#else + +void vse_write_reg(struct vse_ic_dev *dev, u32 offset, u32 val) +{ + __raw_writel(val, dev->base + offset); +} + +u32 vse_read_reg(struct vse_ic_dev *dev, u32 offset) +{ + return __raw_readl(dev->base + offset); +} + +#endif + +int vse_reset(struct vse_ic_dev *dev) +{ + pr_info("enter %s\n", __func__); + +#ifdef VSE_REG_RESET + __raw_writel(0, dev->reset); + __raw_writel(1, dev->reset); +#endif + vse_write_reg(dev, VSE_REG_CTRL, 0x100); + return 0; +} + +void vse_triger_dma_read(struct vse_ic_dev *dev) +{ + u32 reg = vse_read_reg(dev, VSE_REG_CTRL); + + REG_SET_BIT(reg, VSE_CONTROL_DMA_FRAME_START_BIT, 1); + vse_write_reg(dev, VSE_REG_CTRL, reg); + vse_write_reg(dev, VSE_REG_DMA_CTRL, 5); +} + +void setMIBaseAddress(struct vse_ic_dev *dev, u32 width, u32 height, u32 format, + u64 addr, int channel) +{ + u32 stride = ALIGN_UP(width, 16); + u32 crSize = 0; + u32 yBaseAddr = addr; + u32 regAddress = VSE_MI_BASE(channel); + u32 crBaseAddr = 0; + u32 ysize = stride * height; + u32 cbSize = ysize; + u32 cbBaseAddr = yBaseAddr + ysize; + + if (ysize == 0) + return; + + switch (format) { + case MEDIA_PIX_FMT_YUV420SP: + cbSize /= 2; + crSize = 0; + break; + case MEDIA_PIX_FMT_YUV422SP: + break; + case MEDIA_PIX_FMT_YUV444: + case MEDIA_PIX_FMT_RGB888P: + crSize = ysize; + crBaseAddr = cbBaseAddr + cbSize; + break; + case MEDIA_PIX_FMT_RGB888: /* only supoort RGB interleave format. RGB RGB RGB .. */ + ysize *= 3; + cbSize = 0; + cbBaseAddr = 0; + break; + } + + vse_write_reg(dev, regAddress + VSE_REG_MI_Y_BASE_ADDR_INIT, yBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_Y_SIZE_INIT, ysize); + vse_write_reg(dev, regAddress + VSE_REG_MI_CB_BASE_ADDR_INIT, + cbBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_CB_SIZE_INIT, cbSize); + vse_write_reg(dev, regAddress + VSE_REG_MI_CR_BASE_ADDR_INIT, + crBaseAddr); + vse_write_reg(dev, regAddress + VSE_REG_MI_CR_SIZE_INIT, crSize); +} + +int vse_start_dma_read(struct vse_ic_dev *dev, u64 addr) +{ + u32 writeFormat = 0; + u32 writeString = 0; + u32 reg = 0; + u32 address = VSE_REG_DMA_FORMAT; + u32 width = dev->params.src_w; + u32 height = dev->params.src_h; + u32 format = dev->params.in_format; + u32 ysize, cbSize; + u32 yBaseAddr, cbBaseAddr, crBaseAddr; + u32 stride; + + switch (format) { + case MEDIA_PIX_FMT_YUV422SP: + writeFormat = 1; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV422I: + writeFormat = 1; + writeString = 1; + break; + case MEDIA_PIX_FMT_YUV420SP: + writeFormat = 0; + writeString = 0; + break; + } + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_FMT_ALIGNED, 0); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_STR, writeString); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_FMT, writeFormat); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_10BIT, 0); + vse_write_reg(dev, address, reg); + stride = ALIGN_UP(width, 16); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_WIDTH, width); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_HEIGHT, height); + vse_write_reg(dev, VSE_REG_DMA_Y_PIC_STRIDE, stride); + ysize = stride * height; + cbSize = ysize; + yBaseAddr = addr; + cbBaseAddr = yBaseAddr + ysize; + crBaseAddr = 0; + + if (format == MEDIA_PIX_FMT_YUV420SP) { + cbSize /= 2; + } else if (format == MEDIA_PIX_FMT_YUV422I) { + cbSize /= 2; + crBaseAddr = cbBaseAddr + cbSize; + } + vse_write_reg(dev, VSE_REG_Y_PIC_START_ADDR, yBaseAddr); + vse_write_reg(dev, VSE_REG_CB_PIC_START_ADDR, cbBaseAddr); + vse_write_reg(dev, VSE_REG_CR_PIC_START_ADDR, crBaseAddr); + vse_triger_dma_read(dev); + return 0; +} + +void setFormatConvPack(struct vse_ic_dev *dev, u32 enable, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_ENABLE_PACK, enable); + vse_write_reg(dev, address, reg); +} + +void setFormatConvFull(struct vse_ic_dev *dev, u32 y_full, u32 cbcr_full, + u32 noco422, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_Y_FULL, y_full); + REG_SET_MASK(reg, VSE_FORMAT_CONV_CBCR_FULL, cbcr_full); + REG_SET_MASK(reg, VSE_FORMAT_CONV_CONFIG_422NOCO, 0); + vse_write_reg(dev, address, reg); +} + +static u32 format_conv_map[] = { 2, 2, 1, 3, 6, 6 }; + +void setFormatConvFormat(struct vse_ic_dev *dev, u32 inputFormat, + u32 outputFormat, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel) + VSE_REG_FORMAT_CONV_CTRL; + + if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + } else if (inputFormat == MEDIA_PIX_FMT_YUV422SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + inputFormat = MEDIA_PIX_FMT_YUV420SP; + } else if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat != MEDIA_PIX_FMT_YUV420SP) { + inputFormat = MEDIA_PIX_FMT_YUV422SP; + } + + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_FORMAT_CONV_OUTPUT_FORMAT, + format_conv_map[outputFormat]); + REG_SET_MASK(reg, VSE_FORMAT_CONV_INPUT_FORMAT, + format_conv_map[inputFormat]); + vse_write_reg(dev, address, reg); +} + +void setInputSize(struct vse_ic_dev *dev, u32 width, u32 height) +{ + u32 reg = ((height & 0x1FFF) << 16) | (width & 0x1FFF); + + vse_write_reg(dev, VSE_REG_IN_SIZE, reg); +} + +void setCropSize(struct vse_ic_dev *dev, u32 left, u32 right, u32 top, + u32 bottom, int channel) +{ + u32 hreg = ((right & 0x1FFF) << 16) | (left & 0x1FFF); + u32 vreg = ((bottom & 0x1FFF) << 16) | (top & 0x1FFF); + + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_CROP_XDIR, hreg); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_CROP_YDIR, vreg); +} + +void updateResizeControl(struct vse_ic_dev *dev, u32 reg, int channel) +{ + u32 address = VSE_RSZBASE(channel); + + vse_write_reg(dev, address, reg); +} + +void resizeControlAutoUpdate(struct vse_ic_dev *dev, u32 autoUpdate, + int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_AUTO_UPDATE_BIT, autoUpdate); + vse_write_reg(dev, address, reg); +} + +void resizeControlConfigUpdate(struct vse_ic_dev *dev, u32 configUpdate, + int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT, configUpdate); + vse_write_reg(dev, address, reg); +} + +void resizeControlEnableCrop(struct vse_ic_dev *dev, u32 enable, int channel) +{ + u32 reg; + u32 address = VSE_RSZBASE(channel); + + reg = vse_read_reg(dev, address); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_CROP_ENABLE_BIT, enable); + vse_write_reg(dev, address, reg); +} + +void updateVseControl(struct vse_ic_dev *dev, u32 inputChannel, u32 inputFormat, + u32 enbalePath0, u32 enbalePath1, u32 enbalePath2, + u32 autoUpdate, u32 configUpdate) +{ + u32 reg = 0; + + REG_SET_BIT(reg, VSE_CONTROL_AUTO_UPDATE_BIT, autoUpdate); + REG_SET_BIT(reg, VSE_CONTROL_CONFIG_UPDATE_BIT, configUpdate); + REG_SET_BIT(reg, VSE_CONTROL_PATH0_ENABLE_BIT, enbalePath0); + REG_SET_BIT(reg, VSE_CONTROL_PATH1_ENABLE_BIT, enbalePath1); + REG_SET_BIT(reg, VSE_CONTROL_PATH2_ENABLE_BIT, enbalePath2); + + REG_SET_MASK(reg, VSE_CONTROL_INPUT_SELECT, inputChannel); + REG_SET_MASK(reg, VSE_CONTROL_INPUT_FORMAT, inputFormat); + vse_write_reg(dev, VSE_REG_CTRL, reg); + + /* BUS ID and BUS CONFIG, hardcode here, user need adjust it on their hardware. */ + vse_write_reg(dev, VSE_REG_MI0_BUS_ID, 0x01000108); + vse_write_reg(dev, 0x000003e0, 0x001000fa); + vse_write_reg(dev, 0x000003e8, 0x924c5214); + vse_write_reg(dev, 0x000003f0, 0x100000fa); + vse_write_reg(dev, 0x000003f4, 0x01000108); + vse_write_reg(dev, 0x000003f8, 0x924c5214); +} + +void enableMIControl(struct vse_ic_dev *dev, u32 enable, int channel) +{ + u32 reg = vse_read_reg(dev, VSE_REG_MI_CTRL); + + REG_SET_BIT(reg, channel, enable); + REG_SET_BIT(reg, VSE_MI_CONTROL_RDMA_ENABLE_BIT, 1); + vse_write_reg(dev, VSE_REG_MI_CTRL, reg); +} + +void setMIBufferInfo(struct vse_ic_dev *dev, u32 width, u32 height, u32 format, + u32 is10Bit, u32 aligned, int channel) +{ + u32 writeFormat = 0; + u32 writeString = 0; + u32 reg = 0; + u32 address; + + u32 stride = ALIGN_UP(width, 16); + u32 size = stride * height; + + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_LENGTH, stride); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_WIDTH, + width); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_HEIGHT, + height); + vse_write_reg(dev, VSE_MI_BASE(channel) + VSE_REG_MI_Y_PIC_SIZE, size); + + switch (format) { + case MEDIA_PIX_FMT_YUV422SP: + writeFormat = 1; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV422I: + writeFormat = 1; + writeString = 1; + break; + case MEDIA_PIX_FMT_YUV420SP: + writeFormat = 0; + writeString = 0; + break; + case MEDIA_PIX_FMT_YUV444: + writeFormat = 2; + writeString = 2; + break; + case MEDIA_PIX_FMT_RGB888: + writeFormat = 2; + writeString = 1; + break; + case MEDIA_PIX_FMT_RGB888P: + writeFormat = 2; + writeString = 2; + break; + } + + address = VSE_MI_BASE(channel) + VSE_REG_MI_FMT; + reg = vse_read_reg(dev, address); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_FMT_ALIGNED, aligned); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_STR, writeString); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_FMT, writeFormat); + REG_SET_MASK(reg, VSE_MI_FORMAT_WR_YUV_10BIT, is10Bit); + vse_write_reg(dev, address, reg); +} + +void setMIControlConfig(struct vse_ic_dev *dev, u32 enableOffset, + u32 enableUpdateBaseAddress, u32 configUpdate, u32 skip, + u32 autoUpdate, u32 enablePingpong, int channel) +{ + u32 reg = 0; + + REG_SET_BIT(reg, VSE_MI_PATH_INIT_OFFSET_EN_BIT, enableOffset); + REG_SET_BIT(reg, VSE_MI_PATH_INIT_BASE_EN_BIT, enableUpdateBaseAddress); + REG_SET_BIT(reg, VSE_MI_PATH_CONFIG_UPDATE_BIT, configUpdate); + REG_SET_BIT(reg, VSE_MI_PATH_ENABLE_SKIP_BIT, skip); + REG_SET_BIT(reg, VSE_MI_PATH_AUTO_UPDATE_BIT, autoUpdate); + REG_SET_BIT(reg, VSE_MI_PATH_ENABLE_PINGPONG_BIT, enablePingpong); + vse_write_reg(dev, VSE_MI_BASE(channel), reg); +} + +u32 vse_get_scale_factor(int src, int dst) +{ + if (dst >= src) { + return ((65536 * (src - 1)) / (dst - 1)); + } else if (dst < src) { + return ((65536 * (dst - 1)) / (src - 1)) + 1; + } + return 0; +} + +void setScaleFactor(struct vse_ic_dev *dev, u32 src_w, u32 src_h, u32 dst_w, + u32 dst_h, u32 inputFormat, u32 outputFormat, int channel) +{ + bool hyup, vyup, hcup, vcup; + u32 scale_factor = vse_get_scale_factor(src_w, dst_w); + u32 address = VSE_RSZBASE(channel); + u32 reg = vse_read_reg(dev, address); + + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HY, + scale_factor); + scale_factor = vse_get_scale_factor(src_h, dst_h); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_VY, + scale_factor); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VY_ENABLE_BIT, + ((src_h != dst_h) & 0x01)); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HY_ENABLE_BIT, + ((src_w != dst_w) & 0x01)); + hyup = src_w < dst_w; + vyup = src_h < dst_h; + + /* Format conv module doesn't support convert other formats to YUV420SP. + doesn't support convert 420SP to other formats too. + so scale down/up cbcr here. + */ + src_w /= 2; + dst_w /= 2; + if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + src_h /= 2; + dst_h /= 2; + } else if (inputFormat == MEDIA_PIX_FMT_YUV422SP + && outputFormat == MEDIA_PIX_FMT_YUV420SP) { + /* scale 422 to 420 */ + dst_h /= 2; + } else if (inputFormat == MEDIA_PIX_FMT_YUV420SP + && outputFormat != MEDIA_PIX_FMT_YUV420SP) { + /* scale 420 to 422 + cbcr width*2, use input buffer as 422SP */ + src_h /= 2; + } + + hcup = src_w < dst_w; + vcup = src_h < dst_h; + scale_factor = vse_get_scale_factor(src_w, dst_w); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HCB, + scale_factor); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_HCR, + scale_factor); + scale_factor = vse_get_scale_factor(src_h, dst_h); + vse_write_reg(dev, VSE_RSZBASE(channel) + VSE_RSZ_SCALE_VC, + scale_factor); + + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VCUP_BIT, vcup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VYUP_BIT, vyup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HCUP_BIT, hcup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HYUP_BIT, hyup); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_VC_ENABLE_BIT, + (src_h != dst_h)); + REG_SET_BIT(reg, VSE_RESIZE_CONTROL_SCALE_HC_ENABLE_BIT, + (src_w != dst_w)); + vse_write_reg(dev, address, reg); +} + +int vse_read_irq(struct vse_ic_dev *dev, u32 *ret) +{ + pr_info("enter %s\n", __func__); + *ret = vse_read_reg(dev, VSE_REG_MI_MSI); + return 0; +} + +int vse_clear_irq(struct vse_ic_dev *dev) +{ + pr_info("enter %s\n", __func__); + vse_write_reg(dev, VSE_REG_MI_MSI, 0); + return 0; +} + +int vse_mask_irq(struct vse_ic_dev *dev, u32 mask) +{ + pr_info("enter %s 0x%08x\n", __func__, mask); + vse_write_reg(dev, VSE_REG_MI_IMSC, mask); + return 0; +} + +int vse_ioc_qcap(struct vse_ic_dev *dev, void *args) +{ + struct v4l2_capability *cap = (struct v4l2_capability *)args; + + strcpy((char *)cap->driver, "viv_vse"); + return 0; +} + +int vse_update_buffers(struct vse_ic_dev *dev, u64 *addr) +{ + struct vse_params *param = &dev->params; + struct vse_mi_settings *mi = param->mi_settings; + int i = 0; + + pr_info("enter %s\n", __func__); + for (; i < 3; i++) { + if (addr[i] != 0) { + setMIBaseAddress(dev, mi[i].width, mi[i].height, + mi[i].out_format, addr[i], i); + } + } + return 0; +} + +int vse_update_mi_info(struct vse_ic_dev *dev) +{ + struct vse_params *param = &dev->params; + struct vse_mi_settings *mi = param->mi_settings; + int i = 0; + + pr_info("enter %s\n", __func__); + + for (; i < 3; i++) { + if (!mi[i].enable) + continue; + setMIBufferInfo(dev, mi[i].width, mi[i].height, + mi[i].out_format, false, false, i); + enableMIControl(dev, mi[i].enable, i); + setMIControlConfig(dev, true, true, true, false, true, false, + i); + } + return 0; +} + +int vse_s_params(struct vse_ic_dev *dev) +{ + struct vse_params *param = &dev->params; + int i = 0; + int input_select = 0; + int crop_w, crop_h, scale_w, scale_h; + struct vse_crop_size *cropSize; + struct vse_size *outputSize; + + pr_info("enter %s\n", __func__); + setInputSize(dev, param->src_w, param->src_h); + + for (; i < 3; i++) { + if (!param->resize_enable[i]) + continue; + cropSize = ¶m->crop_size[i]; + outputSize = ¶m->out_size[i]; + crop_w = cropSize->right - cropSize->left + 1; + crop_h = cropSize->bottom - cropSize->top + 1; + scale_w = param->src_w; + scale_h = param->src_h; + if (crop_w > 1 && crop_h > 1) { + resizeControlEnableCrop(dev, 1, i); + setCropSize(dev, cropSize->left, cropSize->right, + cropSize->top, cropSize->bottom, i); + scale_w = crop_w; + scale_h = crop_h; + } else { + resizeControlEnableCrop(dev, 0, i); + } + + /* ONLY SUPPORT Semiplanar NOW, all enable pack */ + setFormatConvPack(dev, true, i); + setFormatConvFull(dev, true, true, false, i); + setFormatConvFormat(dev, param->in_format, + param->format_conv[i].out_format, i); + setScaleFactor(dev, scale_w, scale_h, outputSize->width, + outputSize->height, param->in_format, + param->format_conv[i].out_format, i); + resizeControlAutoUpdate(dev, 1, i); + resizeControlConfigUpdate(dev, 1, i); + } + +#ifndef HAL_CMODEL + input_select = param->input_select; +#endif + updateVseControl(dev, input_select, param->in_format, + param->resize_enable[0], + param->resize_enable[1], + param->resize_enable[2], true, true); + return 0; +} + +long vse_priv_ioctl(struct vse_ic_dev *dev, unsigned int cmd, void *args) +{ + int ret = -1; + + switch (cmd) { + case VSEIOC_RESET: + ret = vse_reset(dev); + break; + case VSEIOC_S_PARAMS: + viv_check_retval(copy_from_user + (&dev->params, args, sizeof(dev->params))); + ret = vse_s_params(dev); + break; + case VSEIOC_CLEAR_IRQ: + ret = vse_clear_irq(dev); + break; + case VSEIOC_READ_IRQ:{ + u32 irq = 0; + ret = vse_read_irq(dev, &irq); + viv_check_retval(copy_to_user(args, &irq, sizeof(irq))); + break; + } + case VSEIOC_START_DMA_READ:{ + u64 addr; + viv_check_retval(copy_from_user + (&addr, args, sizeof(addr))); + ret = vse_start_dma_read(dev, addr); + break; + } + case VSEIOC_U_MI_INFO: + ret = vse_update_mi_info(dev); + break; + case VSEIOC_U_BUFFER:{ + u64 addrs[3]; + viv_check_retval(copy_from_user + (addrs, args, sizeof(addrs))); + vse_update_buffers(dev, addrs); + break; + } + case VSEIOC_MASK_IRQ:{ + u32 mask; + viv_check_retval(copy_from_user + (&mask, args, sizeof(mask))); + vse_mask_irq(dev, mask); + break; + } + case VIDIOC_QUERYCAP: + ret = vse_ioc_qcap(dev, args); + break; + default: + pr_err("unsupported vse command %d", cmd); + break; + } + return ret; +} + +int vvnative_vse_init(struct vse_ic_dev *dev) +{ + return 0; +} + +int vvnative_vse_deinit(struct vse_ic_dev *dev) +{ + return 0; +} diff --git a/vvcam_ry/vse/vse_ioctl.h b/vvcam_ry/vse/vse_ioctl.h new file mode 100755 index 0000000..609ee41 --- /dev/null +++ b/vvcam_ry/vse/vse_ioctl.h @@ -0,0 +1,90 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VSE_IOC_H_ +#define _VSE_IOC_H_ +#include "vse_dev.h" + +enum { + VSEIOC_RESET = 0x100, + VSEIOC_S_PARAMS, + VSEIOC_U_BUFFER, + VSEIOC_U_MI_INFO, + VSEIOC_MASK_IRQ, + VSEIOC_READ_IRQ, + VSEIOC_CLEAR_IRQ, + VSEIOC_START_DMA_READ, +}; + +#ifdef __KERNEL__ + +long vse_priv_ioctl(struct vse_ic_dev *dev, unsigned int cmd, void *args); +int vvnative_vse_init(struct vse_ic_dev *dev); +int vvnative_vse_deinit(struct vse_ic_dev *dev); + + + +int vse_reset(struct vse_ic_dev *dev); +int vse_s_params(struct vse_ic_dev *dev); +int vse_update_mi_info(struct vse_ic_dev *dev); +int vse_mask_irq(struct vse_ic_dev *dev, u32 mask); +int vse_clear_irq(struct vse_ic_dev *dev); +int vse_read_irq(struct vse_ic_dev *dev, u32 * ret); + +/* dma input pa */ +int vse_start_dma_read(struct vse_ic_dev *dev, u64 addr); +/* mi output pa */ +int vse_update_buffers(struct vse_ic_dev *dev, u64 * addr); + +#endif + +#endif /* _VSE_IOC_H_ */ diff --git a/vvcam_ry/vse/vse_regs.h b/vvcam_ry/vse/vse_regs.h new file mode 100755 index 0000000..456a547 --- /dev/null +++ b/vvcam_ry/vse/vse_regs.h @@ -0,0 +1,481 @@ +/**************************************************************************** + * + * The MIT License (MIT) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + ***************************************************************************** + * + * The GPL License (GPL) + * + * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; + * + ***************************************************************************** + * + * Note: This software is released under dual MIT and GPL licenses. A + * recipient may use this file under the terms of either the MIT license or + * GPL License. If you wish to use only one license not the other, you can + * indicate your decision by deleting one of the above license notices in your + * version of this file. + * + *****************************************************************************/ +#ifndef _VSE_REGS_H_ +#define _VSE_REGS_H_ + +/* product identification */ +#define VSE_REG_ID 0x00000000 + +/* VSE CTL + 17 regs_enable_ram_clk "clk domain ram clock 1: enable 0: disable" + 16 auto_upd + 15 cfg_upd + 14 dma_frame_start_clk + 13:11 input select + 000 isp0 mp + 001 isp0 sp + 010 isp1 mp + 011 isp1 sp + 100 dewarp + 101 dma + 10:9 input format + 00 YUV422SP + 01 YUV422I + 10 YUV420SP + 8 soft reset + 7:0 path enable + bit:0 path 0 + bit:1 path 1 + bit:2 path 2 + */ +#define VSE_REG_CTRL 0x00000004 + +#define VSE_CONTROL_ENABLE_RAM_CLK 17 +#define VSE_CONTROL_AUTO_UPDATE_BIT 16 +#define VSE_CONTROL_CONFIG_UPDATE_BIT 15 +#define VSE_CONTROL_DMA_FRAME_START_BIT 14 +#define VSE_CONTROL_INPUT_SELECT_SHIFT 11 +#define VSE_CONTROL_INPUT_SELECT (7 << 11) +#define VSE_CONTROL_INPUT_FORMAT_SHIFT 9 +#define VSE_CONTROL_INPUT_FORMAT (3 << 9) +#define VSE_CONTROL_SOFT_RESET_BIT 8 +#define VSE_CONTROL_PATH2_ENABLE_BIT 2 +#define VSE_CONTROL_PATH1_ENABLE_BIT 1 +#define VSE_CONTROL_PATH0_ENABLE_BIT 0 + +/* input size 28:16 height, 12:0 width */ +#define VSE_REG_IN_SIZE 0x00000008 +#define VSE_REG_CTRL_SHD 0x0000000C + +/* RSZ CTL + 10 auto update + 9 config update + 8 crop enable + 7 scale vc up + 6 scale vy up + 5 scale hc up + 4 scale hy up + 3 scale vc enable + 2 scale vy enable + 1 scale hc enable + 0 scale hy enable + */ +#define VSE_REG_RSZ0_CTL 0x00000010 +#define VSE_REG_RSZ1_CTL 0x000000A0 /* repeat */ +#define VSE_REG_RSZ2_CTL 0x00000130 /* repeat */ +#define VSE_RSZBASE(c) ((c) == 0 ? VSE_REG_RSZ0_CTL : ((c) == 1 ? VSE_REG_RSZ1_CTL : VSE_REG_RSZ2_CTL)) + +/* NOTICE: repeat 3 times, using as VSE_REG_RSZX_CTL + VSE_RSZ_SCALE_HY */ + +#define VSE_RSZ_SCALE_HY 0x00000004 +#define VSE_RSZ_SCALE_HCB 0x00000008 +#define VSE_RSZ_SCALE_HCR 0x0000000C +#define VSE_RSZ_SCALE_VY 0x00000010 +#define VSE_RSZ_SCALE_VC 0x00000014 +#define VSE_RSZ_PHASE_HY 0x00000018 +#define VSE_RSZ_PHASE_HC 0x0000001C +#define VSE_RSZ_PHASE_VY 0x00000020 +#define VSE_RSZ_PHASE_VC 0x00000024 +#define VSE_RSZ_SCALE_LUT_ADDR 0x00000028 +#define VSE_RSZ_SCALE_LUT 0x0000002C + +/* RSZ0 CTRL SHD + 8 crop enable + 7 scale vc up + 6 scale vy up + 5 scale hc up + 4 scale hy up + 3 scale vc enable + 2 scale vy enable + 1 scale hc enable + 0 scale hy enable + */ +#define VSE_RSZ_CTRL_SHD 0x00000030 +#define VSE_RSZ_SCALE_HY_SHD 0x00000034 +#define VSE_RSZ_SCALE_HCB_SHD 0x00000038 +#define VSE_RSZ_SCALE_HCR_SHD 0x0000003C +#define VSE_RSZ_SCALE_VY_SHD 0x00000040 +#define VSE_RSZ_SCALE_VC_SHD 0x00000044 +#define VSE_RSZ_PHASE_HY_SHD 0x00000048 +#define VSE_RSZ_PHASE_HC_SHD 0x0000004C +#define VSE_RSZ_PHASE_VY_SHD 0x00000050 +#define VSE_RSZ_PHASE_VC_SHD 0x00000054 + +/* 28:16 h end, 12:0 h start */ +#define VSE_RSZ_CROP_XDIR 0x00000058 + +/* 28:16 v end, 12:0 v start */ +#define VSE_RSZ_CROP_YDIR 0x0000005C +#define VSE_RSZ_CROP_XDIR_SHD 0x00000060 +#define VSE_RSZ_CROP_YDIR_SHD 0x00000064 + +/* 2:0 frame scale */ +#define VSE_RSZ_FRAME_RATE 0x00000068 + +/* frame conv ctrl + 10 rsz_pack_format + 9 expand_8to10_method + 8 expand_8to10_enable + 7 cfg_422nocosited + 6 cfg_cbcr_full + 5 cfg_y_full + 4:2 rsz_output_format + 1:0 rsz_input_format + */ +#define VSE_REG_FORMAT_CONV_CTRL 0x0000006C +/********************************************************/ +/* END OF RSZ REGS */ + +#define VSE_REG_HBLANK_VALUE 0x000001A0 + +#define VSE_REG_VBLANK_VALUE 0x000001A4 + +#define VSE_REG_VSYNC_WIDTH 0x000001A8 + +#define VSE_REG_HSYNC_PREAMBLE 0x000001AC + +/* mi ctrl + 4 mi3_ycbcr_rdma_start + 3 mi3_ycbcr_rdma_path_enable + 2 mi2_ycbcr_path_enable + 1 mi1_ycbcr_path_enable + 0 mi0_ycbcr_path_enable + */ +#define VSE_REG_MI_CTRL 0x000001B0 +#define VSE_REG_MI_CTRL_SHD 0x000001B4 + +/* mi0 ctrl + 5 mi0_init_offset_en : Enables updating of the offset counters shadow registers for mi0 picture to the programmed register init values. + 4 mi0_init_base_en : Enables updating of the base address and buffer size shadow registers for mi0 picture to the programmed register init values + 3 mi0_cfg_upd : Forced configuration update. Leads to an immediate update of the shadow registers. + 2 mi0_mi_skip : Skip of current or next starting mi0 picture + 1 mi0_auto_update : automatic update of configuration registers for mi0 path at frame end. 1: enabled 0: disabled + 0 mi0_pingpong_enable : pingpong mode of configuration registers for mi0 path at frame end. 1: enabled 0: disabled +*/ +/* REPEAT 3 TIMES */ +#define VSE_REG_MI_PATH_0 0x000001C0 +#define VSE_REG_MI_PATH_1 0x00000260 +#define VSE_REG_MI_PATH_2 0x00000310 +#define VSE_MI_BASE(c) ((c) == 0 ? VSE_REG_MI_PATH_0 : ((c) == 1 ? VSE_REG_MI_PATH_1 : VSE_REG_MI_PATH_2)) + +/* mi0 format + 8:7 mi0_wr_yuv_nvy + 6 mi0_wr_yuv_n21 + 5 mi0_wr_fmt_aligned : 0 unaligned, 1 aligned + 4:3 mi0_wr_yuv_str + 2:1 mi0_wr_yuv_fmt + 0 mi0_wr_yuv_bit : 0 8bit, 1 10 bit. + */ +#define VSE_REG_MI_FMT 0x00000004 + +/* Base address of mi0 picture Y component ring buffer. */ +#define VSE_REG_MI_Y_BASE_ADDR_INIT 0x00000014 +/* Size of mi0 picture Y component ring buffer. */ +#define VSE_REG_MI_Y_SIZE_INIT 0x00000018 +/* Offset counter init value of mi0 picture Y component ring buffer. */ +#define VSE_REG_MI_Y_OFFSET_COUNT_INIT 0x0000001C +/* Line length of mi0 picture Y component or RGB picture n pixel, also known as line stride. */ +#define VSE_REG_MI_Y_LENGTH 0x00000020 +/* Image width of the mi0 picture Y component or RGB picture in pixel */ +#define VSE_REG_MI_Y_PIC_WIDTH 0x00000024 +/* Image height of the y component or RGB picture in pixel. */ +#define VSE_REG_MI_Y_PIC_HEIGHT 0x00000028 +/* Image size of the Y component or RGB picture in pixel which has to be the Y line length multiplied by the Y image height */ +#define VSE_REG_MI_Y_PIC_SIZE 0x0000002C + +/* CBCR */ +#define VSE_REG_MI_CB_BASE_ADDR_INIT 0x00000030 +#define VSE_REG_MI_CB_SIZE_INIT 0x00000034 +#define VSE_REG_MI_CB_OFFSET_COUNT_INIT 0x00000038 +#define VSE_REG_MI_CR_BASE_ADDR_INIT 0x0000003C +#define VSE_REG_MI_CR_SIZE_INIT 0x00000040 +#define VSE_REG_MI_CR_OFFSET_COUNT_INIT 0x00000044 + +/* 2nd ping pong base address of main picture Y component buffer. */ +#define VSE_REG_MI_Y_BASE_ADDR_INIT2 0x00000048 +#define VSE_REG_MI_CB_BASE_ADDR_INIT2 0x0000004C +#define VSE_REG_MI_CR_BASE_ADDR_INIT2 0x00000050 + +/* Offset counter value which points to the start address of the previously processed picture. Updated at frame end. */ +#define VSE_REG_MI_Y_OFFS_CNT_START 0x00000054 +#define VSE_REG_MI_CB_OFFS_CNT_START 0x00000058 +#define VSE_REG_MI_CR_OFFS_CNT_START 0x0000005C + +/* MI SHD */ +#define VSE_REG_MI_Y_BASE_ADDR_SHD 0x00000060 +#define VSE_REG_MI_Y_SIZE_SHD 0x00000064 +#define VSE_REG_MI_Y_OFFS_COUNT_SHD 0x00000068 +#define VSE_REG_MI_CB_BASE_ADDR_SHD 0x0000006C +#define VSE_REG_MI_CB_SIZE_SHD 0x00000070 +#define VSE_REG_MI_CB_OFFS_COUNT_SHD 0x00000074 +#define VSE_REG_MI_CR_BASE_ADDR_SHD 0x00000078 +#define VSE_REG_MI_CR_SIZE_SHD 0x0000007C +#define VSE_REG_MI_CR_OFFS_COUNT_SHD 0x00000080 +#define VSE_REG_MI_STATUS_CLR 0x00000084 +#define VSE_REG_MI_CTRL_STATUS 0x00000088 +#define VSE_REG_MI_Y_IRQ_OFFS_INIT 0x0000008C +#define VSE_REG_MI_Y_IRQ_OFFS_SHD 0x00000090 +/********************************************************/ +/* END OF MI0 MI1 MI2 */ + +/* MI3 DMA CTL + 7 regs_enable_ram_clk "clk domain ram clock 1: enable 0: disable" + 6:5 burst_len_chrom + 4:3 burst_len_lum + 2 frame start + 1 soft reset + 0 soft_upd + */ +#define VSE_REG_DMA_CTRL 0x000003A8 + +/* MI3 DMA FORMAT + 8:7 mi3_rd_yuv_nvy + 6 mi3_rd_yuv_n21 + 5 mi3_rd_fmt_aligned + 4:3 mi3_rd_yuv_str + 2:1 mi3_rd_yuv_fmt + 0 mi3_rd_yuv_bit +*/ +#define VSE_REG_DMA_FORMAT 0x000003AC + +#define VSE_REG_DMA_Y_PIC_WIDTH 0x000003B0 +#define VSE_REG_DMA_Y_PIC_HEIGHT 0x000003B4 +#define VSE_REG_DMA_Y_PIC_STRIDE 0x000003B8 +#define VSE_REG_Y_PIC_START_ADDR 0x000003BC +#define VSE_REG_CB_PIC_START_ADDR 0x000003C0 +#define VSE_REG_CR_PIC_START_ADDR 0x000003C4 +#define VSE_REG_Y_START_ADDR_SHD 0x000003C8 +#define VSE_REG_CB_START_ADDR_SHD 0x000003CC +#define VSE_REG_CR_START_ADDR_SHD 0x000003D0 +/* #define VSE_REG_DMA_STATUS 0x000003D4 */ +/********************************************************/ +/* END OF MI3 */ + +/* MI0 bus config + 19:16 mi_m0_wr_swap_v + 15:12 mi_m0_wr_swap_u + 11:8 mi_m0_wr_swap_y + 7:6 mi_m0_rd_issue_cap + 5:4 mi_m0_wr_issue_cap + 3:2 mi_m0_rd_burst_len + 1:0 mi_m0_wr_burst_len + */ +#define VSE_REG_MI0_BUS_CONFIG 0x000003E0 + +/* MI0 bus id + 24 mi_m0_rd_id_en + 23:16 mi_m0_rd_id_cfg + 8 mi_m0_wr_id_en + 7:0 mi_m0_wr_id_cfg + */ +#define VSE_REG_MI0_BUS_ID 0x000003E4 +#define VSE_REG_MI0_BUS_TIME_OUT 0x000003E8 +#define VSE_REG_MI0_AXI_STATUS 0x000003EC + +#define VSE_REG_MI1_BUS_CONFIG 0x000003F0 +#define VSE_REG_MI1_BUS_ID 0x000003F4 +#define VSE_REG_MI1_BUS_TIME_OUT 0x000003F8 +#define VSE_REG_MI1_AXI_STATUS 0x000003FC +/********************************************************/ +/* END OF BUS CONFIG */ + +/* MI IMSC STATUS + 12 mi_dma_ycbcr_ready + 11 wrap_mi2_cr + 10 wrap_mi2_cb + 9 wrap_mi2_y + 8 wrap_mi1_cr + 7 wrap_mi1_cb + 6 wrap_mi1_y + 5 wrap_mi0_cr + 4 wrap_mi0_cb + 3 wrap_mi0_y + 2 mi2_ycbcr_frame_end + 1 mi1_ycbcr_frame_end + 0 mi0_ycbcr_frame_end + */ +#define VSE_REG_MI_IMSC 0x00000400 + +/* MI IMSC ERROR + 5 mi2_bus_buserr + 4 mi2_bus_timeo + 3 mi1_bus_buserr + 2 mi1_bus_timeo + 1 mi0_bus_buserr + 0 mi0_bus_timeo + */ +#define VSE_REG_MI_IMSC1 0x00000404 +#define VSE_REG_MI_ISR 0x00000408 /* same as imsc */ +#define VSE_REG_MI_ISR1 0x0000040C /* same as imsc1 */ +#define VSE_REG_MI_MSI 0x00000410 +#define VSE_REG_MI_MSI1 0x00000414 +#define VSE_REG_MI_ICR 0x00000418 +#define VSE_REG_MI_ICR1 0x0000041C +#define VSE_REG_MI_RIS 0x00000420 +#define VSE_REG_MI_RIS1 0x00000424 + +/* slice of VSE_REG_FORMAT_CONV_CTRL */ +#define VSE_FORMAT_CONV_ENABLE_PACK_SHIFT 10 +#define VSE_FORMAT_CONV_ENABLE_PACK (1 << 10) +#define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD_SHIFT 9 +#define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD (1 << 9) +#define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE_SHIFT 8 +#define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE (1 << 8) +#define VSE_FORMAT_CONV_CONFIG_422NOCO_SHIFT 7 +#define VSE_FORMAT_CONV_CONFIG_422NOCO (1 << 7) +#define VSE_FORMAT_CONV_CBCR_FULL_SHIFT 6 +#define VSE_FORMAT_CONV_CBCR_FULL (1 << 6) +#define VSE_FORMAT_CONV_Y_FULL_SHIFT 5 +#define VSE_FORMAT_CONV_Y_FULL (1 << 5) +#define VSE_FORMAT_CONV_OUTPUT_FORMAT_SHIFT 2 +#define VSE_FORMAT_CONV_OUTPUT_FORMAT (7 << 2) +#define VSE_FORMAT_CONV_INPUT_FORMAT_SHIFT 0 +#define VSE_FORMAT_CONV_INPUT_FORMAT (3) + +/* slice of VSE_REG_RSZ0_CTL */ +#define VSE_RESIZE_CONTROL_AUTO_UPDATE_BIT 10 +#define VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT 9 +#define VSE_RESIZE_CONTROL_CROP_ENABLE_BIT 8 +#define VSE_RESIZE_CONTROL_SCALE_VCUP_BIT 7 +#define VSE_RESIZE_CONTROL_SCALE_VYUP_BIT 6 +#define VSE_RESIZE_CONTROL_SCALE_HCUP_BIT 5 +#define VSE_RESIZE_CONTROL_SCALE_HYUP_BIT 4 +#define VSE_RESIZE_CONTROL_SCALE_VC_ENABLE_BIT 3 +#define VSE_RESIZE_CONTROL_SCALE_VY_ENABLE_BIT 2 +#define VSE_RESIZE_CONTROL_SCALE_HC_ENABLE_BIT 1 +#define VSE_RESIZE_CONTROL_SCALE_HY_ENABLE_BIT 0 + +/* slice of VSE_REG_MI_FMT */ +#define VSE_MI_FORMAT_WR_YUV_NVY_SHIFT 7 +#define VSE_MI_FORMAT_WR_YUV_NVY (3 << 7) +#define VSE_MI_FORMAT_WR_YUV_N21_SHIFT 6 +#define VSE_MI_FORMAT_WR_YUV_N21 (1 << 6) +#define VSE_MI_FORMAT_WR_FMT_ALIGNED_SHIFT 5 +#define VSE_MI_FORMAT_WR_FMT_ALIGNED (1 << 5) +#define VSE_MI_FORMAT_WR_YUV_STR_SHIFT 3 +#define VSE_MI_FORMAT_WR_YUV_STR (3 << 3) +#define VSE_MI_FORMAT_WR_YUV_FMT_SHIFT 1 +#define VSE_MI_FORMAT_WR_YUV_FMT (3 << 1) +#define VSE_MI_FORMAT_WR_YUV_10BIT_SHIFT 0 +#define VSE_MI_FORMAT_WR_YUV_10BIT (1) + +/* slice of VSE_REG_MI_CTRL */ +#define VSE_MI_CONTROL_RDMA_START_BIT 4 +#define VSE_MI_CONTROL_RDMA_ENABLE_BIT 3 +#define VSE_MI_CONTROL_MI2_PATH_ENABLE_BIT 2 +#define VSE_MI_CONTROL_MI1_PATH_ENABLE_BIT 1 +#define VSE_MI_CONTROL_MI0_PATH_ENABLE_BIT 0 + +/* slice of VSE_REG_MI_PATH */ +#define VSE_MI_PATH_INIT_OFFSET_EN_BIT 5 +#define VSE_MI_PATH_INIT_BASE_EN_BIT 4 +#define VSE_MI_PATH_CONFIG_UPDATE_BIT 3 +#define VSE_MI_PATH_ENABLE_SKIP_BIT 2 +#define VSE_MI_PATH_AUTO_UPDATE_BIT 1 +#define VSE_MI_PATH_ENABLE_PINGPONG_BIT 0 + +#define VSE_MI_ISR_STATUS_DMA_YCBCR_READY_BIT 12 +#define VSE_MI_ISR_STATUS_WRAP_MI2_CR_BIT 11 +#define VSE_MI_ISR_STATUS_WRAP_MI2_CB_BIT 10 +#define VSE_MI_ISR_STATUS_WRAP_MI2_Y_BIT 9 +#define VSE_MI_ISR_STATUS_WRAP_MI1_CR_BIT 8 +#define VSE_MI_ISR_STATUS_WRAP_MI1_CB_BIT 7 +#define VSE_MI_ISR_STATUS_WRAP_MI1_Y_BIT 6 +#define VSE_MI_ISR_STATUS_WRAP_MI0_CR_BIT 5 +#define VSE_MI_ISR_STATUS_WRAP_MI0_CB_BIT 4 +#define VSE_MI_ISR_STATUS_WRAP_MI0_Y_BIT 3 +#define VSE_MI_ISR_STATUS_MI2_FRAME_END_BIT 2 +#define VSE_MI_ISR_STATUS_MI1_FRAME_END_BIT 1 +#define VSE_MI_ISR_STATUS_MI0_FRAME_END_BIT 0 + +#define VSE_MI_ISR_ERROR_MI2_BUS_ERROR_BIT 5 +#define VSE_MI_ISR_ERROR_MI2_BUS_TIMEOUT_BIT 4 +#define VSE_MI_ISR_ERROR_MI1_BUS_ERROR_BIT 3 +#define VSE_MI_ISR_ERROR_MI1_BUS_TIMEOUT_BIT 2 +#define VSE_MI_ISR_ERROR_MI0_BUS_ERROR_BIT 1 +#define VSE_MI_ISR_ERROR_MI0_BUS_TIMEOUT_BIT 0 + +#define VSE_MI_BUS_CONFIG_WR_SWAP_V_SHIFT 16 +#define VSE_MI_BUS_CONFIG_WR_SWAP_V (0XF << 16) +#define VSE_MI_BUS_CONFIG_WR_SWAP_U_SHIFT 12 +#define VSE_MI_BUS_CONFIG_WR_SWAP_U (0XF << 12) +#define VSE_MI_BUS_CONFIG_WR_SWAP_Y_SHIFT 8 +#define VSE_MI_BUS_CONFIG_WR_SWAP_Y (0XF << 8) +#define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP_SHIFT 6 +#define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP (0X3 << 6) +#define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP_SHIFT 4 +#define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP (0X3 << 4) +#define VSE_MI_BUS_CONFIG_RD_BURST_LEN_SHIFT 2 +#define VSE_MI_BUS_CONFIG_RD_BURST_LEN (0X3 << 2) +#define VSE_MI_BUS_CONFIG_WR_BURST_LEN_SHIFT 0 +#define VSE_MI_BUS_CONFIG_WR_BURST_LEN (0X3 << 0) + +#ifndef REG_GET_MASK +#define REG_GET_MASK(reg, mask)\ + (((reg) & (mask)) >> (mask##_SHIFT)) + +#define REG_SET_MASK(reg, mask, value)\ + {\ + ((reg) = (((reg) & ~(mask)) | (((value) << (mask##_SHIFT)) & (mask))));\ + } + +#define REG_GET_BIT(reg, shift)\ + (((reg) & 1) >> shift) + +#define REG_SET_BIT(reg, shift, value)\ + {\ + ((reg) = (((reg) & ~(1 << (shift))) | (((value) & 1) << (shift))));\ + } +#endif + +#endif /* _VSE_REGS_H_ */ diff --git a/vvcam_ry/vvcam.mk b/vvcam_ry/vvcam.mk new file mode 100755 index 0000000..650e79d --- /dev/null +++ b/vvcam_ry/vvcam.mk @@ -0,0 +1,36 @@ +#the device/fsl/common/build/kernel.mk should be included before this file + +KERNEL_DIR := $(TARGET_OUT_INTERMEDIATES)/KERNEL_OBJ +TARGET_ARCH := $(TARGET_KERNEL_ARCH) +VVCAM_CROSS_COMPILE := aarch64-linux-gnu- + +VVCAM_SRC_PATH := $(VVCAM_PATH)/vvcam/v4l2 +VVCAM_OUT := $(TARGET_OUT_INTERMEDIATES)/VVCAM_OBJ + +KERNEL_CFLAGS ?= KCFLAGS=-mno-android +ARCH_TYPE ?= $(TARGET_ARCH) + +VVCAM_KERNELENVSH := $(VVCAM_OUT)/kernelenv.sh +$(VVCAM_KERNELENVSH): + mkdir -p $(VVCAM_OUT) + echo 'export KERNEL_DIR=$(KERNEL_DIR)' > $(VVCAM_KERNELENVSH) + echo 'export CROSS_COMPILE=$(VVCAM_CROSS_COMPILE)' >> $(VVCAM_KERNELENVSH) + echo 'export ARCH_TYPE=$(ARCH_TYPE)' >> $(VVCAM_KERNELENVSH) + +vvcam: $(VVCAM_KERNELENVSH) $(VVCAM_SRC_PATH) + $(hide) if [ ${clean_build} = 1 ]; then \ + PATH=$$PATH $(MAKE) -f Kbuild -C $(VVCAM_SRC_PATH) ANDROID=yes clean; \ + fi + @ . $(VVCAM_KERNELENVSH); $(kernel_build_shell_env) \ + $(MAKE) -f Kbuild -C $(VVCAM_SRC_PATH) ANDROID=yes \ + PWD=$(ANDROID_BUILD_TOP)/vendor/nxp-opensource/verisilicon_sw_isp_vvcam/vvcam/v4l2 \ + $(CLANG_TO_COMPILE) \ + $(KERNEL_CFLAGS) \ + ARCH_TYPE=$(ARCH_TYPE) \ + DEBUG=$(DEBUG); \ + cp $(VVCAM_SRC_PATH)/sensor/ov2775/ov2775.ko $(VVCAM_OUT); + cp $(VVCAM_SRC_PATH)/sensor/camera-proxy-driver/basler-camera-driver-vvcam.ko $(VVCAM_OUT); + cp $(VVCAM_SRC_PATH)/sensor/os08a20/os08a20.ko $(VVCAM_OUT); + cp $(VVCAM_SRC_PATH)/video/vvcam-video.ko $(VVCAM_OUT); + cp $(VVCAM_SRC_PATH)/vvcam-isp.ko $(VVCAM_OUT); + cp $(VVCAM_SRC_PATH)/vvcam-dwe.ko $(VVCAM_OUT);