mirror of
https://github.com/thead-yocto-mirror/vi-kernel
synced 2026-07-20 06:48:08 +02:00
346 lines
11 KiB
C
Executable File
346 lines
11 KiB
C
Executable File
/*
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* Copyright (C) 2021 Alibaba Group Holding Limited
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* Author: Shenwuyi <shenwuyi.swy@alibaba-inc.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __VI_PRE_H__
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#define __VI_PRE_H__
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/of_irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_dma.h>
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#include <linux/device.h>
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#include <linux/videodev2.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/cdev.h>
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#define VI_PRE_DEV_NAME "vi_pre"
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#define VI_PRE_NAME "vipre"
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#define VI_PRE_MAXCNT 1
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#define HDRPRO_CTRL(n) (0x0094 + (n-1) * 4)
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#define HDRPRO_COE(n) (0x009c + (n-1) * 4)
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#define HDRPRO_LINW(n) (0x00b0 + (n-1) * 4)
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#define HDRPRO_LINA(n) (0x00d0 + (n-1) * 4)
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#define HDRPRO_LINB(n) (0x0110 + (n-1) * 4)
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#define MIPI2DMA_CTRL(n) (0x0198 + (n) * 4)
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#define VIPRE_BUS_ERR (1 << 5)
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#define VIPRE_FIFO_OVER (1 << 4)
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#define VIPRE_IDLE_DONE (1 << 3)
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#define VIPRE_NMOVERFLOW (1 << 2)
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#define VIPRE_LINE_DONE (1 << 1)
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#define VIPRE_FRAME_DONE (1 << 0)
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/* mipi2dma ctrl0 */
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enum mipi2dma_ctrl0_regval {
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//RAWMOD
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MIPI2DMA_CTRL0_RAW6 = 0 << 4,
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MIPI2DMA_CTRL0_RAW7 = 1 << 4,
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MIPI2DMA_CTRL0_RAW8 = 2 << 4,
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MIPI2DMA_CTRL0_RAW10 = 3 << 4,
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MIPI2DMA_CTRL0_RAW12 = 4 << 4,
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//RAWPOS
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MIPI2DMA_CTRL0_LOW_BIT_MODE = 0 << 3,
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MIPI2DMA_CTRL0_HIGH_BIT_MODE = 1 << 3,
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//mnum
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MIPI2DMA_CTRL0_1_FRAME = 0 << 1,
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MIPI2DMA_CTRL0_2_FRAME = 1 << 1,
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MIPI2DMA_CTRL0_3_FRAME = 2 << 1,
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MIPI2DMA_CTRL0_4_FRAME = 3 << 1,
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//mnmod
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MIPI2DMA_CTRL0_MODE_M_FRAME = 0 << 0,
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MIPI2DMA_CTRL0_MODE_N_LINE = 1 << 0,
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};
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/* mipi2dma ctrl1 */
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enum mipi2dma_ctrl1_regval {
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//MIPI2DMA_WBURSTLEN
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MIPI2DMA_CTRL1_WBURSTLEN_4 = 3 << 16,
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MIPI2DMA_CTRL1_WBURSTLEN_8 = 7 << 16,
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MIPI2DMA_CTRL1_WBURSTLEN_16 = 15 << 16,
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};
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/* mipi2dma ctrl10 */
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enum mipi2dma_ctrl10_regval {
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MIPI2DMA_START = 1 << 0,
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MIPI2DMA_STOP = 0 << 0,
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};
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/* mipi2dma ctrl51 */
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enum mipi2dma_ctrl51_regval {
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MIPI2DMA_CTRL51_CROSS_4K_EN = 1 << 0,
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MIPI2DMA_CTRL51_CROSS_4K_DIS = 0 << 0,
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};
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//MIPI2DMA
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#define MIPI2DMA_CTRL1_WOSNUM_SHIFT 0
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#define MIPI2DMA_CTRL3_VERTICAL_SHIFT 16
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#define MIPI2DMA_CTRL3_HORIZON_SHIFT 0
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#define MIPI2DMA_CTRL4_BURSTREM_SHIFT 27
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#define MIPI2DMA_CTRL4_READNUM_SHIFT 16
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#define MIPI2DMA_CTRL4_HORIZON_CNT128_SHIFT 0
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#define MIPI2DMA_CTRL5_N_NLINENUM_SHIFT 16
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#define MIPI2DMA_CTRL5_N_LINENUM_SHIFT 0
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#define MIPI2DMA_CTRL6_N_STRIDE_SHIFT 0
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#define MIPI2DMA_CTRL7_M0_STRIDE_SHIFT 16
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#define MIPI2DMA_CTRL7_M1_STRIDE_SHIFT 0
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#define MIPI2DMA_CTRL8_M2_STRIDE_SHIFT 16
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#define MIPI2DMA_CTRL8_M3_STRIDE_SHIFT 0
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#define MIPI2DMA_CTRL15_N_SADDR_ID0_H_SHIFT 0
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#define MIPI2DMA_CTRL16_N_SADDR_ID0_L_SHIFT 0
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#define MIPI2DMA_CTRL17_N_SADDR_ID1_H_SHIFT 0
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#define MIPI2DMA_CTRL18_N_SADDR_ID1_L_SHIFT 0
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#define MIPI2DMA_CTRL19_N_SADDR_ID2_H_SHIFT 0
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#define MIPI2DMA_CTRL20_N_SADDR_ID2_L_SHIFT 0
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#define MIPI2DMA_CTRL25_M0_SADDR_ID0_H_SHIFT 0
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#define MIPI2DMA_CTRL26_M0_SADDR_ID0_L_SHIFT 0
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#define MIPI2DMA_CTRL27_M0_SADDR_ID1_H_SHIFT 0
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#define MIPI2DMA_CTRL28_M0_SADDR_ID1_L_SHIFT 0
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#define MIPI2DMA_CTRL29_M0_SADDR_ID2_H_SHIFT 0
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#define MIPI2DMA_CTRL30_M0_SADDR_ID2_L_SHIFT 0
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#define MIPI2DMA_CTRL31_M1_SADDR_ID0_H_SHIFT 0
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#define MIPI2DMA_CTRL32_M1_SADDR_ID0_L_SHIFT 0
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#define MIPI2DMA_CTRL33_M1_SADDR_ID1_H_SHIFT 0
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#define MIPI2DMA_CTRL34_M1_SADDR_ID1_L_SHIFT 0
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#define MIPI2DMA_CTRL35_M1_SADDR_ID2_H_SHIFT 0
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#define MIPI2DMA_CTRL36_M1_SADDR_ID2_L_SHIFT 0
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#define MIPI2DMA_CTRL37_M2_SADDR_ID0_H_SHIFT 0
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#define MIPI2DMA_CTRL38_M2_SADDR_ID0_L_SHIFT 0
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#define MIPI2DMA_CTRL39_M2_SADDR_ID1_H_SHIFT 0
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#define MIPI2DMA_CTRL40_M2_SADDR_ID1_L_SHIFT 0
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#define MIPI2DMA_CTRL41_M2_SADDR_ID2_H_SHIFT 0
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#define MIPI2DMA_CTRL42_M2_SADDR_ID2_L_SHIFT 0
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#define MIPI2DMA_CTRL44_BUSERR_MASK_SHIFT 21
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#define MIPI2DMA_CTRL44_FIFO_OVERERR_MASK_SHIFT 20
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#define MIPI2DMA_CTRL44_IDLE_DONE_MASK_SHIFT 19
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#define MIPI2DMA_CTRL44_MN_OVERERR_MASK_SHIFT 18
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#define MIPI2DMA_CTRL44_NLINE_DONE_MASK_SHIFT 17
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#define MIPI2DMA_CTRL44_MFRAME_DONE_MASK_SHIFT 16
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#define MIPI2DMA_CTRL45_M3_SADDR_ID0_H_SHIFT 0
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#define MIPI2DMA_CTRL46_M3_SADDR_ID0_L_SHIFT 0
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#define MIPI2DMA_CTRL47_M3_SADDR_ID1_H_SHIFT 0
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#define MIPI2DMA_CTRL48_M3_SADDR_ID1_L_SHIFT 0
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#define MIPI2DMA_CTRL49_M3_SADDR_ID2_H_SHIFT 0
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#define MIPI2DMA_CTRL50_M3_SADDR_ID2_L_SHIFT 0
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//HDRPRO
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#define HDRPRO_CTRL1_HDRPRO_RAWMOD_MASK 0x00e00000
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#define HDRPRO_CTRL1_BAYER_MODSEL_MASK 0x00180000
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#define HDRPRO_CTRL1_COLOR_MODSEL_MASK 0x00070000
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#define HDRPRO_CTRL1_LAST_DELAY_MASK 0x0000fff8
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#define HDRPRO_CTRL1_HDRPRO_ID_MASK 0x00000006
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#define HDRPRO_CTRL1_HDRPRO_EN_MASK 0x00000001
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#define HDRPRO_CTRL1_HDRPRO_ID_SHIFT 1
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#define HDRPRO_CTRL2_VERTICAL_MASK 0x1fff0000
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#define HDRPRO_CTRL2_HORIZON_MASK 0x00001fff
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#define HDRPRO_CTRL2_VERTICAL_SHIFT 16
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#define HDRPRO_CTRL2_HORIZON_SHIFT 0
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#define HDRPRO_COE1_BE_BLACK_WR_MASK 0xf0000000
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#define HDRPRO_COE1_BE_BLACK_WB_MASK 0x0f000000
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#define HDRPRO_COE1_BE_BLACK_WG0_MASK 0x00f00000
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#define HDRPRO_COE1_BE_BLACK_WG1_MASK 0x000f0000
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#define HDRPRO_COE1_BE_COLOR_WG0_00_MASK 0x0000f000
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#define HDRPRO_COE1_BE_COLOR_WG0_01_MASK 0x00000f00
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#define HDRPRO_COE1_BE_COLOR_WG0_02_MASK 0x000000f0
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#define HDRPRO_COE1_BE_COLOR_WG0_10_MASK 0x0000000f
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#define HDRPRO_COE1_BE_BLACK_WR_SHIFT 28
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#define HDRPRO_COE1_BE_BLACK_WB_SHIFT 24
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#define HDRPRO_COE1_BE_BLACK_WG0_SHIFT 20
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#define HDRPRO_COE1_BE_BLACK_WG1_SHIFT 16
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#define HDRPRO_COE1_BE_COLOR_WG0_00_SHIFT 12
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#define HDRPRO_COE1_BE_COLOR_WG0_01_SHIFT 8
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#define HDRPRO_COE1_BE_COLOR_WG0_02_SHIFT 4
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#define HDRPRO_COE1_BE_COLOR_WG0_10_SHIFT 0
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#define HDRPRO_COE2_BE_COLOR_WG0_11_SHIFT 28
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#define HDRPRO_COE2_BE_COLOR_WG0_12_SHIFT 24
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#define HDRPRO_COE2_BE_COLOR_WG0_20_SHIFT 20
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#define HDRPRO_COE2_BE_COLOR_WG0_21_SHIFT 16
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#define HDRPRO_COE2_BE_COLOR_WG0_22_SHIFT 12
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#define HDRPRO_COE2_BE_COLOR_WG1_00_SHIFT 8
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#define HDRPRO_COE2_BE_COLOR_WG1_01_SHIFT 4
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#define HDRPRO_COE2_BE_COLOR_WG1_02_SHIFT 0
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#define HDRPRO_COE3_BE_COLOR_WG1_10_SHIFT 28
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#define HDRPRO_COE3_BE_COLOR_WG1_11_SHIFT 24
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#define HDRPRO_COE3_BE_COLOR_WG1_12_SHIFT 20
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#define HDRPRO_COE3_BE_COLOR_WG1_20_SHIFT 16
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#define HDRPRO_COE3_BE_COLOR_WG1_21_SHIFT 12
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#define HDRPRO_COE3_BE_COLOR_WG1_22_SHIFT 8
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#define HDRPRO_COE3_BE_COLOR_WR_00_SHIFT 4
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#define HDRPRO_COE3_BE_COLOR_WR_01_SHIFT 0
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#define HDRPRO_COE4_BE_COLOR_WR_02_SHIFT 28
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#define HDRPRO_COE4_BE_COLOR_WR_10_SHIFT 24
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#define HDRPRO_COE4_BE_COLOR_WR_11_SHIFT 20
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#define HDRPRO_COE4_BE_COLOR_WR_12_SHIFT 16
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#define HDRPRO_COE4_BE_COLOR_WR_20_SHIFT 12
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#define HDRPRO_COE4_BE_COLOR_WR_21_SHIFT 8
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#define HDRPRO_COE4_BE_COLOR_WR_22_SHIFT 4
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#define HDRPRO_COE4_BE_COLOR_WB_00_SHIFT 0
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#define HDRPRO_COE5_BE_COLOR_WB_01_SHIFT 28
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#define HDRPRO_COE5_BE_COLOR_WB_02_SHIFT 24
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#define HDRPRO_COE5_BE_COLOR_WB_10_SHIFT 20
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#define HDRPRO_COE5_BE_COLOR_WB_11_SHIFT 16
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#define HDRPRO_COE5_BE_COLOR_WB_12_SHIFT 12
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#define HDRPRO_COE5_BE_COLOR_WB_20_SHIFT 8
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#define HDRPRO_COE5_BE_COLOR_WB_21_SHIFT 4
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#define HDRPRO_COE5_BE_COLOR_WB_22_SHIFT 0
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#define HDRPRO_LINW1_W1_MASK 0x0fff0000
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#define HDRPRO_LINW1_W2_MASK 0x00000fff
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#define HDRPRO_LINW2_W3_MASK 0x0fff0000
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#define HDRPRO_LINW2_W4_MASK 0x00000fff
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#define HDRPRO_LINW3_W5_MASK 0x0fff0000
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#define HDRPRO_LINW3_W6_MASK 0x00000fff
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#define HDRPRO_LINW4_W7_MASK 0x0fff0000
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#define HDRPRO_LINW4_W8_MASK 0x00000fff
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#define HDRPRO_LINW5_W9_MASK 0x0fff0000
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#define HDRPRO_LINW5_W10_MASK 0x00000fff
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#define HDRPRO_LINW6_W11_MASK 0x0fff0000
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#define HDRPRO_LINW6_W12_MASK 0x00000fff
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#define HDRPRO_LINW7_W13_MASK 0x0fff0000
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#define HDRPRO_LINW7_W14_MASK 0x00000fff
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#define HDRPRO_LINW8_W15_MASK 0x0fff0000
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#define HDRPRO_LINW8_W16_MASK 0x00000fff
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#define HDRPRO_LINW1_W1_SHIFT 16
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#define HDRPRO_LINW1_W2_SHIFT 0
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#define HDRPRO_LINW2_W3_SHIFT 16
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#define HDRPRO_LINW2_W4_SHIFT 0
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#define HDRPRO_LINW3_W5_SHIFT 16
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#define HDRPRO_LINW3_W6_SHIFT 0
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#define HDRPRO_LINW4_W7_SHIFT 16
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#define HDRPRO_LINW4_W8_SHIFT 0
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#define HDRPRO_LINW5_W9_SHIFT 16
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#define HDRPRO_LINW5_W10_SHIFT 0
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#define HDRPRO_LINW6_W11_SHIFT 16
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#define HDRPRO_LINW6_W12_SHIFT 0
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#define HDRPRO_LINW7_W13_SHIFT 16
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#define HDRPRO_LINW7_W14_SHIFT 0
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#define HDRPRO_LINW8_W15_SHIFT 16
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#define HDRPRO_LINW8_W16_SHIFT 0
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#define HDRPRO_LINA1_A1_MASK 0x000fffff
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#define HDRPRO_LINA2_A2_MASK 0x000fffff
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#define HDRPRO_LINA3_A3_MASK 0x000fffff
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#define HDRPRO_LINA4_A4_MASK 0x000fffff
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#define HDRPRO_LINA5_A5_MASK 0x000fffff
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#define HDRPRO_LINA6_A6_MASK 0x000fffff
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#define HDRPRO_LINA7_A7_MASK 0x000fffff
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#define HDRPRO_LINA8_A8_MASK 0x000fffff
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#define HDRPRO_LINA9_A9_MASK 0x000fffff
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#define HDRPRO_LINA10_A10_MASK 0x000fffff
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#define HDRPRO_LINA11_A11_MASK 0x000fffff
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#define HDRPRO_LINA12_A12_MASK 0x000fffff
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#define HDRPRO_LINA13_A13_MASK 0x000fffff
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#define HDRPRO_LINA14_A14_MASK 0x000fffff
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#define HDRPRO_LINA15_A15_MASK 0x000fffff
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#define HDRPRO_LINA16_A16_MASK 0x000fffff
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#define HDRPRO_LINA1_A1_SHIFT 0
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#define HDRPRO_LINA2_A2_SHIFT 0
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#define HDRPRO_LINA3_A3_SHIFT 0
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#define HDRPRO_LINA4_A4_SHIFT 0
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#define HDRPRO_LINA5_A5_SHIFT 0
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#define HDRPRO_LINA6_A6_SHIFT 0
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#define HDRPRO_LINA7_A7_SHIFT 0
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#define HDRPRO_LINA8_A8_SHIFT 0
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#define HDRPRO_LINA9_A9_SHIFT 0
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#define HDRPRO_LINA10_A10_SHIFT 0
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#define HDRPRO_LINA11_A11_SHIFT 0
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#define HDRPRO_LINA12_A12_SHIFT 0
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#define HDRPRO_LINA13_A13_SHIFT 0
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#define HDRPRO_LINA14_A14_SHIFT 0
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#define HDRPRO_LINA15_A15_SHIFT 0
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#define HDRPRO_LINA16_A16_SHIFT 0
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#define HDRPRO_LINB1_B1_MASK 0x0000ffff
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#define HDRPRO_LINB2_B2_MASK 0x0000ffff
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#define HDRPRO_LINB3_B3_MASK 0x0000ffff
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#define HDRPRO_LINB4_B4_MASK 0x0000ffff
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#define HDRPRO_LINB5_B5_MASK 0x0000ffff
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#define HDRPRO_LINB6_B6_MASK 0x0000ffff
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#define HDRPRO_LINB7_B7_MASK 0x0000ffff
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#define HDRPRO_LINB8_B8_MASK 0x0000ffff
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#define HDRPRO_LINB9_B9_MASK 0x0000ffff
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#define HDRPRO_LINB10_B10_MASK 0x0000ffff
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#define HDRPRO_LINB11_B11_MASK 0x0000ffff
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#define HDRPRO_LINB12_B12_MASK 0x0000ffff
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#define HDRPRO_LINB13_B13_MASK 0x0000ffff
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#define HDRPRO_LINB14_B14_MASK 0x0000ffff
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#define HDRPRO_LINB15_B15_MASK 0x0000ffff
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#define HDRPRO_LINB16_B16_MASK 0x0000ffff
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#define HDRPRO_LINB1_B1_SHIFT 0
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#define HDRPRO_LINB2_B2_SHIFT 0
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#define HDRPRO_LINB3_B3_SHIFT 0
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#define HDRPRO_LINB4_B4_SHIFT 0
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#define HDRPRO_LINB5_B5_SHIFT 0
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#define HDRPRO_LINB6_B6_SHIFT 0
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#define HDRPRO_LINB7_B7_SHIFT 0
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#define HDRPRO_LINB8_B8_SHIFT 0
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#define HDRPRO_LINB9_B9_SHIFT 0
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#define HDRPRO_LINB10_B10_SHIFT 0
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#define HDRPRO_LINB11_B11_SHIFT 0
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#define HDRPRO_LINB12_B12_SHIFT 0
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#define HDRPRO_LINB13_B13_SHIFT 0
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#define HDRPRO_LINB14_B14_SHIFT 0
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#define HDRPRO_LINB15_B15_SHIFT 0
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#define HDRPRO_LINB16_B16_SHIFT 0
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struct vi_pre_dev {
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int id;
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int irq;
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dev_t devt;
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struct class *class;
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struct cdev cdev;
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spinlock_t slock; /* interrupt handling lock */
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struct mutex mutex;
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void __iomem *reg_base;
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unsigned long cnt; //used to cnt frame num or line num;
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int update_frame_id;
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int update_vc_id;
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bool is_mframe_mode;
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struct clk *aclk;
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struct clk *pclk;
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struct clk *pixclk;
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struct platform_device *pdev;
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};
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#endif/*__VI_PRE_H__*/
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