mirror of
https://github.com/thead-yocto-mirror/vi-kernel
synced 2026-07-20 23:08:03 +02:00
288 lines
8.2 KiB
C
Executable File
288 lines
8.2 KiB
C
Executable File
/*
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* Copyright (C) 2021 Alibaba Group Holding Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/regmap.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/io.h>
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#include "dec400.h"
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#include "dec400_ioctl.h"
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#define DEC400_WRITE_PHYSICAL_ADDR 0xc2a00000
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//#define DEC400_WRITE_PHYSICAL_ADDR 0xe10b8000
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#define DEC400_READ_PHYSICAL_ADDR 0xe0ac8000
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#define RES 3
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#define DEBUG
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static void dec400_write(struct dec400_dev *dec, unsigned int addr, unsigned int val)
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{
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writel(val, dec->reg_base + addr);
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}
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static void dec400_set_bypass(struct dec400_dev *dec, void *args)
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{
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dec400_write(dec, DEC_CONTROL, DEC_BYPASS);
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}
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static int dec400_compress_init(struct dec400_dev *dec, void *args)
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{
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unsigned int val = 0;
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//val = 0;
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//val |= DEC_EN;
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//val |= 0x00FC0000; //need confirm with VSI, no any description
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//dec400_write(dec, DEC_CONTROL, val); //val 0x00FC0000
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dec400_write(dec, DEC_CONTROL, 0x100008c); //0x101008c
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//val = 0;
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//val |= WRITE_MISS_POLICY;
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//dec400_write(dec, DEC_CONTROL_EX, val);//0x00080000
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dec400_write(dec, DEC_CONTROL_EX, 0xa0000);
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//Tile status cache's AXI read/write ID.
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//val = 0x00410104;
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//dec400_write(dec, DEC_CONTROL_EX2, val);
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dec400_write(dec, DEC_CONTROL_EX2, 0x3fe840);
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//enable intr
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dec400_write(dec, 0x80c, 0xffffffff);
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dec400_write(dec, 0x810, 0xffffffff);
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dec400_write(dec, 0x814, 0xffffffff);
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return 0;
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}
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static int dec400_mmu_config(struct dec400_dev *dec, void *args)
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{
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#define ISP0_PAGE_TABLE_ARRAY_ADDR 0xEEFFFFF0
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unsigned int val = 0;
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val = 0;
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val |= DEC_EN;
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val |= 0x00FC0000; //need confirm with VSI, no any description
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dec400_write(dec, DEC_CONTROL, val); //val 0x00FC0000
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dec400_write(dec, 0x0388, 0x00000001); //0xE2 gcregMMUAHBControlRegAddrs
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// table array base address
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//0xFEFFFFF0
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dec400_write(dec, 0x038C, ISP0_PAGE_TABLE_ARRAY_ADDR); // 0xE3 gcregMMUAHBTableArrayBaseAddressLowRegAddrs
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//WriteRegister(reg_base, 0x00184, 0x00000001);//gcregMMUConfigurationRegAddrs, flush
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dec400_write(dec, 0x01AC, 0x00000000);//dcreMMUConfigRegAddrs
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return 0;
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}
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static int dec400_compress_set_buffer(struct dec400_dev *dec, void *args)
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{
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unsigned int y_start = 0, y_end = 0, y_cache = 0;
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unsigned int uv_start = 0, uv_end = 0, uv_cache = 0;
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unsigned int val = 0;
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y_start = DEC400_WRITE_PHYSICAL_ADDR;
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y_end = y_start + dec_timing[RES].y_total - 1;
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y_cache = y_start + dec_timing[RES].buffer_offset;
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uv_start = y_start + dec_timing[RES].y_total;
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uv_end = uv_start + dec_timing[RES].uv_total - 1;
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uv_cache = y_cache + dec_timing[RES].uv_total;
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#ifdef DEBUG
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pr_info("%s, dec400 y_start = 0x%x, y_end = 0x%x, uv_start = 0x%x, uv_end = 0x%x\n",
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__func__, y_start, y_end, uv_start, uv_end);
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pr_info("%s, dec400 y_cache = 0x%x, uv_cache = 0x%x\n", __func__, y_cache, uv_cache);
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#endif
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val = 0;
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val |= DEC_COMPRESS_EN;
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val |= DEC_FMT_YUV_ONLY;
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val |= DEC_ALIGN_32_BYTE;
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val |= DEC_RASTER128X1;
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dec400_write(dec, DEC_WRITE_CFG_CH(0), val);
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dec400_write(dec, DEC_WRITE_EX_CFG_CH(0), 0);
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dec400_write(dec, DEC_WRITE_BUF_BASE_CH(0), y_start);
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dec400_write(dec, DEC_WRITE_BUF_END_CH(0), y_end);
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dec400_write(dec, DEC_WRITE_CACHE_BASE_CH(0), y_cache);
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dec400_write(dec, 0xf80, 0xffffffff);
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#ifdef DEBUG
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pr_info("%s, dec400 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n",
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__func__,
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DEC_WRITE_CFG_CH(0), val,
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DEC_WRITE_EX_CFG_CH(0), 0,
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DEC_WRITE_BUF_BASE_CH(0), y_start,
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DEC_WRITE_BUF_END_CH(0), y_end,
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DEC_WRITE_CACHE_BASE_CH(0), y_cache);
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#endif
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val = 0;
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val |= DEC_COMPRESS_EN;
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val |= DEC_FMT_UV_MIX;
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val |= DEC_ALIGN_32_BYTE;
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val |= DEC_RASTER64X1;
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dec400_write(dec, DEC_WRITE_CFG_CH(1), val);
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dec400_write(dec, DEC_WRITE_EX_CFG_CH(1), 0);
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dec400_write(dec, DEC_WRITE_BUF_BASE_CH(1), uv_start);
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dec400_write(dec, DEC_WRITE_BUF_END_CH(1), uv_end);
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dec400_write(dec, DEC_WRITE_CACHE_BASE_CH(1), uv_cache);
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dec400_write(dec, 0xf84, 0xffffffff);
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#ifdef DEBUG
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pr_info("%s, dec400+1 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n",
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__func__,
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DEC_WRITE_CFG_CH(1), val,
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DEC_WRITE_EX_CFG_CH(1), 0,
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DEC_WRITE_BUF_BASE_CH(1), uv_start,
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DEC_WRITE_BUF_END_CH(1), uv_end,
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DEC_WRITE_CACHE_BASE_CH(1), uv_cache);
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#endif
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return 0;
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}
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static int dec400_decompress_init(struct dec400_dev *dec, void *args)
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{
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unsigned int val = 0;
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//val = 0;
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//val |= DEC_EN;
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//val |= 0x00FC0000; //need confirm with VSI, no any description
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//dec400_write(dec, DEC_CONTROL, val); //val 0x00FC0000
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dec400_write(dec, DEC_CONTROL, 0x100008c); //0x101008c
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//val = 0;
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//val |= WRITE_MISS_POLICY;
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//dec400_write(dec, DEC_CONTROL_EX, val);//0x00080000
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dec400_write(dec, DEC_CONTROL_EX, 0xa0000);
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//Tile status cache's AXI read/write ID.
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//val = 0x00410104;
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//dec400_write(dec, DEC_CONTROL_EX2, val);
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dec400_write(dec, DEC_CONTROL_EX2, 0x3fe840);
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//enable intr
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dec400_write(dec, 0x80c, 0xffffffff);
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dec400_write(dec, 0x810, 0xffffffff);
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dec400_write(dec, 0x814, 0xffffffff);
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return 0;
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}
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static int dec400_decompress_set_buffer(struct dec400_dev *dec, void *args)
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{
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unsigned int y_start = 0, y_end = 0, y_cache = 0;
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unsigned int uv_start = 0, uv_end = 0, uv_cache = 0;
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unsigned int val = 0;
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y_start = DEC400_READ_PHYSICAL_ADDR;
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y_end = y_start + dec_timing[RES].y_total - 1;
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//y_cache = y_start + dec_timing[RES].buffer_offset;
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y_cache = DEC400_WRITE_PHYSICAL_ADDR + dec_timing[RES].buffer_offset;
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uv_start = y_start + dec_timing[RES].y_total;
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uv_end = uv_start + dec_timing[RES].uv_total - 1;
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uv_cache = y_cache + dec_timing[RES].uv_total;
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#ifdef DEBUG
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pr_info("%s, dec400 y_start = 0x%x, y_end = 0x%x, uv_start = 0x%x, uv_end = 0x%x\n",
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__func__, y_start, y_end, uv_start, uv_end);
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pr_info("%s, dec400 y_cache = 0x%x, uv_cache = 0x%x\n", __func__, y_cache, uv_cache);
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#endif
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#if 0
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dec400_write(dec, 0x00000880, 0x14020029);
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dec400_write(dec, 0x00000900, 0x00000000);
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dec400_write(dec, 0x00000A80, y_start);
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dec400_write(dec, 0x00001080, y_cache);
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dec400_write(dec, 0x00000B80, y_end);
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dec400_write(dec, 0x00000884, 0x1E020031);
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dec400_write(dec, 0x00000904, 0x00000000);
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dec400_write(dec, 0x00000A84, uv_start);
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dec400_write(dec, 0x00001084, uv_cache);
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dec400_write(dec, 0x00000B84, uv_end);
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#endif
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val = 0;
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val |= DEC_COMPRESS_EN;
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val |= DEC_FMT_YUV_ONLY;
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val |= DEC_ALIGN_32_BYTE;
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val |= DEC_RASTER128X1;
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dec400_write(dec, DEC_READ_CFG_CH(0), val);
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dec400_write(dec, DEC_READ_EX_CFG_CH(0), 0);
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dec400_write(dec, DEC_READ_BUF_BASE_CH(0), y_start);
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dec400_write(dec, DEC_READ_BUF_END_CH(0), y_end);
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dec400_write(dec, DEC_READ_CACHE_BASE_CH(0), y_cache);
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#ifdef DEBUG
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pr_info("%s, dec400+1 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n",
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__func__,
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DEC_READ_CFG_CH(0), val,
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DEC_READ_EX_CFG_CH(0), 0,
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DEC_READ_BUF_BASE_CH(0), y_start,
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DEC_READ_BUF_END_CH(0), y_end,
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DEC_READ_CACHE_BASE_CH(0), y_cache);
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#endif
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val = 0;
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val |= DEC_COMPRESS_EN;
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val |= DEC_FMT_UV_MIX;
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val |= DEC_ALIGN_32_BYTE;
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val |= DEC_RASTER64X1;
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dec400_write(dec, DEC_READ_CFG_CH(1), val);
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dec400_write(dec, DEC_READ_EX_CFG_CH(1), 0);
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dec400_write(dec, DEC_READ_BUF_BASE_CH(1), uv_start);
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dec400_write(dec, DEC_READ_BUF_END_CH(1), uv_end);
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dec400_write(dec, DEC_READ_CACHE_BASE_CH(1), uv_cache);
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#ifdef DEBUG
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pr_info("%s, dec400+1 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n",
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__func__,
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DEC_READ_CFG_CH(1), val,
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DEC_READ_EX_CFG_CH(1), 0,
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DEC_READ_BUF_BASE_CH(1), uv_start,
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DEC_READ_BUF_END_CH(1), uv_end,
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DEC_READ_CACHE_BASE_CH(1), uv_cache);
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#endif
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return 0;
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}
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unsigned int dec400_priv_ioctl(struct dec400_dev *dev, unsigned int cmd, void *args)
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{
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int ret = -1;
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if (!dev) {
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pr_err("%s invalid para\n", __func__);
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return ret;
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}
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switch (cmd) {
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case DEC400IOC_RESET:
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ret = 0;
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break;
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case DEC400IOC_COMPRESS_INIT:
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ret = dec400_compress_init(dev, args);
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break;
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case DEC400IOC_COMPRESS_SET_BUFFER:
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ret = dec400_compress_set_buffer(dev, args);
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break;
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case DEC400IOC_DECOMPRESS_INIT:
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ret = dec400_decompress_init(dev, args);
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break;
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case DEC400IOC_DECOMPRESS_SET_BUFFER:
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ret = dec400_decompress_set_buffer(dev, args);
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break;
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case DEC400IOC_MMU_CONFIG:
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ret = dec400_mmu_config(dev, args);
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break;
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default:
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pr_err("unsupported command %d\n", cmd);
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break;
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}
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return ret;
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}
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