mirror of
https://github.com/thead-yocto-mirror/vi-kernel
synced 2026-06-21 17:02:34 +02:00
382 lines
9.8 KiB
C
Executable File
382 lines
9.8 KiB
C
Executable File
/****************************************************************************
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*****************************************************************************
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*
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* The GPL License (GPL)
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*
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* Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program;
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*
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*****************************************************************************
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*
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* Note: This software is released under dual MIT and GPL licenses. A
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* recipient may use this file under the terms of either the MIT license or
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* GPL License. If you wish to use only one license not the other, you can
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* indicate your decision by deleting one of the above license notices in your
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* version of this file.
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*
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*****************************************************************************/
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#include "dwe_ioctl.h"
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#include "dwe_regs.h"
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#ifndef __KERNEL__
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#include <stdlib.h>
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#include <unistd.h>
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#include <string.h>
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#ifdef USE_V4L2
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#include <linux/videodev2.h>
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#endif
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#endif
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#ifndef __KERNEL__
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#ifdef HAL_CMODEL
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#define DEWARP_REGISTER_OFFSET 0
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#else
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#define DEWARP_REGISTER_OFFSET 0x380000
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#endif
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#define DEWARP_REGISTER_CTL 0x308250
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pReadBar g_read_func;
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pWriteBar g_write_func;
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void dwe_set_func(pReadBar read_func, pWriteBar write_func)
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{
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g_read_func = read_func;
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g_write_func = write_func;
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}
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void dwe_write_reg(struct dwe_ic_dev *dev, u32 offset, u32 val)
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{
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g_write_func(DEWARP_REGISTER_OFFSET + offset, val);
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}
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u32 dwe_read_reg(struct dwe_ic_dev *dev, u32 offset)
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{
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u32 data;
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g_read_func(DEWARP_REGISTER_OFFSET + offset, &data);
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return data;
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}
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void dwe_write_extreg(u32 offset, u32 val)
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{
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g_write_func(DEWARP_REGISTER_CTL + offset, val);
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}
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u32 dwe_read_extreg(u32 offset)
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{
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u32 data;
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g_read_func(DEWARP_REGISTER_CTL + offset, &data);
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return data;
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}
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long dwe_copy_data(void *dst, void *src, int size)
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{
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if (dst != src)
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memcpy(dst, src, size);
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return 0;
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}
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#else
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void dwe_write_reg(struct dwe_ic_dev *dev, u32 offset, u32 val)
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{
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__raw_writel(val, dev->base + offset);
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}
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u32 dwe_read_reg(struct dwe_ic_dev *dev, u32 offset)
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{
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return __raw_readl(dev->base + offset);
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}
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#endif
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int dwe_reset(struct dwe_ic_dev *dev)
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{
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pr_debug("enter %s\n", __func__);
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#ifdef DWE_REG_RESET
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__raw_writel(0, dev->reset);
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__raw_writel(1, dev->reset);
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#endif
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dwe_write_reg(dev, DEWARP_CTRL, 0x0c);
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return 0;
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}
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int dwe_s_params(struct dwe_ic_dev *dev, struct dwe_hw_info *info)
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{
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u32 reg = 0;
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u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16);
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u32 vUp = (info->split_v1 & ~0x0F) | 0x0C;
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u32 vDown = (info->split_v2 & ~0x0F) | 0x0C;
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u32 hLine = (info->split_h & ~0x0F) | 0x0C;
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pr_debug("enter %s\n", __func__);
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dwe_write_reg(dev, MAP_LUT_SIZE,
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((info->map_w & 0x7ff) | ((info->map_h & 0x7ff) << 16)));
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dwe_write_reg(dev, SRC_IMG_SIZE,
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((info->src_w & 0x1fff) |
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((info->src_h & 0x1fff) << 16)));
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dwe_write_reg(dev, SRC_IMG_STRIDE, info->src_stride);
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dwe_write_reg(dev, DST_IMG_SIZE,
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((info->dst_w & 0x1FFF) |
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((info->dst_h & 0x1FFF) << 16)));
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dwe_write_reg(dev, DST_IMG_STRIDE, info->dst_stride);
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dwe_write_reg(dev, DST_IMG_Y_SIZE1, reg_y_rbuff_size >> 4);
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dwe_write_reg(dev, DST_IMG_UV_SIZE1, info->dst_size_uv >> 4);
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dwe_write_reg(dev, VERTICAL_SPLIT_LINE,
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(vUp & 0x1fff) | ((vDown & 0x1fff) << 16));
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dwe_write_reg(dev, HORIZON_SPLIT_LINE, (hLine & 0x1fff));
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reg = 0x4C800001;
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reg |= ((info->split_line & 0x1) << 11);
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reg |= ((info->in_format & 0x3) << 4);
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reg |= ((info->out_format & 0x3) << 6);
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reg |=
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((info->src_auto_shadow & 0x1) << 8) |
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((info->dst_auto_shadow & 0x1) << 10);
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reg |= ((info->hand_shake & 0x1) << 9);
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dwe_write_reg(dev, DEWARP_CTRL, reg);
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dwe_write_reg(dev, BOUNDRY_PIXEL,
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(((info->boundary_y & 0xff) << 16) |
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((info->boundary_u & 0xff)
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<< 8) | (info->boundary_v & 0xff)));
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dwe_write_reg(dev, SCALE_FACTOR, info->scale_factor);
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dwe_write_reg(dev, ROI_START,
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((info->roi_x & 0x1fff) |
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((info->roi_y & 0x1fff) << 16)));
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return 0;
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}
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int dwe_enable_bus(struct dwe_ic_dev *dev, bool enable)
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{
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u32 reg = dwe_read_reg(dev, BUS_CTRL);
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/* pr_debug("enter %s\n", __func__); */
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if (enable) {
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dwe_write_reg(dev, BUS_CTRL, reg | DEWRAP_BUS_CTRL_ENABLE_MASK);
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} else {
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dwe_write_reg(dev, BUS_CTRL,
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reg & ~DEWRAP_BUS_CTRL_ENABLE_MASK);
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}
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return 0;
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}
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int dwe_disable_irq(struct dwe_ic_dev *dev)
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{
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/* pr_debug("enter %s\n", __func__); */
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dwe_write_reg(dev, INTERRUPT_STATUS, INT_CLR_MASK);
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return 0;
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}
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int dwe_clear_irq(struct dwe_ic_dev *dev)
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{
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u32 reg_dewarp_ctrl;
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/* pr_debug("enter %s\n", __func__); */
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reg_dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL);
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dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl | 2);
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dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl);
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dwe_write_reg(dev, INTERRUPT_STATUS, INT_CLR_MASK | INT_MSK_STATUS_MASK);
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return 0;
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}
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int dwe_read_irq(struct dwe_ic_dev *dev, u32 *ret)
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{
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u32 irq = 0;
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irq = dwe_read_reg(dev, INTERRUPT_STATUS);
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*ret = irq;
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return 0;
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}
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int dwe_start(struct dwe_ic_dev *dev)
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{
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#if defined(__KERNEL__) && defined(ENABLE_IRQ)
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dev->src = NULL;
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dev->dst = NULL;
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dev->error = BUF_ERR_UNDERFLOW;
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#endif
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return 0;
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}
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int dwe_stop(struct dwe_ic_dev *dev)
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{
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dwe_enable_bus(dev, 0);
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dwe_disable_irq(dev);
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return 0;
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}
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int dwe_start_dma_read(struct dwe_ic_dev *dev,
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struct dwe_hw_info *info, u64 addr)
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{
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#ifdef DWE_REG_RESET
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u32 regStart = 1 << 4;
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u32 reg;
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#endif
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u32 reg_dst_y_base = (u32)addr;
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u32 reg_y_rbuff_size = ALIGN_UP(info->src_stride * info->src_h, 16);
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u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size;
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/* pr_debug("enter %s\n", __func__); */
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dwe_write_reg(dev, SRC_IMG_Y_BASE, (reg_dst_y_base) >> 4);
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dwe_write_reg(dev, SRC_IMG_UV_BASE, (reg_dst_uv_base) >> 4);
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#ifdef DWE_REG_RESET
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reg = __raw_readl(dev->reset);
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__raw_writel(reg | regStart, dev->reset);
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__raw_writel(reg & ~regStart, dev->reset);
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#endif
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return 0;
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}
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int dwe_set_buffer(struct dwe_ic_dev *dev, struct dwe_hw_info *info, u64 addr)
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{
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u32 reg_dst_y_base = (u32) addr;
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u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16);
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u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size;
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/* pr_debug("enter %s\n", __func__); */
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dwe_write_reg(dev, DST_IMG_Y_BASE, (reg_dst_y_base) >> 4);
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dwe_write_reg(dev, DST_IMG_UV_BASE, (reg_dst_uv_base) >> 4);
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return 0;
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}
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int dwe_set_lut(struct dwe_ic_dev *dev, u64 addr)
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{
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dwe_write_reg(dev, MAP_LUT_ADDR, ((u32) addr) >> 4);
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return 0;
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}
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int dwe_ioc_qcap(struct dwe_ic_dev *dev, void __user *args)
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{
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#ifdef __KERNEL__
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struct v4l2_capability *cap = (struct v4l2_capability *)args;
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strcpy((char *)cap->driver, "viv_dewarp100");
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#endif
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return 0;
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}
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long dwe_priv_ioctl(struct dwe_ic_dev *dev, unsigned int cmd, void __user *args)
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{
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int ret = -1;
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switch (cmd) {
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case DWEIOC_RESET:
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ret = dwe_reset(dev);
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break;
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case DWEIOC_S_PARAMS:
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viv_check_retval(copy_from_user
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(&dev->info[0][0], args, sizeof(dev->info[0][0])));
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ret = dwe_s_params(dev, &dev->info[0][0]);
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break;
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#ifndef ENABLE_IRQ
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case DWEIOC_ENABLE_BUS:
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ret = dwe_enable_bus(dev, 1);
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break;
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case DWEIOC_DISABLE_BUS:
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ret = dwe_enable_bus(dev, 0);
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break;
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case DWEIOC_DISABLE_IRQ:
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ret = dwe_disable_irq(dev);
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break;
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case DWEIOC_CLEAR_IRQ:
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ret = dwe_clear_irq(dev);
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break;
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#endif
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case DWEIOC_READ_IRQ: {
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u32 irq = 0;
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#ifndef ENABLE_IRQ
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ret = dwe_read_irq(dev, &irq);
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#endif
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viv_check_retval(copy_to_user(args, &irq, sizeof(irq)));
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break;
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}
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case DWEIOC_START:
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ret = dwe_start(dev);
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break;
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case DWEIOC_STOP:
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ret = dwe_stop(dev);
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break;
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case DWEIOC_START_DMA_READ: {
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#ifndef ENABLE_IRQ
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u64 addr;
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viv_check_retval(copy_from_user(&addr, args, sizeof(addr)));
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ret = dwe_start_dma_read(dev, &dev->info[0][0], addr);
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#endif
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break;
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}
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case DWEIOC_SET_BUFFER: {
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#ifndef ENABLE_IRQ
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u64 addr;
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viv_check_retval(copy_from_user(&addr, args, sizeof(addr)));
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ret = dwe_set_buffer(dev, &dev->info[0][0], addr);
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#endif
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break;
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}
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case DWEIOC_SET_LUT: {
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struct lut_info info;
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viv_check_retval(copy_from_user(&info, args, sizeof(info)));
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#ifndef ENABLE_IRQ
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ret = dwe_set_lut(dev, info.addr);
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#endif
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break;
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}
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#ifdef __KERNEL__
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case VIDIOC_QUERYCAP:
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ret = dwe_ioc_qcap(dev, args);
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break;
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#endif
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default:
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pr_err("unsupported dwe command %d", cmd);
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break;
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}
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return ret;
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}
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