mirror of
https://github.com/thead-yocto-mirror/vi-kernel
synced 2026-06-21 17:02:34 +02:00
194 lines
7.4 KiB
C
Executable File
194 lines
7.4 KiB
C
Executable File
/****************************************************************************
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*****************************************************************************
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*
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* The GPL License (GPL)
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*
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* Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program;
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*
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*****************************************************************************
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*
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* Note: This software is released under dual MIT and GPL licenses. A
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* recipient may use this file under the terms of either the MIT license or
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* GPL License. If you wish to use only one license not the other, you can
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* indicate your decision by deleting one of the above license notices in your
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* version of this file.
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*
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*****************************************************************************/
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#ifdef __KERNEL__
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#include <linux/io.h>
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#include <linux/module.h>
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#else
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#endif
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#include "mrv_all_bits.h"
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#include "isp_ioctl.h"
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#include "isp_types.h"
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extern MrvAllRegister_t *all_regs;
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int isp_s_dpf(struct isp_ic_dev *dev)
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{
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struct isp_dpf_context *dpf = &dev->dpf;
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u32 value;
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int i = 0;
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u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
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u32 isp_dpf_mode = isp_read_reg(dev, REG_ADDR(isp_dpf_mode));
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//pr_info("enter %s\n", __func__);
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if (!dpf->enable) {
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isp_write_reg(dev, REG_ADDR(isp_dpf_mode),
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isp_dpf_mode & ~MRV_DPF_DPF_ENABLE_MASK);
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return 0;
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}
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isp_dpf_mode &=
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(MRV_DPF_DPF_ENABLE_MASK | MRV_DPF_NLL_SEGMENTATION_MASK);
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switch (dpf->gain_usage) {
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case IC_DPF_GAIN_USAGE_DISABLED:
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 0);
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break;
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case IC_DPF_GAIN_USAGE_NF_GAINS:
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 1);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1);
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break;
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case IC_DPF_GAIN_USAGE_LSC_GAINS:
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 0);
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break;
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case IC_DPF_GAIN_USAGE_NF_LSC_GAINS:
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 1);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1);
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break;
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case IC_DPF_GAIN_USAGE_AWB_GAINS:
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1);
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break;
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case IC_DPF_GAIN_USAGE_AWB_LSC_GAINS:
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1);
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break;
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default:
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/*pr_err("%s: unsupported gain usage\n", __func__);*/
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break;
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}
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switch (dpf->filter_type) {
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case IC_DPF_RB_FILTERSIZE_13x9:
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_RB_FILTER_SIZE, 0U);
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break;
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case IC_DPF_RB_FILTERSIZE_9x9:
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_RB_FILTER_SIZE, 1U);
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break;
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default:
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/*pr_err
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("%s: unsupported filter kernel size for red/blue pixel\n",
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__func__);*/
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break;
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}
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_R_FILTER_OFF, dpf->filter_r_off);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_GR_FILTER_OFF, dpf->filter_gr_off);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_GB_FILTER_OFF, dpf->filter_gb_off);
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_B_FILTER_OFF, dpf->filter_b_off);
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value = 0;
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G1, dpf->weight_g[0]);
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G2, dpf->weight_g[1]);
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G3, dpf->weight_g[2]);
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G4, dpf->weight_g[3]);
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isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_g_1_4), value);
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value = 0;
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G5, dpf->weight_g[4]);
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G6, dpf->weight_g[5]);
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isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_g_5_6), value);
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value = 0;
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB1, dpf->weight_rb[0]);
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB2, dpf->weight_rb[1]);
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB3, dpf->weight_rb[2]);
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB4, dpf->weight_rb[3]);
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isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_rb_1_4), value);
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value = 0;
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB5, dpf->weight_rb[4]);
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REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB6, dpf->weight_rb[5]);
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isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_rb_5_6), value);
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isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_r), dpf->nf_gain_r);
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isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_gr), dpf->nf_gain_gr);
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isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_gb), dpf->nf_gain_gb);
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isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_b), dpf->nf_gain_b);
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isp_write_reg(dev, REG_ADDR(isp_dpf_strength_r),
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(MRV_DPF_INV_WEIGHT_R_MASK & dpf->strength_r));
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isp_write_reg(dev, REG_ADDR(isp_dpf_strength_g),
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(MRV_DPF_INV_WEIGHT_G_MASK & dpf->strength_g));
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isp_write_reg(dev, REG_ADDR(isp_dpf_strength_b),
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(MRV_DPF_INV_WEIGHT_B_MASK & dpf->strength_b));
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for (i = 0; i < 17; i++) {
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if (dpf->denoise_talbe[i] <= MRV_DPF_NLL_COEFF_N_MASK) {
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isp_write_reg(dev,
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REG_ADDR(nlf_lookup_table_block_arr[i]),
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dpf->denoise_talbe[i]);
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}
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}
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switch (dpf->x_scale) {
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case IC_NLL_SCALE_LINEAR:
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_NLL_SEGMENTATION, 0);
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break;
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case IC_NLL_SCALE_LOGARITHMIC:
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REG_SET_SLICE(isp_dpf_mode, MRV_DPF_NLL_SEGMENTATION, 1);
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break;
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default:
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break;
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}
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isp_write_reg(dev, REG_ADDR(isp_dpf_mode), isp_dpf_mode);
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isp_write_reg(dev, REG_ADDR(isp_dpf_mode),
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isp_dpf_mode | MRV_DPF_DPF_ENABLE_MASK);
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REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
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isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
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return 0;
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}
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