mirror of
https://github.com/thead-yocto-mirror/vi-kernel
synced 2026-06-21 17:02:34 +02:00
280 lines
7.8 KiB
C
Executable File
280 lines
7.8 KiB
C
Executable File
/****************************************************************************
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*****************************************************************************
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*
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* The GPL License (GPL)
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*
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* Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program;
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*
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*****************************************************************************
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*
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* Note: This software is released under dual MIT and GPL licenses. A
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* recipient may use this file under the terms of either the MIT license or
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* GPL License. If you wish to use only one license not the other, you can
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* indicate your decision by deleting one of the above license notices in your
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* version of this file.
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*
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*****************************************************************************/
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#ifdef ENABLE_IRQ
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#include "isp_ioctl.h"
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#include "isp_types.h"
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#include "mrv_all_bits.h"
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#include "video/vvbuf.h"
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extern MrvAllRegister_t *all_regs;
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#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG
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static int config_dma_buf(struct isp_mi_data_path_context *path,
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dma_addr_t dma, struct isp_buffer_context *buf)
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{
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u32 size = path->out_width * path->out_height;
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buf->addr_y = dma;
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switch (path->out_mode) {
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case IC_MI_DATAMODE_YUV444:
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case IC_MI_DATAMODE_YUV422:
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case IC_MI_DATAMODE_YUV420:
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if (path->data_layout == IC_MI_DATASTORAGE_PLANAR) {
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buf->size_y = size + ISP_BUF_GAP;
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buf->addr_cb = buf->addr_y + size;
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buf->size_cb = size + ISP_BUF_GAP;
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buf->addr_cr = buf->addr_cb + size;
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buf->size_cr = size + ISP_BUF_GAP;
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} else if (path->data_layout ==
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IC_MI_DATASTORAGE_SEMIPLANAR) {
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buf->size_y = size + ISP_BUF_GAP;
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buf->addr_cb = buf->addr_y + size;
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if (path->out_mode == IC_MI_DATAMODE_YUV420)
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buf->size_cb = (size >> 1) + ISP_BUF_GAP;
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else
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buf->size_cb = size + ISP_BUF_GAP;
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} else if (path->data_layout ==
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IC_MI_DATASTORAGE_INTERLEAVED) {
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buf->size_y = (size << 1) + ISP_BUF_GAP;
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} else
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return -1;
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break;
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case IC_MI_DATAMODE_RAW8:
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buf->size_y = size + ISP_BUF_GAP;
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break;
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case IC_MI_DATAMODE_RAW10:
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case IC_MI_DATAMODE_RAW12:
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buf->size_y = (size << 1) + ISP_BUF_GAP;
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break;
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default:
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pr_err("unsupported out mode:%d\n", path->out_mode);
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return -1;
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}
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#ifdef ISP_MP_34BIT
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buf->addr_y >>= 2;
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buf->addr_cb >>= 2;
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buf->addr_cr >>= 2;
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#endif
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return 0;
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}
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#endif
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static int update_dma_buffer(struct isp_ic_dev *dev)
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{
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#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG
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struct isp_mi_context *mi = &dev->mi;
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struct vb2_dc_buf *buf = NULL;
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struct isp_buffer_context dmabuf;
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int i,dequeued;
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for (i = 0; i < MI_PATH_NUM; ++i) {
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if (!mi->path[i].enable)
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continue;
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if (dev->mi_buf[i]) {
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vvbuf_ready(dev->bctx, dev->mi_buf[i]->pad,
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dev->mi_buf[i]);
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dev->mi_buf[i] = NULL;
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}
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if (dev->state && !(*dev->state & STATE_DRIVER_STARTED))
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continue;
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dequeued = 1;
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buf = vvbuf_try_dqbuf(dev->bctx);
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if (!buf) {
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buf = dev->mi_buf_shd[i];
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if (!buf)
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return -ENOMEM;
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dev->mi_buf_shd[i] = NULL;
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dequeued = 0;
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} else if (dev->mi_buf_shd[i]) {
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dev->mi_buf[i] = dev->mi_buf_shd[i];
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dev->mi_buf_shd[i] = NULL;
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}
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memset(&dmabuf, 0, sizeof(dmabuf));
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dmabuf.path = i;
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if (config_dma_buf(&mi->path[i], buf->dma, &dmabuf))
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continue;
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isp_set_buffer(dev, &dmabuf);
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dev->mi_buf_shd[i] = buf;
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if (dequeued)
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vvbuf_try_dqbuf_done(dev->bctx, buf);
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}
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#endif
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return 0;
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}
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int clean_dma_buffer(struct isp_ic_dev *dev)
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{
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#ifdef CONFIG_VIDEOBUF2_DMA_CONTIG
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int i;
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if (!dev->free)
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return 0;
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dev->free(dev, NULL);
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for (i = 0; i < MI_PATH_NUM; ++i) {
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if (dev->mi_buf[i]) {
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dev->free(dev, dev->mi_buf[i]);
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dev->mi_buf[i] = NULL;
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}
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if (dev->mi_buf_shd[i]) {
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dev->free(dev, dev->mi_buf_shd[i]);
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dev->mi_buf_shd[i] = NULL;
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}
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}
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#endif
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return 0;
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}
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void isp_clear_interrupts(struct isp_ic_dev *dev)
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{
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u32 isp_mis, mi_mis;
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isp_mis = isp_read_reg(dev, REG_ADDR(isp_mis));
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isp_write_reg(dev, REG_ADDR(isp_icr), isp_mis);
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#ifdef ISP_MIV1
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mi_mis = isp_read_reg(dev, REG_ADDR(mi_mis));
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isp_write_reg(dev, REG_ADDR(mi_icr), mi_mis);
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#elif defined(ISP_MIV2)
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mi_mis = isp_read_reg(dev, REG_ADDR(miv2_mis));
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isp_write_reg(dev, REG_ADDR(miv2_icr), mi_mis);
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#else
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mi_mis = 0;
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#endif
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}
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irqreturn_t isp_hw_isr(int irq, void *data)
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{
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struct isp_ic_dev *dev = (struct isp_ic_dev *)data;
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static const u32 frameendmask = MRV_MI_MP_FRAME_END_MASK |
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#ifdef ISP_MI_BP
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MRV_MI_BP_FRAME_END_MASK |
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#endif
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MRV_MI_SP_FRAME_END_MASK;
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static const u32 errormask = MRV_MI_WRAP_MP_Y_MASK |
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MRV_MI_WRAP_MP_CB_MASK |
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MRV_MI_WRAP_MP_CR_MASK |
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#ifdef ISP_MI_BP
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MRV_MI_BP_WRAP_R_MASK |
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MRV_MI_BP_WRAP_GR_MASK |
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MRV_MI_BP_WRAP_GB_MASK |
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MRV_MI_BP_WRAP_B_MASK |
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#endif
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MRV_MI_WRAP_SP_Y_MASK |
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MRV_MI_WRAP_SP_CB_MASK |
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MRV_MI_WRAP_SP_CR_MASK |
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MRV_MI_FILL_MP_Y_MASK;
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static const u32 fifofullmask = MRV_MI_MP_Y_FIFO_FULL_MASK |
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MRV_MI_MP_CB_FIFO_FULL_MASK |
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MRV_MI_MP_CR_FIFO_FULL_MASK |
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MRV_MI_SP_Y_FIFO_FULL_MASK |
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MRV_MI_SP_CB_FIFO_FULL_MASK |
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MRV_MI_SP_CR_FIFO_FULL_MASK;
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u32 isp_mis, mi_mis, mi_status;
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struct isp_irq_data irq_data;
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int rc = 0;
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if (!dev)
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return IRQ_HANDLED;
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isp_mis = isp_read_reg(dev, REG_ADDR(isp_mis));
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isp_write_reg(dev, REG_ADDR(isp_icr), isp_mis);
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#ifdef ISP_MIV1
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mi_mis = isp_read_reg(dev, REG_ADDR(mi_mis));
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isp_write_reg(dev, REG_ADDR(mi_icr), mi_mis);
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#elif defined(ISP_MIV2)
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mi_mis = isp_read_reg(dev, REG_ADDR(miv2_mis));
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isp_write_reg(dev, REG_ADDR(miv2_icr), mi_mis);
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#else
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mi_mis = 0;
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#endif
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mi_status = isp_read_reg(dev, REG_ADDR(mi_status));
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if (mi_status & fifofullmask) {
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isp_write_reg(dev, REG_ADDR(mi_status), mi_status);
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pr_debug("MI FIFO full: 0x%x\n", mi_status);
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}
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if (mi_mis & errormask)
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pr_debug("MI mis error: 0x%x\n", mi_mis);
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if (mi_mis & frameendmask)
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rc = update_dma_buffer(dev);
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if (isp_mis) {
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if(isp_mis & MRV_ISP_MIS_FRAME_MASK) {
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if (dev->isp_update_flag & ISP_FLT_UPDATE) {
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isp_s_flt(dev);
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dev->isp_update_flag &= (~ISP_FLT_UPDATE);
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}
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if (dev->gamma_out.changed) {
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isp_s_gamma_out(dev);
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}
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}
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memset(&irq_data, 0, sizeof(irq_data));
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irq_data.val = isp_mis;
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if (dev->post_event)
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dev->post_event(dev, &irq_data, sizeof(irq_data));
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}
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return IRQ_HANDLED;
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}
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#endif
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