mirror of
https://github.com/thead-yocto-mirror/vi-kernel
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456 lines
16 KiB
C
Executable File
456 lines
16 KiB
C
Executable File
/****************************************************************************
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*****************************************************************************
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*
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* The GPL License (GPL)
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*
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* Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program;
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*
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*****************************************************************************
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*
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* Note: This software is released under dual MIT and GPL licenses. A
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* recipient may use this file under the terms of either the MIT license or
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* GPL License. If you wish to use only one license not the other, you can
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* indicate your decision by deleting one of the above license notices in your
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* version of this file.
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*
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*****************************************************************************/
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#ifdef __KERNEL__
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#include <linux/io.h>
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#include <linux/module.h>
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#endif
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#include "isp_ioctl.h"
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#include "mrv_all_bits.h"
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#include "isp_types.h"
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#ifdef ISP_3DNR
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extern MrvAllRegister_t *all_regs;
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static void dnr3_hw_init(struct isp_ic_dev *dev)
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{
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struct isp_3dnr_context *dnr3 = &dev->dnr3;
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u32 regVal = 0;
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int i, pos;
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/* spacial */
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u32 update_spacial = 900;
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u32 strength_curve_spacial = 64;
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u32 thr_edge_v_inv = 1024;
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u32 thr_edge_h_inv = 1024;
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u32 thr_range_s_inv = 1024;
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/* temperal */
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u32 update_temperal = 1020;
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u32 strength_curve_temperal = 64;
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u32 range_t_h = 2;
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u32 range_t_v = 2;
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u32 thr_range_t_inv = 41943;
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u32 thr_motion_inv = 1024;
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u32 range_d = 1;
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u32 thr_delta_h_inv = 1023;
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u32 thr_delta_v_inv = 1023;
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u32 thr_delta_t_inv = 1023;
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u32 strength = dnr3->strength;
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strength = MIN(MAX(strength, 0), 128);
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if (dnr3->init) { //for 3dnr init
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u32 isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl));
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REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_HORIZONTAL_EN,
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dnr3->enable_h);
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REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_VERTICAL_EN,
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dnr3->enable_v);
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REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_TEMPERAL_EN,
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dnr3->enable_temperal);
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REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_DILATE_EN,
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dnr3->enable_dilate);
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REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl);
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}
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regVal = 0;
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REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_SPACIAL,
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strength_curve_spacial);
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REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, thr_edge_h_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal);
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regVal = 0;
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REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_TEMPERAL,
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strength_curve_temperal);
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REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, thr_edge_v_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal);
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regVal = 0;
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REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, thr_range_s_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal);
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regVal = 0;
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REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, range_t_h);
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REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, range_t_v);
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REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, thr_range_t_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal);
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regVal = 0;
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REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, range_d);
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REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, thr_motion_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal);
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regVal = 0;
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REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, thr_delta_h_inv);
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REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, thr_delta_v_inv);
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REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, thr_delta_t_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal);
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/* spacial */
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for (i = 0; i < 6; i++) {
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regVal = 0;
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pos = i * 3;
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if (i < 5) {
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REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE0,
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dnr3->spacial_curve[pos + 0]);
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REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1,
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dnr3->spacial_curve[pos + 1]);
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REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2,
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dnr3->spacial_curve[pos + 2]);
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} else {
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REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1,
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dnr3->spacial_curve[pos + 0]);
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REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2,
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dnr3->spacial_curve[pos + 1]);
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}
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_s[i]), regVal);
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regVal = 0;
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if (i < 5) {
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REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE0,
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dnr3->temperal_curve[pos + 0]);
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REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1,
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dnr3->temperal_curve[pos + 1]);
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REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2,
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dnr3->temperal_curve[pos + 2]);
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} else {
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REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1,
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dnr3->temperal_curve[pos + 0]);
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REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2,
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dnr3->temperal_curve[pos + 1]);
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}
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_t[i]), regVal);
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}
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regVal = 0;
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REG_SET_SLICE(regVal, DENOISE3D_UPDATE_SPACIAL, update_spacial);
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REG_SET_SLICE(regVal, DENOISE3D_UPDATE_TEMPERAL, update_temperal);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_dummy_hblank), 0x80);
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}
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int isp_u_3dnr_strength(struct isp_ic_dev *dev)
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{
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#ifndef ISP_3DNR
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//pr_err("Not supported 3dnr\n");
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return -1;
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#else
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struct isp_3dnr_context *dnr3 = &dev->dnr3;
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u32 isp_ctrl;
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u32 isp_denoise3d_strength;
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isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength));
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REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength);
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isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
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REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
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isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
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return 0;
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#endif
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}
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int isp_s_3dnr(struct isp_ic_dev *dev)
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{
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#ifndef ISP_3DNR
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//pr_err("Not supported 3dnr\n");
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return -1;
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#else
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u32 isp_denoise3d_ctrl;
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struct isp_3dnr_context *dnr3 = &dev->dnr3;
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u32 isp_denoise3d_strength, isp_denoise3d_motion, isp_denoise3d_delta_inv;
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pr_info("enter %s\n", __func__);
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if (dnr3->update_bin) {
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dnr3_hw_init(dev);
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}
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isp_denoise3d_motion =
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isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion));
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REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion),
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isp_denoise3d_motion);
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isp_denoise3d_delta_inv =
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isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv));
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REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv),
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isp_denoise3d_delta_inv);
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isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength));
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#ifndef NR200
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if (!dnr3->enable) {
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REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, 0);
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} else {
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REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength);
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isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl));
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REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl);
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}
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength);
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#else
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isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl));
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REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl);
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u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
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REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
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isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
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#endif
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return 0;
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#endif
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}
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int isp_s_3dnr_motion(struct isp_ic_dev *dev)
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{
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#ifndef ISP_3DNR
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pr_err("Not supported 3dnr\n");
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return -1;
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#else
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struct isp_3dnr_context *dnr3 = &dev->dnr3;
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u32 isp_denoise3d_motion;
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u32 isp_ctrl;
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isp_denoise3d_motion =
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isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion));
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REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion),
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isp_denoise3d_motion);
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isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
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REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
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isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
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#endif
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return 0;
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}
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int isp_s_3dnr_delta(struct isp_ic_dev *dev)
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{
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#ifndef ISP_3DNR
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pr_err("Not supported 3dnr\n");
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return -1;
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#else
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struct isp_3dnr_context *dnr3 = &dev->dnr3;
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u32 isp_denoise3d_delta_inv;
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u32 isp_ctrl;
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isp_denoise3d_delta_inv =
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isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv));
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REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv),
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isp_denoise3d_delta_inv);
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isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
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REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
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isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
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#endif
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return 0;
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}
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int isp_u_3dnr(struct isp_ic_dev *dev, struct isp_3dnr_update *dnr3_update)
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{
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#ifndef ISP_3DNR
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pr_err("unsupported function: %s", __func__);
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return -EINVAL;
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#else
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u32 regVal = 0;
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pr_info("enter %s\n", __func__);
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regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength));
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REG_SET_SLICE(regVal, DENOISE3D_STRENGTH, dev->dnr3.strength);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal);
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regVal = 0;
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regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_h));
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REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV,
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dnr3_update->thr_edge_h_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal);
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regVal = 0;
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regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_v));
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REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV,
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dnr3_update->thr_edge_v_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal);
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regVal = 0;
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regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_s));
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REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV,
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dnr3_update->thr_range_s_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal);
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regVal = 0;
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regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_t));
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REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, dnr3_update->range_t_h);
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REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, dnr3_update->range_t_v);
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REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV,
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dnr3_update->thr_range_t_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal);
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regVal = 0;
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regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion));
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REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, dnr3_update->range_d);
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REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV,
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dnr3_update->thr_motion_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal);
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regVal = 0;
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regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv));
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REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV,
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dnr3_update->thr_delta_h_inv);
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REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV,
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dnr3_update->thr_delta_v_inv);
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REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV,
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dnr3_update->thr_delta_t_inv);
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isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal);
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#ifdef NR200
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u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
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REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
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isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
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#endif
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return 0;
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#endif
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}
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int isp_g_3dnr(struct isp_ic_dev *dev, u32 * avg)
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{
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if (!dev || !avg) {
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return -EINVAL;
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}
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*avg = isp_read_reg(dev, REG_ADDR(isp_denoise3d_average));
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return 0;
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}
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int isp_r_3dnr(struct isp_ic_dev *dev)
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{
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#ifndef ISP_3DNR
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return -1;
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#else
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u32 in_width, in_height;
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u32 size, lval;
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u32 miv2_sp2_bus_id;
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u32 miv2_sp2_fmt;
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u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
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u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc));
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u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl));
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//SP2_RAW_PATH_ENABLE is shadow bit, need set SP2_MI_CFG_UPD to update to shadow.
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//So here config before set SP2_MI_CFG_UPD
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REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1);
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REG_SET_SLICE(miv2_ctrl, SP2_RAW_PATH_ENABLE, 1);
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isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
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#ifndef NR200
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in_width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size));
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in_height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size));
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#else
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in_width = isp_read_reg(dev, REG_ADDR(isp_out_h_size));
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in_height = isp_read_reg(dev, REG_ADDR(isp_out_v_size));
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#endif
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lval = (in_width * 12 + 127)/ 128;
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lval <<= 4;
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size = in_height * lval; //raw12 unaligned
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//write reference frame config
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isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_base_ad_init), dev->dnr3.pa);
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isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_size_init), size);
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isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_offs_cnt_init), 0);
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isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_llength), lval);
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isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_width), in_width);
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isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_height), in_height);
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isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_size), size);
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miv2_sp2_bus_id = isp_read_reg(dev, REG_ADDR(miv2_sp2_bus_id));
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REG_SET_SLICE(miv2_sp2_bus_id, SP2_WR_ID_EN, 1);
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REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_ID_EN, 1);
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REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_BURST_LEN, 2); //sp2 rd burst lenghth 16
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REG_SET_SLICE(miv2_sp2_bus_id, SP2_BUS_SW_EN, 1);
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isp_write_reg(dev, REG_ADDR(miv2_sp2_bus_id), miv2_sp2_bus_id);
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|
|
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miv2_sp2_fmt = isp_read_reg(dev, REG_ADDR(miv2_sp2_fmt));
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REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_BIT, 2); //raw12
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REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_ALIGNED, 0); //unaligned
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|
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REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_BIT, 2); //raw12
|
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REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_ALIGNED, 0); //unaligned
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isp_write_reg(dev, REG_ADDR(miv2_sp2_fmt), miv2_sp2_fmt);
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|
|
|
//read reference frame config
|
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isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), dev->dnr3.pa);
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isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_width), in_width);
|
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isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_llength), lval);
|
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isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_lval), lval);
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|
isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_size), size);
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|
|
|
|
|
REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1);
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|
REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1);
|
|
REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1);
|
|
|
|
/* we successfully programmed a buffer to marvin, so we need
|
|
* to enable updateing of base and offset registers */
|
|
miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK);
|
|
isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl);
|
|
|
|
miv2_imsc |= SP2_DMA_RAW_READY_MASK;
|
|
isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc);
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|
|
|
return 0;
|
|
#endif
|
|
}
|
|
#endif
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