mirror of
https://github.com/thead-yocto-mirror/vi-kernel
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428 lines
16 KiB
C
Executable File
428 lines
16 KiB
C
Executable File
/****************************************************************************
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*****************************************************************************
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*
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* The GPL License (GPL)
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*
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* Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program;
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*
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*****************************************************************************
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*
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* Note: This software is released under dual MIT and GPL licenses. A
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* recipient may use this file under the terms of either the MIT license or
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* GPL License. If you wish to use only one license not the other, you can
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* indicate your decision by deleting one of the above license notices in your
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* version of this file.
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*
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*****************************************************************************/
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#ifdef __KERNEL__
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#include <linux/io.h>
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#include <linux/module.h>
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#endif
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#include "mrv_all_bits.h"
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#include "isp_ioctl.h"
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#include "isp_types.h"
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extern MrvAllRegister_t *all_regs;
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#ifdef ISP_DEMOSAIC2_RY
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int isp_enable_dmsc(struct isp_ic_dev *dev)
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{
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u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
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u32 isp_dmsc_size_ctrl =
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isp_read_reg(dev, REG_ADDR(isp_dmsc_size_ctrl));
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isp_info("enter %s\n", __func__);
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REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_BYPASS, 0U);
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REG_SET_SLICE(isp_dmsc_size_ctrl, ISP_DMSC_IMAGE_H_SIZE,
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isp_read_reg(dev, REG_ADDR(isp_acq_h_size)));
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REG_SET_SLICE(isp_dmsc_size_ctrl, ISP_DMSC_IMAGE_H_BLANK, 0x039c);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_size_ctrl), isp_dmsc_size_ctrl);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl_shd), isp_dmsc_ctrl);
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return 0;
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}
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int isp_disable_dmsc(struct isp_ic_dev *dev)
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{
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u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
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isp_dmsc_ctrl = 0; //clear fpga default bit 3 and 13 to keep the same value with cmodel.
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isp_info("enter %s\n", __func__);
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REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_BYPASS, 1U);
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/*clear the reg default val to keep weith cmodel */
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_fact), 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_clip), 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt2), 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl), 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb), 0);
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//isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_a), 0);
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//isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_c), 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl), 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr), 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr), 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y), 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
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return 0;
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}
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int isp_set_dmsc_intp(struct isp_ic_dev *dev)
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{
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u32 isp_dmsc_intp_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_intp_thr));
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isp_info("enter %s\n", __func__);
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REG_SET_SLICE(isp_dmsc_intp_thr, ISP_DMSC_INTERPLATION_DIR_THR_MAX,
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dev->demosaic.intp.intp_dir_thr_max);
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REG_SET_SLICE(isp_dmsc_intp_thr, ISP_DMSC_INTERPLATION_DIR_THR_MIN,
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dev->demosaic.intp.intp_dir_thr_min);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_intp_thr), isp_dmsc_intp_thr);
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return 0;
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}
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int isp_set_dmsc_dmoi(struct isp_ic_dev *dev)
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{
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struct isp_dmoi_context *pDemoire = &dev->demosaic.demoire;
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u32 isp_dmsc_dmoi_ctrl =
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isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl));
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u32 isp_dmsc_dmoi_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr));
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u32 isp_dmsc_dmoi_patn_thr =
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isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_patn_thr));
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u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
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isp_info("enter %s\n", __func__);
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if (!pDemoire->enable) {
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REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEMOIRE_ENABLE, 0U);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
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return 0;
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}
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REG_SET_SLICE(isp_dmsc_dmoi_ctrl, ISP_DMSC_DEMOIRE_AREA_THR,
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pDemoire->demoire_area_thr);
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REG_SET_SLICE(isp_dmsc_dmoi_ctrl, ISP_DMSC_DEMOIRE_SAT_SHRINK,
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pDemoire->demoire_sat_shrink);
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REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_R2,
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pDemoire->demoire_r2);
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REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_R1,
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pDemoire->demoire_r1);
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REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_T2_SHIFT,
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pDemoire->demoire_t2_shift);
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REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_T1,
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pDemoire->demoire_t1);
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REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_R2,
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pDemoire->demoire_edge_r2);
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REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_R1,
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pDemoire->demoire_edge_r1);
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REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT,
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pDemoire->demoire_edge_t2_shift);
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REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_T1,
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pDemoire->demoire_edge_t1);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl), isp_dmsc_dmoi_ctrl);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr), isp_dmsc_dmoi_thr);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_patn_thr),
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isp_dmsc_dmoi_patn_thr);
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REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEMOIRE_ENABLE, 1U);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
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return 0;
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}
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int isp_set_dmsc_sharpen(struct isp_ic_dev *dev)
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{
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struct isp_shap_context *pSharpen = &dev->demosaic.sharpen;
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u32 isp_dmsc_shap_fact =
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isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_fact));
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u32 isp_dmsc_shap_clip =
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isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_clip));
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u32 isp_dmsc_shap_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_thr));
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u32 isp_dmsc_shap_ratio =
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isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_ratio));
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u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
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isp_info("enter %s\n", __func__);
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if (!pSharpen->enable) {
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REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_ENBALE, 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl_shd), isp_dmsc_ctrl);
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return 0;
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}
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REG_SET_SLICE(isp_dmsc_shap_fact, ISP_DMSC_SHARPEN_FACTOR_BLACK,
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pSharpen->sharpen_factor_black);
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REG_SET_SLICE(isp_dmsc_shap_fact, ISP_DMSC_SHARPEN_FACTOR_WHITE,
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pSharpen->sharpen_factor_white);
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REG_SET_SLICE(isp_dmsc_shap_clip, ISP_DMSC_SHARPEN_CLIP_BLACK,
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pSharpen->sharpen_clip_black);
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REG_SET_SLICE(isp_dmsc_shap_clip, ISP_DMSC_SHARPEN_CLIP_WHITE,
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pSharpen->sharpen_clip_white);
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REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T4_SHIFT,
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pSharpen->sharpen_t4_shift);
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REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T3,
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pSharpen->sharpen_t3);
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REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T2_SHIFT,
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pSharpen->sharpen_t2_shift);
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REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T1,
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pSharpen->sharpen_t1);
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REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R3,
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pSharpen->sharpen_r3);
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REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R2,
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pSharpen->sharpen_r2);
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REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R1,
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pSharpen->sharpen_r1);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_fact), isp_dmsc_shap_fact);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_clip), isp_dmsc_shap_clip);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_thr), isp_dmsc_shap_thr);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_ratio), isp_dmsc_shap_ratio);
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REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_ENBALE, 1);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
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return 0;
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}
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int isp_set_dmsc_gfilter(struct isp_ic_dev *dev)
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{
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struct isp_gfilter_context *pgfilter = &dev->demosaic.gFilter;
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u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
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u32 isp_dmsc_shap_filt1 =
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isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_filt1));
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u32 isp_dmsc_shap_filt2 =
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isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_filt2));
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isp_info("enter %s\n", __func__);
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REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_00,
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pgfilter->hf_filt_00);
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REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_01,
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pgfilter->hf_filt_01);
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REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_02,
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pgfilter->hf_filt_02);
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REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_10,
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pgfilter->hf_filt_10);
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REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_11,
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pgfilter->hf_filt_11);
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REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_12,
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pgfilter->hf_filt_12);
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REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_20,
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pgfilter->hf_filt_20);
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REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_21,
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pgfilter->hf_filt_21);
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REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_22,
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pgfilter->hf_filt_22);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt1), isp_dmsc_shap_filt1);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt2), isp_dmsc_shap_filt2);
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REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_SIZE, pgfilter->sharpen_size);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
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return 0;
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}
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int isp_set_dmsc_sharpen_line(struct isp_ic_dev *dev)
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{
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struct isp_shap_line_context *sharpenLine = &dev->demosaic.sharpenLine;
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u32 isp_dmsc_shap_line_ctrl =
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isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_line_ctrl));
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u32 isp_dmsc_shap_line_ratio =
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isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_line_ratio));
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u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
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isp_info("enter %s\n", __func__);
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if (!sharpenLine->enable) {
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REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_LINE_ENABLE, 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
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return 0;
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}
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REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_SHIFT2,
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sharpenLine->sharpen_line_shift2);
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REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_SHIFT1,
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sharpenLine->sharpen_line_shift1);
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REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_T1,
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sharpenLine->sharpen_line_t1);
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REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_STRENGTH,
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sharpenLine->sharpen_line_strength);
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REG_SET_SLICE(isp_dmsc_shap_line_ratio, ISP_DMSC_SHARPEN_LINE_R2,
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sharpenLine->sharpen_line_r2);
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REG_SET_SLICE(isp_dmsc_shap_line_ratio, ISP_DMSC_SHARPEN_LINE_R1,
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sharpenLine->sharpen_line_r1);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_line_ctrl),
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isp_dmsc_shap_line_ctrl);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_line_ratio),
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isp_dmsc_shap_line_ratio);
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REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_LINE_ENABLE, 1);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
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return 0;
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}
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int isp_set_dmsc_cac(struct isp_ic_dev *dev)
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{
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struct isp_cac_context *cac = &dev->cac;
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u32 val = 0;
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u32 isp_dmsc_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl));
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isp_info("enter %s\n", __func__);
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if (!cac->enable) {
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REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_CAC_EN, 0);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl),
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isp_dmsc_cac_ctrl);
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return 0;
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}
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REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode);
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REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_count_start),
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cac->hstart | (cac->vstart << 16));
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isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_a), cac->ar | (cac->ab << 16));
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isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_b), cac->br | (cac->bb << 16));
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isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_c), cac->cr | (cac->cb << 16));
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REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns);
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REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_x_norm), val);
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val = 0;
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REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns);
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REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_y_norm), val);
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REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_CAC_EN, 1);
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isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl), isp_dmsc_cac_ctrl);
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return 0;
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|
}
|
|
|
|
int isp_set_dmsc_depurple(struct isp_ic_dev *dev)
|
|
{
|
|
struct isp_depurple_context *depurple = &dev->demosaic.depurple;
|
|
u32 isp_dmsc_dpul_ctrl =
|
|
isp_read_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl));
|
|
u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
|
|
|
|
isp_info("enter %s\n", __func__);
|
|
if (!depurple->enable) {
|
|
REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEPURPLE_ENABLE, 0U);
|
|
isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
|
|
return 0;
|
|
}
|
|
|
|
REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_RED_SAT, depurple->red_sat);
|
|
REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_BLUE_SAT, depurple->blue_sat);
|
|
REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_SAT_SHRINK,
|
|
depurple->depurple_sat_shrink);
|
|
REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_THR,
|
|
depurple->depurple_thr);
|
|
isp_write_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl), isp_dmsc_dpul_ctrl);
|
|
REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEPURPLE_ENABLE, 1U);
|
|
isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int isp_set_dmsc_skin(struct isp_ic_dev *dev)
|
|
{
|
|
struct isp_skin_context *skin = &dev->demosaic.skin;
|
|
u32 isp_dmsc_skin_thr_cb =
|
|
isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb));
|
|
u32 isp_dmsc_skin_thr_cr =
|
|
isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr));
|
|
u32 isp_dmsc_skin_thr_y =
|
|
isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y));
|
|
|
|
u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
|
|
|
|
isp_info("enter %s\n", __func__);
|
|
if (!skin->enable) {
|
|
REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SKIN_ENABLE, 0U);
|
|
isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
|
|
return 0;
|
|
}
|
|
|
|
REG_SET_SLICE(isp_dmsc_skin_thr_cb, ISP_DMSC_SKIN_CB_THR_MAX_2047,
|
|
skin->cb_thr_max_2047);
|
|
REG_SET_SLICE(isp_dmsc_skin_thr_cb, ISP_DMSC_SKIN_CB_THR_MIN_2047,
|
|
skin->cb_thr_min_2047);
|
|
REG_SET_SLICE(isp_dmsc_skin_thr_cr, ISP_DMSC_SKIN_CR_THR_MAX_2047,
|
|
skin->cr_thr_max_2047);
|
|
REG_SET_SLICE(isp_dmsc_skin_thr_cr, ISP_DMSC_SKIN_CR_THR_MIN_2047,
|
|
skin->cr_thr_min_2047);
|
|
REG_SET_SLICE(isp_dmsc_skin_thr_y, ISP_DMSC_SKIN_Y_THR_MAX,
|
|
skin->y_thr_max_2047);
|
|
REG_SET_SLICE(isp_dmsc_skin_thr_y, ISP_DMSC_SKIN_Y_THR_MIN,
|
|
skin->y_thr_min_2047);
|
|
|
|
isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb),
|
|
isp_dmsc_skin_thr_cb);
|
|
isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr),
|
|
isp_dmsc_skin_thr_cr);
|
|
isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y), isp_dmsc_skin_thr_y);
|
|
REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SKIN_ENABLE, 1U);
|
|
isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int isp_s_dmsc(struct isp_ic_dev *dev)
|
|
{
|
|
u32 isp_dmsc_ctrl;
|
|
/*Clear the cmodel register default value to match the fpga default value */
|
|
isp_disable_dmsc(dev);
|
|
|
|
isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
|
|
isp_info("enter %s\n", __func__);
|
|
if (!dev->demosaic.enable) {
|
|
isp_disable_dmsc(dev);
|
|
return 0;
|
|
}
|
|
REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_THR,
|
|
dev->demosaic.demosaic_thr);
|
|
REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DENOISE_STRENGTH,
|
|
dev->demosaic.denoise_stren);
|
|
isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
|
|
|
|
isp_set_dmsc_intp(dev);
|
|
isp_enable_dmsc(dev);
|
|
isp_set_dmsc_gfilter(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif
|