mirror of
https://github.com/thead-yocto-mirror/xtensa_dsp
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151 lines
4.1 KiB
C
151 lines
4.1 KiB
C
/*
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* Data structures and constants for generic XRP interface between
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* linux and DSP
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*
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* Copyright (c) 2015 - 2019 Cadence Design Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Alternatively you can use and distribute this file under the terms of
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* the GNU General Public License version 2 or later.
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*/
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#ifndef _XRP_KERNEL_DSP_INTERFACE_H
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#define _XRP_KERNEL_DSP_INTERFACE_H
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#ifndef XRP_DSP_COMM_BASE_MAGIC
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#define XRP_DSP_COMM_BASE_MAGIC 0x20161006
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#endif
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enum {
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XRP_DSP_SYNC_IDLE = 0,
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XRP_DSP_SYNC_HOST_TO_DSP = 0x1,
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XRP_DSP_SYNC_DSP_TO_HOST = 0x3,
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XRP_DSP_SYNC_START = 0x101,
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XRP_DSP_SYNC_DSP_READY_V1 = 0x203,
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XRP_DSP_SYNC_DSP_READY_V2 = 0x303,
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};
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enum {
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XRP_DSP_SYNC_TYPE_ACCEPT = 0x80000000,
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XRP_DSP_SYNC_TYPE_MASK = 0x00ffffff,
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XRP_DSP_SYNC_TYPE_LAST = 0,
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XRP_DSP_SYNC_TYPE_HW_SPEC_DATA = 1,
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XRP_DSP_SYNC_TYPE_HW_QUEUES = 2,
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XRP_DSP_SYNC_TYPE_HW_DEBUG_INFO =3,
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};
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struct xrp_dsp_tlv {
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__u32 type;
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__u32 length;
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__u32 value[0];
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};
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struct xrp_dsp_sync_v1 {
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__u32 sync;
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__u32 hw_sync_data[0];
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};
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struct xrp_dsp_sync_v2 {
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__u32 sync;
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__u32 reserved[3];
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struct xrp_dsp_tlv hw_sync_data[0];
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};
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enum log_level{
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FW_DEBUG_LOG_MODE_QUIET, /* disabel FW log printf */
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FW_DEBUG_LOG_MODE_ERR, /* enable FW log printf with error level */
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FW_DEBUG_LOG_MODE_WRN, /* enable FW log printf with warning level */
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FW_DEBUG_LOG_MODE_INF, /* enable FW log printf with info level*/
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FW_DEBUG_LOG_MODE_DBG, /* enable FW log printf with debug level*/
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FW_DEBUG_LOG_MODE_TRACE, /* enable FW log printf with trace level*/
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};
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struct xrp_dsp_debug_info{
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__u32 panic_addr;
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__u32 log_level;
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__u32 profile_addr;
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};
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enum {
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XRP_DSP_BUFFER_FLAG_READ = 0x1,
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XRP_DSP_BUFFER_FLAG_WRITE = 0x2,
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};
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struct xrp_dsp_buffer {
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/*
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* When submitted to DSP: types of access allowed
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* When returned to host: actual access performed
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*/
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__u32 flags;
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__u32 size;
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__u32 addr;
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};
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enum {
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XRP_DSP_CMD_FLAG_REQUEST_VALID = 0x00000001,
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XRP_DSP_CMD_FLAG_RESPONSE_VALID = 0x00000002,
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XRP_DSP_CMD_FLAG_REQUEST_NSID = 0x00000004,
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XRP_DSP_CMD_FLAG_RESPONSE_DELIVERY_FAIL = 0x00000008,
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};
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enum {
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XRP_DSP_REPORT_INVALID = 0,
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XRP_DSP_REPORT_WORKING = 0x1,
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XRP_DSP_REPORT_OVERWIRTE = 0x3,
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};
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#define XRP_DSP_REPORT_TO_HOST_FLAG (0x10000000)
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#define XRP_DSP_CMD_INLINE_DATA_SIZE 16
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#define XRP_DSP_CMD_INLINE_BUFFER_COUNT 1
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#define XRP_DSP_CMD_NAMESPACE_ID_SIZE 16
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#define XRP_DSP_CMD_STRIDE 128
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struct xrp_dsp_cmd {
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__u32 flags;
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__u32 in_data_size;
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__u32 out_data_size;
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__u32 buffer_size;
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union {
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__u32 in_data_addr;
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__u8 in_data[XRP_DSP_CMD_INLINE_DATA_SIZE];
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};
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union {
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__u32 out_data_addr;
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__u8 out_data[XRP_DSP_CMD_INLINE_DATA_SIZE];
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};
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union {
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__u32 buffer_addr;
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struct xrp_dsp_buffer buffer_data[XRP_DSP_CMD_INLINE_BUFFER_COUNT];
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__u8 buffer_alignment[XRP_DSP_CMD_INLINE_DATA_SIZE];
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};
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__u8 nsid[XRP_DSP_CMD_NAMESPACE_ID_SIZE];
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/*************DSP report channel***************************************/
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__u32 report_id;
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__u32 report_paylad_size;
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__u32 report_buffer_size;
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__u32 report_status;
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union {
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__u32 report_addr;
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__u8 report_data[XRP_DSP_CMD_INLINE_DATA_SIZE];
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};
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__u32 cmd_flag;
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};
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#endif
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