mirror of
https://github.com/clockworkpi/uConsole.git
synced 2025-12-31 11:28:51 +01:00
add a06 uconsole kernel patches
This commit is contained in:
cuu
parent
0680eee263
commit
26aecbfc92
0
Code/patch/a06/20230630/README.md
Normal file
0
Code/patch/a06/20230630/README.md
Normal file
37
Code/patch/a06/20230630/z-10000_a06_sound_230701.patch
Normal file
37
Code/patch/a06/20230630/z-10000_a06_sound_230701.patch
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@ -0,0 +1,37 @@
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diff --git a/sound/soc/codecs/es8328.c b/sound/soc/codecs/es8328.c
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index a7ab8dcc7..7518bbeb2 100644
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--- a/sound/soc/codecs/es8328.c
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+++ b/sound/soc/codecs/es8328.c
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@@ -253,11 +253,11 @@ static const struct snd_kcontrol_new es8328_snd_controls[] = {
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SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
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ES8328_LOUT1VOL, ES8328_ROUT1VOL,
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0, ES8328_OUT1VOL_MAX, 0, play_tlv),
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-
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+/*
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SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
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ES8328_LOUT2VOL, ES8328_ROUT2VOL,
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0, ES8328_OUT2VOL_MAX, 0, play_tlv),
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-
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+*/
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SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1,
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4, 0, 8, 0, mic_tlv),
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};
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@@ -871,6 +871,10 @@ static int es8328_component_probe(struct snd_soc_component *component)
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ES8328_DACCONTROL17_LD2LO, ES8328_DACCONTROL17_LD2LO);
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snd_soc_component_update_bits(component, ES8328_DACCONTROL20,
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ES8328_DACCONTROL20_RD2RO, ES8328_DACCONTROL20_RD2RO);
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+ snd_soc_component_update_bits(component, ES8328_LOUT2VOL,
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+ 0x3f, 0x1e);
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+ snd_soc_component_update_bits(component, ES8328_ROUT2VOL,
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+ 0x3f, 0x1e);
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}
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return 0;
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@@ -893,6 +897,7 @@ static void es8328_remove(struct snd_soc_component *component)
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}
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const struct regmap_config es8328_regmap_config = {
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+ .name = "es8328",
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = ES8328_REG_MAX,
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518
Code/patch/a06/20230630/z-10000_a06_uc_panel_230701.patch
Normal file
518
Code/patch/a06/20230630/z-10000_a06_uc_panel_230701.patch
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@ -0,0 +1,518 @@
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diff --git a/arch/arm64/boot/dts/rockchip/rk3399-clockworkpi-a06.dts b/arch/arm64/boot/dts/rockchip/rk3399-clockworkpi-a06.dts
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index b4e3324c1..3a1f950c1 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3399-clockworkpi-a06.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-clockworkpi-a06.dts
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@@ -304,7 +304,7 @@ mipi_dsi_out: endpoint {
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};
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dsi_panel: panel {
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- compatible = "cw,cwd686";
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+ compatible = "cw,cwu50";
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reg = <0>;
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backlight = <&ocp8178_backlight>;
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reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
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diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
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index 78854de4b..69222a60b 100644
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--- a/drivers/gpu/drm/panel/Makefile
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+++ b/drivers/gpu/drm/panel/Makefile
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@@ -65,4 +65,4 @@ obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
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obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o
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obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o
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obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
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-obj-$(CONFIG_DRM_PANEL_CWD686) += panel-cwd686.o
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+obj-$(CONFIG_DRM_PANEL_CWD686) += panel-cwd686.o panel-cwu50.o
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diff --git a/drivers/gpu/drm/panel/panel-cwu50.c b/drivers/gpu/drm/panel/panel-cwu50.c
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new file mode 100644
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index 000000000..157834c0f
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--- /dev/null
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+++ b/drivers/gpu/drm/panel/panel-cwu50.c
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@@ -0,0 +1,489 @@
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+/*
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+ * SPDX-License-Identifier: GPL-2.0+
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+ * Copyright (c) 2021 Clockwork Tech LLC
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+ * Copyright (c) 2021 Max Fierke <max@maxfierke.com>
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+ *
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+ */
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+
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+#include <drm/drm_modes.h>
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+#include <drm/drm_mipi_dsi.h>
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+#include <drm/drm_panel.h>
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+#include <linux/backlight.h>
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+#include <linux/gpio/consumer.h>
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+#include <linux/regulator/consumer.h>
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+#include <linux/delay.h>
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+#include <linux/of_device.h>
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+#include <linux/module.h>
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+
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+struct cwu50 {
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+ struct device *dev;
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+ struct drm_panel panel;
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+ struct regulator *supply;
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+ struct gpio_desc *enable_gpio;
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+ struct gpio_desc *reset_gpio;
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+ struct backlight_device *backlight;
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+ bool prepared;
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+ bool enabled;
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+ enum drm_panel_orientation orientation;
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+};
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+
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+static const struct drm_display_mode default_mode = {
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+ .clock = 62500,
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+ .hdisplay = 720,
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+ .hsync_start = 720 + 43,
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+ .hsync_end = 720+ 43 + 20,
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+ .htotal = 720 + 43 + 20 + 20,
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+ .vdisplay = 1280,
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+ .vsync_start = 1280 + 8,
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+ .vsync_end = 1280 + 8+ 2,
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+ .vtotal = 1280 + 8 + 2 + 16,
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+};
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+
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+static inline struct cwu50 *panel_to_cwu50(struct drm_panel *panel)
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+{
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+ return container_of(panel, struct cwu50, panel);
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+}
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+
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+#define dcs_write_seq(seq...) \
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+({ \
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+ static const u8 d[] = { seq }; \
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+ mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
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+})
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+
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+static void cwu50_init_sequence(struct cwu50 *ctx)
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+{
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+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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+
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+ dcs_write_seq(0xE1,0x93);
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+ dcs_write_seq(0xE2,0x65);
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+ dcs_write_seq(0xE3,0xF8);
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+ dcs_write_seq(0x70,0x20);
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+ dcs_write_seq(0x71,0x13);
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+ dcs_write_seq(0x72,0x06);
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+ dcs_write_seq(0x75,0x03);
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+ dcs_write_seq(0xE0,0x01);
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+ dcs_write_seq(0x00,0x00);
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+ dcs_write_seq(0x01,0x47);//VCOM0x47
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+ dcs_write_seq(0x03,0x00);
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+ dcs_write_seq(0x04,0x4D);
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+ dcs_write_seq(0x0C,0x64);
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+ dcs_write_seq(0x17,0x00);
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+ dcs_write_seq(0x18,0xBF);
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+ dcs_write_seq(0x19,0x00);
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+ dcs_write_seq(0x1A,0x00);
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+ dcs_write_seq(0x1B,0xBF);
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+ dcs_write_seq(0x1C,0x00);
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+ dcs_write_seq(0x1F,0x7E);
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+ dcs_write_seq(0x20,0x24);
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+ dcs_write_seq(0x21,0x24);
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+ dcs_write_seq(0x22,0x4E);
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+ dcs_write_seq(0x24,0xFE);
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+ dcs_write_seq(0x37,0x09);
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+ dcs_write_seq(0x38,0x04);
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+ dcs_write_seq(0x3C,0x76);
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+ dcs_write_seq(0x3D,0xFF);
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+ dcs_write_seq(0x3E,0xFF);
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+ dcs_write_seq(0x3F,0x7F);
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+ dcs_write_seq(0x40,0x04);//Dot inversion type
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+ dcs_write_seq(0x41,0xA0);
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+ dcs_write_seq(0x44,0x11);
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+ dcs_write_seq(0x55,0x02);
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+ dcs_write_seq(0x56,0x01);
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+ dcs_write_seq(0x57,0x49);
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+ dcs_write_seq(0x58,0x09);
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+ dcs_write_seq(0x59,0x2A);
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+ dcs_write_seq(0x5A,0x1A);
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+ dcs_write_seq(0x5B,0x1A);
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+ dcs_write_seq(0x5D,0x78);
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+ dcs_write_seq(0x5E,0x6E);
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+ dcs_write_seq(0x5F,0x66);
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+ dcs_write_seq(0x60,0x5E);
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+ dcs_write_seq(0x61,0x60);
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+ dcs_write_seq(0x62,0x54);
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+ dcs_write_seq(0x63,0x5C);
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+ dcs_write_seq(0x64,0x47);
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+ dcs_write_seq(0x65,0x5F);
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+ dcs_write_seq(0x66,0x5D);
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+ dcs_write_seq(0x67,0x5B);
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+ dcs_write_seq(0x68,0x76);
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+ dcs_write_seq(0x69,0x61);
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+ dcs_write_seq(0x6A,0x63);
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+ dcs_write_seq(0x6B,0x50);
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+ dcs_write_seq(0x6C,0x45);
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+ dcs_write_seq(0x6D,0x34);
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+ dcs_write_seq(0x6E,0x1C);
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+ dcs_write_seq(0x6F,0x07);
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+ dcs_write_seq(0x70,0x78);
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+ dcs_write_seq(0x71,0x6E);
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+ dcs_write_seq(0x72,0x66);
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+ dcs_write_seq(0x73,0x5E);
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+ dcs_write_seq(0x74,0x60);
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+ dcs_write_seq(0x75,0x54);
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+ dcs_write_seq(0x76,0x5C);
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+ dcs_write_seq(0x77,0x47);
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+ dcs_write_seq(0x78,0x5F);
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+ dcs_write_seq(0x79,0x5D);
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+ dcs_write_seq(0x7A,0x5B);
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+ dcs_write_seq(0x7B,0x76);
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+ dcs_write_seq(0x7C,0x61);
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+ dcs_write_seq(0x7D,0x63);
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+ dcs_write_seq(0x7E,0x50);
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+ dcs_write_seq(0x7F,0x45);
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+ dcs_write_seq(0x80,0x34);
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+ dcs_write_seq(0x81,0x1C);
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+ dcs_write_seq(0x82,0x07);
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+ dcs_write_seq(0xE0,0x02);
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+ dcs_write_seq(0x00,0x44);
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+ dcs_write_seq(0x01,0x46);
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+ dcs_write_seq(0x02,0x48);
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+ dcs_write_seq(0x03,0x4A);
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+ dcs_write_seq(0x04,0x40);
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+ dcs_write_seq(0x05,0x42);
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+ dcs_write_seq(0x06,0x1F);
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+ dcs_write_seq(0x07,0x1F);
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+ dcs_write_seq(0x08,0x1F);
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+ dcs_write_seq(0x09,0x1F);
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+ dcs_write_seq(0x0A,0x1F);
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+ dcs_write_seq(0x0B,0x1F);
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+ dcs_write_seq(0x0C,0x1F);
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+ dcs_write_seq(0x0D,0x1F);
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+ dcs_write_seq(0x0E,0x1F);
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+ dcs_write_seq(0x0F,0x1F);
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+ dcs_write_seq(0x10,0x1F);
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+ dcs_write_seq(0x11,0x1F);
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+ dcs_write_seq(0x12,0x1F);
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+ dcs_write_seq(0x13,0x1F);
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+ dcs_write_seq(0x14,0x1E);
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+ dcs_write_seq(0x15,0x1F);
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+ dcs_write_seq(0x16,0x45);
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+ dcs_write_seq(0x17,0x47);
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+ dcs_write_seq(0x18,0x49);
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+ dcs_write_seq(0x19,0x4B);
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+ dcs_write_seq(0x1A,0x41);
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+ dcs_write_seq(0x1B,0x43);
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+ dcs_write_seq(0x1C,0x1F);
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+ dcs_write_seq(0x1D,0x1F);
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+ dcs_write_seq(0x1E,0x1F);
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+ dcs_write_seq(0x1F,0x1F);
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+ dcs_write_seq(0x20,0x1F);
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+ dcs_write_seq(0x21,0x1F);
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+ dcs_write_seq(0x22,0x1F);
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+ dcs_write_seq(0x23,0x1F);
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+ dcs_write_seq(0x24,0x1F);
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+ dcs_write_seq(0x25,0x1F);
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+ dcs_write_seq(0x26,0x1F);
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+ dcs_write_seq(0x27,0x1F);
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+ dcs_write_seq(0x28,0x1F);
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+ dcs_write_seq(0x29,0x1F);
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+ dcs_write_seq(0x2A,0x1E);
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+ dcs_write_seq(0x2B,0x1F);
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+ dcs_write_seq(0x2C,0x0B);
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+ dcs_write_seq(0x2D,0x09);
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+ dcs_write_seq(0x2E,0x07);
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+ dcs_write_seq(0x2F,0x05);
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+ dcs_write_seq(0x30,0x03);
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+ dcs_write_seq(0x31,0x01);
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+ dcs_write_seq(0x32,0x1F);
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+ dcs_write_seq(0x33,0x1F);
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+ dcs_write_seq(0x34,0x1F);
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+ dcs_write_seq(0x35,0x1F);
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+ dcs_write_seq(0x36,0x1F);
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+ dcs_write_seq(0x37,0x1F);
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+ dcs_write_seq(0x38,0x1F);
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+ dcs_write_seq(0x39,0x1F);
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+ dcs_write_seq(0x3A,0x1F);
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+ dcs_write_seq(0x3B,0x1F);
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+ dcs_write_seq(0x3C,0x1F);
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+ dcs_write_seq(0x3D,0x1F);
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+ dcs_write_seq(0x3E,0x1F);
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+ dcs_write_seq(0x3F,0x1F);
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+ dcs_write_seq(0x40,0x1F);
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+ dcs_write_seq(0x41,0x1E);
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+ dcs_write_seq(0x42,0x0A);
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+ dcs_write_seq(0x43,0x08);
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+ dcs_write_seq(0x44,0x06);
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+ dcs_write_seq(0x45,0x04);
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+ dcs_write_seq(0x46,0x02);
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+ dcs_write_seq(0x47,0x00);
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+ dcs_write_seq(0x48,0x1F);
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+ dcs_write_seq(0x49,0x1F);
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+ dcs_write_seq(0x4A,0x1F);
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+ dcs_write_seq(0x4B,0x1F);
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+ dcs_write_seq(0x4C,0x1F);
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+ dcs_write_seq(0x4D,0x1F);
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+ dcs_write_seq(0x4E,0x1F);
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+ dcs_write_seq(0x4F,0x1F);
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+ dcs_write_seq(0x50,0x1F);
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+ dcs_write_seq(0x51,0x1F);
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+ dcs_write_seq(0x52,0x1F);
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+ dcs_write_seq(0x53,0x1F);
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+ dcs_write_seq(0x54,0x1F);
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+ dcs_write_seq(0x55,0x1F);
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+ dcs_write_seq(0x56,0x1F);
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+ dcs_write_seq(0x57,0x1E);
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+ dcs_write_seq(0x58,0x40);
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+ dcs_write_seq(0x59,0x00);
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+ dcs_write_seq(0x5A,0x00);
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+ dcs_write_seq(0x5B,0x30);
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+ dcs_write_seq(0x5C,0x02);
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+ dcs_write_seq(0x5D,0x40);
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+ dcs_write_seq(0x5E,0x01);
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+ dcs_write_seq(0x5F,0x02);
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+ dcs_write_seq(0x60,0x00);
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+ dcs_write_seq(0x61,0x01);
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+ dcs_write_seq(0x62,0x02);
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+ dcs_write_seq(0x63,0x65);
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+ dcs_write_seq(0x64,0x66);
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+ dcs_write_seq(0x65,0x00);
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+ dcs_write_seq(0x66,0x00);
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+ dcs_write_seq(0x67,0x74);
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+ dcs_write_seq(0x68,0x06);
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+ dcs_write_seq(0x69,0x65);
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+ dcs_write_seq(0x6A,0x66);
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+ dcs_write_seq(0x6B,0x10);
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+ dcs_write_seq(0x6C,0x00);
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+ dcs_write_seq(0x6D,0x04);
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+ dcs_write_seq(0x6E,0x04);
|
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+ dcs_write_seq(0x6F,0x88);
|
||||
+ dcs_write_seq(0x70,0x00);
|
||||
+ dcs_write_seq(0x71,0x00);
|
||||
+ dcs_write_seq(0x72,0x06);
|
||||
+ dcs_write_seq(0x73,0x7B);
|
||||
+ dcs_write_seq(0x74,0x00);
|
||||
+ dcs_write_seq(0x75,0x87);
|
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+ dcs_write_seq(0x76,0x00);
|
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+ dcs_write_seq(0x77,0x5D);
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+ dcs_write_seq(0x78,0x17);
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||||
+ dcs_write_seq(0x79,0x1F);
|
||||
+ dcs_write_seq(0x7A,0x00);
|
||||
+ dcs_write_seq(0x7B,0x00);
|
||||
+ dcs_write_seq(0x7C,0x00);
|
||||
+ dcs_write_seq(0x7D,0x03);
|
||||
+ dcs_write_seq(0x7E,0x7B);
|
||||
+ dcs_write_seq(0xE0,0x04);
|
||||
+ dcs_write_seq(0x09,0x10);
|
||||
+ dcs_write_seq(0xE0,0x00);
|
||||
+ dcs_write_seq(0xE6,0x02);
|
||||
+ dcs_write_seq(0xE7,0x02);
|
||||
+ dcs_write_seq(0x11);// SLPOUT
|
||||
+ msleep (120);
|
||||
+ dcs_write_seq(0x29);// DSPON
|
||||
+ msleep (20);
|
||||
+ dcs_write_seq(0x35,0x00);
|
||||
+}
|
||||
+
|
||||
+static int cwu50_disable(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct cwu50 *ctx = panel_to_cwu50(panel);
|
||||
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!ctx->enabled)
|
||||
+ return 0;
|
||||
+
|
||||
+ backlight_disable(ctx->backlight);
|
||||
+
|
||||
+ ctx->enabled = false;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cwu50_unprepare(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct cwu50 *ctx = panel_to_cwu50(panel);
|
||||
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!ctx->prepared)
|
||||
+ return 0;
|
||||
+
|
||||
+ ret = mipi_dsi_dcs_set_display_off(dsi);
|
||||
+ if (ret) {
|
||||
+ dev_err(ctx->dev, "failed to turn display off (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
|
||||
+ if (ret) {
|
||||
+ dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ msleep(120);
|
||||
+
|
||||
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
|
||||
+ msleep(5);
|
||||
+
|
||||
+ ctx->prepared = false;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cwu50_prepare(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct cwu50 *ctx = panel_to_cwu50(panel);
|
||||
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
+ int ret;
|
||||
+
|
||||
+ if (ctx->prepared)
|
||||
+ return 0;
|
||||
+
|
||||
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
|
||||
+ msleep(10);
|
||||
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
|
||||
+ msleep(120);
|
||||
+
|
||||
+ /* Enabe tearing mode: send TE (tearing effect) at VBLANK */
|
||||
+ ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
|
||||
+ if (ret) {
|
||||
+ dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ /* Exit sleep mode and power on */
|
||||
+
|
||||
+ cwu50_init_sequence(ctx);
|
||||
+
|
||||
+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
|
||||
+ if (ret) {
|
||||
+ dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ msleep(120);
|
||||
+
|
||||
+ ret = mipi_dsi_dcs_set_display_on(dsi);
|
||||
+ if (ret) {
|
||||
+ dev_err(ctx->dev, "failed to turn display on (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ msleep(20);
|
||||
+
|
||||
+ ctx->prepared = true;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cwu50_enable(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct cwu50 *ctx = panel_to_cwu50(panel);
|
||||
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
+ int ret;
|
||||
+
|
||||
+ if (ctx->enabled)
|
||||
+ return 0;
|
||||
+
|
||||
+ backlight_enable(ctx->backlight);
|
||||
+
|
||||
+ ctx->enabled = true;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cwu50_get_modes(struct drm_panel *panel, struct drm_connector *connector)
|
||||
+{
|
||||
+ struct cwu50 *ctx = panel_to_cwu50(panel);
|
||||
+ struct drm_display_mode *mode;
|
||||
+
|
||||
+ mode = drm_mode_duplicate(connector->dev, &default_mode);
|
||||
+ if (!mode) {
|
||||
+ dev_err(panel->dev, "bad mode or failed to add mode\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ drm_mode_set_name(mode);
|
||||
+ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
|
||||
+
|
||||
+ connector->display_info.width_mm = mode->width_mm;
|
||||
+ connector->display_info.height_mm = mode->height_mm;
|
||||
+
|
||||
+ /* set up connector's "panel orientation" property */
|
||||
+ drm_connector_set_panel_orientation(connector, ctx->orientation);
|
||||
+
|
||||
+ drm_mode_probed_add(connector, mode);
|
||||
+
|
||||
+ return 1; /* Number of modes */
|
||||
+}
|
||||
+
|
||||
+static const struct drm_panel_funcs cwu50_drm_funcs = {
|
||||
+ .disable = cwu50_disable,
|
||||
+ .unprepare = cwu50_unprepare,
|
||||
+ .prepare = cwu50_prepare,
|
||||
+ .enable = cwu50_enable,
|
||||
+ .get_modes = cwu50_get_modes,
|
||||
+};
|
||||
+
|
||||
+static int cwu50_probe(struct mipi_dsi_device *dsi)
|
||||
+{
|
||||
+ struct device *dev = &dsi->dev;
|
||||
+ struct cwu50 *ctx;
|
||||
+ int ret;
|
||||
+
|
||||
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
||||
+ if (!ctx)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ mipi_dsi_set_drvdata(dsi, ctx);
|
||||
+ ctx->dev = dev;
|
||||
+
|
||||
+ dsi->lanes = 4;
|
||||
+ dsi->format = MIPI_DSI_FMT_RGB888;
|
||||
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO |MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
|
||||
+
|
||||
+ ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
|
||||
+ if (IS_ERR(ctx->reset_gpio)) {
|
||||
+ ret = PTR_ERR(ctx->reset_gpio);
|
||||
+ if (ret != -EPROBE_DEFER)
|
||||
+ dev_err(dev, "failed to request GPIO (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ctx->backlight = devm_of_find_backlight(dev);
|
||||
+ if (IS_ERR(ctx->backlight)) {
|
||||
+ return PTR_ERR(ctx->backlight);
|
||||
+ }
|
||||
+
|
||||
+ ret = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ drm_panel_init(&ctx->panel, dev, &cwu50_drm_funcs, DRM_MODE_CONNECTOR_DSI);
|
||||
+
|
||||
+ drm_panel_add(&ctx->panel);
|
||||
+
|
||||
+ ret = mipi_dsi_attach(dsi);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
|
||||
+ drm_panel_remove(&ctx->panel);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int cwu50_remove(struct mipi_dsi_device *dsi)
|
||||
+{
|
||||
+ struct cwu50 *ctx = mipi_dsi_get_drvdata(dsi);
|
||||
+
|
||||
+ mipi_dsi_detach(dsi);
|
||||
+ drm_panel_remove(&ctx->panel);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id cwu50_of_match[] = {
|
||||
+ { .compatible = "cw,cwu50" },
|
||||
+ { }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, cwu50_of_match);
|
||||
+
|
||||
+static struct mipi_dsi_driver cwu50_driver = {
|
||||
+ .probe = cwu50_probe,
|
||||
+ .remove = cwu50_remove,
|
||||
+ .driver = {
|
||||
+ .name = "panel-cwu50",
|
||||
+ .of_match_table = cwu50_of_match,
|
||||
+ },
|
||||
+};
|
||||
+module_mipi_dsi_driver(cwu50_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("DRM Driver for cwu50 MIPI DSI panel");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
Loading…
x
Reference in New Issue
Block a user