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add lightbox to developer's guide

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Signed-off-by: Michel-FK <michel.stempin@funkey-project.com>
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Michel-FK 2021-01-23 19:38:27 +01:00
parent 33a9f6d237
commit 22b62cb264
12 changed files with 21 additions and 21 deletions
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6
docs/developers/hardware_ref/architecture.md
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@ -14,15 +14,15 @@ to the following electronic diagram, featuring 3 main blocks:
- 1x 420 mAh 402540 LiPo battery, containing an active protection - 1x 420 mAh 402540 LiPo battery, containing an active protection
circuitry circuitry
![FunKey S Block Diagram](/assets/images/FunKey_S_Block_Diagram.png) ![FunKey S Block Diagram](/assets/images/FunKey_S_Block_Diagram.png){: .lightbox}
## 3D View ## 3D View
A 3D rendering of the PCBA done in KiCAD produces the images below: A 3D rendering of the PCBA done in KiCAD produces the images below:
![FunKey Top](/assets/images/FunKey_S_Top.png) ![FunKey Top](/assets/images/FunKey_S_Top.png){: .lightbox}
![FunKey Bottom](/assets/images/FunKey_S_Bottom.png) ![FunKey Bottom](/assets/images/FunKey_S_Bottom.png){: .lightbox}
## BOM ## BOM

2
docs/developers/hardware_ref/audio.md
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@ -53,7 +53,7 @@ required to drive the speaker.
Here is the corresponding schematic: Here is the corresponding schematic:
![Audio Schematics](/assets/images/Audio_Schematics.png) ![Audio Schematics](/assets/images/Audio_Schematics.png){: .lightbox}
We chose the right headphone channel HPOUTR that is fed to the audio We chose the right headphone channel HPOUTR that is fed to the audio
amplifier **U2** through a coupling capacitor **C3**. amplifier **U2** through a coupling capacitor **C3**.

4
docs/developers/hardware_ref/buttons.md
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@ -76,7 +76,7 @@ when required.
Here is the corresponding main schematic for the buttons: Here is the corresponding main schematic for the buttons:
![Main Button Schematics](/assets/images/Main_Button_Schematics.png) ![Main Button Schematics](/assets/images/Main_Button_Schematics.png){: .lightbox}
The main component is of course the I/O expander **U1**, with the The main component is of course the I/O expander **U1**, with the
control signals to the CPU/PMIC on the north side. control signals to the CPU/PMIC on the north side.
@ -107,7 +107,7 @@ user!
The other buttons are wired in the same fashion: The other buttons are wired in the same fashion:
![Secondary Button Schematics](/assets/images/Secondary_Button_Schematics.png) ![Secondary Button Schematics](/assets/images/Secondary_Button_Schematics.png){: .lightbox}
The "U", "L", "D", "R", "A", "B", "X" and "Y" buttons **S3**, **S4**, The "U", "L", "D", "R", "A", "B", "X" and "Y" buttons **S3**, **S4**,
**S5**, **S6**, **S8**, **S9**, **S10** and **S11** are of the same **S5**, **S6**, **S8**, **S9**, **S10** and **S11** are of the same

6
docs/developers/hardware_ref/cpu.md
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@ -57,7 +57,7 @@ purpose.
Here is the part of the schematics corresponding to the CPU core: Here is the part of the schematics corresponding to the CPU core:
![CPU Schematics](/assets/images/CPU_Schematics.png) ![CPU Schematics](/assets/images/CPU_Schematics.png){: .lightbox}
## SoC Blocks ## SoC Blocks
@ -190,13 +190,13 @@ termination resistors on the data lines DQx.
DDR2 or DDR3 DRAMs feature merged drivers and dynamic on-chip DDR2 or DDR3 DRAMs feature merged drivers and dynamic on-chip
termination like this ("VDDQ/2" is labeled "SVREF" in our schematic): termination like this ("VDDQ/2" is labeled "SVREF" in our schematic):
![DRAM Merged Drivers](/assets/images/DRAM_Merged_Drivers.png) ![DRAM Merged Drivers](/assets/images/DRAM_Merged_Drivers.png){: .lightbox}
The V3s DDR2 DRAM has an active termination calibration circuitry and The V3s DDR2 DRAM has an active termination calibration circuitry and
procedure called "_ZQ Calibration_" requiring an accurate 1% 240 Ω procedure called "_ZQ Calibration_" requiring an accurate 1% 240 Ω
resistor **R11** connected internally like this: resistor **R11** connected internally like this:
![Pull-Up Calibration](/assets/images/Pull-Up_Calibration.png) ![Pull-Up Calibration](/assets/images/Pull-Up_Calibration.png){: .lightbox}
More information on the DDR2 DRAM ZQ Calibration subject can be found More information on the DDR2 DRAM ZQ Calibration subject can be found
in this [Micron Application Note][14]. in this [Micron Application Note][14].

2
docs/developers/hardware_ref/magnetic_switch.md
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@ -27,7 +27,7 @@ Meder MK24][1].
Here is the corresponding schematics, already covered in the PMIC discussion: Here is the corresponding schematics, already covered in the PMIC discussion:
![Magnetic Sensor Schematics](/assets/images/Magnetic_Sensor_Schematics.png) ![Magnetic Sensor Schematics](/assets/images/Magnetic_Sensor_Schematics.png){: .lightbox}
The global PMIC chip enable signal N_OE is activated by default The global PMIC chip enable signal N_OE is activated by default
through a 47kΩ resistor **R17** to GND, but the magnetic Reed switch through a 47kΩ resistor **R17** to GND, but the magnetic Reed switch

2
docs/developers/hardware_ref/power/decoupling.md
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@ -97,7 +97,7 @@ are used for much lower currents and much briefer periods (typically
The last part of the FunKey schematics merely contains only decoupling The last part of the FunKey schematics merely contains only decoupling
capacitors: capacitors:
![Decoupling Schematics](/assets/images/Decoupling_Schematics.png) ![Decoupling Schematics](/assets/images/Decoupling_Schematics.png){: .lightbox}
One exception is the Allwinner V3s CPU HPR/HPL circuit which features One exception is the Allwinner V3s CPU HPR/HPL circuit which features
an RC-to-ground circuit between the amplifier and the preamplifier an RC-to-ground circuit between the amplifier and the preamplifier

2
docs/developers/hardware_ref/power/dram.md
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@ -19,7 +19,7 @@ Design][2].
Here is the corresponding DRAM Power schematics: Here is the corresponding DRAM Power schematics:
![DRAM Power Schematics](/assets/images/DRAM_Power_Schematics.png) ![DRAM Power Schematics](/assets/images/DRAM_Power_Schematics.png){: .lightbox}
Nothing very fancy here: the SMPS chip **U4** has its required input Nothing very fancy here: the SMPS chip **U4** has its required input
filter capacitor **C37** and output capacitors **C65** and **C73**. filter capacitor **C37** and output capacitors **C65** and **C73**.

6
docs/developers/hardware_ref/power/pmic.md
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@ -28,7 +28,7 @@ Their AXP20x products are highly-integrated PMICs that are optimized
for applications requiring single-cell Li-battery (Li-Ion/Polymer), for applications requiring single-cell Li-battery (Li-Ion/Polymer),
multiple output DC-DC converters and LDOs. Here is a block diagram: multiple output DC-DC converters and LDOs. Here is a block diagram:
![PMIC Block Diagram](/assets/images/AXP20x_Block_Diagram.png) ![PMIC Block Diagram](/assets/images/AXP20x_Block_Diagram.png){: .lightbox}
The AXP20x features: The AXP20x features:
@ -88,7 +88,7 @@ schematics for using an AXP203 to supply the power to a V3s-based
dashboard camera design. It follows closely the application diagram dashboard camera design. It follows closely the application diagram
provided in the AXP20x datasheets: provided in the AXP20x datasheets:
![AXP20x Application Diagram](/assets/images/AXP20x_Application_Diagram.png) ![AXP20x Application Diagram](/assets/images/AXP20x_Application_Diagram.png){: .lightbox}
More hints are provided in our self-translated [V3s Hardware Design More hints are provided in our self-translated [V3s Hardware Design
Guide][10] (page 7) too. Guide][10] (page 7) too.
@ -110,7 +110,7 @@ S** device only uses 2 out of the 5 integrated LDOs:
Here are the PMIC schematics: Here are the PMIC schematics:
![PMIC Schematics](/assets/images/PMIC_Schematics.png) ![PMIC Schematics](/assets/images/PMIC_Schematics.png){: .lightbox}
These schematics may look intimidating and complex, but they are in These schematics may look intimidating and complex, but they are in
fact just a collection of simple basic elements, and it is actually fact just a collection of simple basic elements, and it is actually

4
docs/developers/hardware_ref/screen.md
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@ -82,7 +82,7 @@ a one-time tooling fee of ~ $800.
The schematic is quite simple: The schematic is quite simple:
![SPI LCD Schematics](/assets/images/SPI_LCD_Schematics.png) ![SPI LCD Schematics](/assets/images/SPI_LCD_Schematics.png){: .lightbox}
The main component is of course the Hirose screen connector **J3**, The main component is of course the Hirose screen connector **J3**,
with the following signals: with the following signals:
@ -120,7 +120,7 @@ the screen, we need to drive these LEDs "from the high-side",
i.e. between the +3V3 power supply and the LEDA pin, so a MOSFET-P i.e. between the +3V3 power supply and the LEDA pin, so a MOSFET-P
transistor is necessary: transistor is necessary:
![Backlight Schematics](/assets/images/Backlight_Schematics.png) ![Backlight Schematics](/assets/images/Backlight_Schematics.png){: .lightbox}
As we want the backlight to be on by default, we need to drive it to As we want the backlight to be on by default, we need to drive it to
GND by default: this is the role of **R7**. The role of **R5** is then GND by default: this is the role of **R7**. The role of **R5** is then

4
docs/developers/hardware_ref/sd-card.md
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@ -26,7 +26,7 @@ But a good summary of the requirements is given in the "[<i>AN10911
SD(HC)-memory card and MMC Interface conditioning</i>][3]" application SD(HC)-memory card and MMC Interface conditioning</i>][3]" application
note from NXP, from which this schematic is taken: note from NXP, from which this schematic is taken:
![SD/MMC Interface](/assets/images/SD_MMC_Interface.png) ![SD MMC Interface](/assets/images/SD_MMC_Interface.png){: .lightbox}
!!! Warning !!! Warning
This schematic does not include details concerning card-supply and This schematic does not include details concerning card-supply and
@ -80,7 +80,7 @@ an open-drain output mode, and its value should be undercut (down to
The FunKey SD Card interface schematic is the following: The FunKey SD Card interface schematic is the following:
![SD Card Schematics](/assets/images/SD_Card_Schematics.png) ![SD Card Schematics](/assets/images/SD_Card_Schematics.png){: .lightbox}
![TF-110](/assets/images/TF-110.png){: align=left } ![TF-110](/assets/images/TF-110.png){: align=left }

2
docs/developers/hardware_ref/uart.md
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@ -12,7 +12,7 @@ loging into the system over an UART.
The Console schematic only requires a minimum of external components: The Console schematic only requires a minimum of external components:
![Console Schematics](/assets/images/UART_Schematics.png) ![Console Schematics](/assets/images/UART_Schematics.png){: .lightbox}
Besides the 3-pin 1.27 mm (0.05") pitch header J1 that will not be Besides the 3-pin 1.27 mm (0.05") pitch header J1 that will not be
mounted on standard products, there is only a single series resistor mounted on standard products, there is only a single series resistor

2
docs/developers/hardware_ref/usb.md
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@ -22,7 +22,7 @@ user don't pull the chord straight.
The USB schematic is the following: The USB schematic is the following:
![USB Schematics](/assets/images/USB_Schematics.png) ![USB Schematics](/assets/images/USB_Schematics.png){: .lightbox}
Before connecting 2 devices using an USB cable, they may be at Before connecting 2 devices using an USB cable, they may be at
completely different absolute voltages, and during cable insertion, completely different absolute voltages, and during cable insertion,