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ctr/3ds: attempt to improve cache flushing

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This commit is contained in:
notaz
2018-01-31 23:44:45 +02:00
committed by twinaphex
parent 2de0bf3318
commit f5d7a8de11
2 changed files with 13 additions and 35 deletions
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45
platform/libretro/3ds/3ds_utils.c
View File

@@ -20,48 +20,29 @@ static void ctr_enable_all_svc_kernel(void)
svc_access_control[3]=0x3FFFFFFF;
}
static void ctr_invalidate_ICache_kernel(void)
{
__asm__ volatile(
"cpsid aif\n\t"
"mov r0, #0\n\t"
"mcr p15, 0, r0, c7, c5, 0\n\t");
}
static void ctr_flush_DCache_kernel(void)
{
__asm__ volatile(
"cpsid aif\n\t"
"mov r0, #0\n\t"
"mcr p15, 0, r0, c7, c10, 0\n\t");
}
static void ctr_enable_all_svc(void)
{
svcBackdoor((ctr_callback_type)ctr_enable_all_svc_kernel);
}
void ctr_invalidate_ICache(void)
static void ctr_clean_invalidate_kernel(void)
{
// __asm__ volatile("svc 0x2E\n\t");
svcBackdoor((ctr_callback_type)ctr_invalidate_ICache_kernel);
__asm__ volatile(
"mrs r1, cpsr\n"
"cpsid aif\n" // disable interrupts
"mov r0, #0\n"
"mcr p15, 0, r0, c7, c10, 0\n" // clean dcache
"mcr p15, 0, r0, c7, c10, 4\n" // DSB
"mcr p15, 0, r0, c7, c5, 0\n" // invalidate icache+BTAC
"msr cpsr_cx, r1\n" // restore interrupts
::: "r0", "r1");
}
void ctr_flush_DCache(void)
{
// __asm__ volatile("svc 0x4B\n\t");
svcBackdoor((ctr_callback_type)ctr_flush_DCache_kernel);
}
void ctr_flush_invalidate_cache(void)
{
ctr_flush_DCache();
ctr_invalidate_ICache();
// __asm__ volatile("svc 0x2E\n\t");
// __asm__ volatile("svc 0x4B\n\t");
svcBackdoor((ctr_callback_type)ctr_clean_invalidate_kernel);
}
int ctr_svchack_init(void)

3
platform/libretro/3ds/3ds_utils.h
View File

@@ -1,9 +1,6 @@
#ifndef _3DS_UTILS_H
#define _3DS_UTILS_H
void ctr_invalidate_ICache(void);
void ctr_flush_DCache(void);
void ctr_flush_invalidate_cache(void);
int ctr_svchack_init(void);