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Generate ld rd, (rs) instructions properly.

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--HG--
branch : dtrg-videocore
This commit is contained in:
David Given 2013-05-22 11:02:46 +01:00
parent 9e556d8b7b
commit cdce394b6c
1 changed files with 1 additions and 1 deletions
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2
mach/vc4/as/mach5.c
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@ -254,7 +254,7 @@ void mem_instr(quad opcode, int cc, int rd, long offset, int rs)
if ((rs < 0x10) && (rd < 0x10) && (offset == 0)) if ((rs < 0x10) && (rd < 0x10) && (offset == 0))
{ {
emit2(B16(00001000,00000000) | (opcode<<8) | (rs<<4) | (rd<<4)); emit2(B16(00001000,00000000) | (opcode<<8) | (rs<<4) | (rd<<0));
return; return;
} }