o add bank test
o cleanup bank debug in uploaded o add header dump to uploader
This commit is contained in:
optixx
parent
09f42acfc8
commit
74312e08e1
@ -182,7 +182,7 @@ AVRDUDE_PROGRAMMER = stk500v2
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# com1 = serial port. Use lpt1 to connect to parallel port.
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# com1 = serial port. Use lpt1 to connect to parallel port.
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AVRDUDE_PORT = /dev/tty.PL2303-00001124
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AVRDUDE_PORT = /dev/tty.PL2303-00002126
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AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex
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AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex
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@ -39,13 +39,20 @@ extern FILE uart_stdout;
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#define LED_PORT PORTD
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#define LED_PORT PORTD
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#define LED_DIR DDRD
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#define LED_DIR DDRD
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//#define FILENAME "sprite.raw"
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//#define FILENAME "sprite.raw" ok
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//#define FILENAME "ascii.smc"
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//#define FILENAME "ascii.smc" ok
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#define FILENAME "rom.smc"
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//#define FILENAME "rom.smc" ok
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//#define FILENAME "supert.smc"
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//#define FILENAME "supert.smc"
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//#define FILENAME "vortex.smc"
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//#define FILENAME "vortex.smc"
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//#define FILENAME "mrdo.smc"
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//#define FILENAME "mrdo.smc"
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//#define FILENAME "hungry.smc"
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//#define FILENAME "hungry.smc"
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//#define FILENAME "bank01.smc" ok
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//#define FILENAME "bank02.smc" ok
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//#define FILENAME "bank03.smc" ok
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//#define FILENAME "bank04.smc"
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//#define FILENAME "bank05.smc"
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//#define FILENAME "bank06.smc"
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#define FILENAME "bank07.smc"
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#define DUMPNAME "dump256.smc"
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#define DUMPNAME "dump256.smc"
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#define BUFFER_SIZE 512
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#define BUFFER_SIZE 512
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@ -283,9 +290,10 @@ int main(void)
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for (uint16_t block_cnt=0; block_cnt<BLOCKS; block_cnt++) {
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for (uint16_t block_cnt=0; block_cnt<BLOCKS; block_cnt++) {
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fat_read_file (fat_cluster,read_buffer,block_cnt);
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fat_read_file (fat_cluster,read_buffer,block_cnt);
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if (block_cnt % 64 == 0){
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if (block_cnt && block_cnt % 64 == 0){
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bank_cnt++;
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printf("Write Ram Bank: 0x%x Addr: 0x%lx Skipped: %li\n",bank_cnt,rom_addr,skip_block);
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printf("Write Ram Bank: 0x%x Addr: 0x%lx Skipped: %li\n",bank_cnt,rom_addr,skip_block);
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bank_cnt++;
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skip_block=0;
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}
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}
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if (sram_check(read_buffer,512))
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if (sram_check(read_buffer,512))
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sram_copy(rom_addr,read_buffer,512);
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sram_copy(rom_addr,read_buffer,512);
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@ -293,9 +301,16 @@ int main(void)
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skip_block +=1;
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skip_block +=1;
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rom_addr += 512;
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rom_addr += 512;
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}
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}
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printf("Done 0x%lx Skipped %li\n",rom_addr,skip_block);
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printf("Write Ram Bank: 0x%x Addr: 0x%lx Skipped: %li\n",bank_cnt,rom_addr,skip_block);
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printf("Done\n");
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}
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}
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printf("Dump Headern\r");
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rom_addr = 0x8000-512;
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sram_read_buffer(rom_addr,read_buffer,512);
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dump_packet(rom_addr,512,read_buffer);
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#if 0
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#if 0
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printf("Dump Memory\n\r");
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printf("Dump Memory\n\r");
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rom_addr = 0x000000;
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rom_addr = 0x000000;
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143
snes/banktest/LoadGraphics.asm
Normal file
143
snes/banktest/LoadGraphics.asm
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@ -0,0 +1,143 @@
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;============================================================================
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; Macros
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;============================================================================
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;============================================================================
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;LoadPalette - Macro that loads palette information into CGRAM
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;----------------------------------------------------------------------------
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; In: SRC_ADDR -- 24 bit address of source data,
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; START -- Color # to start on,
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; SIZE -- # of COLORS to copy
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;----------------------------------------------------------------------------
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; Out: None
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;----------------------------------------------------------------------------
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; Modifies: A,X
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; Requires: mem/A = 8 bit, X/Y = 16 bit
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;----------------------------------------------------------------------------
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.MACRO LoadPalette
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lda #\2
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sta $2121 ; Start at START color
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lda #:\1 ; Using : before the parameter gets its bank.
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ldx #\1 ; Not using : gets the offset address.
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ldy #(\3 * 2) ; 2 bytes for every color
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jsr DMAPalette
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.ENDM
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;============================================================================
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; LoadBlockToVRAM -- Macro that simplifies calling LoadVRAM to copy data to VRAM
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;----------------------------------------------------------------------------
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; In: SRC_ADDR -- 24 bit address of source data
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; DEST -- VRAM address to write to (WORD address!!)
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; SIZE -- number of BYTEs to copy
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;----------------------------------------------------------------------------
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; Out: None
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;----------------------------------------------------------------------------
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; Modifies: A, X, Y
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;----------------------------------------------------------------------------
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;LoadBlockToVRAM SRC_ADDRESS, DEST, SIZE
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; requires: mem/A = 8 bit, X/Y = 16 bit
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.MACRO LoadBlockToVRAM
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lda #$80
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sta $2115
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ldx #\2 ; DEST
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stx $2116 ; $2116: Word address for accessing VRAM.
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lda #:\1 ; SRCBANK
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ldx #\1 ; SRCOFFSET
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ldy #\3 ; SIZE
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jsr LoadVRAM
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.ENDM
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;============================================================================
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; Routines
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;============================================================================
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.BANK 0
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.ORG 0
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.SECTION "LoadVRAMCode" SEMIFREE
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;============================================================================
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; LoadVRAM -- Load data into VRAM
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;----------------------------------------------------------------------------
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; In: A:X -- points to the data
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; Y -- Number of bytes to copy (0 to 65535) (assumes 16-bit index)
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;----------------------------------------------------------------------------
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; Out: None
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;----------------------------------------------------------------------------
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; Modifies: none
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;----------------------------------------------------------------------------
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; Notes: Assumes VRAM address has been previously set!!
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;----------------------------------------------------------------------------
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LoadVRAM:
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pha
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phx
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phy
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phb
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php ; Preserve Registers
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sep #$20
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stx $4302 ; Store Data offset into DMA source offset
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sta $4304 ; Store data Bank into DMA source bank
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sty $4305 ; Store size of data block
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lda #$01
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sta $4300 ; Set DMA mode (word, normal increment)
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lda #$18 ; Set the destination register (VRAM write register)
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sta $4301
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lda #$01 ; Initiate DMA transfer (channel 1)
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sta $420B
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plp ; restore registers
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plb
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ply
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plx
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pla
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rts ; return
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;============================================================================
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.ENDS
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.BANK 0
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.ORG 0
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.SECTION "DMAPaletteCode" SEMIFREE
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;============================================================================
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; DMAPalette -- Load entire palette using DMA
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;----------------------------------------------------------------------------
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; In: A:X -- points to the data
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; Y -- Size of data
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;----------------------------------------------------------------------------
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; Out: None
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;----------------------------------------------------------------------------
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; Modifies: none
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;----------------------------------------------------------------------------
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DMAPalette:
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pha
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phx
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phb
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php ; Preserve Registers
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sep #$20
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stx $4302 ; Store data offset into DMA source offset
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sta $4304 ; Store data bank into DMA source bank
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sty $4305 ; Store size of data block
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stz $4300 ; Set DMA Mode (byte, normal increment)
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lda #$22 ; Set destination register ($2122 - CGRAM Write)
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sta $4301
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lda #$01 ; Initiate DMA transfer
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sta $420B
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plp ; Restore registers
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plb
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plx
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pla
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rts ; return from subroutine
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;============================================================================
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.ENDS
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33
snes/banktest/Makefile
Normal file
33
snes/banktest/Makefile
Normal file
@ -0,0 +1,33 @@
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#wla-65816 -o %1.asm %1.obj
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#wlalink -vr temp.prj %1.smc
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AS=wla-65816
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LD=wlalink
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OBJS=vram2.o
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APP=vram2.smc
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GFX=
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all: clean $(APP)
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run:
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zsnes $(APP)
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linkfile:
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echo "[objects]" > linkerfile.prj
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optixx.inc: optixx.pcx
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wine tools/pcx2snes.exe optixx.pcx -b2 -nOptixx -ooptixx.inc
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%.o: %.asm
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echo "$@" >> linkerfile.prj
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$(AS) -o $? $@
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$(APP): linkfile $(GFX) $(OBJS) $(GFX)
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$(LD) -vr linkerfile.prj $@
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clean:
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rm -vf $(APP) *.prj *.o
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61
snes/banktest/header.inc
Normal file
61
snes/banktest/header.inc
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;------------------------------ Header File ---------------------------------
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; This is basically a combo of MarctheMER's and Neviksti's header files
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; Perhaps reading their's will also help your understanding of the header,
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; but I believe this will be the simplest method of defining your header,
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; as Marc's doesn't provide a full explanation, and Neviksti's can be
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; a bit more difficult for beginners (using the WLA directives is easier).
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;----------------------------------------------------------------------------
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;==LoRom== ; We'll get to HiRom some other time.
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.MEMORYMAP ; Begin describing the system architecture.
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SLOTSIZE $8000 ; The slot is $8000 bytes in size. More details on slots later.
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DEFAULTSLOT 0 ; There's only 1 slot in SNES, there are more in other consoles.
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SLOT 0 $8000 ; Define's Slot 0's starting address.
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.ENDME ; End MemoryMap definition
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.ROMBANKSIZE $8000 ; Every ROM bank is 32 KBytes in size
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.ROMBANKS 8 ; 2 Mbits - Tell WLA we want to use 8 ROM Banks
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.SNESHEADER
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ID "SNES" ; 1-4 letter string, just leave it as "SNES"
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NAME "SNES Tile Demo " ; Program Title - can't be over 21 bytes,
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; "123456789012345678901" ; use spaces for unused bytes of the name.
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SLOWROM
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LOROM
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CARTRIDGETYPE $00 ; $00 = ROM only, see WLA documentation for others
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ROMSIZE $08 ; $08 = 2 Mbits, see WLA doc for more..
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SRAMSIZE $00 ; No SRAM see WLA doc for more..
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COUNTRY $01 ; $01 = U.S. $00 = Japan, that's all I know
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LICENSEECODE $00 ; Just use $00
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VERSION $00 ; $00 = 1.00, $01 = 1.01, etc.
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.ENDSNES
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.SNESNATIVEVECTOR ; Define Native Mode interrupt vector table
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COP EmptyHandler
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BRK EmptyHandler
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ABORT EmptyHandler
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NMI EmptyHandler
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IRQ EmptyHandler
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.ENDNATIVEVECTOR
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.SNESEMUVECTOR ; Define Emulation Mode interrupt vector table
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COP EmptyHandler
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ABORT EmptyHandler
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NMI EmptyHandler
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RESET Start
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IRQBRK EmptyHandler
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.ENDEMUVECTOR
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.BANK 0 SLOT 0 ; Defines the ROM bank and the slot it is inserted in memory.
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.ORG 0 ; .ORG 0 is really $8000, because the slot starts at $8000
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.SECTION "EmptyVectors" SEMIFREE
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EmptyHandler:
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rti
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.ENDS
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.EMPTYFILL $00
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262
snes/banktest/init.inc
Normal file
262
snes/banktest/init.inc
Normal file
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;------------------------------------------------------------------------
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;- Written by: Neviksti
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;- If you use my code, please share your creations with me
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;- as I am always curious :)
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;------------------------------------------------------------------------
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;----------------------------------------------------------------------------
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; InitSNES -- my "standard" initialization of SNES memory and registers
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;----------------------------------------------------------------------------
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.MACRO InitSNES
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sei ;disable interrupts
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clc ;switch to native mode
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xce
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REP #$38 ; mem/A = 16 bit, X/Y = 16 bit
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;decimal mode off
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LDX #$1FFF ;Setup the stack
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TXS ;Transfer Index X to Stack Pointer Register
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;do the rest of the initialization in a routine
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JSL $008000
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SEP #$20 ; mem/A = 8 bit
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.ENDM
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;----------------------------------------------------------------------------
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.BANK 0 SLOT 0
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.ORG 0
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.SECTION "InitializeSNESCode" FORCE
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InitializeSNES:
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PHK ;set Data Bank = Program Bank
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PLB
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LDA #$0000 ;set Direct Page = $0000
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TCD ;Transfer Accumulator to Direct Register
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LDX $1FFD ;we clear all the mem at one point ...
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STX $4372 ;so save the return address in a place that won't get overwritten
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LDX $1FFF
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STX $4374
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SEP #$20 ; mem/A = 8 bit
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REP #$10
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LDA #$8F
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STA $2100 ;turn screen off for now, set brightness to normal
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LDX #$2101
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_Loop00: ;regs $2101-$210C
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STZ $00,X ;set Sprite,Character,Tile sizes to lowest, and set addresses to $0000
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INX
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CPX #$210D
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BNE _Loop00
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_Loop01: ;regs $210D-$2114
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STZ $00,X ;Set all BG scroll values to $0000
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STZ $00,X
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INX
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CPX #$2115
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BNE _Loop01
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LDA #$80 ;reg $2115
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STA $2115 ; Initialize VRAM transfer mode to word-access, increment by 1
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STZ $2116 ;regs $2117-$2117
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STZ $2117 ;VRAM address = $0000
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;reg $2118-$2119
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;VRAM write register... don't need to initialize
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STZ $211A ;clear Mode7 setting
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LDX #$211B
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_Loop02: ;regs $211B-$2120
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STZ $00,X ;clear out the Mode7 matrix values
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STZ $00,X
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INX
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CPX #$2121
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BNE _Loop02
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;reg $2121 - Color address, doesn't need initilaizing
|
||||||
|
;reg $2122 - Color data, is initialized later
|
||||||
|
|
||||||
|
LDX #$2123
|
||||||
|
_Loop03: ;regs $2123-$2133
|
||||||
|
STZ $00,X ;turn off windows, main screens, sub screens, color addition,
|
||||||
|
INX ;fixed color = $00, no super-impose (external synchronization),
|
||||||
|
CPX #$2134 ;no interlaced mode, normal resolution
|
||||||
|
BNE _Loop03
|
||||||
|
|
||||||
|
;regs $2134-$2136 - multiplication result, no initialization needed
|
||||||
|
;reg $2137 - software H/V latch, no initialization needed
|
||||||
|
;reg $2138 - Sprite data read, no initialization needed
|
||||||
|
;regs $2139-$213A - VRAM data read, no initialization needed
|
||||||
|
;reg $213B - Color RAM data read, no initialization needed
|
||||||
|
;regs $213C-$213D - H/V latched data read, no initialization needed
|
||||||
|
|
||||||
|
STZ $213E ;reg $213E - might not be necesary, but selects PPU master/slave mode
|
||||||
|
;reg $213F - PPU status flag, no initialization needed
|
||||||
|
|
||||||
|
;reg $2140-$2143 - APU communication regs, no initialization required
|
||||||
|
|
||||||
|
;reg $2180 - read/write WRAM register, no initialization required
|
||||||
|
;reg $2181-$2183 - WRAM address, no initialization required
|
||||||
|
|
||||||
|
;reg $4016-$4017 - serial JoyPad read registers, no need to initialize
|
||||||
|
|
||||||
|
|
||||||
|
STZ $4200 ;reg $4200 - disable timers, NMI,and auto-joyread
|
||||||
|
|
||||||
|
LDA #$FF
|
||||||
|
STA $4201 ;reg $4201 - programmable I/O write port, initalize to allow reading at in-port
|
||||||
|
|
||||||
|
;regs $4202-$4203 - multiplication registers, no initialization required
|
||||||
|
;regs $4204-$4206 - division registers, no initialization required
|
||||||
|
|
||||||
|
;regs $4207-$4208 - Horizontal-IRQ timer setting, since we disabled this, it is OK to not init
|
||||||
|
;regs $4209-$420A - Vertical-IRQ timer setting, since we disabled this, it is OK to not init
|
||||||
|
|
||||||
|
STZ $420B ;reg $420B - turn off all general DMA channels
|
||||||
|
STZ $420C ;reg $420C - turn off all H-MA channels
|
||||||
|
|
||||||
|
STZ $420D ;reg $420D - ROM access time to slow (2.68Mhz)
|
||||||
|
|
||||||
|
LDA $4210 ;reg $4210 - NMI status, reading resets
|
||||||
|
|
||||||
|
;reg $4211 - IRQ status, no need to initialize
|
||||||
|
;reg $4212 - H/V blank and JoyRead status, no need to initialize
|
||||||
|
;reg $4213 - programmable I/O inport, no need to initialize
|
||||||
|
|
||||||
|
;reg $4214-$4215 - divide results, no need to initialize
|
||||||
|
;reg $4216-$4217 - multiplication or remainder results, no need to initialize
|
||||||
|
|
||||||
|
;regs $4218-$421f - JoyPad read registers, no need to initialize
|
||||||
|
|
||||||
|
;regs $4300-$437F
|
||||||
|
;no need to intialize because DMA was disabled above
|
||||||
|
;also, we're not sure what all of the registers do, so it is better to leave them at
|
||||||
|
;their reset state value
|
||||||
|
|
||||||
|
JSR ClearVRAM ;Reset VRAM
|
||||||
|
JSR ClearPalette ;Reset colors
|
||||||
|
|
||||||
|
;**** clear Sprite tables ********
|
||||||
|
|
||||||
|
STZ $2102 ;sprites initialized to be off the screen, palette 0, character 0
|
||||||
|
STZ $2103
|
||||||
|
LDX #$0080
|
||||||
|
LDA #$F0
|
||||||
|
_Loop08:
|
||||||
|
STA $2104 ;set X = 240
|
||||||
|
STA $2104 ;set Y = 240
|
||||||
|
STZ $2104 ;set character = $00
|
||||||
|
STZ $2104 ;set priority=0, no flips
|
||||||
|
DEX
|
||||||
|
BNE _Loop08
|
||||||
|
|
||||||
|
LDX #$0020
|
||||||
|
_Loop09:
|
||||||
|
STZ $2104 ;set size bit=0, x MSB = 0
|
||||||
|
DEX
|
||||||
|
BNE _Loop09
|
||||||
|
|
||||||
|
;**** clear WRAM ********
|
||||||
|
|
||||||
|
STZ $2181 ;set WRAM address to $000000
|
||||||
|
STZ $2182
|
||||||
|
STZ $2183
|
||||||
|
|
||||||
|
LDX #$8008
|
||||||
|
STX $4300 ;Set DMA mode to fixed source, BYTE to $2180
|
||||||
|
LDX #wram_fill_byte
|
||||||
|
STX $4302 ;Set source offset
|
||||||
|
LDA #:wram_fill_byte
|
||||||
|
STA $4304 ;Set source bank
|
||||||
|
LDX #$0000
|
||||||
|
STX $4305 ;Set transfer size to 64k bytes
|
||||||
|
LDA #$01
|
||||||
|
STA $420B ;Initiate transfer
|
||||||
|
|
||||||
|
LDA #$01 ;now set the next 64k bytes
|
||||||
|
STA $420B ;Initiate transfer
|
||||||
|
|
||||||
|
PHK ;make sure Data Bank = Program Bank
|
||||||
|
PLB
|
||||||
|
|
||||||
|
CLI ;enable interrupts again
|
||||||
|
|
||||||
|
LDX $4372 ;get our return address...
|
||||||
|
STX $1FFD
|
||||||
|
LDA $4374
|
||||||
|
STA $1FFF
|
||||||
|
RTL
|
||||||
|
|
||||||
|
wram_fill_byte:
|
||||||
|
.db $00
|
||||||
|
|
||||||
|
;----------------------------------------------------------------------------
|
||||||
|
; ClearVRAM -- Sets every byte of VRAM to zero
|
||||||
|
; In: None
|
||||||
|
; Out: None
|
||||||
|
; Modifies: flags
|
||||||
|
;----------------------------------------------------------------------------
|
||||||
|
ClearVRAM:
|
||||||
|
pha
|
||||||
|
phx
|
||||||
|
php
|
||||||
|
|
||||||
|
REP #$30 ; mem/A = 8 bit, X/Y = 16 bit
|
||||||
|
SEP #$20
|
||||||
|
|
||||||
|
LDA #$80
|
||||||
|
STA $2115 ;Set VRAM port to word access
|
||||||
|
LDX #$1809
|
||||||
|
STX $4300 ;Set DMA mode to fixed source, WORD to $2118/9
|
||||||
|
LDX #$0000
|
||||||
|
STX $2116 ;Set VRAM port address to $0000
|
||||||
|
STX $0000 ;Set $00:0000 to $0000 (assumes scratchpad ram)
|
||||||
|
STX $4302 ;Set source address to $xx:0000
|
||||||
|
LDA #$00
|
||||||
|
STA $4304 ;Set source bank to $00
|
||||||
|
LDX #$FFFF
|
||||||
|
STX $4305 ;Set transfer size to 64k-1 bytes
|
||||||
|
LDA #$01
|
||||||
|
STA $420B ;Initiate transfer
|
||||||
|
|
||||||
|
STZ $2119 ;clear the last byte of the VRAM
|
||||||
|
|
||||||
|
plp
|
||||||
|
plx
|
||||||
|
pla
|
||||||
|
RTS
|
||||||
|
|
||||||
|
;----------------------------------------------------------------------------
|
||||||
|
; ClearPalette -- Reset all palette colors to zero
|
||||||
|
; In: None
|
||||||
|
; Out: None
|
||||||
|
; Modifies: flags
|
||||||
|
;----------------------------------------------------------------------------
|
||||||
|
ClearPalette:
|
||||||
|
PHX
|
||||||
|
PHP
|
||||||
|
REP #$30 ; mem/A = 8 bit, X/Y = 16 bit
|
||||||
|
SEP #$20
|
||||||
|
|
||||||
|
STZ $2121
|
||||||
|
LDX #$0100
|
||||||
|
ClearPaletteLoop:
|
||||||
|
STZ $2122
|
||||||
|
STZ $2122
|
||||||
|
DEX
|
||||||
|
BNE ClearPaletteLoop
|
||||||
|
|
||||||
|
PLP
|
||||||
|
PLX
|
||||||
|
RTS
|
||||||
|
|
||||||
|
.ENDS
|
||||||
169
snes/banktest/optixx.inc
Normal file
169
snes/banktest/optixx.inc
Normal file
@ -0,0 +1,169 @@
|
|||||||
|
; Created with eKid's pcx2snes converter ;
|
||||||
|
|
||||||
|
OptixxData:
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $03, $00, $0F, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $FF, $00, $FF, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $FE, $00, $FE, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $1F, $00, $1F, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $FF, $00, $FF, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $F0, $00, $FC, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $03, $00, $03, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $FF, $00, $FF, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $FF, $00, $FF, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $FE, $00, $FE, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $1F, $00, $1F, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $80, $00, $80, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $3F, $00, $3F, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $01, $00, $01, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $F8, $00, $F8, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $01, $00, $03, $00, $07, $00, $07, $00, $07, $00
|
||||||
|
.db $3F, $00, $7F, $00, $FF, $00, $FF, $00, $FC, $00, $F0, $00, $E0, $00, $E0, $00
|
||||||
|
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $00, $00, $00, $00, $01, $00, $01, $00
|
||||||
|
.db $FE, $00, $FC, $00, $FC, $00, $FC, $00, $FC, $00, $FC, $00, $F8, $00, $F8, $00
|
||||||
|
.db $1F, $00, $1F, $00, $3F, $00, $3F, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $FE, $00, $FF, $00, $FF, $00, $FF, $00, $3F, $00, $1F, $00, $0F, $00, $0F, $00
|
||||||
|
.db $03, $00, $03, $00, $87, $00, $C7, $00, $C0, $00, $C0, $00, $C0, $00, $C0, $00
|
||||||
|
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $FE, $00, $FC, $00, $FC, $00, $FC, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $1F, $00, $1F, $00, $3F, $00, $3F, $00, $3F, $00, $3F, $00, $3F, $00, $7E, $00
|
||||||
|
.db $80, $00, $80, $00, $80, $00, $00, $00, $03, $00, $03, $00, $03, $00, $07, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $F0, $00, $F0, $00, $F0, $00, $E0, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $3F, $00, $7E, $00, $7E, $00, $7E, $00, $7E, $00, $7E, $00, $FC, $00, $FC, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $1F, $00, $1F, $00, $1F, $00, $3F, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $80, $00, $80, $00, $80, $00, $00, $00
|
||||||
|
.db $01, $00, $03, $00, $03, $00, $03, $00, $03, $00, $03, $00, $07, $00, $07, $00
|
||||||
|
.db $F8, $00, $F0, $00, $F0, $00, $F0, $00, $F0, $00, $F0, $00, $E0, $00, $E0, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $0F, $00, $0F, $00, $0F, $00, $0F, $00, $1F, $00, $1F, $00, $1F, $00, $1F, $00
|
||||||
|
.db $C0, $00, $C0, $00, $C0, $00, $C0, $00, $80, $00, $80, $00, $80, $00, $80, $00
|
||||||
|
.db $01, $00, $01, $00, $03, $00, $03, $00, $03, $00, $03, $00, $03, $00, $07, $00
|
||||||
|
.db $F8, $00, $F8, $00, $F8, $00, $F0, $00, $F0, $00, $F0, $00, $F0, $00, $E0, $00
|
||||||
|
.db $00, $00, $00, $00, $7F, $00, $7F, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||||
|
.db $00, $00, $00, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||||
|
.db $0F, $00, $1F, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||||
|
.db $C0, $00, $C0, $00, $8A, $00, $8F, $00, $9F, $00, $9F, $00, $9F, $00, $1F, $00
|
||||||
|
.db $00, $00, $00, $00, $80, $00, $C0, $00, $80, $00, $80, $00, $80, $00, $80, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $7E, $00, $7E, $00, $7E, $00, $7E, $00, $FC, $00, $FC, $00, $FC, $00, $FC, $00
|
||||||
|
.db $07, $00, $07, $00, $07, $00, $07, $00, $07, $00, $03, $00, $07, $00, $0F, $00
|
||||||
|
.db $E0, $00, $F0, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||||
|
.db $00, $00, $01, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||||
|
.db $FC, $00, $FC, $00, $F8, $00, $F8, $00, $F0, $00, $E0, $00, $F0, $00, $F0, $00
|
||||||
|
.db $3F, $00, $3F, $00, $3F, $00, $3F, $00, $3F, $00, $1F, $00, $3F, $00, $7F, $00
|
||||||
|
.db $00, $00, $80, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||||
|
.db $07, $00, $0F, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||||
|
.db $E0, $00, $E0, $00, $C0, $00, $C0, $00, $80, $00, $00, $00, $80, $00, $80, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $3F, $00, $3F, $00, $3F, $00, $3F, $00, $3F, $00, $7E, $00, $7E, $00, $7F, $00
|
||||||
|
.db $80, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $FF, $00
|
||||||
|
.db $07, $00, $07, $00, $07, $00, $0F, $00, $0F, $00, $3F, $00, $7F, $00, $FF, $00
|
||||||
|
.db $E1, $00, $E1, $00, $E1, $00, $E1, $00, $C1, $00, $C3, $00, $83, $00, $03, $00
|
||||||
|
.db $FC, $00, $F8, $00, $F8, $00, $F8, $00, $F8, $00, $F8, $00, $F0, $00, $F0, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $3F, $00, $3F, $00, $3F, $00, $3F, $00, $3F, $00, $3F, $00, $3F, $00, $1F, $00
|
||||||
|
.db $80, $00, $00, $00, $00, $00, $00, $00, $00, $00, $80, $00, $C0, $00, $FF, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $F0, $00
|
||||||
|
.db $01, $00, $01, $00, $01, $00, $01, $00, $01, $00, $03, $00, $03, $00, $03, $00
|
||||||
|
.db $FC, $00, $F8, $00, $F8, $00, $F8, $00, $F8, $00, $F8, $00, $F0, $00, $F0, $00
|
||||||
|
.db $0F, $00, $1F, $00, $1F, $00, $1F, $00, $1F, $00, $3F, $00, $3F, $00, $3F, $00
|
||||||
|
.db $C0, $00, $C0, $00, $80, $00, $80, $00, $80, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $07, $00, $03, $00, $03, $00, $03, $00, $07, $00, $07, $00, $07, $00, $00, $00
|
||||||
|
.db $F0, $00, $F0, $00, $F0, $00, $F0, $00, $E0, $00, $E1, $00, $E1, $00, $01, $00
|
||||||
|
.db $7E, $00, $FE, $00, $FC, $00, $FC, $00, $FC, $00, $F8, $00, $F8, $00, $F8, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $3F, $00, $1F, $00, $1F, $00, $1F, $00, $3F, $00, $3F, $00, $3F, $00, $00, $00
|
||||||
|
.db $80, $00, $80, $00, $80, $00, $80, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $7F, $00, $7F, $00, $FF, $00, $FF, $00, $FF, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $FE, $00, $FC, $00, $F8, $00, $E0, $00, $80, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $03, $00, $03, $00, $03, $00, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $F0, $00, $F0, $00, $E0, $00, $E0, $00, $E0, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $1F, $00, $0F, $00, $07, $00, $03, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $E0, $00, $E0, $00, $E0, $00, $E0, $00, $C0, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $03, $00, $03, $00, $03, $00, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $F0, $00, $F0, $00, $E0, $00, $E0, $00, $E0, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $3F, $00, $3F, $00, $3E, $00, $1E, $00, $0E, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $01, $00, $01, $00, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $F8, $00, $F8, $00, $F0, $00, $F0, $00, $70, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
.db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
|
||||||
|
|
||||||
|
OptixxPalette:
|
||||||
|
.db $DE, $7B, $00, $00, $00, $00, $00, $00
|
||||||
|
|
||||||
|
; 160 tiles (0 spaces)
|
||||||
|
; 2560 bytes
|
||||||
BIN
snes/banktest/optixx.pcx
Normal file
BIN
snes/banktest/optixx.pcx
Normal file
Binary file not shown.
91
snes/banktest/vram2.asm
Normal file
91
snes/banktest/vram2.asm
Normal file
@ -0,0 +1,91 @@
|
|||||||
|
;============================================================================
|
||||||
|
; Includes
|
||||||
|
;============================================================================
|
||||||
|
|
||||||
|
;== Include MemoryMap, Vector Table, and HeaderInfo ==
|
||||||
|
.INCLUDE "header.inc"
|
||||||
|
|
||||||
|
;== Include SNES Initialization routines ==
|
||||||
|
.INCLUDE "init.inc"
|
||||||
|
.INCLUDE "LoadGraphics.asm"
|
||||||
|
|
||||||
|
|
||||||
|
;============================================================================
|
||||||
|
; Main Code
|
||||||
|
;============================================================================
|
||||||
|
|
||||||
|
.BANK 0 SLOT 0
|
||||||
|
.ORG 0
|
||||||
|
.SECTION "MainCode"
|
||||||
|
|
||||||
|
Start:
|
||||||
|
InitSNES ; Clear registers, etc.
|
||||||
|
|
||||||
|
; Load Palette for our tiles
|
||||||
|
LoadPalette OptixxPalette, 0, 16
|
||||||
|
|
||||||
|
; Load Tile data to VRAM
|
||||||
|
;LoadBlockToVRAM TilesData, $0000, $0020 ; 2 tiles, 2bpp, = 32 bytes
|
||||||
|
LoadBlockToVRAM OptixxData, $0000, 0xa00 ; 160 tiles, 2bpp, = 2560 bytes
|
||||||
|
|
||||||
|
lda #$80
|
||||||
|
sta $2115
|
||||||
|
ldx #$0800 ; 5AF
|
||||||
|
stx $2116
|
||||||
|
|
||||||
|
ldx #$0
|
||||||
|
Start_do:
|
||||||
|
stx $2118
|
||||||
|
inx
|
||||||
|
cpx #160
|
||||||
|
bne Start_do
|
||||||
|
|
||||||
|
; Setup Video modes and other stuff, then turn on the screen
|
||||||
|
jsr SetupVideo
|
||||||
|
|
||||||
|
Infinity:
|
||||||
|
jmp Infinity ; bwa hahahahaha
|
||||||
|
|
||||||
|
|
||||||
|
;============================================================================
|
||||||
|
; SetupVideo -- Sets up the video mode and tile-related registers
|
||||||
|
;----------------------------------------------------------------------------
|
||||||
|
; In: None
|
||||||
|
;----------------------------------------------------------------------------
|
||||||
|
; Out: None
|
||||||
|
;----------------------------------------------------------------------------
|
||||||
|
SetupVideo:
|
||||||
|
php
|
||||||
|
|
||||||
|
lda #$00
|
||||||
|
sta $2105 ; Set Video mode 0, 8x8 tiles, 4 color BG1/BG2/BG3/BG4
|
||||||
|
|
||||||
|
lda #$08 ; Set BG1's Tile Map offset to $0400 (Word address)
|
||||||
|
sta $2107 ; And the Tile Map size to 32x32
|
||||||
|
|
||||||
|
stz $210B ; Set BG1's Character VRAM offset to $0000 (word address)
|
||||||
|
|
||||||
|
lda #$01 ; Enable BG1
|
||||||
|
sta $212C
|
||||||
|
|
||||||
|
lda #$FF
|
||||||
|
sta $210E
|
||||||
|
sta $210E
|
||||||
|
|
||||||
|
lda #$0F
|
||||||
|
sta $2100 ; Turn on screen, full Brightness
|
||||||
|
|
||||||
|
plp
|
||||||
|
rts
|
||||||
|
;============================================================================
|
||||||
|
.ENDS
|
||||||
|
|
||||||
|
;============================================================================
|
||||||
|
; Character Data
|
||||||
|
;============================================================================
|
||||||
|
|
||||||
|
.BANK 7 SLOT 0
|
||||||
|
.ORG 0
|
||||||
|
.SECTION "CharacterData01"
|
||||||
|
.INCLUDE "optixx.inc"
|
||||||
|
.ENDS
|
||||||
Loading…
x
Reference in New Issue
Block a user