add timer and more debug code
This commit is contained in:
parent
fef90c7f6e
commit
c55a66f90d
@ -8,7 +8,7 @@ AVRDUDE = avrdude -c usbasp -p $(DEVICE)
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CFLAGS = -Iusbdrv -I. -DDEBUG_LEVEL=0
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CFLAGS = -Iusbdrv -I. -DDEBUG_LEVEL=0
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#-std=gnu99
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#-std=gnu99
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OBJECTS = usbdrv/usbdrv.o usbdrv/usbdrvasm.o usbdrv/oddebug.o main.o usb_bulk.o uart.o fifo.o sram.o crc.o debug.o dump.o
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OBJECTS = usbdrv/usbdrv.o usbdrv/usbdrvasm.o usbdrv/oddebug.o main.o usb_bulk.o uart.o fifo.o sram.o crc.o debug.o dump.o timer.o
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COMPILE = avr-gcc -Wall -Os -DF_CPU=$(F_CPU) $(CFLAGS) -mmcu=$(DEVICE)
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COMPILE = avr-gcc -Wall -Os -DF_CPU=$(F_CPU) $(CFLAGS) -mmcu=$(DEVICE)
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@ -15,6 +15,7 @@
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#include "dump.h"
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#include "dump.h"
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#include "crc.h"
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#include "crc.h"
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#include "usb_bulk.h"
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#include "usb_bulk.h"
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#include "timer.h"
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extern FILE uart_stdout;
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extern FILE uart_stdout;
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@ -109,6 +110,10 @@ usbMsgLen_t usbFunctionSetup(uchar data[8])
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req_bank_size = (1 << rq->wValue.word) & 0xffff;
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req_bank_size = (1 << rq->wValue.word) & 0xffff;
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sync_errors = 0;
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sync_errors = 0;
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debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: bank_size=0x%x\n", req_bank_size);
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debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: bank_size=0x%x\n", req_bank_size);
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if (req_addr == 0x000000){
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debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: timer_start\n");
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timer_start();
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}
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/*
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/*
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* -------------------------------------------------------------------------
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* -------------------------------------------------------------------------
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*/
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*/
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@ -119,12 +124,14 @@ usbMsgLen_t usbFunctionSetup(uchar data[8])
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req_addr = req_addr << 16;
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req_addr = req_addr << 16;
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req_addr = req_addr | rq->wIndex.word;
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req_addr = req_addr | rq->wIndex.word;
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sram_bulk_write_start(req_addr);
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sram_bulk_write_start(req_addr);
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//debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx \n",req_bank,req_addr);
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rx_remaining = rq->wLength.word;
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rx_remaining = rq->wLength.word;
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if (req_addr && req_addr % req_bank_size == 0) {
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if (req_addr && req_addr % req_bank_size == 0) {
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debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr= 0x%08lx \n",
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debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr= 0x%08lx time=%i\n",
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req_bank, req_addr);
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req_bank, req_addr,timer_stop());
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req_bank++;
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req_bank++;
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timer_start();
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}
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}
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ret_len = USB_MAX_TRANS;
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ret_len = USB_MAX_TRANS;
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@ -293,7 +300,7 @@ int main(void)
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system_init();
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system_init();
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printf("Sytem Init\n");
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printf("Sytem Init\n");
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avr_bus_active();
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usbInit();
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usbInit();
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printf("USB Init\n");
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printf("USB Init\n");
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usbDeviceDisconnect(); /* enforce re-enumeration, do this while
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usbDeviceDisconnect(); /* enforce re-enumeration, do this while
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@ -311,38 +318,62 @@ int main(void)
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led_on();
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led_on();
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usbDeviceConnect();
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usbDeviceConnect();
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printf("USB connect\n");
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printf("USB connect\n");
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avr_bus_active();
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printf("Activate AVR bus\n");
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printf("IRQ off\n");
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snes_irq_lo();
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snes_irq_off();
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printf("Set Snes lowrom\n");
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snes_lorom();
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printf("Disable snes WR\n");
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snes_wr_disable();
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sei();
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sei();
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printf("USB poll\n");
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printf("USB poll\n");
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while (req_state != REQ_STATUS_BOOT){
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while (req_state != REQ_STATUS_BOOT){
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usbPoll();
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usbPoll();
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}
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}
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printf("USB poll done\n");
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printf("USB poll done\n");
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usbDeviceDisconnect();
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usbDeviceDisconnect();
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printf("USB disconnect\n");
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printf("USB disconnect\n");
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crc_check_bulk_memory(0x000000, 0x80000);
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crc_check_bulk_memory(0x000000, 0x80000);
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#if 0
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//dump_memory(0x7f00,0x8000);
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dump_memory(0x0000,0x0080);
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printf("crc=0x%x\n",crc_check_bulk_memory(0x000000, 0x80));
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#endif
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dump_memory(0x7f00,0x8000);
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printf("IRQ off\n");
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snes_irq_lo();
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snes_irq_off();
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printf("Set Snes lowrom\n");
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snes_lorom();
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printf("Disable snes WR\n");
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printf("Disable snes WR\n");
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snes_wr_disable();
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snes_wr_disable();
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printf("Use Snes lowrom\n");
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snes_lorom();
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printf("IRQ off\n");
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snes_irq_off();
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printf("Activate Snes bus\n");
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snes_bus_active();
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snes_bus_active();
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printf("Activate Snes bus\n");
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#if 0
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i = 50;
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while (--i) { /* fake USB disconnect for > 250 ms */
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_delay_ms(100);
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printf(".");
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}
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printf("\n");
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avr_bus_active();
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printf("Activate AVR bus\n");
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crc_check_bulk_memory(0x000000, 0x80000);
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#endif
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while(1);
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while(1);
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return 0;
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return 0;
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}
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}
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@ -28,13 +28,15 @@ void system_init(void)
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DDRC &= ~ (1 << SNES_WR_PIN);
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DDRC &= ~ (1 << SNES_WR_PIN);
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PORTC &= ~((1 << AVR_ADDR_LATCH_PIN)
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PORTC &= ~((1 << AVR_ADDR_LATCH_PIN)
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| (1 << AVR_ADDR_SCK_PIN));
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| (1 << AVR_ADDR_SCK_PIN)
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| (1 << SNES_WR_PIN));
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PORTC |= ( (1 << AVR_ADDR_DOWN_PIN)
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PORTC |= ( (1 << AVR_ADDR_DOWN_PIN)
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| (1 << AVR_ADDR_UP_PIN)
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| (1 << AVR_ADDR_UP_PIN)
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| (1 << AVR_ADDR_LOAD_PIN)
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| (1 << AVR_ADDR_LOAD_PIN));
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| (1 << SNES_WR_PIN));
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//| (1 << SNES_WR_PIN));
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/*-------------------------------------------------*/
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/*-------------------------------------------------*/
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DDRB |= ( (1 << AVR_RD_PIN)
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DDRB |= ( (1 << AVR_RD_PIN)
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@ -42,10 +44,12 @@ void system_init(void)
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| (1 << AVR_CS_PIN)
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| (1 << AVR_CS_PIN)
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| (1 << SNES_IRQ_PIN));
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| (1 << SNES_IRQ_PIN));
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PORTB |= ( (1 << AVR_RD_PIN)
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PORTB |= ( (1 << AVR_RD_PIN)
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| (1 << AVR_WR_PIN)
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| (1 << AVR_WR_PIN)
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| (1 << AVR_CS_PIN)
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| (1 << AVR_CS_PIN)
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| (1 << SNES_IRQ_PIN));
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| (1 << SNES_IRQ_PIN));
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/*-------------------------------------------------*/
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/*-------------------------------------------------*/
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@ -56,8 +56,12 @@
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#define SNES_IRQ_DIR DDRB
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#define SNES_IRQ_DIR DDRB
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#define SNES_IRQ_PIN PB3
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#define SNES_IRQ_PIN PB3
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#define snes_irq_off() (SNES_IRQ_PORT |= (1 << SNES_IRQ_PIN))
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#define snes_irq_on() (SNES_IRQ_PORT &= ~(1 << SNES_IRQ_PIN))
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#define snes_irq_on() (SNES_IRQ_DIR |= (1 << SNES_IRQ_PIN))
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#define snes_irq_hi() (SNES_IRQ_PORT |= (1 << SNES_IRQ_PIN))
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#define snes_irq_off() (SNES_IRQ_DIR &= ~(1 << SNES_IRQ_PIN))
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#define snes_irq_lo() (SNES_IRQ_PORT &= ~(1 << SNES_IRQ_PIN))
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@ -120,9 +124,11 @@
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#define AVR_SNES_SW_PIN PD5
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#define AVR_SNES_SW_PIN PD5
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#define avr_bus_active() ((AVR_SNES_SW_PORT &= ~(1 << AVR_SNES_SW_PIN)),\
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#define avr_bus_active() ((AVR_SNES_SW_PORT &= ~(1 << AVR_SNES_SW_PIN)),\
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(HI_LOROM_SW_PORT |= (1 << HI_LOROM_SW_PIN)))
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(HI_LOROM_SW_PORT |= (1 << HI_LOROM_SW_PIN)),\
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(AVR_CS_DIR |= (1 << AVR_CS_PIN)))
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#define snes_bus_active() (AVR_SNES_SW_PORT |= (1 << AVR_SNES_SW_PIN))
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#define snes_bus_active() ((AVR_SNES_SW_PORT |= (1 << AVR_SNES_SW_PIN)),\
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(AVR_CS_DIR &= ~(1 << AVR_CS_PIN)))
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#define HI_LOROM_SW_PORT PORTD
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#define HI_LOROM_SW_PORT PORTD
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#define HI_LOROM_SW_DIR DDRD
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#define HI_LOROM_SW_DIR DDRD
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@ -136,6 +142,7 @@
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#define SNES_WR_EN_PIN PD7
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#define SNES_WR_EN_PIN PD7
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#define snes_wr_disable() (SNES_WR_EN_PORT &= ~(1 << SNES_WR_EN_PIN))
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#define snes_wr_disable() (SNES_WR_EN_PORT &= ~(1 << SNES_WR_EN_PIN))
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#define snes_wr_enable() (SNES_WR_EN_PORT |= (1 << SNES_WR_EN_PIN))
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#define snes_wr_enable() (SNES_WR_EN_PORT |= (1 << SNES_WR_EN_PIN))
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@ -1,6 +1,6 @@
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#include <io.h>
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#include <interrupt.h>
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#include <avr/io.h>
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#include <signal.h>
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#include <avr/interrupt.h> /* for sei() */
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#ifndef OCR1A
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#ifndef OCR1A
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@ -12,26 +12,26 @@
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#endif
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#endif
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//#define XTAL 11059201L // nominal value
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//#define XTAL 11059201L // nominal value
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#define XTAL 20000000L
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#define XTAL 20000000UL
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#define DEBOUNCE 256L // debounce clock (256Hz = 4msec)
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#define DEBOUNCE 500UL // debounce clock (256Hz = 4msec)
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#define uint8_t unsigned char
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#define uint8_t unsigned char
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#define uint unsigned int
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#define uint unsigned int
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uint8_t prescaler;
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uint16_t prescaler;
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uint8_t volatile second; // count seconds
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uint16_t volatile second; // count seconds
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SIGNAL (SIG_OUTPUT_COMPARE1A)
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ISR (SIG_OUTPUT_COMPARE1A)
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{
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{
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#if XTAL % DEBOUNCE // bei rest
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#if XTAL % DEBOUNCE // bei rest
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OCR1A = XTAL / DEBOUNCE - 1; // compare DEBOUNCE - 1 times
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OCR1A = 20000000UL / DEBOUNCE - 1; // compare DEBOUNCE - 1 times
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#endif
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#endif
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if( --prescaler == 0 ){
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if( --prescaler == 0 ){
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prescaler = (uint8_t)DEBOUNCE;
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prescaler = (uint16_t)DEBOUNCE;
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second++; // exact one second over
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second++; // exact one second over
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#if XTAL % DEBOUNCE // handle remainder
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#if XTAL % DEBOUNCE // handle remainder
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OCR1A = XTAL / DEBOUNCE + XTAL % DEBOUNCE - 1; // compare once per second
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OCR1A = XTAL / DEBOUNCE + XTAL % DEBOUNCE - 1; // compare once per second
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@ -39,24 +39,24 @@ SIGNAL (SIG_OUTPUT_COMPARE1A)
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}
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}
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}
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}
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void timer_start( void )
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uint16_t timer_start( void )
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{
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{
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TCCR1B = (1<<WGM12) | (1<<CS10); // divide by 1
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TCCR1B = (1<<WGM12) | (1<<CS10); // divide by 1
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// clear on compare
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// clear on compare
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OCR1A = XTAL / DEBOUNCE - 1; // Output Compare Register
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OCR1A = XTAL / DEBOUNCE - 1UL; // Output Compare Register
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TCNT1 = 0; // Timmer startet mit 0
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TCNT1 = 0; // Timmer startet mit 0
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second = 0;
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second = 0;
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prescaler = (uint8_t)DEBOUNCE; //software teiler
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prescaler = (uint16_t)DEBOUNCE; //software teiler
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TIMSK = 1<<OCIE1A; // beim Vergleichswertes Compare Match
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TIMSK1 = 1<<OCIE1A; // beim Vergleichswertes Compare Match
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// Interrupt (SIG_OUTPUT_COMPARE1A)
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// Interrupt (SIG_OUTPUT_COMPARE1A)
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sei();
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sei();
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}
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}
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uint16_t timer_stop(void)
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uint16_t timer_stop(void)
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{
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{
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cli():
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//cli();
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return second
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return second;
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}
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}
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