FPGA: fix BS-X mapping, S-RTC interface
This commit is contained in:
ikari
parent
bfe9a91d07
commit
04bc32de86
@ -36,6 +36,7 @@ module address(
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input [23:0] ROM_MASK,
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input use_msu,
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output msu_enable,
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output srtc_enable,
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output use_bsx,
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input [14:0] bsx_regs
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);
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@ -126,13 +127,13 @@ assign SRAM_ADDR_FULL = (MODE) ? MCU_ADDR
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: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK))
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:(MAPPER == 3'b011) ?
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(IS_SAVERAM ? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
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: IS_WRITABLE ? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
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: IS_WRITABLE ? (24'h400000 + (SNES_ADDR & 24'h0FFFFF /*7ffff*/))
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: ((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
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|(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
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? (24'h800000 + ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]} & 24'h0FFFFF))
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: ((bsx_regs[1] ? 24'h400000 : 24'h000000)
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+ bsx_regs[2] ? ({2'b00, SNES_ADDR[21:0]} & (ROM_MASK >> bsx_regs[1]))
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: ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]} & (ROM_MASK >> bsx_regs[1]))))
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+ bsx_regs[2] ? ({2'b00, SNES_ADDR[21:0]} & (ROM_MASK /* >> bsx_regs[1] */))
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: ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]} & (ROM_MASK /* >> bsx_regs[1] */))))
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:(MAPPER == 3'b110) ?
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(IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
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: (SNES_ADDR[15] ? ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
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@ -151,4 +152,6 @@ assign ROM_ADDR0 = SRAM_ADDR_FULL[0];
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assign msu_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
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assign use_bsx = (MAPPER == 3'b011);
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assign srtc_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
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endmodule
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@ -39,7 +39,7 @@ always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
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wire sysclk_rising = (sysclk_sreg == 2'b01);
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always @(posedge clk) begin
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if(sysclk_counter < 92000000) begin
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if(sysclk_counter < 96000000) begin
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sysclk_counter <= sysclk_counter + 1;
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if(sysclk_rising) sysclk_value <= sysclk_value + 1;
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end else begin
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@ -39,8 +39,11 @@ module data(
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input [7:0] MSU_DATA_OUT,
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output [7:0] BSX_DATA_IN,
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input [7:0] BSX_DATA_OUT,
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output [7:0] SRTC_DATA_IN,
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input [7:0] SRTC_DATA_OUT,
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input msu_enable,
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input bsx_data_ovr
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input bsx_data_ovr,
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input srtc_enable
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);
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reg [7:0] SNES_IN_MEM;
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@ -52,9 +55,11 @@ wire [7:0] FROM_ROM_BYTE;
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assign MSU_DATA_IN = SNES_DATA;
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assign BSX_DATA_IN = SNES_DATA;
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assign SRTC_DATA_IN = SNES_DATA;
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assign SNES_DATA = SNES_READ ? 8'bZ : (!MCU_OVR ? 8'h00 : (msu_enable ? MSU_DATA_OUT :
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bsx_data_ovr ? BSX_DATA_OUT : SNES_OUT_MEM));
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bsx_data_ovr ? BSX_DATA_OUT :
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srtc_enable ? SRTC_DATA_OUT : SNES_OUT_MEM));
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assign FROM_ROM_BYTE = (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
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@ -1,5 +1,5 @@
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NET "CLKIN" TNM_NET = "CLKIN";
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TIMESPEC TS_CLKIN = PERIOD "CLKIN" 23 MHz HIGH 50 %;
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TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %;
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//TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
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NET "SNES_CS" IOSTANDARD = LVCMOS33;
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NET "SNES_READ" IOSTANDARD = LVCMOS33;
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@ -416,7 +416,7 @@ NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33;
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NET "SNES_ADDR[9]" DRIVE = 8;
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NET "SNES_CPU_CLK" LOC = P94;
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NET "SNES_CPU_CLK" LOC = P95;
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NET "SNES_CS" LOC = P116;
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NET "SNES_DATABUS_DIR" LOC = P111;
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NET "SNES_DATABUS_OE" LOC = P109;
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@ -443,7 +443,7 @@ NET "SNES_DATA[7]" DRIVE = 8;
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NET "SNES_IRQ" LOC = P114;
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NET "SNES_READ" LOC = P115;
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NET "SNES_REFRESH" LOC = P155;
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NET "SNES_WRITE" LOC = P95;
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NET "SNES_WRITE" LOC = P94;
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NET "SPI_MISO" LOC = P72;
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@ -114,8 +114,9 @@ wire [7:0] bsx_regs_set_bits;
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wire [59:0] rtc_data;
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wire [59:0] rtc_data_in;
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wire [7:0] RTC_SNES_DATA_IN;
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wire [7:0] RTC_SNES_DATA_OUT;
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wire [59:0] srtc_rtc_data_out;
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wire [7:0] SRTC_SNES_DATA_IN;
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wire [7:0] SRTC_SNES_DATA_OUT;
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//wire SD_DMA_EN; //SPI_DMA_CTRL;
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@ -148,11 +149,28 @@ dac snes_dac(.clkin(CLK2),
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.reset(dac_reset)
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);
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srtc snes_srtc (
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.clkin(CLK2),
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/*XXX*/.reg_addr(srtc_reg_addr),
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.addr_in(SNES_ADDR[0]),
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.data_in(SRTC_SNES_DATA_IN),
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.data_out(SRTC_SNES_DATA_OUT),
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.rtc_data_in(rtc_data),
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.reg_we(SNES_WRITE),
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.reg_oe(SNES_READ),
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.enable(srtc_enable),
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.rtc_data_out(srtc_rtc_data_out),
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.rtc_we(srtc_rtc_we),
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.reset(srtc_reset)
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);
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rtc snes_rtc (
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.clkin(CLKIN),
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.rtc_data(rtc_data),
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.rtc_data_in(rtc_data_in),
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.pgm_we(rtc_pgm_we)
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.pgm_we(rtc_pgm_we),
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.rtc_data_in1(srtc_rtc_data_out),
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.we1(srtc_rtc_we)
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);
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msu snes_msu (
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@ -260,7 +278,8 @@ mcu_cmd snes_mcu_cmd(
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.bsx_regs_reset_out(bsx_regs_reset_bits),
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.bsx_regs_reset_we(bsx_regs_reset_we),
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.rtc_data_out(rtc_data_in),
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.rtc_pgm_we(rtc_pgm_we)
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.rtc_pgm_we(rtc_pgm_we),
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.srtc_reset(srtc_reset)
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);
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// dcm1: dfs 4x
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@ -368,7 +387,9 @@ address snes_addr(
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.msu_enable(msu_enable),
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//BS-X
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.use_bsx(use_bsx),
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.bsx_regs(bsx_regs)
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.bsx_regs(bsx_regs),
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//SRTC
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.srtc_enable(srtc_enable)
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);
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wire SNES_READ_CYCLEw;
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@ -396,8 +417,11 @@ data snes_data(.CLK(CLK2),
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.MSU_DATA_OUT(MSU_SNES_DATA_OUT),
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.BSX_DATA_IN(BSX_SNES_DATA_IN),
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.BSX_DATA_OUT(BSX_SNES_DATA_OUT),
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.SRTC_DATA_IN(SRTC_SNES_DATA_IN),
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.SRTC_DATA_OUT(SRTC_SNES_DATA_OUT),
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.msu_enable(msu_enable),
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.bsx_data_ovr(bsx_data_ovr)
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.bsx_data_ovr(bsx_data_ovr),
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.srtc_enable(srtc_enable)
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);
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parameter MODE_SNES = 1'b0;
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@ -515,6 +539,7 @@ always @(posedge CLK2) begin
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end else begin
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case (STATE)
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STATE_0: begin
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SNES_WRITE_CYCLE <= SNES_WRITE;
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STATE <= STATE_1; STATEIDX <= 11;
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end
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STATE_1: begin
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@ -634,7 +659,8 @@ assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
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//assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
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assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
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bsx_data_ovr ? 1'b0 : ((IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR) | (SNES_READ & SNES_WRITE));
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bsx_data_ovr ? 1'b0 :
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srtc_enable ? 1'b0 : ((IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR) | (SNES_READ & SNES_WRITE));
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assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
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assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
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@ -80,6 +80,9 @@ module mcu_cmd(
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output [55:0] rtc_data_out,
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output rtc_pgm_we,
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// S-RTC
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output srtc_reset,
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// SNES sync/clk
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input snes_sysclk
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);
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@ -118,6 +121,8 @@ reg bsx_regs_reset_we_buf;
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reg [55:0] rtc_data_out_buf;
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reg rtc_pgm_we_buf;
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reg srtc_reset_buf;
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reg [31:0] SNES_SYSCLK_FREQ_BUF;
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reg [7:0] MCU_DATA_OUT_BUF;
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@ -332,7 +337,15 @@ always @(posedge clk) begin
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32'h4:
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bsx_regs_reset_we_buf <= 1'b0;
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endcase
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8'he7:
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case (spi_byte_cnt)
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32'h2: begin
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srtc_reset_buf <= 1'b1;
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end
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32'h3: begin
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srtc_reset_buf <= 1'b0;
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end
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endcase
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endcase
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end
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if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[3]) && (spi_byte_cnt > (32'h1+cmd_data[4])))) begin
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@ -447,6 +460,8 @@ assign bsx_regs_set_out = bsx_regs_set_out_buf;
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assign rtc_data_out = rtc_data_out_buf;
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assign rtc_pgm_we = rtc_pgm_we_buf;
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assign srtc_reset = srtc_reset_buf;
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assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
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assign mcu_mapper = MAPPER_BUF;
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assign mcu_sram_size = SRAM_SIZE_BUF;
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@ -22,6 +22,8 @@ module rtc (
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input clkin,
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input pgm_we,
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input [59:0] rtc_data_in,
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input we1,
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input [59:0] rtc_data_in1,
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output [59:0] rtc_data
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);
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@ -32,11 +34,15 @@ reg [1:0] pgm_we_sreg;
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always @(posedge clkin) pgm_we_sreg <= {pgm_we_sreg[0], pgm_we};
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wire pgm_we_rising = (pgm_we_sreg[1:0] == 2'b01);
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reg [2:0] we1_sreg;
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always @(posedge clkin) we1_sreg <= {we1_sreg[1:0], we1};
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wire we1_rising = (we1_sreg[2:1] == 2'b01);
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reg [31:0] tick_cnt;
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always @(posedge clkin) begin
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tick_cnt <= tick_cnt + 1;
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if(tick_cnt == 23000000) tick_cnt <= 0;
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if((tick_cnt == 24000000) || pgm_we_rising) tick_cnt <= 0;
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end
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assign rtc_data = rtc_data_out_r;
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@ -97,7 +103,7 @@ initial begin
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dom1[10] <= 0; dom10[10] <= 3;
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dom1[11] <= 1; dom10[11] <= 3;
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month <= 0;
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rtc_data_r <= 60'h019900101000000;
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rtc_data_r <= 60'h220110301000000;
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tick_cnt <= 0;
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end
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@ -163,6 +169,8 @@ end
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always @(posedge clkin) begin
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if(pgm_we_rising) begin
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rtc_data_r <= rtc_data_in;
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end else if (we1_rising) begin
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rtc_data_r <= rtc_data_in1;
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end else begin
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case(rtc_state)
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STATE_SEC1: begin
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@ -113,7 +113,7 @@
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<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Add I/O Pads" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Advanced FSM Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -123,7 +123,7 @@
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<property xil_pn:name="Auto Constrain" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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@ -216,7 +216,7 @@
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<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -267,7 +267,7 @@
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<property xil_pn:name="Key 5 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance with IOB Packing;/mnt/store/bin/Xilinx/12.3/ISE_DS/ISE/spartan3/data/spartan3_performance_with_iobpacking.xds" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance without IOB Packing;/mnt/store/bin/Xilinx/12.3/ISE_DS/ISE/spartan3/data/spartan3_performance_without_iobpacking.xds" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -309,7 +309,7 @@
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<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
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<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
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<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
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@ -337,8 +337,8 @@
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<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
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<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Parallel Case" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@ -372,7 +372,7 @@
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Set/Reset (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
@ -395,7 +395,7 @@
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Resource Sharing Precision" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing Synthesis" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
@ -487,7 +487,7 @@
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/mnt/store/bin/Xilinx/12.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/mnt/store/bin/Xilinx/12.3/ISE_DS/ISE/spartan3/data/spartan3_performance_with_iobpacking.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
|
||||
186
verilog/sd2snes/srtc.v
Normal file
186
verilog/sd2snes/srtc.v
Normal file
@ -0,0 +1,186 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 13:33:14 02/09/2011
|
||||
// Design Name:
|
||||
// Module Name: srtc
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module srtc(
|
||||
input clkin,
|
||||
input [4:0] reg_addr,
|
||||
input addr_in,
|
||||
input [7:0] data_in,
|
||||
output [7:0] data_out,
|
||||
input [59:0] rtc_data_in,
|
||||
output [59:0] rtc_data_out,
|
||||
input reg_we,
|
||||
input reg_oe,
|
||||
input enable,
|
||||
output rtc_we,
|
||||
input reset
|
||||
);
|
||||
|
||||
reg rtc_dirty_r;
|
||||
assign rtc_dirty = rtc_dirty_r;
|
||||
|
||||
reg [59:0] rtc_data_r;
|
||||
reg [59:0] rtc_data_out_r;
|
||||
assign rtc_data_out = rtc_data_out_r;
|
||||
|
||||
reg [3:0] rtc_ptr;
|
||||
|
||||
reg [7:0] data_out_r;
|
||||
reg [7:0] data_in_r;
|
||||
reg [4:0] mode_r;
|
||||
reg [3:0] command_r;
|
||||
reg rtc_we_r;
|
||||
assign rtc_we = rtc_we_r;
|
||||
assign data_out = data_out_r;
|
||||
|
||||
reg [5:0] reg_oe_sreg;
|
||||
always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe};
|
||||
wire reg_oe_falling = (reg_oe_sreg[5:0] == 6'b100000);
|
||||
wire reg_oe_rising = (reg_oe_sreg[5:0] == 6'b000001);
|
||||
|
||||
reg [1:0] reg_we_sreg;
|
||||
always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we};
|
||||
wire reg_we_rising = (reg_we_sreg[1:0] == 2'b01);
|
||||
|
||||
reg [1:0] reset_sreg;
|
||||
always @(posedge clkin) reset_sreg <= {reset_sreg[0], reset};
|
||||
wire reset_rising = (reset_sreg[1:0] == 2'b01);
|
||||
|
||||
reg[2:0] we_countdown_r;
|
||||
|
||||
parameter SRTC_IDLE = 5'b00001;
|
||||
parameter SRTC_READ = 5'b00010;
|
||||
parameter SRTC_COMMAND = 5'b00100;
|
||||
parameter SRTC_WRITE = 5'b01000;
|
||||
parameter SRTC_WRITE2 = 5'b10000;
|
||||
|
||||
initial begin
|
||||
rtc_we_r = 0;
|
||||
mode_r <= SRTC_READ;
|
||||
rtc_ptr <= 4'hf;
|
||||
end
|
||||
|
||||
always @(posedge clkin) begin
|
||||
if(reset_rising) begin
|
||||
mode_r <= SRTC_READ;
|
||||
rtc_ptr <= 4'hf;
|
||||
end else if(mode_r == SRTC_WRITE2) begin
|
||||
we_countdown_r <= we_countdown_r - 1;
|
||||
if (we_countdown_r == 3'b000) begin
|
||||
mode_r <= SRTC_WRITE;
|
||||
rtc_we_r <= 0;
|
||||
end
|
||||
end else if(reg_we_rising && enable) begin
|
||||
case (addr_in)
|
||||
// 1'b0: // data register is read only
|
||||
|
||||
1'b1: // control register
|
||||
case (data_in[3:0])
|
||||
4'hd: begin
|
||||
mode_r <= SRTC_READ;
|
||||
rtc_ptr <= 4'hf;
|
||||
end
|
||||
4'he: begin
|
||||
mode_r <= SRTC_COMMAND;
|
||||
end
|
||||
4'hf: begin
|
||||
end
|
||||
default: begin
|
||||
if(mode_r == SRTC_COMMAND) begin
|
||||
case (data_in[3:0])
|
||||
4'h0: begin
|
||||
mode_r <= SRTC_WRITE;
|
||||
rtc_data_out_r <= rtc_data_in;
|
||||
rtc_ptr <= 4'h0;
|
||||
end
|
||||
4'h4: begin
|
||||
mode_r <= SRTC_IDLE;
|
||||
rtc_ptr <= 4'hf;
|
||||
end
|
||||
default:
|
||||
mode_r <= SRTC_IDLE;
|
||||
endcase
|
||||
end else if(mode_r == SRTC_WRITE) begin
|
||||
rtc_ptr <= rtc_ptr + 1;
|
||||
case(rtc_ptr)
|
||||
0: rtc_data_out_r[3:0] <= data_in[3:0];
|
||||
1: rtc_data_out_r[7:4] <= data_in[3:0];
|
||||
2: rtc_data_out_r[11:8] <= data_in[3:0];
|
||||
3: rtc_data_out_r[15:12] <= data_in[3:0];
|
||||
4: rtc_data_out_r[19:16] <= data_in[3:0];
|
||||
5: rtc_data_out_r[23:20] <= data_in[3:0];
|
||||
6: rtc_data_out_r[27:24] <= data_in[3:0];
|
||||
7: rtc_data_out_r[31:28] <= data_in[3:0];
|
||||
8: begin
|
||||
rtc_data_out_r[35:32] <= data_in[3:0] < 10 ? data_in[3:0]
|
||||
: data_in[3:0] - 10;
|
||||
rtc_data_out_r[39:36] <= data_in[3:0] < 10 ? 0 : 1;
|
||||
end
|
||||
9: rtc_data_out_r[43:40] <= data_in[3:0];
|
||||
10: rtc_data_out_r[47:44] <= data_in[3:0];
|
||||
11: begin
|
||||
rtc_data_out_r[51:48] <= data_in[3:0] < 10 ? data_in[3:0]
|
||||
: data_in[3:0] - 10;
|
||||
rtc_data_out_r[55:52] <= data_in[3:0] < 10 ? 1 : 2;
|
||||
end
|
||||
default:
|
||||
rtc_dirty_r <= 1;
|
||||
endcase
|
||||
mode_r <= SRTC_WRITE2;
|
||||
we_countdown_r <= 5;
|
||||
rtc_we_r <= 1;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
endcase
|
||||
end else if(reg_oe_falling && enable) begin
|
||||
case (addr_in)
|
||||
1'b0: // read data register
|
||||
if(mode_r == SRTC_READ) begin
|
||||
case(rtc_ptr)
|
||||
0: data_out_r <= rtc_data_r[3:0];
|
||||
1: data_out_r <= rtc_data_r[7:4];
|
||||
2: data_out_r <= rtc_data_r[11:8];
|
||||
3: data_out_r <= rtc_data_r[15:12];
|
||||
4: data_out_r <= rtc_data_r[19:16];
|
||||
5: data_out_r <= rtc_data_r[23:20];
|
||||
6: data_out_r <= rtc_data_r[27:24];
|
||||
7: data_out_r <= rtc_data_r[31:28];
|
||||
8: data_out_r <= rtc_data_r[35:32] + (rtc_data_r[39:36] << 1) + (rtc_data_r[39:36] << 3);
|
||||
9: data_out_r <= rtc_data_r[43:40];
|
||||
10: data_out_r <= rtc_data_r[47:44];
|
||||
11: data_out_r <= rtc_data_r[51:48] + (rtc_data_r[55:52] << 1) + (rtc_data_r[55:52] << 3) - 10;
|
||||
12: data_out_r <= rtc_data_r[59:56];
|
||||
15: begin
|
||||
rtc_data_r <= rtc_data_in;
|
||||
data_out_r <= 8'h0f;
|
||||
end
|
||||
default: data_out_r <= 8'h0f;
|
||||
endcase
|
||||
rtc_ptr <= rtc_ptr == 13 ? 15 : rtc_ptr + 1;
|
||||
end else begin
|
||||
data_out_r <= 8'h00;
|
||||
end
|
||||
// 1'b1: // control register is write only
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user