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Merge branch 'udev' into develop

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This commit is contained in:
Godzil 2013-10-06 14:42:39 +01:00
parent 043eeea399
commit 1d928e7091
58 changed files with 752 additions and 3028 deletions
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15
CHANGELOG
View File

@ -79,3 +79,18 @@ v0.1.4a (bugfix release)
* Fix DMA initialization in the menu (could cause sprite corruption in some games)
v0.1.5
======
* Sort directories by entire file name instead of first 20 characters only
* Correctly map SRAM larger than 8192 bytes (HiROM) / 32768 bytes (LoROM)
(fixes Dezaemon, Ongaku Tsukuuru - Kanadeeru)
* SPC player: fix soft fade-in (first note cut off) on S-APU consoles
(1CHIP / some Jr.)
* More accurate BS-X memory map
* Ignore input from non-standard controllers (Super Scope, Mouse etc.)
* Fixes:
- minor memory access timing tweaks
(should help with occasional glitches on some systems)

3
snes/boot/const.a65
View File

@ -2,7 +2,8 @@ version .byt " v0.1",0
zero .word 0
bg2tile .byt $20
space64 .byt $20, $20, $20, $20, $20, $20, $20, $20
space64
.byt $20, $20, $20, $20, $20, $20, $20, $20
.byt $20, $20, $20, $20, $20, $20, $20, $20
.byt $20, $20, $20, $20, $20, $20, $20, $20
.byt $20, $20, $20, $20, $20, $20, $20, $20

64
snes/boot/data.a65
View File

@ -1,41 +1,43 @@
.data
;don't anger the stack!
;----------parameters for text output----------
print_x .byt 0 ;x coordinate
.byt 0
print_y .byt 0 ;y coordinate
.byt 0
print_src .word 0 ;source data address
print_bank .byt 0 ;source data bank
print_pal .word 0 ;palette number for text output
print_temp .word 0 ;work variable
print_count .byt 0 ;how many characters may be printed?
print_count_tmp .byt 0 ;work variable
print_done .word 0 ;how many characters were printed?
print_x .byt 0 ; x coordinate
.byt 0
print_y .byt 0 ; y coordinate
.byt 0
print_src .word 0 ; source data address
print_bank .byt 0 ; source data bank
print_pal .word 0 ; palette number for text output
print_temp .word 0 ; work variable
print_count .byt 0 ; how many characters may be printed?
print_count_tmp .byt 0 ; work variable
print_done .word 0 ; how many characters were printed?
;----------parameters for dma----------
dma_a_bank .byt 0
dma_a_addr .word 0
dma_b_reg .byt 0
dma_len .word 0
dma_mode .byt 0
dma_a_bank .byt 0
dma_a_addr .word 0
dma_b_reg .byt 0
dma_len .word 0
dma_mode .byt 0
;----------state information----------
isr_done .byt 0 ; isr done flag
isr_done .byt 0 ; isr done flag
;----------menu layout/system constants (224/448)
textdmasize .word 0 ; number of bytes to copy each frame
textdmasize .word 0 ; number of bytes to copy each frame
infloop .byt 0,0 ; to be filled w/ 80 FE
infloop .byt 0,0 ; to be filled w/ 80 FE
printloop_wram .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
printloop_wram
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
loprint_wram .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
loprint_wram
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

2
snes/boot/palette.a65
View File

@ -1,4 +1,4 @@
palette
;fonts
.byt $42, $08, $ff, $7f, $00, $00, $9c, $73
.byt $42, $08, $ff, $43, $00, $00, $18, $63
.byt $42, $08, $ff, $43, $00, $00, $18, $63

30
snes/boot/reset.a65
View File

@ -11,24 +11,24 @@
; NMI - called on VBlank
NMI_ROUTINE:
sep #$20 : .as
rep #$10 : .xl
lda #$00
pha
plb
lda $4210
sep #$20 : .as
rep #$10 : .xl
lda #$00
pha
plb
lda $4210
ldx #BG1_TILE_BASE
stx $2116
DMA0(#$01, #36*64, #^BG1_TILE_BUF, #!BG1_TILE_BUF, #$18)
ldx #BG1_TILE_BASE
stx $2116
DMA0(#$01, #36*64, #^BG1_TILE_BUF, #!BG1_TILE_BUF, #$18)
lda #$01
sta isr_done
rtl
lda #$01
sta isr_done
rtl
; IRQ - called when triggered
IRQ_ROUTINE:
sep #$20 : .as
lda $4211 ;Acknowledge irq
rtl
sep #$20 : .as
lda $4211 ;Acknowledge irq
rtl

10
snes/pad.a65
View File

@ -4,7 +4,15 @@ read_pad:
read_pad1
ldx pad1mem ;byetUDLRaxlriiii
lda $4218
ora $421a
and #$000f
bne +
lda $4218
+ sta pad1mem
lda $421a
and #$000f
bne +
lda $421a
+ ora pad1mem
sta pad1mem
and #$0f00
bne read_pad1_count

20
snes/spcplay.a65
View File

@ -261,7 +261,19 @@ upload_dsp_regs:
ldx #$0000
-
; initialize FLG and KON ($6c/$4c) to avoid artifacts
cpx #$4C
bne +
lda #$00
bra upload_skip_load
+
cpx #$6C
bne +
lda #$E0
bra upload_skip_load
+
lda @SPC_DSP_REGS,x
upload_skip_load
jsr spc_upload_byte
inx
cpx #128
@ -439,6 +451,14 @@ restore_final:
ldx #$f3C4 ; MOV $f3,A -> $f2 has been set-up before by SPC700 loader
jsr exec_instr
; ---- wait a bit (the newer S-APU takes its time to ramp up the volume)
lda #$10
- pha
jsr waitblank
pla
dec
bne -
; ---- Restore DSP KON register
lda #$4C

4
src/Makefile
View File

@ -75,7 +75,7 @@ ASRC = startup.S crc.S
# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
# Use s -mcall-prologues when you really need size...
#OPT = 2
OPT = 2
OPT = s
# Debugging format.
DEBUG = dwarf-2
@ -198,7 +198,7 @@ ALL_ASFLAGS = -I. -x assembler-with-cpp $(ASFLAGS) $(CDEFS)
# Default target.
all: build
build: elf bin hex
build: elf bin hex cfgware.h
$(E) " SIZE $(TARGET).elf"
$(Q)$(ELFSIZE)|grep -v debug
cp $(TARGET).bin $(OBJDIR)/firmware.img

4
src/bootldr/config.h
View File

@ -55,8 +55,8 @@
//#define CONFIG_CPU_FREQUENCY 46000000
#define CONFIG_UART_PCLKDIV 1
#define CONFIG_UART_TX_BUF_SHIFT 8
#define CONFIG_UART_BAUDRATE 921600
//#define CONFIG_UART_BAUDRATE 115200
//#define CONFIG_UART_BAUDRATE 921600
#define CONFIG_UART_BAUDRATE 115200
#define CONFIG_UART_DEADLOCKABLE
#define SSP_CLK_DIVISOR_FAST 2

3
src/bootldr/fileops.h
View File

@ -31,7 +31,8 @@
enum filestates { FILE_OK=0, FILE_ERR, FILE_EOF };
BYTE file_buf[512];
#define GCC_ALIGN_WORKAROUND __attribute__ ((aligned(4)))
BYTE file_buf[512] GCC_ALIGN_WORKAROUND;
FATFS fatfs;
FIL file_handle;
FRESULT file_res;

2
src/bootldr/iap.c
View File

@ -189,7 +189,7 @@ FLASH_RES flash_file(uint8_t *filename) {
}
DBG_UART uart_putc('w');
if((res = iap_ram2flash(flash_addr, file_buf, 512)) != CMD_SUCCESS) {
DBG_BL printf("error %ld while writing to address %08lx (sector %d)\n", res, flash_addr, current_sec);
//printf("error %ld while writing to address %08lx (sector %d)\n", res, flash_addr, current_sec);
DBG_UART uart_putc('X');
return ERR_FLASH;
}

8
src/bootldr/lpc1754.cfg
View File

@ -27,9 +27,9 @@ if { [info exists CPUTAPID ] } {
#delays on reset lines
#if your OpenOCD version rejects "jtag_nsrst_delay" replace it with:
#adapter_nsrst_delay 200
jtag_nsrst_delay 200
jtag_ntrst_delay 200
adapter_nsrst_delay 200
#jtag_nsrst_delay 200
#jtag_ntrst_delay 200
# LPC2000 & LPC1700 -> SRST causes TRST
#reset_config srst_pulls_trst
@ -56,7 +56,7 @@ flash bank $_FLASHNAME lpc2000 0x0 0x20000 0 0 $_TARGETNAME \
# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
jtag_khz 1000
adapter_khz 1000
$_TARGETNAME configure -event reset-init {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select

6
src/bootldr/main.c
View File

@ -52,8 +52,12 @@ int main(void) {
clock_init();
// LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */
sdn_init();
for(i = 0; i < 20; i++) uart_putc('-');
uart_putc('\n');
DBG_BL printf("chksum=%08lx\n", *(uint32_t*)28);
DBG_BL printf("\n\nsd2snes mk.2 bootloader\nver.: " VER "\ncpu clock: %ld Hz\n", CONFIG_CPU_FREQUENCY);
/*DBG_BL*/ printf("\n\nsd2snes mk.2 bootloader\nver.: " VER "\ncpu clock: %ld Hz\n", CONFIG_CPU_FREQUENCY);
DBG_BL printf("PCONP=%lx\n", LPC_SC->PCONP);
/* setup timer (fpga clk) */
LPC_TIM3->CTCR=0;

2541
src/cfgware.h
View File

File diff suppressed because it is too large Load Diff

35
src/cli.c
View File

@ -58,8 +58,8 @@ static char *curchar;
/* Word lists */
static char command_words[] =
"cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0rm\0mkdir\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0";
enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_MKDIR, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16 };
"cd\0reset\0sreset\0dir\0ls\0test\0exit\0loadrom\0loadraw\0saveraw\0put\0rm\0mkdir\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0memset\0";
enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_EXIT, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_MKDIR, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16, CMD_MEMSET };
/* ------------------------------------------------------------------------- */
/* Parse functions */
@ -104,11 +104,11 @@ static int32_t parse_unsigned(uint32_t lower, uint32_t upper, uint8_t base) {
/* Parse the string starting with curchar for a word in wordlist */
static int8_t parse_wordlist(char *wordlist) {
uint8_t i, matched;
char *cur, *ptr;
char c;
unsigned char *cur, *ptr;
unsigned char c;
i = 0;
ptr = wordlist;
ptr = (unsigned char *)wordlist;
// Command list on "?"
if (strlen(curchar) == 1 && *curchar == '?') {
@ -128,7 +128,7 @@ static int8_t parse_wordlist(char *wordlist) {
}
while (1) {
cur = curchar;
cur = (unsigned char *)curchar;
matched = 1;
c = *ptr;
do {
@ -138,9 +138,9 @@ static int8_t parse_wordlist(char *wordlist) {
return -1;
}
if (tolower(c) != tolower(*cur)) {
if (tolower((int)c) != tolower((int)*cur)) {
// Check for end-of-word
if (cur != curchar && (*cur == ' ' || *cur == 0)) {
if (cur != (unsigned char*)curchar && (*cur == ' ' || *cur == 0)) {
// Partial match found, return that
break;
} else {
@ -156,7 +156,7 @@ static int8_t parse_wordlist(char *wordlist) {
if (matched) {
char *tmp = curchar;
curchar = cur;
curchar = (char *)cur;
// Return match only if whitespace or end-of-string follows
// (avoids mismatching partial words)
if (skip_spaces()) {
@ -269,7 +269,7 @@ static void cmd_show_directory(void) {
strlwr((char *)name);
}
printf("%s",name);
printf("%s [%s] (%ld)",finfo.lfname, finfo.fname, finfo.fsize);
/* Directory indicator (Unix-style) */
if (finfo.fattrib & AM_DIR)
@ -420,6 +420,13 @@ void cmd_w16(void) {
sram_writeshort(val, offset);
}
void cmd_memset(void) {
uint32_t offset = parse_unsigned(0, 16777215, 16);
uint32_t len = parse_unsigned(0, 16777216, 16);
uint8_t val = parse_unsigned(0, 255, 16);
sram_memset(offset, len, val);
}
/* ------------------------------------------------------------------------- */
/* CLI interface functions */
/* ------------------------------------------------------------------------- */
@ -502,7 +509,7 @@ void cli_loop(void) {
cmd_show_directory();
break;
case CMD_RESUME:
case CMD_EXIT:
return;
break;
@ -569,7 +576,11 @@ void cli_loop(void) {
case CMD_W16:
cmd_w16();
break;
}
case CMD_MEMSET:
cmd_memset();
break;
}
}
}

4
src/clock.c
View File

@ -27,7 +27,7 @@ void clock_init() {
-> FPGA freq = 11289473.7Hz
First, disable and disconnect PLL0.
*/
// clock_disconnect();
clock_disconnect();
/* PLL is disabled and disconnected. setup PCLK NOW as it cannot be changed
reliably with PLL0 connected.
@ -74,7 +74,7 @@ void disablePLL0() {
}
void connectPLL0() {
while(!(LPC_SC->PLL0STAT&PLOCK0));
while(!(LPC_SC->PLL0STAT & PLOCK0));
LPC_SC->PLL0CON |= PLLC0;
PLL0feed();
}

2
src/clock.h
View File

@ -74,6 +74,4 @@ void disableMainOsc(void);
void PLL0feed(void);
void setClkSrc(uint8_t src);
#endif

4
src/config
View File

@ -1,4 +1,4 @@
CONFIG_VERSION="0.1.4a"
CONFIG_VERSION="0.1.5"
#FWVER=00010300
CONFIG_FWVER=0x01010400
CONFIG_FWVER=0x00010500
CONFIG_MCU_FOSC=12000000

1
src/config.h
View File

@ -64,6 +64,7 @@
#define FPGA_MCU_RDY_BIT 9
#define QSORT_MAXELEM 2048
#define SORT_STRLEN 256
#define CLTBL_SIZE 100
#define DIR_FILE_MAX 16380

7
src/filetypes.c
View File

@ -65,7 +65,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
static uint32_t next_subdir_tgt;
static uint32_t parent_tgt;
static uint32_t dir_end = 0;
static uint8_t was_empty = 0;
/* static uint8_t was_empty = 0;*/
static uint16_t num_files_total = 0;
static uint16_t num_dirs_total = 0;
uint32_t dir_tgt;
@ -147,7 +147,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
res = f_readdir(&dir, &fno);
if (res != FR_OK || fno.fname[0] == 0) {
if(pass) {
if(!numentries) was_empty=1;
/* if(!numentries) was_empty=1;*/
}
break;
}
@ -194,7 +194,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
sram_writeblock("/\0", old_db_tgt + sizeof(next_subdir_tgt) + sizeof(len) + pathlen, 2);
}
dir_tgt += 4;
was_empty = 0;
/* was_empty = 0;*/
} else if(!mkdb) {
path[len]='/';
strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
@ -275,6 +275,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
sram_writeshort(num_dirs_total, SRAM_DB_ADDR+14);
if(depth==0) return crc;
else return switched_dir_tgt;
return was_empty; // tricky!
}

86
src/fpga_spi.c
View File

@ -1,6 +1,6 @@
/* sd2snes - SD card based universal cartridge for the SNES
Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
AVR firmware portion
Copyright (C) 2009-2012 Maximilian Rehkopf <otakon@gmx.net>
uC firmware portion
Inspired by and based on code from sd2iec, written by Ingo Korb et al.
See sdcard.c|h, config.h.
@ -149,7 +149,7 @@ void fpga_spi_init(void) {
void set_msu_addr(uint16_t address) {
FPGA_SELECT();
FPGA_TX_BYTE(0x02);
FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_MSUBUF);
FPGA_TX_BYTE((address>>8)&0xff);
FPGA_TX_BYTE((address)&0xff);
FPGA_DESELECT();
@ -157,7 +157,7 @@ void set_msu_addr(uint16_t address) {
void set_dac_addr(uint16_t address) {
FPGA_SELECT();
FPGA_TX_BYTE(0x01);
FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_DACBUF);
FPGA_TX_BYTE((address>>8)&0xff);
FPGA_TX_BYTE((address)&0xff);
FPGA_DESELECT();
@ -165,7 +165,7 @@ void set_dac_addr(uint16_t address) {
void set_mcu_addr(uint32_t address) {
FPGA_SELECT();
FPGA_TX_BYTE(0x00);
FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_MEM);
FPGA_TX_BYTE((address>>16)&0xff);
FPGA_TX_BYTE((address>>8)&0xff);
FPGA_TX_BYTE((address)&0xff);
@ -174,7 +174,7 @@ void set_mcu_addr(uint32_t address) {
void set_saveram_mask(uint32_t mask) {
FPGA_SELECT();
FPGA_TX_BYTE(0x20);
FPGA_TX_BYTE(FPGA_CMD_SETRAMMASK);
FPGA_TX_BYTE((mask>>16)&0xff);
FPGA_TX_BYTE((mask>>8)&0xff);
FPGA_TX_BYTE((mask)&0xff);
@ -183,7 +183,7 @@ void set_saveram_mask(uint32_t mask) {
void set_rom_mask(uint32_t mask) {
FPGA_SELECT();
FPGA_TX_BYTE(0x10);
FPGA_TX_BYTE(FPGA_CMD_SETROMMASK);
FPGA_TX_BYTE((mask>>16)&0xff);
FPGA_TX_BYTE((mask>>8)&0xff);
FPGA_TX_BYTE((mask)&0xff);
@ -192,13 +192,13 @@ void set_rom_mask(uint32_t mask) {
void set_mapper(uint8_t val) {
FPGA_SELECT();
FPGA_TX_BYTE(0x30 | (val & 0x0f));
FPGA_TX_BYTE(FPGA_CMD_SETMAPPER(val));
FPGA_DESELECT();
}
uint8_t fpga_test() {
FPGA_SELECT();
FPGA_TX_BYTE(0xF0); /* TEST */
FPGA_TX_BYTE(FPGA_CMD_TEST);
uint8_t result = FPGA_RX_BYTE();
FPGA_DESELECT();
return result;
@ -206,7 +206,7 @@ uint8_t fpga_test() {
uint16_t fpga_status() {
FPGA_SELECT();
FPGA_TX_BYTE(0xF1); /* STATUS */
FPGA_TX_BYTE(FPGA_CMD_GETSTATUS);
uint16_t result = (FPGA_RX_BYTE()) << 8;
result |= FPGA_RX_BYTE();
FPGA_DESELECT();
@ -214,65 +214,53 @@ uint16_t fpga_status() {
}
void fpga_set_sddma_range(uint16_t start, uint16_t end) {
printf("%s %08X -> %08X\n", __func__, start, end);
FPGA_SELECT();
FPGA_TX_BYTE(0x60); /* DMA_RANGE */
FPGA_TX_BYTE(FPGA_CMD_SDDMA_RANGE);
FPGA_TX_BYTE(start>>8);
FPGA_TX_BYTE(start&0xff);
FPGA_TX_BYTE(end>>8);
FPGA_TX_BYTE(end&0xff);
//if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test);
FPGA_DESELECT();
}
void fpga_sddma(uint8_t tgt, uint8_t partial) {
//printf("%s %02X -> %02X\n", __func__, tgt, partial);
uint32_t test = 0;
uint8_t status = 0;
BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 0;
FPGA_SELECT();
FPGA_TX_BYTE(0x40 | (tgt & 0x3) | ((partial & 1) << 2) ); /* DO DMA */
FPGA_TX_BYTE(FPGA_CMD_SDDMA | (tgt & 3) | (partial ? FPGA_SDDMA_PARTIAL : 0));
FPGA_TX_BYTE(0x00); /* dummy for falling DMA_EN edge */
//if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test);
FPGA_DESELECT();
FPGA_SELECT();
FPGA_TX_BYTE(0xF1); /* STATUS */
FPGA_TX_BYTE(FPGA_CMD_GETSTATUS);
DBG_SD printf("FPGA DMA request sent, wait for completion...");
while((status=FPGA_RX_BYTE()) & 0x80) {
while(FPGA_RX_BYTE() & 0x80) {
FPGA_RX_BYTE(); /* eat the 2nd status byte */
test++;
}
DBG_SD printf("...complete\n");
FPGA_DESELECT();
// if(test<5)printf("loopy: %ld %02x\n", test, status);
BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1;
}
void set_dac_vol(uint8_t volume) {
FPGA_SELECT();
FPGA_TX_BYTE(0x50);
FPGA_TX_BYTE(volume);
FPGA_TX_BYTE(0x00); /* latch rise */
FPGA_TX_BYTE(0x00); /* latch fall */
FPGA_DESELECT();
}
void dac_play() {
FPGA_SELECT();
FPGA_TX_BYTE(0xe2);
FPGA_TX_BYTE(FPGA_CMD_DACPLAY);
FPGA_TX_BYTE(0x00); /* latch reset */
FPGA_DESELECT();
}
void dac_pause() {
FPGA_SELECT();
FPGA_TX_BYTE(0xe1);
FPGA_TX_BYTE(FPGA_CMD_DACPAUSE);
FPGA_TX_BYTE(0x00); /* latch reset */
FPGA_DESELECT();
}
void dac_reset() {
FPGA_SELECT();
FPGA_TX_BYTE(0xe3);
FPGA_TX_BYTE(FPGA_CMD_DACRESETPTR);
FPGA_TX_BYTE(0x00); /* latch reset */
FPGA_TX_BYTE(0x00); /* latch reset */
FPGA_DESELECT();
@ -280,7 +268,7 @@ void dac_reset() {
void msu_reset(uint16_t address) {
FPGA_SELECT();
FPGA_TX_BYTE(0xe4);
FPGA_TX_BYTE(FPGA_CMD_MSUSETPTR);
FPGA_TX_BYTE((address>>8) & 0xff); /* address hi */
FPGA_TX_BYTE(address & 0xff); /* address lo */
FPGA_TX_BYTE(0x00); /* latch reset */
@ -290,24 +278,16 @@ void msu_reset(uint16_t address) {
void set_msu_status(uint8_t set, uint8_t reset) {
FPGA_SELECT();
FPGA_TX_BYTE(0xe0);
FPGA_TX_BYTE(FPGA_CMD_MSUSETBITS);
FPGA_TX_BYTE(set);
FPGA_TX_BYTE(reset);
FPGA_TX_BYTE(0x00); /* latch reset */
FPGA_DESELECT();
}
uint8_t get_msu_volume() {
FPGA_SELECT();
FPGA_TX_BYTE(0xF4); /* MSU_VOLUME */
uint8_t result = FPGA_RX_BYTE();
FPGA_DESELECT();
return result;
}
uint16_t get_msu_track() {
FPGA_SELECT();
FPGA_TX_BYTE(0xF3); /* MSU_TRACK */
FPGA_TX_BYTE(FPGA_CMD_MSUGETTRACK);
uint16_t result = (FPGA_RX_BYTE()) << 8;
result |= FPGA_RX_BYTE();
FPGA_DESELECT();
@ -316,7 +296,7 @@ uint16_t get_msu_track() {
uint32_t get_msu_offset() {
FPGA_SELECT();
FPGA_TX_BYTE(0xF2); /* MSU_OFFSET */
FPGA_TX_BYTE(FPGA_CMD_MSUGETADDR);
uint32_t result = (FPGA_RX_BYTE()) << 24;
result |= (FPGA_RX_BYTE()) << 16;
result |= (FPGA_RX_BYTE()) << 8;
@ -327,7 +307,7 @@ uint32_t get_msu_offset() {
uint32_t get_snes_sysclk() {
FPGA_SELECT();
FPGA_TX_BYTE(0xFE); /* GET_SYSCLK */
FPGA_TX_BYTE(FPGA_CMD_GETSYSCLK);
FPGA_TX_BYTE(0x00); /* dummy (copy current sysclk count to register) */
uint32_t result = (FPGA_RX_BYTE()) << 24;
result |= (FPGA_RX_BYTE()) << 16;
@ -339,7 +319,7 @@ uint32_t get_snes_sysclk() {
void set_bsx_regs(uint8_t set, uint8_t reset) {
FPGA_SELECT();
FPGA_TX_BYTE(0xe6);
FPGA_TX_BYTE(FPGA_CMD_BSXSETBITS);
FPGA_TX_BYTE(set);
FPGA_TX_BYTE(reset);
FPGA_TX_BYTE(0x00); /* latch reset */
@ -348,7 +328,7 @@ void set_bsx_regs(uint8_t set, uint8_t reset) {
void set_fpga_time(uint64_t time) {
FPGA_SELECT();
FPGA_TX_BYTE(0xe5);
FPGA_TX_BYTE(FPGA_CMD_RTCSET);
FPGA_TX_BYTE((time >> 48) & 0xff);
FPGA_TX_BYTE((time >> 40) & 0xff);
FPGA_TX_BYTE((time >> 32) & 0xff);
@ -362,7 +342,7 @@ void set_fpga_time(uint64_t time) {
void fpga_reset_srtc_state() {
FPGA_SELECT();
FPGA_TX_BYTE(0xe7);
FPGA_TX_BYTE(FPGA_CMD_SRTCRESET);
FPGA_TX_BYTE(0x00);
FPGA_TX_BYTE(0x00);
FPGA_DESELECT();
@ -370,7 +350,7 @@ void fpga_reset_srtc_state() {
void fpga_reset_dspx_addr() {
FPGA_SELECT();
FPGA_TX_BYTE(0xe8);
FPGA_TX_BYTE(FPGA_CMD_DSPRESETPTR);
FPGA_TX_BYTE(0x00);
FPGA_TX_BYTE(0x00);
FPGA_DESELECT();
@ -378,7 +358,7 @@ void fpga_reset_dspx_addr() {
void fpga_write_dspx_pgm(uint32_t data) {
FPGA_SELECT();
FPGA_TX_BYTE(0xe9);
FPGA_TX_BYTE(FPGA_CMD_DSPWRITEPGM);
FPGA_TX_BYTE((data>>16)&0xff);
FPGA_TX_BYTE((data>>8)&0xff);
FPGA_TX_BYTE((data)&0xff);
@ -389,7 +369,7 @@ void fpga_write_dspx_pgm(uint32_t data) {
void fpga_write_dspx_dat(uint16_t data) {
FPGA_SELECT();
FPGA_TX_BYTE(0xea);
FPGA_TX_BYTE(FPGA_CMD_DSPWRITEDAT);
FPGA_TX_BYTE((data>>8)&0xff);
FPGA_TX_BYTE((data)&0xff);
FPGA_TX_BYTE(0x00);
@ -399,7 +379,7 @@ void fpga_write_dspx_dat(uint16_t data) {
void fpga_dspx_reset(uint8_t reset) {
FPGA_SELECT();
FPGA_TX_BYTE(reset ? 0xeb : 0xec);
FPGA_TX_BYTE(reset ? FPGA_CMD_DSPRESET : FPGA_CMD_DSPUNRESET);
FPGA_TX_BYTE(0x00);
FPGA_DESELECT();
}
@ -407,7 +387,7 @@ void fpga_dspx_reset(uint8_t reset) {
void fpga_set_features(uint8_t feat) {
printf("set features: %02x\n", feat);
FPGA_SELECT();
FPGA_TX_BYTE(0xed);
FPGA_TX_BYTE(FPGA_CMD_SETFEATURE);
FPGA_TX_BYTE(feat);
FPGA_DESELECT();
}
@ -415,7 +395,7 @@ void fpga_set_features(uint8_t feat) {
void fpga_set_213f(uint8_t data) {
printf("set 213f: %d\n", data);
FPGA_SELECT();
FPGA_TX_BYTE(0xee);
FPGA_TX_BYTE(FPGA_CMD_SET213F);
FPGA_TX_BYTE(data);
FPGA_DESELECT();
}

40
src/fpga_spi.h
View File

@ -57,6 +57,44 @@
#define FPGA_WAIT_RDY() do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0)
/* command parameters */
#define FPGA_MEM_AUTOINC (0x8)
#define FPGA_SDDMA_PARTIAL (0x4)
#define FPGA_TGT_MEM (0x0)
#define FPGA_TGT_DACBUF (0x1)
#define FPGA_TGT_MSUBUF (0x2)
/* commands */
#define FPGA_CMD_SETADDR (0x00)
#define FPGA_CMD_SETROMMASK (0x10)
#define FPGA_CMD_SETRAMMASK (0x20)
#define FPGA_CMD_SETMAPPER(x) (0x30 | (x & 15))
#define FPGA_CMD_SDDMA (0x40)
#define FPGA_CMD_SDDMA_RANGE (0x60)
#define FPGA_CMD_READMEM (0x80)
#define FPGA_CMD_WRITEMEM (0x90)
#define FPGA_CMD_MSUSETBITS (0xe0)
#define FPGA_CMD_DACPAUSE (0xe1)
#define FPGA_CMD_DACPLAY (0xe2)
#define FPGA_CMD_DACRESETPTR (0xe3)
#define FPGA_CMD_MSUSETPTR (0xe4)
#define FPGA_CMD_RTCSET (0xe5)
#define FPGA_CMD_BSXSETBITS (0xe6)
#define FPGA_CMD_SRTCRESET (0xe7)
#define FPGA_CMD_DSPRESETPTR (0xe8)
#define FPGA_CMD_DSPWRITEPGM (0xe9)
#define FPGA_CMD_DSPWRITEDAT (0xea)
#define FPGA_CMD_DSPRESET (0xeb)
#define FPGA_CMD_DSPUNRESET (0xec)
#define FPGA_CMD_SETFEATURE (0xed)
#define FPGA_CMD_SET213F (0xee)
#define FPGA_CMD_TEST (0xf0)
#define FPGA_CMD_GETSTATUS (0xf1)
#define FPGA_CMD_MSUGETADDR (0xf2)
#define FPGA_CMD_MSUGETTRACK (0xf3)
#define FPGA_CMD_GETSYSCLK (0xfe)
#define FPGA_CMD_ECHO (0xff)
void fpga_spi_init(void);
uint8_t fpga_test(void);
uint16_t fpga_status(void);
@ -65,7 +103,6 @@ void spi_sd(void);
void spi_none(void);
void set_mcu_addr(uint32_t);
void set_dac_addr(uint16_t);
void set_dac_vol(uint8_t);
void dac_play(void);
void dac_pause(void);
void dac_reset(void);
@ -77,7 +114,6 @@ void set_rom_mask(uint32_t);
void set_mapper(uint8_t val);
void fpga_sddma(uint8_t tgt, uint8_t partial);
void fpga_set_sddma_range(uint16_t start, uint16_t end);
uint8_t get_msu_volume(void);
uint16_t get_msu_track(void);
uint32_t get_msu_offset(void);
uint32_t get_snes_sysclk(void);

73
src/main.c
View File

@ -48,12 +48,14 @@ extern volatile int reset_changed;
extern volatile cfg_t CFG;
enum system_states {
enum system_states
{
SYS_RTC_STATUS = 0,
SYS_LAST_STATUS = 1
};
int main(void) {
int main(void)
{
LPC_GPIO2->FIODIR = BV(4) | BV(5);
LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT);
BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
@ -88,7 +90,9 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
file_init();
cic_init(0);
/* setup timer (fpga clk) */
LPC_TIM3->TCR=2;
LPC_TIM3->CTCR=0;
LPC_TIM3->PR=0;
LPC_TIM3->EMR=EMC0TOGGLE;
LPC_TIM3->MCR=MR0R;
LPC_TIM3->MR0=1;
@ -119,17 +123,21 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
/* some sanity checks */
uint8_t card_go = 0;
while(!card_go) {
if(disk_status(0) & (STA_NOINIT|STA_NODISK)) {
snes_bootprint(" No SD Card found! \0");
while(disk_status(0) & (STA_NOINIT|STA_NODISK));
delay_ms(200);
if(disk_status(0) & (STA_NOINIT|STA_NODISK))
{
snes_bootprint(" No SD Card found! \0");
while(disk_status(0) & (STA_NOINIT|STA_NODISK));
delay_ms(200);
}
file_open((uint8_t*)"/sd2snes/menu.bin", FA_READ);
if(file_status != FILE_OK) {
snes_bootprint(" /sd2snes/menu.bin not found! \0");
while(disk_status(0) == RES_OK);
} else {
card_go = 1;
if(file_status != FILE_OK)
{
snes_bootprint(" /sd2snes/menu.bin not found! \0");
while(disk_status(0) == RES_OK);
}
else
{
card_go = 1;
}
file_close();
}
@ -254,6 +262,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
cfg_set_last_game_valid(1);
cfg_save();
filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
printf("Filesize = %lu\n", filesize);
break;
case SNES_CMD_SETRTC:
/* get time from RAM */
@ -292,9 +301,11 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
break;
}
}
printf("loaded %lu bytes\n", filesize);
printf("cmd was %x, going to snes main loop\n", cmd);
if(romprops.has_msu1 && msu1_loop()) {
if(romprops.has_msu1) {
while(!msu1_loop());
prepare_reset();
continue;
}
@ -302,30 +313,38 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
cmd=0;
uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
uint16_t reset_count=0;
while(fpga_test() == FPGA_TEST_TOKEN) {
while(fpga_test() == FPGA_TEST_TOKEN)
{
cli_entrycheck();
sleep_ms(250);
sram_reliable();
printf("%s ", get_cic_statename(get_cic_state()));
if(reset_changed) {
if(reset_changed)
{
printf("reset\n");
reset_changed = 0;
fpga_reset_srtc_state();
}
snes_reset_now=get_snes_reset();
if(snes_reset_now) {
if(!snes_reset_prev) {
printf("RESET BUTTON DOWN\n");
snes_reset_state=1;
reset_count=0;
}
} else {
if(snes_reset_prev) {
printf("RESET BUTTON UP\n");
snes_reset_state=0;
}
snes_reset_now = get_snes_reset();
if (snes_reset_now)
{
if (!snes_reset_prev)
{
printf("RESET BUTTON DOWN\n");
snes_reset_state = 1;
reset_count = 0;
}
}
else
{
if (snes_reset_prev)
{
printf("RESET BUTTON UP\n");
snes_reset_state = 0;
}
}
if(snes_reset_state) {
if (snes_reset_state)
{
reset_count++;
} else {
sram_reliable();

45
src/memory.c
View File

@ -54,11 +54,12 @@ void sram_hexdump(uint32_t addr, uint32_t len) {
uint32_t ptr;
for(ptr=0; ptr < len; ptr += 16) {
sram_readblock((void*)buf, ptr+addr, 16);
uart_trace(buf, 0, 16);
uart_trace(buf, 0, 16, addr);
}
}
void sram_writebyte(uint8_t val, uint32_t addr) {
printf("WriteB %8Xh @%08lXh\n", val, addr);
set_mcu_addr(addr);
FPGA_SELECT();
FPGA_TX_BYTE(0x98); /* WRITE */
@ -74,10 +75,12 @@ uint8_t sram_readbyte(uint32_t addr) {
FPGA_WAIT_RDY();
uint8_t val = FPGA_RX_BYTE();
FPGA_DESELECT();
//printf(" ReadB %8Xh @%08lXh\n", val, addr);
return val;
}
void sram_writeshort(uint16_t val, uint32_t addr) {
printf("WriteS %8Xh @%08lXh\n", val, addr);
set_mcu_addr(addr);
FPGA_SELECT();
FPGA_TX_BYTE(0x98); /* WRITE */
@ -89,6 +92,7 @@ void sram_writeshort(uint16_t val, uint32_t addr) {
}
void sram_writelong(uint32_t val, uint32_t addr) {
printf("WriteL %8lXh @%08lXh\n", val, addr);
set_mcu_addr(addr);
FPGA_SELECT();
FPGA_TX_BYTE(0x98); /* WRITE */
@ -112,6 +116,7 @@ uint16_t sram_readshort(uint32_t addr) {
FPGA_WAIT_RDY();
val |= ((uint32_t)FPGA_RX_BYTE()<<8);
FPGA_DESELECT();
//printf(" ReadS %8lXh @%08lXh\n", val, addr);
return val;
}
@ -128,6 +133,7 @@ uint32_t sram_readlong(uint32_t addr) {
FPGA_WAIT_RDY();
val |= ((uint32_t)FPGA_RX_BYTE()<<24);
FPGA_DESELECT();
//printf(" ReadL %8lXh @%08lXh\n", val, addr);
return val;
}
@ -163,7 +169,21 @@ void sram_readblock(void* buf, uint32_t addr, uint16_t size) {
FPGA_DESELECT();
}
void sram_readstrn(void* buf, uint32_t addr, uint16_t size) {
uint16_t count=size;
uint8_t* tgt = buf;
set_mcu_addr(addr);
FPGA_SELECT();
FPGA_TX_BYTE(0x88); /* READ */
while(count--) {
FPGA_WAIT_RDY();
if(!(*(tgt++) = FPGA_RX_BYTE())) break;
}
FPGA_DESELECT();
}
void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
printf("WriteZ %08lX -> %08lX [%d]\n", addr, addr+size, size);
uint16_t count=size;
uint8_t* src = buf;
set_mcu_addr(addr);
@ -178,7 +198,7 @@ void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
UINT bytes_read;
DWORD filesize;
DWORD filesize, read_size = 0;
UINT count=0;
tick_t ticksstart, ticks_total=0;
ticksstart=getticks();
@ -206,12 +226,14 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
ff_sd_offload=1;
sd_offload_tgt=0;
bytes_read = file_read();
read_size += bytes_read;
if (file_res || !bytes_read) break;
if(!(count++ % 512)) {
uart_putc('.');
uart_putc('.');
}
}
file_close();
printf("Read %ld [%08lX] bytes...\n", read_size, read_size);
set_mapper(romprops.mapper_id);
printf("rom header map: %02x; mapper id: %d\n", romprops.header.map, romprops.mapper_id);
ticks_total=getticks()-ticksstart;
@ -261,6 +283,9 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
rammask = romprops.ramsize_bytes - 1;
}
rommask = romprops.romsize_bytes - 1;
if (rommask >= SRAM_SAVE_ADDR)
rommask = SRAM_SAVE_ADDR - 1;
printf("ramsize=%x rammask=%lx\nromsize=%x rommask=%lx\n", romprops.header.ramsize, rammask, romprops.header.romsize, rommask);
set_saveram_mask(rammask);
set_rom_mask(rommask);
@ -460,7 +485,7 @@ uint32_t load_bootrle(uint32_t base_addr) {
void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr) {
uint32_t count = 0;
uint32_t num = 0;
//uint32_t num = 0;
FPGA_DESELECT();
file_open(filename, FA_CREATE_ALWAYS | FA_WRITE);
@ -477,7 +502,7 @@ void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr) {
count++;
}
FPGA_DESELECT();
num = file_write();
/*num = */file_write();
if(file_res) {
uart_putc(0x30+file_res);
}
@ -524,9 +549,9 @@ uint8_t sram_reliable() {
val=sram_readlong(SRAM_SCRATCHPAD);
if(val==0x12345678) {
score++;
} else {
printf("i=%d val=%08lX\n", i, val);
}
} //else {
//printf("i=%d val=%08lX\n", i, val);
//}
}
if(score<SRAM_RELIABILITY_SCORE) {
result = 0;
@ -581,7 +606,7 @@ uint64_t sram_gettime(uint32_t base_addr) {
void load_dspx(const uint8_t *filename, uint8_t coretype) {
UINT bytes_read;
DWORD filesize;
//DWORD filesize;
uint16_t word_cnt;
uint8_t wordsize_cnt = 0;
uint16_t sector_remaining = 0;
@ -605,7 +630,7 @@ void load_dspx(const uint8_t *filename, uint8_t coretype) {
}
file_open((uint8_t*)filename, FA_READ);
filesize = file_handle.fsize;
/*filesize = file_handle.fsize;*/
if(file_res) {
printf("Could not read %s: error %d\n", filename, file_res);
return;

32
src/memory.h
View File

@ -30,24 +30,26 @@
#include <arm/NXP/LPC17xx/LPC17xx.h>
#include "smc.h"
#define SRAM_ROM_ADDR (0x000000L)
#define SRAM_SAVE_ADDR (0xE00000L)
#define MASK_BITS (0x000000)
#define SRAM_MENU_ADDR (0xC00000L)
#define SRAM_DIR_ADDR (0xC10000L)
#define SRAM_DB_ADDR (0xC80000L)
#define SRAM_ROM_ADDR ((0x000000L) & ~MASK_BITS)
#define SRAM_SAVE_ADDR ((0x600000L) & ~MASK_BITS)
#define SRAM_SPC_DATA_ADDR (0xFD0000L)
#define SRAM_SPC_HEADER_ADDR (0xFE0000L)
#define SRAM_MENU_ADDR ((0x500000L) & ~MASK_BITS)
#define SRAM_DIR_ADDR ((0x510000L) & ~MASK_BITS)
#define SRAM_DB_ADDR ((0x580000L) & ~MASK_BITS)
#define SRAM_MENU_SAVE_ADDR (0xFF0000L)
#define SRAM_CMD_ADDR (0xFF1000L)
#define SRAM_PARAM_ADDR (0xFF1004L)
#define SRAM_STATUS_ADDR (0xFF1100L)
#define SRAM_SYSINFO_ADDR (0xFF1200L)
#define SRAM_LASTGAME_ADDR (0xFF1420L)
#define SRAM_SCRATCHPAD (0xFFFF00L)
#define SRAM_DIRID (0xFFFFF0L)
#define SRAM_SPC_DATA_ADDR ((0x7D0000L) & ~MASK_BITS)
#define SRAM_SPC_HEADER_ADDR ((0x7E0000L) & ~MASK_BITS)
#define SRAM_MENU_SAVE_ADDR ((0x7F0000L) & ~MASK_BITS)
#define SRAM_CMD_ADDR ((0x7F1000L) & ~MASK_BITS)
#define SRAM_PARAM_ADDR ((0x7F1004L) & ~MASK_BITS)
#define SRAM_STATUS_ADDR ((0x7F1100L) & ~MASK_BITS)
#define SRAM_SYSINFO_ADDR ((0x7F1200L) & ~MASK_BITS)
#define SRAM_LASTGAME_ADDR ((0x7F1420L) & ~MASK_BITS)
#define SRAM_SCRATCHPAD ((0x7FFF00L) & ~MASK_BITS)
#define SRAM_DIRID ((0x7FFFF0L) & ~MASK_BITS)
#define SRAM_RELIABILITY_SCORE (0x100)
#define LOADROM_WITH_SRAM (1)

6
src/msu1.c
View File

@ -161,7 +161,6 @@ int msu1_check(uint8_t* filename) {
int msu1_loop() {
/* it is assumed that the MSU file is already opened by calling msu1_check(). */
set_dac_vol(0x00);
while(fpga_status() & 0x4000);
uint16_t dac_addr = 0;
uint16_t msu_addr = 0;
@ -204,21 +203,18 @@ int msu1_loop() {
/* Data buffer refill */
if((fpga_status_now & 0x2000) != (fpga_status_prev & 0x2000)) {
DBG_MSU1 printf("data\n");
uint8_t pageno = 0;
if(fpga_status_now & 0x2000) {
msu_addr = 0x0;
msu_page1_start = msu_page2_start + msu_page_size;
pageno = 1;
} else {
msu_addr = 0x2000;
msu_page2_start = msu_page1_start + msu_page_size;
pageno = 2;
}
set_msu_addr(msu_addr);
sd_offload_tgt=2;
ff_sd_offload=1;
msu_res = f_read(&msufile, file_buf, 8192, &msu_data_bytes_read);
DBG_MSU1 printf("data buffer refilled. res=%d page1=%08lx page2=%08lx\n", msu_res, msu_page1_start, msu_page2_start);
DBG_MSU1 printf("data buffer refilled. page=%d res=%d page1=%08lx page2=%08lx\n", pageno, msu_res, msu_page1_start, msu_page2_start);
}
/* Audio buffer refill */

46
src/sdcard.h
View File

@ -1,46 +0,0 @@
/* sd2iec - SD/MMC to Commodore serial bus interface/controller
Copyright (C) 2007-2010 Ingo Korb <ingo@akana.de>
Inspiration and low-level SD/MMC access based on code from MMC2IEC
by Lars Pontoppidan et al., see sdcard.c|h and config.h.
FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; version 2 of the License only.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
sdcard.h: Definitions for the SD/MMC access routines
*/
#ifndef SDCARD_H
#define SDCARD_H
#include "diskio.h"
#define SD_TX_BYTE(x) spi_tx_byte(x, SPI_SD);
#define SD_RX_BYTE(x) spi_rx_byte(x, SPI_SD);
#define SD_TX_BLOCK(x,y) spi_tx_block(x,y, SPI_SD);
#define SD_RX_BLOCK(x,y) spi_rx_block(x,y, SPI_SD);
/* These functions are weak-aliased to disk_... */
void sd_init(void);
DSTATUS sd_status(BYTE drv);
DSTATUS sd_initialize(BYTE drv);
DRESULT sd_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count);
DRESULT sd_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count);
DRESULT sd_getinfo(BYTE drv, BYTE page, void *buffer);
void sd_changed(void);
#endif

2
src/sdnative.c
View File

@ -933,7 +933,7 @@ DSTATUS sdn_initialize(BYTE drv) {
if((rsplen=cmd_slow(SEND_IF_COND, 0x000001aa, 0x87, NULL, rsp))) {
DBG_SD printf("CMD8 response:\n");
DBG_SD uart_trace(rsp, 0, rsplen);
DBG_SD uart_trace(rsp, 0, rsplen, 0);
hcs=1;
}
while(1) {

2
src/smc.c
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@ -199,7 +199,7 @@ void smc_id(snes_romprops_t* props) {
props->ramsize_bytes = (uint32_t)1024 << header->ramsize;
props->romsize_bytes = (uint32_t)1024 << header->romsize;
props->expramsize_bytes = (uint32_t)1024 << header->expramsize;
/*dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); */
//dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes);
if(props->ramsize_bytes > 32768 || props->ramsize_bytes < 2048) {
props->ramsize_bytes = 0;
}

16
src/snes.c
View File

@ -83,6 +83,10 @@ void snes_reset_pulse() {
* state: put SNES in reset state when 1, release when 0
*/
void snes_reset(int state) {
if (state == 0)
printf("Releasing SNES RESET\n");
else
printf("Pull SNES RESET\n");
BITBAND(SNES_RESET_REG->FIODIR, SNES_RESET_BIT) = state;
}
@ -123,7 +127,7 @@ void snes_main_loop() {
samecount++;
}
if(diffcount>=1 && samecount==5) {
printf("SaveRAM CRC: 0x%04lx; saving\n", saveram_crc);
printf("SaveRAM CRC: 0x%04lx; saving %s\n", saveram_crc, file_lfn);
writeled(1);
save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR);
writeled(0);
@ -170,12 +174,16 @@ void get_selected_name(uint8_t* fn) {
sram_readblock(fn, addr + 7 + SRAM_MENU_ADDR, 256);
}
void snes_bootprint(void* msg) {
void snes_bootprint(void* msg)
{
printf("%s\n", (char*)msg);
sram_writeblock(msg, SRAM_CMD_ADDR, 33);
}
void snes_menu_errmsg(int err, void* msg) {
void snes_menu_errmsg(int err, void* msg)
{
printf("%d: %s\n", err, (char*)msg);
sram_writeblock(msg, SRAM_CMD_ADDR+1, 64);
sram_writebyte(err, SRAM_CMD_ADDR);
}

7
src/sort.c
View File

@ -15,7 +15,7 @@
*/
uint32_t stat_getstring = 0;
static char sort_str1[21], sort_str2[21];
static char sort_str1[SORT_STRLEN+1], sort_str2[SORT_STRLEN+1];
uint32_t ptrcache[QSORT_MAXELEM] IN_AHBRAM;
/* get element from pointer table in external RAM*/
@ -71,13 +71,12 @@ void sort_getstring_for_dirent(char *ptr, uint32_t addr) {
if(addr & 0x80000000) {
/* is directory link, name offset 4 */
leaf_offset = sram_readbyte(addr + 4 + SRAM_MENU_ADDR);
sram_readblock(ptr, addr + 5 + leaf_offset + SRAM_MENU_ADDR, 20);
sram_readstrn(ptr, addr + 5 + leaf_offset + SRAM_MENU_ADDR, SORT_STRLEN);
} else {
/* is file link, name offset 6 */
leaf_offset = sram_readbyte(addr + 6 + SRAM_MENU_ADDR);
sram_readblock(ptr, addr + 7 + leaf_offset + SRAM_MENU_ADDR, 20);
sram_readstrn(ptr, addr + 7 + leaf_offset + SRAM_MENU_ADDR, SORT_STRLEN);
}
ptr[20]=0;
}
void sort_heapify(uint32_t addr, unsigned int i, unsigned int heapsize)

3
src/tests/Makefile
View File

@ -138,7 +138,8 @@ CFLAGS += $(CDEFS) $(CINCS)
CFLAGS += -O$(OPT)
CFLAGS += $(CPUFLAGS) -nostartfiles
#CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums
CFLAGS += -Wall -Wstrict-prototypes -Werror
CFLAGS += -Wall -Wstrict-prototypes
# -Werror
CFLAGS += -Wa,-adhlns=$(OBJDIR)/$(<:.c=.lst)
CFLAGS += -I$(OBJDIR)
CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))

3
src/tests/config.h
View File

@ -38,7 +38,8 @@
//#define CONFIG_CPU_FREQUENCY 46000000
#define CONFIG_UART_PCLKDIV 1
#define CONFIG_UART_TX_BUF_SHIFT 8
#define CONFIG_UART_BAUDRATE 921600
//#define CONFIG_UART_BAUDRATE 921600
#define CONFIG_UART_BAUDRATE 115200
#define CONFIG_UART_DEADLOCKABLE
#define SSP_CLK_DIVISOR_FAST 2

14
src/tests/openocd-usb.cfg
View File

@ -5,8 +5,14 @@
#
interface ft2232
ft2232_vid_pid 0x0403 0x6010
ft2232_device_desc "Dual RS232"
ft2232_layout "oocdlink"
ft2232_latency 2
ft2232_vid_pid 0x15ba 0x0003
ft2232_device_desc "Olimex OpenOCD JTAG"
ft2232_layout "olimex-jtag"
#interface ft2232
#ft2232_vid_pid 0x0403 0x6010
#ft2232_device_desc "Dual RS232"
#ft2232_layout "oocdlink"
#ft2232_latency 2
#adapter_khz 10

214
src/tests/tests.c
View File

@ -152,74 +152,178 @@ int test_fpga() {
return PASSED;
}
int test_mem() {
printf("RAM test\n========\n");
printf("Testing RAM0 (128Mbit) - writing RAM -");
uint32_t addr;
/*************************************************************************************/
/*************************************************************************************/
typedef struct memory_test
{
char name[20];
int a_len;
int d_len;
unsigned int (*read)(unsigned int addr);
void (*write)(unsigned int addr, unsigned int data);
void (*open)(void);
void (*close)(void);
} memory_test;
/*************************************************************************************/
void rom_open(void)
{
snes_reset(1);
fpga_select_mem(0);
set_mcu_addr(0);
FPGA_DESELECT();
delay_ms(1);
FPGA_SELECT();
delay_ms(1);
FPGA_TX_BYTE(0x98);
for(addr=0; addr < 16777216; addr++) {
if((addr&0xffff) == 0)printf("\x8%c", PROGRESS[(addr>>16)&3]);
FPGA_TX_BYTE((addr)+(addr>>8)+(addr>>16));
FPGA_WAIT_RDY();
}
FPGA_DESELECT();
printf(" verifying RAM -");
uint8_t data, expect, error=0, failed=0;
set_mcu_addr(0);
FPGA_SELECT();
FPGA_TX_BYTE(0x88);
for(addr=0; addr < 16777216; addr++) {
if((addr&0xffff) == 0)printf("\x8%c", PROGRESS[(addr>>16)&3]);
FPGA_WAIT_RDY();
data = FPGA_RX_BYTE();
expect = (addr)+(addr>>8)+(addr>>16);
if(data != expect) {
printf("error @0x%06lx: expected 0x%02x, got 0x%02x\n", addr, expect, data);
error++;
failed=1;
if(error>20) {
printf("too many errors, aborting\n");
break;
}
}
}
FPGA_DESELECT();
if(error) printf("RAM0 FAILED\n");
else printf("RAM0 PASSED\n");
printf("Testing RAM1 (4Mbit) - writing RAM - ");
}
void rom_close(void)
{
}
unsigned int rom_read(unsigned int addr)
{
return sram_readbyte(addr);
}
void rom_write(unsigned int addr, unsigned int data)
{
sram_writebyte(data, addr);
}
memory_test rom = {
.name = "RAM0 (128Mbit)",
.a_len = 22,
.d_len = 8,
.read = rom_read,
.write = rom_write,
.open = rom_open,
.close = rom_close,
};
/*************************************************************************************/
void sram_open(void)
{
snes_reset(1);
fpga_select_mem(1);
for(addr=0; addr < 524288; addr++) {
sram_writebyte((addr)+(addr>>8)+(addr>>16), addr);
}
printf("verifying RAM...");
error = 0;
for(addr=0; addr < 524288; addr++) {
data = sram_readbyte(addr);
expect = (addr)+(addr>>8)+(addr>>16);
if(data != expect) {
printf("error @0x%05lx: expected 0x%02x, got 0x%02x\n", addr, expect, data);
error++;
failed=1;
if(error>20) {
printf("too many errors, aborting\n");
break;
}
}
void sram_close(void)
{
}
unsigned int sram_read(unsigned int addr)
{
return sram_readbyte(addr);
}
void sram_write(unsigned int addr, unsigned int data)
{
sram_writebyte(data, addr);
}
memory_test sram =
{
.name = "RAM1(4Mbit)",
.a_len = 19,
.d_len = 8,
.read = sram_read,
.write = sram_write,
.open = sram_open,
.close = sram_close,
};
int do_test(memory_test *test)
{
int i, j, read, want;
int ret = 0;
int a_mask = (1 << test->a_len) - 1;
int d_mask = (1 << test->d_len) - 1;
test->open();
printf("-- Will test %s\n", test->name);
printf("---- Fill with AA55 ");
test->write(0, 0xAA);
for (i = 1; i < a_mask; i++)
{
if((i&0xffff) == 0)printf("\x8%c", PROGRESS[(i>>16)&3]);
want = (i&1)?0x55:0xAA;
test->write(i, want);
want = ((i-1)&1)?0x55:0xAA;
read = test->read(i-1);
if (read != want)
{
printf("Failed [@%8X Want: %02X Get: %02X]", i-1, want, read);
ret |= 1;
break;
}
}
if(error) printf("RAM1 FAILED\n\n\n");
else printf("RAM1 PASSED\n\n\n");
if(failed) return FAILED;
printf("Ok \n---- Fill with 00 ");
for (i = 0; i < a_mask; i++)
{
if((i&0xffff) == 0)printf("\x8%c", PROGRESS[(i>>16)&3]);
test->write(i, 0);
}
printf("Ok \n---- Check data lines...\n"
"----- ");
for (i = 0; i < test->d_len; i++) printf("%X", i);
printf("\n");
/* Check on 4 addresses, taken evenly */
#define TEST_NUM (10)
for (j = 0; j < TEST_NUM; j ++)
{
printf("----- %8X [", j * a_mask/TEST_NUM);
for (i = 0; i < test->d_len; i++)
{
read = test->read(j * a_mask/TEST_NUM);
if ((test->read(j * a_mask/TEST_NUM) & (1<<i)) != 0)
{
printf("1", read);
ret |= 2;
goto next_data;
}
test->write(j * a_mask/TEST_NUM, (1<<i));
read = test->read(j * a_mask/TEST_NUM);
if (read == 0)
{
printf("0");
ret |= 4;
goto next_data;
}
printf("x");
next_data:
test->write(j * a_mask/4, 0);
}
printf("]\n");
}
test->close();
return ret;
}
int test_mem()
{
int ret = PASSED;
printf("RAM test\n========\n");
if (do_test(&rom) != 0)
ret = FAILED;
if (do_test(&sram) != 0);
ret = FAILED;
return PASSED;
}
int test_clk() {
uint32_t sysclk[4];
int32_t diff, max_diff = 0;

10
src/timer.c
View File

@ -57,9 +57,17 @@ void timer_init(void) {
/* clear RIT mask */
LPC_RIT->RIMASK = 0; /*xffffffff;*/
/* PCLK = CCLK */
/* PCLK_RIT = CCLK */
BITBAND(LPC_SC->PCLKSEL1, 27) = 0;
BITBAND(LPC_SC->PCLKSEL1, 26) = 1;
/* PCLK_TIMER3 = CCLK/4 */
BITBAND(LPC_SC->PCLKSEL1, 15) = 0;
BITBAND(LPC_SC->PCLKSEL1, 14) = 0;
/* enable timer 3 */
BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1;
/* enable SysTick */
SysTick_Config((SysTick->CALIB & SysTick_CALIB_TENMS_Msk));
}

7
src/uart.c
View File

@ -238,7 +238,7 @@ void uart_puthex(uint8_t num) {
uart_putc('a'+tmp-10);
}
void uart_trace(void *ptr, uint16_t start, uint16_t len) {
void uart_trace(void *ptr, uint16_t start, uint16_t len, uint32_t addr) {
uint16_t i;
uint8_t j;
uint8_t ch;
@ -247,8 +247,9 @@ void uart_trace(void *ptr, uint16_t start, uint16_t len) {
data+=start;
for(i=0;i<len;i+=16) {
uart_puthex(start>>8);
uart_puthex(start&0xff);
uart_puthex((addr + start)>>16);
uart_puthex(((addr + start)>>8) & 0xff);
uart_puthex((addr + start)&0xff);
uart_putc('|');
uart_putc(' ');
for(j=0;j<16;j++) {

2
src/uart.h
View File

@ -26,7 +26,7 @@ unsigned char uart_gotc(void);
void uart_putc(char c);
void uart_puts(const char *str);
void uart_puthex(uint8_t num);
void uart_trace(void *ptr, uint16_t start, uint16_t len);
void uart_trace(void *ptr, uint16_t start, uint16_t len, uint32_t addr);
void uart_flush(void);
int printf(const char *fmt, ...);
int snprintf(char *str, size_t size, const char *format, ...);

12
src/utils/bin2h.c
View File

@ -3,19 +3,20 @@
int main(int argc, char *argv[])
{
char var_name[30] = "cfgware"
FILE *fpIn = NULL, *fpOut = NULL;
unsigned char buffer[5], i;
if ( argc == 3 )
if ( argc == 4 )
{
fpIn = fopen(argv[1], "rb");
fpOut = fopen(argv[2], "wt");
}
else if (argc == 2)
else if (argc == 3)
{
fpIn = fopen(argv[1], "rb");
fpOut = stdout;
}
else if ( argc == 1 )
else if ( argc == 2 )
{
fpIn = stdin;
fpOut = stdout;
@ -26,10 +27,13 @@ int main(int argc, char *argv[])
return -1;
}
if (argc > 1)
sprintf()
if (fpIn == NULL) { fprintf(stderr, "Can't open '%s`: Aborting.", argv[1]); return -1; }
if (fpOut == NULL) { fprintf(stderr, "Can't open '%s`: Aborting.", argv[2]); return -1; }
fprintf(fpOut, "const uint8_t cfgware[] = {\n");
fprintf(fpOut, "const uint8_t %s[] = {\n", var_name);
i = 0;
while(!feof(fpIn))
{

BIN
src/utils/lpcchksum
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Binary file not shown.

BIN
src/utils/lpcchksum.o
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Binary file not shown.

12
src/xmodem.c
View File

@ -6,8 +6,8 @@
#include "xmodem.h"
void xmodem_rxfile(FIL* fil) {
uint8_t rxbuf[XMODEM_BLKSIZE], sum=0, sender_sum;
uint8_t blknum, blknum2;
uint8_t rxbuf[XMODEM_BLKSIZE], sum=0/*, sender_sum*/;
/* uint8_t blknum, blknum2;*/
uint8_t count;
uint32_t totalbytes = 0;
uint32_t totalwritten = 0;
@ -19,13 +19,13 @@ void xmodem_rxfile(FIL* fil) {
uart_putc(ASC_NAK);
} while (uart_getc() != ASC_SOH);
do {
blknum=uart_getc();
blknum2=uart_getc();
/*blknum=*/uart_getc();
/*blknum2=*/uart_getc();
for(count=0; count<XMODEM_BLKSIZE; count++) {
sum += rxbuf[count] = uart_getc();
totalbytes++;
}
sender_sum = uart_getc();
/*sender_sum =*/ uart_getc();
res=f_write(fil, rxbuf, XMODEM_BLKSIZE, &written);
totalwritten += written;
uart_putc(ASC_ACK);
@ -33,5 +33,7 @@ void xmodem_rxfile(FIL* fil) {
uart_putc(ASC_ACK);
uart_flush();
sleep_ms(1000);
sender_sum = blknum + blknum2;
printf("%x:%x:%x\n", blknum, blknum2, sender_sum);
printf("received %ld bytes, wrote %ld bytes. last res = %d\n", totalbytes, totalwritten, res);
}

119
verilog/sd2snes/address.v
View File

@ -33,6 +33,7 @@ module address(
output msu_enable,
output srtc_enable,
output use_bsx,
output bsx_tristate,
input [14:0] bsx_regs,
output dspx_enable,
output dspx_dp_enable,
@ -71,47 +72,101 @@ wire [23:0] SRAM_SNES_ADDR;
assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]));
/* HiROM SRAM is 8K end at 0x8000 and is at bank 0x20 and 0xA0 */
assign IS_SAVERAM_HIROM = ((SNES_ADDR[22:21] == 2'b01)
& SNES_ADDR[15:13] == 3'b011)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd Offset 0000-7fff
TODO: 0000-ffff for small ROMs? */
assign IS_SAVERAM_LOROM = SNES_ADDR[22:16] == 7'b111
( &SNES_ADDR[22:20]
& (SNES_ADDR[19:16] < 4'b1110)
& !SNES_ADDR[15] )
assign IS_SAVERAM_EXHIROM = (!SNES_ADDR[22]
& SNES_ADDR[21]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15])
assign IS_SAVERAM_BSX = ( (SNES_ADDR[23:19] == 5'b00010)
& (SNES_ADDR[15:12] == 4'b0101)
)
assign IS_SAVERAM_STARTOCEAN = (!SNES_ADDR[22]
& SNES_ADDR[21]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15])
assign IS_SAVERAM_MENU = (!SNES_ADDR[22]
& SNES_ADDR[21]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15])
assign IS_SAVERAM = SAVERAM_MASK[0]
&(featurebits[FEAT_ST0010]
?((SNES_ADDR[22:19] == 4'b1101)
& &(~SNES_ADDR[15:12])
& SNES_ADDR[11])
:((MAPPER == 3'b000
|| MAPPER == 3'b010
|| MAPPER == 3'b110
|| MAPPER == 3'b111)
? (!SNES_ADDR[22]
& SNES_ADDR[21]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
)
:(
( MAPPER == 3'b000
|| MAPPER == 3'b010
|| MAPPER == 3'b110
|| MAPPER == 3'b111)
? (!SNES_ADDR[22]
& SNES_ADDR[21]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15])
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd Offset 0000-7fff
TODO: 0000-ffff for small ROMs? */
:(MAPPER == 3'b001)
? (&SNES_ADDR[22:20]
& (SNES_ADDR[19:16] < 4'b1110)
& !SNES_ADDR[15]
)
:(MAPPER == 3'b001)
? ( &SNES_ADDR[22:20]
& (SNES_ADDR[19:16] < 4'b1110)
& !SNES_ADDR[15]
)
/* BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff */
:(MAPPER == 3'b011)
? ((SNES_ADDR[23:19] == 5'b00010)
& (SNES_ADDR[15:12] == 4'b0101)
)
: 1'b0));
:(MAPPER == 3'b011)
? ( (SNES_ADDR[23:19] == 5'b00010)
& (SNES_ADDR[15:12] == 4'b0101)
)
: 1'b0
)
);
/* BS-X has 4 MBits of extra RAM that can be mapped to various places */
wire [2:0] BSX_PSRAM_BANK = {bsx_regs[2], bsx_regs[6], bsx_regs[5]};
wire [23:0] BSX_CHKADDR = bsx_regs[2] ? SNES_ADDR : {SNES_ADDR[23], 1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]};
wire BSX_PSRAM_LOHI = (bsx_regs[3] & ~SNES_ADDR[23]) | (bsx_regs[4] & SNES_ADDR[23]);
wire BSX_IS_PSRAM = BSX_PSRAM_LOHI
& (( (BSX_CHKADDR[22:20] == BSX_PSRAM_BANK)
&(SNES_ADDR[15] | bsx_regs[2])
&(~(SNES_ADDR[19] & bsx_regs[2])))
| (bsx_regs[2]
? (SNES_ADDR[22:21] == 2'b01 & SNES_ADDR[15:13] == 3'b011)
: (&SNES_ADDR[22:20] & ~SNES_ADDR[15]))
);
wire BSX_IS_CARTROM = ((bsx_regs[7] & (SNES_ADDR[23:22] == 2'b00))
|(bsx_regs[8] & (SNES_ADDR[23:22] == 2'b10)))
& SNES_ADDR[15];
wire BSX_HOLE_LOHI = (bsx_regs[9] & ~SNES_ADDR[23]) | (bsx_regs[10] & SNES_ADDR[23]);
wire BSX_IS_HOLE = BSX_HOLE_LOHI
& (bsx_regs[2] ? (SNES_ADDR[21:20] == {bsx_regs[11], 1'b0})
: (SNES_ADDR[22:21] == {bsx_regs[11], 1'b0}));
assign bsx_tristate = (MAPPER == 3'b011) & ~BSX_IS_CARTROM & ~BSX_IS_PSRAM & BSX_IS_HOLE;
assign IS_WRITABLE = IS_SAVERAM
|((MAPPER == 3'b011)
?((bsx_regs[3] && SNES_ADDR[23:20]==4'b0110)
|(!bsx_regs[5] && SNES_ADDR[23:20]==4'b0100)
|(!bsx_regs[6] && SNES_ADDR[23:20]==4'b0101)
|(SNES_ADDR[23:19] == 5'b01110)
|(SNES_ADDR[23:21] == 3'b001
&& SNES_ADDR[15:13] == 3'b011)
)
? BSX_IS_PSRAM
: 1'b0);
wire [23:0] BSX_ADDR = bsx_regs[2] ? {1'b0, SNES_ADDR[22:0]}
: {2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]};
/* BSX regs:
Index Function
1 0=map flash to ROM area; 1=map PRAM to ROM area
@ -125,25 +180,25 @@ assign IS_WRITABLE = IS_SAVERAM
assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
?(IS_SAVERAM
? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
? 24'h600000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER == 3'b001)
?(IS_SAVERAM
? 24'hE00000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
? 24'h600000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK))
:(MAPPER == 3'b010)
?(IS_SAVERAM
? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
? 24'h600000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
& ROM_MASK))
:(MAPPER == 3'b011)
?(IS_SAVERAM
? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
? 24'h600000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
: IS_WRITABLE
? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
: bs_page_enable
@ -169,7 +224,7 @@ assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
)
:(MAPPER == 3'b110)
?(IS_SAVERAM
? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
? 24'h600000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
:(SNES_ADDR[15]
?({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
@ -182,7 +237,7 @@ assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
)
:(MAPPER == 3'b111)
?(IS_SAVERAM
? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
? 24'h7F0000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hC00000)

10
verilog/sd2snes/bsx.v
View File

@ -135,8 +135,8 @@ wire [7:0] rtc_year100 = rtc_data[51:48] + (rtc_data[55:52] << 3) + (rtc_data[55
wire [15:0] rtc_year = (rtc_year100 << 6) + (rtc_year100 << 5) + (rtc_year100 << 2) + rtc_year1;
initial begin
regs_tmpr <= 15'b000000100000000;
regs_outr <= 15'b000000100000000;
regs_tmpr <= 15'b000101111101100;
regs_outr <= 15'b000101111101100;
bsx_counter <= 0;
base_regs[5'h08] <= 0;
base_regs[5'h09] <= 0;
@ -213,7 +213,7 @@ always @(posedge clkin) begin
14: reg_data_outr <= rtc_day;
15: reg_data_outr <= rtc_month;
16: reg_data_outr <= rtc_year[7:0];
17: reg_data_outr <= rtc_year[15:8];
17: reg_data_outr <= rtc_hour;
default: reg_data_outr <= 8'h0;
endcase
end
@ -240,8 +240,8 @@ always @(posedge clkin) begin
regs_tmpr[8:1] <= (regs_tmpr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
end else if(reg_we_rising && cart_enable) begin
if(reg_addr == 4'he && reg_data_in[7])
regs_outr <= regs_tmpr | 15'b100000000000000;
if(reg_addr == 4'he)
regs_outr <= regs_tmpr;
else
regs_tmpr[reg_addr] <= reg_data_in[7];
end else if(reg_we_rising && base_enable) begin

57
verilog/sd2snes/main.v
View File

@ -440,6 +440,7 @@ address snes_addr(
.bs_page_offset(bs_page_offset),
.bs_page(bs_page),
.bs_page_enable(bs_page_enable),
.bsx_tristate(bsx_tristate),
//SRTC
.srtc_enable(srtc_enable),
//uPD77C25
@ -472,10 +473,10 @@ parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
parameter ST_MCU_WR_END = 18'b010000000000000000;
parameter ROM_RD_WAIT = 4'h0;
parameter ROM_RD_WAIT = 4'h1;
parameter ROM_RD_WAIT_MCU = 4'h6;
parameter ROM_WR_WAIT = 4'h4;
parameter ROM_WR_WAIT1 = 4'h2;
parameter ROM_WR_WAIT1 = 4'h3;
parameter ROM_WR_WAIT2 = 4'h1;
parameter ROM_WR_WAIT_MCU = 4'h5;
@ -533,8 +534,12 @@ initial ROM_SAr = 1'b1;
//wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
wire ROM_SA = ROM_SAr;
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
//assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
//assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
//WARNING DUE TO BAD SOLDER WE LOST HALF OF THE PSRAM!!!
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[22:0] : (ROM_SA) ? MAPPED_SNES_ADDR[22:0] : ROM_ADDRr[22:0];
assign ROM_ADDR0 = 1'b0; //(SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
reg ROM_WEr;
initial ROM_WEr = 1'b1;
@ -581,14 +586,12 @@ always @(posedge CLK2) begin
ROM_DOUT_ENr <= 1'b0;
if(SNES_cycle_start & ~SNES_WRITE) begin
STATE <= ST_SNES_WR_ADDR;
if(IS_SAVERAM | IS_WRITABLE | IS_FLASHWR) begin
if(IS_WRITABLE | (IS_FLASHWR & ~bsx_tristate)) begin
ROM_WEr <= 1'b0;
ROM_DOUT_ENr <= 1'b1;
end
end else if(SNES_cycle_start) begin
// STATE <= ST_SNES_RD_ADDR;
STATE <= ST_SNES_RD_END;
SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
STATE <= ST_SNES_RD_ADDR;
// STATE <= ST_SNES_RD_END;
end else if(SNES_DEADr & MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
end else if(SNES_DEADr & MCU_WR_PENDr) begin
@ -601,12 +604,15 @@ always @(posedge CLK2) begin
end
ST_SNES_RD_WAIT: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
// if(ST_MEM_DELAYr == 0) begin
// end
// else STATE <= ST_SNES_RD_WAIT;
if(ST_MEM_DELAYr == 0) begin
STATE <= ST_SNES_RD_END;
SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
else STATE <= ST_SNES_RD_WAIT;
end
ST_SNES_WR_ADDR: begin
ROM_DOUT_ENr <= 1'b1;
ST_MEM_DELAYr <= ROM_WR_WAIT1;
STATE <= ST_SNES_WR_WAIT1;
end
@ -624,11 +630,12 @@ always @(posedge CLK2) begin
if(ST_MEM_DELAYr == 0) begin
STATE <= ST_SNES_WR_END;
ROM_WEr <= 1'b1;
ROM_DOUT_ENr <= 1'b0;
end
else STATE <= ST_SNES_WR_WAIT2;
end
ST_SNES_RD_END, ST_SNES_WR_END: begin
ROM_DOUT_ENr <= 1'b0;
// ROM_DOUT_ENr <= 1'b0;
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
end else if(MCU_WR_PENDr) begin
@ -648,7 +655,7 @@ always @(posedge CLK2) begin
else STATE <= ST_MCU_RD_WAIT;
end
ST_MCU_RD_END: begin
MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8]; /*ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];*/
STATE <= ST_IDLE;
end
@ -657,18 +664,18 @@ always @(posedge CLK2) begin
ROM_SAr <= 1'b0;
ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
STATE <= ST_MCU_WR_WAIT;
ROM_DOUT_ENr <= 1'b1;
ROM_WEr <= 1'b0;
end
ST_MCU_WR_WAIT: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
ROM_DOUT_ENr <= 1'b1;
if(ST_MEM_DELAYr == 0) begin
ROM_WEr <= 1'b1;
STATE <= ST_MCU_WR_END;
end
else STATE <= ST_MCU_WR_WAIT;
end
ST_MCU_WR_END: begin
ST_MCU_WR_END: begin
ROM_DOUT_ENr <= 1'b0;
STATE <= ST_IDLE;
end
@ -704,18 +711,25 @@ always @(posedge CLK2) begin
MCU_WRITE_1<= MCU_WRITE;
end
/*
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
/*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
//: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA
: (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
/*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
//: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA
: (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
);
*/
assign ROM_DATA[7:0] = SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
assign ROM_DATA[15:8] = SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
@ -726,8 +740,8 @@ assign ROM_OE = 1'b0;
assign ROM_CE = 1'b0;
assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
assign ROM_BHE = 1'b0; ///*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
assign ROM_BLE = 1'b0; ///*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
msu_enable ? 1'b0 :
@ -739,6 +753,7 @@ assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
((IS_ROM & SNES_CS)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
|(SNES_READr[0] & SNES_WRITEr[0])
| bsx_tristate
);
assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescmd_rd_enable)))
@ -747,7 +762,7 @@ assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescm
assign SNES_IRQ = 1'b0;
assign p113_out = 1'b0;
assign p113_out = 1'b1;
/*
wire [35:0] CONTROL0;

2
verilog/sd2snes/sd2snes.xise
View File

@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">

50
verilog/sd2snes_cx4/main.v
View File

@ -370,13 +370,13 @@ parameter ST_CX4_RD_ADDR = 21'b000100000000000000000;
parameter ST_CX4_RD_WAIT = 21'b001000000000000000000;
parameter ST_CX4_RD_END = 21'b010000000000000000000;
parameter ROM_RD_WAIT = 4'h0;
parameter ROM_RD_WAIT = 4'h1;
parameter ROM_RD_WAIT_MCU = 4'h6;
parameter ROM_WR_WAIT = 4'h4;
parameter ROM_WR_WAIT1 = 4'h2;
parameter ROM_WR_WAIT1 = 4'h3;
parameter ROM_WR_WAIT2 = 4'h1;
parameter ROM_WR_WAIT_MCU = 4'h5;
parameter ROM_RD_WAIT_CX4 = 4'h6;
parameter ROM_RD_WAIT_CX4 = 4'h7;
parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
@ -510,9 +510,8 @@ always @(posedge CLK2) begin
ROM_DOUT_ENr <= 1'b1;
end
end else if(SNES_cycle_start) begin
// STATE <= ST_SNES_RD_ADDR;
STATE <= ST_SNES_RD_END;
SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
STATE <= ST_SNES_RD_ADDR;
// STATE <= ST_SNES_RD_END;
end else if(SNES_DEADr & MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
end else if(SNES_DEADr & MCU_WR_PENDr) begin
@ -525,12 +524,15 @@ always @(posedge CLK2) begin
end
ST_SNES_RD_WAIT: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
// if(ST_MEM_DELAYr == 0) begin
// end
// else STATE <= ST_SNES_RD_WAIT;
if(ST_MEM_DELAYr == 0) begin
STATE <= ST_SNES_RD_END;
SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
else STATE <= ST_SNES_RD_WAIT;
end
ST_SNES_WR_ADDR: begin
ROM_DOUT_ENr <= 1'b1;
ST_MEM_DELAYr <= ROM_WR_WAIT1;
STATE <= ST_SNES_WR_WAIT1;
end
@ -546,19 +548,19 @@ always @(posedge CLK2) begin
ST_SNES_WR_WAIT2: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) begin
STATE <= ST_SNES_WR_END;
ROM_WEr <= 1'b1;
STATE <= ST_SNES_WR_END;
ROM_WEr <= 1'b1;
end
else STATE <= ST_SNES_WR_WAIT2;
end
ST_SNES_RD_END, ST_SNES_WR_END: begin
ROM_DOUT_ENr <= 1'b0;
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
end else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
end else STATE <= ST_IDLE;
end
end
ST_SNES_RD_END, ST_SNES_WR_END: begin
// ROM_DOUT_ENr <= 1'b0;
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
end else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
end else STATE <= ST_IDLE;
end
ST_MCU_RD_ADDR: begin
ROM_SAr <= 1'b0;
ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
@ -581,12 +583,12 @@ always @(posedge CLK2) begin
ROM_SAr <= 1'b0;
ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
STATE <= ST_MCU_WR_WAIT;
ROM_DOUT_ENr <= 1'b1;
ROM_WEr <= 1'b0;
end
ST_MCU_WR_WAIT: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
ROM_DOUT_ENr <= 1'b1;
if(ST_MEM_DELAYr == 0) begin
ROM_WEr <= 1'b1;
STATE <= ST_MCU_WR_END;
end
@ -604,13 +606,13 @@ always @(posedge CLK2) begin
ST_CX4_RD_WAIT: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) begin
CX4_DINr <= CX4_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
STATE <= ST_CX4_RD_END;
end
else STATE <= ST_CX4_RD_WAIT;
end
ST_CX4_RD_END: begin
ROM_CAr <= 1'b0;
CX4_DINr <= CX4_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
STATE <= ST_IDLE;
end

8
verilog/sd2snes_test/ipcore_dir/PA.xco
View File

@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Fri Dec 9 20:36:25 2011
# Xilinx Core Generator version 13.4
# Date: Fri Aug 17 17:03:15 2012
#
##############################################################
#
@ -99,7 +99,7 @@ CSET write_width_a=8
CSET write_width_b=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
MISC pkg_timestamp=2011-03-11T08:24:14Z
# END Extra information
GENERATE
# CRC: 213d12c4
# CRC: 370f2518

2
verilog/sd2snes_test/ipcore_dir/PA.xise
View File

@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="PA.ngc" xil_pn:type="FILE_NGC">

8
verilog/sd2snes_test/ipcore_dir/bram.xco
View File

@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Fri Dec 9 20:35:22 2011
# Xilinx Core Generator version 13.4
# Date: Fri Aug 17 17:07:29 2012
#
##############################################################
#
@ -99,7 +99,7 @@ CSET write_width_a=8
CSET write_width_b=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
MISC pkg_timestamp=2011-03-11T08:24:14Z
# END Extra information
GENERATE
# CRC: cb4729a5
# CRC: 1d2c05e

2
verilog/sd2snes_test/ipcore_dir/bram.xise
View File

@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="bram.ngc" xil_pn:type="FILE_NGC">

8
verilog/sd2snes_test/ipcore_dir/dac_buf.xco
View File

@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Fri Dec 9 20:37:13 2011
# Xilinx Core Generator version 13.4
# Date: Fri Aug 17 17:13:12 2012
#
##############################################################
#
@ -99,7 +99,7 @@ CSET write_width_a=8
CSET write_width_b=32
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-06-21T06:43:52.000Z
MISC pkg_timestamp=2012-01-07T13:55:09Z
# END Extra information
GENERATE
# CRC: 360f80d1
# CRC: 786d7d96

2
verilog/sd2snes_test/ipcore_dir/dac_buf.xise
View File

@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="dac_buf.ngc" xil_pn:type="FILE_NGC">

33
verilog/sd2snes_test/main.v
View File

@ -29,12 +29,12 @@ module main(
input SNES_CS,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input SNES_SYSCLK,
input SNES_REFRESH,
input [7:0] SNES_PA,
input SNES_PARD,
input SNES_PAWR,
@ -386,8 +386,8 @@ end
wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? ram0_addr[23:1] : ROM_ADDRr[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? ram0_addr[0] : ROM_ADDRr[0];
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[22:0] : (ASSERT_SNES_ADDR) ? ram0_addr[22:0] : ROM_ADDRr[22:0];
assign ROM_ADDR0 = 1'b0; //(SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? ram0_addr[0] : ROM_ADDRr[0];
assign RAM_ADDR = ASSERT_SNES_ADDR ? ram1_addr : RAM_ADDRr;
@ -441,8 +441,8 @@ always @(posedge CLK2) begin
if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
else STATE <= ST_SNES_RD_WAIT;
if(ram0_enable) begin
if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
else SNES_DINr <= ROM_DATA[15:8];
if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
else SNES_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
end else if(ram1_enable) begin
SNES_DINr <= RAM_DATA[7:0];
end
@ -450,8 +450,8 @@ always @(posedge CLK2) begin
ST_SNES_RD_END: begin
STATE <= ST_IDLE;
if(ram0_enable) begin
if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
else SNES_DINr <= ROM_DATA[15:8];
if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
else SNES_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
end else if(ram1_enable) begin
SNES_DINr <= RAM_DATA[7:0];
end
@ -498,8 +498,8 @@ always @(posedge CLK2) begin
end
else STATE <= ST_MCU_RD_WAIT;
if(MCU_RAMSEL == 1'b0) begin
if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
else MCU_DINr <= ROM_DATA[15:8];
if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
else MCU_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
end else MCU_DINr <= RAM_DATA;
end
ST_MCU_RD_WAIT2: begin
@ -548,14 +548,11 @@ always @(posedge CLK2) begin
end
end
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
assign ROM_DATA[7:0] = (SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
: (!ROM_WE ? ROM_DOUTr : 8'bZ)
)
:8'bZ;
);
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
assign ROM_DATA[15:8] = (SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
: (!ROM_WE ? ROM_DOUTr : 8'bZ)
);
@ -575,7 +572,7 @@ assign ROM_OE = 1'b0;
assign ROM_CE = 1'b0;
assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
assign ROM_BLE = !ROM_WE ? ROM_ADDR0 : 1'b0;
assign SNES_DATABUS_OE = PA_enable ? 1'b0
: bram_enable ? 1'b0

49
verilog/sd2snes_test/sd2snes_test.xise
View File

@ -9,72 +9,63 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<file xil_pn:name="../sd2snes/srtc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/bram.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="ipcore_dir/PA.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/bram.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/PA.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/dac_buf.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
@ -126,8 +117,8 @@
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xa3s400" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
@ -242,7 +233,7 @@
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="pqg208" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
@ -316,7 +307,7 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="11" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="11" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@ -364,7 +355,7 @@
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>

4
verilog/sd2sneslite/address.v
View File

@ -47,10 +47,10 @@ assign IS_SAVERAM = (!SNES_ADDR[22]
);
assign SRAM_SNES_ADDR = (IS_SAVERAM
? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
? 24'h7F0000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hC00000)
+ 24'h500000)
);
assign ROM_ADDR = SRAM_SNES_ADDR;

26
verilog/sd2sneslite/main.v
View File

@ -101,7 +101,6 @@ wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
spi snes_spi(
.clk(CLK2),
@ -253,8 +252,7 @@ initial ROM_SAr = 1'b1;
//wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
wire ROM_SA = ROM_SAr;
assign ROM_ADDR = (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
assign ROM_ADDR0 = (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
assign ROM_ADDR = (ROM_SA) ? MAPPED_SNES_ADDR[22:0] : ROM_ADDRr[22:0];
reg ROM_WEr;
initial ROM_WEr = 1'b1;
@ -308,7 +306,8 @@ always @(posedge CLK2) begin
end else if(SNES_cycle_start) begin
// STATE <= ST_SNES_RD_ADDR;
STATE <= ST_SNES_RD_END;
SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
SNES_DOUTr <= ROM_DATA[7:0] | ROM_DATA[15:8];
//(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end else if(SNES_DEADr & MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
end else if(SNES_DEADr & MCU_WR_PENDr) begin
@ -368,7 +367,8 @@ always @(posedge CLK2) begin
else STATE <= ST_MCU_RD_WAIT;
end
ST_MCU_RD_END: begin
MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
//ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
STATE <= ST_IDLE;
end
@ -400,14 +400,10 @@ reg ROM_WE_1;
always @(posedge CLK2) begin
ROM_WE_1 <= ROM_WE;
end
assign ROM_DATA[7:0] = ROM_ADDR0
?(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
assign ROM_DATA[7:0] = (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
assign ROM_DATA[15:8] = (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
assign ROM_WE = ROM_WEr;
// OE always active. Overridden by WE when needed.
@ -415,8 +411,8 @@ assign ROM_OE = 1'b0;
assign ROM_CE = 1'b0;
assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
assign ROM_BHE = 1'b0;// /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
assign ROM_BLE = 1'b0;// /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
assign SNES_DATABUS_OE = ((IS_ROM & SNES_CS)
|(!IS_ROM & !IS_SAVERAM)

3
verilog/sd2sneslite/sd2sneslite.xise
View File

@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
@ -312,6 +312,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>