godzil/sd2snes
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

FPGA: prepare new SNES command interface for future use (SNES side)

Browse Source
This commit is contained in:
Maximilian Rehkopf 2012-07-09 01:29:47 +02:00
parent 0d02bfded7
commit 3530613349
4 changed files with 51 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
verilog/sd2snes/address.v
View File

@ -38,6 +38,8 @@ module address(
output dspx_dp_enable, output dspx_dp_enable,
output dspx_a0, output dspx_a0,
output r213f_enable, output r213f_enable,
output snescmd_rd_enable,
output snescmd_wr_enable,
input [8:0] bs_page_offset, input [8:0] bs_page_offset,
input [9:0] bs_page, input [9:0] bs_page,
input bs_page_enable input bs_page_enable
@ -244,4 +246,16 @@ initial r213f_enable_r = 6'b000000;
always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w}; always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w};
assign r213f_enable = &r213f_enable_r[5:2] & featurebits[FEAT_213F]; assign r213f_enable = &r213f_enable_r[5:2] & featurebits[FEAT_213F];
wire snescmd_rd_enable_w = (SNES_PA[7:4] == 4'b1111);
//reg [5:0] snescmd_rd_enable_r;
//initial snescmd_rd_enable_r = 6'b000000;
//always @(posedge CLK) snescmd_rd_enable_r <= {snescmd_rd_enable_r[4:0], snescmd_rd_enable_w};
assign snescmd_rd_enable = snescmd_rd_enable_w /*&snescmd_rd_enable_r[5:1]*/;
assign snescmd_wr_enable_w = (SNES_ADDR[23:4] == 20'hccccc);
//reg [5:0] snescmd_wr_enable_r;
//initial snescmd_wr_enable_r = 6'b000000;
//always @(posedge CLK) snescmd_wr_enable_r <= {snescmd_wr_enable_r[4:0], snescmd_wr_enable_w};
assign snescmd_wr_enable = snescmd_wr_enable_w /*&snescmd_wr_enable_r[5:1]*/;
endmodule endmodule

16
verilog/sd2snes/main.v
View File

@ -407,7 +407,9 @@ address snes_addr(
.dspx_enable(dspx_enable), .dspx_enable(dspx_enable),
.dspx_dp_enable(dspx_dp_enable), .dspx_dp_enable(dspx_dp_enable),
.dspx_a0(DSPX_A0), .dspx_a0(DSPX_A0),
.r213f_enable(r213f_enable) .r213f_enable(r213f_enable),
.snescmd_rd_enable(snescmd_rd_enable),
.snescmd_wr_enable(snescmd_wr_enable)
); );
parameter MODE_SNES = 1'b0; parameter MODE_SNES = 1'b0;
@ -457,9 +459,11 @@ initial r213f_forceread = 0;
initial r213f_state = 2'b01; initial r213f_state = 2'b01;
initial r213f_delay = 3'b011; initial r213f_delay = 3'b011;
reg[7:0] snescmd_regs[15:0];
assign SNES_DATA = (r213f_enable & (!SNES_PARD ^ r213f_forceread)) ? r213fr assign SNES_DATA = (snescmd_rd_enable & ~SNES_PARD) ? snescmd_regs[SNES_ADDR[3:0]]
:(!SNES_READ ^ r213f_forceread) :(r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
? (srtc_enable ? SRTC_SNES_DATA_OUT ? (srtc_enable ? SRTC_SNES_DATA_OUT
:dspx_enable ? DSPX_SNES_DATA_OUT :dspx_enable ? DSPX_SNES_DATA_OUT
:dspx_dp_enable ? DSPX_SNES_DATA_OUT :dspx_dp_enable ? DSPX_SNES_DATA_OUT
@ -629,6 +633,12 @@ always @(posedge SYSCLK2) begin
end end
end end
always @(posedge CLK2) begin
if(SNES_WR_end & snescmd_wr_enable) begin
snescmd_regs[SNES_ADDR[3:0]] <= SNES_DATA;
end
end
assign ROM_DATA[7:0] = ROM_ADDR0 assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ) ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
: (!ROM_WE ? ROM_DOUTr : 8'bZ) : (!ROM_WE ? ROM_DOUTr : 8'bZ)

15
verilog/sd2snes_cx4/address.v
View File

@ -34,7 +34,9 @@ module address(
output msu_enable, output msu_enable,
output cx4_enable, output cx4_enable,
output cx4_vect_enable, output cx4_vect_enable,
output r213f_enable output r213f_enable,
output snescmd_rd_enable,
output snescmd_wr_enable
); );
wire [23:0] SRAM_SNES_ADDR; wire [23:0] SRAM_SNES_ADDR;
@ -68,9 +70,12 @@ assign cx4_enable = &cx4_enable_r[5:2];
assign cx4_vect_enable = &SNES_ADDR[15:5]; assign cx4_vect_enable = &SNES_ADDR[15:5];
wire r213f_enable_w = (SNES_PA == 8'h3f); wire r213f_enable_w = (SNES_PA == 8'h3f);
reg [5:0] r213f_enable_r; assign r213f_enable = r213f_enable_w;
initial r213f_enable_r = 6'b000000;
always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w}; wire snescmd_rd_enable_w = (SNES_PA[7:4] == 4'b1111);
assign r213f_enable = &r213f_enable_r[5:2]; assign snescmd_rd_enable = snescmd_rd_enable_w;
wire snescmd_wr_enable_w = (SNES_ADDR[23:4] == 20'hccccc);
assign snescmd_wr_enable = snescmd_wr_enable_w;
endmodule endmodule

22
verilog/sd2snes_cx4/main.v
View File

@ -304,7 +304,11 @@ address snes_addr(
//CX4 //CX4
.cx4_enable(cx4_enable), .cx4_enable(cx4_enable),
.cx4_vect_enable(cx4_vect_enable), .cx4_vect_enable(cx4_vect_enable),
.r213f_enable(r213f_enable) //region
.r213f_enable(r213f_enable),
//CMD Interface
.snescmd_rd_enable(snescmd_rd_enable),
.snescmd_wr_enable(snescmd_wr_enable)
); );
reg [7:0] CX4_DINr; reg [7:0] CX4_DINr;
@ -379,13 +383,15 @@ initial r213f_forceread = 0;
initial r213f_state = 2'b01; initial r213f_state = 2'b01;
initial r213f_delay = 3'b011; initial r213f_delay = 3'b011;
assign SNES_DATA = (r213f_enable & (!SNES_PARD ^ r213f_forceread)) ? r213fr reg[7:0] snescmd_regs[15:0];
:(!SNES_READ ^ r213f_forceread)
? (msu_enable ? MSU_SNES_DATA_OUT assign SNES_DATA = (snescmd_rd_enable & ~SNES_PARD) ? snescmd_regs[SNES_ADDR[3:0]]
:cx4_enable ? CX4_SNES_DATA_OUT :(r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT :(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
:SNES_DINr) ? (msu_enable ? MSU_SNES_DATA_OUT
: 8'bZ; :cx4_enable ? CX4_SNES_DATA_OUT
:(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
:SNES_DOUTr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
reg [3:0] ST_MEM_DELAYr; reg [3:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr; reg MCU_RD_PENDr;