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FPGA/MSU: more robust edge detection

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This commit is contained in:
Maximilian Rehkopf 2011-08-17 00:15:07 +02:00
parent f18f809cfa
commit 3d608f2785
1 changed files with 2 additions and 2 deletions
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verilog/sd2snes/msu.v
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@ -72,11 +72,11 @@ always @(posedge clkin) reg_enable_sreg <= {reg_enable_sreg[6:0], enable};
reg [5:0] reg_oe_sreg;
always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe};
//wire reg_oe_falling = (reg_oe_sreg[3:0] == 4'b1000);
wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[1:0] == 2'b01);
wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001);
reg [5:0] reg_we_sreg;
always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[4:0], reg_we};
wire reg_we_rising = reg_enable_sreg[4] && (reg_we_sreg[1:0] == 2'b01);
wire reg_we_rising = reg_enable_sreg[4] && (reg_we_sreg[5:0] == 6'b000001);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;