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FPGA: uPD77c25 WIP

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This commit is contained in:
ikari 2011-06-11 03:32:37 +02:00
parent 00e090aef9
commit 56538dc5e1
9 changed files with 400 additions and 313 deletions
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48
verilog/sd2snes/address.v
View File

@ -52,7 +52,9 @@ wire [23:0] SRAM_ADDR_FULL;
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
011 BS-X
011 BS-X
100 DSPx (HiROM - 00-0f:6000-7fff)
101 DSPx (LoROM - 30-3f:8000-ffff)
110 brainfuck interleaved 96MBit Star Ocean =)
111 menu (ROM in upper SRAM)
*/
@ -66,28 +68,30 @@ assign IS_ROM = ( (MAPPER == 3'b000) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b010) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b011) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b110) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b011) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b100) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b101) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b110) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b111) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: 1'b0);
assign IS_SAVERAM = ((MAPPER == 3'b000 || MAPPER == 3'b010 || MAPPER == 3'b110 || MAPPER == 3'b111) ? (!SNES_ADDR[22]
& SNES_ADDR[21:20]
assign IS_SAVERAM = ((MAPPER == 3'b000 || MAPPER == 3'b010 || MAPPER == 3'b100 || MAPPER == 3'b110 || MAPPER == 3'b111) ? (!SNES_ADDR[22]
& &SNES_ADDR[21:20]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
& SNES_CS
)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd
Offset 0000-7fff TODO: 0000-ffff for
small ROMs */
:(MAPPER == 3'b001) ? (&SNES_ADDR[22:20]
:(MAPPER == 3'b001 || MAPPER == 3'b101) ? (&SNES_ADDR[22:20]
& (SNES_ADDR[19:16] < 4'b1110)
& !SNES_ADDR[15]
& !SNES_CS)
& !SNES_ADDR[15])
/* BS-X: SRAM @ Bank 0x10-0x17
Offset 5000-5fff */
:(MAPPER == 3'b011) ? ((SNES_ADDR[23:19] == 5'b00010)
@ -118,10 +122,10 @@ assign IS_WRITABLE = IS_SAVERAM | (
*/
assign SRAM_ADDR_FULL = (MODE) ? MCU_ADDR
: ((MAPPER == 3'b000) ?
: ((MAPPER[1:0] == 2'b00) ?
(IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER == 3'b001) ?
:(MAPPER[1:0] == 2'b01) ?
(IS_SAVERAM ? 24'hE00000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK))
:(MAPPER == 3'b010) ?
@ -156,8 +160,20 @@ assign use_bsx = (MAPPER == 3'b011);
assign srtc_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
// DSP1 1mb lorom: DR=20-3f:8000-bfff; SR=20-3f:c000-ffff
assign dspx_enable = (MAPPER == 3'b001) && (!SNES_ADDR[22] && SNES_ADDR[21] && (SNES_ADDR[15] == 1'b1));
assign dspx_a0 = SNES_ADDR[14];
// DSP1 LoROM: DR=30-3f:8000-bfff; SR=30-3f:c000-ffff
// or DR=60-6f:0000-3fff; SR=60-6f:4000-7fff
// DSP1 HiROM: DR=00-0f:6000-6fff; SR=00-0f:7000-7fff
assign dspx_enable =
(MAPPER == 3'b101) ?
(ROM_MASK[20] ?
(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15])
:(~SNES_ADDR[22] & SNES_ADDR[21] & SNES_ADDR[20] & SNES_ADDR[15])
)
:(MAPPER == 3'b100) ?
(~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & &SNES_ADDR[14:13]/* & CS */)
:1'b0;
assign dspx_a0 = (MAPPER == 3'b101) ? SNES_ADDR[14]
:(MAPPER == 3'b100) ? SNES_ADDR[12]
:1'b1;
endmodule

28
verilog/sd2snes/ipcore_dir/upd77c25_datrom.v
View File

@ -39,13 +39,21 @@
module upd77c25_datrom(
clka,
wea,
addra,
douta
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
output [15 : 0] douta;
input [15 : 0] dina;
input clkb;
input [9 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
@ -57,7 +65,7 @@ output [15 : 0] douta;
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
@ -81,7 +89,7 @@ output [15 : 0] douta;
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
@ -111,21 +119,21 @@ output [15 : 0] douta;
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DOUTA(douta),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),

16
verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco
View File

@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 13.1
# Date: Thu Jun 2 00:42:40 2011
# Date: Thu Jun 9 10:19:40 2011
#
##############################################################
#
@ -37,12 +37,12 @@ SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes/dsp1b_datrom.coe
CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes/dsp4_dat.coe
CSET collision_warnings=ALL
CSET component_name=upd77c25_datrom
CSET disable_collision_warnings=false
@ -55,7 +55,7 @@ CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=true
CSET memory_type=Single_Port_ROM
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
@ -63,9 +63,9 @@ CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=0
CSET port_b_clock=0
CSET port_b_enable_rate=0
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=16
@ -98,4 +98,4 @@ CSET write_width_b=16
MISC pkg_timestamp=2011-02-03T22:20:43.000Z
# END Extra information
GENERATE
# CRC: d64159b2
# CRC: 9cef39ed

4
verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v
View File

@ -111,8 +111,8 @@ output [23 : 0] doutb;
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_MODE_B("NO_CHANGE"),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(24),
.C_WRITE_WIDTH_B(24),
.C_XDEVICEFAMILY("spartan3")

12
verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco
View File

@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 13.1
# Date: Tue May 31 20:54:32 2011
# Date: Thu Jun 9 08:57:56 2011
#
##############################################################
#
@ -20,7 +20,7 @@ SET createndf = false
SET designentry = Advanced
SET device = xc3s400
SET devicefamily = spartan3
SET flowvendor = Foundation_ISE
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
@ -42,7 +42,7 @@ CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes/dsp1b_pgmrom.coe
CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes/dsp4_pgm.coe
CSET collision_warnings=ALL
CSET component_name=upd77c25_pgmrom
CSET disable_collision_warnings=false
@ -56,8 +56,8 @@ CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=true
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=NO_CHANGE
CSET operating_mode_b=NO_CHANGE
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
@ -98,4 +98,4 @@ CSET write_width_b=24
MISC pkg_timestamp=2011-02-03T22:20:43.000Z
# END Extra information
GENERATE
# CRC: f1fd9704
# CRC: 85a39b6f

34
verilog/sd2snes/main.v
View File

@ -121,6 +121,14 @@ wire [7:0] SRTC_SNES_DATA_OUT;
wire [7:0] DSPX_SNES_DATA_IN;
wire [7:0] DSPX_SNES_DATA_OUT;
wire [23:0] dspx_pgm_data;
wire [10:0] dspx_pgm_addr;
wire dspx_pgm_we;
wire [15:0] dspx_dat_data;
wire [9:0] dspx_dat_addr;
wire dspx_dat_we;
//wire SD_DMA_EN; //SPI_DMA_CTRL;
sd_dma snes_sd_dma(.CLK(CLK2),
@ -238,14 +246,14 @@ upd77c25 snes_dspx (
.nCS(~dspx_enable),
.nRD(SNES_READ),
.nWR(SNES_WRITE),
.RST(1'b1 /* XXX DSPX_RST*/),
.RST(~dspx_reset),
.CLK(CLK2),
.PGM_WR(DSPX_PGM_WR),
.PGM_DI(DSPX_PGM_DI),
.PGM_WR_ADDR(DSPX_PGM_WR_ADDR),
.DAT_WR(DSPX_DAT_WR),
.DAT_DI(DSPX_DAT_DI),
.DAT_WR_ADDR(DSPX_DAT_WR_ADDR)
.PGM_WR(dspx_pgm_we),
.PGM_DI(dspx_pgm_data),
.PGM_WR_ADDR(dspx_pgm_addr),
.DAT_WR(dspx_dat_we),
.DAT_DI(dspx_dat_data),
.DAT_WR_ADDR(dspx_dat_addr)
);
mcu_cmd snes_mcu_cmd(
@ -299,7 +307,14 @@ mcu_cmd snes_mcu_cmd(
.bsx_regs_reset_we(bsx_regs_reset_we),
.rtc_data_out(rtc_data_in),
.rtc_pgm_we(rtc_pgm_we),
.srtc_reset(srtc_reset)
.srtc_reset(srtc_reset),
.dspx_pgm_data_out(dspx_pgm_data),
.dspx_pgm_addr_out(dspx_pgm_addr),
.dspx_pgm_we_out(dspx_pgm_we),
.dspx_dat_data_out(dspx_dat_data),
.dspx_dat_addr_out(dspx_dat_addr),
.dspx_dat_we_out(dspx_dat_we),
.dspx_reset_out(dspx_reset)
);
// dcm1: dfs 4x
@ -689,7 +704,8 @@ assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
//assign SRAM_WE = !MCU_ENA ? MCU_WRITE : 1'b1;
//assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
assign SNES_DATABUS_OE = msu_enable ? (SNES_READ & SNES_WRITE) :
assign SNES_DATABUS_OE = dspx_enable ? 1'b0 :
msu_enable ? (SNES_READ & SNES_WRITE) :
bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
srtc_enable ? (SNES_READ & SNES_WRITE) : ((IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR) | (SNES_READ & SNES_WRITE));
assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;

55
verilog/sd2snes/mcu_cmd.v
View File

@ -82,11 +82,27 @@ module mcu_cmd(
// S-RTC
output srtc_reset,
// uPD77C25
output reg [23:0] dspx_pgm_data_out,
output reg [10:0] dspx_pgm_addr_out,
output reg dspx_pgm_we_out,
output reg [15:0] dspx_dat_data_out,
output reg [9:0] dspx_dat_addr_out,
output reg dspx_dat_we_out,
output reg dspx_reset_out,
// SNES sync/clk
input snes_sysclk
);
);
initial begin
dspx_pgm_addr_out = 11'b00000000000;
dspx_dat_addr_out = 9'b000000000;
dspx_reset_out = 1'b1;
end
wire [31:0] snes_sysclk_freq;
@ -172,6 +188,7 @@ initial begin
DAC_VOL_LATCH_BUF = 0;
spi_dma_nextaddr_r = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
end
// command interpretation
@ -346,7 +363,41 @@ always @(posedge clk) begin
srtc_reset_buf <= 1'b0;
end
endcase
8'he8: begin// reset DSPx PGM+DAT address
case (spi_byte_cnt)
32'h2: begin
dspx_pgm_addr_out <= 11'b00000000000;
dspx_dat_addr_out <= 9'b000000000;
end
endcase
end
8'he9:// write DSPx PGM w/ increment
case (spi_byte_cnt)
32'h2: dspx_pgm_data_out[23:16] <= param_data[7:0];
32'h3: dspx_pgm_data_out[15:8] <= param_data[7:0];
32'h4: dspx_pgm_data_out[7:0] <= param_data[7:0];
32'h5: dspx_pgm_we_out <= 1'b1;
32'h6: begin
dspx_pgm_we_out <= 1'b0;
dspx_pgm_addr_out <= dspx_pgm_addr_out + 1;
end
endcase
8'hea:// write DSPx DAT w/ increment
case (spi_byte_cnt)
32'h2: dspx_dat_data_out[15:8] <= param_data[7:0];
32'h3: dspx_dat_data_out[7:0] <= param_data[7:0];
32'h4: dspx_dat_we_out <= 1'b1;
32'h5: begin
dspx_dat_we_out <= 1'b0;
dspx_dat_addr_out <= dspx_dat_addr_out + 1;
end
endcase
8'heb: // put DSPx into reset
dspx_reset_out <= 1'b1;
8'hec: // release DSPx reset
dspx_reset_out <= 1'b0;
endcase
end
if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[3]) && (spi_byte_cnt > (32'h1+cmd_data[4])))) begin
case (SD_DMA_TGTr)

386
verilog/sd2snes/sd2snes.xise
View File

@ -9,132 +9,145 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="data.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="dac_dcm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="rtc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_datrom.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="bsx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="dac_dcm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="data.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="rtc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="main_tf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="updtest_tf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_datrom.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_datram.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="ipcore_dir/pgmrom.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="ipcore_dir/dac_buf.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/msu_databuf.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_datrom.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_datram.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/pgmrom.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
<property xil_pn:name="Add File to project" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Pads" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Advanced FSM Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Array Bounds Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Constrain" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Baud rate" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
@ -146,7 +159,6 @@
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SmartModels (PPC, MGT) Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
@ -157,10 +169,8 @@
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Powerdown" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Convert Tristates To Logic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -170,49 +180,36 @@
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Default Enum Encoding Goal" xil_pn:value="default" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Bandgap Generator for DCMs to save power" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable I/O insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Display Incremental Messages" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="EDIF" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Extra Effort" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fanout Guide" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Frequency" xil_pn:value="0.0" xil_pn:valueState="default"/>
<property xil_pn:name="Full Case" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
@ -223,34 +220,26 @@
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate UCF from RTL Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 0 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 1 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 2 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 3 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Start View" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="AbstractSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="main.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
@ -258,47 +247,35 @@
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Key 1 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Key 2 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Key 3 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Key 4 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Key 5 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance without IOB Packing;/mnt/store/bin/Xilinx/12.3/ISE_DS/ISE/spartan3/data/spartan3_performance_without_iobpacking.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load Timing Specification Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 0 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 1 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 2 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 3 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 4 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 5 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Message Filter File" xil_pn:value="filter.filter" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
@ -307,14 +284,10 @@
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Critical Paths" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Critical Paths Synthesis" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Start/End Points" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Summary Paths" xil_pn:value="10" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
@ -328,33 +301,27 @@
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Precision Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Synplify Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Base Name" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
<property xil_pn:name="Parallel Case" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="main_timesim.v" xil_pn:valueState="default"/>
@ -362,70 +329,54 @@
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Precision Optimization Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Push Tristates across Process/Block Boundaries" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Set/Reset (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Clock Frequencies" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Critical Paths" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Missing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Timing Summary" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Timing Violations" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Resource Sharing Precision" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing Synthesis" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/upd77c25" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.upd77c25" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/updtest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Show Clock Domain Crossing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Show Net Fan Out" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
@ -439,34 +390,29 @@
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.upd77c25" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Search Directories for 'Include" xil_pn:value="../sd2snes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting CBC Value (Hex)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Key" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Symbolic FSM Compiler" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Sysgen Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Transform Set/Reset on DFFs to Latches" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tri-state Buffer Transformation Mode" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Update modelsim.ini File for Xilinx SmartModel Use" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -475,7 +421,6 @@
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -484,56 +429,49 @@
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP48" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Safe FSM" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/ikari/prj/sd2snes/verilog/sd2snes/smartxplorer_results/run2/currentprojectnavigatorsettingsct2.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax Precision" xil_pn:value="VHDL 93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Standard" xil_pn:value="Verilog 2001" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Mapped VHDL Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Write Mapped Verilog Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Write Vendor Constraint File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|upd77c25" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|updtest" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|tf_main_3" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="Module|updtest" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|updtest" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Module|updtest" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-02-09T13:53:51" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="4242BCD96D77D9605D7AD490E992E4A2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-05-31T10:16:17" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BA4DFC5FF4C86353E777AD9971C302BC" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<bindings>
<binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
</bindings>
<libraries/>

130
verilog/sd2snes/upd77c25.v
View File

@ -13,7 +13,7 @@
// Dependencies:
//
// Revision:
// Revision 0.1 - core fully operational, no firmware download
// Revision 0.2 - core fully operational, firmware download
//
//////////////////////////////////////////////////////////////////////////////////
module upd77c25(
@ -78,10 +78,15 @@ wire [10:0] pgm_addra;
wire [23:0] pgm_dina;
wire [23:0] pgm_doutb;
pgmrom pgmrom (
.clka(CLK),
.addra(pc), // Bus [10 : 0]
.douta(pgm_doutb)); // Bus [23 : 0]
upd77c25_pgmrom pgmrom (
.clka(CLK), // input clka
.wea(PGM_WR), // input [0 : 0] wea
.addra(PGM_WR_ADDR), // input [10 : 0] addra
.dina(PGM_DI), // input [23 : 0] dina
.clkb(CLK), // input clkb
.addrb(pc), // input [10 : 0] addrb
.doutb(pgm_doutb) // output [23 : 0] doutb
);
wire [23:0] opcode_w = pgm_doutb;
reg [23:0] opcode;
@ -100,9 +105,14 @@ wire [15:0] dat_dina;
wire [15:0] dat_doutb;
upd77c25_datrom datrom (
.clka(CLK),
.addra(regs_rp), // Bus [9 : 0]
.douta(dat_doutb)); // Bus [15 : 0]
.clka(CLK), // input clka
.wea(DAT_WR), // input [0 : 0] wea
.addra(DAT_WR_ADDR), // input [9 : 0] addra
.dina(DAT_DI), // input [15 : 0] dina
.clkb(CLK), // input clkb
.addrb(regs_rp), // input [9 : 0] addrb
.doutb(dat_doutb) // output [15 : 0] doutb
);
wire [15:0] ram_douta;
wire [7:0] ram_addra;
@ -149,14 +159,14 @@ reg [15:0] idb;
reg [15:0] regs_ab [1:0];
/*assign DR = regs_dr;
assign DR = regs_dr;
assign SR = regs_sr;
assign PC = pc;
assign A = regs_ab[0];
assign B = regs_ab[1];
assign FL_A = {flags_s1[0],flags_s0[0],flags_c[0],flags_z[0],flags_ov1[0],flags_ov0[0]};
assign FL_B = {flags_s1[1],flags_s0[1],flags_c[1],flags_z[1],flags_ov1[1],flags_ov0[1]};
*/
initial begin
alu_store = 2'b11;
@ -186,22 +196,25 @@ always @(posedge CLK) begin
end
reg [5:0] reg_nCS_sreg;
initial reg_nCS_sreg = 6'b111111;
always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[4:0], nCS};
reg [5:0] reg_oe_sreg;
initial reg_oe_sreg = 6'b111111;
always @(posedge CLK) reg_oe_sreg <= {reg_oe_sreg[4:0], nRD};
wire reg_oe_falling = !nCS && (reg_oe_sreg[3:0] == 4'b1110);
wire reg_oe_falling = !nCS && (reg_oe_sreg[3:0] == 4'b1000);
reg [3:0] reg_we_sreg;
initial reg_we_sreg = 4'b1111;
always @(posedge CLK) reg_we_sreg <= {reg_we_sreg[2:0], nWR};
wire reg_we_rising = !nCS && (reg_we_sreg[3:0] == 4'b0001);
reg [5:0] reg_we_sreg;
initial reg_we_sreg = 6'b111111;
always @(posedge CLK) reg_we_sreg <= {reg_we_sreg[4:0], nWR};
wire reg_we_rising = !nCS && (reg_we_sreg[5:0] == 6'b000001);
always @(posedge CLK) begin
if(RST) begin
if((op_src == 4'b1000 && op[1] == 1'b0 && insn_state == 3'b011)
|| (op_dst == 4'b0110 && op != 2'b10 && insn_state == 3'b011)) regs_sr[SR_RQM] <= 1'b1;
else if(reg_we_rising && A0 == 1'b0) begin
if((reg_we_rising) && (A0 == 1'b0)) begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b1) begin
regs_sr[SR_RQM] <= 1'b0;
@ -209,9 +222,10 @@ always @(posedge CLK) begin
end else begin
regs_sr[SR_RQM] <= 1'b0;
end
end else if(reg_oe_falling) begin
case(A0)
1'b0: begin
end
else if(reg_oe_falling && (A0 == 1'b0)) begin
// case(A0)
// 1'b0: begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b1) begin
regs_sr[SR_RQM] <= 1'b0;
@ -219,9 +233,9 @@ always @(posedge CLK) begin
end else begin
regs_sr[SR_RQM] <= 1'b0;
end
end
endcase
end
// end
// endcase
end
end else begin
regs_sr[SR_RQM] <= 1'b0;
end
@ -229,31 +243,62 @@ end
always @(posedge CLK) begin
if(RST) begin
if(ld_dst == 4'b0110 && insn_state == 3'b011) begin
if (op == I_OP || op == I_RT) regs_dr <= idb;
else if (op == I_LD) regs_dr <= ld_id;
end
else if(reg_we_rising && A0 == 1'b0) begin
if(reg_we_rising && (A0 == 1'b0)) begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b0) begin
regs_sr[SR_DRS] <= 1'b1;
regs_dr[7:0] <= DI;
end else begin
regs_sr[SR_DRS] <= 1'b0;
regs_dr[15:8] <= DI;
end
end else begin
regs_dr[7:0] <= DI;
end
end
end else if(reg_oe_falling) begin
case(A0)
1'b0: begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b0) begin
regs_sr[SR_DRS] <= 1'b1;
DO <= regs_dr[7:0];
end else begin
regs_sr[SR_DRS] <= 1'b0;
end
end
end
endcase
end
end else begin
regs_sr[SR_DRS] <= 1'b0;
end
end
always @(posedge CLK) begin
if(RST) begin
if(reg_we_rising && (A0 == 1'b0)) begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b0) begin
regs_dr[7:0] <= DI;
end else begin
regs_dr[15:8] <= DI;
end
end else begin
regs_dr[7:0] <= DI;
end
end else if(ld_dst == 4'b0110 && insn_state == 3'b011) begin
if (op == I_OP || op == I_RT) regs_dr <= idb;
else if (op == I_LD) regs_dr <= ld_id;
end
end else begin
regs_dr <= 16'h0000;
end
end
always @(posedge CLK) begin
if(RST) begin
if(reg_oe_falling) begin
case(A0)
1'b0: begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b0) begin
DO <= regs_dr[7:0];
end else begin
DO <= regs_dr[15:8];
end
end else begin
@ -264,8 +309,6 @@ always @(posedge CLK) begin
endcase
end
end else begin
regs_sr[SR_DRS] <= 1'b0;
regs_dr <= 16'h0000;
DO <= 8'h00;
end
end
@ -285,7 +328,7 @@ always @(posedge CLK) begin
op_rpdcr <= opcode_w[8];
op_src <= opcode_w[7:4];
op_dst <= opcode_w[3:0];
jp_brch = opcode_w[21:13];
jp_brch <= opcode_w[21:13];
jp_na <= opcode_w[12:2];
ld_id <= opcode_w[21:6];
@ -579,6 +622,21 @@ always @(posedge CLK) begin
flags_s1 <= 2'b0;
regs_tr <= 16'b0;
regs_trb <= 16'b0;
opcode <= 23'b0;
op_pselect <= 2'b0;
op_alu <= 4'b0;
op_asl <= 1'b0;
op_dpl <= 2'b0;
op_dphm <= 4'b0;
op_rpdcr <= 1'b0;
op_src <= 4'b0;
op_dst <= 4'b0;
jp_brch <= 9'b0;
jp_na <= 11'b0;
ld_id <= 16'b0;
ld_dst <= 4'b0;
regs_m <= 16'b0;
regs_n <= 16'b0;
end
end