godzil/sd2snes
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certainly something

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This commit is contained in:
ikari 2009-10-03 22:46:27 +02:00
parent 38812ce99d
commit 64899bdb22
8 changed files with 66 additions and 22 deletions
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4
src/Makefile
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@ -308,10 +308,10 @@ endif
# Type: avrdude -c ?
# to get a full listing.
#
AVRDUDE_PROGRAMMER = stk200
AVRDUDE_PROGRAMMER = dragon_isp
# com1 = serial port. Use lpt1 to connect to parallel port.
AVRDUDE_PORT = /dev/parport0 # programmer connected to serial device
AVRDUDE_PORT = usb # programmer connected to serial device
AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex
# AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep

2
src/filetypes.c
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@ -118,7 +118,7 @@ FRESULT get_db_id(uint16_t* id) {
file_open("/sd2snes/sd2snes.db", FA_READ);
if(file_res == FR_OK) {
file_readblock(id, 0, 2);
/* XXX */ *id=0xdead;
/* XXX */// *id=0xdead;
file_close();
} else {
*id=0xdead;

3
src/main.c
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@ -127,7 +127,7 @@ int main(void) {
#ifdef CLOCK_PRESCALE
clock_prescale_set(CLOCK_PRESCALE);
#endif
spi_none();
snes_reset(1);
uart_init();
sei(); // suspected to reset the AVR when inserting an SD card
@ -145,6 +145,7 @@ int main(void) {
uart_putc('W');
fpga_init();
fpga_pgm("/sd2snes/main.bit");
_delay_ms(100);
fpga_spi_init();
uart_putc('!');
_delay_ms(100);

4
src/snes.c
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@ -47,7 +47,7 @@ void snes_reset(int state) {
void snes_main_loop() {
if(initloop) {
saveram_crc_old = calc_sram_crc(saveram_base_addr, saveram_size);
save_sram("/quite a long test filename.srm", saveram_size, saveram_base_addr);
save_sram("/test.srm", saveram_size, saveram_base_addr);
initloop=0;
}
saveram_crc = calc_sram_crc(saveram_base_addr, saveram_size);
@ -56,7 +56,7 @@ void snes_main_loop() {
uart_puthexshort(saveram_crc);
uart_putcrlf();
set_busy_led(1);
save_sram("/quite a long test filename.srm", saveram_size, saveram_base_addr);
save_sram("/test.srm", saveram_size, saveram_base_addr);
set_busy_led(0);
}
saveram_crc_old = saveram_crc;

12
verilog/sd2snes/dcm.v
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@ -20,12 +20,10 @@
//////////////////////////////////////////////////////////////////////////////////
module my_dcm (
input CLKIN,
input CLKFB,
output CLK2X,
output CLKFX,
output CLK0,
output LOCKED,
input RST
input RST,
output[7:0] STATUS
);
// DCM: Digital Clock Manager Circuit
@ -39,10 +37,10 @@ module my_dcm (
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(46.561), // Specify period of input clock
.CLKIN_PERIOD(36.561), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
.DESKEW_ADJUST("SOURCE_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
@ -50,7 +48,7 @@ module my_dcm (
.FACTORY_JF(16'hC080), // FACTORY JF values
// .LOC("DCM_X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output

14
verilog/sd2snes/main.ucf
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@ -74,7 +74,6 @@ NET "SNES_REFRESH" IOSTANDARD = LVCMOS33;
NET "SPI_MISO" IOSTANDARD = LVCMOS33;
NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
NET "SPI_SCK" IOSTANDARD = LVCMOS33;
NET "SPI_SS" IOSTANDARD = LVCMOS33;
NET "SRAM_DATA[10]" IOSTANDARD = LVCMOS33;
NET "SRAM_DATA[11]" IOSTANDARD = LVCMOS33;
NET "SRAM_DATA[12]" IOSTANDARD = LVCMOS33;
@ -181,8 +180,7 @@ NET "SRAM_DATA[7]" LOC = P116;
NET "SRAM_DATA[8]" LOC = P96;
NET "SRAM_DATA[9]" LOC = P98;
NET "SRAM_OE" LOC = P93;
NET "CLKIN" IOSTANDARD = LVCMOS33;
TIMESPEC TS_test = FROM "FFS" TO "FFS" 10 ns;
TIMESPEC TS_test = FROM FFS TO FFS 10 ns;
NET "SNES_ADDR<0>" MAXDELAY = 10 ns;
NET "SNES_ADDR<0>" MAXSKEW = 5 ns;
NET "SNES_ADDR<1>" MAXDELAY = 10 ns;
@ -231,3 +229,13 @@ NET "SNES_ADDR<22>" MAXDELAY = 10 ns;
NET "SNES_ADDR<22>" MAXSKEW = 5 ns;
NET "SNES_ADDR<23>" MAXDELAY = 10 ns;
NET "SNES_ADDR<23>" MAXSKEW = 5 ns;
NET "CLKIN" IOSTANDARD = LVCMOS33;
NET "CLKIN" PULLUP;
NET "SPI_SS" IOSTANDARD = LVCMOS33;
NET "SPI_SS" PULLUP;
NET "DCM_FX_STOPPED" LOC = P44;
NET "DCM_FX_STOPPED" IOSTANDARD = LVCMOS33;
NET "DCM_IN_STOPPED" LOC = P41;
NET "DCM_IN_STOPPED" IOSTANDARD = LVCMOS33;
//NET "DCM_RST" LOC = P46;
//NET "DCM_RST" IOSTANDARD = LVCMOS33;

48
verilog/sd2snes/main.v
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@ -49,10 +49,12 @@ module main(
output SPI_MISO,
input SPI_SS,
input SPI_SCK,
input AVR_ENA
input AVR_ENA,
/* debug */
output DCM_IN_STOPPED,
output DCM_FX_STOPPED
//input DCM_RST
);
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
@ -107,15 +109,49 @@ avr_cmd snes_avr_cmd(
.rom_mask_out(ROM_MASK)
);
wire [7:0] DCM_STATUS;
assign DCM_FX_STOPPED = DCM_STATUS[2];
assign DCM_IN_STOPPED = DCM_STATUS[1];
my_dcm snes_dcm(.CLKIN(CLKIN),
.CLK2X(CLK),
.CLKFB(CLKFB),
.CLKFX(CLK2),
.CLK0(CLK0),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST)
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
assign DCM_RST = 1'b0;
/*always @(posedge CLKIN) begin
if(DCM_FX_STOPPED)
DCM_RST <= 1'b1;
else
DCM_RST <= 1'b0;
end
*/
/*reg DO_DCM_RESET, DCM_RESETTING;
reg DCM_RSTr;
assign DCM_RST = DCM_RSTr;
reg [2:0] DCM_RESET_CNT;
initial DO_DCM_RESET = 1'b0;
initial DCM_RESETTING = 1'b0;
always @(posedge CLKIN) begin
if(!DCM_LOCKED && !DCM_RESETTING) begin
DCM_RSTr <= 1'b1;
DO_DCM_RESET <= 1'b1;
DCM_RESET_CNT <= 3'b0;
end else if (DO_DCM_RESET) begin
DCM_RSTr <= 1'b0;
DCM_RESET_CNT <= DCM_RESET_CNT + 1;
end
end
always @(posedge CLKIN) begin
if (DO_DCM_RESET)
DCM_RESETTING <= 1'b1;
else if (DCM_RESET_CNT == 3'b110)
DCM_RESETTING <= 1'b0;
end
*/
wire SNES_RW;
reg [1:0] SNES_READr;
reg [1:0] SNES_WRITEr;

1
verilog/sd2snes/sd2snes.xise
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@ -101,6 +101,7 @@
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
</properties>