463 lines
12 KiB
Verilog
463 lines
12 KiB
Verilog
`timescale 1 ns / 1 ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Rehkopf
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// Engineer: Rehkopf
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//
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// Create Date: 01:13:46 05/09/2009
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// Design Name:
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// Module Name: main
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: Master Control FSM
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//
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// Dependencies: address
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module main(
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/* input clock */
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input CLKIN,
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/* SNES signals */
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input [23:0] SNES_ADDR,
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input SNES_READ,
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input SNES_WRITE,
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input SNES_CS,
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inout [7:0] SNES_DATA,
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input SNES_CPU_CLK,
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input SNES_REFRESH,
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inout SNES_IRQ,
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output SNES_DATABUS_OE,
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output SNES_DATABUS_DIR,
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output IRQ_DIR,
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/* SRAM signals */
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inout [15:0] SRAM_DATA,
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output [19:0] SRAM_ADDR,
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output [3:0] SRAM_CE2,
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output SRAM_OE,
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output SRAM_WE,
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output SRAM_BHE,
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output SRAM_BLE,
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/* AVR signals */
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input SPI_MOSI,
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output SPI_MISO,
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input SPI_SS,
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input SPI_SCK,
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input AVR_ENA,
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/* debug */
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output DCM_IN_STOPPED,
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output DCM_FX_STOPPED
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//input DCM_RST
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);
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wire [7:0] spi_cmd_data;
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wire [7:0] spi_param_data;
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wire [7:0] spi_input_data;
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wire [31:0] spi_byte_cnt;
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wire [2:0] spi_bit_cnt;
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wire [23:0] AVR_ADDR;
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wire [7:0] avr_data_in;
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wire [7:0] avr_data_out;
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wire [7:0] AVR_IN_DATA;
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wire [7:0] AVR_OUT_DATA;
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wire [3:0] MAPPER;
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wire [23:0] SAVERAM_MASK;
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wire [23:0] ROM_MASK;
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spi snes_spi(.clk(CLK2),
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.MOSI(SPI_MOSI),
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.MISO(SPI_MISO),
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.SSEL(SPI_SS),
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.SCK(SPI_SCK),
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.LED(SPI_LSB),
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.cmd_ready(spi_cmd_ready),
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.param_ready(spi_param_ready),
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.cmd_data(spi_cmd_data),
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.param_data(spi_param_data),
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.endmessage(spi_endmessage),
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.startmessage(spi_startmessage),
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.input_data(spi_input_data),
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.byte_cnt(spi_byte_cnt),
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.bit_cnt(spi_bit_cnt)
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);
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avr_cmd snes_avr_cmd(
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.clk(CLK2),
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.cmd_ready(spi_cmd_ready),
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.param_ready(spi_param_ready),
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.cmd_data(spi_cmd_data),
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.param_data(spi_param_data),
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.avr_mapper(MAPPER),
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.avr_sram_size(SRAM_SIZE),
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.avr_read(AVR_READ),
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.avr_write(AVR_WRITE),
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.avr_data_in(AVR_OUT_DATA),
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.avr_data_out(AVR_IN_DATA),
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.spi_byte_cnt(spi_byte_cnt),
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.spi_bit_cnt(spi_bit_cnt),
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.spi_data_out(spi_input_data),
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.addr_out(AVR_ADDR),
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.endmessage(spi_endmessage),
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.startmessage(spi_startmessage),
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.saveram_mask_out(SAVERAM_MASK),
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.rom_mask_out(ROM_MASK)
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);
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wire [7:0] DCM_STATUS;
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assign DCM_FX_STOPPED = DCM_STATUS[2];
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assign DCM_IN_STOPPED = DCM_STATUS[1];
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my_dcm snes_dcm(.CLKIN(CLKIN),
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.CLKFX(CLK2),
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.LOCKED(DCM_LOCKED),
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.RST(DCM_RST),
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.STATUS(DCM_STATUS)
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);
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assign DCM_RST = 1'b0;
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/*always @(posedge CLKIN) begin
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if(DCM_FX_STOPPED)
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DCM_RST <= 1'b1;
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else
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DCM_RST <= 1'b0;
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end
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*/
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/*reg DO_DCM_RESET, DCM_RESETTING;
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reg DCM_RSTr;
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assign DCM_RST = DCM_RSTr;
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reg [2:0] DCM_RESET_CNT;
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initial DO_DCM_RESET = 1'b0;
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initial DCM_RESETTING = 1'b0;
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always @(posedge CLKIN) begin
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if(!DCM_LOCKED && !DCM_RESETTING) begin
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DCM_RSTr <= 1'b1;
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DO_DCM_RESET <= 1'b1;
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DCM_RESET_CNT <= 3'b0;
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end else if (DO_DCM_RESET) begin
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DCM_RSTr <= 1'b0;
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DCM_RESET_CNT <= DCM_RESET_CNT + 1;
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end
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end
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always @(posedge CLKIN) begin
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if (DO_DCM_RESET)
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DCM_RESETTING <= 1'b1;
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else if (DCM_RESET_CNT == 3'b110)
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DCM_RESETTING <= 1'b0;
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end
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*/
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wire SNES_RW;
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reg [1:0] SNES_READr;
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reg [1:0] SNES_WRITEr;
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reg [1:0] SNES_CSr;
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reg [5:0] SNES_CPU_CLKr;
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reg [5:0] SNES_RWr;
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reg [23:0] SNES_ADDRr;
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reg [23:0] SNES_ADDR_PREVr;
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reg [3:0] SNES_ADDRCHGr;
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wire SNES_READs = (SNES_READr == 2'b11);
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wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
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wire SNES_CSs = (SNES_CSr == 2'b11);
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wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
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wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
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wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000001);
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wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr);
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wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
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assign SNES_RW = (SNES_READ & SNES_WRITE);
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always @(posedge CLK2) begin
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SNES_READr <= {SNES_READr[0], SNES_READ};
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SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
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SNES_CSr <= {SNES_CSr[0], SNES_CS};
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SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
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SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
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end
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reg ADDR_WRITE;
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//reg [23:0] SNES_ADDRr;
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//wire [23:0] SNES_ADDRw = SNES_ADDR;
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address snes_addr(
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.CLK(CLK2),
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.MAPPER(MAPPER),
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.SNES_ADDR(SNES_ADDR), // requested address from SNES
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.SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
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.SRAM_ADDR(SRAM_ADDR), // Address to request from SRAM (active low)
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.ROM_SEL(SRAM_CE2), // which SRAM unit to access
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.AVR_ENA(AVR_ENA), // enable AVR mode (active low)
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.MODE(MODE), // AVR(1) or SNES(0) ("bus phase")
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.IS_SAVERAM(IS_SAVERAM),
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.IS_ROM(IS_ROM),
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.AVR_ADDR(AVR_ADDR),
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.SRAM_ADDR0(SRAM_ADDR0),
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.SAVERAM_MASK(SAVERAM_MASK),
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.ROM_MASK(ROM_MASK)
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);
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wire SNES_READ_CYCLEw;
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wire SNES_WRITE_CYCLEw;
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wire AVR_READ_CYCLEw;
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wire AVR_WRITE_CYCLEw;
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data snes_data(.CLK(CLK2),
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.SNES_READ(SNES_READ),
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.SNES_WRITE(SNES_WRITE),
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.AVR_READ(AVR_READ),
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.AVR_WRITE(AVR_WRITE),
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.SNES_DATA(SNES_DATA),
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.SRAM_DATA(SRAM_DATA),
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.MODE(MODE),
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.SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
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.AVR_DATA_TO_MEM(AVR_DATA_TO_MEM),
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.SRAM_DATA_TO_SNES_MEM(SRAM_DATA_TO_SNES_MEM),
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.SRAM_DATA_TO_AVR_MEM(SRAM_DATA_TO_AVR_MEM),
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.AVR_ENA(AVR_ENA),
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.AVR_IN_DATA(AVR_IN_DATA),
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.AVR_OUT_DATA(AVR_OUT_DATA),
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.SRAM_ADDR0(SRAM_ADDR0)
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);
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parameter MODE_SNES = 1'b0;
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parameter MODE_AVR = 1'b1;
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parameter STATE_0 = 13'b0000000000001;
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parameter STATE_1 = 13'b0000000000010;
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parameter STATE_2 = 13'b0000000000100;
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parameter STATE_3 = 13'b0000000001000;
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parameter STATE_4 = 13'b0000000010000;
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parameter STATE_5 = 13'b0000000100000;
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parameter STATE_6 = 13'b0000001000000;
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parameter STATE_7 = 13'b0000010000000;
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parameter STATE_8 = 13'b0000100000000;
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parameter STATE_9 = 13'b0001000000000;
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parameter STATE_10 = 13'b0010000000000;
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parameter STATE_11 = 13'b0100000000000;
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parameter STATE_IDLE = 13'b1000000000000;
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reg [12:0] STATE;
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reg [3:0] STATEIDX;
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reg [1:0] CYCLE_RESET;
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reg SRAM_WE_MASK;
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reg SRAM_OE_MASK;
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reg [12:0] SRAM_WE_ARRAY [3:0];
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reg [12:0] SRAM_OE_ARRAY [3:0];
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reg [12:0] SNES_DATA_TO_MEM_ARRAY[1:0];
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reg [12:0] AVR_DATA_TO_MEM_ARRAY[1:0];
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reg [12:0] SRAM_DATA_TO_SNES_MEM_ARRAY[1:0];
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reg [12:0] SRAM_DATA_TO_AVR_MEM_ARRAY[1:0];
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reg [12:0] MODE_ARRAY;
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reg SNES_READ_CYCLE;
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reg SNES_WRITE_CYCLE;
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reg AVR_READ_CYCLE;
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reg AVR_WRITE_CYCLE;
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reg AVR_SPI_WRITEONCE;
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reg AVR_SPI_READONCE;
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reg AVR_SPI_WRITE;
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reg AVR_SPI_READ;
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reg AVR_SPI_ADDR_INCREMENT;
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reg [7:0] AVR_DATA_IN;
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reg [3:0] MAPPER_BUF;
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reg SNES_DATABUS_OE_BUF;
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reg SNES_DATABUS_DIR_BUF;
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assign MODE = !AVR_ENA ? MODE_AVR : MODE_ARRAY[STATEIDX];
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initial begin
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CYCLE_RESET = 2'b0;
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STATE = STATE_IDLE;
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STATEIDX = 12;
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SRAM_WE_MASK = 1'b1;
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SRAM_OE_MASK = 1'b1;
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SNES_READ_CYCLE = 1'b1;
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SNES_WRITE_CYCLE = 1'b1;
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AVR_READ_CYCLE = 1'b1;
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AVR_WRITE_CYCLE = 1'b1;
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MODE_ARRAY = 13'b0000000111111;
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SRAM_WE_ARRAY[2'b00] = 13'b1000000000000;
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SRAM_WE_ARRAY[2'b01] = 13'b1000000111111;
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SRAM_WE_ARRAY[2'b10] = 13'b1111111000000;
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SRAM_WE_ARRAY[2'b11] = 13'b1111111111111;
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SRAM_OE_ARRAY[2'b00] = 13'b1111111111111;
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SRAM_OE_ARRAY[2'b01] = 13'b1111111000000;
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SRAM_OE_ARRAY[2'b10] = 13'b0000000111111;
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SRAM_OE_ARRAY[2'b11] = 13'b0000000000000;
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SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0001000000000; // SNES write
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SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0000000000000; // SNES read
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AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000010000; // AVR write
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AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0000000000000; // AVR read
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SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0000000000000; // SNES write
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SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0000100000000; // SNES read
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SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 13'b0000000000000; // AVR write
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SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0000000000001; // AVR read
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end
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// falling edge of SNES /RD or /WR marks the beginning of a new cycle
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// SNES READ or WRITE always starts @posedge CLK !!
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// CPU cycle can be 6, 8 or 12 CLKIN cycles so we must satisfy
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// the minimum of 6 SNES cycles to get everything done.
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// we have 24 internal cycles to work with. (CLKIN * 4)
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always @(posedge CLK2) begin
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CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start};
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end
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always @(posedge CLK2) begin
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if (SNES_RW_start) begin
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SNES_READ_CYCLE <= SNES_READ;
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SNES_WRITE_CYCLE <= SNES_WRITE;
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AVR_READ_CYCLE <= AVR_READ;
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AVR_WRITE_CYCLE <= AVR_WRITE;
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STATE <= STATE_0;
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STATEIDX <= 11;
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end else begin
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case (STATE)
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STATE_0: begin
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STATE <= STATE_1; STATEIDX <= 10;
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end
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STATE_1: begin
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STATE <= STATE_2; STATEIDX <= 9;
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end
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STATE_2: begin
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STATE <= STATE_3; STATEIDX <= 8;
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end
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STATE_3: begin
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STATE <= STATE_4; STATEIDX <= 7;
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end
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STATE_4: begin
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STATE <= STATE_5; STATEIDX <= 6;
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end
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STATE_5: begin
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STATE <= STATE_6; STATEIDX <= 5;
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end
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STATE_6: begin
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STATE <= STATE_7; STATEIDX <= 4;
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end
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STATE_7: begin
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STATE <= STATE_8; STATEIDX <= 3;
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end
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STATE_8: begin
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STATE <= STATE_9; STATEIDX <= 2;
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end
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STATE_9: begin
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STATE <= STATE_10; STATEIDX <= 1;
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end
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STATE_10: begin
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STATE <= STATE_11; STATEIDX <= 0;
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end
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STATE_11: begin
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STATE <= STATE_IDLE; STATEIDX <= 12;
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end
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STATE_IDLE: begin
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STATE <= STATE_IDLE; STATEIDX <= 12;
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end
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default: begin
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STATE <= STATE_IDLE; STATEIDX <= 12;
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end
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endcase
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end
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end
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/*
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always @(posedge CLK2) begin
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case (STATE)
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STATE_9: begin
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STATEIDX <= 9;
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end
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STATE_0: begin
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STATEIDX <= 8;
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end
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STATE_1: begin
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STATEIDX <= 7;
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end
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STATE_2: begin
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STATEIDX <= 6;
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end
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STATE_3: begin
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STATEIDX <= 5;
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end
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STATE_4: begin
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STATEIDX <= 4;
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end
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STATE_5: begin
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STATEIDX <= 3;
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end
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STATE_6: begin
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STATEIDX <= 2;
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end
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STATE_7: begin
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STATEIDX <= 1;
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end
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STATE_8: begin
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STATEIDX <= 0;
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end
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default:
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STATEIDX <= 9;
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endcase
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end
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*/
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// When in AVR mode, enable SRAM_WE according to AVR programming
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// else enable SRAM_WE according to state&cycle
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assign SRAM_WE = !AVR_ENA ? AVR_WRITE
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: ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]);
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// When in AVR mode, enable SRAM_OE whenever not writing
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// else enable SRAM_OE according to state&cycle
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assign SRAM_OE = !AVR_ENA ? AVR_READ
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: SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX];
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assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
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assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0;
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// dumb version
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//assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs;
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//assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1;
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//assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
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assign SNES_DATABUS_OE = (IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM) | (SNES_READ & SNES_WRITE);
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assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
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assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
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assign AVR_DATA_TO_MEM = AVR_DATA_TO_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
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assign SRAM_DATA_TO_SNES_MEM = SRAM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
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assign SRAM_DATA_TO_AVR_MEM = SRAM_DATA_TO_AVR_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
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assign SNES_READ_CYCLEw = SNES_READ_CYCLE;
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assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE;
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assign IRQ_DIR = 1'b0;
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assign SNES_IRQ = 1'bZ;
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endmodule
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