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FPGA/BSX: fix checksum registers

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This commit is contained in:
Maximilian Rehkopf 2012-07-09 02:00:29 +02:00
parent 3af05cef91
commit 684e2c3b81
2 changed files with 15 additions and 14 deletions
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19
verilog/sd2snes/bsx.v
View File

@ -182,24 +182,25 @@ end
always @(posedge clkin) begin
if(reg_oe_rising) begin
if(base_enable) begin
if(reg_oe_rising && base_enable) begin
case(base_addr)
5'h0b: bs_stb0_offset <= bs_stb0_offset + 1;
5'h0b: begin
bs_stb0_offset <= bs_stb0_offset + 1;
base_regs[5'h0d] <= base_regs[5'h0d] | reg_data_in;
end
5'h0c: bs_page0_offset <= bs_page0_offset + 1;
5'h11: bs_stb1_offset <= bs_stb1_offset + 1;
5'h11: begin
bs_stb1_offset <= bs_stb1_offset + 1;
base_regs[5'h13] <= base_regs[5'h13] | reg_data_in;
end
5'h12: bs_page1_offset <= bs_page1_offset + 1;
endcase
end
end
end else
if(reg_oe_falling) begin
if(cart_enable)
reg_data_outr <= {regs_outr[reg_addr], 7'b0};
else if(base_enable) begin
case(base_addr)
5'h0b, 5'h11: begin
base_regs[base_addr+5'h02] <= base_regs[base_addr+5'h02] | reg_data_in;
end
5'h0c, 5'h12: begin
case (bs_page1_offset)
4: reg_data_outr <= 8'h3;

2
verilog/sd2snes/main.v
View File

@ -463,7 +463,7 @@ reg [7:0] ROM_DOUTr;
assign DSPX_SNES_DATA_IN = SNES_DATA;
assign SRTC_SNES_DATA_IN = SNES_DATA[3:0];
assign MSU_SNES_DATA_IN = SNES_DATA;
assign BSX_SNES_DATA_IN = bs_page_enable ? SNES_DINr : SNES_DATA;
assign BSX_SNES_DATA_IN = SNES_DATA;
reg [7:0] r213fr;
reg r213f_forceread;