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firmware, FPGA: fix for some SD cards

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ikari 2011-11-10 17:54:52 +01:00
parent 3fda86125c
commit 68f255d75b
3 changed files with 9 additions and 6 deletions
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3
src/sdnative.c
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@ -867,6 +867,9 @@ DRESULT sdn_initialize(BYTE drv) {
if(rsp[1]&0x80) break;
}
BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0;
BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1;
ccs = (rsp[1]>>6) & 1; /* SDHC/XC */
cmd_slow(ALL_SEND_CID, 0, 0x4d, NULL, rsp);

6
verilog/sd2snes/sd_dma.v
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@ -71,9 +71,9 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
// we have 4 internal cycles per SD clock, 8 per RAM byte write
reg [2:0] clkcnt;
initial clkcnt = 3'b000;
reg SD_CLKr;
always @(posedge CLK) SD_CLKr <= clkcnt[1];
assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ;
reg [1:0] SD_CLKr;
always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin

6
verilog/sd2snes_cx4/sd_dma.v
View File

@ -71,9 +71,9 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
// we have 4 internal cycles per SD clock, 8 per RAM byte write
reg [2:0] clkcnt;
initial clkcnt = 3'b000;
reg SD_CLKr;
always @(posedge CLK) SD_CLKr <= clkcnt[1];
assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ;
reg [1:0] SD_CLKr;
always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin