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FPGA/Cx4: fully operational except reset vector area

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This commit is contained in:
ikari 2011-10-30 01:53:56 +02:00
parent 8c76dfbeb6
commit 7643790fed
6 changed files with 1535 additions and 1993 deletions
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184
verilog/sd2snes_cx4/cx4.v
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@ -42,12 +42,11 @@ parameter BUSY_DMA = 2'b01;
parameter BUSY_CPU = 2'b10; parameter BUSY_CPU = 2'b10;
wire datram_enable = CS & (ADDR[11:0] < 12'hc00); wire datram_enable = CS & (ADDR[11:0] < 12'hc00);
wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11001); wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] < 5'b10011);
wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11001); wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] >= 5'b10011);
wire vector_enable = CS & (ADDR[12:5] == 8'b11111011); wire vector_enable = CS & (ADDR[12:5] == 8'b11111011);
wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11); wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11);
wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000); wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000);
wire debug_enable = CS & (&(ADDR[12:7]) && &(ADDR[5:4]));
wire [7:0] DATRAM_DO; wire [7:0] DATRAM_DO;
reg [7:0] MMIO_DOr; reg [7:0] MMIO_DOr;
@ -55,15 +54,12 @@ wire [7:0] MMIO_DO;
wire [7:0] STATUS_DO; wire [7:0] STATUS_DO;
wire [7:0] VECTOR_DO; wire [7:0] VECTOR_DO;
wire [7:0] GPR_DO; wire [7:0] GPR_DO;
wire [7:0] DEBUG_DO;
reg [7:0] DEBUG_DOr;
assign DO = datram_enable ? DATRAM_DO assign DO = datram_enable ? DATRAM_DO
: mmio_enable ? MMIO_DO : mmio_enable ? MMIO_DO
: status_enable ? STATUS_DO : status_enable ? STATUS_DO
: vector_enable ? VECTOR_DO : vector_enable ? VECTOR_DO
: gpr_enable ? GPR_DO : gpr_enable ? GPR_DO
: debug_enable ? DEBUG_DO
: 8'h00; : 8'h00;
/* 0x1f40 - 0x1f52: MMIO /* 0x1f40 - 0x1f52: MMIO
@ -73,7 +69,7 @@ reg [15:0] cx4_mmio_dmalen;
reg [23:0] cx4_mmio_dmatgt; reg [23:0] cx4_mmio_dmatgt;
reg cx4_mmio_cachepage; reg cx4_mmio_cachepage;
reg [23:0] cx4_mmio_pgmoff; reg [23:0] cx4_mmio_pgmoff;
reg [1:0] cx4_mmio_r1f4c; reg [1:0] cx4_mmio_savepage;
reg [14:0] cx4_mmio_pgmpage; reg [14:0] cx4_mmio_pgmpage;
reg [7:0] cx4_mmio_pc; reg [7:0] cx4_mmio_pc;
reg [7:0] cx4_mmio_r1f50; reg [7:0] cx4_mmio_r1f50;
@ -88,9 +84,13 @@ reg [7:0] vector [31:0];
reg [7:0] gpr [47:0]; reg [7:0] gpr [47:0];
wire [47:0] cpu_mul_result; wire [47:0] cpu_mul_result;
reg [14:0] cx4_mmio_pagemem[1:0];
reg [23:0] const [15:0]; reg [23:0] const [15:0];
reg [15:0] cachetag [1:0]; // 15: valid; 14-0: bank number reg [14:0] cachetag [1:0]; // 14-0: bank number
reg [1:0] cachevalid;
reg [14:0] cache_pgmpage; reg [14:0] cache_pgmpage;
reg [14:0] cpu_cache_pgmpage; reg [14:0] cpu_cache_pgmpage;
reg cache_cachepage; reg cache_cachepage;
@ -105,14 +105,16 @@ initial begin
cache_cachepage = 1'b0; cache_cachepage = 1'b0;
cpu_cache_cachepage = 1'b0; cpu_cache_cachepage = 1'b0;
cpu_cache_done = 1'b0; cpu_cache_done = 1'b0;
cachetag[0] = 16'h0000; cachetag[0] = 14'h0000;
cachetag[1] = 16'h0000; cachetag[1] = 14'h0000;
cachevalid = 2'b00;
cx4_busy = 3'b000; cx4_busy = 3'b000;
cx4_mmio_pgmoff = 24'h000000; cx4_mmio_pgmoff = 24'h000000;
cx4_mmio_pgmpage = 15'h0000; cx4_mmio_pgmpage = 15'h0000;
cx4_mmio_dmasrc = 24'h000000; cx4_mmio_dmasrc = 24'h000000;
cx4_mmio_dmalen = 16'h0000; cx4_mmio_dmalen = 16'h0000;
cx4_mmio_dmatgt = 24'h000000; cx4_mmio_dmatgt = 24'h000000;
cx4_mmio_savepage = 2'b00;
const[0] = 24'h000000; const[0] = 24'h000000;
const[1] = 24'hffffff; const[1] = 24'hffffff;
const[2] = 24'h00ff00; const[2] = 24'h00ff00;
@ -144,7 +146,6 @@ assign MMIO_DO = MMIO_DOr;
assign VECTOR_DO = vector [ADDR[4:0]]; assign VECTOR_DO = vector [ADDR[4:0]];
assign GPR_DO = gpr [ADDR[5:0]]; assign GPR_DO = gpr [ADDR[5:0]];
assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0}; assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0};
assign DEBUG_DO = DEBUG_DOr;
reg [7:0] DIr; reg [7:0] DIr;
always @(posedge CLK) DIr <= DI; always @(posedge CLK) DIr <= DI;
@ -198,6 +199,11 @@ assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr | cpu_bus_rq;
reg cpu_page; reg cpu_page;
reg [14:0] cpu_p; reg [14:0] cpu_p;
reg [7:0] cpu_pc; reg [7:0] cpu_pc;
reg [23:0] cpu_a;
reg fl_n;
reg fl_z;
reg fl_c;
reg cpu_go_en_r; reg cpu_go_en_r;
initial cpu_go_en_r = 1'b0; initial cpu_go_en_r = 1'b0;
@ -222,7 +228,7 @@ always @(posedge CLK) begin
5'h09: MMIO_DOr <= cx4_mmio_pgmoff[7:0]; // 1f49 5'h09: MMIO_DOr <= cx4_mmio_pgmoff[7:0]; // 1f49
5'h0a: MMIO_DOr <= cx4_mmio_pgmoff[15:8]; // 1f4a 5'h0a: MMIO_DOr <= cx4_mmio_pgmoff[15:8]; // 1f4a
5'h0b: MMIO_DOr <= cx4_mmio_pgmoff[23:16]; // 1f4b 5'h0b: MMIO_DOr <= cx4_mmio_pgmoff[23:16]; // 1f4b
5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_r1f4c}; // 1f4c 5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_savepage}; // 1f4c
5'h0d: MMIO_DOr <= cx4_mmio_pgmpage[7:0]; // 1f4d 5'h0d: MMIO_DOr <= cx4_mmio_pgmpage[7:0]; // 1f4d
5'h0e: MMIO_DOr <= {1'b0, cx4_mmio_pgmpage[14:8]}; // 1f4e 5'h0e: MMIO_DOr <= {1'b0, cx4_mmio_pgmpage[14:8]}; // 1f4e
5'h0f: MMIO_DOr <= cx4_mmio_pc; // 1f4f 5'h0f: MMIO_DOr <= cx4_mmio_pc; // 1f4f
@ -233,58 +239,47 @@ always @(posedge CLK) begin
endcase endcase
end end
always @(posedge CLK) begin
case(ADDR[3:0])
4'h0: DEBUG_DOr <= cachetag[0][15:8]; // 1f40
4'h1: DEBUG_DOr <= cachetag[0][7:0]; // 1f41
4'h2: DEBUG_DOr <= cachetag[1][15:8]; // 1f42
4'h3: DEBUG_DOr <= cachetag[1][7:0]; // 1f43
4'h4: DEBUG_DOr <= cpu_page;
4'h5: DEBUG_DOr <= cpu_p;
4'h6: DEBUG_DOr <= cpu_pc;
4'h7: DEBUG_DOr <= cx4_busy;
4'h8: DEBUG_DOr <= cpu_page_stack[0];
4'h9: DEBUG_DOr <= cpu_pc_stack[0];
4'ha: DEBUG_DOr <= cpu_page_stack[1];
4'hb: DEBUG_DOr <= cpu_pc_stack[1];
4'hc: DEBUG_DOr <= cpu_page_stack[2];
4'hd: DEBUG_DOr <= cpu_pc_stack[2];
4'he: DEBUG_DOr <= cpu_page_stack[3];
4'hf: DEBUG_DOr <= cpu_pc_stack[3];
endcase
end
always @(posedge CLK) begin always @(posedge CLK) begin
if(MMIO_WR_EN) begin if(MMIO_WR_EN) begin
case(ADDR[4:0]) case(ADDR[4:0])
5'h00: cx4_mmio_dmasrc[7:0] <= DI; // 1f40 5'h00: cx4_mmio_dmasrc[7:0] <= DIr; // 1f40
5'h01: cx4_mmio_dmasrc[15:8] <= DI; // 1f41 5'h01: cx4_mmio_dmasrc[15:8] <= DIr; // 1f41
5'h02: cx4_mmio_dmasrc[23:16] <= DI; // 1f42 5'h02: cx4_mmio_dmasrc[23:16] <= DIr; // 1f42
5'h03: cx4_mmio_dmalen[7:0] <= DI; // 1f43 5'h03: cx4_mmio_dmalen[7:0] <= DIr; // 1f43
5'h04: cx4_mmio_dmalen[15:8] <= DI; // 1f44 5'h04: cx4_mmio_dmalen[15:8] <= DIr; // 1f44
5'h05: cx4_mmio_dmatgt[7:0] <= DI; // 1f45 5'h05: cx4_mmio_dmatgt[7:0] <= DIr; // 1f45
5'h06: cx4_mmio_dmatgt[15:8] <= DI; // 1f46 5'h06: cx4_mmio_dmatgt[15:8] <= DIr; // 1f46
5'h07: begin 5'h07: begin
cx4_mmio_dmatgt[23:16] <= DI; // 1f47 cx4_mmio_dmatgt[23:16] <= DIr; // 1f47
DMA_TRIG_ENr <= 1'b1; DMA_TRIG_ENr <= 1'b1;
end end
5'h08: begin 5'h08: begin
cx4_mmio_cachepage <= DI[0]; // 1f48 cx4_mmio_cachepage <= DIr[0]; // 1f48
CACHE_TRIG_ENr <= 1'b1; CACHE_TRIG_ENr <= 1'b1;
end end
5'h09: cx4_mmio_pgmoff[7:0] <= DI; // 1f49 5'h09: cx4_mmio_pgmoff[7:0] <= DIr; // 1f49
5'h0a: cx4_mmio_pgmoff[15:8] <= DI; // 1f4a 5'h0a: cx4_mmio_pgmoff[15:8] <= DIr; // 1f4a
5'h0b: cx4_mmio_pgmoff[23:16] <= DI; // 1f4b 5'h0b: cx4_mmio_pgmoff[23:16] <= DIr; // 1f4b
5'h0c: cx4_mmio_r1f4c <= DI[1:0]; // 1f4c 5'h0c: begin
5'h0d: cx4_mmio_pgmpage[7:0] <= DI; // 1f4d cx4_mmio_savepage <= DIr[1:0];
5'h0e: cx4_mmio_pgmpage[14:8] <= DI[6:0]; // 1f4e if(DIr[0]) cx4_mmio_pagemem[0] <= cx4_mmio_pgmpage;
if(DIr[1]) cx4_mmio_pagemem[1] <= cx4_mmio_pgmpage;
end
5'h0d: cx4_mmio_pgmpage[7:0] <= DIr; // 1f4d
5'h0e: cx4_mmio_pgmpage[14:8] <= DIr[6:0]; // 1f4e
5'h0f: begin 5'h0f: begin
cx4_mmio_pc <= DI; // 1f4f cx4_mmio_pc <= DIr; // 1f4f
if(cx4_mmio_savepage[0]
&& cx4_mmio_pagemem[0] == cx4_mmio_pgmpage)
cx4_mmio_cachepage <= 1'b0;
else if(cx4_mmio_savepage[1]
&& cx4_mmio_pagemem[1] == cx4_mmio_pgmpage)
cx4_mmio_cachepage <= 1'b1;
cpu_go_en_r <= 1'b1; cpu_go_en_r <= 1'b1;
end end
5'h10: cx4_mmio_r1f50 <= DI & 8'h77; // 1f50 5'h10: cx4_mmio_r1f50 <= DIr & 8'h77; // 1f50
5'h11: cx4_mmio_r1f51 <= DI[0]; // 1f51 5'h11: cx4_mmio_r1f51 <= DIr[0]; // 1f51
5'h12: cx4_mmio_r1f52 <= DI[0]; // 1f52 5'h12: cx4_mmio_r1f52 <= DIr[0]; // 1f52
endcase endcase
end else begin end else begin
CACHE_TRIG_ENr <= 1'b0; CACHE_TRIG_ENr <= 1'b0;
@ -294,7 +289,7 @@ always @(posedge CLK) begin
end end
always @(posedge CLK) begin always @(posedge CLK) begin
if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DI; if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DIr;
end end
reg [4:0] CACHE_ST; reg [4:0] CACHE_ST;
@ -333,14 +328,14 @@ always @(posedge CLK) begin
case(CACHE_ST) case(CACHE_ST)
ST_CACHE_IDLE: begin ST_CACHE_IDLE: begin
if(CACHE_TRIG_EN if(CACHE_TRIG_EN
& (~cachetag[cx4_mmio_cachepage][15] & (~cachevalid[cx4_mmio_cachepage]
| |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) begin | |(cachetag[cx4_mmio_cachepage] ^ cx4_mmio_pgmpage))) begin
CACHE_ST <= ST_CACHE_START; CACHE_ST <= ST_CACHE_START;
cache_pgmpage <= cx4_mmio_pgmpage; cache_pgmpage <= cx4_mmio_pgmpage;
cache_cachepage <= cx4_mmio_cachepage; cache_cachepage <= cx4_mmio_cachepage;
end else if(cpu_cache_en end else if(cpu_cache_en
& (~cachetag[~cpu_page][15] & (~cachevalid[~cpu_page]
| |(cachetag[~cpu_page][14:0] ^ cpu_p))) begin | |(cachetag[~cpu_page] ^ cpu_p))) begin
CACHE_ST <= ST_CACHE_START; CACHE_ST <= ST_CACHE_START;
cache_pgmpage <= cpu_p; cache_pgmpage <= cpu_p;
cache_cachepage <= ~cpu_page; cache_cachepage <= ~cpu_page;
@ -370,7 +365,8 @@ always @(posedge CLK) begin
cx4_pgmrom_addr <= cx4_pgmrom_addr + 1; cx4_pgmrom_addr <= cx4_pgmrom_addr + 1;
if(cache_count == 9'h1ff) begin if(cache_count == 9'h1ff) begin
cx4_busy[BUSY_CACHE] <= 1'b0; cx4_busy[BUSY_CACHE] <= 1'b0;
cachetag[cache_cachepage] <= {1'b1,cache_pgmpage}; cachetag[cache_cachepage] <= cache_pgmpage;
cachevalid[cache_cachepage] <= 1'b1;
CACHE_ST <= ST_CACHE_IDLE; CACHE_ST <= ST_CACHE_IDLE;
end else begin end else begin
CACHE_BUS_RRQr <= 1'b1; CACHE_BUS_RRQr <= 1'b1;
@ -439,7 +435,6 @@ reg [2:0] cpu_sp;
initial cpu_sp = 3'b000; initial cpu_sp = 3'b000;
wire [15:0] cpu_op_w; wire [15:0] cpu_op_w;
reg [15:0] cpu_op; reg [15:0] cpu_op;
reg [23:0] cpu_a;
reg [23:0] cpu_busdata; reg [23:0] cpu_busdata;
reg [23:0] cpu_romdata; reg [23:0] cpu_romdata;
reg [23:0] cpu_ramdata; reg [23:0] cpu_ramdata;
@ -455,9 +450,6 @@ reg [23:0] cpu_dummy;
reg [23:0] cpu_tmp; reg [23:0] cpu_tmp;
reg [23:0] cpu_sa; // tmp register for shifted accumulator reg [23:0] cpu_sa; // tmp register for shifted accumulator
reg fl_n;
reg fl_z;
reg fl_c;
wire [9:0] cx4_datrom_addr = cpu_a[9:0]; wire [9:0] cx4_datrom_addr = cpu_a[9:0];
wire [23:0] cx4_datrom_do; wire [23:0] cx4_datrom_do;
@ -499,19 +491,24 @@ reg op_call;
reg op_jump; reg op_jump;
reg condtrue; reg condtrue;
/* XXX DEBUG */
reg [23:0] dbg_cnt;
initial dbg_cnt = 24'b0;
always @(posedge CLK) dbg_cnt <= dbg_cnt + 1;
wire step_enable = 1'b1;
always @(posedge CLK) begin always @(posedge CLK) begin
if(cpu_go_en_r) cx4_busy[BUSY_CPU] <= 1'b1; if(cpu_go_en_r) cx4_busy[BUSY_CPU] <= 1'b1;
else if((op == OP_HLT) && step_enable) cx4_busy[BUSY_CPU] <= 1'b0; else if(op == OP_HLT) cx4_busy[BUSY_CPU] <= 1'b0;
end end
always @(posedge CLK) begin always @(posedge CLK) begin
if(step_enable | cpu_go_en_r) begin case(op_sa)
2'b00: cpu_sa <= cpu_a;
2'b01: cpu_sa <= cpu_a << 1;
2'b10: cpu_sa <= cpu_a << 8;
2'b11: cpu_sa <= cpu_a << 16;
endcase
end
reg jp_docache;
initial jp_docache = 1'b0;
always @(posedge CLK) begin
case(CPU_STATE) case(CPU_STATE)
ST_CPU_IDLE: begin ST_CPU_IDLE: begin
if(cpu_go_en_r) begin if(cpu_go_en_r) begin
@ -537,6 +534,10 @@ if(step_enable | cpu_go_en_r) begin
2'b00: condtrue <= fl_c; 2'b00: condtrue <= fl_c;
2'b01: condtrue <= fl_n; 2'b01: condtrue <= fl_n;
endcase endcase
if(op_p && !jp_docache) begin
jp_docache <= 1'b1;
cpu_cache_en <= 1'b1;
end
end end
OP_SKIP: begin OP_SKIP: begin
case(cpu_op[9:8]) case(cpu_op[9:8])
@ -562,14 +563,6 @@ if(step_enable | cpu_go_en_r) begin
gpr[op_param[3:0]*3]}; gpr[op_param[3:0]*3]};
default: cpu_idb <= 24'b0; default: cpu_idb <= 24'b0;
endcase endcase
if(op==OP_ALU || op==OP_CMP) begin
case(op_sa)
2'b00: cpu_sa <= cpu_a;
2'b01: cpu_sa <= cpu_a << 1;
2'b10: cpu_sa <= cpu_a << 8;
2'b11: cpu_sa <= cpu_a << 16;
endcase
end
end end
OP_ST: begin OP_ST: begin
cpu_idb <= cpu_a; cpu_idb <= cpu_a;
@ -615,9 +608,12 @@ if(step_enable | cpu_go_en_r) begin
end end
ST_CPU_1: begin ST_CPU_1: begin
CPU_STATE <= ST_CPU_2; CPU_STATE <= ST_CPU_2;
condtrue <= 1'b0;
case(op) case(op)
OP_JP: begin OP_JP: begin
if(!cx4_busy[BUSY_CACHE]) begin cpu_cache_en <= 1'b0;
if(!cpu_cache_en && !cx4_busy[BUSY_CACHE]) begin
jp_docache <= 1'b0;
if(condtrue) begin if(condtrue) begin
if(op_call) begin if(op_call) begin
cpu_page_stack[cpu_sp] <= cpu_page; cpu_page_stack[cpu_sp] <= cpu_page;
@ -659,10 +655,8 @@ if(step_enable | cpu_go_en_r) begin
end end
OP_ST, OP_SWP: begin OP_ST, OP_SWP: begin
casex(op_param) casex(op_param)
// 8'h00: cpu_a <= cpu_idb;
8'h01: cpu_acch <= cpu_idb; 8'h01: cpu_acch <= cpu_idb;
8'h02: cpu_accl <= cpu_idb; 8'h02: cpu_accl <= cpu_idb;
// 8'h03: cpu_busdata <= cpu_idb;
8'h08: cpu_romdata <= cpu_idb; 8'h08: cpu_romdata <= cpu_idb;
8'h0c: cpu_ramdata <= cpu_idb; 8'h0c: cpu_ramdata <= cpu_idb;
8'h13: cpu_busaddr <= cpu_idb; 8'h13: cpu_busaddr <= cpu_idb;
@ -707,8 +701,8 @@ if(step_enable | cpu_go_en_r) begin
5'b10110: cpu_alu_res <= cpu_sa & cpu_idb; 5'b10110: cpu_alu_res <= cpu_sa & cpu_idb;
5'b10111: cpu_alu_res <= cpu_sa | cpu_idb; 5'b10111: cpu_alu_res <= cpu_sa | cpu_idb;
5'b11000: cpu_alu_res <= cpu_a >> cpu_idb; 5'b11000: cpu_alu_res <= cpu_a >> cpu_idb;
5'b11001: cpu_alu_res <= $signed(cpu_a) >>> cpu_idb; 5'b11001: cpu_alu_res <= ($signed(cpu_a)) >>> cpu_idb;
5'b11010: {cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb; 5'b11010: {cpu_dummy, cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb;
5'b11011: cpu_alu_res <= cpu_a << cpu_idb; 5'b11011: cpu_alu_res <= cpu_a << cpu_idb;
endcase endcase
end end
@ -717,12 +711,6 @@ if(step_enable | cpu_go_en_r) begin
ST_CPU_3: begin ST_CPU_3: begin
CPU_STATE <= ST_CPU_0; CPU_STATE <= ST_CPU_0;
case(op) case(op)
OP_LD: begin
casex(cpu_op[11:8])
4'b0x11: cpu_cache_en <= 1'b1;
4'b1100: cpu_cache_en <= 1'b1;
endcase
end
OP_BUS: cpu_busaddr <= cpu_busaddr + 1; OP_BUS: cpu_busaddr <= cpu_busaddr + 1;
OP_WRRAM: cx4_cpu_datram_we <= 1'b0; OP_WRRAM: cx4_cpu_datram_we <= 1'b0;
OP_CMP: begin OP_CMP: begin
@ -803,12 +791,14 @@ if(step_enable | cpu_go_en_r) begin
end end
endcase endcase
end end
end
reg[2:0] BUSRD_STATE; reg[2:0] BUSRD_STATE;
parameter ST_BUSRD_IDLE = 2'b01; parameter ST_BUSRD_IDLE = 3'b001;
parameter ST_BUSRD_WAIT = 2'b10; parameter ST_BUSRD_WAIT = 3'b010;
parameter ST_BUSRD_END = 3'b100;
initial BUSRD_STATE = ST_BUSRD_IDLE; initial BUSRD_STATE = ST_BUSRD_IDLE;
reg cpu_bus_rq2;
always @(posedge CLK) cpu_bus_rq2 <= cpu_bus_rq;
always @(posedge CLK) begin always @(posedge CLK) begin
if(CPU_STATE == ST_CPU_2 if(CPU_STATE == ST_CPU_2
@ -818,13 +808,15 @@ always @(posedge CLK) begin
else begin else begin
case(BUSRD_STATE) case(BUSRD_STATE)
ST_BUSRD_IDLE: begin ST_BUSRD_IDLE: begin
if(cpu_bus_rq) begin if(cpu_bus_rq2) begin
BUSRD_STATE <= ST_BUSRD_WAIT; BUSRD_STATE <= ST_BUSRD_WAIT;
end end
end end
ST_BUSRD_WAIT: begin ST_BUSRD_WAIT: begin
if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_IDLE; if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_END;
else BUSRD_STATE <= ST_BUSRD_WAIT; else BUSRD_STATE <= ST_BUSRD_WAIT;
end
ST_BUSRD_END: begin
if(~cpu_busaddr[22]) cpu_busdata <= BUS_DI; if(~cpu_busaddr[22]) cpu_busdata <= BUS_DI;
else cpu_busdata <= 8'h00; else cpu_busdata <= 8'h00;
end end
@ -841,7 +833,7 @@ always @(posedge CLK) begin
gpr[op_param[3:0]*3+1] <= cpu_idb[15:8]; gpr[op_param[3:0]*3+1] <= cpu_idb[15:8];
gpr[op_param[3:0]*3] <= cpu_idb[7:0]; gpr[op_param[3:0]*3] <= cpu_idb[7:0];
end end
else if(GPR_WR_EN) gpr[ADDR[5:0]] <= DI; else if(GPR_WR_EN) gpr[ADDR[5:0]] <= DIr;
end end
/*************************** /***************************
@ -861,7 +853,7 @@ cx4_datram cx4_datram (
.clka(CLK), // input clka .clka(CLK), // input clka
.wea(DATRAM_WR_EN), // input [0 : 0] wea .wea(DATRAM_WR_EN), // input [0 : 0] wea
.addra(ADDR[11:0]), // input [11 : 0] addra .addra(ADDR[11:0]), // input [11 : 0] addra
.dina(DI), // input [7 : 0] dina .dina(DIr), // input [7 : 0] dina
.douta(DATRAM_DO), // output [7 : 0] douta .douta(DATRAM_DO), // output [7 : 0] douta
.clkb(CLK), // input clkb .clkb(CLK), // input clkb
.web(cx4_datram_we), // input [0 : 0] web .web(cx4_datram_we), // input [0 : 0] web

3058
verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v
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File diff suppressed because it is too large Load Diff

6
verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco
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@ -1,7 +1,7 @@
############################################################## ##############################################################
# #
# Xilinx Core Generator version 13.2 # Xilinx Core Generator version 13.2
# Date: Mon Oct 24 22:04:01 2011 # Date: Fri Oct 28 08:30:26 2011
# #
############################################################## ##############################################################
# #
@ -49,7 +49,7 @@ CSET multtype=Parallel_Multiplier
CSET optgoal=Speed CSET optgoal=Speed
CSET outputwidthhigh=47 CSET outputwidthhigh=47
CSET outputwidthlow=0 CSET outputwidthlow=0
CSET pipestages=3 CSET pipestages=2
CSET portatype=Signed CSET portatype=Signed
CSET portawidth=24 CSET portawidth=24
CSET portbtype=Signed CSET portbtype=Signed
@ -65,4 +65,4 @@ CSET zerodetect=false
MISC pkg_timestamp=2011-06-21T06:26:54.000Z MISC pkg_timestamp=2011-06-21T06:26:54.000Z
# END Extra information # END Extra information
GENERATE GENERATE
# CRC: fd22ef14 # CRC: efe4d30e

4
verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise
View File

@ -50,8 +50,8 @@
<!-- --> <!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_mul" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_mul" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-25T00:04:25" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-28T10:30:58" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="384E11781B113D7487AFCF863F4DA087" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5048768FEE0CA0B8A63A1C80E928CC84" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties> </properties>

24
verilog/sd2snes_cx4/main.v
View File

@ -299,7 +299,8 @@ cx4 snes_cx4 (
.BUS_DI(CX4_DINr), .BUS_DI(CX4_DINr),
.BUS_ADDR(CX4_ADDR), .BUS_ADDR(CX4_ADDR),
.BUS_RRQ(CX4_RRQ), .BUS_RRQ(CX4_RRQ),
.BUS_RDY(CX4_RDY) .BUS_RDY(CX4_RDY),
.cx4_active(cx4_active)
); );
parameter MODE_SNES = 1'b0; parameter MODE_SNES = 1'b0;
@ -359,7 +360,7 @@ always @(posedge CLK2) begin
end end
wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE; wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE;
wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART; wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART & ~cx4_active;
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1]; assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0]; assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
@ -393,7 +394,7 @@ always @(posedge CLK2) begin
if(CX4_RRQ) begin if(CX4_RRQ) begin
CX4_RD_PENDr <= 1'b1; CX4_RD_PENDr <= 1'b1;
RQ_CX4_RDYr <= 1'b0; RQ_CX4_RDYr <= 1'b0;
end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin end else if(STATE == ST_CX4_RD_END) begin
CX4_RD_PENDr <= 1'b0; CX4_RD_PENDr <= 1'b0;
RQ_CX4_RDYr <= 1'b1; RQ_CX4_RDYr <= 1'b1;
end end
@ -402,21 +403,24 @@ end
reg snes_wr_cycle; reg snes_wr_cycle;
always @(posedge CLK2) begin always @(posedge CLK2) begin
if(SNES_cycle_start & IS_CART) begin if(SNES_cycle_start & IS_CART & ~cx4_active) begin
STATE <= ST_SNES_RD_ADDR; STATE <= ST_SNES_RD_ADDR;
end else if(SNES_WR_start & IS_CART) begin end else if(SNES_WR_start & IS_CART & ~cx4_active) begin
STATE <= ST_SNES_WR_ADDR; STATE <= ST_SNES_WR_ADDR;
end else begin end else begin
case(STATE) case(STATE)
ST_IDLE: begin ST_IDLE: begin
ROM_ADDRr <= MAPPED_SNES_ADDR; ROM_ADDRr <= MAPPED_SNES_ADDR;
if(CX4_RRQ | CX4_RD_PENDr) begin if(CX4_RD_PENDr) begin
ROM_ADDRr <= CX4_ADDR;
STATE <= ST_CX4_RD_WAIT; STATE <= ST_CX4_RD_WAIT;
ROM_ADDRr <= CX4_ADDR;
ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
end end
else if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR; else if(~cx4_active) begin
if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR; else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
else STATE <= ST_IDLE;
end
else STATE <= ST_IDLE; else STATE <= ST_IDLE;
end end
ST_SNES_RD_ADDR: begin ST_SNES_RD_ADDR: begin
@ -518,9 +522,7 @@ always @(posedge CLK2) begin
end end
ST_CX4_RD_WAIT: begin ST_CX4_RD_WAIT: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
if(ST_MEM_DELAYr == 4'h0) begin if(ST_MEM_DELAYr == 4'h0) STATE <= ST_CX4_RD_END;
STATE <= ST_IDLE;
end
else STATE <= ST_CX4_RD_WAIT; else STATE <= ST_CX4_RD_WAIT;
if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0]; if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0];
else CX4_DINr <= ROM_DATA[15:8]; else CX4_DINr <= ROM_DATA[15:8];

8
verilog/sd2snes_cx4/sd2snes_cx4.xise
View File

@ -238,7 +238,7 @@
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Map Effort Level" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/> <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
@ -320,7 +320,7 @@
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="30" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
@ -366,8 +366,8 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="3" xil_pn:valueState="non-default"/> <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="3" xil_pn:valueState="non-default"/> <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>