FPGA/Cx4: WIP
This commit is contained in:
ikari
parent
fc53d173bf
commit
8c76dfbeb6
@ -50,6 +50,7 @@
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#define FPGA_SPI_FAST() spi_set_speed(SPI_SPEED_FPGA_FAST)
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#define FPGA_SPI_SLOW() spi_set_speed(SPI_SPEED_FPGA_SLOW)
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#define FEAT_CX4 (1 << 4)
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#define FEAT_MSU1 (1 << 3)
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#define FEAT_SRTC (1 << 2)
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#define FEAT_ST0010 (1 << 1)
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37
src/memory.c
37
src/memory.c
@ -226,18 +226,16 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
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sram_writebyte(0xfc, rombase+0xd5);
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set_fpga_time(0x0220110301180530LL);
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}
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if(romprops.has_dspx) {
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printf("DSPx game. Loading firmware image %s...\n", romprops.necdsp_fw);
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if(romprops.has_st0010) {
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load_dspx(romprops.necdsp_fw, 1);
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} else {
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load_dspx(romprops.necdsp_fw, 0);
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if(file_res && romprops.necdsp_fw == DSPFW_1) {
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load_dspx(DSPFW_1B, 0);
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}
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fpga_pgm((uint8_t*)"/sd2snes/cx4.bit");
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if(romprops.has_dspx || romprops.has_cx4) {
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printf("DSPx game. Loading firmware image %s...\n", romprops.dsp_fw);
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load_dspx(romprops.dsp_fw, romprops.fpga_features);
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/* fallback to DSP1B firmware if DSP1.bin is not present */
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if(file_res && romprops.dsp_fw == DSPFW_1) {
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load_dspx(DSPFW_1B, romprops.fpga_features);
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}
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if(file_res) {
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snes_menu_errmsg(MENU_ERR_NODSP, (void*)romprops.necdsp_fw);
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snes_menu_errmsg(MENU_ERR_NODSP, (void*)romprops.dsp_fw);
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}
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}
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uint32_t rammask;
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@ -494,22 +492,29 @@ uint64_t sram_gettime(uint32_t base_addr) {
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return result & 0x00ffffffffffffffLL;
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}
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void load_dspx(const uint8_t *filename, uint8_t st0010) {
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void load_dspx(const uint8_t *filename, uint8_t coretype) {
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UINT bytes_read;
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DWORD filesize;
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uint16_t word_cnt;
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uint8_t wordsize_cnt = 0;
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uint16_t sector_remaining = 0;
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uint16_t sector_cnt = 0;
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uint16_t pgmsize = 2048;
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uint16_t datsize;
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uint16_t pgmsize = 0;
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uint16_t datsize = 0;
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uint32_t pgmdata = 0;
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uint16_t datdata = 0;
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if(st0010) {
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if(coretype & FEAT_ST0010) {
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datsize = 1536;
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} else {
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pgmsize = 2048;
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} else if (coretype & FEAT_DSPX) {
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datsize = 1024;
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pgmsize = 2048;
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} else if (coretype & FEAT_CX4) {
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datsize = 0;
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pgmsize = 1024; /* Cx4 data ROM */
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} else {
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printf("load_dspx: unknown core (%02x)!\n", coretype);
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}
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file_open((uint8_t*)filename, FA_READ);
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@ -539,7 +544,7 @@ void load_dspx(const uint8_t *filename, uint8_t st0010) {
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}
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wordsize_cnt = 0;
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if(st0010) {
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if(coretype & FEAT_ST0010) {
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file_seek(0xc000);
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sector_remaining = 0;
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}
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22
src/smc.c
22
src/smc.c
@ -83,6 +83,7 @@ void smc_id(snes_romprops_t* props) {
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props->has_dspx = 0;
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props->has_st0010 = 0;
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props->has_cx4 = 0;
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props->fpga_features = 0;
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for(uint8_t num = 0; num < 6; num++) {
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if(!file_readblock(header, hdr_addr[num], sizeof(snes_header_t))
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@ -144,39 +145,44 @@ void smc_id(snes_romprops_t* props) {
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props->mapper_id = 0;
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if(header->map == 0x31 && (header->carttype == 0x03 || header->carttype == 0x05)) {
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props->has_dspx = 1;
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props->necdsp_fw = DSPFW_1B;
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props->dsp_fw = DSPFW_1B;
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props->fpga_features |= FEAT_DSPX;
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}
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break;
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case 0x20: /* LoROM */
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props->mapper_id = 1;
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if ((header->map == 0x20 && header->carttype == 0x03) ||
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if (header->map == 0x20 && header->carttype == 0xf3) {
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props->has_cx4 = 1;
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props->dsp_fw = CX4FW;
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props->fpga_features |= FEAT_CX4;
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}
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else if ((header->map == 0x20 && header->carttype == 0x03) ||
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(header->map == 0x30 && header->carttype == 0x05 && header->licensee != 0xb2)) {
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props->has_dspx = 1;
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props->fpga_features |= FEAT_DSPX;
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// Pilotwings uses DSP1 instead of DSP1B
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if(!memcmp(header->name, "PILOTWINGS", 10)) {
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props->necdsp_fw = DSPFW_1;
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props->dsp_fw = DSPFW_1;
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} else {
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props->necdsp_fw = DSPFW_1B;
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props->dsp_fw = DSPFW_1B;
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}
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} else if (header->map == 0x20 && header->carttype == 0x05) {
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props->has_dspx = 1;
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props->necdsp_fw = DSPFW_2;
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props->dsp_fw = DSPFW_2;
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props->fpga_features |= FEAT_DSPX;
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} else if (header->map == 0x30 && header->carttype == 0x05 && header->licensee == 0xb2) {
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props->has_dspx = 1;
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props->necdsp_fw = DSPFW_3;
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props->dsp_fw = DSPFW_3;
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props->fpga_features |= FEAT_DSPX;
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} else if (header->map == 0x30 && header->carttype == 0x03) {
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props->has_dspx = 1;
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props->necdsp_fw = DSPFW_4;
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props->dsp_fw = DSPFW_4;
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props->fpga_features |= FEAT_DSPX;
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} else if (header->map == 0x30 && header->carttype == 0xf6 && header->romsize >= 0xa) {
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props->has_dspx = 1;
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props->has_st0010 = 1;
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props->necdsp_fw = DSPFW_ST0010;
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props->dsp_fw = DSPFW_ST0010;
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props->fpga_features |= FEAT_ST0010;
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header->ramsize = 2;
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}
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@ -33,6 +33,7 @@
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#define DSPFW_4 ((const uint8_t*)"/sd2snes/dsp4.bin")
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#define DSPFW_1B ((const uint8_t*)"/sd2snes/dsp1b.bin")
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#define DSPFW_ST0010 ((const uint8_t*)"/sd2snes/st0010.bin")
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#define CX4FW ((const uint8_t*)"/sd2snes/cx4.bin")
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typedef struct _snes_header {
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uint8_t maker[2]; /* 0xB0 */
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@ -60,10 +61,11 @@ typedef struct _snes_romprops {
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uint32_t expramsize_bytes; /* ExpRAM size in bytes */
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uint32_t ramsize_bytes; /* CartRAM size in bytes */
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uint32_t romsize_bytes; /* ROM size in bytes (rounded up) */
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const uint8_t* necdsp_fw; /* NEC DSP ROM filename */
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const uint8_t* dsp_fw; /* DSP (NEC / Hitachi) ROM filename */
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uint8_t has_dspx; /* DSP[1-4] presence flag */
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uint8_t has_st0010; /* st0010 presence flag (additional to dspx)*/
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uint8_t has_msu1; /* MSU1 presence flag */
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uint8_t has_cx4; /* CX4 presence flag */
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uint8_t fpga_features; /* feature/peripheral enable bits*/
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snes_header_t header; /* original header from ROM image */
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} snes_romprops_t;
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@ -16,55 +16,55 @@
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<files>
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<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
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</file>
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<file xil_pn:name="bsx.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
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</file>
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<file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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</file>
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<file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
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</file>
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<file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
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</file>
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<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
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</file>
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<file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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</file>
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<file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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</file>
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<file xil_pn:name="rtc.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
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</file>
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<file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
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</file>
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<file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
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</file>
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<file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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</file>
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<file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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</file>
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<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
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@ -72,7 +72,7 @@
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</file>
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<file xil_pn:name="main_tf.v" xil_pn:type="FILE_VERILOG"/>
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<file xil_pn:name="updtest_tf.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="19"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="19"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="19"/>
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@ -90,11 +90,11 @@
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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</file>
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<file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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</file>
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<file xil_pn:name="ipcore_dir/upd77c25_datram.xise" xil_pn:type="FILE_COREGENISE">
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@ -377,8 +377,8 @@
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<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="12" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="12" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="8" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="8" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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@ -433,7 +433,7 @@
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|updtest" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
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@ -42,11 +42,12 @@ parameter BUSY_DMA = 2'b01;
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parameter BUSY_CPU = 2'b10;
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wire datram_enable = CS & (ADDR[11:0] < 12'hc00);
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wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11000);
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wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11000);
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wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11001);
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wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11001);
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wire vector_enable = CS & (ADDR[12:5] == 8'b11111011);
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wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11);
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wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000);
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wire debug_enable = CS & (&(ADDR[12:7]) && &(ADDR[5:4]));
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wire [7:0] DATRAM_DO;
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reg [7:0] MMIO_DOr;
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@ -54,12 +55,15 @@ wire [7:0] MMIO_DO;
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wire [7:0] STATUS_DO;
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wire [7:0] VECTOR_DO;
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wire [7:0] GPR_DO;
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wire [7:0] DEBUG_DO;
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reg [7:0] DEBUG_DOr;
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assign DO = datram_enable ? DATRAM_DO
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: mmio_enable ? MMIO_DO
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: status_enable ? STATUS_DO
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: vector_enable ? VECTOR_DO
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: gpr_enable ? GPR_DO
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: debug_enable ? DEBUG_DO
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: 8'h00;
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/* 0x1f40 - 0x1f52: MMIO
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@ -87,7 +91,20 @@ wire [47:0] cpu_mul_result;
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reg [23:0] const [15:0];
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reg [15:0] cachetag [1:0]; // 15: valid; 14-0: bank number
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reg [14:0] cache_pgmpage;
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reg [14:0] cpu_cache_pgmpage;
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reg cache_cachepage;
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reg cpu_cache_cachepage;
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reg cpu_cache_done;
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reg [7:0] cpu_pc_stack [7:0];
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reg [7:0] cpu_page_stack;
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initial begin
|
||||
cache_pgmpage = 15'b0;
|
||||
cpu_cache_pgmpage = 15'b0;
|
||||
cache_cachepage = 1'b0;
|
||||
cpu_cache_cachepage = 1'b0;
|
||||
cpu_cache_done = 1'b0;
|
||||
cachetag[0] = 16'h0000;
|
||||
cachetag[1] = 16'h0000;
|
||||
cx4_busy = 3'b000;
|
||||
@ -112,12 +129,22 @@ initial begin
|
||||
const[13] = 24'hfeffff;
|
||||
const[14] = 24'h000100;
|
||||
const[15] = 24'h00feff;
|
||||
cpu_pc_stack[0] = 8'b0;
|
||||
cpu_pc_stack[1] = 8'b0;
|
||||
cpu_pc_stack[2] = 8'b0;
|
||||
cpu_pc_stack[3] = 8'b0;
|
||||
cpu_pc_stack[4] = 8'b0;
|
||||
cpu_pc_stack[5] = 8'b0;
|
||||
cpu_pc_stack[6] = 8'b0;
|
||||
cpu_pc_stack[7] = 8'b0;
|
||||
cpu_page_stack = 8'b0;
|
||||
end
|
||||
|
||||
assign MMIO_DO = MMIO_DOr;
|
||||
assign VECTOR_DO = vector [ADDR[4:0]];
|
||||
assign GPR_DO = gpr [ADDR[5:0]];
|
||||
assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0};
|
||||
assign DEBUG_DO = DEBUG_DOr;
|
||||
|
||||
reg [7:0] DIr;
|
||||
always @(posedge CLK) DIr <= DI;
|
||||
@ -143,9 +170,11 @@ reg [23:0] cpu_idb; // tmp register for reg file read
|
||||
*/
|
||||
reg CACHE_TRIG_ENr;
|
||||
reg CACHE_TRIG_EN2r;
|
||||
reg cpu_cache_en;
|
||||
initial begin
|
||||
CACHE_TRIG_ENr = 1'b0;
|
||||
CACHE_TRIG_EN2r = 1'b0;
|
||||
cpu_cache_en = 1'b0;
|
||||
end
|
||||
always @(posedge CLK) CACHE_TRIG_EN2r <= CACHE_TRIG_ENr;
|
||||
wire CACHE_TRIG_EN = CACHE_TRIG_EN2r;
|
||||
@ -156,11 +185,19 @@ wire DMA_TRIG_EN = DMA_TRIG_ENr;
|
||||
|
||||
reg CACHE_BUS_RRQr;
|
||||
reg DMA_BUS_RRQr;
|
||||
reg cpu_bus_rq;
|
||||
|
||||
initial begin
|
||||
CACHE_BUS_RRQr = 1'b0;
|
||||
DMA_BUS_RRQr = 1'b0;
|
||||
cpu_bus_rq = 1'b0;
|
||||
end
|
||||
assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr;
|
||||
|
||||
assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr | cpu_bus_rq;
|
||||
|
||||
reg cpu_page;
|
||||
reg [14:0] cpu_p;
|
||||
reg [7:0] cpu_pc;
|
||||
|
||||
reg cpu_go_en_r;
|
||||
initial cpu_go_en_r = 1'b0;
|
||||
@ -192,23 +229,31 @@ always @(posedge CLK) begin
|
||||
5'h10: MMIO_DOr <= cx4_mmio_r1f50; // 1f50
|
||||
5'h11: MMIO_DOr <= {7'b0, cx4_mmio_r1f51}; // 1f51
|
||||
5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52}; // 1f52
|
||||
|
||||
5'h13: MMIO_DOr <= cpu_mul_result[47:40]; // 1f40
|
||||
5'h14: MMIO_DOr <= cpu_mul_result[39:32]; // 1f40
|
||||
5'h15: MMIO_DOr <= cpu_mul_result[31:24]; // 1f40
|
||||
5'h16: MMIO_DOr <= cpu_mul_result[23:16]; // 1f40
|
||||
5'h17: MMIO_DOr <= cpu_mul_result[15:8]; // 1f40
|
||||
5'h18: MMIO_DOr <= cpu_mul_result[7:0]; // 1f40
|
||||
|
||||
|
||||
// 5'h14: MMIO_DOr <= cachetag[0][15:8]; // 1f40
|
||||
// 5'h15: MMIO_DOr <= cachetag[0][7:0]; // 1f41
|
||||
// 5'h16: MMIO_DOr <= cachetag[1][15:8]; // 1f42
|
||||
// 5'h17: MMIO_DOr <= cachetag[1][7:0]; // 1f43
|
||||
default: MMIO_DOr <= 8'hff;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
case(ADDR[3:0])
|
||||
4'h0: DEBUG_DOr <= cachetag[0][15:8]; // 1f40
|
||||
4'h1: DEBUG_DOr <= cachetag[0][7:0]; // 1f41
|
||||
4'h2: DEBUG_DOr <= cachetag[1][15:8]; // 1f42
|
||||
4'h3: DEBUG_DOr <= cachetag[1][7:0]; // 1f43
|
||||
4'h4: DEBUG_DOr <= cpu_page;
|
||||
4'h5: DEBUG_DOr <= cpu_p;
|
||||
4'h6: DEBUG_DOr <= cpu_pc;
|
||||
4'h7: DEBUG_DOr <= cx4_busy;
|
||||
4'h8: DEBUG_DOr <= cpu_page_stack[0];
|
||||
4'h9: DEBUG_DOr <= cpu_pc_stack[0];
|
||||
4'ha: DEBUG_DOr <= cpu_page_stack[1];
|
||||
4'hb: DEBUG_DOr <= cpu_pc_stack[1];
|
||||
4'hc: DEBUG_DOr <= cpu_page_stack[2];
|
||||
4'hd: DEBUG_DOr <= cpu_pc_stack[2];
|
||||
4'he: DEBUG_DOr <= cpu_page_stack[3];
|
||||
4'hf: DEBUG_DOr <= cpu_pc_stack[3];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(MMIO_WR_EN) begin
|
||||
case(ADDR[4:0])
|
||||
@ -272,10 +317,11 @@ reg [23:0] CACHE_SRC_ADDRr;
|
||||
wire [22:0] MAPPED_CACHE_SRC_ADDR = {CACHE_SRC_ADDRr[23:16],CACHE_SRC_ADDRr[14:0]};
|
||||
reg [23:0] DMA_SRC_ADDRr;
|
||||
wire [22:0] MAPPED_DMA_SRC_ADDR = {DMA_SRC_ADDRr[23:16],DMA_SRC_ADDRr[14:0]};
|
||||
wire [22:0] MAPPED_CPU_BUS_ADDR;
|
||||
|
||||
assign BUS_ADDR = cx4_busy[BUSY_CACHE] ? MAPPED_CACHE_SRC_ADDR
|
||||
: cx4_busy[BUSY_DMA] ? MAPPED_DMA_SRC_ADDR
|
||||
: 24'h800000 /* XXX cx4_bus_addr */;
|
||||
: MAPPED_CPU_BUS_ADDR;
|
||||
|
||||
reg cx4_pgmrom_we;
|
||||
initial cx4_pgmrom_we = 1'b0;
|
||||
@ -288,15 +334,24 @@ always @(posedge CLK) begin
|
||||
ST_CACHE_IDLE: begin
|
||||
if(CACHE_TRIG_EN
|
||||
& (~cachetag[cx4_mmio_cachepage][15]
|
||||
| |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage)))
|
||||
begin
|
||||
| |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) begin
|
||||
CACHE_ST <= ST_CACHE_START;
|
||||
end else CACHE_ST <= ST_CACHE_IDLE;
|
||||
cache_pgmpage <= cx4_mmio_pgmpage;
|
||||
cache_cachepage <= cx4_mmio_cachepage;
|
||||
end else if(cpu_cache_en
|
||||
& (~cachetag[~cpu_page][15]
|
||||
| |(cachetag[~cpu_page][14:0] ^ cpu_p))) begin
|
||||
CACHE_ST <= ST_CACHE_START;
|
||||
cache_pgmpage <= cpu_p;
|
||||
cache_cachepage <= ~cpu_page;
|
||||
cx4_busy[BUSY_CACHE] <= 1'b1;
|
||||
end
|
||||
else CACHE_ST <= ST_CACHE_IDLE;
|
||||
end
|
||||
ST_CACHE_START: begin
|
||||
cx4_busy[BUSY_CACHE] <= 1'b1;
|
||||
CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cx4_mmio_pgmpage, 9'b0};
|
||||
cx4_pgmrom_addr <= {cx4_mmio_cachepage, 9'b0};
|
||||
CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cache_pgmpage, 9'b0};
|
||||
cx4_pgmrom_addr <= {cache_cachepage, 9'b0};
|
||||
CACHE_ST <= ST_CACHE_WAIT;
|
||||
cache_count <= 10'b0;
|
||||
CACHE_BUS_RRQr <= 1'b1;
|
||||
@ -315,7 +370,7 @@ always @(posedge CLK) begin
|
||||
cx4_pgmrom_addr <= cx4_pgmrom_addr + 1;
|
||||
if(cache_count == 9'h1ff) begin
|
||||
cx4_busy[BUSY_CACHE] <= 1'b0;
|
||||
cachetag[cx4_mmio_cachepage] <= {1'b1,cx4_mmio_pgmpage};
|
||||
cachetag[cache_cachepage] <= {1'b1,cache_pgmpage};
|
||||
CACHE_ST <= ST_CACHE_IDLE;
|
||||
end else begin
|
||||
CACHE_BUS_RRQr <= 1'b1;
|
||||
@ -334,7 +389,7 @@ reg [11:0] cx4_dma_datram_addr;
|
||||
reg [11:0] cx4_cpu_datram_addr;
|
||||
wire [11:0] cx4_datram_addr = cx4_busy[BUSY_DMA] ? cx4_dma_datram_addr : cx4_cpu_datram_addr;
|
||||
reg [23:0] cx4_cpu_datram_di;
|
||||
wire [23:0] cx4_datram_di = cx4_busy[BUSY_DMA] ? BUS_DI : cx4_cpu_datram_di;
|
||||
wire [7:0] cx4_datram_di = cx4_busy[BUSY_DMA] ? BUS_DI : cx4_cpu_datram_di;
|
||||
reg [15:0] dma_count;
|
||||
initial dma_count = 16'b0;
|
||||
|
||||
@ -380,10 +435,8 @@ end
|
||||
=========== CPU ===========
|
||||
***************************/
|
||||
reg [4:0] CPU_STATE;
|
||||
reg cpu_page;
|
||||
reg [7:0] cpu_pc;
|
||||
reg [8:0] cpu_stack [7:0];
|
||||
reg [2:0] cpu_sp;
|
||||
initial cpu_sp = 3'b000;
|
||||
wire [15:0] cpu_op_w;
|
||||
reg [15:0] cpu_op;
|
||||
reg [23:0] cpu_a;
|
||||
@ -391,17 +444,20 @@ reg [23:0] cpu_busdata;
|
||||
reg [23:0] cpu_romdata;
|
||||
reg [23:0] cpu_ramdata;
|
||||
reg [23:0] cpu_busaddr;
|
||||
assign MAPPED_CPU_BUS_ADDR = {cpu_busaddr[23:16], cpu_busaddr[14:0]};
|
||||
reg [23:0] cpu_romaddr;
|
||||
reg [23:0] cpu_ramaddr;
|
||||
reg [23:0] cpu_acch;
|
||||
reg [23:0] cpu_accl;
|
||||
reg [23:0] cpu_mul_src;
|
||||
reg [24:0] cpu_alu_res;
|
||||
reg [23:0] cpu_dummy;
|
||||
reg [23:0] cpu_tmp;
|
||||
|
||||
reg [23:0] cpu_sa; // tmp register for shifted accumulator
|
||||
reg fl_n;
|
||||
reg fl_z;
|
||||
reg fl_c;
|
||||
reg [15:0] cpu_p;
|
||||
|
||||
wire [9:0] cx4_datrom_addr = cpu_a[9:0];
|
||||
wire [23:0] cx4_datrom_do;
|
||||
@ -413,49 +469,63 @@ parameter ST_CPU_1 = 5'b00100;
|
||||
parameter ST_CPU_2 = 5'b01000;
|
||||
parameter ST_CPU_3 = 5'b10000;
|
||||
|
||||
initial CPU_STATE <= ST_CPU_IDLE;
|
||||
initial CPU_STATE = ST_CPU_IDLE;
|
||||
|
||||
parameter OP_NOP = 4'b0000;
|
||||
parameter OP_JP = 4'b0001;
|
||||
parameter OP_SKIP = 4'b0010;
|
||||
parameter OP_RT = 4'b0011;
|
||||
parameter OP_LD = 4'b0100;
|
||||
parameter OP_ST = 4'b0101;
|
||||
parameter OP_SWP = 4'b0110;
|
||||
parameter OP_RDROM = 4'b0111;
|
||||
parameter OP_RDRAM = 4'b1000;
|
||||
parameter OP_WRRAM = 4'b1001;
|
||||
parameter OP_ALU = 4'b1010;
|
||||
parameter OP_MUL = 4'b1011;
|
||||
parameter OP_WAI = 4'b1100;
|
||||
parameter OP_BUS = 4'b1101;
|
||||
parameter OP_HLT = 4'b1110;
|
||||
parameter OP_NOP = 5'b00000;
|
||||
parameter OP_JP = 5'b00001;
|
||||
parameter OP_SKIP = 5'b00010;
|
||||
parameter OP_RT = 5'b00011;
|
||||
parameter OP_LD = 5'b00100;
|
||||
parameter OP_ST = 5'b00101;
|
||||
parameter OP_SWP = 5'b00110;
|
||||
parameter OP_RDROM = 5'b00111;
|
||||
parameter OP_RDRAM = 5'b01000;
|
||||
parameter OP_WRRAM = 5'b01001;
|
||||
parameter OP_ALU = 5'b01010;
|
||||
parameter OP_MUL = 5'b01011;
|
||||
parameter OP_WAI = 5'b01100;
|
||||
parameter OP_BUS = 5'b01101;
|
||||
parameter OP_CMP = 5'b01110;
|
||||
parameter OP_SEX = 5'b01111;
|
||||
parameter OP_HLT = 5'b10000;
|
||||
|
||||
wire [6:0] op_id = cpu_op_w[15:10];
|
||||
reg [7:0] op_param;
|
||||
reg [3:0] op;
|
||||
reg [4:0] op;
|
||||
reg [1:0] op_sa;
|
||||
reg op_imm;
|
||||
reg op_p;
|
||||
reg op_call;
|
||||
reg op_jump;
|
||||
reg condtrue;
|
||||
reg cpu_bus_rq;
|
||||
|
||||
/* XXX DEBUG */
|
||||
reg [23:0] dbg_cnt;
|
||||
initial dbg_cnt = 24'b0;
|
||||
always @(posedge CLK) dbg_cnt <= dbg_cnt + 1;
|
||||
wire step_enable = 1'b1;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(cpu_go_en_r) cx4_busy[BUSY_CPU] <= 1'b1;
|
||||
else if((op == OP_HLT) && step_enable) cx4_busy[BUSY_CPU] <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(step_enable | cpu_go_en_r) begin
|
||||
case(CPU_STATE)
|
||||
ST_CPU_IDLE: begin
|
||||
if(cpu_go_en_r) begin
|
||||
cpu_pc <= cx4_mmio_pc;
|
||||
cpu_page <= cx4_mmio_cachepage;
|
||||
cpu_p <= cx4_mmio_pgmpage;
|
||||
op <= OP_NOP;
|
||||
CPU_STATE <= ST_CPU_2;
|
||||
cx4_busy[BUSY_CPU] <= 1'b1;
|
||||
end
|
||||
else CPU_STATE <= ST_CPU_IDLE;
|
||||
end
|
||||
ST_CPU_0: begin // Phase 0:
|
||||
cpu_cache_en <= 1'b0;
|
||||
if(op == OP_HLT) begin
|
||||
cx4_busy[BUSY_CPU] <= 1'b0;
|
||||
CPU_STATE <= ST_CPU_IDLE;
|
||||
end
|
||||
else CPU_STATE <= ST_CPU_1;
|
||||
@ -475,7 +545,7 @@ always @(posedge CLK) begin
|
||||
2'b11: condtrue <= (fl_n == cpu_op[0]);
|
||||
endcase
|
||||
end
|
||||
OP_LD, OP_SWP, OP_ALU, OP_MUL: begin
|
||||
OP_LD, OP_ALU, OP_MUL, OP_CMP, OP_SEX: begin
|
||||
if(op_imm) cpu_idb <= {16'b0, op_param};
|
||||
else casex(op_param)
|
||||
8'h00: cpu_idb <= cpu_a;
|
||||
@ -492,7 +562,7 @@ always @(posedge CLK) begin
|
||||
gpr[op_param[3:0]*3]};
|
||||
default: cpu_idb <= 24'b0;
|
||||
endcase
|
||||
if(op==OP_ALU) begin
|
||||
if(op==OP_ALU || op==OP_CMP) begin
|
||||
case(op_sa)
|
||||
2'b00: cpu_sa <= cpu_a;
|
||||
2'b01: cpu_sa <= cpu_a << 1;
|
||||
@ -504,8 +574,26 @@ always @(posedge CLK) begin
|
||||
OP_ST: begin
|
||||
cpu_idb <= cpu_a;
|
||||
end
|
||||
OP_SWP: begin
|
||||
cpu_idb <= cpu_a;
|
||||
casex(op_param)
|
||||
8'h00: cpu_tmp <= cpu_a;
|
||||
8'h01: cpu_tmp <= cpu_acch;
|
||||
8'h02: cpu_tmp <= cpu_accl;
|
||||
8'h03: cpu_tmp <= cpu_busdata;
|
||||
8'h08: cpu_tmp <= cpu_romdata;
|
||||
8'h0c: cpu_tmp <= cpu_ramdata;
|
||||
8'h13: cpu_tmp <= cpu_busaddr;
|
||||
8'h1c: cpu_tmp <= cpu_ramaddr;
|
||||
8'h5x: cpu_tmp <= const[op_param[3:0]];
|
||||
8'h6x: cpu_tmp <= {gpr[op_param[3:0]*3+2],
|
||||
gpr[op_param[3:0]*3+1],
|
||||
gpr[op_param[3:0]*3]};
|
||||
default: cpu_tmp <= 24'b0;
|
||||
endcase
|
||||
end
|
||||
OP_RDRAM, OP_WRRAM: begin
|
||||
if(op_imm) cpu_ramaddr <= {16'b0, op_param};
|
||||
if(op_imm) cx4_cpu_datram_addr <= {16'b0, op_param} + cpu_ramaddr;
|
||||
else casex(op_param)
|
||||
8'h00: cx4_cpu_datram_addr <= cpu_a;
|
||||
8'h01: cx4_cpu_datram_addr <= cpu_acch;
|
||||
@ -522,32 +610,39 @@ always @(posedge CLK) begin
|
||||
default: cx4_cpu_datram_addr <= 24'b0;
|
||||
endcase
|
||||
end
|
||||
OP_BUS: cpu_bus_rq <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
ST_CPU_1: begin
|
||||
CPU_STATE <= ST_CPU_2;
|
||||
case(op)
|
||||
OP_JP: begin
|
||||
if(condtrue) begin
|
||||
if(op_call) begin
|
||||
cpu_stack[cpu_sp] <= cpu_pc + 1;
|
||||
cpu_sp <= cpu_sp + 1;
|
||||
end
|
||||
cpu_pc <= op_param;
|
||||
if(!cx4_busy[BUSY_CACHE]) begin
|
||||
if(condtrue) begin
|
||||
if(op_call) begin
|
||||
cpu_page_stack[cpu_sp] <= cpu_page;
|
||||
cpu_pc_stack[cpu_sp] <= cpu_pc + 1;
|
||||
cpu_sp <= cpu_sp + 1;
|
||||
end
|
||||
cpu_pc <= op_param;
|
||||
cpu_page <= cpu_page ^ op_p;
|
||||
end else cpu_pc <= cpu_pc + 1;
|
||||
end
|
||||
end
|
||||
OP_SKIP: begin
|
||||
if(condtrue) begin
|
||||
cpu_pc <= cpu_pc + 2;
|
||||
end
|
||||
if(condtrue) cpu_pc <= cpu_pc + 2;
|
||||
else cpu_pc <= cpu_pc + 1;
|
||||
end
|
||||
OP_RT: begin
|
||||
cpu_pc <= cpu_stack[cpu_sp - 1];
|
||||
cpu_page <= cpu_page_stack[cpu_sp - 1];
|
||||
cpu_pc <= cpu_pc_stack[cpu_sp - 1];
|
||||
cpu_sp <= cpu_sp - 1;
|
||||
end
|
||||
OP_LD, OP_ST, OP_SWP, OP_RDROM, OP_RDRAM, OP_WRRAM, OP_ALU, OP_MUL, OP_BUS:
|
||||
cpu_pc <= cpu_pc + 1;
|
||||
OP_WAI: if(BUS_RDY) cpu_pc <= cpu_pc + 1;
|
||||
OP_BUS: begin
|
||||
cpu_bus_rq <= 1'b0;
|
||||
cpu_pc <= cpu_pc + 1;
|
||||
end
|
||||
default: cpu_pc <= cpu_pc + 1;
|
||||
endcase
|
||||
end
|
||||
@ -559,56 +654,101 @@ always @(posedge CLK) begin
|
||||
4'b0x00: cpu_a <= cpu_idb;
|
||||
4'b0x11: cpu_p <= cpu_idb;
|
||||
4'b1100: cpu_p[7:0] <= op_param;
|
||||
4'b1101: cpu_p[15:8] <= op_param;
|
||||
4'b1101: cpu_p[14:8] <= op_param;
|
||||
endcase
|
||||
end
|
||||
OP_ST: begin
|
||||
casex(op_param)
|
||||
8'h00: cpu_a <= cpu_idb;
|
||||
OP_ST, OP_SWP: begin
|
||||
casex(op_param)
|
||||
// 8'h00: cpu_a <= cpu_idb;
|
||||
8'h01: cpu_acch <= cpu_idb;
|
||||
8'h02: cpu_accl <= cpu_idb;
|
||||
8'h03: cpu_busdata <= cpu_idb;
|
||||
// 8'h03: cpu_busdata <= cpu_idb;
|
||||
8'h08: cpu_romdata <= cpu_idb;
|
||||
8'h0c: cpu_ramdata <= cpu_idb;
|
||||
8'h13: cpu_busaddr <= cpu_idb;
|
||||
8'h1c: cpu_ramaddr <= cpu_idb;
|
||||
endcase
|
||||
end
|
||||
OP_SWP: begin
|
||||
casex(op_param)
|
||||
8'h00: cpu_a <= cpu_a;
|
||||
8'h01: cpu_acch <= cpu_a;
|
||||
8'h02: cpu_accl <= cpu_a;
|
||||
8'h03: cpu_busdata <= cpu_a;
|
||||
8'h08: cpu_romdata <= cpu_a;
|
||||
8'h0c: cpu_ramdata <= cpu_a;
|
||||
8'h13: cpu_busaddr <= cpu_a;
|
||||
8'h1c: cpu_ramaddr <= cpu_a;
|
||||
endcase
|
||||
if(op==OP_SWP) cpu_a <= cpu_tmp;
|
||||
end
|
||||
OP_RDROM: cpu_romdata <= cx4_datrom_do;
|
||||
OP_RDRAM: cpu_ramdata <= cx4_datram_do;
|
||||
OP_RDRAM: begin
|
||||
case(cpu_op[9:8])
|
||||
2'b00: cpu_ramdata[7:0] <= cx4_datram_do;
|
||||
2'b01: cpu_ramdata[15:8] <= cx4_datram_do;
|
||||
2'b10: cpu_ramdata[23:16] <= cx4_datram_do;
|
||||
endcase
|
||||
end
|
||||
OP_WRRAM: begin
|
||||
case(cpu_op[9:8])
|
||||
2'b00: cx4_cpu_datram_di[7:0] <= cpu_ramdata[7:0];
|
||||
2'b01: cx4_cpu_datram_di[15:8] <= cpu_ramdata[15:8];
|
||||
2'b10: cx4_cpu_datram_di[23:16] <= cpu_ramdata[23:16];
|
||||
2'b00: cx4_cpu_datram_di <= cpu_ramdata[7:0];
|
||||
2'b01: cx4_cpu_datram_di <= cpu_ramdata[15:8];
|
||||
2'b10: cx4_cpu_datram_di <= cpu_ramdata[23:16];
|
||||
endcase
|
||||
cx4_cpu_datram_we <= 1'b1;
|
||||
end
|
||||
OP_ALU: begin
|
||||
/* XXX TODO FUCK YEAH ALU */
|
||||
OP_CMP: begin
|
||||
case(cpu_op[15:11])
|
||||
5'b01001: cpu_alu_res <= cpu_idb - cpu_sa;
|
||||
5'b01010: cpu_alu_res <= cpu_sa - cpu_idb;
|
||||
endcase
|
||||
end
|
||||
OP_SEX: begin
|
||||
case(cpu_op[9:8])
|
||||
2'b01: cpu_alu_res <= {{16{cpu_idb[7]}}, cpu_idb[7:0]};
|
||||
2'b10: cpu_alu_res <= {{8{cpu_idb[15]}}, cpu_idb[15:0]};
|
||||
endcase
|
||||
end
|
||||
OP_ALU: begin
|
||||
case(cpu_op[15:11])
|
||||
5'b10000: cpu_alu_res <= cpu_sa + cpu_idb;
|
||||
5'b10001: cpu_alu_res <= cpu_idb - cpu_sa;
|
||||
5'b10010: cpu_alu_res <= cpu_sa - cpu_idb;
|
||||
5'b10101: cpu_alu_res <= cpu_sa ^ cpu_idb;
|
||||
5'b10110: cpu_alu_res <= cpu_sa & cpu_idb;
|
||||
5'b10111: cpu_alu_res <= cpu_sa | cpu_idb;
|
||||
5'b11000: cpu_alu_res <= cpu_a >> cpu_idb;
|
||||
5'b11001: cpu_alu_res <= $signed(cpu_a) >>> cpu_idb;
|
||||
5'b11010: {cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb;
|
||||
5'b11011: cpu_alu_res <= cpu_a << cpu_idb;
|
||||
endcase
|
||||
end
|
||||
OP_BUS: cpu_bus_rq <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
ST_CPU_3: begin
|
||||
CPU_STATE <= ST_CPU_0;
|
||||
case(op)
|
||||
OP_SWP: cpu_a <= cpu_idb;
|
||||
OP_LD: begin
|
||||
casex(cpu_op[11:8])
|
||||
4'b0x11: cpu_cache_en <= 1'b1;
|
||||
4'b1100: cpu_cache_en <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
OP_BUS: cpu_busaddr <= cpu_busaddr + 1;
|
||||
OP_WRRAM: cx4_cpu_datram_we <= 1'b0;
|
||||
OP_CMP: begin
|
||||
fl_n <= cpu_alu_res[23];
|
||||
fl_z <= cpu_alu_res[23:0] == 24'b0;
|
||||
fl_c <= ~cpu_alu_res[24];
|
||||
end
|
||||
OP_SEX: cpu_a <= cpu_alu_res[23:0];
|
||||
OP_ALU: begin
|
||||
/* XXX TODO FUCKING FLAGS */
|
||||
cpu_a <= cpu_alu_res[23:0];
|
||||
case(cpu_op[15:11])
|
||||
5'b10000: begin
|
||||
fl_n <= cpu_alu_res[23];
|
||||
fl_z <= cpu_alu_res[23:0] == 24'b0;
|
||||
fl_c <= cpu_alu_res[24];
|
||||
end
|
||||
5'b10001, 5'b10010: begin
|
||||
fl_n <= cpu_alu_res[23];
|
||||
fl_z <= cpu_alu_res[23:0] == 24'b0;
|
||||
fl_c <= ~cpu_alu_res[24];
|
||||
end
|
||||
default: begin
|
||||
fl_n <= cpu_alu_res[23];
|
||||
fl_z <= cpu_alu_res[23:0] == 24'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
OP_MUL: begin
|
||||
cpu_acch <= cpu_mul_result[47:24];
|
||||
@ -616,7 +756,6 @@ always @(posedge CLK) begin
|
||||
fl_z <= (cpu_mul_result == 48'b0);
|
||||
fl_n <= cpu_mul_result[47];
|
||||
end
|
||||
OP_BUS: cpu_bus_rq <= 1'b0;
|
||||
endcase
|
||||
cpu_op <= cpu_op_w;
|
||||
casex(cpu_op_w[15:11])
|
||||
@ -636,9 +775,9 @@ always @(posedge CLK) begin
|
||||
5'b01101: op <= OP_RDRAM;
|
||||
5'b11101: op <= OP_WRRAM;
|
||||
|
||||
5'b01001: op <= OP_ALU;
|
||||
5'b01010: op <= OP_ALU;
|
||||
5'b01011: op <= OP_ALU;
|
||||
5'b01001: op <= OP_CMP;
|
||||
5'b01010: op <= OP_CMP;
|
||||
5'b01011: op <= OP_SEX;
|
||||
5'b10000: op <= OP_ALU;
|
||||
5'b10001: op <= OP_ALU;
|
||||
5'b10010: op <= OP_ALU;
|
||||
@ -659,22 +798,45 @@ always @(posedge CLK) begin
|
||||
op_imm <= cpu_op_w[10];
|
||||
op_p <= cpu_op_w[9];
|
||||
op_call <= cpu_op_w[13];
|
||||
op_param <= cpu_op_w[7:0];
|
||||
op_sa <= cpu_op_w[9:8];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg[2:0] BUSRD_STATE;
|
||||
parameter ST_BUSRD_IDLE = 2'b01;
|
||||
parameter ST_BUSRD_WAIT = 2'b10;
|
||||
initial BUSRD_STATE = ST_BUSRD_IDLE;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CPU_STATE == ST_CPU_2
|
||||
&& (op == OP_ST || op == OP_SWP)
|
||||
&& op_param == 8'h03)
|
||||
cpu_busdata <= cpu_idb;
|
||||
else begin
|
||||
case(BUSRD_STATE)
|
||||
ST_BUSRD_IDLE: begin
|
||||
if(cpu_bus_rq) begin
|
||||
BUSRD_STATE <= ST_BUSRD_WAIT;
|
||||
end
|
||||
end
|
||||
ST_BUSRD_WAIT: begin
|
||||
if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_IDLE;
|
||||
else BUSRD_STATE <= ST_BUSRD_WAIT;
|
||||
if(~cpu_busaddr[22]) cpu_busdata <= BUS_DI;
|
||||
else cpu_busdata <= 8'h00;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// gpr write, either by CPU or by MMIO
|
||||
always @(posedge CLK) begin
|
||||
if(CPU_STATE == ST_CPU_2
|
||||
&& (op == OP_SWP)
|
||||
&& (op_param[7:4] == 8'h6)) begin
|
||||
gpr[op_param[3:0]*3+2] <= cpu_a[23:16];
|
||||
gpr[op_param[3:0]*3+1] <= cpu_a[15:8];
|
||||
gpr[op_param[3:0]*3] <= cpu_a[7:0];
|
||||
end
|
||||
else if(CPU_STATE == ST_CPU_2
|
||||
&& (op == OP_ST)
|
||||
&& (op_param[7:4] == 8'h6)) begin
|
||||
&& (op == OP_ST || op == OP_SWP)
|
||||
&& (op_param[7:4] == 4'h6)) begin
|
||||
gpr[op_param[3:0]*3+2] <= cpu_idb[23:16];
|
||||
gpr[op_param[3:0]*3+1] <= cpu_idb[15:8];
|
||||
gpr[op_param[3:0]*3] <= cpu_idb[7:0];
|
||||
@ -714,7 +876,7 @@ cx4_pgmrom cx4_pgmrom (
|
||||
.addra(cx4_pgmrom_addr), // input [9 : 0] addra
|
||||
.dina(BUS_DI), // input [7 : 0] dina
|
||||
.clkb(CLK), // input clkb
|
||||
.addrb(cpu_pc), // input [8 : 0] addrb
|
||||
.addrb({cpu_page,cpu_pc}), // input [8 : 0] addrb
|
||||
.doutb(cpu_op_w) // output [15 : 0] doutb
|
||||
);
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 13.2
|
||||
# Date: Fri Oct 21 20:38:07 2011
|
||||
# Date: Mon Oct 24 22:04:01 2011
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
@ -49,7 +49,7 @@ CSET multtype=Parallel_Multiplier
|
||||
CSET optgoal=Speed
|
||||
CSET outputwidthhigh=47
|
||||
CSET outputwidthlow=0
|
||||
CSET pipestages=2
|
||||
CSET pipestages=3
|
||||
CSET portatype=Signed
|
||||
CSET portawidth=24
|
||||
CSET portbtype=Signed
|
||||
@ -65,4 +65,4 @@ CSET zerodetect=false
|
||||
MISC pkg_timestamp=2011-06-21T06:26:54.000Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: efe4d30e
|
||||
# CRC: fd22ef14
|
||||
|
||||
@ -29,335 +29,29 @@
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|cx4_mul" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="cx4_mul.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/cx4_mul" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="cx4_mul" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="cx4_mul_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="cx4_mul_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="cx4_mul_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="cx4_mul_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_mul" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-21T22:38:29" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BA4F9A4C077E07CDE90A18AE4A7F1BA5" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-25T00:04:25" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="384E11781B113D7487AFCF863F4DA087" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
@ -83,11 +83,11 @@ output [15 : 0] doutb;
|
||||
.C_HAS_RSTB(0),
|
||||
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||
.C_INIT_FILE_NAME("no_coe_file_loaded"),
|
||||
.C_INIT_FILE_NAME("cx4_pgmrom.mif"),
|
||||
.C_INITA_VAL("0"),
|
||||
.C_INITB_VAL("0"),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_LOAD_INIT_FILE(0),
|
||||
.C_LOAD_INIT_FILE(1),
|
||||
.C_MEM_TYPE(1),
|
||||
.C_MUX_PIPELINE_STAGES(0),
|
||||
.C_PRIM_TYPE(1),
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 13.2
|
||||
# Date: Tue Oct 18 18:45:53 2011
|
||||
# Date: Sun Oct 23 22:07:47 2011
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
@ -46,7 +46,7 @@ CSET axi_id_width=4
|
||||
CSET axi_slave_type=Memory_Slave
|
||||
CSET axi_type=AXI4_Full
|
||||
CSET byte_size=9
|
||||
CSET coe_file=no_coe_file_loaded
|
||||
CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes_cx4/cx4_e.coe
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=cx4_pgmrom
|
||||
CSET disable_collision_warnings=false
|
||||
@ -58,7 +58,7 @@ CSET enable_b=Always_Enabled
|
||||
CSET error_injection_type=Single_Bit_Error_Injection
|
||||
CSET fill_remaining_memory_locations=false
|
||||
CSET interface_type=Native
|
||||
CSET load_init_file=false
|
||||
CSET load_init_file=true
|
||||
CSET memory_type=Simple_Dual_Port_RAM
|
||||
CSET operating_mode_a=WRITE_FIRST
|
||||
CSET operating_mode_b=WRITE_FIRST
|
||||
@ -102,4 +102,4 @@ CSET write_width_b=16
|
||||
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 30264765
|
||||
# CRC: a9280b11
|
||||
|
||||
@ -50,8 +50,8 @@
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_pgmrom" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-18T20:46:37" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="794C12953A9C2D6BA0C9CD2CFBCA719F" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-24T00:08:31" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C14775871011A35EE55463DDAA37D8AF" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
@ -106,6 +106,10 @@ wire [7:0] CX4_SNES_DATA_OUT;
|
||||
wire [23:0] MAPPED_SNES_ADDR;
|
||||
wire ROM_ADDR0;
|
||||
|
||||
wire [23:0] cx4_datrom_data;
|
||||
wire [9:0] cx4_datrom_addr;
|
||||
wire cx4_datrom_we;
|
||||
|
||||
sd_dma snes_sd_dma(
|
||||
.CLK(CLK2),
|
||||
.SD_DAT(SD_DAT),
|
||||
@ -226,7 +230,11 @@ mcu_cmd snes_mcu_cmd(
|
||||
.mcu_rrq(MCU_RRQ),
|
||||
.mcu_wrq(MCU_WRQ),
|
||||
.mcu_rq_rdy(MCU_RDY),
|
||||
.use_msu1(use_msu1)
|
||||
.use_msu1(use_msu1),
|
||||
.cx4_datrom_addr_out(cx4_datrom_addr),
|
||||
.cx4_datrom_data_out(cx4_datrom_data),
|
||||
.cx4_datrom_we_out(cx4_datrom_we),
|
||||
.cx4_reset_out(cx4_reset)
|
||||
);
|
||||
|
||||
wire [7:0] DCM_STATUS;
|
||||
@ -285,9 +293,9 @@ cx4 snes_cx4 (
|
||||
.nRD(SNES_READ),
|
||||
.nWR(SNES_WRITE),
|
||||
.CLK(CLK2),
|
||||
.DATROM_DI(DATROM_DI),
|
||||
.DATROM_WE(DATROM_WE),
|
||||
.DATROM_ADDR(DATROM_ADDR),
|
||||
.DATROM_DI(cx4_datrom_data),
|
||||
.DATROM_WE(cx4_datrom_we),
|
||||
.DATROM_ADDR(cx4_datrom_addr),
|
||||
.BUS_DI(CX4_DINr),
|
||||
.BUS_ADDR(CX4_ADDR),
|
||||
.BUS_RRQ(CX4_RRQ),
|
||||
|
||||
@ -283,14 +283,14 @@
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="main_timesim.v" xil_pn:valueState="default"/>
|
||||
@ -311,7 +311,7 @@
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
@ -330,7 +330,7 @@
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
@ -338,8 +338,8 @@
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.main" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main/snes_cx4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.cx4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
|
||||
@ -361,13 +361,13 @@
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Search Directories for 'Include" xil_pn:value="../sd2snes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.main" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.cx4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
@ -405,7 +405,7 @@
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/ikari/prj/sd2snes/verilog/sd2snes_cx4/smartxplorer_results/run4/currentprojectnavigatorsettingsct4.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user