FPGA/Cx4: fully operational except reset vector area
This commit is contained in:
ikari
parent
8c76dfbeb6
commit
7643790fed
@ -42,12 +42,11 @@ parameter BUSY_DMA = 2'b01;
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parameter BUSY_CPU = 2'b10;
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wire datram_enable = CS & (ADDR[11:0] < 12'hc00);
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wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11001);
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wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11001);
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wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] < 5'b10011);
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wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] >= 5'b10011);
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wire vector_enable = CS & (ADDR[12:5] == 8'b11111011);
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wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11);
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wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000);
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wire debug_enable = CS & (&(ADDR[12:7]) && &(ADDR[5:4]));
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wire [7:0] DATRAM_DO;
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reg [7:0] MMIO_DOr;
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@ -55,15 +54,12 @@ wire [7:0] MMIO_DO;
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wire [7:0] STATUS_DO;
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wire [7:0] VECTOR_DO;
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wire [7:0] GPR_DO;
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wire [7:0] DEBUG_DO;
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reg [7:0] DEBUG_DOr;
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assign DO = datram_enable ? DATRAM_DO
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: mmio_enable ? MMIO_DO
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: status_enable ? STATUS_DO
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: vector_enable ? VECTOR_DO
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: gpr_enable ? GPR_DO
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: debug_enable ? DEBUG_DO
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: 8'h00;
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/* 0x1f40 - 0x1f52: MMIO
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@ -73,7 +69,7 @@ reg [15:0] cx4_mmio_dmalen;
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reg [23:0] cx4_mmio_dmatgt;
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reg cx4_mmio_cachepage;
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reg [23:0] cx4_mmio_pgmoff;
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reg [1:0] cx4_mmio_r1f4c;
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reg [1:0] cx4_mmio_savepage;
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reg [14:0] cx4_mmio_pgmpage;
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reg [7:0] cx4_mmio_pc;
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reg [7:0] cx4_mmio_r1f50;
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@ -88,9 +84,13 @@ reg [7:0] vector [31:0];
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reg [7:0] gpr [47:0];
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wire [47:0] cpu_mul_result;
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reg [14:0] cx4_mmio_pagemem[1:0];
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reg [23:0] const [15:0];
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reg [15:0] cachetag [1:0]; // 15: valid; 14-0: bank number
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reg [14:0] cachetag [1:0]; // 14-0: bank number
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reg [1:0] cachevalid;
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reg [14:0] cache_pgmpage;
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reg [14:0] cpu_cache_pgmpage;
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reg cache_cachepage;
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@ -105,14 +105,16 @@ initial begin
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cache_cachepage = 1'b0;
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cpu_cache_cachepage = 1'b0;
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cpu_cache_done = 1'b0;
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cachetag[0] = 16'h0000;
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cachetag[1] = 16'h0000;
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cachetag[0] = 14'h0000;
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cachetag[1] = 14'h0000;
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cachevalid = 2'b00;
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cx4_busy = 3'b000;
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cx4_mmio_pgmoff = 24'h000000;
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cx4_mmio_pgmpage = 15'h0000;
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cx4_mmio_dmasrc = 24'h000000;
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cx4_mmio_dmalen = 16'h0000;
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cx4_mmio_dmatgt = 24'h000000;
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cx4_mmio_savepage = 2'b00;
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const[0] = 24'h000000;
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const[1] = 24'hffffff;
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const[2] = 24'h00ff00;
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@ -144,7 +146,6 @@ assign MMIO_DO = MMIO_DOr;
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assign VECTOR_DO = vector [ADDR[4:0]];
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assign GPR_DO = gpr [ADDR[5:0]];
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assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0};
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assign DEBUG_DO = DEBUG_DOr;
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reg [7:0] DIr;
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always @(posedge CLK) DIr <= DI;
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@ -198,6 +199,11 @@ assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr | cpu_bus_rq;
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reg cpu_page;
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reg [14:0] cpu_p;
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reg [7:0] cpu_pc;
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reg [23:0] cpu_a;
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reg fl_n;
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reg fl_z;
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reg fl_c;
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reg cpu_go_en_r;
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initial cpu_go_en_r = 1'b0;
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@ -222,7 +228,7 @@ always @(posedge CLK) begin
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5'h09: MMIO_DOr <= cx4_mmio_pgmoff[7:0]; // 1f49
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5'h0a: MMIO_DOr <= cx4_mmio_pgmoff[15:8]; // 1f4a
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5'h0b: MMIO_DOr <= cx4_mmio_pgmoff[23:16]; // 1f4b
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5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_r1f4c}; // 1f4c
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5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_savepage}; // 1f4c
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5'h0d: MMIO_DOr <= cx4_mmio_pgmpage[7:0]; // 1f4d
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5'h0e: MMIO_DOr <= {1'b0, cx4_mmio_pgmpage[14:8]}; // 1f4e
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5'h0f: MMIO_DOr <= cx4_mmio_pc; // 1f4f
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@ -233,58 +239,47 @@ always @(posedge CLK) begin
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endcase
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end
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always @(posedge CLK) begin
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case(ADDR[3:0])
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4'h0: DEBUG_DOr <= cachetag[0][15:8]; // 1f40
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4'h1: DEBUG_DOr <= cachetag[0][7:0]; // 1f41
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4'h2: DEBUG_DOr <= cachetag[1][15:8]; // 1f42
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4'h3: DEBUG_DOr <= cachetag[1][7:0]; // 1f43
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4'h4: DEBUG_DOr <= cpu_page;
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4'h5: DEBUG_DOr <= cpu_p;
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4'h6: DEBUG_DOr <= cpu_pc;
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4'h7: DEBUG_DOr <= cx4_busy;
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4'h8: DEBUG_DOr <= cpu_page_stack[0];
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4'h9: DEBUG_DOr <= cpu_pc_stack[0];
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4'ha: DEBUG_DOr <= cpu_page_stack[1];
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4'hb: DEBUG_DOr <= cpu_pc_stack[1];
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4'hc: DEBUG_DOr <= cpu_page_stack[2];
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4'hd: DEBUG_DOr <= cpu_pc_stack[2];
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4'he: DEBUG_DOr <= cpu_page_stack[3];
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4'hf: DEBUG_DOr <= cpu_pc_stack[3];
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endcase
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end
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always @(posedge CLK) begin
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if(MMIO_WR_EN) begin
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case(ADDR[4:0])
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5'h00: cx4_mmio_dmasrc[7:0] <= DI; // 1f40
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5'h01: cx4_mmio_dmasrc[15:8] <= DI; // 1f41
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5'h02: cx4_mmio_dmasrc[23:16] <= DI; // 1f42
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5'h03: cx4_mmio_dmalen[7:0] <= DI; // 1f43
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5'h04: cx4_mmio_dmalen[15:8] <= DI; // 1f44
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5'h05: cx4_mmio_dmatgt[7:0] <= DI; // 1f45
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5'h06: cx4_mmio_dmatgt[15:8] <= DI; // 1f46
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5'h00: cx4_mmio_dmasrc[7:0] <= DIr; // 1f40
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5'h01: cx4_mmio_dmasrc[15:8] <= DIr; // 1f41
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5'h02: cx4_mmio_dmasrc[23:16] <= DIr; // 1f42
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5'h03: cx4_mmio_dmalen[7:0] <= DIr; // 1f43
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5'h04: cx4_mmio_dmalen[15:8] <= DIr; // 1f44
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5'h05: cx4_mmio_dmatgt[7:0] <= DIr; // 1f45
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5'h06: cx4_mmio_dmatgt[15:8] <= DIr; // 1f46
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5'h07: begin
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cx4_mmio_dmatgt[23:16] <= DI; // 1f47
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cx4_mmio_dmatgt[23:16] <= DIr; // 1f47
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DMA_TRIG_ENr <= 1'b1;
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end
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5'h08: begin
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cx4_mmio_cachepage <= DI[0]; // 1f48
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cx4_mmio_cachepage <= DIr[0]; // 1f48
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CACHE_TRIG_ENr <= 1'b1;
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end
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5'h09: cx4_mmio_pgmoff[7:0] <= DI; // 1f49
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5'h0a: cx4_mmio_pgmoff[15:8] <= DI; // 1f4a
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5'h0b: cx4_mmio_pgmoff[23:16] <= DI; // 1f4b
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5'h0c: cx4_mmio_r1f4c <= DI[1:0]; // 1f4c
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5'h0d: cx4_mmio_pgmpage[7:0] <= DI; // 1f4d
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5'h0e: cx4_mmio_pgmpage[14:8] <= DI[6:0]; // 1f4e
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5'h09: cx4_mmio_pgmoff[7:0] <= DIr; // 1f49
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5'h0a: cx4_mmio_pgmoff[15:8] <= DIr; // 1f4a
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5'h0b: cx4_mmio_pgmoff[23:16] <= DIr; // 1f4b
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5'h0c: begin
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cx4_mmio_savepage <= DIr[1:0];
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if(DIr[0]) cx4_mmio_pagemem[0] <= cx4_mmio_pgmpage;
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if(DIr[1]) cx4_mmio_pagemem[1] <= cx4_mmio_pgmpage;
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end
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5'h0d: cx4_mmio_pgmpage[7:0] <= DIr; // 1f4d
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5'h0e: cx4_mmio_pgmpage[14:8] <= DIr[6:0]; // 1f4e
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5'h0f: begin
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cx4_mmio_pc <= DI; // 1f4f
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cx4_mmio_pc <= DIr; // 1f4f
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if(cx4_mmio_savepage[0]
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&& cx4_mmio_pagemem[0] == cx4_mmio_pgmpage)
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cx4_mmio_cachepage <= 1'b0;
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else if(cx4_mmio_savepage[1]
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&& cx4_mmio_pagemem[1] == cx4_mmio_pgmpage)
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cx4_mmio_cachepage <= 1'b1;
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cpu_go_en_r <= 1'b1;
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end
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5'h10: cx4_mmio_r1f50 <= DI & 8'h77; // 1f50
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5'h11: cx4_mmio_r1f51 <= DI[0]; // 1f51
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5'h12: cx4_mmio_r1f52 <= DI[0]; // 1f52
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5'h10: cx4_mmio_r1f50 <= DIr & 8'h77; // 1f50
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5'h11: cx4_mmio_r1f51 <= DIr[0]; // 1f51
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5'h12: cx4_mmio_r1f52 <= DIr[0]; // 1f52
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endcase
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end else begin
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CACHE_TRIG_ENr <= 1'b0;
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@ -294,7 +289,7 @@ always @(posedge CLK) begin
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end
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always @(posedge CLK) begin
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if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DI;
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if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DIr;
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end
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reg [4:0] CACHE_ST;
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@ -333,14 +328,14 @@ always @(posedge CLK) begin
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case(CACHE_ST)
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ST_CACHE_IDLE: begin
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if(CACHE_TRIG_EN
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& (~cachetag[cx4_mmio_cachepage][15]
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| |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) begin
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& (~cachevalid[cx4_mmio_cachepage]
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| |(cachetag[cx4_mmio_cachepage] ^ cx4_mmio_pgmpage))) begin
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CACHE_ST <= ST_CACHE_START;
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cache_pgmpage <= cx4_mmio_pgmpage;
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cache_cachepage <= cx4_mmio_cachepage;
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end else if(cpu_cache_en
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& (~cachetag[~cpu_page][15]
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| |(cachetag[~cpu_page][14:0] ^ cpu_p))) begin
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& (~cachevalid[~cpu_page]
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| |(cachetag[~cpu_page] ^ cpu_p))) begin
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CACHE_ST <= ST_CACHE_START;
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cache_pgmpage <= cpu_p;
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cache_cachepage <= ~cpu_page;
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@ -370,7 +365,8 @@ always @(posedge CLK) begin
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cx4_pgmrom_addr <= cx4_pgmrom_addr + 1;
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if(cache_count == 9'h1ff) begin
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cx4_busy[BUSY_CACHE] <= 1'b0;
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cachetag[cache_cachepage] <= {1'b1,cache_pgmpage};
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cachetag[cache_cachepage] <= cache_pgmpage;
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cachevalid[cache_cachepage] <= 1'b1;
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CACHE_ST <= ST_CACHE_IDLE;
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end else begin
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CACHE_BUS_RRQr <= 1'b1;
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@ -439,7 +435,6 @@ reg [2:0] cpu_sp;
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initial cpu_sp = 3'b000;
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wire [15:0] cpu_op_w;
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reg [15:0] cpu_op;
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reg [23:0] cpu_a;
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reg [23:0] cpu_busdata;
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reg [23:0] cpu_romdata;
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reg [23:0] cpu_ramdata;
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@ -455,9 +450,6 @@ reg [23:0] cpu_dummy;
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reg [23:0] cpu_tmp;
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reg [23:0] cpu_sa; // tmp register for shifted accumulator
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reg fl_n;
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reg fl_z;
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reg fl_c;
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wire [9:0] cx4_datrom_addr = cpu_a[9:0];
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wire [23:0] cx4_datrom_do;
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@ -499,19 +491,24 @@ reg op_call;
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reg op_jump;
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reg condtrue;
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/* XXX DEBUG */
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reg [23:0] dbg_cnt;
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initial dbg_cnt = 24'b0;
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always @(posedge CLK) dbg_cnt <= dbg_cnt + 1;
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wire step_enable = 1'b1;
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always @(posedge CLK) begin
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if(cpu_go_en_r) cx4_busy[BUSY_CPU] <= 1'b1;
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else if((op == OP_HLT) && step_enable) cx4_busy[BUSY_CPU] <= 1'b0;
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else if(op == OP_HLT) cx4_busy[BUSY_CPU] <= 1'b0;
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end
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always @(posedge CLK) begin
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if(step_enable | cpu_go_en_r) begin
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case(op_sa)
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2'b00: cpu_sa <= cpu_a;
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2'b01: cpu_sa <= cpu_a << 1;
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2'b10: cpu_sa <= cpu_a << 8;
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2'b11: cpu_sa <= cpu_a << 16;
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endcase
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end
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reg jp_docache;
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initial jp_docache = 1'b0;
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always @(posedge CLK) begin
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case(CPU_STATE)
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ST_CPU_IDLE: begin
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if(cpu_go_en_r) begin
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@ -537,6 +534,10 @@ if(step_enable | cpu_go_en_r) begin
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2'b00: condtrue <= fl_c;
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2'b01: condtrue <= fl_n;
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endcase
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if(op_p && !jp_docache) begin
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jp_docache <= 1'b1;
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cpu_cache_en <= 1'b1;
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end
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end
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OP_SKIP: begin
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case(cpu_op[9:8])
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@ -562,14 +563,6 @@ if(step_enable | cpu_go_en_r) begin
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gpr[op_param[3:0]*3]};
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default: cpu_idb <= 24'b0;
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endcase
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if(op==OP_ALU || op==OP_CMP) begin
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case(op_sa)
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2'b00: cpu_sa <= cpu_a;
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2'b01: cpu_sa <= cpu_a << 1;
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2'b10: cpu_sa <= cpu_a << 8;
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2'b11: cpu_sa <= cpu_a << 16;
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endcase
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end
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end
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OP_ST: begin
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cpu_idb <= cpu_a;
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@ -615,9 +608,12 @@ if(step_enable | cpu_go_en_r) begin
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end
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ST_CPU_1: begin
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CPU_STATE <= ST_CPU_2;
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condtrue <= 1'b0;
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case(op)
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OP_JP: begin
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if(!cx4_busy[BUSY_CACHE]) begin
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cpu_cache_en <= 1'b0;
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if(!cpu_cache_en && !cx4_busy[BUSY_CACHE]) begin
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jp_docache <= 1'b0;
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if(condtrue) begin
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if(op_call) begin
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cpu_page_stack[cpu_sp] <= cpu_page;
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@ -659,10 +655,8 @@ if(step_enable | cpu_go_en_r) begin
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end
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OP_ST, OP_SWP: begin
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casex(op_param)
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// 8'h00: cpu_a <= cpu_idb;
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8'h01: cpu_acch <= cpu_idb;
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8'h02: cpu_accl <= cpu_idb;
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// 8'h03: cpu_busdata <= cpu_idb;
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8'h08: cpu_romdata <= cpu_idb;
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8'h0c: cpu_ramdata <= cpu_idb;
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8'h13: cpu_busaddr <= cpu_idb;
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@ -707,8 +701,8 @@ if(step_enable | cpu_go_en_r) begin
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5'b10110: cpu_alu_res <= cpu_sa & cpu_idb;
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5'b10111: cpu_alu_res <= cpu_sa | cpu_idb;
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5'b11000: cpu_alu_res <= cpu_a >> cpu_idb;
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5'b11001: cpu_alu_res <= $signed(cpu_a) >>> cpu_idb;
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5'b11010: {cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb;
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5'b11001: cpu_alu_res <= ($signed(cpu_a)) >>> cpu_idb;
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5'b11010: {cpu_dummy, cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb;
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5'b11011: cpu_alu_res <= cpu_a << cpu_idb;
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endcase
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end
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@ -717,12 +711,6 @@ if(step_enable | cpu_go_en_r) begin
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ST_CPU_3: begin
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CPU_STATE <= ST_CPU_0;
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case(op)
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OP_LD: begin
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casex(cpu_op[11:8])
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4'b0x11: cpu_cache_en <= 1'b1;
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4'b1100: cpu_cache_en <= 1'b1;
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endcase
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end
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OP_BUS: cpu_busaddr <= cpu_busaddr + 1;
|
||||
OP_WRRAM: cx4_cpu_datram_we <= 1'b0;
|
||||
OP_CMP: begin
|
||||
@ -803,12 +791,14 @@ if(step_enable | cpu_go_en_r) begin
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg[2:0] BUSRD_STATE;
|
||||
parameter ST_BUSRD_IDLE = 2'b01;
|
||||
parameter ST_BUSRD_WAIT = 2'b10;
|
||||
parameter ST_BUSRD_IDLE = 3'b001;
|
||||
parameter ST_BUSRD_WAIT = 3'b010;
|
||||
parameter ST_BUSRD_END = 3'b100;
|
||||
initial BUSRD_STATE = ST_BUSRD_IDLE;
|
||||
reg cpu_bus_rq2;
|
||||
always @(posedge CLK) cpu_bus_rq2 <= cpu_bus_rq;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CPU_STATE == ST_CPU_2
|
||||
@ -818,13 +808,15 @@ always @(posedge CLK) begin
|
||||
else begin
|
||||
case(BUSRD_STATE)
|
||||
ST_BUSRD_IDLE: begin
|
||||
if(cpu_bus_rq) begin
|
||||
if(cpu_bus_rq2) begin
|
||||
BUSRD_STATE <= ST_BUSRD_WAIT;
|
||||
end
|
||||
end
|
||||
ST_BUSRD_WAIT: begin
|
||||
if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_IDLE;
|
||||
if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_END;
|
||||
else BUSRD_STATE <= ST_BUSRD_WAIT;
|
||||
end
|
||||
ST_BUSRD_END: begin
|
||||
if(~cpu_busaddr[22]) cpu_busdata <= BUS_DI;
|
||||
else cpu_busdata <= 8'h00;
|
||||
end
|
||||
@ -841,7 +833,7 @@ always @(posedge CLK) begin
|
||||
gpr[op_param[3:0]*3+1] <= cpu_idb[15:8];
|
||||
gpr[op_param[3:0]*3] <= cpu_idb[7:0];
|
||||
end
|
||||
else if(GPR_WR_EN) gpr[ADDR[5:0]] <= DI;
|
||||
else if(GPR_WR_EN) gpr[ADDR[5:0]] <= DIr;
|
||||
end
|
||||
|
||||
/***************************
|
||||
@ -861,7 +853,7 @@ cx4_datram cx4_datram (
|
||||
.clka(CLK), // input clka
|
||||
.wea(DATRAM_WR_EN), // input [0 : 0] wea
|
||||
.addra(ADDR[11:0]), // input [11 : 0] addra
|
||||
.dina(DI), // input [7 : 0] dina
|
||||
.dina(DIr), // input [7 : 0] dina
|
||||
.douta(DATRAM_DO), // output [7 : 0] douta
|
||||
.clkb(CLK), // input clkb
|
||||
.web(cx4_datram_we), // input [0 : 0] web
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 13.2
|
||||
# Date: Mon Oct 24 22:04:01 2011
|
||||
# Date: Fri Oct 28 08:30:26 2011
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
@ -49,7 +49,7 @@ CSET multtype=Parallel_Multiplier
|
||||
CSET optgoal=Speed
|
||||
CSET outputwidthhigh=47
|
||||
CSET outputwidthlow=0
|
||||
CSET pipestages=3
|
||||
CSET pipestages=2
|
||||
CSET portatype=Signed
|
||||
CSET portawidth=24
|
||||
CSET portbtype=Signed
|
||||
@ -65,4 +65,4 @@ CSET zerodetect=false
|
||||
MISC pkg_timestamp=2011-06-21T06:26:54.000Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: fd22ef14
|
||||
# CRC: efe4d30e
|
||||
|
||||
@ -50,8 +50,8 @@
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_mul" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-25T00:04:25" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="384E11781B113D7487AFCF863F4DA087" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-28T10:30:58" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5048768FEE0CA0B8A63A1C80E928CC84" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
@ -299,7 +299,8 @@ cx4 snes_cx4 (
|
||||
.BUS_DI(CX4_DINr),
|
||||
.BUS_ADDR(CX4_ADDR),
|
||||
.BUS_RRQ(CX4_RRQ),
|
||||
.BUS_RDY(CX4_RDY)
|
||||
.BUS_RDY(CX4_RDY),
|
||||
.cx4_active(cx4_active)
|
||||
);
|
||||
|
||||
parameter MODE_SNES = 1'b0;
|
||||
@ -359,7 +360,7 @@ always @(posedge CLK2) begin
|
||||
end
|
||||
|
||||
wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE;
|
||||
wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART;
|
||||
wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART & ~cx4_active;
|
||||
|
||||
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
|
||||
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
|
||||
@ -393,7 +394,7 @@ always @(posedge CLK2) begin
|
||||
if(CX4_RRQ) begin
|
||||
CX4_RD_PENDr <= 1'b1;
|
||||
RQ_CX4_RDYr <= 1'b0;
|
||||
end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin
|
||||
end else if(STATE == ST_CX4_RD_END) begin
|
||||
CX4_RD_PENDr <= 1'b0;
|
||||
RQ_CX4_RDYr <= 1'b1;
|
||||
end
|
||||
@ -402,21 +403,24 @@ end
|
||||
reg snes_wr_cycle;
|
||||
|
||||
always @(posedge CLK2) begin
|
||||
if(SNES_cycle_start & IS_CART) begin
|
||||
if(SNES_cycle_start & IS_CART & ~cx4_active) begin
|
||||
STATE <= ST_SNES_RD_ADDR;
|
||||
end else if(SNES_WR_start & IS_CART) begin
|
||||
end else if(SNES_WR_start & IS_CART & ~cx4_active) begin
|
||||
STATE <= ST_SNES_WR_ADDR;
|
||||
end else begin
|
||||
case(STATE)
|
||||
ST_IDLE: begin
|
||||
ROM_ADDRr <= MAPPED_SNES_ADDR;
|
||||
if(CX4_RRQ | CX4_RD_PENDr) begin
|
||||
ROM_ADDRr <= CX4_ADDR;
|
||||
if(CX4_RD_PENDr) begin
|
||||
STATE <= ST_CX4_RD_WAIT;
|
||||
ROM_ADDRr <= CX4_ADDR;
|
||||
ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
|
||||
end
|
||||
else if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
|
||||
else if(~cx4_active) begin
|
||||
if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
|
||||
else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
|
||||
else STATE <= ST_IDLE;
|
||||
end
|
||||
else STATE <= ST_IDLE;
|
||||
end
|
||||
ST_SNES_RD_ADDR: begin
|
||||
@ -518,9 +522,7 @@ always @(posedge CLK2) begin
|
||||
end
|
||||
ST_CX4_RD_WAIT: begin
|
||||
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
||||
if(ST_MEM_DELAYr == 4'h0) begin
|
||||
STATE <= ST_IDLE;
|
||||
end
|
||||
if(ST_MEM_DELAYr == 4'h0) STATE <= ST_CX4_RD_END;
|
||||
else STATE <= ST_CX4_RD_WAIT;
|
||||
if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0];
|
||||
else CX4_DINr <= ROM_DATA[15:8];
|
||||
|
||||
@ -238,7 +238,7 @@
|
||||
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
@ -320,7 +320,7 @@
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="30" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
@ -366,8 +366,8 @@
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user