misc stuff, preparation hack for autonomous clock (needs to be reverted)

verilog/sd2snes/dcm.v

@@ -21,6 +21,7 @@
 module my_dcm (
          input CLKIN,
          output CLKFX,
+         output CLK2X,
          output LOCKED,
          input CLKFB,
          input RST,
@@ -37,18 +38,18 @@ module my_dcm (
       .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                           //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
       .CLKFX_DIVIDE(1),   // Can be any integer from 1 to 32
-      .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
+      .CLKFX_MULTIPLY(7), // Can be any integer from 2 to 32
       .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
       .CLKIN_PERIOD(47.000),  // Specify period of input clock
       .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
       .CLK_FEEDBACK("1X"),  // Specify clock feedback of NONE, 1X or 2X
-      .DESKEW_ADJUST("SOURCE_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                             //   an integer from 0 to 15
       .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
       .DLL_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for DLL
       .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
-      .FACTORY_JF(16'hC080),   // FACTORY JF values
-//      .LOC("DCM_X0Y0"),
+      .FACTORY_JF(16'hFFFF),   // FACTORY JF values
+//      .LOC("X0Y0"),
       .PHASE_SHIFT(0),     // Amount of fixed phase shift from -255 to 255
       .STARTUP_WAIT("TRUE")   // Delay configuration DONE until DCM LOCK, TRUE/FALSE
    ) DCM_inst (

verilog/sd2snes/main.ucf

@@ -1,5 +1,5 @@
 NET "CLKIN" TNM_NET = CLKIN;
-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.477 MHz HIGH 50 %;
+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 12.288 MHz HIGH 50 %;
 NET "AVR_ENA" IOSTANDARD = LVCMOS33;
 NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33;
 NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33;

verilog/sd2snes/main.v

@@ -109,7 +109,9 @@ avr_cmd snes_avr_cmd(
     .rom_mask_out(ROM_MASK)
 );
 
-wire [7:0] DCM_STATUS;
+//wire [7:0] DCM_STATUS;
+
+// dcm1: dfs 4x
 my_dcm snes_dcm(.CLKIN(CLKIN),
                   .CLKFX(CLK2),
                   .LOCKED(DCM_LOCKED),
@@ -118,16 +120,20 @@ my_dcm snes_dcm(.CLKIN(CLKIN),
                   .CLKFB(CLKFB),
                   .CLK0(CLK0)
                 );
-reg DCM_RSTr;
-assign DCM_RST = DCM_RSTr;
+
+dcm_srl16 snes_dcm_resetter(.CLK(CLKIN),
+                              .Q(DCM_RST)
+                           );
+                           
 assign CLKFB = CLK0;
-wire DCM_FX_STOPPED = DCM_STATUS[2];
-always @(posedge CLKIN) begin
-   if(DCM_FX_STOPPED)
-      DCM_RSTr <= 1'b1;
-   else
-      DCM_RSTr <= 1'b0;
-end
+
+//wire DCM_FX_STOPPED = DCM_STATUS[2];
+//always @(posedge CLKIN) begin
+//   if(DCM_FX_STOPPED)
+//      DCM_RSTr <= 1'b1;
+//   else
+//      DCM_RSTr <= 1'b0;
+//end
 
 /*reg DO_DCM_RESET, DCM_RESETTING;
 reg DCM_RSTr;

verilog/sd2snes/sd2snes.xise

@@ -65,6 +65,10 @@
       <association xil_pn:name="BehavioralSimulation"/>
       <association xil_pn:name="Implementation"/>
     </file>
+    <file xil_pn:name="dcm_srl16.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation"/>
+    </file>
   </files>
 
   <properties>
@@ -73,7 +77,9 @@
     <property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
     <property xil_pn:name="Device" xil_pn:value="xc3s200"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="6"/>
     <property xil_pn:name="Enable BitStream Compression" xil_pn:value="true"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="3"/>
     <property xil_pn:name="Extra Effort" xil_pn:value="Normal"/>
     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal"/>
     <property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
@@ -94,6 +100,7 @@
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
     <property xil_pn:name="Project Description" xil_pn:value="sd2snes"/>
     <property xil_pn:name="Register Duplication" xil_pn:value="On"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="5"/>
     <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High"/>
     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|main_tf2"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Module|main_tf2"/>