firmware: SPC player (necronomfive)
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11bf7ffd5b
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8c2f74d8cd
@ -194,6 +194,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
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switch(type) {
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switch(type) {
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case TYPE_IPS:
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case TYPE_IPS:
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case TYPE_SMC:
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case TYPE_SMC:
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case TYPE_SPC:
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/* file_open_by_filinfo(&fno);
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/* file_open_by_filinfo(&fno);
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if(file_res){
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if(file_res){
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printf("ZOMG NOOOO %d\n", file_res);
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printf("ZOMG NOOOO %d\n", file_res);
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@ -271,18 +272,14 @@ SNES_FTYPE determine_filetype(char* filename) {
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) {
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) {
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return TYPE_SMC;
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return TYPE_SMC;
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}
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}
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if( (!strcasecmp(ext+1, "IPS"))
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/* if( (!strcasecmp(ext+1, "IPS"))
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||(!strcasecmp(ext+1, "UPS"))
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||(!strcasecmp(ext+1, "UPS"))
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) {
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) {
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return TYPE_IPS;
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return TYPE_IPS;
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}
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/* later
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if(!strcasecmp_P(ext+1, PSTR("SRM"))) {
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return TYPE_SRM;
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}
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if(!strcasecmp_P(ext+1, PSTR("SPC"))) {
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return TYPE_SPC;
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}*/
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}*/
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if(!strcasecmp(ext+1, "SPC")) {
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return TYPE_SPC;
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}
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return TYPE_UNKNOWN;
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return TYPE_UNKNOWN;
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}
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}
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15
src/main.c
15
src/main.c
@ -265,6 +265,21 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
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sysinfo_loop();
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sysinfo_loop();
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cmd=0; /* stay in menu loop */
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cmd=0; /* stay in menu loop */
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break;
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break;
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case SNES_CMD_LOADSPC:
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/* load SPC file */
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get_selected_name(file_lfn);
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printf("Selected name: %s\n", file_lfn);
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filesize = load_spc(file_lfn, SRAM_SPC_DATA_ADDR, SRAM_SPC_HEADER_ADDR);
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cmd=0; /* stay in menu loop */
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break;
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case SNES_CMD_RESET:
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/* process RESET request from SNES */
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printf("RESET requested by SNES\n");
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snes_reset(1);
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sleep_ms(1);
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snes_reset(0);
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cmd=0; /* stay in menu loop */
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break;
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case SNES_CMD_LOADLAST:
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case SNES_CMD_LOADLAST:
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cfg_get_last_game(file_lfn);
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cfg_get_last_game(file_lfn);
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printf("Selected name: %s\n", file_lfn);
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printf("Selected name: %s\n", file_lfn);
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65
src/memory.c
65
src/memory.c
@ -299,6 +299,71 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
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return (uint32_t)filesize;
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return (uint32_t)filesize;
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}
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}
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uint32_t load_spc(uint8_t* filename, uint32_t spc_data_addr, uint32_t spc_header_addr) {
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DWORD filesize;
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UINT bytes_read;
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uint8_t data;
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UINT j;
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printf("%s\n", filename);
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file_open(filename, FA_READ); /* Open SPC file */
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if(file_res) return 0;
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filesize = file_handle.fsize;
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if (filesize < 65920) { /* At this point, we care about filesize only */
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file_close(); /* since SNES decides if it is an SPC file */
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sram_writebyte(0, spc_header_addr); /* If file is too small, destroy previous SPC header */
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return 0;
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}
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set_mcu_addr(spc_data_addr);
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f_lseek(&file_handle, 0x100L); /* Load 64K data segment */
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for(;;) {
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bytes_read = file_read();
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if (file_res || !bytes_read) break;
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FPGA_SELECT();
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FPGA_TX_BYTE(0x98);
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for(j=0; j<bytes_read; j++) {
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FPGA_TX_BYTE(file_buf[j]);
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FPGA_WAIT_RDY();
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}
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FPGA_DESELECT();
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}
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file_close();
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file_open(filename, FA_READ); /* Reopen SPC file to reset file_getc state*/
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set_mcu_addr(spc_header_addr);
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f_lseek(&file_handle, 0x0L); /* Load 256 bytes header */
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FPGA_SELECT();
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FPGA_TX_BYTE(0x98);
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for (j = 0; j < 256; j++) {
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data = file_getc();
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FPGA_TX_BYTE(data);
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FPGA_WAIT_RDY();
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}
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FPGA_DESELECT();
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file_close();
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file_open(filename, FA_READ); /* Reopen SPC file to reset file_getc state*/
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set_mcu_addr(spc_header_addr+0x100);
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f_lseek(&file_handle, 0x10100L); /* Load 128 DSP registers */
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FPGA_SELECT();
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FPGA_TX_BYTE(0x98);
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for (j = 0; j < 128; j++) {
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data = file_getc();
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FPGA_TX_BYTE(data);
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FPGA_WAIT_RDY();
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}
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FPGA_DESELECT();
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file_close(); /* Done ! */
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return (uint32_t)filesize;
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}
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uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr) {
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uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr) {
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set_mcu_addr(base_addr);
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set_mcu_addr(base_addr);
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UINT bytes_read;
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UINT bytes_read;
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@ -34,14 +34,18 @@
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#define SRAM_SAVE_ADDR (0xE00000L)
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#define SRAM_SAVE_ADDR (0xE00000L)
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#define SRAM_MENU_ADDR (0xE00000L)
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#define SRAM_MENU_ADDR (0xE00000L)
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#define SRAM_DB_ADDR (0xE40000L)
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#define SRAM_DIR_ADDR (0xE10000L)
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#define SRAM_DIR_ADDR (0xE10000L)
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#define SRAM_DB_ADDR (0xE40000L)
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#define SRAM_SPC_DATA_ADDR (0xFD0000L)
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#define SRAM_SPC_HEADER_ADDR (0xFE0000L)
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#define SRAM_MENU_SAVE_ADDR (0xFF0000L)
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#define SRAM_CMD_ADDR (0xFF1000L)
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#define SRAM_CMD_ADDR (0xFF1000L)
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#define SRAM_PARAM_ADDR (0xFF1004L)
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#define SRAM_PARAM_ADDR (0xFF1004L)
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#define SRAM_STATUS_ADDR (0xFF1100L)
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#define SRAM_STATUS_ADDR (0xFF1100L)
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#define SRAM_SYSINFO_ADDR (0xFF1200L)
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#define SRAM_SYSINFO_ADDR (0xFF1200L)
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#define SRAM_LASTGAME_ADDR (0xFF1420L)
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#define SRAM_LASTGAME_ADDR (0xFF1420L)
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#define SRAM_MENU_SAVE_ADDR (0xFF0000L)
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#define SRAM_SCRATCHPAD (0xFFFF00L)
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#define SRAM_SCRATCHPAD (0xFFFF00L)
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#define SRAM_DIRID (0xFFFFF0L)
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#define SRAM_DIRID (0xFFFFF0L)
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#define SRAM_RELIABILITY_SCORE (0x100)
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#define SRAM_RELIABILITY_SCORE (0x100)
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@ -50,6 +54,7 @@
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#define LOADROM_WITH_RESET (2)
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#define LOADROM_WITH_RESET (2)
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uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags);
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uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags);
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uint32_t load_spc(uint8_t* filename, uint32_t spc_data_addr, uint32_t spc_header_addr);
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uint32_t load_sram(uint8_t* filename, uint32_t base_addr);
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uint32_t load_sram(uint8_t* filename, uint32_t base_addr);
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uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr);
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uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr);
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uint32_t load_sram_rle(uint8_t* filename, uint32_t base_addr);
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uint32_t load_sram_rle(uint8_t* filename, uint32_t base_addr);
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@ -31,10 +31,12 @@
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#define SNES_CMD_SETRTC (2)
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#define SNES_CMD_SETRTC (2)
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#define SNES_CMD_SYSINFO (3)
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#define SNES_CMD_SYSINFO (3)
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#define SNES_CMD_LOADLAST (4)
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#define SNES_CMD_LOADLAST (4)
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#define SNES_CMD_LOADSPC (5)
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#define SNES_CMD_RESET (6)
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#define MENU_ERR_OK (0)
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#define MENU_ERR_OK (0)
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#define MENU_ERR_NODSP (1)
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#define MENU_ERR_NODSP (1)
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#define MENU_ERR_NOBSX (2)
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#define MENU_ERR_NOBSX (2)
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uint8_t crc_valid;
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uint8_t crc_valid;
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