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Firmware: region override (patch register $213f)

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This commit is contained in:
ikari 2012-01-14 01:10:13 +01:00
parent 3506cb0ba2
commit afc26397b1
4 changed files with 18 additions and 3 deletions
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11
src/fpga_spi.c
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@ -80,6 +80,7 @@
EB - put DSP into reset EB - put DSP into reset
EC - release DSP from reset EC - release DSP from reset
ED - set feature enable bits (see below) ED - set feature enable bits (see below)
EE - set $213f override value (0=NTSC, 1=PAL)
F0 - receive test token (to see if FPGA is alive) F0 - receive test token (to see if FPGA is alive)
F1 - receive status (16bit, MSB first), see below F1 - receive status (16bit, MSB first), see below
@ -117,7 +118,7 @@
7 - 7 -
6 - 6 -
5 - 5 -
4 - 4 enable $213F override
3 enable MSU1 registers 3 enable MSU1 registers
2 enable SRTC registers 2 enable SRTC registers
1 enable ST0010 mapping 1 enable ST0010 mapping
@ -411,3 +412,11 @@ void fpga_set_features(uint8_t feat) {
FPGA_DESELECT(); FPGA_DESELECT();
} }
void fpga_set_213f(uint8_t data) {
printf("set 213f: %d\n", data);
FPGA_SELECT();
FPGA_TX_BYTE(0xee);
FPGA_TX_BYTE(data);
FPGA_DESELECT();
}

5
src/fpga_spi.h
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@ -50,12 +50,14 @@
#define FPGA_SPI_FAST() spi_set_speed(SPI_SPEED_FPGA_FAST) #define FPGA_SPI_FAST() spi_set_speed(SPI_SPEED_FPGA_FAST)
#define FPGA_SPI_SLOW() spi_set_speed(SPI_SPEED_FPGA_SLOW) #define FPGA_SPI_SLOW() spi_set_speed(SPI_SPEED_FPGA_SLOW)
#define FEAT_CX4 (1 << 4) #define FEAT_213F (1 << 4)
#define FEAT_MSU1 (1 << 3) #define FEAT_MSU1 (1 << 3)
#define FEAT_SRTC (1 << 2) #define FEAT_SRTC (1 << 2)
#define FEAT_ST0010 (1 << 1) #define FEAT_ST0010 (1 << 1)
#define FEAT_DSPX (1 << 0) #define FEAT_DSPX (1 << 0)
#define FEAT_CX4 (1 << 4)
#define FPGA_WAIT_RDY() do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0) #define FPGA_WAIT_RDY() do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0)
void fpga_spi_init(void); void fpga_spi_init(void);
@ -90,4 +92,5 @@ void fpga_write_dspx_pgm(uint32_t data);
void fpga_write_dspx_dat(uint16_t data); void fpga_write_dspx_dat(uint16_t data);
void fpga_dspx_reset(uint8_t reset); void fpga_dspx_reset(uint8_t reset);
void fpga_set_features(uint8_t feat); void fpga_set_features(uint8_t feat);
void fpga_set_213f(uint8_t data);
#endif #endif

2
src/memory.c
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@ -281,7 +281,9 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
printf("done\n"); printf("done\n");
romprops.fpga_features |= FEAT_SRTC; romprops.fpga_features |= FEAT_SRTC;
romprops.fpga_features |= FEAT_213F;
fpga_set_213f(romprops.region);
fpga_set_features(romprops.fpga_features); fpga_set_features(romprops.fpga_features);
if(flags & LOADROM_WITH_RESET) { if(flags & LOADROM_WITH_RESET) {

3
src/smc.h
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@ -66,10 +66,11 @@ typedef struct _snes_romprops {
const uint8_t* dsp_fw; /* DSP (NEC / Hitachi) ROM filename */ const uint8_t* dsp_fw; /* DSP (NEC / Hitachi) ROM filename */
const uint8_t* fpga_conf; /* FPGA config file to load (default: base) */ const uint8_t* fpga_conf; /* FPGA config file to load (default: base) */
uint8_t has_dspx; /* DSP[1-4] presence flag */ uint8_t has_dspx; /* DSP[1-4] presence flag */
uint8_t has_st0010; /* st0010 presence flag (additional to dspx)*/ uint8_t has_st0010; /* st0010 presence flag (additional to dspx) */
uint8_t has_msu1; /* MSU1 presence flag */ uint8_t has_msu1; /* MSU1 presence flag */
uint8_t has_cx4; /* CX4 presence flag */ uint8_t has_cx4; /* CX4 presence flag */
uint8_t fpga_features; /* feature/peripheral enable bits*/ uint8_t fpga_features; /* feature/peripheral enable bits*/
uint8_t region; /* game region (derived from destination code) */
snes_header_t header; /* original header from ROM image */ snes_header_t header; /* original header from ROM image */
} snes_romprops_t; } snes_romprops_t;