new SRAM access (SPI)
This commit is contained in:
ikari
parent
784b47d7ed
commit
ceb5bec774
@ -62,8 +62,8 @@
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# error Unknown chip!
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# endif
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# define SD_CHANGE_VECT INT0_vect
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# define SDCARD_WP (PIND & _BV(PD6))
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# define SDCARD_WP_SETUP() do { DDRD &= ~ _BV(PD6); PORTD |= _BV(PD6); } while(0)
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# define SDCARD_WP (PINB & _BV(PB3))
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# define SDCARD_WP_SETUP() do { DDRB &= ~ _BV(PB3); PORTB |= _BV(PB3); } while(0)
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# define SD_CHANGE_ICR MCUCR
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# define SD_SUPPLY_VOLTAGE (1L<<21)
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# define DEVICE_SELECT (8+!(PINA & _BV(PA2))+2*!(PINA & _BV(PA3)))
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10
src/fpga.c
10
src/fpga.c
@ -200,6 +200,12 @@ void set_avr_mapper(uint8_t val) {
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}
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void set_avr_bank(uint8_t val) {
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PORTB &= 0xFC;
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PORTB |= val&0x03;
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SPI_SS_HIGH();
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FPGA_SS_LOW();
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spiTransferByte(0x00); // SET ADDRESS
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spiTransferByte(val * 0x20); // select chip
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spiTransferByte(0x00); // select chip
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spiTransferByte(0x00); // select chip
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FPGA_SS_HIGH();
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SPI_SS_LOW();
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}
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@ -46,3 +46,12 @@ void toggle_busy_led(void) {
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PORTB &= ~_BV(PB1);
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DDRB ^= _BV(PB1);
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}
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void set_busy_led(uint8_t state) {
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PORTB &= ~_BV(PB1);
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if(state) {
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DDRB |= _BV(PB1);
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} else {
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DDRB &= ~_BV(PB1);
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}
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}
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11
src/led.h
11
src/led.h
@ -40,16 +40,7 @@ extern volatile uint8_t led_state;
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/* Update the LEDs to match the buffer state */
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void update_leds(void);
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void toggle_busy_led(void);
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void set_busy_led(uint8_t);
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/* Wrapped in do..while to avoid "ambigious else" warnings */
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#ifdef SINGLE_LED
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# define set_dirty_led(x) do{if (x) { led_state |= LED_DIRTY; } else { led_state &= (uint8_t)~LED_DIRTY; }}while(0)
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# define set_busy_led(x) do{if (x) { led_state |= LED_BUSY ; } else { led_state &= (uint8_t)~LED_BUSY ; }}while(0)
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# define set_error_led(x) do{if (x) { led_state |= LED_ERROR; } else { led_state &= (uint8_t)~LED_ERROR; }}while(0)
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#else
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# define set_dirty_led(x) do{if (x) { DIRTY_LED_ON(); } else { DIRTY_LED_OFF(); }}while(0)
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# define set_busy_led(x) do{if (x) { BUSY_LED_ON(); } else { BUSY_LED_OFF(); }}while(0)
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# define set_error_led(x) do{if (x) { led_state |= LED_ERROR; } else { led_state &= (uint8_t)~LED_ERROR; update_leds(); }}while(0)
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#endif
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#endif
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42
src/main.c
42
src/main.c
@ -45,6 +45,8 @@
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#include "fileops.h"
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#include "memory.h"
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#include "fpga_spi.h"
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#include "spi.h"
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#include "avrcompat.h"
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char stringbuf[100];
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@ -168,33 +170,49 @@ int main(void) {
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load_rom("/test.smc");
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uart_putc(')');
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/*XXX uart_putc('[');
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uart_putc('[');
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load_sram("/test.srm");
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uart_putc(']');*/
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set_avr_mapper(1);
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uart_putc(']');
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set_busy_led(0);
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set_avr_mapper(0);
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set_avr_ena(1);
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_delay_ms(100);
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uart_puts_P(PSTR("SNES GO!"));
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snes_reset(0);
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_delay_ms(6553.6);
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while(1) {
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// snes_main_loop();
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snes_main_loop();
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}
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while(1) {
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uint8_t data=PINC;
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/* HERE BE LIONS */
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while(1) {
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SPI_SS_HIGH();
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FPGA_SS_LOW();
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spiTransferByte(0x00);
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spiTransferByte(0x00);
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spiTransferByte(0x7f);
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spiTransferByte(0xc0);
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FPGA_SS_HIGH();
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FPGA_SS_LOW();
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spiTransferByte(0x81); // read w/ increment... hopefully
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spiTransferByte(0x00); // 1 dummy read
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uart_putcrlf();
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for(uint8_t cnt=0; cnt<16; cnt++) {
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uint8_t data=spiTransferByte(0x00);
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_delay_ms(2);
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if(data>=0x20 && data <= 0x7a) {
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uart_putc(data);
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} else {
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uart_putc('.');
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// uart_putc('.');
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uart_putc("0123456789ABCDEF"[data>>4]);
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uart_putc("0123456789ABCDEF"[data&15]);
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uart_putc(' ');
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}
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SET_AVR_NEXTADDR();
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CLR_AVR_NEXTADDR();
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// set_avr_bank(3);
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}
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FPGA_SS_HIGH();
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}
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while(1);
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}
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66
src/memory.c
66
src/memory.c
@ -39,10 +39,10 @@ uint32_t load_rom(char* filename) {
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SPI_SS_HIGH();
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if (file_res || !bytes_read) break;
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FPGA_SS_LOW();
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_delay_us(1);
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spiTransferByte(0x91); // write w/ increment
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if(!(count++ % 16)) {
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toggle_busy_led();
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uart_putc('.');
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}
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for(int j=0; j<bytes_read; j++) {
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spiTransferByte(file_buf[j]);
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@ -51,7 +51,6 @@ uint32_t load_rom(char* filename) {
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// _delay_ms(2);
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}
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spiTransferByte(0x00); // dummy tx for increment+write pulse
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_delay_us(10);
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FPGA_SS_HIGH();
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}
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file_close();
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@ -60,47 +59,49 @@ uint32_t load_rom(char* filename) {
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uint32_t load_sram(char* filename) {
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set_avr_bank(3);
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AVR_ADDR_RESET();
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SET_AVR_READ();
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UINT bytes_read;
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DWORD filesize;
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file_open(filename, FA_READ);
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filesize = file_handle.fsize;
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if(file_res) return 0;
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for(;;) {
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FPGA_SS_HIGH();
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SPI_SS_LOW();
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bytes_read = file_read();
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SPI_SS_HIGH();
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if (file_res || !bytes_read) break;
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FPGA_SS_LOW();
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spiTransferByte(0x91);
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for(int j=0; j<bytes_read; j++) {
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SET_AVR_DATA(file_buf[j]);
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AVR_WRITE();
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AVR_NEXTADDR();
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spiTransferByte(file_buf[j]);
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}
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spiTransferByte(0x00); // dummy tx
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FPGA_SS_HIGH();
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}
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file_close();
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return (uint32_t)filesize;
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}
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void save_sram(char* filename, uint32_t sram_size) {
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void save_sram(char* filename, uint32_t sram_size, uint32_t base_addr) {
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uint32_t count = 0;
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uint32_t num = 0;
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set_avr_bank(3);
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_delay_us(100);
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AVR_ADDR_RESET();
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CLR_AVR_READ();
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SET_AVR_WRITE();
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spi_sd();
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file_open(filename, FA_CREATE_ALWAYS | FA_WRITE);
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if(file_res) {
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uart_putc(0x30+file_res);
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}
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while(count<sram_size) {
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set_avr_addr(base_addr+count);
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spi_fpga();
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spiTransferByte(0x81); // read
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spiTransferByte(0); // dummy
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for(int j=0; j<sizeof(file_buf); j++) {
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_delay_us(5);
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file_buf[j] = AVR_DATA;
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CLR_AVR_ADDR_EN();
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SET_AVR_NEXTADDR();
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_delay_us(5);
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CLR_AVR_NEXTADDR();
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SET_AVR_ADDR_EN();
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file_buf[j] = spiTransferByte(0x00);
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count++;
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}
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spi_sd();
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num = file_write();
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}
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file_close();
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@ -109,25 +110,24 @@ void save_sram(char* filename, uint32_t sram_size) {
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uint32_t calc_sram_crc(uint32_t size) {
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uint8_t data;
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set_avr_bank(3);
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_delay_us(100);
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AVR_ADDR_RESET();
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SET_AVR_WRITE();
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CLR_AVR_READ();
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uint32_t count;
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uint16_t crc;
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crc=0;
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set_avr_bank(3);
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SPI_SS_HIGH();
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FPGA_SS_HIGH();
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FPGA_SS_LOW();
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spiTransferByte(0x81);
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spiTransferByte(0x00);
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for(count=0; count<size; count++) {
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_delay_us(5);
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data = AVR_DATA;
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data = spiTransferByte(0);
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/* uart_putc(hex[(data>>4)]);
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uart_putc(hex[data&0xf]);
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uart_putc(' ');
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_delay_ms(2);*/
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crc += crc16_update(crc, &data, 1);
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CLR_AVR_ADDR_EN();
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SET_AVR_NEXTADDR();
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_delay_us(5);
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CLR_AVR_NEXTADDR();
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SET_AVR_ADDR_EN();
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}
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FPGA_SS_HIGH();
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/* uart_putc(hex[(crc>>28)&0xf]);
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uart_putc(hex[(crc>>24)&0xf]);
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uart_putc(hex[(crc>>20)&0xf]);
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@ -5,6 +5,6 @@
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#define MEMORY_H
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uint32_t load_rom(char* filename);
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uint32_t load_sram(char* filename);
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void save_sram(char* filename, uint32_t sram_size);
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void save_sram(char* filename, uint32_t sram_size, uint32_t base_addr);
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uint32_t calc_sram_crc(uint32_t size);
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#endif
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@ -10,12 +10,13 @@
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#include "memory.h"
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#include "fileops.h"
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#include "ff.h"
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#include "led.h"
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uint8_t initloop=1;
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uint32_t sram_crc, sram_crc_old;
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uint32_t sram_size = 8192; // sane default
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uint32_t sram_base_addr = 0x600000; // chip 3
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void snes_init() {
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DDRD |= _BV(PD5); // PD5 = RESET_DIR
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DDRD |= _BV(PD6); // PD6 = RESET
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@ -46,13 +47,16 @@ void snes_reset(int state) {
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void snes_main_loop() {
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if(initloop) {
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sram_crc_old = calc_sram_crc(sram_size);
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save_sram("/test.srm", sram_size, sram_base_addr);
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initloop=0;
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}
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sram_crc = calc_sram_crc(sram_size);
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if(sram_crc != sram_crc_old) {
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uart_putc('U');
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uart_putcrlf();
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save_sram("/test.srm", sram_size);
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set_busy_led(1);
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save_sram("/test.srm", sram_size, sram_base_addr);
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set_busy_led(0);
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}
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sram_crc_old = sram_crc;
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uart_putc('.');
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@ -31,8 +31,6 @@ module address(
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output IS_ROM, // address mapped as ROM?
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input [23:0] AVR_ADDR, // allow address to be set externally
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input ADDR_WRITE,
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output SRAM_BHE,
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output SRAM_BLE,
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output SRAM_ADDR0
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);
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@ -40,7 +38,7 @@ reg [22:0] SRAM_ADDR_BUF;
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reg [3:0] ROM_SEL_BUF;
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reg [3:0] AVR_ROM_SEL_BUF;
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reg [3:0] CS_ARRAY[3:0];
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reg [1:0] AVR_BANK;
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wire [1:0] SRAM_BANK;
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wire [3:0] CURRENT_ROM_SEL;
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wire [22:0] SRAM_ADDR_FULL;
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@ -50,7 +48,6 @@ initial begin
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CS_ARRAY[1] = 4'b0010;
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CS_ARRAY[2] = 4'b0100;
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CS_ARRAY[3] = 4'b1000;
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AVR_BANK = 2'b0;
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end
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/* currently supported mappers:
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@ -84,7 +81,7 @@ assign IS_ROM = ( (MAPPER == 3'b000) ? ( (!SNES_ADDR[22]
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assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR
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: ((MAPPER == 3'b000) ?
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(IS_SAVERAM ? SNES_ADDR[14:0] - 15'h6000
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: SNES_ADDR[22:0])
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: (SNES_ADDR[22:0] & 23'b00111111111111111111111))
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:(MAPPER == 3'b001) ?
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(IS_SAVERAM ? SNES_ADDR[14:0]
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: {1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]})
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@ -93,11 +90,9 @@ assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR
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assign SRAM_BANK = SRAM_ADDR_FULL[22:21];
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assign SRAM_ADDR = SRAM_ADDR_FULL[20:1];
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// XXX assign ROM_SEL = (MODE) ? CS_ARRAY[AVR_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK];
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assign ROM_SEL = 4'b0001;
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assign ROM_SEL = (MODE) ? CS_ARRAY[SRAM_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK];
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// assign ROM_SEL = 4'b0001;
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assign SRAM_BHE = !AVR_ENA ? SRAM_ADDR_FULL[0] : 1'b0;
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assign SRAM_BLE = !AVR_ENA ? !SRAM_ADDR_FULL[0] : 1'b0;
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assign SRAM_ADDR0 = SRAM_ADDR_FULL[0];
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endmodule
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@ -43,21 +43,22 @@ reg [7:0] AVR_IN_MEM;
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reg [7:0] AVR_OUT_MEM;
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wire [7:0] FROM_SRAM_BYTE;
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wire [7:0] TO_SRAM_BYTE;
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assign SNES_DATA = SNES_READ ? 8'bZ : SNES_OUT_MEM;
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assign FROM_SRAM_BYTE = (SRAM_ADDR0 ? SRAM_DATA[7:0] : SRAM_DATA[15:8]);
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assign TO_SRAM_BYTE = !AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ) // /**/ : 8'bZ;
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: MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ)
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: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ);
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assign AVR_OUT_DATA = !AVR_ENA ? (FROM_SRAM_BYTE)
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: (AVR_OUT_MEM);
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// XXX assign SRAM_DATA = (SRAM_BHE ? {8'bZ, TO_SRAM_BYTE} : {TO_SRAM_BYTE, 8'bZ});
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assign SRAM_DATA = !AVR_ENA ? ((SRAM_ADDR0 ? {8'bZ, TO_SRAM_BYTE} : {TO_SRAM_BYTE, 8'bZ})) : 16'bZ;
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assign SRAM_DATA[7:0] = SRAM_ADDR0 ? (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ)
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: (MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ)
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: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)))
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: 8'bZ;
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assign SRAM_DATA[15:8] = SRAM_ADDR0 ? 8'bZ : (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ)
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: (MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ)
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: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)));
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always @(posedge CLK) begin
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if(SNES_DATA_TO_MEM)
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SNES_IN_MEM <= SNES_DATA;
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@ -1,4 +1,3 @@
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NET "CLK" TNM_NET = CLK;
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NET "CLKIN" TNM_NET = CLKIN;
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TIMESPEC TS_CLKIN = PERIOD "CLKIN" 30 MHz HIGH 50 %;
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NET "AVR_ENA" IOSTANDARD = LVCMOS33;
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@ -73,7 +72,6 @@ NET "SRAM_WE" IOSTANDARD = LVCMOS33;
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NET "SNES_CPU_CLK" IOSTANDARD = LVCMOS33;
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NET "SNES_IRQ" IOSTANDARD = LVCMOS33;
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NET "SNES_REFRESH" IOSTANDARD = LVCMOS33;
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NET "SPI_LSB" IOSTANDARD = LVCMOS33;
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NET "SPI_MISO" IOSTANDARD = LVCMOS33;
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NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
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NET "SPI_SCK" IOSTANDARD = LVCMOS33;
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@ -185,5 +183,3 @@ NET "SRAM_DATA[8]" LOC = P96;
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NET "SRAM_DATA[9]" LOC = P98;
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NET "SRAM_OE" LOC = P93;
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NET "CLKIN" IOSTANDARD = LVCMOS33;
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NET "CLKIN" SLEW = FAST;
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NET "CLKIN" PULLUP;
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@ -49,11 +49,10 @@ module main(
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output SPI_MISO,
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input SPI_SS,
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input SPI_SCK,
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input AVR_ENA,
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input AVR_ENA
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/* debug */
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output MODE,
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output SPI_LSB
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);
|
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wire [7:0] spi_cmd_data;
|
||||
wire [7:0] spi_param_data;
|
||||
@ -67,7 +66,7 @@ wire [7:0] AVR_IN_DATA;
|
||||
wire [7:0] AVR_OUT_DATA;
|
||||
wire [3:0] MAPPER;
|
||||
|
||||
spi snes_spi(.clk(CLK),
|
||||
spi snes_spi(.clk(CLK2),
|
||||
.MOSI(SPI_MOSI),
|
||||
.MISO(SPI_MISO),
|
||||
.SSEL(SPI_SS),
|
||||
@ -78,13 +77,14 @@ spi snes_spi(.clk(CLK),
|
||||
.cmd_data(spi_cmd_data),
|
||||
.param_data(spi_param_data),
|
||||
.endmessage(spi_endmessage),
|
||||
.startmessage(spi_startmessage),
|
||||
.input_data(spi_input_data),
|
||||
.byte_cnt(spi_byte_cnt),
|
||||
.bit_cnt(spi_bit_cnt)
|
||||
);
|
||||
|
||||
avr_cmd snes_avr_cmd(
|
||||
.clk(CLK),
|
||||
.clk(CLK2),
|
||||
.cmd_ready(spi_cmd_ready),
|
||||
.param_ready(spi_param_ready),
|
||||
.cmd_data(spi_cmd_data),
|
||||
@ -97,7 +97,10 @@ avr_cmd snes_avr_cmd(
|
||||
.avr_data_out(AVR_IN_DATA),
|
||||
.spi_byte_cnt(spi_byte_cnt),
|
||||
.spi_bit_cnt(spi_bit_cnt),
|
||||
.addr_out(AVR_ADDR)
|
||||
.spi_data_out(spi_input_data),
|
||||
.addr_out(AVR_ADDR),
|
||||
.endmessage(spi_endmessage),
|
||||
.startmessage(spi_startmessage)
|
||||
);
|
||||
|
||||
my_dcm snes_dcm(.CLKIN(CLKIN),
|
||||
@ -131,7 +134,7 @@ reg ADDR_WRITE;
|
||||
|
||||
|
||||
address snes_addr(
|
||||
.CLK(CLK),
|
||||
.CLK(CLK2),
|
||||
.MAPPER(MAPPER),
|
||||
.SNES_ADDR(SNES_ADDR), // requested address from SNES
|
||||
.SNES_CS(SNES_CSs), // "CART" pin from SNES (active low)
|
||||
@ -142,12 +145,10 @@ address snes_addr(
|
||||
.IS_SAVERAM(IS_SAVERAM),
|
||||
.IS_ROM(IS_ROM),
|
||||
.AVR_ADDR(AVR_ADDR),
|
||||
.SRAM_BHE(SRAM_BHE),
|
||||
.SRAM_BLE(SRAM_BLE),
|
||||
.SRAM_ADDR0(SRAM_ADDR0)
|
||||
);
|
||||
|
||||
data snes_data(.CLK(CLK),
|
||||
data snes_data(.CLK(CLK2),
|
||||
.SNES_READ(SNES_READs),
|
||||
.SNES_WRITE(SNES_WRITEs),
|
||||
.AVR_READ(AVR_READ),
|
||||
@ -168,31 +169,33 @@ data snes_data(.CLK(CLK),
|
||||
parameter MODE_SNES = 1'b0;
|
||||
parameter MODE_AVR = 1'b1;
|
||||
|
||||
parameter STATE_0 = 8'b00000001;
|
||||
parameter STATE_1 = 8'b00000010;
|
||||
parameter STATE_2 = 8'b00000100;
|
||||
parameter STATE_3 = 8'b00001000;
|
||||
parameter STATE_4 = 8'b00010000;
|
||||
parameter STATE_5 = 8'b00100000;
|
||||
parameter STATE_6 = 8'b01000000;
|
||||
parameter STATE_7 = 8'b10000000;
|
||||
parameter STATE_0 = 10'b0000000001;
|
||||
parameter STATE_1 = 10'b0000000010;
|
||||
parameter STATE_2 = 10'b0000000100;
|
||||
parameter STATE_3 = 10'b0000001000;
|
||||
parameter STATE_4 = 10'b0000010000;
|
||||
parameter STATE_5 = 10'b0000100000;
|
||||
parameter STATE_6 = 10'b0001000000;
|
||||
parameter STATE_7 = 10'b0010000000;
|
||||
parameter STATE_8 = 10'b0100000000;
|
||||
parameter STATE_9 = 10'b1000000000;
|
||||
|
||||
reg [7:0] STATE;
|
||||
reg [2:0] STATEIDX;
|
||||
reg [9:0] STATE;
|
||||
reg [3:0] STATEIDX;
|
||||
|
||||
reg STATE_RESET, CYCLE_RESET, CYCLE_RESET_ACK;
|
||||
reg SRAM_WE_MASK;
|
||||
reg SRAM_OE_MASK;
|
||||
|
||||
reg [7:0] SRAM_WE_ARRAY [3:0];
|
||||
reg [7:0] SRAM_OE_ARRAY [3:0];
|
||||
reg [9:0] SRAM_WE_ARRAY [3:0];
|
||||
reg [9:0] SRAM_OE_ARRAY [3:0];
|
||||
|
||||
reg [7:0] SNES_DATA_TO_MEM_ARRAY[1:0];
|
||||
reg [7:0] AVR_DATA_TO_MEM_ARRAY[1:0];
|
||||
reg [7:0] SRAM_DATA_TO_SNES_MEM_ARRAY[1:0];
|
||||
reg [7:0] SRAM_DATA_TO_AVR_MEM_ARRAY[1:0];
|
||||
reg [9:0] SNES_DATA_TO_MEM_ARRAY[1:0];
|
||||
reg [9:0] AVR_DATA_TO_MEM_ARRAY[1:0];
|
||||
reg [9:0] SRAM_DATA_TO_SNES_MEM_ARRAY[1:0];
|
||||
reg [9:0] SRAM_DATA_TO_AVR_MEM_ARRAY[1:0];
|
||||
|
||||
reg [7:0] MODE_ARRAY;
|
||||
reg [9:0] MODE_ARRAY;
|
||||
|
||||
reg SNES_READ_CYCLE;
|
||||
reg SNES_WRITE_CYCLE;
|
||||
@ -215,8 +218,8 @@ initial begin
|
||||
CYCLE_RESET = 0;
|
||||
CYCLE_RESET_ACK = 0;
|
||||
|
||||
STATE = STATE_7;
|
||||
STATEIDX = 7;
|
||||
STATE = STATE_9;
|
||||
STATEIDX = 9;
|
||||
SRAM_WE_MASK = 1'b1;
|
||||
SRAM_OE_MASK = 1'b1;
|
||||
SNES_READ_CYCLE = 1'b1;
|
||||
@ -224,29 +227,29 @@ initial begin
|
||||
AVR_READ_CYCLE = 1'b1;
|
||||
AVR_WRITE_CYCLE = 1'b1;
|
||||
|
||||
MODE_ARRAY = 8'b00001111;
|
||||
MODE_ARRAY = 10'b0000011111;
|
||||
|
||||
SRAM_WE_ARRAY[2'b00] = 8'b10001000;
|
||||
SRAM_WE_ARRAY[2'b01] = 8'b10001111;
|
||||
SRAM_WE_ARRAY[2'b10] = 8'b11111000;
|
||||
SRAM_WE_ARRAY[2'b11] = 8'b11111111;
|
||||
SRAM_WE_ARRAY[2'b00] = 10'b1000010000;
|
||||
SRAM_WE_ARRAY[2'b01] = 10'b1000011111;
|
||||
SRAM_WE_ARRAY[2'b10] = 10'b1111110000;
|
||||
SRAM_WE_ARRAY[2'b11] = 10'b1111111111;
|
||||
|
||||
SRAM_OE_ARRAY[2'b00] = 8'b11111111;
|
||||
SRAM_OE_ARRAY[2'b01] = 8'b11110000;
|
||||
SRAM_OE_ARRAY[2'b10] = 8'b00001111;
|
||||
SRAM_OE_ARRAY[2'b11] = 8'b00000000;
|
||||
SRAM_OE_ARRAY[2'b00] = 10'b1111111111;
|
||||
SRAM_OE_ARRAY[2'b01] = 10'b1111100000;
|
||||
SRAM_OE_ARRAY[2'b10] = 10'b0000011111;
|
||||
SRAM_OE_ARRAY[2'b11] = 10'b0000000000;
|
||||
|
||||
SNES_DATA_TO_MEM_ARRAY[1'b0] = 8'b10000000;
|
||||
SNES_DATA_TO_MEM_ARRAY[1'b1] = 8'b00000000;
|
||||
SNES_DATA_TO_MEM_ARRAY[1'b0] = 10'b1000000000;
|
||||
SNES_DATA_TO_MEM_ARRAY[1'b1] = 10'b0000000000;
|
||||
|
||||
AVR_DATA_TO_MEM_ARRAY[1'b0] = 8'b00010000;
|
||||
AVR_DATA_TO_MEM_ARRAY[1'b1] = 8'b00000000;
|
||||
AVR_DATA_TO_MEM_ARRAY[1'b0] = 10'b0000100000;
|
||||
AVR_DATA_TO_MEM_ARRAY[1'b1] = 10'b0000000000;
|
||||
|
||||
SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 8'b00000000;
|
||||
SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 8'b00100000;
|
||||
SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 10'b0000000000;
|
||||
SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 10'b0000100000;
|
||||
|
||||
SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 8'b00000000;
|
||||
SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 8'b00000001;
|
||||
SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 10'b0000000000;
|
||||
SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 10'b0000000001;
|
||||
end
|
||||
|
||||
// falling edge of SNES /RD or /WR marks the beginning of a new cycle
|
||||
@ -263,7 +266,7 @@ always @(posedge CLK2) begin
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
always @(posedge CLK2) begin
|
||||
if (CYCLE_RESET && !CYCLE_RESET_ACK) begin
|
||||
CYCLE_RESET_ACK <= 1;
|
||||
STATE <= STATE_0;
|
||||
@ -283,53 +286,65 @@ always @(posedge CLK) begin
|
||||
STATE <= STATE_6;
|
||||
STATE_6:
|
||||
STATE <= STATE_7;
|
||||
STATE_7: begin
|
||||
STATE_7:
|
||||
STATE <= STATE_8;
|
||||
STATE_8:
|
||||
STATE <= STATE_9;
|
||||
STATE_9: begin
|
||||
if (SNES_RW /* || !AVR_ENA */) // check for end of SNES cycle to avoid looping
|
||||
CYCLE_RESET_ACK <= 0; // ready for new cycle
|
||||
STATE <= STATE_7;
|
||||
STATE <= STATE_9;
|
||||
end
|
||||
default:
|
||||
STATE <= STATE_7;
|
||||
STATE <= STATE_9;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK2) begin
|
||||
|
||||
case (STATE)
|
||||
|
||||
STATE_7: begin
|
||||
case (STATE)
|
||||
STATE_9: begin
|
||||
SNES_READ_CYCLE <= SNES_READs;
|
||||
SNES_WRITE_CYCLE <= SNES_WRITEs;
|
||||
AVR_READ_CYCLE <= AVR_READ;
|
||||
AVR_WRITE_CYCLE <= AVR_WRITE;
|
||||
STATEIDX <= 7;
|
||||
STATEIDX <= 9;
|
||||
end
|
||||
|
||||
STATE_0: begin
|
||||
STATEIDX <= 6;
|
||||
STATEIDX <= 8;
|
||||
end
|
||||
|
||||
STATE_1: begin
|
||||
STATEIDX <= 5;
|
||||
STATEIDX <= 7;
|
||||
end
|
||||
|
||||
STATE_2: begin
|
||||
STATEIDX <= 4;
|
||||
STATEIDX <= 6;
|
||||
end
|
||||
|
||||
STATE_3: begin
|
||||
STATEIDX <= 3;
|
||||
STATEIDX <= 5;
|
||||
end
|
||||
|
||||
STATE_4: begin
|
||||
STATEIDX <= 2;
|
||||
STATEIDX <= 4;
|
||||
end
|
||||
|
||||
STATE_5: begin
|
||||
STATEIDX <= 1;
|
||||
STATEIDX <= 3;
|
||||
end
|
||||
|
||||
STATE_6: begin
|
||||
STATEIDX <= 2;
|
||||
end
|
||||
|
||||
STATE_7: begin
|
||||
STATEIDX <= 1;
|
||||
end
|
||||
|
||||
STATE_8: begin
|
||||
STATEIDX <= 0;
|
||||
end
|
||||
endcase
|
||||
@ -337,21 +352,20 @@ end
|
||||
|
||||
// When in AVR mode, enable SRAM_WE according to AVR programming
|
||||
// else enable SRAM_WE according to state&cycle
|
||||
//assign SRAM_WE = !AVR_ENA ? AVR_WRITE
|
||||
// : ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]);
|
||||
assign SRAM_WE = !AVR_ENA ? AVR_WRITE
|
||||
: ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]);
|
||||
|
||||
// When in AVR mode, enable SRAM_OE whenever not writing
|
||||
// else enable SRAM_OE according to state&cycle
|
||||
assign SRAM_OE = !AVR_ENA ? AVR_READ
|
||||
: SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX];
|
||||
|
||||
assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
|
||||
assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0;
|
||||
|
||||
// dumb version
|
||||
//assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs;
|
||||
assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
SNES_DATABUS_OE_BUF <= SNES_CSs | (SNES_READs & SNES_WRITEs);
|
||||
end
|
||||
//assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1;
|
||||
|
||||
//assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
|
||||
assign SNES_DATABUS_OE = (IS_ROM & SNES_CSs) | (!IS_ROM & !IS_SAVERAM) | (SNES_READs & SNES_WRITEs);
|
||||
|
||||
@ -81,7 +81,7 @@
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="sd2snes"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|main"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|main_tf2"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Module|main_tf2"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user