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FPGA: pull-up SD clock

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This commit is contained in:
ikari 2012-02-27 22:12:35 +01:00
parent 7eb65e35ce
commit e2f33c28c9
4 changed files with 6 additions and 4 deletions
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1
verilog/sd2snes/main.ucf
View File

@ -535,6 +535,7 @@ NET "SD_DAT[3]" LOC = P63;
# PlanAhead Generated IO constraints
NET "SD_CLK" IOSTANDARD = LVCMOS33;
NET "SD_CLK" PULLUP;
NET "SD_CMD" IOSTANDARD = LVCMOS33;
NET "SD_DAT[0]" IOSTANDARD = LVCMOS33;
NET "SD_DAT[1]" IOSTANDARD = LVCMOS33;

4
verilog/sd2snes/sd2snes.xise
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@ -377,8 +377,8 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>

1
verilog/sd2snes_cx4/main.ucf
View File

@ -535,6 +535,7 @@ NET "SD_DAT[3]" LOC = P63;
# PlanAhead Generated IO constraints
NET "SD_CLK" IOSTANDARD = LVCMOS33;
NET "SD_CLK" PULLUP;
NET "SD_CMD" IOSTANDARD = LVCMOS33;
NET "SD_DAT[0]" IOSTANDARD = LVCMOS33;
NET "SD_DAT[1]" IOSTANDARD = LVCMOS33;

4
verilog/sd2snes_cx4/sd2snes_cx4.xise
View File

@ -366,8 +366,8 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="11" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="11" xil_pn:valueState="non-default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>