Maximilian Rehkopf
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60d7a08117
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FPGA: Adjust Cx4 timing to new master clock rate
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2012-07-09 02:13:44 +02:00 |
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Maximilian Rehkopf
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7df6909266
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FPGA: rework shared memory access FSM
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2012-07-09 02:12:59 +02:00 |
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Maximilian Rehkopf
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2a1ef40796
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FPGA/cx4: adjust Cx4 CPU timing
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2012-05-19 18:07:13 +02:00 |
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Maximilian Rehkopf
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1b272a7a7d
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FPGA/Cx4: introduce wait states (fix MMX2 attract mode)
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2012-05-02 10:30:22 +02:00 |
|
ikari
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3dd64cb98f
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FPGA/cx4: timing closure
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2011-11-01 20:56:30 +01:00 |
|
ikari
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314da586a4
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FPGA/cx4: implement reset vector access
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2011-11-01 20:54:07 +01:00 |
|
ikari
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7643790fed
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FPGA/Cx4: fully operational except reset vector area
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2011-10-30 01:54:39 +02:00 |
|
ikari
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8c76dfbeb6
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FPGA/Cx4: WIP
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2011-10-27 15:42:13 +02:00 |
|
ikari
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fb9a28bf38
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FPGA/cx4: rework CPU FSM (ALU still missing)
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2011-10-23 20:56:07 +02:00 |
|
ikari
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e57c4aa450
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FPGA/cx4: initial commit
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2011-10-23 04:10:55 +02:00 |
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