Maximilian Rehkopf
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2a1ef40796
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FPGA/cx4: adjust Cx4 CPU timing
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2012-05-19 18:07:13 +02:00 |
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Maximilian Rehkopf
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f5caf21fac
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FPGA: slightly tighten timing constraints
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2012-05-02 10:41:07 +02:00 |
|
ikari
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e2f33c28c9
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FPGA: pull-up SD clock
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2012-02-27 22:12:35 +01:00 |
|
ikari
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f0a2e85c65
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FPGA: updated project files
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2012-01-14 23:16:57 +01:00 |
|
ikari
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3dd64cb98f
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FPGA/cx4: timing closure
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2011-11-01 20:56:30 +01:00 |
|
ikari
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7643790fed
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FPGA/Cx4: fully operational except reset vector area
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2011-10-30 01:54:39 +02:00 |
|
ikari
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8c76dfbeb6
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FPGA/Cx4: WIP
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2011-10-27 15:42:13 +02:00 |
|
ikari
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e57c4aa450
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FPGA/cx4: initial commit
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2011-10-23 04:10:55 +02:00 |
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