Merge branch 'develop' into merging

Conflicts:
	src/bootldr/fileops.h
	src/bootldr/iap.c
	src/fpga_spi.c
	src/memory.c
	src/smc.c
	verilog/sd2snes/address.v

snes/boot/const.a65

@@ -2,7 +2,8 @@ version		.byt "                            v0.1",0
 zero		.word	0
 bg2tile		.byt $20
 
-space64	.byt $20, $20, $20, $20, $20, $20, $20, $20
+space64	
+    .byt $20, $20, $20, $20, $20, $20, $20, $20
 	.byt $20, $20, $20, $20, $20, $20, $20, $20
 	.byt $20, $20, $20, $20, $20, $20, $20, $20
 	.byt $20, $20, $20, $20, $20, $20, $20, $20

snes/boot/data.a65

@@ -1,41 +1,43 @@
 .data
 ;don't anger the stack!
 ;----------parameters for text output----------
-print_x	.byt 0		;x coordinate
+print_x         .byt  0  ; x coordinate
-	.byt 0
+                .byt  0
-print_y	.byt 0		;y coordinate
+print_y         .byt  0  ; y coordinate
-	.byt 0
+                .byt  0
-print_src	.word 0	;source data address
+print_src       .word 0  ; source data address
-print_bank	.byt 0	;source data bank
+print_bank      .byt  0  ; source data bank
-print_pal	.word 0	;palette number for text output
+print_pal       .word 0  ; palette number for text output
-print_temp	.word 0 ;work variable
+print_temp      .word 0  ; work variable
-print_count	.byt 0	;how many characters may be printed?
+print_count     .byt  0  ; how many characters may be printed?
-print_count_tmp .byt 0	;work variable
+print_count_tmp .byt  0  ; work variable
-print_done	.word 0  ;how many characters were printed?
+print_done      .word 0  ; how many characters were printed?
 ;----------parameters for dma----------
-dma_a_bank	.byt 0
+dma_a_bank      .byt  0
-dma_a_addr	.word 0
+dma_a_addr      .word 0
-dma_b_reg	.byt 0
+dma_b_reg       .byt  0
-dma_len		.word 0
+dma_len         .word 0
-dma_mode	.byt 0
+dma_mode        .byt  0
 
 ;----------state information----------
-isr_done	.byt 0  ; isr done flag
+isr_done        .byt  0  ; isr done flag
 ;----------menu layout/system constants (224/448)
-textdmasize	.word 0 ; number of bytes to copy each frame
+textdmasize     .word 0 ; number of bytes to copy each frame
 
-infloop		.byt 0,0  ; to be filled w/ 80 FE
+infloop         .byt 0,0  ; to be filled w/ 80 FE
 
-printloop_wram	.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+printloop_wram 
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
 
-loprint_wram	.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+loprint_wram 
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-		.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+      .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

snes/boot/palette.a65

@@ -1,4 +1,4 @@
 palette
 ;fonts
 	.byt  $42, $08, $ff, $7f, $00, $00, $9c, $73
-        .byt  $42, $08, $ff, $43, $00, $00, $18, $63
+    .byt  $42, $08, $ff, $43, $00, $00, $18, $63

snes/boot/reset.a65

@@ -11,24 +11,24 @@
 
 ; NMI - called on VBlank
 NMI_ROUTINE:
-        sep #$20 : .as
+    sep #$20 : .as
-	rep #$10 : .xl
+    rep #$10 : .xl
-	lda #$00
+    lda #$00
-	pha
+    pha
-	plb
+    plb
-        lda $4210
+    lda $4210
 
-	ldx #BG1_TILE_BASE
+    ldx #BG1_TILE_BASE
-	stx $2116
+    stx $2116
-	DMA0(#$01, #36*64, #^BG1_TILE_BUF, #!BG1_TILE_BUF, #$18)
+    DMA0(#$01, #36*64, #^BG1_TILE_BUF, #!BG1_TILE_BUF, #$18)
 
-	lda #$01
+    lda #$01
-	sta isr_done
+    sta isr_done
-        rtl
+    rtl
 
 ; IRQ - called when triggered
 IRQ_ROUTINE:
-        sep #$20 : .as
+    sep #$20 : .as
-        lda $4211  ;Acknowledge irq
+    lda $4211  ;Acknowledge irq
-        rtl
+    rtl
 

src/Makefile

@@ -124,7 +124,8 @@ NM = $(ARCH)-nm
 REMOVE = rm -f
 COPY = cp
 AWK = awk
-
+RLE = ../utils/rle
+BIN2H = utils/bin2h
 
 #---------------- Compiler Options ----------------
 #  -g*:          generate debugging information
@@ -197,7 +198,7 @@ ALL_ASFLAGS = -I. -x assembler-with-cpp $(ASFLAGS) $(CDEFS)
 # Default target.
 all: build
 
-build: elf bin hex
+build: elf bin hex cfgware.h
 	$(E) "  SIZE   $(TARGET).elf"
 	$(Q)$(ELFSIZE)|grep -v debug
 	cp $(TARGET).bin $(OBJDIR)/firmware.img
@@ -230,6 +231,13 @@ HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex
 ELFSIZE = $(SIZE) -A $(TARGET).elf
 
 
+# Generate cfgware.h
+cfgware.h: $(OBJDIR)/fpga_rle.bit
+	$(E) "  BIN2H  $@"
+	$(Q) $(BIN2H) $< $@
+$(OBJDIR)/fpga_rle.bit: sd2sneslite.bit
+	$(E) "  RLE    $@"
+	$(Q) $(RLE) $< $@
 
 # Generate autoconf.h from config
 .PRECIOUS : $(OBJDIR)/autoconf.h
@@ -302,6 +310,7 @@ clean_list :
 	$(Q)$(REMOVE) $(TARGET).sym
 	$(Q)$(REMOVE) $(TARGET).lss
 	$(Q)$(REMOVE) $(OBJ)
+	$(Q)$(REMOVE) cfgware.h
 	$(Q)$(REMOVE) $(OBJDIR)/autoconf.h
 	$(Q)$(REMOVE) $(OBJDIR)/*.bin
 	$(Q)$(REMOVE) $(LST)

src/bootldr/lpc1754.cfg

@@ -27,9 +27,9 @@ if { [info exists CPUTAPID ] } {
 
 #delays on reset lines
 #if your OpenOCD version rejects "jtag_nsrst_delay" replace it with:
-#adapter_nsrst_delay 200
+adapter_nsrst_delay 200
-jtag_nsrst_delay 200
+#jtag_nsrst_delay 200
-jtag_ntrst_delay 200
+#jtag_ntrst_delay 200
 
 # LPC2000 & LPC1700 -> SRST causes TRST
 #reset_config srst_pulls_trst
@@ -56,7 +56,7 @@ flash bank $_FLASHNAME lpc2000 0x0 0x20000 0 0 $_TARGETNAME \
 # Run with *real slow* clock by default since the
 # boot rom could have been playing with the PLL, so
 # we have no idea what clock the target is running at.
-jtag_khz 1000
+adapter_khz 1000
 
 $_TARGETNAME configure -event reset-init {
 	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select

src/bootldr/main.c

@@ -52,8 +52,12 @@ int main(void) {
   clock_init();
 //  LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
   sdn_init();
+
+  for(i = 0; i < 20; i++) uart_putc('-');
+  uart_putc('\n');
+
   DBG_BL printf("chksum=%08lx\n", *(uint32_t*)28);
-  DBG_BL printf("\n\nsd2snes mk.2 bootloader\nver.: " VER "\ncpu clock: %ld Hz\n", CONFIG_CPU_FREQUENCY);
+  /*DBG_BL*/ printf("\n\nsd2snes mk.2 bootloader\nver.: " VER "\ncpu clock: %ld Hz\n", CONFIG_CPU_FREQUENCY);
 DBG_BL printf("PCONP=%lx\n", LPC_SC->PCONP);
 /* setup timer (fpga clk) */
   LPC_TIM3->CTCR=0;

src/bootldr/openocd-usb.cfg

@@ -5,8 +5,14 @@
 #
 
 interface ft2232
-ft2232_vid_pid 0x0403 0x6010
+ft2232_vid_pid 0x15ba 0x0003
-ft2232_device_desc "Dual RS232"
+ft2232_device_desc "Olimex OpenOCD JTAG"
-ft2232_layout "oocdlink"
+ft2232_layout "olimex-jtag"
-ft2232_latency 2
+
+
+#interface ft2232
+#ft2232_vid_pid 0x0403 0x6010
+#ft2232_device_desc "Dual RS232"
+#ft2232_layout "oocdlink"
+#ft2232_latency 2
 #adapter_khz 10

src/cli.c

@@ -104,11 +104,11 @@ static int32_t parse_unsigned(uint32_t lower, uint32_t upper, uint8_t base) {
 /* Parse the string starting with curchar for a word in wordlist */
 static int8_t parse_wordlist(char *wordlist) {
   uint8_t i, matched;
-  char *cur, *ptr;
+  unsigned char *cur, *ptr;
-  char c;
+  unsigned char c;
 
   i = 0;
-  ptr = wordlist;
+  ptr = (unsigned char *)wordlist;
 
   // Command list on "?"
   if (strlen(curchar) == 1 && *curchar == '?') {
@@ -128,7 +128,7 @@ static int8_t parse_wordlist(char *wordlist) {
   }
 
   while (1) {
-    cur = curchar;
+    cur = (unsigned char *)curchar;
     matched = 1;
     c = *ptr;
     do {
@@ -140,7 +140,7 @@ static int8_t parse_wordlist(char *wordlist) {
 
       if (tolower((int)c) != tolower((int)*cur)) {
         // Check for end-of-word
-        if (cur != curchar && (*cur == ' ' || *cur == 0)) {
+        if (cur != (unsigned char*)curchar && (*cur == ' ' || *cur == 0)) {
           // Partial match found, return that
           break;
         } else {
@@ -156,7 +156,7 @@ static int8_t parse_wordlist(char *wordlist) {
     if (matched) {
       char *tmp = curchar;
 
-      curchar = cur;
+      curchar = (char *)cur;
       // Return match only if whitespace or end-of-string follows
       // (avoids mismatching partial words)
       if (skip_spaces()) {

src/filetypes.c

@@ -275,6 +275,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t
   sram_writeshort(num_dirs_total, SRAM_DB_ADDR+14);
   if(depth==0) return crc;
   else return switched_dir_tgt;
+  return was_empty; // tricky!
 }
 
 

src/fpga_spi.c

@@ -214,6 +214,7 @@ uint16_t fpga_status() {
 }
 
 void fpga_set_sddma_range(uint16_t start, uint16_t end) {
+  printf("%s %08X -> %08X\n", __func__, start, end);
   FPGA_SELECT();
   FPGA_TX_BYTE(FPGA_CMD_SDDMA_RANGE);
   FPGA_TX_BYTE(start>>8);

src/main.c

@@ -48,12 +48,14 @@ extern volatile int reset_changed;
 
 extern volatile cfg_t CFG;
 
-enum system_states {
+enum system_states
+{
   SYS_RTC_STATUS = 0,
   SYS_LAST_STATUS = 1
 };
 
-int main(void) {
+int main(void)
+{
   LPC_GPIO2->FIODIR = BV(4) | BV(5);
   LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT);
   BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
@@ -121,17 +123,21 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
     /* some sanity checks */
     uint8_t card_go = 0;
     while(!card_go) {
-      if(disk_status(0) & (STA_NOINIT|STA_NODISK)) {
+      if(disk_status(0) & (STA_NOINIT|STA_NODISK))
-	snes_bootprint("        No SD Card found!       \0");
+      {
-	while(disk_status(0) & (STA_NOINIT|STA_NODISK));
+        snes_bootprint("        No SD Card found!       \0");
-	delay_ms(200);
+        while(disk_status(0) & (STA_NOINIT|STA_NODISK));
+          delay_ms(200);
       }
       file_open((uint8_t*)"/sd2snes/menu.bin", FA_READ);
-      if(file_status != FILE_OK) {
+      if(file_status != FILE_OK)
-	snes_bootprint("  /sd2snes/menu.bin not found!  \0");
+      {
-	while(disk_status(0) == RES_OK);
+        snes_bootprint("  /sd2snes/menu.bin not found!  \0");
-      } else {
+        while(disk_status(0) == RES_OK);
-	card_go = 1;
+      } 
+      else
+      {
+        card_go = 1;
       }
       file_close();
     }
@@ -256,6 +262,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
           cfg_set_last_game_valid(1);
           cfg_save();
 	  filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
+	  printf("Filesize = %lu\n", filesize);
 	  break;
 	case SNES_CMD_SETRTC:
           /* get time from RAM */
@@ -306,30 +313,38 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
     cmd=0;
     uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
     uint16_t reset_count=0;
-    while(fpga_test() == FPGA_TEST_TOKEN) {
+    while(fpga_test() == FPGA_TEST_TOKEN)
+    {
       cli_entrycheck();
       sleep_ms(250);
       sram_reliable();
       printf("%s ", get_cic_statename(get_cic_state()));
-      if(reset_changed) {
+      if(reset_changed)
+      {
         printf("reset\n");
         reset_changed = 0;
         fpga_reset_srtc_state();
       }
-      snes_reset_now=get_snes_reset();
+      snes_reset_now = get_snes_reset();
-      if(snes_reset_now) {
+      if (snes_reset_now)
-	if(!snes_reset_prev) {
+      {
-	  printf("RESET BUTTON DOWN\n");
+        if (!snes_reset_prev)
-	  snes_reset_state=1;
+        {
-	  reset_count=0;
+          printf("RESET BUTTON DOWN\n");
-	}
+          snes_reset_state = 1;
-      } else {
+          reset_count = 0;
-	if(snes_reset_prev) {
+        }
-	  printf("RESET BUTTON UP\n");
-	  snes_reset_state=0;
-	}
       } 
-      if(snes_reset_state) {
+      else
+      {
+        if (snes_reset_prev)
+        {
+          printf("RESET BUTTON UP\n");
+          snes_reset_state = 0;
+        }
+      }
+      if (snes_reset_state)
+      {
 	reset_count++;
       } else {
 	sram_reliable();

src/memory.c

@@ -54,11 +54,12 @@ void sram_hexdump(uint32_t addr, uint32_t len) {
   uint32_t ptr;
   for(ptr=0; ptr < len; ptr += 16) {
     sram_readblock((void*)buf, ptr+addr, 16);
-    uart_trace(buf, 0, 16);
+    uart_trace(buf, 0, 16, addr);
   }
 }
 
 void sram_writebyte(uint8_t val, uint32_t addr) {
+  printf("WriteB %8Xh @%08lXh\n", val, addr);
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x98); /* WRITE */
@@ -74,10 +75,12 @@ uint8_t sram_readbyte(uint32_t addr) {
   FPGA_WAIT_RDY();
   uint8_t val = FPGA_RX_BYTE();
   FPGA_DESELECT();
+  //printf(" ReadB %8Xh @%08lXh\n", val, addr);
   return val;
 }
 
 void sram_writeshort(uint16_t val, uint32_t addr) {
+  printf("WriteS %8Xh @%08lXh\n", val, addr);
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x98); /* WRITE */
@@ -89,6 +92,7 @@ void sram_writeshort(uint16_t val, uint32_t addr) {
 }
 
 void sram_writelong(uint32_t val, uint32_t addr) {
+  printf("WriteL %8lXh @%08lXh\n", val, addr);
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x98); /* WRITE */
@@ -112,6 +116,7 @@ uint16_t sram_readshort(uint32_t addr) {
   FPGA_WAIT_RDY();
   val |= ((uint32_t)FPGA_RX_BYTE()<<8);
   FPGA_DESELECT();
+  //printf(" ReadS %8lXh @%08lXh\n", val, addr);
   return val;
 }
 
@@ -128,6 +133,7 @@ uint32_t sram_readlong(uint32_t addr) {
   FPGA_WAIT_RDY();
   val |= ((uint32_t)FPGA_RX_BYTE()<<24);
   FPGA_DESELECT();
+  //printf(" ReadL %8lXh @%08lXh\n", val, addr);
   return val;
 }
 
@@ -177,6 +183,7 @@ void sram_readstrn(void* buf, uint32_t addr, uint16_t size) {
 }
 
 void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
+  printf("WriteZ %08lX -> %08lX [%d]\n", addr, addr+size, size);
   uint16_t count=size;
   uint8_t* src = buf;
   set_mcu_addr(addr);
@@ -191,7 +198,7 @@ void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
 
 uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
   UINT bytes_read;
-  DWORD filesize;
+  DWORD filesize, read_size = 0;
   UINT count=0;
   tick_t ticksstart, ticks_total=0;
   ticksstart=getticks();
@@ -219,12 +226,14 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
     ff_sd_offload=1;
     sd_offload_tgt=0;
     bytes_read = file_read();
+    read_size += bytes_read;
     if (file_res || !bytes_read) break;
     if(!(count++ % 512)) {
       uart_putc('.');
     }
   }
   file_close();
+  printf("Read %ld [%08lX] bytes...\n", read_size, read_size);
   set_mapper(romprops.mapper_id);
   printf("rom header map: %02x; mapper id: %d\n", romprops.header.map, romprops.mapper_id);
   ticks_total=getticks()-ticksstart;
@@ -274,6 +283,9 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
     rammask = romprops.ramsize_bytes - 1;
   }
   rommask = romprops.romsize_bytes - 1;
+  if (rommask >= SRAM_SAVE_ADDR)
+    rommask = SRAM_SAVE_ADDR - 1;
+  
   printf("ramsize=%x rammask=%lx\nromsize=%x rommask=%lx\n", romprops.header.ramsize, rammask, romprops.header.romsize, rommask);
   set_saveram_mask(rammask);
   set_rom_mask(rommask);
@@ -536,9 +548,9 @@ uint8_t sram_reliable() {
     val=sram_readlong(SRAM_SCRATCHPAD);
     if(val==0x12345678) {
       score++;
-    } else {
+    } //else {
-      printf("i=%d val=%08lX\n", i, val);
+      //printf("i=%d val=%08lX\n", i, val);
-    }
+    //}
   }
   if(score<SRAM_RELIABILITY_SCORE) {
     result = 0;

src/memory.h

@@ -30,24 +30,26 @@
 #include <arm/NXP/LPC17xx/LPC17xx.h>
 #include "smc.h"
 
-#define SRAM_ROM_ADDR           (0x000000L)
+#define MASK_BITS                (0x000000)
-#define SRAM_SAVE_ADDR          (0xE00000L)
 
-#define SRAM_MENU_ADDR          (0xC00000L)
+#define SRAM_ROM_ADDR           ((0x000000L) & ~MASK_BITS)
-#define SRAM_DIR_ADDR           (0xC10000L)
+#define SRAM_SAVE_ADDR          ((0x600000L) & ~MASK_BITS)
-#define SRAM_DB_ADDR            (0xC80000L)
 
-#define SRAM_SPC_DATA_ADDR      (0xFD0000L)
+#define SRAM_MENU_ADDR          ((0x500000L) & ~MASK_BITS)
-#define SRAM_SPC_HEADER_ADDR    (0xFE0000L)
+#define SRAM_DIR_ADDR           ((0x510000L) & ~MASK_BITS)
+#define SRAM_DB_ADDR            ((0x580000L) & ~MASK_BITS)
 
-#define SRAM_MENU_SAVE_ADDR     (0xFF0000L)
+#define SRAM_SPC_DATA_ADDR      ((0x7D0000L) & ~MASK_BITS)
-#define SRAM_CMD_ADDR           (0xFF1000L)
+#define SRAM_SPC_HEADER_ADDR    ((0x7E0000L) & ~MASK_BITS)
-#define SRAM_PARAM_ADDR         (0xFF1004L)
+
-#define SRAM_STATUS_ADDR        (0xFF1100L)
+#define SRAM_MENU_SAVE_ADDR     ((0x7F0000L) & ~MASK_BITS)
-#define SRAM_SYSINFO_ADDR       (0xFF1200L)
+#define SRAM_CMD_ADDR           ((0x7F1000L) & ~MASK_BITS)
-#define SRAM_LASTGAME_ADDR      (0xFF1420L)
+#define SRAM_PARAM_ADDR         ((0x7F1004L) & ~MASK_BITS)
-#define SRAM_SCRATCHPAD         (0xFFFF00L)
+#define SRAM_STATUS_ADDR        ((0x7F1100L) & ~MASK_BITS)
-#define SRAM_DIRID              (0xFFFFF0L)
+#define SRAM_SYSINFO_ADDR       ((0x7F1200L) & ~MASK_BITS)
+#define SRAM_LASTGAME_ADDR      ((0x7F1420L) & ~MASK_BITS)
+#define SRAM_SCRATCHPAD         ((0x7FFF00L) & ~MASK_BITS)
+#define SRAM_DIRID              ((0x7FFFF0L) & ~MASK_BITS)
 #define SRAM_RELIABILITY_SCORE  (0x100)
 
 #define LOADROM_WITH_SRAM	(1)

src/msu1.c

@@ -214,7 +214,7 @@ int msu1_loop() {
       sd_offload_tgt=2;
       ff_sd_offload=1;
       msu_res = f_read(&msufile, file_buf, 8192, &msu_data_bytes_read);
-      DBG_MSU1 printf("data buffer refilled. res=%d page1=%08lx page2=%08lx\n", msu_res, msu_page1_start, msu_page2_start);
+      DBG_MSU1 printf("data buffer refilled. page=%d res=%d page1=%08lx page2=%08lx\n", pageno, msu_res, msu_page1_start, msu_page2_start);
     }
 
     /* Audio buffer refill */

src/openocd-usb.cfg

@@ -5,8 +5,14 @@
 #
 
 interface ft2232
-ft2232_vid_pid 0x0403 0x6010
+ft2232_vid_pid 0x15ba 0x0003
-ft2232_device_desc "Dual RS232"
+ft2232_device_desc "Olimex OpenOCD JTAG"
-ft2232_layout "oocdlink"
+ft2232_layout "olimex-jtag"
-ft2232_latency 2
+
+
+#interface ft2232
+#ft2232_vid_pid 0x0403 0x6010
+#ft2232_device_desc "Dual RS232"
+#ft2232_layout "oocdlink"
+#ft2232_latency 2
 #adapter_khz 10

src/sdnative.c

@@ -933,7 +933,7 @@ DSTATUS sdn_initialize(BYTE drv) {
 
   if((rsplen=cmd_slow(SEND_IF_COND, 0x000001aa, 0x87, NULL, rsp))) {
     DBG_SD printf("CMD8 response:\n");
-    DBG_SD uart_trace(rsp, 0, rsplen);
+    DBG_SD uart_trace(rsp, 0, rsplen, 0);
     hcs=1;
   }
   while(1) {

src/smc.c

@@ -208,8 +208,8 @@ void smc_id(snes_romprops_t* props) {
   props->ramsize_bytes = (uint32_t)1024 << header->ramsize;
   props->romsize_bytes = (uint32_t)1024 << header->romsize;
   props->expramsize_bytes = (uint32_t)1024 << header->expramsize;
-/*dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); */
+  //dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); 
-  if(props->ramsize_bytes < 2048) {
+  if(props->ramsize_bytes > 32768 || props->ramsize_bytes < 2048) {
     props->ramsize_bytes = 0;
   }
   props->region = (header->destcode <= 1 || header->destcode >= 13) ? 0 : 1;

src/snes.c

@@ -83,6 +83,10 @@ void snes_reset_pulse() {
  *  state: put SNES in reset state when 1, release when 0
  */
 void snes_reset(int state) {
+  if (state == 0)
+    printf("Releasing SNES RESET\n");
+  else
+    printf("Pull SNES RESET\n");
   BITBAND(SNES_RESET_REG->FIODIR, SNES_RESET_BIT) = state;
 }
 
@@ -170,11 +174,15 @@ void get_selected_name(uint8_t* fn) {
   sram_readblock(fn, addr + 7 + SRAM_MENU_ADDR, 256);
 }
 
-void snes_bootprint(void* msg) {
+void snes_bootprint(void* msg)
+{
+  printf("%s\n", (char*)msg);
   sram_writeblock(msg, SRAM_CMD_ADDR, 33);
 }
 
-void snes_menu_errmsg(int err, void* msg) {
+void snes_menu_errmsg(int err, void* msg)
+{
+  printf("%d: %s\n", err, (char*)msg);
   sram_writeblock(msg, SRAM_CMD_ADDR+1, 64);
   sram_writebyte(err, SRAM_CMD_ADDR);
 }

src/tests/Makefile

@@ -138,7 +138,8 @@ CFLAGS += $(CDEFS) $(CINCS)
 CFLAGS += -O$(OPT)
 CFLAGS += $(CPUFLAGS) -nostartfiles
 #CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums
-CFLAGS += -Wall -Wstrict-prototypes -Werror
+CFLAGS += -Wall -Wstrict-prototypes
+# -Werror
 CFLAGS += -Wa,-adhlns=$(OBJDIR)/$(<:.c=.lst)
 CFLAGS += -I$(OBJDIR)
 CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))

src/tests/config.h

@@ -38,7 +38,8 @@
 //#define CONFIG_CPU_FREQUENCY      46000000
 #define CONFIG_UART_PCLKDIV       1
 #define CONFIG_UART_TX_BUF_SHIFT  8
-#define CONFIG_UART_BAUDRATE      921600
+//#define CONFIG_UART_BAUDRATE      921600
+#define CONFIG_UART_BAUDRATE 115200
 #define CONFIG_UART_DEADLOCKABLE
 
 #define SSP_CLK_DIVISOR_FAST 2

src/tests/openocd-usb.cfg

@@ -5,8 +5,14 @@
 #
 
 interface ft2232
-ft2232_vid_pid 0x0403 0x6010
+ft2232_vid_pid 0x15ba 0x0003
-ft2232_device_desc "Dual RS232"
+ft2232_device_desc "Olimex OpenOCD JTAG"
-ft2232_layout "oocdlink"
+ft2232_layout "olimex-jtag"
-ft2232_latency 2
+
+
+#interface ft2232
+#ft2232_vid_pid 0x0403 0x6010
+#ft2232_device_desc "Dual RS232"
+#ft2232_layout "oocdlink"
+#ft2232_latency 2
 #adapter_khz 10

src/tests/tests.c

@@ -152,74 +152,178 @@ int test_fpga() {
   return PASSED;
 }
 
-int test_mem() {
+/*************************************************************************************/
-  printf("RAM test\n========\n");
+/*************************************************************************************/
-  printf("Testing RAM0 (128Mbit) - writing RAM -");
+
-  uint32_t addr;
+typedef struct memory_test
+{
+  char name[20];
+  int a_len;
+  int d_len;
+
+  unsigned int (*read)(unsigned int addr);
+  void (*write)(unsigned int addr, unsigned int data);
+  void (*open)(void);
+  void (*close)(void);
+} memory_test;
+
+/*************************************************************************************/
+
+void rom_open(void)
+{
   snes_reset(1);
   fpga_select_mem(0);
-  set_mcu_addr(0);
   FPGA_DESELECT();
   delay_ms(1);
   FPGA_SELECT();
   delay_ms(1);
-  FPGA_TX_BYTE(0x98);
+}
-  for(addr=0; addr < 16777216; addr++) {
+void rom_close(void)
-    if((addr&0xffff) == 0)printf("\x8%c", PROGRESS[(addr>>16)&3]);
+{
-    FPGA_TX_BYTE((addr)+(addr>>8)+(addr>>16));
+}
-    FPGA_WAIT_RDY();
+
-  }
+unsigned int rom_read(unsigned int addr)
-  FPGA_DESELECT();
+{
-  printf(" verifying RAM -");
+  return sram_readbyte(addr);
-  uint8_t data, expect, error=0, failed=0;
+}
-  set_mcu_addr(0);
+
-  FPGA_SELECT();
+void rom_write(unsigned int addr, unsigned int data)
-  FPGA_TX_BYTE(0x88);
+{
-  for(addr=0; addr < 16777216; addr++) {
+  sram_writebyte(data, addr);
-    if((addr&0xffff) == 0)printf("\x8%c", PROGRESS[(addr>>16)&3]);
+}
-    FPGA_WAIT_RDY();
+
-    data = FPGA_RX_BYTE();
+memory_test rom = {
-    expect = (addr)+(addr>>8)+(addr>>16);
+  .name = "RAM0 (128Mbit)",
-    if(data != expect) {
+  .a_len = 22,
-      printf("error @0x%06lx: expected 0x%02x, got 0x%02x\n", addr, expect, data);
+  .d_len = 8,
-      error++;
+  .read = rom_read,
-      failed=1;
+  .write = rom_write,
-      if(error>20) {
+  .open = rom_open,
-        printf("too many errors, aborting\n");
+  .close = rom_close,
-        break;
+};
-      }
+
-    }
+/*************************************************************************************/
-  }
+
-  FPGA_DESELECT();
+void sram_open(void)
-  if(error) printf("RAM0 FAILED\n");
+{
-  else printf("RAM0 PASSED\n");
-  printf("Testing RAM1 (4Mbit) - writing RAM - ");
   snes_reset(1);
   fpga_select_mem(1);
-  for(addr=0; addr < 524288; addr++) {
+}
-    sram_writebyte((addr)+(addr>>8)+(addr>>16), addr);
+
-  }
+void sram_close(void)
-  printf("verifying RAM...");
+{
-  error = 0;
+}
-  for(addr=0; addr < 524288; addr++) {
+
-    data = sram_readbyte(addr);
+unsigned int sram_read(unsigned int addr)
-    expect = (addr)+(addr>>8)+(addr>>16);
+{
-    if(data != expect) {
+  return sram_readbyte(addr);
-      printf("error @0x%05lx: expected 0x%02x, got 0x%02x\n", addr, expect, data);
+}
-      error++;
+
-      failed=1;
+void sram_write(unsigned int addr, unsigned int data)
-      if(error>20) {
+{
-        printf("too many errors, aborting\n");
+  sram_writebyte(data, addr);
-        break;
+}
-      }
+
+memory_test sram = 
+{
+  .name = "RAM1(4Mbit)",
+  .a_len = 19,
+  .d_len = 8,
+  .read = sram_read,
+  .write = sram_write,
+  .open = sram_open,
+  .close = sram_close,
+};
+
+int do_test(memory_test *test)
+{
+  int i, j, read, want;
+  int ret = 0;
+  int a_mask = (1 << test->a_len) - 1;
+  int d_mask = (1 << test->d_len) - 1;
+
+  test->open();
+
+  printf("-- Will test %s\n", test->name);
+  printf("---- Fill with AA55  ");
+  test->write(0, 0xAA);
+  for (i = 1; i < a_mask; i++)
+  {
+    if((i&0xffff) == 0)printf("\x8%c", PROGRESS[(i>>16)&3]);
+    want = (i&1)?0x55:0xAA;
+    test->write(i, want);
+
+    want = ((i-1)&1)?0x55:0xAA;
+    read = test->read(i-1);
+
+    if (read != want)
+    {
+      printf("Failed [@%8X Want: %02X Get: %02X]", i-1, want, read);
+      ret |= 1;
+      break;
     }
   }
-  if(error) printf("RAM1 FAILED\n\n\n");
+
-  else printf("RAM1 PASSED\n\n\n");
+  printf("Ok \n---- Fill with 00    ");
-  if(failed) return FAILED;
+  for (i = 0; i < a_mask; i++)
+  {
+    if((i&0xffff) == 0)printf("\x8%c", PROGRESS[(i>>16)&3]);
+    test->write(i, 0);
+  }
+
+  printf("Ok \n---- Check data lines...\n"
+         "-----           ");
+  for (i = 0; i < test->d_len; i++) printf("%X", i);
+  printf("\n");
+  /* Check on 4 addresses, taken evenly */
+#define TEST_NUM (10)
+
+  for (j = 0; j < TEST_NUM; j ++)
+  {
+    printf("----- %8X [", j * a_mask/TEST_NUM);
+    for (i = 0; i < test->d_len; i++)
+    {
+      read = test->read(j * a_mask/TEST_NUM);
+      if ((test->read(j * a_mask/TEST_NUM) & (1<<i)) != 0)
+      {
+        printf("1", read);
+        ret |= 2;
+        goto next_data;
+      }
+      test->write(j * a_mask/TEST_NUM, (1<<i));
+      read = test->read(j * a_mask/TEST_NUM);
+      if (read == 0)
+      {
+        printf("0");
+        ret |= 4;
+        goto next_data;
+      }
+      printf("x");
+
+next_data:
+      test->write(j * a_mask/4, 0);
+    }
+    printf("]\n");
+  }
+
+
+  test->close();
+  return ret;
+}
+
+int test_mem()
+{
+  int ret = PASSED;
+  printf("RAM test\n========\n");
+
+  if (do_test(&rom) != 0)
+    ret = FAILED;
+  if (do_test(&sram) != 0);
+    ret = FAILED;
   return PASSED;
 }
 
+
 int test_clk() {
   uint32_t sysclk[4];
   int32_t diff, max_diff = 0;

src/uart.c

@@ -238,7 +238,7 @@ void uart_puthex(uint8_t num) {
     uart_putc('a'+tmp-10);
 }
 
-void uart_trace(void *ptr, uint16_t start, uint16_t len) {
+void uart_trace(void *ptr, uint16_t start, uint16_t len, uint32_t addr) {
   uint16_t i;
   uint8_t j;
   uint8_t ch;
@@ -247,8 +247,9 @@ void uart_trace(void *ptr, uint16_t start, uint16_t len) {
   data+=start;
   for(i=0;i<len;i+=16) {
 
-    uart_puthex(start>>8);
+    uart_puthex((addr + start)>>16);
-    uart_puthex(start&0xff);
+    uart_puthex(((addr + start)>>8) & 0xff);
+    uart_puthex((addr + start)&0xff);
     uart_putc('|');
     uart_putc(' ');
     for(j=0;j<16;j++) {

src/uart.h

@@ -26,7 +26,7 @@ unsigned char uart_gotc(void);
 void uart_putc(char c);
 void uart_puts(const char *str);
 void uart_puthex(uint8_t num);
-void uart_trace(void *ptr, uint16_t start, uint16_t len);
+void uart_trace(void *ptr, uint16_t start, uint16_t len, uint32_t addr);
 void uart_flush(void);
 int  printf(const char *fmt, ...);
 int  snprintf(char *str, size_t size, const char *format, ...);

src/utils/Makefile

@@ -2,11 +2,14 @@
 CC = gcc
 CFLAGS = -Wall -Wstrict-prototypes -Werror
 
-all: lpcchksum genhdr
+all: lpcchksum genhdr bin2h
 
 genhdr: genhdr.o
 	$(CC) $(CFLAGS) $^ --output $@
 
+bin2h: bin2h.o
+	$(CC) $(CFLAGS) $^ --output $@
+
 lpcchksum: lpcchksum.o
 	$(CC) $(CFLAGS) $^ --output $@
 

src/utils/bin2h.c

@@ -0,0 +1,49 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(int argc, char *argv[])
+{
+   char var_name[30] = "cfgware"
+   FILE *fpIn = NULL, *fpOut = NULL;
+   unsigned char buffer[5], i;
+   if ( argc == 4 )
+   {
+      fpIn = fopen(argv[1], "rb");
+      fpOut = fopen(argv[2], "wt");
+   }
+   else if (argc == 3)
+   {
+      fpIn = fopen(argv[1], "rb");
+      fpOut = stdout;
+   }
+   else if ( argc == 2 )
+   {
+      fpIn = stdin;
+      fpOut = stdout;
+   }
+   else
+   {
+      fprintf(stderr, "usage: %s [infile] [outfile]\n", argv[0]);
+      return -1;
+   }
+   
+   if (argc > 1)
+      sprintf()
+
+   if (fpIn == NULL) { fprintf(stderr, "Can't open '%s`: Aborting.", argv[1]); return -1; }
+   if (fpOut == NULL) { fprintf(stderr, "Can't open '%s`: Aborting.", argv[2]); return -1; }
+   
+   fprintf(fpOut, "const uint8_t %s[] = {\n", var_name);
+   i = 0;
+   while(!feof(fpIn))
+   {
+      fread(buffer, 1, 1, fpIn);
+      fprintf(fpOut, "0x%02X, ", buffer[0]);
+      i++; if (i > 8) { fprintf(fpOut, "\n"); i = 0; }
+   }
+   if (i > 0)
+      fprintf(fpOut, "\n");
+   fprintf(fpOut, "};");
+   fclose(fpOut); fclose(fpIn);
+   return 0;
+}

src/xmodem.c

@@ -33,5 +33,7 @@ void xmodem_rxfile(FIL* fil) {
   uart_putc(ASC_ACK);
   uart_flush();
   sleep_ms(1000);
+  sender_sum = blknum + blknum2;
+  printf("%x:%x:%x\n", blknum, blknum2, sender_sum);
   printf("received %ld bytes, wrote %ld bytes. last res = %d\n", totalbytes, totalwritten, res);
 }

verilog/sd2snes/main.v

@@ -534,8 +534,12 @@ initial ROM_SAr = 1'b1;
 //wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
 wire ROM_SA = ROM_SAr;
 
-assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
+//assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
-assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
+//assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
+
+//WARNING DUE TO BAD SOLDER WE LOST HALF OF THE PSRAM!!!
+assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[22:0] : (ROM_SA) ? MAPPED_SNES_ADDR[22:0] : ROM_ADDRr[22:0];
+assign ROM_ADDR0 = 1'b0; //(SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
 
 reg ROM_WEr;
 initial ROM_WEr = 1'b1;
@@ -651,7 +655,7 @@ always @(posedge CLK2) begin
 		else STATE <= ST_MCU_RD_WAIT;
 	 end
 	 ST_MCU_RD_END: begin
-      MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
+      MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8]; /*ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];*/
 	   STATE <= ST_IDLE;
 	 end
 	 
@@ -707,18 +711,25 @@ always @(posedge CLK2) begin
   MCU_WRITE_1<= MCU_WRITE;
 end
 
+/*
 assign ROM_DATA[7:0] = ROM_ADDR0
                        ?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
-							                   /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
+							                   //: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA 
                                         : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
                         )
                        :8'bZ;
 
 assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
                         :(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
-								                 /*:  ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
+								                 //:  ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA 
                                          : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
                          );
+*/
+assign ROM_DATA[7:0] = SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
+							  : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
+
+assign ROM_DATA[15:8] = SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
+								                 : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
 
 assign ROM_WE = SD_DMA_TO_ROM
                 ?MCU_WRITE
@@ -729,8 +740,8 @@ assign ROM_OE = 1'b0;
 
 assign ROM_CE = 1'b0;
 
-assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BHE = 1'b0; ///*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
-assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BLE = 1'b0; ///*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
 
 assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
                          msu_enable ? 1'b0 :
@@ -751,7 +762,7 @@ assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescm
 
 assign SNES_IRQ = 1'b0;
 
-assign p113_out = 1'b0;
+assign p113_out = 1'b1;
 
 /*
 wire [35:0] CONTROL0;

verilog/sd2snes/sd2snes.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">

verilog/sd2snes_test/ipcore_dir/PA.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.2
+# Xilinx Core Generator version 13.4
-# Date: Fri Dec  9 20:36:25 2011
+# Date: Fri Aug 17 17:03:15 2012
 #
 ##############################################################
 #
@@ -99,7 +99,7 @@ CSET write_width_a=8
 CSET write_width_b=8
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-03-11T08:24:14.000Z
+MISC pkg_timestamp=2011-03-11T08:24:14Z
 # END Extra information
 GENERATE
-# CRC: 213d12c4
+# CRC: 370f2518

verilog/sd2snes_test/ipcore_dir/PA.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="PA.ngc" xil_pn:type="FILE_NGC">

verilog/sd2snes_test/ipcore_dir/bram.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.2
+# Xilinx Core Generator version 13.4
-# Date: Fri Dec  9 20:35:22 2011
+# Date: Fri Aug 17 17:07:29 2012
 #
 ##############################################################
 #
@@ -99,7 +99,7 @@ CSET write_width_a=8
 CSET write_width_b=8
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-03-11T08:24:14.000Z
+MISC pkg_timestamp=2011-03-11T08:24:14Z
 # END Extra information
 GENERATE
-# CRC: cb4729a5
+# CRC:  1d2c05e

verilog/sd2snes_test/ipcore_dir/bram.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="bram.ngc" xil_pn:type="FILE_NGC">

verilog/sd2snes_test/ipcore_dir/dac_buf.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.2
+# Xilinx Core Generator version 13.4
-# Date: Fri Dec  9 20:37:13 2011
+# Date: Fri Aug 17 17:13:12 2012
 #
 ##############################################################
 #
@@ -99,7 +99,7 @@ CSET write_width_a=8
 CSET write_width_b=32
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-06-21T06:43:52.000Z
+MISC pkg_timestamp=2012-01-07T13:55:09Z
 # END Extra information
 GENERATE
-# CRC: 360f80d1
+# CRC: 786d7d96

verilog/sd2snes_test/ipcore_dir/dac_buf.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="dac_buf.ngc" xil_pn:type="FILE_NGC">

verilog/sd2snes_test/main.v

@@ -29,12 +29,12 @@ module main(
   input SNES_CS,
   inout [7:0] SNES_DATA,
   input SNES_CPU_CLK,
-  input SNES_REFRESH,
   output SNES_IRQ,
   output SNES_DATABUS_OE,
   output SNES_DATABUS_DIR,
-  input SNES_SYSCLK,
 
+  input SNES_SYSCLK,  
+  input SNES_REFRESH,
   input [7:0] SNES_PA,
   input SNES_PARD,
   input SNES_PAWR,
@@ -386,8 +386,8 @@ end
 
 wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
 
-assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? ram0_addr[23:1] : ROM_ADDRr[23:1];
+assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[22:0] : (ASSERT_SNES_ADDR) ? ram0_addr[22:0] : ROM_ADDRr[22:0];
-assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? ram0_addr[0] : ROM_ADDRr[0];
+assign ROM_ADDR0 = 1'b0; //(SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? ram0_addr[0] : ROM_ADDRr[0];
 
 assign RAM_ADDR = ASSERT_SNES_ADDR ? ram1_addr : RAM_ADDRr;
 
@@ -441,8 +441,8 @@ always @(posedge CLK2) begin
         if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
         else STATE <= ST_SNES_RD_WAIT;
         if(ram0_enable) begin
-          if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
+          if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
-          else SNES_DINr <= ROM_DATA[15:8];
+          else SNES_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
         end else if(ram1_enable) begin
           SNES_DINr <= RAM_DATA[7:0];
         end
@@ -450,8 +450,8 @@ always @(posedge CLK2) begin
       ST_SNES_RD_END: begin
         STATE <= ST_IDLE;
         if(ram0_enable) begin
-          if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
+          if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
-          else SNES_DINr <= ROM_DATA[15:8];
+          else SNES_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
         end else if(ram1_enable) begin
           SNES_DINr <= RAM_DATA[7:0];
         end
@@ -498,8 +498,8 @@ always @(posedge CLK2) begin
         end
         else STATE <= ST_MCU_RD_WAIT;
         if(MCU_RAMSEL == 1'b0) begin
-          if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
+          if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
-          else MCU_DINr <= ROM_DATA[15:8];
+          else MCU_DINr <= ROM_DATA[15:8] | ROM_DATA[7:0];
         end else MCU_DINr <= RAM_DATA;
       end
       ST_MCU_RD_WAIT2: begin
@@ -548,14 +548,11 @@ always @(posedge CLK2) begin
   end
 end
 
-assign ROM_DATA[7:0] = ROM_ADDR0
+assign ROM_DATA[7:0] = (SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                       ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
                                         : (!ROM_WE ? ROM_DOUTr : 8'bZ)
-                        )
+                        );
-                       :8'bZ;
 
-assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
+assign ROM_DATA[15:8] = (SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                        :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
                                          : (!ROM_WE ? ROM_DOUTr : 8'bZ)
                          );
 
@@ -575,7 +572,7 @@ assign ROM_OE = 1'b0;
 assign ROM_CE = 1'b0;
 
 assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
-assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
+assign ROM_BLE = !ROM_WE ? ROM_ADDR0 : 1'b0;
 
 assign SNES_DATABUS_OE = PA_enable ? 1'b0
                          : bram_enable ? 1'b0

verilog/sd2snes_test/sd2snes_test.xise

@@ -9,72 +9,63 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
-    <file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../sd2snes/srtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="ipcore_dir/bram.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="ipcore_dir/PA.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="ipcore_dir/bram.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/PA.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/dac_buf.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
   </files>
 
   <properties>
@@ -126,8 +117,8 @@
     <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
     <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xa3s400" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan3" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
@@ -242,7 +233,7 @@
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="pqg208" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
@@ -316,7 +307,7 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="11" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="11" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -364,7 +355,7 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes_test" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan3" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>

verilog/sd2sneslite/address.v

@@ -47,10 +47,10 @@ assign IS_SAVERAM = (!SNES_ADDR[22]
                         );
 
 assign SRAM_SNES_ADDR = (IS_SAVERAM
-                             ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
+                             ? 24'h7F0000 + ((SNES_ADDR[14:0] - 15'h6000)
                                              & SAVERAM_MASK)
                              : (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
-                                + 24'hC00000)
+                                + 24'h500000)
                          );
 								 
 assign ROM_ADDR = SRAM_SNES_ADDR;

verilog/sd2sneslite/main.v

@@ -101,7 +101,6 @@ wire [23:0] SAVERAM_MASK;
 wire [23:0] ROM_MASK;
 
 wire [23:0] MAPPED_SNES_ADDR;
-wire ROM_ADDR0;
 
 spi snes_spi(
   .clk(CLK2),
@@ -253,8 +252,7 @@ initial ROM_SAr = 1'b1;
 //wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
 wire ROM_SA = ROM_SAr;
 
-assign ROM_ADDR  = (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
+assign ROM_ADDR  = (ROM_SA) ? MAPPED_SNES_ADDR[22:0] : ROM_ADDRr[22:0];
-assign ROM_ADDR0 = (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
 
 reg ROM_WEr;
 initial ROM_WEr = 1'b1;
@@ -308,7 +306,8 @@ always @(posedge CLK2) begin
 		end else if(SNES_cycle_start) begin
 //		  STATE <= ST_SNES_RD_ADDR;		  
         STATE <= ST_SNES_RD_END;
-        SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
+        SNES_DOUTr <= ROM_DATA[7:0] | ROM_DATA[15:8];
+		  //(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
 		end else if(SNES_DEADr & MCU_RD_PENDr) begin
 		  STATE <= ST_MCU_RD_ADDR;
 		end else if(SNES_DEADr & MCU_WR_PENDr) begin
@@ -368,7 +367,8 @@ always @(posedge CLK2) begin
 		else STATE <= ST_MCU_RD_WAIT;
 	 end
 	 ST_MCU_RD_END: begin
-      MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
+      MCU_DINr <= ROM_DATA[7:0] | ROM_DATA[15:8];
+		//ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
 	   STATE <= ST_IDLE;
 	 end
 	 
@@ -401,12 +401,8 @@ always @(posedge CLK2) begin
   ROM_WE_1 <= ROM_WE;
 end
 
-assign ROM_DATA[7:0] = ROM_ADDR0
+assign ROM_DATA[7:0] = (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
-                       ?(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ)
+assign ROM_DATA[15:8] = (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
-                       :8'bZ;
-
-assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
-                        :(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
 								
 assign ROM_WE = ROM_WEr;
 
@@ -415,8 +411,8 @@ assign ROM_OE = 1'b0;
 
 assign ROM_CE = 1'b0;
 
-assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BHE = 1'b0;// /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
-assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BLE = 1'b0;// /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
 
 assign SNES_DATABUS_OE = ((IS_ROM & SNES_CS)
                           |(!IS_ROM & !IS_SAVERAM)

verilog/sd2sneslite/sd2sneslite.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
@@ -312,6 +312,7 @@
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>