125 lines
3.0 KiB
Verilog
125 lines
3.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 21:16:09 07/10/2009
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// Design Name:
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// Module Name: spi
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module spi(
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input clk,
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input SCK,
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input MOSI,
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inout MISO,
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input SSEL,
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output cmd_ready,
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output param_ready,
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output [7:0] cmd_data,
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output [7:0] param_data,
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input [7:0] input_data,
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output [31:0] byte_cnt,
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output [2:0] bit_cnt
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);
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reg [7:0] cmd_data_r;
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reg [7:0] param_data_r;
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reg [2:0] SSELr;
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reg [2:0] SSELSCKr;
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always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
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always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
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wire SSEL_inactive = SSELr[1];
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wire SSEL_active = ~SSELr[1]; // SSEL is active low
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wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
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wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
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// bit count for one SPI byte + byte count for the message
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reg [2:0] bitcnt;
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initial bitcnt = 3'b000;
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wire bitcnt_msb = bitcnt[2];
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reg [2:0] bitcnt_wrap_r;
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always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
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wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
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reg [31:0] byte_cnt_r;
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reg byte_received; // high when a byte has been received
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reg [7:0] byte_data_received;
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assign bit_cnt = bitcnt;
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always @(posedge SCK) begin
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if(SSELSCKr[1]) bitcnt <= 3'b000;
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else bitcnt <= bitcnt + 3'b001;
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end
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always @(posedge SCK) begin
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if(~SSELSCKr[1]) begin
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byte_data_received <= {byte_data_received[6:0], MOSI};
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end
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if(~SSELSCKr[1] && bitcnt==3'b111) byte_received <= 1'b1;
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else byte_received <= 1'b0;
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end
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//reg [2:0] byte_received_r;
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//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
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//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
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always @(posedge clk) begin
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if(SSEL_inactive) begin
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byte_cnt_r <= 16'h0000;
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end else if(byte_received_sync) begin
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byte_cnt_r <= byte_cnt_r + 16'h0001;
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end
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end
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reg [7:0] byte_data_sent;
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assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
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reg cmd_ready_r;
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reg param_ready_r;
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reg cmd_ready_r2;
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reg param_ready_r2;
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assign cmd_ready = cmd_ready_r;
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assign param_ready = param_ready_r;
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assign cmd_data = cmd_data_r;
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assign param_data = param_data_r;
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assign byte_cnt = byte_cnt_r;
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always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
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always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
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// fill registers
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always @(posedge clk) begin
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if (SSEL_startmessage)
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cmd_data_r <= 8'h00;
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else if(cmd_ready_r2)
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cmd_data_r <= byte_data_received;
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else if(param_ready_r2)
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param_data_r <= byte_data_received;
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end
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// delay ready signals by one clock
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always @(posedge clk) begin
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cmd_ready_r <= cmd_ready_r2;
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param_ready_r <= param_ready_r2;
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end
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endmodule
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