677 lines
10 KiB
Plaintext
677 lines
10 KiB
Plaintext
#include "memmap.i65"
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; SPC Player
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; SPC700 transfer and IO routines by Shay Green <gblargg@gmail.com>
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spcplayer:
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php
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sep #$30 : .as : .xs
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ldx #$0a ; Check if SPC header is present
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-
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lda @SPC_HEADER,x
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cmp @text_spcid,x
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beq +
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jmp spc_exit
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+
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dey
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bne -
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rep #$10 : .xl ; Now draw lots of stuff
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stz bar_wl
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dec bar_wl
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stz bar_xl
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dec bar_xl
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stz bar_yl
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dec bar_yl
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jsr backup_screen
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lda #^text_spcplay ; Loading window
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sta window_tbank
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ldx #!text_spcplay
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stx window_taddr
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lda @spcplay_win_x
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sta window_x
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lda @spcplay_win_y
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sta window_y
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lda @spcplay_win_w
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sta window_w
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lda @spcplay_win_h
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sta window_h
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jsr draw_window
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lda #^text_spcload ; Loading text
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ldx #!text_spcload
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sta print_bank
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stx print_src
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stz print_pal
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lda #29
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sta print_count
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lda #17
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sta print_y
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lda #17
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sta print_x
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jsr hiprint
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stz isr_done
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-
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lda isr_done ; Wait until text is being printed...
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beq -
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jsr spc700_load ; Load SPC into SPC700
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lda #^text_spcplay
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sta window_tbank
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ldx #!text_spcplay
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stx window_taddr
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lda @spcstart_win_x
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sta window_x
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lda @spcstart_win_y
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sta window_y
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lda @spcstart_win_w
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sta window_w
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lda @spcstart_win_h
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sta window_h
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jsr draw_window
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lda #^text_spcstarta
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ldx #!text_spcstarta
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sta print_bank
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stx print_src
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lda #$01
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sta print_pal
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lda #30
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sta print_count
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lda #15
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sta print_y
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lda #17
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sta print_x
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jsr hiprint
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lda #^text_spcstartb
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ldx #!text_spcstartb
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sta print_bank
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stx print_src
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lda #$01
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sta print_pal
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lda #07
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sta print_count
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lda #17
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sta print_y
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lda #12
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sta print_x
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jsr hiprint
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lda #$fe
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ldx #$004e
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sta print_bank
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stx print_src
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stz print_pal
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lda #32
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sta print_count
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lda #17
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sta print_y
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lda #20
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sta print_x
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jsr hiprint
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lda #^text_spcstartc
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ldx #!text_spcstartc
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sta print_bank
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stx print_src
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lda #$01
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sta print_pal
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lda #07
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sta print_count
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lda #18
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sta print_y
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lda #12
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sta print_x
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jsr hiprint
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lda #$fe
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ldx #$002e
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sta print_bank
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stx print_src
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stz print_pal
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lda #32
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sta print_count
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lda #18
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sta print_y
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lda #20
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sta print_x
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jsr hiprint
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lda #^text_spcstartd
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ldx #!text_spcstartd
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sta print_bank
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stx print_src
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lda #$01
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sta print_pal
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lda #07
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sta print_count
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lda #19
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sta print_y
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lda #12
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sta print_x
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jsr hiprint
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lda #$fe
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ldx #$00b0
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sta longptr+2
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sta print_bank
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stx longptr
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ldy #$00
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lda [longptr], y
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cmp #$41
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bpl +
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inx
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+ stx print_src
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stz print_pal
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lda #32
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sta print_count
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lda #19
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sta print_y
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lda #20
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sta print_x
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jsr hiprint
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spc_playloop:
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lda isr_done ; SPC player loop
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lsr
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bcc spc_playloop
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jsr printtime
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stz isr_done
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jsr read_pad
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lda #$80
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and pad1trig+1
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bne spc_key_b
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bra spc_playloop
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spc_key_b:
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rep #$20 : .al
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tsc
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sta saved_sp ; Save SP for later re-entry
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lda #$fa50 ; Write reset signature
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sta @warm_signature
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sep #$20 : .as
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sei ; Blank screen & issue CMD_RESET command to Microcontroller...
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stz $2100 ; ...this is required, because there is no other way to stop S-SMP & S-DSP
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lda #CMD_RESET
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sta @MCU_CMD
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-
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bra - ; At this point, the SNES waits for an external reset from the Microcontroller
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spc_exit: ; Return from player in case of wrong SPC file data
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plp
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rts
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;---------------------------------------
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spc700_load:
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php
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sep #$20 : .as
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rep #$10 : .xl
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sei ; Disable NMI & IRQ
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stz $4200 ; The SPC player code is really timing sensitive ;)
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jsr upload_dsp_regs ; Upload S-DSP registers
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jsr upload_high_ram ; Upload 63.5K of SPC700 ram
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jsr upload_low_ram ; Upload rest of ram
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jsr restore_final ; Restore SPC700 state & start execution
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lda #$81 ; VBlank NMI + Auto Joypad Read
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sta $4200 ; enable V-BLANK NMI
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cli
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plp
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rts
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;---------------------------------------
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; Uploads DSP registers and some other setup code
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upload_dsp_regs:
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; ---- Begin upload
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ldy #$0002
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jsr spc_begin_upload
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; ---- Upload loader
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ldx #$0000
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-
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lda @loader,x
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jsr spc_upload_byte
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inx
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cpy #31 ; size of loader
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bne -
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; ---- Upload SP, PC & PSW
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lda @SPC_HEADER+43
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jsr spc_upload_byte
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lda @SPC_HEADER+38
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jsr spc_upload_byte
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lda @SPC_HEADER+37
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jsr spc_upload_byte
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lda @SPC_HEADER+42
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jsr spc_upload_byte
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; ---- Upload DSP registers
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ldx #$0000
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-
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; initialize FLG and KON ($6c/$4c) to avoid artifacts
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cpx #$4C
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bne +
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lda #$00
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bra upload_skip_load
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+
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cpx #$6C
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bne +
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lda #$E0
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bra upload_skip_load
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+
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lda @SPC_DSP_REGS,x
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upload_skip_load
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jsr spc_upload_byte
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inx
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cpx #128
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bne -
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; --- Upload fixed values for $F1-$F3
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ldy #$00F1
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jsr spc_next_upload
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lda #$80 ; stop timers
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jsr spc_upload_byte
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lda #$6c ; get dspaddr set for later
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jsr spc_upload_byte
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lda #$60
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jsr spc_upload_byte
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; ---- Upload $f8-$1ff
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ldy #$00F8
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jsr spc_next_upload
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ldx #$00F8
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-
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lda @SPC_DATA,x
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jsr spc_upload_byte
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inx
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cpx #$200
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bne -
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; ---- Execute loader
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ldy #$0002
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jsr spc_execute
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rts
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;---------------------------------------
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upload_high_ram:
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ldy #$0002
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jsr spc_begin_upload
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; ---- Upload transfer routine
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ldx #$0000
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-
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lda @transfer,x
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jsr spc_upload_byte
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inx
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cpy #43 ; size of transfer routine
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bne -
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ldx #$023f ; prepare transfer address
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; ---- Execute transfer routine
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ldy #$0002
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sty APUIO2
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stz APUIO1
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lda APUIO0
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inc
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inc
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sta APUIO0
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; Wait for acknowledgement
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-
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cmp APUIO0
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bne -
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; ---- Burst transfer of 63.5K using custom routine
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outer_transfer_loop:
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ldy #$003f ; 3
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inner_transfer_loop:
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lda @SPC_DATA,x ; 5 |
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sta APUIO0 ; 4 |
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lda @SPC_DATA+$40,x ; 5 |
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sta APUIO1 ; 4 |
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lda @SPC_DATA+$80,x ; 5 |
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sta APUIO2 ; 4 |
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lda @SPC_DATA+$C0,x ; 5 |
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sta APUIO3 ; 4 |
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tya ; 2 >> 38 cycles
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-
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cmp APUIO3 ; 4 |
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bne - ; 3 |
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dex ; 2 |
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dey ; 2 |
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bpl inner_transfer_loop ; 3 >> 14 cycles
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rep #$21 : .al ; 3 |
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txa ; 2 |
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adc #$140 ; 3 |
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tax ; 2 |
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sep #$20 : .as ; 3 |
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cpx #$003f ; 3 |
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bne outer_transfer_loop ; 3 >> 19 cycles
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rts
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;---------------------------------------
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upload_low_ram:
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; ---- Upload $0002-$00EF using IPL
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ldy #$0002
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jsr spc_begin_upload
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ldx #$0002
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-
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lda @SPC_DATA,x
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jsr spc_upload_byte
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inx
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cpx #$00F0
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bne -
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rts
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;---------------------------------------
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; Executes final restoration code
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restore_final:
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jsr start_exec_io ; prepare execution from I/O registers
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stz $420d ; SPC700 I/O code requires SLOW timing
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; ---- Restore first two bytes of RAM
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lda @SPC_DATA
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xba
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lda #$e8 ; MOV A,#@SPC_DATA
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tax
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jsr exec_instr
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ldx #$00C4 ; MOV $00,A
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jsr exec_instr
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lda @SPC_DATA+1
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xba
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lda #$e8 ; MOV A,#@SPC_DATA+1
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tax
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jsr exec_instr
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ldx #$01C4 ; MOV $01,A
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jsr exec_instr
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; ---- Restore SP
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lda @SPC_HEADER+43
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sec
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sbc #3
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xba
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lda #$cd ; MOV X,#@SPC_HEADER+43
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tax
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jsr exec_instr
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ldx #$bd ; MOV SP,X
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jsr exec_instr
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; ---- Restore X
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lda @SPC_HEADER+40
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xba
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lda #$cd ; MOV X,#@SPC_HEADER+40
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tax
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jsr exec_instr
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; ---- Restore Y
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lda @SPC_HEADER+41
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xba
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lda #$8d ; MOV Y,#@SPC_HEADER+41
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tax
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jsr exec_instr
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; ---- Restore DSP FLG register
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lda @SPC_DSP_REGS+$6c
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xba
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lda #$e8 ; MOV A,#@SPC_DSP_REGS+$6c
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tax
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jsr exec_instr
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ldx #$f3C4 ; MOV $f3,A -> $f2 has been set-up before by SPC700 loader
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jsr exec_instr
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; ---- wait a bit (the newer S-APU takes its time to ramp up the volume)
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lda #$10
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- pha
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jsr waitblank
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pla
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dec
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bne -
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; ---- Restore DSP KON register
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lda #$4C
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xba
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lda #$e8 ; MOV A,#$4c
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tax
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jsr exec_instr
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ldx #$f2C4 ; MOV $f2,A
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jsr exec_instr
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lda @SPC_DSP_REGS+$4C
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xba
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lda #$e8 ; MOV A,#@SPC_DSP_REGS+$4c
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tax
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jsr exec_instr
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ldx #$f3C4 ; MOV $f3,A
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jsr exec_instr
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; ---- Restore DSP register address
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lda @SPC_DATA+$F2
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xba
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lda #$e8 ; MOV A,#@SPC_DATA+$F2
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tax
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jsr exec_instr
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ldx #$f2C4 ; MOV dest,A
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jsr exec_instr
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; ---- Restore CONTROL register
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lda @SPC_DATA+$F1
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and #$CF ; don't clear input ports
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xba
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lda #$e8 ; MOV A,#@SPC_DATA+$F1
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tax
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jsr exec_instr
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ldx #$f1C4 ; MOV $F1,A
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jsr exec_instr
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;---- Restore A
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lda @SPC_HEADER+39
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xba
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lda #$e8 ; MOV A,#@SPC_HEADER+39
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tax
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jsr exec_instr
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;---- Restore PSW and PC
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ldx #$7F00 ; NOP; RTI
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stx APUIO0
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lda #$FC ; Patch loop to execute instruction just written
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sta APUIO3
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;---- restore IO ports $f4 - $f7
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rep #$20 : .al
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lda @SPC_DATA+$F4
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tax
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lda @SPC_DATA+$F6
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sta APUIO2
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stx APUIO0 ; last to avoid overwriting RETI before run
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sep #$20 : .as
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lda #$01
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sta $420d ; restore FAST CPU operation
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rts
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;---------------------------------------
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spc_begin_upload:
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sty APUIO2 ; Set address
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ldy #$BBAA ; Wait for SPC
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-
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cpy APUIO0
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bne -
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lda #$CC ; Send acknowledgement
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sta APUIO1
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sta APUIO0
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- ; Wait for acknowledgement
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cmp APUIO0
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bne -
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ldy #0 ; Initialize index
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rts
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;---------------------------------------
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spc_upload_byte:
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sta APUIO1
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tya ; Signal it's ready
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sta APUIO0
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- ; Wait for acknowledgement
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cmp APUIO0
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bne -
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iny
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rts
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;---------------------------------------
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spc_next_upload:
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sty APUIO2
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; Send command
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; Special case operation has been fully tested.
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lda APUIO0
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inc
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inc
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bne +
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inc
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+
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sta APUIO1
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sta APUIO0
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; Wait for acknowledgement
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-
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cmp APUIO0
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bne -
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ldy #0
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rts
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;---------------------------------------
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spc_execute:
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sty APUIO2
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stz APUIO1
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lda APUIO0
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inc
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inc
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sta APUIO0
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; Wait for acknowledgement
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-
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cmp APUIO0
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bne -
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rts
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;---------------------------------------
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start_exec_io:
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; Set execution address
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ldx #$00F5
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stx APUIO2
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stz APUIO1 ; NOP
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ldx #$FE2F ; BRA *-2
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; Signal to SPC that we're ready
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lda APUIO0
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inc
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inc
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sta APUIO0
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; Wait for acknowledgement
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-
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cmp APUIO0
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bne -
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; Quickly write branch
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stx APUIO2
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rts
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;---------------------------------------
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exec_instr:
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; Replace instruction
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stx APUIO0
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lda #$FC
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sta APUIO3 ; 30
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; SPC BRA loop takes 4 cycles, so it reads
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; the branch offset every 4 SPC cycles (84 master).
|
|
; We must handle the case where it read just before
|
|
; the write above, and when it reads just after it.
|
|
; If it reads just after, we have at least 7 SPC
|
|
; cycles (147 master) to change restore the branch
|
|
; offset.
|
|
|
|
; 48 minimum, 90 maximum
|
|
ora #0
|
|
ora #0
|
|
ora #0
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
; 66 delay, about the middle of the above limits
|
|
phd ;4
|
|
pld ;5
|
|
|
|
; Give plenty of extra time if single execution
|
|
; isn't needed, as this avoids such tight timing
|
|
; requirements.
|
|
|
|
; phd ;4
|
|
; pld ;5
|
|
; phd ;4
|
|
; pld ;5
|
|
|
|
; Patch loop to skip first two bytes
|
|
lda #$FE ; 16
|
|
sta APUIO3 ; 30
|
|
|
|
; 38 minimum (assuming 66 delay above)
|
|
phd ; 4
|
|
pld ; 5
|
|
|
|
; Give plenty of extra time if single execution
|
|
; isn't needed, as this avoids such tight timing
|
|
; requirements.
|
|
|
|
phd
|
|
pld
|
|
phd
|
|
pld
|
|
rts
|