Maximilian Rehkopf a5a02992e5 FPGA/embedded config: slightly tighten timing constraints

2012-06-11 01:52:45 +02:00

..

address.v

FPGA: adjust menu memory mapping to make more room for file database

2012-06-10 20:07:45 +02:00

avr_cmd.v

feature reduced FPGA config for uC flash embedding

2010-12-31 02:49:04 +01:00

data.v

FPGA: merge recent changes into sd2sneslite

2011-10-08 17:05:22 +02:00

dcm.v

FPGA: merge recent changes into sd2sneslite

2011-10-08 17:05:22 +02:00

main.ucf

FPGA/embedded config: slightly tighten timing constraints

2012-06-11 01:52:45 +02:00

main.v

FPGA: clean up (port size mismatches, unused regs/wires, ...)

2011-10-09 14:13:35 +02:00

sd2sneslite.xise

FPGA: adjust menu memory mapping to make more room for file database

2012-06-10 20:07:45 +02:00

spi.v

FPGA: clean up (port size mismatches, unused regs/wires, ...)

2011-10-09 14:13:35 +02:00