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FPGA/embedded config: slightly tighten timing constraints

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This commit is contained in:
Maximilian Rehkopf
2012-06-11 01:52:45 +02:00
parent 0f38935981
commit a5a02992e5
1 changed files with 2 additions and 2 deletions
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4
verilog/sd2sneslite/main.ucf
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@@ -1,5 +1,5 @@
NET "CLKIN" TNM_NET = "CLKIN";
TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %;
TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24.05 MHz HIGH 50 %;
//TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
NET "p113_out" IOSTANDARD = LVCMOS33;
@@ -9,7 +9,7 @@ NET "p113_out" LOC = P113;
NET "SPI_SCK" LOC = P71;
NET "SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
NET "SPI_SCK" TNM_NET = "SPI_SCK";
TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48MHz HIGH 50 %;
TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48.1MHz HIGH 50 %;
NET "SPI_SCK" IOSTANDARD = LVCMOS33;
NET "SPI_SCK" DRIVE = 8;