148 lines
4.5 KiB
Verilog
148 lines
4.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 22:18:56 12/20/2009
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// Design Name:
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// Module Name: spi_dma
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module spi_dma(
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input clk,
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output spi_dma_ovr,
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input spi_dma_miso,
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output spi_dma_sck,
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input spi_dma_trig,
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output spi_dma_nextaddr,
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output [7:0] spi_dma_sram_data,
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output spi_dma_sram_we,
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output spi_dma_done
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);
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reg spi_dma_sram_we_r;
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reg spi_dma_done_r;
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reg spi_dma_ovr_r;
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reg spi_dma_nextaddr_r;
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reg [7:0] spi_dma_sram_data_r;
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reg [3:0] spi_dma_bitcnt; // extra bits
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reg [9:0] spi_dma_bytecnt;
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reg [3:0] spi_dma_clkcnt;
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reg [3:0] spi_dma_sck_int_r;
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reg [5:0] spi_dma_trig_r;
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reg [4:0] spi_dma_miso_r;
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reg spi_dma_sck_out_r;
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reg spi_dma_sck_out_r2;
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initial begin
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spi_dma_clkcnt <= 4'b0000;
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spi_dma_bitcnt <= 4'b1110;
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spi_dma_bytecnt <= 10'b0000000000;
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spi_dma_nextaddr_r <= 1'b0;
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spi_dma_sram_we_r <= 1'b1;
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spi_dma_done_r <= 1'b1;
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spi_dma_sck_int_r <= 4'b0000;
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spi_dma_trig_r <= 6'b000000;
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spi_dma_ovr_r <= 1'b0;
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spi_dma_sck_out_r <= 1'b0;
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spi_dma_sck_out_r2 <= 1'b0;
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end
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// synthesize clock
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wire spi_dma_sck_int = spi_dma_clkcnt[1];
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assign spi_dma_sck = spi_dma_sck_out_r & spi_dma_sck_out_r2;
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always @(posedge clk) begin
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spi_dma_clkcnt <= spi_dma_clkcnt + 1;
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spi_dma_sck_int_r <= {spi_dma_sck_int_r[2:0], spi_dma_sck_int};
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spi_dma_trig_r <= {spi_dma_trig_r[4:0], spi_dma_trig};
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spi_dma_miso_r <= {spi_dma_miso_r[3:0], spi_dma_miso};
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end
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wire spi_dma_trig_rising = (spi_dma_trig_r[5:1] == 5'b00011);
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wire spi_dma_trig_falling = (spi_dma_trig_r[5:1] == 5'b11100);
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wire spi_dma_sck_rising = (spi_dma_sck_int_r[2:1] == 2'b01);
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wire spi_dma_sck_falling = (spi_dma_sck_int_r[2:1] == 2'b10);
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wire spi_dma_sck_rising2 = (spi_dma_sck_int_r[2:1] == 2'b01);
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wire spi_dma_sck_falling2 = (spi_dma_sck_int_r[2:1] == 2'b10);
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assign spi_dma_nextaddr = spi_dma_nextaddr_r & (spi_dma_bytecnt < 512);
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assign spi_dma_sram_data = spi_dma_sram_data_r;
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assign spi_dma_sram_we = spi_dma_sram_we_r | (spi_dma_bytecnt > 511);
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assign spi_dma_done = spi_dma_done_r;
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assign spi_dma_ovr = spi_dma_ovr_r;
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always @(posedge clk) begin
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if (spi_dma_trig_falling & !spi_dma_ovr_r) begin
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spi_dma_done_r <= 0;
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spi_dma_ovr_r <= 1;
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end else if (spi_dma_bitcnt == 0 && spi_dma_bytecnt == 514) begin
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spi_dma_done_r <= 1;
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spi_dma_ovr_r <= 0;
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end
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end
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always @(posedge clk) begin
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if(spi_dma_sck_falling)
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spi_dma_sck_out_r2 <= 0;
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else if(spi_dma_sck_rising)
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spi_dma_sck_out_r2 <= 1;
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end
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// fetch a little later
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//always @(posedge spi_dma_sck) begin
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// if (/*spi_dma_sck_rising & */spi_dma_ovr_r & spi_dma_bitcnt <= 8)
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// spi_dma_sram_data_r <= {spi_dma_sram_data_r[6:0], spi_dma_miso_r[0]};
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//end
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always @(posedge clk) begin
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if(spi_dma_sck_rising & spi_dma_ovr_r) begin
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if (spi_dma_bitcnt < 8) begin
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spi_dma_sck_out_r <= 1;
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spi_dma_bitcnt <= spi_dma_bitcnt + 1;
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spi_dma_sram_data_r <= {spi_dma_sram_data_r[6:0], spi_dma_miso_r[0]};
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end else if (spi_dma_bitcnt == 8) begin
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spi_dma_sck_out_r <= 0;
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spi_dma_bitcnt <= spi_dma_bitcnt + 1;
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spi_dma_sram_data_r <= {spi_dma_sram_data_r[6:0], spi_dma_miso_r[0]};
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end else if (spi_dma_bitcnt == 9) begin
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spi_dma_sck_out_r <= 0;
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spi_dma_sram_we_r <= 0;
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spi_dma_bitcnt <= 10;
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end else if (spi_dma_bitcnt == 10) begin
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spi_dma_sram_we_r <= 1;
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spi_dma_nextaddr_r <= 1;
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spi_dma_bitcnt <= spi_dma_bitcnt + 1;
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end else if (spi_dma_bitcnt == 11) begin
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spi_dma_nextaddr_r <= 0;
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spi_dma_bytecnt <= spi_dma_bytecnt + 1;
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spi_dma_bitcnt <= spi_dma_bitcnt + 1;
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end else if (spi_dma_bitcnt == 12) begin
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spi_dma_bitcnt <= 0;
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end else if (spi_dma_bitcnt == 4'b1101) begin
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spi_dma_sck_out_r <= 0;
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spi_dma_bitcnt <= 4'b1110;
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end else if (spi_dma_bitcnt == 4'b1110) begin
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spi_dma_bitcnt <= spi_dma_bitcnt + 1;
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end else if (spi_dma_bitcnt == 4'b1111) begin
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spi_dma_bitcnt <= 0;
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end
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end else if (spi_dma_trig_falling & !spi_dma_ovr_r) begin
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spi_dma_bitcnt <= 4'b1101;
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spi_dma_bytecnt <= 10'b0000000000;
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end
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end
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endmodule
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