Maximilian Rehkopf 2a1ef40796 FPGA/cx4: adjust Cx4 CPU timing

2012-05-19 18:07:13 +02:00

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sd2snes

FPGA: Map mode 21 SRAM to 20:xxxx as well

2012-05-02 10:46:01 +02:00

sd2snes_cx4

FPGA/cx4: adjust Cx4 CPU timing

2012-05-19 18:07:13 +02:00

sd2snes_test

FPGA: add SD clock pullup to test configuration

2012-05-02 10:46:27 +02:00

sd2sneslite

FPGA: clean up (port size mismatches, unused regs/wires, ...)

2011-10-09 14:13:35 +02:00