FPGA: add SD clock pullup to test configuration

2012-05-02 10:46:27 +02:00
parent e63658e2ad
commit 7109f9e030
1 changed files with 1 additions and 0 deletions
--- a/verilog/sd2snes_test/main.ucf
+++ b/verilog/sd2snes_test/main.ucf
@@ -535,6 +535,7 @@ NET "SD_DAT[3]" LOC = P63;
 # PlanAhead Generated IO constraints 

 NET "SD_CLK" IOSTANDARD = LVCMOS33;
+NET "SD_CLK" PULLUP;
 NET "SD_CMD" IOSTANDARD = LVCMOS33;
 NET "SD_DAT[0]" IOSTANDARD = LVCMOS33;
 NET "SD_DAT[1]" IOSTANDARD = LVCMOS33;