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sd2snes/verilog
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Maximilian Rehkopf 1a52da6272 FPGA: Adjust DAC I²S signal timing
2012-07-09 01:41:47 +02:00
..
sd2snes
FPGA: Adjust DAC I²S signal timing
2012-07-09 01:41:47 +02:00
sd2snes_cx4
FPGA: Adjust DAC I²S signal timing
2012-07-09 01:41:47 +02:00
sd2snes_test
FPGA: add SD clock pullup to test configuration
2012-05-02 10:46:27 +02:00
sd2sneslite
FPGA: simple SNES address input filtering
2012-07-09 01:37:57 +02:00
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