130 lines
4.5 KiB
C
130 lines
4.5 KiB
C
/* sd2snes - SD card based universal cartridge for the SNES
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Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
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uC firmware portion
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Inspired by and based on code from sd2iec, written by Ingo Korb et al.
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See sdcard.c|h, config.h.
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FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
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see ff.c|h.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; version 2 of the License only.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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fpga_spi.h: functions for SPI ctrl, SRAM interfacing and feature configuration
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*/
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#ifndef _FPGA_SPI_H
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#define _FPGA_SPI_H
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#include <arm/NXP/LPC17xx/LPC17xx.h>
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#include "bits.h"
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#include "spi.h"
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#include "config.h"
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#define FPGA_SS_BIT 16
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#define FPGA_SS_REG LPC_GPIO0
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#define FPGA_SELECT() do {FPGA_TX_SYNC(); BITBAND(FPGA_SS_REG->FIOCLR, FPGA_SS_BIT) = 1;} while (0)
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#define FPGA_SELECT_ASYNC() do {BITBAND(FPGA_SS_REG->FIOCLR, FPGA_SS_BIT) = 1;} while (0)
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#define FPGA_DESELECT() do {FPGA_TX_SYNC(); BITBAND(FPGA_SS_REG->FIOSET, FPGA_SS_BIT) = 1;} while (0)
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#define FPGA_DESELECT_ASYNC() do {BITBAND(FPGA_SS_REG->FIOSET, FPGA_SS_BIT) = 1;} while (0)
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#define FPGA_TX_SYNC() spi_tx_sync()
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#define FPGA_TX_BYTE(x) spi_tx_byte(x)
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#define FPGA_RX_BYTE() spi_rx_byte()
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#define FPGA_TXRX_BYTE(x) spi_txrx_byte(x)
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#define FPGA_TX_BLOCK(x,y) spi_tx_block(x,y)
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#define FPGA_RX_BLOCK(x,y) spi_rx_block(x,y)
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#define FEAT_213F (1 << 4)
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#define FEAT_MSU1 (1 << 3)
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#define FEAT_SRTC (1 << 2)
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#define FEAT_ST0010 (1 << 1)
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#define FEAT_DSPX (1 << 0)
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#define FEAT_CX4 (1 << 4)
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#define FPGA_WAIT_RDY() do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0)
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/* command parameters */
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#define FPGA_MEM_AUTOINC (0x8)
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#define FPGA_SDDMA_PARTIAL (0x4)
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#define FPGA_TGT_MEM (0x0)
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#define FPGA_TGT_DACBUF (0x1)
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#define FPGA_TGT_MSUBUF (0x2)
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/* commands */
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#define FPGA_CMD_SETADDR (0x00)
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#define FPGA_CMD_SETROMMASK (0x10)
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#define FPGA_CMD_SETRAMMASK (0x20)
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#define FPGA_CMD_SETMAPPER(x) (0x30 | (x & 15))
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#define FPGA_CMD_SDDMA (0x40)
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#define FPGA_CMD_SDDMA_RANGE (0x60)
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#define FPGA_CMD_READMEM (0x80)
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#define FPGA_CMD_WRITEMEM (0x90)
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#define FPGA_CMD_MSUSETBITS (0xe0)
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#define FPGA_CMD_DACPAUSE (0xe1)
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#define FPGA_CMD_DACPLAY (0xe2)
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#define FPGA_CMD_DACRESETPTR (0xe3)
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#define FPGA_CMD_MSUSETPTR (0xe4)
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#define FPGA_CMD_RTCSET (0xe5)
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#define FPGA_CMD_BSXSETBITS (0xe6)
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#define FPGA_CMD_SRTCRESET (0xe7)
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#define FPGA_CMD_DSPRESETPTR (0xe8)
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#define FPGA_CMD_DSPWRITEPGM (0xe9)
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#define FPGA_CMD_DSPWRITEDAT (0xea)
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#define FPGA_CMD_DSPRESET (0xeb)
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#define FPGA_CMD_DSPUNRESET (0xec)
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#define FPGA_CMD_SETFEATURE (0xed)
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#define FPGA_CMD_SET213F (0xee)
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#define FPGA_CMD_TEST (0xf0)
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#define FPGA_CMD_GETSTATUS (0xf1)
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#define FPGA_CMD_MSUGETADDR (0xf2)
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#define FPGA_CMD_MSUGETTRACK (0xf3)
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#define FPGA_CMD_GETSYSCLK (0xfe)
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#define FPGA_CMD_ECHO (0xff)
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void fpga_spi_init(void);
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uint8_t fpga_test(void);
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uint16_t fpga_status(void);
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void spi_fpga(void);
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void spi_sd(void);
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void spi_none(void);
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void set_mcu_addr(uint32_t);
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void set_dac_addr(uint16_t);
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void dac_play(void);
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void dac_pause(void);
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void dac_reset(void);
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void msu_reset(uint16_t);
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void set_msu_addr(uint16_t);
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void set_msu_status(uint8_t set, uint8_t reset);
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void set_saveram_mask(uint32_t);
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void set_rom_mask(uint32_t);
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void set_mapper(uint8_t val);
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void fpga_sddma(uint8_t tgt, uint8_t partial);
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void fpga_set_sddma_range(uint16_t start, uint16_t end);
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uint16_t get_msu_track(void);
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uint32_t get_msu_offset(void);
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uint32_t get_snes_sysclk(void);
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void set_bsx_regs(uint8_t set, uint8_t reset);
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void set_fpga_time(uint64_t time);
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void fpga_reset_srtc_state(void);
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void fpga_reset_dspx_addr(void);
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void fpga_write_dspx_pgm(uint32_t data);
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void fpga_write_dspx_dat(uint16_t data);
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void fpga_dspx_reset(uint8_t reset);
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void fpga_set_features(uint8_t feat);
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void fpga_set_213f(uint8_t data);
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#endif
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